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commit 7bdd6731f8337fd57bf91772aa1917e44239d7c2
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Author: Mark Wielaard <mark@klomp.org>
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Date: Fri Dec 7 10:42:22 2018 -0500
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Implement ppc64 ldbrx as 64-bit load and Iop_Reverse8sIn64_x1.
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This makes it possible for memcheck to analyse the new gcc strcmp
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inlined code correctly even if the ldbrx load is partly beyond an
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addressable block.
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Partially resolves bug 386945.
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diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c
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index 8977d4f..a81dace 100644
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--- a/VEX/priv/guest_ppc_toIR.c
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+++ b/VEX/priv/guest_ppc_toIR.c
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@@ -9178,24 +9178,28 @@ static Bool dis_int_ldst_rev ( UInt theInstr )
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case 0x214: // ldbrx (Load Doubleword Byte-Reverse Indexed)
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{
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- // JRS FIXME:
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- // * is the host_endness conditional below actually necessary?
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- // * can we just do a 64-bit load followed by by Iop_Reverse8sIn64_x1?
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- // That would be a lot more efficient.
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- IRExpr * nextAddr;
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- IRTemp w3 = newTemp( Ity_I32 );
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- IRTemp w4 = newTemp( Ity_I32 );
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- DIP("ldbrx r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr);
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- assign( w1, load( Ity_I32, mkexpr( EA ) ) );
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- assign( w2, gen_byterev32( w1 ) );
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- nextAddr = binop( mkSzOp( ty, Iop_Add8 ), mkexpr( EA ),
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- ty == Ity_I64 ? mkU64( 4 ) : mkU32( 4 ) );
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- assign( w3, load( Ity_I32, nextAddr ) );
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- assign( w4, gen_byterev32( w3 ) );
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- if (host_endness == VexEndnessLE)
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- putIReg( rD_addr, binop( Iop_32HLto64, mkexpr( w2 ), mkexpr( w4 ) ) );
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+ /* Caller makes sure we are only called in mode64. */
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+
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+ /* If we supported swapping LE/BE loads in the backend then we could
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+ just load the value with the bytes reversed by doing a BE load
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+ on an LE machine and a LE load on a BE machine.
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+
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+ IRTemp dw1 = newTemp(Ity_I64);
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+ if (host_endness == VexEndnessBE)
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+ assign( dw1, IRExpr_Load(Iend_LE, Ity_I64, mkexpr(EA)));
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else
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- putIReg( rD_addr, binop( Iop_32HLto64, mkexpr( w4 ), mkexpr( w2 ) ) );
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+ assign( dw1, IRExpr_Load(Iend_BE, Ity_I64, mkexpr(EA)));
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+ putIReg( rD_addr, mkexpr(dw1) );
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+
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+ But since we currently don't we load the value as is and then
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+ switch it around with Iop_Reverse8sIn64_x1. */
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+
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+ IRTemp dw1 = newTemp(Ity_I64);
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+ IRTemp dw2 = newTemp(Ity_I64);
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+ DIP("ldbrx r%u,r%u,r%u\n", rD_addr, rA_addr, rB_addr);
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+ assign( dw1, load(Ity_I64, mkexpr(EA)) );
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+ assign( dw2, unop(Iop_Reverse8sIn64_x1, mkexpr(dw1)) );
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+ putIReg( rD_addr, mkexpr(dw2) );
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break;
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}
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diff --git a/VEX/priv/host_ppc_isel.c b/VEX/priv/host_ppc_isel.c
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index 750cf8d..4fc3eb5 100644
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--- a/VEX/priv/host_ppc_isel.c
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+++ b/VEX/priv/host_ppc_isel.c
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@@ -2210,6 +2210,63 @@ static HReg iselWordExpr_R_wrk ( ISelEnv* env, const IRExpr* e,
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return rr;
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}
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+ case Iop_Reverse8sIn64_x1: {
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+ /* See Iop_Reverse8sIn32_x1, but extended to 64bit.
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+ Can only be used in 64bit mode. */
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+ vassert (mode64);
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+
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+ HReg r_src = iselWordExpr_R(env, e->Iex.Unop.arg, IEndianess);
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+ HReg rr = newVRegI(env);
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+ HReg rMask = newVRegI(env);
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+ HReg rnMask = newVRegI(env);
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+ HReg rtHi = newVRegI(env);
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+ HReg rtLo = newVRegI(env);
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+
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+ // Copy r_src since we need to modify it
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+ addInstr(env, mk_iMOVds_RR(rr, r_src));
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+
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+ // r = (r & 0x00FF00FF00FF00FF) << 8 | (r & 0xFF00FF00FF00FF00) >> 8
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+ addInstr(env, PPCInstr_LI(rMask, 0x00FF00FF00FF00FFULL,
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+ True/* 64bit imm*/));
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+ addInstr(env, PPCInstr_Unary(Pun_NOT, rnMask, rMask));
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+ addInstr(env, PPCInstr_Alu(Palu_AND, rtHi, rr, PPCRH_Reg(rMask)));
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+ addInstr(env, PPCInstr_Shft(Pshft_SHL, False/*64 bit shift*/,
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+ rtHi, rtHi,
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+ PPCRH_Imm(False/*!signed imm*/, 8)));
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+ addInstr(env, PPCInstr_Alu(Palu_AND, rtLo, rr, PPCRH_Reg(rnMask)));
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+ addInstr(env, PPCInstr_Shft(Pshft_SHR, False/*64 bit shift*/,
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+ rtLo, rtLo,
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+ PPCRH_Imm(False/*!signed imm*/, 8)));
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+ addInstr(env, PPCInstr_Alu(Palu_OR, rr, rtHi, PPCRH_Reg(rtLo)));
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+
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+ // r = (r & 0x0000FFFF0000FFFF) << 16 | (r & 0xFFFF0000FFFF0000) >> 16
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+ addInstr(env, PPCInstr_LI(rMask, 0x0000FFFF0000FFFFULL,
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+ True/* !64bit imm*/));
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+ addInstr(env, PPCInstr_Unary(Pun_NOT, rnMask, rMask));
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+ addInstr(env, PPCInstr_Alu(Palu_AND, rtHi, rr, PPCRH_Reg(rMask)));
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+ addInstr(env, PPCInstr_Shft(Pshft_SHL, False/*64 bit shift*/,
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+ rtHi, rtHi,
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+ PPCRH_Imm(False/*!signed imm*/, 16)));
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+ addInstr(env, PPCInstr_Alu(Palu_AND, rtLo, rr, PPCRH_Reg(rnMask)));
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+ addInstr(env, PPCInstr_Shft(Pshft_SHR, False/*64 bit shift*/,
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+ rtLo, rtLo,
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+ PPCRH_Imm(False/*!signed imm*/, 16)));
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+ addInstr(env, PPCInstr_Alu(Palu_OR, rr, rtHi, PPCRH_Reg(rtLo)));
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+
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+ // r = (r & 0x00000000FFFFFFFF) << 32 | (r & 0xFFFFFFFF00000000) >> 32
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+ /* We don't need to mask anymore, just two more shifts and an or. */
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+ addInstr(env, mk_iMOVds_RR(rtLo, rr));
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+ addInstr(env, PPCInstr_Shft(Pshft_SHL, False/*64 bit shift*/,
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+ rtLo, rtLo,
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+ PPCRH_Imm(False/*!signed imm*/, 32)));
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+ addInstr(env, PPCInstr_Shft(Pshft_SHR, False/*64 bit shift*/,
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+ rr, rr,
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+ PPCRH_Imm(False/*!signed imm*/, 32)));
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+ addInstr(env, PPCInstr_Alu(Palu_OR, rr, rr, PPCRH_Reg(rtLo)));
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+
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+ return rr;
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+ }
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+
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case Iop_Left8:
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case Iop_Left16:
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case Iop_Left32:
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