diff --git a/SOURCES/gcc8-rh1760208-1.patch b/SOURCES/gcc8-rh1760208-1.patch new file mode 100644 index 0000000..038de2c --- /dev/null +++ b/SOURCES/gcc8-rh1760208-1.patch @@ -0,0 +1,508 @@ +commit 8358562298cf72905c128c2c96526b7fdccf742c +Author: Segher Boessenkool +Date: Fri Aug 30 16:13:51 2019 +0200 + + backport: altivec.md (unspec): Delete UNSPEC_DARN... + + Backport from trunk + 2019-08-22 Segher Boessenkool + + * config/rs6000/altivec.md (unspec): Delete UNSPEC_DARN, UNSPEC_DARN_32, + UNSPEC_DARN_RAW, UNSPEC_CMPRB, UNSPEC_CMPRB2, UNSPEC_CMPEQB; move to... + * config/rs6000/rs6000.md (unspec): ... here. + * config/rs6000/altivec.md (darn_32, darn_raw, darn, cmprb, + *cmprb_internal, setb_signed, setb_unsigned, cmprb2, *cmprb2_internal, + cmpeqb, *cmpeqb_internal): Delete, move to... + * config/rs6000/rs6000.md (darn_32, darn_raw, darn, cmprb, + *cmprb_internal, setb_signed, setb_unsigned, cmprb2, *cmprb2_internal, + cmpeqb, *cmpeqb_internal): ... here. + + From-SVN: r275180 + +--- gcc/config/rs6000/altivec.md ++++ gcc/config/rs6000/altivec.md +@@ -80,9 +80,6 @@ + UNSPEC_VUPKHPX + UNSPEC_VUPKLPX + UNSPEC_CONVERT_4F32_8I16 +- UNSPEC_DARN +- UNSPEC_DARN_32 +- UNSPEC_DARN_RAW + UNSPEC_DST + UNSPEC_DSTT + UNSPEC_DSTST +@@ -161,9 +158,6 @@ + UNSPEC_BCDADD + UNSPEC_BCDSUB + UNSPEC_BCD_OVERFLOW +- UNSPEC_CMPRB +- UNSPEC_CMPRB2 +- UNSPEC_CMPEQB + UNSPEC_VRLMI + UNSPEC_VRLNM + ]) +@@ -4317,223 +4311,6 @@ + [(set_attr "length" "4") + (set_attr "type" "vecsimple")]) + +-(define_insn "darn_32" +- [(set (match_operand:SI 0 "register_operand" "=r") +- (unspec:SI [(const_int 0)] UNSPEC_DARN_32))] +- "TARGET_P9_MISC" +- "darn %0,0" +- [(set_attr "type" "integer")]) +- +-(define_insn "darn_raw" +- [(set (match_operand:DI 0 "register_operand" "=r") +- (unspec:DI [(const_int 0)] UNSPEC_DARN_RAW))] +- "TARGET_P9_MISC && TARGET_64BIT" +- "darn %0,2" +- [(set_attr "type" "integer")]) +- +-(define_insn "darn" +- [(set (match_operand:DI 0 "register_operand" "=r") +- (unspec:DI [(const_int 0)] UNSPEC_DARN))] +- "TARGET_P9_MISC && TARGET_64BIT" +- "darn %0,1" +- [(set_attr "type" "integer")]) +- +-;; Test byte within range. +-;; +-;; The bytes of operand 1 are organized as xx:xx:xx:vv, where xx +-;; represents a byte whose value is ignored in this context and +-;; vv, the least significant byte, holds the byte value that is to +-;; be tested for membership within the range specified by operand 2. +-;; The bytes of operand 2 are organized as xx:xx:hi:lo. +-;; +-;; Return in target register operand 0 a value of 1 if lo <= vv and +-;; vv <= hi. Otherwise, set register operand 0 to 0. +-;; +-;; Though the instructions to which this expansion maps operate on +-;; 64-bit registers, the current implementation only operates on +-;; SI-mode operands as the high-order bits provide no information +-;; that is not already available in the low-order bits. To avoid the +-;; costs of data widening operations, future enhancements might allow +-;; DI mode for operand 0 and/or might allow operand 1 to be QI mode. +-(define_expand "cmprb" +- [(set (match_dup 3) +- (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r") +- (match_operand:SI 2 "gpc_reg_operand" "r")] +- UNSPEC_CMPRB)) +- (set (match_operand:SI 0 "gpc_reg_operand" "=r") +- (if_then_else:SI (lt (match_dup 3) +- (const_int 0)) +- (const_int -1) +- (if_then_else (gt (match_dup 3) +- (const_int 0)) +- (const_int 1) +- (const_int 0))))] +- "TARGET_P9_MISC" +-{ +- operands[3] = gen_reg_rtx (CCmode); +-}) +- +-;; The bytes of operand 1 are organized as xx:xx:xx:vv, where xx +-;; represents a byte whose value is ignored in this context and +-;; vv, the least significant byte, holds the byte value that is to +-;; be tested for membership within the range specified by operand 2. +-;; The bytes of operand 2 are organized as xx:xx:hi:lo. +-;; +-;; Set bit 1 (the GT bit, 0x4) of CR register operand 0 to 1 if +-;; lo <= vv and vv <= hi. Otherwise, set the GT bit to 0. The other +-;; 3 bits of the target CR register are all set to 0. +-(define_insn "*cmprb_internal" +- [(set (match_operand:CC 0 "cc_reg_operand" "=y") +- (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r") +- (match_operand:SI 2 "gpc_reg_operand" "r")] +- UNSPEC_CMPRB))] +- "TARGET_P9_MISC" +- "cmprb %0,0,%1,%2" +- [(set_attr "type" "logical")]) +- +-;; Set operand 0 register to -1 if the LT bit (0x8) of condition +-;; register operand 1 is on. Otherwise, set operand 0 register to 1 +-;; if the GT bit (0x4) of condition register operand 1 is on. +-;; Otherwise, set operand 0 to 0. Note that the result stored into +-;; register operand 0 is non-zero iff either the LT or GT bits are on +-;; within condition register operand 1. +-(define_insn "setb_signed" +- [(set (match_operand:SI 0 "gpc_reg_operand" "=r") +- (if_then_else:SI (lt (match_operand:CC 1 "cc_reg_operand" "y") +- (const_int 0)) +- (const_int -1) +- (if_then_else (gt (match_dup 1) +- (const_int 0)) +- (const_int 1) +- (const_int 0))))] +- "TARGET_P9_MISC" +- "setb %0,%1" +- [(set_attr "type" "logical")]) +- +-(define_insn "setb_unsigned" +- [(set (match_operand:SI 0 "gpc_reg_operand" "=r") +- (if_then_else:SI (ltu (match_operand:CCUNS 1 "cc_reg_operand" "y") +- (const_int 0)) +- (const_int -1) +- (if_then_else (gtu (match_dup 1) +- (const_int 0)) +- (const_int 1) +- (const_int 0))))] +- "TARGET_P9_MISC" +- "setb %0,%1" +- [(set_attr "type" "logical")]) +- +-;; Test byte within two ranges. +-;; +-;; The bytes of operand 1 are organized as xx:xx:xx:vv, where xx +-;; represents a byte whose value is ignored in this context and +-;; vv, the least significant byte, holds the byte value that is to +-;; be tested for membership within the range specified by operand 2. +-;; The bytes of operand 2 are organized as hi_1:lo_1:hi_2:lo_2. +-;; +-;; Return in target register operand 0 a value of 1 if (lo_1 <= vv and +-;; vv <= hi_1) or if (lo_2 <= vv and vv <= hi_2). Otherwise, set register +-;; operand 0 to 0. +-;; +-;; Though the instructions to which this expansion maps operate on +-;; 64-bit registers, the current implementation only operates on +-;; SI-mode operands as the high-order bits provide no information +-;; that is not already available in the low-order bits. To avoid the +-;; costs of data widening operations, future enhancements might allow +-;; DI mode for operand 0 and/or might allow operand 1 to be QI mode. +-(define_expand "cmprb2" +- [(set (match_dup 3) +- (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r") +- (match_operand:SI 2 "gpc_reg_operand" "r")] +- UNSPEC_CMPRB2)) +- (set (match_operand:SI 0 "gpc_reg_operand" "=r") +- (if_then_else:SI (lt (match_dup 3) +- (const_int 0)) +- (const_int -1) +- (if_then_else (gt (match_dup 3) +- (const_int 0)) +- (const_int 1) +- (const_int 0))))] +- "TARGET_P9_MISC" +-{ +- operands[3] = gen_reg_rtx (CCmode); +-}) +- +-;; The bytes of operand 1 are organized as xx:xx:xx:vv, where xx +-;; represents a byte whose value is ignored in this context and +-;; vv, the least significant byte, holds the byte value that is to +-;; be tested for membership within the ranges specified by operand 2. +-;; The bytes of operand 2 are organized as hi_1:lo_1:hi_2:lo_2. +-;; +-;; Set bit 1 (the GT bit, 0x4) of CR register operand 0 to 1 if +-;; (lo_1 <= vv and vv <= hi_1) or if (lo_2 <= vv and vv <= hi_2). +-;; Otherwise, set the GT bit to 0. The other 3 bits of the target +-;; CR register are all set to 0. +-(define_insn "*cmprb2_internal" +- [(set (match_operand:CC 0 "cc_reg_operand" "=y") +- (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r") +- (match_operand:SI 2 "gpc_reg_operand" "r")] +- UNSPEC_CMPRB2))] +- "TARGET_P9_MISC" +- "cmprb %0,1,%1,%2" +- [(set_attr "type" "logical")]) +- +-;; Test byte membership within set of 8 bytes. +-;; +-;; The bytes of operand 1 are organized as xx:xx:xx:vv, where xx +-;; represents a byte whose value is ignored in this context and +-;; vv, the least significant byte, holds the byte value that is to +-;; be tested for membership within the set specified by operand 2. +-;; The bytes of operand 2 are organized as e0:e1:e2:e3:e4:e5:e6:e7. +-;; +-;; Return in target register operand 0 a value of 1 if vv equals one +-;; of the values e0, e1, e2, e3, e4, e5, e6, or e7. Otherwise, set +-;; register operand 0 to 0. Note that the 8 byte values held within +-;; operand 2 need not be unique. +-;; +-;; Though the instructions to which this expansion maps operate on +-;; 64-bit registers, the current implementation requires that operands +-;; 0 and 1 have mode SI as the high-order bits provide no information +-;; that is not already available in the low-order bits. To avoid the +-;; costs of data widening operations, future enhancements might allow +-;; DI mode for operand 0 and/or might allow operand 1 to be QI mode. +-(define_expand "cmpeqb" +- [(set (match_dup 3) +- (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r") +- (match_operand:DI 2 "gpc_reg_operand" "r")] +- UNSPEC_CMPEQB)) +- (set (match_operand:SI 0 "gpc_reg_operand" "=r") +- (if_then_else:SI (lt (match_dup 3) +- (const_int 0)) +- (const_int -1) +- (if_then_else (gt (match_dup 3) +- (const_int 0)) +- (const_int 1) +- (const_int 0))))] +- "TARGET_P9_MISC && TARGET_64BIT" +-{ +- operands[3] = gen_reg_rtx (CCmode); +-}) +- +-;; The bytes of operand 1 are organized as xx:xx:xx:vv, where xx +-;; represents a byte whose value is ignored in this context and +-;; vv, the least significant byte, holds the byte value that is to +-;; be tested for membership within the set specified by operand 2. +-;; The bytes of operand 2 are organized as e0:e1:e2:e3:e4:e5:e6:e7. +-;; +-;; Set bit 1 (the GT bit, 0x4) of CR register operand 0 to 1 if vv +-;; equals one of the values e0, e1, e2, e3, e4, e5, e6, or e7. Otherwise, +-;; set the GT bit to zero. The other 3 bits of the target CR register +-;; are all set to 0. +-(define_insn "*cmpeqb_internal" +- [(set (match_operand:CC 0 "cc_reg_operand" "=y") +- (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r") +- (match_operand:DI 2 "gpc_reg_operand" "r")] +- UNSPEC_CMPEQB))] +- "TARGET_P9_MISC && TARGET_64BIT" +- "cmpeqb %0,%1,%2" +- [(set_attr "type" "logical")]) +- + (define_expand "bcd_" + [(parallel [(set (reg:CCFP CR6_REGNO) + (compare:CCFP +--- gcc/config/rs6000/rs6000.md ++++ gcc/config/rs6000/rs6000.md +@@ -136,6 +136,12 @@ + UNSPEC_LSQ + UNSPEC_FUSION_GPR + UNSPEC_STACK_CHECK ++ UNSPEC_DARN ++ UNSPEC_DARN_32 ++ UNSPEC_DARN_RAW ++ UNSPEC_CMPRB ++ UNSPEC_CMPRB2 ++ UNSPEC_CMPEQB + UNSPEC_FUSION_P9 + UNSPEC_FUSION_ADDIS + UNSPEC_ADD_ROUND_TO_ODD +@@ -14600,7 +14606,225 @@ + "xscmpuqp %0,%1,%2" + [(set_attr "type" "veccmp") + (set_attr "size" "128")]) ++ ++;; Miscellaneous ISA 3.0 (power9) instructions ++ ++(define_insn "darn_32" ++ [(set (match_operand:SI 0 "register_operand" "=r") ++ (unspec:SI [(const_int 0)] UNSPEC_DARN_32))] ++ "TARGET_P9_MISC" ++ "darn %0,0" ++ [(set_attr "type" "integer")]) ++ ++(define_insn "darn_raw" ++ [(set (match_operand:DI 0 "register_operand" "=r") ++ (unspec:DI [(const_int 0)] UNSPEC_DARN_RAW))] ++ "TARGET_P9_MISC && TARGET_64BIT" ++ "darn %0,2" ++ [(set_attr "type" "integer")]) ++ ++(define_insn "darn" ++ [(set (match_operand:DI 0 "register_operand" "=r") ++ (unspec:DI [(const_int 0)] UNSPEC_DARN))] ++ "TARGET_P9_MISC && TARGET_64BIT" ++ "darn %0,1" ++ [(set_attr "type" "integer")]) ++ ++;; Test byte within range. ++;; ++;; The bytes of operand 1 are organized as xx:xx:xx:vv, where xx ++;; represents a byte whose value is ignored in this context and ++;; vv, the least significant byte, holds the byte value that is to ++;; be tested for membership within the range specified by operand 2. ++;; The bytes of operand 2 are organized as xx:xx:hi:lo. ++;; ++;; Return in target register operand 0 a value of 1 if lo <= vv and ++;; vv <= hi. Otherwise, set register operand 0 to 0. ++;; ++;; Though the instructions to which this expansion maps operate on ++;; 64-bit registers, the current implementation only operates on ++;; SI-mode operands as the high-order bits provide no information ++;; that is not already available in the low-order bits. To avoid the ++;; costs of data widening operations, future enhancements might allow ++;; DI mode for operand 0 and/or might allow operand 1 to be QI mode. ++(define_expand "cmprb" ++ [(set (match_dup 3) ++ (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r") ++ (match_operand:SI 2 "gpc_reg_operand" "r")] ++ UNSPEC_CMPRB)) ++ (set (match_operand:SI 0 "gpc_reg_operand" "=r") ++ (if_then_else:SI (lt (match_dup 3) ++ (const_int 0)) ++ (const_int -1) ++ (if_then_else (gt (match_dup 3) ++ (const_int 0)) ++ (const_int 1) ++ (const_int 0))))] ++ "TARGET_P9_MISC" ++{ ++ operands[3] = gen_reg_rtx (CCmode); ++}) ++ ++;; The bytes of operand 1 are organized as xx:xx:xx:vv, where xx ++;; represents a byte whose value is ignored in this context and ++;; vv, the least significant byte, holds the byte value that is to ++;; be tested for membership within the range specified by operand 2. ++;; The bytes of operand 2 are organized as xx:xx:hi:lo. ++;; ++;; Set bit 1 (the GT bit, 0x4) of CR register operand 0 to 1 if ++;; lo <= vv and vv <= hi. Otherwise, set the GT bit to 0. The other ++;; 3 bits of the target CR register are all set to 0. ++(define_insn "*cmprb_internal" ++ [(set (match_operand:CC 0 "cc_reg_operand" "=y") ++ (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r") ++ (match_operand:SI 2 "gpc_reg_operand" "r")] ++ UNSPEC_CMPRB))] ++ "TARGET_P9_MISC" ++ "cmprb %0,0,%1,%2" ++ [(set_attr "type" "logical")]) ++ ++;; Set operand 0 register to -1 if the LT bit (0x8) of condition ++;; register operand 1 is on. Otherwise, set operand 0 register to 1 ++;; if the GT bit (0x4) of condition register operand 1 is on. ++;; Otherwise, set operand 0 to 0. Note that the result stored into ++;; register operand 0 is non-zero iff either the LT or GT bits are on ++;; within condition register operand 1. ++(define_insn "setb_signed" ++ [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ++ (if_then_else:SI (lt (match_operand:CC 1 "cc_reg_operand" "y") ++ (const_int 0)) ++ (const_int -1) ++ (if_then_else (gt (match_dup 1) ++ (const_int 0)) ++ (const_int 1) ++ (const_int 0))))] ++ "TARGET_P9_MISC" ++ "setb %0,%1" ++ [(set_attr "type" "logical")]) ++ ++(define_insn "setb_unsigned" ++ [(set (match_operand:SI 0 "gpc_reg_operand" "=r") ++ (if_then_else:SI (ltu (match_operand:CCUNS 1 "cc_reg_operand" "y") ++ (const_int 0)) ++ (const_int -1) ++ (if_then_else (gtu (match_dup 1) ++ (const_int 0)) ++ (const_int 1) ++ (const_int 0))))] ++ "TARGET_P9_MISC" ++ "setb %0,%1" ++ [(set_attr "type" "logical")]) ++ ++;; Test byte within two ranges. ++;; ++;; The bytes of operand 1 are organized as xx:xx:xx:vv, where xx ++;; represents a byte whose value is ignored in this context and ++;; vv, the least significant byte, holds the byte value that is to ++;; be tested for membership within the range specified by operand 2. ++;; The bytes of operand 2 are organized as hi_1:lo_1:hi_2:lo_2. ++;; ++;; Return in target register operand 0 a value of 1 if (lo_1 <= vv and ++;; vv <= hi_1) or if (lo_2 <= vv and vv <= hi_2). Otherwise, set register ++;; operand 0 to 0. ++;; ++;; Though the instructions to which this expansion maps operate on ++;; 64-bit registers, the current implementation only operates on ++;; SI-mode operands as the high-order bits provide no information ++;; that is not already available in the low-order bits. To avoid the ++;; costs of data widening operations, future enhancements might allow ++;; DI mode for operand 0 and/or might allow operand 1 to be QI mode. ++(define_expand "cmprb2" ++ [(set (match_dup 3) ++ (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r") ++ (match_operand:SI 2 "gpc_reg_operand" "r")] ++ UNSPEC_CMPRB2)) ++ (set (match_operand:SI 0 "gpc_reg_operand" "=r") ++ (if_then_else:SI (lt (match_dup 3) ++ (const_int 0)) ++ (const_int -1) ++ (if_then_else (gt (match_dup 3) ++ (const_int 0)) ++ (const_int 1) ++ (const_int 0))))] ++ "TARGET_P9_MISC" ++{ ++ operands[3] = gen_reg_rtx (CCmode); ++}) ++ ++;; The bytes of operand 1 are organized as xx:xx:xx:vv, where xx ++;; represents a byte whose value is ignored in this context and ++;; vv, the least significant byte, holds the byte value that is to ++;; be tested for membership within the ranges specified by operand 2. ++;; The bytes of operand 2 are organized as hi_1:lo_1:hi_2:lo_2. ++;; ++;; Set bit 1 (the GT bit, 0x4) of CR register operand 0 to 1 if ++;; (lo_1 <= vv and vv <= hi_1) or if (lo_2 <= vv and vv <= hi_2). ++;; Otherwise, set the GT bit to 0. The other 3 bits of the target ++;; CR register are all set to 0. ++(define_insn "*cmprb2_internal" ++ [(set (match_operand:CC 0 "cc_reg_operand" "=y") ++ (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r") ++ (match_operand:SI 2 "gpc_reg_operand" "r")] ++ UNSPEC_CMPRB2))] ++ "TARGET_P9_MISC" ++ "cmprb %0,1,%1,%2" ++ [(set_attr "type" "logical")]) + ++;; Test byte membership within set of 8 bytes. ++;; ++;; The bytes of operand 1 are organized as xx:xx:xx:vv, where xx ++;; represents a byte whose value is ignored in this context and ++;; vv, the least significant byte, holds the byte value that is to ++;; be tested for membership within the set specified by operand 2. ++;; The bytes of operand 2 are organized as e0:e1:e2:e3:e4:e5:e6:e7. ++;; ++;; Return in target register operand 0 a value of 1 if vv equals one ++;; of the values e0, e1, e2, e3, e4, e5, e6, or e7. Otherwise, set ++;; register operand 0 to 0. Note that the 8 byte values held within ++;; operand 2 need not be unique. ++;; ++;; Though the instructions to which this expansion maps operate on ++;; 64-bit registers, the current implementation requires that operands ++;; 0 and 1 have mode SI as the high-order bits provide no information ++;; that is not already available in the low-order bits. To avoid the ++;; costs of data widening operations, future enhancements might allow ++;; DI mode for operand 0 and/or might allow operand 1 to be QI mode. ++(define_expand "cmpeqb" ++ [(set (match_dup 3) ++ (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r") ++ (match_operand:DI 2 "gpc_reg_operand" "r")] ++ UNSPEC_CMPEQB)) ++ (set (match_operand:SI 0 "gpc_reg_operand" "=r") ++ (if_then_else:SI (lt (match_dup 3) ++ (const_int 0)) ++ (const_int -1) ++ (if_then_else (gt (match_dup 3) ++ (const_int 0)) ++ (const_int 1) ++ (const_int 0))))] ++ "TARGET_P9_MISC && TARGET_64BIT" ++{ ++ operands[3] = gen_reg_rtx (CCmode); ++}) ++ ++;; The bytes of operand 1 are organized as xx:xx:xx:vv, where xx ++;; represents a byte whose value is ignored in this context and ++;; vv, the least significant byte, holds the byte value that is to ++;; be tested for membership within the set specified by operand 2. ++;; The bytes of operand 2 are organized as e0:e1:e2:e3:e4:e5:e6:e7. ++;; ++;; Set bit 1 (the GT bit, 0x4) of CR register operand 0 to 1 if vv ++;; equals one of the values e0, e1, e2, e3, e4, e5, e6, or e7. Otherwise, ++;; set the GT bit to zero. The other 3 bits of the target CR register ++;; are all set to 0. ++(define_insn "*cmpeqb_internal" ++ [(set (match_operand:CC 0 "cc_reg_operand" "=y") ++ (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r") ++ (match_operand:DI 2 "gpc_reg_operand" "r")] ++ UNSPEC_CMPEQB))] ++ "TARGET_P9_MISC && TARGET_64BIT" ++ "cmpeqb %0,%1,%2" ++ [(set_attr "type" "logical")]) + + + (include "sync.md") diff --git a/SOURCES/gcc8-rh1760208-2.patch b/SOURCES/gcc8-rh1760208-2.patch new file mode 100644 index 0000000..7d7c1c0 --- /dev/null +++ b/SOURCES/gcc8-rh1760208-2.patch @@ -0,0 +1,67 @@ +commit c2894790640da2c0761924ff1b06efddbdfa031e +Author: Segher Boessenkool +Date: Fri Aug 30 16:15:39 2019 +0200 + + backport: re PR target/91481 (POWER9 "DARN" RNG intrinsic produces repeated output (CVE-2019-15847)) + + Backport from trunk + 2019-08-22 Segher Boessenkool + + PR target/91481 + * config/rs6000/rs6000.md (unspec): Delete UNSPEC_DARN, UNSPEC_DARN_32, + and UNSPEC_DARN_RAW. + (unspecv): New enumerator values UNSPECV_DARN, UNSPECV_DARN_32, and + UNSPECV_DARN_RAW. + (darn_32): Use an unspec_volatile, and UNSPECV_DARN_32. + (darn_raw): Use an unspec_volatile, and UNSPECV_DARN_RAW. + (darn): Use an unspec_volatile, and UNSPECV_DARN. + + From-SVN: r275181 + +--- gcc/config/rs6000/rs6000.md ++++ gcc/config/rs6000/rs6000.md +@@ -136,9 +136,6 @@ + UNSPEC_LSQ + UNSPEC_FUSION_GPR + UNSPEC_STACK_CHECK +- UNSPEC_DARN +- UNSPEC_DARN_32 +- UNSPEC_DARN_RAW + UNSPEC_CMPRB + UNSPEC_CMPRB2 + UNSPEC_CMPEQB +@@ -168,6 +165,9 @@ + UNSPECV_EH_RR ; eh_reg_restore + UNSPECV_ISYNC ; isync instruction + UNSPECV_MFTB ; move from time base ++ UNSPECV_DARN ; darn 1 (deliver a random number) ++ UNSPECV_DARN_32 ; darn 2 ++ UNSPECV_DARN_RAW ; darn 0 + UNSPECV_NLGR ; non-local goto receiver + UNSPECV_MFFS ; Move from FPSCR + UNSPECV_MTFSF ; Move to FPSCR Fields +@@ -14611,21 +14611,21 @@ + + (define_insn "darn_32" + [(set (match_operand:SI 0 "register_operand" "=r") +- (unspec:SI [(const_int 0)] UNSPEC_DARN_32))] ++ (unspec_volatile:SI [(const_int 0)] UNSPECV_DARN_32))] + "TARGET_P9_MISC" + "darn %0,0" + [(set_attr "type" "integer")]) + + (define_insn "darn_raw" + [(set (match_operand:DI 0 "register_operand" "=r") +- (unspec:DI [(const_int 0)] UNSPEC_DARN_RAW))] ++ (unspec_volatile:DI [(const_int 0)] UNSPECV_DARN_RAW))] + "TARGET_P9_MISC && TARGET_64BIT" + "darn %0,2" + [(set_attr "type" "integer")]) + + (define_insn "darn" + [(set (match_operand:DI 0 "register_operand" "=r") +- (unspec:DI [(const_int 0)] UNSPEC_DARN))] ++ (unspec_volatile:DI [(const_int 0)] UNSPECV_DARN))] + "TARGET_P9_MISC && TARGET_64BIT" + "darn %0,1" + [(set_attr "type" "integer")]) diff --git a/SOURCES/gcc8-rh1760208-3.patch b/SOURCES/gcc8-rh1760208-3.patch new file mode 100644 index 0000000..92640d0 --- /dev/null +++ b/SOURCES/gcc8-rh1760208-3.patch @@ -0,0 +1,34 @@ +commit ff12f8b9ae10bf7270ec7ead28a479f6105058eb +Author: Segher Boessenkool +Date: Fri Aug 30 16:17:20 2019 +0200 + + backport: re PR target/91481 (POWER9 "DARN" RNG intrinsic produces repeated output (CVE-2019-15847)) + + Backport from trunk + 2019-08-23 Segher Boessenkool + + gcc/testsuite/ + PR target/91481 + * gcc.target/powerpc/darn-3.c: New testcase. + + From-SVN: r275182 + +--- /dev/null ++++ gcc/testsuite/gcc.target/powerpc/darn-3.c +@@ -0,0 +1,16 @@ ++/* { dg-do compile { target { powerpc*-*-* } } } */ ++/* { dg-skip-if "" { powerpc*-*-aix* } } */ ++/* { dg-options "-O2 -mdejagnu-cpu=power9" } */ ++ ++static int darn32(void) { return __builtin_darn_32(); } ++ ++int four(void) ++{ ++ int sum = 0; ++ int i; ++ for (i = 0; i < 4; i++) ++ sum += darn32(); ++ return sum; ++} ++ ++/* { dg-final { scan-assembler-times {(?n)\mdarn .*,0\M} 4 } } */ diff --git a/SOURCES/gcc8-rh1760208-4.patch b/SOURCES/gcc8-rh1760208-4.patch new file mode 100644 index 0000000..4faff6b --- /dev/null +++ b/SOURCES/gcc8-rh1760208-4.patch @@ -0,0 +1,26 @@ +commit 710d6269e1d93d6da1fdf2952f746e35a0a02365 +Author: Segher Boessenkool +Date: Sat Aug 31 20:58:04 2019 +0200 + + rs6000: Fix darn-3.c for GCC 8 and GCC 7 + + Apparently I didn't properly test the testcase backport to GCC 8 and + GCC 7. This makes it not fail there. + + + PR target/91481 + * gcc.target/powerpc/darn-3.c: Fix testcase. + + From-SVN: r275244 + +--- gcc/testsuite/gcc.target/powerpc/darn-3.c ++++ gcc/testsuite/gcc.target/powerpc/darn-3.c +@@ -1,6 +1,7 @@ + /* { dg-do compile { target { powerpc*-*-* } } } */ + /* { dg-skip-if "" { powerpc*-*-aix* } } */ +-/* { dg-options "-O2 -mdejagnu-cpu=power9" } */ ++/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ ++/* { dg-options "-O2 -mcpu=power9" } */ + + static int darn32(void) { return __builtin_darn_32(); } + diff --git a/SPECS/gcc.spec b/SPECS/gcc.spec index 9d69e72..0f18e18 100644 --- a/SPECS/gcc.spec +++ b/SPECS/gcc.spec @@ -90,7 +90,7 @@ Summary: GCC version 8 Name: %{?scl_prefix}gcc Version: %{gcc_version} -Release: %{gcc_release}.1%{?dist} +Release: %{gcc_release}.2%{?dist} # libgcc, libgfortran, libgomp, libstdc++ and crtstuff have # GCC Runtime Exception. License: GPLv3+ and GPLv3+ with exceptions and GPLv2+ with exceptions and LGPLv2+ and BSD @@ -255,6 +255,10 @@ Patch14: gcc8-pr89629.patch Patch15: gcc8-pr90139.patch Patch16: gcc8-pr90756.patch Patch17: gcc8-pr86098.patch +Patch18: gcc8-rh1760208-1.patch +Patch19: gcc8-rh1760208-2.patch +Patch20: gcc8-rh1760208-3.patch +Patch21: gcc8-rh1760208-4.patch Patch1000: gcc8-libstdc++-compat.patch Patch1001: gcc8-alt-compat-test.patch @@ -635,6 +639,10 @@ This package contains Leak Sanitizer static runtime library. %patch15 -p0 -b .pr90139~ %patch16 -p0 -b .pr90756~ %patch17 -p0 -b .pr86098~ +%patch18 -p0 -b .rh1760208-1~ +%patch19 -p0 -b .rh1760208-2~ +%patch20 -p0 -b .rh1760208-3~ +%patch21 -p0 -b .rh1760208-4~ %patch1000 -p0 -b .libstdc++-compat~ %ifarch %{ix86} x86_64 @@ -2502,6 +2510,10 @@ fi %doc rpm.doc/changelogs/libcc1/ChangeLog* %changelog +* Tue Feb 4 2020 Marek Polacek 8.3.1-3.2 +- move UNSPEC_DARN* from altivec.md to rs6000.md (#1760208) +- use unspec_volatile for darn (PR target/91481, #1760208, CVE-2019-15847) + * Wed Jul 17 2019 Marek Polacek 8.3.1-3.1 - fix tree-outof-ssa.c ICE with vector types (PR middle-end/90139, #1730724) - fix out-of-ssa with unsupported vector types (PR rtl-optimization/90756,