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commit 54a2f1efc188660df9da78523b6925aab4c3a668
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Author: rsandifo <rsandifo@138bc75d-0d04-0410-961f-82ee72b054a4>
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Date: Tue Jan 13 14:11:15 2015 +0000
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gcc/
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* config/aarch64/aarch64.md (subsi3, *subsi3_uxtw, subdi3)
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(*sub_<optab><ALLX:mode>_<GPI:mode>, *sub_<optab><SHORT:mode>_si_uxtw)
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(*sub_<optab><ALLX:mode>_shft_<GPI:mode>)
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(*sub_<optab><SHORT:mode>_shft_si_uxtw, *sub_<optab><mode>_multp2)
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(*sub_<optab>si_multp2_uxtw, *sub_uxt<mode>_multp2)
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(*sub_uxtsi_multp2_uxtw): Add stack pointer sources.
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gcc/testsuite/
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* gcc.target/aarch64/subsp.c: New test.
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git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@219533 138bc75d-0d04-0410-961f-82ee72b054a4
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diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
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index 17082486ac8..a085c6acaf5 100644
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--- a/gcc/config/aarch64/aarch64.md
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+++ b/gcc/config/aarch64/aarch64.md
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@@ -1610,8 +1610,8 @@
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(define_insn "subsi3"
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[(set (match_operand:SI 0 "register_operand" "=rk")
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- (minus:SI (match_operand:SI 1 "register_operand" "r")
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- (match_operand:SI 2 "register_operand" "r")))]
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+ (minus:SI (match_operand:SI 1 "register_operand" "rk")
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+ (match_operand:SI 2 "register_operand" "r")))]
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""
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"sub\\t%w0, %w1, %w2"
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[(set_attr "v8type" "alu")
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@@ -1622,7 +1622,7 @@
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(define_insn "*subsi3_uxtw"
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[(set (match_operand:DI 0 "register_operand" "=rk")
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(zero_extend:DI
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- (minus:SI (match_operand:SI 1 "register_operand" "r")
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+ (minus:SI (match_operand:SI 1 "register_operand" "rk")
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(match_operand:SI 2 "register_operand" "r"))))]
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""
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"sub\\t%w0, %w1, %w2"
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@@ -1632,7 +1632,7 @@
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(define_insn "subdi3"
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[(set (match_operand:DI 0 "register_operand" "=rk,!w")
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- (minus:DI (match_operand:DI 1 "register_operand" "r,!w")
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+ (minus:DI (match_operand:DI 1 "register_operand" "rk,!w")
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(match_operand:DI 2 "register_operand" "r,!w")))]
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""
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"@
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@@ -1725,7 +1725,7 @@
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(define_insn "*sub_<optab><ALLX:mode>_<GPI:mode>"
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[(set (match_operand:GPI 0 "register_operand" "=rk")
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- (minus:GPI (match_operand:GPI 1 "register_operand" "r")
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+ (minus:GPI (match_operand:GPI 1 "register_operand" "rk")
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(ANY_EXTEND:GPI
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(match_operand:ALLX 2 "register_operand" "r"))))]
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""
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@@ -1738,7 +1738,7 @@
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(define_insn "*sub_<optab><SHORT:mode>_si_uxtw"
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[(set (match_operand:DI 0 "register_operand" "=rk")
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(zero_extend:DI
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- (minus:SI (match_operand:SI 1 "register_operand" "r")
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+ (minus:SI (match_operand:SI 1 "register_operand" "rk")
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(ANY_EXTEND:SI
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(match_operand:SHORT 2 "register_operand" "r")))))]
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""
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@@ -1749,7 +1749,7 @@
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(define_insn "*sub_<optab><ALLX:mode>_shft_<GPI:mode>"
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[(set (match_operand:GPI 0 "register_operand" "=rk")
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- (minus:GPI (match_operand:GPI 1 "register_operand" "r")
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+ (minus:GPI (match_operand:GPI 1 "register_operand" "rk")
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(ashift:GPI (ANY_EXTEND:GPI
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(match_operand:ALLX 2 "register_operand" "r"))
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(match_operand 3 "aarch64_imm3" "Ui3"))))]
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@@ -1763,7 +1763,7 @@
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(define_insn "*sub_<optab><SHORT:mode>_shft_si_uxtw"
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[(set (match_operand:DI 0 "register_operand" "=rk")
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(zero_extend:DI
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- (minus:SI (match_operand:SI 1 "register_operand" "r")
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+ (minus:SI (match_operand:SI 1 "register_operand" "rk")
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(ashift:SI (ANY_EXTEND:SI
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(match_operand:SHORT 2 "register_operand" "r"))
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(match_operand 3 "aarch64_imm3" "Ui3")))))]
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@@ -1775,7 +1775,7 @@
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(define_insn "*sub_<optab><mode>_multp2"
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[(set (match_operand:GPI 0 "register_operand" "=rk")
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- (minus:GPI (match_operand:GPI 4 "register_operand" "r")
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+ (minus:GPI (match_operand:GPI 4 "register_operand" "rk")
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(ANY_EXTRACT:GPI
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(mult:GPI (match_operand:GPI 1 "register_operand" "r")
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(match_operand 2 "aarch64_pwr_imm3" "Up3"))
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@@ -1791,7 +1791,7 @@
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(define_insn "*sub_<optab>si_multp2_uxtw"
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[(set (match_operand:DI 0 "register_operand" "=rk")
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(zero_extend:DI
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- (minus:SI (match_operand:SI 4 "register_operand" "r")
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+ (minus:SI (match_operand:SI 4 "register_operand" "rk")
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(ANY_EXTRACT:SI
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(mult:SI (match_operand:SI 1 "register_operand" "r")
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(match_operand 2 "aarch64_pwr_imm3" "Up3"))
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@@ -1805,7 +1805,7 @@
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(define_insn "*sub_uxt<mode>_multp2"
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[(set (match_operand:GPI 0 "register_operand" "=rk")
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- (minus:GPI (match_operand:GPI 4 "register_operand" "r")
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+ (minus:GPI (match_operand:GPI 4 "register_operand" "rk")
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(and:GPI
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(mult:GPI (match_operand:GPI 1 "register_operand" "r")
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(match_operand 2 "aarch64_pwr_imm3" "Up3"))
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@@ -1823,7 +1823,7 @@
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(define_insn "*sub_uxtsi_multp2_uxtw"
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[(set (match_operand:DI 0 "register_operand" "=rk")
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(zero_extend:DI
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- (minus:SI (match_operand:SI 4 "register_operand" "r")
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+ (minus:SI (match_operand:SI 4 "register_operand" "rk")
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(and:SI
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(mult:SI (match_operand:SI 1 "register_operand" "r")
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(match_operand 2 "aarch64_pwr_imm3" "Up3"))
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diff --git a/gcc/testsuite/gcc.target/aarch64/subsp.c b/gcc/testsuite/gcc.target/aarch64/subsp.c
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new file mode 100644
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index 00000000000..70d848c59d1
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--- /dev/null
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+++ b/gcc/testsuite/gcc.target/aarch64/subsp.c
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@@ -0,0 +1,19 @@
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+/* { dg-options "-O" } */
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+
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+int foo (void *);
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+
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+int
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+f1 (int *x, long y)
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+{
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+ return foo (__builtin_alloca (y));
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+}
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+
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+int
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+f2 (int *x, int y)
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+{
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+ char a[y + 1][16];
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+ return foo (a);
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+}
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+
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+/* { dg-final { scan-assembler "sub\tsp, sp, x\[0-9\]*\n" } } */
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+/* { dg-final { scan-assembler "sub\tsp, sp, x\[0-9\]*, sxtw 4\n" } } */
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