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b40826 |
2011-03-22 Ulrich Drepper <drepper@gmail.com>
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* sysdeps/unix/sysv/linux/i386/sysconf.c (intel_check_word): Increment
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round counter.
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* sysdeps/x86_64/cacheinfo.c (intel_check_word): Likewise.
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2011-03-20 Ulrich Drepper <drepper@gmail.com>
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b40826 |
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[BZ #12587]
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* sysdeps/unix/sysv/linux/i386/sysconf.c (intel_check_word):
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Handle cache information in CPU leaf 4.
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* sysdeps/x86_64/cacheinfo.c (intel_check_word): Likewise.
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Index: glibc-2.12-2-gc4ccff1/sysdeps/unix/sysv/linux/i386/sysconf.c
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===================================================================
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--- glibc-2.12-2-gc4ccff1.orig/sysdeps/unix/sysv/linux/i386/sysconf.c
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+++ glibc-2.12-2-gc4ccff1/sysdeps/unix/sysv/linux/i386/sysconf.c
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@@ -186,6 +186,57 @@ intel_check_word (int name, unsigned int
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/* No need to look further. */
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break;
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}
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+ else if (byte == 0xff)
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+ {
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+ /* CPUID leaf 0x4 contains all the information. We need to
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+ iterate over it. */
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+ unsigned int eax;
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+ unsigned int ebx;
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+ unsigned int ecx;
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+ unsigned int edx;
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+
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+ unsigned int round = 0;
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+ while (1)
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+ {
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+ asm volatile ("xchgl %%ebx, %1; cpuid; xchgl %%ebx, %1"
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+ : "=a" (eax), "=r" (ebx), "=c" (ecx), "=d" (edx)
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+ : "0" (4), "2" (round));
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+
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+ enum { null = 0, data = 1, inst = 2, uni = 3 } type = eax & 0x1f;
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+ if (type == null)
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+ /* That was the end. */
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+ break;
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+
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+ unsigned int level = (eax >> 5) & 0x7;
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+
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+ if ((level == 1 && type == data
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+ && folded_rel_name == M(_SC_LEVEL1_DCACHE_SIZE))
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+ || (level == 1 && type == inst
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+ && folded_rel_name == M(_SC_LEVEL1_ICACHE_SIZE))
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+ || (level == 2 && folded_rel_name == M(_SC_LEVEL2_CACHE_SIZE))
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+ || (level == 3 && folded_rel_name == M(_SC_LEVEL3_CACHE_SIZE))
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+ || (level == 4 && folded_rel_name == M(_SC_LEVEL4_CACHE_SIZE)))
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+ {
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+ unsigned int offset = M(name) - folded_rel_name;
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+
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+ if (offset == 0)
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+ /* Cache size. */
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+ return (((ebx >> 22) + 1)
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+ * (((ebx >> 12) & 0x3ff) + 1)
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+ * ((ebx & 0xfff) + 1)
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+ * (ecx + 1));
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+ if (offset == 1)
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+ return (ebx >> 22) + 1;
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+
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+ assert (offset == 2);
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+ return (ebx & 0xfff) + 1;
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+ }
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+
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+ ++round;
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+ }
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+ /* There is no other cache information anywhere else. */
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+ break;
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+ }
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else
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{
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if (byte == 0x49 && folded_rel_name == M(_SC_LEVEL3_CACHE_SIZE))
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b40826 |
Index: glibc-2.12-2-gc4ccff1/sysdeps/x86_64/cacheinfo.c
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===================================================================
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--- glibc-2.12-2-gc4ccff1.orig/sysdeps/x86_64/cacheinfo.c
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+++ glibc-2.12-2-gc4ccff1/sysdeps/x86_64/cacheinfo.c
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b40826 |
@@ -181,6 +181,57 @@ intel_check_word (int name, unsigned int
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/* No need to look further. */
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break;
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}
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+ else if (byte == 0xff)
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+ {
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+ /* CPUID leaf 0x4 contains all the information. We need to
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+ iterate over it. */
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+ unsigned int eax;
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+ unsigned int ebx;
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+ unsigned int ecx;
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+ unsigned int edx;
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+
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+ unsigned int round = 0;
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+ while (1)
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+ {
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+ asm volatile ("xchgl %%ebx, %1; cpuid; xchgl %%ebx, %1"
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+ : "=a" (eax), "=r" (ebx), "=c" (ecx), "=d" (edx)
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+ : "0" (4), "2" (round));
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+
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+ enum { null = 0, data = 1, inst = 2, uni = 3 } type = eax & 0x1f;
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+ if (type == null)
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+ /* That was the end. */
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+ break;
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+
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+ unsigned int level = (eax >> 5) & 0x7;
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+
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+ if ((level == 1 && type == data
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+ && folded_rel_name == M(_SC_LEVEL1_DCACHE_SIZE))
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+ || (level == 1 && type == inst
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+ && folded_rel_name == M(_SC_LEVEL1_ICACHE_SIZE))
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+ || (level == 2 && folded_rel_name == M(_SC_LEVEL2_CACHE_SIZE))
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+ || (level == 3 && folded_rel_name == M(_SC_LEVEL3_CACHE_SIZE))
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+ || (level == 4 && folded_rel_name == M(_SC_LEVEL4_CACHE_SIZE)))
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+ {
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+ unsigned int offset = M(name) - folded_rel_name;
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+
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+ if (offset == 0)
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+ /* Cache size. */
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+ return (((ebx >> 22) + 1)
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+ * (((ebx >> 12) & 0x3ff) + 1)
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+ * ((ebx & 0xfff) + 1)
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+ * (ecx + 1));
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+ if (offset == 1)
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+ return (ebx >> 22) + 1;
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+
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+ assert (offset == 2);
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+ return (ebx & 0xfff) + 1;
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+ }
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+
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+ ++round;
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+ }
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+ /* There is no other cache information anywhere else. */
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+ break;
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+ }
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else
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b40826 |
{
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b40826 |
if (byte == 0x49 && folded_rel_name == M(_SC_LEVEL3_CACHE_SIZE))
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