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2004-07-09 Jakub Jelinek <jakub@redhat.com>
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* Backport from mainline:
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2004-07-08 Paolo Bonzini <bonzini@gnu.org>
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Jakub Jelinek <jakub@redhat.com>
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* config/i386/i386.c (override_options): Enable
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SSE prefetches with -mtune, as long as we are
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compiling for i686 or higher. All i686 processors
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accept SSE prefetches as NOPS, some i586's don't.
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2004-07-07 Jakub Jelinek <jakub@redhat.com>
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* config/i386/i386.c (override_options): Don't set x86_prefetch_sse
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from -mtune= option.
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2004-07-08 Jakub Jelinek <jakub@redhat.com>
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* gcc.mist-tests/i386-prefetch.exp (PREFETCH_SSE): Change all
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-march=i386 into -march=i686. Add -march=i686 -mcpu=prescott and
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-march=prescott.
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2003-08-04 Janis Johnson <janis187@us.ibm.com>
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PR target/11739
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* gcc.misc-tests/i386-prefetch.exp: Use -march=i386 when specifying
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a value for -mcpu.
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--- gcc/config/i386/i386.c.jj 2004-07-01 12:52:56.000000000 +0200
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+++ gcc/config/i386/i386.c 2004-08-12 14:26:55.039997547 +0200
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@@ -1064,11 +1064,17 @@ override_options ()
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ix86_cpu = processor_alias_table[i].processor;
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if (TARGET_64BIT && !(processor_alias_table[i].flags & PTA_64BIT))
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error ("CPU you selected does not support x86-64 instruction set");
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+
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+ /* Intel CPUs have always interpreted SSE prefetch instructions as
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+ NOPs; so, we can enable SSE prefetch instructions even when
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+ -mtune (rather than -march) points us to a processor that has them.
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+ However, the VIA C3 gives a SIGILL, so we only do that for i686 and
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+ higher processors. */
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+ if (TARGET_CMOVE && (processor_alias_table[i].flags & PTA_PREFETCH_SSE))
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+ x86_prefetch_sse = true;
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break;
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}
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- if (processor_alias_table[i].flags & PTA_PREFETCH_SSE)
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- x86_prefetch_sse = true;
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if (i == pta_size)
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error ("bad value (%s) for -mcpu= switch", ix86_cpu_string);
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--- gcc/testsuite/gcc.misc-tests/i386-prefetch.exp.jj 2002-01-18 19:41:41.000000000 +0100
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+++ gcc/testsuite/gcc.misc-tests/i386-prefetch.exp 2004-08-12 14:34:28.702060131 +0200
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@@ -24,14 +24,14 @@
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# Do not generate prefetch instructions for the following options.
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set PREFETCH_NONE [list \
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- { -mcpu=i386 } \
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- { -mcpu=i486 } \
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- { -mcpu=i586 } \
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- { -mcpu=i686 } \
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- { -mcpu=pentium2 } \
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- { -mcpu=k6 } \
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- { -mcpu=k6-2 } \
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- { -mcpu=k6-3 } \
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+ { -march=i386 -mcpu=i386 } \
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+ { -march=i386 -mcpu=i486 } \
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+ { -march=i386 -mcpu=i586 } \
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+ { -march=i386 -mcpu=i686 } \
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+ { -march=i386 -mcpu=pentium2 } \
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+ { -march=i386 -mcpu=k6 } \
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+ { -march=i386 -mcpu=k6-2 } \
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+ { -march=i386 -mcpu=k6-3 } \
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{ -march=i386 } \
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{ -march=i486 } \
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{ -march=i586 } \
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@@ -44,12 +44,14 @@ set PREFETCH_NONE [list \
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# instructions as nops.
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set PREFETCH_SSE [list \
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- { -mcpu=pentium3 } \
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- { -mcpu=pentium4 } \
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- { -mcpu=athlon } \
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- { -mcpu=athlon-4 } \
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+ { -march=i686 -mcpu=pentium3 } \
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+ { -march=i686 -mcpu=pentium4 } \
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+ { -march=i686 -mcpu=prescott } \
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+ { -march=i686 -mcpu=athlon } \
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+ { -march=i686 -mcpu=athlon-4 } \
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{ -march=pentium3 } \
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- { -march=pentium4 } ]
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+ { -march=pentium4 } \
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+ { -march=prescott } ]
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# Generate 3DNow! prefetch instructions for the following.
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