diff --git a/SOURCES/binutils-CVE-2021-3487.patch b/SOURCES/binutils-CVE-2021-3487.patch
new file mode 100644
index 0000000..f6eb1e5
--- /dev/null
+++ b/SOURCES/binutils-CVE-2021-3487.patch
@@ -0,0 +1,38 @@
+--- binutils.orig/bfd/dwarf2.c 2021-04-14 14:24:18.945917267 +0100
++++ binutils-2.30/bfd/dwarf2.c 2021-04-14 14:25:51.908614106 +0100
+@@ -532,6 +532,10 @@ read_section (bfd * abfd,
+ /* The section may have already been read. */
+ if (contents == NULL)
+ {
++ bfd_size_type amt;
++ asection *msec;
++ ufile_ptr filesize;
++
+ msec = bfd_get_section_by_name (abfd, section_name);
+ if (! msec)
+ {
+@@ -547,10 +551,22 @@ read_section (bfd * abfd,
+ return FALSE;
+ }
+
+- *section_size = msec->rawsize ? msec->rawsize : msec->size;
++ amt = bfd_get_section_limit_octets (abfd, msec);
++ filesize = bfd_get_file_size (abfd);
++ if (amt >= filesize)
++ {
++ /* PR 26946 */
++ _bfd_error_handler (_("DWARF error: section %s is larger than its filesize! (0x%lx vs 0x%lx)"),
++ section_name, (long) amt, (long) filesize);
++ bfd_set_error (bfd_error_bad_value);
++ return FALSE;
++ }
++ *section_size = amt;
++
+ /* Paranoia - alloc one extra so that we can make sure a string
+ section is NUL terminated. */
+- amt = *section_size + 1;
++ amt += 1;
++
+ if (amt == 0)
+ {
+ bfd_set_error (bfd_error_no_memory);
diff --git a/SOURCES/binutils-aarch64-armv8.6-support.patch b/SOURCES/binutils-aarch64-armv8.6-support.patch
deleted file mode 100644
index fd070a7..0000000
--- a/SOURCES/binutils-aarch64-armv8.6-support.patch
+++ /dev/null
@@ -1,146139 +0,0 @@
-diff -rup binutils-2.30/bfd/archures.c binutils-2.30.new/bfd/archures.c
---- binutils-2.30/bfd/archures.c 2021-03-23 16:21:44.001022834 +0000
-+++ binutils-2.30.new/bfd/archures.c 2021-03-23 16:20:02.829710624 +0000
-@@ -526,6 +526,7 @@ DESCRIPTION
- .#define bfd_mach_tilegx32 2
- . bfd_arch_aarch64, {* AArch64. *}
- .#define bfd_mach_aarch64 0
-+.#define bfd_mach_aarch64_8R 1
- .#define bfd_mach_aarch64_ilp32 32
- . bfd_arch_nios2, {* Nios II. *}
- .#define bfd_mach_nios2 0
-diff -rup binutils-2.30/bfd/bfd-in2.h binutils-2.30.new/bfd/bfd-in2.h
---- binutils-2.30/bfd/bfd-in2.h 2021-03-23 16:21:44.002022828 +0000
-+++ binutils-2.30.new/bfd/bfd-in2.h 2021-03-23 16:20:02.815710719 +0000
-@@ -985,12 +985,6 @@ extern void bfd_elf64_aarch64_init_maps
- extern void bfd_elf32_aarch64_init_maps
- (bfd *);
-
--extern void bfd_elf64_aarch64_set_options
-- (bfd *, struct bfd_link_info *, int, int, int, int, int, int);
--
--extern void bfd_elf32_aarch64_set_options
-- (bfd *, struct bfd_link_info *, int, int, int, int, int, int);
--
- /* ELF AArch64 mapping symbol support. */
- #define BFD_AARCH64_SPECIAL_SYM_TYPE_MAP (1 << 0)
- #define BFD_AARCH64_SPECIAL_SYM_TYPE_TAG (1 << 1)
-@@ -2388,6 +2382,7 @@ enum bfd_architecture
- #define bfd_mach_tilegx32 2
- bfd_arch_aarch64, /* AArch64. */
- #define bfd_mach_aarch64 0
-+#define bfd_mach_aarch64_8R 1
- #define bfd_mach_aarch64_ilp32 32
- bfd_arch_nios2, /* Nios II. */
- #define bfd_mach_nios2 0
-@@ -5961,6 +5956,36 @@ of a signed value. Changes instruction
- value's sign. */
- BFD_RELOC_AARCH64_MOVW_G2_S,
-
-+/* AArch64 MOV[NZ] instruction with most significant bits 0 to 15
-+of a signed value. Changes instruction to MOVZ or MOVN depending on the
-+value's sign. */
-+ BFD_RELOC_AARCH64_MOVW_PREL_G0,
-+
-+/* AArch64 MOV[NZ] instruction with most significant bits 0 to 15
-+of a signed value. Changes instruction to MOVZ or MOVN depending on the
-+value's sign. */
-+ BFD_RELOC_AARCH64_MOVW_PREL_G0_NC,
-+
-+/* AArch64 MOVK instruction with most significant bits 16 to 31
-+of a signed value. */
-+ BFD_RELOC_AARCH64_MOVW_PREL_G1,
-+
-+/* AArch64 MOVK instruction with most significant bits 16 to 31
-+of a signed value. */
-+ BFD_RELOC_AARCH64_MOVW_PREL_G1_NC,
-+
-+/* AArch64 MOVK instruction with most significant bits 32 to 47
-+of a signed value. */
-+ BFD_RELOC_AARCH64_MOVW_PREL_G2,
-+
-+/* AArch64 MOVK instruction with most significant bits 32 to 47
-+of a signed value. */
-+ BFD_RELOC_AARCH64_MOVW_PREL_G2_NC,
-+
-+/* AArch64 MOVK instruction with most significant bits 47 to 63
-+of a signed value. */
-+ BFD_RELOC_AARCH64_MOVW_PREL_G3,
-+
- /* AArch64 Load Literal instruction, holding a 19 bit pc-relative word
- offset. The lowest two bits must be zero and are not stored in the
- instruction, giving a 21 bit signed byte offset. */
-@@ -6188,6 +6213,34 @@ instructions. */
- /* AArch64 TLS LOCAL EXEC relocation. */
- BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC,
-
-+/* bit[11:1] of byte offset to module TLS base address, encoded in ldst
-+instructions. */
-+ BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12,
-+
-+/* Similar as BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12, but no overflow check. */
-+ BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC,
-+
-+/* bit[11:2] of byte offset to module TLS base address, encoded in ldst
-+instructions. */
-+ BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12,
-+
-+/* Similar as BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12, but no overflow check. */
-+ BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC,
-+
-+/* bit[11:3] of byte offset to module TLS base address, encoded in ldst
-+instructions. */
-+ BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12,
-+
-+/* Similar as BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12, but no overflow check. */
-+ BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC,
-+
-+/* bit[11:0] of byte offset to module TLS base address, encoded in ldst
-+instructions. */
-+ BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12,
-+
-+/* Similar as BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12, but no overflow check. */
-+ BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC,
-+
- /* AArch64 TLS DESC relocation. */
- BFD_RELOC_AARCH64_TLSDESC_LD_PREL19,
-
-@@ -6271,6 +6324,14 @@ any object files. */
- /* Similar as BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12, but no overflow check. */
- BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC,
-
-+/* AArch64 pseudo relocation code for TLS local exec mode. It's to be
-+used internally by the AArch64 assembler and not (currently) written to
-+any object files. */
-+ BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12,
-+
-+/* Similar as BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12, but no overflow check. */
-+ BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC,
-+
- /* AArch64 pseudo relocation code to be used internally by the AArch64
- assembler and not (currently) written to any object files. */
- BFD_RELOC_AARCH64_LD_GOT_LO12_NC,
-diff -rup binutils-2.30/bfd/cpu-aarch64.c binutils-2.30.new/bfd/cpu-aarch64.c
---- binutils-2.30/bfd/cpu-aarch64.c 2018-01-13 13:31:15.000000000 +0000
-+++ binutils-2.30.new/bfd/cpu-aarch64.c 2021-03-23 16:20:02.830710617 +0000
-@@ -1,5 +1,5 @@
- /* BFD support for AArch64.
-- Copyright (C) 2009-2018 Free Software Foundation, Inc.
-+ Copyright (C) 2009-2021 Free Software Foundation, Inc.
- Contributed by ARM Ltd.
-
- This file is part of BFD, the Binary File Descriptor library.
-@@ -22,6 +22,7 @@
- #include "bfd.h"
- #include "libbfd.h"
- #include "libiberty.h"
-+#include "cpu-aarch64.h"
-
- /* This routine is provided two arch_infos and works out which Aarch64
- machine which would be compatible with both and returns a pointer
-@@ -68,10 +69,11 @@ static struct
- }
- processors[] =
- {
-- /* These two are example CPUs supported in GCC, once we have real
-- CPUs they will be removed. */
-- { bfd_mach_aarch64, "example-1" },
-- { bfd_mach_aarch64, "example-2" }
-+ { bfd_mach_aarch64, "cortex-a34" },
-+ { bfd_mach_aarch64, "cortex-a65" },
-+ { bfd_mach_aarch64, "cortex-a65ae" },
-+ { bfd_mach_aarch64, "cortex-a76ae" },
-+ { bfd_mach_aarch64, "cortex-a77" }
- };
-
- static bfd_boolean
-@@ -103,10 +105,14 @@ scan (const struct bfd_arch_info *info,
- #define N(NUMBER, PRINT, WORDSIZE, DEFAULT, NEXT) \
- { WORDSIZE, WORDSIZE, 8, bfd_arch_aarch64, NUMBER, \
- "aarch64", PRINT, 4, DEFAULT, compatible, scan, \
-- bfd_arch_default_fill, NEXT }
-+ bfd_arch_default_fill, NEXT, 0 }
-+
-+static const bfd_arch_info_type bfd_aarch64_arch_v8_r =
-+ N (bfd_mach_aarch64_8R, "aarch64:armv8-r", 64, FALSE, NULL);
-
- static const bfd_arch_info_type bfd_aarch64_arch_ilp32 =
-- N (bfd_mach_aarch64_ilp32, "aarch64:ilp32", 32, FALSE, NULL);
-+ N (bfd_mach_aarch64_ilp32, "aarch64:ilp32", 32, FALSE,
-+ &bfd_aarch64_arch_v8_r);
-
- const bfd_arch_info_type bfd_aarch64_arch =
- N (0, "aarch64", 64, TRUE, &bfd_aarch64_arch_ilp32);
-diff -rup binutils-2.30/bfd/reloc.c binutils-2.30.new/bfd/reloc.c
---- binutils-2.30/bfd/reloc.c 2018-01-13 13:31:15.000000000 +0000
-+++ binutils-2.30.new/bfd/reloc.c 2021-03-23 16:20:02.829710624 +0000
-@@ -7071,6 +7071,43 @@ ENUMDOC
- of a signed value. Changes instruction to MOVZ or MOVN depending on the
- value's sign.
- ENUM
-+ BFD_RELOC_AARCH64_MOVW_PREL_G0
-+ENUMDOC
-+ AArch64 MOV[NZ] instruction with most significant bits 0 to 15
-+ of a signed value. Changes instruction to MOVZ or MOVN depending on the
-+ value's sign.
-+ENUM
-+ BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
-+ENUMDOC
-+ AArch64 MOV[NZ] instruction with most significant bits 0 to 15
-+ of a signed value. Changes instruction to MOVZ or MOVN depending on the
-+ value's sign.
-+ENUM
-+ BFD_RELOC_AARCH64_MOVW_PREL_G1
-+ENUMDOC
-+ AArch64 MOVK instruction with most significant bits 16 to 31
-+ of a signed value.
-+ENUM
-+ BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
-+ENUMDOC
-+ AArch64 MOVK instruction with most significant bits 16 to 31
-+ of a signed value.
-+ENUM
-+ BFD_RELOC_AARCH64_MOVW_PREL_G2
-+ENUMDOC
-+ AArch64 MOVK instruction with most significant bits 32 to 47
-+ of a signed value.
-+ENUM
-+ BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
-+ENUMDOC
-+ AArch64 MOVK instruction with most significant bits 32 to 47
-+ of a signed value.
-+ENUM
-+ BFD_RELOC_AARCH64_MOVW_PREL_G3
-+ENUMDOC
-+ AArch64 MOVK instruction with most significant bits 47 to 63
-+ of a signed value.
-+ENUM
- BFD_RELOC_AARCH64_LD_LO19_PCREL
- ENUMDOC
- AArch64 Load Literal instruction, holding a 19 bit pc-relative word
-@@ -7359,6 +7396,42 @@ ENUM
- ENUMDOC
- AArch64 TLS LOCAL EXEC relocation.
- ENUM
-+ BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
-+ENUMDOC
-+ bit[11:1] of byte offset to module TLS base address, encoded in ldst
-+ instructions.
-+ENUM
-+ BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
-+ENUMDOC
-+ Similar as BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12, but no overflow check.
-+ENUM
-+ BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
-+ENUMDOC
-+ bit[11:2] of byte offset to module TLS base address, encoded in ldst
-+ instructions.
-+ENUM
-+ BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
-+ENUMDOC
-+ Similar as BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12, but no overflow check.
-+ENUM
-+ BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
-+ENUMDOC
-+ bit[11:3] of byte offset to module TLS base address, encoded in ldst
-+ instructions.
-+ENUM
-+ BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
-+ENUMDOC
-+ Similar as BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12, but no overflow check.
-+ENUM
-+ BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
-+ENUMDOC
-+ bit[11:0] of byte offset to module TLS base address, encoded in ldst
-+ instructions.
-+ENUM
-+ BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
-+ENUMDOC
-+ Similar as BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12, but no overflow check.
-+ENUM
- BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
- ENUMDOC
- AArch64 TLS DESC relocation.
-@@ -7467,6 +7540,16 @@ ENUM
- ENUMDOC
- Similar as BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12, but no overflow check.
- ENUM
-+ BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
-+ENUMDOC
-+ AArch64 pseudo relocation code for TLS local exec mode. It's to be
-+ used internally by the AArch64 assembler and not (currently) written to
-+ any object files.
-+ENUM
-+ BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
-+ENUMDOC
-+ Similar as BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12, but no overflow check.
-+ENUM
- BFD_RELOC_AARCH64_LD_GOT_LO12_NC
- ENUMDOC
- AArch64 pseudo relocation code to be used internally by the AArch64
-diff -rup binutils-2.30/gas/config/tc-aarch64.c binutils-2.30.new/gas/config/tc-aarch64.c
---- binutils-2.30/gas/config/tc-aarch64.c 2021-03-23 16:21:44.128021971 +0000
-+++ binutils-2.30.new/gas/config/tc-aarch64.c 2021-03-23 16:19:55.031763633 +0000
-@@ -1,6 +1,6 @@
- /* tc-aarch64.c -- Assemble for the AArch64 ISA
-
-- Copyright (C) 2009-2018 Free Software Foundation, Inc.
-+ Copyright (C) 2009-2021 Free Software Foundation, Inc.
- Contributed by ARM Ltd.
-
- This file is part of GAS.
-@@ -35,6 +35,9 @@
-
- #include "dwarf2dbg.h"
-
-+/* Number of littlenums required to hold an extended precision number. */
-+#define MAX_LITTLENUMS 6
-+
- /* Types of processor to assemble for. */
- #ifndef CPU_DEFAULT
- #define CPU_DEFAULT AARCH64_ARCH_V8
-@@ -55,6 +58,9 @@ static const aarch64_feature_set *march_
- /* Constants for known architecture features. */
- static const aarch64_feature_set cpu_default = CPU_DEFAULT;
-
-+/* Currently active instruction sequence. */
-+static aarch64_instr_sequence *insn_sequence = NULL;
-+
- #ifdef OBJ_ELF
- /* Pre-defined "_GLOBAL_OFFSET_TABLE_" */
- static symbolS *GOT_symbol;
-@@ -146,6 +152,13 @@ static aarch64_instruction inst;
- static bfd_boolean parse_operands (char *, const aarch64_opcode *);
- static bfd_boolean programmer_friendly_fixup (aarch64_instruction *);
-
-+#ifdef OBJ_ELF
-+# define now_instr_sequence seg_info \
-+ (now_seg)->tc_segment_info_data.insn_sequence
-+#else
-+static struct aarch64_instr_sequence now_instr_sequence;
-+#endif
-+
- /* Diagnostics inline function utilities.
-
- These are lightweight utilities which should only be called by parse_operands
-@@ -228,9 +241,6 @@ set_fatal_syntax_error (const char *erro
- set_error (AARCH64_OPDE_FATAL_SYNTAX_ERROR, error);
- }
-
--/* Number of littlenums required to hold an extended precision number. */
--#define MAX_LITTLENUMS 6
--
- /* Return value for certain parsers when the parsing fails; those parsers
- return the information of the parsed result, e.g. register number, on
- success. */
-@@ -243,12 +253,6 @@ set_fatal_syntax_error (const char *erro
- typedef struct
- {
- const char *template;
-- unsigned long value;
--} asm_barrier_opt;
--
--typedef struct
--{
-- const char *template;
- uint32_t value;
- } asm_nzcv;
-
-@@ -439,24 +443,28 @@ get_reg_expected_msg (aarch64_reg_type r
-
- /* Some well known registers that we refer to directly elsewhere. */
- #define REG_SP 31
-+#define REG_ZR 31
-
- /* Instructions take 4 bytes in the object file. */
- #define INSN_SIZE 4
-
--static struct hash_control *aarch64_ops_hsh;
--static struct hash_control *aarch64_cond_hsh;
--static struct hash_control *aarch64_shift_hsh;
--static struct hash_control *aarch64_sys_regs_hsh;
--static struct hash_control *aarch64_pstatefield_hsh;
--static struct hash_control *aarch64_sys_regs_ic_hsh;
--static struct hash_control *aarch64_sys_regs_dc_hsh;
--static struct hash_control *aarch64_sys_regs_at_hsh;
--static struct hash_control *aarch64_sys_regs_tlbi_hsh;
--static struct hash_control *aarch64_reg_hsh;
--static struct hash_control *aarch64_barrier_opt_hsh;
--static struct hash_control *aarch64_nzcv_hsh;
--static struct hash_control *aarch64_pldop_hsh;
--static struct hash_control *aarch64_hint_opt_hsh;
-+#define htab_t struct hash_control *
-+
-+static htab_t aarch64_ops_hsh;
-+static htab_t aarch64_cond_hsh;
-+static htab_t aarch64_shift_hsh;
-+static htab_t aarch64_sys_regs_hsh;
-+static htab_t aarch64_pstatefield_hsh;
-+static htab_t aarch64_sys_regs_ic_hsh;
-+static htab_t aarch64_sys_regs_dc_hsh;
-+static htab_t aarch64_sys_regs_at_hsh;
-+static htab_t aarch64_sys_regs_tlbi_hsh;
-+static htab_t aarch64_sys_regs_sr_hsh;
-+static htab_t aarch64_reg_hsh;
-+static htab_t aarch64_barrier_opt_hsh;
-+static htab_t aarch64_nzcv_hsh;
-+static htab_t aarch64_pldop_hsh;
-+static htab_t aarch64_hint_opt_hsh;
-
- /* Stuff needed to resolve the label ambiguity
- As:
-@@ -520,7 +528,7 @@ const char EXP_CHARS[] = "eE";
- /* As in 0f12.456 */
- /* or 0d1.2345e12 */
-
--const char FLT_CHARS[] = "rRsSfFdDxXeEpP";
-+const char FLT_CHARS[] = "rRsSfFdDxXeEpPhH";
-
- /* Prefix character that indicates the start of an immediate value. */
- #define is_immediate_prefix(C) ((C) == '#')
-@@ -618,6 +626,96 @@ my_get_expression (expressionS * ep, cha
- return TRUE;
- }
-
-+#define MAX_PRECISION 5
-+#define H_PRECISION 1
-+#define F_PRECISION 2
-+#define D_PRECISION 4
-+#define X_PRECISION 5
-+#define P_PRECISION 5
-+/* Length in LittleNums of guard bits. */
-+#define GUARD 2
-+
-+static void
-+make_invalid_floating_point_number (LITTLENUM_TYPE *words)
-+{
-+ as_bad (_("cannot create floating-point number"));
-+ /* Zero the leftmost bit. */
-+ words[0] = (LITTLENUM_TYPE) ((unsigned) -1) >> 1;
-+ words[1] = (LITTLENUM_TYPE) -1;
-+ words[2] = (LITTLENUM_TYPE) -1;
-+ words[3] = (LITTLENUM_TYPE) -1;
-+ words[4] = (LITTLENUM_TYPE) -1;
-+ words[5] = (LITTLENUM_TYPE) -1;
-+}
-+
-+char * atof_ieee_detail (char *, int, int, LITTLENUM_TYPE *, FLONUM_TYPE *);
-+
-+/* Build a floating point constant at str into a IEEE floating
-+ point number. This function does the same thing as atof_ieee
-+ however it allows more control over the exact format, i.e.
-+ explicitly specifying the precision and number of exponent bits
-+ instead of relying on this infomation being deduced from a given type.
-+
-+ If generic_float_info is not NULL then it will be set to contain generic
-+ infomation about the parsed floating point number.
-+
-+ Returns pointer past text consumed. */
-+char *
-+atof_ieee_detail (char * str,
-+ int precision,
-+ int exponent_bits,
-+ LITTLENUM_TYPE * words,
-+ FLONUM_TYPE * generic_float_info)
-+{
-+ /* Extra bits for zeroed low-order bits.
-+ The 1st MAX_PRECISION are zeroed, the last contain flonum bits. */
-+ static LITTLENUM_TYPE bits[MAX_PRECISION + MAX_PRECISION + GUARD];
-+ char *return_value;
-+
-+ /* Number of 16-bit words in the format. */
-+ FLONUM_TYPE save_gen_flonum;
-+
-+ /* We have to save the generic_floating_point_number because it
-+ contains storage allocation about the array of LITTLENUMs where
-+ the value is actually stored. We will allocate our own array of
-+ littlenums below, but have to restore the global one on exit. */
-+ save_gen_flonum = generic_floating_point_number;
-+
-+ return_value = str;
-+ generic_floating_point_number.low = bits + MAX_PRECISION;
-+ generic_floating_point_number.high = NULL;
-+ generic_floating_point_number.leader = NULL;
-+ generic_floating_point_number.exponent = 0;
-+ generic_floating_point_number.sign = '\0';
-+
-+ /* Use more LittleNums than seems necessary: the highest flonum may
-+ have 15 leading 0 bits, so could be useless. */
-+
-+ memset (bits, '\0', sizeof (LITTLENUM_TYPE) * MAX_PRECISION);
-+
-+ generic_floating_point_number.high
-+ = generic_floating_point_number.low + precision - 1 + GUARD;
-+
-+ if (atof_generic (&return_value, ".", EXP_CHARS,
-+ &generic_floating_point_number))
-+ {
-+ make_invalid_floating_point_number (words);
-+ return NULL;
-+ }
-+
-+ if (generic_float_info)
-+ *generic_float_info = generic_floating_point_number;
-+
-+ gen_to_words (words, precision, exponent_bits);
-+
-+ /* Restore the generic_floating_point_number's storage alloc (and
-+ everything else). */
-+ generic_floating_point_number = save_gen_flonum;
-+
-+ return return_value;
-+}
-+
-+
- /* Turn a string in input_line_pointer into a floating point constant
- of type TYPE, and store the appropriate bytes in *LITP. The number
- of LITTLENUMS emitted is stored in *SIZEP. An error message is
-@@ -626,6 +724,54 @@ my_get_expression (expressionS * ep, cha
- const char *
- md_atof (int type, char *litP, int *sizeP)
- {
-+ /* If this is a bfloat16 type, then parse it slightly differently -
-+ as it does not follow the IEEE standard exactly. */
-+ if (type == 'b')
-+ {
-+ char * t;
-+ LITTLENUM_TYPE words[MAX_LITTLENUMS];
-+ FLONUM_TYPE generic_float;
-+
-+ t = atof_ieee_detail (input_line_pointer, 1, 8, words, &generic_float);
-+
-+ if (t)
-+ input_line_pointer = t;
-+ else
-+ return _("invalid floating point number");
-+
-+ switch (generic_float.sign)
-+ {
-+ /* Is +Inf. */
-+ case 'P':
-+ words[0] = 0x7f80;
-+ break;
-+
-+ /* Is -Inf. */
-+ case 'N':
-+ words[0] = 0xff80;
-+ break;
-+
-+ /* Is NaN. */
-+ /* bfloat16 has two types of NaN - quiet and signalling.
-+ Quiet NaN has bit[6] == 1 && faction != 0, whereas
-+ signalling Nan's have bit[0] == 0 && fraction != 0.
-+ Chose this specific encoding as it is the same form
-+ as used by other IEEE 754 encodings in GAS. */
-+ case 0:
-+ words[0] = 0x7fff;
-+ break;
-+
-+ default:
-+ break;
-+ }
-+
-+ *sizeP = 2;
-+
-+ md_number_to_chars (litP, (valueT) words[0], sizeof (LITTLENUM_TYPE));
-+
-+ return NULL;
-+ }
-+
- return ieee_md_atof (type, litP, sizeP, target_big_endian);
- }
-
-@@ -826,7 +972,7 @@ parse_vector_type_for_operand (aarch64_r
- return FALSE;
- }
-
--elt_size:
-+ elt_size:
- switch (TOLOWER (*ptr))
- {
- case 'b':
-@@ -1945,7 +2091,7 @@ s_variant_pcs (int ignored ATTRIBUTE_UNU
- restore_line_pointer (c);
- demand_empty_rest_of_line ();
- bfdsym = symbol_get_bfdsym (sym);
-- elfsym = elf_symbol_from (bfd_asymbol_bfd (bfdsym), bfdsym);
-+ elfsym = elf_symbol_from (NULL, bfdsym);
- gas_assert (elfsym);
- elfsym->internal_elf_sym.st_other |= STO_AARCH64_VARIANT_PCS;
- }
-@@ -2088,6 +2234,8 @@ const pseudo_typeS md_pseudo_table[] = {
- {"dword", s_aarch64_elf_cons, 8},
- {"variant_pcs", s_variant_pcs, 0},
- #endif
-+ {"float16", float_cons, 'h'},
-+ {"bfloat16", float_cons, 'b'},
- {0, 0, 0}
- };
-
-@@ -2122,7 +2270,7 @@ reg_name_p (char *str, aarch64_reg_type
- return FALSE;
-
- skip_whitespace (str);
-- if (*str == ',' || is_end_of_line[(unsigned int) *str])
-+ if (*str == ',' || is_end_of_line[(unsigned char) *str])
- return TRUE;
-
- return FALSE;
-@@ -2302,7 +2450,6 @@ parse_aarch64_imm_float (char **ccp, int
- char *str = *ccp;
- char *fpnum;
- LITTLENUM_TYPE words[MAX_LITTLENUMS];
-- int found_fpchar = 0;
- int64_t val = 0;
- unsigned fpword = 0;
- bfd_boolean hex_p = FALSE;
-@@ -2332,26 +2479,10 @@ parse_aarch64_imm_float (char **ccp, int
-
- hex_p = TRUE;
- }
-- else
-- {
-- if (reg_name_p (str, reg_type))
-- {
-- set_recoverable_error (_("immediate operand required"));
-- return FALSE;
-- }
--
-- /* We must not accidentally parse an integer as a floating-point number.
-- Make sure that the value we parse is not an integer by checking for
-- special characters '.' or 'e'. */
-- for (; *fpnum != '\0' && *fpnum != ' ' && *fpnum != '\n'; fpnum++)
-- if (*fpnum == '.' || *fpnum == 'e' || *fpnum == 'E')
-- {
-- found_fpchar = 1;
-- break;
-- }
--
-- if (!found_fpchar)
-- return FALSE;
-+ else if (reg_name_p (str, reg_type))
-+ {
-+ set_recoverable_error (_("immediate operand required"));
-+ return FALSE;
- }
-
- if (! hex_p)
-@@ -2373,7 +2504,7 @@ parse_aarch64_imm_float (char **ccp, int
- *ccp = str;
- return TRUE;
-
--invalid_fp:
-+ invalid_fp:
- set_fatal_syntax_error (_("invalid floating-point constant"));
- return FALSE;
- }
-@@ -2600,6 +2731,69 @@ static struct reloc_table_entry reloc_ta
- 0,
- 0},
-
-+ /* Most significant bits 0-15 of signed/unsigned address/value: MOVZ */
-+ {"prel_g0", 1,
-+ 0, /* adr_type */
-+ 0,
-+ BFD_RELOC_AARCH64_MOVW_PREL_G0,
-+ 0,
-+ 0,
-+ 0},
-+
-+ /* Most significant bits 0-15 of signed/unsigned address/value: MOVK */
-+ {"prel_g0_nc", 1,
-+ 0, /* adr_type */
-+ 0,
-+ BFD_RELOC_AARCH64_MOVW_PREL_G0_NC,
-+ 0,
-+ 0,
-+ 0},
-+
-+ /* Most significant bits 16-31 of signed/unsigned address/value: MOVZ */
-+ {"prel_g1", 1,
-+ 0, /* adr_type */
-+ 0,
-+ BFD_RELOC_AARCH64_MOVW_PREL_G1,
-+ 0,
-+ 0,
-+ 0},
-+
-+ /* Most significant bits 16-31 of signed/unsigned address/value: MOVK */
-+ {"prel_g1_nc", 1,
-+ 0, /* adr_type */
-+ 0,
-+ BFD_RELOC_AARCH64_MOVW_PREL_G1_NC,
-+ 0,
-+ 0,
-+ 0},
-+
-+ /* Most significant bits 32-47 of signed/unsigned address/value: MOVZ */
-+ {"prel_g2", 1,
-+ 0, /* adr_type */
-+ 0,
-+ BFD_RELOC_AARCH64_MOVW_PREL_G2,
-+ 0,
-+ 0,
-+ 0},
-+
-+ /* Most significant bits 32-47 of signed/unsigned address/value: MOVK */
-+ {"prel_g2_nc", 1,
-+ 0, /* adr_type */
-+ 0,
-+ BFD_RELOC_AARCH64_MOVW_PREL_G2_NC,
-+ 0,
-+ 0,
-+ 0},
-+
-+ /* Most significant bits 48-63 of signed/unsigned address/value: MOVZ */
-+ {"prel_g3", 1,
-+ 0, /* adr_type */
-+ 0,
-+ BFD_RELOC_AARCH64_MOVW_PREL_G3,
-+ 0,
-+ 0,
-+ 0},
-+
- /* Get to the page containing GOT entry for a symbol. */
- {"got", 1,
- 0, /* adr_type */
-@@ -2862,7 +3056,7 @@ static struct reloc_table_entry reloc_ta
- 0,
- 0,
- BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12,
-- 0,
-+ BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12,
- 0},
-
- /* Get tp offset for a symbol. */
-@@ -2880,7 +3074,7 @@ static struct reloc_table_entry reloc_ta
- 0,
- 0,
- BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC,
-- 0,
-+ BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC,
- 0},
-
- /* Most significant bits 32-47 of address/value: MOVZ. */
-@@ -3337,6 +3531,7 @@ parse_shifter_operand_reloc (char **str,
- [base,Xm,SXTX {#imm}]
- [base,Wm,(S|U)XTW {#imm}]
- Pre-indexed
-+ [base]! // in ldraa/ldrab exclusive
- [base,#imm]!
- Post-indexed
- [base],#imm
-@@ -3350,6 +3545,7 @@ parse_shifter_operand_reloc (char **str,
- [base,Zm.D,(S|U)XTW {#imm}] // ignores top 32 bits of Zm.D elements
- [Zn.S,#imm]
- [Zn.D,#imm]
-+ [Zn.S{, Xm}]
- [Zn.S,Zm.S{,LSL #imm}] // in ADR
- [Zn.D,Zm.D{,LSL #imm}] // in ADR
- [Zn.D,Zm.D,(S|U)XTW {#imm}] // in ADR
-@@ -3515,6 +3711,7 @@ parse_address_main (char **str, aarch64_
- return FALSE;
- }
- /* We only accept:
-+ [base,Xm] # For vector plus scalar SVE2 indexing.
- [base,Xm{,LSL #imm}]
- [base,Xm,SXTX {#imm}]
- [base,Wm,(S|U)XTW {#imm}] */
-@@ -3528,7 +3725,10 @@ parse_address_main (char **str, aarch64_
- return FALSE;
- }
- if (aarch64_get_qualifier_esize (*base_qualifier)
-- != aarch64_get_qualifier_esize (*offset_qualifier))
-+ != aarch64_get_qualifier_esize (*offset_qualifier)
-+ && (operand->type != AARCH64_OPND_SVE_ADDR_ZX
-+ || *base_qualifier != AARCH64_OPND_QLF_S_S
-+ || *offset_qualifier != AARCH64_OPND_QLF_X))
- {
- set_syntax_error (_("offset has different size from base"));
- return FALSE;
-@@ -3646,18 +3846,43 @@ parse_address_main (char **str, aarch64_
- }
-
- /* If at this point neither .preind nor .postind is set, we have a
-- bare [Rn]{!}; reject [Rn]! but accept [Rn] as a shorthand for [Rn,#0]. */
-+ bare [Rn]{!}; only accept [Rn]! as a shorthand for [Rn,#0]! for ldraa and
-+ ldrab, accept [Rn] as a shorthand for [Rn,#0].
-+ For SVE2 vector plus scalar offsets, allow [Zn.<T>] as shorthand for
-+ [Zn.<T>, xzr]. */
- if (operand->addr.preind == 0 && operand->addr.postind == 0)
- {
- if (operand->addr.writeback)
- {
-- /* Reject [Rn]! */
-- set_syntax_error (_("missing offset in the pre-indexed address"));
-- return FALSE;
-+ if (operand->type == AARCH64_OPND_ADDR_SIMM10)
-+ {
-+ /* Accept [Rn]! as a shorthand for [Rn,#0]! */
-+ operand->addr.offset.is_reg = 0;
-+ operand->addr.offset.imm = 0;
-+ operand->addr.preind = 1;
-+ }
-+ else
-+ {
-+ /* Reject [Rn]! */
-+ set_syntax_error (_("missing offset in the pre-indexed address"));
-+ return FALSE;
-+ }
-+ }
-+ else
-+ {
-+ operand->addr.preind = 1;
-+ if (operand->type == AARCH64_OPND_SVE_ADDR_ZX)
-+ {
-+ operand->addr.offset.is_reg = 1;
-+ operand->addr.offset.regno = REG_ZR;
-+ *offset_qualifier = AARCH64_OPND_QLF_X;
-+ }
-+ else
-+ {
-+ inst.reloc.exp.X_op = O_constant;
-+ inst.reloc.exp.X_add_number = 0;
-+ }
- }
-- operand->addr.preind = 1;
-- inst.reloc.exp.X_op = O_constant;
-- inst.reloc.exp.X_add_number = 0;
- }
-
- *str = p;
-@@ -3849,7 +4074,7 @@ static int
- parse_barrier (char **str)
- {
- char *p, *q;
-- const asm_barrier_opt *o;
-+ const struct aarch64_name_value_pair *o;
-
- p = q = *str;
- while (ISALPHA (*q))
-@@ -3881,7 +4106,7 @@ parse_barrier_psb (char **str,
- if (!o)
- {
- set_fatal_syntax_error
-- ( _("unknown or missing option to PSB"));
-+ ( _("unknown or missing option to PSB/TSB"));
- return PARSE_FAIL;
- }
-
-@@ -3889,7 +4114,48 @@ parse_barrier_psb (char **str,
- {
- /* PSB only accepts option name 'CSYNC'. */
- set_syntax_error
-- (_("the specified option is not accepted for PSB"));
-+ (_("the specified option is not accepted for PSB/TSB"));
-+ return PARSE_FAIL;
-+ }
-+
-+ *str = q;
-+ *hint_opt = o;
-+ return 0;
-+}
-+
-+/* Parse an operand for BTI. Set *HINT_OPT to the hint-option record
-+ return 0 if successful. Otherwise return PARSE_FAIL. */
-+
-+static int
-+parse_bti_operand (char **str,
-+ const struct aarch64_name_value_pair ** hint_opt)
-+{
-+ char *p, *q;
-+ const struct aarch64_name_value_pair *o;
-+
-+ p = q = *str;
-+ while (ISALPHA (*q))
-+ q++;
-+
-+ o = hash_find_n (aarch64_hint_opt_hsh, p, q - p);
-+ if (!o)
-+ {
-+ set_fatal_syntax_error
-+ ( _("unknown option to BTI"));
-+ return PARSE_FAIL;
-+ }
-+
-+ switch (o->value)
-+ {
-+ /* Valid BTI operands. */
-+ case HINT_OPD_C:
-+ case HINT_OPD_J:
-+ case HINT_OPD_JC:
-+ break;
-+
-+ default:
-+ set_syntax_error
-+ (_("unknown option to BTI"));
- return PARSE_FAIL;
- }
-
-@@ -3909,21 +4175,26 @@ parse_barrier_psb (char **str,
- */
-
- static int
--parse_sys_reg (char **str, struct hash_control *sys_regs,
-- int imple_defined_p, int pstatefield_p)
-+parse_sys_reg (char **str, htab_t sys_regs,
-+ int imple_defined_p, int pstatefield_p,
-+ uint32_t* flags)
- {
- char *p, *q;
-- char buf[32];
-+ char buf[AARCH64_MAX_SYSREG_NAME_LEN];
- const aarch64_sys_reg *o;
- int value;
-
- p = buf;
- for (q = *str; ISALNUM (*q) || *q == '_'; q++)
-- if (p < buf + 31)
-+ if (p < buf + (sizeof (buf) - 1))
- *p++ = TOLOWER (*q);
- *p = '\0';
-- /* Assert that BUF be large enough. */
-- gas_assert (p - buf == q - *str);
-+
-+ /* If the name is longer than AARCH64_MAX_SYSREG_NAME_LEN then it cannot be a
-+ valid system register. This is enforced by construction of the hash
-+ table. */
-+ if (p - buf != q - *str)
-+ return PARSE_FAIL;
-
- o = hash_find (sys_regs, buf);
- if (!o)
-@@ -3941,6 +4212,8 @@ parse_sys_reg (char **str, struct hash_c
- if (op0 > 3 || op1 > 7 || cn > 15 || cm > 15 || op2 > 7)
- return PARSE_FAIL;
- value = (op0 << 14) | (op1 << 11) | (cn << 7) | (cm << 3) | op2;
-+ if (flags)
-+ *flags = 0;
- }
- }
- else
-@@ -3948,13 +4221,17 @@ parse_sys_reg (char **str, struct hash_c
- if (pstatefield_p && !aarch64_pstatefield_supported_p (cpu_variant, o))
- as_bad (_("selected processor does not support PSTATE field "
- "name '%s'"), buf);
-- if (!pstatefield_p && !aarch64_sys_reg_supported_p (cpu_variant, o))
-+ if (!pstatefield_p
-+ && !aarch64_sys_ins_reg_supported_p (cpu_variant, o->name,
-+ o->value, o->flags, o->features))
- as_bad (_("selected processor does not support system register "
- "name '%s'"), buf);
-- if (aarch64_sys_reg_deprecated_p (o))
-+ if (aarch64_sys_reg_deprecated_p (o->flags))
- as_warn (_("system register name '%s' is deprecated and may be "
- "removed in a future release"), buf);
- value = o->value;
-+ if (flags)
-+ *flags = o->flags;
- }
-
- *str = q;
-@@ -3965,25 +4242,35 @@ parse_sys_reg (char **str, struct hash_c
- for the option, or NULL. */
-
- static const aarch64_sys_ins_reg *
--parse_sys_ins_reg (char **str, struct hash_control *sys_ins_regs)
-+parse_sys_ins_reg (char **str, htab_t sys_ins_regs)
- {
- char *p, *q;
-- char buf[32];
-+ char buf[AARCH64_MAX_SYSREG_NAME_LEN];
- const aarch64_sys_ins_reg *o;
-
- p = buf;
- for (q = *str; ISALNUM (*q) || *q == '_'; q++)
-- if (p < buf + 31)
-+ if (p < buf + (sizeof (buf) - 1))
- *p++ = TOLOWER (*q);
- *p = '\0';
-
-+ /* If the name is longer than AARCH64_MAX_SYSREG_NAME_LEN then it cannot be a
-+ valid system register. This is enforced by construction of the hash
-+ table. */
-+ if (p - buf != q - *str)
-+ return NULL;
-+
- o = hash_find (sys_ins_regs, buf);
- if (!o)
- return NULL;
-
-- if (!aarch64_sys_ins_reg_supported_p (cpu_variant, o))
-+ if (!aarch64_sys_ins_reg_supported_p (cpu_variant,
-+ o->name, o->value, o->flags, 0))
- as_bad (_("selected processor does not support system register "
- "name '%s'"), buf);
-+ if (aarch64_sys_reg_deprecated_p (o->flags))
-+ as_warn (_("system register name '%s' is deprecated and may be "
-+ "removed in a future release"), buf);
-
- *str = q;
- return o;
-@@ -4137,7 +4424,10 @@ reencode_movzn_to_movn (uint32_t opcode)
- static fixS *
- fix_new_aarch64 (fragS * frag,
- int where,
-- short int size, expressionS * exp, int pc_rel, int reloc)
-+ short int size,
-+ expressionS * exp,
-+ int pc_rel,
-+ int reloc)
- {
- fixS *new_fix;
-
-@@ -4371,6 +4661,7 @@ record_operand_error (const aarch64_opco
- info.index = idx;
- info.kind = kind;
- info.error = error;
-+ info.non_fatal = FALSE;
- record_operand_error_info (opcode, &info);
- }
-
-@@ -4386,6 +4677,7 @@ record_operand_error_with_data (const aa
- info.data[0] = extra_data[0];
- info.data[1] = extra_data[1];
- info.data[2] = extra_data[2];
-+ info.non_fatal = FALSE;
- record_operand_error_info (opcode, &info);
- }
-
-@@ -4504,7 +4796,8 @@ print_operands (char *buf, const aarch64
- break;
-
- /* Generate the operand string in STR. */
-- aarch64_print_operand (str, sizeof (str), 0, opcode, opnds, i, NULL, NULL);
-+ aarch64_print_operand (str, sizeof (str), 0, opcode, opnds, i, NULL, NULL,
-+ NULL, cpu_variant);
-
- /* Delimiter. */
- if (str[0] != '\0')
-@@ -4550,12 +4843,14 @@ output_operand_error_record (const opera
- enum aarch64_opnd opd_code = (idx >= 0 ? opcode->operands[idx]
- : AARCH64_OPND_NIL);
-
-+ typedef void (*handler_t)(const char *format, ...);
-+ handler_t handler = detail->non_fatal ? as_warn : as_bad;
-+
- switch (detail->kind)
- {
- case AARCH64_OPDE_NIL:
- gas_assert (0);
- break;
--
- case AARCH64_OPDE_SYNTAX_ERROR:
- case AARCH64_OPDE_RECOVERABLE:
- case AARCH64_OPDE_FATAL_SYNTAX_ERROR:
-@@ -4565,21 +4860,21 @@ output_operand_error_record (const opera
- if (detail->error != NULL)
- {
- if (idx < 0)
-- as_bad (_("%s -- `%s'"), detail->error, str);
-+ handler (_("%s -- `%s'"), detail->error, str);
- else
-- as_bad (_("%s at operand %d -- `%s'"),
-- detail->error, idx + 1, str);
-+ handler (_("%s at operand %d -- `%s'"),
-+ detail->error, idx + 1, str);
- }
- else
- {
- gas_assert (idx >= 0);
-- as_bad (_("operand %d must be %s -- `%s'"), idx + 1,
-- aarch64_get_operand_desc (opd_code), str);
-+ handler (_("operand %d must be %s -- `%s'"), idx + 1,
-+ aarch64_get_operand_desc (opd_code), str);
- }
- break;
-
- case AARCH64_OPDE_INVALID_VARIANT:
-- as_bad (_("operand mismatch -- `%s'"), str);
-+ handler (_("operand mismatch -- `%s'"), str);
- if (verbose_error_p)
- {
- /* We will try to correct the erroneous instruction and also provide
-@@ -4627,7 +4922,7 @@ output_operand_error_record (const opera
- && programmer_friendly_fixup (&inst);
- gas_assert (result);
- result = aarch64_opcode_encode (opcode, inst_base, &inst_base->value,
-- NULL, NULL);
-+ NULL, NULL, insn_sequence);
- gas_assert (!result);
-
- /* Find the most matched qualifier sequence. */
-@@ -4676,36 +4971,36 @@ output_operand_error_record (const opera
- break;
-
- case AARCH64_OPDE_UNTIED_OPERAND:
-- as_bad (_("operand %d must be the same register as operand 1 -- `%s'"),
-- detail->index + 1, str);
-+ handler (_("operand %d must be the same register as operand 1 -- `%s'"),
-+ detail->index + 1, str);
- break;
-
- case AARCH64_OPDE_OUT_OF_RANGE:
- if (detail->data[0] != detail->data[1])
-- as_bad (_("%s out of range %d to %d at operand %d -- `%s'"),
-- detail->error ? detail->error : _("immediate value"),
-- detail->data[0], detail->data[1], idx + 1, str);
-+ handler (_("%s out of range %d to %d at operand %d -- `%s'"),
-+ detail->error ? detail->error : _("immediate value"),
-+ detail->data[0], detail->data[1], idx + 1, str);
- else
-- as_bad (_("%s must be %d at operand %d -- `%s'"),
-- detail->error ? detail->error : _("immediate value"),
-- detail->data[0], idx + 1, str);
-+ handler (_("%s must be %d at operand %d -- `%s'"),
-+ detail->error ? detail->error : _("immediate value"),
-+ detail->data[0], idx + 1, str);
- break;
-
- case AARCH64_OPDE_REG_LIST:
- if (detail->data[0] == 1)
-- as_bad (_("invalid number of registers in the list; "
-- "only 1 register is expected at operand %d -- `%s'"),
-- idx + 1, str);
-+ handler (_("invalid number of registers in the list; "
-+ "only 1 register is expected at operand %d -- `%s'"),
-+ idx + 1, str);
- else
-- as_bad (_("invalid number of registers in the list; "
-- "%d registers are expected at operand %d -- `%s'"),
-- detail->data[0], idx + 1, str);
-+ handler (_("invalid number of registers in the list; "
-+ "%d registers are expected at operand %d -- `%s'"),
-+ detail->data[0], idx + 1, str);
- break;
-
- case AARCH64_OPDE_UNALIGNED:
-- as_bad (_("immediate value must be a multiple of "
-- "%d at operand %d -- `%s'"),
-- detail->data[0], idx + 1, str);
-+ handler (_("immediate value must be a multiple of "
-+ "%d at operand %d -- `%s'"),
-+ detail->data[0], idx + 1, str);
- break;
-
- default:
-@@ -4719,10 +5014,15 @@ output_operand_error_record (const opera
- When this function is called, the operand error information had
- been collected for an assembly line and there will be multiple
- errors in the case of multiple instruction templates; output the
-- error message that most closely describes the problem. */
-+ error message that most closely describes the problem.
-+
-+ The errors to be printed can be filtered on printing all errors
-+ or only non-fatal errors. This distinction has to be made because
-+ the error buffer may already be filled with fatal errors we don't want to
-+ print due to the different instruction templates. */
-
- static void
--output_operand_error_report (char *str)
-+output_operand_error_report (char *str, bfd_boolean non_fatal_only)
- {
- int largest_error_pos;
- const char *msg = NULL;
-@@ -4740,9 +5040,14 @@ output_operand_error_report (char *str)
- /* Only one error. */
- if (head == operand_error_report.tail)
- {
-- DEBUG_TRACE ("single opcode entry with error kind: %s",
-- operand_mismatch_kind_names[head->detail.kind]);
-- output_operand_error_record (head, str);
-+ /* If the only error is a non-fatal one and we don't want to print it,
-+ just exit. */
-+ if (!non_fatal_only || head->detail.non_fatal)
-+ {
-+ DEBUG_TRACE ("single opcode entry with error kind: %s",
-+ operand_mismatch_kind_names[head->detail.kind]);
-+ output_operand_error_record (head, str);
-+ }
- return;
- }
-
-@@ -4753,16 +5058,21 @@ output_operand_error_report (char *str)
- {
- gas_assert (curr->detail.kind != AARCH64_OPDE_NIL);
- DEBUG_TRACE ("\t%s", operand_mismatch_kind_names[curr->detail.kind]);
-- if (operand_error_higher_severity_p (curr->detail.kind, kind))
-+ if (operand_error_higher_severity_p (curr->detail.kind, kind)
-+ && (!non_fatal_only || (non_fatal_only && curr->detail.non_fatal)))
- kind = curr->detail.kind;
- }
-- gas_assert (kind != AARCH64_OPDE_NIL);
-+
-+ gas_assert (kind != AARCH64_OPDE_NIL || non_fatal_only);
-
- /* Pick up one of errors of KIND to report. */
- largest_error_pos = -2; /* Index can be -1 which means unknown index. */
- for (curr = head; curr != NULL; curr = curr->next)
- {
-- if (curr->detail.kind != kind)
-+ /* If we don't want to print non-fatal errors then don't consider them
-+ at all. */
-+ if (curr->detail.kind != kind
-+ || (non_fatal_only && !curr->detail.non_fatal))
- continue;
- /* If there are multiple errors, pick up the one with the highest
- mismatching operand index. In the case of multiple errors with
-@@ -4778,6 +5088,17 @@ output_operand_error_report (char *str)
- }
- }
-
-+ /* The way errors are collected in the back-end is a bit non-intuitive. But
-+ essentially, because each operand template is tried recursively you may
-+ always have errors collected from the previous tried OPND. These are
-+ usually skipped if there is one successful match. However now with the
-+ non-fatal errors we have to ignore those previously collected hard errors
-+ when we're only interested in printing the non-fatal ones. This condition
-+ prevents us from printing errors that are not appropriate, since we did
-+ match a condition, but it also has warnings that it wants to print. */
-+ if (non_fatal_only && !record)
-+ return;
-+
- gas_assert (largest_error_pos != -2 && record != NULL);
- DEBUG_TRACE ("Pick up error kind %s to report",
- operand_mismatch_kind_names[record->detail.kind]);
-@@ -4802,7 +5123,8 @@ get_aarch64_insn (char *buf)
- {
- unsigned char *where = (unsigned char *) buf;
- uint32_t result;
-- result = (where[0] | (where[1] << 8) | (where[2] << 16) | (where[3] << 24));
-+ result = ((where[0] | (where[1] << 8) | (where[2] << 16)
-+ | ((uint32_t) where[3] << 24)));
- return result;
- }
-
-@@ -4957,6 +5279,10 @@ vectype_to_qualifier (const struct vecto
- if (vectype->type == NT_b && vectype->width == 4)
- return AARCH64_OPND_QLF_S_4B;
-
-+ /* Special case S_2H. */
-+ if (vectype->type == NT_h && vectype->width == 2)
-+ return AARCH64_OPND_QLF_S_2H;
-+
- /* Vector element register. */
- return AARCH64_OPND_QLF_S_B + vectype->type;
- }
-@@ -4989,7 +5315,7 @@ vectype_to_qualifier (const struct vecto
- return offset;
- }
-
--vectype_conversion_fail:
-+ vectype_conversion_fail:
- first_error (_("bad vector arrangement type"));
- return AARCH64_OPND_QLF_NIL;
- }
-@@ -5014,6 +5340,8 @@ process_omitted_operand (enum aarch64_op
- case AARCH64_OPND_Rm:
- case AARCH64_OPND_Rt:
- case AARCH64_OPND_Rt2:
-+ case AARCH64_OPND_Rt_LS64:
-+ case AARCH64_OPND_Rt_SP:
- case AARCH64_OPND_Rs:
- case AARCH64_OPND_Ra:
- case AARCH64_OPND_Rt_SYS:
-@@ -5041,6 +5369,7 @@ process_omitted_operand (enum aarch64_op
- case AARCH64_OPND_Ed:
- case AARCH64_OPND_En:
- case AARCH64_OPND_Em:
-+ case AARCH64_OPND_Em16:
- case AARCH64_OPND_SM3_IMM2:
- operand->reglane.regno = default_value;
- break;
-@@ -5079,6 +5408,11 @@ process_omitted_operand (enum aarch64_op
-
- case AARCH64_OPND_BARRIER_ISB:
- operand->barrier = aarch64_barrier_options + default_value;
-+ break;
-+
-+ case AARCH64_OPND_BTI_TARGET:
-+ operand->hint_option = aarch64_hint_options + default_value;
-+ break;
-
- default:
- break;
-@@ -5102,6 +5436,10 @@ process_movw_reloc_info (void)
- case BFD_RELOC_AARCH64_MOVW_G0_S:
- case BFD_RELOC_AARCH64_MOVW_G1_S:
- case BFD_RELOC_AARCH64_MOVW_G2_S:
-+ case BFD_RELOC_AARCH64_MOVW_PREL_G0:
-+ case BFD_RELOC_AARCH64_MOVW_PREL_G1:
-+ case BFD_RELOC_AARCH64_MOVW_PREL_G2:
-+ case BFD_RELOC_AARCH64_MOVW_PREL_G3:
- case BFD_RELOC_AARCH64_TLSGD_MOVW_G1:
- case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0:
- case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1:
-@@ -5119,6 +5457,8 @@ process_movw_reloc_info (void)
- case BFD_RELOC_AARCH64_MOVW_G0_NC:
- case BFD_RELOC_AARCH64_MOVW_G0_S:
- case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC:
-+ case BFD_RELOC_AARCH64_MOVW_PREL_G0:
-+ case BFD_RELOC_AARCH64_MOVW_PREL_G0_NC:
- case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC:
- case BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC:
- case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC:
-@@ -5132,6 +5472,8 @@ process_movw_reloc_info (void)
- case BFD_RELOC_AARCH64_MOVW_G1_NC:
- case BFD_RELOC_AARCH64_MOVW_G1_S:
- case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1:
-+ case BFD_RELOC_AARCH64_MOVW_PREL_G1:
-+ case BFD_RELOC_AARCH64_MOVW_PREL_G1_NC:
- case BFD_RELOC_AARCH64_TLSDESC_OFF_G1:
- case BFD_RELOC_AARCH64_TLSGD_MOVW_G1:
- case BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1:
-@@ -5144,6 +5486,8 @@ process_movw_reloc_info (void)
- case BFD_RELOC_AARCH64_MOVW_G2:
- case BFD_RELOC_AARCH64_MOVW_G2_NC:
- case BFD_RELOC_AARCH64_MOVW_G2_S:
-+ case BFD_RELOC_AARCH64_MOVW_PREL_G2:
-+ case BFD_RELOC_AARCH64_MOVW_PREL_G2_NC:
- case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2:
- case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2:
- if (is32)
-@@ -5156,6 +5500,7 @@ process_movw_reloc_info (void)
- shift = 32;
- break;
- case BFD_RELOC_AARCH64_MOVW_G3:
-+ case BFD_RELOC_AARCH64_MOVW_PREL_G3:
- if (is32)
- {
- set_fatal_syntax_error
-@@ -5202,7 +5547,7 @@ ldst_lo12_determine_real_reloc_type (voi
- enum aarch64_opnd_qualifier opd0_qlf = inst.base.operands[0].qualifier;
- enum aarch64_opnd_qualifier opd1_qlf = inst.base.operands[1].qualifier;
-
-- const bfd_reloc_code_real_type reloc_ldst_lo12[3][5] = {
-+ const bfd_reloc_code_real_type reloc_ldst_lo12[5][5] = {
- {
- BFD_RELOC_AARCH64_LDST8_LO12,
- BFD_RELOC_AARCH64_LDST16_LO12,
-@@ -5223,13 +5568,31 @@ ldst_lo12_determine_real_reloc_type (voi
- BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC,
- BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC,
- BFD_RELOC_AARCH64_NONE
-+ },
-+ {
-+ BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12,
-+ BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12,
-+ BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12,
-+ BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12,
-+ BFD_RELOC_AARCH64_NONE
-+ },
-+ {
-+ BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC,
-+ BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC,
-+ BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC,
-+ BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC,
-+ BFD_RELOC_AARCH64_NONE
- }
- };
-
- gas_assert (inst.reloc.type == BFD_RELOC_AARCH64_LDST_LO12
- || inst.reloc.type == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
- || (inst.reloc.type
-- == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC));
-+ == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC)
-+ || (inst.reloc.type
-+ == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12)
-+ || (inst.reloc.type
-+ == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC));
- gas_assert (inst.base.opcode->operands[1] == AARCH64_OPND_ADDR_UIMM12);
-
- if (opd1_qlf == AARCH64_OPND_QLF_NIL)
-@@ -5240,7 +5603,9 @@ ldst_lo12_determine_real_reloc_type (voi
-
- logsz = get_logsz (aarch64_get_qualifier_esize (opd1_qlf));
- if (inst.reloc.type == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
-- || inst.reloc.type == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC)
-+ || inst.reloc.type == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
-+ || inst.reloc.type == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
-+ || inst.reloc.type == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC)
- gas_assert (logsz <= 3);
- else
- gas_assert (logsz <= 4);
-@@ -5345,14 +5710,31 @@ parse_operands (char *str, const aarch64
- case AARCH64_OPND_Rt2:
- case AARCH64_OPND_Rs:
- case AARCH64_OPND_Ra:
-+ case AARCH64_OPND_Rt_LS64:
- case AARCH64_OPND_Rt_SYS:
- case AARCH64_OPND_PAIRREG:
- case AARCH64_OPND_SVE_Rm:
- po_int_reg_or_fail (REG_TYPE_R_Z);
-+
-+ /* In LS64 load/store instructions Rt register number must be even
-+ and <=22. */
-+ if (operands[i] == AARCH64_OPND_Rt_LS64)
-+ {
-+ /* We've already checked if this is valid register.
-+ This will check if register number (Rt) is not undefined for LS64
-+ instructions:
-+ if Rt<4:3> == '11' || Rt<0> == '1' then UNDEFINED. */
-+ if ((info->reg.regno & 0x18) == 0x18 || (info->reg.regno & 0x01) == 0x01)
-+ {
-+ set_syntax_error (_("invalid Rt register number in 64-byte load/store"));
-+ goto failure;
-+ }
-+ }
- break;
-
- case AARCH64_OPND_Rd_SP:
- case AARCH64_OPND_Rn_SP:
-+ case AARCH64_OPND_Rt_SP:
- case AARCH64_OPND_SVE_Rn_SP:
- case AARCH64_OPND_Rm_SP:
- po_int_reg_or_fail (REG_TYPE_R_SP);
-@@ -5477,6 +5859,8 @@ parse_operands (char *str, const aarch64
-
- case AARCH64_OPND_SVE_Zm3_INDEX:
- case AARCH64_OPND_SVE_Zm3_22_INDEX:
-+ case AARCH64_OPND_SVE_Zm3_11_INDEX:
-+ case AARCH64_OPND_SVE_Zm4_11_INDEX:
- case AARCH64_OPND_SVE_Zm4_INDEX:
- case AARCH64_OPND_SVE_Zn_INDEX:
- reg_type = REG_TYPE_ZN;
-@@ -5485,6 +5869,7 @@ parse_operands (char *str, const aarch64
- case AARCH64_OPND_Ed:
- case AARCH64_OPND_En:
- case AARCH64_OPND_Em:
-+ case AARCH64_OPND_Em16:
- case AARCH64_OPND_SM3_IMM2:
- reg_type = REG_TYPE_VN;
- vector_reg_index:
-@@ -5533,11 +5918,20 @@ parse_operands (char *str, const aarch64
- val = parse_vector_reg_list (&str, reg_type, &vectype);
- if (val == PARSE_FAIL)
- goto failure;
-+
- if (! reg_list_valid_p (val, /* accept_alternate */ 0))
- {
- set_fatal_syntax_error (_("invalid register list"));
- goto failure;
- }
-+
-+ if (vectype.width != 0 && *str != ',')
-+ {
-+ set_fatal_syntax_error
-+ (_("expected element type rather than vector type"));
-+ goto failure;
-+ }
-+
- info->reglist.first_regno = (val >> 2) & 0x1f;
- info->reglist.num_regs = (val & 0x3) + 1;
- }
-@@ -5591,7 +5985,10 @@ parse_operands (char *str, const aarch64
- case AARCH64_OPND_CCMP_IMM:
- case AARCH64_OPND_SIMM5:
- case AARCH64_OPND_FBITS:
-+ case AARCH64_OPND_TME_UIMM16:
- case AARCH64_OPND_UIMM4:
-+ case AARCH64_OPND_UIMM4_ADDG:
-+ case AARCH64_OPND_UIMM10:
- case AARCH64_OPND_UIMM3_OP1:
- case AARCH64_OPND_UIMM3_OP2:
- case AARCH64_OPND_IMM_VLSL:
-@@ -5603,8 +6000,10 @@ parse_operands (char *str, const aarch64
- case AARCH64_OPND_SVE_LIMM_MOV:
- case AARCH64_OPND_SVE_SHLIMM_PRED:
- case AARCH64_OPND_SVE_SHLIMM_UNPRED:
-+ case AARCH64_OPND_SVE_SHLIMM_UNPRED_22:
- case AARCH64_OPND_SVE_SHRIMM_PRED:
- case AARCH64_OPND_SVE_SHRIMM_UNPRED:
-+ case AARCH64_OPND_SVE_SHRIMM_UNPRED_22:
- case AARCH64_OPND_SVE_SIMM5:
- case AARCH64_OPND_SVE_SIMM5B:
- case AARCH64_OPND_SVE_SIMM6:
-@@ -5618,6 +6017,7 @@ parse_operands (char *str, const aarch64
- case AARCH64_OPND_IMM_ROT3:
- case AARCH64_OPND_SVE_IMM_ROT1:
- case AARCH64_OPND_SVE_IMM_ROT2:
-+ case AARCH64_OPND_SVE_IMM_ROT3:
- po_imm_nc_or_fail ();
- info->imm.value = val;
- break;
-@@ -5865,6 +6265,7 @@ parse_operands (char *str, const aarch64
- break;
-
- case AARCH64_OPND_EXCEPTION:
-+ case AARCH64_OPND_UNDEFINED:
- po_misc_or_fail (parse_immediate_expression (&str, &inst.reloc.exp,
- imm_reg_type));
- assign_imm_if_const_or_fixup_later (&inst.reloc, info,
-@@ -6062,6 +6463,8 @@ parse_operands (char *str, const aarch64
-
- case AARCH64_OPND_ADDR_SIMM9:
- case AARCH64_OPND_ADDR_SIMM9_2:
-+ case AARCH64_OPND_ADDR_SIMM11:
-+ case AARCH64_OPND_ADDR_SIMM13:
- po_misc_or_fail (parse_address (&str, info));
- if (info->addr.pcrel || info->addr.offset.is_reg
- || (!info->addr.preind && !info->addr.postind)
-@@ -6116,7 +6519,11 @@ parse_operands (char *str, const aarch64
- || (inst.reloc.type
- == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12)
- || (inst.reloc.type
-- == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC))
-+ == BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC)
-+ || (inst.reloc.type
-+ == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12)
-+ || (inst.reloc.type
-+ == BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC))
- inst.reloc.type = ldst_lo12_determine_real_reloc_type ();
- /* Leave qualifier to be determined by libopcodes. */
- break;
-@@ -6144,6 +6551,7 @@ parse_operands (char *str, const aarch64
- break;
-
- case AARCH64_OPND_SVE_ADDR_RI_S4x16:
-+ case AARCH64_OPND_SVE_ADDR_RI_S4x32:
- case AARCH64_OPND_SVE_ADDR_RI_S4xVL:
- case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL:
- case AARCH64_OPND_SVE_ADDR_RI_S4x3xVL:
-@@ -6182,6 +6590,25 @@ parse_operands (char *str, const aarch64
- info->addr.offset.imm = inst.reloc.exp.X_add_number;
- break;
-
-+ case AARCH64_OPND_SVE_ADDR_R:
-+ /* [<Xn|SP>{, <R><m>}]
-+ but recognizing SVE registers. */
-+ po_misc_or_fail (parse_sve_address (&str, info, &base_qualifier,
-+ &offset_qualifier));
-+ if (offset_qualifier == AARCH64_OPND_QLF_NIL)
-+ {
-+ offset_qualifier = AARCH64_OPND_QLF_X;
-+ info->addr.offset.is_reg = 1;
-+ info->addr.offset.regno = 31;
-+ }
-+ else if (base_qualifier != AARCH64_OPND_QLF_X
-+ || offset_qualifier != AARCH64_OPND_QLF_X)
-+ {
-+ set_syntax_error (_("invalid addressing mode"));
-+ goto failure;
-+ }
-+ goto regoff_addr;
-+
- case AARCH64_OPND_SVE_ADDR_RR:
- case AARCH64_OPND_SVE_ADDR_RR_LSL1:
- case AARCH64_OPND_SVE_ADDR_RR_LSL2:
-@@ -6228,6 +6655,33 @@ parse_operands (char *str, const aarch64
- info->qualifier = offset_qualifier;
- goto regoff_addr;
-
-+ case AARCH64_OPND_SVE_ADDR_ZX:
-+ /* [Zn.<T>{, <Xm>}]. */
-+ po_misc_or_fail (parse_sve_address (&str, info, &base_qualifier,
-+ &offset_qualifier));
-+ /* Things to check:
-+ base_qualifier either S_S or S_D
-+ offset_qualifier must be X
-+ */
-+ if ((base_qualifier != AARCH64_OPND_QLF_S_S
-+ && base_qualifier != AARCH64_OPND_QLF_S_D)
-+ || offset_qualifier != AARCH64_OPND_QLF_X)
-+ {
-+ set_syntax_error (_("invalid addressing mode"));
-+ goto failure;
-+ }
-+ info->qualifier = base_qualifier;
-+ if (!info->addr.offset.is_reg || info->addr.pcrel
-+ || !info->addr.preind || info->addr.writeback
-+ || info->shifter.operator_present != 0)
-+ {
-+ set_syntax_error (_("invalid addressing mode"));
-+ goto failure;
-+ }
-+ info->shifter.kind = AARCH64_MOD_LSL;
-+ break;
-+
-+
- case AARCH64_OPND_SVE_ADDR_ZI_U5:
- case AARCH64_OPND_SVE_ADDR_ZI_U5x2:
- case AARCH64_OPND_SVE_ADDR_ZI_U5x4:
-@@ -6269,17 +6723,21 @@ parse_operands (char *str, const aarch64
- goto regoff_addr;
-
- case AARCH64_OPND_SYSREG:
-- if ((val = parse_sys_reg (&str, aarch64_sys_regs_hsh, 1, 0))
-- == PARSE_FAIL)
-- {
-- set_syntax_error (_("unknown or missing system register name"));
-- goto failure;
-- }
-- inst.base.operands[i].sysreg = val;
-- break;
-+ {
-+ uint32_t sysreg_flags;
-+ if ((val = parse_sys_reg (&str, aarch64_sys_regs_hsh, 1, 0,
-+ &sysreg_flags)) == PARSE_FAIL)
-+ {
-+ set_syntax_error (_("unknown or missing system register name"));
-+ goto failure;
-+ }
-+ inst.base.operands[i].sysreg.value = val;
-+ inst.base.operands[i].sysreg.flags = sysreg_flags;
-+ break;
-+ }
-
- case AARCH64_OPND_PSTATEFIELD:
-- if ((val = parse_sys_reg (&str, aarch64_pstatefield_hsh, 0, 1))
-+ if ((val = parse_sys_reg (&str, aarch64_pstatefield_hsh, 0, 1, NULL))
- == PARSE_FAIL)
- {
- set_syntax_error (_("unknown or missing PSTATE field name"));
-@@ -6292,18 +6750,26 @@ parse_operands (char *str, const aarch64
- inst.base.operands[i].sysins_op =
- parse_sys_ins_reg (&str, aarch64_sys_regs_ic_hsh);
- goto sys_reg_ins;
-+
- case AARCH64_OPND_SYSREG_DC:
- inst.base.operands[i].sysins_op =
- parse_sys_ins_reg (&str, aarch64_sys_regs_dc_hsh);
- goto sys_reg_ins;
-+
- case AARCH64_OPND_SYSREG_AT:
- inst.base.operands[i].sysins_op =
- parse_sys_ins_reg (&str, aarch64_sys_regs_at_hsh);
- goto sys_reg_ins;
-+
-+ case AARCH64_OPND_SYSREG_SR:
-+ inst.base.operands[i].sysins_op =
-+ parse_sys_ins_reg (&str, aarch64_sys_regs_sr_hsh);
-+ goto sys_reg_ins;
-+
- case AARCH64_OPND_SYSREG_TLBI:
- inst.base.operands[i].sysins_op =
- parse_sys_ins_reg (&str, aarch64_sys_regs_tlbi_hsh);
--sys_reg_ins:
-+ sys_reg_ins:
- if (inst.base.operands[i].sysins_op == NULL)
- {
- set_fatal_syntax_error ( _("unknown or missing operation name"));
-@@ -6324,12 +6790,53 @@ sys_reg_ins:
- backtrack_pos = 0;
- goto failure;
- }
-+ if (val != PARSE_FAIL
-+ && operands[i] == AARCH64_OPND_BARRIER)
-+ {
-+ /* Regular barriers accept options CRm (C0-C15).
-+ DSB nXS barrier variant accepts values > 15. */
-+ if (val < 0 || val > 15)
-+ {
-+ set_syntax_error (_("the specified option is not accepted in DSB"));
-+ goto failure;
-+ }
-+ }
- /* This is an extension to accept a 0..15 immediate. */
- if (val == PARSE_FAIL)
- po_imm_or_fail (0, 15);
- info->barrier = aarch64_barrier_options + val;
- break;
-
-+ case AARCH64_OPND_BARRIER_DSB_NXS:
-+ val = parse_barrier (&str);
-+ if (val != PARSE_FAIL)
-+ {
-+ /* DSB nXS barrier variant accept only <option>nXS qualifiers. */
-+ if (!(val == 16 || val == 20 || val == 24 || val == 28))
-+ {
-+ set_syntax_error (_("the specified option is not accepted in DSB"));
-+ /* Turn off backtrack as this optional operand is present. */
-+ backtrack_pos = 0;
-+ goto failure;
-+ }
-+ }
-+ else
-+ {
-+ /* DSB nXS barrier variant accept 5-bit unsigned immediate, with
-+ possible values 16, 20, 24 or 28 , encoded as val<3:2>. */
-+ if (! parse_constant_immediate (&str, &val, imm_reg_type))
-+ goto failure;
-+ if (!(val == 16 || val == 20 || val == 24 || val == 28))
-+ {
-+ set_syntax_error (_("immediate value must be 16, 20, 24, 28"));
-+ goto failure;
-+ }
-+ }
-+ /* Option index is encoded as 2-bit value in val<3:2>. */
-+ val = (val >> 2) - 4;
-+ info->barrier = aarch64_barrier_dsb_nxs_options + val;
-+ break;
-+
- case AARCH64_OPND_PRFOP:
- val = parse_pldop (&str);
- /* This is an extension to accept a 0..31 immediate. */
-@@ -6344,6 +6851,12 @@ sys_reg_ins:
- goto failure;
- break;
-
-+ case AARCH64_OPND_BTI_TARGET:
-+ val = parse_bti_operand (&str, &(info->hint_option));
-+ if (val == PARSE_FAIL)
-+ goto failure;
-+ break;
-+
- default:
- as_fatal (_("unhandled operand code %d"), operands[i]);
- }
-@@ -6352,7 +6865,7 @@ sys_reg_ins:
- inst.base.operands[i].present = 1;
- continue;
-
--failure:
-+ failure:
- /* The parse routine should already have set the error, but in case
- not, set a default one here. */
- if (! error_p ())
-@@ -6418,7 +6931,7 @@ failure:
- (_("unexpected characters following instruction"));
- }
-
--parse_operands_return:
-+ parse_operands_return:
-
- if (error_p ())
- {
-@@ -6568,9 +7081,12 @@ warn_unpredictable_ldst (aarch64_instruc
- == AARCH64_OPND_CLASS_INT_REG)
- && opnds[0].reg.regno == opnds[1].addr.base_regno
- && opnds[1].addr.base_regno != REG_SP
-+ /* Exempt STG/STZG/ST2G/STZ2G. */
-+ && !(opnds[1].type == AARCH64_OPND_ADDR_SIMM13)
- && opnds[1].addr.writeback)
- as_warn (_("unpredictable transfer with writeback -- `%s'"), str);
- break;
-+
- case ldstpair_off:
- case ldstnapair_offs:
- case ldstpair_indexed:
-@@ -6580,6 +7096,8 @@ warn_unpredictable_ldst (aarch64_instruc
- && (opnds[0].reg.regno == opnds[2].addr.base_regno
- || opnds[1].reg.regno == opnds[2].addr.base_regno)
- && opnds[2].addr.base_regno != REG_SP
-+ /* Exempt STGP. */
-+ && !(opnds[2].type == AARCH64_OPND_ADDR_SIMM11)
- && opnds[2].addr.writeback)
- as_warn (_("unpredictable transfer with writeback -- `%s'"), str);
- /* Load operations must load different registers. */
-@@ -6587,11 +7105,38 @@ warn_unpredictable_ldst (aarch64_instruc
- && opnds[0].reg.regno == opnds[1].reg.regno)
- as_warn (_("unpredictable load of register pair -- `%s'"), str);
- break;
-+
-+ case ldstexcl:
-+ /* It is unpredictable if the destination and status registers are the
-+ same. */
-+ if ((aarch64_get_operand_class (opnds[0].type)
-+ == AARCH64_OPND_CLASS_INT_REG)
-+ && (aarch64_get_operand_class (opnds[1].type)
-+ == AARCH64_OPND_CLASS_INT_REG)
-+ && (opnds[0].reg.regno == opnds[1].reg.regno
-+ || opnds[0].reg.regno == opnds[2].reg.regno))
-+ as_warn (_("unpredictable: identical transfer and status registers"
-+ " --`%s'"),
-+ str);
-+
-+ break;
-+
- default:
- break;
- }
- }
-
-+static void
-+force_automatic_sequence_close (void)
-+{
-+ if (now_instr_sequence.instr)
-+ {
-+ as_warn (_("previous `%s' sequence has not been closed"),
-+ now_instr_sequence.instr->opcode->name);
-+ init_insn_sequence (NULL, &now_instr_sequence);
-+ }
-+}
-+
- /* A wrapper function to interface with libopcodes on encoding and
- record the error message if there is any.
-
-@@ -6602,15 +7147,15 @@ do_encode (const aarch64_opcode *opcode,
- aarch64_insn *code)
- {
- aarch64_operand_error error_info;
-+ memset (&error_info, '\0', sizeof (error_info));
- error_info.kind = AARCH64_OPDE_NIL;
-- if (aarch64_opcode_encode (opcode, instr, code, NULL, &error_info))
-+ if (aarch64_opcode_encode (opcode, instr, code, NULL, &error_info, insn_sequence)
-+ && !error_info.non_fatal)
- return TRUE;
-- else
-- {
-- gas_assert (error_info.kind != AARCH64_OPDE_NIL);
-- record_operand_error_info (opcode, &error_info);
-- return FALSE;
-- }
-+
-+ gas_assert (error_info.kind != AARCH64_OPDE_NIL);
-+ record_operand_error_info (opcode, &error_info);
-+ return error_info.non_fatal;
- }
-
- #ifdef DEBUG_AARCH64
-@@ -6650,6 +7195,9 @@ md_assemble (char *str)
- S_SET_SEGMENT (last_label_seen, now_seg);
- }
-
-+ /* Update the current insn_sequence from the segment. */
-+ insn_sequence = &seg_info (now_seg)->tc_segment_info_data.insn_sequence;
-+
- inst.reloc.type = BFD_RELOC_UNUSED;
-
- DEBUG_TRACE ("\n\n");
-@@ -6747,6 +7295,9 @@ md_assemble (char *str)
- memcpy (copy, &inst.base, sizeof (struct aarch64_inst));
- output_inst (copy);
- }
-+
-+ /* Issue non-fatal messages if any. */
-+ output_operand_error_report (str, TRUE);
- return;
- }
-
-@@ -6760,7 +7311,7 @@ md_assemble (char *str)
- while (template != NULL);
-
- /* Issue the error messages if any. */
-- output_operand_error_report (str);
-+ output_operand_error_report (str, FALSE);
- }
-
- /* Various frobbings of labels and their addresses. */
-@@ -6779,6 +7330,13 @@ aarch64_frob_label (symbolS * sym)
- dwarf2_emit_label (sym);
- }
-
-+void
-+aarch64_frob_section (asection *sec ATTRIBUTE_UNUSED)
-+{
-+ /* Check to see if we have a block to close. */
-+ force_automatic_sequence_close ();
-+}
-+
- int
- aarch64_data_in_code (void)
- {
-@@ -7059,7 +7617,6 @@ aarch64_init_frag (fragS * fragP, int ma
- void
- tc_aarch64_frame_initial_instructions (void)
- {
-- cfi_add_CFA_def_cfa (REG_SP, 0);
- }
- #endif /* OBJ_ELF */
-
-@@ -7239,7 +7796,8 @@ try_to_encode_as_unscaled_ldst (aarch64_
-
- DEBUG_TRACE ("Found LDURB entry to encode programmer-friendly LDRB");
-
-- if (!aarch64_opcode_encode (instr->opcode, instr, &instr->value, NULL, NULL))
-+ if (!aarch64_opcode_encode (instr->opcode, instr, &instr->value, NULL, NULL,
-+ insn_sequence))
- return FALSE;
-
- return TRUE;
-@@ -7273,7 +7831,7 @@ fix_mov_imm_insn (fixS *fixP, char *buf,
- opcode = aarch64_get_opcode (OP_MOV_IMM_WIDE);
- aarch64_replace_opcode (instr, opcode);
- if (aarch64_opcode_encode (instr->opcode, instr,
-- &instr->value, NULL, NULL))
-+ &instr->value, NULL, NULL, insn_sequence))
- {
- put_aarch64_insn (buf, instr->value);
- return;
-@@ -7282,7 +7840,7 @@ fix_mov_imm_insn (fixS *fixP, char *buf,
- opcode = aarch64_get_opcode (OP_MOV_IMM_WIDEN);
- aarch64_replace_opcode (instr, opcode);
- if (aarch64_opcode_encode (instr->opcode, instr,
-- &instr->value, NULL, NULL))
-+ &instr->value, NULL, NULL, insn_sequence))
- {
- put_aarch64_insn (buf, instr->value);
- return;
-@@ -7295,7 +7853,7 @@ fix_mov_imm_insn (fixS *fixP, char *buf,
- opcode = aarch64_get_opcode (OP_MOV_IMM_LOG);
- aarch64_replace_opcode (instr, opcode);
- if (aarch64_opcode_encode (instr->opcode, instr,
-- &instr->value, NULL, NULL))
-+ &instr->value, NULL, NULL, insn_sequence))
- {
- put_aarch64_insn (buf, instr->value);
- return;
-@@ -7344,11 +7902,12 @@ fix_insn (fixS *fixP, uint32_t flags, of
- switch (opnd)
- {
- case AARCH64_OPND_EXCEPTION:
-+ case AARCH64_OPND_UNDEFINED:
- if (unsigned_overflow (value, 16))
- as_bad_where (fixP->fx_file, fixP->fx_line,
- _("immediate out of range"));
- insn = get_aarch64_insn (buf);
-- insn |= encode_svc_imm (value);
-+ insn |= (opnd == AARCH64_OPND_EXCEPTION) ? encode_svc_imm (value) : value;
- put_aarch64_insn (buf, insn);
- break;
-
-@@ -7406,7 +7965,7 @@ fix_insn (fixS *fixP, uint32_t flags, of
- idx = aarch64_operand_index (new_inst->opcode->operands, opnd);
- new_inst->operands[idx].imm.value = value;
- if (aarch64_opcode_encode (new_inst->opcode, new_inst,
-- &new_inst->value, NULL, NULL))
-+ &new_inst->value, NULL, NULL, insn_sequence))
- put_aarch64_insn (buf, new_inst->value);
- else
- as_bad_where (fixP->fx_file, fixP->fx_line,
-@@ -7440,6 +7999,8 @@ fix_insn (fixS *fixP, uint32_t flags, of
- case AARCH64_OPND_ADDR_SIMM9_2:
- case AARCH64_OPND_ADDR_SIMM10:
- case AARCH64_OPND_ADDR_UIMM12:
-+ case AARCH64_OPND_ADDR_SIMM11:
-+ case AARCH64_OPND_ADDR_SIMM13:
- /* Immediate offset in an address. */
- insn = get_aarch64_insn (buf);
-
-@@ -7460,7 +8021,7 @@ fix_insn (fixS *fixP, uint32_t flags, of
-
- /* Encode/fix-up. */
- if (aarch64_opcode_encode (new_inst->opcode, new_inst,
-- &new_inst->value, NULL, NULL))
-+ &new_inst->value, NULL, NULL, insn_sequence))
- {
- put_aarch64_insn (buf, new_inst->value);
- break;
-@@ -7631,12 +8192,16 @@ md_apply_fix (fixS * fixP, valueT * valP
- case BFD_RELOC_AARCH64_MOVW_G0_NC:
- case BFD_RELOC_AARCH64_MOVW_G0_S:
- case BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC:
-+ case BFD_RELOC_AARCH64_MOVW_PREL_G0:
-+ case BFD_RELOC_AARCH64_MOVW_PREL_G0_NC:
- scale = 0;
- goto movw_common;
- case BFD_RELOC_AARCH64_MOVW_G1:
- case BFD_RELOC_AARCH64_MOVW_G1_NC:
- case BFD_RELOC_AARCH64_MOVW_G1_S:
- case BFD_RELOC_AARCH64_MOVW_GOTOFF_G1:
-+ case BFD_RELOC_AARCH64_MOVW_PREL_G1:
-+ case BFD_RELOC_AARCH64_MOVW_PREL_G1_NC:
- scale = 16;
- goto movw_common;
- case BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC:
-@@ -7658,9 +8223,12 @@ md_apply_fix (fixS * fixP, valueT * valP
- case BFD_RELOC_AARCH64_MOVW_G2:
- case BFD_RELOC_AARCH64_MOVW_G2_NC:
- case BFD_RELOC_AARCH64_MOVW_G2_S:
-+ case BFD_RELOC_AARCH64_MOVW_PREL_G2:
-+ case BFD_RELOC_AARCH64_MOVW_PREL_G2_NC:
- scale = 32;
- goto movw_common;
- case BFD_RELOC_AARCH64_MOVW_G3:
-+ case BFD_RELOC_AARCH64_MOVW_PREL_G3:
- scale = 48;
- movw_common:
- if (fixP->fx_done || !seg->use_rela_p)
-@@ -7692,6 +8260,9 @@ md_apply_fix (fixS * fixP, valueT * valP
- case BFD_RELOC_AARCH64_MOVW_G0_S:
- case BFD_RELOC_AARCH64_MOVW_G1_S:
- case BFD_RELOC_AARCH64_MOVW_G2_S:
-+ case BFD_RELOC_AARCH64_MOVW_PREL_G0:
-+ case BFD_RELOC_AARCH64_MOVW_PREL_G1:
-+ case BFD_RELOC_AARCH64_MOVW_PREL_G2:
- /* NOTE: We can only come here with movz or movn. */
- if (signed_overflow (value, scale + 16))
- as_bad_where (fixP->fx_file, fixP->fx_line,
-@@ -7780,6 +8351,14 @@ md_apply_fix (fixS * fixP, valueT * valP
- case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1:
- case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC:
- case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2:
-+ case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12:
-+ case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC:
-+ case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12:
-+ case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC:
-+ case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12:
-+ case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC:
-+ case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12:
-+ case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC:
- case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12:
- case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12:
- case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC:
-@@ -7842,12 +8421,11 @@ md_apply_fix (fixS * fixP, valueT * valP
- break;
- }
-
--apply_fix_return:
-+ apply_fix_return:
- /* Free the allocated the struct aarch64_inst.
- N.B. currently there are very limited number of fix-up types actually use
- this field, so the impact on the performance should be minimal . */
-- if (fixP->tc_fix_data.inst != NULL)
-- free (fixP->tc_fix_data.inst);
-+ free (fixP->tc_fix_data.inst);
-
- return;
- }
-@@ -8014,6 +8592,14 @@ aarch64_force_relocation (struct fix *fi
- case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1:
- case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC:
- case BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2:
-+ case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12:
-+ case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC:
-+ case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12:
-+ case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC:
-+ case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12:
-+ case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC:
-+ case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12:
-+ case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC:
- case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12:
- case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12:
- case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC:
-@@ -8053,15 +8639,18 @@ aarch64_after_parse_args (void)
- const char *
- elf64_aarch64_target_format (void)
- {
-- if (strcmp (TARGET_OS, "cloudabi") == 0)
-- {
-- /* FIXME: What to do for ilp32_p ? */
-- return target_big_endian ? "elf64-bigaarch64-cloudabi" : "elf64-littleaarch64-cloudabi";
-- }
-+#ifdef TE_CLOUDABI
-+ /* FIXME: What to do for ilp32_p ? */
-+ if (target_big_endian)
-+ return "elf64-bigaarch64-cloudabi";
-+ else
-+ return "elf64-littleaarch64-cloudabi";
-+#else
- if (target_big_endian)
- return ilp32_p ? "elf32-bigaarch64" : "elf64-bigaarch64";
- else
- return ilp32_p ? "elf32-littleaarch64" : "elf64-littleaarch64";
-+#endif
- }
-
- void
-@@ -8170,13 +8759,20 @@ aarch64_adjust_symtab (void)
- }
-
- static void
--checked_hash_insert (struct hash_control *table, const char *key, void *value)
-+checked_hash_insert (htab_t table, const char *key, void *value)
- {
- const char *hash_err;
-
- hash_err = hash_insert (table, key, value);
- if (hash_err)
-- printf ("Internal Error: Can't hash %s\n", key);
-+ printf ("Internal Error: Can't hash %s (error: %s)\n", key, hash_err);
-+}
-+
-+static void
-+sysreg_hash_insert (htab_t table, const char *key, void *value)
-+{
-+ gas_assert (strlen (key) < AARCH64_MAX_SYSREG_NAME_LEN);
-+ hash_insert (table, key, value);
- }
-
- static void
-@@ -8241,6 +8837,7 @@ md_begin (void)
- || (aarch64_sys_regs_ic_hsh = hash_new ()) == NULL
- || (aarch64_sys_regs_dc_hsh = hash_new ()) == NULL
- || (aarch64_sys_regs_at_hsh = hash_new ()) == NULL
-+ || (aarch64_sys_regs_sr_hsh = hash_new ()) == NULL
- || (aarch64_sys_regs_tlbi_hsh = hash_new ()) == NULL
- || (aarch64_reg_hsh = hash_new ()) == NULL
- || (aarch64_barrier_opt_hsh = hash_new ()) == NULL
-@@ -8252,34 +8849,39 @@ md_begin (void)
- fill_instruction_hash_table ();
-
- for (i = 0; aarch64_sys_regs[i].name != NULL; ++i)
-- checked_hash_insert (aarch64_sys_regs_hsh, aarch64_sys_regs[i].name,
-+ sysreg_hash_insert (aarch64_sys_regs_hsh, aarch64_sys_regs[i].name,
- (void *) (aarch64_sys_regs + i));
-
- for (i = 0; aarch64_pstatefields[i].name != NULL; ++i)
-- checked_hash_insert (aarch64_pstatefield_hsh,
-+ sysreg_hash_insert (aarch64_pstatefield_hsh,
- aarch64_pstatefields[i].name,
- (void *) (aarch64_pstatefields + i));
-
- for (i = 0; aarch64_sys_regs_ic[i].name != NULL; i++)
-- checked_hash_insert (aarch64_sys_regs_ic_hsh,
-+ sysreg_hash_insert (aarch64_sys_regs_ic_hsh,
- aarch64_sys_regs_ic[i].name,
- (void *) (aarch64_sys_regs_ic + i));
-
- for (i = 0; aarch64_sys_regs_dc[i].name != NULL; i++)
-- checked_hash_insert (aarch64_sys_regs_dc_hsh,
-+ sysreg_hash_insert (aarch64_sys_regs_dc_hsh,
- aarch64_sys_regs_dc[i].name,
- (void *) (aarch64_sys_regs_dc + i));
-
- for (i = 0; aarch64_sys_regs_at[i].name != NULL; i++)
-- checked_hash_insert (aarch64_sys_regs_at_hsh,
-+ sysreg_hash_insert (aarch64_sys_regs_at_hsh,
- aarch64_sys_regs_at[i].name,
- (void *) (aarch64_sys_regs_at + i));
-
- for (i = 0; aarch64_sys_regs_tlbi[i].name != NULL; i++)
-- checked_hash_insert (aarch64_sys_regs_tlbi_hsh,
-+ sysreg_hash_insert (aarch64_sys_regs_tlbi_hsh,
- aarch64_sys_regs_tlbi[i].name,
- (void *) (aarch64_sys_regs_tlbi + i));
-
-+ for (i = 0; aarch64_sys_regs_sr[i].name != NULL; i++)
-+ sysreg_hash_insert (aarch64_sys_regs_sr_hsh,
-+ aarch64_sys_regs_sr[i].name,
-+ (void *) (aarch64_sys_regs_sr + i));
-+
- for (i = 0; i < ARRAY_SIZE (reg_names); i++)
- checked_hash_insert (aarch64_reg_hsh, reg_names[i].name,
- (void *) (reg_names + i));
-@@ -8329,6 +8931,16 @@ md_begin (void)
- (void *) (aarch64_barrier_options + i));
- }
-
-+ for (i = 0; i < ARRAY_SIZE (aarch64_barrier_dsb_nxs_options); i++)
-+ {
-+ const char *name = aarch64_barrier_dsb_nxs_options[i].name;
-+ checked_hash_insert (aarch64_barrier_opt_hsh, name,
-+ (void *) (aarch64_barrier_dsb_nxs_options + i));
-+ /* Also hash the name in the upper case. */
-+ checked_hash_insert (aarch64_barrier_opt_hsh, get_upper_str (name),
-+ (void *) (aarch64_barrier_dsb_nxs_options + i));
-+ }
-+
- for (i = 0; i < ARRAY_SIZE (aarch64_prfops); i++)
- {
- const char* name = aarch64_prfops[i].name;
-@@ -8345,12 +8957,15 @@ md_begin (void)
- for (i = 0; aarch64_hint_options[i].name != NULL; i++)
- {
- const char* name = aarch64_hint_options[i].name;
-+ const char* upper_name = get_upper_str(name);
-
- checked_hash_insert (aarch64_hint_opt_hsh, name,
- (void *) (aarch64_hint_options + i));
-- /* Also hash the name in the upper case. */
-- checked_hash_insert (aarch64_pldop_hsh, get_upper_str (name),
-- (void *) (aarch64_hint_options + i));
-+
-+ /* Also hash the name in the upper case if not the same. */
-+ if (strcmp (name, upper_name) != 0)
-+ checked_hash_insert (aarch64_hint_opt_hsh, upper_name,
-+ (void *) (aarch64_hint_options + i));
- }
-
- /* Set the cpu variant based on the command-line options. */
-@@ -8431,6 +9046,8 @@ struct aarch64_cpu_option_table
- recognized by GCC. */
- static const struct aarch64_cpu_option_table aarch64_cpus[] = {
- {"all", AARCH64_ANY, NULL},
-+ {"cortex-a34", AARCH64_FEATURE (AARCH64_ARCH_V8,
-+ AARCH64_FEATURE_CRC), "Cortex-A34"},
- {"cortex-a35", AARCH64_FEATURE (AARCH64_ARCH_V8,
- AARCH64_FEATURE_CRC), "Cortex-A35"},
- {"cortex-a53", AARCH64_FEATURE (AARCH64_ARCH_V8,
-@@ -8447,6 +9064,57 @@ static const struct aarch64_cpu_option_t
- {"cortex-a75", AARCH64_FEATURE (AARCH64_ARCH_V8_2,
- AARCH64_FEATURE_RCPC | AARCH64_FEATURE_F16 | AARCH64_FEATURE_DOTPROD),
- "Cortex-A75"},
-+ {"cortex-a76", AARCH64_FEATURE (AARCH64_ARCH_V8_2,
-+ AARCH64_FEATURE_RCPC | AARCH64_FEATURE_F16 | AARCH64_FEATURE_DOTPROD),
-+ "Cortex-A76"},
-+ {"cortex-a76ae", AARCH64_FEATURE (AARCH64_ARCH_V8_2,
-+ AARCH64_FEATURE_F16 | AARCH64_FEATURE_RCPC
-+ | AARCH64_FEATURE_DOTPROD
-+ | AARCH64_FEATURE_SSBS),
-+ "Cortex-A76AE"},
-+ {"cortex-a77", AARCH64_FEATURE (AARCH64_ARCH_V8_2,
-+ AARCH64_FEATURE_F16 | AARCH64_FEATURE_RCPC
-+ | AARCH64_FEATURE_DOTPROD
-+ | AARCH64_FEATURE_SSBS),
-+ "Cortex-A77"},
-+ {"cortex-a65", AARCH64_FEATURE (AARCH64_ARCH_V8_2,
-+ AARCH64_FEATURE_F16 | AARCH64_FEATURE_RCPC
-+ | AARCH64_FEATURE_DOTPROD
-+ | AARCH64_FEATURE_SSBS),
-+ "Cortex-A65"},
-+ {"cortex-a65ae", AARCH64_FEATURE (AARCH64_ARCH_V8_2,
-+ AARCH64_FEATURE_F16 | AARCH64_FEATURE_RCPC
-+ | AARCH64_FEATURE_DOTPROD
-+ | AARCH64_FEATURE_SSBS),
-+ "Cortex-A65AE"},
-+ {"cortex-a78", AARCH64_FEATURE (AARCH64_ARCH_V8_2,
-+ AARCH64_FEATURE_F16
-+ | AARCH64_FEATURE_RCPC
-+ | AARCH64_FEATURE_DOTPROD
-+ | AARCH64_FEATURE_SSBS
-+ | AARCH64_FEATURE_PROFILE),
-+ "Cortex-A78"},
-+ {"cortex-a78ae", AARCH64_FEATURE (AARCH64_ARCH_V8_2,
-+ AARCH64_FEATURE_F16
-+ | AARCH64_FEATURE_RCPC
-+ | AARCH64_FEATURE_DOTPROD
-+ | AARCH64_FEATURE_SSBS
-+ | AARCH64_FEATURE_PROFILE),
-+ "Cortex-A78AE"},
-+ {"cortex-a78c", AARCH64_FEATURE (AARCH64_ARCH_V8_2,
-+ AARCH64_FEATURE_DOTPROD
-+ | AARCH64_FEATURE_F16
-+ | AARCH64_FEATURE_FLAGM
-+ | AARCH64_FEATURE_PAC
-+ | AARCH64_FEATURE_PROFILE
-+ | AARCH64_FEATURE_RCPC
-+ | AARCH64_FEATURE_SSBS),
-+ "Cortex-A78C"},
-+ {"ares", AARCH64_FEATURE (AARCH64_ARCH_V8_2,
-+ AARCH64_FEATURE_RCPC | AARCH64_FEATURE_F16
-+ | AARCH64_FEATURE_DOTPROD
-+ | AARCH64_FEATURE_PROFILE),
-+ "Ares"},
- {"exynos-m1", AARCH64_FEATURE (AARCH64_ARCH_V8,
- AARCH64_FEATURE_CRC | AARCH64_FEATURE_CRYPTO),
- "Samsung Exynos M1"},
-@@ -8454,11 +9122,40 @@ static const struct aarch64_cpu_option_t
- AARCH64_FEATURE_CRC | AARCH64_FEATURE_CRYPTO
- | AARCH64_FEATURE_RDMA),
- "Qualcomm Falkor"},
-+ {"neoverse-e1", AARCH64_FEATURE (AARCH64_ARCH_V8_2,
-+ AARCH64_FEATURE_RCPC | AARCH64_FEATURE_F16
-+ | AARCH64_FEATURE_DOTPROD
-+ | AARCH64_FEATURE_SSBS),
-+ "Neoverse E1"},
-+ {"neoverse-n1", AARCH64_FEATURE (AARCH64_ARCH_V8_2,
-+ AARCH64_FEATURE_RCPC | AARCH64_FEATURE_F16
-+ | AARCH64_FEATURE_DOTPROD
-+ | AARCH64_FEATURE_PROFILE),
-+ "Neoverse N1"},
-+ {"neoverse-n2", AARCH64_FEATURE (AARCH64_ARCH_V8_5,
-+ AARCH64_FEATURE_BFLOAT16
-+ | AARCH64_FEATURE_I8MM
-+ | AARCH64_FEATURE_F16
-+ | AARCH64_FEATURE_SVE
-+ | AARCH64_FEATURE_SVE2
-+ | AARCH64_FEATURE_SVE2_BITPERM
-+ | AARCH64_FEATURE_MEMTAG
-+ | AARCH64_FEATURE_RNG),
-+ "Neoverse N2"},
-+ {"neoverse-v1", AARCH64_FEATURE (AARCH64_ARCH_V8_4,
-+ AARCH64_FEATURE_PROFILE
-+ | AARCH64_FEATURE_CVADP
-+ | AARCH64_FEATURE_SVE
-+ | AARCH64_FEATURE_SSBS
-+ | AARCH64_FEATURE_RNG
-+ | AARCH64_FEATURE_F16
-+ | AARCH64_FEATURE_BFLOAT16
-+ | AARCH64_FEATURE_I8MM), "Neoverse V1"},
- {"qdf24xx", AARCH64_FEATURE (AARCH64_ARCH_V8,
- AARCH64_FEATURE_CRC | AARCH64_FEATURE_CRYPTO
- | AARCH64_FEATURE_RDMA),
- "Qualcomm QDF24XX"},
-- {"saphira", AARCH64_FEATURE (AARCH64_ARCH_V8_3,
-+ {"saphira", AARCH64_FEATURE (AARCH64_ARCH_V8_4,
- AARCH64_FEATURE_CRYPTO | AARCH64_FEATURE_PROFILE),
- "Qualcomm Saphira"},
- {"thunderx", AARCH64_FEATURE (AARCH64_ARCH_V8,
-@@ -8474,6 +9171,14 @@ static const struct aarch64_cpu_option_t
- {"xgene1", AARCH64_ARCH_V8, "APM X-Gene 1"},
- {"xgene2", AARCH64_FEATURE (AARCH64_ARCH_V8,
- AARCH64_FEATURE_CRC), "APM X-Gene 2"},
-+ {"cortex-r82", AARCH64_ARCH_V8_R, "Cortex-R82"},
-+ {"cortex-x1", AARCH64_FEATURE (AARCH64_ARCH_V8_2,
-+ AARCH64_FEATURE_F16
-+ | AARCH64_FEATURE_RCPC
-+ | AARCH64_FEATURE_DOTPROD
-+ | AARCH64_FEATURE_SSBS
-+ | AARCH64_FEATURE_PROFILE),
-+ "Cortex-X1"},
- {"generic", AARCH64_ARCH_V8, NULL},
-
- {NULL, AARCH64_ARCH_NONE, NULL}
-@@ -8494,6 +9199,10 @@ static const struct aarch64_arch_option_
- {"armv8.2-a", AARCH64_ARCH_V8_2},
- {"armv8.3-a", AARCH64_ARCH_V8_3},
- {"armv8.4-a", AARCH64_ARCH_V8_4},
-+ {"armv8.5-a", AARCH64_ARCH_V8_5},
-+ {"armv8.6-a", AARCH64_ARCH_V8_6},
-+ {"armv8.7-a", AARCH64_ARCH_V8_7},
-+ {"armv8-r", AARCH64_ARCH_V8_R},
- {NULL, AARCH64_ARCH_NONE}
- };
-
-@@ -8508,9 +9217,7 @@ struct aarch64_option_cpu_value_table
- static const struct aarch64_option_cpu_value_table aarch64_features[] = {
- {"crc", AARCH64_FEATURE (AARCH64_FEATURE_CRC, 0),
- AARCH64_ARCH_NONE},
-- {"crypto", AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO
-- | AARCH64_FEATURE_AES
-- | AARCH64_FEATURE_SHA2, 0),
-+ {"crypto", AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO, 0),
- AARCH64_FEATURE (AARCH64_FEATURE_SIMD, 0)},
- {"fp", AARCH64_FEATURE (AARCH64_FEATURE_FP, 0),
- AARCH64_ARCH_NONE},
-@@ -8537,6 +9244,8 @@ static const struct aarch64_option_cpu_v
- AARCH64_FEATURE (AARCH64_FEATURE_F16
- | AARCH64_FEATURE_SIMD
- | AARCH64_FEATURE_COMPNUM, 0)},
-+ {"tme", AARCH64_FEATURE (AARCH64_FEATURE_TME, 0),
-+ AARCH64_ARCH_NONE},
- {"compnum", AARCH64_FEATURE (AARCH64_FEATURE_COMPNUM, 0),
- AARCH64_FEATURE (AARCH64_FEATURE_F16
- | AARCH64_FEATURE_SIMD, 0)},
-@@ -8546,12 +9255,48 @@ static const struct aarch64_option_cpu_v
- AARCH64_ARCH_NONE},
- {"sha2", AARCH64_FEATURE (AARCH64_FEATURE_SHA2, 0),
- AARCH64_ARCH_NONE},
-+ {"sb", AARCH64_FEATURE (AARCH64_FEATURE_SB, 0),
-+ AARCH64_ARCH_NONE},
-+ {"predres", AARCH64_FEATURE (AARCH64_FEATURE_PREDRES, 0),
-+ AARCH64_ARCH_NONE},
- {"aes", AARCH64_FEATURE (AARCH64_FEATURE_AES, 0),
- AARCH64_ARCH_NONE},
- {"sm4", AARCH64_FEATURE (AARCH64_FEATURE_SM4, 0),
- AARCH64_ARCH_NONE},
-- {"sha3", AARCH64_FEATURE (AARCH64_FEATURE_SHA2
-- | AARCH64_FEATURE_SHA3, 0),
-+ {"sha3", AARCH64_FEATURE (AARCH64_FEATURE_SHA3, 0),
-+ AARCH64_FEATURE (AARCH64_FEATURE_SHA2, 0)},
-+ {"rng", AARCH64_FEATURE (AARCH64_FEATURE_RNG, 0),
-+ AARCH64_ARCH_NONE},
-+ {"ssbs", AARCH64_FEATURE (AARCH64_FEATURE_SSBS, 0),
-+ AARCH64_ARCH_NONE},
-+ {"memtag", AARCH64_FEATURE (AARCH64_FEATURE_MEMTAG, 0),
-+ AARCH64_ARCH_NONE},
-+ {"sve2", AARCH64_FEATURE (AARCH64_FEATURE_SVE2, 0),
-+ AARCH64_FEATURE (AARCH64_FEATURE_SVE, 0)},
-+ {"sve2-sm4", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_SM4, 0),
-+ AARCH64_FEATURE (AARCH64_FEATURE_SVE2
-+ | AARCH64_FEATURE_SM4, 0)},
-+ {"sve2-aes", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_AES, 0),
-+ AARCH64_FEATURE (AARCH64_FEATURE_SVE2
-+ | AARCH64_FEATURE_AES, 0)},
-+ {"sve2-sha3", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_SHA3, 0),
-+ AARCH64_FEATURE (AARCH64_FEATURE_SVE2
-+ | AARCH64_FEATURE_SHA3, 0)},
-+ {"sve2-bitperm", AARCH64_FEATURE (AARCH64_FEATURE_SVE2_BITPERM, 0),
-+ AARCH64_FEATURE (AARCH64_FEATURE_SVE2, 0)},
-+ {"bf16", AARCH64_FEATURE (AARCH64_FEATURE_BFLOAT16, 0),
-+ AARCH64_ARCH_NONE},
-+ {"i8mm", AARCH64_FEATURE (AARCH64_FEATURE_I8MM, 0),
-+ AARCH64_ARCH_NONE},
-+ {"f32mm", AARCH64_FEATURE (AARCH64_FEATURE_F32MM, 0),
-+ AARCH64_FEATURE (AARCH64_FEATURE_SVE, 0)},
-+ {"f64mm", AARCH64_FEATURE (AARCH64_FEATURE_F64MM, 0),
-+ AARCH64_FEATURE (AARCH64_FEATURE_SVE, 0)},
-+ {"ls64", AARCH64_FEATURE (AARCH64_FEATURE_LS64, 0),
-+ AARCH64_ARCH_NONE},
-+ {"flagm", AARCH64_FEATURE (AARCH64_FEATURE_FLAGM, 0),
-+ AARCH64_ARCH_NONE},
-+ {"pauth", AARCH64_FEATURE (AARCH64_FEATURE_PAC, 0),
- AARCH64_ARCH_NONE},
- {NULL, AARCH64_ARCH_NONE, AARCH64_ARCH_NONE},
- };
-@@ -9042,8 +9787,7 @@ aarch64_elf_copy_symbol_attributes (symb
- }
- else
- {
-- if (destelf->size != NULL)
-- free (destelf->size);
-+ free (destelf->size);
- destelf->size = NULL;
- }
- S_SET_SIZE (dest, S_GET_SIZE (src));
-diff -rup binutils-2.30/gas/config/tc-aarch64.h binutils-2.30.new/gas/config/tc-aarch64.h
---- binutils-2.30/gas/config/tc-aarch64.h 2021-03-23 16:21:44.128021971 +0000
-+++ binutils-2.30.new/gas/config/tc-aarch64.h 2021-03-23 16:19:55.026763667 +0000
-@@ -1,5 +1,5 @@
- /* tc-aarch64.h -- Header file for tc-aarch64.c.
-- Copyright (C) 2009-2018 Free Software Foundation, Inc.
-+ Copyright (C) 2009-2021 Free Software Foundation, Inc.
- Contributed by ARM Ltd.
-
- This file is part of GAS.
-@@ -78,6 +78,45 @@ struct aarch64_fix
- /* We also need to mark assembler created symbols: */
- #define tc_frob_fake_label(S) aarch64_frob_label (S)
-
-+#define tc_frob_section(S) aarch64_frob_section (S)
-+
-+/* The key used to sign a function's return address. */
-+enum pointer_auth_key {
-+ AARCH64_PAUTH_KEY_A,
-+ AARCH64_PAUTH_KEY_B
-+};
-+
-+/* The extra fields required by AArch64 in fde_entry and cie_entry. Currently
-+ only used to store the key used to sign the frame's return address. */
-+#define tc_fde_entry_extras enum pointer_auth_key pauth_key;
-+#define tc_cie_entry_extras enum pointer_auth_key pauth_key;
-+
-+/* The extra initialisation steps needed by AArch64 in alloc_fde_entry.
-+ Currently only used to initialise the key used to sign the return
-+ address. */
-+#define tc_fde_entry_init_extra(fde) fde->pauth_key = AARCH64_PAUTH_KEY_A;
-+
-+/* Extra checks required by AArch64 when outputting the current cie_entry.
-+ Currently only used to output a 'B' if the return address is signed with the
-+ B key. */
-+#define tc_output_cie_extra(cie) \
-+ do \
-+ { \
-+ if (cie->pauth_key == AARCH64_PAUTH_KEY_B) \
-+ out_one ('B'); \
-+ } \
-+ while (0)
-+
-+/* Extra equivalence checks required by AArch64 when selecting the correct cie
-+ for some fde. Currently only used to check for quivalence between keys used
-+ to sign ther return address. */
-+#define tc_cie_fde_equivalent_extra(cie, fde) (cie->pauth_key == fde->pauth_key)
-+
-+/* The extra initialisation steps needed by AArch64 in select_cie_for_fde.
-+ Currently only used to initialise the key used to sign the return
-+ address. */
-+#define tc_cie_entry_init_extra(cie, fde) cie->pauth_key = fde->pauth_key;
-+
- #define TC_FIX_TYPE struct aarch64_fix
- #define TC_INIT_FIX_DATA(FIX) { (FIX)->tc_fix_data.inst = NULL; \
- (FIX)->tc_fix_data.opnd = AARCH64_OPND_NIL; }
-@@ -140,8 +179,7 @@ struct aarch64_frag_type
- };
-
- #define TC_FRAG_TYPE struct aarch64_frag_type
--/* NOTE: max_chars is a local variable from frag_var / frag_variant. */
--#define TC_FRAG_INIT(fragp) aarch64_init_frag (fragp, max_chars)
-+#define TC_FRAG_INIT(fragp) aarch64_init_frag (fragp, max_chars)
- #define HANDLE_ALIGN(fragp) aarch64_handle_align (fragp)
-
- #define md_do_align(N, FILL, LEN, MAX, LABEL) \
-@@ -189,6 +227,7 @@ struct aarch64_segment_info_type
- {
- enum mstate mapstate;
- unsigned int marked_pr_dependency;
-+ aarch64_instr_sequence insn_sequence;
- };
-
- /* We want .cfi_* pseudo-ops for generating unwind info. */
-@@ -223,6 +262,7 @@ extern int aarch64_force_relocation (str
- extern void aarch64_cleanup (void);
- extern void aarch64_start_line_hook (void);
- extern void aarch64_frob_label (symbolS *);
-+extern void aarch64_frob_section (asection *sec);
- extern int aarch64_data_in_code (void);
- extern char * aarch64_canonicalize_symbol_name (char *);
- extern void aarch64_adjust_symtab (void);
-diff -rup binutils-2.30/gas/testsuite/gas/aarch64/advsimd-armv8_3.d binutils-2.30.new/gas/testsuite/gas/aarch64/advsimd-armv8_3.d
---- binutils-2.30/gas/testsuite/gas/aarch64/advsimd-armv8_3.d 2018-01-13 13:31:15.000000000 +0000
-+++ binutils-2.30.new/gas/testsuite/gas/aarch64/advsimd-armv8_3.d 2021-03-23 16:19:56.770751812 +0000
-@@ -7,27 +7,7752 @@ Disassembly of section \.text:
-
- 0+ <.*>:
- [^:]+: 6ec3c441 fcmla v1.2d, v2.2d, v3.2d, #0
-+[^:]+: 6ec4c441 fcmla v1.2d, v2.2d, v4.2d, #0
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-+[^:]+: 6e5ef4a5 fcadd v5.8h, v5.8h, v30.8h, #270
-+[^:]+: 6e43f5c5 fcadd v5.8h, v14.8h, v3.8h, #270
-+[^:]+: 6e44f5c5 fcadd v5.8h, v14.8h, v4.8h, #270
-+[^:]+: 6e46f5c5 fcadd v5.8h, v14.8h, v6.8h, #270
-+[^:]+: 6e4ff5c5 fcadd v5.8h, v14.8h, v15.8h, #270
-+[^:]+: 6e5ef5c5 fcadd v5.8h, v14.8h, v30.8h, #270
-+[^:]+: 6e43f7e5 fcadd v5.8h, v31.8h, v3.8h, #270
-+[^:]+: 6e44f7e5 fcadd v5.8h, v31.8h, v4.8h, #270
-+[^:]+: 6e46f7e5 fcadd v5.8h, v31.8h, v6.8h, #270
-+[^:]+: 6e4ff7e5 fcadd v5.8h, v31.8h, v15.8h, #270
-+[^:]+: 6e5ef7e5 fcadd v5.8h, v31.8h, v30.8h, #270
-+[^:]+: 6e43f44d fcadd v13.8h, v2.8h, v3.8h, #270
-+[^:]+: 6e44f44d fcadd v13.8h, v2.8h, v4.8h, #270
-+[^:]+: 6e46f44d fcadd v13.8h, v2.8h, v6.8h, #270
-+[^:]+: 6e4ff44d fcadd v13.8h, v2.8h, v15.8h, #270
-+[^:]+: 6e5ef44d fcadd v13.8h, v2.8h, v30.8h, #270
-+[^:]+: 6e43f46d fcadd v13.8h, v3.8h, v3.8h, #270
-+[^:]+: 6e44f46d fcadd v13.8h, v3.8h, v4.8h, #270
-+[^:]+: 6e46f46d fcadd v13.8h, v3.8h, v6.8h, #270
-+[^:]+: 6e4ff46d fcadd v13.8h, v3.8h, v15.8h, #270
-+[^:]+: 6e5ef46d fcadd v13.8h, v3.8h, v30.8h, #270
-+[^:]+: 6e43f4ad fcadd v13.8h, v5.8h, v3.8h, #270
-+[^:]+: 6e44f4ad fcadd v13.8h, v5.8h, v4.8h, #270
-+[^:]+: 6e46f4ad fcadd v13.8h, v5.8h, v6.8h, #270
-+[^:]+: 6e4ff4ad fcadd v13.8h, v5.8h, v15.8h, #270
-+[^:]+: 6e5ef4ad fcadd v13.8h, v5.8h, v30.8h, #270
-+[^:]+: 6e43f5cd fcadd v13.8h, v14.8h, v3.8h, #270
-+[^:]+: 6e44f5cd fcadd v13.8h, v14.8h, v4.8h, #270
-+[^:]+: 6e46f5cd fcadd v13.8h, v14.8h, v6.8h, #270
-+[^:]+: 6e4ff5cd fcadd v13.8h, v14.8h, v15.8h, #270
-+[^:]+: 6e5ef5cd fcadd v13.8h, v14.8h, v30.8h, #270
-+[^:]+: 6e43f7ed fcadd v13.8h, v31.8h, v3.8h, #270
-+[^:]+: 6e44f7ed fcadd v13.8h, v31.8h, v4.8h, #270
-+[^:]+: 6e46f7ed fcadd v13.8h, v31.8h, v6.8h, #270
-+[^:]+: 6e4ff7ed fcadd v13.8h, v31.8h, v15.8h, #270
-+[^:]+: 6e5ef7ed fcadd v13.8h, v31.8h, v30.8h, #270
-+[^:]+: 6e43f45b fcadd v27.8h, v2.8h, v3.8h, #270
-+[^:]+: 6e44f45b fcadd v27.8h, v2.8h, v4.8h, #270
-+[^:]+: 6e46f45b fcadd v27.8h, v2.8h, v6.8h, #270
-+[^:]+: 6e4ff45b fcadd v27.8h, v2.8h, v15.8h, #270
-+[^:]+: 6e5ef45b fcadd v27.8h, v2.8h, v30.8h, #270
-+[^:]+: 6e43f47b fcadd v27.8h, v3.8h, v3.8h, #270
-+[^:]+: 6e44f47b fcadd v27.8h, v3.8h, v4.8h, #270
-+[^:]+: 6e46f47b fcadd v27.8h, v3.8h, v6.8h, #270
-+[^:]+: 6e4ff47b fcadd v27.8h, v3.8h, v15.8h, #270
-+[^:]+: 6e5ef47b fcadd v27.8h, v3.8h, v30.8h, #270
-+[^:]+: 6e43f4bb fcadd v27.8h, v5.8h, v3.8h, #270
-+[^:]+: 6e44f4bb fcadd v27.8h, v5.8h, v4.8h, #270
-+[^:]+: 6e46f4bb fcadd v27.8h, v5.8h, v6.8h, #270
-+[^:]+: 6e4ff4bb fcadd v27.8h, v5.8h, v15.8h, #270
-+[^:]+: 6e5ef4bb fcadd v27.8h, v5.8h, v30.8h, #270
-+[^:]+: 6e43f5db fcadd v27.8h, v14.8h, v3.8h, #270
-+[^:]+: 6e44f5db fcadd v27.8h, v14.8h, v4.8h, #270
-+[^:]+: 6e46f5db fcadd v27.8h, v14.8h, v6.8h, #270
-+[^:]+: 6e4ff5db fcadd v27.8h, v14.8h, v15.8h, #270
-+[^:]+: 6e5ef5db fcadd v27.8h, v14.8h, v30.8h, #270
-+[^:]+: 6e43f7fb fcadd v27.8h, v31.8h, v3.8h, #270
-+[^:]+: 6e44f7fb fcadd v27.8h, v31.8h, v4.8h, #270
-+[^:]+: 6e46f7fb fcadd v27.8h, v31.8h, v6.8h, #270
-+[^:]+: 6e4ff7fb fcadd v27.8h, v31.8h, v15.8h, #270
-+[^:]+: 6e5ef7fb fcadd v27.8h, v31.8h, v30.8h, #270
-diff -rup binutils-2.30/gas/testsuite/gas/aarch64/advsimd-armv8_3.s binutils-2.30.new/gas/testsuite/gas/aarch64/advsimd-armv8_3.s
---- binutils-2.30/gas/testsuite/gas/aarch64/advsimd-armv8_3.s 2018-01-13 13:31:15.000000000 +0000
-+++ binutils-2.30.new/gas/testsuite/gas/aarch64/advsimd-armv8_3.s 2021-03-23 16:19:56.767751833 +0000
-@@ -1,36 +1,64 @@
- /* Test file for ARMv8.3 complex arithmetics instructions. */
- .text
-
-+ .macro three_same op, sz
-+ .irp rot, 0, 90, 180, 270
-+ .irp d, 1.\sz, 2.\sz, 5.\sz, 13.\sz, 27.\sz
-+ .irp m, 2.\sz, 3.\sz, 5.\sz, 14.\sz, 31.\sz
-+ .irp n, 3.\sz, 4.\sz, 6.\sz, 15.\sz, 30.\sz
-+ \op v\d, v\m, v\n, #\rot
-+ .endr
-+ .endr
-+ .endr
-+ .endr
-+ .endm
-+
-+ .macro three_element op, sz1, sz2, idx
-+ .irp rot, 0, 90, 180, 270
-+ .irp d, 1.\sz1, 2.\sz1, 5.\sz1, 13.\sz1, 27.\sz1
-+ .irp m, 2.\sz1, 3.\sz1, 5.\sz1, 14.\sz1, 31.\sz1
-+ .irp n, 3.\sz2, 4.\sz2, 6.\sz2, 15.\sz2, 30.\sz2
-+ \op v\d, v\m, v\n[\idx], #\rot
-+ .endr
-+ .endr
-+ .endr
-+ .endr
-+ .endm
-+
-+ .macro three_same_rot op, sz
-+ .irp rot, 90, 270
-+ .irp d, 1.\sz, 2.\sz, 5.\sz, 13.\sz, 27.\sz
-+ .irp m, 2.\sz, 3.\sz, 5.\sz, 14.\sz, 31.\sz
-+ .irp n, 3.\sz, 4.\sz, 6.\sz, 15.\sz, 30.\sz
-+ \op v\d, v\m, v\n, #\rot
-+ .endr
-+ .endr
-+ .endr
-+ .endr
-+ .endm
-+
- /* Three-same operands FCMLA. */
-- fcmla v1.2d, v2.2d, v3.2d, #0
-- fcmla v1.2d, v2.2d, v3.2d, #90
-- fcmla v1.2d, v2.2d, v3.2d, #180
-- fcmla v1.2d, v2.2d, v3.2d, #270
--
-- fcmla v1.2s, v2.2s, v3.2s, #90
-- fcmla v1.4s, v2.4s, v3.4s, #90
-- fcmla v1.4h, v2.4h, v3.4h, #90
-- fcmla v1.8h, v2.8h, v3.8h, #90
-+ three_same fcmla, 2d
-+ three_same fcmla, 2s
-+ three_same fcmla, 4s
-+ three_same fcmla, 4h
-+ three_same fcmla, 8h
-
- /* Indexed element FCMLA. */
-- fcmla v1.4s, v2.4s, v3.s[0], #0
-- fcmla v1.4s, v2.4s, v3.s[0], #90
-- fcmla v1.4s, v2.4s, v3.s[0], #180
-- fcmla v1.4s, v2.4s, v3.s[0], #270
-- fcmla v1.4s, v2.4s, v3.s[1], #90
--
-- fcmla v1.4h, v2.4h, v3.h[0], #90
-- fcmla v1.4h, v2.4h, v3.h[1], #90
-- fcmla v1.8h, v2.8h, v3.h[0], #90
-- fcmla v1.8h, v2.8h, v3.h[1], #90
-- fcmla v1.8h, v2.8h, v3.h[2], #90
-- fcmla v1.8h, v2.8h, v3.h[3], #90
-+ three_element fcmla, 4s, s, 0
-+ three_element fcmla, 4s, s, 1
-
-- /* Three-same operands FADD. */
-- fcadd v1.2d, v2.2d, v3.2d, #90
-- fcadd v1.2d, v2.2d, v3.2d, #270
-+ three_element fcmla, 4h, h, 0
-+ three_element fcmla, 4h, h, 1
-
-- fcadd v1.2s, v2.2s, v3.2s, #90
-- fcadd v1.4s, v2.4s, v3.4s, #90
-- fcadd v1.4h, v2.4h, v3.4h, #90
-- fcadd v1.8h, v2.8h, v3.8h, #90
-+ three_element fcmla, 8h, h, 0
-+ three_element fcmla, 8h, h, 1
-+ three_element fcmla, 8h, h, 2
-+ three_element fcmla, 8h, h, 3
-+
-+ /* Three-same operands FADD. */
-+ three_same_rot fcadd, 2d
-+ three_same_rot fcadd, 2s
-+ three_same_rot fcadd, 4s
-+ three_same_rot fcadd, 4h
-+ three_same_rot fcadd, 8h
-diff -rup binutils-2.30/gas/testsuite/gas/aarch64/advsimd-compnum.d binutils-2.30.new/gas/testsuite/gas/aarch64/advsimd-compnum.d
---- binutils-2.30/gas/testsuite/gas/aarch64/advsimd-compnum.d 2018-01-13 13:31:15.000000000 +0000
-+++ binutils-2.30.new/gas/testsuite/gas/aarch64/advsimd-compnum.d 2021-03-23 16:19:56.738752030 +0000
-@@ -6,35 +6,8253 @@
- Disassembly of section \.text:
-
- 0+ <.*>:
--[^:]+: 6ec3c441 fcmla v1\.2d, v2\.2d, v3\.2d, #0
--[^:]+: 6ec3cc41 fcmla v1\.2d, v2\.2d, v3\.2d, #90
--[^:]+: 6ec3d441 fcmla v1\.2d, v2\.2d, v3\.2d, #180
--[^:]+: 6ec3dc41 fcmla v1\.2d, v2\.2d, v3\.2d, #270
--[^:]+: 2e83cc41 fcmla v1\.2s, v2\.2s, v3\.2s, #90
--[^:]+: 6e83cc41 fcmla v1\.4s, v2\.4s, v3\.4s, #90
--[^:]+: 2e43cc41 fcmla v1\.4h, v2\.4h, v3\.4h, #90
--[^:]+: 6e43cc41 fcmla v1\.8h, v2\.8h, v3\.8h, #90
--[^:]+: 6f831041 fcmla v1\.4s, v2\.4s, v3\.s\[0\], #0
--[^:]+: 6f833041 fcmla v1\.4s, v2\.4s, v3\.s\[0\], #90
--[^:]+: 6f835041 fcmla v1\.4s, v2\.4s, v3\.s\[0\], #180
--[^:]+: 6f837041 fcmla v1\.4s, v2\.4s, v3\.s\[0\], #270
--[^:]+: 6f833841 fcmla v1\.4s, v2\.4s, v3\.s\[1\], #90
--[^:]+: 2f433041 fcmla v1\.4h, v2\.4h, v3\.h\[0\], #90
--[^:]+: 2f633041 fcmla v1\.4h, v2\.4h, v3\.h\[1\], #90
--[^:]+: 6f433041 fcmla v1\.8h, v2\.8h, v3\.h\[0\], #90
--[^:]+: 6f633041 fcmla v1\.8h, v2\.8h, v3\.h\[1\], #90
--[^:]+: 6f433841 fcmla v1\.8h, v2\.8h, v3\.h\[2\], #90
--[^:]+: 6f633841 fcmla v1\.8h, v2\.8h, v3\.h\[3\], #90
--[^:]+: 6ec3e441 fcadd v1\.2d, v2\.2d, v3\.2d, #90
--[^:]+: 6ec3f441 fcadd v1\.2d, v2\.2d, v3\.2d, #270
--[^:]+: 2e83e441 fcadd v1\.2s, v2\.2s, v3\.2s, #90
--[^:]+: 6e83e441 fcadd v1\.4s, v2\.4s, v3\.4s, #90
--[^:]+: 2e43e441 fcadd v1\.4h, v2\.4h, v3\.4h, #90
--[^:]+: 6e43e441 fcadd v1\.8h, v2\.8h, v3\.8h, #90
--[^:]+: 4e63d441 fadd v1\.2d, v2\.2d, v3\.2d
--[^:]+: 0e23d441 fadd v1\.2s, v2\.2s, v3\.2s
--[^:]+: 4e23d441 fadd v1\.4s, v2\.4s, v3\.4s
--[^:]+: 0e401400 fadd v0\.4h, v0\.4h, v0\.4h
--[^:]+: 0e431441 fadd v1\.4h, v2\.4h, v3\.4h
--[^:]+: 4e401400 fadd v0\.8h, v0\.8h, v0\.8h
--[^:]+: 4e431441 fadd v1\.8h, v2\.8h, v3\.8h
-+[^:]+: 6ec3c441 fcmla v1.2d, v2.2d, v3.2d, #0
-+[^:]+: 6ec4c441 fcmla v1.2d, v2.2d, v4.2d, #0
-+[^:]+: 6ec6c441 fcmla v1.2d, v2.2d, v6.2d, #0
-+[^:]+: 6ecfc441 fcmla v1.2d, v2.2d, v15.2d, #0
-+[^:]+: 6edec441 fcmla v1.2d, v2.2d, v30.2d, #0
-+[^:]+: 6ec3c461 fcmla v1.2d, v3.2d, v3.2d, #0
-+[^:]+: 6ec4c461 fcmla v1.2d, v3.2d, v4.2d, #0
-+[^:]+: 6ec6c461 fcmla v1.2d, v3.2d, v6.2d, #0
-+[^:]+: 6ecfc461 fcmla v1.2d, v3.2d, v15.2d, #0
-+[^:]+: 6edec461 fcmla v1.2d, v3.2d, v30.2d, #0
-+[^:]+: 6ec3c4a1 fcmla v1.2d, v5.2d, v3.2d, #0
-+[^:]+: 6ec4c4a1 fcmla v1.2d, v5.2d, v4.2d, #0
-+[^:]+: 6ec6c4a1 fcmla v1.2d, v5.2d, v6.2d, #0
-+[^:]+: 6ecfc4a1 fcmla v1.2d, v5.2d, v15.2d, #0
-+[^:]+: 6edec4a1 fcmla v1.2d, v5.2d, v30.2d, #0
-+[^:]+: 6ec3c5c1 fcmla v1.2d, v14.2d, v3.2d, #0
-+[^:]+: 6ec4c5c1 fcmla v1.2d, v14.2d, v4.2d, #0
-+[^:]+: 6ec6c5c1 fcmla v1.2d, v14.2d, v6.2d, #0
-+[^:]+: 6ecfc5c1 fcmla v1.2d, v14.2d, v15.2d, #0
-+[^:]+: 6edec5c1 fcmla v1.2d, v14.2d, v30.2d, #0
-+[^:]+: 6ec3c7e1 fcmla v1.2d, v31.2d, v3.2d, #0
-+[^:]+: 6ec4c7e1 fcmla v1.2d, v31.2d, v4.2d, #0
-+[^:]+: 6ec6c7e1 fcmla v1.2d, v31.2d, v6.2d, #0
-+[^:]+: 6ecfc7e1 fcmla v1.2d, v31.2d, v15.2d, #0
-+[^:]+: 6edec7e1 fcmla v1.2d, v31.2d, v30.2d, #0
-+[^:]+: 6ec3c442 fcmla v2.2d, v2.2d, v3.2d, #0
-+[^:]+: 6ec4c442 fcmla v2.2d, v2.2d, v4.2d, #0
-+[^:]+: 6ec6c442 fcmla v2.2d, v2.2d, v6.2d, #0
-+[^:]+: 6ecfc442 fcmla v2.2d, v2.2d, v15.2d, #0
-+[^:]+: 6edec442 fcmla v2.2d, v2.2d, v30.2d, #0
-+[^:]+: 6ec3c462 fcmla v2.2d, v3.2d, v3.2d, #0
-+[^:]+: 6ec4c462 fcmla v2.2d, v3.2d, v4.2d, #0
-+[^:]+: 6ec6c462 fcmla v2.2d, v3.2d, v6.2d, #0
-+[^:]+: 6ecfc462 fcmla v2.2d, v3.2d, v15.2d, #0
-+[^:]+: 6edec462 fcmla v2.2d, v3.2d, v30.2d, #0
-+[^:]+: 6ec3c4a2 fcmla v2.2d, v5.2d, v3.2d, #0
-+[^:]+: 6ec4c4a2 fcmla v2.2d, v5.2d, v4.2d, #0
-+[^:]+: 6ec6c4a2 fcmla v2.2d, v5.2d, v6.2d, #0
-+[^:]+: 6ecfc4a2 fcmla v2.2d, v5.2d, v15.2d, #0
-+[^:]+: 6edec4a2 fcmla v2.2d, v5.2d, v30.2d, #0
-+[^:]+: 6ec3c5c2 fcmla v2.2d, v14.2d, v3.2d, #0
-+[^:]+: 6ec4c5c2 fcmla v2.2d, v14.2d, v4.2d, #0
-+[^:]+: 6ec6c5c2 fcmla v2.2d, v14.2d, v6.2d, #0
-+[^:]+: 6ecfc5c2 fcmla v2.2d, v14.2d, v15.2d, #0
-+[^:]+: 6edec5c2 fcmla v2.2d, v14.2d, v30.2d, #0
-+[^:]+: 6ec3c7e2 fcmla v2.2d, v31.2d, v3.2d, #0
-+[^:]+: 6ec4c7e2 fcmla v2.2d, v31.2d, v4.2d, #0
-+[^:]+: 6ec6c7e2 fcmla v2.2d, v31.2d, v6.2d, #0
-+[^:]+: 6ecfc7e2 fcmla v2.2d, v31.2d, v15.2d, #0
-+[^:]+: 6edec7e2 fcmla v2.2d, v31.2d, v30.2d, #0
-+[^:]+: 6ec3c445 fcmla v5.2d, v2.2d, v3.2d, #0
-+[^:]+: 6ec4c445 fcmla v5.2d, v2.2d, v4.2d, #0
-+[^:]+: 6ec6c445 fcmla v5.2d, v2.2d, v6.2d, #0
-+[^:]+: 6ecfc445 fcmla v5.2d, v2.2d, v15.2d, #0
-+[^:]+: 6edec445 fcmla v5.2d, v2.2d, v30.2d, #0
-+[^:]+: 6ec3c465 fcmla v5.2d, v3.2d, v3.2d, #0
-+[^:]+: 6ec4c465 fcmla v5.2d, v3.2d, v4.2d, #0
-+[^:]+: 6ec6c465 fcmla v5.2d, v3.2d, v6.2d, #0
-+[^:]+: 6ecfc465 fcmla v5.2d, v3.2d, v15.2d, #0
-+[^:]+: 6edec465 fcmla v5.2d, v3.2d, v30.2d, #0
-+[^:]+: 6ec3c4a5 fcmla v5.2d, v5.2d, v3.2d, #0
-+[^:]+: 6ec4c4a5 fcmla v5.2d, v5.2d, v4.2d, #0
-+[^:]+: 6ec6c4a5 fcmla v5.2d, v5.2d, v6.2d, #0
-+[^:]+: 6ecfc4a5 fcmla v5.2d, v5.2d, v15.2d, #0
-+[^:]+: 6edec4a5 fcmla v5.2d, v5.2d, v30.2d, #0
-+[^:]+: 6ec3c5c5 fcmla v5.2d, v14.2d, v3.2d, #0
-+[^:]+: 6ec4c5c5 fcmla v5.2d, v14.2d, v4.2d, #0
-+[^:]+: 6ec6c5c5 fcmla v5.2d, v14.2d, v6.2d, #0
-+[^:]+: 6ecfc5c5 fcmla v5.2d, v14.2d, v15.2d, #0
-+[^:]+: 6edec5c5 fcmla v5.2d, v14.2d, v30.2d, #0
-+[^:]+: 6ec3c7e5 fcmla v5.2d, v31.2d, v3.2d, #0
-+[^:]+: 6ec4c7e5 fcmla v5.2d, v31.2d, v4.2d, #0
-+[^:]+: 6ec6c7e5 fcmla v5.2d, v31.2d, v6.2d, #0
-+[^:]+: 6ecfc7e5 fcmla v5.2d, v31.2d, v15.2d, #0
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-+[^:]+: 4e4f15c5 fadd v5.8h, v14.8h, v15.8h
-+[^:]+: 4e5e15c5 fadd v5.8h, v14.8h, v30.8h
-+[^:]+: 4e4317e5 fadd v5.8h, v31.8h, v3.8h
-+[^:]+: 4e4417e5 fadd v5.8h, v31.8h, v4.8h
-+[^:]+: 4e4617e5 fadd v5.8h, v31.8h, v6.8h
-+[^:]+: 4e4f17e5 fadd v5.8h, v31.8h, v15.8h
-+[^:]+: 4e5e17e5 fadd v5.8h, v31.8h, v30.8h
-+[^:]+: 4e43144d fadd v13.8h, v2.8h, v3.8h
-+[^:]+: 4e44144d fadd v13.8h, v2.8h, v4.8h
-+[^:]+: 4e46144d fadd v13.8h, v2.8h, v6.8h
-+[^:]+: 4e4f144d fadd v13.8h, v2.8h, v15.8h
-+[^:]+: 4e5e144d fadd v13.8h, v2.8h, v30.8h
-+[^:]+: 4e43146d fadd v13.8h, v3.8h, v3.8h
-+[^:]+: 4e44146d fadd v13.8h, v3.8h, v4.8h
-+[^:]+: 4e46146d fadd v13.8h, v3.8h, v6.8h
-+[^:]+: 4e4f146d fadd v13.8h, v3.8h, v15.8h
-+[^:]+: 4e5e146d fadd v13.8h, v3.8h, v30.8h
-+[^:]+: 4e4314ad fadd v13.8h, v5.8h, v3.8h
-+[^:]+: 4e4414ad fadd v13.8h, v5.8h, v4.8h
-+[^:]+: 4e4614ad fadd v13.8h, v5.8h, v6.8h
-+[^:]+: 4e4f14ad fadd v13.8h, v5.8h, v15.8h
-+[^:]+: 4e5e14ad fadd v13.8h, v5.8h, v30.8h
-+[^:]+: 4e4315cd fadd v13.8h, v14.8h, v3.8h
-+[^:]+: 4e4415cd fadd v13.8h, v14.8h, v4.8h
-+[^:]+: 4e4615cd fadd v13.8h, v14.8h, v6.8h
-+[^:]+: 4e4f15cd fadd v13.8h, v14.8h, v15.8h
-+[^:]+: 4e5e15cd fadd v13.8h, v14.8h, v30.8h
-+[^:]+: 4e4317ed fadd v13.8h, v31.8h, v3.8h
-+[^:]+: 4e4417ed fadd v13.8h, v31.8h, v4.8h
-+[^:]+: 4e4617ed fadd v13.8h, v31.8h, v6.8h
-+[^:]+: 4e4f17ed fadd v13.8h, v31.8h, v15.8h
-+[^:]+: 4e5e17ed fadd v13.8h, v31.8h, v30.8h
-+[^:]+: 4e43145b fadd v27.8h, v2.8h, v3.8h
-+[^:]+: 4e44145b fadd v27.8h, v2.8h, v4.8h
-+[^:]+: 4e46145b fadd v27.8h, v2.8h, v6.8h
-+[^:]+: 4e4f145b fadd v27.8h, v2.8h, v15.8h
-+[^:]+: 4e5e145b fadd v27.8h, v2.8h, v30.8h
-+[^:]+: 4e43147b fadd v27.8h, v3.8h, v3.8h
-+[^:]+: 4e44147b fadd v27.8h, v3.8h, v4.8h
-+[^:]+: 4e46147b fadd v27.8h, v3.8h, v6.8h
-+[^:]+: 4e4f147b fadd v27.8h, v3.8h, v15.8h
-+[^:]+: 4e5e147b fadd v27.8h, v3.8h, v30.8h
-+[^:]+: 4e4314bb fadd v27.8h, v5.8h, v3.8h
-+[^:]+: 4e4414bb fadd v27.8h, v5.8h, v4.8h
-+[^:]+: 4e4614bb fadd v27.8h, v5.8h, v6.8h
-+[^:]+: 4e4f14bb fadd v27.8h, v5.8h, v15.8h
-+[^:]+: 4e5e14bb fadd v27.8h, v5.8h, v30.8h
-+[^:]+: 4e4315db fadd v27.8h, v14.8h, v3.8h
-+[^:]+: 4e4415db fadd v27.8h, v14.8h, v4.8h
-+[^:]+: 4e4615db fadd v27.8h, v14.8h, v6.8h
-+[^:]+: 4e4f15db fadd v27.8h, v14.8h, v15.8h
-+[^:]+: 4e5e15db fadd v27.8h, v14.8h, v30.8h
-+[^:]+: 4e4317fb fadd v27.8h, v31.8h, v3.8h
-+[^:]+: 4e4417fb fadd v27.8h, v31.8h, v4.8h
-+[^:]+: 4e4617fb fadd v27.8h, v31.8h, v6.8h
-+[^:]+: 4e4f17fb fadd v27.8h, v31.8h, v15.8h
-+[^:]+: 4e5e17fb fadd v27.8h, v31.8h, v30.8h
-diff -rup binutils-2.30/gas/testsuite/gas/aarch64/advsimd-compnum.s binutils-2.30.new/gas/testsuite/gas/aarch64/advsimd-compnum.s
---- binutils-2.30/gas/testsuite/gas/aarch64/advsimd-compnum.s 2018-01-13 13:31:15.000000000 +0000
-+++ binutils-2.30.new/gas/testsuite/gas/aarch64/advsimd-compnum.s 2021-03-23 16:19:56.739752023 +0000
-@@ -1,9 +1,16 @@
- .include "advsimd-armv8_3.s"
-
-- fadd v1.2d, v2.2d, v3.2d
-- fadd v1.2s, v2.2s, v3.2s
-- fadd v1.4s, v2.4s, v3.4s
-- fadd v0.4h, v0.4h, v0.4h
-- fadd v1.4h, v2.4h, v3.4h
-- fadd v0.8h, v0.8h, v0.8h
-- fadd v1.8h, v2.8h, v3.8h
-+ .macro three_same_no_rot op, sz
-+ .irp d, 1.\sz, 2.\sz, 5.\sz, 13.\sz, 27.\sz
-+ .irp m, 2.\sz, 3.\sz, 5.\sz, 14.\sz, 31.\sz
-+ .irp n, 3.\sz, 4.\sz, 6.\sz, 15.\sz, 30.\sz
-+ \op v\d, v\m, v\n
-+ .endr
-+ .endr
-+ .endr
-+ .endm
-+
-+ three_same_no_rot fadd, 2d
-+ three_same_no_rot fadd, 2s
-+ three_same_no_rot fadd, 4h
-+ three_same_no_rot fadd, 8h
-Only in binutils-2.30.new/gas/testsuite/gas/aarch64: armv8-ras-1_1-invalid.d
-Only in binutils-2.30.new/gas/testsuite/gas/aarch64: armv8-ras-1_1-invalid.l
-Only in binutils-2.30.new/gas/testsuite/gas/aarch64: armv8-ras-1_1-invalid.s
-Only in binutils-2.30.new/gas/testsuite/gas/aarch64: armv8-ras-1_1.d
-Only in binutils-2.30.new/gas/testsuite/gas/aarch64: armv8-ras-1_1.s
-diff -rup binutils-2.30/gas/testsuite/gas/aarch64/armv8_4-a.d binutils-2.30.new/gas/testsuite/gas/aarch64/armv8_4-a.d
---- binutils-2.30/gas/testsuite/gas/aarch64/armv8_4-a.d 2018-01-13 13:31:15.000000000 +0000
-+++ binutils-2.30.new/gas/testsuite/gas/aarch64/armv8_4-a.d 2021-03-23 16:19:56.745751982 +0000
-@@ -2202,3 +2202,4 @@ Disassembly of section \.text:
- [^:]+:\s+998033fe ldapursw x30, \[sp, #3\]
- [^:]+:\s+998523fe ldapursw x30, \[sp, #82\]
- [^:]+:\s+9980d3fe ldapursw x30, \[sp, #13\]
-+[^:]+:\s+d500401f cfinv
-\ No newline at end of file
-diff -rup binutils-2.30/gas/testsuite/gas/aarch64/armv8_4-a.s binutils-2.30.new/gas/testsuite/gas/aarch64/armv8_4-a.s
---- binutils-2.30/gas/testsuite/gas/aarch64/armv8_4-a.s 2018-01-13 13:31:15.000000000 +0000
-+++ binutils-2.30.new/gas/testsuite/gas/aarch64/armv8_4-a.s 2021-03-23 16:19:56.750751949 +0000
-@@ -144,3 +144,6 @@ func:
- gen1reg_iter ldapursw x,", [sp]"
- gen3reg_iter ldapursw x,, [x,,,]
- gen2reg_iter_offset ldapursw x,,sp
-+
-+ cfinv
-+
-Only in binutils-2.30.new/gas/testsuite/gas/aarch64: armv8_5-a-dp.d
-Only in binutils-2.30.new/gas/testsuite/gas/aarch64: armv8_5-a-dp.s
-Only in binutils-2.30.new/gas/testsuite/gas/aarch64: armv8_5-a-memtag.d
-Only in binutils-2.30.new/gas/testsuite/gas/aarch64: armv8_5-a-memtag.s
-Only in binutils-2.30.new/gas/testsuite/gas/aarch64: bfloat16-directive-be.d
-Only in binutils-2.30.new/gas/testsuite/gas/aarch64: bfloat16-directive-le.d
-Only in binutils-2.30.new/gas/testsuite/gas/aarch64: bfloat16-directive.s
-Only in binutils-2.30.new/gas/testsuite/gas/aarch64: bfloat16.d
-Only in binutils-2.30.new/gas/testsuite/gas/aarch64: bfloat16.s
-Only in binutils-2.30.new/gas/testsuite/gas/aarch64: dgh.d
-Only in binutils-2.30.new/gas/testsuite/gas/aarch64: dgh.s
-diff -rup binutils-2.30/gas/testsuite/gas/aarch64/diagnostic.l binutils-2.30.new/gas/testsuite/gas/aarch64/diagnostic.l
---- binutils-2.30/gas/testsuite/gas/aarch64/diagnostic.l 2018-01-13 13:31:15.000000000 +0000
-+++ binutils-2.30.new/gas/testsuite/gas/aarch64/diagnostic.l 2021-03-23 16:19:56.754751921 +0000
-@@ -144,10 +144,6 @@
- [^:]*:256: Error: register element index out of range 0 to 15 at operand 1 -- `ld2 {v0\.b,v1\.b}\[-1\],\[x0\]'
- [^:]*:259: Error: register element index out of range 0 to 15 at operand 1 -- `ld2 {v0\.b,v1\.b}\[16\],\[x0\]'
- [^:]*:260: Error: register element index out of range 0 to 15 at operand 1 -- `ld2 {v0\.b,v1\.b}\[67\],\[x0\]'
--[^:]*:262: Error: invalid floating-point constant at operand 2 -- `fmov d0,#2'
--[^:]*:263: Error: invalid floating-point constant at operand 2 -- `fmov d0,#-2'
--[^:]*:264: Error: invalid floating-point constant at operand 2 -- `fmov s0,2'
--[^:]*:265: Error: invalid floating-point constant at operand 2 -- `fmov s0,-2'
- [^:]*:267: Error: integer 64-bit register expected at operand 2 -- `st2 {v0.4s,v1.4s},\[sp\],xzr'
- [^:]*:268: Error: integer or zero register expected at operand 2 -- `str x1,\[x2,sp\]'
- [^:]*:271: Error: relocation not allowed at operand 3 -- `ldnp x1,x2,\[x3,#:lo12:foo\]'
-Only in binutils-2.30.new/gas/testsuite/gas/aarch64: f32mm.d
-Only in binutils-2.30.new/gas/testsuite/gas/aarch64: f32mm.s
-Only in binutils-2.30.new/gas/testsuite/gas/aarch64: f64mm.d
-Only in binutils-2.30.new/gas/testsuite/gas/aarch64: f64mm.s
-Only in binutils-2.30.new/gas/testsuite/gas/aarch64: i8mm.d
-Only in binutils-2.30.new/gas/testsuite/gas/aarch64: i8mm.s
-Only in binutils-2.30.new/gas/testsuite/gas/aarch64: illegal-bfloat16.d
-Only in binutils-2.30.new/gas/testsuite/gas/aarch64: illegal-bfloat16.l
-Only in binutils-2.30.new/gas/testsuite/gas/aarch64: illegal-bfloat16.s
-diff -rup binutils-2.30/gas/testsuite/gas/aarch64/illegal-ldraa.l binutils-2.30.new/gas/testsuite/gas/aarch64/illegal-ldraa.l
---- binutils-2.30/gas/testsuite/gas/aarch64/illegal-ldraa.l 2018-01-13 13:31:15.000000000 +0000
-+++ binutils-2.30.new/gas/testsuite/gas/aarch64/illegal-ldraa.l 2021-03-23 16:19:56.740752016 +0000
-@@ -6,7 +6,6 @@
- [^:]+:13: Error: immediate offset out of range -4096 to 4088 at operand 2 -- `ldraa x0,\[x1,#5555\]'
- [^:]+:14: Error: immediate offset out of range -4096 to 4088 at operand 2 -- `ldraa x0,\[x1,#-4104\]'
- [^:]+:15: Error: 64-bit integer or SP register expected at operand 2 -- `ldraa x0,\[xz\]'
--[^:]+:16: Error: missing offset in the pre-indexed address at operand 2 -- `ldraa x0,\[x1\]!'
- [^:]+:17: Error: invalid expression in the address at operand 2 -- `ldraa x0,\[sp\],'
- [^:]+:18: Error: immediate value must be a multiple of 8 at operand 2 -- `ldraa x0,\[x1,#1\]!'
- [^:]+:19: Error: immediate value must be a multiple of 8 at operand 2 -- `ldraa x0,\[x1,#4\]!'
-@@ -23,7 +22,6 @@
- [^:]+:32: Error: immediate offset out of range -4096 to 4088 at operand 2 -- `ldrab x0,\[x1,#5555\]'
- [^:]+:33: Error: immediate offset out of range -4096 to 4088 at operand 2 -- `ldrab x0,\[x1,#-4104\]'
- [^:]+:34: Error: 64-bit integer or SP register expected at operand 2 -- `ldrab x0,\[xz\]'
--[^:]+:35: Error: missing offset in the pre-indexed address at operand 2 -- `ldrab x0,\[x1\]!'
- [^:]+:36: Error: invalid expression in the address at operand 2 -- `ldrab x0,\[sp\],'
- [^:]+:37: Error: immediate value must be a multiple of 8 at operand 2 -- `ldrab x0,\[x1,#1\]!'
- [^:]+:38: Error: immediate value must be a multiple of 8 at operand 2 -- `ldrab x0,\[x1,#4\]!'
-diff -rup binutils-2.30/gas/testsuite/gas/aarch64/illegal-ras-1.d binutils-2.30.new/gas/testsuite/gas/aarch64/illegal-ras-1.d
---- binutils-2.30/gas/testsuite/gas/aarch64/illegal-ras-1.d 2018-01-13 13:31:15.000000000 +0000
-+++ binutils-2.30.new/gas/testsuite/gas/aarch64/illegal-ras-1.d 2021-03-23 16:19:56.774751785 +0000
-@@ -1,4 +1,6 @@
- #name: Illegal RAS instruction use.
- #source: illegal-ras-1.s
- #as: -march=armv8-a -mno-verbose-error
--#error-output: illegal-ras-1.l
-+#objdump: -d
-+
-+#pass
-diff -rup binutils-2.30/gas/testsuite/gas/aarch64/illegal-sysreg-2.d binutils-2.30.new/gas/testsuite/gas/aarch64/illegal-sysreg-2.d
---- binutils-2.30/gas/testsuite/gas/aarch64/illegal-sysreg-2.d 2018-01-13 13:31:15.000000000 +0000
-+++ binutils-2.30.new/gas/testsuite/gas/aarch64/illegal-sysreg-2.d 2021-03-23 16:19:56.748751962 +0000
-@@ -1,3 +1,4 @@
- #as: -march=armv8-a
- #source: sysreg-2.s
- #error-output: illegal-sysreg-2.l
-+#not-target: aarch*-*-*
-Only in binutils-2.30.new/gas/testsuite/gas/aarch64: ls64.d
-Only in binutils-2.30.new/gas/testsuite/gas/aarch64: ls64.s
-diff -rup binutils-2.30/gas/testsuite/gas/aarch64/pr19721.d binutils-2.30.new/gas/testsuite/gas/aarch64/pr19721.d
---- binutils-2.30/gas/testsuite/gas/aarch64/pr19721.d 2018-01-13 13:31:15.000000000 +0000
-+++ binutils-2.30.new/gas/testsuite/gas/aarch64/pr19721.d 2021-03-23 16:19:56.771751806 +0000
-@@ -6,5 +6,5 @@ Disassembly of section \.text:
-
- 0+000 <.*>:
- 0: aa1103e7 mov x7, x17
-- 4: aa1167e7 mov x7, x17, lsl #25
-- 8: aa1167e7 mov x7, x17, lsl #25
-+ 4: aa1167e7 orr x7, xzr, x17, lsl #25
-+ 8: aa1167e7 orr x7, xzr, x17, lsl #25
-Only in binutils-2.30.new/gas/testsuite/gas/aarch64: sve-bfloat-movprfx.d
-Only in binutils-2.30.new/gas/testsuite/gas/aarch64: sve-bfloat-movprfx.s
-diff -rup binutils-2.30/gas/testsuite/gas/aarch64/sve-invalid.d binutils-2.30.new/gas/testsuite/gas/aarch64/sve-invalid.d
---- binutils-2.30/gas/testsuite/gas/aarch64/sve-invalid.d 2018-01-13 13:31:15.000000000 +0000
-+++ binutils-2.30.new/gas/testsuite/gas/aarch64/sve-invalid.d 2021-03-23 16:19:56.745751982 +0000
-@@ -2,3 +2,4 @@
- #as: -march=armv8-a+sve
- #source: sve-invalid.s
- #error-output: sve-invalid.l
-+#not-target: aarch*-*-*
-diff -rup binutils-2.30/gas/testsuite/gas/aarch64/sve-invalid.l binutils-2.30.new/gas/testsuite/gas/aarch64/sve-invalid.l
---- binutils-2.30/gas/testsuite/gas/aarch64/sve-invalid.l 2018-01-13 13:31:15.000000000 +0000
-+++ binutils-2.30.new/gas/testsuite/gas/aarch64/sve-invalid.l 2021-03-23 16:19:56.756751908 +0000
-@@ -820,391 +820,3 @@
- .*: Error: immediate out of range at operand 3 -- `bic z0\.d,z0\.d,#0xd'
- .*: Error: immediate zero expected at operand 4 -- `fcmeq p0\.s,p1/z,z2\.s,#1'
- .*: Error: immediate zero expected at operand 4 -- `fcmeq p0\.s,p1/z,z2\.s,#1\.0'
--.*: Error: invalid floating-point constant at operand 4 -- `fadd z0\.s,p1/m,z0\.s,#0'
--.*: Error: floating-point value must be 0\.5 or 1\.0 at operand 4 -- `fadd z0\.s,p1/m,z0\.s,#0\.0'
--.*: Error: invalid floating-point constant at operand 4 -- `fadd z0\.s,p1/m,z0\.s,#1'
--.*: Error: floating-point value must be 0\.5 or 1\.0 at operand 4 -- `fadd z0\.s,p1/m,z0\.s,#1\.5'
--.*: Error: invalid floating-point constant at operand 4 -- `fadd z0\.s,p1/m,z0\.s,#2'
--.*: Error: floating-point value must be 0\.5 or 1\.0 at operand 4 -- `fadd z0\.s,p1/m,z0\.s,#2\.0'
--.*: Error: invalid floating-point constant at operand 4 -- `fmul z0\.s,p1/m,z0\.s,#0'
--.*: Error: floating-point value must be 0\.5 or 2\.0 at operand 4 -- `fmul z0\.s,p1/m,z0\.s,#0\.0'
--.*: Error: invalid floating-point constant at operand 4 -- `fmul z0\.s,p1/m,z0\.s,#1'
--.*: Error: floating-point value must be 0\.5 or 2\.0 at operand 4 -- `fmul z0\.s,p1/m,z0\.s,#1\.0'
--.*: Error: floating-point value must be 0\.5 or 2\.0 at operand 4 -- `fmul z0\.s,p1/m,z0\.s,#1\.5'
--.*: Error: invalid floating-point constant at operand 4 -- `fmul z0\.s,p1/m,z0\.s,#2'
--.*: Error: invalid floating-point constant at operand 4 -- `fmax z0\.s,p1/m,z0\.s,#0'
--.*: Error: floating-point value must be 0\.0 or 1\.0 at operand 4 -- `fmax z0\.s,p1/m,z0\.s,#0\.5'
--.*: Error: invalid floating-point constant at operand 4 -- `fmax z0\.s,p1/m,z0\.s,#1'
--.*: Error: floating-point value must be 0\.0 or 1\.0 at operand 4 -- `fmax z0\.s,p1/m,z0\.s,#1\.5'
--.*: Error: invalid floating-point constant at operand 4 -- `fmax z0\.s,p1/m,z0\.s,#2'
--.*: Error: floating-point value must be 0\.0 or 1\.0 at operand 4 -- `fmax z0\.s,p1/m,z0\.s,#2\.0'
--.*: Error: operand 2 must be an enumeration value such as POW2 -- `ptrue p1\.b,vl0'
--.*: Error: operand 2 must be an enumeration value such as POW2 -- `ptrue p1\.b,vl255'
--.*: Error: operand 2 must be an enumeration value such as POW2 -- `ptrue p1\.b,#-1'
--.*: Error: operand 2 must be an enumeration value such as POW2 -- `ptrue p1\.b,#32'
--.*: Error: immediate operand required at operand 2 -- `ptrue p1\.b,x0'
--.*: Error: immediate operand required at operand 2 -- `ptrue p1\.b,z0\.s'
--.*: Error: operand 2 must be an enumeration value such as POW2 -- `cntb x0,vl0'
--.*: Error: operand 2 must be an enumeration value such as POW2 -- `cntb x0,vl255'
--.*: Error: operand 2 must be an enumeration value such as POW2 -- `cntb x0,#-1'
--.*: Error: operand 2 must be an enumeration value such as POW2 -- `cntb x0,#32'
--.*: Error: immediate operand required at operand 2 -- `cntb x0,x0'
--.*: Error: immediate operand required at operand 2 -- `cntb x0,z0\.s'
--.*: Error: operand 2 must be an enumeration value such as POW2 -- `cntb x0,mul#1'
--.*: Error: multiplier out of range 1 to 16 at operand 2 -- `cntb x0,pow2,mul#0'
--.*: Error: multiplier out of range 1 to 16 at operand 2 -- `cntb x0,pow2,mul#17'
--.*: Error: shift expression expected at operand 2 -- `cntb x0,pow2,#1'
--.*: Error: operand 1 must be an enumeration value such as PLDL1KEEP -- `prfb pldl0keep,p1,\[x0\]'
--.*: Error: operand 1 must be an enumeration value such as PLDL1KEEP -- `prfb pldl4keep,p1,\[x0\]'
--.*: Error: operand 1 must be an enumeration value such as PLDL1KEEP -- `prfb #-1,p1,\[x0\]'
--.*: Error: operand 1 must be an enumeration value such as PLDL1KEEP -- `prfb #16,p1,\[x0\]'
--.*: Error: immediate operand required at operand 1 -- `prfb x0,p1,\[x0\]'
--.*: Error: immediate operand required at operand 1 -- `prfb z0\.s,p1,\[x0\]'
--.*: Error: immediate value out of range 0 to 7 at operand 3 -- `lsl z0\.b,z0\.b,#-1'
--.*: Error: immediate value out of range 0 to 7 at operand 3 -- `lsl z0\.b,z0\.b,#8'
--.*: Error: immediate value out of range 0 to 7 at operand 3 -- `lsl z0\.b,z0\.b,#9'
--.*: Error: operand 3 must be an SVE vector register -- `lsl z0\.b,z0\.b,x0'
--.*: Error: immediate value out of range 0 to 15 at operand 3 -- `lsl z0\.h,z0\.h,#-1'
--.*: Error: immediate value out of range 0 to 15 at operand 3 -- `lsl z0\.h,z0\.h,#16'
--.*: Error: immediate value out of range 0 to 15 at operand 3 -- `lsl z0\.h,z0\.h,#17'
--.*: Error: immediate value out of range 0 to 31 at operand 3 -- `lsl z0\.s,z0\.s,#-1'
--.*: Error: immediate value out of range 0 to 31 at operand 3 -- `lsl z0\.s,z0\.s,#32'
--.*: Error: immediate value out of range 0 to 31 at operand 3 -- `lsl z0\.s,z0\.s,#33'
--.*: Error: immediate value out of range 0 to 63 at operand 3 -- `lsl z0\.d,z0\.d,#-1'
--.*: Error: immediate value out of range 0 to 63 at operand 3 -- `lsl z0\.d,z0\.d,#64'
--.*: Error: immediate value out of range 0 to 63 at operand 3 -- `lsl z0\.d,z0\.d,#65'
--.*: Error: immediate value out of range 0 to 7 at operand 4 -- `lsl z0\.b,p1/m,z0\.b,#-1'
--.*: Error: immediate value out of range 0 to 7 at operand 4 -- `lsl z0\.b,p1/m,z0\.b,#8'
--.*: Error: immediate value out of range 0 to 7 at operand 4 -- `lsl z0\.b,p1/m,z0\.b,#9'
--.*: Error: operand 4 must be an SVE vector register -- `lsl z0\.b,p1/m,z0\.b,x0'
--.*: Error: immediate value out of range 0 to 15 at operand 4 -- `lsl z0\.h,p1/m,z0\.h,#-1'
--.*: Error: immediate value out of range 0 to 15 at operand 4 -- `lsl z0\.h,p1/m,z0\.h,#16'
--.*: Error: immediate value out of range 0 to 15 at operand 4 -- `lsl z0\.h,p1/m,z0\.h,#17'
--.*: Error: immediate value out of range 0 to 31 at operand 4 -- `lsl z0\.s,p1/m,z0\.s,#-1'
--.*: Error: immediate value out of range 0 to 31 at operand 4 -- `lsl z0\.s,p1/m,z0\.s,#32'
--.*: Error: immediate value out of range 0 to 31 at operand 4 -- `lsl z0\.s,p1/m,z0\.s,#33'
--.*: Error: immediate value out of range 0 to 63 at operand 4 -- `lsl z0\.d,p1/m,z0\.d,#-1'
--.*: Error: immediate value out of range 0 to 63 at operand 4 -- `lsl z0\.d,p1/m,z0\.d,#64'
--.*: Error: immediate value out of range 0 to 63 at operand 4 -- `lsl z0\.d,p1/m,z0\.d,#65'
--.*: Error: immediate value out of range 1 to 8 at operand 3 -- `lsr z0\.b,z0\.b,#-1'
--.*: Error: immediate value out of range 1 to 8 at operand 3 -- `lsr z0\.b,z0\.b,#0'
--.*: Error: immediate value out of range 1 to 8 at operand 3 -- `lsr z0\.b,z0\.b,#9'
--.*: Error: operand 3 must be an SVE vector register -- `lsr z0\.b,z0\.b,x0'
--.*: Error: immediate value out of range 1 to 16 at operand 3 -- `lsr z0\.h,z0\.h,#-1'
--.*: Error: immediate value out of range 1 to 16 at operand 3 -- `lsr z0\.h,z0\.h,#0'
--.*: Error: immediate value out of range 1 to 16 at operand 3 -- `lsr z0\.h,z0\.h,#17'
--.*: Error: immediate value out of range 1 to 32 at operand 3 -- `lsr z0\.s,z0\.s,#-1'
--.*: Error: immediate value out of range 1 to 32 at operand 3 -- `lsr z0\.s,z0\.s,#0'
--.*: Error: immediate value out of range 1 to 32 at operand 3 -- `lsr z0\.s,z0\.s,#33'
--.*: Error: immediate value out of range 1 to 64 at operand 3 -- `lsr z0\.d,z0\.d,#-1'
--.*: Error: immediate value out of range 1 to 64 at operand 3 -- `lsr z0\.d,z0\.d,#0'
--.*: Error: immediate value out of range 1 to 64 at operand 3 -- `lsr z0\.d,z0\.d,#65'
--.*: Error: immediate value out of range 1 to 8 at operand 4 -- `lsr z0\.b,p1/m,z0\.b,#-1'
--.*: Error: immediate value out of range 1 to 8 at operand 4 -- `lsr z0\.b,p1/m,z0\.b,#0'
--.*: Error: immediate value out of range 1 to 8 at operand 4 -- `lsr z0\.b,p1/m,z0\.b,#9'
--.*: Error: operand 4 must be an SVE vector register -- `lsr z0\.b,p1/m,z0\.b,x0'
--.*: Error: immediate value out of range 1 to 16 at operand 4 -- `lsr z0\.h,p1/m,z0\.h,#-1'
--.*: Error: immediate value out of range 1 to 16 at operand 4 -- `lsr z0\.h,p1/m,z0\.h,#0'
--.*: Error: immediate value out of range 1 to 16 at operand 4 -- `lsr z0\.h,p1/m,z0\.h,#17'
--.*: Error: immediate value out of range 1 to 32 at operand 4 -- `lsr z0\.s,p1/m,z0\.s,#-1'
--.*: Error: immediate value out of range 1 to 32 at operand 4 -- `lsr z0\.s,p1/m,z0\.s,#0'
--.*: Error: immediate value out of range 1 to 32 at operand 4 -- `lsr z0\.s,p1/m,z0\.s,#33'
--.*: Error: immediate value out of range 1 to 64 at operand 4 -- `lsr z0\.d,p1/m,z0\.d,#-1'
--.*: Error: immediate value out of range 1 to 64 at operand 4 -- `lsr z0\.d,p1/m,z0\.d,#0'
--.*: Error: immediate value out of range 1 to 64 at operand 4 -- `lsr z0\.d,p1/m,z0\.d,#65'
--.*: Error: immediate value out of range -16 to 15 at operand 2 -- `index z0\.s,#-17,#1'
--.*: Error: immediate value out of range -16 to 15 at operand 2 -- `index z0\.s,#16,#1'
--.*: Error: immediate value out of range -16 to 15 at operand 3 -- `index z0\.s,#0,#-17'
--.*: Error: immediate value out of range -16 to 15 at operand 3 -- `index z0\.s,#0,#16'
--.*: Error: immediate value out of range -32 to 31 at operand 3 -- `addpl x0,sp,#-33'
--.*: Error: immediate value out of range -32 to 31 at operand 3 -- `addpl sp,x0,#32'
--.*: Error: operand 2 must be an integer register or SP -- `addpl x0,xzr,#1'
--.*: Error: operand 1 must be an integer or stack pointer register -- `addpl xzr,x0,#1'
--.*: Error: immediate value out of range -128 to 127 at operand 3 -- `mul z0\.b,z0\.b,#-129'
--.*: Error: immediate value out of range -128 to 127 at operand 3 -- `mul z0\.b,z0\.b,#128'
--.*: Error: immediate value out of range -128 to 127 at operand 3 -- `mul z0\.s,z0\.s,#-129'
--.*: Error: immediate value out of range -128 to 127 at operand 3 -- `mul z0\.s,z0\.s,#128'
--.*: Error: immediate value out of range 0 to 7 at operand 4 -- `ftmad z0\.s,z0\.s,z1\.s,#-1'
--.*: Error: immediate value out of range 0 to 7 at operand 4 -- `ftmad z0\.s,z0\.s,z1\.s,#8'
--.*: Error: immediate operand required at operand 4 -- `ftmad z0\.s,z0\.s,z1\.s,z2\.s'
--.*: Error: immediate value out of range 0 to 127 at operand 4 -- `cmphi p0\.s,p1/z,z2\.s,#-1'
--.*: Error: immediate value out of range 0 to 127 at operand 4 -- `cmphi p0\.s,p1/z,z2\.s,#128'
--.*: Error: immediate value out of range 0 to 255 at operand 3 -- `umax z0\.s,z0\.s,#-1'
--.*: Error: immediate value out of range 0 to 255 at operand 3 -- `umax z0\.s,z0\.s,#256'
--.*: Error: immediate value out of range 0 to 255 at operand 4 -- `ext z0\.b,z0\.b,z1\.b,#-1'
--.*: Error: immediate value out of range 0 to 255 at operand 4 -- `ext z0\.b,z0\.b,z1\.b,#256'
--.*: Error: register element index out of range 0 to 63 at operand 2 -- `dup z0\.b,z1\.b\[-1\]'
--.*: Error: register element index out of range 0 to 63 at operand 2 -- `dup z0\.b,z1\.b\[64\]'
--.*: Error: constant expression required at operand 2 -- `dup z0\.b,z1\.b\[x0\]'
--.*: Error: register element index out of range 0 to 31 at operand 2 -- `dup z0\.h,z1\.h\[-1\]'
--.*: Error: register element index out of range 0 to 31 at operand 2 -- `dup z0\.h,z1\.h\[32\]'
--.*: Error: constant expression required at operand 2 -- `dup z0\.h,z1\.h\[x0\]'
--.*: Error: register element index out of range 0 to 15 at operand 2 -- `dup z0\.s,z1\.s\[-1\]'
--.*: Error: register element index out of range 0 to 15 at operand 2 -- `dup z0\.s,z1\.s\[16\]'
--.*: Error: constant expression required at operand 2 -- `dup z0\.s,z1\.s\[x0\]'
--.*: Error: register element index out of range 0 to 7 at operand 2 -- `dup z0\.d,z1\.d\[-1\]'
--.*: Error: register element index out of range 0 to 7 at operand 2 -- `dup z0\.d,z1\.d\[8\]'
--.*: Error: constant expression required at operand 2 -- `dup z0\.d,z1\.d\[x0\]'
--.*: Error: operand mismatch -- `fabd z0\.b,p0/m,z0\.b,z0\.b'
--.*: Info: did you mean this\?
--.*: Info: fabd z0\.h, p0/m, z0\.h, z0\.h
--.*: Info: other valid variant\(s\):
--.*: Info: fabd z0\.s, p0/m, z0\.s, z0\.s
--.*: Info: fabd z0\.d, p0/m, z0\.d, z0\.d
--.*: Error: operand mismatch -- `fabd z0\.q,p0/m,z0\.q,z0\.q'
--.*: Info: did you mean this\?
--.*: Info: fabd z0\.h, p0/m, z0\.h, z0\.h
--.*: Info: other valid variant\(s\):
--.*: Info: fabd z0\.s, p0/m, z0\.s, z0\.s
--.*: Info: fabd z0\.d, p0/m, z0\.d, z0\.d
--.*: Error: operand mismatch -- `fcadd z0\.b,p0/m,z0\.b,z0\.b,#90'
--.*: Info: did you mean this\?
--.*: Info: fcadd z0\.h, p0/m, z0\.h, z0\.h, #90
--.*: Info: other valid variant\(s\):
--.*: Info: fcadd z0\.s, p0/m, z0\.s, z0\.s, #90
--.*: Info: fcadd z0\.d, p0/m, z0\.d, z0\.d, #90
--.*: Error: rotate expected to be 90 or 270 at operand 5 -- `fcadd z0\.h,p0/m,z0\.h,z0\.h,#-180'
--.*: Error: rotate expected to be 90 or 270 at operand 5 -- `fcadd z0\.h,p0/m,z0\.h,z0\.h,#-90'
--.*: Error: rotate expected to be 90 or 270 at operand 5 -- `fcadd z0\.h,p0/m,z0\.h,z0\.h,#0'
--.*: Error: rotate expected to be 90 or 270 at operand 5 -- `fcadd z0\.h,p0/m,z0\.h,z0\.h,#89'
--.*: Error: unexpected characters following instruction at operand 5 -- `fcadd z0\.h,p0/m,z0\.h,z0\.h,#90\.0'
--.*: Error: rotate expected to be 90 or 270 at operand 5 -- `fcadd z0\.h,p0/m,z0\.h,z0\.h,#180'
--.*: Error: rotate expected to be 90 or 270 at operand 5 -- `fcadd z0\.h,p0/m,z0\.h,z0\.h,#360'
--.*: Error: rotate expected to be 90 or 270 at operand 5 -- `fcadd z0\.h,p0/m,z0\.h,z0\.h,#450'
--.*: Error: operand mismatch -- `fcadd z0\.h,p0/z,z0\.h,z0\.h,#90'
--.*: Info: did you mean this\?
--.*: Info: fcadd z0\.h, p0/m, z0\.h, z0\.h, #90
--.*: Info: other valid variant\(s\):
--.*: Info: fcadd z0\.s, p0/m, z0\.s, z0\.s, #90
--.*: Info: fcadd z0\.d, p0/m, z0\.d, z0\.d, #90
--.*: Error: operand 3 must be the same register as operand 1 -- `fcadd z0\.h,p0/m,z1\.h,z0\.h,#90'
--.*: Error: operand mismatch -- `fcadd z0\.q,p0/m,z0\.q,z0\.q,#90'
--.*: Info: did you mean this\?
--.*: Info: fcadd z0\.h, p0/m, z0\.h, z0\.h, #90
--.*: Info: other valid variant\(s\):
--.*: Info: fcadd z0\.s, p0/m, z0\.s, z0\.s, #90
--.*: Info: fcadd z0\.d, p0/m, z0\.d, z0\.d, #90
--.*: Error: operand mismatch -- `fcmla z0\.b,p0/m,z0\.b,z0\.b,#90'
--.*: Info: did you mean this\?
--.*: Info: fcmla z0\.h, p0/m, z0\.h, z0\.h, #90
--.*: Info: other valid variant\(s\):
--.*: Info: fcmla z0\.s, p0/m, z0\.s, z0\.s, #90
--.*: Info: fcmla z0\.d, p0/m, z0\.d, z0\.d, #90
--.*: Error: rotate expected to be 0, 90, 180 or 270 at operand 5 -- `fcmla z0\.h,p0/m,z0\.h,z0\.h,#-180'
--.*: Error: rotate expected to be 0, 90, 180 or 270 at operand 5 -- `fcmla z0\.h,p0/m,z0\.h,z0\.h,#-90'
--.*: Error: rotate expected to be 0, 90, 180 or 270 at operand 5 -- `fcmla z0\.h,p0/m,z0\.h,z0\.h,#89'
--.*: Error: unexpected characters following instruction at operand 5 -- `fcmla z0\.h,p0/m,z0\.h,z0\.h,#90\.0'
--.*: Error: rotate expected to be 0, 90, 180 or 270 at operand 5 -- `fcmla z0\.h,p0/m,z0\.h,z0\.h,#360'
--.*: Error: rotate expected to be 0, 90, 180 or 270 at operand 5 -- `fcmla z0\.h,p0/m,z0\.h,z0\.h,#450'
--.*: Error: operand mismatch -- `fcmla z0\.h,p0/z,z0\.h,z0\.h,#90'
--.*: Info: did you mean this\?
--.*: Info: fcmla z0\.h, p0/m, z0\.h, z0\.h, #90
--.*: Info: other valid variant\(s\):
--.*: Info: fcmla z0\.s, p0/m, z0\.s, z0\.s, #90
--.*: Info: fcmla z0\.d, p0/m, z0\.d, z0\.d, #90
--.*: Error: operand mismatch -- `fcmla z0\.q,p0/m,z0\.q,z0\.q,#90'
--.*: Info: did you mean this\?
--.*: Info: fcmla z0\.h, p0/m, z0\.h, z0\.h, #90
--.*: Info: other valid variant\(s\):
--.*: Info: fcmla z0\.s, p0/m, z0\.s, z0\.s, #90
--.*: Info: fcmla z0\.d, p0/m, z0\.d, z0\.d, #90
--.*: Error: operand mismatch -- `fcmla z0\.b,z1\.b,z2\.b\[0\],#0'
--.*: Info: did you mean this\?
--.*: Info: fcmla z0\.h, z1\.h, z2\.h\[0\], #0
--.*: Error: register element index out of range 0 to 3 at operand 3 -- `fcmla z0\.h,z1\.h,z2\.h\[-1\],#0'
--.*: Error: register element index out of range 0 to 3 at operand 3 -- `fcmla z0\.h,z1\.h,z2\.h\[4\],#0'
--.*: Error: z0-z7 expected at operand 3 -- `fcmla z0\.h,z1\.h,z8\.h\[0\],#0'
--.*: Error: rotate expected to be 0, 90, 180 or 270 at operand 4 -- `fcmla z0\.h,z1\.h,z2\.h\[0\],#-180'
--.*: Error: rotate expected to be 0, 90, 180 or 270 at operand 4 -- `fcmla z0\.h,z1\.h,z2\.h\[0\],#-90'
--.*: Error: rotate expected to be 0, 90, 180 or 270 at operand 4 -- `fcmla z0\.h,z1\.h,z2\.h\[0\],#89'
--.*: Error: unexpected characters following instruction at operand 4 -- `fcmla z0\.h,z1\.h,z2\.h\[0\],#90\.0'
--.*: Error: rotate expected to be 0, 90, 180 or 270 at operand 4 -- `fcmla z0\.h,z1\.h,z2\.h\[0\],#360'
--.*: Error: rotate expected to be 0, 90, 180 or 270 at operand 4 -- `fcmla z0\.h,z1\.h,z2\.h\[0\],#450'
--.*: Error: register element index out of range 0 to 1 at operand 3 -- `fcmla z0\.s,z1\.s,z2\.s\[-1\],#0'
--.*: Error: register element index out of range 0 to 1 at operand 3 -- `fcmla z0\.s,z1\.s,z2\.s\[2\],#0'
--.*: Error: z0-z15 expected at operand 3 -- `fcmla z0\.s,z1\.s,z16\.s\[0\],#0'
--.*: Error: rotate expected to be 0, 90, 180 or 270 at operand 4 -- `fcmla z0\.s,z1\.s,z2\.s\[0\],#-180'
--.*: Error: rotate expected to be 0, 90, 180 or 270 at operand 4 -- `fcmla z0\.s,z1\.s,z2\.s\[0\],#-90'
--.*: Error: rotate expected to be 0, 90, 180 or 270 at operand 4 -- `fcmla z0\.s,z1\.s,z2\.s\[0\],#89'
--.*: Error: unexpected characters following instruction at operand 4 -- `fcmla z0\.s,z1\.s,z2\.s\[0\],#90\.0'
--.*: Error: rotate expected to be 0, 90, 180 or 270 at operand 4 -- `fcmla z0\.s,z1\.s,z2\.s\[0\],#360'
--.*: Error: rotate expected to be 0, 90, 180 or 270 at operand 4 -- `fcmla z0\.s,z1\.s,z2\.s\[0\],#450'
--.*: Error: operand mismatch -- `fcmla z0\.q,z1\.q,z2\.q\[0\],#0'
--.*: Info: did you mean this\?
--.*: Info: fcmla z0\.h, z1\.h, z2\.h\[0\], #0
--.*: Error: operand mismatch -- `fmla z0\.b,z1\.b,z2\.b\[0\]'
--.*: Info: did you mean this\?
--.*: Info: fmla z0\.h, z1\.h, z2\.h\[0\]
--.*: Error: register element index out of range 0 to 7 at operand 3 -- `fmla z0\.h,z1\.h,z2\.h\[-1\]'
--.*: Error: register element index out of range 0 to 7 at operand 3 -- `fmla z0\.h,z1\.h,z2\.h\[8\]'
--.*: Error: z0-z7 expected at operand 3 -- `fmla z0\.h,z1\.h,z8\.h\[0\]'
--.*: Error: register element index out of range 0 to 3 at operand 3 -- `fmla z0\.s,z1\.s,z2\.s\[-1\]'
--.*: Error: register element index out of range 0 to 3 at operand 3 -- `fmla z0\.s,z1\.s,z2\.s\[4\]'
--.*: Error: z0-z7 expected at operand 3 -- `fmla z0\.s,z1\.s,z8\.s\[0\]'
--.*: Error: register element index out of range 0 to 1 at operand 3 -- `fmla z0\.d,z1\.d,z2\.d\[-1\]'
--.*: Error: register element index out of range 0 to 1 at operand 3 -- `fmla z0\.d,z1\.d,z2\.d\[2\]'
--.*: Error: z0-z15 expected at operand 3 -- `fmla z0\.d,z1\.d,z16\.d\[0\]'
--.*: Error: operand mismatch -- `fmla z0\.q,z1\.q,z2\.q\[0\]'
--.*: Info: did you mean this\?
--.*: Info: fmla z0\.h, z1\.h, z2\.h\[0\]
--.*: Error: operand mismatch -- `fmls z0\.b,z1\.b,z2\.b\[0\]'
--.*: Info: did you mean this\?
--.*: Info: fmls z0\.h, z1\.h, z2\.h\[0\]
--.*: Error: register element index out of range 0 to 7 at operand 3 -- `fmls z0\.h,z1\.h,z2\.h\[-1\]'
--.*: Error: register element index out of range 0 to 7 at operand 3 -- `fmls z0\.h,z1\.h,z2\.h\[8\]'
--.*: Error: z0-z7 expected at operand 3 -- `fmls z0\.h,z1\.h,z8\.h\[0\]'
--.*: Error: register element index out of range 0 to 3 at operand 3 -- `fmls z0\.s,z1\.s,z2\.s\[-1\]'
--.*: Error: register element index out of range 0 to 3 at operand 3 -- `fmls z0\.s,z1\.s,z2\.s\[4\]'
--.*: Error: z0-z7 expected at operand 3 -- `fmls z0\.s,z1\.s,z8\.s\[0\]'
--.*: Error: register element index out of range 0 to 1 at operand 3 -- `fmls z0\.d,z1\.d,z2\.d\[-1\]'
--.*: Error: register element index out of range 0 to 1 at operand 3 -- `fmls z0\.d,z1\.d,z2\.d\[2\]'
--.*: Error: z0-z15 expected at operand 3 -- `fmls z0\.d,z1\.d,z16\.d\[0\]'
--.*: Error: operand mismatch -- `fmls z0\.q,z1\.q,z2\.q\[0\]'
--.*: Info: did you mean this\?
--.*: Info: fmls z0\.h, z1\.h, z2\.h\[0\]
--.*: Error: operand mismatch -- `fmul z0\.b,z1\.b,z2\.b\[0\]'
--.*: Info: did you mean this\?
--.*: Info: fmul z0\.h, z1\.h, z2\.h\[0\]
--.*: Error: register element index out of range 0 to 7 at operand 3 -- `fmul z0\.h,z1\.h,z2\.h\[-1\]'
--.*: Error: register element index out of range 0 to 7 at operand 3 -- `fmul z0\.h,z1\.h,z2\.h\[8\]'
--.*: Error: z0-z7 expected at operand 3 -- `fmul z0\.h,z1\.h,z8\.h\[0\]'
--.*: Error: register element index out of range 0 to 3 at operand 3 -- `fmul z0\.s,z1\.s,z2\.s\[-1\]'
--.*: Error: register element index out of range 0 to 3 at operand 3 -- `fmul z0\.s,z1\.s,z2\.s\[4\]'
--.*: Error: z0-z7 expected at operand 3 -- `fmul z0\.s,z1\.s,z8\.s\[0\]'
--.*: Error: register element index out of range 0 to 1 at operand 3 -- `fmul z0\.d,z1\.d,z2\.d\[-1\]'
--.*: Error: register element index out of range 0 to 1 at operand 3 -- `fmul z0\.d,z1\.d,z2\.d\[2\]'
--.*: Error: z0-z15 expected at operand 3 -- `fmul z0\.d,z1\.d,z16\.d\[0\]'
--.*: Error: operand mismatch -- `fmul z0\.q,z1\.q,z2\.q\[0\]'
--.*: Info: did you mean this\?
--.*: Info: fmul z0\.h, z1\.h, z2\.h\[0\]
--.*: Error: operand mismatch -- `ld1rqb {z0\.b},p0,\[x0,#0\]'
--.*: Info: did you mean this\?
--.*: Info: ld1rqb {z0\.b}, p0/z, \[x0\]
--.*: Error: operand mismatch -- `ld1rqb {z0\.b},p0/m,\[x0,#0\]'
--.*: Info: did you mean this\?
--.*: Info: ld1rqb {z0\.b}, p0/z, \[x0\]
--.*: Error: p0-p7 expected at operand 2 -- `ld1rqb {z0\.b},p8/z,\[x0,#0\]'
--.*: Error: immediate offset out of range -128 to 112 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#-144\]'
--.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#-15\]'
--.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#-14\]'
--.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#-13\]'
--.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#-12\]'
--.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#-11\]'
--.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#-10\]'
--.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#-9\]'
--.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#-8\]'
--.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#-7\]'
--.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#-6\]'
--.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#-5\]'
--.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#-4\]'
--.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#-3\]'
--.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#-2\]'
--.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#-1\]'
--.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#1\]'
--.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#2\]'
--.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#3\]'
--.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#4\]'
--.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#5\]'
--.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#6\]'
--.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#7\]'
--.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#8\]'
--.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#9\]'
--.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#10\]'
--.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#11\]'
--.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#12\]'
--.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#13\]'
--.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#14\]'
--.*: Error: immediate value must be a multiple of 16 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#15\]'
--.*: Error: immediate offset out of range -128 to 112 at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,#128\]'
--.*: Error: operand mismatch -- `ld1rqb {z0\.h},p0/z,\[x0,#0\]'
--.*: Info: did you mean this\?
--.*: Info: ld1rqb {z0\.b}, p0/z, \[x0\]
--.*: Error: operand mismatch -- `ld1rqb {z0\.s},p0/z,\[x0,#0\]'
--.*: Info: did you mean this\?
--.*: Info: ld1rqb {z0\.b}, p0/z, \[x0\]
--.*: Error: operand mismatch -- `ld1rqb {z0\.d},p0/z,\[x0,#0\]'
--.*: Info: did you mean this\?
--.*: Info: ld1rqb {z0\.b}, p0/z, \[x0\]
--.*: Error: operand mismatch -- `ld1rqb {z0\.q},p0/z,\[x0,#0\]'
--.*: Info: did you mean this\?
--.*: Info: ld1rqb {z0\.b}, p0/z, \[x0\]
--.*: Error: index register xzr is not allowed at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,xzr\]'
--.*: Error: invalid addressing mode at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,x1,lsl#1\]'
--.*: Error: invalid addressing mode at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,x1,lsl#2\]'
--.*: Error: invalid addressing mode at operand 3 -- `ld1rqb {z0\.b},p0/z,\[x0,x1,lsl#3\]'
--.*: Error: index register xzr is not allowed at operand 3 -- `ld1rqh {z0\.h},p0/z,\[x0,xzr,lsl#1\]'
--.*: Error: invalid addressing mode at operand 3 -- `ld1rqh {z0\.h},p0/z,\[x0,x1\]'
--.*: Error: invalid addressing mode at operand 3 -- `ld1rqh {z0\.h},p0/z,\[x0,x1,lsl#2\]'
--.*: Error: invalid addressing mode at operand 3 -- `ld1rqh {z0\.h},p0/z,\[x0,x1,lsl#3\]'
--.*: Error: index register xzr is not allowed at operand 3 -- `ld1rqw {z0\.s},p0/z,\[x0,xzr,lsl#2\]'
--.*: Error: invalid addressing mode at operand 3 -- `ld1rqw {z0\.s},p0/z,\[x0,x1\]'
--.*: Error: invalid addressing mode at operand 3 -- `ld1rqw {z0\.s},p0/z,\[x0,x1,lsl#1\]'
--.*: Error: invalid addressing mode at operand 3 -- `ld1rqw {z0\.s},p0/z,\[x0,x1,lsl#3\]'
--.*: Error: index register xzr is not allowed at operand 3 -- `ld1rqd {z0\.d},p0/z,\[x0,xzr,lsl#3\]'
--.*: Error: invalid addressing mode at operand 3 -- `ld1rqd {z0\.d},p0/z,\[x0,x1\]'
--.*: Error: invalid addressing mode at operand 3 -- `ld1rqd {z0\.d},p0/z,\[x0,x1,lsl#1\]'
--.*: Error: invalid addressing mode at operand 3 -- `ld1rqd {z0\.d},p0/z,\[x0,x1,lsl#2\]'
--.*: Error: operand mismatch -- `sdot z0\.b,z1\.b,z2\.b'
--.*: Info: did you mean this\?
--.*: Info: sdot z0\.s, z1\.b, z2\.b
--.*: Info: other valid variant\(s\):
--.*: Info: sdot z0\.d, z1\.h, z2\.h
--.*: Error: operand mismatch -- `sdot z0\.h,z1\.h,z2\.h'
--.*: Info: did you mean this\?
--.*: Info: sdot z0\.d, z1\.h, z2\.h
--.*: Info: other valid variant\(s\):
--.*: Info: sdot z0\.s, z1\.b, z2\.b
--.*: Error: operand mismatch -- `sdot z0\.s,z1\.s,z2\.s'
--.*: Info: did you mean this\?
--.*: Info: sdot z0\.s, z1\.b, z2\.b
--.*: Info: other valid variant\(s\):
--.*: Info: sdot z0\.d, z1\.h, z2\.h
--.*: Error: operand mismatch -- `sdot z0\.d,z1\.d,z2\.d'
--.*: Info: did you mean this\?
--.*: Info: sdot z0\.d, z1\.h, z2\.h
--.*: Info: other valid variant\(s\):
--.*: Info: sdot z0\.s, z1\.b, z2\.b
--.*: Error: operand mismatch -- `sdot z0\.b,z1\.b,z2\.b\[0\]'
--.*: Info: did you mean this\?
--.*: Info: sdot z0\.s, z1\.b, z2\.b\[0\]
--.*: Error: operand mismatch -- `sdot z0\.h,z1\.h,z2\.h\[0\]'
--.*: Info: did you mean this\?
--.*: Info: sdot z0\.s, z1\.b, z2\.b\[0\]
--.*: Error: operand mismatch -- `sdot z0\.s,z1\.s,z2\.s\[0\]'
--.*: Info: did you mean this\?
--.*: Info: sdot z0\.s, z1\.b, z2\.b\[0\]
--.*: Error: operand mismatch -- `sdot z0\.d,z1\.d,z2\.d\[0\]'
--.*: Info: did you mean this\?
--.*: Info: sdot z0\.s, z1\.b, z2\.b\[0\]
--.*: Error: operand mismatch -- `udot z0\.b,z1\.b,z2\.b'
--.*: Info: did you mean this\?
--.*: Info: udot z0\.s, z1\.b, z2\.b
--.*: Info: other valid variant\(s\):
--.*: Info: udot z0\.d, z1\.h, z2\.h
--.*: Error: operand mismatch -- `udot z0\.h,z1\.h,z2\.h'
--.*: Info: did you mean this\?
--.*: Info: udot z0\.d, z1\.h, z2\.h
--.*: Info: other valid variant\(s\):
--.*: Info: udot z0\.s, z1\.b, z2\.b
--.*: Error: operand mismatch -- `udot z0\.s,z1\.s,z2\.s'
--.*: Info: did you mean this\?
--.*: Info: udot z0\.s, z1\.b, z2\.b
--.*: Info: other valid variant\(s\):
--.*: Info: udot z0\.d, z1\.h, z2\.h
--.*: Error: operand mismatch -- `udot z0\.d,z1\.d,z2\.d'
--.*: Info: did you mean this\?
--.*: Info: udot z0\.d, z1\.h, z2\.h
--.*: Info: other valid variant\(s\):
--.*: Info: udot z0\.s, z1\.b, z2\.b
--.*: Error: operand mismatch -- `udot z0\.b,z1\.b,z2\.b\[0\]'
--.*: Info: did you mean this\?
--.*: Info: udot z0\.s, z1\.b, z2\.b\[0\]
--.*: Error: operand mismatch -- `udot z0\.h,z1\.h,z2\.h\[0\]'
--.*: Info: did you mean this\?
--.*: Info: udot z0\.s, z1\.b, z2\.b\[0\]
--.*: Error: operand mismatch -- `udot z0\.s,z1\.s,z2\.s\[0\]'
--.*: Info: did you mean this\?
--.*: Info: udot z0\.s, z1\.b, z2\.b\[0\]
--.*: Error: operand mismatch -- `udot z0\.d,z1\.d,z2\.d\[0\]'
--.*: Info: did you mean this\?
--.*: Info: udot z0\.s, z1\.b, z2\.b\[0\]
-diff -rup binutils-2.30/gas/testsuite/gas/aarch64/sve-invalid.s binutils-2.30.new/gas/testsuite/gas/aarch64/sve-invalid.s
---- binutils-2.30/gas/testsuite/gas/aarch64/sve-invalid.s 2018-01-13 13:31:15.000000000 +0000
-+++ binutils-2.30.new/gas/testsuite/gas/aarch64/sve-invalid.s 2021-03-23 16:19:56.743751996 +0000
-@@ -908,419 +908,3 @@
-
- fcmeq p0.s, p1/z, z2.s, #0 // OK
- fcmeq p0.s, p1/z, z2.s, #0.0 // OK
-- fcmeq p0.s, p1/z, z2.s, #1
-- fcmeq p0.s, p1/z, z2.s, #1.0
--
-- fadd z0.s, p1/m, z0.s, #0
-- fadd z0.s, p1/m, z0.s, #0.0
-- fadd z0.s, p1/m, z0.s, #0.5 // OK
-- fadd z0.s, p1/m, z0.s, #1
-- fadd z0.s, p1/m, z0.s, #1.0 // OK
-- fadd z0.s, p1/m, z0.s, #1.5
-- fadd z0.s, p1/m, z0.s, #2
-- fadd z0.s, p1/m, z0.s, #2.0
--
-- fmul z0.s, p1/m, z0.s, #0
-- fmul z0.s, p1/m, z0.s, #0.0
-- fmul z0.s, p1/m, z0.s, #0.5 // OK
-- fmul z0.s, p1/m, z0.s, #1
-- fmul z0.s, p1/m, z0.s, #1.0
-- fmul z0.s, p1/m, z0.s, #1.5
-- fmul z0.s, p1/m, z0.s, #2
-- fmul z0.s, p1/m, z0.s, #2.0 // OK
--
-- fmax z0.s, p1/m, z0.s, #0
-- fmax z0.s, p1/m, z0.s, #0.0 // OK
-- fmax z0.s, p1/m, z0.s, #0.5
-- fmax z0.s, p1/m, z0.s, #1
-- fmax z0.s, p1/m, z0.s, #1.0 // OK
-- fmax z0.s, p1/m, z0.s, #1.5
-- fmax z0.s, p1/m, z0.s, #2
-- fmax z0.s, p1/m, z0.s, #2.0
--
-- ptrue p1.b, vl0
-- ptrue p1.b, vl255
-- ptrue p1.b, #-1
-- ptrue p1.b, #0 // OK
-- ptrue p1.b, #31 // OK
-- ptrue p1.b, #32
-- ptrue p1.b, x0
-- ptrue p1.b, z0.s
--
-- cntb x0, vl0
-- cntb x0, vl255
-- cntb x0, #-1
-- cntb x0, #0 // OK
-- cntb x0, #31 // OK
-- cntb x0, #32
-- cntb x0, x0
-- cntb x0, z0.s
-- cntb x0, mul #1
-- cntb x0, pow2, mul #0
-- cntb x0, pow2, mul #1 // OK
-- cntb x0, pow2, mul #16 // OK
-- cntb x0, pow2, mul #17
-- cntb x0, pow2, #1
--
-- prfb pldl0keep, p1, [x0]
-- prfb pldl1keep, p1, [x0] // OK
-- prfb pldl2keep, p1, [x0] // OK
-- prfb pldl3keep, p1, [x0] // OK
-- prfb pldl4keep, p1, [x0]
-- prfb #-1, p1, [x0]
-- prfb #0, p1, [x0] // OK
-- prfb #15, p1, [x0] // OK
-- prfb #16, p1, [x0]
-- prfb x0, p1, [x0]
-- prfb z0.s, p1, [x0]
--
-- lsl z0.b, z0.b, #-1
-- lsl z0.b, z0.b, #0 // OK
-- lsl z0.b, z0.b, #1 // OK
-- lsl z0.b, z0.b, #7 // OK
-- lsl z0.b, z0.b, #8
-- lsl z0.b, z0.b, #9
-- lsl z0.b, z0.b, x0
--
-- lsl z0.h, z0.h, #-1
-- lsl z0.h, z0.h, #0 // OK
-- lsl z0.h, z0.h, #1 // OK
-- lsl z0.h, z0.h, #15 // OK
-- lsl z0.h, z0.h, #16
-- lsl z0.h, z0.h, #17
--
-- lsl z0.s, z0.s, #-1
-- lsl z0.s, z0.s, #0 // OK
-- lsl z0.s, z0.s, #1 // OK
-- lsl z0.s, z0.s, #31 // OK
-- lsl z0.s, z0.s, #32
-- lsl z0.s, z0.s, #33
--
-- lsl z0.d, z0.d, #-1
-- lsl z0.d, z0.d, #0 // OK
-- lsl z0.d, z0.d, #1 // OK
-- lsl z0.d, z0.d, #63 // OK
-- lsl z0.d, z0.d, #64
-- lsl z0.d, z0.d, #65
--
-- lsl z0.b, p1/m, z0.b, #-1
-- lsl z0.b, p1/m, z0.b, #0 // OK
-- lsl z0.b, p1/m, z0.b, #1 // OK
-- lsl z0.b, p1/m, z0.b, #7 // OK
-- lsl z0.b, p1/m, z0.b, #8
-- lsl z0.b, p1/m, z0.b, #9
-- lsl z0.b, p1/m, z0.b, x0
--
-- lsl z0.h, p1/m, z0.h, #-1
-- lsl z0.h, p1/m, z0.h, #0 // OK
-- lsl z0.h, p1/m, z0.h, #1 // OK
-- lsl z0.h, p1/m, z0.h, #15 // OK
-- lsl z0.h, p1/m, z0.h, #16
-- lsl z0.h, p1/m, z0.h, #17
--
-- lsl z0.s, p1/m, z0.s, #-1
-- lsl z0.s, p1/m, z0.s, #0 // OK
-- lsl z0.s, p1/m, z0.s, #1 // OK
-- lsl z0.s, p1/m, z0.s, #31 // OK
-- lsl z0.s, p1/m, z0.s, #32
-- lsl z0.s, p1/m, z0.s, #33
--
-- lsl z0.d, p1/m, z0.d, #-1
-- lsl z0.d, p1/m, z0.d, #0 // OK
-- lsl z0.d, p1/m, z0.d, #1 // OK
-- lsl z0.d, p1/m, z0.d, #63 // OK
-- lsl z0.d, p1/m, z0.d, #64
-- lsl z0.d, p1/m, z0.d, #65
--
-- lsr z0.b, z0.b, #-1
-- lsr z0.b, z0.b, #0
-- lsr z0.b, z0.b, #1 // OK
-- lsr z0.b, z0.b, #7 // OK
-- lsr z0.b, z0.b, #8 // OK
-- lsr z0.b, z0.b, #9
-- lsr z0.b, z0.b, x0
--
-- lsr z0.h, z0.h, #-1
-- lsr z0.h, z0.h, #0
-- lsr z0.h, z0.h, #1 // OK
-- lsr z0.h, z0.h, #15 // OK
-- lsr z0.h, z0.h, #16 // OK
-- lsr z0.h, z0.h, #17
--
-- lsr z0.s, z0.s, #-1
-- lsr z0.s, z0.s, #0
-- lsr z0.s, z0.s, #1 // OK
-- lsr z0.s, z0.s, #31 // OK
-- lsr z0.s, z0.s, #32 // OK
-- lsr z0.s, z0.s, #33
--
-- lsr z0.d, z0.d, #-1
-- lsr z0.d, z0.d, #0
-- lsr z0.d, z0.d, #1 // OK
-- lsr z0.d, z0.d, #63 // OK
-- lsr z0.d, z0.d, #64 // OK
-- lsr z0.d, z0.d, #65
--
-- lsr z0.b, p1/m, z0.b, #-1
-- lsr z0.b, p1/m, z0.b, #0
-- lsr z0.b, p1/m, z0.b, #1 // OK
-- lsr z0.b, p1/m, z0.b, #7 // OK
-- lsr z0.b, p1/m, z0.b, #8 // OK
-- lsr z0.b, p1/m, z0.b, #9
-- lsr z0.b, p1/m, z0.b, x0
--
-- lsr z0.h, p1/m, z0.h, #-1
-- lsr z0.h, p1/m, z0.h, #0
-- lsr z0.h, p1/m, z0.h, #1 // OK
-- lsr z0.h, p1/m, z0.h, #15 // OK
-- lsr z0.h, p1/m, z0.h, #16 // OK
-- lsr z0.h, p1/m, z0.h, #17
--
-- lsr z0.s, p1/m, z0.s, #-1
-- lsr z0.s, p1/m, z0.s, #0
-- lsr z0.s, p1/m, z0.s, #1 // OK
-- lsr z0.s, p1/m, z0.s, #31 // OK
-- lsr z0.s, p1/m, z0.s, #32 // OK
-- lsr z0.s, p1/m, z0.s, #33
--
-- lsr z0.d, p1/m, z0.d, #-1
-- lsr z0.d, p1/m, z0.d, #0
-- lsr z0.d, p1/m, z0.d, #1 // OK
-- lsr z0.d, p1/m, z0.d, #63 // OK
-- lsr z0.d, p1/m, z0.d, #64 // OK
-- lsr z0.d, p1/m, z0.d, #65
--
-- index z0.s, #-17, #1
-- index z0.s, #-16, #1 // OK
-- index z0.s, #15, #1 // OK
-- index z0.s, #16, #1
--
-- index z0.s, #0, #-17
-- index z0.s, #0, #-16 // OK
-- index z0.s, #0, #15 // OK
-- index z0.s, #0, #16
--
-- addpl x0, sp, #-33
-- addpl x0, sp, #-32 // OK
-- addpl sp, x0, #31 // OK
-- addpl sp, x0, #32
-- addpl x0, xzr, #1
-- addpl xzr, x0, #1
--
-- mul z0.b, z0.b, #-129
-- mul z0.b, z0.b, #-128 // OK
-- mul z0.b, z0.b, #127 // OK
-- mul z0.b, z0.b, #128
--
-- mul z0.s, z0.s, #-129
-- mul z0.s, z0.s, #-128 // OK
-- mul z0.s, z0.s, #127 // OK
-- mul z0.s, z0.s, #128
--
-- ftmad z0.s, z0.s, z1.s, #-1
-- ftmad z0.s, z0.s, z1.s, #0 // OK
-- ftmad z0.s, z0.s, z1.s, #7 // OK
-- ftmad z0.s, z0.s, z1.s, #8
-- ftmad z0.s, z0.s, z1.s, z2.s
--
-- cmphi p0.s,p1/z,z2.s,#-1
-- cmphi p0.s,p1/z,z2.s,#0 // OK
-- cmphi p0.s,p1/z,z2.s,#127 // OK
-- cmphi p0.s,p1/z,z2.s,#128
--
-- umax z0.s, z0.s, #-1
-- umax z0.s, z0.s, #0 // OK
-- umax z0.s, z0.s, #255 // OK
-- umax z0.s, z0.s, #256
--
-- ext z0.b, z0.b, z1.b, #-1
-- ext z0.b, z0.b, z1.b, #0 // OK
-- ext z0.b, z0.b, z1.b, #255 // OK
-- ext z0.b, z0.b, z1.b, #256
--
-- dup z0.b, z1.b[-1]
-- dup z0.b, z1.b[0] // OK
-- dup z0.b, z1.b[63] // OK
-- dup z0.b, z1.b[64]
-- dup z0.b, z1.b[x0]
--
-- dup z0.h, z1.h[-1]
-- dup z0.h, z1.h[0] // OK
-- dup z0.h, z1.h[31] // OK
-- dup z0.h, z1.h[32]
-- dup z0.h, z1.h[x0]
--
-- dup z0.s, z1.s[-1]
-- dup z0.s, z1.s[0] // OK
-- dup z0.s, z1.s[15] // OK
-- dup z0.s, z1.s[16]
-- dup z0.s, z1.s[x0]
--
-- dup z0.d, z1.d[-1]
-- dup z0.d, z1.d[0] // OK
-- dup z0.d, z1.d[7] // OK
-- dup z0.d, z1.d[8]
-- dup z0.d, z1.d[x0]
--
-- fabd z0.b, p0/m, z0.b, z0.b
-- fabd z0.q, p0/m, z0.q, z0.q
--
-- fcadd z0.b, p0/m, z0.b, z0.b, #90
-- fcadd z0.h, p0/m, z0.h, z0.h, #-180
-- fcadd z0.h, p0/m, z0.h, z0.h, #-90
-- fcadd z0.h, p0/m, z0.h, z0.h, #0
-- fcadd z0.h, p0/m, z0.h, z0.h, #89
-- fcadd z0.h, p0/m, z0.h, z0.h, #90.0
-- fcadd z0.h, p0/m, z0.h, z0.h, #180
-- fcadd z0.h, p0/m, z0.h, z0.h, #360
-- fcadd z0.h, p0/m, z0.h, z0.h, #450
-- fcadd z0.h, p0/z, z0.h, z0.h, #90
-- fcadd z0.h, p0/m, z1.h, z0.h, #90
-- fcadd z0.q, p0/m, z0.q, z0.q, #90
--
-- fcmla z0.b, p0/m, z0.b, z0.b, #90
-- fcmla z0.h, p0/m, z0.h, z0.h, #-180
-- fcmla z0.h, p0/m, z0.h, z0.h, #-90
-- fcmla z0.h, p0/m, z0.h, z0.h, #89
-- fcmla z0.h, p0/m, z0.h, z0.h, #90.0
-- fcmla z0.h, p0/m, z0.h, z0.h, #360
-- fcmla z0.h, p0/m, z0.h, z0.h, #450
-- fcmla z0.h, p0/z, z0.h, z0.h, #90
-- fcmla z0.q, p0/m, z0.q, z0.q, #90
--
-- fcmla z0.b, z1.b, z2.b[0], #0
-- fcmla z0.h, z1.h, z2.h[-1], #0
-- fcmla z0.h, z1.h, z2.h[4], #0
-- fcmla z0.h, z1.h, z8.h[0], #0
-- fcmla z0.h, z1.h, z2.h[0], #-180
-- fcmla z0.h, z1.h, z2.h[0], #-90
-- fcmla z0.h, z1.h, z2.h[0], #89
-- fcmla z0.h, z1.h, z2.h[0], #90.0
-- fcmla z0.h, z1.h, z2.h[0], #360
-- fcmla z0.h, z1.h, z2.h[0], #450
-- fcmla z0.s, z1.s, z2.s[-1], #0
-- fcmla z0.s, z1.s, z2.s[2], #0
-- fcmla z0.s, z1.s, z16.s[0], #0
-- fcmla z0.s, z1.s, z2.s[0], #-180
-- fcmla z0.s, z1.s, z2.s[0], #-90
-- fcmla z0.s, z1.s, z2.s[0], #89
-- fcmla z0.s, z1.s, z2.s[0], #90.0
-- fcmla z0.s, z1.s, z2.s[0], #360
-- fcmla z0.s, z1.s, z2.s[0], #450
-- fcmla z0.q, z1.q, z2.q[0], #0
--
-- fmla z0.b, z1.b, z2.b[0]
-- fmla z0.h, z1.h, z2.h[-1]
-- fmla z0.h, z1.h, z2.h[8]
-- fmla z0.h, z1.h, z8.h[0]
-- fmla z0.s, z1.s, z2.s[-1]
-- fmla z0.s, z1.s, z2.s[4]
-- fmla z0.s, z1.s, z8.s[0]
-- fmla z0.d, z1.d, z2.d[-1]
-- fmla z0.d, z1.d, z2.d[2]
-- fmla z0.d, z1.d, z16.d[0]
-- fmla z0.q, z1.q, z2.q[0]
--
-- fmls z0.b, z1.b, z2.b[0]
-- fmls z0.h, z1.h, z2.h[-1]
-- fmls z0.h, z1.h, z2.h[8]
-- fmls z0.h, z1.h, z8.h[0]
-- fmls z0.s, z1.s, z2.s[-1]
-- fmls z0.s, z1.s, z2.s[4]
-- fmls z0.s, z1.s, z8.s[0]
-- fmls z0.d, z1.d, z2.d[-1]
-- fmls z0.d, z1.d, z2.d[2]
-- fmls z0.d, z1.d, z16.d[0]
-- fmls z0.q, z1.q, z2.q[0]
--
-- fmul z0.b, z1.b, z2.b[0]
-- fmul z0.h, z1.h, z2.h[-1]
-- fmul z0.h, z1.h, z2.h[8]
-- fmul z0.h, z1.h, z8.h[0]
-- fmul z0.s, z1.s, z2.s[-1]
-- fmul z0.s, z1.s, z2.s[4]
-- fmul z0.s, z1.s, z8.s[0]
-- fmul z0.d, z1.d, z2.d[-1]
-- fmul z0.d, z1.d, z2.d[2]
-- fmul z0.d, z1.d, z16.d[0]
-- fmul z0.q, z1.q, z2.q[0]
--
-- ld1rqb {z0.b}, p0, [x0, #0]
-- ld1rqb {z0.b}, p0/m, [x0, #0]
-- ld1rqb {z0.b}, p8/z, [x0, #0]
-- ld1rqb {z0.b}, p0/z, [x0, #-144]
-- ld1rqb {z0.b}, p0/z, [x0, #-15]
-- ld1rqb {z0.b}, p0/z, [x0, #-14]
-- ld1rqb {z0.b}, p0/z, [x0, #-13]
-- ld1rqb {z0.b}, p0/z, [x0, #-12]
-- ld1rqb {z0.b}, p0/z, [x0, #-11]
-- ld1rqb {z0.b}, p0/z, [x0, #-10]
-- ld1rqb {z0.b}, p0/z, [x0, #-9]
-- ld1rqb {z0.b}, p0/z, [x0, #-8]
-- ld1rqb {z0.b}, p0/z, [x0, #-7]
-- ld1rqb {z0.b}, p0/z, [x0, #-6]
-- ld1rqb {z0.b}, p0/z, [x0, #-5]
-- ld1rqb {z0.b}, p0/z, [x0, #-4]
-- ld1rqb {z0.b}, p0/z, [x0, #-3]
-- ld1rqb {z0.b}, p0/z, [x0, #-2]
-- ld1rqb {z0.b}, p0/z, [x0, #-1]
-- ld1rqb {z0.b}, p0/z, [x0, #1]
-- ld1rqb {z0.b}, p0/z, [x0, #2]
-- ld1rqb {z0.b}, p0/z, [x0, #3]
-- ld1rqb {z0.b}, p0/z, [x0, #4]
-- ld1rqb {z0.b}, p0/z, [x0, #5]
-- ld1rqb {z0.b}, p0/z, [x0, #6]
-- ld1rqb {z0.b}, p0/z, [x0, #7]
-- ld1rqb {z0.b}, p0/z, [x0, #8]
-- ld1rqb {z0.b}, p0/z, [x0, #9]
-- ld1rqb {z0.b}, p0/z, [x0, #10]
-- ld1rqb {z0.b}, p0/z, [x0, #11]
-- ld1rqb {z0.b}, p0/z, [x0, #12]
-- ld1rqb {z0.b}, p0/z, [x0, #13]
-- ld1rqb {z0.b}, p0/z, [x0, #14]
-- ld1rqb {z0.b}, p0/z, [x0, #15]
-- ld1rqb {z0.b}, p0/z, [x0, #128]
-- ld1rqb {z0.h}, p0/z, [x0, #0]
-- ld1rqb {z0.s}, p0/z, [x0, #0]
-- ld1rqb {z0.d}, p0/z, [x0, #0]
-- ld1rqb {z0.q}, p0/z, [x0, #0]
--
-- ld1rqb {z0.b}, p0/z, [x0, xzr]
-- ld1rqb {z0.b}, p0/z, [x0, x1, lsl #1]
-- ld1rqb {z0.b}, p0/z, [x0, x1, lsl #2]
-- ld1rqb {z0.b}, p0/z, [x0, x1, lsl #3]
--
-- ld1rqh {z0.h}, p0/z, [x0, xzr, lsl #1]
-- ld1rqh {z0.h}, p0/z, [x0, x1]
-- ld1rqh {z0.h}, p0/z, [x0, x1, lsl #2]
-- ld1rqh {z0.h}, p0/z, [x0, x1, lsl #3]
--
-- ld1rqw {z0.s}, p0/z, [x0, xzr, lsl #2]
-- ld1rqw {z0.s}, p0/z, [x0, x1]
-- ld1rqw {z0.s}, p0/z, [x0, x1, lsl #1]
-- ld1rqw {z0.s}, p0/z, [x0, x1, lsl #3]
--
-- ld1rqd {z0.d}, p0/z, [x0, xzr, lsl #3]
-- ld1rqd {z0.d}, p0/z, [x0, x1]
-- ld1rqd {z0.d}, p0/z, [x0, x1, lsl #1]
-- ld1rqd {z0.d}, p0/z, [x0, x1, lsl #2]
--
-- sdot z0.b, z1.b, z2.b
-- sdot z0.h, z1.h, z2.h
-- sdot z0.s, z1.s, z2.s
-- sdot z0.d, z1.d, z2.d
--
-- sdot z0.b, z1.b, z2.b[0]
-- sdot z0.h, z1.h, z2.h[0]
-- sdot z0.s, z1.s, z2.s[0]
-- sdot z0.d, z1.d, z2.d[0]
--
-- udot z0.b, z1.b, z2.b
-- udot z0.h, z1.h, z2.h
-- udot z0.s, z1.s, z2.s
-- udot z0.d, z1.d, z2.d
--
-- udot z0.b, z1.b, z2.b[0]
-- udot z0.h, z1.h, z2.h[0]
-- udot z0.s, z1.s, z2.s[0]
-- udot z0.d, z1.d, z2.d[0]
-Only in binutils-2.30.new/gas/testsuite/gas/aarch64: sve-movprfx-mm.d
-Only in binutils-2.30.new/gas/testsuite/gas/aarch64: sve-movprfx-mm.s
-diff -rup binutils-2.30/gas/testsuite/gas/aarch64/sve.d binutils-2.30.new/gas/testsuite/gas/aarch64/sve.d
---- binutils-2.30/gas/testsuite/gas/aarch64/sve.d 2018-01-13 13:31:15.000000000 +0000
-+++ binutils-2.30.new/gas/testsuite/gas/aarch64/sve.d 2021-03-23 16:19:56.761751874 +0000
-@@ -6,40559 +6,48668 @@
- Disassembly of section .*:
-
- 0+ <.*>:
--.*: 2579c000 fmov z0\.h, #2\.0+e\+00
--.*: 2579c000 fmov z0\.h, #2\.0+e\+00
--.*: 2579c001 fmov z1\.h, #2\.0+e\+00
--.*: 2579c001 fmov z1\.h, #2\.0+e\+00
--.*: 2579c01f fmov z31\.h, #2\.0+e\+00
--.*: 2579c01f fmov z31\.h, #2\.0+e\+00
--.*: 2579c600 fmov z0\.h, #1\.60+e\+01
--.*: 2579c600 fmov z0\.h, #1\.60+e\+01
--.*: 2579c900 fmov z0\.h, #1\.8750+e-01
--.*: 2579c900 fmov z0\.h, #1\.8750+e-01
--.*: 2579cfe0 fmov z0\.h, #1\.93750+e\+00
--.*: 2579cfe0 fmov z0\.h, #1\.93750+e\+00
--.*: 2579d100 fmov z0\.h, #-3\.0+e\+00
--.*: 2579d100 fmov z0\.h, #-3\.0+e\+00
--.*: 2579d800 fmov z0\.h, #-1\.250+e-01
--.*: 2579d800 fmov z0\.h, #-1\.250+e-01
--.*: 2579dfe0 fmov z0\.h, #-1\.93750+e\+00
--.*: 2579dfe0 fmov z0\.h, #-1\.93750+e\+00
--.*: 25b9c000 fmov z0\.s, #2\.0+e\+00
--.*: 25b9c000 fmov z0\.s, #2\.0+e\+00
--.*: 25b9c001 fmov z1\.s, #2\.0+e\+00
--.*: 25b9c001 fmov z1\.s, #2\.0+e\+00
--.*: 25b9c01f fmov z31\.s, #2\.0+e\+00
--.*: 25b9c01f fmov z31\.s, #2\.0+e\+00
--.*: 25b9c600 fmov z0\.s, #1\.60+e\+01
--.*: 25b9c600 fmov z0\.s, #1\.60+e\+01
--.*: 25b9c900 fmov z0\.s, #1\.8750+e-01
--.*: 25b9c900 fmov z0\.s, #1\.8750+e-01
--.*: 25b9cfe0 fmov z0\.s, #1\.93750+e\+00
--.*: 25b9cfe0 fmov z0\.s, #1\.93750+e\+00
--.*: 25b9d100 fmov z0\.s, #-3\.0+e\+00
--.*: 25b9d100 fmov z0\.s, #-3\.0+e\+00
--.*: 25b9d800 fmov z0\.s, #-1\.250+e-01
--.*: 25b9d800 fmov z0\.s, #-1\.250+e-01
--.*: 25b9dfe0 fmov z0\.s, #-1\.93750+e\+00
--.*: 25b9dfe0 fmov z0\.s, #-1\.93750+e\+00
--.*: 25f9c000 fmov z0\.d, #2\.0+e\+00
--.*: 25f9c000 fmov z0\.d, #2\.0+e\+00
--.*: 25f9c001 fmov z1\.d, #2\.0+e\+00
--.*: 25f9c001 fmov z1\.d, #2\.0+e\+00
--.*: 25f9c01f fmov z31\.d, #2\.0+e\+00
--.*: 25f9c01f fmov z31\.d, #2\.0+e\+00
--.*: 25f9c600 fmov z0\.d, #1\.60+e\+01
--.*: 25f9c600 fmov z0\.d, #1\.60+e\+01
--.*: 25f9c900 fmov z0\.d, #1\.8750+e-01
--.*: 25f9c900 fmov z0\.d, #1\.8750+e-01
--.*: 25f9cfe0 fmov z0\.d, #1\.93750+e\+00
--.*: 25f9cfe0 fmov z0\.d, #1\.93750+e\+00
--.*: 25f9d100 fmov z0\.d, #-3\.0+e\+00
--.*: 25f9d100 fmov z0\.d, #-3\.0+e\+00
--.*: 25f9d800 fmov z0\.d, #-1\.250+e-01
--.*: 25f9d800 fmov z0\.d, #-1\.250+e-01
--.*: 25f9dfe0 fmov z0\.d, #-1\.93750+e\+00
--.*: 25f9dfe0 fmov z0\.d, #-1\.93750+e\+00
--.*: 0550c000 fmov z0\.h, p0/m, #2\.0+e\+00
--.*: 0550c000 fmov z0\.h, p0/m, #2\.0+e\+00
--.*: 0550c001 fmov z1\.h, p0/m, #2\.0+e\+00
--.*: 0550c001 fmov z1\.h, p0/m, #2\.0+e\+00
--.*: 0550c01f fmov z31\.h, p0/m, #2\.0+e\+00
--.*: 0550c01f fmov z31\.h, p0/m, #2\.0+e\+00
--.*: 0552c000 fmov z0\.h, p2/m, #2\.0+e\+00
--.*: 0552c000 fmov z0\.h, p2/m, #2\.0+e\+00
--.*: 055fc000 fmov z0\.h, p15/m, #2\.0+e\+00
--.*: 055fc000 fmov z0\.h, p15/m, #2\.0+e\+00
--.*: 0550c600 fmov z0\.h, p0/m, #1\.60+e\+01
--.*: 0550c600 fmov z0\.h, p0/m, #1\.60+e\+01
--.*: 0550c900 fmov z0\.h, p0/m, #1\.8750+e-01
--.*: 0550c900 fmov z0\.h, p0/m, #1\.8750+e-01
--.*: 0550cfe0 fmov z0\.h, p0/m, #1\.93750+e\+00
--.*: 0550cfe0 fmov z0\.h, p0/m, #1\.93750+e\+00
--.*: 0550d100 fmov z0\.h, p0/m, #-3\.0+e\+00
--.*: 0550d100 fmov z0\.h, p0/m, #-3\.0+e\+00
--.*: 0550d800 fmov z0\.h, p0/m, #-1\.250+e-01
--.*: 0550d800 fmov z0\.h, p0/m, #-1\.250+e-01
--.*: 0550dfe0 fmov z0\.h, p0/m, #-1\.93750+e\+00
--.*: 0550dfe0 fmov z0\.h, p0/m, #-1\.93750+e\+00
--.*: 0590c000 fmov z0\.s, p0/m, #2\.0+e\+00
--.*: 0590c000 fmov z0\.s, p0/m, #2\.0+e\+00
--.*: 0590c001 fmov z1\.s, p0/m, #2\.0+e\+00
--.*: 0590c001 fmov z1\.s, p0/m, #2\.0+e\+00
--.*: 0590c01f fmov z31\.s, p0/m, #2\.0+e\+00
--.*: 0590c01f fmov z31\.s, p0/m, #2\.0+e\+00
--.*: 0592c000 fmov z0\.s, p2/m, #2\.0+e\+00
--.*: 0592c000 fmov z0\.s, p2/m, #2\.0+e\+00
--.*: 059fc000 fmov z0\.s, p15/m, #2\.0+e\+00
--.*: 059fc000 fmov z0\.s, p15/m, #2\.0+e\+00
--.*: 0590c600 fmov z0\.s, p0/m, #1\.60+e\+01
--.*: 0590c600 fmov z0\.s, p0/m, #1\.60+e\+01
--.*: 0590c900 fmov z0\.s, p0/m, #1\.8750+e-01
--.*: 0590c900 fmov z0\.s, p0/m, #1\.8750+e-01
--.*: 0590cfe0 fmov z0\.s, p0/m, #1\.93750+e\+00
--.*: 0590cfe0 fmov z0\.s, p0/m, #1\.93750+e\+00
--.*: 0590d100 fmov z0\.s, p0/m, #-3\.0+e\+00
--.*: 0590d100 fmov z0\.s, p0/m, #-3\.0+e\+00
--.*: 0590d800 fmov z0\.s, p0/m, #-1\.250+e-01
--.*: 0590d800 fmov z0\.s, p0/m, #-1\.250+e-01
--.*: 0590dfe0 fmov z0\.s, p0/m, #-1\.93750+e\+00
--.*: 0590dfe0 fmov z0\.s, p0/m, #-1\.93750+e\+00
--.*: 05d0c000 fmov z0\.d, p0/m, #2\.0+e\+00
--.*: 05d0c000 fmov z0\.d, p0/m, #2\.0+e\+00
--.*: 05d0c001 fmov z1\.d, p0/m, #2\.0+e\+00
--.*: 05d0c001 fmov z1\.d, p0/m, #2\.0+e\+00
--.*: 05d0c01f fmov z31\.d, p0/m, #2\.0+e\+00
--.*: 05d0c01f fmov z31\.d, p0/m, #2\.0+e\+00
--.*: 05d2c000 fmov z0\.d, p2/m, #2\.0+e\+00
--.*: 05d2c000 fmov z0\.d, p2/m, #2\.0+e\+00
--.*: 05dfc000 fmov z0\.d, p15/m, #2\.0+e\+00
--.*: 05dfc000 fmov z0\.d, p15/m, #2\.0+e\+00
--.*: 05d0c600 fmov z0\.d, p0/m, #1\.60+e\+01
--.*: 05d0c600 fmov z0\.d, p0/m, #1\.60+e\+01
--.*: 05d0c900 fmov z0\.d, p0/m, #1\.8750+e-01
--.*: 05d0c900 fmov z0\.d, p0/m, #1\.8750+e-01
--.*: 05d0cfe0 fmov z0\.d, p0/m, #1\.93750+e\+00
--.*: 05d0cfe0 fmov z0\.d, p0/m, #1\.93750+e\+00
--.*: 05d0d100 fmov z0\.d, p0/m, #-3\.0+e\+00
--.*: 05d0d100 fmov z0\.d, p0/m, #-3\.0+e\+00
--.*: 05d0d800 fmov z0\.d, p0/m, #-1\.250+e-01
--.*: 05d0d800 fmov z0\.d, p0/m, #-1\.250+e-01
--.*: 05d0dfe0 fmov z0\.d, p0/m, #-1\.93750+e\+00
--.*: 05d0dfe0 fmov z0\.d, p0/m, #-1\.93750+e\+00
--.*: 04603000 mov z0\.d, z0\.d
--.*: 04603000 mov z0\.d, z0\.d
--.*: 04603001 mov z1\.d, z0\.d
--.*: 04603001 mov z1\.d, z0\.d
--.*: 0460301f mov z31\.d, z0\.d
--.*: 0460301f mov z31\.d, z0\.d
--.*: 04623040 mov z0\.d, z2\.d
--.*: 04623040 mov z0\.d, z2\.d
--.*: 047f33e0 mov z0\.d, z31\.d
--.*: 047f33e0 mov z0\.d, z31\.d
--.*: 05212000 mov z0\.b, b0
--.*: 05212000 mov z0\.b, b0
--.*: 05212001 mov z1\.b, b0
--.*: 05212001 mov z1\.b, b0
--.*: 0521201f mov z31\.b, b0
--.*: 0521201f mov z31\.b, b0
--.*: 05212040 mov z0\.b, b2
--.*: 05212040 mov z0\.b, b2
--.*: 052123e0 mov z0\.b, b31
--.*: 052123e0 mov z0\.b, b31
--.*: 05222000 mov z0\.h, h0
--.*: 05222000 mov z0\.h, h0
--.*: 05222001 mov z1\.h, h0
--.*: 05222001 mov z1\.h, h0
--.*: 0522201f mov z31\.h, h0
--.*: 0522201f mov z31\.h, h0
--.*: 05222040 mov z0\.h, h2
--.*: 05222040 mov z0\.h, h2
--.*: 052223e0 mov z0\.h, h31
--.*: 052223e0 mov z0\.h, h31
--.*: 05242000 mov z0\.s, s0
--.*: 05242000 mov z0\.s, s0
--.*: 05242001 mov z1\.s, s0
--.*: 05242001 mov z1\.s, s0
--.*: 0524201f mov z31\.s, s0
--.*: 0524201f mov z31\.s, s0
--.*: 05242040 mov z0\.s, s2
--.*: 05242040 mov z0\.s, s2
--.*: 052423e0 mov z0\.s, s31
--.*: 052423e0 mov z0\.s, s31
--.*: 05282000 mov z0\.d, d0
--.*: 05282000 mov z0\.d, d0
--.*: 05282001 mov z1\.d, d0
--.*: 05282001 mov z1\.d, d0
--.*: 0528201f mov z31\.d, d0
--.*: 0528201f mov z31\.d, d0
--.*: 05282040 mov z0\.d, d2
--.*: 05282040 mov z0\.d, d2
--.*: 052823e0 mov z0\.d, d31
--.*: 052823e0 mov z0\.d, d31
--.*: 05302000 mov z0\.q, q0
--.*: 05302000 mov z0\.q, q0
--.*: 05302001 mov z1\.q, q0
--.*: 05302001 mov z1\.q, q0
--.*: 0530201f mov z31\.q, q0
--.*: 0530201f mov z31\.q, q0
--.*: 05302040 mov z0\.q, q2
--.*: 05302040 mov z0\.q, q2
--.*: 053023e0 mov z0\.q, q31
--.*: 053023e0 mov z0\.q, q31
--.*: 05203800 mov z0\.b, w0
--.*: 05203800 mov z0\.b, w0
--.*: 05203801 mov z1\.b, w0
--.*: 05203801 mov z1\.b, w0
--.*: 0520381f mov z31\.b, w0
--.*: 0520381f mov z31\.b, w0
--.*: 05203840 mov z0\.b, w2
--.*: 05203840 mov z0\.b, w2
--.*: 05203be0 mov z0\.b, wsp
--.*: 05203be0 mov z0\.b, wsp
--.*: 05603800 mov z0\.h, w0
--.*: 05603800 mov z0\.h, w0
--.*: 05603801 mov z1\.h, w0
--.*: 05603801 mov z1\.h, w0
--.*: 0560381f mov z31\.h, w0
--.*: 0560381f mov z31\.h, w0
--.*: 05603840 mov z0\.h, w2
--.*: 05603840 mov z0\.h, w2
--.*: 05603be0 mov z0\.h, wsp
--.*: 05603be0 mov z0\.h, wsp
--.*: 05a03800 mov z0\.s, w0
--.*: 05a03800 mov z0\.s, w0
--.*: 05a03801 mov z1\.s, w0
--.*: 05a03801 mov z1\.s, w0
--.*: 05a0381f mov z31\.s, w0
--.*: 05a0381f mov z31\.s, w0
--.*: 05a03840 mov z0\.s, w2
--.*: 05a03840 mov z0\.s, w2
--.*: 05a03be0 mov z0\.s, wsp
--.*: 05a03be0 mov z0\.s, wsp
--.*: 05e03800 mov z0\.d, x0
--.*: 05e03800 mov z0\.d, x0
--.*: 05e03801 mov z1\.d, x0
--.*: 05e03801 mov z1\.d, x0
--.*: 05e0381f mov z31\.d, x0
--.*: 05e0381f mov z31\.d, x0
--.*: 05e03840 mov z0\.d, x2
--.*: 05e03840 mov z0\.d, x2
--.*: 05e03be0 mov z0\.d, sp
--.*: 05e03be0 mov z0\.d, sp
--.*: 25804000 mov p0\.b, p0\.b
--.*: 25804000 mov p0\.b, p0\.b
--.*: 25804001 mov p1\.b, p0\.b
--.*: 25804001 mov p1\.b, p0\.b
--.*: 2580400f mov p15\.b, p0\.b
--.*: 2580400f mov p15\.b, p0\.b
--.*: 25824840 mov p0\.b, p2\.b
--.*: 25824840 mov p0\.b, p2\.b
--.*: 258f7de0 mov p0\.b, p15\.b
--.*: 258f7de0 mov p0\.b, p15\.b
--.*: 05232000 mov z0\.b, z0\.b\[1\]
--.*: 05232000 mov z0\.b, z0\.b\[1\]
--.*: 05232001 mov z1\.b, z0\.b\[1\]
--.*: 05232001 mov z1\.b, z0\.b\[1\]
--.*: 0523201f mov z31\.b, z0\.b\[1\]
--.*: 0523201f mov z31\.b, z0\.b\[1\]
--.*: 05232040 mov z0\.b, z2\.b\[1\]
--.*: 05232040 mov z0\.b, z2\.b\[1\]
--.*: 052323e0 mov z0\.b, z31\.b\[1\]
--.*: 052323e0 mov z0\.b, z31\.b\[1\]
--.*: 05252000 mov z0\.b, z0\.b\[2\]
--.*: 05252000 mov z0\.b, z0\.b\[2\]
--.*: 05fd2000 mov z0\.b, z0\.b\[62\]
--.*: 05fd2000 mov z0\.b, z0\.b\[62\]
--.*: 05ff2000 mov z0\.b, z0\.b\[63\]
--.*: 05ff2000 mov z0\.b, z0\.b\[63\]
--.*: 05252001 mov z1\.b, z0\.b\[2\]
--.*: 05252001 mov z1\.b, z0\.b\[2\]
--.*: 0525201f mov z31\.b, z0\.b\[2\]
--.*: 0525201f mov z31\.b, z0\.b\[2\]
--.*: 05252040 mov z0\.b, z2\.b\[2\]
--.*: 05252040 mov z0\.b, z2\.b\[2\]
--.*: 052523e0 mov z0\.b, z31\.b\[2\]
--.*: 052523e0 mov z0\.b, z31\.b\[2\]
--.*: 05272000 mov z0\.b, z0\.b\[3\]
--.*: 05272000 mov z0\.b, z0\.b\[3\]
--.*: 05262000 mov z0\.h, z0\.h\[1\]
--.*: 05262000 mov z0\.h, z0\.h\[1\]
--.*: 05262001 mov z1\.h, z0\.h\[1\]
--.*: 05262001 mov z1\.h, z0\.h\[1\]
--.*: 0526201f mov z31\.h, z0\.h\[1\]
--.*: 0526201f mov z31\.h, z0\.h\[1\]
--.*: 05262040 mov z0\.h, z2\.h\[1\]
--.*: 05262040 mov z0\.h, z2\.h\[1\]
--.*: 052623e0 mov z0\.h, z31\.h\[1\]
--.*: 052623e0 mov z0\.h, z31\.h\[1\]
--.*: 052a2000 mov z0\.h, z0\.h\[2\]
--.*: 052a2000 mov z0\.h, z0\.h\[2\]
--.*: 05fa2000 mov z0\.h, z0\.h\[30\]
--.*: 05fa2000 mov z0\.h, z0\.h\[30\]
--.*: 05fe2000 mov z0\.h, z0\.h\[31\]
--.*: 05fe2000 mov z0\.h, z0\.h\[31\]
--.*: 05272001 mov z1\.b, z0\.b\[3\]
--.*: 05272001 mov z1\.b, z0\.b\[3\]
--.*: 0527201f mov z31\.b, z0\.b\[3\]
--.*: 0527201f mov z31\.b, z0\.b\[3\]
--.*: 05272040 mov z0\.b, z2\.b\[3\]
--.*: 05272040 mov z0\.b, z2\.b\[3\]
--.*: 052723e0 mov z0\.b, z31\.b\[3\]
--.*: 052723e0 mov z0\.b, z31\.b\[3\]
--.*: 05292000 mov z0\.b, z0\.b\[4\]
--.*: 05292000 mov z0\.b, z0\.b\[4\]
--.*: 05292001 mov z1\.b, z0\.b\[4\]
--.*: 05292001 mov z1\.b, z0\.b\[4\]
--.*: 0529201f mov z31\.b, z0\.b\[4\]
--.*: 0529201f mov z31\.b, z0\.b\[4\]
--.*: 05292040 mov z0\.b, z2\.b\[4\]
--.*: 05292040 mov z0\.b, z2\.b\[4\]
--.*: 052923e0 mov z0\.b, z31\.b\[4\]
--.*: 052923e0 mov z0\.b, z31\.b\[4\]
--.*: 052b2000 mov z0\.b, z0\.b\[5\]
--.*: 052b2000 mov z0\.b, z0\.b\[5\]
--.*: 052a2001 mov z1\.h, z0\.h\[2\]
--.*: 052a2001 mov z1\.h, z0\.h\[2\]
--.*: 052a201f mov z31\.h, z0\.h\[2\]
--.*: 052a201f mov z31\.h, z0\.h\[2\]
--.*: 052a2040 mov z0\.h, z2\.h\[2\]
--.*: 052a2040 mov z0\.h, z2\.h\[2\]
--.*: 052a23e0 mov z0\.h, z31\.h\[2\]
--.*: 052a23e0 mov z0\.h, z31\.h\[2\]
--.*: 052e2000 mov z0\.h, z0\.h\[3\]
--.*: 052e2000 mov z0\.h, z0\.h\[3\]
--.*: 052b2001 mov z1\.b, z0\.b\[5\]
--.*: 052b2001 mov z1\.b, z0\.b\[5\]
--.*: 052b201f mov z31\.b, z0\.b\[5\]
--.*: 052b201f mov z31\.b, z0\.b\[5\]
--.*: 052b2040 mov z0\.b, z2\.b\[5\]
--.*: 052b2040 mov z0\.b, z2\.b\[5\]
--.*: 052b23e0 mov z0\.b, z31\.b\[5\]
--.*: 052b23e0 mov z0\.b, z31\.b\[5\]
--.*: 052d2000 mov z0\.b, z0\.b\[6\]
--.*: 052d2000 mov z0\.b, z0\.b\[6\]
--.*: 052c2000 mov z0\.s, z0\.s\[1\]
--.*: 052c2000 mov z0\.s, z0\.s\[1\]
--.*: 052c2001 mov z1\.s, z0\.s\[1\]
--.*: 052c2001 mov z1\.s, z0\.s\[1\]
--.*: 052c201f mov z31\.s, z0\.s\[1\]
--.*: 052c201f mov z31\.s, z0\.s\[1\]
--.*: 052c2040 mov z0\.s, z2\.s\[1\]
--.*: 052c2040 mov z0\.s, z2\.s\[1\]
--.*: 052c23e0 mov z0\.s, z31\.s\[1\]
--.*: 052c23e0 mov z0\.s, z31\.s\[1\]
--.*: 05342000 mov z0\.s, z0\.s\[2\]
--.*: 05342000 mov z0\.s, z0\.s\[2\]
--.*: 05f42000 mov z0\.s, z0\.s\[14\]
--.*: 05f42000 mov z0\.s, z0\.s\[14\]
--.*: 05fc2000 mov z0\.s, z0\.s\[15\]
--.*: 05fc2000 mov z0\.s, z0\.s\[15\]
--.*: 052d2001 mov z1\.b, z0\.b\[6\]
--.*: 052d2001 mov z1\.b, z0\.b\[6\]
--.*: 052d201f mov z31\.b, z0\.b\[6\]
--.*: 052d201f mov z31\.b, z0\.b\[6\]
--.*: 052d2040 mov z0\.b, z2\.b\[6\]
--.*: 052d2040 mov z0\.b, z2\.b\[6\]
--.*: 052d23e0 mov z0\.b, z31\.b\[6\]
--.*: 052d23e0 mov z0\.b, z31\.b\[6\]
--.*: 052f2000 mov z0\.b, z0\.b\[7\]
--.*: 052f2000 mov z0\.b, z0\.b\[7\]
--.*: 052e2001 mov z1\.h, z0\.h\[3\]
--.*: 052e2001 mov z1\.h, z0\.h\[3\]
--.*: 052e201f mov z31\.h, z0\.h\[3\]
--.*: 052e201f mov z31\.h, z0\.h\[3\]
--.*: 052e2040 mov z0\.h, z2\.h\[3\]
--.*: 052e2040 mov z0\.h, z2\.h\[3\]
--.*: 052e23e0 mov z0\.h, z31\.h\[3\]
--.*: 052e23e0 mov z0\.h, z31\.h\[3\]
--.*: 05322000 mov z0\.h, z0\.h\[4\]
--.*: 05322000 mov z0\.h, z0\.h\[4\]
--.*: 052f2001 mov z1\.b, z0\.b\[7\]
--.*: 052f2001 mov z1\.b, z0\.b\[7\]
--.*: 052f201f mov z31\.b, z0\.b\[7\]
--.*: 052f201f mov z31\.b, z0\.b\[7\]
--.*: 052f2040 mov z0\.b, z2\.b\[7\]
--.*: 052f2040 mov z0\.b, z2\.b\[7\]
--.*: 052f23e0 mov z0\.b, z31\.b\[7\]
--.*: 052f23e0 mov z0\.b, z31\.b\[7\]
--.*: 05312000 mov z0\.b, z0\.b\[8\]
--.*: 05312000 mov z0\.b, z0\.b\[8\]
--.*: 05702000 mov z0\.q, z0\.q\[1\]
--.*: 05702000 mov z0\.q, z0\.q\[1\]
--.*: 05702001 mov z1\.q, z0\.q\[1\]
--.*: 05702001 mov z1\.q, z0\.q\[1\]
--.*: 0570201f mov z31\.q, z0\.q\[1\]
--.*: 0570201f mov z31\.q, z0\.q\[1\]
--.*: 05702040 mov z0\.q, z2\.q\[1\]
--.*: 05702040 mov z0\.q, z2\.q\[1\]
--.*: 057023e0 mov z0\.q, z31\.q\[1\]
--.*: 057023e0 mov z0\.q, z31\.q\[1\]
--.*: 05302000 mov z0\.q, q0
--.*: 05302000 mov z0\.q, q0
--.*: 05b02000 mov z0\.q, z0\.q\[2\]
--.*: 05b02000 mov z0\.q, z0\.q\[2\]
--.*: 05f02000 mov z0\.q, z0\.q\[3\]
--.*: 05f02000 mov z0\.q, z0\.q\[3\]
--.*: 05c000e0 mov z0\.s, #0xff
--.*: 05c000e0 mov z0\.s, #0xff
--.*: 05c000e0 mov z0\.s, #0xff
--.*: 05c000e1 mov z1\.s, #0xff
--.*: 05c000e1 mov z1\.s, #0xff
--.*: 05c000e1 mov z1\.s, #0xff
--.*: 05c000ff mov z31\.s, #0xff
--.*: 05c000ff mov z31\.s, #0xff
--.*: 05c000ff mov z31\.s, #0xff
--.*: 05c005a0 mov z0\.h, #0x3fff
--.*: 05c005a0 mov z0\.h, #0x3fff
--.*: 05c005a0 mov z0\.h, #0x3fff
--.*: 05c005a0 mov z0\.h, #0x3fff
--.*: 05c00980 mov z0\.s, #0x80000fff
--.*: 05c00980 mov z0\.s, #0x80000fff
--.*: 05c00980 mov z0\.s, #0x80000fff
--.*: 05c00ae0 mov z0\.s, #0x807fffff
--.*: 05c00ae0 mov z0\.s, #0x807fffff
--.*: 05c00ae0 mov z0\.s, #0x807fffff
--.*: 05c00d40 mov z0\.h, #0x83ff
--.*: 05c00d40 mov z0\.h, #0x83ff
--.*: 05c00d40 mov z0\.h, #0x83ff
--.*: 05c00d40 mov z0\.h, #0x83ff
--.*: 05c01020 mov z0\.s, #0xc0000000
--.*: 05c01020 mov z0\.s, #0xc0000000
--.*: 05c01020 mov z0\.s, #0xc0000000
--.*: 05c03ac0 mov z0\.s, #0xfe00ffff
--.*: 05c03ac0 mov z0\.s, #0xfe00ffff
--.*: 05c03ac0 mov z0\.s, #0xfe00ffff
--.*: 05c21620 mov z0\.d, #0xc000ffffffffffff
--.*: 05c21620 mov z0\.d, #0xc000ffffffffffff
--.*: 05c33640 mov z0\.d, #0xfffffffffc001fff
--.*: 05c33640 mov z0\.d, #0xfffffffffc001fff
--.*: 05c3ffa0 mov z0\.d, #0x7ffffffffffffffe
--.*: 05c3ffa0 mov z0\.d, #0x7ffffffffffffffe
--.*: 2538c000 mov z0\.b, #0
--.*: 2538c000 mov z0\.b, #0
--.*: 2538c000 mov z0\.b, #0
--.*: 2538c001 mov z1\.b, #0
--.*: 2538c001 mov z1\.b, #0
--.*: 2538c001 mov z1\.b, #0
--.*: 2538c01f mov z31\.b, #0
--.*: 2538c01f mov z31\.b, #0
--.*: 2538c01f mov z31\.b, #0
--.*: 2538cfe0 mov z0\.b, #127
--.*: 2538cfe0 mov z0\.b, #127
--.*: 2538cfe0 mov z0\.b, #127
--.*: 2538d000 mov z0\.b, #-128
--.*: 2538d000 mov z0\.b, #-128
--.*: 2538d000 mov z0\.b, #-128
--.*: 2538d020 mov z0\.b, #-127
--.*: 2538d020 mov z0\.b, #-127
--.*: 2538d020 mov z0\.b, #-127
--.*: 2538dfe0 mov z0\.b, #-1
--.*: 2538dfe0 mov z0\.b, #-1
--.*: 2538dfe0 mov z0\.b, #-1
--.*: 2578c000 mov z0\.h, #0
--.*: 2578c000 mov z0\.h, #0
--.*: 2578c000 mov z0\.h, #0
--.*: 2578c001 mov z1\.h, #0
--.*: 2578c001 mov z1\.h, #0
--.*: 2578c001 mov z1\.h, #0
--.*: 2578c01f mov z31\.h, #0
--.*: 2578c01f mov z31\.h, #0
--.*: 2578c01f mov z31\.h, #0
--.*: 2578cfe0 mov z0\.h, #127
--.*: 2578cfe0 mov z0\.h, #127
--.*: 2578cfe0 mov z0\.h, #127
--.*: 2578d000 mov z0\.h, #-128
--.*: 2578d000 mov z0\.h, #-128
--.*: 2578d000 mov z0\.h, #-128
--.*: 2578d020 mov z0\.h, #-127
--.*: 2578d020 mov z0\.h, #-127
--.*: 2578d020 mov z0\.h, #-127
--.*: 2578dfe0 mov z0\.h, #-1
--.*: 2578dfe0 mov z0\.h, #-1
--.*: 2578dfe0 mov z0\.h, #-1
--.*: 2578e000 mov z0\.h, #0, lsl #8
--.*: 2578e000 mov z0\.h, #0, lsl #8
--.*: 2578efe0 mov z0\.h, #32512
--.*: 2578efe0 mov z0\.h, #32512
--.*: 2578efe0 mov z0\.h, #32512
--.*: 2578efe0 mov z0\.h, #32512
--.*: 2578f000 mov z0\.h, #-32768
--.*: 2578f000 mov z0\.h, #-32768
--.*: 2578f000 mov z0\.h, #-32768
--.*: 2578f000 mov z0\.h, #-32768
--.*: 2578f020 mov z0\.h, #-32512
--.*: 2578f020 mov z0\.h, #-32512
--.*: 2578f020 mov z0\.h, #-32512
--.*: 2578f020 mov z0\.h, #-32512
--.*: 2578ffe0 mov z0\.h, #-256
--.*: 2578ffe0 mov z0\.h, #-256
--.*: 2578ffe0 mov z0\.h, #-256
--.*: 2578ffe0 mov z0\.h, #-256
--.*: 25b8c000 mov z0\.s, #0
--.*: 25b8c000 mov z0\.s, #0
--.*: 25b8c000 mov z0\.s, #0
--.*: 25b8c001 mov z1\.s, #0
--.*: 25b8c001 mov z1\.s, #0
--.*: 25b8c001 mov z1\.s, #0
--.*: 25b8c01f mov z31\.s, #0
--.*: 25b8c01f mov z31\.s, #0
--.*: 25b8c01f mov z31\.s, #0
--.*: 25b8cfe0 mov z0\.s, #127
--.*: 25b8cfe0 mov z0\.s, #127
--.*: 25b8cfe0 mov z0\.s, #127
--.*: 25b8d000 mov z0\.s, #-128
--.*: 25b8d000 mov z0\.s, #-128
--.*: 25b8d000 mov z0\.s, #-128
--.*: 25b8d020 mov z0\.s, #-127
--.*: 25b8d020 mov z0\.s, #-127
--.*: 25b8d020 mov z0\.s, #-127
--.*: 25b8dfe0 mov z0\.s, #-1
--.*: 25b8dfe0 mov z0\.s, #-1
--.*: 25b8dfe0 mov z0\.s, #-1
--.*: 25b8e000 mov z0\.s, #0, lsl #8
--.*: 25b8e000 mov z0\.s, #0, lsl #8
--.*: 25b8efe0 mov z0\.s, #32512
--.*: 25b8efe0 mov z0\.s, #32512
--.*: 25b8efe0 mov z0\.s, #32512
--.*: 25b8efe0 mov z0\.s, #32512
--.*: 25b8f000 mov z0\.s, #-32768
--.*: 25b8f000 mov z0\.s, #-32768
--.*: 25b8f000 mov z0\.s, #-32768
--.*: 25b8f000 mov z0\.s, #-32768
--.*: 25b8f020 mov z0\.s, #-32512
--.*: 25b8f020 mov z0\.s, #-32512
--.*: 25b8f020 mov z0\.s, #-32512
--.*: 25b8f020 mov z0\.s, #-32512
--.*: 25b8ffe0 mov z0\.s, #-256
--.*: 25b8ffe0 mov z0\.s, #-256
--.*: 25b8ffe0 mov z0\.s, #-256
--.*: 25b8ffe0 mov z0\.s, #-256
--.*: 25f8c000 mov z0\.d, #0
--.*: 25f8c000 mov z0\.d, #0
--.*: 25f8c000 mov z0\.d, #0
--.*: 25f8c001 mov z1\.d, #0
--.*: 25f8c001 mov z1\.d, #0
--.*: 25f8c001 mov z1\.d, #0
--.*: 25f8c01f mov z31\.d, #0
--.*: 25f8c01f mov z31\.d, #0
--.*: 25f8c01f mov z31\.d, #0
--.*: 25f8cfe0 mov z0\.d, #127
--.*: 25f8cfe0 mov z0\.d, #127
--.*: 25f8cfe0 mov z0\.d, #127
--.*: 25f8d000 mov z0\.d, #-128
--.*: 25f8d000 mov z0\.d, #-128
--.*: 25f8d000 mov z0\.d, #-128
--.*: 25f8d020 mov z0\.d, #-127
--.*: 25f8d020 mov z0\.d, #-127
--.*: 25f8d020 mov z0\.d, #-127
--.*: 25f8dfe0 mov z0\.d, #-1
--.*: 25f8dfe0 mov z0\.d, #-1
--.*: 25f8dfe0 mov z0\.d, #-1
--.*: 25f8e000 mov z0\.d, #0, lsl #8
--.*: 25f8e000 mov z0\.d, #0, lsl #8
--.*: 25f8efe0 mov z0\.d, #32512
--.*: 25f8efe0 mov z0\.d, #32512
--.*: 25f8efe0 mov z0\.d, #32512
--.*: 25f8efe0 mov z0\.d, #32512
--.*: 25f8f000 mov z0\.d, #-32768
--.*: 25f8f000 mov z0\.d, #-32768
--.*: 25f8f000 mov z0\.d, #-32768
--.*: 25f8f000 mov z0\.d, #-32768
--.*: 25f8f020 mov z0\.d, #-32512
--.*: 25f8f020 mov z0\.d, #-32512
--.*: 25f8f020 mov z0\.d, #-32512
--.*: 25f8f020 mov z0\.d, #-32512
--.*: 25f8ffe0 mov z0\.d, #-256
--.*: 25f8ffe0 mov z0\.d, #-256
--.*: 25f8ffe0 mov z0\.d, #-256
--.*: 25f8ffe0 mov z0\.d, #-256
--.*: 05208000 mov z0\.b, p0/m, b0
--.*: 05208000 mov z0\.b, p0/m, b0
--.*: 05208001 mov z1\.b, p0/m, b0
--.*: 05208001 mov z1\.b, p0/m, b0
--.*: 0520801f mov z31\.b, p0/m, b0
--.*: 0520801f mov z31\.b, p0/m, b0
--.*: 05208800 mov z0\.b, p2/m, b0
--.*: 05208800 mov z0\.b, p2/m, b0
--.*: 05209c00 mov z0\.b, p7/m, b0
--.*: 05209c00 mov z0\.b, p7/m, b0
--.*: 05208060 mov z0\.b, p0/m, b3
--.*: 05208060 mov z0\.b, p0/m, b3
--.*: 052083e0 mov z0\.b, p0/m, b31
--.*: 052083e0 mov z0\.b, p0/m, b31
--.*: 05608000 mov z0\.h, p0/m, h0
--.*: 05608000 mov z0\.h, p0/m, h0
--.*: 05608001 mov z1\.h, p0/m, h0
--.*: 05608001 mov z1\.h, p0/m, h0
--.*: 0560801f mov z31\.h, p0/m, h0
--.*: 0560801f mov z31\.h, p0/m, h0
--.*: 05608800 mov z0\.h, p2/m, h0
--.*: 05608800 mov z0\.h, p2/m, h0
--.*: 05609c00 mov z0\.h, p7/m, h0
--.*: 05609c00 mov z0\.h, p7/m, h0
--.*: 05608060 mov z0\.h, p0/m, h3
--.*: 05608060 mov z0\.h, p0/m, h3
--.*: 056083e0 mov z0\.h, p0/m, h31
--.*: 056083e0 mov z0\.h, p0/m, h31
--.*: 05a08000 mov z0\.s, p0/m, s0
--.*: 05a08000 mov z0\.s, p0/m, s0
--.*: 05a08001 mov z1\.s, p0/m, s0
--.*: 05a08001 mov z1\.s, p0/m, s0
--.*: 05a0801f mov z31\.s, p0/m, s0
--.*: 05a0801f mov z31\.s, p0/m, s0
--.*: 05a08800 mov z0\.s, p2/m, s0
--.*: 05a08800 mov z0\.s, p2/m, s0
--.*: 05a09c00 mov z0\.s, p7/m, s0
--.*: 05a09c00 mov z0\.s, p7/m, s0
--.*: 05a08060 mov z0\.s, p0/m, s3
--.*: 05a08060 mov z0\.s, p0/m, s3
--.*: 05a083e0 mov z0\.s, p0/m, s31
--.*: 05a083e0 mov z0\.s, p0/m, s31
--.*: 05e08000 mov z0\.d, p0/m, d0
--.*: 05e08000 mov z0\.d, p0/m, d0
--.*: 05e08001 mov z1\.d, p0/m, d0
--.*: 05e08001 mov z1\.d, p0/m, d0
--.*: 05e0801f mov z31\.d, p0/m, d0
--.*: 05e0801f mov z31\.d, p0/m, d0
--.*: 05e08800 mov z0\.d, p2/m, d0
--.*: 05e08800 mov z0\.d, p2/m, d0
--.*: 05e09c00 mov z0\.d, p7/m, d0
--.*: 05e09c00 mov z0\.d, p7/m, d0
--.*: 05e08060 mov z0\.d, p0/m, d3
--.*: 05e08060 mov z0\.d, p0/m, d3
--.*: 05e083e0 mov z0\.d, p0/m, d31
--.*: 05e083e0 mov z0\.d, p0/m, d31
--.*: 0520c000 mov z0\.b, p0/m, z0\.b
--.*: 0520c000 mov z0\.b, p0/m, z0\.b
--.*: 0521c001 mov z1\.b, p0/m, z0\.b
--.*: 0521c001 mov z1\.b, p0/m, z0\.b
--.*: 053fc01f mov z31\.b, p0/m, z0\.b
--.*: 053fc01f mov z31\.b, p0/m, z0\.b
--.*: 0520c800 mov z0\.b, p2/m, z0\.b
--.*: 0520c800 mov z0\.b, p2/m, z0\.b
--.*: 0520fc00 mov z0\.b, p15/m, z0\.b
--.*: 0520fc00 mov z0\.b, p15/m, z0\.b
--.*: 0520c060 mov z0\.b, p0/m, z3\.b
--.*: 0520c060 mov z0\.b, p0/m, z3\.b
--.*: 0520c3e0 mov z0\.b, p0/m, z31\.b
--.*: 0520c3e0 mov z0\.b, p0/m, z31\.b
--.*: 0560c000 mov z0\.h, p0/m, z0\.h
--.*: 0560c000 mov z0\.h, p0/m, z0\.h
--.*: 0561c001 mov z1\.h, p0/m, z0\.h
--.*: 0561c001 mov z1\.h, p0/m, z0\.h
--.*: 057fc01f mov z31\.h, p0/m, z0\.h
--.*: 057fc01f mov z31\.h, p0/m, z0\.h
--.*: 0560c800 mov z0\.h, p2/m, z0\.h
--.*: 0560c800 mov z0\.h, p2/m, z0\.h
--.*: 0560fc00 mov z0\.h, p15/m, z0\.h
--.*: 0560fc00 mov z0\.h, p15/m, z0\.h
--.*: 0560c060 mov z0\.h, p0/m, z3\.h
--.*: 0560c060 mov z0\.h, p0/m, z3\.h
--.*: 0560c3e0 mov z0\.h, p0/m, z31\.h
--.*: 0560c3e0 mov z0\.h, p0/m, z31\.h
--.*: 05a0c000 mov z0\.s, p0/m, z0\.s
--.*: 05a0c000 mov z0\.s, p0/m, z0\.s
--.*: 05a1c001 mov z1\.s, p0/m, z0\.s
--.*: 05a1c001 mov z1\.s, p0/m, z0\.s
--.*: 05bfc01f mov z31\.s, p0/m, z0\.s
--.*: 05bfc01f mov z31\.s, p0/m, z0\.s
--.*: 05a0c800 mov z0\.s, p2/m, z0\.s
--.*: 05a0c800 mov z0\.s, p2/m, z0\.s
--.*: 05a0fc00 mov z0\.s, p15/m, z0\.s
--.*: 05a0fc00 mov z0\.s, p15/m, z0\.s
--.*: 05a0c060 mov z0\.s, p0/m, z3\.s
--.*: 05a0c060 mov z0\.s, p0/m, z3\.s
--.*: 05a0c3e0 mov z0\.s, p0/m, z31\.s
--.*: 05a0c3e0 mov z0\.s, p0/m, z31\.s
--.*: 05e0c000 mov z0\.d, p0/m, z0\.d
--.*: 05e0c000 mov z0\.d, p0/m, z0\.d
--.*: 05e1c001 mov z1\.d, p0/m, z0\.d
--.*: 05e1c001 mov z1\.d, p0/m, z0\.d
--.*: 05ffc01f mov z31\.d, p0/m, z0\.d
--.*: 05ffc01f mov z31\.d, p0/m, z0\.d
--.*: 05e0c800 mov z0\.d, p2/m, z0\.d
--.*: 05e0c800 mov z0\.d, p2/m, z0\.d
--.*: 05e0fc00 mov z0\.d, p15/m, z0\.d
--.*: 05e0fc00 mov z0\.d, p15/m, z0\.d
--.*: 05e0c060 mov z0\.d, p0/m, z3\.d
--.*: 05e0c060 mov z0\.d, p0/m, z3\.d
--.*: 05e0c3e0 mov z0\.d, p0/m, z31\.d
--.*: 05e0c3e0 mov z0\.d, p0/m, z31\.d
--.*: 0528a000 mov z0\.b, p0/m, w0
--.*: 0528a000 mov z0\.b, p0/m, w0
--.*: 0528a001 mov z1\.b, p0/m, w0
--.*: 0528a001 mov z1\.b, p0/m, w0
--.*: 0528a01f mov z31\.b, p0/m, w0
--.*: 0528a01f mov z31\.b, p0/m, w0
--.*: 0528a800 mov z0\.b, p2/m, w0
--.*: 0528a800 mov z0\.b, p2/m, w0
--.*: 0528bc00 mov z0\.b, p7/m, w0
--.*: 0528bc00 mov z0\.b, p7/m, w0
--.*: 0528a060 mov z0\.b, p0/m, w3
--.*: 0528a060 mov z0\.b, p0/m, w3
--.*: 0528a3e0 mov z0\.b, p0/m, wsp
--.*: 0528a3e0 mov z0\.b, p0/m, wsp
--.*: 0568a000 mov z0\.h, p0/m, w0
--.*: 0568a000 mov z0\.h, p0/m, w0
--.*: 0568a001 mov z1\.h, p0/m, w0
--.*: 0568a001 mov z1\.h, p0/m, w0
--.*: 0568a01f mov z31\.h, p0/m, w0
--.*: 0568a01f mov z31\.h, p0/m, w0
--.*: 0568a800 mov z0\.h, p2/m, w0
--.*: 0568a800 mov z0\.h, p2/m, w0
--.*: 0568bc00 mov z0\.h, p7/m, w0
--.*: 0568bc00 mov z0\.h, p7/m, w0
--.*: 0568a060 mov z0\.h, p0/m, w3
--.*: 0568a060 mov z0\.h, p0/m, w3
--.*: 0568a3e0 mov z0\.h, p0/m, wsp
--.*: 0568a3e0 mov z0\.h, p0/m, wsp
--.*: 05a8a000 mov z0\.s, p0/m, w0
--.*: 05a8a000 mov z0\.s, p0/m, w0
--.*: 05a8a001 mov z1\.s, p0/m, w0
--.*: 05a8a001 mov z1\.s, p0/m, w0
--.*: 05a8a01f mov z31\.s, p0/m, w0
--.*: 05a8a01f mov z31\.s, p0/m, w0
--.*: 05a8a800 mov z0\.s, p2/m, w0
--.*: 05a8a800 mov z0\.s, p2/m, w0
--.*: 05a8bc00 mov z0\.s, p7/m, w0
--.*: 05a8bc00 mov z0\.s, p7/m, w0
--.*: 05a8a060 mov z0\.s, p0/m, w3
--.*: 05a8a060 mov z0\.s, p0/m, w3
--.*: 05a8a3e0 mov z0\.s, p0/m, wsp
--.*: 05a8a3e0 mov z0\.s, p0/m, wsp
--.*: 05e8a000 mov z0\.d, p0/m, x0
--.*: 05e8a000 mov z0\.d, p0/m, x0
--.*: 05e8a001 mov z1\.d, p0/m, x0
--.*: 05e8a001 mov z1\.d, p0/m, x0
--.*: 05e8a01f mov z31\.d, p0/m, x0
--.*: 05e8a01f mov z31\.d, p0/m, x0
--.*: 05e8a800 mov z0\.d, p2/m, x0
--.*: 05e8a800 mov z0\.d, p2/m, x0
--.*: 05e8bc00 mov z0\.d, p7/m, x0
--.*: 05e8bc00 mov z0\.d, p7/m, x0
--.*: 05e8a060 mov z0\.d, p0/m, x3
--.*: 05e8a060 mov z0\.d, p0/m, x3
--.*: 05e8a3e0 mov z0\.d, p0/m, sp
--.*: 05e8a3e0 mov z0\.d, p0/m, sp
--.*: 25004000 mov p0\.b, p0/z, p0\.b
--.*: 25004000 mov p0\.b, p0/z, p0\.b
--.*: 25004001 mov p1\.b, p0/z, p0\.b
--.*: 25004001 mov p1\.b, p0/z, p0\.b
--.*: 2500400f mov p15\.b, p0/z, p0\.b
--.*: 2500400f mov p15\.b, p0/z, p0\.b
--.*: 25004800 mov p0\.b, p2/z, p0\.b
--.*: 25004800 mov p0\.b, p2/z, p0\.b
--.*: 25007c00 mov p0\.b, p15/z, p0\.b
--.*: 25007c00 mov p0\.b, p15/z, p0\.b
--.*: 25034060 mov p0\.b, p0/z, p3\.b
--.*: 25034060 mov p0\.b, p0/z, p3\.b
--.*: 250f41e0 mov p0\.b, p0/z, p15\.b
--.*: 250f41e0 mov p0\.b, p0/z, p15\.b
--.*: 25004210 mov p0\.b, p0/m, p0\.b
--.*: 25004210 mov p0\.b, p0/m, p0\.b
--.*: 25014211 mov p1\.b, p0/m, p0\.b
--.*: 25014211 mov p1\.b, p0/m, p0\.b
--.*: 250f421f mov p15\.b, p0/m, p0\.b
--.*: 250f421f mov p15\.b, p0/m, p0\.b
--.*: 25004a10 mov p0\.b, p2/m, p0\.b
--.*: 25004a10 mov p0\.b, p2/m, p0\.b
--.*: 25007e10 mov p0\.b, p15/m, p0\.b
--.*: 25007e10 mov p0\.b, p15/m, p0\.b
--.*: 25004270 mov p0\.b, p0/m, p3\.b
--.*: 25004270 mov p0\.b, p0/m, p3\.b
--.*: 250043f0 mov p0\.b, p0/m, p15\.b
--.*: 250043f0 mov p0\.b, p0/m, p15\.b
--.*: 05100000 mov z0\.b, p0/z, #0
--.*: 05100000 mov z0\.b, p0/z, #0
--.*: 05100000 mov z0\.b, p0/z, #0
--.*: 05100001 mov z1\.b, p0/z, #0
--.*: 05100001 mov z1\.b, p0/z, #0
--.*: 05100001 mov z1\.b, p0/z, #0
--.*: 0510001f mov z31\.b, p0/z, #0
--.*: 0510001f mov z31\.b, p0/z, #0
--.*: 0510001f mov z31\.b, p0/z, #0
--.*: 05120000 mov z0\.b, p2/z, #0
--.*: 05120000 mov z0\.b, p2/z, #0
--.*: 05120000 mov z0\.b, p2/z, #0
--.*: 051f0000 mov z0\.b, p15/z, #0
--.*: 051f0000 mov z0\.b, p15/z, #0
--.*: 051f0000 mov z0\.b, p15/z, #0
--.*: 05100fe0 mov z0\.b, p0/z, #127
--.*: 05100fe0 mov z0\.b, p0/z, #127
--.*: 05100fe0 mov z0\.b, p0/z, #127
--.*: 05101000 mov z0\.b, p0/z, #-128
--.*: 05101000 mov z0\.b, p0/z, #-128
--.*: 05101000 mov z0\.b, p0/z, #-128
--.*: 05101020 mov z0\.b, p0/z, #-127
--.*: 05101020 mov z0\.b, p0/z, #-127
--.*: 05101020 mov z0\.b, p0/z, #-127
--.*: 05101fe0 mov z0\.b, p0/z, #-1
--.*: 05101fe0 mov z0\.b, p0/z, #-1
--.*: 05101fe0 mov z0\.b, p0/z, #-1
--.*: 05104000 mov z0\.b, p0/m, #0
--.*: 05104000 mov z0\.b, p0/m, #0
--.*: 05104000 mov z0\.b, p0/m, #0
--.*: 05104001 mov z1\.b, p0/m, #0
--.*: 05104001 mov z1\.b, p0/m, #0
--.*: 05104001 mov z1\.b, p0/m, #0
--.*: 0510401f mov z31\.b, p0/m, #0
--.*: 0510401f mov z31\.b, p0/m, #0
--.*: 0510401f mov z31\.b, p0/m, #0
--.*: 05124000 mov z0\.b, p2/m, #0
--.*: 05124000 mov z0\.b, p2/m, #0
--.*: 05124000 mov z0\.b, p2/m, #0
--.*: 051f4000 mov z0\.b, p15/m, #0
--.*: 051f4000 mov z0\.b, p15/m, #0
--.*: 051f4000 mov z0\.b, p15/m, #0
--.*: 05104fe0 mov z0\.b, p0/m, #127
--.*: 05104fe0 mov z0\.b, p0/m, #127
--.*: 05104fe0 mov z0\.b, p0/m, #127
--.*: 05105000 mov z0\.b, p0/m, #-128
--.*: 05105000 mov z0\.b, p0/m, #-128
--.*: 05105000 mov z0\.b, p0/m, #-128
--.*: 05105020 mov z0\.b, p0/m, #-127
--.*: 05105020 mov z0\.b, p0/m, #-127
--.*: 05105020 mov z0\.b, p0/m, #-127
--.*: 05105fe0 mov z0\.b, p0/m, #-1
--.*: 05105fe0 mov z0\.b, p0/m, #-1
--.*: 05105fe0 mov z0\.b, p0/m, #-1
--.*: 05500000 mov z0\.h, p0/z, #0
--.*: 05500000 mov z0\.h, p0/z, #0
--.*: 05500000 mov z0\.h, p0/z, #0
--.*: 05500001 mov z1\.h, p0/z, #0
--.*: 05500001 mov z1\.h, p0/z, #0
--.*: 05500001 mov z1\.h, p0/z, #0
--.*: 0550001f mov z31\.h, p0/z, #0
--.*: 0550001f mov z31\.h, p0/z, #0
--.*: 0550001f mov z31\.h, p0/z, #0
--.*: 05520000 mov z0\.h, p2/z, #0
--.*: 05520000 mov z0\.h, p2/z, #0
--.*: 05520000 mov z0\.h, p2/z, #0
--.*: 055f0000 mov z0\.h, p15/z, #0
--.*: 055f0000 mov z0\.h, p15/z, #0
--.*: 055f0000 mov z0\.h, p15/z, #0
--.*: 05500fe0 mov z0\.h, p0/z, #127
--.*: 05500fe0 mov z0\.h, p0/z, #127
--.*: 05500fe0 mov z0\.h, p0/z, #127
--.*: 05501000 mov z0\.h, p0/z, #-128
--.*: 05501000 mov z0\.h, p0/z, #-128
--.*: 05501000 mov z0\.h, p0/z, #-128
--.*: 05501020 mov z0\.h, p0/z, #-127
--.*: 05501020 mov z0\.h, p0/z, #-127
--.*: 05501020 mov z0\.h, p0/z, #-127
--.*: 05501fe0 mov z0\.h, p0/z, #-1
--.*: 05501fe0 mov z0\.h, p0/z, #-1
--.*: 05501fe0 mov z0\.h, p0/z, #-1
--.*: 05502000 mov z0\.h, p0/z, #0, lsl #8
--.*: 05502000 mov z0\.h, p0/z, #0, lsl #8
--.*: 05502fe0 mov z0\.h, p0/z, #32512
--.*: 05502fe0 mov z0\.h, p0/z, #32512
--.*: 05502fe0 mov z0\.h, p0/z, #32512
--.*: 05502fe0 mov z0\.h, p0/z, #32512
--.*: 05503000 mov z0\.h, p0/z, #-32768
--.*: 05503000 mov z0\.h, p0/z, #-32768
--.*: 05503000 mov z0\.h, p0/z, #-32768
--.*: 05503000 mov z0\.h, p0/z, #-32768
--.*: 05503020 mov z0\.h, p0/z, #-32512
--.*: 05503020 mov z0\.h, p0/z, #-32512
--.*: 05503020 mov z0\.h, p0/z, #-32512
--.*: 05503020 mov z0\.h, p0/z, #-32512
--.*: 05503fe0 mov z0\.h, p0/z, #-256
--.*: 05503fe0 mov z0\.h, p0/z, #-256
--.*: 05503fe0 mov z0\.h, p0/z, #-256
--.*: 05503fe0 mov z0\.h, p0/z, #-256
--.*: 05504000 mov z0\.h, p0/m, #0
--.*: 05504000 mov z0\.h, p0/m, #0
--.*: 05504000 mov z0\.h, p0/m, #0
--.*: 05504001 mov z1\.h, p0/m, #0
--.*: 05504001 mov z1\.h, p0/m, #0
--.*: 05504001 mov z1\.h, p0/m, #0
--.*: 0550401f mov z31\.h, p0/m, #0
--.*: 0550401f mov z31\.h, p0/m, #0
--.*: 0550401f mov z31\.h, p0/m, #0
--.*: 05524000 mov z0\.h, p2/m, #0
--.*: 05524000 mov z0\.h, p2/m, #0
--.*: 05524000 mov z0\.h, p2/m, #0
--.*: 055f4000 mov z0\.h, p15/m, #0
--.*: 055f4000 mov z0\.h, p15/m, #0
--.*: 055f4000 mov z0\.h, p15/m, #0
--.*: 05504fe0 mov z0\.h, p0/m, #127
--.*: 05504fe0 mov z0\.h, p0/m, #127
--.*: 05504fe0 mov z0\.h, p0/m, #127
--.*: 05505000 mov z0\.h, p0/m, #-128
--.*: 05505000 mov z0\.h, p0/m, #-128
--.*: 05505000 mov z0\.h, p0/m, #-128
--.*: 05505020 mov z0\.h, p0/m, #-127
--.*: 05505020 mov z0\.h, p0/m, #-127
--.*: 05505020 mov z0\.h, p0/m, #-127
--.*: 05505fe0 mov z0\.h, p0/m, #-1
--.*: 05505fe0 mov z0\.h, p0/m, #-1
--.*: 05505fe0 mov z0\.h, p0/m, #-1
--.*: 05506000 mov z0\.h, p0/m, #0, lsl #8
--.*: 05506000 mov z0\.h, p0/m, #0, lsl #8
--.*: 05506fe0 mov z0\.h, p0/m, #32512
--.*: 05506fe0 mov z0\.h, p0/m, #32512
--.*: 05506fe0 mov z0\.h, p0/m, #32512
--.*: 05506fe0 mov z0\.h, p0/m, #32512
--.*: 05507000 mov z0\.h, p0/m, #-32768
--.*: 05507000 mov z0\.h, p0/m, #-32768
--.*: 05507000 mov z0\.h, p0/m, #-32768
--.*: 05507000 mov z0\.h, p0/m, #-32768
--.*: 05507020 mov z0\.h, p0/m, #-32512
--.*: 05507020 mov z0\.h, p0/m, #-32512
--.*: 05507020 mov z0\.h, p0/m, #-32512
--.*: 05507020 mov z0\.h, p0/m, #-32512
--.*: 05507fe0 mov z0\.h, p0/m, #-256
--.*: 05507fe0 mov z0\.h, p0/m, #-256
--.*: 05507fe0 mov z0\.h, p0/m, #-256
--.*: 05507fe0 mov z0\.h, p0/m, #-256
--.*: 05900000 mov z0\.s, p0/z, #0
--.*: 05900000 mov z0\.s, p0/z, #0
--.*: 05900000 mov z0\.s, p0/z, #0
--.*: 05900001 mov z1\.s, p0/z, #0
--.*: 05900001 mov z1\.s, p0/z, #0
--.*: 05900001 mov z1\.s, p0/z, #0
--.*: 0590001f mov z31\.s, p0/z, #0
--.*: 0590001f mov z31\.s, p0/z, #0
--.*: 0590001f mov z31\.s, p0/z, #0
--.*: 05920000 mov z0\.s, p2/z, #0
--.*: 05920000 mov z0\.s, p2/z, #0
--.*: 05920000 mov z0\.s, p2/z, #0
--.*: 059f0000 mov z0\.s, p15/z, #0
--.*: 059f0000 mov z0\.s, p15/z, #0
--.*: 059f0000 mov z0\.s, p15/z, #0
--.*: 05900fe0 mov z0\.s, p0/z, #127
--.*: 05900fe0 mov z0\.s, p0/z, #127
--.*: 05900fe0 mov z0\.s, p0/z, #127
--.*: 05901000 mov z0\.s, p0/z, #-128
--.*: 05901000 mov z0\.s, p0/z, #-128
--.*: 05901000 mov z0\.s, p0/z, #-128
--.*: 05901020 mov z0\.s, p0/z, #-127
--.*: 05901020 mov z0\.s, p0/z, #-127
--.*: 05901020 mov z0\.s, p0/z, #-127
--.*: 05901fe0 mov z0\.s, p0/z, #-1
--.*: 05901fe0 mov z0\.s, p0/z, #-1
--.*: 05901fe0 mov z0\.s, p0/z, #-1
--.*: 05902000 mov z0\.s, p0/z, #0, lsl #8
--.*: 05902000 mov z0\.s, p0/z, #0, lsl #8
--.*: 05902fe0 mov z0\.s, p0/z, #32512
--.*: 05902fe0 mov z0\.s, p0/z, #32512
--.*: 05902fe0 mov z0\.s, p0/z, #32512
--.*: 05902fe0 mov z0\.s, p0/z, #32512
--.*: 05903000 mov z0\.s, p0/z, #-32768
--.*: 05903000 mov z0\.s, p0/z, #-32768
--.*: 05903000 mov z0\.s, p0/z, #-32768
--.*: 05903000 mov z0\.s, p0/z, #-32768
--.*: 05903020 mov z0\.s, p0/z, #-32512
--.*: 05903020 mov z0\.s, p0/z, #-32512
--.*: 05903020 mov z0\.s, p0/z, #-32512
--.*: 05903020 mov z0\.s, p0/z, #-32512
--.*: 05903fe0 mov z0\.s, p0/z, #-256
--.*: 05903fe0 mov z0\.s, p0/z, #-256
--.*: 05903fe0 mov z0\.s, p0/z, #-256
--.*: 05903fe0 mov z0\.s, p0/z, #-256
--.*: 05904000 mov z0\.s, p0/m, #0
--.*: 05904000 mov z0\.s, p0/m, #0
--.*: 05904000 mov z0\.s, p0/m, #0
--.*: 05904001 mov z1\.s, p0/m, #0
--.*: 05904001 mov z1\.s, p0/m, #0
--.*: 05904001 mov z1\.s, p0/m, #0
--.*: 0590401f mov z31\.s, p0/m, #0
--.*: 0590401f mov z31\.s, p0/m, #0
--.*: 0590401f mov z31\.s, p0/m, #0
--.*: 05924000 mov z0\.s, p2/m, #0
--.*: 05924000 mov z0\.s, p2/m, #0
--.*: 05924000 mov z0\.s, p2/m, #0
--.*: 059f4000 mov z0\.s, p15/m, #0
--.*: 059f4000 mov z0\.s, p15/m, #0
--.*: 059f4000 mov z0\.s, p15/m, #0
--.*: 05904fe0 mov z0\.s, p0/m, #127
--.*: 05904fe0 mov z0\.s, p0/m, #127
--.*: 05904fe0 mov z0\.s, p0/m, #127
--.*: 05905000 mov z0\.s, p0/m, #-128
--.*: 05905000 mov z0\.s, p0/m, #-128
--.*: 05905000 mov z0\.s, p0/m, #-128
--.*: 05905020 mov z0\.s, p0/m, #-127
--.*: 05905020 mov z0\.s, p0/m, #-127
--.*: 05905020 mov z0\.s, p0/m, #-127
--.*: 05905fe0 mov z0\.s, p0/m, #-1
--.*: 05905fe0 mov z0\.s, p0/m, #-1
--.*: 05905fe0 mov z0\.s, p0/m, #-1
--.*: 05906000 mov z0\.s, p0/m, #0, lsl #8
--.*: 05906000 mov z0\.s, p0/m, #0, lsl #8
--.*: 05906fe0 mov z0\.s, p0/m, #32512
--.*: 05906fe0 mov z0\.s, p0/m, #32512
--.*: 05906fe0 mov z0\.s, p0/m, #32512
--.*: 05906fe0 mov z0\.s, p0/m, #32512
--.*: 05907000 mov z0\.s, p0/m, #-32768
--.*: 05907000 mov z0\.s, p0/m, #-32768
--.*: 05907000 mov z0\.s, p0/m, #-32768
--.*: 05907000 mov z0\.s, p0/m, #-32768
--.*: 05907020 mov z0\.s, p0/m, #-32512
--.*: 05907020 mov z0\.s, p0/m, #-32512
--.*: 05907020 mov z0\.s, p0/m, #-32512
--.*: 05907020 mov z0\.s, p0/m, #-32512
--.*: 05907fe0 mov z0\.s, p0/m, #-256
--.*: 05907fe0 mov z0\.s, p0/m, #-256
--.*: 05907fe0 mov z0\.s, p0/m, #-256
--.*: 05907fe0 mov z0\.s, p0/m, #-256
--.*: 05d00000 mov z0\.d, p0/z, #0
--.*: 05d00000 mov z0\.d, p0/z, #0
--.*: 05d00000 mov z0\.d, p0/z, #0
--.*: 05d00001 mov z1\.d, p0/z, #0
--.*: 05d00001 mov z1\.d, p0/z, #0
--.*: 05d00001 mov z1\.d, p0/z, #0
--.*: 05d0001f mov z31\.d, p0/z, #0
--.*: 05d0001f mov z31\.d, p0/z, #0
--.*: 05d0001f mov z31\.d, p0/z, #0
--.*: 05d20000 mov z0\.d, p2/z, #0
--.*: 05d20000 mov z0\.d, p2/z, #0
--.*: 05d20000 mov z0\.d, p2/z, #0
--.*: 05df0000 mov z0\.d, p15/z, #0
--.*: 05df0000 mov z0\.d, p15/z, #0
--.*: 05df0000 mov z0\.d, p15/z, #0
--.*: 05d00fe0 mov z0\.d, p0/z, #127
--.*: 05d00fe0 mov z0\.d, p0/z, #127
--.*: 05d00fe0 mov z0\.d, p0/z, #127
--.*: 05d01000 mov z0\.d, p0/z, #-128
--.*: 05d01000 mov z0\.d, p0/z, #-128
--.*: 05d01000 mov z0\.d, p0/z, #-128
--.*: 05d01020 mov z0\.d, p0/z, #-127
--.*: 05d01020 mov z0\.d, p0/z, #-127
--.*: 05d01020 mov z0\.d, p0/z, #-127
--.*: 05d01fe0 mov z0\.d, p0/z, #-1
--.*: 05d01fe0 mov z0\.d, p0/z, #-1
--.*: 05d01fe0 mov z0\.d, p0/z, #-1
--.*: 05d02000 mov z0\.d, p0/z, #0, lsl #8
--.*: 05d02000 mov z0\.d, p0/z, #0, lsl #8
--.*: 05d02fe0 mov z0\.d, p0/z, #32512
--.*: 05d02fe0 mov z0\.d, p0/z, #32512
--.*: 05d02fe0 mov z0\.d, p0/z, #32512
--.*: 05d02fe0 mov z0\.d, p0/z, #32512
--.*: 05d03000 mov z0\.d, p0/z, #-32768
--.*: 05d03000 mov z0\.d, p0/z, #-32768
--.*: 05d03000 mov z0\.d, p0/z, #-32768
--.*: 05d03000 mov z0\.d, p0/z, #-32768
--.*: 05d03020 mov z0\.d, p0/z, #-32512
--.*: 05d03020 mov z0\.d, p0/z, #-32512
--.*: 05d03020 mov z0\.d, p0/z, #-32512
--.*: 05d03020 mov z0\.d, p0/z, #-32512
--.*: 05d03fe0 mov z0\.d, p0/z, #-256
--.*: 05d03fe0 mov z0\.d, p0/z, #-256
--.*: 05d03fe0 mov z0\.d, p0/z, #-256
--.*: 05d03fe0 mov z0\.d, p0/z, #-256
--.*: 05d04000 mov z0\.d, p0/m, #0
--.*: 05d04000 mov z0\.d, p0/m, #0
--.*: 05d04000 mov z0\.d, p0/m, #0
--.*: 05d04001 mov z1\.d, p0/m, #0
--.*: 05d04001 mov z1\.d, p0/m, #0
--.*: 05d04001 mov z1\.d, p0/m, #0
--.*: 05d0401f mov z31\.d, p0/m, #0
--.*: 05d0401f mov z31\.d, p0/m, #0
--.*: 05d0401f mov z31\.d, p0/m, #0
--.*: 05d24000 mov z0\.d, p2/m, #0
--.*: 05d24000 mov z0\.d, p2/m, #0
--.*: 05d24000 mov z0\.d, p2/m, #0
--.*: 05df4000 mov z0\.d, p15/m, #0
--.*: 05df4000 mov z0\.d, p15/m, #0
--.*: 05df4000 mov z0\.d, p15/m, #0
--.*: 05d04fe0 mov z0\.d, p0/m, #127
--.*: 05d04fe0 mov z0\.d, p0/m, #127
--.*: 05d04fe0 mov z0\.d, p0/m, #127
--.*: 05d05000 mov z0\.d, p0/m, #-128
--.*: 05d05000 mov z0\.d, p0/m, #-128
--.*: 05d05000 mov z0\.d, p0/m, #-128
--.*: 05d05020 mov z0\.d, p0/m, #-127
--.*: 05d05020 mov z0\.d, p0/m, #-127
--.*: 05d05020 mov z0\.d, p0/m, #-127
--.*: 05d05fe0 mov z0\.d, p0/m, #-1
--.*: 05d05fe0 mov z0\.d, p0/m, #-1
--.*: 05d05fe0 mov z0\.d, p0/m, #-1
--.*: 05d06000 mov z0\.d, p0/m, #0, lsl #8
--.*: 05d06000 mov z0\.d, p0/m, #0, lsl #8
--.*: 05d06fe0 mov z0\.d, p0/m, #32512
--.*: 05d06fe0 mov z0\.d, p0/m, #32512
--.*: 05d06fe0 mov z0\.d, p0/m, #32512
--.*: 05d06fe0 mov z0\.d, p0/m, #32512
--.*: 05d07000 mov z0\.d, p0/m, #-32768
--.*: 05d07000 mov z0\.d, p0/m, #-32768
--.*: 05d07000 mov z0\.d, p0/m, #-32768
--.*: 05d07000 mov z0\.d, p0/m, #-32768
--.*: 05d07020 mov z0\.d, p0/m, #-32512
--.*: 05d07020 mov z0\.d, p0/m, #-32512
--.*: 05d07020 mov z0\.d, p0/m, #-32512
--.*: 05d07020 mov z0\.d, p0/m, #-32512
--.*: 05d07fe0 mov z0\.d, p0/m, #-256
--.*: 05d07fe0 mov z0\.d, p0/m, #-256
--.*: 05d07fe0 mov z0\.d, p0/m, #-256
--.*: 05d07fe0 mov z0\.d, p0/m, #-256
--.*: 25c04000 movs p0\.b, p0\.b
--.*: 25c04000 movs p0\.b, p0\.b
--.*: 25c04001 movs p1\.b, p0\.b
--.*: 25c04001 movs p1\.b, p0\.b
--.*: 25c0400f movs p15\.b, p0\.b
--.*: 25c0400f movs p15\.b, p0\.b
--.*: 25c24840 movs p0\.b, p2\.b
--.*: 25c24840 movs p0\.b, p2\.b
--.*: 25cf7de0 movs p0\.b, p15\.b
--.*: 25cf7de0 movs p0\.b, p15\.b
--.*: 25404000 movs p0\.b, p0/z, p0\.b
--.*: 25404000 movs p0\.b, p0/z, p0\.b
--.*: 25404001 movs p1\.b, p0/z, p0\.b
--.*: 25404001 movs p1\.b, p0/z, p0\.b
--.*: 2540400f movs p15\.b, p0/z, p0\.b
--.*: 2540400f movs p15\.b, p0/z, p0\.b
--.*: 25404800 movs p0\.b, p2/z, p0\.b
--.*: 25404800 movs p0\.b, p2/z, p0\.b
--.*: 25407c00 movs p0\.b, p15/z, p0\.b
--.*: 25407c00 movs p0\.b, p15/z, p0\.b
--.*: 25434060 movs p0\.b, p0/z, p3\.b
--.*: 25434060 movs p0\.b, p0/z, p3\.b
--.*: 254f41e0 movs p0\.b, p0/z, p15\.b
--.*: 254f41e0 movs p0\.b, p0/z, p15\.b
--.*: 25004200 not p0\.b, p0/z, p0\.b
--.*: 25004200 not p0\.b, p0/z, p0\.b
--.*: 25004201 not p1\.b, p0/z, p0\.b
--.*: 25004201 not p1\.b, p0/z, p0\.b
--.*: 2500420f not p15\.b, p0/z, p0\.b
--.*: 2500420f not p15\.b, p0/z, p0\.b
--.*: 25024a00 not p0\.b, p2/z, p0\.b
--.*: 25024a00 not p0\.b, p2/z, p0\.b
--.*: 250f7e00 not p0\.b, p15/z, p0\.b
--.*: 250f7e00 not p0\.b, p15/z, p0\.b
--.*: 25004260 not p0\.b, p0/z, p3\.b
--.*: 25004260 not p0\.b, p0/z, p3\.b
--.*: 250043e0 not p0\.b, p0/z, p15\.b
--.*: 250043e0 not p0\.b, p0/z, p15\.b
--.*: 25404200 nots p0\.b, p0/z, p0\.b
--.*: 25404200 nots p0\.b, p0/z, p0\.b
--.*: 25404201 nots p1\.b, p0/z, p0\.b
--.*: 25404201 nots p1\.b, p0/z, p0\.b
--.*: 2540420f nots p15\.b, p0/z, p0\.b
--.*: 2540420f nots p15\.b, p0/z, p0\.b
--.*: 25424a00 nots p0\.b, p2/z, p0\.b
--.*: 25424a00 nots p0\.b, p2/z, p0\.b
--.*: 254f7e00 nots p0\.b, p15/z, p0\.b
--.*: 254f7e00 nots p0\.b, p15/z, p0\.b
--.*: 25404260 nots p0\.b, p0/z, p3\.b
--.*: 25404260 nots p0\.b, p0/z, p3\.b
--.*: 254043e0 nots p0\.b, p0/z, p15\.b
--.*: 254043e0 nots p0\.b, p0/z, p15\.b
--.*: 0416a000 abs z0\.b, p0/m, z0\.b
--.*: 0416a000 abs z0\.b, p0/m, z0\.b
--.*: 0416a001 abs z1\.b, p0/m, z0\.b
--.*: 0416a001 abs z1\.b, p0/m, z0\.b
--.*: 0416a01f abs z31\.b, p0/m, z0\.b
--.*: 0416a01f abs z31\.b, p0/m, z0\.b
--.*: 0416a800 abs z0\.b, p2/m, z0\.b
--.*: 0416a800 abs z0\.b, p2/m, z0\.b
--.*: 0416bc00 abs z0\.b, p7/m, z0\.b
--.*: 0416bc00 abs z0\.b, p7/m, z0\.b
--.*: 0416a060 abs z0\.b, p0/m, z3\.b
--.*: 0416a060 abs z0\.b, p0/m, z3\.b
--.*: 0416a3e0 abs z0\.b, p0/m, z31\.b
--.*: 0416a3e0 abs z0\.b, p0/m, z31\.b
--.*: 0456a000 abs z0\.h, p0/m, z0\.h
--.*: 0456a000 abs z0\.h, p0/m, z0\.h
--.*: 0456a001 abs z1\.h, p0/m, z0\.h
--.*: 0456a001 abs z1\.h, p0/m, z0\.h
--.*: 0456a01f abs z31\.h, p0/m, z0\.h
--.*: 0456a01f abs z31\.h, p0/m, z0\.h
--.*: 0456a800 abs z0\.h, p2/m, z0\.h
--.*: 0456a800 abs z0\.h, p2/m, z0\.h
--.*: 0456bc00 abs z0\.h, p7/m, z0\.h
--.*: 0456bc00 abs z0\.h, p7/m, z0\.h
--.*: 0456a060 abs z0\.h, p0/m, z3\.h
--.*: 0456a060 abs z0\.h, p0/m, z3\.h
--.*: 0456a3e0 abs z0\.h, p0/m, z31\.h
--.*: 0456a3e0 abs z0\.h, p0/m, z31\.h
--.*: 0496a000 abs z0\.s, p0/m, z0\.s
--.*: 0496a000 abs z0\.s, p0/m, z0\.s
--.*: 0496a001 abs z1\.s, p0/m, z0\.s
--.*: 0496a001 abs z1\.s, p0/m, z0\.s
--.*: 0496a01f abs z31\.s, p0/m, z0\.s
--.*: 0496a01f abs z31\.s, p0/m, z0\.s
--.*: 0496a800 abs z0\.s, p2/m, z0\.s
--.*: 0496a800 abs z0\.s, p2/m, z0\.s
--.*: 0496bc00 abs z0\.s, p7/m, z0\.s
--.*: 0496bc00 abs z0\.s, p7/m, z0\.s
--.*: 0496a060 abs z0\.s, p0/m, z3\.s
--.*: 0496a060 abs z0\.s, p0/m, z3\.s
--.*: 0496a3e0 abs z0\.s, p0/m, z31\.s
--.*: 0496a3e0 abs z0\.s, p0/m, z31\.s
--.*: 04d6a000 abs z0\.d, p0/m, z0\.d
--.*: 04d6a000 abs z0\.d, p0/m, z0\.d
--.*: 04d6a001 abs z1\.d, p0/m, z0\.d
--.*: 04d6a001 abs z1\.d, p0/m, z0\.d
--.*: 04d6a01f abs z31\.d, p0/m, z0\.d
--.*: 04d6a01f abs z31\.d, p0/m, z0\.d
--.*: 04d6a800 abs z0\.d, p2/m, z0\.d
--.*: 04d6a800 abs z0\.d, p2/m, z0\.d
--.*: 04d6bc00 abs z0\.d, p7/m, z0\.d
--.*: 04d6bc00 abs z0\.d, p7/m, z0\.d
--.*: 04d6a060 abs z0\.d, p0/m, z3\.d
--.*: 04d6a060 abs z0\.d, p0/m, z3\.d
--.*: 04d6a3e0 abs z0\.d, p0/m, z31\.d
--.*: 04d6a3e0 abs z0\.d, p0/m, z31\.d
--.*: 04200000 add z0\.b, z0\.b, z0\.b
--.*: 04200000 add z0\.b, z0\.b, z0\.b
--.*: 04200001 add z1\.b, z0\.b, z0\.b
--.*: 04200001 add z1\.b, z0\.b, z0\.b
--.*: 0420001f add z31\.b, z0\.b, z0\.b
--.*: 0420001f add z31\.b, z0\.b, z0\.b
--.*: 04200040 add z0\.b, z2\.b, z0\.b
--.*: 04200040 add z0\.b, z2\.b, z0\.b
--.*: 042003e0 add z0\.b, z31\.b, z0\.b
--.*: 042003e0 add z0\.b, z31\.b, z0\.b
--.*: 04230000 add z0\.b, z0\.b, z3\.b
--.*: 04230000 add z0\.b, z0\.b, z3\.b
--.*: 043f0000 add z0\.b, z0\.b, z31\.b
--.*: 043f0000 add z0\.b, z0\.b, z31\.b
--.*: 04600000 add z0\.h, z0\.h, z0\.h
--.*: 04600000 add z0\.h, z0\.h, z0\.h
--.*: 04600001 add z1\.h, z0\.h, z0\.h
--.*: 04600001 add z1\.h, z0\.h, z0\.h
--.*: 0460001f add z31\.h, z0\.h, z0\.h
--.*: 0460001f add z31\.h, z0\.h, z0\.h
--.*: 04600040 add z0\.h, z2\.h, z0\.h
--.*: 04600040 add z0\.h, z2\.h, z0\.h
--.*: 046003e0 add z0\.h, z31\.h, z0\.h
--.*: 046003e0 add z0\.h, z31\.h, z0\.h
--.*: 04630000 add z0\.h, z0\.h, z3\.h
--.*: 04630000 add z0\.h, z0\.h, z3\.h
--.*: 047f0000 add z0\.h, z0\.h, z31\.h
--.*: 047f0000 add z0\.h, z0\.h, z31\.h
--.*: 04a00000 add z0\.s, z0\.s, z0\.s
--.*: 04a00000 add z0\.s, z0\.s, z0\.s
--.*: 04a00001 add z1\.s, z0\.s, z0\.s
--.*: 04a00001 add z1\.s, z0\.s, z0\.s
--.*: 04a0001f add z31\.s, z0\.s, z0\.s
--.*: 04a0001f add z31\.s, z0\.s, z0\.s
--.*: 04a00040 add z0\.s, z2\.s, z0\.s
--.*: 04a00040 add z0\.s, z2\.s, z0\.s
--.*: 04a003e0 add z0\.s, z31\.s, z0\.s
--.*: 04a003e0 add z0\.s, z31\.s, z0\.s
--.*: 04a30000 add z0\.s, z0\.s, z3\.s
--.*: 04a30000 add z0\.s, z0\.s, z3\.s
--.*: 04bf0000 add z0\.s, z0\.s, z31\.s
--.*: 04bf0000 add z0\.s, z0\.s, z31\.s
--.*: 04e00000 add z0\.d, z0\.d, z0\.d
--.*: 04e00000 add z0\.d, z0\.d, z0\.d
--.*: 04e00001 add z1\.d, z0\.d, z0\.d
--.*: 04e00001 add z1\.d, z0\.d, z0\.d
--.*: 04e0001f add z31\.d, z0\.d, z0\.d
--.*: 04e0001f add z31\.d, z0\.d, z0\.d
--.*: 04e00040 add z0\.d, z2\.d, z0\.d
--.*: 04e00040 add z0\.d, z2\.d, z0\.d
--.*: 04e003e0 add z0\.d, z31\.d, z0\.d
--.*: 04e003e0 add z0\.d, z31\.d, z0\.d
--.*: 04e30000 add z0\.d, z0\.d, z3\.d
--.*: 04e30000 add z0\.d, z0\.d, z3\.d
--.*: 04ff0000 add z0\.d, z0\.d, z31\.d
--.*: 04ff0000 add z0\.d, z0\.d, z31\.d
--.*: 2520c000 add z0\.b, z0\.b, #0
--.*: 2520c000 add z0\.b, z0\.b, #0
--.*: 2520c000 add z0\.b, z0\.b, #0
--.*: 2520c001 add z1\.b, z1\.b, #0
--.*: 2520c001 add z1\.b, z1\.b, #0
--.*: 2520c001 add z1\.b, z1\.b, #0
--.*: 2520c01f add z31\.b, z31\.b, #0
--.*: 2520c01f add z31\.b, z31\.b, #0
--.*: 2520c01f add z31\.b, z31\.b, #0
--.*: 2520c002 add z2\.b, z2\.b, #0
--.*: 2520c002 add z2\.b, z2\.b, #0
--.*: 2520c002 add z2\.b, z2\.b, #0
--.*: 2520cfe0 add z0\.b, z0\.b, #127
--.*: 2520cfe0 add z0\.b, z0\.b, #127
--.*: 2520cfe0 add z0\.b, z0\.b, #127
--.*: 2520d000 add z0\.b, z0\.b, #128
--.*: 2520d000 add z0\.b, z0\.b, #128
--.*: 2520d000 add z0\.b, z0\.b, #128
--.*: 2520d020 add z0\.b, z0\.b, #129
--.*: 2520d020 add z0\.b, z0\.b, #129
--.*: 2520d020 add z0\.b, z0\.b, #129
--.*: 2520dfe0 add z0\.b, z0\.b, #255
--.*: 2520dfe0 add z0\.b, z0\.b, #255
--.*: 2520dfe0 add z0\.b, z0\.b, #255
--.*: 2560c000 add z0\.h, z0\.h, #0
--.*: 2560c000 add z0\.h, z0\.h, #0
--.*: 2560c000 add z0\.h, z0\.h, #0
--.*: 2560c001 add z1\.h, z1\.h, #0
--.*: 2560c001 add z1\.h, z1\.h, #0
--.*: 2560c001 add z1\.h, z1\.h, #0
--.*: 2560c01f add z31\.h, z31\.h, #0
--.*: 2560c01f add z31\.h, z31\.h, #0
--.*: 2560c01f add z31\.h, z31\.h, #0
--.*: 2560c002 add z2\.h, z2\.h, #0
--.*: 2560c002 add z2\.h, z2\.h, #0
--.*: 2560c002 add z2\.h, z2\.h, #0
--.*: 2560cfe0 add z0\.h, z0\.h, #127
--.*: 2560cfe0 add z0\.h, z0\.h, #127
--.*: 2560cfe0 add z0\.h, z0\.h, #127
--.*: 2560d000 add z0\.h, z0\.h, #128
--.*: 2560d000 add z0\.h, z0\.h, #128
--.*: 2560d000 add z0\.h, z0\.h, #128
--.*: 2560d020 add z0\.h, z0\.h, #129
--.*: 2560d020 add z0\.h, z0\.h, #129
--.*: 2560d020 add z0\.h, z0\.h, #129
--.*: 2560dfe0 add z0\.h, z0\.h, #255
--.*: 2560dfe0 add z0\.h, z0\.h, #255
--.*: 2560dfe0 add z0\.h, z0\.h, #255
--.*: 2560e000 add z0\.h, z0\.h, #0, lsl #8
--.*: 2560e000 add z0\.h, z0\.h, #0, lsl #8
--.*: 2560efe0 add z0\.h, z0\.h, #32512
--.*: 2560efe0 add z0\.h, z0\.h, #32512
--.*: 2560efe0 add z0\.h, z0\.h, #32512
--.*: 2560efe0 add z0\.h, z0\.h, #32512
--.*: 2560f000 add z0\.h, z0\.h, #32768
--.*: 2560f000 add z0\.h, z0\.h, #32768
--.*: 2560f000 add z0\.h, z0\.h, #32768
--.*: 2560f000 add z0\.h, z0\.h, #32768
--.*: 2560f020 add z0\.h, z0\.h, #33024
--.*: 2560f020 add z0\.h, z0\.h, #33024
--.*: 2560f020 add z0\.h, z0\.h, #33024
--.*: 2560f020 add z0\.h, z0\.h, #33024
--.*: 2560ffe0 add z0\.h, z0\.h, #65280
--.*: 2560ffe0 add z0\.h, z0\.h, #65280
--.*: 2560ffe0 add z0\.h, z0\.h, #65280
--.*: 2560ffe0 add z0\.h, z0\.h, #65280
--.*: 25a0c000 add z0\.s, z0\.s, #0
--.*: 25a0c000 add z0\.s, z0\.s, #0
--.*: 25a0c000 add z0\.s, z0\.s, #0
--.*: 25a0c001 add z1\.s, z1\.s, #0
--.*: 25a0c001 add z1\.s, z1\.s, #0
--.*: 25a0c001 add z1\.s, z1\.s, #0
--.*: 25a0c01f add z31\.s, z31\.s, #0
--.*: 25a0c01f add z31\.s, z31\.s, #0
--.*: 25a0c01f add z31\.s, z31\.s, #0
--.*: 25a0c002 add z2\.s, z2\.s, #0
--.*: 25a0c002 add z2\.s, z2\.s, #0
--.*: 25a0c002 add z2\.s, z2\.s, #0
--.*: 25a0cfe0 add z0\.s, z0\.s, #127
--.*: 25a0cfe0 add z0\.s, z0\.s, #127
--.*: 25a0cfe0 add z0\.s, z0\.s, #127
--.*: 25a0d000 add z0\.s, z0\.s, #128
--.*: 25a0d000 add z0\.s, z0\.s, #128
--.*: 25a0d000 add z0\.s, z0\.s, #128
--.*: 25a0d020 add z0\.s, z0\.s, #129
--.*: 25a0d020 add z0\.s, z0\.s, #129
--.*: 25a0d020 add z0\.s, z0\.s, #129
--.*: 25a0dfe0 add z0\.s, z0\.s, #255
--.*: 25a0dfe0 add z0\.s, z0\.s, #255
--.*: 25a0dfe0 add z0\.s, z0\.s, #255
--.*: 25a0e000 add z0\.s, z0\.s, #0, lsl #8
--.*: 25a0e000 add z0\.s, z0\.s, #0, lsl #8
--.*: 25a0efe0 add z0\.s, z0\.s, #32512
--.*: 25a0efe0 add z0\.s, z0\.s, #32512
--.*: 25a0efe0 add z0\.s, z0\.s, #32512
--.*: 25a0efe0 add z0\.s, z0\.s, #32512
--.*: 25a0f000 add z0\.s, z0\.s, #32768
--.*: 25a0f000 add z0\.s, z0\.s, #32768
--.*: 25a0f000 add z0\.s, z0\.s, #32768
--.*: 25a0f000 add z0\.s, z0\.s, #32768
--.*: 25a0f020 add z0\.s, z0\.s, #33024
--.*: 25a0f020 add z0\.s, z0\.s, #33024
--.*: 25a0f020 add z0\.s, z0\.s, #33024
--.*: 25a0f020 add z0\.s, z0\.s, #33024
--.*: 25a0ffe0 add z0\.s, z0\.s, #65280
--.*: 25a0ffe0 add z0\.s, z0\.s, #65280
--.*: 25a0ffe0 add z0\.s, z0\.s, #65280
--.*: 25a0ffe0 add z0\.s, z0\.s, #65280
--.*: 25e0c000 add z0\.d, z0\.d, #0
--.*: 25e0c000 add z0\.d, z0\.d, #0
--.*: 25e0c000 add z0\.d, z0\.d, #0
--.*: 25e0c001 add z1\.d, z1\.d, #0
--.*: 25e0c001 add z1\.d, z1\.d, #0
--.*: 25e0c001 add z1\.d, z1\.d, #0
--.*: 25e0c01f add z31\.d, z31\.d, #0
--.*: 25e0c01f add z31\.d, z31\.d, #0
--.*: 25e0c01f add z31\.d, z31\.d, #0
--.*: 25e0c002 add z2\.d, z2\.d, #0
--.*: 25e0c002 add z2\.d, z2\.d, #0
--.*: 25e0c002 add z2\.d, z2\.d, #0
--.*: 25e0cfe0 add z0\.d, z0\.d, #127
--.*: 25e0cfe0 add z0\.d, z0\.d, #127
--.*: 25e0cfe0 add z0\.d, z0\.d, #127
--.*: 25e0d000 add z0\.d, z0\.d, #128
--.*: 25e0d000 add z0\.d, z0\.d, #128
--.*: 25e0d000 add z0\.d, z0\.d, #128
--.*: 25e0d020 add z0\.d, z0\.d, #129
--.*: 25e0d020 add z0\.d, z0\.d, #129
--.*: 25e0d020 add z0\.d, z0\.d, #129
--.*: 25e0dfe0 add z0\.d, z0\.d, #255
--.*: 25e0dfe0 add z0\.d, z0\.d, #255
--.*: 25e0dfe0 add z0\.d, z0\.d, #255
--.*: 25e0e000 add z0\.d, z0\.d, #0, lsl #8
--.*: 25e0e000 add z0\.d, z0\.d, #0, lsl #8
--.*: 25e0efe0 add z0\.d, z0\.d, #32512
--.*: 25e0efe0 add z0\.d, z0\.d, #32512
--.*: 25e0efe0 add z0\.d, z0\.d, #32512
--.*: 25e0efe0 add z0\.d, z0\.d, #32512
--.*: 25e0f000 add z0\.d, z0\.d, #32768
--.*: 25e0f000 add z0\.d, z0\.d, #32768
--.*: 25e0f000 add z0\.d, z0\.d, #32768
--.*: 25e0f000 add z0\.d, z0\.d, #32768
--.*: 25e0f020 add z0\.d, z0\.d, #33024
--.*: 25e0f020 add z0\.d, z0\.d, #33024
--.*: 25e0f020 add z0\.d, z0\.d, #33024
--.*: 25e0f020 add z0\.d, z0\.d, #33024
--.*: 25e0ffe0 add z0\.d, z0\.d, #65280
--.*: 25e0ffe0 add z0\.d, z0\.d, #65280
--.*: 25e0ffe0 add z0\.d, z0\.d, #65280
--.*: 25e0ffe0 add z0\.d, z0\.d, #65280
--.*: 04000000 add z0\.b, p0/m, z0\.b, z0\.b
--.*: 04000000 add z0\.b, p0/m, z0\.b, z0\.b
--.*: 04000001 add z1\.b, p0/m, z1\.b, z0\.b
--.*: 04000001 add z1\.b, p0/m, z1\.b, z0\.b
--.*: 0400001f add z31\.b, p0/m, z31\.b, z0\.b
--.*: 0400001f add z31\.b, p0/m, z31\.b, z0\.b
--.*: 04000800 add z0\.b, p2/m, z0\.b, z0\.b
--.*: 04000800 add z0\.b, p2/m, z0\.b, z0\.b
--.*: 04001c00 add z0\.b, p7/m, z0\.b, z0\.b
--.*: 04001c00 add z0\.b, p7/m, z0\.b, z0\.b
--.*: 04000003 add z3\.b, p0/m, z3\.b, z0\.b
--.*: 04000003 add z3\.b, p0/m, z3\.b, z0\.b
--.*: 04000080 add z0\.b, p0/m, z0\.b, z4\.b
--.*: 04000080 add z0\.b, p0/m, z0\.b, z4\.b
--.*: 040003e0 add z0\.b, p0/m, z0\.b, z31\.b
--.*: 040003e0 add z0\.b, p0/m, z0\.b, z31\.b
--.*: 04400000 add z0\.h, p0/m, z0\.h, z0\.h
--.*: 04400000 add z0\.h, p0/m, z0\.h, z0\.h
--.*: 04400001 add z1\.h, p0/m, z1\.h, z0\.h
--.*: 04400001 add z1\.h, p0/m, z1\.h, z0\.h
--.*: 0440001f add z31\.h, p0/m, z31\.h, z0\.h
--.*: 0440001f add z31\.h, p0/m, z31\.h, z0\.h
--.*: 04400800 add z0\.h, p2/m, z0\.h, z0\.h
--.*: 04400800 add z0\.h, p2/m, z0\.h, z0\.h
--.*: 04401c00 add z0\.h, p7/m, z0\.h, z0\.h
--.*: 04401c00 add z0\.h, p7/m, z0\.h, z0\.h
--.*: 04400003 add z3\.h, p0/m, z3\.h, z0\.h
--.*: 04400003 add z3\.h, p0/m, z3\.h, z0\.h
--.*: 04400080 add z0\.h, p0/m, z0\.h, z4\.h
--.*: 04400080 add z0\.h, p0/m, z0\.h, z4\.h
--.*: 044003e0 add z0\.h, p0/m, z0\.h, z31\.h
--.*: 044003e0 add z0\.h, p0/m, z0\.h, z31\.h
--.*: 04800000 add z0\.s, p0/m, z0\.s, z0\.s
--.*: 04800000 add z0\.s, p0/m, z0\.s, z0\.s
--.*: 04800001 add z1\.s, p0/m, z1\.s, z0\.s
--.*: 04800001 add z1\.s, p0/m, z1\.s, z0\.s
--.*: 0480001f add z31\.s, p0/m, z31\.s, z0\.s
--.*: 0480001f add z31\.s, p0/m, z31\.s, z0\.s
--.*: 04800800 add z0\.s, p2/m, z0\.s, z0\.s
--.*: 04800800 add z0\.s, p2/m, z0\.s, z0\.s
--.*: 04801c00 add z0\.s, p7/m, z0\.s, z0\.s
--.*: 04801c00 add z0\.s, p7/m, z0\.s, z0\.s
--.*: 04800003 add z3\.s, p0/m, z3\.s, z0\.s
--.*: 04800003 add z3\.s, p0/m, z3\.s, z0\.s
--.*: 04800080 add z0\.s, p0/m, z0\.s, z4\.s
--.*: 04800080 add z0\.s, p0/m, z0\.s, z4\.s
--.*: 048003e0 add z0\.s, p0/m, z0\.s, z31\.s
--.*: 048003e0 add z0\.s, p0/m, z0\.s, z31\.s
--.*: 04c00000 add z0\.d, p0/m, z0\.d, z0\.d
--.*: 04c00000 add z0\.d, p0/m, z0\.d, z0\.d
--.*: 04c00001 add z1\.d, p0/m, z1\.d, z0\.d
--.*: 04c00001 add z1\.d, p0/m, z1\.d, z0\.d
--.*: 04c0001f add z31\.d, p0/m, z31\.d, z0\.d
--.*: 04c0001f add z31\.d, p0/m, z31\.d, z0\.d
--.*: 04c00800 add z0\.d, p2/m, z0\.d, z0\.d
--.*: 04c00800 add z0\.d, p2/m, z0\.d, z0\.d
--.*: 04c01c00 add z0\.d, p7/m, z0\.d, z0\.d
--.*: 04c01c00 add z0\.d, p7/m, z0\.d, z0\.d
--.*: 04c00003 add z3\.d, p0/m, z3\.d, z0\.d
--.*: 04c00003 add z3\.d, p0/m, z3\.d, z0\.d
--.*: 04c00080 add z0\.d, p0/m, z0\.d, z4\.d
--.*: 04c00080 add z0\.d, p0/m, z0\.d, z4\.d
--.*: 04c003e0 add z0\.d, p0/m, z0\.d, z31\.d
--.*: 04c003e0 add z0\.d, p0/m, z0\.d, z31\.d
--.*: 04605000 addpl x0, x0, #0
--.*: 04605000 addpl x0, x0, #0
--.*: 04605001 addpl x1, x0, #0
--.*: 04605001 addpl x1, x0, #0
--.*: 0460501f addpl sp, x0, #0
--.*: 0460501f addpl sp, x0, #0
--.*: 04625000 addpl x0, x2, #0
--.*: 04625000 addpl x0, x2, #0
--.*: 047f5000 addpl x0, sp, #0
--.*: 047f5000 addpl x0, sp, #0
--.*: 046053e0 addpl x0, x0, #31
--.*: 046053e0 addpl x0, x0, #31
--.*: 04605400 addpl x0, x0, #-32
--.*: 04605400 addpl x0, x0, #-32
--.*: 04605420 addpl x0, x0, #-31
--.*: 04605420 addpl x0, x0, #-31
--.*: 046057e0 addpl x0, x0, #-1
--.*: 046057e0 addpl x0, x0, #-1
--.*: 04205000 addvl x0, x0, #0
--.*: 04205000 addvl x0, x0, #0
--.*: 04205001 addvl x1, x0, #0
--.*: 04205001 addvl x1, x0, #0
--.*: 0420501f addvl sp, x0, #0
--.*: 0420501f addvl sp, x0, #0
--.*: 04225000 addvl x0, x2, #0
--.*: 04225000 addvl x0, x2, #0
--.*: 043f5000 addvl x0, sp, #0
--.*: 043f5000 addvl x0, sp, #0
--.*: 042053e0 addvl x0, x0, #31
--.*: 042053e0 addvl x0, x0, #31
--.*: 04205400 addvl x0, x0, #-32
--.*: 04205400 addvl x0, x0, #-32
--.*: 04205420 addvl x0, x0, #-31
--.*: 04205420 addvl x0, x0, #-31
--.*: 042057e0 addvl x0, x0, #-1
--.*: 042057e0 addvl x0, x0, #-1
--.*: 0420a000 adr z0\.d, \[z0\.d, z0\.d, sxtw\]
--.*: 0420a000 adr z0\.d, \[z0\.d, z0\.d, sxtw\]
--.*: 0420a000 adr z0\.d, \[z0\.d, z0\.d, sxtw\]
--.*: 0420a001 adr z1\.d, \[z0\.d, z0\.d, sxtw\]
--.*: 0420a001 adr z1\.d, \[z0\.d, z0\.d, sxtw\]
--.*: 0420a001 adr z1\.d, \[z0\.d, z0\.d, sxtw\]
--.*: 0420a01f adr z31\.d, \[z0\.d, z0\.d, sxtw\]
--.*: 0420a01f adr z31\.d, \[z0\.d, z0\.d, sxtw\]
--.*: 0420a01f adr z31\.d, \[z0\.d, z0\.d, sxtw\]
--.*: 0420a040 adr z0\.d, \[z2\.d, z0\.d, sxtw\]
--.*: 0420a040 adr z0\.d, \[z2\.d, z0\.d, sxtw\]
--.*: 0420a040 adr z0\.d, \[z2\.d, z0\.d, sxtw\]
--.*: 0420a3e0 adr z0\.d, \[z31\.d, z0\.d, sxtw\]
--.*: 0420a3e0 adr z0\.d, \[z31\.d, z0\.d, sxtw\]
--.*: 0420a3e0 adr z0\.d, \[z31\.d, z0\.d, sxtw\]
--.*: 0423a000 adr z0\.d, \[z0\.d, z3\.d, sxtw\]
--.*: 0423a000 adr z0\.d, \[z0\.d, z3\.d, sxtw\]
--.*: 0423a000 adr z0\.d, \[z0\.d, z3\.d, sxtw\]
--.*: 043fa000 adr z0\.d, \[z0\.d, z31\.d, sxtw\]
--.*: 043fa000 adr z0\.d, \[z0\.d, z31\.d, sxtw\]
--.*: 043fa000 adr z0\.d, \[z0\.d, z31\.d, sxtw\]
--.*: 0420a400 adr z0\.d, \[z0\.d, z0\.d, sxtw #1\]
--.*: 0420a400 adr z0\.d, \[z0\.d, z0\.d, sxtw #1\]
--.*: 0420a401 adr z1\.d, \[z0\.d, z0\.d, sxtw #1\]
--.*: 0420a401 adr z1\.d, \[z0\.d, z0\.d, sxtw #1\]
--.*: 0420a41f adr z31\.d, \[z0\.d, z0\.d, sxtw #1\]
--.*: 0420a41f adr z31\.d, \[z0\.d, z0\.d, sxtw #1\]
--.*: 0420a440 adr z0\.d, \[z2\.d, z0\.d, sxtw #1\]
--.*: 0420a440 adr z0\.d, \[z2\.d, z0\.d, sxtw #1\]
--.*: 0420a7e0 adr z0\.d, \[z31\.d, z0\.d, sxtw #1\]
--.*: 0420a7e0 adr z0\.d, \[z31\.d, z0\.d, sxtw #1\]
--.*: 0423a400 adr z0\.d, \[z0\.d, z3\.d, sxtw #1\]
--.*: 0423a400 adr z0\.d, \[z0\.d, z3\.d, sxtw #1\]
--.*: 043fa400 adr z0\.d, \[z0\.d, z31\.d, sxtw #1\]
--.*: 043fa400 adr z0\.d, \[z0\.d, z31\.d, sxtw #1\]
--.*: 0420a800 adr z0\.d, \[z0\.d, z0\.d, sxtw #2\]
--.*: 0420a800 adr z0\.d, \[z0\.d, z0\.d, sxtw #2\]
--.*: 0420a801 adr z1\.d, \[z0\.d, z0\.d, sxtw #2\]
--.*: 0420a801 adr z1\.d, \[z0\.d, z0\.d, sxtw #2\]
--.*: 0420a81f adr z31\.d, \[z0\.d, z0\.d, sxtw #2\]
--.*: 0420a81f adr z31\.d, \[z0\.d, z0\.d, sxtw #2\]
--.*: 0420a840 adr z0\.d, \[z2\.d, z0\.d, sxtw #2\]
--.*: 0420a840 adr z0\.d, \[z2\.d, z0\.d, sxtw #2\]
--.*: 0420abe0 adr z0\.d, \[z31\.d, z0\.d, sxtw #2\]
--.*: 0420abe0 adr z0\.d, \[z31\.d, z0\.d, sxtw #2\]
--.*: 0423a800 adr z0\.d, \[z0\.d, z3\.d, sxtw #2\]
--.*: 0423a800 adr z0\.d, \[z0\.d, z3\.d, sxtw #2\]
--.*: 043fa800 adr z0\.d, \[z0\.d, z31\.d, sxtw #2\]
--.*: 043fa800 adr z0\.d, \[z0\.d, z31\.d, sxtw #2\]
--.*: 0420ac00 adr z0\.d, \[z0\.d, z0\.d, sxtw #3\]
--.*: 0420ac00 adr z0\.d, \[z0\.d, z0\.d, sxtw #3\]
--.*: 0420ac01 adr z1\.d, \[z0\.d, z0\.d, sxtw #3\]
--.*: 0420ac01 adr z1\.d, \[z0\.d, z0\.d, sxtw #3\]
--.*: 0420ac1f adr z31\.d, \[z0\.d, z0\.d, sxtw #3\]
--.*: 0420ac1f adr z31\.d, \[z0\.d, z0\.d, sxtw #3\]
--.*: 0420ac40 adr z0\.d, \[z2\.d, z0\.d, sxtw #3\]
--.*: 0420ac40 adr z0\.d, \[z2\.d, z0\.d, sxtw #3\]
--.*: 0420afe0 adr z0\.d, \[z31\.d, z0\.d, sxtw #3\]
--.*: 0420afe0 adr z0\.d, \[z31\.d, z0\.d, sxtw #3\]
--.*: 0423ac00 adr z0\.d, \[z0\.d, z3\.d, sxtw #3\]
--.*: 0423ac00 adr z0\.d, \[z0\.d, z3\.d, sxtw #3\]
--.*: 043fac00 adr z0\.d, \[z0\.d, z31\.d, sxtw #3\]
--.*: 043fac00 adr z0\.d, \[z0\.d, z31\.d, sxtw #3\]
--.*: 0460a000 adr z0\.d, \[z0\.d, z0\.d, uxtw\]
--.*: 0460a000 adr z0\.d, \[z0\.d, z0\.d, uxtw\]
--.*: 0460a000 adr z0\.d, \[z0\.d, z0\.d, uxtw\]
--.*: 0460a001 adr z1\.d, \[z0\.d, z0\.d, uxtw\]
--.*: 0460a001 adr z1\.d, \[z0\.d, z0\.d, uxtw\]
--.*: 0460a001 adr z1\.d, \[z0\.d, z0\.d, uxtw\]
--.*: 0460a01f adr z31\.d, \[z0\.d, z0\.d, uxtw\]
--.*: 0460a01f adr z31\.d, \[z0\.d, z0\.d, uxtw\]
--.*: 0460a01f adr z31\.d, \[z0\.d, z0\.d, uxtw\]
--.*: 0460a040 adr z0\.d, \[z2\.d, z0\.d, uxtw\]
--.*: 0460a040 adr z0\.d, \[z2\.d, z0\.d, uxtw\]
--.*: 0460a040 adr z0\.d, \[z2\.d, z0\.d, uxtw\]
--.*: 0460a3e0 adr z0\.d, \[z31\.d, z0\.d, uxtw\]
--.*: 0460a3e0 adr z0\.d, \[z31\.d, z0\.d, uxtw\]
--.*: 0460a3e0 adr z0\.d, \[z31\.d, z0\.d, uxtw\]
--.*: 0463a000 adr z0\.d, \[z0\.d, z3\.d, uxtw\]
--.*: 0463a000 adr z0\.d, \[z0\.d, z3\.d, uxtw\]
--.*: 0463a000 adr z0\.d, \[z0\.d, z3\.d, uxtw\]
--.*: 047fa000 adr z0\.d, \[z0\.d, z31\.d, uxtw\]
--.*: 047fa000 adr z0\.d, \[z0\.d, z31\.d, uxtw\]
--.*: 047fa000 adr z0\.d, \[z0\.d, z31\.d, uxtw\]
--.*: 0460a400 adr z0\.d, \[z0\.d, z0\.d, uxtw #1\]
--.*: 0460a400 adr z0\.d, \[z0\.d, z0\.d, uxtw #1\]
--.*: 0460a401 adr z1\.d, \[z0\.d, z0\.d, uxtw #1\]
--.*: 0460a401 adr z1\.d, \[z0\.d, z0\.d, uxtw #1\]
--.*: 0460a41f adr z31\.d, \[z0\.d, z0\.d, uxtw #1\]
--.*: 0460a41f adr z31\.d, \[z0\.d, z0\.d, uxtw #1\]
--.*: 0460a440 adr z0\.d, \[z2\.d, z0\.d, uxtw #1\]
--.*: 0460a440 adr z0\.d, \[z2\.d, z0\.d, uxtw #1\]
--.*: 0460a7e0 adr z0\.d, \[z31\.d, z0\.d, uxtw #1\]
--.*: 0460a7e0 adr z0\.d, \[z31\.d, z0\.d, uxtw #1\]
--.*: 0463a400 adr z0\.d, \[z0\.d, z3\.d, uxtw #1\]
--.*: 0463a400 adr z0\.d, \[z0\.d, z3\.d, uxtw #1\]
--.*: 047fa400 adr z0\.d, \[z0\.d, z31\.d, uxtw #1\]
--.*: 047fa400 adr z0\.d, \[z0\.d, z31\.d, uxtw #1\]
--.*: 0460a800 adr z0\.d, \[z0\.d, z0\.d, uxtw #2\]
--.*: 0460a800 adr z0\.d, \[z0\.d, z0\.d, uxtw #2\]
--.*: 0460a801 adr z1\.d, \[z0\.d, z0\.d, uxtw #2\]
--.*: 0460a801 adr z1\.d, \[z0\.d, z0\.d, uxtw #2\]
--.*: 0460a81f adr z31\.d, \[z0\.d, z0\.d, uxtw #2\]
--.*: 0460a81f adr z31\.d, \[z0\.d, z0\.d, uxtw #2\]
--.*: 0460a840 adr z0\.d, \[z2\.d, z0\.d, uxtw #2\]
--.*: 0460a840 adr z0\.d, \[z2\.d, z0\.d, uxtw #2\]
--.*: 0460abe0 adr z0\.d, \[z31\.d, z0\.d, uxtw #2\]
--.*: 0460abe0 adr z0\.d, \[z31\.d, z0\.d, uxtw #2\]
--.*: 0463a800 adr z0\.d, \[z0\.d, z3\.d, uxtw #2\]
--.*: 0463a800 adr z0\.d, \[z0\.d, z3\.d, uxtw #2\]
--.*: 047fa800 adr z0\.d, \[z0\.d, z31\.d, uxtw #2\]
--.*: 047fa800 adr z0\.d, \[z0\.d, z31\.d, uxtw #2\]
--.*: 0460ac00 adr z0\.d, \[z0\.d, z0\.d, uxtw #3\]
--.*: 0460ac00 adr z0\.d, \[z0\.d, z0\.d, uxtw #3\]
--.*: 0460ac01 adr z1\.d, \[z0\.d, z0\.d, uxtw #3\]
--.*: 0460ac01 adr z1\.d, \[z0\.d, z0\.d, uxtw #3\]
--.*: 0460ac1f adr z31\.d, \[z0\.d, z0\.d, uxtw #3\]
--.*: 0460ac1f adr z31\.d, \[z0\.d, z0\.d, uxtw #3\]
--.*: 0460ac40 adr z0\.d, \[z2\.d, z0\.d, uxtw #3\]
--.*: 0460ac40 adr z0\.d, \[z2\.d, z0\.d, uxtw #3\]
--.*: 0460afe0 adr z0\.d, \[z31\.d, z0\.d, uxtw #3\]
--.*: 0460afe0 adr z0\.d, \[z31\.d, z0\.d, uxtw #3\]
--.*: 0463ac00 adr z0\.d, \[z0\.d, z3\.d, uxtw #3\]
--.*: 0463ac00 adr z0\.d, \[z0\.d, z3\.d, uxtw #3\]
--.*: 047fac00 adr z0\.d, \[z0\.d, z31\.d, uxtw #3\]
--.*: 047fac00 adr z0\.d, \[z0\.d, z31\.d, uxtw #3\]
--.*: 04a0a000 adr z0\.s, \[z0\.s, z0\.s\]
--.*: 04a0a000 adr z0\.s, \[z0\.s, z0\.s\]
--.*: 04a0a000 adr z0\.s, \[z0\.s, z0\.s\]
--.*: 04a0a001 adr z1\.s, \[z0\.s, z0\.s\]
--.*: 04a0a001 adr z1\.s, \[z0\.s, z0\.s\]
--.*: 04a0a001 adr z1\.s, \[z0\.s, z0\.s\]
--.*: 04a0a01f adr z31\.s, \[z0\.s, z0\.s\]
--.*: 04a0a01f adr z31\.s, \[z0\.s, z0\.s\]
--.*: 04a0a01f adr z31\.s, \[z0\.s, z0\.s\]
--.*: 04a0a040 adr z0\.s, \[z2\.s, z0\.s\]
--.*: 04a0a040 adr z0\.s, \[z2\.s, z0\.s\]
--.*: 04a0a040 adr z0\.s, \[z2\.s, z0\.s\]
--.*: 04a0a3e0 adr z0\.s, \[z31\.s, z0\.s\]
--.*: 04a0a3e0 adr z0\.s, \[z31\.s, z0\.s\]
--.*: 04a0a3e0 adr z0\.s, \[z31\.s, z0\.s\]
--.*: 04a3a000 adr z0\.s, \[z0\.s, z3\.s\]
--.*: 04a3a000 adr z0\.s, \[z0\.s, z3\.s\]
--.*: 04a3a000 adr z0\.s, \[z0\.s, z3\.s\]
--.*: 04bfa000 adr z0\.s, \[z0\.s, z31\.s\]
--.*: 04bfa000 adr z0\.s, \[z0\.s, z31\.s\]
--.*: 04bfa000 adr z0\.s, \[z0\.s, z31\.s\]
--.*: 04a0a400 adr z0\.s, \[z0\.s, z0\.s, lsl #1\]
--.*: 04a0a400 adr z0\.s, \[z0\.s, z0\.s, lsl #1\]
--.*: 04a0a401 adr z1\.s, \[z0\.s, z0\.s, lsl #1\]
--.*: 04a0a401 adr z1\.s, \[z0\.s, z0\.s, lsl #1\]
--.*: 04a0a41f adr z31\.s, \[z0\.s, z0\.s, lsl #1\]
--.*: 04a0a41f adr z31\.s, \[z0\.s, z0\.s, lsl #1\]
--.*: 04a0a440 adr z0\.s, \[z2\.s, z0\.s, lsl #1\]
--.*: 04a0a440 adr z0\.s, \[z2\.s, z0\.s, lsl #1\]
--.*: 04a0a7e0 adr z0\.s, \[z31\.s, z0\.s, lsl #1\]
--.*: 04a0a7e0 adr z0\.s, \[z31\.s, z0\.s, lsl #1\]
--.*: 04a3a400 adr z0\.s, \[z0\.s, z3\.s, lsl #1\]
--.*: 04a3a400 adr z0\.s, \[z0\.s, z3\.s, lsl #1\]
--.*: 04bfa400 adr z0\.s, \[z0\.s, z31\.s, lsl #1\]
--.*: 04bfa400 adr z0\.s, \[z0\.s, z31\.s, lsl #1\]
--.*: 04a0a800 adr z0\.s, \[z0\.s, z0\.s, lsl #2\]
--.*: 04a0a800 adr z0\.s, \[z0\.s, z0\.s, lsl #2\]
--.*: 04a0a801 adr z1\.s, \[z0\.s, z0\.s, lsl #2\]
--.*: 04a0a801 adr z1\.s, \[z0\.s, z0\.s, lsl #2\]
--.*: 04a0a81f adr z31\.s, \[z0\.s, z0\.s, lsl #2\]
--.*: 04a0a81f adr z31\.s, \[z0\.s, z0\.s, lsl #2\]
--.*: 04a0a840 adr z0\.s, \[z2\.s, z0\.s, lsl #2\]
--.*: 04a0a840 adr z0\.s, \[z2\.s, z0\.s, lsl #2\]
--.*: 04a0abe0 adr z0\.s, \[z31\.s, z0\.s, lsl #2\]
--.*: 04a0abe0 adr z0\.s, \[z31\.s, z0\.s, lsl #2\]
--.*: 04a3a800 adr z0\.s, \[z0\.s, z3\.s, lsl #2\]
--.*: 04a3a800 adr z0\.s, \[z0\.s, z3\.s, lsl #2\]
--.*: 04bfa800 adr z0\.s, \[z0\.s, z31\.s, lsl #2\]
--.*: 04bfa800 adr z0\.s, \[z0\.s, z31\.s, lsl #2\]
--.*: 04a0ac00 adr z0\.s, \[z0\.s, z0\.s, lsl #3\]
--.*: 04a0ac00 adr z0\.s, \[z0\.s, z0\.s, lsl #3\]
--.*: 04a0ac01 adr z1\.s, \[z0\.s, z0\.s, lsl #3\]
--.*: 04a0ac01 adr z1\.s, \[z0\.s, z0\.s, lsl #3\]
--.*: 04a0ac1f adr z31\.s, \[z0\.s, z0\.s, lsl #3\]
--.*: 04a0ac1f adr z31\.s, \[z0\.s, z0\.s, lsl #3\]
--.*: 04a0ac40 adr z0\.s, \[z2\.s, z0\.s, lsl #3\]
--.*: 04a0ac40 adr z0\.s, \[z2\.s, z0\.s, lsl #3\]
--.*: 04a0afe0 adr z0\.s, \[z31\.s, z0\.s, lsl #3\]
--.*: 04a0afe0 adr z0\.s, \[z31\.s, z0\.s, lsl #3\]
--.*: 04a3ac00 adr z0\.s, \[z0\.s, z3\.s, lsl #3\]
--.*: 04a3ac00 adr z0\.s, \[z0\.s, z3\.s, lsl #3\]
--.*: 04bfac00 adr z0\.s, \[z0\.s, z31\.s, lsl #3\]
--.*: 04bfac00 adr z0\.s, \[z0\.s, z31\.s, lsl #3\]
--.*: 04e0a000 adr z0\.d, \[z0\.d, z0\.d\]
--.*: 04e0a000 adr z0\.d, \[z0\.d, z0\.d\]
--.*: 04e0a000 adr z0\.d, \[z0\.d, z0\.d\]
--.*: 04e0a001 adr z1\.d, \[z0\.d, z0\.d\]
--.*: 04e0a001 adr z1\.d, \[z0\.d, z0\.d\]
--.*: 04e0a001 adr z1\.d, \[z0\.d, z0\.d\]
--.*: 04e0a01f adr z31\.d, \[z0\.d, z0\.d\]
--.*: 04e0a01f adr z31\.d, \[z0\.d, z0\.d\]
--.*: 04e0a01f adr z31\.d, \[z0\.d, z0\.d\]
--.*: 04e0a040 adr z0\.d, \[z2\.d, z0\.d\]
--.*: 04e0a040 adr z0\.d, \[z2\.d, z0\.d\]
--.*: 04e0a040 adr z0\.d, \[z2\.d, z0\.d\]
--.*: 04e0a3e0 adr z0\.d, \[z31\.d, z0\.d\]
--.*: 04e0a3e0 adr z0\.d, \[z31\.d, z0\.d\]
--.*: 04e0a3e0 adr z0\.d, \[z31\.d, z0\.d\]
--.*: 04e3a000 adr z0\.d, \[z0\.d, z3\.d\]
--.*: 04e3a000 adr z0\.d, \[z0\.d, z3\.d\]
--.*: 04e3a000 adr z0\.d, \[z0\.d, z3\.d\]
--.*: 04ffa000 adr z0\.d, \[z0\.d, z31\.d\]
--.*: 04ffa000 adr z0\.d, \[z0\.d, z31\.d\]
--.*: 04ffa000 adr z0\.d, \[z0\.d, z31\.d\]
--.*: 04e0a400 adr z0\.d, \[z0\.d, z0\.d, lsl #1\]
--.*: 04e0a400 adr z0\.d, \[z0\.d, z0\.d, lsl #1\]
--.*: 04e0a401 adr z1\.d, \[z0\.d, z0\.d, lsl #1\]
--.*: 04e0a401 adr z1\.d, \[z0\.d, z0\.d, lsl #1\]
--.*: 04e0a41f adr z31\.d, \[z0\.d, z0\.d, lsl #1\]
--.*: 04e0a41f adr z31\.d, \[z0\.d, z0\.d, lsl #1\]
--.*: 04e0a440 adr z0\.d, \[z2\.d, z0\.d, lsl #1\]
--.*: 04e0a440 adr z0\.d, \[z2\.d, z0\.d, lsl #1\]
--.*: 04e0a7e0 adr z0\.d, \[z31\.d, z0\.d, lsl #1\]
--.*: 04e0a7e0 adr z0\.d, \[z31\.d, z0\.d, lsl #1\]
--.*: 04e3a400 adr z0\.d, \[z0\.d, z3\.d, lsl #1\]
--.*: 04e3a400 adr z0\.d, \[z0\.d, z3\.d, lsl #1\]
--.*: 04ffa400 adr z0\.d, \[z0\.d, z31\.d, lsl #1\]
--.*: 04ffa400 adr z0\.d, \[z0\.d, z31\.d, lsl #1\]
--.*: 04e0a800 adr z0\.d, \[z0\.d, z0\.d, lsl #2\]
--.*: 04e0a800 adr z0\.d, \[z0\.d, z0\.d, lsl #2\]
--.*: 04e0a801 adr z1\.d, \[z0\.d, z0\.d, lsl #2\]
--.*: 04e0a801 adr z1\.d, \[z0\.d, z0\.d, lsl #2\]
--.*: 04e0a81f adr z31\.d, \[z0\.d, z0\.d, lsl #2\]
--.*: 04e0a81f adr z31\.d, \[z0\.d, z0\.d, lsl #2\]
--.*: 04e0a840 adr z0\.d, \[z2\.d, z0\.d, lsl #2\]
--.*: 04e0a840 adr z0\.d, \[z2\.d, z0\.d, lsl #2\]
--.*: 04e0abe0 adr z0\.d, \[z31\.d, z0\.d, lsl #2\]
--.*: 04e0abe0 adr z0\.d, \[z31\.d, z0\.d, lsl #2\]
--.*: 04e3a800 adr z0\.d, \[z0\.d, z3\.d, lsl #2\]
--.*: 04e3a800 adr z0\.d, \[z0\.d, z3\.d, lsl #2\]
--.*: 04ffa800 adr z0\.d, \[z0\.d, z31\.d, lsl #2\]
--.*: 04ffa800 adr z0\.d, \[z0\.d, z31\.d, lsl #2\]
--.*: 04e0ac00 adr z0\.d, \[z0\.d, z0\.d, lsl #3\]
--.*: 04e0ac00 adr z0\.d, \[z0\.d, z0\.d, lsl #3\]
--.*: 04e0ac01 adr z1\.d, \[z0\.d, z0\.d, lsl #3\]
--.*: 04e0ac01 adr z1\.d, \[z0\.d, z0\.d, lsl #3\]
--.*: 04e0ac1f adr z31\.d, \[z0\.d, z0\.d, lsl #3\]
--.*: 04e0ac1f adr z31\.d, \[z0\.d, z0\.d, lsl #3\]
--.*: 04e0ac40 adr z0\.d, \[z2\.d, z0\.d, lsl #3\]
--.*: 04e0ac40 adr z0\.d, \[z2\.d, z0\.d, lsl #3\]
--.*: 04e0afe0 adr z0\.d, \[z31\.d, z0\.d, lsl #3\]
--.*: 04e0afe0 adr z0\.d, \[z31\.d, z0\.d, lsl #3\]
--.*: 04e3ac00 adr z0\.d, \[z0\.d, z3\.d, lsl #3\]
--.*: 04e3ac00 adr z0\.d, \[z0\.d, z3\.d, lsl #3\]
--.*: 04ffac00 adr z0\.d, \[z0\.d, z31\.d, lsl #3\]
--.*: 04ffac00 adr z0\.d, \[z0\.d, z31\.d, lsl #3\]
--.*: 04203000 and z0\.d, z0\.d, z0\.d
--.*: 04203000 and z0\.d, z0\.d, z0\.d
--.*: 04203001 and z1\.d, z0\.d, z0\.d
--.*: 04203001 and z1\.d, z0\.d, z0\.d
--.*: 0420301f and z31\.d, z0\.d, z0\.d
--.*: 0420301f and z31\.d, z0\.d, z0\.d
--.*: 04203040 and z0\.d, z2\.d, z0\.d
--.*: 04203040 and z0\.d, z2\.d, z0\.d
--.*: 042033e0 and z0\.d, z31\.d, z0\.d
--.*: 042033e0 and z0\.d, z31\.d, z0\.d
--.*: 04233000 and z0\.d, z0\.d, z3\.d
--.*: 04233000 and z0\.d, z0\.d, z3\.d
--.*: 043f3000 and z0\.d, z0\.d, z31\.d
--.*: 043f3000 and z0\.d, z0\.d, z31\.d
--.*: 05800000 and z0\.s, z0\.s, #0x1
--.*: 05800000 and z0\.s, z0\.s, #0x1
--.*: 05800000 and z0\.s, z0\.s, #0x1
--.*: 05800001 and z1\.s, z1\.s, #0x1
--.*: 05800001 and z1\.s, z1\.s, #0x1
--.*: 05800001 and z1\.s, z1\.s, #0x1
--.*: 0580001f and z31\.s, z31\.s, #0x1
--.*: 0580001f and z31\.s, z31\.s, #0x1
--.*: 0580001f and z31\.s, z31\.s, #0x1
--.*: 05800002 and z2\.s, z2\.s, #0x1
--.*: 05800002 and z2\.s, z2\.s, #0x1
--.*: 05800002 and z2\.s, z2\.s, #0x1
--.*: 058000c0 and z0\.s, z0\.s, #0x7f
--.*: 058000c0 and z0\.s, z0\.s, #0x7f
--.*: 058000c0 and z0\.s, z0\.s, #0x7f
--.*: 058003c0 and z0\.s, z0\.s, #0x7fffffff
--.*: 058003c0 and z0\.s, z0\.s, #0x7fffffff
--.*: 058003c0 and z0\.s, z0\.s, #0x7fffffff
--.*: 05800400 and z0\.h, z0\.h, #0x1
--.*: 05800400 and z0\.h, z0\.h, #0x1
--.*: 05800400 and z0\.h, z0\.h, #0x1
--.*: 05800400 and z0\.h, z0\.h, #0x1
--.*: 058005c0 and z0\.h, z0\.h, #0x7fff
--.*: 058005c0 and z0\.h, z0\.h, #0x7fff
--.*: 058005c0 and z0\.h, z0\.h, #0x7fff
--.*: 058005c0 and z0\.h, z0\.h, #0x7fff
--.*: 05800600 and z0\.b, z0\.b, #0x1
--.*: 05800600 and z0\.b, z0\.b, #0x1
--.*: 05800600 and z0\.b, z0\.b, #0x1
--.*: 05800600 and z0\.b, z0\.b, #0x1
--.*: 05800600 and z0\.b, z0\.b, #0x1
--.*: 05800780 and z0\.b, z0\.b, #0x55
--.*: 05800780 and z0\.b, z0\.b, #0x55
--.*: 05800780 and z0\.b, z0\.b, #0x55
--.*: 05800780 and z0\.b, z0\.b, #0x55
--.*: 05800780 and z0\.b, z0\.b, #0x55
--.*: 05800800 and z0\.s, z0\.s, #0x80000000
--.*: 05800800 and z0\.s, z0\.s, #0x80000000
--.*: 05800800 and z0\.s, z0\.s, #0x80000000
--.*: 05800bc0 and z0\.s, z0\.s, #0xbfffffff
--.*: 05800bc0 and z0\.s, z0\.s, #0xbfffffff
--.*: 05800bc0 and z0\.s, z0\.s, #0xbfffffff
--.*: 05800c00 and z0\.h, z0\.h, #0x8000
--.*: 05800c00 and z0\.h, z0\.h, #0x8000
--.*: 05800c00 and z0\.h, z0\.h, #0x8000
--.*: 05800c00 and z0\.h, z0\.h, #0x8000
--.*: 05800ec0 and z0\.b, z0\.b, #0xbf
--.*: 05800ec0 and z0\.b, z0\.b, #0xbf
--.*: 05800ec0 and z0\.b, z0\.b, #0xbf
--.*: 05800ec0 and z0\.b, z0\.b, #0xbf
--.*: 05800ec0 and z0\.b, z0\.b, #0xbf
--.*: 05801e80 and z0\.b, z0\.b, #0xe3
--.*: 05801e80 and z0\.b, z0\.b, #0xe3
--.*: 05801e80 and z0\.b, z0\.b, #0xe3
--.*: 05801e80 and z0\.b, z0\.b, #0xe3
--.*: 05801e80 and z0\.b, z0\.b, #0xe3
--.*: 0580bbc0 and z0\.s, z0\.s, #0xfffffeff
--.*: 0580bbc0 and z0\.s, z0\.s, #0xfffffeff
--.*: 0580bbc0 and z0\.s, z0\.s, #0xfffffeff
--.*: 0583ffc0 and z0\.d, z0\.d, #0xfffffffffffffffe
--.*: 0583ffc0 and z0\.d, z0\.d, #0xfffffffffffffffe
--.*: 041a0000 and z0\.b, p0/m, z0\.b, z0\.b
--.*: 041a0000 and z0\.b, p0/m, z0\.b, z0\.b
--.*: 041a0001 and z1\.b, p0/m, z1\.b, z0\.b
--.*: 041a0001 and z1\.b, p0/m, z1\.b, z0\.b
--.*: 041a001f and z31\.b, p0/m, z31\.b, z0\.b
--.*: 041a001f and z31\.b, p0/m, z31\.b, z0\.b
--.*: 041a0800 and z0\.b, p2/m, z0\.b, z0\.b
--.*: 041a0800 and z0\.b, p2/m, z0\.b, z0\.b
--.*: 041a1c00 and z0\.b, p7/m, z0\.b, z0\.b
--.*: 041a1c00 and z0\.b, p7/m, z0\.b, z0\.b
--.*: 041a0003 and z3\.b, p0/m, z3\.b, z0\.b
--.*: 041a0003 and z3\.b, p0/m, z3\.b, z0\.b
--.*: 041a0080 and z0\.b, p0/m, z0\.b, z4\.b
--.*: 041a0080 and z0\.b, p0/m, z0\.b, z4\.b
--.*: 041a03e0 and z0\.b, p0/m, z0\.b, z31\.b
--.*: 041a03e0 and z0\.b, p0/m, z0\.b, z31\.b
--.*: 045a0000 and z0\.h, p0/m, z0\.h, z0\.h
--.*: 045a0000 and z0\.h, p0/m, z0\.h, z0\.h
--.*: 045a0001 and z1\.h, p0/m, z1\.h, z0\.h
--.*: 045a0001 and z1\.h, p0/m, z1\.h, z0\.h
--.*: 045a001f and z31\.h, p0/m, z31\.h, z0\.h
--.*: 045a001f and z31\.h, p0/m, z31\.h, z0\.h
--.*: 045a0800 and z0\.h, p2/m, z0\.h, z0\.h
--.*: 045a0800 and z0\.h, p2/m, z0\.h, z0\.h
--.*: 045a1c00 and z0\.h, p7/m, z0\.h, z0\.h
--.*: 045a1c00 and z0\.h, p7/m, z0\.h, z0\.h
--.*: 045a0003 and z3\.h, p0/m, z3\.h, z0\.h
--.*: 045a0003 and z3\.h, p0/m, z3\.h, z0\.h
--.*: 045a0080 and z0\.h, p0/m, z0\.h, z4\.h
--.*: 045a0080 and z0\.h, p0/m, z0\.h, z4\.h
--.*: 045a03e0 and z0\.h, p0/m, z0\.h, z31\.h
--.*: 045a03e0 and z0\.h, p0/m, z0\.h, z31\.h
--.*: 049a0000 and z0\.s, p0/m, z0\.s, z0\.s
--.*: 049a0000 and z0\.s, p0/m, z0\.s, z0\.s
--.*: 049a0001 and z1\.s, p0/m, z1\.s, z0\.s
--.*: 049a0001 and z1\.s, p0/m, z1\.s, z0\.s
--.*: 049a001f and z31\.s, p0/m, z31\.s, z0\.s
--.*: 049a001f and z31\.s, p0/m, z31\.s, z0\.s
--.*: 049a0800 and z0\.s, p2/m, z0\.s, z0\.s
--.*: 049a0800 and z0\.s, p2/m, z0\.s, z0\.s
--.*: 049a1c00 and z0\.s, p7/m, z0\.s, z0\.s
--.*: 049a1c00 and z0\.s, p7/m, z0\.s, z0\.s
--.*: 049a0003 and z3\.s, p0/m, z3\.s, z0\.s
--.*: 049a0003 and z3\.s, p0/m, z3\.s, z0\.s
--.*: 049a0080 and z0\.s, p0/m, z0\.s, z4\.s
--.*: 049a0080 and z0\.s, p0/m, z0\.s, z4\.s
--.*: 049a03e0 and z0\.s, p0/m, z0\.s, z31\.s
--.*: 049a03e0 and z0\.s, p0/m, z0\.s, z31\.s
--.*: 04da0000 and z0\.d, p0/m, z0\.d, z0\.d
--.*: 04da0000 and z0\.d, p0/m, z0\.d, z0\.d
--.*: 04da0001 and z1\.d, p0/m, z1\.d, z0\.d
--.*: 04da0001 and z1\.d, p0/m, z1\.d, z0\.d
--.*: 04da001f and z31\.d, p0/m, z31\.d, z0\.d
--.*: 04da001f and z31\.d, p0/m, z31\.d, z0\.d
--.*: 04da0800 and z0\.d, p2/m, z0\.d, z0\.d
--.*: 04da0800 and z0\.d, p2/m, z0\.d, z0\.d
--.*: 04da1c00 and z0\.d, p7/m, z0\.d, z0\.d
--.*: 04da1c00 and z0\.d, p7/m, z0\.d, z0\.d
--.*: 04da0003 and z3\.d, p0/m, z3\.d, z0\.d
--.*: 04da0003 and z3\.d, p0/m, z3\.d, z0\.d
--.*: 04da0080 and z0\.d, p0/m, z0\.d, z4\.d
--.*: 04da0080 and z0\.d, p0/m, z0\.d, z4\.d
--.*: 04da03e0 and z0\.d, p0/m, z0\.d, z31\.d
--.*: 04da03e0 and z0\.d, p0/m, z0\.d, z31\.d
--.*: 25004000 mov p0\.b, p0/z, p0\.b
--.*: 25004000 mov p0\.b, p0/z, p0\.b
--.*: 25004001 mov p1\.b, p0/z, p0\.b
--.*: 25004001 mov p1\.b, p0/z, p0\.b
--.*: 2500400f mov p15\.b, p0/z, p0\.b
--.*: 2500400f mov p15\.b, p0/z, p0\.b
--.*: 25004800 mov p0\.b, p2/z, p0\.b
--.*: 25004800 mov p0\.b, p2/z, p0\.b
--.*: 25007c00 mov p0\.b, p15/z, p0\.b
--.*: 25007c00 mov p0\.b, p15/z, p0\.b
--.*: 25004060 and p0\.b, p0/z, p3\.b, p0\.b
--.*: 25004060 and p0\.b, p0/z, p3\.b, p0\.b
--.*: 250041e0 and p0\.b, p0/z, p15\.b, p0\.b
--.*: 250041e0 and p0\.b, p0/z, p15\.b, p0\.b
--.*: 25044000 and p0\.b, p0/z, p0\.b, p4\.b
--.*: 25044000 and p0\.b, p0/z, p0\.b, p4\.b
--.*: 250f4000 and p0\.b, p0/z, p0\.b, p15\.b
--.*: 250f4000 and p0\.b, p0/z, p0\.b, p15\.b
--.*: 25404000 movs p0\.b, p0/z, p0\.b
--.*: 25404000 movs p0\.b, p0/z, p0\.b
--.*: 25404001 movs p1\.b, p0/z, p0\.b
--.*: 25404001 movs p1\.b, p0/z, p0\.b
--.*: 2540400f movs p15\.b, p0/z, p0\.b
--.*: 2540400f movs p15\.b, p0/z, p0\.b
--.*: 25404800 movs p0\.b, p2/z, p0\.b
--.*: 25404800 movs p0\.b, p2/z, p0\.b
--.*: 25407c00 movs p0\.b, p15/z, p0\.b
--.*: 25407c00 movs p0\.b, p15/z, p0\.b
--.*: 25404060 ands p0\.b, p0/z, p3\.b, p0\.b
--.*: 25404060 ands p0\.b, p0/z, p3\.b, p0\.b
--.*: 254041e0 ands p0\.b, p0/z, p15\.b, p0\.b
--.*: 254041e0 ands p0\.b, p0/z, p15\.b, p0\.b
--.*: 25444000 ands p0\.b, p0/z, p0\.b, p4\.b
--.*: 25444000 ands p0\.b, p0/z, p0\.b, p4\.b
--.*: 254f4000 ands p0\.b, p0/z, p0\.b, p15\.b
--.*: 254f4000 ands p0\.b, p0/z, p0\.b, p15\.b
--.*: 041a2000 andv b0, p0, z0\.b
--.*: 041a2000 andv b0, p0, z0\.b
--.*: 041a2001 andv b1, p0, z0\.b
--.*: 041a2001 andv b1, p0, z0\.b
--.*: 041a201f andv b31, p0, z0\.b
--.*: 041a201f andv b31, p0, z0\.b
--.*: 041a2800 andv b0, p2, z0\.b
--.*: 041a2800 andv b0, p2, z0\.b
--.*: 041a3c00 andv b0, p7, z0\.b
--.*: 041a3c00 andv b0, p7, z0\.b
--.*: 041a2060 andv b0, p0, z3\.b
--.*: 041a2060 andv b0, p0, z3\.b
--.*: 041a23e0 andv b0, p0, z31\.b
--.*: 041a23e0 andv b0, p0, z31\.b
--.*: 045a2000 andv h0, p0, z0\.h
--.*: 045a2000 andv h0, p0, z0\.h
--.*: 045a2001 andv h1, p0, z0\.h
--.*: 045a2001 andv h1, p0, z0\.h
--.*: 045a201f andv h31, p0, z0\.h
--.*: 045a201f andv h31, p0, z0\.h
--.*: 045a2800 andv h0, p2, z0\.h
--.*: 045a2800 andv h0, p2, z0\.h
--.*: 045a3c00 andv h0, p7, z0\.h
--.*: 045a3c00 andv h0, p7, z0\.h
--.*: 045a2060 andv h0, p0, z3\.h
--.*: 045a2060 andv h0, p0, z3\.h
--.*: 045a23e0 andv h0, p0, z31\.h
--.*: 045a23e0 andv h0, p0, z31\.h
--.*: 049a2000 andv s0, p0, z0\.s
--.*: 049a2000 andv s0, p0, z0\.s
--.*: 049a2001 andv s1, p0, z0\.s
--.*: 049a2001 andv s1, p0, z0\.s
--.*: 049a201f andv s31, p0, z0\.s
--.*: 049a201f andv s31, p0, z0\.s
--.*: 049a2800 andv s0, p2, z0\.s
--.*: 049a2800 andv s0, p2, z0\.s
--.*: 049a3c00 andv s0, p7, z0\.s
--.*: 049a3c00 andv s0, p7, z0\.s
--.*: 049a2060 andv s0, p0, z3\.s
--.*: 049a2060 andv s0, p0, z3\.s
--.*: 049a23e0 andv s0, p0, z31\.s
--.*: 049a23e0 andv s0, p0, z31\.s
--.*: 04da2000 andv d0, p0, z0\.d
--.*: 04da2000 andv d0, p0, z0\.d
--.*: 04da2001 andv d1, p0, z0\.d
--.*: 04da2001 andv d1, p0, z0\.d
--.*: 04da201f andv d31, p0, z0\.d
--.*: 04da201f andv d31, p0, z0\.d
--.*: 04da2800 andv d0, p2, z0\.d
--.*: 04da2800 andv d0, p2, z0\.d
--.*: 04da3c00 andv d0, p7, z0\.d
--.*: 04da3c00 andv d0, p7, z0\.d
--.*: 04da2060 andv d0, p0, z3\.d
--.*: 04da2060 andv d0, p0, z3\.d
--.*: 04da23e0 andv d0, p0, z31\.d
--.*: 04da23e0 andv d0, p0, z31\.d
--.*: 04208000 asr z0\.b, z0\.b, z0\.d
--.*: 04208000 asr z0\.b, z0\.b, z0\.d
--.*: 04208001 asr z1\.b, z0\.b, z0\.d
--.*: 04208001 asr z1\.b, z0\.b, z0\.d
--.*: 0420801f asr z31\.b, z0\.b, z0\.d
--.*: 0420801f asr z31\.b, z0\.b, z0\.d
--.*: 04208040 asr z0\.b, z2\.b, z0\.d
--.*: 04208040 asr z0\.b, z2\.b, z0\.d
--.*: 042083e0 asr z0\.b, z31\.b, z0\.d
--.*: 042083e0 asr z0\.b, z31\.b, z0\.d
--.*: 04238000 asr z0\.b, z0\.b, z3\.d
--.*: 04238000 asr z0\.b, z0\.b, z3\.d
--.*: 043f8000 asr z0\.b, z0\.b, z31\.d
--.*: 043f8000 asr z0\.b, z0\.b, z31\.d
--.*: 04608000 asr z0\.h, z0\.h, z0\.d
--.*: 04608000 asr z0\.h, z0\.h, z0\.d
--.*: 04608001 asr z1\.h, z0\.h, z0\.d
--.*: 04608001 asr z1\.h, z0\.h, z0\.d
--.*: 0460801f asr z31\.h, z0\.h, z0\.d
--.*: 0460801f asr z31\.h, z0\.h, z0\.d
--.*: 04608040 asr z0\.h, z2\.h, z0\.d
--.*: 04608040 asr z0\.h, z2\.h, z0\.d
--.*: 046083e0 asr z0\.h, z31\.h, z0\.d
--.*: 046083e0 asr z0\.h, z31\.h, z0\.d
--.*: 04638000 asr z0\.h, z0\.h, z3\.d
--.*: 04638000 asr z0\.h, z0\.h, z3\.d
--.*: 047f8000 asr z0\.h, z0\.h, z31\.d
--.*: 047f8000 asr z0\.h, z0\.h, z31\.d
--.*: 04a08000 asr z0\.s, z0\.s, z0\.d
--.*: 04a08000 asr z0\.s, z0\.s, z0\.d
--.*: 04a08001 asr z1\.s, z0\.s, z0\.d
--.*: 04a08001 asr z1\.s, z0\.s, z0\.d
--.*: 04a0801f asr z31\.s, z0\.s, z0\.d
--.*: 04a0801f asr z31\.s, z0\.s, z0\.d
--.*: 04a08040 asr z0\.s, z2\.s, z0\.d
--.*: 04a08040 asr z0\.s, z2\.s, z0\.d
--.*: 04a083e0 asr z0\.s, z31\.s, z0\.d
--.*: 04a083e0 asr z0\.s, z31\.s, z0\.d
--.*: 04a38000 asr z0\.s, z0\.s, z3\.d
--.*: 04a38000 asr z0\.s, z0\.s, z3\.d
--.*: 04bf8000 asr z0\.s, z0\.s, z31\.d
--.*: 04bf8000 asr z0\.s, z0\.s, z31\.d
--.*: 04289000 asr z0\.b, z0\.b, #8
--.*: 04289000 asr z0\.b, z0\.b, #8
--.*: 04289001 asr z1\.b, z0\.b, #8
--.*: 04289001 asr z1\.b, z0\.b, #8
--.*: 0428901f asr z31\.b, z0\.b, #8
--.*: 0428901f asr z31\.b, z0\.b, #8
--.*: 04289040 asr z0\.b, z2\.b, #8
--.*: 04289040 asr z0\.b, z2\.b, #8
--.*: 042893e0 asr z0\.b, z31\.b, #8
--.*: 042893e0 asr z0\.b, z31\.b, #8
--.*: 04299000 asr z0\.b, z0\.b, #7
--.*: 04299000 asr z0\.b, z0\.b, #7
--.*: 042e9000 asr z0\.b, z0\.b, #2
--.*: 042e9000 asr z0\.b, z0\.b, #2
--.*: 042f9000 asr z0\.b, z0\.b, #1
--.*: 042f9000 asr z0\.b, z0\.b, #1
--.*: 04309000 asr z0\.h, z0\.h, #16
--.*: 04309000 asr z0\.h, z0\.h, #16
--.*: 04309001 asr z1\.h, z0\.h, #16
--.*: 04309001 asr z1\.h, z0\.h, #16
--.*: 0430901f asr z31\.h, z0\.h, #16
--.*: 0430901f asr z31\.h, z0\.h, #16
--.*: 04309040 asr z0\.h, z2\.h, #16
--.*: 04309040 asr z0\.h, z2\.h, #16
--.*: 043093e0 asr z0\.h, z31\.h, #16
--.*: 043093e0 asr z0\.h, z31\.h, #16
--.*: 04319000 asr z0\.h, z0\.h, #15
--.*: 04319000 asr z0\.h, z0\.h, #15
--.*: 043e9000 asr z0\.h, z0\.h, #2
--.*: 043e9000 asr z0\.h, z0\.h, #2
--.*: 043f9000 asr z0\.h, z0\.h, #1
--.*: 043f9000 asr z0\.h, z0\.h, #1
--.*: 04389000 asr z0\.h, z0\.h, #8
--.*: 04389000 asr z0\.h, z0\.h, #8
--.*: 04389001 asr z1\.h, z0\.h, #8
--.*: 04389001 asr z1\.h, z0\.h, #8
--.*: 0438901f asr z31\.h, z0\.h, #8
--.*: 0438901f asr z31\.h, z0\.h, #8
--.*: 04389040 asr z0\.h, z2\.h, #8
--.*: 04389040 asr z0\.h, z2\.h, #8
--.*: 043893e0 asr z0\.h, z31\.h, #8
--.*: 043893e0 asr z0\.h, z31\.h, #8
--.*: 04399000 asr z0\.h, z0\.h, #7
--.*: 04399000 asr z0\.h, z0\.h, #7
--.*: 046e9000 asr z0\.s, z0\.s, #18
--.*: 046e9000 asr z0\.s, z0\.s, #18
--.*: 046f9000 asr z0\.s, z0\.s, #17
--.*: 046f9000 asr z0\.s, z0\.s, #17
--.*: 04609000 asr z0\.s, z0\.s, #32
--.*: 04609000 asr z0\.s, z0\.s, #32
--.*: 04609001 asr z1\.s, z0\.s, #32
--.*: 04609001 asr z1\.s, z0\.s, #32
--.*: 0460901f asr z31\.s, z0\.s, #32
--.*: 0460901f asr z31\.s, z0\.s, #32
--.*: 04609040 asr z0\.s, z2\.s, #32
--.*: 04609040 asr z0\.s, z2\.s, #32
--.*: 046093e0 asr z0\.s, z31\.s, #32
--.*: 046093e0 asr z0\.s, z31\.s, #32
--.*: 04619000 asr z0\.s, z0\.s, #31
--.*: 04619000 asr z0\.s, z0\.s, #31
--.*: 047e9000 asr z0\.s, z0\.s, #2
--.*: 047e9000 asr z0\.s, z0\.s, #2
--.*: 047f9000 asr z0\.s, z0\.s, #1
--.*: 047f9000 asr z0\.s, z0\.s, #1
--.*: 04689000 asr z0\.s, z0\.s, #24
--.*: 04689000 asr z0\.s, z0\.s, #24
--.*: 04689001 asr z1\.s, z0\.s, #24
--.*: 04689001 asr z1\.s, z0\.s, #24
--.*: 0468901f asr z31\.s, z0\.s, #24
--.*: 0468901f asr z31\.s, z0\.s, #24
--.*: 04689040 asr z0\.s, z2\.s, #24
--.*: 04689040 asr z0\.s, z2\.s, #24
--.*: 046893e0 asr z0\.s, z31\.s, #24
--.*: 046893e0 asr z0\.s, z31\.s, #24
--.*: 04699000 asr z0\.s, z0\.s, #23
--.*: 04699000 asr z0\.s, z0\.s, #23
--.*: 04ae9000 asr z0\.d, z0\.d, #50
--.*: 04ae9000 asr z0\.d, z0\.d, #50
--.*: 04af9000 asr z0\.d, z0\.d, #49
--.*: 04af9000 asr z0\.d, z0\.d, #49
--.*: 04709000 asr z0\.s, z0\.s, #16
--.*: 04709000 asr z0\.s, z0\.s, #16
--.*: 04709001 asr z1\.s, z0\.s, #16
--.*: 04709001 asr z1\.s, z0\.s, #16
--.*: 0470901f asr z31\.s, z0\.s, #16
--.*: 0470901f asr z31\.s, z0\.s, #16
--.*: 04709040 asr z0\.s, z2\.s, #16
--.*: 04709040 asr z0\.s, z2\.s, #16
--.*: 047093e0 asr z0\.s, z31\.s, #16
--.*: 047093e0 asr z0\.s, z31\.s, #16
--.*: 04719000 asr z0\.s, z0\.s, #15
--.*: 04719000 asr z0\.s, z0\.s, #15
--.*: 04be9000 asr z0\.d, z0\.d, #34
--.*: 04be9000 asr z0\.d, z0\.d, #34
--.*: 04bf9000 asr z0\.d, z0\.d, #33
--.*: 04bf9000 asr z0\.d, z0\.d, #33
--.*: 04789000 asr z0\.s, z0\.s, #8
--.*: 04789000 asr z0\.s, z0\.s, #8
--.*: 04789001 asr z1\.s, z0\.s, #8
--.*: 04789001 asr z1\.s, z0\.s, #8
--.*: 0478901f asr z31\.s, z0\.s, #8
--.*: 0478901f asr z31\.s, z0\.s, #8
--.*: 04789040 asr z0\.s, z2\.s, #8
--.*: 04789040 asr z0\.s, z2\.s, #8
--.*: 047893e0 asr z0\.s, z31\.s, #8
--.*: 047893e0 asr z0\.s, z31\.s, #8
--.*: 04799000 asr z0\.s, z0\.s, #7
--.*: 04799000 asr z0\.s, z0\.s, #7
--.*: 04ee9000 asr z0\.d, z0\.d, #18
--.*: 04ee9000 asr z0\.d, z0\.d, #18
--.*: 04ef9000 asr z0\.d, z0\.d, #17
--.*: 04ef9000 asr z0\.d, z0\.d, #17
--.*: 04a09000 asr z0\.d, z0\.d, #64
--.*: 04a09000 asr z0\.d, z0\.d, #64
--.*: 04a09001 asr z1\.d, z0\.d, #64
--.*: 04a09001 asr z1\.d, z0\.d, #64
--.*: 04a0901f asr z31\.d, z0\.d, #64
--.*: 04a0901f asr z31\.d, z0\.d, #64
--.*: 04a09040 asr z0\.d, z2\.d, #64
--.*: 04a09040 asr z0\.d, z2\.d, #64
--.*: 04a093e0 asr z0\.d, z31\.d, #64
--.*: 04a093e0 asr z0\.d, z31\.d, #64
--.*: 04a19000 asr z0\.d, z0\.d, #63
--.*: 04a19000 asr z0\.d, z0\.d, #63
--.*: 04fe9000 asr z0\.d, z0\.d, #2
--.*: 04fe9000 asr z0\.d, z0\.d, #2
--.*: 04ff9000 asr z0\.d, z0\.d, #1
--.*: 04ff9000 asr z0\.d, z0\.d, #1
--.*: 04a89000 asr z0\.d, z0\.d, #56
--.*: 04a89000 asr z0\.d, z0\.d, #56
--.*: 04a89001 asr z1\.d, z0\.d, #56
--.*: 04a89001 asr z1\.d, z0\.d, #56
--.*: 04a8901f asr z31\.d, z0\.d, #56
--.*: 04a8901f asr z31\.d, z0\.d, #56
--.*: 04a89040 asr z0\.d, z2\.d, #56
--.*: 04a89040 asr z0\.d, z2\.d, #56
--.*: 04a893e0 asr z0\.d, z31\.d, #56
--.*: 04a893e0 asr z0\.d, z31\.d, #56
--.*: 04a99000 asr z0\.d, z0\.d, #55
--.*: 04a99000 asr z0\.d, z0\.d, #55
--.*: 04b09000 asr z0\.d, z0\.d, #48
--.*: 04b09000 asr z0\.d, z0\.d, #48
--.*: 04b09001 asr z1\.d, z0\.d, #48
--.*: 04b09001 asr z1\.d, z0\.d, #48
--.*: 04b0901f asr z31\.d, z0\.d, #48
--.*: 04b0901f asr z31\.d, z0\.d, #48
--.*: 04b09040 asr z0\.d, z2\.d, #48
--.*: 04b09040 asr z0\.d, z2\.d, #48
--.*: 04b093e0 asr z0\.d, z31\.d, #48
--.*: 04b093e0 asr z0\.d, z31\.d, #48
--.*: 04b19000 asr z0\.d, z0\.d, #47
--.*: 04b19000 asr z0\.d, z0\.d, #47
--.*: 04b89000 asr z0\.d, z0\.d, #40
--.*: 04b89000 asr z0\.d, z0\.d, #40
--.*: 04b89001 asr z1\.d, z0\.d, #40
--.*: 04b89001 asr z1\.d, z0\.d, #40
--.*: 04b8901f asr z31\.d, z0\.d, #40
--.*: 04b8901f asr z31\.d, z0\.d, #40
--.*: 04b89040 asr z0\.d, z2\.d, #40
--.*: 04b89040 asr z0\.d, z2\.d, #40
--.*: 04b893e0 asr z0\.d, z31\.d, #40
--.*: 04b893e0 asr z0\.d, z31\.d, #40
--.*: 04b99000 asr z0\.d, z0\.d, #39
--.*: 04b99000 asr z0\.d, z0\.d, #39
--.*: 04e09000 asr z0\.d, z0\.d, #32
--.*: 04e09000 asr z0\.d, z0\.d, #32
--.*: 04e09001 asr z1\.d, z0\.d, #32
--.*: 04e09001 asr z1\.d, z0\.d, #32
--.*: 04e0901f asr z31\.d, z0\.d, #32
--.*: 04e0901f asr z31\.d, z0\.d, #32
--.*: 04e09040 asr z0\.d, z2\.d, #32
--.*: 04e09040 asr z0\.d, z2\.d, #32
--.*: 04e093e0 asr z0\.d, z31\.d, #32
--.*: 04e093e0 asr z0\.d, z31\.d, #32
--.*: 04e19000 asr z0\.d, z0\.d, #31
--.*: 04e19000 asr z0\.d, z0\.d, #31
--.*: 04e89000 asr z0\.d, z0\.d, #24
--.*: 04e89000 asr z0\.d, z0\.d, #24
--.*: 04e89001 asr z1\.d, z0\.d, #24
--.*: 04e89001 asr z1\.d, z0\.d, #24
--.*: 04e8901f asr z31\.d, z0\.d, #24
--.*: 04e8901f asr z31\.d, z0\.d, #24
--.*: 04e89040 asr z0\.d, z2\.d, #24
--.*: 04e89040 asr z0\.d, z2\.d, #24
--.*: 04e893e0 asr z0\.d, z31\.d, #24
--.*: 04e893e0 asr z0\.d, z31\.d, #24
--.*: 04e99000 asr z0\.d, z0\.d, #23
--.*: 04e99000 asr z0\.d, z0\.d, #23
--.*: 04f09000 asr z0\.d, z0\.d, #16
--.*: 04f09000 asr z0\.d, z0\.d, #16
--.*: 04f09001 asr z1\.d, z0\.d, #16
--.*: 04f09001 asr z1\.d, z0\.d, #16
--.*: 04f0901f asr z31\.d, z0\.d, #16
--.*: 04f0901f asr z31\.d, z0\.d, #16
--.*: 04f09040 asr z0\.d, z2\.d, #16
--.*: 04f09040 asr z0\.d, z2\.d, #16
--.*: 04f093e0 asr z0\.d, z31\.d, #16
--.*: 04f093e0 asr z0\.d, z31\.d, #16
--.*: 04f19000 asr z0\.d, z0\.d, #15
--.*: 04f19000 asr z0\.d, z0\.d, #15
--.*: 04f89000 asr z0\.d, z0\.d, #8
--.*: 04f89000 asr z0\.d, z0\.d, #8
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--.*: 0480821f asr z31\.d, p0/m, z31\.d, #48
--.*: 0480821f asr z31\.d, p0/m, z31\.d, #48
--.*: 04808a00 asr z0\.d, p2/m, z0\.d, #48
--.*: 04808a00 asr z0\.d, p2/m, z0\.d, #48
--.*: 04809e00 asr z0\.d, p7/m, z0\.d, #48
--.*: 04809e00 asr z0\.d, p7/m, z0\.d, #48
--.*: 04808203 asr z3\.d, p0/m, z3\.d, #48
--.*: 04808203 asr z3\.d, p0/m, z3\.d, #48
--.*: 04808220 asr z0\.d, p0/m, z0\.d, #47
--.*: 04808220 asr z0\.d, p0/m, z0\.d, #47
--.*: 04808300 asr z0\.d, p0/m, z0\.d, #40
--.*: 04808300 asr z0\.d, p0/m, z0\.d, #40
--.*: 04808301 asr z1\.d, p0/m, z1\.d, #40
--.*: 04808301 asr z1\.d, p0/m, z1\.d, #40
--.*: 0480831f asr z31\.d, p0/m, z31\.d, #40
--.*: 0480831f asr z31\.d, p0/m, z31\.d, #40
--.*: 04808b00 asr z0\.d, p2/m, z0\.d, #40
--.*: 04808b00 asr z0\.d, p2/m, z0\.d, #40
--.*: 04809f00 asr z0\.d, p7/m, z0\.d, #40
--.*: 04809f00 asr z0\.d, p7/m, z0\.d, #40
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--.*: 04808303 asr z3\.d, p0/m, z3\.d, #40
--.*: 04808320 asr z0\.d, p0/m, z0\.d, #39
--.*: 04808320 asr z0\.d, p0/m, z0\.d, #39
--.*: 04c08000 asr z0\.d, p0/m, z0\.d, #32
--.*: 04c08000 asr z0\.d, p0/m, z0\.d, #32
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--.*: 04c08001 asr z1\.d, p0/m, z1\.d, #32
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--.*: 04c0801f asr z31\.d, p0/m, z31\.d, #32
--.*: 04c08800 asr z0\.d, p2/m, z0\.d, #32
--.*: 04c08800 asr z0\.d, p2/m, z0\.d, #32
--.*: 04c09c00 asr z0\.d, p7/m, z0\.d, #32
--.*: 04c09c00 asr z0\.d, p7/m, z0\.d, #32
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--.*: 04c08003 asr z3\.d, p0/m, z3\.d, #32
--.*: 04c08020 asr z0\.d, p0/m, z0\.d, #31
--.*: 04c08020 asr z0\.d, p0/m, z0\.d, #31
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--.*: 04c08100 asr z0\.d, p0/m, z0\.d, #24
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--.*: 04c08101 asr z1\.d, p0/m, z1\.d, #24
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--.*: 04c0811f asr z31\.d, p0/m, z31\.d, #24
--.*: 04c08900 asr z0\.d, p2/m, z0\.d, #24
--.*: 04c08900 asr z0\.d, p2/m, z0\.d, #24
--.*: 04c09d00 asr z0\.d, p7/m, z0\.d, #24
--.*: 04c09d00 asr z0\.d, p7/m, z0\.d, #24
--.*: 04c08103 asr z3\.d, p0/m, z3\.d, #24
--.*: 04c08103 asr z3\.d, p0/m, z3\.d, #24
--.*: 04c08120 asr z0\.d, p0/m, z0\.d, #23
--.*: 04c08120 asr z0\.d, p0/m, z0\.d, #23
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--.*: 04c0821f asr z31\.d, p0/m, z31\.d, #16
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--.*: 04048201 asrd z1\.h, p0/m, z1\.h, #16
--.*: 0404821f asrd z31\.h, p0/m, z31\.h, #16
--.*: 0404821f asrd z31\.h, p0/m, z31\.h, #16
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--.*: 04048a00 asrd z0\.h, p2/m, z0\.h, #16
--.*: 04049e00 asrd z0\.h, p7/m, z0\.h, #16
--.*: 04049e00 asrd z0\.h, p7/m, z0\.h, #16
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--.*: 04048203 asrd z3\.h, p0/m, z3\.h, #16
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--.*: 040483c0 asrd z0\.h, p0/m, z0\.h, #2
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--.*: 04048300 asrd z0\.h, p0/m, z0\.h, #8
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--.*: 04048303 asrd z3\.h, p0/m, z3\.h, #8
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--.*: 04048320 asrd z0\.h, p0/m, z0\.h, #7
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--.*: 04448000 asrd z0\.s, p0/m, z0\.s, #32
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--.*: 04448003 asrd z3\.s, p0/m, z3\.s, #32
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--.*: 048483c0 asrd z0\.d, p0/m, z0\.d, #34
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--.*: 04448300 asrd z0\.s, p0/m, z0\.s, #8
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--.*: 04c481c0 asrd z0\.d, p0/m, z0\.d, #18
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--.*: 04c481e0 asrd z0\.d, p0/m, z0\.d, #17
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--.*: 04848000 asrd z0\.d, p0/m, z0\.d, #64
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--.*: 04848001 asrd z1\.d, p0/m, z1\.d, #64
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--.*: 0484801f asrd z31\.d, p0/m, z31\.d, #64
--.*: 04848800 asrd z0\.d, p2/m, z0\.d, #64
--.*: 04848800 asrd z0\.d, p2/m, z0\.d, #64
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--.*: 04849c00 asrd z0\.d, p7/m, z0\.d, #64
--.*: 04848003 asrd z3\.d, p0/m, z3\.d, #64
--.*: 04848003 asrd z3\.d, p0/m, z3\.d, #64
--.*: 04848020 asrd z0\.d, p0/m, z0\.d, #63
--.*: 04848020 asrd z0\.d, p0/m, z0\.d, #63
--.*: 04c483c0 asrd z0\.d, p0/m, z0\.d, #2
--.*: 04c483c0 asrd z0\.d, p0/m, z0\.d, #2
--.*: 04c483e0 asrd z0\.d, p0/m, z0\.d, #1
--.*: 04c483e0 asrd z0\.d, p0/m, z0\.d, #1
--.*: 04848100 asrd z0\.d, p0/m, z0\.d, #56
--.*: 04848100 asrd z0\.d, p0/m, z0\.d, #56
--.*: 04848101 asrd z1\.d, p0/m, z1\.d, #56
--.*: 04848101 asrd z1\.d, p0/m, z1\.d, #56
--.*: 0484811f asrd z31\.d, p0/m, z31\.d, #56
--.*: 0484811f asrd z31\.d, p0/m, z31\.d, #56
--.*: 04848900 asrd z0\.d, p2/m, z0\.d, #56
--.*: 04848900 asrd z0\.d, p2/m, z0\.d, #56
--.*: 04849d00 asrd z0\.d, p7/m, z0\.d, #56
--.*: 04849d00 asrd z0\.d, p7/m, z0\.d, #56
--.*: 04848103 asrd z3\.d, p0/m, z3\.d, #56
--.*: 04848103 asrd z3\.d, p0/m, z3\.d, #56
--.*: 04848120 asrd z0\.d, p0/m, z0\.d, #55
--.*: 04848120 asrd z0\.d, p0/m, z0\.d, #55
--.*: 04848200 asrd z0\.d, p0/m, z0\.d, #48
--.*: 04848200 asrd z0\.d, p0/m, z0\.d, #48
--.*: 04848201 asrd z1\.d, p0/m, z1\.d, #48
--.*: 04848201 asrd z1\.d, p0/m, z1\.d, #48
--.*: 0484821f asrd z31\.d, p0/m, z31\.d, #48
--.*: 0484821f asrd z31\.d, p0/m, z31\.d, #48
--.*: 04848a00 asrd z0\.d, p2/m, z0\.d, #48
--.*: 04848a00 asrd z0\.d, p2/m, z0\.d, #48
--.*: 04849e00 asrd z0\.d, p7/m, z0\.d, #48
--.*: 04849e00 asrd z0\.d, p7/m, z0\.d, #48
--.*: 04848203 asrd z3\.d, p0/m, z3\.d, #48
--.*: 04848203 asrd z3\.d, p0/m, z3\.d, #48
--.*: 04848220 asrd z0\.d, p0/m, z0\.d, #47
--.*: 04848220 asrd z0\.d, p0/m, z0\.d, #47
--.*: 04848300 asrd z0\.d, p0/m, z0\.d, #40
--.*: 04848300 asrd z0\.d, p0/m, z0\.d, #40
--.*: 04848301 asrd z1\.d, p0/m, z1\.d, #40
--.*: 04848301 asrd z1\.d, p0/m, z1\.d, #40
--.*: 0484831f asrd z31\.d, p0/m, z31\.d, #40
--.*: 0484831f asrd z31\.d, p0/m, z31\.d, #40
--.*: 04848b00 asrd z0\.d, p2/m, z0\.d, #40
--.*: 04848b00 asrd z0\.d, p2/m, z0\.d, #40
--.*: 04849f00 asrd z0\.d, p7/m, z0\.d, #40
--.*: 04849f00 asrd z0\.d, p7/m, z0\.d, #40
--.*: 04848303 asrd z3\.d, p0/m, z3\.d, #40
--.*: 04848303 asrd z3\.d, p0/m, z3\.d, #40
--.*: 04848320 asrd z0\.d, p0/m, z0\.d, #39
--.*: 04848320 asrd z0\.d, p0/m, z0\.d, #39
--.*: 04c48000 asrd z0\.d, p0/m, z0\.d, #32
--.*: 04c48000 asrd z0\.d, p0/m, z0\.d, #32
--.*: 04c48001 asrd z1\.d, p0/m, z1\.d, #32
--.*: 04c48001 asrd z1\.d, p0/m, z1\.d, #32
--.*: 04c4801f asrd z31\.d, p0/m, z31\.d, #32
--.*: 04c4801f asrd z31\.d, p0/m, z31\.d, #32
--.*: 04c48800 asrd z0\.d, p2/m, z0\.d, #32
--.*: 04c48800 asrd z0\.d, p2/m, z0\.d, #32
--.*: 04c49c00 asrd z0\.d, p7/m, z0\.d, #32
--.*: 04c49c00 asrd z0\.d, p7/m, z0\.d, #32
--.*: 04c48003 asrd z3\.d, p0/m, z3\.d, #32
--.*: 04c48003 asrd z3\.d, p0/m, z3\.d, #32
--.*: 04c48020 asrd z0\.d, p0/m, z0\.d, #31
--.*: 04c48020 asrd z0\.d, p0/m, z0\.d, #31
--.*: 04c48100 asrd z0\.d, p0/m, z0\.d, #24
--.*: 04c48100 asrd z0\.d, p0/m, z0\.d, #24
--.*: 04c48101 asrd z1\.d, p0/m, z1\.d, #24
--.*: 04c48101 asrd z1\.d, p0/m, z1\.d, #24
--.*: 04c4811f asrd z31\.d, p0/m, z31\.d, #24
--.*: 04c4811f asrd z31\.d, p0/m, z31\.d, #24
--.*: 04c48900 asrd z0\.d, p2/m, z0\.d, #24
--.*: 04c48900 asrd z0\.d, p2/m, z0\.d, #24
--.*: 04c49d00 asrd z0\.d, p7/m, z0\.d, #24
--.*: 04c49d00 asrd z0\.d, p7/m, z0\.d, #24
--.*: 04c48103 asrd z3\.d, p0/m, z3\.d, #24
--.*: 04c48103 asrd z3\.d, p0/m, z3\.d, #24
--.*: 04c48120 asrd z0\.d, p0/m, z0\.d, #23
--.*: 04c48120 asrd z0\.d, p0/m, z0\.d, #23
--.*: 04c48200 asrd z0\.d, p0/m, z0\.d, #16
--.*: 04c48200 asrd z0\.d, p0/m, z0\.d, #16
--.*: 04c48201 asrd z1\.d, p0/m, z1\.d, #16
--.*: 04c48201 asrd z1\.d, p0/m, z1\.d, #16
--.*: 04c4821f asrd z31\.d, p0/m, z31\.d, #16
--.*: 04c4821f asrd z31\.d, p0/m, z31\.d, #16
--.*: 04c48a00 asrd z0\.d, p2/m, z0\.d, #16
--.*: 04c48a00 asrd z0\.d, p2/m, z0\.d, #16
--.*: 04c49e00 asrd z0\.d, p7/m, z0\.d, #16
--.*: 04c49e00 asrd z0\.d, p7/m, z0\.d, #16
--.*: 04c48203 asrd z3\.d, p0/m, z3\.d, #16
--.*: 04c48203 asrd z3\.d, p0/m, z3\.d, #16
--.*: 04c48220 asrd z0\.d, p0/m, z0\.d, #15
--.*: 04c48220 asrd z0\.d, p0/m, z0\.d, #15
--.*: 04c48300 asrd z0\.d, p0/m, z0\.d, #8
--.*: 04c48300 asrd z0\.d, p0/m, z0\.d, #8
--.*: 04c48301 asrd z1\.d, p0/m, z1\.d, #8
--.*: 04c48301 asrd z1\.d, p0/m, z1\.d, #8
--.*: 04c4831f asrd z31\.d, p0/m, z31\.d, #8
--.*: 04c4831f asrd z31\.d, p0/m, z31\.d, #8
--.*: 04c48b00 asrd z0\.d, p2/m, z0\.d, #8
--.*: 04c48b00 asrd z0\.d, p2/m, z0\.d, #8
--.*: 04c49f00 asrd z0\.d, p7/m, z0\.d, #8
--.*: 04c49f00 asrd z0\.d, p7/m, z0\.d, #8
--.*: 04c48303 asrd z3\.d, p0/m, z3\.d, #8
--.*: 04c48303 asrd z3\.d, p0/m, z3\.d, #8
--.*: 04c48320 asrd z0\.d, p0/m, z0\.d, #7
--.*: 04c48320 asrd z0\.d, p0/m, z0\.d, #7
--.*: 04148000 asrr z0\.b, p0/m, z0\.b, z0\.b
--.*: 04148000 asrr z0\.b, p0/m, z0\.b, z0\.b
--.*: 04148001 asrr z1\.b, p0/m, z1\.b, z0\.b
--.*: 04148001 asrr z1\.b, p0/m, z1\.b, z0\.b
--.*: 0414801f asrr z31\.b, p0/m, z31\.b, z0\.b
--.*: 0414801f asrr z31\.b, p0/m, z31\.b, z0\.b
--.*: 04148800 asrr z0\.b, p2/m, z0\.b, z0\.b
--.*: 04148800 asrr z0\.b, p2/m, z0\.b, z0\.b
--.*: 04149c00 asrr z0\.b, p7/m, z0\.b, z0\.b
--.*: 04149c00 asrr z0\.b, p7/m, z0\.b, z0\.b
--.*: 04148003 asrr z3\.b, p0/m, z3\.b, z0\.b
--.*: 04148003 asrr z3\.b, p0/m, z3\.b, z0\.b
--.*: 04148080 asrr z0\.b, p0/m, z0\.b, z4\.b
--.*: 04148080 asrr z0\.b, p0/m, z0\.b, z4\.b
--.*: 041483e0 asrr z0\.b, p0/m, z0\.b, z31\.b
--.*: 041483e0 asrr z0\.b, p0/m, z0\.b, z31\.b
--.*: 04548000 asrr z0\.h, p0/m, z0\.h, z0\.h
--.*: 04548000 asrr z0\.h, p0/m, z0\.h, z0\.h
--.*: 04548001 asrr z1\.h, p0/m, z1\.h, z0\.h
--.*: 04548001 asrr z1\.h, p0/m, z1\.h, z0\.h
--.*: 0454801f asrr z31\.h, p0/m, z31\.h, z0\.h
--.*: 0454801f asrr z31\.h, p0/m, z31\.h, z0\.h
--.*: 04548800 asrr z0\.h, p2/m, z0\.h, z0\.h
--.*: 04548800 asrr z0\.h, p2/m, z0\.h, z0\.h
--.*: 04549c00 asrr z0\.h, p7/m, z0\.h, z0\.h
--.*: 04549c00 asrr z0\.h, p7/m, z0\.h, z0\.h
--.*: 04548003 asrr z3\.h, p0/m, z3\.h, z0\.h
--.*: 04548003 asrr z3\.h, p0/m, z3\.h, z0\.h
--.*: 04548080 asrr z0\.h, p0/m, z0\.h, z4\.h
--.*: 04548080 asrr z0\.h, p0/m, z0\.h, z4\.h
--.*: 045483e0 asrr z0\.h, p0/m, z0\.h, z31\.h
--.*: 045483e0 asrr z0\.h, p0/m, z0\.h, z31\.h
--.*: 04948000 asrr z0\.s, p0/m, z0\.s, z0\.s
--.*: 04948000 asrr z0\.s, p0/m, z0\.s, z0\.s
--.*: 04948001 asrr z1\.s, p0/m, z1\.s, z0\.s
--.*: 04948001 asrr z1\.s, p0/m, z1\.s, z0\.s
--.*: 0494801f asrr z31\.s, p0/m, z31\.s, z0\.s
--.*: 0494801f asrr z31\.s, p0/m, z31\.s, z0\.s
--.*: 04948800 asrr z0\.s, p2/m, z0\.s, z0\.s
--.*: 04948800 asrr z0\.s, p2/m, z0\.s, z0\.s
--.*: 04949c00 asrr z0\.s, p7/m, z0\.s, z0\.s
--.*: 04949c00 asrr z0\.s, p7/m, z0\.s, z0\.s
--.*: 04948003 asrr z3\.s, p0/m, z3\.s, z0\.s
--.*: 04948003 asrr z3\.s, p0/m, z3\.s, z0\.s
--.*: 04948080 asrr z0\.s, p0/m, z0\.s, z4\.s
--.*: 04948080 asrr z0\.s, p0/m, z0\.s, z4\.s
--.*: 049483e0 asrr z0\.s, p0/m, z0\.s, z31\.s
--.*: 049483e0 asrr z0\.s, p0/m, z0\.s, z31\.s
--.*: 04d48000 asrr z0\.d, p0/m, z0\.d, z0\.d
--.*: 04d48000 asrr z0\.d, p0/m, z0\.d, z0\.d
--.*: 04d48001 asrr z1\.d, p0/m, z1\.d, z0\.d
--.*: 04d48001 asrr z1\.d, p0/m, z1\.d, z0\.d
--.*: 04d4801f asrr z31\.d, p0/m, z31\.d, z0\.d
--.*: 04d4801f asrr z31\.d, p0/m, z31\.d, z0\.d
--.*: 04d48800 asrr z0\.d, p2/m, z0\.d, z0\.d
--.*: 04d48800 asrr z0\.d, p2/m, z0\.d, z0\.d
--.*: 04d49c00 asrr z0\.d, p7/m, z0\.d, z0\.d
--.*: 04d49c00 asrr z0\.d, p7/m, z0\.d, z0\.d
--.*: 04d48003 asrr z3\.d, p0/m, z3\.d, z0\.d
--.*: 04d48003 asrr z3\.d, p0/m, z3\.d, z0\.d
--.*: 04d48080 asrr z0\.d, p0/m, z0\.d, z4\.d
--.*: 04d48080 asrr z0\.d, p0/m, z0\.d, z4\.d
--.*: 04d483e0 asrr z0\.d, p0/m, z0\.d, z31\.d
--.*: 04d483e0 asrr z0\.d, p0/m, z0\.d, z31\.d
--.*: 04e03000 bic z0\.d, z0\.d, z0\.d
--.*: 04e03000 bic z0\.d, z0\.d, z0\.d
--.*: 04e03001 bic z1\.d, z0\.d, z0\.d
--.*: 04e03001 bic z1\.d, z0\.d, z0\.d
--.*: 04e0301f bic z31\.d, z0\.d, z0\.d
--.*: 04e0301f bic z31\.d, z0\.d, z0\.d
--.*: 04e03040 bic z0\.d, z2\.d, z0\.d
--.*: 04e03040 bic z0\.d, z2\.d, z0\.d
--.*: 04e033e0 bic z0\.d, z31\.d, z0\.d
--.*: 04e033e0 bic z0\.d, z31\.d, z0\.d
--.*: 04e33000 bic z0\.d, z0\.d, z3\.d
--.*: 04e33000 bic z0\.d, z0\.d, z3\.d
--.*: 04ff3000 bic z0\.d, z0\.d, z31\.d
--.*: 04ff3000 bic z0\.d, z0\.d, z31\.d
--.*: 041b0000 bic z0\.b, p0/m, z0\.b, z0\.b
--.*: 041b0000 bic z0\.b, p0/m, z0\.b, z0\.b
--.*: 041b0001 bic z1\.b, p0/m, z1\.b, z0\.b
--.*: 041b0001 bic z1\.b, p0/m, z1\.b, z0\.b
--.*: 041b001f bic z31\.b, p0/m, z31\.b, z0\.b
--.*: 041b001f bic z31\.b, p0/m, z31\.b, z0\.b
--.*: 041b0800 bic z0\.b, p2/m, z0\.b, z0\.b
--.*: 041b0800 bic z0\.b, p2/m, z0\.b, z0\.b
--.*: 041b1c00 bic z0\.b, p7/m, z0\.b, z0\.b
--.*: 041b1c00 bic z0\.b, p7/m, z0\.b, z0\.b
--.*: 041b0003 bic z3\.b, p0/m, z3\.b, z0\.b
--.*: 041b0003 bic z3\.b, p0/m, z3\.b, z0\.b
--.*: 041b0080 bic z0\.b, p0/m, z0\.b, z4\.b
--.*: 041b0080 bic z0\.b, p0/m, z0\.b, z4\.b
--.*: 041b03e0 bic z0\.b, p0/m, z0\.b, z31\.b
--.*: 041b03e0 bic z0\.b, p0/m, z0\.b, z31\.b
--.*: 045b0000 bic z0\.h, p0/m, z0\.h, z0\.h
--.*: 045b0000 bic z0\.h, p0/m, z0\.h, z0\.h
--.*: 045b0001 bic z1\.h, p0/m, z1\.h, z0\.h
--.*: 045b0001 bic z1\.h, p0/m, z1\.h, z0\.h
--.*: 045b001f bic z31\.h, p0/m, z31\.h, z0\.h
--.*: 045b001f bic z31\.h, p0/m, z31\.h, z0\.h
--.*: 045b0800 bic z0\.h, p2/m, z0\.h, z0\.h
--.*: 045b0800 bic z0\.h, p2/m, z0\.h, z0\.h
--.*: 045b1c00 bic z0\.h, p7/m, z0\.h, z0\.h
--.*: 045b1c00 bic z0\.h, p7/m, z0\.h, z0\.h
--.*: 045b0003 bic z3\.h, p0/m, z3\.h, z0\.h
--.*: 045b0003 bic z3\.h, p0/m, z3\.h, z0\.h
--.*: 045b0080 bic z0\.h, p0/m, z0\.h, z4\.h
--.*: 045b0080 bic z0\.h, p0/m, z0\.h, z4\.h
--.*: 045b03e0 bic z0\.h, p0/m, z0\.h, z31\.h
--.*: 045b03e0 bic z0\.h, p0/m, z0\.h, z31\.h
--.*: 049b0000 bic z0\.s, p0/m, z0\.s, z0\.s
--.*: 049b0000 bic z0\.s, p0/m, z0\.s, z0\.s
--.*: 049b0001 bic z1\.s, p0/m, z1\.s, z0\.s
--.*: 049b0001 bic z1\.s, p0/m, z1\.s, z0\.s
--.*: 049b001f bic z31\.s, p0/m, z31\.s, z0\.s
--.*: 049b001f bic z31\.s, p0/m, z31\.s, z0\.s
--.*: 049b0800 bic z0\.s, p2/m, z0\.s, z0\.s
--.*: 049b0800 bic z0\.s, p2/m, z0\.s, z0\.s
--.*: 049b1c00 bic z0\.s, p7/m, z0\.s, z0\.s
--.*: 049b1c00 bic z0\.s, p7/m, z0\.s, z0\.s
--.*: 049b0003 bic z3\.s, p0/m, z3\.s, z0\.s
--.*: 049b0003 bic z3\.s, p0/m, z3\.s, z0\.s
--.*: 049b0080 bic z0\.s, p0/m, z0\.s, z4\.s
--.*: 049b0080 bic z0\.s, p0/m, z0\.s, z4\.s
--.*: 049b03e0 bic z0\.s, p0/m, z0\.s, z31\.s
--.*: 049b03e0 bic z0\.s, p0/m, z0\.s, z31\.s
--.*: 04db0000 bic z0\.d, p0/m, z0\.d, z0\.d
--.*: 04db0000 bic z0\.d, p0/m, z0\.d, z0\.d
--.*: 04db0001 bic z1\.d, p0/m, z1\.d, z0\.d
--.*: 04db0001 bic z1\.d, p0/m, z1\.d, z0\.d
--.*: 04db001f bic z31\.d, p0/m, z31\.d, z0\.d
--.*: 04db001f bic z31\.d, p0/m, z31\.d, z0\.d
--.*: 04db0800 bic z0\.d, p2/m, z0\.d, z0\.d
--.*: 04db0800 bic z0\.d, p2/m, z0\.d, z0\.d
--.*: 04db1c00 bic z0\.d, p7/m, z0\.d, z0\.d
--.*: 04db1c00 bic z0\.d, p7/m, z0\.d, z0\.d
--.*: 04db0003 bic z3\.d, p0/m, z3\.d, z0\.d
--.*: 04db0003 bic z3\.d, p0/m, z3\.d, z0\.d
--.*: 04db0080 bic z0\.d, p0/m, z0\.d, z4\.d
--.*: 04db0080 bic z0\.d, p0/m, z0\.d, z4\.d
--.*: 04db03e0 bic z0\.d, p0/m, z0\.d, z31\.d
--.*: 04db03e0 bic z0\.d, p0/m, z0\.d, z31\.d
--.*: 25004010 bic p0\.b, p0/z, p0\.b, p0\.b
--.*: 25004010 bic p0\.b, p0/z, p0\.b, p0\.b
--.*: 25004011 bic p1\.b, p0/z, p0\.b, p0\.b
--.*: 25004011 bic p1\.b, p0/z, p0\.b, p0\.b
--.*: 2500401f bic p15\.b, p0/z, p0\.b, p0\.b
--.*: 2500401f bic p15\.b, p0/z, p0\.b, p0\.b
--.*: 25004810 bic p0\.b, p2/z, p0\.b, p0\.b
--.*: 25004810 bic p0\.b, p2/z, p0\.b, p0\.b
--.*: 25007c10 bic p0\.b, p15/z, p0\.b, p0\.b
--.*: 25007c10 bic p0\.b, p15/z, p0\.b, p0\.b
--.*: 25004070 bic p0\.b, p0/z, p3\.b, p0\.b
--.*: 25004070 bic p0\.b, p0/z, p3\.b, p0\.b
--.*: 250041f0 bic p0\.b, p0/z, p15\.b, p0\.b
--.*: 250041f0 bic p0\.b, p0/z, p15\.b, p0\.b
--.*: 25044010 bic p0\.b, p0/z, p0\.b, p4\.b
--.*: 25044010 bic p0\.b, p0/z, p0\.b, p4\.b
--.*: 250f4010 bic p0\.b, p0/z, p0\.b, p15\.b
--.*: 250f4010 bic p0\.b, p0/z, p0\.b, p15\.b
--.*: 25404010 bics p0\.b, p0/z, p0\.b, p0\.b
--.*: 25404010 bics p0\.b, p0/z, p0\.b, p0\.b
--.*: 25404011 bics p1\.b, p0/z, p0\.b, p0\.b
--.*: 25404011 bics p1\.b, p0/z, p0\.b, p0\.b
--.*: 2540401f bics p15\.b, p0/z, p0\.b, p0\.b
--.*: 2540401f bics p15\.b, p0/z, p0\.b, p0\.b
--.*: 25404810 bics p0\.b, p2/z, p0\.b, p0\.b
--.*: 25404810 bics p0\.b, p2/z, p0\.b, p0\.b
--.*: 25407c10 bics p0\.b, p15/z, p0\.b, p0\.b
--.*: 25407c10 bics p0\.b, p15/z, p0\.b, p0\.b
--.*: 25404070 bics p0\.b, p0/z, p3\.b, p0\.b
--.*: 25404070 bics p0\.b, p0/z, p3\.b, p0\.b
--.*: 254041f0 bics p0\.b, p0/z, p15\.b, p0\.b
--.*: 254041f0 bics p0\.b, p0/z, p15\.b, p0\.b
--.*: 25444010 bics p0\.b, p0/z, p0\.b, p4\.b
--.*: 25444010 bics p0\.b, p0/z, p0\.b, p4\.b
--.*: 254f4010 bics p0\.b, p0/z, p0\.b, p15\.b
--.*: 254f4010 bics p0\.b, p0/z, p0\.b, p15\.b
--.*: 25104000 brka p0\.b, p0/z, p0\.b
--.*: 25104000 brka p0\.b, p0/z, p0\.b
--.*: 25104001 brka p1\.b, p0/z, p0\.b
--.*: 25104001 brka p1\.b, p0/z, p0\.b
--.*: 2510400f brka p15\.b, p0/z, p0\.b
--.*: 2510400f brka p15\.b, p0/z, p0\.b
--.*: 25104800 brka p0\.b, p2/z, p0\.b
--.*: 25104800 brka p0\.b, p2/z, p0\.b
--.*: 25107c00 brka p0\.b, p15/z, p0\.b
--.*: 25107c00 brka p0\.b, p15/z, p0\.b
--.*: 25104060 brka p0\.b, p0/z, p3\.b
--.*: 25104060 brka p0\.b, p0/z, p3\.b
--.*: 251041e0 brka p0\.b, p0/z, p15\.b
--.*: 251041e0 brka p0\.b, p0/z, p15\.b
--.*: 25104010 brka p0\.b, p0/m, p0\.b
--.*: 25104010 brka p0\.b, p0/m, p0\.b
--.*: 25104011 brka p1\.b, p0/m, p0\.b
--.*: 25104011 brka p1\.b, p0/m, p0\.b
--.*: 2510401f brka p15\.b, p0/m, p0\.b
--.*: 2510401f brka p15\.b, p0/m, p0\.b
--.*: 25104810 brka p0\.b, p2/m, p0\.b
--.*: 25104810 brka p0\.b, p2/m, p0\.b
--.*: 25107c10 brka p0\.b, p15/m, p0\.b
--.*: 25107c10 brka p0\.b, p15/m, p0\.b
--.*: 25104070 brka p0\.b, p0/m, p3\.b
--.*: 25104070 brka p0\.b, p0/m, p3\.b
--.*: 251041f0 brka p0\.b, p0/m, p15\.b
--.*: 251041f0 brka p0\.b, p0/m, p15\.b
--.*: 25504000 brkas p0\.b, p0/z, p0\.b
--.*: 25504000 brkas p0\.b, p0/z, p0\.b
--.*: 25504001 brkas p1\.b, p0/z, p0\.b
--.*: 25504001 brkas p1\.b, p0/z, p0\.b
--.*: 2550400f brkas p15\.b, p0/z, p0\.b
--.*: 2550400f brkas p15\.b, p0/z, p0\.b
--.*: 25504800 brkas p0\.b, p2/z, p0\.b
--.*: 25504800 brkas p0\.b, p2/z, p0\.b
--.*: 25507c00 brkas p0\.b, p15/z, p0\.b
--.*: 25507c00 brkas p0\.b, p15/z, p0\.b
--.*: 25504060 brkas p0\.b, p0/z, p3\.b
--.*: 25504060 brkas p0\.b, p0/z, p3\.b
--.*: 255041e0 brkas p0\.b, p0/z, p15\.b
--.*: 255041e0 brkas p0\.b, p0/z, p15\.b
--.*: 25904000 brkb p0\.b, p0/z, p0\.b
--.*: 25904000 brkb p0\.b, p0/z, p0\.b
--.*: 25904001 brkb p1\.b, p0/z, p0\.b
--.*: 25904001 brkb p1\.b, p0/z, p0\.b
--.*: 2590400f brkb p15\.b, p0/z, p0\.b
--.*: 2590400f brkb p15\.b, p0/z, p0\.b
--.*: 25904800 brkb p0\.b, p2/z, p0\.b
--.*: 25904800 brkb p0\.b, p2/z, p0\.b
--.*: 25907c00 brkb p0\.b, p15/z, p0\.b
--.*: 25907c00 brkb p0\.b, p15/z, p0\.b
--.*: 25904060 brkb p0\.b, p0/z, p3\.b
--.*: 25904060 brkb p0\.b, p0/z, p3\.b
--.*: 259041e0 brkb p0\.b, p0/z, p15\.b
--.*: 259041e0 brkb p0\.b, p0/z, p15\.b
--.*: 25904010 brkb p0\.b, p0/m, p0\.b
--.*: 25904010 brkb p0\.b, p0/m, p0\.b
--.*: 25904011 brkb p1\.b, p0/m, p0\.b
--.*: 25904011 brkb p1\.b, p0/m, p0\.b
--.*: 2590401f brkb p15\.b, p0/m, p0\.b
--.*: 2590401f brkb p15\.b, p0/m, p0\.b
--.*: 25904810 brkb p0\.b, p2/m, p0\.b
--.*: 25904810 brkb p0\.b, p2/m, p0\.b
--.*: 25907c10 brkb p0\.b, p15/m, p0\.b
--.*: 25907c10 brkb p0\.b, p15/m, p0\.b
--.*: 25904070 brkb p0\.b, p0/m, p3\.b
--.*: 25904070 brkb p0\.b, p0/m, p3\.b
--.*: 259041f0 brkb p0\.b, p0/m, p15\.b
--.*: 259041f0 brkb p0\.b, p0/m, p15\.b
--.*: 25d04000 brkbs p0\.b, p0/z, p0\.b
--.*: 25d04000 brkbs p0\.b, p0/z, p0\.b
--.*: 25d04001 brkbs p1\.b, p0/z, p0\.b
--.*: 25d04001 brkbs p1\.b, p0/z, p0\.b
--.*: 25d0400f brkbs p15\.b, p0/z, p0\.b
--.*: 25d0400f brkbs p15\.b, p0/z, p0\.b
--.*: 25d04800 brkbs p0\.b, p2/z, p0\.b
--.*: 25d04800 brkbs p0\.b, p2/z, p0\.b
--.*: 25d07c00 brkbs p0\.b, p15/z, p0\.b
--.*: 25d07c00 brkbs p0\.b, p15/z, p0\.b
--.*: 25d04060 brkbs p0\.b, p0/z, p3\.b
--.*: 25d04060 brkbs p0\.b, p0/z, p3\.b
--.*: 25d041e0 brkbs p0\.b, p0/z, p15\.b
--.*: 25d041e0 brkbs p0\.b, p0/z, p15\.b
--.*: 25184000 brkn p0\.b, p0/z, p0\.b, p0\.b
--.*: 25184000 brkn p0\.b, p0/z, p0\.b, p0\.b
--.*: 25184001 brkn p1\.b, p0/z, p0\.b, p1\.b
--.*: 25184001 brkn p1\.b, p0/z, p0\.b, p1\.b
--.*: 2518400f brkn p15\.b, p0/z, p0\.b, p15\.b
--.*: 2518400f brkn p15\.b, p0/z, p0\.b, p15\.b
--.*: 25184800 brkn p0\.b, p2/z, p0\.b, p0\.b
--.*: 25184800 brkn p0\.b, p2/z, p0\.b, p0\.b
--.*: 25187c00 brkn p0\.b, p15/z, p0\.b, p0\.b
--.*: 25187c00 brkn p0\.b, p15/z, p0\.b, p0\.b
--.*: 25184060 brkn p0\.b, p0/z, p3\.b, p0\.b
--.*: 25184060 brkn p0\.b, p0/z, p3\.b, p0\.b
--.*: 251841e0 brkn p0\.b, p0/z, p15\.b, p0\.b
--.*: 251841e0 brkn p0\.b, p0/z, p15\.b, p0\.b
--.*: 25184004 brkn p4\.b, p0/z, p0\.b, p4\.b
--.*: 25184004 brkn p4\.b, p0/z, p0\.b, p4\.b
--.*: 25584000 brkns p0\.b, p0/z, p0\.b, p0\.b
--.*: 25584000 brkns p0\.b, p0/z, p0\.b, p0\.b
--.*: 25584001 brkns p1\.b, p0/z, p0\.b, p1\.b
--.*: 25584001 brkns p1\.b, p0/z, p0\.b, p1\.b
--.*: 2558400f brkns p15\.b, p0/z, p0\.b, p15\.b
--.*: 2558400f brkns p15\.b, p0/z, p0\.b, p15\.b
--.*: 25584800 brkns p0\.b, p2/z, p0\.b, p0\.b
--.*: 25584800 brkns p0\.b, p2/z, p0\.b, p0\.b
--.*: 25587c00 brkns p0\.b, p15/z, p0\.b, p0\.b
--.*: 25587c00 brkns p0\.b, p15/z, p0\.b, p0\.b
--.*: 25584060 brkns p0\.b, p0/z, p3\.b, p0\.b
--.*: 25584060 brkns p0\.b, p0/z, p3\.b, p0\.b
--.*: 255841e0 brkns p0\.b, p0/z, p15\.b, p0\.b
--.*: 255841e0 brkns p0\.b, p0/z, p15\.b, p0\.b
--.*: 25584004 brkns p4\.b, p0/z, p0\.b, p4\.b
--.*: 25584004 brkns p4\.b, p0/z, p0\.b, p4\.b
--.*: 2500c000 brkpa p0\.b, p0/z, p0\.b, p0\.b
--.*: 2500c000 brkpa p0\.b, p0/z, p0\.b, p0\.b
--.*: 2500c001 brkpa p1\.b, p0/z, p0\.b, p0\.b
--.*: 2500c001 brkpa p1\.b, p0/z, p0\.b, p0\.b
--.*: 2500c00f brkpa p15\.b, p0/z, p0\.b, p0\.b
--.*: 2500c00f brkpa p15\.b, p0/z, p0\.b, p0\.b
--.*: 2500c800 brkpa p0\.b, p2/z, p0\.b, p0\.b
--.*: 2500c800 brkpa p0\.b, p2/z, p0\.b, p0\.b
--.*: 2500fc00 brkpa p0\.b, p15/z, p0\.b, p0\.b
--.*: 2500fc00 brkpa p0\.b, p15/z, p0\.b, p0\.b
--.*: 2500c060 brkpa p0\.b, p0/z, p3\.b, p0\.b
--.*: 2500c060 brkpa p0\.b, p0/z, p3\.b, p0\.b
--.*: 2500c1e0 brkpa p0\.b, p0/z, p15\.b, p0\.b
--.*: 2500c1e0 brkpa p0\.b, p0/z, p15\.b, p0\.b
--.*: 2504c000 brkpa p0\.b, p0/z, p0\.b, p4\.b
--.*: 2504c000 brkpa p0\.b, p0/z, p0\.b, p4\.b
--.*: 250fc000 brkpa p0\.b, p0/z, p0\.b, p15\.b
--.*: 250fc000 brkpa p0\.b, p0/z, p0\.b, p15\.b
--.*: 2540c000 brkpas p0\.b, p0/z, p0\.b, p0\.b
--.*: 2540c000 brkpas p0\.b, p0/z, p0\.b, p0\.b
--.*: 2540c001 brkpas p1\.b, p0/z, p0\.b, p0\.b
--.*: 2540c001 brkpas p1\.b, p0/z, p0\.b, p0\.b
--.*: 2540c00f brkpas p15\.b, p0/z, p0\.b, p0\.b
--.*: 2540c00f brkpas p15\.b, p0/z, p0\.b, p0\.b
--.*: 2540c800 brkpas p0\.b, p2/z, p0\.b, p0\.b
--.*: 2540c800 brkpas p0\.b, p2/z, p0\.b, p0\.b
--.*: 2540fc00 brkpas p0\.b, p15/z, p0\.b, p0\.b
--.*: 2540fc00 brkpas p0\.b, p15/z, p0\.b, p0\.b
--.*: 2540c060 brkpas p0\.b, p0/z, p3\.b, p0\.b
--.*: 2540c060 brkpas p0\.b, p0/z, p3\.b, p0\.b
--.*: 2540c1e0 brkpas p0\.b, p0/z, p15\.b, p0\.b
--.*: 2540c1e0 brkpas p0\.b, p0/z, p15\.b, p0\.b
--.*: 2544c000 brkpas p0\.b, p0/z, p0\.b, p4\.b
--.*: 2544c000 brkpas p0\.b, p0/z, p0\.b, p4\.b
--.*: 254fc000 brkpas p0\.b, p0/z, p0\.b, p15\.b
--.*: 254fc000 brkpas p0\.b, p0/z, p0\.b, p15\.b
--.*: 2500c010 brkpb p0\.b, p0/z, p0\.b, p0\.b
--.*: 2500c010 brkpb p0\.b, p0/z, p0\.b, p0\.b
--.*: 2500c011 brkpb p1\.b, p0/z, p0\.b, p0\.b
--.*: 2500c011 brkpb p1\.b, p0/z, p0\.b, p0\.b
--.*: 2500c01f brkpb p15\.b, p0/z, p0\.b, p0\.b
--.*: 2500c01f brkpb p15\.b, p0/z, p0\.b, p0\.b
--.*: 2500c810 brkpb p0\.b, p2/z, p0\.b, p0\.b
--.*: 2500c810 brkpb p0\.b, p2/z, p0\.b, p0\.b
--.*: 2500fc10 brkpb p0\.b, p15/z, p0\.b, p0\.b
--.*: 2500fc10 brkpb p0\.b, p15/z, p0\.b, p0\.b
--.*: 2500c070 brkpb p0\.b, p0/z, p3\.b, p0\.b
--.*: 2500c070 brkpb p0\.b, p0/z, p3\.b, p0\.b
--.*: 2500c1f0 brkpb p0\.b, p0/z, p15\.b, p0\.b
--.*: 2500c1f0 brkpb p0\.b, p0/z, p15\.b, p0\.b
--.*: 2504c010 brkpb p0\.b, p0/z, p0\.b, p4\.b
--.*: 2504c010 brkpb p0\.b, p0/z, p0\.b, p4\.b
--.*: 250fc010 brkpb p0\.b, p0/z, p0\.b, p15\.b
--.*: 250fc010 brkpb p0\.b, p0/z, p0\.b, p15\.b
--.*: 2540c010 brkpbs p0\.b, p0/z, p0\.b, p0\.b
--.*: 2540c010 brkpbs p0\.b, p0/z, p0\.b, p0\.b
--.*: 2540c011 brkpbs p1\.b, p0/z, p0\.b, p0\.b
--.*: 2540c011 brkpbs p1\.b, p0/z, p0\.b, p0\.b
--.*: 2540c01f brkpbs p15\.b, p0/z, p0\.b, p0\.b
--.*: 2540c01f brkpbs p15\.b, p0/z, p0\.b, p0\.b
--.*: 2540c810 brkpbs p0\.b, p2/z, p0\.b, p0\.b
--.*: 2540c810 brkpbs p0\.b, p2/z, p0\.b, p0\.b
--.*: 2540fc10 brkpbs p0\.b, p15/z, p0\.b, p0\.b
--.*: 2540fc10 brkpbs p0\.b, p15/z, p0\.b, p0\.b
--.*: 2540c070 brkpbs p0\.b, p0/z, p3\.b, p0\.b
--.*: 2540c070 brkpbs p0\.b, p0/z, p3\.b, p0\.b
--.*: 2540c1f0 brkpbs p0\.b, p0/z, p15\.b, p0\.b
--.*: 2540c1f0 brkpbs p0\.b, p0/z, p15\.b, p0\.b
--.*: 2544c010 brkpbs p0\.b, p0/z, p0\.b, p4\.b
--.*: 2544c010 brkpbs p0\.b, p0/z, p0\.b, p4\.b
--.*: 254fc010 brkpbs p0\.b, p0/z, p0\.b, p15\.b
--.*: 254fc010 brkpbs p0\.b, p0/z, p0\.b, p15\.b
--.*: 05288000 clasta z0\.b, p0, z0\.b, z0\.b
--.*: 05288000 clasta z0\.b, p0, z0\.b, z0\.b
--.*: 05288001 clasta z1\.b, p0, z1\.b, z0\.b
--.*: 05288001 clasta z1\.b, p0, z1\.b, z0\.b
--.*: 0528801f clasta z31\.b, p0, z31\.b, z0\.b
--.*: 0528801f clasta z31\.b, p0, z31\.b, z0\.b
--.*: 05288800 clasta z0\.b, p2, z0\.b, z0\.b
--.*: 05288800 clasta z0\.b, p2, z0\.b, z0\.b
--.*: 05289c00 clasta z0\.b, p7, z0\.b, z0\.b
--.*: 05289c00 clasta z0\.b, p7, z0\.b, z0\.b
--.*: 05288003 clasta z3\.b, p0, z3\.b, z0\.b
--.*: 05288003 clasta z3\.b, p0, z3\.b, z0\.b
--.*: 05288080 clasta z0\.b, p0, z0\.b, z4\.b
--.*: 05288080 clasta z0\.b, p0, z0\.b, z4\.b
--.*: 052883e0 clasta z0\.b, p0, z0\.b, z31\.b
--.*: 052883e0 clasta z0\.b, p0, z0\.b, z31\.b
--.*: 05688000 clasta z0\.h, p0, z0\.h, z0\.h
--.*: 05688000 clasta z0\.h, p0, z0\.h, z0\.h
--.*: 05688001 clasta z1\.h, p0, z1\.h, z0\.h
--.*: 05688001 clasta z1\.h, p0, z1\.h, z0\.h
--.*: 0568801f clasta z31\.h, p0, z31\.h, z0\.h
--.*: 0568801f clasta z31\.h, p0, z31\.h, z0\.h
--.*: 05688800 clasta z0\.h, p2, z0\.h, z0\.h
--.*: 05688800 clasta z0\.h, p2, z0\.h, z0\.h
--.*: 05689c00 clasta z0\.h, p7, z0\.h, z0\.h
--.*: 05689c00 clasta z0\.h, p7, z0\.h, z0\.h
--.*: 05688003 clasta z3\.h, p0, z3\.h, z0\.h
--.*: 05688003 clasta z3\.h, p0, z3\.h, z0\.h
--.*: 05688080 clasta z0\.h, p0, z0\.h, z4\.h
--.*: 05688080 clasta z0\.h, p0, z0\.h, z4\.h
--.*: 056883e0 clasta z0\.h, p0, z0\.h, z31\.h
--.*: 056883e0 clasta z0\.h, p0, z0\.h, z31\.h
--.*: 05a88000 clasta z0\.s, p0, z0\.s, z0\.s
--.*: 05a88000 clasta z0\.s, p0, z0\.s, z0\.s
--.*: 05a88001 clasta z1\.s, p0, z1\.s, z0\.s
--.*: 05a88001 clasta z1\.s, p0, z1\.s, z0\.s
--.*: 05a8801f clasta z31\.s, p0, z31\.s, z0\.s
--.*: 05a8801f clasta z31\.s, p0, z31\.s, z0\.s
--.*: 05a88800 clasta z0\.s, p2, z0\.s, z0\.s
--.*: 05a88800 clasta z0\.s, p2, z0\.s, z0\.s
--.*: 05a89c00 clasta z0\.s, p7, z0\.s, z0\.s
--.*: 05a89c00 clasta z0\.s, p7, z0\.s, z0\.s
--.*: 05a88003 clasta z3\.s, p0, z3\.s, z0\.s
--.*: 05a88003 clasta z3\.s, p0, z3\.s, z0\.s
--.*: 05a88080 clasta z0\.s, p0, z0\.s, z4\.s
--.*: 05a88080 clasta z0\.s, p0, z0\.s, z4\.s
--.*: 05a883e0 clasta z0\.s, p0, z0\.s, z31\.s
--.*: 05a883e0 clasta z0\.s, p0, z0\.s, z31\.s
--.*: 05e88000 clasta z0\.d, p0, z0\.d, z0\.d
--.*: 05e88000 clasta z0\.d, p0, z0\.d, z0\.d
--.*: 05e88001 clasta z1\.d, p0, z1\.d, z0\.d
--.*: 05e88001 clasta z1\.d, p0, z1\.d, z0\.d
--.*: 05e8801f clasta z31\.d, p0, z31\.d, z0\.d
--.*: 05e8801f clasta z31\.d, p0, z31\.d, z0\.d
--.*: 05e88800 clasta z0\.d, p2, z0\.d, z0\.d
--.*: 05e88800 clasta z0\.d, p2, z0\.d, z0\.d
--.*: 05e89c00 clasta z0\.d, p7, z0\.d, z0\.d
--.*: 05e89c00 clasta z0\.d, p7, z0\.d, z0\.d
--.*: 05e88003 clasta z3\.d, p0, z3\.d, z0\.d
--.*: 05e88003 clasta z3\.d, p0, z3\.d, z0\.d
--.*: 05e88080 clasta z0\.d, p0, z0\.d, z4\.d
--.*: 05e88080 clasta z0\.d, p0, z0\.d, z4\.d
--.*: 05e883e0 clasta z0\.d, p0, z0\.d, z31\.d
--.*: 05e883e0 clasta z0\.d, p0, z0\.d, z31\.d
--.*: 052a8000 clasta b0, p0, b0, z0\.b
--.*: 052a8000 clasta b0, p0, b0, z0\.b
--.*: 052a8001 clasta b1, p0, b1, z0\.b
--.*: 052a8001 clasta b1, p0, b1, z0\.b
--.*: 052a801f clasta b31, p0, b31, z0\.b
--.*: 052a801f clasta b31, p0, b31, z0\.b
--.*: 052a8800 clasta b0, p2, b0, z0\.b
--.*: 052a8800 clasta b0, p2, b0, z0\.b
--.*: 052a9c00 clasta b0, p7, b0, z0\.b
--.*: 052a9c00 clasta b0, p7, b0, z0\.b
--.*: 052a8003 clasta b3, p0, b3, z0\.b
--.*: 052a8003 clasta b3, p0, b3, z0\.b
--.*: 052a8080 clasta b0, p0, b0, z4\.b
--.*: 052a8080 clasta b0, p0, b0, z4\.b
--.*: 052a83e0 clasta b0, p0, b0, z31\.b
--.*: 052a83e0 clasta b0, p0, b0, z31\.b
--.*: 056a8000 clasta h0, p0, h0, z0\.h
--.*: 056a8000 clasta h0, p0, h0, z0\.h
--.*: 056a8001 clasta h1, p0, h1, z0\.h
--.*: 056a8001 clasta h1, p0, h1, z0\.h
--.*: 056a801f clasta h31, p0, h31, z0\.h
--.*: 056a801f clasta h31, p0, h31, z0\.h
--.*: 056a8800 clasta h0, p2, h0, z0\.h
--.*: 056a8800 clasta h0, p2, h0, z0\.h
--.*: 056a9c00 clasta h0, p7, h0, z0\.h
--.*: 056a9c00 clasta h0, p7, h0, z0\.h
--.*: 056a8003 clasta h3, p0, h3, z0\.h
--.*: 056a8003 clasta h3, p0, h3, z0\.h
--.*: 056a8080 clasta h0, p0, h0, z4\.h
--.*: 056a8080 clasta h0, p0, h0, z4\.h
--.*: 056a83e0 clasta h0, p0, h0, z31\.h
--.*: 056a83e0 clasta h0, p0, h0, z31\.h
--.*: 05aa8000 clasta s0, p0, s0, z0\.s
--.*: 05aa8000 clasta s0, p0, s0, z0\.s
--.*: 05aa8001 clasta s1, p0, s1, z0\.s
--.*: 05aa8001 clasta s1, p0, s1, z0\.s
--.*: 05aa801f clasta s31, p0, s31, z0\.s
--.*: 05aa801f clasta s31, p0, s31, z0\.s
--.*: 05aa8800 clasta s0, p2, s0, z0\.s
--.*: 05aa8800 clasta s0, p2, s0, z0\.s
--.*: 05aa9c00 clasta s0, p7, s0, z0\.s
--.*: 05aa9c00 clasta s0, p7, s0, z0\.s
--.*: 05aa8003 clasta s3, p0, s3, z0\.s
--.*: 05aa8003 clasta s3, p0, s3, z0\.s
--.*: 05aa8080 clasta s0, p0, s0, z4\.s
--.*: 05aa8080 clasta s0, p0, s0, z4\.s
--.*: 05aa83e0 clasta s0, p0, s0, z31\.s
--.*: 05aa83e0 clasta s0, p0, s0, z31\.s
--.*: 05ea8000 clasta d0, p0, d0, z0\.d
--.*: 05ea8000 clasta d0, p0, d0, z0\.d
--.*: 05ea8001 clasta d1, p0, d1, z0\.d
--.*: 05ea8001 clasta d1, p0, d1, z0\.d
--.*: 05ea801f clasta d31, p0, d31, z0\.d
--.*: 05ea801f clasta d31, p0, d31, z0\.d
--.*: 05ea8800 clasta d0, p2, d0, z0\.d
--.*: 05ea8800 clasta d0, p2, d0, z0\.d
--.*: 05ea9c00 clasta d0, p7, d0, z0\.d
--.*: 05ea9c00 clasta d0, p7, d0, z0\.d
--.*: 05ea8003 clasta d3, p0, d3, z0\.d
--.*: 05ea8003 clasta d3, p0, d3, z0\.d
--.*: 05ea8080 clasta d0, p0, d0, z4\.d
--.*: 05ea8080 clasta d0, p0, d0, z4\.d
--.*: 05ea83e0 clasta d0, p0, d0, z31\.d
--.*: 05ea83e0 clasta d0, p0, d0, z31\.d
--.*: 0530a000 clasta w0, p0, w0, z0\.b
--.*: 0530a000 clasta w0, p0, w0, z0\.b
--.*: 0530a001 clasta w1, p0, w1, z0\.b
--.*: 0530a001 clasta w1, p0, w1, z0\.b
--.*: 0530a01f clasta wzr, p0, wzr, z0\.b
--.*: 0530a01f clasta wzr, p0, wzr, z0\.b
--.*: 0530a800 clasta w0, p2, w0, z0\.b
--.*: 0530a800 clasta w0, p2, w0, z0\.b
--.*: 0530bc00 clasta w0, p7, w0, z0\.b
--.*: 0530bc00 clasta w0, p7, w0, z0\.b
--.*: 0530a003 clasta w3, p0, w3, z0\.b
--.*: 0530a003 clasta w3, p0, w3, z0\.b
--.*: 0530a080 clasta w0, p0, w0, z4\.b
--.*: 0530a080 clasta w0, p0, w0, z4\.b
--.*: 0530a3e0 clasta w0, p0, w0, z31\.b
--.*: 0530a3e0 clasta w0, p0, w0, z31\.b
--.*: 0570a000 clasta w0, p0, w0, z0\.h
--.*: 0570a000 clasta w0, p0, w0, z0\.h
--.*: 0570a001 clasta w1, p0, w1, z0\.h
--.*: 0570a001 clasta w1, p0, w1, z0\.h
--.*: 0570a01f clasta wzr, p0, wzr, z0\.h
--.*: 0570a01f clasta wzr, p0, wzr, z0\.h
--.*: 0570a800 clasta w0, p2, w0, z0\.h
--.*: 0570a800 clasta w0, p2, w0, z0\.h
--.*: 0570bc00 clasta w0, p7, w0, z0\.h
--.*: 0570bc00 clasta w0, p7, w0, z0\.h
--.*: 0570a003 clasta w3, p0, w3, z0\.h
--.*: 0570a003 clasta w3, p0, w3, z0\.h
--.*: 0570a080 clasta w0, p0, w0, z4\.h
--.*: 0570a080 clasta w0, p0, w0, z4\.h
--.*: 0570a3e0 clasta w0, p0, w0, z31\.h
--.*: 0570a3e0 clasta w0, p0, w0, z31\.h
--.*: 05b0a000 clasta w0, p0, w0, z0\.s
--.*: 05b0a000 clasta w0, p0, w0, z0\.s
--.*: 05b0a001 clasta w1, p0, w1, z0\.s
--.*: 05b0a001 clasta w1, p0, w1, z0\.s
--.*: 05b0a01f clasta wzr, p0, wzr, z0\.s
--.*: 05b0a01f clasta wzr, p0, wzr, z0\.s
--.*: 05b0a800 clasta w0, p2, w0, z0\.s
--.*: 05b0a800 clasta w0, p2, w0, z0\.s
--.*: 05b0bc00 clasta w0, p7, w0, z0\.s
--.*: 05b0bc00 clasta w0, p7, w0, z0\.s
--.*: 05b0a003 clasta w3, p0, w3, z0\.s
--.*: 05b0a003 clasta w3, p0, w3, z0\.s
--.*: 05b0a080 clasta w0, p0, w0, z4\.s
--.*: 05b0a080 clasta w0, p0, w0, z4\.s
--.*: 05b0a3e0 clasta w0, p0, w0, z31\.s
--.*: 05b0a3e0 clasta w0, p0, w0, z31\.s
--.*: 05f0a000 clasta x0, p0, x0, z0\.d
--.*: 05f0a000 clasta x0, p0, x0, z0\.d
--.*: 05f0a001 clasta x1, p0, x1, z0\.d
--.*: 05f0a001 clasta x1, p0, x1, z0\.d
--.*: 05f0a01f clasta xzr, p0, xzr, z0\.d
--.*: 05f0a01f clasta xzr, p0, xzr, z0\.d
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--.*: 04d9bc00 clz z0\.d, p7/m, z0\.d
--.*: 04d9a060 clz z0\.d, p0/m, z3\.d
--.*: 04d9a060 clz z0\.d, p0/m, z3\.d
--.*: 04d9a3e0 clz z0\.d, p0/m, z31\.d
--.*: 04d9a3e0 clz z0\.d, p0/m, z31\.d
--.*: 24002000 cmpeq p0\.b, p0/z, z0\.b, z0\.d
--.*: 24002000 cmpeq p0\.b, p0/z, z0\.b, z0\.d
--.*: 24002001 cmpeq p1\.b, p0/z, z0\.b, z0\.d
--.*: 24002001 cmpeq p1\.b, p0/z, z0\.b, z0\.d
--.*: 2400200f cmpeq p15\.b, p0/z, z0\.b, z0\.d
--.*: 2400200f cmpeq p15\.b, p0/z, z0\.b, z0\.d
--.*: 24002800 cmpeq p0\.b, p2/z, z0\.b, z0\.d
--.*: 24002800 cmpeq p0\.b, p2/z, z0\.b, z0\.d
--.*: 24003c00 cmpeq p0\.b, p7/z, z0\.b, z0\.d
--.*: 24003c00 cmpeq p0\.b, p7/z, z0\.b, z0\.d
--.*: 24002060 cmpeq p0\.b, p0/z, z3\.b, z0\.d
--.*: 24002060 cmpeq p0\.b, p0/z, z3\.b, z0\.d
--.*: 240023e0 cmpeq p0\.b, p0/z, z31\.b, z0\.d
--.*: 240023e0 cmpeq p0\.b, p0/z, z31\.b, z0\.d
--.*: 24042000 cmpeq p0\.b, p0/z, z0\.b, z4\.d
--.*: 24042000 cmpeq p0\.b, p0/z, z0\.b, z4\.d
--.*: 241f2000 cmpeq p0\.b, p0/z, z0\.b, z31\.d
--.*: 241f2000 cmpeq p0\.b, p0/z, z0\.b, z31\.d
--.*: 24402000 cmpeq p0\.h, p0/z, z0\.h, z0\.d
--.*: 24402000 cmpeq p0\.h, p0/z, z0\.h, z0\.d
--.*: 24402001 cmpeq p1\.h, p0/z, z0\.h, z0\.d
--.*: 24402001 cmpeq p1\.h, p0/z, z0\.h, z0\.d
--.*: 2440200f cmpeq p15\.h, p0/z, z0\.h, z0\.d
--.*: 2440200f cmpeq p15\.h, p0/z, z0\.h, z0\.d
--.*: 24402800 cmpeq p0\.h, p2/z, z0\.h, z0\.d
--.*: 24402800 cmpeq p0\.h, p2/z, z0\.h, z0\.d
--.*: 24403c00 cmpeq p0\.h, p7/z, z0\.h, z0\.d
--.*: 24403c00 cmpeq p0\.h, p7/z, z0\.h, z0\.d
--.*: 24402060 cmpeq p0\.h, p0/z, z3\.h, z0\.d
--.*: 24402060 cmpeq p0\.h, p0/z, z3\.h, z0\.d
--.*: 244023e0 cmpeq p0\.h, p0/z, z31\.h, z0\.d
--.*: 244023e0 cmpeq p0\.h, p0/z, z31\.h, z0\.d
--.*: 24442000 cmpeq p0\.h, p0/z, z0\.h, z4\.d
--.*: 24442000 cmpeq p0\.h, p0/z, z0\.h, z4\.d
--.*: 245f2000 cmpeq p0\.h, p0/z, z0\.h, z31\.d
--.*: 245f2000 cmpeq p0\.h, p0/z, z0\.h, z31\.d
--.*: 24802000 cmpeq p0\.s, p0/z, z0\.s, z0\.d
--.*: 24802000 cmpeq p0\.s, p0/z, z0\.s, z0\.d
--.*: 24802001 cmpeq p1\.s, p0/z, z0\.s, z0\.d
--.*: 24802001 cmpeq p1\.s, p0/z, z0\.s, z0\.d
--.*: 2480200f cmpeq p15\.s, p0/z, z0\.s, z0\.d
--.*: 2480200f cmpeq p15\.s, p0/z, z0\.s, z0\.d
--.*: 24802800 cmpeq p0\.s, p2/z, z0\.s, z0\.d
--.*: 24802800 cmpeq p0\.s, p2/z, z0\.s, z0\.d
--.*: 24803c00 cmpeq p0\.s, p7/z, z0\.s, z0\.d
--.*: 24803c00 cmpeq p0\.s, p7/z, z0\.s, z0\.d
--.*: 24802060 cmpeq p0\.s, p0/z, z3\.s, z0\.d
--.*: 24802060 cmpeq p0\.s, p0/z, z3\.s, z0\.d
--.*: 248023e0 cmpeq p0\.s, p0/z, z31\.s, z0\.d
--.*: 248023e0 cmpeq p0\.s, p0/z, z31\.s, z0\.d
--.*: 24842000 cmpeq p0\.s, p0/z, z0\.s, z4\.d
--.*: 24842000 cmpeq p0\.s, p0/z, z0\.s, z4\.d
--.*: 249f2000 cmpeq p0\.s, p0/z, z0\.s, z31\.d
--.*: 249f2000 cmpeq p0\.s, p0/z, z0\.s, z31\.d
--.*: 2400a000 cmpeq p0\.b, p0/z, z0\.b, z0\.b
--.*: 2400a000 cmpeq p0\.b, p0/z, z0\.b, z0\.b
--.*: 2400a001 cmpeq p1\.b, p0/z, z0\.b, z0\.b
--.*: 2400a001 cmpeq p1\.b, p0/z, z0\.b, z0\.b
--.*: 2400a00f cmpeq p15\.b, p0/z, z0\.b, z0\.b
--.*: 2400a00f cmpeq p15\.b, p0/z, z0\.b, z0\.b
--.*: 2400a800 cmpeq p0\.b, p2/z, z0\.b, z0\.b
--.*: 2400a800 cmpeq p0\.b, p2/z, z0\.b, z0\.b
--.*: 2400bc00 cmpeq p0\.b, p7/z, z0\.b, z0\.b
--.*: 2400bc00 cmpeq p0\.b, p7/z, z0\.b, z0\.b
--.*: 2400a060 cmpeq p0\.b, p0/z, z3\.b, z0\.b
--.*: 2400a060 cmpeq p0\.b, p0/z, z3\.b, z0\.b
--.*: 2400a3e0 cmpeq p0\.b, p0/z, z31\.b, z0\.b
--.*: 2400a3e0 cmpeq p0\.b, p0/z, z31\.b, z0\.b
--.*: 2404a000 cmpeq p0\.b, p0/z, z0\.b, z4\.b
--.*: 2404a000 cmpeq p0\.b, p0/z, z0\.b, z4\.b
--.*: 241fa000 cmpeq p0\.b, p0/z, z0\.b, z31\.b
--.*: 241fa000 cmpeq p0\.b, p0/z, z0\.b, z31\.b
--.*: 2440a000 cmpeq p0\.h, p0/z, z0\.h, z0\.h
--.*: 2440a000 cmpeq p0\.h, p0/z, z0\.h, z0\.h
--.*: 2440a001 cmpeq p1\.h, p0/z, z0\.h, z0\.h
--.*: 2440a001 cmpeq p1\.h, p0/z, z0\.h, z0\.h
--.*: 2440a00f cmpeq p15\.h, p0/z, z0\.h, z0\.h
--.*: 2440a00f cmpeq p15\.h, p0/z, z0\.h, z0\.h
--.*: 2440a800 cmpeq p0\.h, p2/z, z0\.h, z0\.h
--.*: 2440a800 cmpeq p0\.h, p2/z, z0\.h, z0\.h
--.*: 2440bc00 cmpeq p0\.h, p7/z, z0\.h, z0\.h
--.*: 2440bc00 cmpeq p0\.h, p7/z, z0\.h, z0\.h
--.*: 2440a060 cmpeq p0\.h, p0/z, z3\.h, z0\.h
--.*: 2440a060 cmpeq p0\.h, p0/z, z3\.h, z0\.h
--.*: 2440a3e0 cmpeq p0\.h, p0/z, z31\.h, z0\.h
--.*: 2440a3e0 cmpeq p0\.h, p0/z, z31\.h, z0\.h
--.*: 2444a000 cmpeq p0\.h, p0/z, z0\.h, z4\.h
--.*: 2444a000 cmpeq p0\.h, p0/z, z0\.h, z4\.h
--.*: 245fa000 cmpeq p0\.h, p0/z, z0\.h, z31\.h
--.*: 245fa000 cmpeq p0\.h, p0/z, z0\.h, z31\.h
--.*: 2480a000 cmpeq p0\.s, p0/z, z0\.s, z0\.s
--.*: 2480a000 cmpeq p0\.s, p0/z, z0\.s, z0\.s
--.*: 2480a001 cmpeq p1\.s, p0/z, z0\.s, z0\.s
--.*: 2480a001 cmpeq p1\.s, p0/z, z0\.s, z0\.s
--.*: 2480a00f cmpeq p15\.s, p0/z, z0\.s, z0\.s
--.*: 2480a00f cmpeq p15\.s, p0/z, z0\.s, z0\.s
--.*: 2480a800 cmpeq p0\.s, p2/z, z0\.s, z0\.s
--.*: 2480a800 cmpeq p0\.s, p2/z, z0\.s, z0\.s
--.*: 2480bc00 cmpeq p0\.s, p7/z, z0\.s, z0\.s
--.*: 2480bc00 cmpeq p0\.s, p7/z, z0\.s, z0\.s
--.*: 2480a060 cmpeq p0\.s, p0/z, z3\.s, z0\.s
--.*: 2480a060 cmpeq p0\.s, p0/z, z3\.s, z0\.s
--.*: 2480a3e0 cmpeq p0\.s, p0/z, z31\.s, z0\.s
--.*: 2480a3e0 cmpeq p0\.s, p0/z, z31\.s, z0\.s
--.*: 2484a000 cmpeq p0\.s, p0/z, z0\.s, z4\.s
--.*: 2484a000 cmpeq p0\.s, p0/z, z0\.s, z4\.s
--.*: 249fa000 cmpeq p0\.s, p0/z, z0\.s, z31\.s
--.*: 249fa000 cmpeq p0\.s, p0/z, z0\.s, z31\.s
--.*: 24c0a000 cmpeq p0\.d, p0/z, z0\.d, z0\.d
--.*: 24c0a000 cmpeq p0\.d, p0/z, z0\.d, z0\.d
--.*: 24c0a001 cmpeq p1\.d, p0/z, z0\.d, z0\.d
--.*: 24c0a001 cmpeq p1\.d, p0/z, z0\.d, z0\.d
--.*: 24c0a00f cmpeq p15\.d, p0/z, z0\.d, z0\.d
--.*: 24c0a00f cmpeq p15\.d, p0/z, z0\.d, z0\.d
--.*: 24c0a800 cmpeq p0\.d, p2/z, z0\.d, z0\.d
--.*: 24c0a800 cmpeq p0\.d, p2/z, z0\.d, z0\.d
--.*: 24c0bc00 cmpeq p0\.d, p7/z, z0\.d, z0\.d
--.*: 24c0bc00 cmpeq p0\.d, p7/z, z0\.d, z0\.d
--.*: 24c0a060 cmpeq p0\.d, p0/z, z3\.d, z0\.d
--.*: 24c0a060 cmpeq p0\.d, p0/z, z3\.d, z0\.d
--.*: 24c0a3e0 cmpeq p0\.d, p0/z, z31\.d, z0\.d
--.*: 24c0a3e0 cmpeq p0\.d, p0/z, z31\.d, z0\.d
--.*: 24c4a000 cmpeq p0\.d, p0/z, z0\.d, z4\.d
--.*: 24c4a000 cmpeq p0\.d, p0/z, z0\.d, z4\.d
--.*: 24dfa000 cmpeq p0\.d, p0/z, z0\.d, z31\.d
--.*: 24dfa000 cmpeq p0\.d, p0/z, z0\.d, z31\.d
--.*: 25008000 cmpeq p0\.b, p0/z, z0\.b, #0
--.*: 25008000 cmpeq p0\.b, p0/z, z0\.b, #0
--.*: 25008001 cmpeq p1\.b, p0/z, z0\.b, #0
--.*: 25008001 cmpeq p1\.b, p0/z, z0\.b, #0
--.*: 2500800f cmpeq p15\.b, p0/z, z0\.b, #0
--.*: 2500800f cmpeq p15\.b, p0/z, z0\.b, #0
--.*: 25008800 cmpeq p0\.b, p2/z, z0\.b, #0
--.*: 25008800 cmpeq p0\.b, p2/z, z0\.b, #0
--.*: 25009c00 cmpeq p0\.b, p7/z, z0\.b, #0
--.*: 25009c00 cmpeq p0\.b, p7/z, z0\.b, #0
--.*: 25008060 cmpeq p0\.b, p0/z, z3\.b, #0
--.*: 25008060 cmpeq p0\.b, p0/z, z3\.b, #0
--.*: 250083e0 cmpeq p0\.b, p0/z, z31\.b, #0
--.*: 250083e0 cmpeq p0\.b, p0/z, z31\.b, #0
--.*: 250f8000 cmpeq p0\.b, p0/z, z0\.b, #15
--.*: 250f8000 cmpeq p0\.b, p0/z, z0\.b, #15
--.*: 25108000 cmpeq p0\.b, p0/z, z0\.b, #-16
--.*: 25108000 cmpeq p0\.b, p0/z, z0\.b, #-16
--.*: 25118000 cmpeq p0\.b, p0/z, z0\.b, #-15
--.*: 25118000 cmpeq p0\.b, p0/z, z0\.b, #-15
--.*: 251f8000 cmpeq p0\.b, p0/z, z0\.b, #-1
--.*: 251f8000 cmpeq p0\.b, p0/z, z0\.b, #-1
--.*: 25408000 cmpeq p0\.h, p0/z, z0\.h, #0
--.*: 25408000 cmpeq p0\.h, p0/z, z0\.h, #0
--.*: 25408001 cmpeq p1\.h, p0/z, z0\.h, #0
--.*: 25408001 cmpeq p1\.h, p0/z, z0\.h, #0
--.*: 2540800f cmpeq p15\.h, p0/z, z0\.h, #0
--.*: 2540800f cmpeq p15\.h, p0/z, z0\.h, #0
--.*: 25408800 cmpeq p0\.h, p2/z, z0\.h, #0
--.*: 25408800 cmpeq p0\.h, p2/z, z0\.h, #0
--.*: 25409c00 cmpeq p0\.h, p7/z, z0\.h, #0
--.*: 25409c00 cmpeq p0\.h, p7/z, z0\.h, #0
--.*: 25408060 cmpeq p0\.h, p0/z, z3\.h, #0
--.*: 25408060 cmpeq p0\.h, p0/z, z3\.h, #0
--.*: 254083e0 cmpeq p0\.h, p0/z, z31\.h, #0
--.*: 254083e0 cmpeq p0\.h, p0/z, z31\.h, #0
--.*: 254f8000 cmpeq p0\.h, p0/z, z0\.h, #15
--.*: 254f8000 cmpeq p0\.h, p0/z, z0\.h, #15
--.*: 25508000 cmpeq p0\.h, p0/z, z0\.h, #-16
--.*: 25508000 cmpeq p0\.h, p0/z, z0\.h, #-16
--.*: 25518000 cmpeq p0\.h, p0/z, z0\.h, #-15
--.*: 25518000 cmpeq p0\.h, p0/z, z0\.h, #-15
--.*: 255f8000 cmpeq p0\.h, p0/z, z0\.h, #-1
--.*: 255f8000 cmpeq p0\.h, p0/z, z0\.h, #-1
--.*: 25808000 cmpeq p0\.s, p0/z, z0\.s, #0
--.*: 25808000 cmpeq p0\.s, p0/z, z0\.s, #0
--.*: 25808001 cmpeq p1\.s, p0/z, z0\.s, #0
--.*: 25808001 cmpeq p1\.s, p0/z, z0\.s, #0
--.*: 2580800f cmpeq p15\.s, p0/z, z0\.s, #0
--.*: 2580800f cmpeq p15\.s, p0/z, z0\.s, #0
--.*: 25808800 cmpeq p0\.s, p2/z, z0\.s, #0
--.*: 25808800 cmpeq p0\.s, p2/z, z0\.s, #0
--.*: 25809c00 cmpeq p0\.s, p7/z, z0\.s, #0
--.*: 25809c00 cmpeq p0\.s, p7/z, z0\.s, #0
--.*: 25808060 cmpeq p0\.s, p0/z, z3\.s, #0
--.*: 25808060 cmpeq p0\.s, p0/z, z3\.s, #0
--.*: 258083e0 cmpeq p0\.s, p0/z, z31\.s, #0
--.*: 258083e0 cmpeq p0\.s, p0/z, z31\.s, #0
--.*: 258f8000 cmpeq p0\.s, p0/z, z0\.s, #15
--.*: 258f8000 cmpeq p0\.s, p0/z, z0\.s, #15
--.*: 25908000 cmpeq p0\.s, p0/z, z0\.s, #-16
--.*: 25908000 cmpeq p0\.s, p0/z, z0\.s, #-16
--.*: 25918000 cmpeq p0\.s, p0/z, z0\.s, #-15
--.*: 25918000 cmpeq p0\.s, p0/z, z0\.s, #-15
--.*: 259f8000 cmpeq p0\.s, p0/z, z0\.s, #-1
--.*: 259f8000 cmpeq p0\.s, p0/z, z0\.s, #-1
--.*: 25c08000 cmpeq p0\.d, p0/z, z0\.d, #0
--.*: 25c08000 cmpeq p0\.d, p0/z, z0\.d, #0
--.*: 25c08001 cmpeq p1\.d, p0/z, z0\.d, #0
--.*: 25c08001 cmpeq p1\.d, p0/z, z0\.d, #0
--.*: 25c0800f cmpeq p15\.d, p0/z, z0\.d, #0
--.*: 25c0800f cmpeq p15\.d, p0/z, z0\.d, #0
--.*: 25c08800 cmpeq p0\.d, p2/z, z0\.d, #0
--.*: 25c08800 cmpeq p0\.d, p2/z, z0\.d, #0
--.*: 25c09c00 cmpeq p0\.d, p7/z, z0\.d, #0
--.*: 25c09c00 cmpeq p0\.d, p7/z, z0\.d, #0
--.*: 25c08060 cmpeq p0\.d, p0/z, z3\.d, #0
--.*: 25c08060 cmpeq p0\.d, p0/z, z3\.d, #0
--.*: 25c083e0 cmpeq p0\.d, p0/z, z31\.d, #0
--.*: 25c083e0 cmpeq p0\.d, p0/z, z31\.d, #0
--.*: 25cf8000 cmpeq p0\.d, p0/z, z0\.d, #15
--.*: 25cf8000 cmpeq p0\.d, p0/z, z0\.d, #15
--.*: 25d08000 cmpeq p0\.d, p0/z, z0\.d, #-16
--.*: 25d08000 cmpeq p0\.d, p0/z, z0\.d, #-16
--.*: 25d18000 cmpeq p0\.d, p0/z, z0\.d, #-15
--.*: 25d18000 cmpeq p0\.d, p0/z, z0\.d, #-15
--.*: 25df8000 cmpeq p0\.d, p0/z, z0\.d, #-1
--.*: 25df8000 cmpeq p0\.d, p0/z, z0\.d, #-1
--.*: 24004000 cmpge p0\.b, p0/z, z0\.b, z0\.d
--.*: 24004000 cmpge p0\.b, p0/z, z0\.b, z0\.d
--.*: 24004001 cmpge p1\.b, p0/z, z0\.b, z0\.d
--.*: 24004001 cmpge p1\.b, p0/z, z0\.b, z0\.d
--.*: 2400400f cmpge p15\.b, p0/z, z0\.b, z0\.d
--.*: 2400400f cmpge p15\.b, p0/z, z0\.b, z0\.d
--.*: 24004800 cmpge p0\.b, p2/z, z0\.b, z0\.d
--.*: 24004800 cmpge p0\.b, p2/z, z0\.b, z0\.d
--.*: 24005c00 cmpge p0\.b, p7/z, z0\.b, z0\.d
--.*: 24005c00 cmpge p0\.b, p7/z, z0\.b, z0\.d
--.*: 24004060 cmpge p0\.b, p0/z, z3\.b, z0\.d
--.*: 24004060 cmpge p0\.b, p0/z, z3\.b, z0\.d
--.*: 240043e0 cmpge p0\.b, p0/z, z31\.b, z0\.d
--.*: 240043e0 cmpge p0\.b, p0/z, z31\.b, z0\.d
--.*: 24044000 cmpge p0\.b, p0/z, z0\.b, z4\.d
--.*: 24044000 cmpge p0\.b, p0/z, z0\.b, z4\.d
--.*: 241f4000 cmpge p0\.b, p0/z, z0\.b, z31\.d
--.*: 241f4000 cmpge p0\.b, p0/z, z0\.b, z31\.d
--.*: 24404000 cmpge p0\.h, p0/z, z0\.h, z0\.d
--.*: 24404000 cmpge p0\.h, p0/z, z0\.h, z0\.d
--.*: 24404001 cmpge p1\.h, p0/z, z0\.h, z0\.d
--.*: 24404001 cmpge p1\.h, p0/z, z0\.h, z0\.d
--.*: 2440400f cmpge p15\.h, p0/z, z0\.h, z0\.d
--.*: 2440400f cmpge p15\.h, p0/z, z0\.h, z0\.d
--.*: 24404800 cmpge p0\.h, p2/z, z0\.h, z0\.d
--.*: 24404800 cmpge p0\.h, p2/z, z0\.h, z0\.d
--.*: 24405c00 cmpge p0\.h, p7/z, z0\.h, z0\.d
--.*: 24405c00 cmpge p0\.h, p7/z, z0\.h, z0\.d
--.*: 24404060 cmpge p0\.h, p0/z, z3\.h, z0\.d
--.*: 24404060 cmpge p0\.h, p0/z, z3\.h, z0\.d
--.*: 244043e0 cmpge p0\.h, p0/z, z31\.h, z0\.d
--.*: 244043e0 cmpge p0\.h, p0/z, z31\.h, z0\.d
--.*: 24444000 cmpge p0\.h, p0/z, z0\.h, z4\.d
--.*: 24444000 cmpge p0\.h, p0/z, z0\.h, z4\.d
--.*: 245f4000 cmpge p0\.h, p0/z, z0\.h, z31\.d
--.*: 245f4000 cmpge p0\.h, p0/z, z0\.h, z31\.d
--.*: 24804000 cmpge p0\.s, p0/z, z0\.s, z0\.d
--.*: 24804000 cmpge p0\.s, p0/z, z0\.s, z0\.d
--.*: 24804001 cmpge p1\.s, p0/z, z0\.s, z0\.d
--.*: 24804001 cmpge p1\.s, p0/z, z0\.s, z0\.d
--.*: 2480400f cmpge p15\.s, p0/z, z0\.s, z0\.d
--.*: 2480400f cmpge p15\.s, p0/z, z0\.s, z0\.d
--.*: 24804800 cmpge p0\.s, p2/z, z0\.s, z0\.d
--.*: 24804800 cmpge p0\.s, p2/z, z0\.s, z0\.d
--.*: 24805c00 cmpge p0\.s, p7/z, z0\.s, z0\.d
--.*: 24805c00 cmpge p0\.s, p7/z, z0\.s, z0\.d
--.*: 24804060 cmpge p0\.s, p0/z, z3\.s, z0\.d
--.*: 24804060 cmpge p0\.s, p0/z, z3\.s, z0\.d
--.*: 248043e0 cmpge p0\.s, p0/z, z31\.s, z0\.d
--.*: 248043e0 cmpge p0\.s, p0/z, z31\.s, z0\.d
--.*: 24844000 cmpge p0\.s, p0/z, z0\.s, z4\.d
--.*: 24844000 cmpge p0\.s, p0/z, z0\.s, z4\.d
--.*: 249f4000 cmpge p0\.s, p0/z, z0\.s, z31\.d
--.*: 249f4000 cmpge p0\.s, p0/z, z0\.s, z31\.d
--.*: 24008000 cmpge p0\.b, p0/z, z0\.b, z0\.b
--.*: 24008000 cmpge p0\.b, p0/z, z0\.b, z0\.b
--.*: 24008001 cmpge p1\.b, p0/z, z0\.b, z0\.b
--.*: 24008001 cmpge p1\.b, p0/z, z0\.b, z0\.b
--.*: 2400800f cmpge p15\.b, p0/z, z0\.b, z0\.b
--.*: 2400800f cmpge p15\.b, p0/z, z0\.b, z0\.b
--.*: 24008800 cmpge p0\.b, p2/z, z0\.b, z0\.b
--.*: 24008800 cmpge p0\.b, p2/z, z0\.b, z0\.b
--.*: 24009c00 cmpge p0\.b, p7/z, z0\.b, z0\.b
--.*: 24009c00 cmpge p0\.b, p7/z, z0\.b, z0\.b
--.*: 24008060 cmpge p0\.b, p0/z, z3\.b, z0\.b
--.*: 24008060 cmpge p0\.b, p0/z, z3\.b, z0\.b
--.*: 240083e0 cmpge p0\.b, p0/z, z31\.b, z0\.b
--.*: 240083e0 cmpge p0\.b, p0/z, z31\.b, z0\.b
--.*: 24048000 cmpge p0\.b, p0/z, z0\.b, z4\.b
--.*: 24048000 cmpge p0\.b, p0/z, z0\.b, z4\.b
--.*: 241f8000 cmpge p0\.b, p0/z, z0\.b, z31\.b
--.*: 241f8000 cmpge p0\.b, p0/z, z0\.b, z31\.b
--.*: 24408000 cmpge p0\.h, p0/z, z0\.h, z0\.h
--.*: 24408000 cmpge p0\.h, p0/z, z0\.h, z0\.h
--.*: 24408001 cmpge p1\.h, p0/z, z0\.h, z0\.h
--.*: 24408001 cmpge p1\.h, p0/z, z0\.h, z0\.h
--.*: 2440800f cmpge p15\.h, p0/z, z0\.h, z0\.h
--.*: 2440800f cmpge p15\.h, p0/z, z0\.h, z0\.h
--.*: 24408800 cmpge p0\.h, p2/z, z0\.h, z0\.h
--.*: 24408800 cmpge p0\.h, p2/z, z0\.h, z0\.h
--.*: 24409c00 cmpge p0\.h, p7/z, z0\.h, z0\.h
--.*: 24409c00 cmpge p0\.h, p7/z, z0\.h, z0\.h
--.*: 24408060 cmpge p0\.h, p0/z, z3\.h, z0\.h
--.*: 24408060 cmpge p0\.h, p0/z, z3\.h, z0\.h
--.*: 244083e0 cmpge p0\.h, p0/z, z31\.h, z0\.h
--.*: 244083e0 cmpge p0\.h, p0/z, z31\.h, z0\.h
--.*: 24448000 cmpge p0\.h, p0/z, z0\.h, z4\.h
--.*: 24448000 cmpge p0\.h, p0/z, z0\.h, z4\.h
--.*: 245f8000 cmpge p0\.h, p0/z, z0\.h, z31\.h
--.*: 245f8000 cmpge p0\.h, p0/z, z0\.h, z31\.h
--.*: 24808000 cmpge p0\.s, p0/z, z0\.s, z0\.s
--.*: 24808000 cmpge p0\.s, p0/z, z0\.s, z0\.s
--.*: 24808001 cmpge p1\.s, p0/z, z0\.s, z0\.s
--.*: 24808001 cmpge p1\.s, p0/z, z0\.s, z0\.s
--.*: 2480800f cmpge p15\.s, p0/z, z0\.s, z0\.s
--.*: 2480800f cmpge p15\.s, p0/z, z0\.s, z0\.s
--.*: 24808800 cmpge p0\.s, p2/z, z0\.s, z0\.s
--.*: 24808800 cmpge p0\.s, p2/z, z0\.s, z0\.s
--.*: 24809c00 cmpge p0\.s, p7/z, z0\.s, z0\.s
--.*: 24809c00 cmpge p0\.s, p7/z, z0\.s, z0\.s
--.*: 24808060 cmpge p0\.s, p0/z, z3\.s, z0\.s
--.*: 24808060 cmpge p0\.s, p0/z, z3\.s, z0\.s
--.*: 248083e0 cmpge p0\.s, p0/z, z31\.s, z0\.s
--.*: 248083e0 cmpge p0\.s, p0/z, z31\.s, z0\.s
--.*: 24848000 cmpge p0\.s, p0/z, z0\.s, z4\.s
--.*: 24848000 cmpge p0\.s, p0/z, z0\.s, z4\.s
--.*: 249f8000 cmpge p0\.s, p0/z, z0\.s, z31\.s
--.*: 249f8000 cmpge p0\.s, p0/z, z0\.s, z31\.s
--.*: 24c08000 cmpge p0\.d, p0/z, z0\.d, z0\.d
--.*: 24c08000 cmpge p0\.d, p0/z, z0\.d, z0\.d
--.*: 24c08001 cmpge p1\.d, p0/z, z0\.d, z0\.d
--.*: 24c08001 cmpge p1\.d, p0/z, z0\.d, z0\.d
--.*: 24c0800f cmpge p15\.d, p0/z, z0\.d, z0\.d
--.*: 24c0800f cmpge p15\.d, p0/z, z0\.d, z0\.d
--.*: 24c08800 cmpge p0\.d, p2/z, z0\.d, z0\.d
--.*: 24c08800 cmpge p0\.d, p2/z, z0\.d, z0\.d
--.*: 24c09c00 cmpge p0\.d, p7/z, z0\.d, z0\.d
--.*: 24c09c00 cmpge p0\.d, p7/z, z0\.d, z0\.d
--.*: 24c08060 cmpge p0\.d, p0/z, z3\.d, z0\.d
--.*: 24c08060 cmpge p0\.d, p0/z, z3\.d, z0\.d
--.*: 24c083e0 cmpge p0\.d, p0/z, z31\.d, z0\.d
--.*: 24c083e0 cmpge p0\.d, p0/z, z31\.d, z0\.d
--.*: 24c48000 cmpge p0\.d, p0/z, z0\.d, z4\.d
--.*: 24c48000 cmpge p0\.d, p0/z, z0\.d, z4\.d
--.*: 24df8000 cmpge p0\.d, p0/z, z0\.d, z31\.d
--.*: 24df8000 cmpge p0\.d, p0/z, z0\.d, z31\.d
--.*: 25000000 cmpge p0\.b, p0/z, z0\.b, #0
--.*: 25000000 cmpge p0\.b, p0/z, z0\.b, #0
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--.*: 25000001 cmpge p1\.b, p0/z, z0\.b, #0
--.*: 2500000f cmpge p15\.b, p0/z, z0\.b, #0
--.*: 2500000f cmpge p15\.b, p0/z, z0\.b, #0
--.*: 25000800 cmpge p0\.b, p2/z, z0\.b, #0
--.*: 25000800 cmpge p0\.b, p2/z, z0\.b, #0
--.*: 25001c00 cmpge p0\.b, p7/z, z0\.b, #0
--.*: 25001c00 cmpge p0\.b, p7/z, z0\.b, #0
--.*: 25000060 cmpge p0\.b, p0/z, z3\.b, #0
--.*: 25000060 cmpge p0\.b, p0/z, z3\.b, #0
--.*: 250003e0 cmpge p0\.b, p0/z, z31\.b, #0
--.*: 250003e0 cmpge p0\.b, p0/z, z31\.b, #0
--.*: 250f0000 cmpge p0\.b, p0/z, z0\.b, #15
--.*: 250f0000 cmpge p0\.b, p0/z, z0\.b, #15
--.*: 25100000 cmpge p0\.b, p0/z, z0\.b, #-16
--.*: 25100000 cmpge p0\.b, p0/z, z0\.b, #-16
--.*: 25110000 cmpge p0\.b, p0/z, z0\.b, #-15
--.*: 25110000 cmpge p0\.b, p0/z, z0\.b, #-15
--.*: 251f0000 cmpge p0\.b, p0/z, z0\.b, #-1
--.*: 251f0000 cmpge p0\.b, p0/z, z0\.b, #-1
--.*: 25400000 cmpge p0\.h, p0/z, z0\.h, #0
--.*: 25400000 cmpge p0\.h, p0/z, z0\.h, #0
--.*: 25400001 cmpge p1\.h, p0/z, z0\.h, #0
--.*: 25400001 cmpge p1\.h, p0/z, z0\.h, #0
--.*: 2540000f cmpge p15\.h, p0/z, z0\.h, #0
--.*: 2540000f cmpge p15\.h, p0/z, z0\.h, #0
--.*: 25400800 cmpge p0\.h, p2/z, z0\.h, #0
--.*: 25400800 cmpge p0\.h, p2/z, z0\.h, #0
--.*: 25401c00 cmpge p0\.h, p7/z, z0\.h, #0
--.*: 25401c00 cmpge p0\.h, p7/z, z0\.h, #0
--.*: 25400060 cmpge p0\.h, p0/z, z3\.h, #0
--.*: 25400060 cmpge p0\.h, p0/z, z3\.h, #0
--.*: 254003e0 cmpge p0\.h, p0/z, z31\.h, #0
--.*: 254003e0 cmpge p0\.h, p0/z, z31\.h, #0
--.*: 254f0000 cmpge p0\.h, p0/z, z0\.h, #15
--.*: 254f0000 cmpge p0\.h, p0/z, z0\.h, #15
--.*: 25500000 cmpge p0\.h, p0/z, z0\.h, #-16
--.*: 25500000 cmpge p0\.h, p0/z, z0\.h, #-16
--.*: 25510000 cmpge p0\.h, p0/z, z0\.h, #-15
--.*: 25510000 cmpge p0\.h, p0/z, z0\.h, #-15
--.*: 255f0000 cmpge p0\.h, p0/z, z0\.h, #-1
--.*: 255f0000 cmpge p0\.h, p0/z, z0\.h, #-1
--.*: 25800000 cmpge p0\.s, p0/z, z0\.s, #0
--.*: 25800000 cmpge p0\.s, p0/z, z0\.s, #0
--.*: 25800001 cmpge p1\.s, p0/z, z0\.s, #0
--.*: 25800001 cmpge p1\.s, p0/z, z0\.s, #0
--.*: 2580000f cmpge p15\.s, p0/z, z0\.s, #0
--.*: 2580000f cmpge p15\.s, p0/z, z0\.s, #0
--.*: 25800800 cmpge p0\.s, p2/z, z0\.s, #0
--.*: 25800800 cmpge p0\.s, p2/z, z0\.s, #0
--.*: 25801c00 cmpge p0\.s, p7/z, z0\.s, #0
--.*: 25801c00 cmpge p0\.s, p7/z, z0\.s, #0
--.*: 25800060 cmpge p0\.s, p0/z, z3\.s, #0
--.*: 25800060 cmpge p0\.s, p0/z, z3\.s, #0
--.*: 258003e0 cmpge p0\.s, p0/z, z31\.s, #0
--.*: 258003e0 cmpge p0\.s, p0/z, z31\.s, #0
--.*: 258f0000 cmpge p0\.s, p0/z, z0\.s, #15
--.*: 258f0000 cmpge p0\.s, p0/z, z0\.s, #15
--.*: 25900000 cmpge p0\.s, p0/z, z0\.s, #-16
--.*: 25900000 cmpge p0\.s, p0/z, z0\.s, #-16
--.*: 25910000 cmpge p0\.s, p0/z, z0\.s, #-15
--.*: 25910000 cmpge p0\.s, p0/z, z0\.s, #-15
--.*: 259f0000 cmpge p0\.s, p0/z, z0\.s, #-1
--.*: 259f0000 cmpge p0\.s, p0/z, z0\.s, #-1
--.*: 25c00000 cmpge p0\.d, p0/z, z0\.d, #0
--.*: 25c00000 cmpge p0\.d, p0/z, z0\.d, #0
--.*: 25c00001 cmpge p1\.d, p0/z, z0\.d, #0
--.*: 25c00001 cmpge p1\.d, p0/z, z0\.d, #0
--.*: 25c0000f cmpge p15\.d, p0/z, z0\.d, #0
--.*: 25c0000f cmpge p15\.d, p0/z, z0\.d, #0
--.*: 25c00800 cmpge p0\.d, p2/z, z0\.d, #0
--.*: 25c00800 cmpge p0\.d, p2/z, z0\.d, #0
--.*: 25c01c00 cmpge p0\.d, p7/z, z0\.d, #0
--.*: 25c01c00 cmpge p0\.d, p7/z, z0\.d, #0
--.*: 25c00060 cmpge p0\.d, p0/z, z3\.d, #0
--.*: 25c00060 cmpge p0\.d, p0/z, z3\.d, #0
--.*: 25c003e0 cmpge p0\.d, p0/z, z31\.d, #0
--.*: 25c003e0 cmpge p0\.d, p0/z, z31\.d, #0
--.*: 25cf0000 cmpge p0\.d, p0/z, z0\.d, #15
--.*: 25cf0000 cmpge p0\.d, p0/z, z0\.d, #15
--.*: 25d00000 cmpge p0\.d, p0/z, z0\.d, #-16
--.*: 25d00000 cmpge p0\.d, p0/z, z0\.d, #-16
--.*: 25d10000 cmpge p0\.d, p0/z, z0\.d, #-15
--.*: 25d10000 cmpge p0\.d, p0/z, z0\.d, #-15
--.*: 25df0000 cmpge p0\.d, p0/z, z0\.d, #-1
--.*: 25df0000 cmpge p0\.d, p0/z, z0\.d, #-1
--.*: 24004010 cmpgt p0\.b, p0/z, z0\.b, z0\.d
--.*: 24004010 cmpgt p0\.b, p0/z, z0\.b, z0\.d
--.*: 24004011 cmpgt p1\.b, p0/z, z0\.b, z0\.d
--.*: 24004011 cmpgt p1\.b, p0/z, z0\.b, z0\.d
--.*: 2400401f cmpgt p15\.b, p0/z, z0\.b, z0\.d
--.*: 2400401f cmpgt p15\.b, p0/z, z0\.b, z0\.d
--.*: 24004810 cmpgt p0\.b, p2/z, z0\.b, z0\.d
--.*: 24004810 cmpgt p0\.b, p2/z, z0\.b, z0\.d
--.*: 24005c10 cmpgt p0\.b, p7/z, z0\.b, z0\.d
--.*: 24005c10 cmpgt p0\.b, p7/z, z0\.b, z0\.d
--.*: 24004070 cmpgt p0\.b, p0/z, z3\.b, z0\.d
--.*: 24004070 cmpgt p0\.b, p0/z, z3\.b, z0\.d
--.*: 240043f0 cmpgt p0\.b, p0/z, z31\.b, z0\.d
--.*: 240043f0 cmpgt p0\.b, p0/z, z31\.b, z0\.d
--.*: 24044010 cmpgt p0\.b, p0/z, z0\.b, z4\.d
--.*: 24044010 cmpgt p0\.b, p0/z, z0\.b, z4\.d
--.*: 241f4010 cmpgt p0\.b, p0/z, z0\.b, z31\.d
--.*: 241f4010 cmpgt p0\.b, p0/z, z0\.b, z31\.d
--.*: 24404010 cmpgt p0\.h, p0/z, z0\.h, z0\.d
--.*: 24404010 cmpgt p0\.h, p0/z, z0\.h, z0\.d
--.*: 24404011 cmpgt p1\.h, p0/z, z0\.h, z0\.d
--.*: 24404011 cmpgt p1\.h, p0/z, z0\.h, z0\.d
--.*: 2440401f cmpgt p15\.h, p0/z, z0\.h, z0\.d
--.*: 2440401f cmpgt p15\.h, p0/z, z0\.h, z0\.d
--.*: 24404810 cmpgt p0\.h, p2/z, z0\.h, z0\.d
--.*: 24404810 cmpgt p0\.h, p2/z, z0\.h, z0\.d
--.*: 24405c10 cmpgt p0\.h, p7/z, z0\.h, z0\.d
--.*: 24405c10 cmpgt p0\.h, p7/z, z0\.h, z0\.d
--.*: 24404070 cmpgt p0\.h, p0/z, z3\.h, z0\.d
--.*: 24404070 cmpgt p0\.h, p0/z, z3\.h, z0\.d
--.*: 244043f0 cmpgt p0\.h, p0/z, z31\.h, z0\.d
--.*: 244043f0 cmpgt p0\.h, p0/z, z31\.h, z0\.d
--.*: 24444010 cmpgt p0\.h, p0/z, z0\.h, z4\.d
--.*: 24444010 cmpgt p0\.h, p0/z, z0\.h, z4\.d
--.*: 245f4010 cmpgt p0\.h, p0/z, z0\.h, z31\.d
--.*: 245f4010 cmpgt p0\.h, p0/z, z0\.h, z31\.d
--.*: 24804010 cmpgt p0\.s, p0/z, z0\.s, z0\.d
--.*: 24804010 cmpgt p0\.s, p0/z, z0\.s, z0\.d
--.*: 24804011 cmpgt p1\.s, p0/z, z0\.s, z0\.d
--.*: 24804011 cmpgt p1\.s, p0/z, z0\.s, z0\.d
--.*: 2480401f cmpgt p15\.s, p0/z, z0\.s, z0\.d
--.*: 2480401f cmpgt p15\.s, p0/z, z0\.s, z0\.d
--.*: 24804810 cmpgt p0\.s, p2/z, z0\.s, z0\.d
--.*: 24804810 cmpgt p0\.s, p2/z, z0\.s, z0\.d
--.*: 24805c10 cmpgt p0\.s, p7/z, z0\.s, z0\.d
--.*: 24805c10 cmpgt p0\.s, p7/z, z0\.s, z0\.d
--.*: 24804070 cmpgt p0\.s, p0/z, z3\.s, z0\.d
--.*: 24804070 cmpgt p0\.s, p0/z, z3\.s, z0\.d
--.*: 248043f0 cmpgt p0\.s, p0/z, z31\.s, z0\.d
--.*: 248043f0 cmpgt p0\.s, p0/z, z31\.s, z0\.d
--.*: 24844010 cmpgt p0\.s, p0/z, z0\.s, z4\.d
--.*: 24844010 cmpgt p0\.s, p0/z, z0\.s, z4\.d
--.*: 249f4010 cmpgt p0\.s, p0/z, z0\.s, z31\.d
--.*: 249f4010 cmpgt p0\.s, p0/z, z0\.s, z31\.d
--.*: 24008010 cmpgt p0\.b, p0/z, z0\.b, z0\.b
--.*: 24008010 cmpgt p0\.b, p0/z, z0\.b, z0\.b
--.*: 24008011 cmpgt p1\.b, p0/z, z0\.b, z0\.b
--.*: 24008011 cmpgt p1\.b, p0/z, z0\.b, z0\.b
--.*: 2400801f cmpgt p15\.b, p0/z, z0\.b, z0\.b
--.*: 2400801f cmpgt p15\.b, p0/z, z0\.b, z0\.b
--.*: 24008810 cmpgt p0\.b, p2/z, z0\.b, z0\.b
--.*: 24008810 cmpgt p0\.b, p2/z, z0\.b, z0\.b
--.*: 24009c10 cmpgt p0\.b, p7/z, z0\.b, z0\.b
--.*: 24009c10 cmpgt p0\.b, p7/z, z0\.b, z0\.b
--.*: 24008070 cmpgt p0\.b, p0/z, z3\.b, z0\.b
--.*: 24008070 cmpgt p0\.b, p0/z, z3\.b, z0\.b
--.*: 240083f0 cmpgt p0\.b, p0/z, z31\.b, z0\.b
--.*: 240083f0 cmpgt p0\.b, p0/z, z31\.b, z0\.b
--.*: 24048010 cmpgt p0\.b, p0/z, z0\.b, z4\.b
--.*: 24048010 cmpgt p0\.b, p0/z, z0\.b, z4\.b
--.*: 241f8010 cmpgt p0\.b, p0/z, z0\.b, z31\.b
--.*: 241f8010 cmpgt p0\.b, p0/z, z0\.b, z31\.b
--.*: 24408010 cmpgt p0\.h, p0/z, z0\.h, z0\.h
--.*: 24408010 cmpgt p0\.h, p0/z, z0\.h, z0\.h
--.*: 24408011 cmpgt p1\.h, p0/z, z0\.h, z0\.h
--.*: 24408011 cmpgt p1\.h, p0/z, z0\.h, z0\.h
--.*: 2440801f cmpgt p15\.h, p0/z, z0\.h, z0\.h
--.*: 2440801f cmpgt p15\.h, p0/z, z0\.h, z0\.h
--.*: 24408810 cmpgt p0\.h, p2/z, z0\.h, z0\.h
--.*: 24408810 cmpgt p0\.h, p2/z, z0\.h, z0\.h
--.*: 24409c10 cmpgt p0\.h, p7/z, z0\.h, z0\.h
--.*: 24409c10 cmpgt p0\.h, p7/z, z0\.h, z0\.h
--.*: 24408070 cmpgt p0\.h, p0/z, z3\.h, z0\.h
--.*: 24408070 cmpgt p0\.h, p0/z, z3\.h, z0\.h
--.*: 244083f0 cmpgt p0\.h, p0/z, z31\.h, z0\.h
--.*: 244083f0 cmpgt p0\.h, p0/z, z31\.h, z0\.h
--.*: 24448010 cmpgt p0\.h, p0/z, z0\.h, z4\.h
--.*: 24448010 cmpgt p0\.h, p0/z, z0\.h, z4\.h
--.*: 245f8010 cmpgt p0\.h, p0/z, z0\.h, z31\.h
--.*: 245f8010 cmpgt p0\.h, p0/z, z0\.h, z31\.h
--.*: 24808010 cmpgt p0\.s, p0/z, z0\.s, z0\.s
--.*: 24808010 cmpgt p0\.s, p0/z, z0\.s, z0\.s
--.*: 24808011 cmpgt p1\.s, p0/z, z0\.s, z0\.s
--.*: 24808011 cmpgt p1\.s, p0/z, z0\.s, z0\.s
--.*: 2480801f cmpgt p15\.s, p0/z, z0\.s, z0\.s
--.*: 2480801f cmpgt p15\.s, p0/z, z0\.s, z0\.s
--.*: 24808810 cmpgt p0\.s, p2/z, z0\.s, z0\.s
--.*: 24808810 cmpgt p0\.s, p2/z, z0\.s, z0\.s
--.*: 24809c10 cmpgt p0\.s, p7/z, z0\.s, z0\.s
--.*: 24809c10 cmpgt p0\.s, p7/z, z0\.s, z0\.s
--.*: 24808070 cmpgt p0\.s, p0/z, z3\.s, z0\.s
--.*: 24808070 cmpgt p0\.s, p0/z, z3\.s, z0\.s
--.*: 248083f0 cmpgt p0\.s, p0/z, z31\.s, z0\.s
--.*: 248083f0 cmpgt p0\.s, p0/z, z31\.s, z0\.s
--.*: 24848010 cmpgt p0\.s, p0/z, z0\.s, z4\.s
--.*: 24848010 cmpgt p0\.s, p0/z, z0\.s, z4\.s
--.*: 249f8010 cmpgt p0\.s, p0/z, z0\.s, z31\.s
--.*: 249f8010 cmpgt p0\.s, p0/z, z0\.s, z31\.s
--.*: 24c08010 cmpgt p0\.d, p0/z, z0\.d, z0\.d
--.*: 24c08010 cmpgt p0\.d, p0/z, z0\.d, z0\.d
--.*: 24c08011 cmpgt p1\.d, p0/z, z0\.d, z0\.d
--.*: 24c08011 cmpgt p1\.d, p0/z, z0\.d, z0\.d
--.*: 24c0801f cmpgt p15\.d, p0/z, z0\.d, z0\.d
--.*: 24c0801f cmpgt p15\.d, p0/z, z0\.d, z0\.d
--.*: 24c08810 cmpgt p0\.d, p2/z, z0\.d, z0\.d
--.*: 24c08810 cmpgt p0\.d, p2/z, z0\.d, z0\.d
--.*: 24c09c10 cmpgt p0\.d, p7/z, z0\.d, z0\.d
--.*: 24c09c10 cmpgt p0\.d, p7/z, z0\.d, z0\.d
--.*: 24c08070 cmpgt p0\.d, p0/z, z3\.d, z0\.d
--.*: 24c08070 cmpgt p0\.d, p0/z, z3\.d, z0\.d
--.*: 24c083f0 cmpgt p0\.d, p0/z, z31\.d, z0\.d
--.*: 24c083f0 cmpgt p0\.d, p0/z, z31\.d, z0\.d
--.*: 24c48010 cmpgt p0\.d, p0/z, z0\.d, z4\.d
--.*: 24c48010 cmpgt p0\.d, p0/z, z0\.d, z4\.d
--.*: 24df8010 cmpgt p0\.d, p0/z, z0\.d, z31\.d
--.*: 24df8010 cmpgt p0\.d, p0/z, z0\.d, z31\.d
--.*: 25000010 cmpgt p0\.b, p0/z, z0\.b, #0
--.*: 25000010 cmpgt p0\.b, p0/z, z0\.b, #0
--.*: 25000011 cmpgt p1\.b, p0/z, z0\.b, #0
--.*: 25000011 cmpgt p1\.b, p0/z, z0\.b, #0
--.*: 2500001f cmpgt p15\.b, p0/z, z0\.b, #0
--.*: 2500001f cmpgt p15\.b, p0/z, z0\.b, #0
--.*: 25000810 cmpgt p0\.b, p2/z, z0\.b, #0
--.*: 25000810 cmpgt p0\.b, p2/z, z0\.b, #0
--.*: 25001c10 cmpgt p0\.b, p7/z, z0\.b, #0
--.*: 25001c10 cmpgt p0\.b, p7/z, z0\.b, #0
--.*: 25000070 cmpgt p0\.b, p0/z, z3\.b, #0
--.*: 25000070 cmpgt p0\.b, p0/z, z3\.b, #0
--.*: 250003f0 cmpgt p0\.b, p0/z, z31\.b, #0
--.*: 250003f0 cmpgt p0\.b, p0/z, z31\.b, #0
--.*: 250f0010 cmpgt p0\.b, p0/z, z0\.b, #15
--.*: 250f0010 cmpgt p0\.b, p0/z, z0\.b, #15
--.*: 25100010 cmpgt p0\.b, p0/z, z0\.b, #-16
--.*: 25100010 cmpgt p0\.b, p0/z, z0\.b, #-16
--.*: 25110010 cmpgt p0\.b, p0/z, z0\.b, #-15
--.*: 25110010 cmpgt p0\.b, p0/z, z0\.b, #-15
--.*: 251f0010 cmpgt p0\.b, p0/z, z0\.b, #-1
--.*: 251f0010 cmpgt p0\.b, p0/z, z0\.b, #-1
--.*: 25400010 cmpgt p0\.h, p0/z, z0\.h, #0
--.*: 25400010 cmpgt p0\.h, p0/z, z0\.h, #0
--.*: 25400011 cmpgt p1\.h, p0/z, z0\.h, #0
--.*: 25400011 cmpgt p1\.h, p0/z, z0\.h, #0
--.*: 2540001f cmpgt p15\.h, p0/z, z0\.h, #0
--.*: 2540001f cmpgt p15\.h, p0/z, z0\.h, #0
--.*: 25400810 cmpgt p0\.h, p2/z, z0\.h, #0
--.*: 25400810 cmpgt p0\.h, p2/z, z0\.h, #0
--.*: 25401c10 cmpgt p0\.h, p7/z, z0\.h, #0
--.*: 25401c10 cmpgt p0\.h, p7/z, z0\.h, #0
--.*: 25400070 cmpgt p0\.h, p0/z, z3\.h, #0
--.*: 25400070 cmpgt p0\.h, p0/z, z3\.h, #0
--.*: 254003f0 cmpgt p0\.h, p0/z, z31\.h, #0
--.*: 254003f0 cmpgt p0\.h, p0/z, z31\.h, #0
--.*: 254f0010 cmpgt p0\.h, p0/z, z0\.h, #15
--.*: 254f0010 cmpgt p0\.h, p0/z, z0\.h, #15
--.*: 25500010 cmpgt p0\.h, p0/z, z0\.h, #-16
--.*: 25500010 cmpgt p0\.h, p0/z, z0\.h, #-16
--.*: 25510010 cmpgt p0\.h, p0/z, z0\.h, #-15
--.*: 25510010 cmpgt p0\.h, p0/z, z0\.h, #-15
--.*: 255f0010 cmpgt p0\.h, p0/z, z0\.h, #-1
--.*: 255f0010 cmpgt p0\.h, p0/z, z0\.h, #-1
--.*: 25800010 cmpgt p0\.s, p0/z, z0\.s, #0
--.*: 25800010 cmpgt p0\.s, p0/z, z0\.s, #0
--.*: 25800011 cmpgt p1\.s, p0/z, z0\.s, #0
--.*: 25800011 cmpgt p1\.s, p0/z, z0\.s, #0
--.*: 2580001f cmpgt p15\.s, p0/z, z0\.s, #0
--.*: 2580001f cmpgt p15\.s, p0/z, z0\.s, #0
--.*: 25800810 cmpgt p0\.s, p2/z, z0\.s, #0
--.*: 25800810 cmpgt p0\.s, p2/z, z0\.s, #0
--.*: 25801c10 cmpgt p0\.s, p7/z, z0\.s, #0
--.*: 25801c10 cmpgt p0\.s, p7/z, z0\.s, #0
--.*: 25800070 cmpgt p0\.s, p0/z, z3\.s, #0
--.*: 25800070 cmpgt p0\.s, p0/z, z3\.s, #0
--.*: 258003f0 cmpgt p0\.s, p0/z, z31\.s, #0
--.*: 258003f0 cmpgt p0\.s, p0/z, z31\.s, #0
--.*: 258f0010 cmpgt p0\.s, p0/z, z0\.s, #15
--.*: 258f0010 cmpgt p0\.s, p0/z, z0\.s, #15
--.*: 25900010 cmpgt p0\.s, p0/z, z0\.s, #-16
--.*: 25900010 cmpgt p0\.s, p0/z, z0\.s, #-16
--.*: 25910010 cmpgt p0\.s, p0/z, z0\.s, #-15
--.*: 25910010 cmpgt p0\.s, p0/z, z0\.s, #-15
--.*: 259f0010 cmpgt p0\.s, p0/z, z0\.s, #-1
--.*: 259f0010 cmpgt p0\.s, p0/z, z0\.s, #-1
--.*: 25c00010 cmpgt p0\.d, p0/z, z0\.d, #0
--.*: 25c00010 cmpgt p0\.d, p0/z, z0\.d, #0
--.*: 25c00011 cmpgt p1\.d, p0/z, z0\.d, #0
--.*: 25c00011 cmpgt p1\.d, p0/z, z0\.d, #0
--.*: 25c0001f cmpgt p15\.d, p0/z, z0\.d, #0
--.*: 25c0001f cmpgt p15\.d, p0/z, z0\.d, #0
--.*: 25c00810 cmpgt p0\.d, p2/z, z0\.d, #0
--.*: 25c00810 cmpgt p0\.d, p2/z, z0\.d, #0
--.*: 25c01c10 cmpgt p0\.d, p7/z, z0\.d, #0
--.*: 25c01c10 cmpgt p0\.d, p7/z, z0\.d, #0
--.*: 25c00070 cmpgt p0\.d, p0/z, z3\.d, #0
--.*: 25c00070 cmpgt p0\.d, p0/z, z3\.d, #0
--.*: 25c003f0 cmpgt p0\.d, p0/z, z31\.d, #0
--.*: 25c003f0 cmpgt p0\.d, p0/z, z31\.d, #0
--.*: 25cf0010 cmpgt p0\.d, p0/z, z0\.d, #15
--.*: 25cf0010 cmpgt p0\.d, p0/z, z0\.d, #15
--.*: 25d00010 cmpgt p0\.d, p0/z, z0\.d, #-16
--.*: 25d00010 cmpgt p0\.d, p0/z, z0\.d, #-16
--.*: 25d10010 cmpgt p0\.d, p0/z, z0\.d, #-15
--.*: 25d10010 cmpgt p0\.d, p0/z, z0\.d, #-15
--.*: 25df0010 cmpgt p0\.d, p0/z, z0\.d, #-1
--.*: 25df0010 cmpgt p0\.d, p0/z, z0\.d, #-1
--.*: 24000010 cmphi p0\.b, p0/z, z0\.b, z0\.b
--.*: 24000010 cmphi p0\.b, p0/z, z0\.b, z0\.b
--.*: 24000011 cmphi p1\.b, p0/z, z0\.b, z0\.b
--.*: 24000011 cmphi p1\.b, p0/z, z0\.b, z0\.b
--.*: 2400001f cmphi p15\.b, p0/z, z0\.b, z0\.b
--.*: 2400001f cmphi p15\.b, p0/z, z0\.b, z0\.b
--.*: 24000810 cmphi p0\.b, p2/z, z0\.b, z0\.b
--.*: 24000810 cmphi p0\.b, p2/z, z0\.b, z0\.b
--.*: 24001c10 cmphi p0\.b, p7/z, z0\.b, z0\.b
--.*: 24001c10 cmphi p0\.b, p7/z, z0\.b, z0\.b
--.*: 24000070 cmphi p0\.b, p0/z, z3\.b, z0\.b
--.*: 24000070 cmphi p0\.b, p0/z, z3\.b, z0\.b
--.*: 240003f0 cmphi p0\.b, p0/z, z31\.b, z0\.b
--.*: 240003f0 cmphi p0\.b, p0/z, z31\.b, z0\.b
--.*: 24040010 cmphi p0\.b, p0/z, z0\.b, z4\.b
--.*: 24040010 cmphi p0\.b, p0/z, z0\.b, z4\.b
--.*: 241f0010 cmphi p0\.b, p0/z, z0\.b, z31\.b
--.*: 241f0010 cmphi p0\.b, p0/z, z0\.b, z31\.b
--.*: 24400010 cmphi p0\.h, p0/z, z0\.h, z0\.h
--.*: 24400010 cmphi p0\.h, p0/z, z0\.h, z0\.h
--.*: 24400011 cmphi p1\.h, p0/z, z0\.h, z0\.h
--.*: 24400011 cmphi p1\.h, p0/z, z0\.h, z0\.h
--.*: 2440001f cmphi p15\.h, p0/z, z0\.h, z0\.h
--.*: 2440001f cmphi p15\.h, p0/z, z0\.h, z0\.h
--.*: 24400810 cmphi p0\.h, p2/z, z0\.h, z0\.h
--.*: 24400810 cmphi p0\.h, p2/z, z0\.h, z0\.h
--.*: 24401c10 cmphi p0\.h, p7/z, z0\.h, z0\.h
--.*: 24401c10 cmphi p0\.h, p7/z, z0\.h, z0\.h
--.*: 24400070 cmphi p0\.h, p0/z, z3\.h, z0\.h
--.*: 24400070 cmphi p0\.h, p0/z, z3\.h, z0\.h
--.*: 244003f0 cmphi p0\.h, p0/z, z31\.h, z0\.h
--.*: 244003f0 cmphi p0\.h, p0/z, z31\.h, z0\.h
--.*: 24440010 cmphi p0\.h, p0/z, z0\.h, z4\.h
--.*: 24440010 cmphi p0\.h, p0/z, z0\.h, z4\.h
--.*: 245f0010 cmphi p0\.h, p0/z, z0\.h, z31\.h
--.*: 245f0010 cmphi p0\.h, p0/z, z0\.h, z31\.h
--.*: 24800010 cmphi p0\.s, p0/z, z0\.s, z0\.s
--.*: 24800010 cmphi p0\.s, p0/z, z0\.s, z0\.s
--.*: 24800011 cmphi p1\.s, p0/z, z0\.s, z0\.s
--.*: 24800011 cmphi p1\.s, p0/z, z0\.s, z0\.s
--.*: 2480001f cmphi p15\.s, p0/z, z0\.s, z0\.s
--.*: 2480001f cmphi p15\.s, p0/z, z0\.s, z0\.s
--.*: 24800810 cmphi p0\.s, p2/z, z0\.s, z0\.s
--.*: 24800810 cmphi p0\.s, p2/z, z0\.s, z0\.s
--.*: 24801c10 cmphi p0\.s, p7/z, z0\.s, z0\.s
--.*: 24801c10 cmphi p0\.s, p7/z, z0\.s, z0\.s
--.*: 24800070 cmphi p0\.s, p0/z, z3\.s, z0\.s
--.*: 24800070 cmphi p0\.s, p0/z, z3\.s, z0\.s
--.*: 248003f0 cmphi p0\.s, p0/z, z31\.s, z0\.s
--.*: 248003f0 cmphi p0\.s, p0/z, z31\.s, z0\.s
--.*: 24840010 cmphi p0\.s, p0/z, z0\.s, z4\.s
--.*: 24840010 cmphi p0\.s, p0/z, z0\.s, z4\.s
--.*: 249f0010 cmphi p0\.s, p0/z, z0\.s, z31\.s
--.*: 249f0010 cmphi p0\.s, p0/z, z0\.s, z31\.s
--.*: 24c00010 cmphi p0\.d, p0/z, z0\.d, z0\.d
--.*: 24c00010 cmphi p0\.d, p0/z, z0\.d, z0\.d
--.*: 24c00011 cmphi p1\.d, p0/z, z0\.d, z0\.d
--.*: 24c00011 cmphi p1\.d, p0/z, z0\.d, z0\.d
--.*: 24c0001f cmphi p15\.d, p0/z, z0\.d, z0\.d
--.*: 24c0001f cmphi p15\.d, p0/z, z0\.d, z0\.d
--.*: 24c00810 cmphi p0\.d, p2/z, z0\.d, z0\.d
--.*: 24c00810 cmphi p0\.d, p2/z, z0\.d, z0\.d
--.*: 24c01c10 cmphi p0\.d, p7/z, z0\.d, z0\.d
--.*: 24c01c10 cmphi p0\.d, p7/z, z0\.d, z0\.d
--.*: 24c00070 cmphi p0\.d, p0/z, z3\.d, z0\.d
--.*: 24c00070 cmphi p0\.d, p0/z, z3\.d, z0\.d
--.*: 24c003f0 cmphi p0\.d, p0/z, z31\.d, z0\.d
--.*: 24c003f0 cmphi p0\.d, p0/z, z31\.d, z0\.d
--.*: 24c40010 cmphi p0\.d, p0/z, z0\.d, z4\.d
--.*: 24c40010 cmphi p0\.d, p0/z, z0\.d, z4\.d
--.*: 24df0010 cmphi p0\.d, p0/z, z0\.d, z31\.d
--.*: 24df0010 cmphi p0\.d, p0/z, z0\.d, z31\.d
--.*: 2400c010 cmphi p0\.b, p0/z, z0\.b, z0\.d
--.*: 2400c010 cmphi p0\.b, p0/z, z0\.b, z0\.d
--.*: 2400c011 cmphi p1\.b, p0/z, z0\.b, z0\.d
--.*: 2400c011 cmphi p1\.b, p0/z, z0\.b, z0\.d
--.*: 2400c01f cmphi p15\.b, p0/z, z0\.b, z0\.d
--.*: 2400c01f cmphi p15\.b, p0/z, z0\.b, z0\.d
--.*: 2400c810 cmphi p0\.b, p2/z, z0\.b, z0\.d
--.*: 2400c810 cmphi p0\.b, p2/z, z0\.b, z0\.d
--.*: 2400dc10 cmphi p0\.b, p7/z, z0\.b, z0\.d
--.*: 2400dc10 cmphi p0\.b, p7/z, z0\.b, z0\.d
--.*: 2400c070 cmphi p0\.b, p0/z, z3\.b, z0\.d
--.*: 2400c070 cmphi p0\.b, p0/z, z3\.b, z0\.d
--.*: 2400c3f0 cmphi p0\.b, p0/z, z31\.b, z0\.d
--.*: 2400c3f0 cmphi p0\.b, p0/z, z31\.b, z0\.d
--.*: 2404c010 cmphi p0\.b, p0/z, z0\.b, z4\.d
--.*: 2404c010 cmphi p0\.b, p0/z, z0\.b, z4\.d
--.*: 241fc010 cmphi p0\.b, p0/z, z0\.b, z31\.d
--.*: 241fc010 cmphi p0\.b, p0/z, z0\.b, z31\.d
--.*: 2440c010 cmphi p0\.h, p0/z, z0\.h, z0\.d
--.*: 2440c010 cmphi p0\.h, p0/z, z0\.h, z0\.d
--.*: 2440c011 cmphi p1\.h, p0/z, z0\.h, z0\.d
--.*: 2440c011 cmphi p1\.h, p0/z, z0\.h, z0\.d
--.*: 2440c01f cmphi p15\.h, p0/z, z0\.h, z0\.d
--.*: 2440c01f cmphi p15\.h, p0/z, z0\.h, z0\.d
--.*: 2440c810 cmphi p0\.h, p2/z, z0\.h, z0\.d
--.*: 2440c810 cmphi p0\.h, p2/z, z0\.h, z0\.d
--.*: 2440dc10 cmphi p0\.h, p7/z, z0\.h, z0\.d
--.*: 2440dc10 cmphi p0\.h, p7/z, z0\.h, z0\.d
--.*: 2440c070 cmphi p0\.h, p0/z, z3\.h, z0\.d
--.*: 2440c070 cmphi p0\.h, p0/z, z3\.h, z0\.d
--.*: 2440c3f0 cmphi p0\.h, p0/z, z31\.h, z0\.d
--.*: 2440c3f0 cmphi p0\.h, p0/z, z31\.h, z0\.d
--.*: 2444c010 cmphi p0\.h, p0/z, z0\.h, z4\.d
--.*: 2444c010 cmphi p0\.h, p0/z, z0\.h, z4\.d
--.*: 245fc010 cmphi p0\.h, p0/z, z0\.h, z31\.d
--.*: 245fc010 cmphi p0\.h, p0/z, z0\.h, z31\.d
--.*: 2480c010 cmphi p0\.s, p0/z, z0\.s, z0\.d
--.*: 2480c010 cmphi p0\.s, p0/z, z0\.s, z0\.d
--.*: 2480c011 cmphi p1\.s, p0/z, z0\.s, z0\.d
--.*: 2480c011 cmphi p1\.s, p0/z, z0\.s, z0\.d
--.*: 2480c01f cmphi p15\.s, p0/z, z0\.s, z0\.d
--.*: 2480c01f cmphi p15\.s, p0/z, z0\.s, z0\.d
--.*: 2480c810 cmphi p0\.s, p2/z, z0\.s, z0\.d
--.*: 2480c810 cmphi p0\.s, p2/z, z0\.s, z0\.d
--.*: 2480dc10 cmphi p0\.s, p7/z, z0\.s, z0\.d
--.*: 2480dc10 cmphi p0\.s, p7/z, z0\.s, z0\.d
--.*: 2480c070 cmphi p0\.s, p0/z, z3\.s, z0\.d
--.*: 2480c070 cmphi p0\.s, p0/z, z3\.s, z0\.d
--.*: 2480c3f0 cmphi p0\.s, p0/z, z31\.s, z0\.d
--.*: 2480c3f0 cmphi p0\.s, p0/z, z31\.s, z0\.d
--.*: 2484c010 cmphi p0\.s, p0/z, z0\.s, z4\.d
--.*: 2484c010 cmphi p0\.s, p0/z, z0\.s, z4\.d
--.*: 249fc010 cmphi p0\.s, p0/z, z0\.s, z31\.d
--.*: 249fc010 cmphi p0\.s, p0/z, z0\.s, z31\.d
--.*: 24200010 cmphi p0\.b, p0/z, z0\.b, #0
--.*: 24200010 cmphi p0\.b, p0/z, z0\.b, #0
--.*: 24200011 cmphi p1\.b, p0/z, z0\.b, #0
--.*: 24200011 cmphi p1\.b, p0/z, z0\.b, #0
--.*: 2420001f cmphi p15\.b, p0/z, z0\.b, #0
--.*: 2420001f cmphi p15\.b, p0/z, z0\.b, #0
--.*: 24200810 cmphi p0\.b, p2/z, z0\.b, #0
--.*: 24200810 cmphi p0\.b, p2/z, z0\.b, #0
--.*: 24201c10 cmphi p0\.b, p7/z, z0\.b, #0
--.*: 24201c10 cmphi p0\.b, p7/z, z0\.b, #0
--.*: 24200070 cmphi p0\.b, p0/z, z3\.b, #0
--.*: 24200070 cmphi p0\.b, p0/z, z3\.b, #0
--.*: 242003f0 cmphi p0\.b, p0/z, z31\.b, #0
--.*: 242003f0 cmphi p0\.b, p0/z, z31\.b, #0
--.*: 242fc010 cmphi p0\.b, p0/z, z0\.b, #63
--.*: 242fc010 cmphi p0\.b, p0/z, z0\.b, #63
--.*: 24300010 cmphi p0\.b, p0/z, z0\.b, #64
--.*: 24300010 cmphi p0\.b, p0/z, z0\.b, #64
--.*: 24304010 cmphi p0\.b, p0/z, z0\.b, #65
--.*: 24304010 cmphi p0\.b, p0/z, z0\.b, #65
--.*: 243fc010 cmphi p0\.b, p0/z, z0\.b, #127
--.*: 243fc010 cmphi p0\.b, p0/z, z0\.b, #127
--.*: 24600010 cmphi p0\.h, p0/z, z0\.h, #0
--.*: 24600010 cmphi p0\.h, p0/z, z0\.h, #0
--.*: 24600011 cmphi p1\.h, p0/z, z0\.h, #0
--.*: 24600011 cmphi p1\.h, p0/z, z0\.h, #0
--.*: 2460001f cmphi p15\.h, p0/z, z0\.h, #0
--.*: 2460001f cmphi p15\.h, p0/z, z0\.h, #0
--.*: 24600810 cmphi p0\.h, p2/z, z0\.h, #0
--.*: 24600810 cmphi p0\.h, p2/z, z0\.h, #0
--.*: 24601c10 cmphi p0\.h, p7/z, z0\.h, #0
--.*: 24601c10 cmphi p0\.h, p7/z, z0\.h, #0
--.*: 24600070 cmphi p0\.h, p0/z, z3\.h, #0
--.*: 24600070 cmphi p0\.h, p0/z, z3\.h, #0
--.*: 246003f0 cmphi p0\.h, p0/z, z31\.h, #0
--.*: 246003f0 cmphi p0\.h, p0/z, z31\.h, #0
--.*: 246fc010 cmphi p0\.h, p0/z, z0\.h, #63
--.*: 246fc010 cmphi p0\.h, p0/z, z0\.h, #63
--.*: 24700010 cmphi p0\.h, p0/z, z0\.h, #64
--.*: 24700010 cmphi p0\.h, p0/z, z0\.h, #64
--.*: 24704010 cmphi p0\.h, p0/z, z0\.h, #65
--.*: 24704010 cmphi p0\.h, p0/z, z0\.h, #65
--.*: 247fc010 cmphi p0\.h, p0/z, z0\.h, #127
--.*: 247fc010 cmphi p0\.h, p0/z, z0\.h, #127
--.*: 24a00010 cmphi p0\.s, p0/z, z0\.s, #0
--.*: 24a00010 cmphi p0\.s, p0/z, z0\.s, #0
--.*: 24a00011 cmphi p1\.s, p0/z, z0\.s, #0
--.*: 24a00011 cmphi p1\.s, p0/z, z0\.s, #0
--.*: 24a0001f cmphi p15\.s, p0/z, z0\.s, #0
--.*: 24a0001f cmphi p15\.s, p0/z, z0\.s, #0
--.*: 24a00810 cmphi p0\.s, p2/z, z0\.s, #0
--.*: 24a00810 cmphi p0\.s, p2/z, z0\.s, #0
--.*: 24a01c10 cmphi p0\.s, p7/z, z0\.s, #0
--.*: 24a01c10 cmphi p0\.s, p7/z, z0\.s, #0
--.*: 24a00070 cmphi p0\.s, p0/z, z3\.s, #0
--.*: 24a00070 cmphi p0\.s, p0/z, z3\.s, #0
--.*: 24a003f0 cmphi p0\.s, p0/z, z31\.s, #0
--.*: 24a003f0 cmphi p0\.s, p0/z, z31\.s, #0
--.*: 24afc010 cmphi p0\.s, p0/z, z0\.s, #63
--.*: 24afc010 cmphi p0\.s, p0/z, z0\.s, #63
--.*: 24b00010 cmphi p0\.s, p0/z, z0\.s, #64
--.*: 24b00010 cmphi p0\.s, p0/z, z0\.s, #64
--.*: 24b04010 cmphi p0\.s, p0/z, z0\.s, #65
--.*: 24b04010 cmphi p0\.s, p0/z, z0\.s, #65
--.*: 24bfc010 cmphi p0\.s, p0/z, z0\.s, #127
--.*: 24bfc010 cmphi p0\.s, p0/z, z0\.s, #127
--.*: 24e00010 cmphi p0\.d, p0/z, z0\.d, #0
--.*: 24e00010 cmphi p0\.d, p0/z, z0\.d, #0
--.*: 24e00011 cmphi p1\.d, p0/z, z0\.d, #0
--.*: 24e00011 cmphi p1\.d, p0/z, z0\.d, #0
--.*: 24e0001f cmphi p15\.d, p0/z, z0\.d, #0
--.*: 24e0001f cmphi p15\.d, p0/z, z0\.d, #0
--.*: 24e00810 cmphi p0\.d, p2/z, z0\.d, #0
--.*: 24e00810 cmphi p0\.d, p2/z, z0\.d, #0
--.*: 24e01c10 cmphi p0\.d, p7/z, z0\.d, #0
--.*: 24e01c10 cmphi p0\.d, p7/z, z0\.d, #0
--.*: 24e00070 cmphi p0\.d, p0/z, z3\.d, #0
--.*: 24e00070 cmphi p0\.d, p0/z, z3\.d, #0
--.*: 24e003f0 cmphi p0\.d, p0/z, z31\.d, #0
--.*: 24e003f0 cmphi p0\.d, p0/z, z31\.d, #0
--.*: 24efc010 cmphi p0\.d, p0/z, z0\.d, #63
--.*: 24efc010 cmphi p0\.d, p0/z, z0\.d, #63
--.*: 24f00010 cmphi p0\.d, p0/z, z0\.d, #64
--.*: 24f00010 cmphi p0\.d, p0/z, z0\.d, #64
--.*: 24f04010 cmphi p0\.d, p0/z, z0\.d, #65
--.*: 24f04010 cmphi p0\.d, p0/z, z0\.d, #65
--.*: 24ffc010 cmphi p0\.d, p0/z, z0\.d, #127
--.*: 24ffc010 cmphi p0\.d, p0/z, z0\.d, #127
--.*: 24000000 cmphs p0\.b, p0/z, z0\.b, z0\.b
--.*: 24000000 cmphs p0\.b, p0/z, z0\.b, z0\.b
--.*: 24000001 cmphs p1\.b, p0/z, z0\.b, z0\.b
--.*: 24000001 cmphs p1\.b, p0/z, z0\.b, z0\.b
--.*: 2400000f cmphs p15\.b, p0/z, z0\.b, z0\.b
--.*: 2400000f cmphs p15\.b, p0/z, z0\.b, z0\.b
--.*: 24000800 cmphs p0\.b, p2/z, z0\.b, z0\.b
--.*: 24000800 cmphs p0\.b, p2/z, z0\.b, z0\.b
--.*: 24001c00 cmphs p0\.b, p7/z, z0\.b, z0\.b
--.*: 24001c00 cmphs p0\.b, p7/z, z0\.b, z0\.b
--.*: 24000060 cmphs p0\.b, p0/z, z3\.b, z0\.b
--.*: 24000060 cmphs p0\.b, p0/z, z3\.b, z0\.b
--.*: 240003e0 cmphs p0\.b, p0/z, z31\.b, z0\.b
--.*: 240003e0 cmphs p0\.b, p0/z, z31\.b, z0\.b
--.*: 24040000 cmphs p0\.b, p0/z, z0\.b, z4\.b
--.*: 24040000 cmphs p0\.b, p0/z, z0\.b, z4\.b
--.*: 241f0000 cmphs p0\.b, p0/z, z0\.b, z31\.b
--.*: 241f0000 cmphs p0\.b, p0/z, z0\.b, z31\.b
--.*: 24400000 cmphs p0\.h, p0/z, z0\.h, z0\.h
--.*: 24400000 cmphs p0\.h, p0/z, z0\.h, z0\.h
--.*: 24400001 cmphs p1\.h, p0/z, z0\.h, z0\.h
--.*: 24400001 cmphs p1\.h, p0/z, z0\.h, z0\.h
--.*: 2440000f cmphs p15\.h, p0/z, z0\.h, z0\.h
--.*: 2440000f cmphs p15\.h, p0/z, z0\.h, z0\.h
--.*: 24400800 cmphs p0\.h, p2/z, z0\.h, z0\.h
--.*: 24400800 cmphs p0\.h, p2/z, z0\.h, z0\.h
--.*: 24401c00 cmphs p0\.h, p7/z, z0\.h, z0\.h
--.*: 24401c00 cmphs p0\.h, p7/z, z0\.h, z0\.h
--.*: 24400060 cmphs p0\.h, p0/z, z3\.h, z0\.h
--.*: 24400060 cmphs p0\.h, p0/z, z3\.h, z0\.h
--.*: 244003e0 cmphs p0\.h, p0/z, z31\.h, z0\.h
--.*: 244003e0 cmphs p0\.h, p0/z, z31\.h, z0\.h
--.*: 24440000 cmphs p0\.h, p0/z, z0\.h, z4\.h
--.*: 24440000 cmphs p0\.h, p0/z, z0\.h, z4\.h
--.*: 245f0000 cmphs p0\.h, p0/z, z0\.h, z31\.h
--.*: 245f0000 cmphs p0\.h, p0/z, z0\.h, z31\.h
--.*: 24800000 cmphs p0\.s, p0/z, z0\.s, z0\.s
--.*: 24800000 cmphs p0\.s, p0/z, z0\.s, z0\.s
--.*: 24800001 cmphs p1\.s, p0/z, z0\.s, z0\.s
--.*: 24800001 cmphs p1\.s, p0/z, z0\.s, z0\.s
--.*: 2480000f cmphs p15\.s, p0/z, z0\.s, z0\.s
--.*: 2480000f cmphs p15\.s, p0/z, z0\.s, z0\.s
--.*: 24800800 cmphs p0\.s, p2/z, z0\.s, z0\.s
--.*: 24800800 cmphs p0\.s, p2/z, z0\.s, z0\.s
--.*: 24801c00 cmphs p0\.s, p7/z, z0\.s, z0\.s
--.*: 24801c00 cmphs p0\.s, p7/z, z0\.s, z0\.s
--.*: 24800060 cmphs p0\.s, p0/z, z3\.s, z0\.s
--.*: 24800060 cmphs p0\.s, p0/z, z3\.s, z0\.s
--.*: 248003e0 cmphs p0\.s, p0/z, z31\.s, z0\.s
--.*: 248003e0 cmphs p0\.s, p0/z, z31\.s, z0\.s
--.*: 24840000 cmphs p0\.s, p0/z, z0\.s, z4\.s
--.*: 24840000 cmphs p0\.s, p0/z, z0\.s, z4\.s
--.*: 249f0000 cmphs p0\.s, p0/z, z0\.s, z31\.s
--.*: 249f0000 cmphs p0\.s, p0/z, z0\.s, z31\.s
--.*: 24c00000 cmphs p0\.d, p0/z, z0\.d, z0\.d
--.*: 24c00000 cmphs p0\.d, p0/z, z0\.d, z0\.d
--.*: 24c00001 cmphs p1\.d, p0/z, z0\.d, z0\.d
--.*: 24c00001 cmphs p1\.d, p0/z, z0\.d, z0\.d
--.*: 24c0000f cmphs p15\.d, p0/z, z0\.d, z0\.d
--.*: 24c0000f cmphs p15\.d, p0/z, z0\.d, z0\.d
--.*: 24c00800 cmphs p0\.d, p2/z, z0\.d, z0\.d
--.*: 24c00800 cmphs p0\.d, p2/z, z0\.d, z0\.d
--.*: 24c01c00 cmphs p0\.d, p7/z, z0\.d, z0\.d
--.*: 24c01c00 cmphs p0\.d, p7/z, z0\.d, z0\.d
--.*: 24c00060 cmphs p0\.d, p0/z, z3\.d, z0\.d
--.*: 24c00060 cmphs p0\.d, p0/z, z3\.d, z0\.d
--.*: 24c003e0 cmphs p0\.d, p0/z, z31\.d, z0\.d
--.*: 24c003e0 cmphs p0\.d, p0/z, z31\.d, z0\.d
--.*: 24c40000 cmphs p0\.d, p0/z, z0\.d, z4\.d
--.*: 24c40000 cmphs p0\.d, p0/z, z0\.d, z4\.d
--.*: 24df0000 cmphs p0\.d, p0/z, z0\.d, z31\.d
--.*: 24df0000 cmphs p0\.d, p0/z, z0\.d, z31\.d
--.*: 2400c000 cmphs p0\.b, p0/z, z0\.b, z0\.d
--.*: 2400c000 cmphs p0\.b, p0/z, z0\.b, z0\.d
--.*: 2400c001 cmphs p1\.b, p0/z, z0\.b, z0\.d
--.*: 2400c001 cmphs p1\.b, p0/z, z0\.b, z0\.d
--.*: 2400c00f cmphs p15\.b, p0/z, z0\.b, z0\.d
--.*: 2400c00f cmphs p15\.b, p0/z, z0\.b, z0\.d
--.*: 2400c800 cmphs p0\.b, p2/z, z0\.b, z0\.d
--.*: 2400c800 cmphs p0\.b, p2/z, z0\.b, z0\.d
--.*: 2400dc00 cmphs p0\.b, p7/z, z0\.b, z0\.d
--.*: 2400dc00 cmphs p0\.b, p7/z, z0\.b, z0\.d
--.*: 2400c060 cmphs p0\.b, p0/z, z3\.b, z0\.d
--.*: 2400c060 cmphs p0\.b, p0/z, z3\.b, z0\.d
--.*: 2400c3e0 cmphs p0\.b, p0/z, z31\.b, z0\.d
--.*: 2400c3e0 cmphs p0\.b, p0/z, z31\.b, z0\.d
--.*: 2404c000 cmphs p0\.b, p0/z, z0\.b, z4\.d
--.*: 2404c000 cmphs p0\.b, p0/z, z0\.b, z4\.d
--.*: 241fc000 cmphs p0\.b, p0/z, z0\.b, z31\.d
--.*: 241fc000 cmphs p0\.b, p0/z, z0\.b, z31\.d
--.*: 2440c000 cmphs p0\.h, p0/z, z0\.h, z0\.d
--.*: 2440c000 cmphs p0\.h, p0/z, z0\.h, z0\.d
--.*: 2440c001 cmphs p1\.h, p0/z, z0\.h, z0\.d
--.*: 2440c001 cmphs p1\.h, p0/z, z0\.h, z0\.d
--.*: 2440c00f cmphs p15\.h, p0/z, z0\.h, z0\.d
--.*: 2440c00f cmphs p15\.h, p0/z, z0\.h, z0\.d
--.*: 2440c800 cmphs p0\.h, p2/z, z0\.h, z0\.d
--.*: 2440c800 cmphs p0\.h, p2/z, z0\.h, z0\.d
--.*: 2440dc00 cmphs p0\.h, p7/z, z0\.h, z0\.d
--.*: 2440dc00 cmphs p0\.h, p7/z, z0\.h, z0\.d
--.*: 2440c060 cmphs p0\.h, p0/z, z3\.h, z0\.d
--.*: 2440c060 cmphs p0\.h, p0/z, z3\.h, z0\.d
--.*: 2440c3e0 cmphs p0\.h, p0/z, z31\.h, z0\.d
--.*: 2440c3e0 cmphs p0\.h, p0/z, z31\.h, z0\.d
--.*: 2444c000 cmphs p0\.h, p0/z, z0\.h, z4\.d
--.*: 2444c000 cmphs p0\.h, p0/z, z0\.h, z4\.d
--.*: 245fc000 cmphs p0\.h, p0/z, z0\.h, z31\.d
--.*: 245fc000 cmphs p0\.h, p0/z, z0\.h, z31\.d
--.*: 2480c000 cmphs p0\.s, p0/z, z0\.s, z0\.d
--.*: 2480c000 cmphs p0\.s, p0/z, z0\.s, z0\.d
--.*: 2480c001 cmphs p1\.s, p0/z, z0\.s, z0\.d
--.*: 2480c001 cmphs p1\.s, p0/z, z0\.s, z0\.d
--.*: 2480c00f cmphs p15\.s, p0/z, z0\.s, z0\.d
--.*: 2480c00f cmphs p15\.s, p0/z, z0\.s, z0\.d
--.*: 2480c800 cmphs p0\.s, p2/z, z0\.s, z0\.d
--.*: 2480c800 cmphs p0\.s, p2/z, z0\.s, z0\.d
--.*: 2480dc00 cmphs p0\.s, p7/z, z0\.s, z0\.d
--.*: 2480dc00 cmphs p0\.s, p7/z, z0\.s, z0\.d
--.*: 2480c060 cmphs p0\.s, p0/z, z3\.s, z0\.d
--.*: 2480c060 cmphs p0\.s, p0/z, z3\.s, z0\.d
--.*: 2480c3e0 cmphs p0\.s, p0/z, z31\.s, z0\.d
--.*: 2480c3e0 cmphs p0\.s, p0/z, z31\.s, z0\.d
--.*: 2484c000 cmphs p0\.s, p0/z, z0\.s, z4\.d
--.*: 2484c000 cmphs p0\.s, p0/z, z0\.s, z4\.d
--.*: 249fc000 cmphs p0\.s, p0/z, z0\.s, z31\.d
--.*: 249fc000 cmphs p0\.s, p0/z, z0\.s, z31\.d
--.*: 24200000 cmphs p0\.b, p0/z, z0\.b, #0
--.*: 24200000 cmphs p0\.b, p0/z, z0\.b, #0
--.*: 24200001 cmphs p1\.b, p0/z, z0\.b, #0
--.*: 24200001 cmphs p1\.b, p0/z, z0\.b, #0
--.*: 2420000f cmphs p15\.b, p0/z, z0\.b, #0
--.*: 2420000f cmphs p15\.b, p0/z, z0\.b, #0
--.*: 24200800 cmphs p0\.b, p2/z, z0\.b, #0
--.*: 24200800 cmphs p0\.b, p2/z, z0\.b, #0
--.*: 24201c00 cmphs p0\.b, p7/z, z0\.b, #0
--.*: 24201c00 cmphs p0\.b, p7/z, z0\.b, #0
--.*: 24200060 cmphs p0\.b, p0/z, z3\.b, #0
--.*: 24200060 cmphs p0\.b, p0/z, z3\.b, #0
--.*: 242003e0 cmphs p0\.b, p0/z, z31\.b, #0
--.*: 242003e0 cmphs p0\.b, p0/z, z31\.b, #0
--.*: 242fc000 cmphs p0\.b, p0/z, z0\.b, #63
--.*: 242fc000 cmphs p0\.b, p0/z, z0\.b, #63
--.*: 24300000 cmphs p0\.b, p0/z, z0\.b, #64
--.*: 24300000 cmphs p0\.b, p0/z, z0\.b, #64
--.*: 24304000 cmphs p0\.b, p0/z, z0\.b, #65
--.*: 24304000 cmphs p0\.b, p0/z, z0\.b, #65
--.*: 243fc000 cmphs p0\.b, p0/z, z0\.b, #127
--.*: 243fc000 cmphs p0\.b, p0/z, z0\.b, #127
--.*: 24600000 cmphs p0\.h, p0/z, z0\.h, #0
--.*: 24600000 cmphs p0\.h, p0/z, z0\.h, #0
--.*: 24600001 cmphs p1\.h, p0/z, z0\.h, #0
--.*: 24600001 cmphs p1\.h, p0/z, z0\.h, #0
--.*: 2460000f cmphs p15\.h, p0/z, z0\.h, #0
--.*: 2460000f cmphs p15\.h, p0/z, z0\.h, #0
--.*: 24600800 cmphs p0\.h, p2/z, z0\.h, #0
--.*: 24600800 cmphs p0\.h, p2/z, z0\.h, #0
--.*: 24601c00 cmphs p0\.h, p7/z, z0\.h, #0
--.*: 24601c00 cmphs p0\.h, p7/z, z0\.h, #0
--.*: 24600060 cmphs p0\.h, p0/z, z3\.h, #0
--.*: 24600060 cmphs p0\.h, p0/z, z3\.h, #0
--.*: 246003e0 cmphs p0\.h, p0/z, z31\.h, #0
--.*: 246003e0 cmphs p0\.h, p0/z, z31\.h, #0
--.*: 246fc000 cmphs p0\.h, p0/z, z0\.h, #63
--.*: 246fc000 cmphs p0\.h, p0/z, z0\.h, #63
--.*: 24700000 cmphs p0\.h, p0/z, z0\.h, #64
--.*: 24700000 cmphs p0\.h, p0/z, z0\.h, #64
--.*: 24704000 cmphs p0\.h, p0/z, z0\.h, #65
--.*: 24704000 cmphs p0\.h, p0/z, z0\.h, #65
--.*: 247fc000 cmphs p0\.h, p0/z, z0\.h, #127
--.*: 247fc000 cmphs p0\.h, p0/z, z0\.h, #127
--.*: 24a00000 cmphs p0\.s, p0/z, z0\.s, #0
--.*: 24a00000 cmphs p0\.s, p0/z, z0\.s, #0
--.*: 24a00001 cmphs p1\.s, p0/z, z0\.s, #0
--.*: 24a00001 cmphs p1\.s, p0/z, z0\.s, #0
--.*: 24a0000f cmphs p15\.s, p0/z, z0\.s, #0
--.*: 24a0000f cmphs p15\.s, p0/z, z0\.s, #0
--.*: 24a00800 cmphs p0\.s, p2/z, z0\.s, #0
--.*: 24a00800 cmphs p0\.s, p2/z, z0\.s, #0
--.*: 24a01c00 cmphs p0\.s, p7/z, z0\.s, #0
--.*: 24a01c00 cmphs p0\.s, p7/z, z0\.s, #0
--.*: 24a00060 cmphs p0\.s, p0/z, z3\.s, #0
--.*: 24a00060 cmphs p0\.s, p0/z, z3\.s, #0
--.*: 24a003e0 cmphs p0\.s, p0/z, z31\.s, #0
--.*: 24a003e0 cmphs p0\.s, p0/z, z31\.s, #0
--.*: 24afc000 cmphs p0\.s, p0/z, z0\.s, #63
--.*: 24afc000 cmphs p0\.s, p0/z, z0\.s, #63
--.*: 24b00000 cmphs p0\.s, p0/z, z0\.s, #64
--.*: 24b00000 cmphs p0\.s, p0/z, z0\.s, #64
--.*: 24b04000 cmphs p0\.s, p0/z, z0\.s, #65
--.*: 24b04000 cmphs p0\.s, p0/z, z0\.s, #65
--.*: 24bfc000 cmphs p0\.s, p0/z, z0\.s, #127
--.*: 24bfc000 cmphs p0\.s, p0/z, z0\.s, #127
--.*: 24e00000 cmphs p0\.d, p0/z, z0\.d, #0
--.*: 24e00000 cmphs p0\.d, p0/z, z0\.d, #0
--.*: 24e00001 cmphs p1\.d, p0/z, z0\.d, #0
--.*: 24e00001 cmphs p1\.d, p0/z, z0\.d, #0
--.*: 24e0000f cmphs p15\.d, p0/z, z0\.d, #0
--.*: 24e0000f cmphs p15\.d, p0/z, z0\.d, #0
--.*: 24e00800 cmphs p0\.d, p2/z, z0\.d, #0
--.*: 24e00800 cmphs p0\.d, p2/z, z0\.d, #0
--.*: 24e01c00 cmphs p0\.d, p7/z, z0\.d, #0
--.*: 24e01c00 cmphs p0\.d, p7/z, z0\.d, #0
--.*: 24e00060 cmphs p0\.d, p0/z, z3\.d, #0
--.*: 24e00060 cmphs p0\.d, p0/z, z3\.d, #0
--.*: 24e003e0 cmphs p0\.d, p0/z, z31\.d, #0
--.*: 24e003e0 cmphs p0\.d, p0/z, z31\.d, #0
--.*: 24efc000 cmphs p0\.d, p0/z, z0\.d, #63
--.*: 24efc000 cmphs p0\.d, p0/z, z0\.d, #63
--.*: 24f00000 cmphs p0\.d, p0/z, z0\.d, #64
--.*: 24f00000 cmphs p0\.d, p0/z, z0\.d, #64
--.*: 24f04000 cmphs p0\.d, p0/z, z0\.d, #65
--.*: 24f04000 cmphs p0\.d, p0/z, z0\.d, #65
--.*: 24ffc000 cmphs p0\.d, p0/z, z0\.d, #127
--.*: 24ffc000 cmphs p0\.d, p0/z, z0\.d, #127
--.*: 24006010 cmple p0\.b, p0/z, z0\.b, z0\.d
--.*: 24006010 cmple p0\.b, p0/z, z0\.b, z0\.d
--.*: 24006011 cmple p1\.b, p0/z, z0\.b, z0\.d
--.*: 24006011 cmple p1\.b, p0/z, z0\.b, z0\.d
--.*: 2400601f cmple p15\.b, p0/z, z0\.b, z0\.d
--.*: 2400601f cmple p15\.b, p0/z, z0\.b, z0\.d
--.*: 24006810 cmple p0\.b, p2/z, z0\.b, z0\.d
--.*: 24006810 cmple p0\.b, p2/z, z0\.b, z0\.d
--.*: 24007c10 cmple p0\.b, p7/z, z0\.b, z0\.d
--.*: 24007c10 cmple p0\.b, p7/z, z0\.b, z0\.d
--.*: 24006070 cmple p0\.b, p0/z, z3\.b, z0\.d
--.*: 24006070 cmple p0\.b, p0/z, z3\.b, z0\.d
--.*: 240063f0 cmple p0\.b, p0/z, z31\.b, z0\.d
--.*: 240063f0 cmple p0\.b, p0/z, z31\.b, z0\.d
--.*: 24046010 cmple p0\.b, p0/z, z0\.b, z4\.d
--.*: 24046010 cmple p0\.b, p0/z, z0\.b, z4\.d
--.*: 241f6010 cmple p0\.b, p0/z, z0\.b, z31\.d
--.*: 241f6010 cmple p0\.b, p0/z, z0\.b, z31\.d
--.*: 24406010 cmple p0\.h, p0/z, z0\.h, z0\.d
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--.*: 2404e010 cmpls p0\.b, p0/z, z0\.b, z4\.d
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--.*: 241fe010 cmpls p0\.b, p0/z, z0\.b, z31\.d
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--.*: 249fe010 cmpls p0\.s, p0/z, z0\.s, z31\.d
--.*: 24202010 cmpls p0\.b, p0/z, z0\.b, #0
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--.*: 242fe010 cmpls p0\.b, p0/z, z0\.b, #63
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--.*: 24302010 cmpls p0\.b, p0/z, z0\.b, #64
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--.*: 24306010 cmpls p0\.b, p0/z, z0\.b, #65
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--.*: 243fe010 cmpls p0\.b, p0/z, z0\.b, #127
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--.*: 246fe010 cmpls p0\.h, p0/z, z0\.h, #63
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--.*: 24706010 cmpls p0\.h, p0/z, z0\.h, #65
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--.*: 24afe010 cmpls p0\.s, p0/z, z0\.s, #63
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--.*: 24046000 cmplt p0\.b, p0/z, z0\.b, z4\.d
--.*: 241f6000 cmplt p0\.b, p0/z, z0\.b, z31\.d
--.*: 241f6000 cmplt p0\.b, p0/z, z0\.b, z31\.d
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--.*: 2440600f cmplt p15\.h, p0/z, z0\.h, z0\.d
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--.*: 244063e0 cmplt p0\.h, p0/z, z31\.h, z0\.d
--.*: 244063e0 cmplt p0\.h, p0/z, z31\.h, z0\.d
--.*: 24446000 cmplt p0\.h, p0/z, z0\.h, z4\.d
--.*: 24446000 cmplt p0\.h, p0/z, z0\.h, z4\.d
--.*: 245f6000 cmplt p0\.h, p0/z, z0\.h, z31\.d
--.*: 245f6000 cmplt p0\.h, p0/z, z0\.h, z31\.d
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--.*: 2480600f cmplt p15\.s, p0/z, z0\.s, z0\.d
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--.*: 24806800 cmplt p0\.s, p2/z, z0\.s, z0\.d
--.*: 24807c00 cmplt p0\.s, p7/z, z0\.s, z0\.d
--.*: 24807c00 cmplt p0\.s, p7/z, z0\.s, z0\.d
--.*: 24806060 cmplt p0\.s, p0/z, z3\.s, z0\.d
--.*: 24806060 cmplt p0\.s, p0/z, z3\.s, z0\.d
--.*: 248063e0 cmplt p0\.s, p0/z, z31\.s, z0\.d
--.*: 248063e0 cmplt p0\.s, p0/z, z31\.s, z0\.d
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--.*: 24846000 cmplt p0\.s, p0/z, z0\.s, z4\.d
--.*: 249f6000 cmplt p0\.s, p0/z, z0\.s, z31\.d
--.*: 249f6000 cmplt p0\.s, p0/z, z0\.s, z31\.d
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--.*: 25002060 cmplt p0\.b, p0/z, z3\.b, #0
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--.*: 2540200f cmplt p15\.h, p0/z, z0\.h, #0
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--.*: 25402800 cmplt p0\.h, p2/z, z0\.h, #0
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--.*: 25403c00 cmplt p0\.h, p7/z, z0\.h, #0
--.*: 25402060 cmplt p0\.h, p0/z, z3\.h, #0
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--.*: 254023e0 cmplt p0\.h, p0/z, z31\.h, #0
--.*: 254023e0 cmplt p0\.h, p0/z, z31\.h, #0
--.*: 254f2000 cmplt p0\.h, p0/z, z0\.h, #15
--.*: 254f2000 cmplt p0\.h, p0/z, z0\.h, #15
--.*: 25502000 cmplt p0\.h, p0/z, z0\.h, #-16
--.*: 25502000 cmplt p0\.h, p0/z, z0\.h, #-16
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--.*: 25512000 cmplt p0\.h, p0/z, z0\.h, #-15
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--.*: 255f2000 cmplt p0\.h, p0/z, z0\.h, #-1
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--.*: 25802001 cmplt p1\.s, p0/z, z0\.s, #0
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--.*: 2580200f cmplt p15\.s, p0/z, z0\.s, #0
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--.*: 25802800 cmplt p0\.s, p2/z, z0\.s, #0
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--.*: 258023e0 cmplt p0\.s, p0/z, z31\.s, #0
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--.*: 258f2000 cmplt p0\.s, p0/z, z0\.s, #15
--.*: 25902000 cmplt p0\.s, p0/z, z0\.s, #-16
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--.*: 25c02000 cmplt p0\.d, p0/z, z0\.d, #0
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--.*: 25c0200f cmplt p15\.d, p0/z, z0\.d, #0
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--.*: 25c03c00 cmplt p0\.d, p7/z, z0\.d, #0
--.*: 25c02060 cmplt p0\.d, p0/z, z3\.d, #0
--.*: 25c02060 cmplt p0\.d, p0/z, z3\.d, #0
--.*: 25c023e0 cmplt p0\.d, p0/z, z31\.d, #0
--.*: 25c023e0 cmplt p0\.d, p0/z, z31\.d, #0
--.*: 25cf2000 cmplt p0\.d, p0/z, z0\.d, #15
--.*: 25cf2000 cmplt p0\.d, p0/z, z0\.d, #15
--.*: 25d02000 cmplt p0\.d, p0/z, z0\.d, #-16
--.*: 25d02000 cmplt p0\.d, p0/z, z0\.d, #-16
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--.*: 25d12000 cmplt p0\.d, p0/z, z0\.d, #-15
--.*: 25df2000 cmplt p0\.d, p0/z, z0\.d, #-1
--.*: 25df2000 cmplt p0\.d, p0/z, z0\.d, #-1
--.*: 24002010 cmpne p0\.b, p0/z, z0\.b, z0\.d
--.*: 24002010 cmpne p0\.b, p0/z, z0\.b, z0\.d
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--.*: 24002011 cmpne p1\.b, p0/z, z0\.b, z0\.d
--.*: 2400201f cmpne p15\.b, p0/z, z0\.b, z0\.d
--.*: 2400201f cmpne p15\.b, p0/z, z0\.b, z0\.d
--.*: 24002810 cmpne p0\.b, p2/z, z0\.b, z0\.d
--.*: 24002810 cmpne p0\.b, p2/z, z0\.b, z0\.d
--.*: 24003c10 cmpne p0\.b, p7/z, z0\.b, z0\.d
--.*: 24003c10 cmpne p0\.b, p7/z, z0\.b, z0\.d
--.*: 24002070 cmpne p0\.b, p0/z, z3\.b, z0\.d
--.*: 24002070 cmpne p0\.b, p0/z, z3\.b, z0\.d
--.*: 240023f0 cmpne p0\.b, p0/z, z31\.b, z0\.d
--.*: 240023f0 cmpne p0\.b, p0/z, z31\.b, z0\.d
--.*: 24042010 cmpne p0\.b, p0/z, z0\.b, z4\.d
--.*: 24042010 cmpne p0\.b, p0/z, z0\.b, z4\.d
--.*: 241f2010 cmpne p0\.b, p0/z, z0\.b, z31\.d
--.*: 241f2010 cmpne p0\.b, p0/z, z0\.b, z31\.d
--.*: 24402010 cmpne p0\.h, p0/z, z0\.h, z0\.d
--.*: 24402010 cmpne p0\.h, p0/z, z0\.h, z0\.d
--.*: 24402011 cmpne p1\.h, p0/z, z0\.h, z0\.d
--.*: 24402011 cmpne p1\.h, p0/z, z0\.h, z0\.d
--.*: 2440201f cmpne p15\.h, p0/z, z0\.h, z0\.d
--.*: 2440201f cmpne p15\.h, p0/z, z0\.h, z0\.d
--.*: 24402810 cmpne p0\.h, p2/z, z0\.h, z0\.d
--.*: 24402810 cmpne p0\.h, p2/z, z0\.h, z0\.d
--.*: 24403c10 cmpne p0\.h, p7/z, z0\.h, z0\.d
--.*: 24403c10 cmpne p0\.h, p7/z, z0\.h, z0\.d
--.*: 24402070 cmpne p0\.h, p0/z, z3\.h, z0\.d
--.*: 24402070 cmpne p0\.h, p0/z, z3\.h, z0\.d
--.*: 244023f0 cmpne p0\.h, p0/z, z31\.h, z0\.d
--.*: 244023f0 cmpne p0\.h, p0/z, z31\.h, z0\.d
--.*: 24442010 cmpne p0\.h, p0/z, z0\.h, z4\.d
--.*: 24442010 cmpne p0\.h, p0/z, z0\.h, z4\.d
--.*: 245f2010 cmpne p0\.h, p0/z, z0\.h, z31\.d
--.*: 245f2010 cmpne p0\.h, p0/z, z0\.h, z31\.d
--.*: 24802010 cmpne p0\.s, p0/z, z0\.s, z0\.d
--.*: 24802010 cmpne p0\.s, p0/z, z0\.s, z0\.d
--.*: 24802011 cmpne p1\.s, p0/z, z0\.s, z0\.d
--.*: 24802011 cmpne p1\.s, p0/z, z0\.s, z0\.d
--.*: 2480201f cmpne p15\.s, p0/z, z0\.s, z0\.d
--.*: 2480201f cmpne p15\.s, p0/z, z0\.s, z0\.d
--.*: 24802810 cmpne p0\.s, p2/z, z0\.s, z0\.d
--.*: 24802810 cmpne p0\.s, p2/z, z0\.s, z0\.d
--.*: 24803c10 cmpne p0\.s, p7/z, z0\.s, z0\.d
--.*: 24803c10 cmpne p0\.s, p7/z, z0\.s, z0\.d
--.*: 24802070 cmpne p0\.s, p0/z, z3\.s, z0\.d
--.*: 24802070 cmpne p0\.s, p0/z, z3\.s, z0\.d
--.*: 248023f0 cmpne p0\.s, p0/z, z31\.s, z0\.d
--.*: 248023f0 cmpne p0\.s, p0/z, z31\.s, z0\.d
--.*: 24842010 cmpne p0\.s, p0/z, z0\.s, z4\.d
--.*: 24842010 cmpne p0\.s, p0/z, z0\.s, z4\.d
--.*: 249f2010 cmpne p0\.s, p0/z, z0\.s, z31\.d
--.*: 249f2010 cmpne p0\.s, p0/z, z0\.s, z31\.d
--.*: 2400a010 cmpne p0\.b, p0/z, z0\.b, z0\.b
--.*: 2400a010 cmpne p0\.b, p0/z, z0\.b, z0\.b
--.*: 2400a011 cmpne p1\.b, p0/z, z0\.b, z0\.b
--.*: 2400a011 cmpne p1\.b, p0/z, z0\.b, z0\.b
--.*: 2400a01f cmpne p15\.b, p0/z, z0\.b, z0\.b
--.*: 2400a01f cmpne p15\.b, p0/z, z0\.b, z0\.b
--.*: 2400a810 cmpne p0\.b, p2/z, z0\.b, z0\.b
--.*: 2400a810 cmpne p0\.b, p2/z, z0\.b, z0\.b
--.*: 2400bc10 cmpne p0\.b, p7/z, z0\.b, z0\.b
--.*: 2400bc10 cmpne p0\.b, p7/z, z0\.b, z0\.b
--.*: 2400a070 cmpne p0\.b, p0/z, z3\.b, z0\.b
--.*: 2400a070 cmpne p0\.b, p0/z, z3\.b, z0\.b
--.*: 2400a3f0 cmpne p0\.b, p0/z, z31\.b, z0\.b
--.*: 2400a3f0 cmpne p0\.b, p0/z, z31\.b, z0\.b
--.*: 2404a010 cmpne p0\.b, p0/z, z0\.b, z4\.b
--.*: 2404a010 cmpne p0\.b, p0/z, z0\.b, z4\.b
--.*: 241fa010 cmpne p0\.b, p0/z, z0\.b, z31\.b
--.*: 241fa010 cmpne p0\.b, p0/z, z0\.b, z31\.b
--.*: 2440a010 cmpne p0\.h, p0/z, z0\.h, z0\.h
--.*: 2440a010 cmpne p0\.h, p0/z, z0\.h, z0\.h
--.*: 2440a011 cmpne p1\.h, p0/z, z0\.h, z0\.h
--.*: 2440a011 cmpne p1\.h, p0/z, z0\.h, z0\.h
--.*: 2440a01f cmpne p15\.h, p0/z, z0\.h, z0\.h
--.*: 2440a01f cmpne p15\.h, p0/z, z0\.h, z0\.h
--.*: 2440a810 cmpne p0\.h, p2/z, z0\.h, z0\.h
--.*: 2440a810 cmpne p0\.h, p2/z, z0\.h, z0\.h
--.*: 2440bc10 cmpne p0\.h, p7/z, z0\.h, z0\.h
--.*: 2440bc10 cmpne p0\.h, p7/z, z0\.h, z0\.h
--.*: 2440a070 cmpne p0\.h, p0/z, z3\.h, z0\.h
--.*: 2440a070 cmpne p0\.h, p0/z, z3\.h, z0\.h
--.*: 2440a3f0 cmpne p0\.h, p0/z, z31\.h, z0\.h
--.*: 2440a3f0 cmpne p0\.h, p0/z, z31\.h, z0\.h
--.*: 2444a010 cmpne p0\.h, p0/z, z0\.h, z4\.h
--.*: 2444a010 cmpne p0\.h, p0/z, z0\.h, z4\.h
--.*: 245fa010 cmpne p0\.h, p0/z, z0\.h, z31\.h
--.*: 245fa010 cmpne p0\.h, p0/z, z0\.h, z31\.h
--.*: 2480a010 cmpne p0\.s, p0/z, z0\.s, z0\.s
--.*: 2480a010 cmpne p0\.s, p0/z, z0\.s, z0\.s
--.*: 2480a011 cmpne p1\.s, p0/z, z0\.s, z0\.s
--.*: 2480a011 cmpne p1\.s, p0/z, z0\.s, z0\.s
--.*: 2480a01f cmpne p15\.s, p0/z, z0\.s, z0\.s
--.*: 2480a01f cmpne p15\.s, p0/z, z0\.s, z0\.s
--.*: 2480a810 cmpne p0\.s, p2/z, z0\.s, z0\.s
--.*: 2480a810 cmpne p0\.s, p2/z, z0\.s, z0\.s
--.*: 2480bc10 cmpne p0\.s, p7/z, z0\.s, z0\.s
--.*: 2480bc10 cmpne p0\.s, p7/z, z0\.s, z0\.s
--.*: 2480a070 cmpne p0\.s, p0/z, z3\.s, z0\.s
--.*: 2480a070 cmpne p0\.s, p0/z, z3\.s, z0\.s
--.*: 2480a3f0 cmpne p0\.s, p0/z, z31\.s, z0\.s
--.*: 2480a3f0 cmpne p0\.s, p0/z, z31\.s, z0\.s
--.*: 2484a010 cmpne p0\.s, p0/z, z0\.s, z4\.s
--.*: 2484a010 cmpne p0\.s, p0/z, z0\.s, z4\.s
--.*: 249fa010 cmpne p0\.s, p0/z, z0\.s, z31\.s
--.*: 249fa010 cmpne p0\.s, p0/z, z0\.s, z31\.s
--.*: 24c0a010 cmpne p0\.d, p0/z, z0\.d, z0\.d
--.*: 24c0a010 cmpne p0\.d, p0/z, z0\.d, z0\.d
--.*: 24c0a011 cmpne p1\.d, p0/z, z0\.d, z0\.d
--.*: 24c0a011 cmpne p1\.d, p0/z, z0\.d, z0\.d
--.*: 24c0a01f cmpne p15\.d, p0/z, z0\.d, z0\.d
--.*: 24c0a01f cmpne p15\.d, p0/z, z0\.d, z0\.d
--.*: 24c0a810 cmpne p0\.d, p2/z, z0\.d, z0\.d
--.*: 24c0a810 cmpne p0\.d, p2/z, z0\.d, z0\.d
--.*: 24c0bc10 cmpne p0\.d, p7/z, z0\.d, z0\.d
--.*: 24c0bc10 cmpne p0\.d, p7/z, z0\.d, z0\.d
--.*: 24c0a070 cmpne p0\.d, p0/z, z3\.d, z0\.d
--.*: 24c0a070 cmpne p0\.d, p0/z, z3\.d, z0\.d
--.*: 24c0a3f0 cmpne p0\.d, p0/z, z31\.d, z0\.d
--.*: 24c0a3f0 cmpne p0\.d, p0/z, z31\.d, z0\.d
--.*: 24c4a010 cmpne p0\.d, p0/z, z0\.d, z4\.d
--.*: 24c4a010 cmpne p0\.d, p0/z, z0\.d, z4\.d
--.*: 24dfa010 cmpne p0\.d, p0/z, z0\.d, z31\.d
--.*: 24dfa010 cmpne p0\.d, p0/z, z0\.d, z31\.d
--.*: 25008010 cmpne p0\.b, p0/z, z0\.b, #0
--.*: 25008010 cmpne p0\.b, p0/z, z0\.b, #0
--.*: 25008011 cmpne p1\.b, p0/z, z0\.b, #0
--.*: 25008011 cmpne p1\.b, p0/z, z0\.b, #0
--.*: 2500801f cmpne p15\.b, p0/z, z0\.b, #0
--.*: 2500801f cmpne p15\.b, p0/z, z0\.b, #0
--.*: 25008810 cmpne p0\.b, p2/z, z0\.b, #0
--.*: 25008810 cmpne p0\.b, p2/z, z0\.b, #0
--.*: 25009c10 cmpne p0\.b, p7/z, z0\.b, #0
--.*: 25009c10 cmpne p0\.b, p7/z, z0\.b, #0
--.*: 25008070 cmpne p0\.b, p0/z, z3\.b, #0
--.*: 25008070 cmpne p0\.b, p0/z, z3\.b, #0
--.*: 250083f0 cmpne p0\.b, p0/z, z31\.b, #0
--.*: 250083f0 cmpne p0\.b, p0/z, z31\.b, #0
--.*: 250f8010 cmpne p0\.b, p0/z, z0\.b, #15
--.*: 250f8010 cmpne p0\.b, p0/z, z0\.b, #15
--.*: 25108010 cmpne p0\.b, p0/z, z0\.b, #-16
--.*: 25108010 cmpne p0\.b, p0/z, z0\.b, #-16
--.*: 25118010 cmpne p0\.b, p0/z, z0\.b, #-15
--.*: 25118010 cmpne p0\.b, p0/z, z0\.b, #-15
--.*: 251f8010 cmpne p0\.b, p0/z, z0\.b, #-1
--.*: 251f8010 cmpne p0\.b, p0/z, z0\.b, #-1
--.*: 25408010 cmpne p0\.h, p0/z, z0\.h, #0
--.*: 25408010 cmpne p0\.h, p0/z, z0\.h, #0
--.*: 25408011 cmpne p1\.h, p0/z, z0\.h, #0
--.*: 25408011 cmpne p1\.h, p0/z, z0\.h, #0
--.*: 2540801f cmpne p15\.h, p0/z, z0\.h, #0
--.*: 2540801f cmpne p15\.h, p0/z, z0\.h, #0
--.*: 25408810 cmpne p0\.h, p2/z, z0\.h, #0
--.*: 25408810 cmpne p0\.h, p2/z, z0\.h, #0
--.*: 25409c10 cmpne p0\.h, p7/z, z0\.h, #0
--.*: 25409c10 cmpne p0\.h, p7/z, z0\.h, #0
--.*: 25408070 cmpne p0\.h, p0/z, z3\.h, #0
--.*: 25408070 cmpne p0\.h, p0/z, z3\.h, #0
--.*: 254083f0 cmpne p0\.h, p0/z, z31\.h, #0
--.*: 254083f0 cmpne p0\.h, p0/z, z31\.h, #0
--.*: 254f8010 cmpne p0\.h, p0/z, z0\.h, #15
--.*: 254f8010 cmpne p0\.h, p0/z, z0\.h, #15
--.*: 25508010 cmpne p0\.h, p0/z, z0\.h, #-16
--.*: 25508010 cmpne p0\.h, p0/z, z0\.h, #-16
--.*: 25518010 cmpne p0\.h, p0/z, z0\.h, #-15
--.*: 25518010 cmpne p0\.h, p0/z, z0\.h, #-15
--.*: 255f8010 cmpne p0\.h, p0/z, z0\.h, #-1
--.*: 255f8010 cmpne p0\.h, p0/z, z0\.h, #-1
--.*: 25808010 cmpne p0\.s, p0/z, z0\.s, #0
--.*: 25808010 cmpne p0\.s, p0/z, z0\.s, #0
--.*: 25808011 cmpne p1\.s, p0/z, z0\.s, #0
--.*: 25808011 cmpne p1\.s, p0/z, z0\.s, #0
--.*: 2580801f cmpne p15\.s, p0/z, z0\.s, #0
--.*: 2580801f cmpne p15\.s, p0/z, z0\.s, #0
--.*: 25808810 cmpne p0\.s, p2/z, z0\.s, #0
--.*: 25808810 cmpne p0\.s, p2/z, z0\.s, #0
--.*: 25809c10 cmpne p0\.s, p7/z, z0\.s, #0
--.*: 25809c10 cmpne p0\.s, p7/z, z0\.s, #0
--.*: 25808070 cmpne p0\.s, p0/z, z3\.s, #0
--.*: 25808070 cmpne p0\.s, p0/z, z3\.s, #0
--.*: 258083f0 cmpne p0\.s, p0/z, z31\.s, #0
--.*: 258083f0 cmpne p0\.s, p0/z, z31\.s, #0
--.*: 258f8010 cmpne p0\.s, p0/z, z0\.s, #15
--.*: 258f8010 cmpne p0\.s, p0/z, z0\.s, #15
--.*: 25908010 cmpne p0\.s, p0/z, z0\.s, #-16
--.*: 25908010 cmpne p0\.s, p0/z, z0\.s, #-16
--.*: 25918010 cmpne p0\.s, p0/z, z0\.s, #-15
--.*: 25918010 cmpne p0\.s, p0/z, z0\.s, #-15
--.*: 259f8010 cmpne p0\.s, p0/z, z0\.s, #-1
--.*: 259f8010 cmpne p0\.s, p0/z, z0\.s, #-1
--.*: 25c08010 cmpne p0\.d, p0/z, z0\.d, #0
--.*: 25c08010 cmpne p0\.d, p0/z, z0\.d, #0
--.*: 25c08011 cmpne p1\.d, p0/z, z0\.d, #0
--.*: 25c08011 cmpne p1\.d, p0/z, z0\.d, #0
--.*: 25c0801f cmpne p15\.d, p0/z, z0\.d, #0
--.*: 25c0801f cmpne p15\.d, p0/z, z0\.d, #0
--.*: 25c08810 cmpne p0\.d, p2/z, z0\.d, #0
--.*: 25c08810 cmpne p0\.d, p2/z, z0\.d, #0
--.*: 25c09c10 cmpne p0\.d, p7/z, z0\.d, #0
--.*: 25c09c10 cmpne p0\.d, p7/z, z0\.d, #0
--.*: 25c08070 cmpne p0\.d, p0/z, z3\.d, #0
--.*: 25c08070 cmpne p0\.d, p0/z, z3\.d, #0
--.*: 25c083f0 cmpne p0\.d, p0/z, z31\.d, #0
--.*: 25c083f0 cmpne p0\.d, p0/z, z31\.d, #0
--.*: 25cf8010 cmpne p0\.d, p0/z, z0\.d, #15
--.*: 25cf8010 cmpne p0\.d, p0/z, z0\.d, #15
--.*: 25d08010 cmpne p0\.d, p0/z, z0\.d, #-16
--.*: 25d08010 cmpne p0\.d, p0/z, z0\.d, #-16
--.*: 25d18010 cmpne p0\.d, p0/z, z0\.d, #-15
--.*: 25d18010 cmpne p0\.d, p0/z, z0\.d, #-15
--.*: 25df8010 cmpne p0\.d, p0/z, z0\.d, #-1
--.*: 25df8010 cmpne p0\.d, p0/z, z0\.d, #-1
--.*: 041ba000 cnot z0\.b, p0/m, z0\.b
--.*: 041ba000 cnot z0\.b, p0/m, z0\.b
--.*: 041ba001 cnot z1\.b, p0/m, z0\.b
--.*: 041ba001 cnot z1\.b, p0/m, z0\.b
--.*: 041ba01f cnot z31\.b, p0/m, z0\.b
--.*: 041ba01f cnot z31\.b, p0/m, z0\.b
--.*: 041ba800 cnot z0\.b, p2/m, z0\.b
--.*: 041ba800 cnot z0\.b, p2/m, z0\.b
--.*: 041bbc00 cnot z0\.b, p7/m, z0\.b
--.*: 041bbc00 cnot z0\.b, p7/m, z0\.b
--.*: 041ba060 cnot z0\.b, p0/m, z3\.b
--.*: 041ba060 cnot z0\.b, p0/m, z3\.b
--.*: 041ba3e0 cnot z0\.b, p0/m, z31\.b
--.*: 041ba3e0 cnot z0\.b, p0/m, z31\.b
--.*: 045ba000 cnot z0\.h, p0/m, z0\.h
--.*: 045ba000 cnot z0\.h, p0/m, z0\.h
--.*: 045ba001 cnot z1\.h, p0/m, z0\.h
--.*: 045ba001 cnot z1\.h, p0/m, z0\.h
--.*: 045ba01f cnot z31\.h, p0/m, z0\.h
--.*: 045ba01f cnot z31\.h, p0/m, z0\.h
--.*: 045ba800 cnot z0\.h, p2/m, z0\.h
--.*: 045ba800 cnot z0\.h, p2/m, z0\.h
--.*: 045bbc00 cnot z0\.h, p7/m, z0\.h
--.*: 045bbc00 cnot z0\.h, p7/m, z0\.h
--.*: 045ba060 cnot z0\.h, p0/m, z3\.h
--.*: 045ba060 cnot z0\.h, p0/m, z3\.h
--.*: 045ba3e0 cnot z0\.h, p0/m, z31\.h
--.*: 045ba3e0 cnot z0\.h, p0/m, z31\.h
--.*: 049ba000 cnot z0\.s, p0/m, z0\.s
--.*: 049ba000 cnot z0\.s, p0/m, z0\.s
--.*: 049ba001 cnot z1\.s, p0/m, z0\.s
--.*: 049ba001 cnot z1\.s, p0/m, z0\.s
--.*: 049ba01f cnot z31\.s, p0/m, z0\.s
--.*: 049ba01f cnot z31\.s, p0/m, z0\.s
--.*: 049ba800 cnot z0\.s, p2/m, z0\.s
--.*: 049ba800 cnot z0\.s, p2/m, z0\.s
--.*: 049bbc00 cnot z0\.s, p7/m, z0\.s
--.*: 049bbc00 cnot z0\.s, p7/m, z0\.s
--.*: 049ba060 cnot z0\.s, p0/m, z3\.s
--.*: 049ba060 cnot z0\.s, p0/m, z3\.s
--.*: 049ba3e0 cnot z0\.s, p0/m, z31\.s
--.*: 049ba3e0 cnot z0\.s, p0/m, z31\.s
--.*: 04dba000 cnot z0\.d, p0/m, z0\.d
--.*: 04dba000 cnot z0\.d, p0/m, z0\.d
--.*: 04dba001 cnot z1\.d, p0/m, z0\.d
--.*: 04dba001 cnot z1\.d, p0/m, z0\.d
--.*: 04dba01f cnot z31\.d, p0/m, z0\.d
--.*: 04dba01f cnot z31\.d, p0/m, z0\.d
--.*: 04dba800 cnot z0\.d, p2/m, z0\.d
--.*: 04dba800 cnot z0\.d, p2/m, z0\.d
--.*: 04dbbc00 cnot z0\.d, p7/m, z0\.d
--.*: 04dbbc00 cnot z0\.d, p7/m, z0\.d
--.*: 04dba060 cnot z0\.d, p0/m, z3\.d
--.*: 04dba060 cnot z0\.d, p0/m, z3\.d
--.*: 04dba3e0 cnot z0\.d, p0/m, z31\.d
--.*: 04dba3e0 cnot z0\.d, p0/m, z31\.d
--.*: 041aa000 cnt z0\.b, p0/m, z0\.b
--.*: 041aa000 cnt z0\.b, p0/m, z0\.b
--.*: 041aa001 cnt z1\.b, p0/m, z0\.b
--.*: 041aa001 cnt z1\.b, p0/m, z0\.b
--.*: 041aa01f cnt z31\.b, p0/m, z0\.b
--.*: 041aa01f cnt z31\.b, p0/m, z0\.b
--.*: 041aa800 cnt z0\.b, p2/m, z0\.b
--.*: 041aa800 cnt z0\.b, p2/m, z0\.b
--.*: 041abc00 cnt z0\.b, p7/m, z0\.b
--.*: 041abc00 cnt z0\.b, p7/m, z0\.b
--.*: 041aa060 cnt z0\.b, p0/m, z3\.b
--.*: 041aa060 cnt z0\.b, p0/m, z3\.b
--.*: 041aa3e0 cnt z0\.b, p0/m, z31\.b
--.*: 041aa3e0 cnt z0\.b, p0/m, z31\.b
--.*: 045aa000 cnt z0\.h, p0/m, z0\.h
--.*: 045aa000 cnt z0\.h, p0/m, z0\.h
--.*: 045aa001 cnt z1\.h, p0/m, z0\.h
--.*: 045aa001 cnt z1\.h, p0/m, z0\.h
--.*: 045aa01f cnt z31\.h, p0/m, z0\.h
--.*: 045aa01f cnt z31\.h, p0/m, z0\.h
--.*: 045aa800 cnt z0\.h, p2/m, z0\.h
--.*: 045aa800 cnt z0\.h, p2/m, z0\.h
--.*: 045abc00 cnt z0\.h, p7/m, z0\.h
--.*: 045abc00 cnt z0\.h, p7/m, z0\.h
--.*: 045aa060 cnt z0\.h, p0/m, z3\.h
--.*: 045aa060 cnt z0\.h, p0/m, z3\.h
--.*: 045aa3e0 cnt z0\.h, p0/m, z31\.h
--.*: 045aa3e0 cnt z0\.h, p0/m, z31\.h
--.*: 049aa000 cnt z0\.s, p0/m, z0\.s
--.*: 049aa000 cnt z0\.s, p0/m, z0\.s
--.*: 049aa001 cnt z1\.s, p0/m, z0\.s
--.*: 049aa001 cnt z1\.s, p0/m, z0\.s
--.*: 049aa01f cnt z31\.s, p0/m, z0\.s
--.*: 049aa01f cnt z31\.s, p0/m, z0\.s
--.*: 049aa800 cnt z0\.s, p2/m, z0\.s
--.*: 049aa800 cnt z0\.s, p2/m, z0\.s
--.*: 049abc00 cnt z0\.s, p7/m, z0\.s
--.*: 049abc00 cnt z0\.s, p7/m, z0\.s
--.*: 049aa060 cnt z0\.s, p0/m, z3\.s
--.*: 049aa060 cnt z0\.s, p0/m, z3\.s
--.*: 049aa3e0 cnt z0\.s, p0/m, z31\.s
--.*: 049aa3e0 cnt z0\.s, p0/m, z31\.s
--.*: 04daa000 cnt z0\.d, p0/m, z0\.d
--.*: 04daa000 cnt z0\.d, p0/m, z0\.d
--.*: 04daa001 cnt z1\.d, p0/m, z0\.d
--.*: 04daa001 cnt z1\.d, p0/m, z0\.d
--.*: 04daa01f cnt z31\.d, p0/m, z0\.d
--.*: 04daa01f cnt z31\.d, p0/m, z0\.d
--.*: 04daa800 cnt z0\.d, p2/m, z0\.d
--.*: 04daa800 cnt z0\.d, p2/m, z0\.d
--.*: 04dabc00 cnt z0\.d, p7/m, z0\.d
--.*: 04dabc00 cnt z0\.d, p7/m, z0\.d
--.*: 04daa060 cnt z0\.d, p0/m, z3\.d
--.*: 04daa060 cnt z0\.d, p0/m, z3\.d
--.*: 04daa3e0 cnt z0\.d, p0/m, z31\.d
--.*: 04daa3e0 cnt z0\.d, p0/m, z31\.d
--.*: 0420e000 cntb x0, pow2
--.*: 0420e000 cntb x0, pow2
--.*: 0420e000 cntb x0, pow2
--.*: 0420e001 cntb x1, pow2
--.*: 0420e001 cntb x1, pow2
--.*: 0420e001 cntb x1, pow2
--.*: 0420e01f cntb xzr, pow2
--.*: 0420e01f cntb xzr, pow2
--.*: 0420e01f cntb xzr, pow2
--.*: 0420e020 cntb x0, vl1
--.*: 0420e020 cntb x0, vl1
--.*: 0420e020 cntb x0, vl1
--.*: 0420e040 cntb x0, vl2
--.*: 0420e040 cntb x0, vl2
--.*: 0420e040 cntb x0, vl2
--.*: 0420e060 cntb x0, vl3
--.*: 0420e060 cntb x0, vl3
--.*: 0420e060 cntb x0, vl3
--.*: 0420e080 cntb x0, vl4
--.*: 0420e080 cntb x0, vl4
--.*: 0420e080 cntb x0, vl4
--.*: 0420e0a0 cntb x0, vl5
--.*: 0420e0a0 cntb x0, vl5
--.*: 0420e0a0 cntb x0, vl5
--.*: 0420e0c0 cntb x0, vl6
--.*: 0420e0c0 cntb x0, vl6
--.*: 0420e0c0 cntb x0, vl6
--.*: 0420e0e0 cntb x0, vl7
--.*: 0420e0e0 cntb x0, vl7
--.*: 0420e0e0 cntb x0, vl7
--.*: 0420e100 cntb x0, vl8
--.*: 0420e100 cntb x0, vl8
--.*: 0420e100 cntb x0, vl8
--.*: 0420e120 cntb x0, vl16
--.*: 0420e120 cntb x0, vl16
--.*: 0420e120 cntb x0, vl16
--.*: 0420e140 cntb x0, vl32
--.*: 0420e140 cntb x0, vl32
--.*: 0420e140 cntb x0, vl32
--.*: 0420e160 cntb x0, vl64
--.*: 0420e160 cntb x0, vl64
--.*: 0420e160 cntb x0, vl64
--.*: 0420e180 cntb x0, vl128
--.*: 0420e180 cntb x0, vl128
--.*: 0420e180 cntb x0, vl128
--.*: 0420e1a0 cntb x0, vl256
--.*: 0420e1a0 cntb x0, vl256
--.*: 0420e1a0 cntb x0, vl256
--.*: 0420e1c0 cntb x0, #14
--.*: 0420e1c0 cntb x0, #14
--.*: 0420e1c0 cntb x0, #14
--.*: 0420e1e0 cntb x0, #15
--.*: 0420e1e0 cntb x0, #15
--.*: 0420e1e0 cntb x0, #15
--.*: 0420e200 cntb x0, #16
--.*: 0420e200 cntb x0, #16
--.*: 0420e200 cntb x0, #16
--.*: 0420e220 cntb x0, #17
--.*: 0420e220 cntb x0, #17
--.*: 0420e220 cntb x0, #17
--.*: 0420e240 cntb x0, #18
--.*: 0420e240 cntb x0, #18
--.*: 0420e240 cntb x0, #18
--.*: 0420e260 cntb x0, #19
--.*: 0420e260 cntb x0, #19
--.*: 0420e260 cntb x0, #19
--.*: 0420e280 cntb x0, #20
--.*: 0420e280 cntb x0, #20
--.*: 0420e280 cntb x0, #20
--.*: 0420e2a0 cntb x0, #21
--.*: 0420e2a0 cntb x0, #21
--.*: 0420e2a0 cntb x0, #21
--.*: 0420e2c0 cntb x0, #22
--.*: 0420e2c0 cntb x0, #22
--.*: 0420e2c0 cntb x0, #22
--.*: 0420e2e0 cntb x0, #23
--.*: 0420e2e0 cntb x0, #23
--.*: 0420e2e0 cntb x0, #23
--.*: 0420e300 cntb x0, #24
--.*: 0420e300 cntb x0, #24
--.*: 0420e300 cntb x0, #24
--.*: 0420e320 cntb x0, #25
--.*: 0420e320 cntb x0, #25
--.*: 0420e320 cntb x0, #25
--.*: 0420e340 cntb x0, #26
--.*: 0420e340 cntb x0, #26
--.*: 0420e340 cntb x0, #26
--.*: 0420e360 cntb x0, #27
--.*: 0420e360 cntb x0, #27
--.*: 0420e360 cntb x0, #27
--.*: 0420e380 cntb x0, #28
--.*: 0420e380 cntb x0, #28
--.*: 0420e380 cntb x0, #28
--.*: 0420e3a0 cntb x0, mul4
--.*: 0420e3a0 cntb x0, mul4
--.*: 0420e3a0 cntb x0, mul4
--.*: 0420e3c0 cntb x0, mul3
--.*: 0420e3c0 cntb x0, mul3
--.*: 0420e3c0 cntb x0, mul3
--.*: 0420e3e0 cntb x0
--.*: 0420e3e0 cntb x0
--.*: 0420e3e0 cntb x0
--.*: 0420e3e0 cntb x0
--.*: 0427e000 cntb x0, pow2, mul #8
--.*: 0427e000 cntb x0, pow2, mul #8
--.*: 0428e000 cntb x0, pow2, mul #9
--.*: 0428e000 cntb x0, pow2, mul #9
--.*: 0429e000 cntb x0, pow2, mul #10
--.*: 0429e000 cntb x0, pow2, mul #10
--.*: 042fe000 cntb x0, pow2, mul #16
--.*: 042fe000 cntb x0, pow2, mul #16
--.*: 04e0e000 cntd x0, pow2
--.*: 04e0e000 cntd x0, pow2
--.*: 04e0e000 cntd x0, pow2
--.*: 04e0e001 cntd x1, pow2
--.*: 04e0e001 cntd x1, pow2
--.*: 04e0e001 cntd x1, pow2
--.*: 04e0e01f cntd xzr, pow2
--.*: 04e0e01f cntd xzr, pow2
--.*: 04e0e01f cntd xzr, pow2
--.*: 04e0e020 cntd x0, vl1
--.*: 04e0e020 cntd x0, vl1
--.*: 04e0e020 cntd x0, vl1
--.*: 04e0e040 cntd x0, vl2
--.*: 04e0e040 cntd x0, vl2
--.*: 04e0e040 cntd x0, vl2
--.*: 04e0e060 cntd x0, vl3
--.*: 04e0e060 cntd x0, vl3
--.*: 04e0e060 cntd x0, vl3
--.*: 04e0e080 cntd x0, vl4
--.*: 04e0e080 cntd x0, vl4
--.*: 04e0e080 cntd x0, vl4
--.*: 04e0e0a0 cntd x0, vl5
--.*: 04e0e0a0 cntd x0, vl5
--.*: 04e0e0a0 cntd x0, vl5
--.*: 04e0e0c0 cntd x0, vl6
--.*: 04e0e0c0 cntd x0, vl6
--.*: 04e0e0c0 cntd x0, vl6
--.*: 04e0e0e0 cntd x0, vl7
--.*: 04e0e0e0 cntd x0, vl7
--.*: 04e0e0e0 cntd x0, vl7
--.*: 04e0e100 cntd x0, vl8
--.*: 04e0e100 cntd x0, vl8
--.*: 04e0e100 cntd x0, vl8
--.*: 04e0e120 cntd x0, vl16
--.*: 04e0e120 cntd x0, vl16
--.*: 04e0e120 cntd x0, vl16
--.*: 04e0e140 cntd x0, vl32
--.*: 04e0e140 cntd x0, vl32
--.*: 04e0e140 cntd x0, vl32
--.*: 04e0e160 cntd x0, vl64
--.*: 04e0e160 cntd x0, vl64
--.*: 04e0e160 cntd x0, vl64
--.*: 04e0e180 cntd x0, vl128
--.*: 04e0e180 cntd x0, vl128
--.*: 04e0e180 cntd x0, vl128
--.*: 04e0e1a0 cntd x0, vl256
--.*: 04e0e1a0 cntd x0, vl256
--.*: 04e0e1a0 cntd x0, vl256
--.*: 04e0e1c0 cntd x0, #14
--.*: 04e0e1c0 cntd x0, #14
--.*: 04e0e1c0 cntd x0, #14
--.*: 04e0e1e0 cntd x0, #15
--.*: 04e0e1e0 cntd x0, #15
--.*: 04e0e1e0 cntd x0, #15
--.*: 04e0e200 cntd x0, #16
--.*: 04e0e200 cntd x0, #16
--.*: 04e0e200 cntd x0, #16
--.*: 04e0e220 cntd x0, #17
--.*: 04e0e220 cntd x0, #17
--.*: 04e0e220 cntd x0, #17
--.*: 04e0e240 cntd x0, #18
--.*: 04e0e240 cntd x0, #18
--.*: 04e0e240 cntd x0, #18
--.*: 04e0e260 cntd x0, #19
--.*: 04e0e260 cntd x0, #19
--.*: 04e0e260 cntd x0, #19
--.*: 04e0e280 cntd x0, #20
--.*: 04e0e280 cntd x0, #20
--.*: 04e0e280 cntd x0, #20
--.*: 04e0e2a0 cntd x0, #21
--.*: 04e0e2a0 cntd x0, #21
--.*: 04e0e2a0 cntd x0, #21
--.*: 04e0e2c0 cntd x0, #22
--.*: 04e0e2c0 cntd x0, #22
--.*: 04e0e2c0 cntd x0, #22
--.*: 04e0e2e0 cntd x0, #23
--.*: 04e0e2e0 cntd x0, #23
--.*: 04e0e2e0 cntd x0, #23
--.*: 04e0e300 cntd x0, #24
--.*: 04e0e300 cntd x0, #24
--.*: 04e0e300 cntd x0, #24
--.*: 04e0e320 cntd x0, #25
--.*: 04e0e320 cntd x0, #25
--.*: 04e0e320 cntd x0, #25
--.*: 04e0e340 cntd x0, #26
--.*: 04e0e340 cntd x0, #26
--.*: 04e0e340 cntd x0, #26
--.*: 04e0e360 cntd x0, #27
--.*: 04e0e360 cntd x0, #27
--.*: 04e0e360 cntd x0, #27
--.*: 04e0e380 cntd x0, #28
--.*: 04e0e380 cntd x0, #28
--.*: 04e0e380 cntd x0, #28
--.*: 04e0e3a0 cntd x0, mul4
--.*: 04e0e3a0 cntd x0, mul4
--.*: 04e0e3a0 cntd x0, mul4
--.*: 04e0e3c0 cntd x0, mul3
--.*: 04e0e3c0 cntd x0, mul3
--.*: 04e0e3c0 cntd x0, mul3
--.*: 04e0e3e0 cntd x0
--.*: 04e0e3e0 cntd x0
--.*: 04e0e3e0 cntd x0
--.*: 04e0e3e0 cntd x0
--.*: 04e7e000 cntd x0, pow2, mul #8
--.*: 04e7e000 cntd x0, pow2, mul #8
--.*: 04e8e000 cntd x0, pow2, mul #9
--.*: 04e8e000 cntd x0, pow2, mul #9
--.*: 04e9e000 cntd x0, pow2, mul #10
--.*: 04e9e000 cntd x0, pow2, mul #10
--.*: 04efe000 cntd x0, pow2, mul #16
--.*: 04efe000 cntd x0, pow2, mul #16
--.*: 0460e000 cnth x0, pow2
--.*: 0460e000 cnth x0, pow2
--.*: 0460e000 cnth x0, pow2
--.*: 0460e001 cnth x1, pow2
--.*: 0460e001 cnth x1, pow2
--.*: 0460e001 cnth x1, pow2
--.*: 0460e01f cnth xzr, pow2
--.*: 0460e01f cnth xzr, pow2
--.*: 0460e01f cnth xzr, pow2
--.*: 0460e020 cnth x0, vl1
--.*: 0460e020 cnth x0, vl1
--.*: 0460e020 cnth x0, vl1
--.*: 0460e040 cnth x0, vl2
--.*: 0460e040 cnth x0, vl2
--.*: 0460e040 cnth x0, vl2
--.*: 0460e060 cnth x0, vl3
--.*: 0460e060 cnth x0, vl3
--.*: 0460e060 cnth x0, vl3
--.*: 0460e080 cnth x0, vl4
--.*: 0460e080 cnth x0, vl4
--.*: 0460e080 cnth x0, vl4
--.*: 0460e0a0 cnth x0, vl5
--.*: 0460e0a0 cnth x0, vl5
--.*: 0460e0a0 cnth x0, vl5
--.*: 0460e0c0 cnth x0, vl6
--.*: 0460e0c0 cnth x0, vl6
--.*: 0460e0c0 cnth x0, vl6
--.*: 0460e0e0 cnth x0, vl7
--.*: 0460e0e0 cnth x0, vl7
--.*: 0460e0e0 cnth x0, vl7
--.*: 0460e100 cnth x0, vl8
--.*: 0460e100 cnth x0, vl8
--.*: 0460e100 cnth x0, vl8
--.*: 0460e120 cnth x0, vl16
--.*: 0460e120 cnth x0, vl16
--.*: 0460e120 cnth x0, vl16
--.*: 0460e140 cnth x0, vl32
--.*: 0460e140 cnth x0, vl32
--.*: 0460e140 cnth x0, vl32
--.*: 0460e160 cnth x0, vl64
--.*: 0460e160 cnth x0, vl64
--.*: 0460e160 cnth x0, vl64
--.*: 0460e180 cnth x0, vl128
--.*: 0460e180 cnth x0, vl128
--.*: 0460e180 cnth x0, vl128
--.*: 0460e1a0 cnth x0, vl256
--.*: 0460e1a0 cnth x0, vl256
--.*: 0460e1a0 cnth x0, vl256
--.*: 0460e1c0 cnth x0, #14
--.*: 0460e1c0 cnth x0, #14
--.*: 0460e1c0 cnth x0, #14
--.*: 0460e1e0 cnth x0, #15
--.*: 0460e1e0 cnth x0, #15
--.*: 0460e1e0 cnth x0, #15
--.*: 0460e200 cnth x0, #16
--.*: 0460e200 cnth x0, #16
--.*: 0460e200 cnth x0, #16
--.*: 0460e220 cnth x0, #17
--.*: 0460e220 cnth x0, #17
--.*: 0460e220 cnth x0, #17
--.*: 0460e240 cnth x0, #18
--.*: 0460e240 cnth x0, #18
--.*: 0460e240 cnth x0, #18
--.*: 0460e260 cnth x0, #19
--.*: 0460e260 cnth x0, #19
--.*: 0460e260 cnth x0, #19
--.*: 0460e280 cnth x0, #20
--.*: 0460e280 cnth x0, #20
--.*: 0460e280 cnth x0, #20
--.*: 0460e2a0 cnth x0, #21
--.*: 0460e2a0 cnth x0, #21
--.*: 0460e2a0 cnth x0, #21
--.*: 0460e2c0 cnth x0, #22
--.*: 0460e2c0 cnth x0, #22
--.*: 0460e2c0 cnth x0, #22
--.*: 0460e2e0 cnth x0, #23
--.*: 0460e2e0 cnth x0, #23
--.*: 0460e2e0 cnth x0, #23
--.*: 0460e300 cnth x0, #24
--.*: 0460e300 cnth x0, #24
--.*: 0460e300 cnth x0, #24
--.*: 0460e320 cnth x0, #25
--.*: 0460e320 cnth x0, #25
--.*: 0460e320 cnth x0, #25
--.*: 0460e340 cnth x0, #26
--.*: 0460e340 cnth x0, #26
--.*: 0460e340 cnth x0, #26
--.*: 0460e360 cnth x0, #27
--.*: 0460e360 cnth x0, #27
--.*: 0460e360 cnth x0, #27
--.*: 0460e380 cnth x0, #28
--.*: 0460e380 cnth x0, #28
--.*: 0460e380 cnth x0, #28
--.*: 0460e3a0 cnth x0, mul4
--.*: 0460e3a0 cnth x0, mul4
--.*: 0460e3a0 cnth x0, mul4
--.*: 0460e3c0 cnth x0, mul3
--.*: 0460e3c0 cnth x0, mul3
--.*: 0460e3c0 cnth x0, mul3
--.*: 0460e3e0 cnth x0
--.*: 0460e3e0 cnth x0
--.*: 0460e3e0 cnth x0
--.*: 0460e3e0 cnth x0
--.*: 0467e000 cnth x0, pow2, mul #8
--.*: 0467e000 cnth x0, pow2, mul #8
--.*: 0468e000 cnth x0, pow2, mul #9
--.*: 0468e000 cnth x0, pow2, mul #9
--.*: 0469e000 cnth x0, pow2, mul #10
--.*: 0469e000 cnth x0, pow2, mul #10
--.*: 046fe000 cnth x0, pow2, mul #16
--.*: 046fe000 cnth x0, pow2, mul #16
--.*: 25208000 cntp x0, p0, p0\.b
--.*: 25208000 cntp x0, p0, p0\.b
--.*: 25208001 cntp x1, p0, p0\.b
--.*: 25208001 cntp x1, p0, p0\.b
--.*: 2520801f cntp xzr, p0, p0\.b
--.*: 2520801f cntp xzr, p0, p0\.b
--.*: 25208800 cntp x0, p2, p0\.b
--.*: 25208800 cntp x0, p2, p0\.b
--.*: 2520bc00 cntp x0, p15, p0\.b
--.*: 2520bc00 cntp x0, p15, p0\.b
--.*: 25208060 cntp x0, p0, p3\.b
--.*: 25208060 cntp x0, p0, p3\.b
--.*: 252081e0 cntp x0, p0, p15\.b
--.*: 252081e0 cntp x0, p0, p15\.b
--.*: 25608000 cntp x0, p0, p0\.h
--.*: 25608000 cntp x0, p0, p0\.h
--.*: 25608001 cntp x1, p0, p0\.h
--.*: 25608001 cntp x1, p0, p0\.h
--.*: 2560801f cntp xzr, p0, p0\.h
--.*: 2560801f cntp xzr, p0, p0\.h
--.*: 25608800 cntp x0, p2, p0\.h
--.*: 25608800 cntp x0, p2, p0\.h
--.*: 2560bc00 cntp x0, p15, p0\.h
--.*: 2560bc00 cntp x0, p15, p0\.h
--.*: 25608060 cntp x0, p0, p3\.h
--.*: 25608060 cntp x0, p0, p3\.h
--.*: 256081e0 cntp x0, p0, p15\.h
--.*: 256081e0 cntp x0, p0, p15\.h
--.*: 25a08000 cntp x0, p0, p0\.s
--.*: 25a08000 cntp x0, p0, p0\.s
--.*: 25a08001 cntp x1, p0, p0\.s
--.*: 25a08001 cntp x1, p0, p0\.s
--.*: 25a0801f cntp xzr, p0, p0\.s
--.*: 25a0801f cntp xzr, p0, p0\.s
--.*: 25a08800 cntp x0, p2, p0\.s
--.*: 25a08800 cntp x0, p2, p0\.s
--.*: 25a0bc00 cntp x0, p15, p0\.s
--.*: 25a0bc00 cntp x0, p15, p0\.s
--.*: 25a08060 cntp x0, p0, p3\.s
--.*: 25a08060 cntp x0, p0, p3\.s
--.*: 25a081e0 cntp x0, p0, p15\.s
--.*: 25a081e0 cntp x0, p0, p15\.s
--.*: 25e08000 cntp x0, p0, p0\.d
--.*: 25e08000 cntp x0, p0, p0\.d
--.*: 25e08001 cntp x1, p0, p0\.d
--.*: 25e08001 cntp x1, p0, p0\.d
--.*: 25e0801f cntp xzr, p0, p0\.d
--.*: 25e0801f cntp xzr, p0, p0\.d
--.*: 25e08800 cntp x0, p2, p0\.d
--.*: 25e08800 cntp x0, p2, p0\.d
--.*: 25e0bc00 cntp x0, p15, p0\.d
--.*: 25e0bc00 cntp x0, p15, p0\.d
--.*: 25e08060 cntp x0, p0, p3\.d
--.*: 25e08060 cntp x0, p0, p3\.d
--.*: 25e081e0 cntp x0, p0, p15\.d
--.*: 25e081e0 cntp x0, p0, p15\.d
--.*: 04a0e000 cntw x0, pow2
--.*: 04a0e000 cntw x0, pow2
--.*: 04a0e000 cntw x0, pow2
--.*: 04a0e001 cntw x1, pow2
--.*: 04a0e001 cntw x1, pow2
--.*: 04a0e001 cntw x1, pow2
--.*: 04a0e01f cntw xzr, pow2
--.*: 04a0e01f cntw xzr, pow2
--.*: 04a0e01f cntw xzr, pow2
--.*: 04a0e020 cntw x0, vl1
--.*: 04a0e020 cntw x0, vl1
--.*: 04a0e020 cntw x0, vl1
--.*: 04a0e040 cntw x0, vl2
--.*: 04a0e040 cntw x0, vl2
--.*: 04a0e040 cntw x0, vl2
--.*: 04a0e060 cntw x0, vl3
--.*: 04a0e060 cntw x0, vl3
--.*: 04a0e060 cntw x0, vl3
--.*: 04a0e080 cntw x0, vl4
--.*: 04a0e080 cntw x0, vl4
--.*: 04a0e080 cntw x0, vl4
--.*: 04a0e0a0 cntw x0, vl5
--.*: 04a0e0a0 cntw x0, vl5
--.*: 04a0e0a0 cntw x0, vl5
--.*: 04a0e0c0 cntw x0, vl6
--.*: 04a0e0c0 cntw x0, vl6
--.*: 04a0e0c0 cntw x0, vl6
--.*: 04a0e0e0 cntw x0, vl7
--.*: 04a0e0e0 cntw x0, vl7
--.*: 04a0e0e0 cntw x0, vl7
--.*: 04a0e100 cntw x0, vl8
--.*: 04a0e100 cntw x0, vl8
--.*: 04a0e100 cntw x0, vl8
--.*: 04a0e120 cntw x0, vl16
--.*: 04a0e120 cntw x0, vl16
--.*: 04a0e120 cntw x0, vl16
--.*: 04a0e140 cntw x0, vl32
--.*: 04a0e140 cntw x0, vl32
--.*: 04a0e140 cntw x0, vl32
--.*: 04a0e160 cntw x0, vl64
--.*: 04a0e160 cntw x0, vl64
--.*: 04a0e160 cntw x0, vl64
--.*: 04a0e180 cntw x0, vl128
--.*: 04a0e180 cntw x0, vl128
--.*: 04a0e180 cntw x0, vl128
--.*: 04a0e1a0 cntw x0, vl256
--.*: 04a0e1a0 cntw x0, vl256
--.*: 04a0e1a0 cntw x0, vl256
--.*: 04a0e1c0 cntw x0, #14
--.*: 04a0e1c0 cntw x0, #14
--.*: 04a0e1c0 cntw x0, #14
--.*: 04a0e1e0 cntw x0, #15
--.*: 04a0e1e0 cntw x0, #15
--.*: 04a0e1e0 cntw x0, #15
--.*: 04a0e200 cntw x0, #16
--.*: 04a0e200 cntw x0, #16
--.*: 04a0e200 cntw x0, #16
--.*: 04a0e220 cntw x0, #17
--.*: 04a0e220 cntw x0, #17
--.*: 04a0e220 cntw x0, #17
--.*: 04a0e240 cntw x0, #18
--.*: 04a0e240 cntw x0, #18
--.*: 04a0e240 cntw x0, #18
--.*: 04a0e260 cntw x0, #19
--.*: 04a0e260 cntw x0, #19
--.*: 04a0e260 cntw x0, #19
--.*: 04a0e280 cntw x0, #20
--.*: 04a0e280 cntw x0, #20
--.*: 04a0e280 cntw x0, #20
--.*: 04a0e2a0 cntw x0, #21
--.*: 04a0e2a0 cntw x0, #21
--.*: 04a0e2a0 cntw x0, #21
--.*: 04a0e2c0 cntw x0, #22
--.*: 04a0e2c0 cntw x0, #22
--.*: 04a0e2c0 cntw x0, #22
--.*: 04a0e2e0 cntw x0, #23
--.*: 04a0e2e0 cntw x0, #23
--.*: 04a0e2e0 cntw x0, #23
--.*: 04a0e300 cntw x0, #24
--.*: 04a0e300 cntw x0, #24
--.*: 04a0e300 cntw x0, #24
--.*: 04a0e320 cntw x0, #25
--.*: 04a0e320 cntw x0, #25
--.*: 04a0e320 cntw x0, #25
--.*: 04a0e340 cntw x0, #26
--.*: 04a0e340 cntw x0, #26
--.*: 04a0e340 cntw x0, #26
--.*: 04a0e360 cntw x0, #27
--.*: 04a0e360 cntw x0, #27
--.*: 04a0e360 cntw x0, #27
--.*: 04a0e380 cntw x0, #28
--.*: 04a0e380 cntw x0, #28
--.*: 04a0e380 cntw x0, #28
--.*: 04a0e3a0 cntw x0, mul4
--.*: 04a0e3a0 cntw x0, mul4
--.*: 04a0e3a0 cntw x0, mul4
--.*: 04a0e3c0 cntw x0, mul3
--.*: 04a0e3c0 cntw x0, mul3
--.*: 04a0e3c0 cntw x0, mul3
--.*: 04a0e3e0 cntw x0
--.*: 04a0e3e0 cntw x0
--.*: 04a0e3e0 cntw x0
--.*: 04a0e3e0 cntw x0
--.*: 04a7e000 cntw x0, pow2, mul #8
--.*: 04a7e000 cntw x0, pow2, mul #8
--.*: 04a8e000 cntw x0, pow2, mul #9
--.*: 04a8e000 cntw x0, pow2, mul #9
--.*: 04a9e000 cntw x0, pow2, mul #10
--.*: 04a9e000 cntw x0, pow2, mul #10
--.*: 04afe000 cntw x0, pow2, mul #16
--.*: 04afe000 cntw x0, pow2, mul #16
--.*: 05a18000 compact z0\.s, p0, z0\.s
--.*: 05a18000 compact z0\.s, p0, z0\.s
--.*: 05a18001 compact z1\.s, p0, z0\.s
--.*: 05a18001 compact z1\.s, p0, z0\.s
--.*: 05a1801f compact z31\.s, p0, z0\.s
--.*: 05a1801f compact z31\.s, p0, z0\.s
--.*: 05a18800 compact z0\.s, p2, z0\.s
--.*: 05a18800 compact z0\.s, p2, z0\.s
--.*: 05a19c00 compact z0\.s, p7, z0\.s
--.*: 05a19c00 compact z0\.s, p7, z0\.s
--.*: 05a18060 compact z0\.s, p0, z3\.s
--.*: 05a18060 compact z0\.s, p0, z3\.s
--.*: 05a183e0 compact z0\.s, p0, z31\.s
--.*: 05a183e0 compact z0\.s, p0, z31\.s
--.*: 05e18000 compact z0\.d, p0, z0\.d
--.*: 05e18000 compact z0\.d, p0, z0\.d
--.*: 05e18001 compact z1\.d, p0, z0\.d
--.*: 05e18001 compact z1\.d, p0, z0\.d
--.*: 05e1801f compact z31\.d, p0, z0\.d
--.*: 05e1801f compact z31\.d, p0, z0\.d
--.*: 05e18800 compact z0\.d, p2, z0\.d
--.*: 05e18800 compact z0\.d, p2, z0\.d
--.*: 05e19c00 compact z0\.d, p7, z0\.d
--.*: 05e19c00 compact z0\.d, p7, z0\.d
--.*: 05e18060 compact z0\.d, p0, z3\.d
--.*: 05e18060 compact z0\.d, p0, z3\.d
--.*: 05e183e0 compact z0\.d, p0, z31\.d
--.*: 05e183e0 compact z0\.d, p0, z31\.d
--.*: 05208000 mov z0\.b, p0/m, b0
--.*: 05208000 mov z0\.b, p0/m, b0
--.*: 05208001 mov z1\.b, p0/m, b0
--.*: 05208001 mov z1\.b, p0/m, b0
--.*: 0520801f mov z31\.b, p0/m, b0
--.*: 0520801f mov z31\.b, p0/m, b0
--.*: 05208800 mov z0\.b, p2/m, b0
--.*: 05208800 mov z0\.b, p2/m, b0
--.*: 05209c00 mov z0\.b, p7/m, b0
--.*: 05209c00 mov z0\.b, p7/m, b0
--.*: 05208060 mov z0\.b, p0/m, b3
--.*: 05208060 mov z0\.b, p0/m, b3
--.*: 052083e0 mov z0\.b, p0/m, b31
--.*: 052083e0 mov z0\.b, p0/m, b31
--.*: 05608000 mov z0\.h, p0/m, h0
--.*: 05608000 mov z0\.h, p0/m, h0
--.*: 05608001 mov z1\.h, p0/m, h0
--.*: 05608001 mov z1\.h, p0/m, h0
--.*: 0560801f mov z31\.h, p0/m, h0
--.*: 0560801f mov z31\.h, p0/m, h0
--.*: 05608800 mov z0\.h, p2/m, h0
--.*: 05608800 mov z0\.h, p2/m, h0
--.*: 05609c00 mov z0\.h, p7/m, h0
--.*: 05609c00 mov z0\.h, p7/m, h0
--.*: 05608060 mov z0\.h, p0/m, h3
--.*: 05608060 mov z0\.h, p0/m, h3
--.*: 056083e0 mov z0\.h, p0/m, h31
--.*: 056083e0 mov z0\.h, p0/m, h31
--.*: 05a08000 mov z0\.s, p0/m, s0
--.*: 05a08000 mov z0\.s, p0/m, s0
--.*: 05a08001 mov z1\.s, p0/m, s0
--.*: 05a08001 mov z1\.s, p0/m, s0
--.*: 05a0801f mov z31\.s, p0/m, s0
--.*: 05a0801f mov z31\.s, p0/m, s0
--.*: 05a08800 mov z0\.s, p2/m, s0
--.*: 05a08800 mov z0\.s, p2/m, s0
--.*: 05a09c00 mov z0\.s, p7/m, s0
--.*: 05a09c00 mov z0\.s, p7/m, s0
--.*: 05a08060 mov z0\.s, p0/m, s3
--.*: 05a08060 mov z0\.s, p0/m, s3
--.*: 05a083e0 mov z0\.s, p0/m, s31
--.*: 05a083e0 mov z0\.s, p0/m, s31
--.*: 05e08000 mov z0\.d, p0/m, d0
--.*: 05e08000 mov z0\.d, p0/m, d0
--.*: 05e08001 mov z1\.d, p0/m, d0
--.*: 05e08001 mov z1\.d, p0/m, d0
--.*: 05e0801f mov z31\.d, p0/m, d0
--.*: 05e0801f mov z31\.d, p0/m, d0
--.*: 05e08800 mov z0\.d, p2/m, d0
--.*: 05e08800 mov z0\.d, p2/m, d0
--.*: 05e09c00 mov z0\.d, p7/m, d0
--.*: 05e09c00 mov z0\.d, p7/m, d0
--.*: 05e08060 mov z0\.d, p0/m, d3
--.*: 05e08060 mov z0\.d, p0/m, d3
--.*: 05e083e0 mov z0\.d, p0/m, d31
--.*: 05e083e0 mov z0\.d, p0/m, d31
--.*: 0528a000 mov z0\.b, p0/m, w0
--.*: 0528a000 mov z0\.b, p0/m, w0
--.*: 0528a001 mov z1\.b, p0/m, w0
--.*: 0528a001 mov z1\.b, p0/m, w0
--.*: 0528a01f mov z31\.b, p0/m, w0
--.*: 0528a01f mov z31\.b, p0/m, w0
--.*: 0528a800 mov z0\.b, p2/m, w0
--.*: 0528a800 mov z0\.b, p2/m, w0
--.*: 0528bc00 mov z0\.b, p7/m, w0
--.*: 0528bc00 mov z0\.b, p7/m, w0
--.*: 0528a060 mov z0\.b, p0/m, w3
--.*: 0528a060 mov z0\.b, p0/m, w3
--.*: 0528a3e0 mov z0\.b, p0/m, wsp
--.*: 0528a3e0 mov z0\.b, p0/m, wsp
--.*: 0568a000 mov z0\.h, p0/m, w0
--.*: 0568a000 mov z0\.h, p0/m, w0
--.*: 0568a001 mov z1\.h, p0/m, w0
--.*: 0568a001 mov z1\.h, p0/m, w0
--.*: 0568a01f mov z31\.h, p0/m, w0
--.*: 0568a01f mov z31\.h, p0/m, w0
--.*: 0568a800 mov z0\.h, p2/m, w0
--.*: 0568a800 mov z0\.h, p2/m, w0
--.*: 0568bc00 mov z0\.h, p7/m, w0
--.*: 0568bc00 mov z0\.h, p7/m, w0
--.*: 0568a060 mov z0\.h, p0/m, w3
--.*: 0568a060 mov z0\.h, p0/m, w3
--.*: 0568a3e0 mov z0\.h, p0/m, wsp
--.*: 0568a3e0 mov z0\.h, p0/m, wsp
--.*: 05a8a000 mov z0\.s, p0/m, w0
--.*: 05a8a000 mov z0\.s, p0/m, w0
--.*: 05a8a001 mov z1\.s, p0/m, w0
--.*: 05a8a001 mov z1\.s, p0/m, w0
--.*: 05a8a01f mov z31\.s, p0/m, w0
--.*: 05a8a01f mov z31\.s, p0/m, w0
--.*: 05a8a800 mov z0\.s, p2/m, w0
--.*: 05a8a800 mov z0\.s, p2/m, w0
--.*: 05a8bc00 mov z0\.s, p7/m, w0
--.*: 05a8bc00 mov z0\.s, p7/m, w0
--.*: 05a8a060 mov z0\.s, p0/m, w3
--.*: 05a8a060 mov z0\.s, p0/m, w3
--.*: 05a8a3e0 mov z0\.s, p0/m, wsp
--.*: 05a8a3e0 mov z0\.s, p0/m, wsp
--.*: 05e8a000 mov z0\.d, p0/m, x0
--.*: 05e8a000 mov z0\.d, p0/m, x0
--.*: 05e8a001 mov z1\.d, p0/m, x0
--.*: 05e8a001 mov z1\.d, p0/m, x0
--.*: 05e8a01f mov z31\.d, p0/m, x0
--.*: 05e8a01f mov z31\.d, p0/m, x0
--.*: 05e8a800 mov z0\.d, p2/m, x0
--.*: 05e8a800 mov z0\.d, p2/m, x0
--.*: 05e8bc00 mov z0\.d, p7/m, x0
--.*: 05e8bc00 mov z0\.d, p7/m, x0
--.*: 05e8a060 mov z0\.d, p0/m, x3
--.*: 05e8a060 mov z0\.d, p0/m, x3
--.*: 05e8a3e0 mov z0\.d, p0/m, sp
--.*: 05e8a3e0 mov z0\.d, p0/m, sp
--.*: 05100000 mov z0\.b, p0/z, #0
--.*: 05100000 mov z0\.b, p0/z, #0
--.*: 05100000 mov z0\.b, p0/z, #0
--.*: 05100001 mov z1\.b, p0/z, #0
--.*: 05100001 mov z1\.b, p0/z, #0
--.*: 05100001 mov z1\.b, p0/z, #0
--.*: 0510001f mov z31\.b, p0/z, #0
--.*: 0510001f mov z31\.b, p0/z, #0
--.*: 0510001f mov z31\.b, p0/z, #0
--.*: 05120000 mov z0\.b, p2/z, #0
--.*: 05120000 mov z0\.b, p2/z, #0
--.*: 05120000 mov z0\.b, p2/z, #0
--.*: 051f0000 mov z0\.b, p15/z, #0
--.*: 051f0000 mov z0\.b, p15/z, #0
--.*: 051f0000 mov z0\.b, p15/z, #0
--.*: 05100fe0 mov z0\.b, p0/z, #127
--.*: 05100fe0 mov z0\.b, p0/z, #127
--.*: 05100fe0 mov z0\.b, p0/z, #127
--.*: 05101000 mov z0\.b, p0/z, #-128
--.*: 05101000 mov z0\.b, p0/z, #-128
--.*: 05101000 mov z0\.b, p0/z, #-128
--.*: 05101020 mov z0\.b, p0/z, #-127
--.*: 05101020 mov z0\.b, p0/z, #-127
--.*: 05101020 mov z0\.b, p0/z, #-127
--.*: 05101fe0 mov z0\.b, p0/z, #-1
--.*: 05101fe0 mov z0\.b, p0/z, #-1
--.*: 05101fe0 mov z0\.b, p0/z, #-1
--.*: 05104000 mov z0\.b, p0/m, #0
--.*: 05104000 mov z0\.b, p0/m, #0
--.*: 05104000 mov z0\.b, p0/m, #0
--.*: 05104001 mov z1\.b, p0/m, #0
--.*: 05104001 mov z1\.b, p0/m, #0
--.*: 05104001 mov z1\.b, p0/m, #0
--.*: 0510401f mov z31\.b, p0/m, #0
--.*: 0510401f mov z31\.b, p0/m, #0
--.*: 0510401f mov z31\.b, p0/m, #0
--.*: 05124000 mov z0\.b, p2/m, #0
--.*: 05124000 mov z0\.b, p2/m, #0
--.*: 05124000 mov z0\.b, p2/m, #0
--.*: 051f4000 mov z0\.b, p15/m, #0
--.*: 051f4000 mov z0\.b, p15/m, #0
--.*: 051f4000 mov z0\.b, p15/m, #0
--.*: 05104fe0 mov z0\.b, p0/m, #127
--.*: 05104fe0 mov z0\.b, p0/m, #127
--.*: 05104fe0 mov z0\.b, p0/m, #127
--.*: 05105000 mov z0\.b, p0/m, #-128
--.*: 05105000 mov z0\.b, p0/m, #-128
--.*: 05105000 mov z0\.b, p0/m, #-128
--.*: 05105020 mov z0\.b, p0/m, #-127
--.*: 05105020 mov z0\.b, p0/m, #-127
--.*: 05105020 mov z0\.b, p0/m, #-127
--.*: 05105fe0 mov z0\.b, p0/m, #-1
--.*: 05105fe0 mov z0\.b, p0/m, #-1
--.*: 05105fe0 mov z0\.b, p0/m, #-1
--.*: 05500000 mov z0\.h, p0/z, #0
--.*: 05500000 mov z0\.h, p0/z, #0
--.*: 05500000 mov z0\.h, p0/z, #0
--.*: 05500001 mov z1\.h, p0/z, #0
--.*: 05500001 mov z1\.h, p0/z, #0
--.*: 05500001 mov z1\.h, p0/z, #0
--.*: 0550001f mov z31\.h, p0/z, #0
--.*: 0550001f mov z31\.h, p0/z, #0
--.*: 0550001f mov z31\.h, p0/z, #0
--.*: 05520000 mov z0\.h, p2/z, #0
--.*: 05520000 mov z0\.h, p2/z, #0
--.*: 05520000 mov z0\.h, p2/z, #0
--.*: 055f0000 mov z0\.h, p15/z, #0
--.*: 055f0000 mov z0\.h, p15/z, #0
--.*: 055f0000 mov z0\.h, p15/z, #0
--.*: 05500fe0 mov z0\.h, p0/z, #127
--.*: 05500fe0 mov z0\.h, p0/z, #127
--.*: 05500fe0 mov z0\.h, p0/z, #127
--.*: 05501000 mov z0\.h, p0/z, #-128
--.*: 05501000 mov z0\.h, p0/z, #-128
--.*: 05501000 mov z0\.h, p0/z, #-128
--.*: 05501020 mov z0\.h, p0/z, #-127
--.*: 05501020 mov z0\.h, p0/z, #-127
--.*: 05501020 mov z0\.h, p0/z, #-127
--.*: 05501fe0 mov z0\.h, p0/z, #-1
--.*: 05501fe0 mov z0\.h, p0/z, #-1
--.*: 05501fe0 mov z0\.h, p0/z, #-1
--.*: 05502000 mov z0\.h, p0/z, #0, lsl #8
--.*: 05502000 mov z0\.h, p0/z, #0, lsl #8
--.*: 05502fe0 mov z0\.h, p0/z, #32512
--.*: 05502fe0 mov z0\.h, p0/z, #32512
--.*: 05502fe0 mov z0\.h, p0/z, #32512
--.*: 05502fe0 mov z0\.h, p0/z, #32512
--.*: 05503000 mov z0\.h, p0/z, #-32768
--.*: 05503000 mov z0\.h, p0/z, #-32768
--.*: 05503000 mov z0\.h, p0/z, #-32768
--.*: 05503000 mov z0\.h, p0/z, #-32768
--.*: 05503020 mov z0\.h, p0/z, #-32512
--.*: 05503020 mov z0\.h, p0/z, #-32512
--.*: 05503020 mov z0\.h, p0/z, #-32512
--.*: 05503020 mov z0\.h, p0/z, #-32512
--.*: 05503fe0 mov z0\.h, p0/z, #-256
--.*: 05503fe0 mov z0\.h, p0/z, #-256
--.*: 05503fe0 mov z0\.h, p0/z, #-256
--.*: 05503fe0 mov z0\.h, p0/z, #-256
--.*: 05504000 mov z0\.h, p0/m, #0
--.*: 05504000 mov z0\.h, p0/m, #0
--.*: 05504000 mov z0\.h, p0/m, #0
--.*: 05504001 mov z1\.h, p0/m, #0
--.*: 05504001 mov z1\.h, p0/m, #0
--.*: 05504001 mov z1\.h, p0/m, #0
--.*: 0550401f mov z31\.h, p0/m, #0
--.*: 0550401f mov z31\.h, p0/m, #0
--.*: 0550401f mov z31\.h, p0/m, #0
--.*: 05524000 mov z0\.h, p2/m, #0
--.*: 05524000 mov z0\.h, p2/m, #0
--.*: 05524000 mov z0\.h, p2/m, #0
--.*: 055f4000 mov z0\.h, p15/m, #0
--.*: 055f4000 mov z0\.h, p15/m, #0
--.*: 055f4000 mov z0\.h, p15/m, #0
--.*: 05504fe0 mov z0\.h, p0/m, #127
--.*: 05504fe0 mov z0\.h, p0/m, #127
--.*: 05504fe0 mov z0\.h, p0/m, #127
--.*: 05505000 mov z0\.h, p0/m, #-128
--.*: 05505000 mov z0\.h, p0/m, #-128
--.*: 05505000 mov z0\.h, p0/m, #-128
--.*: 05505020 mov z0\.h, p0/m, #-127
--.*: 05505020 mov z0\.h, p0/m, #-127
--.*: 05505020 mov z0\.h, p0/m, #-127
--.*: 05505fe0 mov z0\.h, p0/m, #-1
--.*: 05505fe0 mov z0\.h, p0/m, #-1
--.*: 05505fe0 mov z0\.h, p0/m, #-1
--.*: 05506000 mov z0\.h, p0/m, #0, lsl #8
--.*: 05506000 mov z0\.h, p0/m, #0, lsl #8
--.*: 05506fe0 mov z0\.h, p0/m, #32512
--.*: 05506fe0 mov z0\.h, p0/m, #32512
--.*: 05506fe0 mov z0\.h, p0/m, #32512
--.*: 05506fe0 mov z0\.h, p0/m, #32512
--.*: 05507000 mov z0\.h, p0/m, #-32768
--.*: 05507000 mov z0\.h, p0/m, #-32768
--.*: 05507000 mov z0\.h, p0/m, #-32768
--.*: 05507000 mov z0\.h, p0/m, #-32768
--.*: 05507020 mov z0\.h, p0/m, #-32512
--.*: 05507020 mov z0\.h, p0/m, #-32512
--.*: 05507020 mov z0\.h, p0/m, #-32512
--.*: 05507020 mov z0\.h, p0/m, #-32512
--.*: 05507fe0 mov z0\.h, p0/m, #-256
--.*: 05507fe0 mov z0\.h, p0/m, #-256
--.*: 05507fe0 mov z0\.h, p0/m, #-256
--.*: 05507fe0 mov z0\.h, p0/m, #-256
--.*: 05900000 mov z0\.s, p0/z, #0
--.*: 05900000 mov z0\.s, p0/z, #0
--.*: 05900000 mov z0\.s, p0/z, #0
--.*: 05900001 mov z1\.s, p0/z, #0
--.*: 05900001 mov z1\.s, p0/z, #0
--.*: 05900001 mov z1\.s, p0/z, #0
--.*: 0590001f mov z31\.s, p0/z, #0
--.*: 0590001f mov z31\.s, p0/z, #0
--.*: 0590001f mov z31\.s, p0/z, #0
--.*: 05920000 mov z0\.s, p2/z, #0
--.*: 05920000 mov z0\.s, p2/z, #0
--.*: 05920000 mov z0\.s, p2/z, #0
--.*: 059f0000 mov z0\.s, p15/z, #0
--.*: 059f0000 mov z0\.s, p15/z, #0
--.*: 059f0000 mov z0\.s, p15/z, #0
--.*: 05900fe0 mov z0\.s, p0/z, #127
--.*: 05900fe0 mov z0\.s, p0/z, #127
--.*: 05900fe0 mov z0\.s, p0/z, #127
--.*: 05901000 mov z0\.s, p0/z, #-128
--.*: 05901000 mov z0\.s, p0/z, #-128
--.*: 05901000 mov z0\.s, p0/z, #-128
--.*: 05901020 mov z0\.s, p0/z, #-127
--.*: 05901020 mov z0\.s, p0/z, #-127
--.*: 05901020 mov z0\.s, p0/z, #-127
--.*: 05901fe0 mov z0\.s, p0/z, #-1
--.*: 05901fe0 mov z0\.s, p0/z, #-1
--.*: 05901fe0 mov z0\.s, p0/z, #-1
--.*: 05902000 mov z0\.s, p0/z, #0, lsl #8
--.*: 05902000 mov z0\.s, p0/z, #0, lsl #8
--.*: 05902fe0 mov z0\.s, p0/z, #32512
--.*: 05902fe0 mov z0\.s, p0/z, #32512
--.*: 05902fe0 mov z0\.s, p0/z, #32512
--.*: 05902fe0 mov z0\.s, p0/z, #32512
--.*: 05903000 mov z0\.s, p0/z, #-32768
--.*: 05903000 mov z0\.s, p0/z, #-32768
--.*: 05903000 mov z0\.s, p0/z, #-32768
--.*: 05903000 mov z0\.s, p0/z, #-32768
--.*: 05903020 mov z0\.s, p0/z, #-32512
--.*: 05903020 mov z0\.s, p0/z, #-32512
--.*: 05903020 mov z0\.s, p0/z, #-32512
--.*: 05903020 mov z0\.s, p0/z, #-32512
--.*: 05903fe0 mov z0\.s, p0/z, #-256
--.*: 05903fe0 mov z0\.s, p0/z, #-256
--.*: 05903fe0 mov z0\.s, p0/z, #-256
--.*: 05903fe0 mov z0\.s, p0/z, #-256
--.*: 05904000 mov z0\.s, p0/m, #0
--.*: 05904000 mov z0\.s, p0/m, #0
--.*: 05904000 mov z0\.s, p0/m, #0
--.*: 05904001 mov z1\.s, p0/m, #0
--.*: 05904001 mov z1\.s, p0/m, #0
--.*: 05904001 mov z1\.s, p0/m, #0
--.*: 0590401f mov z31\.s, p0/m, #0
--.*: 0590401f mov z31\.s, p0/m, #0
--.*: 0590401f mov z31\.s, p0/m, #0
--.*: 05924000 mov z0\.s, p2/m, #0
--.*: 05924000 mov z0\.s, p2/m, #0
--.*: 05924000 mov z0\.s, p2/m, #0
--.*: 059f4000 mov z0\.s, p15/m, #0
--.*: 059f4000 mov z0\.s, p15/m, #0
--.*: 059f4000 mov z0\.s, p15/m, #0
--.*: 05904fe0 mov z0\.s, p0/m, #127
--.*: 05904fe0 mov z0\.s, p0/m, #127
--.*: 05904fe0 mov z0\.s, p0/m, #127
--.*: 05905000 mov z0\.s, p0/m, #-128
--.*: 05905000 mov z0\.s, p0/m, #-128
--.*: 05905000 mov z0\.s, p0/m, #-128
--.*: 05905020 mov z0\.s, p0/m, #-127
--.*: 05905020 mov z0\.s, p0/m, #-127
--.*: 05905020 mov z0\.s, p0/m, #-127
--.*: 05905fe0 mov z0\.s, p0/m, #-1
--.*: 05905fe0 mov z0\.s, p0/m, #-1
--.*: 05905fe0 mov z0\.s, p0/m, #-1
--.*: 05906000 mov z0\.s, p0/m, #0, lsl #8
--.*: 05906000 mov z0\.s, p0/m, #0, lsl #8
--.*: 05906fe0 mov z0\.s, p0/m, #32512
--.*: 05906fe0 mov z0\.s, p0/m, #32512
--.*: 05906fe0 mov z0\.s, p0/m, #32512
--.*: 05906fe0 mov z0\.s, p0/m, #32512
--.*: 05907000 mov z0\.s, p0/m, #-32768
--.*: 05907000 mov z0\.s, p0/m, #-32768
--.*: 05907000 mov z0\.s, p0/m, #-32768
--.*: 05907000 mov z0\.s, p0/m, #-32768
--.*: 05907020 mov z0\.s, p0/m, #-32512
--.*: 05907020 mov z0\.s, p0/m, #-32512
--.*: 05907020 mov z0\.s, p0/m, #-32512
--.*: 05907020 mov z0\.s, p0/m, #-32512
--.*: 05907fe0 mov z0\.s, p0/m, #-256
--.*: 05907fe0 mov z0\.s, p0/m, #-256
--.*: 05907fe0 mov z0\.s, p0/m, #-256
--.*: 05907fe0 mov z0\.s, p0/m, #-256
--.*: 05d00000 mov z0\.d, p0/z, #0
--.*: 05d00000 mov z0\.d, p0/z, #0
--.*: 05d00000 mov z0\.d, p0/z, #0
--.*: 05d00001 mov z1\.d, p0/z, #0
--.*: 05d00001 mov z1\.d, p0/z, #0
--.*: 05d00001 mov z1\.d, p0/z, #0
--.*: 05d0001f mov z31\.d, p0/z, #0
--.*: 05d0001f mov z31\.d, p0/z, #0
--.*: 05d0001f mov z31\.d, p0/z, #0
--.*: 05d20000 mov z0\.d, p2/z, #0
--.*: 05d20000 mov z0\.d, p2/z, #0
--.*: 05d20000 mov z0\.d, p2/z, #0
--.*: 05df0000 mov z0\.d, p15/z, #0
--.*: 05df0000 mov z0\.d, p15/z, #0
--.*: 05df0000 mov z0\.d, p15/z, #0
--.*: 05d00fe0 mov z0\.d, p0/z, #127
--.*: 05d00fe0 mov z0\.d, p0/z, #127
--.*: 05d00fe0 mov z0\.d, p0/z, #127
--.*: 05d01000 mov z0\.d, p0/z, #-128
--.*: 05d01000 mov z0\.d, p0/z, #-128
--.*: 05d01000 mov z0\.d, p0/z, #-128
--.*: 05d01020 mov z0\.d, p0/z, #-127
--.*: 05d01020 mov z0\.d, p0/z, #-127
--.*: 05d01020 mov z0\.d, p0/z, #-127
--.*: 05d01fe0 mov z0\.d, p0/z, #-1
--.*: 05d01fe0 mov z0\.d, p0/z, #-1
--.*: 05d01fe0 mov z0\.d, p0/z, #-1
--.*: 05d02000 mov z0\.d, p0/z, #0, lsl #8
--.*: 05d02000 mov z0\.d, p0/z, #0, lsl #8
--.*: 05d02fe0 mov z0\.d, p0/z, #32512
--.*: 05d02fe0 mov z0\.d, p0/z, #32512
--.*: 05d02fe0 mov z0\.d, p0/z, #32512
--.*: 05d02fe0 mov z0\.d, p0/z, #32512
--.*: 05d03000 mov z0\.d, p0/z, #-32768
--.*: 05d03000 mov z0\.d, p0/z, #-32768
--.*: 05d03000 mov z0\.d, p0/z, #-32768
--.*: 05d03000 mov z0\.d, p0/z, #-32768
--.*: 05d03020 mov z0\.d, p0/z, #-32512
--.*: 05d03020 mov z0\.d, p0/z, #-32512
--.*: 05d03020 mov z0\.d, p0/z, #-32512
--.*: 05d03020 mov z0\.d, p0/z, #-32512
--.*: 05d03fe0 mov z0\.d, p0/z, #-256
--.*: 05d03fe0 mov z0\.d, p0/z, #-256
--.*: 05d03fe0 mov z0\.d, p0/z, #-256
--.*: 05d03fe0 mov z0\.d, p0/z, #-256
--.*: 05d04000 mov z0\.d, p0/m, #0
--.*: 05d04000 mov z0\.d, p0/m, #0
--.*: 05d04000 mov z0\.d, p0/m, #0
--.*: 05d04001 mov z1\.d, p0/m, #0
--.*: 05d04001 mov z1\.d, p0/m, #0
--.*: 05d04001 mov z1\.d, p0/m, #0
--.*: 05d0401f mov z31\.d, p0/m, #0
--.*: 05d0401f mov z31\.d, p0/m, #0
--.*: 05d0401f mov z31\.d, p0/m, #0
--.*: 05d24000 mov z0\.d, p2/m, #0
--.*: 05d24000 mov z0\.d, p2/m, #0
--.*: 05d24000 mov z0\.d, p2/m, #0
--.*: 05df4000 mov z0\.d, p15/m, #0
--.*: 05df4000 mov z0\.d, p15/m, #0
--.*: 05df4000 mov z0\.d, p15/m, #0
--.*: 05d04fe0 mov z0\.d, p0/m, #127
--.*: 05d04fe0 mov z0\.d, p0/m, #127
--.*: 05d04fe0 mov z0\.d, p0/m, #127
--.*: 05d05000 mov z0\.d, p0/m, #-128
--.*: 05d05000 mov z0\.d, p0/m, #-128
--.*: 05d05000 mov z0\.d, p0/m, #-128
--.*: 05d05020 mov z0\.d, p0/m, #-127
--.*: 05d05020 mov z0\.d, p0/m, #-127
--.*: 05d05020 mov z0\.d, p0/m, #-127
--.*: 05d05fe0 mov z0\.d, p0/m, #-1
--.*: 05d05fe0 mov z0\.d, p0/m, #-1
--.*: 05d05fe0 mov z0\.d, p0/m, #-1
--.*: 05d06000 mov z0\.d, p0/m, #0, lsl #8
--.*: 05d06000 mov z0\.d, p0/m, #0, lsl #8
--.*: 05d06fe0 mov z0\.d, p0/m, #32512
--.*: 05d06fe0 mov z0\.d, p0/m, #32512
--.*: 05d06fe0 mov z0\.d, p0/m, #32512
--.*: 05d06fe0 mov z0\.d, p0/m, #32512
--.*: 05d07000 mov z0\.d, p0/m, #-32768
--.*: 05d07000 mov z0\.d, p0/m, #-32768
--.*: 05d07000 mov z0\.d, p0/m, #-32768
--.*: 05d07000 mov z0\.d, p0/m, #-32768
--.*: 05d07020 mov z0\.d, p0/m, #-32512
--.*: 05d07020 mov z0\.d, p0/m, #-32512
--.*: 05d07020 mov z0\.d, p0/m, #-32512
--.*: 05d07020 mov z0\.d, p0/m, #-32512
--.*: 05d07fe0 mov z0\.d, p0/m, #-256
--.*: 05d07fe0 mov z0\.d, p0/m, #-256
--.*: 05d07fe0 mov z0\.d, p0/m, #-256
--.*: 05d07fe0 mov z0\.d, p0/m, #-256
--.*: 25a02000 ctermeq w0, w0
--.*: 25a02000 ctermeq w0, w0
--.*: 25a02020 ctermeq w1, w0
--.*: 25a02020 ctermeq w1, w0
--.*: 25a023e0 ctermeq wzr, w0
--.*: 25a023e0 ctermeq wzr, w0
--.*: 25a22000 ctermeq w0, w2
--.*: 25a22000 ctermeq w0, w2
--.*: 25bf2000 ctermeq w0, wzr
--.*: 25bf2000 ctermeq w0, wzr
--.*: 25e02000 ctermeq x0, x0
--.*: 25e02000 ctermeq x0, x0
--.*: 25e02020 ctermeq x1, x0
--.*: 25e02020 ctermeq x1, x0
--.*: 25e023e0 ctermeq xzr, x0
--.*: 25e023e0 ctermeq xzr, x0
--.*: 25e22000 ctermeq x0, x2
--.*: 25e22000 ctermeq x0, x2
--.*: 25ff2000 ctermeq x0, xzr
--.*: 25ff2000 ctermeq x0, xzr
--.*: 25a02010 ctermne w0, w0
--.*: 25a02010 ctermne w0, w0
--.*: 25a02030 ctermne w1, w0
--.*: 25a02030 ctermne w1, w0
--.*: 25a023f0 ctermne wzr, w0
--.*: 25a023f0 ctermne wzr, w0
--.*: 25a22010 ctermne w0, w2
--.*: 25a22010 ctermne w0, w2
--.*: 25bf2010 ctermne w0, wzr
--.*: 25bf2010 ctermne w0, wzr
--.*: 25e02010 ctermne x0, x0
--.*: 25e02010 ctermne x0, x0
--.*: 25e02030 ctermne x1, x0
--.*: 25e02030 ctermne x1, x0
--.*: 25e023f0 ctermne xzr, x0
--.*: 25e023f0 ctermne xzr, x0
--.*: 25e22010 ctermne x0, x2
--.*: 25e22010 ctermne x0, x2
--.*: 25ff2010 ctermne x0, xzr
--.*: 25ff2010 ctermne x0, xzr
--.*: 0430e400 decb x0, pow2
--.*: 0430e400 decb x0, pow2
--.*: 0430e400 decb x0, pow2
--.*: 0430e401 decb x1, pow2
--.*: 0430e401 decb x1, pow2
--.*: 0430e401 decb x1, pow2
--.*: 0430e41f decb xzr, pow2
--.*: 0430e41f decb xzr, pow2
--.*: 0430e41f decb xzr, pow2
--.*: 0430e420 decb x0, vl1
--.*: 0430e420 decb x0, vl1
--.*: 0430e420 decb x0, vl1
--.*: 0430e440 decb x0, vl2
--.*: 0430e440 decb x0, vl2
--.*: 0430e440 decb x0, vl2
--.*: 0430e460 decb x0, vl3
--.*: 0430e460 decb x0, vl3
--.*: 0430e460 decb x0, vl3
--.*: 0430e480 decb x0, vl4
--.*: 0430e480 decb x0, vl4
--.*: 0430e480 decb x0, vl4
--.*: 0430e4a0 decb x0, vl5
--.*: 0430e4a0 decb x0, vl5
--.*: 0430e4a0 decb x0, vl5
--.*: 0430e4c0 decb x0, vl6
--.*: 0430e4c0 decb x0, vl6
--.*: 0430e4c0 decb x0, vl6
--.*: 0430e4e0 decb x0, vl7
--.*: 0430e4e0 decb x0, vl7
--.*: 0430e4e0 decb x0, vl7
--.*: 0430e500 decb x0, vl8
--.*: 0430e500 decb x0, vl8
--.*: 0430e500 decb x0, vl8
--.*: 0430e520 decb x0, vl16
--.*: 0430e520 decb x0, vl16
--.*: 0430e520 decb x0, vl16
--.*: 0430e540 decb x0, vl32
--.*: 0430e540 decb x0, vl32
--.*: 0430e540 decb x0, vl32
--.*: 0430e560 decb x0, vl64
--.*: 0430e560 decb x0, vl64
--.*: 0430e560 decb x0, vl64
--.*: 0430e580 decb x0, vl128
--.*: 0430e580 decb x0, vl128
--.*: 0430e580 decb x0, vl128
--.*: 0430e5a0 decb x0, vl256
--.*: 0430e5a0 decb x0, vl256
--.*: 0430e5a0 decb x0, vl256
--.*: 0430e5c0 decb x0, #14
--.*: 0430e5c0 decb x0, #14
--.*: 0430e5c0 decb x0, #14
--.*: 0430e5e0 decb x0, #15
--.*: 0430e5e0 decb x0, #15
--.*: 0430e5e0 decb x0, #15
--.*: 0430e600 decb x0, #16
--.*: 0430e600 decb x0, #16
--.*: 0430e600 decb x0, #16
--.*: 0430e620 decb x0, #17
--.*: 0430e620 decb x0, #17
--.*: 0430e620 decb x0, #17
--.*: 0430e640 decb x0, #18
--.*: 0430e640 decb x0, #18
--.*: 0430e640 decb x0, #18
--.*: 0430e660 decb x0, #19
--.*: 0430e660 decb x0, #19
--.*: 0430e660 decb x0, #19
--.*: 0430e680 decb x0, #20
--.*: 0430e680 decb x0, #20
--.*: 0430e680 decb x0, #20
--.*: 0430e6a0 decb x0, #21
--.*: 0430e6a0 decb x0, #21
--.*: 0430e6a0 decb x0, #21
--.*: 0430e6c0 decb x0, #22
--.*: 0430e6c0 decb x0, #22
--.*: 0430e6c0 decb x0, #22
--.*: 0430e6e0 decb x0, #23
--.*: 0430e6e0 decb x0, #23
--.*: 0430e6e0 decb x0, #23
--.*: 0430e700 decb x0, #24
--.*: 0430e700 decb x0, #24
--.*: 0430e700 decb x0, #24
--.*: 0430e720 decb x0, #25
--.*: 0430e720 decb x0, #25
--.*: 0430e720 decb x0, #25
--.*: 0430e740 decb x0, #26
--.*: 0430e740 decb x0, #26
--.*: 0430e740 decb x0, #26
--.*: 0430e760 decb x0, #27
--.*: 0430e760 decb x0, #27
--.*: 0430e760 decb x0, #27
--.*: 0430e780 decb x0, #28
--.*: 0430e780 decb x0, #28
--.*: 0430e780 decb x0, #28
--.*: 0430e7a0 decb x0, mul4
--.*: 0430e7a0 decb x0, mul4
--.*: 0430e7a0 decb x0, mul4
--.*: 0430e7c0 decb x0, mul3
--.*: 0430e7c0 decb x0, mul3
--.*: 0430e7c0 decb x0, mul3
--.*: 0430e7e0 decb x0
--.*: 0430e7e0 decb x0
--.*: 0430e7e0 decb x0
--.*: 0430e7e0 decb x0
--.*: 0437e400 decb x0, pow2, mul #8
--.*: 0437e400 decb x0, pow2, mul #8
--.*: 0438e400 decb x0, pow2, mul #9
--.*: 0438e400 decb x0, pow2, mul #9
--.*: 0439e400 decb x0, pow2, mul #10
--.*: 0439e400 decb x0, pow2, mul #10
--.*: 043fe400 decb x0, pow2, mul #16
--.*: 043fe400 decb x0, pow2, mul #16
--.*: 04f0c400 decd z0\.d, pow2
--.*: 04f0c400 decd z0\.d, pow2
--.*: 04f0c400 decd z0\.d, pow2
--.*: 04f0c401 decd z1\.d, pow2
--.*: 04f0c401 decd z1\.d, pow2
--.*: 04f0c401 decd z1\.d, pow2
--.*: 04f0c41f decd z31\.d, pow2
--.*: 04f0c41f decd z31\.d, pow2
--.*: 04f0c41f decd z31\.d, pow2
--.*: 04f0c420 decd z0\.d, vl1
--.*: 04f0c420 decd z0\.d, vl1
--.*: 04f0c420 decd z0\.d, vl1
--.*: 04f0c440 decd z0\.d, vl2
--.*: 04f0c440 decd z0\.d, vl2
--.*: 04f0c440 decd z0\.d, vl2
--.*: 04f0c460 decd z0\.d, vl3
--.*: 04f0c460 decd z0\.d, vl3
--.*: 04f0c460 decd z0\.d, vl3
--.*: 04f0c480 decd z0\.d, vl4
--.*: 04f0c480 decd z0\.d, vl4
--.*: 04f0c480 decd z0\.d, vl4
--.*: 04f0c4a0 decd z0\.d, vl5
--.*: 04f0c4a0 decd z0\.d, vl5
--.*: 04f0c4a0 decd z0\.d, vl5
--.*: 04f0c4c0 decd z0\.d, vl6
--.*: 04f0c4c0 decd z0\.d, vl6
--.*: 04f0c4c0 decd z0\.d, vl6
--.*: 04f0c4e0 decd z0\.d, vl7
--.*: 04f0c4e0 decd z0\.d, vl7
--.*: 04f0c4e0 decd z0\.d, vl7
--.*: 04f0c500 decd z0\.d, vl8
--.*: 04f0c500 decd z0\.d, vl8
--.*: 04f0c500 decd z0\.d, vl8
--.*: 04f0c520 decd z0\.d, vl16
--.*: 04f0c520 decd z0\.d, vl16
--.*: 04f0c520 decd z0\.d, vl16
--.*: 04f0c540 decd z0\.d, vl32
--.*: 04f0c540 decd z0\.d, vl32
--.*: 04f0c540 decd z0\.d, vl32
--.*: 04f0c560 decd z0\.d, vl64
--.*: 04f0c560 decd z0\.d, vl64
--.*: 04f0c560 decd z0\.d, vl64
--.*: 04f0c580 decd z0\.d, vl128
--.*: 04f0c580 decd z0\.d, vl128
--.*: 04f0c580 decd z0\.d, vl128
--.*: 04f0c5a0 decd z0\.d, vl256
--.*: 04f0c5a0 decd z0\.d, vl256
--.*: 04f0c5a0 decd z0\.d, vl256
--.*: 04f0c5c0 decd z0\.d, #14
--.*: 04f0c5c0 decd z0\.d, #14
--.*: 04f0c5c0 decd z0\.d, #14
--.*: 04f0c5e0 decd z0\.d, #15
--.*: 04f0c5e0 decd z0\.d, #15
--.*: 04f0c5e0 decd z0\.d, #15
--.*: 04f0c600 decd z0\.d, #16
--.*: 04f0c600 decd z0\.d, #16
--.*: 04f0c600 decd z0\.d, #16
--.*: 04f0c620 decd z0\.d, #17
--.*: 04f0c620 decd z0\.d, #17
--.*: 04f0c620 decd z0\.d, #17
--.*: 04f0c640 decd z0\.d, #18
--.*: 04f0c640 decd z0\.d, #18
--.*: 04f0c640 decd z0\.d, #18
--.*: 04f0c660 decd z0\.d, #19
--.*: 04f0c660 decd z0\.d, #19
--.*: 04f0c660 decd z0\.d, #19
--.*: 04f0c680 decd z0\.d, #20
--.*: 04f0c680 decd z0\.d, #20
--.*: 04f0c680 decd z0\.d, #20
--.*: 04f0c6a0 decd z0\.d, #21
--.*: 04f0c6a0 decd z0\.d, #21
--.*: 04f0c6a0 decd z0\.d, #21
--.*: 04f0c6c0 decd z0\.d, #22
--.*: 04f0c6c0 decd z0\.d, #22
--.*: 04f0c6c0 decd z0\.d, #22
--.*: 04f0c6e0 decd z0\.d, #23
--.*: 04f0c6e0 decd z0\.d, #23
--.*: 04f0c6e0 decd z0\.d, #23
--.*: 04f0c700 decd z0\.d, #24
--.*: 04f0c700 decd z0\.d, #24
--.*: 04f0c700 decd z0\.d, #24
--.*: 04f0c720 decd z0\.d, #25
--.*: 04f0c720 decd z0\.d, #25
--.*: 04f0c720 decd z0\.d, #25
--.*: 04f0c740 decd z0\.d, #26
--.*: 04f0c740 decd z0\.d, #26
--.*: 04f0c740 decd z0\.d, #26
--.*: 04f0c760 decd z0\.d, #27
--.*: 04f0c760 decd z0\.d, #27
--.*: 04f0c760 decd z0\.d, #27
--.*: 04f0c780 decd z0\.d, #28
--.*: 04f0c780 decd z0\.d, #28
--.*: 04f0c780 decd z0\.d, #28
--.*: 04f0c7a0 decd z0\.d, mul4
--.*: 04f0c7a0 decd z0\.d, mul4
--.*: 04f0c7a0 decd z0\.d, mul4
--.*: 04f0c7c0 decd z0\.d, mul3
--.*: 04f0c7c0 decd z0\.d, mul3
--.*: 04f0c7c0 decd z0\.d, mul3
--.*: 04f0c7e0 decd z0\.d
--.*: 04f0c7e0 decd z0\.d
--.*: 04f0c7e0 decd z0\.d
--.*: 04f0c7e0 decd z0\.d
--.*: 04f7c400 decd z0\.d, pow2, mul #8
--.*: 04f7c400 decd z0\.d, pow2, mul #8
--.*: 04f8c400 decd z0\.d, pow2, mul #9
--.*: 04f8c400 decd z0\.d, pow2, mul #9
--.*: 04f9c400 decd z0\.d, pow2, mul #10
--.*: 04f9c400 decd z0\.d, pow2, mul #10
--.*: 04ffc400 decd z0\.d, pow2, mul #16
--.*: 04ffc400 decd z0\.d, pow2, mul #16
--.*: 04f0e400 decd x0, pow2
--.*: 04f0e400 decd x0, pow2
--.*: 04f0e400 decd x0, pow2
--.*: 04f0e401 decd x1, pow2
--.*: 04f0e401 decd x1, pow2
--.*: 04f0e401 decd x1, pow2
--.*: 04f0e41f decd xzr, pow2
--.*: 04f0e41f decd xzr, pow2
--.*: 04f0e41f decd xzr, pow2
--.*: 04f0e420 decd x0, vl1
--.*: 04f0e420 decd x0, vl1
--.*: 04f0e420 decd x0, vl1
--.*: 04f0e440 decd x0, vl2
--.*: 04f0e440 decd x0, vl2
--.*: 04f0e440 decd x0, vl2
--.*: 04f0e460 decd x0, vl3
--.*: 04f0e460 decd x0, vl3
--.*: 04f0e460 decd x0, vl3
--.*: 04f0e480 decd x0, vl4
--.*: 04f0e480 decd x0, vl4
--.*: 04f0e480 decd x0, vl4
--.*: 04f0e4a0 decd x0, vl5
--.*: 04f0e4a0 decd x0, vl5
--.*: 04f0e4a0 decd x0, vl5
--.*: 04f0e4c0 decd x0, vl6
--.*: 04f0e4c0 decd x0, vl6
--.*: 04f0e4c0 decd x0, vl6
--.*: 04f0e4e0 decd x0, vl7
--.*: 04f0e4e0 decd x0, vl7
--.*: 04f0e4e0 decd x0, vl7
--.*: 04f0e500 decd x0, vl8
--.*: 04f0e500 decd x0, vl8
--.*: 04f0e500 decd x0, vl8
--.*: 04f0e520 decd x0, vl16
--.*: 04f0e520 decd x0, vl16
--.*: 04f0e520 decd x0, vl16
--.*: 04f0e540 decd x0, vl32
--.*: 04f0e540 decd x0, vl32
--.*: 04f0e540 decd x0, vl32
--.*: 04f0e560 decd x0, vl64
--.*: 04f0e560 decd x0, vl64
--.*: 04f0e560 decd x0, vl64
--.*: 04f0e580 decd x0, vl128
--.*: 04f0e580 decd x0, vl128
--.*: 04f0e580 decd x0, vl128
--.*: 04f0e5a0 decd x0, vl256
--.*: 04f0e5a0 decd x0, vl256
--.*: 04f0e5a0 decd x0, vl256
--.*: 04f0e5c0 decd x0, #14
--.*: 04f0e5c0 decd x0, #14
--.*: 04f0e5c0 decd x0, #14
--.*: 04f0e5e0 decd x0, #15
--.*: 04f0e5e0 decd x0, #15
--.*: 04f0e5e0 decd x0, #15
--.*: 04f0e600 decd x0, #16
--.*: 04f0e600 decd x0, #16
--.*: 04f0e600 decd x0, #16
--.*: 04f0e620 decd x0, #17
--.*: 04f0e620 decd x0, #17
--.*: 04f0e620 decd x0, #17
--.*: 04f0e640 decd x0, #18
--.*: 04f0e640 decd x0, #18
--.*: 04f0e640 decd x0, #18
--.*: 04f0e660 decd x0, #19
--.*: 04f0e660 decd x0, #19
--.*: 04f0e660 decd x0, #19
--.*: 04f0e680 decd x0, #20
--.*: 04f0e680 decd x0, #20
--.*: 04f0e680 decd x0, #20
--.*: 04f0e6a0 decd x0, #21
--.*: 04f0e6a0 decd x0, #21
--.*: 04f0e6a0 decd x0, #21
--.*: 04f0e6c0 decd x0, #22
--.*: 04f0e6c0 decd x0, #22
--.*: 04f0e6c0 decd x0, #22
--.*: 04f0e6e0 decd x0, #23
--.*: 04f0e6e0 decd x0, #23
--.*: 04f0e6e0 decd x0, #23
--.*: 04f0e700 decd x0, #24
--.*: 04f0e700 decd x0, #24
--.*: 04f0e700 decd x0, #24
--.*: 04f0e720 decd x0, #25
--.*: 04f0e720 decd x0, #25
--.*: 04f0e720 decd x0, #25
--.*: 04f0e740 decd x0, #26
--.*: 04f0e740 decd x0, #26
--.*: 04f0e740 decd x0, #26
--.*: 04f0e760 decd x0, #27
--.*: 04f0e760 decd x0, #27
--.*: 04f0e760 decd x0, #27
--.*: 04f0e780 decd x0, #28
--.*: 04f0e780 decd x0, #28
--.*: 04f0e780 decd x0, #28
--.*: 04f0e7a0 decd x0, mul4
--.*: 04f0e7a0 decd x0, mul4
--.*: 04f0e7a0 decd x0, mul4
--.*: 04f0e7c0 decd x0, mul3
--.*: 04f0e7c0 decd x0, mul3
--.*: 04f0e7c0 decd x0, mul3
--.*: 04f0e7e0 decd x0
--.*: 04f0e7e0 decd x0
--.*: 04f0e7e0 decd x0
--.*: 04f0e7e0 decd x0
--.*: 04f7e400 decd x0, pow2, mul #8
--.*: 04f7e400 decd x0, pow2, mul #8
--.*: 04f8e400 decd x0, pow2, mul #9
--.*: 04f8e400 decd x0, pow2, mul #9
--.*: 04f9e400 decd x0, pow2, mul #10
--.*: 04f9e400 decd x0, pow2, mul #10
--.*: 04ffe400 decd x0, pow2, mul #16
--.*: 04ffe400 decd x0, pow2, mul #16
--.*: 0470c400 dech z0\.h, pow2
--.*: 0470c400 dech z0\.h, pow2
--.*: 0470c400 dech z0\.h, pow2
--.*: 0470c401 dech z1\.h, pow2
--.*: 0470c401 dech z1\.h, pow2
--.*: 0470c401 dech z1\.h, pow2
--.*: 0470c41f dech z31\.h, pow2
--.*: 0470c41f dech z31\.h, pow2
--.*: 0470c41f dech z31\.h, pow2
--.*: 0470c420 dech z0\.h, vl1
--.*: 0470c420 dech z0\.h, vl1
--.*: 0470c420 dech z0\.h, vl1
--.*: 0470c440 dech z0\.h, vl2
--.*: 0470c440 dech z0\.h, vl2
--.*: 0470c440 dech z0\.h, vl2
--.*: 0470c460 dech z0\.h, vl3
--.*: 0470c460 dech z0\.h, vl3
--.*: 0470c460 dech z0\.h, vl3
--.*: 0470c480 dech z0\.h, vl4
--.*: 0470c480 dech z0\.h, vl4
--.*: 0470c480 dech z0\.h, vl4
--.*: 0470c4a0 dech z0\.h, vl5
--.*: 0470c4a0 dech z0\.h, vl5
--.*: 0470c4a0 dech z0\.h, vl5
--.*: 0470c4c0 dech z0\.h, vl6
--.*: 0470c4c0 dech z0\.h, vl6
--.*: 0470c4c0 dech z0\.h, vl6
--.*: 0470c4e0 dech z0\.h, vl7
--.*: 0470c4e0 dech z0\.h, vl7
--.*: 0470c4e0 dech z0\.h, vl7
--.*: 0470c500 dech z0\.h, vl8
--.*: 0470c500 dech z0\.h, vl8
--.*: 0470c500 dech z0\.h, vl8
--.*: 0470c520 dech z0\.h, vl16
--.*: 0470c520 dech z0\.h, vl16
--.*: 0470c520 dech z0\.h, vl16
--.*: 0470c540 dech z0\.h, vl32
--.*: 0470c540 dech z0\.h, vl32
--.*: 0470c540 dech z0\.h, vl32
--.*: 0470c560 dech z0\.h, vl64
--.*: 0470c560 dech z0\.h, vl64
--.*: 0470c560 dech z0\.h, vl64
--.*: 0470c580 dech z0\.h, vl128
--.*: 0470c580 dech z0\.h, vl128
--.*: 0470c580 dech z0\.h, vl128
--.*: 0470c5a0 dech z0\.h, vl256
--.*: 0470c5a0 dech z0\.h, vl256
--.*: 0470c5a0 dech z0\.h, vl256
--.*: 0470c5c0 dech z0\.h, #14
--.*: 0470c5c0 dech z0\.h, #14
--.*: 0470c5c0 dech z0\.h, #14
--.*: 0470c5e0 dech z0\.h, #15
--.*: 0470c5e0 dech z0\.h, #15
--.*: 0470c5e0 dech z0\.h, #15
--.*: 0470c600 dech z0\.h, #16
--.*: 0470c600 dech z0\.h, #16
--.*: 0470c600 dech z0\.h, #16
--.*: 0470c620 dech z0\.h, #17
--.*: 0470c620 dech z0\.h, #17
--.*: 0470c620 dech z0\.h, #17
--.*: 0470c640 dech z0\.h, #18
--.*: 0470c640 dech z0\.h, #18
--.*: 0470c640 dech z0\.h, #18
--.*: 0470c660 dech z0\.h, #19
--.*: 0470c660 dech z0\.h, #19
--.*: 0470c660 dech z0\.h, #19
--.*: 0470c680 dech z0\.h, #20
--.*: 0470c680 dech z0\.h, #20
--.*: 0470c680 dech z0\.h, #20
--.*: 0470c6a0 dech z0\.h, #21
--.*: 0470c6a0 dech z0\.h, #21
--.*: 0470c6a0 dech z0\.h, #21
--.*: 0470c6c0 dech z0\.h, #22
--.*: 0470c6c0 dech z0\.h, #22
--.*: 0470c6c0 dech z0\.h, #22
--.*: 0470c6e0 dech z0\.h, #23
--.*: 0470c6e0 dech z0\.h, #23
--.*: 0470c6e0 dech z0\.h, #23
--.*: 0470c700 dech z0\.h, #24
--.*: 0470c700 dech z0\.h, #24
--.*: 0470c700 dech z0\.h, #24
--.*: 0470c720 dech z0\.h, #25
--.*: 0470c720 dech z0\.h, #25
--.*: 0470c720 dech z0\.h, #25
--.*: 0470c740 dech z0\.h, #26
--.*: 0470c740 dech z0\.h, #26
--.*: 0470c740 dech z0\.h, #26
--.*: 0470c760 dech z0\.h, #27
--.*: 0470c760 dech z0\.h, #27
--.*: 0470c760 dech z0\.h, #27
--.*: 0470c780 dech z0\.h, #28
--.*: 0470c780 dech z0\.h, #28
--.*: 0470c780 dech z0\.h, #28
--.*: 0470c7a0 dech z0\.h, mul4
--.*: 0470c7a0 dech z0\.h, mul4
--.*: 0470c7a0 dech z0\.h, mul4
--.*: 0470c7c0 dech z0\.h, mul3
--.*: 0470c7c0 dech z0\.h, mul3
--.*: 0470c7c0 dech z0\.h, mul3
--.*: 0470c7e0 dech z0\.h
--.*: 0470c7e0 dech z0\.h
--.*: 0470c7e0 dech z0\.h
--.*: 0470c7e0 dech z0\.h
--.*: 0477c400 dech z0\.h, pow2, mul #8
--.*: 0477c400 dech z0\.h, pow2, mul #8
--.*: 0478c400 dech z0\.h, pow2, mul #9
--.*: 0478c400 dech z0\.h, pow2, mul #9
--.*: 0479c400 dech z0\.h, pow2, mul #10
--.*: 0479c400 dech z0\.h, pow2, mul #10
--.*: 047fc400 dech z0\.h, pow2, mul #16
--.*: 047fc400 dech z0\.h, pow2, mul #16
--.*: 0470e400 dech x0, pow2
--.*: 0470e400 dech x0, pow2
--.*: 0470e400 dech x0, pow2
--.*: 0470e401 dech x1, pow2
--.*: 0470e401 dech x1, pow2
--.*: 0470e401 dech x1, pow2
--.*: 0470e41f dech xzr, pow2
--.*: 0470e41f dech xzr, pow2
--.*: 0470e41f dech xzr, pow2
--.*: 0470e420 dech x0, vl1
--.*: 0470e420 dech x0, vl1
--.*: 0470e420 dech x0, vl1
--.*: 0470e440 dech x0, vl2
--.*: 0470e440 dech x0, vl2
--.*: 0470e440 dech x0, vl2
--.*: 0470e460 dech x0, vl3
--.*: 0470e460 dech x0, vl3
--.*: 0470e460 dech x0, vl3
--.*: 0470e480 dech x0, vl4
--.*: 0470e480 dech x0, vl4
--.*: 0470e480 dech x0, vl4
--.*: 0470e4a0 dech x0, vl5
--.*: 0470e4a0 dech x0, vl5
--.*: 0470e4a0 dech x0, vl5
--.*: 0470e4c0 dech x0, vl6
--.*: 0470e4c0 dech x0, vl6
--.*: 0470e4c0 dech x0, vl6
--.*: 0470e4e0 dech x0, vl7
--.*: 0470e4e0 dech x0, vl7
--.*: 0470e4e0 dech x0, vl7
--.*: 0470e500 dech x0, vl8
--.*: 0470e500 dech x0, vl8
--.*: 0470e500 dech x0, vl8
--.*: 0470e520 dech x0, vl16
--.*: 0470e520 dech x0, vl16
--.*: 0470e520 dech x0, vl16
--.*: 0470e540 dech x0, vl32
--.*: 0470e540 dech x0, vl32
--.*: 0470e540 dech x0, vl32
--.*: 0470e560 dech x0, vl64
--.*: 0470e560 dech x0, vl64
--.*: 0470e560 dech x0, vl64
--.*: 0470e580 dech x0, vl128
--.*: 0470e580 dech x0, vl128
--.*: 0470e580 dech x0, vl128
--.*: 0470e5a0 dech x0, vl256
--.*: 0470e5a0 dech x0, vl256
--.*: 0470e5a0 dech x0, vl256
--.*: 0470e5c0 dech x0, #14
--.*: 0470e5c0 dech x0, #14
--.*: 0470e5c0 dech x0, #14
--.*: 0470e5e0 dech x0, #15
--.*: 0470e5e0 dech x0, #15
--.*: 0470e5e0 dech x0, #15
--.*: 0470e600 dech x0, #16
--.*: 0470e600 dech x0, #16
--.*: 0470e600 dech x0, #16
--.*: 0470e620 dech x0, #17
--.*: 0470e620 dech x0, #17
--.*: 0470e620 dech x0, #17
--.*: 0470e640 dech x0, #18
--.*: 0470e640 dech x0, #18
--.*: 0470e640 dech x0, #18
--.*: 0470e660 dech x0, #19
--.*: 0470e660 dech x0, #19
--.*: 0470e660 dech x0, #19
--.*: 0470e680 dech x0, #20
--.*: 0470e680 dech x0, #20
--.*: 0470e680 dech x0, #20
--.*: 0470e6a0 dech x0, #21
--.*: 0470e6a0 dech x0, #21
--.*: 0470e6a0 dech x0, #21
--.*: 0470e6c0 dech x0, #22
--.*: 0470e6c0 dech x0, #22
--.*: 0470e6c0 dech x0, #22
--.*: 0470e6e0 dech x0, #23
--.*: 0470e6e0 dech x0, #23
--.*: 0470e6e0 dech x0, #23
--.*: 0470e700 dech x0, #24
--.*: 0470e700 dech x0, #24
--.*: 0470e700 dech x0, #24
--.*: 0470e720 dech x0, #25
--.*: 0470e720 dech x0, #25
--.*: 0470e720 dech x0, #25
--.*: 0470e740 dech x0, #26
--.*: 0470e740 dech x0, #26
--.*: 0470e740 dech x0, #26
--.*: 0470e760 dech x0, #27
--.*: 0470e760 dech x0, #27
--.*: 0470e760 dech x0, #27
--.*: 0470e780 dech x0, #28
--.*: 0470e780 dech x0, #28
--.*: 0470e780 dech x0, #28
--.*: 0470e7a0 dech x0, mul4
--.*: 0470e7a0 dech x0, mul4
--.*: 0470e7a0 dech x0, mul4
--.*: 0470e7c0 dech x0, mul3
--.*: 0470e7c0 dech x0, mul3
--.*: 0470e7c0 dech x0, mul3
--.*: 0470e7e0 dech x0
--.*: 0470e7e0 dech x0
--.*: 0470e7e0 dech x0
--.*: 0470e7e0 dech x0
--.*: 0477e400 dech x0, pow2, mul #8
--.*: 0477e400 dech x0, pow2, mul #8
--.*: 0478e400 dech x0, pow2, mul #9
--.*: 0478e400 dech x0, pow2, mul #9
--.*: 0479e400 dech x0, pow2, mul #10
--.*: 0479e400 dech x0, pow2, mul #10
--.*: 047fe400 dech x0, pow2, mul #16
--.*: 047fe400 dech x0, pow2, mul #16
--.*: 256d8000 decp z0\.h, p0
--.*: 256d8000 decp z0\.h, p0
--.*: 256d8001 decp z1\.h, p0
--.*: 256d8001 decp z1\.h, p0
--.*: 256d801f decp z31\.h, p0
--.*: 256d801f decp z31\.h, p0
--.*: 256d8040 decp z0\.h, p2
--.*: 256d8040 decp z0\.h, p2
--.*: 256d81e0 decp z0\.h, p15
--.*: 256d81e0 decp z0\.h, p15
--.*: 25ad8000 decp z0\.s, p0
--.*: 25ad8000 decp z0\.s, p0
--.*: 25ad8001 decp z1\.s, p0
--.*: 25ad8001 decp z1\.s, p0
--.*: 25ad801f decp z31\.s, p0
--.*: 25ad801f decp z31\.s, p0
--.*: 25ad8040 decp z0\.s, p2
--.*: 25ad8040 decp z0\.s, p2
--.*: 25ad81e0 decp z0\.s, p15
--.*: 25ad81e0 decp z0\.s, p15
--.*: 25ed8000 decp z0\.d, p0
--.*: 25ed8000 decp z0\.d, p0
--.*: 25ed8001 decp z1\.d, p0
--.*: 25ed8001 decp z1\.d, p0
--.*: 25ed801f decp z31\.d, p0
--.*: 25ed801f decp z31\.d, p0
--.*: 25ed8040 decp z0\.d, p2
--.*: 25ed8040 decp z0\.d, p2
--.*: 25ed81e0 decp z0\.d, p15
--.*: 25ed81e0 decp z0\.d, p15
--.*: 252d8800 decp x0, p0\.b
--.*: 252d8800 decp x0, p0\.b
--.*: 252d8801 decp x1, p0\.b
--.*: 252d8801 decp x1, p0\.b
--.*: 252d881f decp xzr, p0\.b
--.*: 252d881f decp xzr, p0\.b
--.*: 252d8840 decp x0, p2\.b
--.*: 252d8840 decp x0, p2\.b
--.*: 252d89e0 decp x0, p15\.b
--.*: 252d89e0 decp x0, p15\.b
--.*: 256d8800 decp x0, p0\.h
--.*: 256d8800 decp x0, p0\.h
--.*: 256d8801 decp x1, p0\.h
--.*: 256d8801 decp x1, p0\.h
--.*: 256d881f decp xzr, p0\.h
--.*: 256d881f decp xzr, p0\.h
--.*: 256d8840 decp x0, p2\.h
--.*: 256d8840 decp x0, p2\.h
--.*: 256d89e0 decp x0, p15\.h
--.*: 256d89e0 decp x0, p15\.h
--.*: 25ad8800 decp x0, p0\.s
--.*: 25ad8800 decp x0, p0\.s
--.*: 25ad8801 decp x1, p0\.s
--.*: 25ad8801 decp x1, p0\.s
--.*: 25ad881f decp xzr, p0\.s
--.*: 25ad881f decp xzr, p0\.s
--.*: 25ad8840 decp x0, p2\.s
--.*: 25ad8840 decp x0, p2\.s
--.*: 25ad89e0 decp x0, p15\.s
--.*: 25ad89e0 decp x0, p15\.s
--.*: 25ed8800 decp x0, p0\.d
--.*: 25ed8800 decp x0, p0\.d
--.*: 25ed8801 decp x1, p0\.d
--.*: 25ed8801 decp x1, p0\.d
--.*: 25ed881f decp xzr, p0\.d
--.*: 25ed881f decp xzr, p0\.d
--.*: 25ed8840 decp x0, p2\.d
--.*: 25ed8840 decp x0, p2\.d
--.*: 25ed89e0 decp x0, p15\.d
--.*: 25ed89e0 decp x0, p15\.d
--.*: 04b0c400 decw z0\.s, pow2
--.*: 04b0c400 decw z0\.s, pow2
--.*: 04b0c400 decw z0\.s, pow2
--.*: 04b0c401 decw z1\.s, pow2
--.*: 04b0c401 decw z1\.s, pow2
--.*: 04b0c401 decw z1\.s, pow2
--.*: 04b0c41f decw z31\.s, pow2
--.*: 04b0c41f decw z31\.s, pow2
--.*: 04b0c41f decw z31\.s, pow2
--.*: 04b0c420 decw z0\.s, vl1
--.*: 04b0c420 decw z0\.s, vl1
--.*: 04b0c420 decw z0\.s, vl1
--.*: 04b0c440 decw z0\.s, vl2
--.*: 04b0c440 decw z0\.s, vl2
--.*: 04b0c440 decw z0\.s, vl2
--.*: 04b0c460 decw z0\.s, vl3
--.*: 04b0c460 decw z0\.s, vl3
--.*: 04b0c460 decw z0\.s, vl3
--.*: 04b0c480 decw z0\.s, vl4
--.*: 04b0c480 decw z0\.s, vl4
--.*: 04b0c480 decw z0\.s, vl4
--.*: 04b0c4a0 decw z0\.s, vl5
--.*: 04b0c4a0 decw z0\.s, vl5
--.*: 04b0c4a0 decw z0\.s, vl5
--.*: 04b0c4c0 decw z0\.s, vl6
--.*: 04b0c4c0 decw z0\.s, vl6
--.*: 04b0c4c0 decw z0\.s, vl6
--.*: 04b0c4e0 decw z0\.s, vl7
--.*: 04b0c4e0 decw z0\.s, vl7
--.*: 04b0c4e0 decw z0\.s, vl7
--.*: 04b0c500 decw z0\.s, vl8
--.*: 04b0c500 decw z0\.s, vl8
--.*: 04b0c500 decw z0\.s, vl8
--.*: 04b0c520 decw z0\.s, vl16
--.*: 04b0c520 decw z0\.s, vl16
--.*: 04b0c520 decw z0\.s, vl16
--.*: 04b0c540 decw z0\.s, vl32
--.*: 04b0c540 decw z0\.s, vl32
--.*: 04b0c540 decw z0\.s, vl32
--.*: 04b0c560 decw z0\.s, vl64
--.*: 04b0c560 decw z0\.s, vl64
--.*: 04b0c560 decw z0\.s, vl64
--.*: 04b0c580 decw z0\.s, vl128
--.*: 04b0c580 decw z0\.s, vl128
--.*: 04b0c580 decw z0\.s, vl128
--.*: 04b0c5a0 decw z0\.s, vl256
--.*: 04b0c5a0 decw z0\.s, vl256
--.*: 04b0c5a0 decw z0\.s, vl256
--.*: 04b0c5c0 decw z0\.s, #14
--.*: 04b0c5c0 decw z0\.s, #14
--.*: 04b0c5c0 decw z0\.s, #14
--.*: 04b0c5e0 decw z0\.s, #15
--.*: 04b0c5e0 decw z0\.s, #15
--.*: 04b0c5e0 decw z0\.s, #15
--.*: 04b0c600 decw z0\.s, #16
--.*: 04b0c600 decw z0\.s, #16
--.*: 04b0c600 decw z0\.s, #16
--.*: 04b0c620 decw z0\.s, #17
--.*: 04b0c620 decw z0\.s, #17
--.*: 04b0c620 decw z0\.s, #17
--.*: 04b0c640 decw z0\.s, #18
--.*: 04b0c640 decw z0\.s, #18
--.*: 04b0c640 decw z0\.s, #18
--.*: 04b0c660 decw z0\.s, #19
--.*: 04b0c660 decw z0\.s, #19
--.*: 04b0c660 decw z0\.s, #19
--.*: 04b0c680 decw z0\.s, #20
--.*: 04b0c680 decw z0\.s, #20
--.*: 04b0c680 decw z0\.s, #20
--.*: 04b0c6a0 decw z0\.s, #21
--.*: 04b0c6a0 decw z0\.s, #21
--.*: 04b0c6a0 decw z0\.s, #21
--.*: 04b0c6c0 decw z0\.s, #22
--.*: 04b0c6c0 decw z0\.s, #22
--.*: 04b0c6c0 decw z0\.s, #22
--.*: 04b0c6e0 decw z0\.s, #23
--.*: 04b0c6e0 decw z0\.s, #23
--.*: 04b0c6e0 decw z0\.s, #23
--.*: 04b0c700 decw z0\.s, #24
--.*: 04b0c700 decw z0\.s, #24
--.*: 04b0c700 decw z0\.s, #24
--.*: 04b0c720 decw z0\.s, #25
--.*: 04b0c720 decw z0\.s, #25
--.*: 04b0c720 decw z0\.s, #25
--.*: 04b0c740 decw z0\.s, #26
--.*: 04b0c740 decw z0\.s, #26
--.*: 04b0c740 decw z0\.s, #26
--.*: 04b0c760 decw z0\.s, #27
--.*: 04b0c760 decw z0\.s, #27
--.*: 04b0c760 decw z0\.s, #27
--.*: 04b0c780 decw z0\.s, #28
--.*: 04b0c780 decw z0\.s, #28
--.*: 04b0c780 decw z0\.s, #28
--.*: 04b0c7a0 decw z0\.s, mul4
--.*: 04b0c7a0 decw z0\.s, mul4
--.*: 04b0c7a0 decw z0\.s, mul4
--.*: 04b0c7c0 decw z0\.s, mul3
--.*: 04b0c7c0 decw z0\.s, mul3
--.*: 04b0c7c0 decw z0\.s, mul3
--.*: 04b0c7e0 decw z0\.s
--.*: 04b0c7e0 decw z0\.s
--.*: 04b0c7e0 decw z0\.s
--.*: 04b0c7e0 decw z0\.s
--.*: 04b7c400 decw z0\.s, pow2, mul #8
--.*: 04b7c400 decw z0\.s, pow2, mul #8
--.*: 04b8c400 decw z0\.s, pow2, mul #9
--.*: 04b8c400 decw z0\.s, pow2, mul #9
--.*: 04b9c400 decw z0\.s, pow2, mul #10
--.*: 04b9c400 decw z0\.s, pow2, mul #10
--.*: 04bfc400 decw z0\.s, pow2, mul #16
--.*: 04bfc400 decw z0\.s, pow2, mul #16
--.*: 04b0e400 decw x0, pow2
--.*: 04b0e400 decw x0, pow2
--.*: 04b0e400 decw x0, pow2
--.*: 04b0e401 decw x1, pow2
--.*: 04b0e401 decw x1, pow2
--.*: 04b0e401 decw x1, pow2
--.*: 04b0e41f decw xzr, pow2
--.*: 04b0e41f decw xzr, pow2
--.*: 04b0e41f decw xzr, pow2
--.*: 04b0e420 decw x0, vl1
--.*: 04b0e420 decw x0, vl1
--.*: 04b0e420 decw x0, vl1
--.*: 04b0e440 decw x0, vl2
--.*: 04b0e440 decw x0, vl2
--.*: 04b0e440 decw x0, vl2
--.*: 04b0e460 decw x0, vl3
--.*: 04b0e460 decw x0, vl3
--.*: 04b0e460 decw x0, vl3
--.*: 04b0e480 decw x0, vl4
--.*: 04b0e480 decw x0, vl4
--.*: 04b0e480 decw x0, vl4
--.*: 04b0e4a0 decw x0, vl5
--.*: 04b0e4a0 decw x0, vl5
--.*: 04b0e4a0 decw x0, vl5
--.*: 04b0e4c0 decw x0, vl6
--.*: 04b0e4c0 decw x0, vl6
--.*: 04b0e4c0 decw x0, vl6
--.*: 04b0e4e0 decw x0, vl7
--.*: 04b0e4e0 decw x0, vl7
--.*: 04b0e4e0 decw x0, vl7
--.*: 04b0e500 decw x0, vl8
--.*: 04b0e500 decw x0, vl8
--.*: 04b0e500 decw x0, vl8
--.*: 04b0e520 decw x0, vl16
--.*: 04b0e520 decw x0, vl16
--.*: 04b0e520 decw x0, vl16
--.*: 04b0e540 decw x0, vl32
--.*: 04b0e540 decw x0, vl32
--.*: 04b0e540 decw x0, vl32
--.*: 04b0e560 decw x0, vl64
--.*: 04b0e560 decw x0, vl64
--.*: 04b0e560 decw x0, vl64
--.*: 04b0e580 decw x0, vl128
--.*: 04b0e580 decw x0, vl128
--.*: 04b0e580 decw x0, vl128
--.*: 04b0e5a0 decw x0, vl256
--.*: 04b0e5a0 decw x0, vl256
--.*: 04b0e5a0 decw x0, vl256
--.*: 04b0e5c0 decw x0, #14
--.*: 04b0e5c0 decw x0, #14
--.*: 04b0e5c0 decw x0, #14
--.*: 04b0e5e0 decw x0, #15
--.*: 04b0e5e0 decw x0, #15
--.*: 04b0e5e0 decw x0, #15
--.*: 04b0e600 decw x0, #16
--.*: 04b0e600 decw x0, #16
--.*: 04b0e600 decw x0, #16
--.*: 04b0e620 decw x0, #17
--.*: 04b0e620 decw x0, #17
--.*: 04b0e620 decw x0, #17
--.*: 04b0e640 decw x0, #18
--.*: 04b0e640 decw x0, #18
--.*: 04b0e640 decw x0, #18
--.*: 04b0e660 decw x0, #19
--.*: 04b0e660 decw x0, #19
--.*: 04b0e660 decw x0, #19
--.*: 04b0e680 decw x0, #20
--.*: 04b0e680 decw x0, #20
--.*: 04b0e680 decw x0, #20
--.*: 04b0e6a0 decw x0, #21
--.*: 04b0e6a0 decw x0, #21
--.*: 04b0e6a0 decw x0, #21
--.*: 04b0e6c0 decw x0, #22
--.*: 04b0e6c0 decw x0, #22
--.*: 04b0e6c0 decw x0, #22
--.*: 04b0e6e0 decw x0, #23
--.*: 04b0e6e0 decw x0, #23
--.*: 04b0e6e0 decw x0, #23
--.*: 04b0e700 decw x0, #24
--.*: 04b0e700 decw x0, #24
--.*: 04b0e700 decw x0, #24
--.*: 04b0e720 decw x0, #25
--.*: 04b0e720 decw x0, #25
--.*: 04b0e720 decw x0, #25
--.*: 04b0e740 decw x0, #26
--.*: 04b0e740 decw x0, #26
--.*: 04b0e740 decw x0, #26
--.*: 04b0e760 decw x0, #27
--.*: 04b0e760 decw x0, #27
--.*: 04b0e760 decw x0, #27
--.*: 04b0e780 decw x0, #28
--.*: 04b0e780 decw x0, #28
--.*: 04b0e780 decw x0, #28
--.*: 04b0e7a0 decw x0, mul4
--.*: 04b0e7a0 decw x0, mul4
--.*: 04b0e7a0 decw x0, mul4
--.*: 04b0e7c0 decw x0, mul3
--.*: 04b0e7c0 decw x0, mul3
--.*: 04b0e7c0 decw x0, mul3
--.*: 04b0e7e0 decw x0
--.*: 04b0e7e0 decw x0
--.*: 04b0e7e0 decw x0
--.*: 04b0e7e0 decw x0
--.*: 04b7e400 decw x0, pow2, mul #8
--.*: 04b7e400 decw x0, pow2, mul #8
--.*: 04b8e400 decw x0, pow2, mul #9
--.*: 04b8e400 decw x0, pow2, mul #9
--.*: 04b9e400 decw x0, pow2, mul #10
--.*: 04b9e400 decw x0, pow2, mul #10
--.*: 04bfe400 decw x0, pow2, mul #16
--.*: 04bfe400 decw x0, pow2, mul #16
--.*: 05203800 mov z0\.b, w0
--.*: 05203800 mov z0\.b, w0
--.*: 05203801 mov z1\.b, w0
--.*: 05203801 mov z1\.b, w0
--.*: 0520381f mov z31\.b, w0
--.*: 0520381f mov z31\.b, w0
--.*: 05203840 mov z0\.b, w2
--.*: 05203840 mov z0\.b, w2
--.*: 05203be0 mov z0\.b, wsp
--.*: 05203be0 mov z0\.b, wsp
--.*: 05603800 mov z0\.h, w0
--.*: 05603800 mov z0\.h, w0
--.*: 05603801 mov z1\.h, w0
--.*: 05603801 mov z1\.h, w0
--.*: 0560381f mov z31\.h, w0
--.*: 0560381f mov z31\.h, w0
--.*: 05603840 mov z0\.h, w2
--.*: 05603840 mov z0\.h, w2
--.*: 05603be0 mov z0\.h, wsp
--.*: 05603be0 mov z0\.h, wsp
--.*: 05a03800 mov z0\.s, w0
--.*: 05a03800 mov z0\.s, w0
--.*: 05a03801 mov z1\.s, w0
--.*: 05a03801 mov z1\.s, w0
--.*: 05a0381f mov z31\.s, w0
--.*: 05a0381f mov z31\.s, w0
--.*: 05a03840 mov z0\.s, w2
--.*: 05a03840 mov z0\.s, w2
--.*: 05a03be0 mov z0\.s, wsp
--.*: 05a03be0 mov z0\.s, wsp
--.*: 05e03800 mov z0\.d, x0
--.*: 05e03800 mov z0\.d, x0
--.*: 05e03801 mov z1\.d, x0
--.*: 05e03801 mov z1\.d, x0
--.*: 05e0381f mov z31\.d, x0
--.*: 05e0381f mov z31\.d, x0
--.*: 05e03840 mov z0\.d, x2
--.*: 05e03840 mov z0\.d, x2
--.*: 05e03be0 mov z0\.d, sp
--.*: 05e03be0 mov z0\.d, sp
--.*: 05212000 mov z0\.b, b0
--.*: 05212000 mov z0\.b, b0
--.*: 05212001 mov z1\.b, b0
--.*: 05212001 mov z1\.b, b0
--.*: 0521201f mov z31\.b, b0
--.*: 0521201f mov z31\.b, b0
--.*: 05212040 mov z0\.b, b2
--.*: 05212040 mov z0\.b, b2
--.*: 052123e0 mov z0\.b, b31
--.*: 052123e0 mov z0\.b, b31
--.*: 05232000 mov z0\.b, z0\.b\[1\]
--.*: 05232000 mov z0\.b, z0\.b\[1\]
--.*: 05fd2000 mov z0\.b, z0\.b\[62\]
--.*: 05fd2000 mov z0\.b, z0\.b\[62\]
--.*: 05ff2000 mov z0\.b, z0\.b\[63\]
--.*: 05ff2000 mov z0\.b, z0\.b\[63\]
--.*: 05222000 mov z0\.h, h0
--.*: 05222000 mov z0\.h, h0
--.*: 05222001 mov z1\.h, h0
--.*: 05222001 mov z1\.h, h0
--.*: 0522201f mov z31\.h, h0
--.*: 0522201f mov z31\.h, h0
--.*: 05222040 mov z0\.h, h2
--.*: 05222040 mov z0\.h, h2
--.*: 052223e0 mov z0\.h, h31
--.*: 052223e0 mov z0\.h, h31
--.*: 05262000 mov z0\.h, z0\.h\[1\]
--.*: 05262000 mov z0\.h, z0\.h\[1\]
--.*: 05fa2000 mov z0\.h, z0\.h\[30\]
--.*: 05fa2000 mov z0\.h, z0\.h\[30\]
--.*: 05fe2000 mov z0\.h, z0\.h\[31\]
--.*: 05fe2000 mov z0\.h, z0\.h\[31\]
--.*: 05232001 mov z1\.b, z0\.b\[1\]
--.*: 05232001 mov z1\.b, z0\.b\[1\]
--.*: 0523201f mov z31\.b, z0\.b\[1\]
--.*: 0523201f mov z31\.b, z0\.b\[1\]
--.*: 05232040 mov z0\.b, z2\.b\[1\]
--.*: 05232040 mov z0\.b, z2\.b\[1\]
--.*: 052323e0 mov z0\.b, z31\.b\[1\]
--.*: 052323e0 mov z0\.b, z31\.b\[1\]
--.*: 05252000 mov z0\.b, z0\.b\[2\]
--.*: 05252000 mov z0\.b, z0\.b\[2\]
--.*: 05242000 mov z0\.s, s0
--.*: 05242000 mov z0\.s, s0
--.*: 05242001 mov z1\.s, s0
--.*: 05242001 mov z1\.s, s0
--.*: 0524201f mov z31\.s, s0
--.*: 0524201f mov z31\.s, s0
--.*: 05242040 mov z0\.s, s2
--.*: 05242040 mov z0\.s, s2
--.*: 052423e0 mov z0\.s, s31
--.*: 052423e0 mov z0\.s, s31
--.*: 052c2000 mov z0\.s, z0\.s\[1\]
--.*: 052c2000 mov z0\.s, z0\.s\[1\]
--.*: 05f42000 mov z0\.s, z0\.s\[14\]
--.*: 05f42000 mov z0\.s, z0\.s\[14\]
--.*: 05fc2000 mov z0\.s, z0\.s\[15\]
--.*: 05fc2000 mov z0\.s, z0\.s\[15\]
--.*: 05252001 mov z1\.b, z0\.b\[2\]
--.*: 05252001 mov z1\.b, z0\.b\[2\]
--.*: 0525201f mov z31\.b, z0\.b\[2\]
--.*: 0525201f mov z31\.b, z0\.b\[2\]
--.*: 05252040 mov z0\.b, z2\.b\[2\]
--.*: 05252040 mov z0\.b, z2\.b\[2\]
--.*: 052523e0 mov z0\.b, z31\.b\[2\]
--.*: 052523e0 mov z0\.b, z31\.b\[2\]
--.*: 05272000 mov z0\.b, z0\.b\[3\]
--.*: 05272000 mov z0\.b, z0\.b\[3\]
--.*: 05262001 mov z1\.h, z0\.h\[1\]
--.*: 05262001 mov z1\.h, z0\.h\[1\]
--.*: 0526201f mov z31\.h, z0\.h\[1\]
--.*: 0526201f mov z31\.h, z0\.h\[1\]
--.*: 05262040 mov z0\.h, z2\.h\[1\]
--.*: 05262040 mov z0\.h, z2\.h\[1\]
--.*: 052623e0 mov z0\.h, z31\.h\[1\]
--.*: 052623e0 mov z0\.h, z31\.h\[1\]
--.*: 052a2000 mov z0\.h, z0\.h\[2\]
--.*: 052a2000 mov z0\.h, z0\.h\[2\]
--.*: 05272001 mov z1\.b, z0\.b\[3\]
--.*: 05272001 mov z1\.b, z0\.b\[3\]
--.*: 0527201f mov z31\.b, z0\.b\[3\]
--.*: 0527201f mov z31\.b, z0\.b\[3\]
--.*: 05272040 mov z0\.b, z2\.b\[3\]
--.*: 05272040 mov z0\.b, z2\.b\[3\]
--.*: 052723e0 mov z0\.b, z31\.b\[3\]
--.*: 052723e0 mov z0\.b, z31\.b\[3\]
--.*: 05292000 mov z0\.b, z0\.b\[4\]
--.*: 05292000 mov z0\.b, z0\.b\[4\]
--.*: 05282000 mov z0\.d, d0
--.*: 05282000 mov z0\.d, d0
--.*: 05282001 mov z1\.d, d0
--.*: 05282001 mov z1\.d, d0
--.*: 0528201f mov z31\.d, d0
--.*: 0528201f mov z31\.d, d0
--.*: 05282040 mov z0\.d, d2
--.*: 05282040 mov z0\.d, d2
--.*: 052823e0 mov z0\.d, d31
--.*: 052823e0 mov z0\.d, d31
--.*: 05382000 mov z0\.d, z0\.d\[1\]
--.*: 05382000 mov z0\.d, z0\.d\[1\]
--.*: 05e82000 mov z0\.d, z0\.d\[6\]
--.*: 05e82000 mov z0\.d, z0\.d\[6\]
--.*: 05f82000 mov z0\.d, z0\.d\[7\]
--.*: 05f82000 mov z0\.d, z0\.d\[7\]
--.*: 05292001 mov z1\.b, z0\.b\[4\]
--.*: 05292001 mov z1\.b, z0\.b\[4\]
--.*: 0529201f mov z31\.b, z0\.b\[4\]
--.*: 0529201f mov z31\.b, z0\.b\[4\]
--.*: 05292040 mov z0\.b, z2\.b\[4\]
--.*: 05292040 mov z0\.b, z2\.b\[4\]
--.*: 052923e0 mov z0\.b, z31\.b\[4\]
--.*: 052923e0 mov z0\.b, z31\.b\[4\]
--.*: 052b2000 mov z0\.b, z0\.b\[5\]
--.*: 052b2000 mov z0\.b, z0\.b\[5\]
--.*: 052a2001 mov z1\.h, z0\.h\[2\]
--.*: 052a2001 mov z1\.h, z0\.h\[2\]
--.*: 052a201f mov z31\.h, z0\.h\[2\]
--.*: 052a201f mov z31\.h, z0\.h\[2\]
--.*: 052a2040 mov z0\.h, z2\.h\[2\]
--.*: 052a2040 mov z0\.h, z2\.h\[2\]
--.*: 052a23e0 mov z0\.h, z31\.h\[2\]
--.*: 052a23e0 mov z0\.h, z31\.h\[2\]
--.*: 052e2000 mov z0\.h, z0\.h\[3\]
--.*: 052e2000 mov z0\.h, z0\.h\[3\]
--.*: 052b2001 mov z1\.b, z0\.b\[5\]
--.*: 052b2001 mov z1\.b, z0\.b\[5\]
--.*: 052b201f mov z31\.b, z0\.b\[5\]
--.*: 052b201f mov z31\.b, z0\.b\[5\]
--.*: 052b2040 mov z0\.b, z2\.b\[5\]
--.*: 052b2040 mov z0\.b, z2\.b\[5\]
--.*: 052b23e0 mov z0\.b, z31\.b\[5\]
--.*: 052b23e0 mov z0\.b, z31\.b\[5\]
--.*: 052d2000 mov z0\.b, z0\.b\[6\]
--.*: 052d2000 mov z0\.b, z0\.b\[6\]
--.*: 052c2001 mov z1\.s, z0\.s\[1\]
--.*: 052c2001 mov z1\.s, z0\.s\[1\]
--.*: 052c201f mov z31\.s, z0\.s\[1\]
--.*: 052c201f mov z31\.s, z0\.s\[1\]
--.*: 052c2040 mov z0\.s, z2\.s\[1\]
--.*: 052c2040 mov z0\.s, z2\.s\[1\]
--.*: 052c23e0 mov z0\.s, z31\.s\[1\]
--.*: 052c23e0 mov z0\.s, z31\.s\[1\]
--.*: 05342000 mov z0\.s, z0\.s\[2\]
--.*: 05342000 mov z0\.s, z0\.s\[2\]
--.*: 052d2001 mov z1\.b, z0\.b\[6\]
--.*: 052d2001 mov z1\.b, z0\.b\[6\]
--.*: 052d201f mov z31\.b, z0\.b\[6\]
--.*: 052d201f mov z31\.b, z0\.b\[6\]
--.*: 052d2040 mov z0\.b, z2\.b\[6\]
--.*: 052d2040 mov z0\.b, z2\.b\[6\]
--.*: 052d23e0 mov z0\.b, z31\.b\[6\]
--.*: 052d23e0 mov z0\.b, z31\.b\[6\]
--.*: 052f2000 mov z0\.b, z0\.b\[7\]
--.*: 052f2000 mov z0\.b, z0\.b\[7\]
--.*: 052e2001 mov z1\.h, z0\.h\[3\]
--.*: 052e2001 mov z1\.h, z0\.h\[3\]
--.*: 052e201f mov z31\.h, z0\.h\[3\]
--.*: 052e201f mov z31\.h, z0\.h\[3\]
--.*: 052e2040 mov z0\.h, z2\.h\[3\]
--.*: 052e2040 mov z0\.h, z2\.h\[3\]
--.*: 052e23e0 mov z0\.h, z31\.h\[3\]
--.*: 052e23e0 mov z0\.h, z31\.h\[3\]
--.*: 05322000 mov z0\.h, z0\.h\[4\]
--.*: 05322000 mov z0\.h, z0\.h\[4\]
--.*: 052f2001 mov z1\.b, z0\.b\[7\]
--.*: 052f2001 mov z1\.b, z0\.b\[7\]
--.*: 052f201f mov z31\.b, z0\.b\[7\]
--.*: 052f201f mov z31\.b, z0\.b\[7\]
--.*: 052f2040 mov z0\.b, z2\.b\[7\]
--.*: 052f2040 mov z0\.b, z2\.b\[7\]
--.*: 052f23e0 mov z0\.b, z31\.b\[7\]
--.*: 052f23e0 mov z0\.b, z31\.b\[7\]
--.*: 05312000 mov z0\.b, z0\.b\[8\]
--.*: 05312000 mov z0\.b, z0\.b\[8\]
--.*: 05702000 mov z0\.q, z0\.q\[1\]
--.*: 05702000 mov z0\.q, z0\.q\[1\]
--.*: 05702001 mov z1\.q, z0\.q\[1\]
--.*: 05702001 mov z1\.q, z0\.q\[1\]
--.*: 0570201f mov z31\.q, z0\.q\[1\]
--.*: 0570201f mov z31\.q, z0\.q\[1\]
--.*: 05702040 mov z0\.q, z2\.q\[1\]
--.*: 05702040 mov z0\.q, z2\.q\[1\]
--.*: 057023e0 mov z0\.q, z31\.q\[1\]
--.*: 057023e0 mov z0\.q, z31\.q\[1\]
--.*: 05302000 mov z0\.q, q0
--.*: 05302000 mov z0\.q, q0
--.*: 05b02000 mov z0\.q, z0\.q\[2\]
--.*: 05b02000 mov z0\.q, z0\.q\[2\]
--.*: 05f02000 mov z0\.q, z0\.q\[3\]
--.*: 05f02000 mov z0\.q, z0\.q\[3\]
--.*: 2538c000 mov z0\.b, #0
--.*: 2538c000 mov z0\.b, #0
--.*: 2538c000 mov z0\.b, #0
--.*: 2538c001 mov z1\.b, #0
--.*: 2538c001 mov z1\.b, #0
--.*: 2538c001 mov z1\.b, #0
--.*: 2538c01f mov z31\.b, #0
--.*: 2538c01f mov z31\.b, #0
--.*: 2538c01f mov z31\.b, #0
--.*: 2538cfe0 mov z0\.b, #127
--.*: 2538cfe0 mov z0\.b, #127
--.*: 2538cfe0 mov z0\.b, #127
--.*: 2538d000 mov z0\.b, #-128
--.*: 2538d000 mov z0\.b, #-128
--.*: 2538d000 mov z0\.b, #-128
--.*: 2538d020 mov z0\.b, #-127
--.*: 2538d020 mov z0\.b, #-127
--.*: 2538d020 mov z0\.b, #-127
--.*: 2538dfe0 mov z0\.b, #-1
--.*: 2538dfe0 mov z0\.b, #-1
--.*: 2538dfe0 mov z0\.b, #-1
--.*: 2578c000 mov z0\.h, #0
--.*: 2578c000 mov z0\.h, #0
--.*: 2578c000 mov z0\.h, #0
--.*: 2578c001 mov z1\.h, #0
--.*: 2578c001 mov z1\.h, #0
--.*: 2578c001 mov z1\.h, #0
--.*: 2578c01f mov z31\.h, #0
--.*: 2578c01f mov z31\.h, #0
--.*: 2578c01f mov z31\.h, #0
--.*: 2578cfe0 mov z0\.h, #127
--.*: 2578cfe0 mov z0\.h, #127
--.*: 2578cfe0 mov z0\.h, #127
--.*: 2578d000 mov z0\.h, #-128
--.*: 2578d000 mov z0\.h, #-128
--.*: 2578d000 mov z0\.h, #-128
--.*: 2578d020 mov z0\.h, #-127
--.*: 2578d020 mov z0\.h, #-127
--.*: 2578d020 mov z0\.h, #-127
--.*: 2578dfe0 mov z0\.h, #-1
--.*: 2578dfe0 mov z0\.h, #-1
--.*: 2578dfe0 mov z0\.h, #-1
--.*: 2578e000 mov z0\.h, #0, lsl #8
--.*: 2578e000 mov z0\.h, #0, lsl #8
--.*: 2578efe0 mov z0\.h, #32512
--.*: 2578efe0 mov z0\.h, #32512
--.*: 2578efe0 mov z0\.h, #32512
--.*: 2578efe0 mov z0\.h, #32512
--.*: 2578f000 mov z0\.h, #-32768
--.*: 2578f000 mov z0\.h, #-32768
--.*: 2578f000 mov z0\.h, #-32768
--.*: 2578f000 mov z0\.h, #-32768
--.*: 2578f020 mov z0\.h, #-32512
--.*: 2578f020 mov z0\.h, #-32512
--.*: 2578f020 mov z0\.h, #-32512
--.*: 2578f020 mov z0\.h, #-32512
--.*: 2578ffe0 mov z0\.h, #-256
--.*: 2578ffe0 mov z0\.h, #-256
--.*: 2578ffe0 mov z0\.h, #-256
--.*: 2578ffe0 mov z0\.h, #-256
--.*: 25b8c000 mov z0\.s, #0
--.*: 25b8c000 mov z0\.s, #0
--.*: 25b8c000 mov z0\.s, #0
--.*: 25b8c001 mov z1\.s, #0
--.*: 25b8c001 mov z1\.s, #0
--.*: 25b8c001 mov z1\.s, #0
--.*: 25b8c01f mov z31\.s, #0
--.*: 25b8c01f mov z31\.s, #0
--.*: 25b8c01f mov z31\.s, #0
--.*: 25b8cfe0 mov z0\.s, #127
--.*: 25b8cfe0 mov z0\.s, #127
--.*: 25b8cfe0 mov z0\.s, #127
--.*: 25b8d000 mov z0\.s, #-128
--.*: 25b8d000 mov z0\.s, #-128
--.*: 25b8d000 mov z0\.s, #-128
--.*: 25b8d020 mov z0\.s, #-127
--.*: 25b8d020 mov z0\.s, #-127
--.*: 25b8d020 mov z0\.s, #-127
--.*: 25b8dfe0 mov z0\.s, #-1
--.*: 25b8dfe0 mov z0\.s, #-1
--.*: 25b8dfe0 mov z0\.s, #-1
--.*: 25b8e000 mov z0\.s, #0, lsl #8
--.*: 25b8e000 mov z0\.s, #0, lsl #8
--.*: 25b8efe0 mov z0\.s, #32512
--.*: 25b8efe0 mov z0\.s, #32512
--.*: 25b8efe0 mov z0\.s, #32512
--.*: 25b8efe0 mov z0\.s, #32512
--.*: 25b8f000 mov z0\.s, #-32768
--.*: 25b8f000 mov z0\.s, #-32768
--.*: 25b8f000 mov z0\.s, #-32768
--.*: 25b8f000 mov z0\.s, #-32768
--.*: 25b8f020 mov z0\.s, #-32512
--.*: 25b8f020 mov z0\.s, #-32512
--.*: 25b8f020 mov z0\.s, #-32512
--.*: 25b8f020 mov z0\.s, #-32512
--.*: 25b8ffe0 mov z0\.s, #-256
--.*: 25b8ffe0 mov z0\.s, #-256
--.*: 25b8ffe0 mov z0\.s, #-256
--.*: 25b8ffe0 mov z0\.s, #-256
--.*: 25f8c000 mov z0\.d, #0
--.*: 25f8c000 mov z0\.d, #0
--.*: 25f8c000 mov z0\.d, #0
--.*: 25f8c001 mov z1\.d, #0
--.*: 25f8c001 mov z1\.d, #0
--.*: 25f8c001 mov z1\.d, #0
--.*: 25f8c01f mov z31\.d, #0
--.*: 25f8c01f mov z31\.d, #0
--.*: 25f8c01f mov z31\.d, #0
--.*: 25f8cfe0 mov z0\.d, #127
--.*: 25f8cfe0 mov z0\.d, #127
--.*: 25f8cfe0 mov z0\.d, #127
--.*: 25f8d000 mov z0\.d, #-128
--.*: 25f8d000 mov z0\.d, #-128
--.*: 25f8d000 mov z0\.d, #-128
--.*: 25f8d020 mov z0\.d, #-127
--.*: 25f8d020 mov z0\.d, #-127
--.*: 25f8d020 mov z0\.d, #-127
--.*: 25f8dfe0 mov z0\.d, #-1
--.*: 25f8dfe0 mov z0\.d, #-1
--.*: 25f8dfe0 mov z0\.d, #-1
--.*: 25f8e000 mov z0\.d, #0, lsl #8
--.*: 25f8e000 mov z0\.d, #0, lsl #8
--.*: 25f8efe0 mov z0\.d, #32512
--.*: 25f8efe0 mov z0\.d, #32512
--.*: 25f8efe0 mov z0\.d, #32512
--.*: 25f8efe0 mov z0\.d, #32512
--.*: 25f8f000 mov z0\.d, #-32768
--.*: 25f8f000 mov z0\.d, #-32768
--.*: 25f8f000 mov z0\.d, #-32768
--.*: 25f8f000 mov z0\.d, #-32768
--.*: 25f8f020 mov z0\.d, #-32512
--.*: 25f8f020 mov z0\.d, #-32512
--.*: 25f8f020 mov z0\.d, #-32512
--.*: 25f8f020 mov z0\.d, #-32512
--.*: 25f8ffe0 mov z0\.d, #-256
--.*: 25f8ffe0 mov z0\.d, #-256
--.*: 25f8ffe0 mov z0\.d, #-256
--.*: 25f8ffe0 mov z0\.d, #-256
--.*: 05c00000 dupm z0\.s, #0x1
--.*: 05c00000 dupm z0\.s, #0x1
--.*: 05c00000 dupm z0\.s, #0x1
--.*: 05c00001 dupm z1\.s, #0x1
--.*: 05c00001 dupm z1\.s, #0x1
--.*: 05c00001 dupm z1\.s, #0x1
--.*: 05c0001f dupm z31\.s, #0x1
--.*: 05c0001f dupm z31\.s, #0x1
--.*: 05c0001f dupm z31\.s, #0x1
--.*: 05c000c0 dupm z0\.s, #0x7f
--.*: 05c000c0 dupm z0\.s, #0x7f
--.*: 05c000c0 dupm z0\.s, #0x7f
--.*: 05c003c0 mov z0\.s, #0x7fffffff
--.*: 05c003c0 mov z0\.s, #0x7fffffff
--.*: 05c003c0 mov z0\.s, #0x7fffffff
--.*: 05c00400 dupm z0\.h, #0x1
--.*: 05c00400 dupm z0\.h, #0x1
--.*: 05c00400 dupm z0\.h, #0x1
--.*: 05c00400 dupm z0\.h, #0x1
--.*: 05c005c0 mov z0\.h, #0x7fff
--.*: 05c005c0 mov z0\.h, #0x7fff
--.*: 05c005c0 mov z0\.h, #0x7fff
--.*: 05c005c0 mov z0\.h, #0x7fff
--.*: 05c00600 dupm z0\.b, #0x1
--.*: 05c00600 dupm z0\.b, #0x1
--.*: 05c00600 dupm z0\.b, #0x1
--.*: 05c00600 dupm z0\.b, #0x1
--.*: 05c00600 dupm z0\.b, #0x1
--.*: 05c00780 dupm z0\.b, #0x55
--.*: 05c00780 dupm z0\.b, #0x55
--.*: 05c00780 dupm z0\.b, #0x55
--.*: 05c00780 dupm z0\.b, #0x55
--.*: 05c00780 dupm z0\.b, #0x55
--.*: 05c00800 mov z0\.s, #0x80000000
--.*: 05c00800 mov z0\.s, #0x80000000
--.*: 05c00800 mov z0\.s, #0x80000000
--.*: 05c00bc0 mov z0\.s, #0xbfffffff
--.*: 05c00bc0 mov z0\.s, #0xbfffffff
--.*: 05c00bc0 mov z0\.s, #0xbfffffff
--.*: 05c00c00 dupm z0\.h, #0x8000
--.*: 05c00c00 dupm z0\.h, #0x8000
--.*: 05c00c00 dupm z0\.h, #0x8000
--.*: 05c00c00 dupm z0\.h, #0x8000
--.*: 05c00ec0 dupm z0\.b, #0xbf
--.*: 05c00ec0 dupm z0\.b, #0xbf
--.*: 05c00ec0 dupm z0\.b, #0xbf
--.*: 05c00ec0 dupm z0\.b, #0xbf
--.*: 05c00ec0 dupm z0\.b, #0xbf
--.*: 05c01e80 dupm z0\.b, #0xe3
--.*: 05c01e80 dupm z0\.b, #0xe3
--.*: 05c01e80 dupm z0\.b, #0xe3
--.*: 05c01e80 dupm z0\.b, #0xe3
--.*: 05c01e80 dupm z0\.b, #0xe3
--.*: 05c0bbc0 mov z0\.s, #0xfffffeff
--.*: 05c0bbc0 mov z0\.s, #0xfffffeff
--.*: 05c0bbc0 mov z0\.s, #0xfffffeff
--.*: 05c3ffc0 dupm z0\.d, #0xfffffffffffffffe
--.*: 05c3ffc0 dupm z0\.d, #0xfffffffffffffffe
--.*: 04a03000 eor z0\.d, z0\.d, z0\.d
--.*: 04a03000 eor z0\.d, z0\.d, z0\.d
--.*: 04a03001 eor z1\.d, z0\.d, z0\.d
--.*: 04a03001 eor z1\.d, z0\.d, z0\.d
--.*: 04a0301f eor z31\.d, z0\.d, z0\.d
--.*: 04a0301f eor z31\.d, z0\.d, z0\.d
--.*: 04a03040 eor z0\.d, z2\.d, z0\.d
--.*: 04a03040 eor z0\.d, z2\.d, z0\.d
--.*: 04a033e0 eor z0\.d, z31\.d, z0\.d
--.*: 04a033e0 eor z0\.d, z31\.d, z0\.d
--.*: 04a33000 eor z0\.d, z0\.d, z3\.d
--.*: 04a33000 eor z0\.d, z0\.d, z3\.d
--.*: 04bf3000 eor z0\.d, z0\.d, z31\.d
--.*: 04bf3000 eor z0\.d, z0\.d, z31\.d
--.*: 05400000 eor z0\.s, z0\.s, #0x1
--.*: 05400000 eor z0\.s, z0\.s, #0x1
--.*: 05400000 eor z0\.s, z0\.s, #0x1
--.*: 05400001 eor z1\.s, z1\.s, #0x1
--.*: 05400001 eor z1\.s, z1\.s, #0x1
--.*: 05400001 eor z1\.s, z1\.s, #0x1
--.*: 0540001f eor z31\.s, z31\.s, #0x1
--.*: 0540001f eor z31\.s, z31\.s, #0x1
--.*: 0540001f eor z31\.s, z31\.s, #0x1
--.*: 05400002 eor z2\.s, z2\.s, #0x1
--.*: 05400002 eor z2\.s, z2\.s, #0x1
--.*: 05400002 eor z2\.s, z2\.s, #0x1
--.*: 054000c0 eor z0\.s, z0\.s, #0x7f
--.*: 054000c0 eor z0\.s, z0\.s, #0x7f
--.*: 054000c0 eor z0\.s, z0\.s, #0x7f
--.*: 054003c0 eor z0\.s, z0\.s, #0x7fffffff
--.*: 054003c0 eor z0\.s, z0\.s, #0x7fffffff
--.*: 054003c0 eor z0\.s, z0\.s, #0x7fffffff
--.*: 05400400 eor z0\.h, z0\.h, #0x1
--.*: 05400400 eor z0\.h, z0\.h, #0x1
--.*: 05400400 eor z0\.h, z0\.h, #0x1
--.*: 05400400 eor z0\.h, z0\.h, #0x1
--.*: 054005c0 eor z0\.h, z0\.h, #0x7fff
--.*: 054005c0 eor z0\.h, z0\.h, #0x7fff
--.*: 054005c0 eor z0\.h, z0\.h, #0x7fff
--.*: 054005c0 eor z0\.h, z0\.h, #0x7fff
--.*: 05400600 eor z0\.b, z0\.b, #0x1
--.*: 05400600 eor z0\.b, z0\.b, #0x1
--.*: 05400600 eor z0\.b, z0\.b, #0x1
--.*: 05400600 eor z0\.b, z0\.b, #0x1
--.*: 05400600 eor z0\.b, z0\.b, #0x1
--.*: 05400780 eor z0\.b, z0\.b, #0x55
--.*: 05400780 eor z0\.b, z0\.b, #0x55
--.*: 05400780 eor z0\.b, z0\.b, #0x55
--.*: 05400780 eor z0\.b, z0\.b, #0x55
--.*: 05400780 eor z0\.b, z0\.b, #0x55
--.*: 05400800 eor z0\.s, z0\.s, #0x80000000
--.*: 05400800 eor z0\.s, z0\.s, #0x80000000
--.*: 05400800 eor z0\.s, z0\.s, #0x80000000
--.*: 05400bc0 eor z0\.s, z0\.s, #0xbfffffff
--.*: 05400bc0 eor z0\.s, z0\.s, #0xbfffffff
--.*: 05400bc0 eor z0\.s, z0\.s, #0xbfffffff
--.*: 05400c00 eor z0\.h, z0\.h, #0x8000
--.*: 05400c00 eor z0\.h, z0\.h, #0x8000
--.*: 05400c00 eor z0\.h, z0\.h, #0x8000
--.*: 05400c00 eor z0\.h, z0\.h, #0x8000
--.*: 05400ec0 eor z0\.b, z0\.b, #0xbf
--.*: 05400ec0 eor z0\.b, z0\.b, #0xbf
--.*: 05400ec0 eor z0\.b, z0\.b, #0xbf
--.*: 05400ec0 eor z0\.b, z0\.b, #0xbf
--.*: 05400ec0 eor z0\.b, z0\.b, #0xbf
--.*: 05401e80 eor z0\.b, z0\.b, #0xe3
--.*: 05401e80 eor z0\.b, z0\.b, #0xe3
--.*: 05401e80 eor z0\.b, z0\.b, #0xe3
--.*: 05401e80 eor z0\.b, z0\.b, #0xe3
--.*: 05401e80 eor z0\.b, z0\.b, #0xe3
--.*: 0540bbc0 eor z0\.s, z0\.s, #0xfffffeff
--.*: 0540bbc0 eor z0\.s, z0\.s, #0xfffffeff
--.*: 0540bbc0 eor z0\.s, z0\.s, #0xfffffeff
--.*: 0543ffc0 eor z0\.d, z0\.d, #0xfffffffffffffffe
--.*: 0543ffc0 eor z0\.d, z0\.d, #0xfffffffffffffffe
--.*: 04190000 eor z0\.b, p0/m, z0\.b, z0\.b
--.*: 04190000 eor z0\.b, p0/m, z0\.b, z0\.b
--.*: 04190001 eor z1\.b, p0/m, z1\.b, z0\.b
--.*: 04190001 eor z1\.b, p0/m, z1\.b, z0\.b
--.*: 0419001f eor z31\.b, p0/m, z31\.b, z0\.b
--.*: 0419001f eor z31\.b, p0/m, z31\.b, z0\.b
--.*: 04190800 eor z0\.b, p2/m, z0\.b, z0\.b
--.*: 04190800 eor z0\.b, p2/m, z0\.b, z0\.b
--.*: 04191c00 eor z0\.b, p7/m, z0\.b, z0\.b
--.*: 04191c00 eor z0\.b, p7/m, z0\.b, z0\.b
--.*: 04190003 eor z3\.b, p0/m, z3\.b, z0\.b
--.*: 04190003 eor z3\.b, p0/m, z3\.b, z0\.b
--.*: 04190080 eor z0\.b, p0/m, z0\.b, z4\.b
--.*: 04190080 eor z0\.b, p0/m, z0\.b, z4\.b
--.*: 041903e0 eor z0\.b, p0/m, z0\.b, z31\.b
--.*: 041903e0 eor z0\.b, p0/m, z0\.b, z31\.b
--.*: 04590000 eor z0\.h, p0/m, z0\.h, z0\.h
--.*: 04590000 eor z0\.h, p0/m, z0\.h, z0\.h
--.*: 04590001 eor z1\.h, p0/m, z1\.h, z0\.h
--.*: 04590001 eor z1\.h, p0/m, z1\.h, z0\.h
--.*: 0459001f eor z31\.h, p0/m, z31\.h, z0\.h
--.*: 0459001f eor z31\.h, p0/m, z31\.h, z0\.h
--.*: 04590800 eor z0\.h, p2/m, z0\.h, z0\.h
--.*: 04590800 eor z0\.h, p2/m, z0\.h, z0\.h
--.*: 04591c00 eor z0\.h, p7/m, z0\.h, z0\.h
--.*: 04591c00 eor z0\.h, p7/m, z0\.h, z0\.h
--.*: 04590003 eor z3\.h, p0/m, z3\.h, z0\.h
--.*: 04590003 eor z3\.h, p0/m, z3\.h, z0\.h
--.*: 04590080 eor z0\.h, p0/m, z0\.h, z4\.h
--.*: 04590080 eor z0\.h, p0/m, z0\.h, z4\.h
--.*: 045903e0 eor z0\.h, p0/m, z0\.h, z31\.h
--.*: 045903e0 eor z0\.h, p0/m, z0\.h, z31\.h
--.*: 04990000 eor z0\.s, p0/m, z0\.s, z0\.s
--.*: 04990000 eor z0\.s, p0/m, z0\.s, z0\.s
--.*: 04990001 eor z1\.s, p0/m, z1\.s, z0\.s
--.*: 04990001 eor z1\.s, p0/m, z1\.s, z0\.s
--.*: 0499001f eor z31\.s, p0/m, z31\.s, z0\.s
--.*: 0499001f eor z31\.s, p0/m, z31\.s, z0\.s
--.*: 04990800 eor z0\.s, p2/m, z0\.s, z0\.s
--.*: 04990800 eor z0\.s, p2/m, z0\.s, z0\.s
--.*: 04991c00 eor z0\.s, p7/m, z0\.s, z0\.s
--.*: 04991c00 eor z0\.s, p7/m, z0\.s, z0\.s
--.*: 04990003 eor z3\.s, p0/m, z3\.s, z0\.s
--.*: 04990003 eor z3\.s, p0/m, z3\.s, z0\.s
--.*: 04990080 eor z0\.s, p0/m, z0\.s, z4\.s
--.*: 04990080 eor z0\.s, p0/m, z0\.s, z4\.s
--.*: 049903e0 eor z0\.s, p0/m, z0\.s, z31\.s
--.*: 049903e0 eor z0\.s, p0/m, z0\.s, z31\.s
--.*: 04d90000 eor z0\.d, p0/m, z0\.d, z0\.d
--.*: 04d90000 eor z0\.d, p0/m, z0\.d, z0\.d
--.*: 04d90001 eor z1\.d, p0/m, z1\.d, z0\.d
--.*: 04d90001 eor z1\.d, p0/m, z1\.d, z0\.d
--.*: 04d9001f eor z31\.d, p0/m, z31\.d, z0\.d
--.*: 04d9001f eor z31\.d, p0/m, z31\.d, z0\.d
--.*: 04d90800 eor z0\.d, p2/m, z0\.d, z0\.d
--.*: 04d90800 eor z0\.d, p2/m, z0\.d, z0\.d
--.*: 04d91c00 eor z0\.d, p7/m, z0\.d, z0\.d
--.*: 04d91c00 eor z0\.d, p7/m, z0\.d, z0\.d
--.*: 04d90003 eor z3\.d, p0/m, z3\.d, z0\.d
--.*: 04d90003 eor z3\.d, p0/m, z3\.d, z0\.d
--.*: 04d90080 eor z0\.d, p0/m, z0\.d, z4\.d
--.*: 04d90080 eor z0\.d, p0/m, z0\.d, z4\.d
--.*: 04d903e0 eor z0\.d, p0/m, z0\.d, z31\.d
--.*: 04d903e0 eor z0\.d, p0/m, z0\.d, z31\.d
--.*: 25004200 not p0\.b, p0/z, p0\.b
--.*: 25004200 not p0\.b, p0/z, p0\.b
--.*: 25004201 not p1\.b, p0/z, p0\.b
--.*: 25004201 not p1\.b, p0/z, p0\.b
--.*: 2500420f not p15\.b, p0/z, p0\.b
--.*: 2500420f not p15\.b, p0/z, p0\.b
--.*: 25004a00 eor p0\.b, p2/z, p0\.b, p0\.b
--.*: 25004a00 eor p0\.b, p2/z, p0\.b, p0\.b
--.*: 25007e00 eor p0\.b, p15/z, p0\.b, p0\.b
--.*: 25007e00 eor p0\.b, p15/z, p0\.b, p0\.b
--.*: 25004260 not p0\.b, p0/z, p3\.b
--.*: 25004260 not p0\.b, p0/z, p3\.b
--.*: 250043e0 not p0\.b, p0/z, p15\.b
--.*: 250043e0 not p0\.b, p0/z, p15\.b
--.*: 25044200 eor p0\.b, p0/z, p0\.b, p4\.b
--.*: 25044200 eor p0\.b, p0/z, p0\.b, p4\.b
--.*: 250f4200 eor p0\.b, p0/z, p0\.b, p15\.b
--.*: 250f4200 eor p0\.b, p0/z, p0\.b, p15\.b
--.*: 25404200 nots p0\.b, p0/z, p0\.b
--.*: 25404200 nots p0\.b, p0/z, p0\.b
--.*: 25404201 nots p1\.b, p0/z, p0\.b
--.*: 25404201 nots p1\.b, p0/z, p0\.b
--.*: 2540420f nots p15\.b, p0/z, p0\.b
--.*: 2540420f nots p15\.b, p0/z, p0\.b
--.*: 25404a00 eors p0\.b, p2/z, p0\.b, p0\.b
--.*: 25404a00 eors p0\.b, p2/z, p0\.b, p0\.b
--.*: 25407e00 eors p0\.b, p15/z, p0\.b, p0\.b
--.*: 25407e00 eors p0\.b, p15/z, p0\.b, p0\.b
--.*: 25404260 nots p0\.b, p0/z, p3\.b
--.*: 25404260 nots p0\.b, p0/z, p3\.b
--.*: 254043e0 nots p0\.b, p0/z, p15\.b
--.*: 254043e0 nots p0\.b, p0/z, p15\.b
--.*: 25444200 eors p0\.b, p0/z, p0\.b, p4\.b
--.*: 25444200 eors p0\.b, p0/z, p0\.b, p4\.b
--.*: 254f4200 eors p0\.b, p0/z, p0\.b, p15\.b
--.*: 254f4200 eors p0\.b, p0/z, p0\.b, p15\.b
--.*: 04192000 eorv b0, p0, z0\.b
--.*: 04192000 eorv b0, p0, z0\.b
--.*: 04192001 eorv b1, p0, z0\.b
--.*: 04192001 eorv b1, p0, z0\.b
--.*: 0419201f eorv b31, p0, z0\.b
--.*: 0419201f eorv b31, p0, z0\.b
--.*: 04192800 eorv b0, p2, z0\.b
--.*: 04192800 eorv b0, p2, z0\.b
--.*: 04193c00 eorv b0, p7, z0\.b
--.*: 04193c00 eorv b0, p7, z0\.b
--.*: 04192060 eorv b0, p0, z3\.b
--.*: 04192060 eorv b0, p0, z3\.b
--.*: 041923e0 eorv b0, p0, z31\.b
--.*: 041923e0 eorv b0, p0, z31\.b
--.*: 04592000 eorv h0, p0, z0\.h
--.*: 04592000 eorv h0, p0, z0\.h
--.*: 04592001 eorv h1, p0, z0\.h
--.*: 04592001 eorv h1, p0, z0\.h
--.*: 0459201f eorv h31, p0, z0\.h
--.*: 0459201f eorv h31, p0, z0\.h
--.*: 04592800 eorv h0, p2, z0\.h
--.*: 04592800 eorv h0, p2, z0\.h
--.*: 04593c00 eorv h0, p7, z0\.h
--.*: 04593c00 eorv h0, p7, z0\.h
--.*: 04592060 eorv h0, p0, z3\.h
--.*: 04592060 eorv h0, p0, z3\.h
--.*: 045923e0 eorv h0, p0, z31\.h
--.*: 045923e0 eorv h0, p0, z31\.h
--.*: 04992000 eorv s0, p0, z0\.s
--.*: 04992000 eorv s0, p0, z0\.s
--.*: 04992001 eorv s1, p0, z0\.s
--.*: 04992001 eorv s1, p0, z0\.s
--.*: 0499201f eorv s31, p0, z0\.s
--.*: 0499201f eorv s31, p0, z0\.s
--.*: 04992800 eorv s0, p2, z0\.s
--.*: 04992800 eorv s0, p2, z0\.s
--.*: 04993c00 eorv s0, p7, z0\.s
--.*: 04993c00 eorv s0, p7, z0\.s
--.*: 04992060 eorv s0, p0, z3\.s
--.*: 04992060 eorv s0, p0, z3\.s
--.*: 049923e0 eorv s0, p0, z31\.s
--.*: 049923e0 eorv s0, p0, z31\.s
--.*: 04d92000 eorv d0, p0, z0\.d
--.*: 04d92000 eorv d0, p0, z0\.d
--.*: 04d92001 eorv d1, p0, z0\.d
--.*: 04d92001 eorv d1, p0, z0\.d
--.*: 04d9201f eorv d31, p0, z0\.d
--.*: 04d9201f eorv d31, p0, z0\.d
--.*: 04d92800 eorv d0, p2, z0\.d
--.*: 04d92800 eorv d0, p2, z0\.d
--.*: 04d93c00 eorv d0, p7, z0\.d
--.*: 04d93c00 eorv d0, p7, z0\.d
--.*: 04d92060 eorv d0, p0, z3\.d
--.*: 04d92060 eorv d0, p0, z3\.d
--.*: 04d923e0 eorv d0, p0, z31\.d
--.*: 04d923e0 eorv d0, p0, z31\.d
--.*: 05200000 ext z0\.b, z0\.b, z0\.b, #0
--.*: 05200000 ext z0\.b, z0\.b, z0\.b, #0
--.*: 05200001 ext z1\.b, z1\.b, z0\.b, #0
--.*: 05200001 ext z1\.b, z1\.b, z0\.b, #0
--.*: 0520001f ext z31\.b, z31\.b, z0\.b, #0
--.*: 0520001f ext z31\.b, z31\.b, z0\.b, #0
--.*: 05200002 ext z2\.b, z2\.b, z0\.b, #0
--.*: 05200002 ext z2\.b, z2\.b, z0\.b, #0
--.*: 05200060 ext z0\.b, z0\.b, z3\.b, #0
--.*: 05200060 ext z0\.b, z0\.b, z3\.b, #0
--.*: 052003e0 ext z0\.b, z0\.b, z31\.b, #0
--.*: 052003e0 ext z0\.b, z0\.b, z31\.b, #0
--.*: 052f1c00 ext z0\.b, z0\.b, z0\.b, #127
--.*: 052f1c00 ext z0\.b, z0\.b, z0\.b, #127
--.*: 05300000 ext z0\.b, z0\.b, z0\.b, #128
--.*: 05300000 ext z0\.b, z0\.b, z0\.b, #128
--.*: 05300400 ext z0\.b, z0\.b, z0\.b, #129
--.*: 05300400 ext z0\.b, z0\.b, z0\.b, #129
--.*: 053f1c00 ext z0\.b, z0\.b, z0\.b, #255
--.*: 053f1c00 ext z0\.b, z0\.b, z0\.b, #255
--.*: 65488000 fabd z0\.h, p0/m, z0\.h, z0\.h
--.*: 65488000 fabd z0\.h, p0/m, z0\.h, z0\.h
--.*: 65488001 fabd z1\.h, p0/m, z1\.h, z0\.h
--.*: 65488001 fabd z1\.h, p0/m, z1\.h, z0\.h
--.*: 6548801f fabd z31\.h, p0/m, z31\.h, z0\.h
--.*: 6548801f fabd z31\.h, p0/m, z31\.h, z0\.h
--.*: 65488800 fabd z0\.h, p2/m, z0\.h, z0\.h
--.*: 65488800 fabd z0\.h, p2/m, z0\.h, z0\.h
--.*: 65489c00 fabd z0\.h, p7/m, z0\.h, z0\.h
--.*: 65489c00 fabd z0\.h, p7/m, z0\.h, z0\.h
--.*: 65488003 fabd z3\.h, p0/m, z3\.h, z0\.h
--.*: 65488003 fabd z3\.h, p0/m, z3\.h, z0\.h
--.*: 65488080 fabd z0\.h, p0/m, z0\.h, z4\.h
--.*: 65488080 fabd z0\.h, p0/m, z0\.h, z4\.h
--.*: 654883e0 fabd z0\.h, p0/m, z0\.h, z31\.h
--.*: 654883e0 fabd z0\.h, p0/m, z0\.h, z31\.h
--.*: 65888000 fabd z0\.s, p0/m, z0\.s, z0\.s
--.*: 65888000 fabd z0\.s, p0/m, z0\.s, z0\.s
--.*: 65888001 fabd z1\.s, p0/m, z1\.s, z0\.s
--.*: 65888001 fabd z1\.s, p0/m, z1\.s, z0\.s
--.*: 6588801f fabd z31\.s, p0/m, z31\.s, z0\.s
--.*: 6588801f fabd z31\.s, p0/m, z31\.s, z0\.s
--.*: 65888800 fabd z0\.s, p2/m, z0\.s, z0\.s
--.*: 65888800 fabd z0\.s, p2/m, z0\.s, z0\.s
--.*: 65889c00 fabd z0\.s, p7/m, z0\.s, z0\.s
--.*: 65889c00 fabd z0\.s, p7/m, z0\.s, z0\.s
--.*: 65888003 fabd z3\.s, p0/m, z3\.s, z0\.s
--.*: 65888003 fabd z3\.s, p0/m, z3\.s, z0\.s
--.*: 65888080 fabd z0\.s, p0/m, z0\.s, z4\.s
--.*: 65888080 fabd z0\.s, p0/m, z0\.s, z4\.s
--.*: 658883e0 fabd z0\.s, p0/m, z0\.s, z31\.s
--.*: 658883e0 fabd z0\.s, p0/m, z0\.s, z31\.s
--.*: 65c88000 fabd z0\.d, p0/m, z0\.d, z0\.d
--.*: 65c88000 fabd z0\.d, p0/m, z0\.d, z0\.d
--.*: 65c88001 fabd z1\.d, p0/m, z1\.d, z0\.d
--.*: 65c88001 fabd z1\.d, p0/m, z1\.d, z0\.d
--.*: 65c8801f fabd z31\.d, p0/m, z31\.d, z0\.d
--.*: 65c8801f fabd z31\.d, p0/m, z31\.d, z0\.d
--.*: 65c88800 fabd z0\.d, p2/m, z0\.d, z0\.d
--.*: 65c88800 fabd z0\.d, p2/m, z0\.d, z0\.d
--.*: 65c89c00 fabd z0\.d, p7/m, z0\.d, z0\.d
--.*: 65c89c00 fabd z0\.d, p7/m, z0\.d, z0\.d
--.*: 65c88003 fabd z3\.d, p0/m, z3\.d, z0\.d
--.*: 65c88003 fabd z3\.d, p0/m, z3\.d, z0\.d
--.*: 65c88080 fabd z0\.d, p0/m, z0\.d, z4\.d
--.*: 65c88080 fabd z0\.d, p0/m, z0\.d, z4\.d
--.*: 65c883e0 fabd z0\.d, p0/m, z0\.d, z31\.d
--.*: 65c883e0 fabd z0\.d, p0/m, z0\.d, z31\.d
--.*: 045ca000 fabs z0\.h, p0/m, z0\.h
--.*: 045ca000 fabs z0\.h, p0/m, z0\.h
--.*: 045ca001 fabs z1\.h, p0/m, z0\.h
--.*: 045ca001 fabs z1\.h, p0/m, z0\.h
--.*: 045ca01f fabs z31\.h, p0/m, z0\.h
--.*: 045ca01f fabs z31\.h, p0/m, z0\.h
--.*: 045ca800 fabs z0\.h, p2/m, z0\.h
--.*: 045ca800 fabs z0\.h, p2/m, z0\.h
--.*: 045cbc00 fabs z0\.h, p7/m, z0\.h
--.*: 045cbc00 fabs z0\.h, p7/m, z0\.h
--.*: 045ca060 fabs z0\.h, p0/m, z3\.h
--.*: 045ca060 fabs z0\.h, p0/m, z3\.h
--.*: 045ca3e0 fabs z0\.h, p0/m, z31\.h
--.*: 045ca3e0 fabs z0\.h, p0/m, z31\.h
--.*: 049ca000 fabs z0\.s, p0/m, z0\.s
--.*: 049ca000 fabs z0\.s, p0/m, z0\.s
--.*: 049ca001 fabs z1\.s, p0/m, z0\.s
--.*: 049ca001 fabs z1\.s, p0/m, z0\.s
--.*: 049ca01f fabs z31\.s, p0/m, z0\.s
--.*: 049ca01f fabs z31\.s, p0/m, z0\.s
--.*: 049ca800 fabs z0\.s, p2/m, z0\.s
--.*: 049ca800 fabs z0\.s, p2/m, z0\.s
--.*: 049cbc00 fabs z0\.s, p7/m, z0\.s
--.*: 049cbc00 fabs z0\.s, p7/m, z0\.s
--.*: 049ca060 fabs z0\.s, p0/m, z3\.s
--.*: 049ca060 fabs z0\.s, p0/m, z3\.s
--.*: 049ca3e0 fabs z0\.s, p0/m, z31\.s
--.*: 049ca3e0 fabs z0\.s, p0/m, z31\.s
--.*: 04dca000 fabs z0\.d, p0/m, z0\.d
--.*: 04dca000 fabs z0\.d, p0/m, z0\.d
--.*: 04dca001 fabs z1\.d, p0/m, z0\.d
--.*: 04dca001 fabs z1\.d, p0/m, z0\.d
--.*: 04dca01f fabs z31\.d, p0/m, z0\.d
--.*: 04dca01f fabs z31\.d, p0/m, z0\.d
--.*: 04dca800 fabs z0\.d, p2/m, z0\.d
--.*: 04dca800 fabs z0\.d, p2/m, z0\.d
--.*: 04dcbc00 fabs z0\.d, p7/m, z0\.d
--.*: 04dcbc00 fabs z0\.d, p7/m, z0\.d
--.*: 04dca060 fabs z0\.d, p0/m, z3\.d
--.*: 04dca060 fabs z0\.d, p0/m, z3\.d
--.*: 04dca3e0 fabs z0\.d, p0/m, z31\.d
--.*: 04dca3e0 fabs z0\.d, p0/m, z31\.d
--.*: 6540c010 facge p0\.h, p0/z, z0\.h, z0\.h
--.*: 6540c010 facge p0\.h, p0/z, z0\.h, z0\.h
--.*: 6540c011 facge p1\.h, p0/z, z0\.h, z0\.h
--.*: 6540c011 facge p1\.h, p0/z, z0\.h, z0\.h
--.*: 6540c01f facge p15\.h, p0/z, z0\.h, z0\.h
--.*: 6540c01f facge p15\.h, p0/z, z0\.h, z0\.h
--.*: 6540c810 facge p0\.h, p2/z, z0\.h, z0\.h
--.*: 6540c810 facge p0\.h, p2/z, z0\.h, z0\.h
--.*: 6540dc10 facge p0\.h, p7/z, z0\.h, z0\.h
--.*: 6540dc10 facge p0\.h, p7/z, z0\.h, z0\.h
--.*: 6540c070 facge p0\.h, p0/z, z3\.h, z0\.h
--.*: 6540c070 facge p0\.h, p0/z, z3\.h, z0\.h
--.*: 6540c3f0 facge p0\.h, p0/z, z31\.h, z0\.h
--.*: 6540c3f0 facge p0\.h, p0/z, z31\.h, z0\.h
--.*: 6544c010 facge p0\.h, p0/z, z0\.h, z4\.h
--.*: 6544c010 facge p0\.h, p0/z, z0\.h, z4\.h
--.*: 655fc010 facge p0\.h, p0/z, z0\.h, z31\.h
--.*: 655fc010 facge p0\.h, p0/z, z0\.h, z31\.h
--.*: 6580c010 facge p0\.s, p0/z, z0\.s, z0\.s
--.*: 6580c010 facge p0\.s, p0/z, z0\.s, z0\.s
--.*: 6580c011 facge p1\.s, p0/z, z0\.s, z0\.s
--.*: 6580c011 facge p1\.s, p0/z, z0\.s, z0\.s
--.*: 6580c01f facge p15\.s, p0/z, z0\.s, z0\.s
--.*: 6580c01f facge p15\.s, p0/z, z0\.s, z0\.s
--.*: 6580c810 facge p0\.s, p2/z, z0\.s, z0\.s
--.*: 6580c810 facge p0\.s, p2/z, z0\.s, z0\.s
--.*: 6580dc10 facge p0\.s, p7/z, z0\.s, z0\.s
--.*: 6580dc10 facge p0\.s, p7/z, z0\.s, z0\.s
--.*: 6580c070 facge p0\.s, p0/z, z3\.s, z0\.s
--.*: 6580c070 facge p0\.s, p0/z, z3\.s, z0\.s
--.*: 6580c3f0 facge p0\.s, p0/z, z31\.s, z0\.s
--.*: 6580c3f0 facge p0\.s, p0/z, z31\.s, z0\.s
--.*: 6584c010 facge p0\.s, p0/z, z0\.s, z4\.s
--.*: 6584c010 facge p0\.s, p0/z, z0\.s, z4\.s
--.*: 659fc010 facge p0\.s, p0/z, z0\.s, z31\.s
--.*: 659fc010 facge p0\.s, p0/z, z0\.s, z31\.s
--.*: 65c0c010 facge p0\.d, p0/z, z0\.d, z0\.d
--.*: 65c0c010 facge p0\.d, p0/z, z0\.d, z0\.d
--.*: 65c0c011 facge p1\.d, p0/z, z0\.d, z0\.d
--.*: 65c0c011 facge p1\.d, p0/z, z0\.d, z0\.d
--.*: 65c0c01f facge p15\.d, p0/z, z0\.d, z0\.d
--.*: 65c0c01f facge p15\.d, p0/z, z0\.d, z0\.d
--.*: 65c0c810 facge p0\.d, p2/z, z0\.d, z0\.d
--.*: 65c0c810 facge p0\.d, p2/z, z0\.d, z0\.d
--.*: 65c0dc10 facge p0\.d, p7/z, z0\.d, z0\.d
--.*: 65c0dc10 facge p0\.d, p7/z, z0\.d, z0\.d
--.*: 65c0c070 facge p0\.d, p0/z, z3\.d, z0\.d
--.*: 65c0c070 facge p0\.d, p0/z, z3\.d, z0\.d
--.*: 65c0c3f0 facge p0\.d, p0/z, z31\.d, z0\.d
--.*: 65c0c3f0 facge p0\.d, p0/z, z31\.d, z0\.d
--.*: 65c4c010 facge p0\.d, p0/z, z0\.d, z4\.d
--.*: 65c4c010 facge p0\.d, p0/z, z0\.d, z4\.d
--.*: 65dfc010 facge p0\.d, p0/z, z0\.d, z31\.d
--.*: 65dfc010 facge p0\.d, p0/z, z0\.d, z31\.d
--.*: 6540e010 facgt p0\.h, p0/z, z0\.h, z0\.h
--.*: 6540e010 facgt p0\.h, p0/z, z0\.h, z0\.h
--.*: 6540e011 facgt p1\.h, p0/z, z0\.h, z0\.h
--.*: 6540e011 facgt p1\.h, p0/z, z0\.h, z0\.h
--.*: 6540e01f facgt p15\.h, p0/z, z0\.h, z0\.h
--.*: 6540e01f facgt p15\.h, p0/z, z0\.h, z0\.h
--.*: 6540e810 facgt p0\.h, p2/z, z0\.h, z0\.h
--.*: 6540e810 facgt p0\.h, p2/z, z0\.h, z0\.h
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--.*: 65802060 faddv s0, p0, z3\.s
--.*: 65802060 faddv s0, p0, z3\.s
--.*: 658023e0 faddv s0, p0, z31\.s
--.*: 658023e0 faddv s0, p0, z31\.s
--.*: 65c02000 faddv d0, p0, z0\.d
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--.*: 65c02001 faddv d1, p0, z0\.d
--.*: 65c0201f faddv d31, p0, z0\.d
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--.*: 65c02800 faddv d0, p2, z0\.d
--.*: 65c02800 faddv d0, p2, z0\.d
--.*: 65c03c00 faddv d0, p7, z0\.d
--.*: 65c03c00 faddv d0, p7, z0\.d
--.*: 65c02060 faddv d0, p0, z3\.d
--.*: 65c02060 faddv d0, p0, z3\.d
--.*: 65c023e0 faddv d0, p0, z31\.d
--.*: 65c023e0 faddv d0, p0, z31\.d
--.*: 64408000 fcadd z0\.h, p0/m, z0\.h, z0\.h, #90
--.*: 64408000 fcadd z0\.h, p0/m, z0\.h, z0\.h, #90
--.*: 64408001 fcadd z1\.h, p0/m, z1\.h, z0\.h, #90
--.*: 64408001 fcadd z1\.h, p0/m, z1\.h, z0\.h, #90
--.*: 6440801f fcadd z31\.h, p0/m, z31\.h, z0\.h, #90
--.*: 6440801f fcadd z31\.h, p0/m, z31\.h, z0\.h, #90
--.*: 64408800 fcadd z0\.h, p2/m, z0\.h, z0\.h, #90
--.*: 64408800 fcadd z0\.h, p2/m, z0\.h, z0\.h, #90
--.*: 64409c00 fcadd z0\.h, p7/m, z0\.h, z0\.h, #90
--.*: 64409c00 fcadd z0\.h, p7/m, z0\.h, z0\.h, #90
--.*: 64408003 fcadd z3\.h, p0/m, z3\.h, z0\.h, #90
--.*: 64408003 fcadd z3\.h, p0/m, z3\.h, z0\.h, #90
--.*: 64408080 fcadd z0\.h, p0/m, z0\.h, z4\.h, #90
--.*: 64408080 fcadd z0\.h, p0/m, z0\.h, z4\.h, #90
--.*: 644083e0 fcadd z0\.h, p0/m, z0\.h, z31\.h, #90
--.*: 644083e0 fcadd z0\.h, p0/m, z0\.h, z31\.h, #90
--.*: 64418000 fcadd z0\.h, p0/m, z0\.h, z0\.h, #270
--.*: 64418000 fcadd z0\.h, p0/m, z0\.h, z0\.h, #270
--.*: 64808000 fcadd z0\.s, p0/m, z0\.s, z0\.s, #90
--.*: 64808000 fcadd z0\.s, p0/m, z0\.s, z0\.s, #90
--.*: 64808001 fcadd z1\.s, p0/m, z1\.s, z0\.s, #90
--.*: 64808001 fcadd z1\.s, p0/m, z1\.s, z0\.s, #90
--.*: 6480801f fcadd z31\.s, p0/m, z31\.s, z0\.s, #90
--.*: 6480801f fcadd z31\.s, p0/m, z31\.s, z0\.s, #90
--.*: 64808800 fcadd z0\.s, p2/m, z0\.s, z0\.s, #90
--.*: 64808800 fcadd z0\.s, p2/m, z0\.s, z0\.s, #90
--.*: 64809c00 fcadd z0\.s, p7/m, z0\.s, z0\.s, #90
--.*: 64809c00 fcadd z0\.s, p7/m, z0\.s, z0\.s, #90
--.*: 64808003 fcadd z3\.s, p0/m, z3\.s, z0\.s, #90
--.*: 64808003 fcadd z3\.s, p0/m, z3\.s, z0\.s, #90
--.*: 64808080 fcadd z0\.s, p0/m, z0\.s, z4\.s, #90
--.*: 64808080 fcadd z0\.s, p0/m, z0\.s, z4\.s, #90
--.*: 648083e0 fcadd z0\.s, p0/m, z0\.s, z31\.s, #90
--.*: 648083e0 fcadd z0\.s, p0/m, z0\.s, z31\.s, #90
--.*: 64818000 fcadd z0\.s, p0/m, z0\.s, z0\.s, #270
--.*: 64818000 fcadd z0\.s, p0/m, z0\.s, z0\.s, #270
--.*: 64c08000 fcadd z0\.d, p0/m, z0\.d, z0\.d, #90
--.*: 64c08000 fcadd z0\.d, p0/m, z0\.d, z0\.d, #90
--.*: 64c08001 fcadd z1\.d, p0/m, z1\.d, z0\.d, #90
--.*: 64c08001 fcadd z1\.d, p0/m, z1\.d, z0\.d, #90
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--.*: 64c0801f fcadd z31\.d, p0/m, z31\.d, z0\.d, #90
--.*: 64c08800 fcadd z0\.d, p2/m, z0\.d, z0\.d, #90
--.*: 64c08800 fcadd z0\.d, p2/m, z0\.d, z0\.d, #90
--.*: 64c09c00 fcadd z0\.d, p7/m, z0\.d, z0\.d, #90
--.*: 64c09c00 fcadd z0\.d, p7/m, z0\.d, z0\.d, #90
--.*: 64c08003 fcadd z3\.d, p0/m, z3\.d, z0\.d, #90
--.*: 64c08003 fcadd z3\.d, p0/m, z3\.d, z0\.d, #90
--.*: 64c08080 fcadd z0\.d, p0/m, z0\.d, z4\.d, #90
--.*: 64c08080 fcadd z0\.d, p0/m, z0\.d, z4\.d, #90
--.*: 64c083e0 fcadd z0\.d, p0/m, z0\.d, z31\.d, #90
--.*: 64c083e0 fcadd z0\.d, p0/m, z0\.d, z31\.d, #90
--.*: 64c18000 fcadd z0\.d, p0/m, z0\.d, z0\.d, #270
--.*: 64c18000 fcadd z0\.d, p0/m, z0\.d, z0\.d, #270
--.*: 64400000 fcmla z0\.h, p0/m, z0\.h, z0\.h, #0
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--.*: 64400001 fcmla z1\.h, p0/m, z0\.h, z0\.h, #0
--.*: 6440001f fcmla z31\.h, p0/m, z0\.h, z0\.h, #0
--.*: 6440001f fcmla z31\.h, p0/m, z0\.h, z0\.h, #0
--.*: 64400800 fcmla z0\.h, p2/m, z0\.h, z0\.h, #0
--.*: 64400800 fcmla z0\.h, p2/m, z0\.h, z0\.h, #0
--.*: 64401c00 fcmla z0\.h, p7/m, z0\.h, z0\.h, #0
--.*: 64401c00 fcmla z0\.h, p7/m, z0\.h, z0\.h, #0
--.*: 64400060 fcmla z0\.h, p0/m, z3\.h, z0\.h, #0
--.*: 64400060 fcmla z0\.h, p0/m, z3\.h, z0\.h, #0
--.*: 644003e0 fcmla z0\.h, p0/m, z31\.h, z0\.h, #0
--.*: 644003e0 fcmla z0\.h, p0/m, z31\.h, z0\.h, #0
--.*: 64440000 fcmla z0\.h, p0/m, z0\.h, z4\.h, #0
--.*: 64440000 fcmla z0\.h, p0/m, z0\.h, z4\.h, #0
--.*: 645f0000 fcmla z0\.h, p0/m, z0\.h, z31\.h, #0
--.*: 645f0000 fcmla z0\.h, p0/m, z0\.h, z31\.h, #0
--.*: 64402000 fcmla z0\.h, p0/m, z0\.h, z0\.h, #90
--.*: 64402000 fcmla z0\.h, p0/m, z0\.h, z0\.h, #90
--.*: 64404000 fcmla z0\.h, p0/m, z0\.h, z0\.h, #180
--.*: 64404000 fcmla z0\.h, p0/m, z0\.h, z0\.h, #180
--.*: 64406000 fcmla z0\.h, p0/m, z0\.h, z0\.h, #270
--.*: 64406000 fcmla z0\.h, p0/m, z0\.h, z0\.h, #270
--.*: 64800000 fcmla z0\.s, p0/m, z0\.s, z0\.s, #0
--.*: 64800000 fcmla z0\.s, p0/m, z0\.s, z0\.s, #0
--.*: 64800001 fcmla z1\.s, p0/m, z0\.s, z0\.s, #0
--.*: 64800001 fcmla z1\.s, p0/m, z0\.s, z0\.s, #0
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--.*: 6480001f fcmla z31\.s, p0/m, z0\.s, z0\.s, #0
--.*: 64800800 fcmla z0\.s, p2/m, z0\.s, z0\.s, #0
--.*: 64800800 fcmla z0\.s, p2/m, z0\.s, z0\.s, #0
--.*: 64801c00 fcmla z0\.s, p7/m, z0\.s, z0\.s, #0
--.*: 64801c00 fcmla z0\.s, p7/m, z0\.s, z0\.s, #0
--.*: 64800060 fcmla z0\.s, p0/m, z3\.s, z0\.s, #0
--.*: 64800060 fcmla z0\.s, p0/m, z3\.s, z0\.s, #0
--.*: 648003e0 fcmla z0\.s, p0/m, z31\.s, z0\.s, #0
--.*: 648003e0 fcmla z0\.s, p0/m, z31\.s, z0\.s, #0
--.*: 64840000 fcmla z0\.s, p0/m, z0\.s, z4\.s, #0
--.*: 64840000 fcmla z0\.s, p0/m, z0\.s, z4\.s, #0
--.*: 649f0000 fcmla z0\.s, p0/m, z0\.s, z31\.s, #0
--.*: 649f0000 fcmla z0\.s, p0/m, z0\.s, z31\.s, #0
--.*: 64802000 fcmla z0\.s, p0/m, z0\.s, z0\.s, #90
--.*: 64802000 fcmla z0\.s, p0/m, z0\.s, z0\.s, #90
--.*: 64804000 fcmla z0\.s, p0/m, z0\.s, z0\.s, #180
--.*: 64804000 fcmla z0\.s, p0/m, z0\.s, z0\.s, #180
--.*: 64806000 fcmla z0\.s, p0/m, z0\.s, z0\.s, #270
--.*: 64806000 fcmla z0\.s, p0/m, z0\.s, z0\.s, #270
--.*: 64c00000 fcmla z0\.d, p0/m, z0\.d, z0\.d, #0
--.*: 64c00000 fcmla z0\.d, p0/m, z0\.d, z0\.d, #0
--.*: 64c00001 fcmla z1\.d, p0/m, z0\.d, z0\.d, #0
--.*: 64c00001 fcmla z1\.d, p0/m, z0\.d, z0\.d, #0
--.*: 64c0001f fcmla z31\.d, p0/m, z0\.d, z0\.d, #0
--.*: 64c0001f fcmla z31\.d, p0/m, z0\.d, z0\.d, #0
--.*: 64c00800 fcmla z0\.d, p2/m, z0\.d, z0\.d, #0
--.*: 64c00800 fcmla z0\.d, p2/m, z0\.d, z0\.d, #0
--.*: 64c01c00 fcmla z0\.d, p7/m, z0\.d, z0\.d, #0
--.*: 64c01c00 fcmla z0\.d, p7/m, z0\.d, z0\.d, #0
--.*: 64c00060 fcmla z0\.d, p0/m, z3\.d, z0\.d, #0
--.*: 64c00060 fcmla z0\.d, p0/m, z3\.d, z0\.d, #0
--.*: 64c003e0 fcmla z0\.d, p0/m, z31\.d, z0\.d, #0
--.*: 64c003e0 fcmla z0\.d, p0/m, z31\.d, z0\.d, #0
--.*: 64c40000 fcmla z0\.d, p0/m, z0\.d, z4\.d, #0
--.*: 64c40000 fcmla z0\.d, p0/m, z0\.d, z4\.d, #0
--.*: 64df0000 fcmla z0\.d, p0/m, z0\.d, z31\.d, #0
--.*: 64df0000 fcmla z0\.d, p0/m, z0\.d, z31\.d, #0
--.*: 64c02000 fcmla z0\.d, p0/m, z0\.d, z0\.d, #90
--.*: 64c02000 fcmla z0\.d, p0/m, z0\.d, z0\.d, #90
--.*: 64c04000 fcmla z0\.d, p0/m, z0\.d, z0\.d, #180
--.*: 64c04000 fcmla z0\.d, p0/m, z0\.d, z0\.d, #180
--.*: 64c06000 fcmla z0\.d, p0/m, z0\.d, z0\.d, #270
--.*: 64c06000 fcmla z0\.d, p0/m, z0\.d, z0\.d, #270
--.*: 64a01000 fcmla z0\.h, z0\.h, z0\.h\[0\], #0
--.*: 64a01000 fcmla z0\.h, z0\.h, z0\.h\[0\], #0
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--.*: 65406800 fcmeq p0\.h, p2/z, z0\.h, z0\.h
--.*: 65406800 fcmeq p0\.h, p2/z, z0\.h, z0\.h
--.*: 65407c00 fcmeq p0\.h, p7/z, z0\.h, z0\.h
--.*: 65407c00 fcmeq p0\.h, p7/z, z0\.h, z0\.h
--.*: 65406060 fcmeq p0\.h, p0/z, z3\.h, z0\.h
--.*: 65406060 fcmeq p0\.h, p0/z, z3\.h, z0\.h
--.*: 654063e0 fcmeq p0\.h, p0/z, z31\.h, z0\.h
--.*: 654063e0 fcmeq p0\.h, p0/z, z31\.h, z0\.h
--.*: 65446000 fcmeq p0\.h, p0/z, z0\.h, z4\.h
--.*: 65446000 fcmeq p0\.h, p0/z, z0\.h, z4\.h
--.*: 655f6000 fcmeq p0\.h, p0/z, z0\.h, z31\.h
--.*: 655f6000 fcmeq p0\.h, p0/z, z0\.h, z31\.h
--.*: 65806000 fcmeq p0\.s, p0/z, z0\.s, z0\.s
--.*: 65806000 fcmeq p0\.s, p0/z, z0\.s, z0\.s
--.*: 65806001 fcmeq p1\.s, p0/z, z0\.s, z0\.s
--.*: 65806001 fcmeq p1\.s, p0/z, z0\.s, z0\.s
--.*: 6580600f fcmeq p15\.s, p0/z, z0\.s, z0\.s
--.*: 6580600f fcmeq p15\.s, p0/z, z0\.s, z0\.s
--.*: 65806800 fcmeq p0\.s, p2/z, z0\.s, z0\.s
--.*: 65806800 fcmeq p0\.s, p2/z, z0\.s, z0\.s
--.*: 65807c00 fcmeq p0\.s, p7/z, z0\.s, z0\.s
--.*: 65807c00 fcmeq p0\.s, p7/z, z0\.s, z0\.s
--.*: 65806060 fcmeq p0\.s, p0/z, z3\.s, z0\.s
--.*: 65806060 fcmeq p0\.s, p0/z, z3\.s, z0\.s
--.*: 658063e0 fcmeq p0\.s, p0/z, z31\.s, z0\.s
--.*: 658063e0 fcmeq p0\.s, p0/z, z31\.s, z0\.s
--.*: 65846000 fcmeq p0\.s, p0/z, z0\.s, z4\.s
--.*: 65846000 fcmeq p0\.s, p0/z, z0\.s, z4\.s
--.*: 659f6000 fcmeq p0\.s, p0/z, z0\.s, z31\.s
--.*: 659f6000 fcmeq p0\.s, p0/z, z0\.s, z31\.s
--.*: 65c06000 fcmeq p0\.d, p0/z, z0\.d, z0\.d
--.*: 65c06000 fcmeq p0\.d, p0/z, z0\.d, z0\.d
--.*: 65c06001 fcmeq p1\.d, p0/z, z0\.d, z0\.d
--.*: 65c06001 fcmeq p1\.d, p0/z, z0\.d, z0\.d
--.*: 65c0600f fcmeq p15\.d, p0/z, z0\.d, z0\.d
--.*: 65c0600f fcmeq p15\.d, p0/z, z0\.d, z0\.d
--.*: 65c06800 fcmeq p0\.d, p2/z, z0\.d, z0\.d
--.*: 65c06800 fcmeq p0\.d, p2/z, z0\.d, z0\.d
--.*: 65c07c00 fcmeq p0\.d, p7/z, z0\.d, z0\.d
--.*: 65c07c00 fcmeq p0\.d, p7/z, z0\.d, z0\.d
--.*: 65c06060 fcmeq p0\.d, p0/z, z3\.d, z0\.d
--.*: 65c06060 fcmeq p0\.d, p0/z, z3\.d, z0\.d
--.*: 65c063e0 fcmeq p0\.d, p0/z, z31\.d, z0\.d
--.*: 65c063e0 fcmeq p0\.d, p0/z, z31\.d, z0\.d
--.*: 65c46000 fcmeq p0\.d, p0/z, z0\.d, z4\.d
--.*: 65c46000 fcmeq p0\.d, p0/z, z0\.d, z4\.d
--.*: 65df6000 fcmeq p0\.d, p0/z, z0\.d, z31\.d
--.*: 65df6000 fcmeq p0\.d, p0/z, z0\.d, z31\.d
--.*: 65502000 fcmge p0\.h, p0/z, z0\.h, #0\.0
--.*: 65502000 fcmge p0\.h, p0/z, z0\.h, #0\.0
--.*: 65502001 fcmge p1\.h, p0/z, z0\.h, #0\.0
--.*: 65502001 fcmge p1\.h, p0/z, z0\.h, #0\.0
--.*: 6550200f fcmge p15\.h, p0/z, z0\.h, #0\.0
--.*: 6550200f fcmge p15\.h, p0/z, z0\.h, #0\.0
--.*: 65502800 fcmge p0\.h, p2/z, z0\.h, #0\.0
--.*: 65502800 fcmge p0\.h, p2/z, z0\.h, #0\.0
--.*: 65503c00 fcmge p0\.h, p7/z, z0\.h, #0\.0
--.*: 65503c00 fcmge p0\.h, p7/z, z0\.h, #0\.0
--.*: 65502060 fcmge p0\.h, p0/z, z3\.h, #0\.0
--.*: 65502060 fcmge p0\.h, p0/z, z3\.h, #0\.0
--.*: 655023e0 fcmge p0\.h, p0/z, z31\.h, #0\.0
--.*: 655023e0 fcmge p0\.h, p0/z, z31\.h, #0\.0
--.*: 65902000 fcmge p0\.s, p0/z, z0\.s, #0\.0
--.*: 65902000 fcmge p0\.s, p0/z, z0\.s, #0\.0
--.*: 65902001 fcmge p1\.s, p0/z, z0\.s, #0\.0
--.*: 65902001 fcmge p1\.s, p0/z, z0\.s, #0\.0
--.*: 6590200f fcmge p15\.s, p0/z, z0\.s, #0\.0
--.*: 6590200f fcmge p15\.s, p0/z, z0\.s, #0\.0
--.*: 65902800 fcmge p0\.s, p2/z, z0\.s, #0\.0
--.*: 65902800 fcmge p0\.s, p2/z, z0\.s, #0\.0
--.*: 65903c00 fcmge p0\.s, p7/z, z0\.s, #0\.0
--.*: 65903c00 fcmge p0\.s, p7/z, z0\.s, #0\.0
--.*: 65902060 fcmge p0\.s, p0/z, z3\.s, #0\.0
--.*: 65902060 fcmge p0\.s, p0/z, z3\.s, #0\.0
--.*: 659023e0 fcmge p0\.s, p0/z, z31\.s, #0\.0
--.*: 659023e0 fcmge p0\.s, p0/z, z31\.s, #0\.0
--.*: 65d02000 fcmge p0\.d, p0/z, z0\.d, #0\.0
--.*: 65d02000 fcmge p0\.d, p0/z, z0\.d, #0\.0
--.*: 65d02001 fcmge p1\.d, p0/z, z0\.d, #0\.0
--.*: 65d02001 fcmge p1\.d, p0/z, z0\.d, #0\.0
--.*: 65d0200f fcmge p15\.d, p0/z, z0\.d, #0\.0
--.*: 65d0200f fcmge p15\.d, p0/z, z0\.d, #0\.0
--.*: 65d02800 fcmge p0\.d, p2/z, z0\.d, #0\.0
--.*: 65d02800 fcmge p0\.d, p2/z, z0\.d, #0\.0
--.*: 65d03c00 fcmge p0\.d, p7/z, z0\.d, #0\.0
--.*: 65d03c00 fcmge p0\.d, p7/z, z0\.d, #0\.0
--.*: 65d02060 fcmge p0\.d, p0/z, z3\.d, #0\.0
--.*: 65d02060 fcmge p0\.d, p0/z, z3\.d, #0\.0
--.*: 65d023e0 fcmge p0\.d, p0/z, z31\.d, #0\.0
--.*: 65d023e0 fcmge p0\.d, p0/z, z31\.d, #0\.0
--.*: 65404000 fcmge p0\.h, p0/z, z0\.h, z0\.h
--.*: 65404000 fcmge p0\.h, p0/z, z0\.h, z0\.h
--.*: 65404001 fcmge p1\.h, p0/z, z0\.h, z0\.h
--.*: 65404001 fcmge p1\.h, p0/z, z0\.h, z0\.h
--.*: 6540400f fcmge p15\.h, p0/z, z0\.h, z0\.h
--.*: 6540400f fcmge p15\.h, p0/z, z0\.h, z0\.h
--.*: 65404800 fcmge p0\.h, p2/z, z0\.h, z0\.h
--.*: 65404800 fcmge p0\.h, p2/z, z0\.h, z0\.h
--.*: 65405c00 fcmge p0\.h, p7/z, z0\.h, z0\.h
--.*: 65405c00 fcmge p0\.h, p7/z, z0\.h, z0\.h
--.*: 65404060 fcmge p0\.h, p0/z, z3\.h, z0\.h
--.*: 65404060 fcmge p0\.h, p0/z, z3\.h, z0\.h
--.*: 654043e0 fcmge p0\.h, p0/z, z31\.h, z0\.h
--.*: 654043e0 fcmge p0\.h, p0/z, z31\.h, z0\.h
--.*: 65444000 fcmge p0\.h, p0/z, z0\.h, z4\.h
--.*: 65444000 fcmge p0\.h, p0/z, z0\.h, z4\.h
--.*: 655f4000 fcmge p0\.h, p0/z, z0\.h, z31\.h
--.*: 655f4000 fcmge p0\.h, p0/z, z0\.h, z31\.h
--.*: 65804000 fcmge p0\.s, p0/z, z0\.s, z0\.s
--.*: 65804000 fcmge p0\.s, p0/z, z0\.s, z0\.s
--.*: 65804001 fcmge p1\.s, p0/z, z0\.s, z0\.s
--.*: 65804001 fcmge p1\.s, p0/z, z0\.s, z0\.s
--.*: 6580400f fcmge p15\.s, p0/z, z0\.s, z0\.s
--.*: 6580400f fcmge p15\.s, p0/z, z0\.s, z0\.s
--.*: 65804800 fcmge p0\.s, p2/z, z0\.s, z0\.s
--.*: 65804800 fcmge p0\.s, p2/z, z0\.s, z0\.s
--.*: 65805c00 fcmge p0\.s, p7/z, z0\.s, z0\.s
--.*: 65805c00 fcmge p0\.s, p7/z, z0\.s, z0\.s
--.*: 65804060 fcmge p0\.s, p0/z, z3\.s, z0\.s
--.*: 65804060 fcmge p0\.s, p0/z, z3\.s, z0\.s
--.*: 658043e0 fcmge p0\.s, p0/z, z31\.s, z0\.s
--.*: 658043e0 fcmge p0\.s, p0/z, z31\.s, z0\.s
--.*: 65844000 fcmge p0\.s, p0/z, z0\.s, z4\.s
--.*: 65844000 fcmge p0\.s, p0/z, z0\.s, z4\.s
--.*: 659f4000 fcmge p0\.s, p0/z, z0\.s, z31\.s
--.*: 659f4000 fcmge p0\.s, p0/z, z0\.s, z31\.s
--.*: 65c04000 fcmge p0\.d, p0/z, z0\.d, z0\.d
--.*: 65c04000 fcmge p0\.d, p0/z, z0\.d, z0\.d
--.*: 65c04001 fcmge p1\.d, p0/z, z0\.d, z0\.d
--.*: 65c04001 fcmge p1\.d, p0/z, z0\.d, z0\.d
--.*: 65c0400f fcmge p15\.d, p0/z, z0\.d, z0\.d
--.*: 65c0400f fcmge p15\.d, p0/z, z0\.d, z0\.d
--.*: 65c04800 fcmge p0\.d, p2/z, z0\.d, z0\.d
--.*: 65c04800 fcmge p0\.d, p2/z, z0\.d, z0\.d
--.*: 65c05c00 fcmge p0\.d, p7/z, z0\.d, z0\.d
--.*: 65c05c00 fcmge p0\.d, p7/z, z0\.d, z0\.d
--.*: 65c04060 fcmge p0\.d, p0/z, z3\.d, z0\.d
--.*: 65c04060 fcmge p0\.d, p0/z, z3\.d, z0\.d
--.*: 65c043e0 fcmge p0\.d, p0/z, z31\.d, z0\.d
--.*: 65c043e0 fcmge p0\.d, p0/z, z31\.d, z0\.d
--.*: 65c44000 fcmge p0\.d, p0/z, z0\.d, z4\.d
--.*: 65c44000 fcmge p0\.d, p0/z, z0\.d, z4\.d
--.*: 65df4000 fcmge p0\.d, p0/z, z0\.d, z31\.d
--.*: 65df4000 fcmge p0\.d, p0/z, z0\.d, z31\.d
--.*: 65502010 fcmgt p0\.h, p0/z, z0\.h, #0\.0
--.*: 65502010 fcmgt p0\.h, p0/z, z0\.h, #0\.0
--.*: 65502011 fcmgt p1\.h, p0/z, z0\.h, #0\.0
--.*: 65502011 fcmgt p1\.h, p0/z, z0\.h, #0\.0
--.*: 6550201f fcmgt p15\.h, p0/z, z0\.h, #0\.0
--.*: 6550201f fcmgt p15\.h, p0/z, z0\.h, #0\.0
--.*: 65502810 fcmgt p0\.h, p2/z, z0\.h, #0\.0
--.*: 65502810 fcmgt p0\.h, p2/z, z0\.h, #0\.0
--.*: 65503c10 fcmgt p0\.h, p7/z, z0\.h, #0\.0
--.*: 65503c10 fcmgt p0\.h, p7/z, z0\.h, #0\.0
--.*: 65502070 fcmgt p0\.h, p0/z, z3\.h, #0\.0
--.*: 65502070 fcmgt p0\.h, p0/z, z3\.h, #0\.0
--.*: 655023f0 fcmgt p0\.h, p0/z, z31\.h, #0\.0
--.*: 655023f0 fcmgt p0\.h, p0/z, z31\.h, #0\.0
--.*: 65902010 fcmgt p0\.s, p0/z, z0\.s, #0\.0
--.*: 65902010 fcmgt p0\.s, p0/z, z0\.s, #0\.0
--.*: 65902011 fcmgt p1\.s, p0/z, z0\.s, #0\.0
--.*: 65902011 fcmgt p1\.s, p0/z, z0\.s, #0\.0
--.*: 6590201f fcmgt p15\.s, p0/z, z0\.s, #0\.0
--.*: 6590201f fcmgt p15\.s, p0/z, z0\.s, #0\.0
--.*: 65902810 fcmgt p0\.s, p2/z, z0\.s, #0\.0
--.*: 65902810 fcmgt p0\.s, p2/z, z0\.s, #0\.0
--.*: 65903c10 fcmgt p0\.s, p7/z, z0\.s, #0\.0
--.*: 65903c10 fcmgt p0\.s, p7/z, z0\.s, #0\.0
--.*: 65902070 fcmgt p0\.s, p0/z, z3\.s, #0\.0
--.*: 65902070 fcmgt p0\.s, p0/z, z3\.s, #0\.0
--.*: 659023f0 fcmgt p0\.s, p0/z, z31\.s, #0\.0
--.*: 659023f0 fcmgt p0\.s, p0/z, z31\.s, #0\.0
--.*: 65d02010 fcmgt p0\.d, p0/z, z0\.d, #0\.0
--.*: 65d02010 fcmgt p0\.d, p0/z, z0\.d, #0\.0
--.*: 65d02011 fcmgt p1\.d, p0/z, z0\.d, #0\.0
--.*: 65d02011 fcmgt p1\.d, p0/z, z0\.d, #0\.0
--.*: 65d0201f fcmgt p15\.d, p0/z, z0\.d, #0\.0
--.*: 65d0201f fcmgt p15\.d, p0/z, z0\.d, #0\.0
--.*: 65d02810 fcmgt p0\.d, p2/z, z0\.d, #0\.0
--.*: 65d02810 fcmgt p0\.d, p2/z, z0\.d, #0\.0
--.*: 65d03c10 fcmgt p0\.d, p7/z, z0\.d, #0\.0
--.*: 65d03c10 fcmgt p0\.d, p7/z, z0\.d, #0\.0
--.*: 65d02070 fcmgt p0\.d, p0/z, z3\.d, #0\.0
--.*: 65d02070 fcmgt p0\.d, p0/z, z3\.d, #0\.0
--.*: 65d023f0 fcmgt p0\.d, p0/z, z31\.d, #0\.0
--.*: 65d023f0 fcmgt p0\.d, p0/z, z31\.d, #0\.0
--.*: 65404010 fcmgt p0\.h, p0/z, z0\.h, z0\.h
--.*: 65404010 fcmgt p0\.h, p0/z, z0\.h, z0\.h
--.*: 65404011 fcmgt p1\.h, p0/z, z0\.h, z0\.h
--.*: 65404011 fcmgt p1\.h, p0/z, z0\.h, z0\.h
--.*: 6540401f fcmgt p15\.h, p0/z, z0\.h, z0\.h
--.*: 6540401f fcmgt p15\.h, p0/z, z0\.h, z0\.h
--.*: 65404810 fcmgt p0\.h, p2/z, z0\.h, z0\.h
--.*: 65404810 fcmgt p0\.h, p2/z, z0\.h, z0\.h
--.*: 65405c10 fcmgt p0\.h, p7/z, z0\.h, z0\.h
--.*: 65405c10 fcmgt p0\.h, p7/z, z0\.h, z0\.h
--.*: 65404070 fcmgt p0\.h, p0/z, z3\.h, z0\.h
--.*: 65404070 fcmgt p0\.h, p0/z, z3\.h, z0\.h
--.*: 654043f0 fcmgt p0\.h, p0/z, z31\.h, z0\.h
--.*: 654043f0 fcmgt p0\.h, p0/z, z31\.h, z0\.h
--.*: 65444010 fcmgt p0\.h, p0/z, z0\.h, z4\.h
--.*: 65444010 fcmgt p0\.h, p0/z, z0\.h, z4\.h
--.*: 655f4010 fcmgt p0\.h, p0/z, z0\.h, z31\.h
--.*: 655f4010 fcmgt p0\.h, p0/z, z0\.h, z31\.h
--.*: 65804010 fcmgt p0\.s, p0/z, z0\.s, z0\.s
--.*: 65804010 fcmgt p0\.s, p0/z, z0\.s, z0\.s
--.*: 65804011 fcmgt p1\.s, p0/z, z0\.s, z0\.s
--.*: 65804011 fcmgt p1\.s, p0/z, z0\.s, z0\.s
--.*: 6580401f fcmgt p15\.s, p0/z, z0\.s, z0\.s
--.*: 6580401f fcmgt p15\.s, p0/z, z0\.s, z0\.s
--.*: 65804810 fcmgt p0\.s, p2/z, z0\.s, z0\.s
--.*: 65804810 fcmgt p0\.s, p2/z, z0\.s, z0\.s
--.*: 65805c10 fcmgt p0\.s, p7/z, z0\.s, z0\.s
--.*: 65805c10 fcmgt p0\.s, p7/z, z0\.s, z0\.s
--.*: 65804070 fcmgt p0\.s, p0/z, z3\.s, z0\.s
--.*: 65804070 fcmgt p0\.s, p0/z, z3\.s, z0\.s
--.*: 658043f0 fcmgt p0\.s, p0/z, z31\.s, z0\.s
--.*: 658043f0 fcmgt p0\.s, p0/z, z31\.s, z0\.s
--.*: 65844010 fcmgt p0\.s, p0/z, z0\.s, z4\.s
--.*: 65844010 fcmgt p0\.s, p0/z, z0\.s, z4\.s
--.*: 659f4010 fcmgt p0\.s, p0/z, z0\.s, z31\.s
--.*: 659f4010 fcmgt p0\.s, p0/z, z0\.s, z31\.s
--.*: 65c04010 fcmgt p0\.d, p0/z, z0\.d, z0\.d
--.*: 65c04010 fcmgt p0\.d, p0/z, z0\.d, z0\.d
--.*: 65c04011 fcmgt p1\.d, p0/z, z0\.d, z0\.d
--.*: 65c04011 fcmgt p1\.d, p0/z, z0\.d, z0\.d
--.*: 65c0401f fcmgt p15\.d, p0/z, z0\.d, z0\.d
--.*: 65c0401f fcmgt p15\.d, p0/z, z0\.d, z0\.d
--.*: 65c04810 fcmgt p0\.d, p2/z, z0\.d, z0\.d
--.*: 65c04810 fcmgt p0\.d, p2/z, z0\.d, z0\.d
--.*: 65c05c10 fcmgt p0\.d, p7/z, z0\.d, z0\.d
--.*: 65c05c10 fcmgt p0\.d, p7/z, z0\.d, z0\.d
--.*: 65c04070 fcmgt p0\.d, p0/z, z3\.d, z0\.d
--.*: 65c04070 fcmgt p0\.d, p0/z, z3\.d, z0\.d
--.*: 65c043f0 fcmgt p0\.d, p0/z, z31\.d, z0\.d
--.*: 65c043f0 fcmgt p0\.d, p0/z, z31\.d, z0\.d
--.*: 65c44010 fcmgt p0\.d, p0/z, z0\.d, z4\.d
--.*: 65c44010 fcmgt p0\.d, p0/z, z0\.d, z4\.d
--.*: 65df4010 fcmgt p0\.d, p0/z, z0\.d, z31\.d
--.*: 65df4010 fcmgt p0\.d, p0/z, z0\.d, z31\.d
--.*: 65512010 fcmle p0\.h, p0/z, z0\.h, #0\.0
--.*: 65512010 fcmle p0\.h, p0/z, z0\.h, #0\.0
--.*: 65512011 fcmle p1\.h, p0/z, z0\.h, #0\.0
--.*: 65512011 fcmle p1\.h, p0/z, z0\.h, #0\.0
--.*: 6551201f fcmle p15\.h, p0/z, z0\.h, #0\.0
--.*: 6551201f fcmle p15\.h, p0/z, z0\.h, #0\.0
--.*: 65512810 fcmle p0\.h, p2/z, z0\.h, #0\.0
--.*: 65512810 fcmle p0\.h, p2/z, z0\.h, #0\.0
--.*: 65513c10 fcmle p0\.h, p7/z, z0\.h, #0\.0
--.*: 65513c10 fcmle p0\.h, p7/z, z0\.h, #0\.0
--.*: 65512070 fcmle p0\.h, p0/z, z3\.h, #0\.0
--.*: 65512070 fcmle p0\.h, p0/z, z3\.h, #0\.0
--.*: 655123f0 fcmle p0\.h, p0/z, z31\.h, #0\.0
--.*: 655123f0 fcmle p0\.h, p0/z, z31\.h, #0\.0
--.*: 65912010 fcmle p0\.s, p0/z, z0\.s, #0\.0
--.*: 65912010 fcmle p0\.s, p0/z, z0\.s, #0\.0
--.*: 65912011 fcmle p1\.s, p0/z, z0\.s, #0\.0
--.*: 65912011 fcmle p1\.s, p0/z, z0\.s, #0\.0
--.*: 6591201f fcmle p15\.s, p0/z, z0\.s, #0\.0
--.*: 6591201f fcmle p15\.s, p0/z, z0\.s, #0\.0
--.*: 65912810 fcmle p0\.s, p2/z, z0\.s, #0\.0
--.*: 65912810 fcmle p0\.s, p2/z, z0\.s, #0\.0
--.*: 65913c10 fcmle p0\.s, p7/z, z0\.s, #0\.0
--.*: 65913c10 fcmle p0\.s, p7/z, z0\.s, #0\.0
--.*: 65912070 fcmle p0\.s, p0/z, z3\.s, #0\.0
--.*: 65912070 fcmle p0\.s, p0/z, z3\.s, #0\.0
--.*: 659123f0 fcmle p0\.s, p0/z, z31\.s, #0\.0
--.*: 659123f0 fcmle p0\.s, p0/z, z31\.s, #0\.0
--.*: 65d12010 fcmle p0\.d, p0/z, z0\.d, #0\.0
--.*: 65d12010 fcmle p0\.d, p0/z, z0\.d, #0\.0
--.*: 65d12011 fcmle p1\.d, p0/z, z0\.d, #0\.0
--.*: 65d12011 fcmle p1\.d, p0/z, z0\.d, #0\.0
--.*: 65d1201f fcmle p15\.d, p0/z, z0\.d, #0\.0
--.*: 65d1201f fcmle p15\.d, p0/z, z0\.d, #0\.0
--.*: 65d12810 fcmle p0\.d, p2/z, z0\.d, #0\.0
--.*: 65d12810 fcmle p0\.d, p2/z, z0\.d, #0\.0
--.*: 65d13c10 fcmle p0\.d, p7/z, z0\.d, #0\.0
--.*: 65d13c10 fcmle p0\.d, p7/z, z0\.d, #0\.0
--.*: 65d12070 fcmle p0\.d, p0/z, z3\.d, #0\.0
--.*: 65d12070 fcmle p0\.d, p0/z, z3\.d, #0\.0
--.*: 65d123f0 fcmle p0\.d, p0/z, z31\.d, #0\.0
--.*: 65d123f0 fcmle p0\.d, p0/z, z31\.d, #0\.0
--.*: 65512000 fcmlt p0\.h, p0/z, z0\.h, #0\.0
--.*: 65512000 fcmlt p0\.h, p0/z, z0\.h, #0\.0
--.*: 65512001 fcmlt p1\.h, p0/z, z0\.h, #0\.0
--.*: 65512001 fcmlt p1\.h, p0/z, z0\.h, #0\.0
--.*: 6551200f fcmlt p15\.h, p0/z, z0\.h, #0\.0
--.*: 6551200f fcmlt p15\.h, p0/z, z0\.h, #0\.0
--.*: 65512800 fcmlt p0\.h, p2/z, z0\.h, #0\.0
--.*: 65512800 fcmlt p0\.h, p2/z, z0\.h, #0\.0
--.*: 65513c00 fcmlt p0\.h, p7/z, z0\.h, #0\.0
--.*: 65513c00 fcmlt p0\.h, p7/z, z0\.h, #0\.0
--.*: 65512060 fcmlt p0\.h, p0/z, z3\.h, #0\.0
--.*: 65512060 fcmlt p0\.h, p0/z, z3\.h, #0\.0
--.*: 655123e0 fcmlt p0\.h, p0/z, z31\.h, #0\.0
--.*: 655123e0 fcmlt p0\.h, p0/z, z31\.h, #0\.0
--.*: 65912000 fcmlt p0\.s, p0/z, z0\.s, #0\.0
--.*: 65912000 fcmlt p0\.s, p0/z, z0\.s, #0\.0
--.*: 65912001 fcmlt p1\.s, p0/z, z0\.s, #0\.0
--.*: 65912001 fcmlt p1\.s, p0/z, z0\.s, #0\.0
--.*: 6591200f fcmlt p15\.s, p0/z, z0\.s, #0\.0
--.*: 6591200f fcmlt p15\.s, p0/z, z0\.s, #0\.0
--.*: 65912800 fcmlt p0\.s, p2/z, z0\.s, #0\.0
--.*: 65912800 fcmlt p0\.s, p2/z, z0\.s, #0\.0
--.*: 65913c00 fcmlt p0\.s, p7/z, z0\.s, #0\.0
--.*: 65913c00 fcmlt p0\.s, p7/z, z0\.s, #0\.0
--.*: 65912060 fcmlt p0\.s, p0/z, z3\.s, #0\.0
--.*: 65912060 fcmlt p0\.s, p0/z, z3\.s, #0\.0
--.*: 659123e0 fcmlt p0\.s, p0/z, z31\.s, #0\.0
--.*: 659123e0 fcmlt p0\.s, p0/z, z31\.s, #0\.0
--.*: 65d12000 fcmlt p0\.d, p0/z, z0\.d, #0\.0
--.*: 65d12000 fcmlt p0\.d, p0/z, z0\.d, #0\.0
--.*: 65d12001 fcmlt p1\.d, p0/z, z0\.d, #0\.0
--.*: 65d12001 fcmlt p1\.d, p0/z, z0\.d, #0\.0
--.*: 65d1200f fcmlt p15\.d, p0/z, z0\.d, #0\.0
--.*: 65d1200f fcmlt p15\.d, p0/z, z0\.d, #0\.0
--.*: 65d12800 fcmlt p0\.d, p2/z, z0\.d, #0\.0
--.*: 65d12800 fcmlt p0\.d, p2/z, z0\.d, #0\.0
--.*: 65d13c00 fcmlt p0\.d, p7/z, z0\.d, #0\.0
--.*: 65d13c00 fcmlt p0\.d, p7/z, z0\.d, #0\.0
--.*: 65d12060 fcmlt p0\.d, p0/z, z3\.d, #0\.0
--.*: 65d12060 fcmlt p0\.d, p0/z, z3\.d, #0\.0
--.*: 65d123e0 fcmlt p0\.d, p0/z, z31\.d, #0\.0
--.*: 65d123e0 fcmlt p0\.d, p0/z, z31\.d, #0\.0
--.*: 65532000 fcmne p0\.h, p0/z, z0\.h, #0\.0
--.*: 65532000 fcmne p0\.h, p0/z, z0\.h, #0\.0
--.*: 65532001 fcmne p1\.h, p0/z, z0\.h, #0\.0
--.*: 65532001 fcmne p1\.h, p0/z, z0\.h, #0\.0
--.*: 6553200f fcmne p15\.h, p0/z, z0\.h, #0\.0
--.*: 6553200f fcmne p15\.h, p0/z, z0\.h, #0\.0
--.*: 65532800 fcmne p0\.h, p2/z, z0\.h, #0\.0
--.*: 65532800 fcmne p0\.h, p2/z, z0\.h, #0\.0
--.*: 65533c00 fcmne p0\.h, p7/z, z0\.h, #0\.0
--.*: 65533c00 fcmne p0\.h, p7/z, z0\.h, #0\.0
--.*: 65532060 fcmne p0\.h, p0/z, z3\.h, #0\.0
--.*: 65532060 fcmne p0\.h, p0/z, z3\.h, #0\.0
--.*: 655323e0 fcmne p0\.h, p0/z, z31\.h, #0\.0
--.*: 655323e0 fcmne p0\.h, p0/z, z31\.h, #0\.0
--.*: 65932000 fcmne p0\.s, p0/z, z0\.s, #0\.0
--.*: 65932000 fcmne p0\.s, p0/z, z0\.s, #0\.0
--.*: 65932001 fcmne p1\.s, p0/z, z0\.s, #0\.0
--.*: 65932001 fcmne p1\.s, p0/z, z0\.s, #0\.0
--.*: 6593200f fcmne p15\.s, p0/z, z0\.s, #0\.0
--.*: 6593200f fcmne p15\.s, p0/z, z0\.s, #0\.0
--.*: 65932800 fcmne p0\.s, p2/z, z0\.s, #0\.0
--.*: 65932800 fcmne p0\.s, p2/z, z0\.s, #0\.0
--.*: 65933c00 fcmne p0\.s, p7/z, z0\.s, #0\.0
--.*: 65933c00 fcmne p0\.s, p7/z, z0\.s, #0\.0
--.*: 65932060 fcmne p0\.s, p0/z, z3\.s, #0\.0
--.*: 65932060 fcmne p0\.s, p0/z, z3\.s, #0\.0
--.*: 659323e0 fcmne p0\.s, p0/z, z31\.s, #0\.0
--.*: 659323e0 fcmne p0\.s, p0/z, z31\.s, #0\.0
--.*: 65d32000 fcmne p0\.d, p0/z, z0\.d, #0\.0
--.*: 65d32000 fcmne p0\.d, p0/z, z0\.d, #0\.0
--.*: 65d32001 fcmne p1\.d, p0/z, z0\.d, #0\.0
--.*: 65d32001 fcmne p1\.d, p0/z, z0\.d, #0\.0
--.*: 65d3200f fcmne p15\.d, p0/z, z0\.d, #0\.0
--.*: 65d3200f fcmne p15\.d, p0/z, z0\.d, #0\.0
--.*: 65d32800 fcmne p0\.d, p2/z, z0\.d, #0\.0
--.*: 65d32800 fcmne p0\.d, p2/z, z0\.d, #0\.0
--.*: 65d33c00 fcmne p0\.d, p7/z, z0\.d, #0\.0
--.*: 65d33c00 fcmne p0\.d, p7/z, z0\.d, #0\.0
--.*: 65d32060 fcmne p0\.d, p0/z, z3\.d, #0\.0
--.*: 65d32060 fcmne p0\.d, p0/z, z3\.d, #0\.0
--.*: 65d323e0 fcmne p0\.d, p0/z, z31\.d, #0\.0
--.*: 65d323e0 fcmne p0\.d, p0/z, z31\.d, #0\.0
--.*: 65406010 fcmne p0\.h, p0/z, z0\.h, z0\.h
--.*: 65406010 fcmne p0\.h, p0/z, z0\.h, z0\.h
--.*: 65406011 fcmne p1\.h, p0/z, z0\.h, z0\.h
--.*: 65406011 fcmne p1\.h, p0/z, z0\.h, z0\.h
--.*: 6540601f fcmne p15\.h, p0/z, z0\.h, z0\.h
--.*: 6540601f fcmne p15\.h, p0/z, z0\.h, z0\.h
--.*: 65406810 fcmne p0\.h, p2/z, z0\.h, z0\.h
--.*: 65406810 fcmne p0\.h, p2/z, z0\.h, z0\.h
--.*: 65407c10 fcmne p0\.h, p7/z, z0\.h, z0\.h
--.*: 65407c10 fcmne p0\.h, p7/z, z0\.h, z0\.h
--.*: 65406070 fcmne p0\.h, p0/z, z3\.h, z0\.h
--.*: 65406070 fcmne p0\.h, p0/z, z3\.h, z0\.h
--.*: 654063f0 fcmne p0\.h, p0/z, z31\.h, z0\.h
--.*: 654063f0 fcmne p0\.h, p0/z, z31\.h, z0\.h
--.*: 65446010 fcmne p0\.h, p0/z, z0\.h, z4\.h
--.*: 65446010 fcmne p0\.h, p0/z, z0\.h, z4\.h
--.*: 655f6010 fcmne p0\.h, p0/z, z0\.h, z31\.h
--.*: 655f6010 fcmne p0\.h, p0/z, z0\.h, z31\.h
--.*: 65806010 fcmne p0\.s, p0/z, z0\.s, z0\.s
--.*: 65806010 fcmne p0\.s, p0/z, z0\.s, z0\.s
--.*: 65806011 fcmne p1\.s, p0/z, z0\.s, z0\.s
--.*: 65806011 fcmne p1\.s, p0/z, z0\.s, z0\.s
--.*: 6580601f fcmne p15\.s, p0/z, z0\.s, z0\.s
--.*: 6580601f fcmne p15\.s, p0/z, z0\.s, z0\.s
--.*: 65806810 fcmne p0\.s, p2/z, z0\.s, z0\.s
--.*: 65806810 fcmne p0\.s, p2/z, z0\.s, z0\.s
--.*: 65807c10 fcmne p0\.s, p7/z, z0\.s, z0\.s
--.*: 65807c10 fcmne p0\.s, p7/z, z0\.s, z0\.s
--.*: 65806070 fcmne p0\.s, p0/z, z3\.s, z0\.s
--.*: 65806070 fcmne p0\.s, p0/z, z3\.s, z0\.s
--.*: 658063f0 fcmne p0\.s, p0/z, z31\.s, z0\.s
--.*: 658063f0 fcmne p0\.s, p0/z, z31\.s, z0\.s
--.*: 65846010 fcmne p0\.s, p0/z, z0\.s, z4\.s
--.*: 65846010 fcmne p0\.s, p0/z, z0\.s, z4\.s
--.*: 659f6010 fcmne p0\.s, p0/z, z0\.s, z31\.s
--.*: 659f6010 fcmne p0\.s, p0/z, z0\.s, z31\.s
--.*: 65c06010 fcmne p0\.d, p0/z, z0\.d, z0\.d
--.*: 65c06010 fcmne p0\.d, p0/z, z0\.d, z0\.d
--.*: 65c06011 fcmne p1\.d, p0/z, z0\.d, z0\.d
--.*: 65c06011 fcmne p1\.d, p0/z, z0\.d, z0\.d
--.*: 65c0601f fcmne p15\.d, p0/z, z0\.d, z0\.d
--.*: 65c0601f fcmne p15\.d, p0/z, z0\.d, z0\.d
--.*: 65c06810 fcmne p0\.d, p2/z, z0\.d, z0\.d
--.*: 65c06810 fcmne p0\.d, p2/z, z0\.d, z0\.d
--.*: 65c07c10 fcmne p0\.d, p7/z, z0\.d, z0\.d
--.*: 65c07c10 fcmne p0\.d, p7/z, z0\.d, z0\.d
--.*: 65c06070 fcmne p0\.d, p0/z, z3\.d, z0\.d
--.*: 65c06070 fcmne p0\.d, p0/z, z3\.d, z0\.d
--.*: 65c063f0 fcmne p0\.d, p0/z, z31\.d, z0\.d
--.*: 65c063f0 fcmne p0\.d, p0/z, z31\.d, z0\.d
--.*: 65c46010 fcmne p0\.d, p0/z, z0\.d, z4\.d
--.*: 65c46010 fcmne p0\.d, p0/z, z0\.d, z4\.d
--.*: 65df6010 fcmne p0\.d, p0/z, z0\.d, z31\.d
--.*: 65df6010 fcmne p0\.d, p0/z, z0\.d, z31\.d
--.*: 6540c000 fcmuo p0\.h, p0/z, z0\.h, z0\.h
--.*: 6540c000 fcmuo p0\.h, p0/z, z0\.h, z0\.h
--.*: 6540c001 fcmuo p1\.h, p0/z, z0\.h, z0\.h
--.*: 6540c001 fcmuo p1\.h, p0/z, z0\.h, z0\.h
--.*: 6540c00f fcmuo p15\.h, p0/z, z0\.h, z0\.h
--.*: 6540c00f fcmuo p15\.h, p0/z, z0\.h, z0\.h
--.*: 6540c800 fcmuo p0\.h, p2/z, z0\.h, z0\.h
--.*: 6540c800 fcmuo p0\.h, p2/z, z0\.h, z0\.h
--.*: 6540dc00 fcmuo p0\.h, p7/z, z0\.h, z0\.h
--.*: 6540dc00 fcmuo p0\.h, p7/z, z0\.h, z0\.h
--.*: 6540c060 fcmuo p0\.h, p0/z, z3\.h, z0\.h
--.*: 6540c060 fcmuo p0\.h, p0/z, z3\.h, z0\.h
--.*: 6540c3e0 fcmuo p0\.h, p0/z, z31\.h, z0\.h
--.*: 6540c3e0 fcmuo p0\.h, p0/z, z31\.h, z0\.h
--.*: 6544c000 fcmuo p0\.h, p0/z, z0\.h, z4\.h
--.*: 6544c000 fcmuo p0\.h, p0/z, z0\.h, z4\.h
--.*: 655fc000 fcmuo p0\.h, p0/z, z0\.h, z31\.h
--.*: 655fc000 fcmuo p0\.h, p0/z, z0\.h, z31\.h
--.*: 6580c000 fcmuo p0\.s, p0/z, z0\.s, z0\.s
--.*: 6580c000 fcmuo p0\.s, p0/z, z0\.s, z0\.s
--.*: 6580c001 fcmuo p1\.s, p0/z, z0\.s, z0\.s
--.*: 6580c001 fcmuo p1\.s, p0/z, z0\.s, z0\.s
--.*: 6580c00f fcmuo p15\.s, p0/z, z0\.s, z0\.s
--.*: 6580c00f fcmuo p15\.s, p0/z, z0\.s, z0\.s
--.*: 6580c800 fcmuo p0\.s, p2/z, z0\.s, z0\.s
--.*: 6580c800 fcmuo p0\.s, p2/z, z0\.s, z0\.s
--.*: 6580dc00 fcmuo p0\.s, p7/z, z0\.s, z0\.s
--.*: 6580dc00 fcmuo p0\.s, p7/z, z0\.s, z0\.s
--.*: 6580c060 fcmuo p0\.s, p0/z, z3\.s, z0\.s
--.*: 6580c060 fcmuo p0\.s, p0/z, z3\.s, z0\.s
--.*: 6580c3e0 fcmuo p0\.s, p0/z, z31\.s, z0\.s
--.*: 6580c3e0 fcmuo p0\.s, p0/z, z31\.s, z0\.s
--.*: 6584c000 fcmuo p0\.s, p0/z, z0\.s, z4\.s
--.*: 6584c000 fcmuo p0\.s, p0/z, z0\.s, z4\.s
--.*: 659fc000 fcmuo p0\.s, p0/z, z0\.s, z31\.s
--.*: 659fc000 fcmuo p0\.s, p0/z, z0\.s, z31\.s
--.*: 65c0c000 fcmuo p0\.d, p0/z, z0\.d, z0\.d
--.*: 65c0c000 fcmuo p0\.d, p0/z, z0\.d, z0\.d
--.*: 65c0c001 fcmuo p1\.d, p0/z, z0\.d, z0\.d
--.*: 65c0c001 fcmuo p1\.d, p0/z, z0\.d, z0\.d
--.*: 65c0c00f fcmuo p15\.d, p0/z, z0\.d, z0\.d
--.*: 65c0c00f fcmuo p15\.d, p0/z, z0\.d, z0\.d
--.*: 65c0c800 fcmuo p0\.d, p2/z, z0\.d, z0\.d
--.*: 65c0c800 fcmuo p0\.d, p2/z, z0\.d, z0\.d
--.*: 65c0dc00 fcmuo p0\.d, p7/z, z0\.d, z0\.d
--.*: 65c0dc00 fcmuo p0\.d, p7/z, z0\.d, z0\.d
--.*: 65c0c060 fcmuo p0\.d, p0/z, z3\.d, z0\.d
--.*: 65c0c060 fcmuo p0\.d, p0/z, z3\.d, z0\.d
--.*: 65c0c3e0 fcmuo p0\.d, p0/z, z31\.d, z0\.d
--.*: 65c0c3e0 fcmuo p0\.d, p0/z, z31\.d, z0\.d
--.*: 65c4c000 fcmuo p0\.d, p0/z, z0\.d, z4\.d
--.*: 65c4c000 fcmuo p0\.d, p0/z, z0\.d, z4\.d
--.*: 65dfc000 fcmuo p0\.d, p0/z, z0\.d, z31\.d
--.*: 65dfc000 fcmuo p0\.d, p0/z, z0\.d, z31\.d
--.*: 0550c000 fmov z0\.h, p0/m, #2\.0+e\+00
--.*: 0550c000 fmov z0\.h, p0/m, #2\.0+e\+00
--.*: 0550c001 fmov z1\.h, p0/m, #2\.0+e\+00
--.*: 0550c001 fmov z1\.h, p0/m, #2\.0+e\+00
--.*: 0550c01f fmov z31\.h, p0/m, #2\.0+e\+00
--.*: 0550c01f fmov z31\.h, p0/m, #2\.0+e\+00
--.*: 0552c000 fmov z0\.h, p2/m, #2\.0+e\+00
--.*: 0552c000 fmov z0\.h, p2/m, #2\.0+e\+00
--.*: 055fc000 fmov z0\.h, p15/m, #2\.0+e\+00
--.*: 055fc000 fmov z0\.h, p15/m, #2\.0+e\+00
--.*: 0550c600 fmov z0\.h, p0/m, #1\.60+e\+01
--.*: 0550c600 fmov z0\.h, p0/m, #1\.60+e\+01
--.*: 0550c900 fmov z0\.h, p0/m, #1\.8750+e-01
--.*: 0550c900 fmov z0\.h, p0/m, #1\.8750+e-01
--.*: 0550cfe0 fmov z0\.h, p0/m, #1\.93750+e\+00
--.*: 0550cfe0 fmov z0\.h, p0/m, #1\.93750+e\+00
--.*: 0550d100 fmov z0\.h, p0/m, #-3\.0+e\+00
--.*: 0550d100 fmov z0\.h, p0/m, #-3\.0+e\+00
--.*: 0550d800 fmov z0\.h, p0/m, #-1\.250+e-01
--.*: 0550d800 fmov z0\.h, p0/m, #-1\.250+e-01
--.*: 0550dfe0 fmov z0\.h, p0/m, #-1\.93750+e\+00
--.*: 0550dfe0 fmov z0\.h, p0/m, #-1\.93750+e\+00
--.*: 0590c000 fmov z0\.s, p0/m, #2\.0+e\+00
--.*: 0590c000 fmov z0\.s, p0/m, #2\.0+e\+00
--.*: 0590c001 fmov z1\.s, p0/m, #2\.0+e\+00
--.*: 0590c001 fmov z1\.s, p0/m, #2\.0+e\+00
--.*: 0590c01f fmov z31\.s, p0/m, #2\.0+e\+00
--.*: 0590c01f fmov z31\.s, p0/m, #2\.0+e\+00
--.*: 0592c000 fmov z0\.s, p2/m, #2\.0+e\+00
--.*: 0592c000 fmov z0\.s, p2/m, #2\.0+e\+00
--.*: 059fc000 fmov z0\.s, p15/m, #2\.0+e\+00
--.*: 059fc000 fmov z0\.s, p15/m, #2\.0+e\+00
--.*: 0590c600 fmov z0\.s, p0/m, #1\.60+e\+01
--.*: 0590c600 fmov z0\.s, p0/m, #1\.60+e\+01
--.*: 0590c900 fmov z0\.s, p0/m, #1\.8750+e-01
--.*: 0590c900 fmov z0\.s, p0/m, #1\.8750+e-01
--.*: 0590cfe0 fmov z0\.s, p0/m, #1\.93750+e\+00
--.*: 0590cfe0 fmov z0\.s, p0/m, #1\.93750+e\+00
--.*: 0590d100 fmov z0\.s, p0/m, #-3\.0+e\+00
--.*: 0590d100 fmov z0\.s, p0/m, #-3\.0+e\+00
--.*: 0590d800 fmov z0\.s, p0/m, #-1\.250+e-01
--.*: 0590d800 fmov z0\.s, p0/m, #-1\.250+e-01
--.*: 0590dfe0 fmov z0\.s, p0/m, #-1\.93750+e\+00
--.*: 0590dfe0 fmov z0\.s, p0/m, #-1\.93750+e\+00
--.*: 05d0c000 fmov z0\.d, p0/m, #2\.0+e\+00
--.*: 05d0c000 fmov z0\.d, p0/m, #2\.0+e\+00
--.*: 05d0c001 fmov z1\.d, p0/m, #2\.0+e\+00
--.*: 05d0c001 fmov z1\.d, p0/m, #2\.0+e\+00
--.*: 05d0c01f fmov z31\.d, p0/m, #2\.0+e\+00
--.*: 05d0c01f fmov z31\.d, p0/m, #2\.0+e\+00
--.*: 05d2c000 fmov z0\.d, p2/m, #2\.0+e\+00
--.*: 05d2c000 fmov z0\.d, p2/m, #2\.0+e\+00
--.*: 05dfc000 fmov z0\.d, p15/m, #2\.0+e\+00
--.*: 05dfc000 fmov z0\.d, p15/m, #2\.0+e\+00
--.*: 05d0c600 fmov z0\.d, p0/m, #1\.60+e\+01
--.*: 05d0c600 fmov z0\.d, p0/m, #1\.60+e\+01
--.*: 05d0c900 fmov z0\.d, p0/m, #1\.8750+e-01
--.*: 05d0c900 fmov z0\.d, p0/m, #1\.8750+e-01
--.*: 05d0cfe0 fmov z0\.d, p0/m, #1\.93750+e\+00
--.*: 05d0cfe0 fmov z0\.d, p0/m, #1\.93750+e\+00
--.*: 05d0d100 fmov z0\.d, p0/m, #-3\.0+e\+00
--.*: 05d0d100 fmov z0\.d, p0/m, #-3\.0+e\+00
--.*: 05d0d800 fmov z0\.d, p0/m, #-1\.250+e-01
--.*: 05d0d800 fmov z0\.d, p0/m, #-1\.250+e-01
--.*: 05d0dfe0 fmov z0\.d, p0/m, #-1\.93750+e\+00
--.*: 05d0dfe0 fmov z0\.d, p0/m, #-1\.93750+e\+00
--.*: 6588a000 fcvt z0\.h, p0/m, z0\.s
--.*: 6588a000 fcvt z0\.h, p0/m, z0\.s
--.*: 6588a001 fcvt z1\.h, p0/m, z0\.s
--.*: 6588a001 fcvt z1\.h, p0/m, z0\.s
--.*: 6588a01f fcvt z31\.h, p0/m, z0\.s
--.*: 6588a01f fcvt z31\.h, p0/m, z0\.s
--.*: 6588a800 fcvt z0\.h, p2/m, z0\.s
--.*: 6588a800 fcvt z0\.h, p2/m, z0\.s
--.*: 6588bc00 fcvt z0\.h, p7/m, z0\.s
--.*: 6588bc00 fcvt z0\.h, p7/m, z0\.s
--.*: 6588a060 fcvt z0\.h, p0/m, z3\.s
--.*: 6588a060 fcvt z0\.h, p0/m, z3\.s
--.*: 6588a3e0 fcvt z0\.h, p0/m, z31\.s
--.*: 6588a3e0 fcvt z0\.h, p0/m, z31\.s
--.*: 6589a000 fcvt z0\.s, p0/m, z0\.h
--.*: 6589a000 fcvt z0\.s, p0/m, z0\.h
--.*: 6589a001 fcvt z1\.s, p0/m, z0\.h
--.*: 6589a001 fcvt z1\.s, p0/m, z0\.h
--.*: 6589a01f fcvt z31\.s, p0/m, z0\.h
--.*: 6589a01f fcvt z31\.s, p0/m, z0\.h
--.*: 6589a800 fcvt z0\.s, p2/m, z0\.h
--.*: 6589a800 fcvt z0\.s, p2/m, z0\.h
--.*: 6589bc00 fcvt z0\.s, p7/m, z0\.h
--.*: 6589bc00 fcvt z0\.s, p7/m, z0\.h
--.*: 6589a060 fcvt z0\.s, p0/m, z3\.h
--.*: 6589a060 fcvt z0\.s, p0/m, z3\.h
--.*: 6589a3e0 fcvt z0\.s, p0/m, z31\.h
--.*: 6589a3e0 fcvt z0\.s, p0/m, z31\.h
--.*: 65c8a000 fcvt z0\.h, p0/m, z0\.d
--.*: 65c8a000 fcvt z0\.h, p0/m, z0\.d
--.*: 65c8a001 fcvt z1\.h, p0/m, z0\.d
--.*: 65c8a001 fcvt z1\.h, p0/m, z0\.d
--.*: 65c8a01f fcvt z31\.h, p0/m, z0\.d
--.*: 65c8a01f fcvt z31\.h, p0/m, z0\.d
--.*: 65c8a800 fcvt z0\.h, p2/m, z0\.d
--.*: 65c8a800 fcvt z0\.h, p2/m, z0\.d
--.*: 65c8bc00 fcvt z0\.h, p7/m, z0\.d
--.*: 65c8bc00 fcvt z0\.h, p7/m, z0\.d
--.*: 65c8a060 fcvt z0\.h, p0/m, z3\.d
--.*: 65c8a060 fcvt z0\.h, p0/m, z3\.d
--.*: 65c8a3e0 fcvt z0\.h, p0/m, z31\.d
--.*: 65c8a3e0 fcvt z0\.h, p0/m, z31\.d
--.*: 65c9a000 fcvt z0\.d, p0/m, z0\.h
--.*: 65c9a000 fcvt z0\.d, p0/m, z0\.h
--.*: 65c9a001 fcvt z1\.d, p0/m, z0\.h
--.*: 65c9a001 fcvt z1\.d, p0/m, z0\.h
--.*: 65c9a01f fcvt z31\.d, p0/m, z0\.h
--.*: 65c9a01f fcvt z31\.d, p0/m, z0\.h
--.*: 65c9a800 fcvt z0\.d, p2/m, z0\.h
--.*: 65c9a800 fcvt z0\.d, p2/m, z0\.h
--.*: 65c9bc00 fcvt z0\.d, p7/m, z0\.h
--.*: 65c9bc00 fcvt z0\.d, p7/m, z0\.h
--.*: 65c9a060 fcvt z0\.d, p0/m, z3\.h
--.*: 65c9a060 fcvt z0\.d, p0/m, z3\.h
--.*: 65c9a3e0 fcvt z0\.d, p0/m, z31\.h
--.*: 65c9a3e0 fcvt z0\.d, p0/m, z31\.h
--.*: 65caa000 fcvt z0\.s, p0/m, z0\.d
--.*: 65caa000 fcvt z0\.s, p0/m, z0\.d
--.*: 65caa001 fcvt z1\.s, p0/m, z0\.d
--.*: 65caa001 fcvt z1\.s, p0/m, z0\.d
--.*: 65caa01f fcvt z31\.s, p0/m, z0\.d
--.*: 65caa01f fcvt z31\.s, p0/m, z0\.d
--.*: 65caa800 fcvt z0\.s, p2/m, z0\.d
--.*: 65caa800 fcvt z0\.s, p2/m, z0\.d
--.*: 65cabc00 fcvt z0\.s, p7/m, z0\.d
--.*: 65cabc00 fcvt z0\.s, p7/m, z0\.d
--.*: 65caa060 fcvt z0\.s, p0/m, z3\.d
--.*: 65caa060 fcvt z0\.s, p0/m, z3\.d
--.*: 65caa3e0 fcvt z0\.s, p0/m, z31\.d
--.*: 65caa3e0 fcvt z0\.s, p0/m, z31\.d
--.*: 65cba000 fcvt z0\.d, p0/m, z0\.s
--.*: 65cba000 fcvt z0\.d, p0/m, z0\.s
--.*: 65cba001 fcvt z1\.d, p0/m, z0\.s
--.*: 65cba001 fcvt z1\.d, p0/m, z0\.s
--.*: 65cba01f fcvt z31\.d, p0/m, z0\.s
--.*: 65cba01f fcvt z31\.d, p0/m, z0\.s
--.*: 65cba800 fcvt z0\.d, p2/m, z0\.s
--.*: 65cba800 fcvt z0\.d, p2/m, z0\.s
--.*: 65cbbc00 fcvt z0\.d, p7/m, z0\.s
--.*: 65cbbc00 fcvt z0\.d, p7/m, z0\.s
--.*: 65cba060 fcvt z0\.d, p0/m, z3\.s
--.*: 65cba060 fcvt z0\.d, p0/m, z3\.s
--.*: 65cba3e0 fcvt z0\.d, p0/m, z31\.s
--.*: 65cba3e0 fcvt z0\.d, p0/m, z31\.s
--.*: 655aa000 fcvtzs z0\.h, p0/m, z0\.h
--.*: 655aa000 fcvtzs z0\.h, p0/m, z0\.h
--.*: 655aa001 fcvtzs z1\.h, p0/m, z0\.h
--.*: 655aa001 fcvtzs z1\.h, p0/m, z0\.h
--.*: 655aa01f fcvtzs z31\.h, p0/m, z0\.h
--.*: 655aa01f fcvtzs z31\.h, p0/m, z0\.h
--.*: 655aa800 fcvtzs z0\.h, p2/m, z0\.h
--.*: 655aa800 fcvtzs z0\.h, p2/m, z0\.h
--.*: 655abc00 fcvtzs z0\.h, p7/m, z0\.h
--.*: 655abc00 fcvtzs z0\.h, p7/m, z0\.h
--.*: 655aa060 fcvtzs z0\.h, p0/m, z3\.h
--.*: 655aa060 fcvtzs z0\.h, p0/m, z3\.h
--.*: 655aa3e0 fcvtzs z0\.h, p0/m, z31\.h
--.*: 655aa3e0 fcvtzs z0\.h, p0/m, z31\.h
--.*: 655ca000 fcvtzs z0\.s, p0/m, z0\.h
--.*: 655ca000 fcvtzs z0\.s, p0/m, z0\.h
--.*: 655ca001 fcvtzs z1\.s, p0/m, z0\.h
--.*: 655ca001 fcvtzs z1\.s, p0/m, z0\.h
--.*: 655ca01f fcvtzs z31\.s, p0/m, z0\.h
--.*: 655ca01f fcvtzs z31\.s, p0/m, z0\.h
--.*: 655ca800 fcvtzs z0\.s, p2/m, z0\.h
--.*: 655ca800 fcvtzs z0\.s, p2/m, z0\.h
--.*: 655cbc00 fcvtzs z0\.s, p7/m, z0\.h
--.*: 655cbc00 fcvtzs z0\.s, p7/m, z0\.h
--.*: 655ca060 fcvtzs z0\.s, p0/m, z3\.h
--.*: 655ca060 fcvtzs z0\.s, p0/m, z3\.h
--.*: 655ca3e0 fcvtzs z0\.s, p0/m, z31\.h
--.*: 655ca3e0 fcvtzs z0\.s, p0/m, z31\.h
--.*: 655ea000 fcvtzs z0\.d, p0/m, z0\.h
--.*: 655ea000 fcvtzs z0\.d, p0/m, z0\.h
--.*: 655ea001 fcvtzs z1\.d, p0/m, z0\.h
--.*: 655ea001 fcvtzs z1\.d, p0/m, z0\.h
--.*: 655ea01f fcvtzs z31\.d, p0/m, z0\.h
--.*: 655ea01f fcvtzs z31\.d, p0/m, z0\.h
--.*: 655ea800 fcvtzs z0\.d, p2/m, z0\.h
--.*: 655ea800 fcvtzs z0\.d, p2/m, z0\.h
--.*: 655ebc00 fcvtzs z0\.d, p7/m, z0\.h
--.*: 655ebc00 fcvtzs z0\.d, p7/m, z0\.h
--.*: 655ea060 fcvtzs z0\.d, p0/m, z3\.h
--.*: 655ea060 fcvtzs z0\.d, p0/m, z3\.h
--.*: 655ea3e0 fcvtzs z0\.d, p0/m, z31\.h
--.*: 655ea3e0 fcvtzs z0\.d, p0/m, z31\.h
--.*: 659ca000 fcvtzs z0\.s, p0/m, z0\.s
--.*: 659ca000 fcvtzs z0\.s, p0/m, z0\.s
--.*: 659ca001 fcvtzs z1\.s, p0/m, z0\.s
--.*: 659ca001 fcvtzs z1\.s, p0/m, z0\.s
--.*: 659ca01f fcvtzs z31\.s, p0/m, z0\.s
--.*: 659ca01f fcvtzs z31\.s, p0/m, z0\.s
--.*: 659ca800 fcvtzs z0\.s, p2/m, z0\.s
--.*: 659ca800 fcvtzs z0\.s, p2/m, z0\.s
--.*: 659cbc00 fcvtzs z0\.s, p7/m, z0\.s
--.*: 659cbc00 fcvtzs z0\.s, p7/m, z0\.s
--.*: 659ca060 fcvtzs z0\.s, p0/m, z3\.s
--.*: 659ca060 fcvtzs z0\.s, p0/m, z3\.s
--.*: 659ca3e0 fcvtzs z0\.s, p0/m, z31\.s
--.*: 659ca3e0 fcvtzs z0\.s, p0/m, z31\.s
--.*: 65d8a000 fcvtzs z0\.s, p0/m, z0\.d
--.*: 65d8a000 fcvtzs z0\.s, p0/m, z0\.d
--.*: 65d8a001 fcvtzs z1\.s, p0/m, z0\.d
--.*: 65d8a001 fcvtzs z1\.s, p0/m, z0\.d
--.*: 65d8a01f fcvtzs z31\.s, p0/m, z0\.d
--.*: 65d8a01f fcvtzs z31\.s, p0/m, z0\.d
--.*: 65d8a800 fcvtzs z0\.s, p2/m, z0\.d
--.*: 65d8a800 fcvtzs z0\.s, p2/m, z0\.d
--.*: 65d8bc00 fcvtzs z0\.s, p7/m, z0\.d
--.*: 65d8bc00 fcvtzs z0\.s, p7/m, z0\.d
--.*: 65d8a060 fcvtzs z0\.s, p0/m, z3\.d
--.*: 65d8a060 fcvtzs z0\.s, p0/m, z3\.d
--.*: 65d8a3e0 fcvtzs z0\.s, p0/m, z31\.d
--.*: 65d8a3e0 fcvtzs z0\.s, p0/m, z31\.d
--.*: 65dca000 fcvtzs z0\.d, p0/m, z0\.s
--.*: 65dca000 fcvtzs z0\.d, p0/m, z0\.s
--.*: 65dca001 fcvtzs z1\.d, p0/m, z0\.s
--.*: 65dca001 fcvtzs z1\.d, p0/m, z0\.s
--.*: 65dca01f fcvtzs z31\.d, p0/m, z0\.s
--.*: 65dca01f fcvtzs z31\.d, p0/m, z0\.s
--.*: 65dca800 fcvtzs z0\.d, p2/m, z0\.s
--.*: 65dca800 fcvtzs z0\.d, p2/m, z0\.s
--.*: 65dcbc00 fcvtzs z0\.d, p7/m, z0\.s
--.*: 65dcbc00 fcvtzs z0\.d, p7/m, z0\.s
--.*: 65dca060 fcvtzs z0\.d, p0/m, z3\.s
--.*: 65dca060 fcvtzs z0\.d, p0/m, z3\.s
--.*: 65dca3e0 fcvtzs z0\.d, p0/m, z31\.s
--.*: 65dca3e0 fcvtzs z0\.d, p0/m, z31\.s
--.*: 65dea000 fcvtzs z0\.d, p0/m, z0\.d
--.*: 65dea000 fcvtzs z0\.d, p0/m, z0\.d
--.*: 65dea001 fcvtzs z1\.d, p0/m, z0\.d
--.*: 65dea001 fcvtzs z1\.d, p0/m, z0\.d
--.*: 65dea01f fcvtzs z31\.d, p0/m, z0\.d
--.*: 65dea01f fcvtzs z31\.d, p0/m, z0\.d
--.*: 65dea800 fcvtzs z0\.d, p2/m, z0\.d
--.*: 65dea800 fcvtzs z0\.d, p2/m, z0\.d
--.*: 65debc00 fcvtzs z0\.d, p7/m, z0\.d
--.*: 65debc00 fcvtzs z0\.d, p7/m, z0\.d
--.*: 65dea060 fcvtzs z0\.d, p0/m, z3\.d
--.*: 65dea060 fcvtzs z0\.d, p0/m, z3\.d
--.*: 65dea3e0 fcvtzs z0\.d, p0/m, z31\.d
--.*: 65dea3e0 fcvtzs z0\.d, p0/m, z31\.d
--.*: 655ba000 fcvtzu z0\.h, p0/m, z0\.h
--.*: 655ba000 fcvtzu z0\.h, p0/m, z0\.h
--.*: 655ba001 fcvtzu z1\.h, p0/m, z0\.h
--.*: 655ba001 fcvtzu z1\.h, p0/m, z0\.h
--.*: 655ba01f fcvtzu z31\.h, p0/m, z0\.h
--.*: 655ba01f fcvtzu z31\.h, p0/m, z0\.h
--.*: 655ba800 fcvtzu z0\.h, p2/m, z0\.h
--.*: 655ba800 fcvtzu z0\.h, p2/m, z0\.h
--.*: 655bbc00 fcvtzu z0\.h, p7/m, z0\.h
--.*: 655bbc00 fcvtzu z0\.h, p7/m, z0\.h
--.*: 655ba060 fcvtzu z0\.h, p0/m, z3\.h
--.*: 655ba060 fcvtzu z0\.h, p0/m, z3\.h
--.*: 655ba3e0 fcvtzu z0\.h, p0/m, z31\.h
--.*: 655ba3e0 fcvtzu z0\.h, p0/m, z31\.h
--.*: 655da000 fcvtzu z0\.s, p0/m, z0\.h
--.*: 655da000 fcvtzu z0\.s, p0/m, z0\.h
--.*: 655da001 fcvtzu z1\.s, p0/m, z0\.h
--.*: 655da001 fcvtzu z1\.s, p0/m, z0\.h
--.*: 655da01f fcvtzu z31\.s, p0/m, z0\.h
--.*: 655da01f fcvtzu z31\.s, p0/m, z0\.h
--.*: 655da800 fcvtzu z0\.s, p2/m, z0\.h
--.*: 655da800 fcvtzu z0\.s, p2/m, z0\.h
--.*: 655dbc00 fcvtzu z0\.s, p7/m, z0\.h
--.*: 655dbc00 fcvtzu z0\.s, p7/m, z0\.h
--.*: 655da060 fcvtzu z0\.s, p0/m, z3\.h
--.*: 655da060 fcvtzu z0\.s, p0/m, z3\.h
--.*: 655da3e0 fcvtzu z0\.s, p0/m, z31\.h
--.*: 655da3e0 fcvtzu z0\.s, p0/m, z31\.h
--.*: 655fa000 fcvtzu z0\.d, p0/m, z0\.h
--.*: 655fa000 fcvtzu z0\.d, p0/m, z0\.h
--.*: 655fa001 fcvtzu z1\.d, p0/m, z0\.h
--.*: 655fa001 fcvtzu z1\.d, p0/m, z0\.h
--.*: 655fa01f fcvtzu z31\.d, p0/m, z0\.h
--.*: 655fa01f fcvtzu z31\.d, p0/m, z0\.h
--.*: 655fa800 fcvtzu z0\.d, p2/m, z0\.h
--.*: 655fa800 fcvtzu z0\.d, p2/m, z0\.h
--.*: 655fbc00 fcvtzu z0\.d, p7/m, z0\.h
--.*: 655fbc00 fcvtzu z0\.d, p7/m, z0\.h
--.*: 655fa060 fcvtzu z0\.d, p0/m, z3\.h
--.*: 655fa060 fcvtzu z0\.d, p0/m, z3\.h
--.*: 655fa3e0 fcvtzu z0\.d, p0/m, z31\.h
--.*: 655fa3e0 fcvtzu z0\.d, p0/m, z31\.h
--.*: 659da000 fcvtzu z0\.s, p0/m, z0\.s
--.*: 659da000 fcvtzu z0\.s, p0/m, z0\.s
--.*: 659da001 fcvtzu z1\.s, p0/m, z0\.s
--.*: 659da001 fcvtzu z1\.s, p0/m, z0\.s
--.*: 659da01f fcvtzu z31\.s, p0/m, z0\.s
--.*: 659da01f fcvtzu z31\.s, p0/m, z0\.s
--.*: 659da800 fcvtzu z0\.s, p2/m, z0\.s
--.*: 659da800 fcvtzu z0\.s, p2/m, z0\.s
--.*: 659dbc00 fcvtzu z0\.s, p7/m, z0\.s
--.*: 659dbc00 fcvtzu z0\.s, p7/m, z0\.s
--.*: 659da060 fcvtzu z0\.s, p0/m, z3\.s
--.*: 659da060 fcvtzu z0\.s, p0/m, z3\.s
--.*: 659da3e0 fcvtzu z0\.s, p0/m, z31\.s
--.*: 659da3e0 fcvtzu z0\.s, p0/m, z31\.s
--.*: 65d9a000 fcvtzu z0\.s, p0/m, z0\.d
--.*: 65d9a000 fcvtzu z0\.s, p0/m, z0\.d
--.*: 65d9a001 fcvtzu z1\.s, p0/m, z0\.d
--.*: 65d9a001 fcvtzu z1\.s, p0/m, z0\.d
--.*: 65d9a01f fcvtzu z31\.s, p0/m, z0\.d
--.*: 65d9a01f fcvtzu z31\.s, p0/m, z0\.d
--.*: 65d9a800 fcvtzu z0\.s, p2/m, z0\.d
--.*: 65d9a800 fcvtzu z0\.s, p2/m, z0\.d
--.*: 65d9bc00 fcvtzu z0\.s, p7/m, z0\.d
--.*: 65d9bc00 fcvtzu z0\.s, p7/m, z0\.d
--.*: 65d9a060 fcvtzu z0\.s, p0/m, z3\.d
--.*: 65d9a060 fcvtzu z0\.s, p0/m, z3\.d
--.*: 65d9a3e0 fcvtzu z0\.s, p0/m, z31\.d
--.*: 65d9a3e0 fcvtzu z0\.s, p0/m, z31\.d
--.*: 65dda000 fcvtzu z0\.d, p0/m, z0\.s
--.*: 65dda000 fcvtzu z0\.d, p0/m, z0\.s
--.*: 65dda001 fcvtzu z1\.d, p0/m, z0\.s
--.*: 65dda001 fcvtzu z1\.d, p0/m, z0\.s
--.*: 65dda01f fcvtzu z31\.d, p0/m, z0\.s
--.*: 65dda01f fcvtzu z31\.d, p0/m, z0\.s
--.*: 65dda800 fcvtzu z0\.d, p2/m, z0\.s
--.*: 65dda800 fcvtzu z0\.d, p2/m, z0\.s
--.*: 65ddbc00 fcvtzu z0\.d, p7/m, z0\.s
--.*: 65ddbc00 fcvtzu z0\.d, p7/m, z0\.s
--.*: 65dda060 fcvtzu z0\.d, p0/m, z3\.s
--.*: 65dda060 fcvtzu z0\.d, p0/m, z3\.s
--.*: 65dda3e0 fcvtzu z0\.d, p0/m, z31\.s
--.*: 65dda3e0 fcvtzu z0\.d, p0/m, z31\.s
--.*: 65dfa000 fcvtzu z0\.d, p0/m, z0\.d
--.*: 65dfa000 fcvtzu z0\.d, p0/m, z0\.d
--.*: 65dfa001 fcvtzu z1\.d, p0/m, z0\.d
--.*: 65dfa001 fcvtzu z1\.d, p0/m, z0\.d
--.*: 65dfa01f fcvtzu z31\.d, p0/m, z0\.d
--.*: 65dfa01f fcvtzu z31\.d, p0/m, z0\.d
--.*: 65dfa800 fcvtzu z0\.d, p2/m, z0\.d
--.*: 65dfa800 fcvtzu z0\.d, p2/m, z0\.d
--.*: 65dfbc00 fcvtzu z0\.d, p7/m, z0\.d
--.*: 65dfbc00 fcvtzu z0\.d, p7/m, z0\.d
--.*: 65dfa060 fcvtzu z0\.d, p0/m, z3\.d
--.*: 65dfa060 fcvtzu z0\.d, p0/m, z3\.d
--.*: 65dfa3e0 fcvtzu z0\.d, p0/m, z31\.d
--.*: 65dfa3e0 fcvtzu z0\.d, p0/m, z31\.d
--.*: 654d8000 fdiv z0\.h, p0/m, z0\.h, z0\.h
--.*: 654d8000 fdiv z0\.h, p0/m, z0\.h, z0\.h
--.*: 654d8001 fdiv z1\.h, p0/m, z1\.h, z0\.h
--.*: 654d8001 fdiv z1\.h, p0/m, z1\.h, z0\.h
--.*: 654d801f fdiv z31\.h, p0/m, z31\.h, z0\.h
--.*: 654d801f fdiv z31\.h, p0/m, z31\.h, z0\.h
--.*: 654d8800 fdiv z0\.h, p2/m, z0\.h, z0\.h
--.*: 654d8800 fdiv z0\.h, p2/m, z0\.h, z0\.h
--.*: 654d9c00 fdiv z0\.h, p7/m, z0\.h, z0\.h
--.*: 654d9c00 fdiv z0\.h, p7/m, z0\.h, z0\.h
--.*: 654d8003 fdiv z3\.h, p0/m, z3\.h, z0\.h
--.*: 654d8003 fdiv z3\.h, p0/m, z3\.h, z0\.h
--.*: 654d8080 fdiv z0\.h, p0/m, z0\.h, z4\.h
--.*: 654d8080 fdiv z0\.h, p0/m, z0\.h, z4\.h
--.*: 654d83e0 fdiv z0\.h, p0/m, z0\.h, z31\.h
--.*: 654d83e0 fdiv z0\.h, p0/m, z0\.h, z31\.h
--.*: 658d8000 fdiv z0\.s, p0/m, z0\.s, z0\.s
--.*: 658d8000 fdiv z0\.s, p0/m, z0\.s, z0\.s
--.*: 658d8001 fdiv z1\.s, p0/m, z1\.s, z0\.s
--.*: 658d8001 fdiv z1\.s, p0/m, z1\.s, z0\.s
--.*: 658d801f fdiv z31\.s, p0/m, z31\.s, z0\.s
--.*: 658d801f fdiv z31\.s, p0/m, z31\.s, z0\.s
--.*: 658d8800 fdiv z0\.s, p2/m, z0\.s, z0\.s
--.*: 658d8800 fdiv z0\.s, p2/m, z0\.s, z0\.s
--.*: 658d9c00 fdiv z0\.s, p7/m, z0\.s, z0\.s
--.*: 658d9c00 fdiv z0\.s, p7/m, z0\.s, z0\.s
--.*: 658d8003 fdiv z3\.s, p0/m, z3\.s, z0\.s
--.*: 658d8003 fdiv z3\.s, p0/m, z3\.s, z0\.s
--.*: 658d8080 fdiv z0\.s, p0/m, z0\.s, z4\.s
--.*: 658d8080 fdiv z0\.s, p0/m, z0\.s, z4\.s
--.*: 658d83e0 fdiv z0\.s, p0/m, z0\.s, z31\.s
--.*: 658d83e0 fdiv z0\.s, p0/m, z0\.s, z31\.s
--.*: 65cd8000 fdiv z0\.d, p0/m, z0\.d, z0\.d
--.*: 65cd8000 fdiv z0\.d, p0/m, z0\.d, z0\.d
--.*: 65cd8001 fdiv z1\.d, p0/m, z1\.d, z0\.d
--.*: 65cd8001 fdiv z1\.d, p0/m, z1\.d, z0\.d
--.*: 65cd801f fdiv z31\.d, p0/m, z31\.d, z0\.d
--.*: 65cd801f fdiv z31\.d, p0/m, z31\.d, z0\.d
--.*: 65cd8800 fdiv z0\.d, p2/m, z0\.d, z0\.d
--.*: 65cd8800 fdiv z0\.d, p2/m, z0\.d, z0\.d
--.*: 65cd9c00 fdiv z0\.d, p7/m, z0\.d, z0\.d
--.*: 65cd9c00 fdiv z0\.d, p7/m, z0\.d, z0\.d
--.*: 65cd8003 fdiv z3\.d, p0/m, z3\.d, z0\.d
--.*: 65cd8003 fdiv z3\.d, p0/m, z3\.d, z0\.d
--.*: 65cd8080 fdiv z0\.d, p0/m, z0\.d, z4\.d
--.*: 65cd8080 fdiv z0\.d, p0/m, z0\.d, z4\.d
--.*: 65cd83e0 fdiv z0\.d, p0/m, z0\.d, z31\.d
--.*: 65cd83e0 fdiv z0\.d, p0/m, z0\.d, z31\.d
--.*: 654c8000 fdivr z0\.h, p0/m, z0\.h, z0\.h
--.*: 654c8000 fdivr z0\.h, p0/m, z0\.h, z0\.h
--.*: 654c8001 fdivr z1\.h, p0/m, z1\.h, z0\.h
--.*: 654c8001 fdivr z1\.h, p0/m, z1\.h, z0\.h
--.*: 654c801f fdivr z31\.h, p0/m, z31\.h, z0\.h
--.*: 654c801f fdivr z31\.h, p0/m, z31\.h, z0\.h
--.*: 654c8800 fdivr z0\.h, p2/m, z0\.h, z0\.h
--.*: 654c8800 fdivr z0\.h, p2/m, z0\.h, z0\.h
--.*: 654c9c00 fdivr z0\.h, p7/m, z0\.h, z0\.h
--.*: 654c9c00 fdivr z0\.h, p7/m, z0\.h, z0\.h
--.*: 654c8003 fdivr z3\.h, p0/m, z3\.h, z0\.h
--.*: 654c8003 fdivr z3\.h, p0/m, z3\.h, z0\.h
--.*: 654c8080 fdivr z0\.h, p0/m, z0\.h, z4\.h
--.*: 654c8080 fdivr z0\.h, p0/m, z0\.h, z4\.h
--.*: 654c83e0 fdivr z0\.h, p0/m, z0\.h, z31\.h
--.*: 654c83e0 fdivr z0\.h, p0/m, z0\.h, z31\.h
--.*: 658c8000 fdivr z0\.s, p0/m, z0\.s, z0\.s
--.*: 658c8000 fdivr z0\.s, p0/m, z0\.s, z0\.s
--.*: 658c8001 fdivr z1\.s, p0/m, z1\.s, z0\.s
--.*: 658c8001 fdivr z1\.s, p0/m, z1\.s, z0\.s
--.*: 658c801f fdivr z31\.s, p0/m, z31\.s, z0\.s
--.*: 658c801f fdivr z31\.s, p0/m, z31\.s, z0\.s
--.*: 658c8800 fdivr z0\.s, p2/m, z0\.s, z0\.s
--.*: 658c8800 fdivr z0\.s, p2/m, z0\.s, z0\.s
--.*: 658c9c00 fdivr z0\.s, p7/m, z0\.s, z0\.s
--.*: 658c9c00 fdivr z0\.s, p7/m, z0\.s, z0\.s
--.*: 658c8003 fdivr z3\.s, p0/m, z3\.s, z0\.s
--.*: 658c8003 fdivr z3\.s, p0/m, z3\.s, z0\.s
--.*: 658c8080 fdivr z0\.s, p0/m, z0\.s, z4\.s
--.*: 658c8080 fdivr z0\.s, p0/m, z0\.s, z4\.s
--.*: 658c83e0 fdivr z0\.s, p0/m, z0\.s, z31\.s
--.*: 658c83e0 fdivr z0\.s, p0/m, z0\.s, z31\.s
--.*: 65cc8000 fdivr z0\.d, p0/m, z0\.d, z0\.d
--.*: 65cc8000 fdivr z0\.d, p0/m, z0\.d, z0\.d
--.*: 65cc8001 fdivr z1\.d, p0/m, z1\.d, z0\.d
--.*: 65cc8001 fdivr z1\.d, p0/m, z1\.d, z0\.d
--.*: 65cc801f fdivr z31\.d, p0/m, z31\.d, z0\.d
--.*: 65cc801f fdivr z31\.d, p0/m, z31\.d, z0\.d
--.*: 65cc8800 fdivr z0\.d, p2/m, z0\.d, z0\.d
--.*: 65cc8800 fdivr z0\.d, p2/m, z0\.d, z0\.d
--.*: 65cc9c00 fdivr z0\.d, p7/m, z0\.d, z0\.d
--.*: 65cc9c00 fdivr z0\.d, p7/m, z0\.d, z0\.d
--.*: 65cc8003 fdivr z3\.d, p0/m, z3\.d, z0\.d
--.*: 65cc8003 fdivr z3\.d, p0/m, z3\.d, z0\.d
--.*: 65cc8080 fdivr z0\.d, p0/m, z0\.d, z4\.d
--.*: 65cc8080 fdivr z0\.d, p0/m, z0\.d, z4\.d
--.*: 65cc83e0 fdivr z0\.d, p0/m, z0\.d, z31\.d
--.*: 65cc83e0 fdivr z0\.d, p0/m, z0\.d, z31\.d
--.*: 2579c000 fmov z0\.h, #2\.0+e\+00
--.*: 2579c000 fmov z0\.h, #2\.0+e\+00
--.*: 2579c001 fmov z1\.h, #2\.0+e\+00
--.*: 2579c001 fmov z1\.h, #2\.0+e\+00
--.*: 2579c01f fmov z31\.h, #2\.0+e\+00
--.*: 2579c01f fmov z31\.h, #2\.0+e\+00
--.*: 2579c600 fmov z0\.h, #1\.60+e\+01
--.*: 2579c600 fmov z0\.h, #1\.60+e\+01
--.*: 2579c900 fmov z0\.h, #1\.8750+e-01
--.*: 2579c900 fmov z0\.h, #1\.8750+e-01
--.*: 2579cfe0 fmov z0\.h, #1\.93750+e\+00
--.*: 2579cfe0 fmov z0\.h, #1\.93750+e\+00
--.*: 2579d100 fmov z0\.h, #-3\.0+e\+00
--.*: 2579d100 fmov z0\.h, #-3\.0+e\+00
--.*: 2579d800 fmov z0\.h, #-1\.250+e-01
--.*: 2579d800 fmov z0\.h, #-1\.250+e-01
--.*: 2579dfe0 fmov z0\.h, #-1\.93750+e\+00
--.*: 2579dfe0 fmov z0\.h, #-1\.93750+e\+00
--.*: 25b9c000 fmov z0\.s, #2\.0+e\+00
--.*: 25b9c000 fmov z0\.s, #2\.0+e\+00
--.*: 25b9c001 fmov z1\.s, #2\.0+e\+00
--.*: 25b9c001 fmov z1\.s, #2\.0+e\+00
--.*: 25b9c01f fmov z31\.s, #2\.0+e\+00
--.*: 25b9c01f fmov z31\.s, #2\.0+e\+00
--.*: 25b9c600 fmov z0\.s, #1\.60+e\+01
--.*: 25b9c600 fmov z0\.s, #1\.60+e\+01
--.*: 25b9c900 fmov z0\.s, #1\.8750+e-01
--.*: 25b9c900 fmov z0\.s, #1\.8750+e-01
--.*: 25b9cfe0 fmov z0\.s, #1\.93750+e\+00
--.*: 25b9cfe0 fmov z0\.s, #1\.93750+e\+00
--.*: 25b9d100 fmov z0\.s, #-3\.0+e\+00
--.*: 25b9d100 fmov z0\.s, #-3\.0+e\+00
--.*: 25b9d800 fmov z0\.s, #-1\.250+e-01
--.*: 25b9d800 fmov z0\.s, #-1\.250+e-01
--.*: 25b9dfe0 fmov z0\.s, #-1\.93750+e\+00
--.*: 25b9dfe0 fmov z0\.s, #-1\.93750+e\+00
--.*: 25f9c000 fmov z0\.d, #2\.0+e\+00
--.*: 25f9c000 fmov z0\.d, #2\.0+e\+00
--.*: 25f9c001 fmov z1\.d, #2\.0+e\+00
--.*: 25f9c001 fmov z1\.d, #2\.0+e\+00
--.*: 25f9c01f fmov z31\.d, #2\.0+e\+00
--.*: 25f9c01f fmov z31\.d, #2\.0+e\+00
--.*: 25f9c600 fmov z0\.d, #1\.60+e\+01
--.*: 25f9c600 fmov z0\.d, #1\.60+e\+01
--.*: 25f9c900 fmov z0\.d, #1\.8750+e-01
--.*: 25f9c900 fmov z0\.d, #1\.8750+e-01
--.*: 25f9cfe0 fmov z0\.d, #1\.93750+e\+00
--.*: 25f9cfe0 fmov z0\.d, #1\.93750+e\+00
--.*: 25f9d100 fmov z0\.d, #-3\.0+e\+00
--.*: 25f9d100 fmov z0\.d, #-3\.0+e\+00
--.*: 25f9d800 fmov z0\.d, #-1\.250+e-01
--.*: 25f9d800 fmov z0\.d, #-1\.250+e-01
--.*: 25f9dfe0 fmov z0\.d, #-1\.93750+e\+00
--.*: 25f9dfe0 fmov z0\.d, #-1\.93750+e\+00
--.*: 0460b800 fexpa z0\.h, z0\.h
--.*: 0460b800 fexpa z0\.h, z0\.h
--.*: 0460b801 fexpa z1\.h, z0\.h
--.*: 0460b801 fexpa z1\.h, z0\.h
--.*: 0460b81f fexpa z31\.h, z0\.h
--.*: 0460b81f fexpa z31\.h, z0\.h
--.*: 0460b840 fexpa z0\.h, z2\.h
--.*: 0460b840 fexpa z0\.h, z2\.h
--.*: 0460bbe0 fexpa z0\.h, z31\.h
--.*: 0460bbe0 fexpa z0\.h, z31\.h
--.*: 04a0b800 fexpa z0\.s, z0\.s
--.*: 04a0b800 fexpa z0\.s, z0\.s
--.*: 04a0b801 fexpa z1\.s, z0\.s
--.*: 04a0b801 fexpa z1\.s, z0\.s
--.*: 04a0b81f fexpa z31\.s, z0\.s
--.*: 04a0b81f fexpa z31\.s, z0\.s
--.*: 04a0b840 fexpa z0\.s, z2\.s
--.*: 04a0b840 fexpa z0\.s, z2\.s
--.*: 04a0bbe0 fexpa z0\.s, z31\.s
--.*: 04a0bbe0 fexpa z0\.s, z31\.s
--.*: 04e0b800 fexpa z0\.d, z0\.d
--.*: 04e0b800 fexpa z0\.d, z0\.d
--.*: 04e0b801 fexpa z1\.d, z0\.d
--.*: 04e0b801 fexpa z1\.d, z0\.d
--.*: 04e0b81f fexpa z31\.d, z0\.d
--.*: 04e0b81f fexpa z31\.d, z0\.d
--.*: 04e0b840 fexpa z0\.d, z2\.d
--.*: 04e0b840 fexpa z0\.d, z2\.d
--.*: 04e0bbe0 fexpa z0\.d, z31\.d
--.*: 04e0bbe0 fexpa z0\.d, z31\.d
--.*: 65608000 fmad z0\.h, p0/m, z0\.h, z0\.h
--.*: 65608000 fmad z0\.h, p0/m, z0\.h, z0\.h
--.*: 65608001 fmad z1\.h, p0/m, z0\.h, z0\.h
--.*: 65608001 fmad z1\.h, p0/m, z0\.h, z0\.h
--.*: 6560801f fmad z31\.h, p0/m, z0\.h, z0\.h
--.*: 6560801f fmad z31\.h, p0/m, z0\.h, z0\.h
--.*: 65608800 fmad z0\.h, p2/m, z0\.h, z0\.h
--.*: 65608800 fmad z0\.h, p2/m, z0\.h, z0\.h
--.*: 65609c00 fmad z0\.h, p7/m, z0\.h, z0\.h
--.*: 65609c00 fmad z0\.h, p7/m, z0\.h, z0\.h
--.*: 65608060 fmad z0\.h, p0/m, z3\.h, z0\.h
--.*: 65608060 fmad z0\.h, p0/m, z3\.h, z0\.h
--.*: 656083e0 fmad z0\.h, p0/m, z31\.h, z0\.h
--.*: 656083e0 fmad z0\.h, p0/m, z31\.h, z0\.h
--.*: 65648000 fmad z0\.h, p0/m, z0\.h, z4\.h
--.*: 65648000 fmad z0\.h, p0/m, z0\.h, z4\.h
--.*: 657f8000 fmad z0\.h, p0/m, z0\.h, z31\.h
--.*: 657f8000 fmad z0\.h, p0/m, z0\.h, z31\.h
--.*: 65a08000 fmad z0\.s, p0/m, z0\.s, z0\.s
--.*: 65a08000 fmad z0\.s, p0/m, z0\.s, z0\.s
--.*: 65a08001 fmad z1\.s, p0/m, z0\.s, z0\.s
--.*: 65a08001 fmad z1\.s, p0/m, z0\.s, z0\.s
--.*: 65a0801f fmad z31\.s, p0/m, z0\.s, z0\.s
--.*: 65a0801f fmad z31\.s, p0/m, z0\.s, z0\.s
--.*: 65a08800 fmad z0\.s, p2/m, z0\.s, z0\.s
--.*: 65a08800 fmad z0\.s, p2/m, z0\.s, z0\.s
--.*: 65a09c00 fmad z0\.s, p7/m, z0\.s, z0\.s
--.*: 65a09c00 fmad z0\.s, p7/m, z0\.s, z0\.s
--.*: 65a08060 fmad z0\.s, p0/m, z3\.s, z0\.s
--.*: 65a08060 fmad z0\.s, p0/m, z3\.s, z0\.s
--.*: 65a083e0 fmad z0\.s, p0/m, z31\.s, z0\.s
--.*: 65a083e0 fmad z0\.s, p0/m, z31\.s, z0\.s
--.*: 65a48000 fmad z0\.s, p0/m, z0\.s, z4\.s
--.*: 65a48000 fmad z0\.s, p0/m, z0\.s, z4\.s
--.*: 65bf8000 fmad z0\.s, p0/m, z0\.s, z31\.s
--.*: 65bf8000 fmad z0\.s, p0/m, z0\.s, z31\.s
--.*: 65e08000 fmad z0\.d, p0/m, z0\.d, z0\.d
--.*: 65e08000 fmad z0\.d, p0/m, z0\.d, z0\.d
--.*: 65e08001 fmad z1\.d, p0/m, z0\.d, z0\.d
--.*: 65e08001 fmad z1\.d, p0/m, z0\.d, z0\.d
--.*: 65e0801f fmad z31\.d, p0/m, z0\.d, z0\.d
--.*: 65e0801f fmad z31\.d, p0/m, z0\.d, z0\.d
--.*: 65e08800 fmad z0\.d, p2/m, z0\.d, z0\.d
--.*: 65e08800 fmad z0\.d, p2/m, z0\.d, z0\.d
--.*: 65e09c00 fmad z0\.d, p7/m, z0\.d, z0\.d
--.*: 65e09c00 fmad z0\.d, p7/m, z0\.d, z0\.d
--.*: 65e08060 fmad z0\.d, p0/m, z3\.d, z0\.d
--.*: 65e08060 fmad z0\.d, p0/m, z3\.d, z0\.d
--.*: 65e083e0 fmad z0\.d, p0/m, z31\.d, z0\.d
--.*: 65e083e0 fmad z0\.d, p0/m, z31\.d, z0\.d
--.*: 65e48000 fmad z0\.d, p0/m, z0\.d, z4\.d
--.*: 65e48000 fmad z0\.d, p0/m, z0\.d, z4\.d
--.*: 65ff8000 fmad z0\.d, p0/m, z0\.d, z31\.d
--.*: 65ff8000 fmad z0\.d, p0/m, z0\.d, z31\.d
--.*: 65468000 fmax z0\.h, p0/m, z0\.h, z0\.h
--.*: 65468000 fmax z0\.h, p0/m, z0\.h, z0\.h
--.*: 65468001 fmax z1\.h, p0/m, z1\.h, z0\.h
--.*: 65468001 fmax z1\.h, p0/m, z1\.h, z0\.h
--.*: 6546801f fmax z31\.h, p0/m, z31\.h, z0\.h
--.*: 6546801f fmax z31\.h, p0/m, z31\.h, z0\.h
--.*: 65468800 fmax z0\.h, p2/m, z0\.h, z0\.h
--.*: 65468800 fmax z0\.h, p2/m, z0\.h, z0\.h
--.*: 65469c00 fmax z0\.h, p7/m, z0\.h, z0\.h
--.*: 65469c00 fmax z0\.h, p7/m, z0\.h, z0\.h
--.*: 65468003 fmax z3\.h, p0/m, z3\.h, z0\.h
--.*: 65468003 fmax z3\.h, p0/m, z3\.h, z0\.h
--.*: 65468080 fmax z0\.h, p0/m, z0\.h, z4\.h
--.*: 65468080 fmax z0\.h, p0/m, z0\.h, z4\.h
--.*: 654683e0 fmax z0\.h, p0/m, z0\.h, z31\.h
--.*: 654683e0 fmax z0\.h, p0/m, z0\.h, z31\.h
--.*: 65868000 fmax z0\.s, p0/m, z0\.s, z0\.s
--.*: 65868000 fmax z0\.s, p0/m, z0\.s, z0\.s
--.*: 65868001 fmax z1\.s, p0/m, z1\.s, z0\.s
--.*: 65868001 fmax z1\.s, p0/m, z1\.s, z0\.s
--.*: 6586801f fmax z31\.s, p0/m, z31\.s, z0\.s
--.*: 6586801f fmax z31\.s, p0/m, z31\.s, z0\.s
--.*: 65868800 fmax z0\.s, p2/m, z0\.s, z0\.s
--.*: 65868800 fmax z0\.s, p2/m, z0\.s, z0\.s
--.*: 65869c00 fmax z0\.s, p7/m, z0\.s, z0\.s
--.*: 65869c00 fmax z0\.s, p7/m, z0\.s, z0\.s
--.*: 65868003 fmax z3\.s, p0/m, z3\.s, z0\.s
--.*: 65868003 fmax z3\.s, p0/m, z3\.s, z0\.s
--.*: 65868080 fmax z0\.s, p0/m, z0\.s, z4\.s
--.*: 65868080 fmax z0\.s, p0/m, z0\.s, z4\.s
--.*: 658683e0 fmax z0\.s, p0/m, z0\.s, z31\.s
--.*: 658683e0 fmax z0\.s, p0/m, z0\.s, z31\.s
--.*: 65c68000 fmax z0\.d, p0/m, z0\.d, z0\.d
--.*: 65c68000 fmax z0\.d, p0/m, z0\.d, z0\.d
--.*: 65c68001 fmax z1\.d, p0/m, z1\.d, z0\.d
--.*: 65c68001 fmax z1\.d, p0/m, z1\.d, z0\.d
--.*: 65c6801f fmax z31\.d, p0/m, z31\.d, z0\.d
--.*: 65c6801f fmax z31\.d, p0/m, z31\.d, z0\.d
--.*: 65c68800 fmax z0\.d, p2/m, z0\.d, z0\.d
--.*: 65c68800 fmax z0\.d, p2/m, z0\.d, z0\.d
--.*: 65c69c00 fmax z0\.d, p7/m, z0\.d, z0\.d
--.*: 65c69c00 fmax z0\.d, p7/m, z0\.d, z0\.d
--.*: 65c68003 fmax z3\.d, p0/m, z3\.d, z0\.d
--.*: 65c68003 fmax z3\.d, p0/m, z3\.d, z0\.d
--.*: 65c68080 fmax z0\.d, p0/m, z0\.d, z4\.d
--.*: 65c68080 fmax z0\.d, p0/m, z0\.d, z4\.d
--.*: 65c683e0 fmax z0\.d, p0/m, z0\.d, z31\.d
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--.*: 64630400 fmls z0\.h, z0\.h, z3\.h\[4\]
--.*: 64780400 fmls z0\.h, z0\.h, z0\.h\[7\]
--.*: 64780400 fmls z0\.h, z0\.h, z0\.h\[7\]
--.*: 647d0400 fmls z0\.h, z0\.h, z5\.h\[7\]
--.*: 647d0400 fmls z0\.h, z0\.h, z5\.h\[7\]
--.*: 64a00400 fmls z0\.s, z0\.s, z0\.s\[0\]
--.*: 64a00400 fmls z0\.s, z0\.s, z0\.s\[0\]
--.*: 64a00401 fmls z1\.s, z0\.s, z0\.s\[0\]
--.*: 64a00401 fmls z1\.s, z0\.s, z0\.s\[0\]
--.*: 64a0041f fmls z31\.s, z0\.s, z0\.s\[0\]
--.*: 64a0041f fmls z31\.s, z0\.s, z0\.s\[0\]
--.*: 64a00440 fmls z0\.s, z2\.s, z0\.s\[0\]
--.*: 64a00440 fmls z0\.s, z2\.s, z0\.s\[0\]
--.*: 64a007e0 fmls z0\.s, z31\.s, z0\.s\[0\]
--.*: 64a007e0 fmls z0\.s, z31\.s, z0\.s\[0\]
--.*: 64a30400 fmls z0\.s, z0\.s, z3\.s\[0\]
--.*: 64a30400 fmls z0\.s, z0\.s, z3\.s\[0\]
--.*: 64a70400 fmls z0\.s, z0\.s, z7\.s\[0\]
--.*: 64a70400 fmls z0\.s, z0\.s, z7\.s\[0\]
--.*: 64a80400 fmls z0\.s, z0\.s, z0\.s\[1\]
--.*: 64a80400 fmls z0\.s, z0\.s, z0\.s\[1\]
--.*: 64ac0400 fmls z0\.s, z0\.s, z4\.s\[1\]
--.*: 64ac0400 fmls z0\.s, z0\.s, z4\.s\[1\]
--.*: 64b30400 fmls z0\.s, z0\.s, z3\.s\[2\]
--.*: 64b30400 fmls z0\.s, z0\.s, z3\.s\[2\]
--.*: 64b80400 fmls z0\.s, z0\.s, z0\.s\[3\]
--.*: 64b80400 fmls z0\.s, z0\.s, z0\.s\[3\]
--.*: 64bd0400 fmls z0\.s, z0\.s, z5\.s\[3\]
--.*: 64bd0400 fmls z0\.s, z0\.s, z5\.s\[3\]
--.*: 64e00400 fmls z0\.d, z0\.d, z0\.d\[0\]
--.*: 64e00400 fmls z0\.d, z0\.d, z0\.d\[0\]
--.*: 64e00401 fmls z1\.d, z0\.d, z0\.d\[0\]
--.*: 64e00401 fmls z1\.d, z0\.d, z0\.d\[0\]
--.*: 64e0041f fmls z31\.d, z0\.d, z0\.d\[0\]
--.*: 64e0041f fmls z31\.d, z0\.d, z0\.d\[0\]
--.*: 64e00440 fmls z0\.d, z2\.d, z0\.d\[0\]
--.*: 64e00440 fmls z0\.d, z2\.d, z0\.d\[0\]
--.*: 64e007e0 fmls z0\.d, z31\.d, z0\.d\[0\]
--.*: 64e007e0 fmls z0\.d, z31\.d, z0\.d\[0\]
--.*: 64e30400 fmls z0\.d, z0\.d, z3\.d\[0\]
--.*: 64e30400 fmls z0\.d, z0\.d, z3\.d\[0\]
--.*: 64ef0400 fmls z0\.d, z0\.d, z15\.d\[0\]
--.*: 64ef0400 fmls z0\.d, z0\.d, z15\.d\[0\]
--.*: 64f00400 fmls z0\.d, z0\.d, z0\.d\[1\]
--.*: 64f00400 fmls z0\.d, z0\.d, z0\.d\[1\]
--.*: 64fb0400 fmls z0\.d, z0\.d, z11\.d\[1\]
--.*: 64fb0400 fmls z0\.d, z0\.d, z11\.d\[1\]
--.*: 6560a000 fmsb z0\.h, p0/m, z0\.h, z0\.h
--.*: 6560a000 fmsb z0\.h, p0/m, z0\.h, z0\.h
--.*: 6560a001 fmsb z1\.h, p0/m, z0\.h, z0\.h
--.*: 6560a001 fmsb z1\.h, p0/m, z0\.h, z0\.h
--.*: 6560a01f fmsb z31\.h, p0/m, z0\.h, z0\.h
--.*: 6560a01f fmsb z31\.h, p0/m, z0\.h, z0\.h
--.*: 6560a800 fmsb z0\.h, p2/m, z0\.h, z0\.h
--.*: 6560a800 fmsb z0\.h, p2/m, z0\.h, z0\.h
--.*: 6560bc00 fmsb z0\.h, p7/m, z0\.h, z0\.h
--.*: 6560bc00 fmsb z0\.h, p7/m, z0\.h, z0\.h
--.*: 6560a060 fmsb z0\.h, p0/m, z3\.h, z0\.h
--.*: 6560a060 fmsb z0\.h, p0/m, z3\.h, z0\.h
--.*: 6560a3e0 fmsb z0\.h, p0/m, z31\.h, z0\.h
--.*: 6560a3e0 fmsb z0\.h, p0/m, z31\.h, z0\.h
--.*: 6564a000 fmsb z0\.h, p0/m, z0\.h, z4\.h
--.*: 6564a000 fmsb z0\.h, p0/m, z0\.h, z4\.h
--.*: 657fa000 fmsb z0\.h, p0/m, z0\.h, z31\.h
--.*: 657fa000 fmsb z0\.h, p0/m, z0\.h, z31\.h
--.*: 65a0a000 fmsb z0\.s, p0/m, z0\.s, z0\.s
--.*: 65a0a000 fmsb z0\.s, p0/m, z0\.s, z0\.s
--.*: 65a0a001 fmsb z1\.s, p0/m, z0\.s, z0\.s
--.*: 65a0a001 fmsb z1\.s, p0/m, z0\.s, z0\.s
--.*: 65a0a01f fmsb z31\.s, p0/m, z0\.s, z0\.s
--.*: 65a0a01f fmsb z31\.s, p0/m, z0\.s, z0\.s
--.*: 65a0a800 fmsb z0\.s, p2/m, z0\.s, z0\.s
--.*: 65a0a800 fmsb z0\.s, p2/m, z0\.s, z0\.s
--.*: 65a0bc00 fmsb z0\.s, p7/m, z0\.s, z0\.s
--.*: 65a0bc00 fmsb z0\.s, p7/m, z0\.s, z0\.s
--.*: 65a0a060 fmsb z0\.s, p0/m, z3\.s, z0\.s
--.*: 65a0a060 fmsb z0\.s, p0/m, z3\.s, z0\.s
--.*: 65a0a3e0 fmsb z0\.s, p0/m, z31\.s, z0\.s
--.*: 65a0a3e0 fmsb z0\.s, p0/m, z31\.s, z0\.s
--.*: 65a4a000 fmsb z0\.s, p0/m, z0\.s, z4\.s
--.*: 65a4a000 fmsb z0\.s, p0/m, z0\.s, z4\.s
--.*: 65bfa000 fmsb z0\.s, p0/m, z0\.s, z31\.s
--.*: 65bfa000 fmsb z0\.s, p0/m, z0\.s, z31\.s
--.*: 65e0a000 fmsb z0\.d, p0/m, z0\.d, z0\.d
--.*: 65e0a000 fmsb z0\.d, p0/m, z0\.d, z0\.d
--.*: 65e0a001 fmsb z1\.d, p0/m, z0\.d, z0\.d
--.*: 65e0a001 fmsb z1\.d, p0/m, z0\.d, z0\.d
--.*: 65e0a01f fmsb z31\.d, p0/m, z0\.d, z0\.d
--.*: 65e0a01f fmsb z31\.d, p0/m, z0\.d, z0\.d
--.*: 65e0a800 fmsb z0\.d, p2/m, z0\.d, z0\.d
--.*: 65e0a800 fmsb z0\.d, p2/m, z0\.d, z0\.d
--.*: 65e0bc00 fmsb z0\.d, p7/m, z0\.d, z0\.d
--.*: 65e0bc00 fmsb z0\.d, p7/m, z0\.d, z0\.d
--.*: 65e0a060 fmsb z0\.d, p0/m, z3\.d, z0\.d
--.*: 65e0a060 fmsb z0\.d, p0/m, z3\.d, z0\.d
--.*: 65e0a3e0 fmsb z0\.d, p0/m, z31\.d, z0\.d
--.*: 65e0a3e0 fmsb z0\.d, p0/m, z31\.d, z0\.d
--.*: 65e4a000 fmsb z0\.d, p0/m, z0\.d, z4\.d
--.*: 65e4a000 fmsb z0\.d, p0/m, z0\.d, z4\.d
--.*: 65ffa000 fmsb z0\.d, p0/m, z0\.d, z31\.d
--.*: 65ffa000 fmsb z0\.d, p0/m, z0\.d, z31\.d
--.*: 65400800 fmul z0\.h, z0\.h, z0\.h
--.*: 65400800 fmul z0\.h, z0\.h, z0\.h
--.*: 65400801 fmul z1\.h, z0\.h, z0\.h
--.*: 65400801 fmul z1\.h, z0\.h, z0\.h
--.*: 6540081f fmul z31\.h, z0\.h, z0\.h
--.*: 6540081f fmul z31\.h, z0\.h, z0\.h
--.*: 65400840 fmul z0\.h, z2\.h, z0\.h
--.*: 65400840 fmul z0\.h, z2\.h, z0\.h
--.*: 65400be0 fmul z0\.h, z31\.h, z0\.h
--.*: 65400be0 fmul z0\.h, z31\.h, z0\.h
--.*: 65430800 fmul z0\.h, z0\.h, z3\.h
--.*: 65430800 fmul z0\.h, z0\.h, z3\.h
--.*: 655f0800 fmul z0\.h, z0\.h, z31\.h
--.*: 655f0800 fmul z0\.h, z0\.h, z31\.h
--.*: 65800800 fmul z0\.s, z0\.s, z0\.s
--.*: 65800800 fmul z0\.s, z0\.s, z0\.s
--.*: 65800801 fmul z1\.s, z0\.s, z0\.s
--.*: 65800801 fmul z1\.s, z0\.s, z0\.s
--.*: 6580081f fmul z31\.s, z0\.s, z0\.s
--.*: 6580081f fmul z31\.s, z0\.s, z0\.s
--.*: 65800840 fmul z0\.s, z2\.s, z0\.s
--.*: 65800840 fmul z0\.s, z2\.s, z0\.s
--.*: 65800be0 fmul z0\.s, z31\.s, z0\.s
--.*: 65800be0 fmul z0\.s, z31\.s, z0\.s
--.*: 65830800 fmul z0\.s, z0\.s, z3\.s
--.*: 65830800 fmul z0\.s, z0\.s, z3\.s
--.*: 659f0800 fmul z0\.s, z0\.s, z31\.s
--.*: 659f0800 fmul z0\.s, z0\.s, z31\.s
--.*: 65c00800 fmul z0\.d, z0\.d, z0\.d
--.*: 65c00800 fmul z0\.d, z0\.d, z0\.d
--.*: 65c00801 fmul z1\.d, z0\.d, z0\.d
--.*: 65c00801 fmul z1\.d, z0\.d, z0\.d
--.*: 65c0081f fmul z31\.d, z0\.d, z0\.d
--.*: 65c0081f fmul z31\.d, z0\.d, z0\.d
--.*: 65c00840 fmul z0\.d, z2\.d, z0\.d
--.*: 65c00840 fmul z0\.d, z2\.d, z0\.d
--.*: 65c00be0 fmul z0\.d, z31\.d, z0\.d
--.*: 65c00be0 fmul z0\.d, z31\.d, z0\.d
--.*: 65c30800 fmul z0\.d, z0\.d, z3\.d
--.*: 65c30800 fmul z0\.d, z0\.d, z3\.d
--.*: 65df0800 fmul z0\.d, z0\.d, z31\.d
--.*: 65df0800 fmul z0\.d, z0\.d, z31\.d
--.*: 65428000 fmul z0\.h, p0/m, z0\.h, z0\.h
--.*: 65428000 fmul z0\.h, p0/m, z0\.h, z0\.h
--.*: 65428001 fmul z1\.h, p0/m, z1\.h, z0\.h
--.*: 65428001 fmul z1\.h, p0/m, z1\.h, z0\.h
--.*: 6542801f fmul z31\.h, p0/m, z31\.h, z0\.h
--.*: 6542801f fmul z31\.h, p0/m, z31\.h, z0\.h
--.*: 65428800 fmul z0\.h, p2/m, z0\.h, z0\.h
--.*: 65428800 fmul z0\.h, p2/m, z0\.h, z0\.h
--.*: 65429c00 fmul z0\.h, p7/m, z0\.h, z0\.h
--.*: 65429c00 fmul z0\.h, p7/m, z0\.h, z0\.h
--.*: 65428003 fmul z3\.h, p0/m, z3\.h, z0\.h
--.*: 65428003 fmul z3\.h, p0/m, z3\.h, z0\.h
--.*: 65428080 fmul z0\.h, p0/m, z0\.h, z4\.h
--.*: 65428080 fmul z0\.h, p0/m, z0\.h, z4\.h
--.*: 654283e0 fmul z0\.h, p0/m, z0\.h, z31\.h
--.*: 654283e0 fmul z0\.h, p0/m, z0\.h, z31\.h
--.*: 65828000 fmul z0\.s, p0/m, z0\.s, z0\.s
--.*: 65828000 fmul z0\.s, p0/m, z0\.s, z0\.s
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--.*: 65828001 fmul z1\.s, p0/m, z1\.s, z0\.s
--.*: 6582801f fmul z31\.s, p0/m, z31\.s, z0\.s
--.*: 6582801f fmul z31\.s, p0/m, z31\.s, z0\.s
--.*: 65828800 fmul z0\.s, p2/m, z0\.s, z0\.s
--.*: 65828800 fmul z0\.s, p2/m, z0\.s, z0\.s
--.*: 65829c00 fmul z0\.s, p7/m, z0\.s, z0\.s
--.*: 65829c00 fmul z0\.s, p7/m, z0\.s, z0\.s
--.*: 65828003 fmul z3\.s, p0/m, z3\.s, z0\.s
--.*: 65828003 fmul z3\.s, p0/m, z3\.s, z0\.s
--.*: 65828080 fmul z0\.s, p0/m, z0\.s, z4\.s
--.*: 65828080 fmul z0\.s, p0/m, z0\.s, z4\.s
--.*: 658283e0 fmul z0\.s, p0/m, z0\.s, z31\.s
--.*: 658283e0 fmul z0\.s, p0/m, z0\.s, z31\.s
--.*: 65c28000 fmul z0\.d, p0/m, z0\.d, z0\.d
--.*: 65c28000 fmul z0\.d, p0/m, z0\.d, z0\.d
--.*: 65c28001 fmul z1\.d, p0/m, z1\.d, z0\.d
--.*: 65c28001 fmul z1\.d, p0/m, z1\.d, z0\.d
--.*: 65c2801f fmul z31\.d, p0/m, z31\.d, z0\.d
--.*: 65c2801f fmul z31\.d, p0/m, z31\.d, z0\.d
--.*: 65c28800 fmul z0\.d, p2/m, z0\.d, z0\.d
--.*: 65c28800 fmul z0\.d, p2/m, z0\.d, z0\.d
--.*: 65c29c00 fmul z0\.d, p7/m, z0\.d, z0\.d
--.*: 65c29c00 fmul z0\.d, p7/m, z0\.d, z0\.d
--.*: 65c28003 fmul z3\.d, p0/m, z3\.d, z0\.d
--.*: 65c28003 fmul z3\.d, p0/m, z3\.d, z0\.d
--.*: 65c28080 fmul z0\.d, p0/m, z0\.d, z4\.d
--.*: 65c28080 fmul z0\.d, p0/m, z0\.d, z4\.d
--.*: 65c283e0 fmul z0\.d, p0/m, z0\.d, z31\.d
--.*: 65c283e0 fmul z0\.d, p0/m, z0\.d, z31\.d
--.*: 655a8000 fmul z0\.h, p0/m, z0\.h, #0\.5
--.*: 655a8000 fmul z0\.h, p0/m, z0\.h, #0\.5
--.*: 655a8000 fmul z0\.h, p0/m, z0\.h, #0\.5
--.*: 655a8000 fmul z0\.h, p0/m, z0\.h, #0\.5
--.*: 655a8001 fmul z1\.h, p0/m, z1\.h, #0\.5
--.*: 655a8001 fmul z1\.h, p0/m, z1\.h, #0\.5
--.*: 655a8001 fmul z1\.h, p0/m, z1\.h, #0\.5
--.*: 655a8001 fmul z1\.h, p0/m, z1\.h, #0\.5
--.*: 655a801f fmul z31\.h, p0/m, z31\.h, #0\.5
--.*: 655a801f fmul z31\.h, p0/m, z31\.h, #0\.5
--.*: 655a801f fmul z31\.h, p0/m, z31\.h, #0\.5
--.*: 655a801f fmul z31\.h, p0/m, z31\.h, #0\.5
--.*: 655a8800 fmul z0\.h, p2/m, z0\.h, #0\.5
--.*: 655a8800 fmul z0\.h, p2/m, z0\.h, #0\.5
--.*: 655a8800 fmul z0\.h, p2/m, z0\.h, #0\.5
--.*: 655a8800 fmul z0\.h, p2/m, z0\.h, #0\.5
--.*: 655a9c00 fmul z0\.h, p7/m, z0\.h, #0\.5
--.*: 655a9c00 fmul z0\.h, p7/m, z0\.h, #0\.5
--.*: 655a9c00 fmul z0\.h, p7/m, z0\.h, #0\.5
--.*: 655a9c00 fmul z0\.h, p7/m, z0\.h, #0\.5
--.*: 655a8003 fmul z3\.h, p0/m, z3\.h, #0\.5
--.*: 655a8003 fmul z3\.h, p0/m, z3\.h, #0\.5
--.*: 655a8003 fmul z3\.h, p0/m, z3\.h, #0\.5
--.*: 655a8003 fmul z3\.h, p0/m, z3\.h, #0\.5
--.*: 655a8020 fmul z0\.h, p0/m, z0\.h, #2\.0
--.*: 655a8020 fmul z0\.h, p0/m, z0\.h, #2\.0
--.*: 655a8020 fmul z0\.h, p0/m, z0\.h, #2\.0
--.*: 655a8020 fmul z0\.h, p0/m, z0\.h, #2\.0
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--.*: 659a8000 fmul z0\.s, p0/m, z0\.s, #0\.5
--.*: 659a8000 fmul z0\.s, p0/m, z0\.s, #0\.5
--.*: 659a8000 fmul z0\.s, p0/m, z0\.s, #0\.5
--.*: 659a8001 fmul z1\.s, p0/m, z1\.s, #0\.5
--.*: 659a8001 fmul z1\.s, p0/m, z1\.s, #0\.5
--.*: 659a8001 fmul z1\.s, p0/m, z1\.s, #0\.5
--.*: 659a8001 fmul z1\.s, p0/m, z1\.s, #0\.5
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--.*: 659a801f fmul z31\.s, p0/m, z31\.s, #0\.5
--.*: 659a801f fmul z31\.s, p0/m, z31\.s, #0\.5
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--.*: 659a8800 fmul z0\.s, p2/m, z0\.s, #0\.5
--.*: 659a8800 fmul z0\.s, p2/m, z0\.s, #0\.5
--.*: 659a8800 fmul z0\.s, p2/m, z0\.s, #0\.5
--.*: 659a9c00 fmul z0\.s, p7/m, z0\.s, #0\.5
--.*: 659a9c00 fmul z0\.s, p7/m, z0\.s, #0\.5
--.*: 659a9c00 fmul z0\.s, p7/m, z0\.s, #0\.5
--.*: 659a9c00 fmul z0\.s, p7/m, z0\.s, #0\.5
--.*: 659a8003 fmul z3\.s, p0/m, z3\.s, #0\.5
--.*: 659a8003 fmul z3\.s, p0/m, z3\.s, #0\.5
--.*: 659a8003 fmul z3\.s, p0/m, z3\.s, #0\.5
--.*: 659a8003 fmul z3\.s, p0/m, z3\.s, #0\.5
--.*: 659a8020 fmul z0\.s, p0/m, z0\.s, #2\.0
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--.*: 659a8020 fmul z0\.s, p0/m, z0\.s, #2\.0
--.*: 659a8020 fmul z0\.s, p0/m, z0\.s, #2\.0
--.*: 65da8000 fmul z0\.d, p0/m, z0\.d, #0\.5
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--.*: 65da8000 fmul z0\.d, p0/m, z0\.d, #0\.5
--.*: 65da8000 fmul z0\.d, p0/m, z0\.d, #0\.5
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--.*: 65da8001 fmul z1\.d, p0/m, z1\.d, #0\.5
--.*: 65da8001 fmul z1\.d, p0/m, z1\.d, #0\.5
--.*: 65da8001 fmul z1\.d, p0/m, z1\.d, #0\.5
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--.*: 65da801f fmul z31\.d, p0/m, z31\.d, #0\.5
--.*: 65da801f fmul z31\.d, p0/m, z31\.d, #0\.5
--.*: 65da801f fmul z31\.d, p0/m, z31\.d, #0\.5
--.*: 65da8800 fmul z0\.d, p2/m, z0\.d, #0\.5
--.*: 65da8800 fmul z0\.d, p2/m, z0\.d, #0\.5
--.*: 65da8800 fmul z0\.d, p2/m, z0\.d, #0\.5
--.*: 65da8800 fmul z0\.d, p2/m, z0\.d, #0\.5
--.*: 65da9c00 fmul z0\.d, p7/m, z0\.d, #0\.5
--.*: 65da9c00 fmul z0\.d, p7/m, z0\.d, #0\.5
--.*: 65da9c00 fmul z0\.d, p7/m, z0\.d, #0\.5
--.*: 65da9c00 fmul z0\.d, p7/m, z0\.d, #0\.5
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--.*: 65da8003 fmul z3\.d, p0/m, z3\.d, #0\.5
--.*: 65da8003 fmul z3\.d, p0/m, z3\.d, #0\.5
--.*: 65da8003 fmul z3\.d, p0/m, z3\.d, #0\.5
--.*: 65da8020 fmul z0\.d, p0/m, z0\.d, #2\.0
--.*: 65da8020 fmul z0\.d, p0/m, z0\.d, #2\.0
--.*: 65da8020 fmul z0\.d, p0/m, z0\.d, #2\.0
--.*: 65da8020 fmul z0\.d, p0/m, z0\.d, #2\.0
--.*: 64202000 fmul z0\.h, z0\.h, z0\.h\[0\]
--.*: 64202000 fmul z0\.h, z0\.h, z0\.h\[0\]
--.*: 64202001 fmul z1\.h, z0\.h, z0\.h\[0\]
--.*: 64202001 fmul z1\.h, z0\.h, z0\.h\[0\]
--.*: 6420201f fmul z31\.h, z0\.h, z0\.h\[0\]
--.*: 6420201f fmul z31\.h, z0\.h, z0\.h\[0\]
--.*: 64202040 fmul z0\.h, z2\.h, z0\.h\[0\]
--.*: 64202040 fmul z0\.h, z2\.h, z0\.h\[0\]
--.*: 642023e0 fmul z0\.h, z31\.h, z0\.h\[0\]
--.*: 642023e0 fmul z0\.h, z31\.h, z0\.h\[0\]
--.*: 64232000 fmul z0\.h, z0\.h, z3\.h\[0\]
--.*: 64232000 fmul z0\.h, z0\.h, z3\.h\[0\]
--.*: 64272000 fmul z0\.h, z0\.h, z7\.h\[0\]
--.*: 64272000 fmul z0\.h, z0\.h, z7\.h\[0\]
--.*: 64282000 fmul z0\.h, z0\.h, z0\.h\[1\]
--.*: 64282000 fmul z0\.h, z0\.h, z0\.h\[1\]
--.*: 642c2000 fmul z0\.h, z0\.h, z4\.h\[1\]
--.*: 642c2000 fmul z0\.h, z0\.h, z4\.h\[1\]
--.*: 64632000 fmul z0\.h, z0\.h, z3\.h\[4\]
--.*: 64632000 fmul z0\.h, z0\.h, z3\.h\[4\]
--.*: 64782000 fmul z0\.h, z0\.h, z0\.h\[7\]
--.*: 64782000 fmul z0\.h, z0\.h, z0\.h\[7\]
--.*: 647d2000 fmul z0\.h, z0\.h, z5\.h\[7\]
--.*: 647d2000 fmul z0\.h, z0\.h, z5\.h\[7\]
--.*: 64a02000 fmul z0\.s, z0\.s, z0\.s\[0\]
--.*: 64a02000 fmul z0\.s, z0\.s, z0\.s\[0\]
--.*: 64a02001 fmul z1\.s, z0\.s, z0\.s\[0\]
--.*: 64a02001 fmul z1\.s, z0\.s, z0\.s\[0\]
--.*: 64a0201f fmul z31\.s, z0\.s, z0\.s\[0\]
--.*: 64a0201f fmul z31\.s, z0\.s, z0\.s\[0\]
--.*: 64a02040 fmul z0\.s, z2\.s, z0\.s\[0\]
--.*: 64a02040 fmul z0\.s, z2\.s, z0\.s\[0\]
--.*: 64a023e0 fmul z0\.s, z31\.s, z0\.s\[0\]
--.*: 64a023e0 fmul z0\.s, z31\.s, z0\.s\[0\]
--.*: 64a32000 fmul z0\.s, z0\.s, z3\.s\[0\]
--.*: 64a32000 fmul z0\.s, z0\.s, z3\.s\[0\]
--.*: 64a72000 fmul z0\.s, z0\.s, z7\.s\[0\]
--.*: 64a72000 fmul z0\.s, z0\.s, z7\.s\[0\]
--.*: 64a82000 fmul z0\.s, z0\.s, z0\.s\[1\]
--.*: 64a82000 fmul z0\.s, z0\.s, z0\.s\[1\]
--.*: 64ac2000 fmul z0\.s, z0\.s, z4\.s\[1\]
--.*: 64ac2000 fmul z0\.s, z0\.s, z4\.s\[1\]
--.*: 64b32000 fmul z0\.s, z0\.s, z3\.s\[2\]
--.*: 64b32000 fmul z0\.s, z0\.s, z3\.s\[2\]
--.*: 64b82000 fmul z0\.s, z0\.s, z0\.s\[3\]
--.*: 64b82000 fmul z0\.s, z0\.s, z0\.s\[3\]
--.*: 64bd2000 fmul z0\.s, z0\.s, z5\.s\[3\]
--.*: 64bd2000 fmul z0\.s, z0\.s, z5\.s\[3\]
--.*: 64e02000 fmul z0\.d, z0\.d, z0\.d\[0\]
--.*: 64e02000 fmul z0\.d, z0\.d, z0\.d\[0\]
--.*: 64e02001 fmul z1\.d, z0\.d, z0\.d\[0\]
--.*: 64e02001 fmul z1\.d, z0\.d, z0\.d\[0\]
--.*: 64e0201f fmul z31\.d, z0\.d, z0\.d\[0\]
--.*: 64e0201f fmul z31\.d, z0\.d, z0\.d\[0\]
--.*: 64e02040 fmul z0\.d, z2\.d, z0\.d\[0\]
--.*: 64e02040 fmul z0\.d, z2\.d, z0\.d\[0\]
--.*: 64e023e0 fmul z0\.d, z31\.d, z0\.d\[0\]
--.*: 64e023e0 fmul z0\.d, z31\.d, z0\.d\[0\]
--.*: 64e32000 fmul z0\.d, z0\.d, z3\.d\[0\]
--.*: 64e32000 fmul z0\.d, z0\.d, z3\.d\[0\]
--.*: 64ef2000 fmul z0\.d, z0\.d, z15\.d\[0\]
--.*: 64ef2000 fmul z0\.d, z0\.d, z15\.d\[0\]
--.*: 64f02000 fmul z0\.d, z0\.d, z0\.d\[1\]
--.*: 64f02000 fmul z0\.d, z0\.d, z0\.d\[1\]
--.*: 64fb2000 fmul z0\.d, z0\.d, z11\.d\[1\]
--.*: 64fb2000 fmul z0\.d, z0\.d, z11\.d\[1\]
--.*: 654a8000 fmulx z0\.h, p0/m, z0\.h, z0\.h
--.*: 654a8000 fmulx z0\.h, p0/m, z0\.h, z0\.h
--.*: 654a8001 fmulx z1\.h, p0/m, z1\.h, z0\.h
--.*: 654a8001 fmulx z1\.h, p0/m, z1\.h, z0\.h
--.*: 654a801f fmulx z31\.h, p0/m, z31\.h, z0\.h
--.*: 654a801f fmulx z31\.h, p0/m, z31\.h, z0\.h
--.*: 654a8800 fmulx z0\.h, p2/m, z0\.h, z0\.h
--.*: 654a8800 fmulx z0\.h, p2/m, z0\.h, z0\.h
--.*: 654a9c00 fmulx z0\.h, p7/m, z0\.h, z0\.h
--.*: 654a9c00 fmulx z0\.h, p7/m, z0\.h, z0\.h
--.*: 654a8003 fmulx z3\.h, p0/m, z3\.h, z0\.h
--.*: 654a8003 fmulx z3\.h, p0/m, z3\.h, z0\.h
--.*: 654a8080 fmulx z0\.h, p0/m, z0\.h, z4\.h
--.*: 654a8080 fmulx z0\.h, p0/m, z0\.h, z4\.h
--.*: 654a83e0 fmulx z0\.h, p0/m, z0\.h, z31\.h
--.*: 654a83e0 fmulx z0\.h, p0/m, z0\.h, z31\.h
--.*: 658a8000 fmulx z0\.s, p0/m, z0\.s, z0\.s
--.*: 658a8000 fmulx z0\.s, p0/m, z0\.s, z0\.s
--.*: 658a8001 fmulx z1\.s, p0/m, z1\.s, z0\.s
--.*: 658a8001 fmulx z1\.s, p0/m, z1\.s, z0\.s
--.*: 658a801f fmulx z31\.s, p0/m, z31\.s, z0\.s
--.*: 658a801f fmulx z31\.s, p0/m, z31\.s, z0\.s
--.*: 658a8800 fmulx z0\.s, p2/m, z0\.s, z0\.s
--.*: 658a8800 fmulx z0\.s, p2/m, z0\.s, z0\.s
--.*: 658a9c00 fmulx z0\.s, p7/m, z0\.s, z0\.s
--.*: 658a9c00 fmulx z0\.s, p7/m, z0\.s, z0\.s
--.*: 658a8003 fmulx z3\.s, p0/m, z3\.s, z0\.s
--.*: 658a8003 fmulx z3\.s, p0/m, z3\.s, z0\.s
--.*: 658a8080 fmulx z0\.s, p0/m, z0\.s, z4\.s
--.*: 658a8080 fmulx z0\.s, p0/m, z0\.s, z4\.s
--.*: 658a83e0 fmulx z0\.s, p0/m, z0\.s, z31\.s
--.*: 658a83e0 fmulx z0\.s, p0/m, z0\.s, z31\.s
--.*: 65ca8000 fmulx z0\.d, p0/m, z0\.d, z0\.d
--.*: 65ca8000 fmulx z0\.d, p0/m, z0\.d, z0\.d
--.*: 65ca8001 fmulx z1\.d, p0/m, z1\.d, z0\.d
--.*: 65ca8001 fmulx z1\.d, p0/m, z1\.d, z0\.d
--.*: 65ca801f fmulx z31\.d, p0/m, z31\.d, z0\.d
--.*: 65ca801f fmulx z31\.d, p0/m, z31\.d, z0\.d
--.*: 65ca8800 fmulx z0\.d, p2/m, z0\.d, z0\.d
--.*: 65ca8800 fmulx z0\.d, p2/m, z0\.d, z0\.d
--.*: 65ca9c00 fmulx z0\.d, p7/m, z0\.d, z0\.d
--.*: 65ca9c00 fmulx z0\.d, p7/m, z0\.d, z0\.d
--.*: 65ca8003 fmulx z3\.d, p0/m, z3\.d, z0\.d
--.*: 65ca8003 fmulx z3\.d, p0/m, z3\.d, z0\.d
--.*: 65ca8080 fmulx z0\.d, p0/m, z0\.d, z4\.d
--.*: 65ca8080 fmulx z0\.d, p0/m, z0\.d, z4\.d
--.*: 65ca83e0 fmulx z0\.d, p0/m, z0\.d, z31\.d
--.*: 65ca83e0 fmulx z0\.d, p0/m, z0\.d, z31\.d
--.*: 045da000 fneg z0\.h, p0/m, z0\.h
--.*: 045da000 fneg z0\.h, p0/m, z0\.h
--.*: 045da001 fneg z1\.h, p0/m, z0\.h
--.*: 045da001 fneg z1\.h, p0/m, z0\.h
--.*: 045da01f fneg z31\.h, p0/m, z0\.h
--.*: 045da01f fneg z31\.h, p0/m, z0\.h
--.*: 045da800 fneg z0\.h, p2/m, z0\.h
--.*: 045da800 fneg z0\.h, p2/m, z0\.h
--.*: 045dbc00 fneg z0\.h, p7/m, z0\.h
--.*: 045dbc00 fneg z0\.h, p7/m, z0\.h
--.*: 045da060 fneg z0\.h, p0/m, z3\.h
--.*: 045da060 fneg z0\.h, p0/m, z3\.h
--.*: 045da3e0 fneg z0\.h, p0/m, z31\.h
--.*: 045da3e0 fneg z0\.h, p0/m, z31\.h
--.*: 049da000 fneg z0\.s, p0/m, z0\.s
--.*: 049da000 fneg z0\.s, p0/m, z0\.s
--.*: 049da001 fneg z1\.s, p0/m, z0\.s
--.*: 049da001 fneg z1\.s, p0/m, z0\.s
--.*: 049da01f fneg z31\.s, p0/m, z0\.s
--.*: 049da01f fneg z31\.s, p0/m, z0\.s
--.*: 049da800 fneg z0\.s, p2/m, z0\.s
--.*: 049da800 fneg z0\.s, p2/m, z0\.s
--.*: 049dbc00 fneg z0\.s, p7/m, z0\.s
--.*: 049dbc00 fneg z0\.s, p7/m, z0\.s
--.*: 049da060 fneg z0\.s, p0/m, z3\.s
--.*: 049da060 fneg z0\.s, p0/m, z3\.s
--.*: 049da3e0 fneg z0\.s, p0/m, z31\.s
--.*: 049da3e0 fneg z0\.s, p0/m, z31\.s
--.*: 04dda000 fneg z0\.d, p0/m, z0\.d
--.*: 04dda000 fneg z0\.d, p0/m, z0\.d
--.*: 04dda001 fneg z1\.d, p0/m, z0\.d
--.*: 04dda001 fneg z1\.d, p0/m, z0\.d
--.*: 04dda01f fneg z31\.d, p0/m, z0\.d
--.*: 04dda01f fneg z31\.d, p0/m, z0\.d
--.*: 04dda800 fneg z0\.d, p2/m, z0\.d
--.*: 04dda800 fneg z0\.d, p2/m, z0\.d
--.*: 04ddbc00 fneg z0\.d, p7/m, z0\.d
--.*: 04ddbc00 fneg z0\.d, p7/m, z0\.d
--.*: 04dda060 fneg z0\.d, p0/m, z3\.d
--.*: 04dda060 fneg z0\.d, p0/m, z3\.d
--.*: 04dda3e0 fneg z0\.d, p0/m, z31\.d
--.*: 04dda3e0 fneg z0\.d, p0/m, z31\.d
--.*: 6560c000 fnmad z0\.h, p0/m, z0\.h, z0\.h
--.*: 6560c000 fnmad z0\.h, p0/m, z0\.h, z0\.h
--.*: 6560c001 fnmad z1\.h, p0/m, z0\.h, z0\.h
--.*: 6560c001 fnmad z1\.h, p0/m, z0\.h, z0\.h
--.*: 6560c01f fnmad z31\.h, p0/m, z0\.h, z0\.h
--.*: 6560c01f fnmad z31\.h, p0/m, z0\.h, z0\.h
--.*: 6560c800 fnmad z0\.h, p2/m, z0\.h, z0\.h
--.*: 6560c800 fnmad z0\.h, p2/m, z0\.h, z0\.h
--.*: 6560dc00 fnmad z0\.h, p7/m, z0\.h, z0\.h
--.*: 6560dc00 fnmad z0\.h, p7/m, z0\.h, z0\.h
--.*: 6560c060 fnmad z0\.h, p0/m, z3\.h, z0\.h
--.*: 6560c060 fnmad z0\.h, p0/m, z3\.h, z0\.h
--.*: 6560c3e0 fnmad z0\.h, p0/m, z31\.h, z0\.h
--.*: 6560c3e0 fnmad z0\.h, p0/m, z31\.h, z0\.h
--.*: 6564c000 fnmad z0\.h, p0/m, z0\.h, z4\.h
--.*: 6564c000 fnmad z0\.h, p0/m, z0\.h, z4\.h
--.*: 657fc000 fnmad z0\.h, p0/m, z0\.h, z31\.h
--.*: 657fc000 fnmad z0\.h, p0/m, z0\.h, z31\.h
--.*: 65a0c000 fnmad z0\.s, p0/m, z0\.s, z0\.s
--.*: 65a0c000 fnmad z0\.s, p0/m, z0\.s, z0\.s
--.*: 65a0c001 fnmad z1\.s, p0/m, z0\.s, z0\.s
--.*: 65a0c001 fnmad z1\.s, p0/m, z0\.s, z0\.s
--.*: 65a0c01f fnmad z31\.s, p0/m, z0\.s, z0\.s
--.*: 65a0c01f fnmad z31\.s, p0/m, z0\.s, z0\.s
--.*: 65a0c800 fnmad z0\.s, p2/m, z0\.s, z0\.s
--.*: 65a0c800 fnmad z0\.s, p2/m, z0\.s, z0\.s
--.*: 65a0dc00 fnmad z0\.s, p7/m, z0\.s, z0\.s
--.*: 65a0dc00 fnmad z0\.s, p7/m, z0\.s, z0\.s
--.*: 65a0c060 fnmad z0\.s, p0/m, z3\.s, z0\.s
--.*: 65a0c060 fnmad z0\.s, p0/m, z3\.s, z0\.s
--.*: 65a0c3e0 fnmad z0\.s, p0/m, z31\.s, z0\.s
--.*: 65a0c3e0 fnmad z0\.s, p0/m, z31\.s, z0\.s
--.*: 65a4c000 fnmad z0\.s, p0/m, z0\.s, z4\.s
--.*: 65a4c000 fnmad z0\.s, p0/m, z0\.s, z4\.s
--.*: 65bfc000 fnmad z0\.s, p0/m, z0\.s, z31\.s
--.*: 65bfc000 fnmad z0\.s, p0/m, z0\.s, z31\.s
--.*: 65e0c000 fnmad z0\.d, p0/m, z0\.d, z0\.d
--.*: 65e0c000 fnmad z0\.d, p0/m, z0\.d, z0\.d
--.*: 65e0c001 fnmad z1\.d, p0/m, z0\.d, z0\.d
--.*: 65e0c001 fnmad z1\.d, p0/m, z0\.d, z0\.d
--.*: 65e0c01f fnmad z31\.d, p0/m, z0\.d, z0\.d
--.*: 65e0c01f fnmad z31\.d, p0/m, z0\.d, z0\.d
--.*: 65e0c800 fnmad z0\.d, p2/m, z0\.d, z0\.d
--.*: 65e0c800 fnmad z0\.d, p2/m, z0\.d, z0\.d
--.*: 65e0dc00 fnmad z0\.d, p7/m, z0\.d, z0\.d
--.*: 65e0dc00 fnmad z0\.d, p7/m, z0\.d, z0\.d
--.*: 65e0c060 fnmad z0\.d, p0/m, z3\.d, z0\.d
--.*: 65e0c060 fnmad z0\.d, p0/m, z3\.d, z0\.d
--.*: 65e0c3e0 fnmad z0\.d, p0/m, z31\.d, z0\.d
--.*: 65e0c3e0 fnmad z0\.d, p0/m, z31\.d, z0\.d
--.*: 65e4c000 fnmad z0\.d, p0/m, z0\.d, z4\.d
--.*: 65e4c000 fnmad z0\.d, p0/m, z0\.d, z4\.d
--.*: 65ffc000 fnmad z0\.d, p0/m, z0\.d, z31\.d
--.*: 65ffc000 fnmad z0\.d, p0/m, z0\.d, z31\.d
--.*: 65604000 fnmla z0\.h, p0/m, z0\.h, z0\.h
--.*: 65604000 fnmla z0\.h, p0/m, z0\.h, z0\.h
--.*: 65604001 fnmla z1\.h, p0/m, z0\.h, z0\.h
--.*: 65604001 fnmla z1\.h, p0/m, z0\.h, z0\.h
--.*: 6560401f fnmla z31\.h, p0/m, z0\.h, z0\.h
--.*: 6560401f fnmla z31\.h, p0/m, z0\.h, z0\.h
--.*: 65604800 fnmla z0\.h, p2/m, z0\.h, z0\.h
--.*: 65604800 fnmla z0\.h, p2/m, z0\.h, z0\.h
--.*: 65605c00 fnmla z0\.h, p7/m, z0\.h, z0\.h
--.*: 65605c00 fnmla z0\.h, p7/m, z0\.h, z0\.h
--.*: 65604060 fnmla z0\.h, p0/m, z3\.h, z0\.h
--.*: 65604060 fnmla z0\.h, p0/m, z3\.h, z0\.h
--.*: 656043e0 fnmla z0\.h, p0/m, z31\.h, z0\.h
--.*: 656043e0 fnmla z0\.h, p0/m, z31\.h, z0\.h
--.*: 65644000 fnmla z0\.h, p0/m, z0\.h, z4\.h
--.*: 65644000 fnmla z0\.h, p0/m, z0\.h, z4\.h
--.*: 657f4000 fnmla z0\.h, p0/m, z0\.h, z31\.h
--.*: 657f4000 fnmla z0\.h, p0/m, z0\.h, z31\.h
--.*: 65a04000 fnmla z0\.s, p0/m, z0\.s, z0\.s
--.*: 65a04000 fnmla z0\.s, p0/m, z0\.s, z0\.s
--.*: 65a04001 fnmla z1\.s, p0/m, z0\.s, z0\.s
--.*: 65a04001 fnmla z1\.s, p0/m, z0\.s, z0\.s
--.*: 65a0401f fnmla z31\.s, p0/m, z0\.s, z0\.s
--.*: 65a0401f fnmla z31\.s, p0/m, z0\.s, z0\.s
--.*: 65a04800 fnmla z0\.s, p2/m, z0\.s, z0\.s
--.*: 65a04800 fnmla z0\.s, p2/m, z0\.s, z0\.s
--.*: 65a05c00 fnmla z0\.s, p7/m, z0\.s, z0\.s
--.*: 65a05c00 fnmla z0\.s, p7/m, z0\.s, z0\.s
--.*: 65a04060 fnmla z0\.s, p0/m, z3\.s, z0\.s
--.*: 65a04060 fnmla z0\.s, p0/m, z3\.s, z0\.s
--.*: 65a043e0 fnmla z0\.s, p0/m, z31\.s, z0\.s
--.*: 65a043e0 fnmla z0\.s, p0/m, z31\.s, z0\.s
--.*: 65a44000 fnmla z0\.s, p0/m, z0\.s, z4\.s
--.*: 65a44000 fnmla z0\.s, p0/m, z0\.s, z4\.s
--.*: 65bf4000 fnmla z0\.s, p0/m, z0\.s, z31\.s
--.*: 65bf4000 fnmla z0\.s, p0/m, z0\.s, z31\.s
--.*: 65e04000 fnmla z0\.d, p0/m, z0\.d, z0\.d
--.*: 65e04000 fnmla z0\.d, p0/m, z0\.d, z0\.d
--.*: 65e04001 fnmla z1\.d, p0/m, z0\.d, z0\.d
--.*: 65e04001 fnmla z1\.d, p0/m, z0\.d, z0\.d
--.*: 65e0401f fnmla z31\.d, p0/m, z0\.d, z0\.d
--.*: 65e0401f fnmla z31\.d, p0/m, z0\.d, z0\.d
--.*: 65e04800 fnmla z0\.d, p2/m, z0\.d, z0\.d
--.*: 65e04800 fnmla z0\.d, p2/m, z0\.d, z0\.d
--.*: 65e05c00 fnmla z0\.d, p7/m, z0\.d, z0\.d
--.*: 65e05c00 fnmla z0\.d, p7/m, z0\.d, z0\.d
--.*: 65e04060 fnmla z0\.d, p0/m, z3\.d, z0\.d
--.*: 65e04060 fnmla z0\.d, p0/m, z3\.d, z0\.d
--.*: 65e043e0 fnmla z0\.d, p0/m, z31\.d, z0\.d
--.*: 65e043e0 fnmla z0\.d, p0/m, z31\.d, z0\.d
--.*: 65e44000 fnmla z0\.d, p0/m, z0\.d, z4\.d
--.*: 65e44000 fnmla z0\.d, p0/m, z0\.d, z4\.d
--.*: 65ff4000 fnmla z0\.d, p0/m, z0\.d, z31\.d
--.*: 65ff4000 fnmla z0\.d, p0/m, z0\.d, z31\.d
--.*: 65606000 fnmls z0\.h, p0/m, z0\.h, z0\.h
--.*: 65606000 fnmls z0\.h, p0/m, z0\.h, z0\.h
--.*: 65606001 fnmls z1\.h, p0/m, z0\.h, z0\.h
--.*: 65606001 fnmls z1\.h, p0/m, z0\.h, z0\.h
--.*: 6560601f fnmls z31\.h, p0/m, z0\.h, z0\.h
--.*: 6560601f fnmls z31\.h, p0/m, z0\.h, z0\.h
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--.*: 65c3801f fsubr z31\.d, p0/m, z31\.d, z0\.d
--.*: 65c3801f fsubr z31\.d, p0/m, z31\.d, z0\.d
--.*: 65c38800 fsubr z0\.d, p2/m, z0\.d, z0\.d
--.*: 65c38800 fsubr z0\.d, p2/m, z0\.d, z0\.d
--.*: 65c39c00 fsubr z0\.d, p7/m, z0\.d, z0\.d
--.*: 65c39c00 fsubr z0\.d, p7/m, z0\.d, z0\.d
--.*: 65c38003 fsubr z3\.d, p0/m, z3\.d, z0\.d
--.*: 65c38003 fsubr z3\.d, p0/m, z3\.d, z0\.d
--.*: 65c38080 fsubr z0\.d, p0/m, z0\.d, z4\.d
--.*: 65c38080 fsubr z0\.d, p0/m, z0\.d, z4\.d
--.*: 65c383e0 fsubr z0\.d, p0/m, z0\.d, z31\.d
--.*: 65c383e0 fsubr z0\.d, p0/m, z0\.d, z31\.d
--.*: 655b8000 fsubr z0\.h, p0/m, z0\.h, #0\.5
--.*: 655b8000 fsubr z0\.h, p0/m, z0\.h, #0\.5
--.*: 655b8000 fsubr z0\.h, p0/m, z0\.h, #0\.5
--.*: 655b8000 fsubr z0\.h, p0/m, z0\.h, #0\.5
--.*: 655b8001 fsubr z1\.h, p0/m, z1\.h, #0\.5
--.*: 655b8001 fsubr z1\.h, p0/m, z1\.h, #0\.5
--.*: 655b8001 fsubr z1\.h, p0/m, z1\.h, #0\.5
--.*: 655b8001 fsubr z1\.h, p0/m, z1\.h, #0\.5
--.*: 655b801f fsubr z31\.h, p0/m, z31\.h, #0\.5
--.*: 655b801f fsubr z31\.h, p0/m, z31\.h, #0\.5
--.*: 655b801f fsubr z31\.h, p0/m, z31\.h, #0\.5
--.*: 655b801f fsubr z31\.h, p0/m, z31\.h, #0\.5
--.*: 655b8800 fsubr z0\.h, p2/m, z0\.h, #0\.5
--.*: 655b8800 fsubr z0\.h, p2/m, z0\.h, #0\.5
--.*: 655b8800 fsubr z0\.h, p2/m, z0\.h, #0\.5
--.*: 655b8800 fsubr z0\.h, p2/m, z0\.h, #0\.5
--.*: 655b9c00 fsubr z0\.h, p7/m, z0\.h, #0\.5
--.*: 655b9c00 fsubr z0\.h, p7/m, z0\.h, #0\.5
--.*: 655b9c00 fsubr z0\.h, p7/m, z0\.h, #0\.5
--.*: 655b9c00 fsubr z0\.h, p7/m, z0\.h, #0\.5
--.*: 655b8003 fsubr z3\.h, p0/m, z3\.h, #0\.5
--.*: 655b8003 fsubr z3\.h, p0/m, z3\.h, #0\.5
--.*: 655b8003 fsubr z3\.h, p0/m, z3\.h, #0\.5
--.*: 655b8003 fsubr z3\.h, p0/m, z3\.h, #0\.5
--.*: 655b8020 fsubr z0\.h, p0/m, z0\.h, #1\.0
--.*: 655b8020 fsubr z0\.h, p0/m, z0\.h, #1\.0
--.*: 655b8020 fsubr z0\.h, p0/m, z0\.h, #1\.0
--.*: 655b8020 fsubr z0\.h, p0/m, z0\.h, #1\.0
--.*: 659b8000 fsubr z0\.s, p0/m, z0\.s, #0\.5
--.*: 659b8000 fsubr z0\.s, p0/m, z0\.s, #0\.5
--.*: 659b8000 fsubr z0\.s, p0/m, z0\.s, #0\.5
--.*: 659b8000 fsubr z0\.s, p0/m, z0\.s, #0\.5
--.*: 659b8001 fsubr z1\.s, p0/m, z1\.s, #0\.5
--.*: 659b8001 fsubr z1\.s, p0/m, z1\.s, #0\.5
--.*: 659b8001 fsubr z1\.s, p0/m, z1\.s, #0\.5
--.*: 659b8001 fsubr z1\.s, p0/m, z1\.s, #0\.5
--.*: 659b801f fsubr z31\.s, p0/m, z31\.s, #0\.5
--.*: 659b801f fsubr z31\.s, p0/m, z31\.s, #0\.5
--.*: 659b801f fsubr z31\.s, p0/m, z31\.s, #0\.5
--.*: 659b801f fsubr z31\.s, p0/m, z31\.s, #0\.5
--.*: 659b8800 fsubr z0\.s, p2/m, z0\.s, #0\.5
--.*: 659b8800 fsubr z0\.s, p2/m, z0\.s, #0\.5
--.*: 659b8800 fsubr z0\.s, p2/m, z0\.s, #0\.5
--.*: 659b8800 fsubr z0\.s, p2/m, z0\.s, #0\.5
--.*: 659b9c00 fsubr z0\.s, p7/m, z0\.s, #0\.5
--.*: 659b9c00 fsubr z0\.s, p7/m, z0\.s, #0\.5
--.*: 659b9c00 fsubr z0\.s, p7/m, z0\.s, #0\.5
--.*: 659b9c00 fsubr z0\.s, p7/m, z0\.s, #0\.5
--.*: 659b8003 fsubr z3\.s, p0/m, z3\.s, #0\.5
--.*: 659b8003 fsubr z3\.s, p0/m, z3\.s, #0\.5
--.*: 659b8003 fsubr z3\.s, p0/m, z3\.s, #0\.5
--.*: 659b8003 fsubr z3\.s, p0/m, z3\.s, #0\.5
--.*: 659b8020 fsubr z0\.s, p0/m, z0\.s, #1\.0
--.*: 659b8020 fsubr z0\.s, p0/m, z0\.s, #1\.0
--.*: 659b8020 fsubr z0\.s, p0/m, z0\.s, #1\.0
--.*: 659b8020 fsubr z0\.s, p0/m, z0\.s, #1\.0
--.*: 65db8000 fsubr z0\.d, p0/m, z0\.d, #0\.5
--.*: 65db8000 fsubr z0\.d, p0/m, z0\.d, #0\.5
--.*: 65db8000 fsubr z0\.d, p0/m, z0\.d, #0\.5
--.*: 65db8000 fsubr z0\.d, p0/m, z0\.d, #0\.5
--.*: 65db8001 fsubr z1\.d, p0/m, z1\.d, #0\.5
--.*: 65db8001 fsubr z1\.d, p0/m, z1\.d, #0\.5
--.*: 65db8001 fsubr z1\.d, p0/m, z1\.d, #0\.5
--.*: 65db8001 fsubr z1\.d, p0/m, z1\.d, #0\.5
--.*: 65db801f fsubr z31\.d, p0/m, z31\.d, #0\.5
--.*: 65db801f fsubr z31\.d, p0/m, z31\.d, #0\.5
--.*: 65db801f fsubr z31\.d, p0/m, z31\.d, #0\.5
--.*: 65db801f fsubr z31\.d, p0/m, z31\.d, #0\.5
--.*: 65db8800 fsubr z0\.d, p2/m, z0\.d, #0\.5
--.*: 65db8800 fsubr z0\.d, p2/m, z0\.d, #0\.5
--.*: 65db8800 fsubr z0\.d, p2/m, z0\.d, #0\.5
--.*: 65db8800 fsubr z0\.d, p2/m, z0\.d, #0\.5
--.*: 65db9c00 fsubr z0\.d, p7/m, z0\.d, #0\.5
--.*: 65db9c00 fsubr z0\.d, p7/m, z0\.d, #0\.5
--.*: 65db9c00 fsubr z0\.d, p7/m, z0\.d, #0\.5
--.*: 65db9c00 fsubr z0\.d, p7/m, z0\.d, #0\.5
--.*: 65db8003 fsubr z3\.d, p0/m, z3\.d, #0\.5
--.*: 65db8003 fsubr z3\.d, p0/m, z3\.d, #0\.5
--.*: 65db8003 fsubr z3\.d, p0/m, z3\.d, #0\.5
--.*: 65db8003 fsubr z3\.d, p0/m, z3\.d, #0\.5
--.*: 65db8020 fsubr z0\.d, p0/m, z0\.d, #1\.0
--.*: 65db8020 fsubr z0\.d, p0/m, z0\.d, #1\.0
--.*: 65db8020 fsubr z0\.d, p0/m, z0\.d, #1\.0
--.*: 65db8020 fsubr z0\.d, p0/m, z0\.d, #1\.0
--.*: 65508000 ftmad z0\.h, z0\.h, z0\.h, #0
--.*: 65508000 ftmad z0\.h, z0\.h, z0\.h, #0
--.*: 65508001 ftmad z1\.h, z1\.h, z0\.h, #0
--.*: 65508001 ftmad z1\.h, z1\.h, z0\.h, #0
--.*: 6550801f ftmad z31\.h, z31\.h, z0\.h, #0
--.*: 6550801f ftmad z31\.h, z31\.h, z0\.h, #0
--.*: 65508002 ftmad z2\.h, z2\.h, z0\.h, #0
--.*: 65508002 ftmad z2\.h, z2\.h, z0\.h, #0
--.*: 65508060 ftmad z0\.h, z0\.h, z3\.h, #0
--.*: 65508060 ftmad z0\.h, z0\.h, z3\.h, #0
--.*: 655083e0 ftmad z0\.h, z0\.h, z31\.h, #0
--.*: 655083e0 ftmad z0\.h, z0\.h, z31\.h, #0
--.*: 65538000 ftmad z0\.h, z0\.h, z0\.h, #3
--.*: 65538000 ftmad z0\.h, z0\.h, z0\.h, #3
--.*: 65548000 ftmad z0\.h, z0\.h, z0\.h, #4
--.*: 65548000 ftmad z0\.h, z0\.h, z0\.h, #4
--.*: 65558000 ftmad z0\.h, z0\.h, z0\.h, #5
--.*: 65558000 ftmad z0\.h, z0\.h, z0\.h, #5
--.*: 65578000 ftmad z0\.h, z0\.h, z0\.h, #7
--.*: 65578000 ftmad z0\.h, z0\.h, z0\.h, #7
--.*: 65908000 ftmad z0\.s, z0\.s, z0\.s, #0
--.*: 65908000 ftmad z0\.s, z0\.s, z0\.s, #0
--.*: 65908001 ftmad z1\.s, z1\.s, z0\.s, #0
--.*: 65908001 ftmad z1\.s, z1\.s, z0\.s, #0
--.*: 6590801f ftmad z31\.s, z31\.s, z0\.s, #0
--.*: 6590801f ftmad z31\.s, z31\.s, z0\.s, #0
--.*: 65908002 ftmad z2\.s, z2\.s, z0\.s, #0
--.*: 65908002 ftmad z2\.s, z2\.s, z0\.s, #0
--.*: 65908060 ftmad z0\.s, z0\.s, z3\.s, #0
--.*: 65908060 ftmad z0\.s, z0\.s, z3\.s, #0
--.*: 659083e0 ftmad z0\.s, z0\.s, z31\.s, #0
--.*: 659083e0 ftmad z0\.s, z0\.s, z31\.s, #0
--.*: 65938000 ftmad z0\.s, z0\.s, z0\.s, #3
--.*: 65938000 ftmad z0\.s, z0\.s, z0\.s, #3
--.*: 65948000 ftmad z0\.s, z0\.s, z0\.s, #4
--.*: 65948000 ftmad z0\.s, z0\.s, z0\.s, #4
--.*: 65958000 ftmad z0\.s, z0\.s, z0\.s, #5
--.*: 65958000 ftmad z0\.s, z0\.s, z0\.s, #5
--.*: 65978000 ftmad z0\.s, z0\.s, z0\.s, #7
--.*: 65978000 ftmad z0\.s, z0\.s, z0\.s, #7
--.*: 65d08000 ftmad z0\.d, z0\.d, z0\.d, #0
--.*: 65d08000 ftmad z0\.d, z0\.d, z0\.d, #0
--.*: 65d08001 ftmad z1\.d, z1\.d, z0\.d, #0
--.*: 65d08001 ftmad z1\.d, z1\.d, z0\.d, #0
--.*: 65d0801f ftmad z31\.d, z31\.d, z0\.d, #0
--.*: 65d0801f ftmad z31\.d, z31\.d, z0\.d, #0
--.*: 65d08002 ftmad z2\.d, z2\.d, z0\.d, #0
--.*: 65d08002 ftmad z2\.d, z2\.d, z0\.d, #0
--.*: 65d08060 ftmad z0\.d, z0\.d, z3\.d, #0
--.*: 65d08060 ftmad z0\.d, z0\.d, z3\.d, #0
--.*: 65d083e0 ftmad z0\.d, z0\.d, z31\.d, #0
--.*: 65d083e0 ftmad z0\.d, z0\.d, z31\.d, #0
--.*: 65d38000 ftmad z0\.d, z0\.d, z0\.d, #3
--.*: 65d38000 ftmad z0\.d, z0\.d, z0\.d, #3
--.*: 65d48000 ftmad z0\.d, z0\.d, z0\.d, #4
--.*: 65d48000 ftmad z0\.d, z0\.d, z0\.d, #4
--.*: 65d58000 ftmad z0\.d, z0\.d, z0\.d, #5
--.*: 65d58000 ftmad z0\.d, z0\.d, z0\.d, #5
--.*: 65d78000 ftmad z0\.d, z0\.d, z0\.d, #7
--.*: 65d78000 ftmad z0\.d, z0\.d, z0\.d, #7
--.*: 65400c00 ftsmul z0\.h, z0\.h, z0\.h
--.*: 65400c00 ftsmul z0\.h, z0\.h, z0\.h
--.*: 65400c01 ftsmul z1\.h, z0\.h, z0\.h
--.*: 65400c01 ftsmul z1\.h, z0\.h, z0\.h
--.*: 65400c1f ftsmul z31\.h, z0\.h, z0\.h
--.*: 65400c1f ftsmul z31\.h, z0\.h, z0\.h
--.*: 65400c40 ftsmul z0\.h, z2\.h, z0\.h
--.*: 65400c40 ftsmul z0\.h, z2\.h, z0\.h
--.*: 65400fe0 ftsmul z0\.h, z31\.h, z0\.h
--.*: 65400fe0 ftsmul z0\.h, z31\.h, z0\.h
--.*: 65430c00 ftsmul z0\.h, z0\.h, z3\.h
--.*: 65430c00 ftsmul z0\.h, z0\.h, z3\.h
--.*: 655f0c00 ftsmul z0\.h, z0\.h, z31\.h
--.*: 655f0c00 ftsmul z0\.h, z0\.h, z31\.h
--.*: 65800c00 ftsmul z0\.s, z0\.s, z0\.s
--.*: 65800c00 ftsmul z0\.s, z0\.s, z0\.s
--.*: 65800c01 ftsmul z1\.s, z0\.s, z0\.s
--.*: 65800c01 ftsmul z1\.s, z0\.s, z0\.s
--.*: 65800c1f ftsmul z31\.s, z0\.s, z0\.s
--.*: 65800c1f ftsmul z31\.s, z0\.s, z0\.s
--.*: 65800c40 ftsmul z0\.s, z2\.s, z0\.s
--.*: 65800c40 ftsmul z0\.s, z2\.s, z0\.s
--.*: 65800fe0 ftsmul z0\.s, z31\.s, z0\.s
--.*: 65800fe0 ftsmul z0\.s, z31\.s, z0\.s
--.*: 65830c00 ftsmul z0\.s, z0\.s, z3\.s
--.*: 65830c00 ftsmul z0\.s, z0\.s, z3\.s
--.*: 659f0c00 ftsmul z0\.s, z0\.s, z31\.s
--.*: 659f0c00 ftsmul z0\.s, z0\.s, z31\.s
--.*: 65c00c00 ftsmul z0\.d, z0\.d, z0\.d
--.*: 65c00c00 ftsmul z0\.d, z0\.d, z0\.d
--.*: 65c00c01 ftsmul z1\.d, z0\.d, z0\.d
--.*: 65c00c01 ftsmul z1\.d, z0\.d, z0\.d
--.*: 65c00c1f ftsmul z31\.d, z0\.d, z0\.d
--.*: 65c00c1f ftsmul z31\.d, z0\.d, z0\.d
--.*: 65c00c40 ftsmul z0\.d, z2\.d, z0\.d
--.*: 65c00c40 ftsmul z0\.d, z2\.d, z0\.d
--.*: 65c00fe0 ftsmul z0\.d, z31\.d, z0\.d
--.*: 65c00fe0 ftsmul z0\.d, z31\.d, z0\.d
--.*: 65c30c00 ftsmul z0\.d, z0\.d, z3\.d
--.*: 65c30c00 ftsmul z0\.d, z0\.d, z3\.d
--.*: 65df0c00 ftsmul z0\.d, z0\.d, z31\.d
--.*: 65df0c00 ftsmul z0\.d, z0\.d, z31\.d
--.*: 0460b000 ftssel z0\.h, z0\.h, z0\.h
--.*: 0460b000 ftssel z0\.h, z0\.h, z0\.h
--.*: 0460b001 ftssel z1\.h, z0\.h, z0\.h
--.*: 0460b001 ftssel z1\.h, z0\.h, z0\.h
--.*: 0460b01f ftssel z31\.h, z0\.h, z0\.h
--.*: 0460b01f ftssel z31\.h, z0\.h, z0\.h
--.*: 0460b040 ftssel z0\.h, z2\.h, z0\.h
--.*: 0460b040 ftssel z0\.h, z2\.h, z0\.h
--.*: 0460b3e0 ftssel z0\.h, z31\.h, z0\.h
--.*: 0460b3e0 ftssel z0\.h, z31\.h, z0\.h
--.*: 0463b000 ftssel z0\.h, z0\.h, z3\.h
--.*: 0463b000 ftssel z0\.h, z0\.h, z3\.h
--.*: 047fb000 ftssel z0\.h, z0\.h, z31\.h
--.*: 047fb000 ftssel z0\.h, z0\.h, z31\.h
--.*: 04a0b000 ftssel z0\.s, z0\.s, z0\.s
--.*: 04a0b000 ftssel z0\.s, z0\.s, z0\.s
--.*: 04a0b001 ftssel z1\.s, z0\.s, z0\.s
--.*: 04a0b001 ftssel z1\.s, z0\.s, z0\.s
--.*: 04a0b01f ftssel z31\.s, z0\.s, z0\.s
--.*: 04a0b01f ftssel z31\.s, z0\.s, z0\.s
--.*: 04a0b040 ftssel z0\.s, z2\.s, z0\.s
--.*: 04a0b040 ftssel z0\.s, z2\.s, z0\.s
--.*: 04a0b3e0 ftssel z0\.s, z31\.s, z0\.s
--.*: 04a0b3e0 ftssel z0\.s, z31\.s, z0\.s
--.*: 04a3b000 ftssel z0\.s, z0\.s, z3\.s
--.*: 04a3b000 ftssel z0\.s, z0\.s, z3\.s
--.*: 04bfb000 ftssel z0\.s, z0\.s, z31\.s
--.*: 04bfb000 ftssel z0\.s, z0\.s, z31\.s
--.*: 04e0b000 ftssel z0\.d, z0\.d, z0\.d
--.*: 04e0b000 ftssel z0\.d, z0\.d, z0\.d
--.*: 04e0b001 ftssel z1\.d, z0\.d, z0\.d
--.*: 04e0b001 ftssel z1\.d, z0\.d, z0\.d
--.*: 04e0b01f ftssel z31\.d, z0\.d, z0\.d
--.*: 04e0b01f ftssel z31\.d, z0\.d, z0\.d
--.*: 04e0b040 ftssel z0\.d, z2\.d, z0\.d
--.*: 04e0b040 ftssel z0\.d, z2\.d, z0\.d
--.*: 04e0b3e0 ftssel z0\.d, z31\.d, z0\.d
--.*: 04e0b3e0 ftssel z0\.d, z31\.d, z0\.d
--.*: 04e3b000 ftssel z0\.d, z0\.d, z3\.d
--.*: 04e3b000 ftssel z0\.d, z0\.d, z3\.d
--.*: 04ffb000 ftssel z0\.d, z0\.d, z31\.d
--.*: 04ffb000 ftssel z0\.d, z0\.d, z31\.d
--.*: 0430e000 incb x0, pow2
--.*: 0430e000 incb x0, pow2
--.*: 0430e000 incb x0, pow2
--.*: 0430e001 incb x1, pow2
--.*: 0430e001 incb x1, pow2
--.*: 0430e001 incb x1, pow2
--.*: 0430e01f incb xzr, pow2
--.*: 0430e01f incb xzr, pow2
--.*: 0430e01f incb xzr, pow2
--.*: 0430e020 incb x0, vl1
--.*: 0430e020 incb x0, vl1
--.*: 0430e020 incb x0, vl1
--.*: 0430e040 incb x0, vl2
--.*: 0430e040 incb x0, vl2
--.*: 0430e040 incb x0, vl2
--.*: 0430e060 incb x0, vl3
--.*: 0430e060 incb x0, vl3
--.*: 0430e060 incb x0, vl3
--.*: 0430e080 incb x0, vl4
--.*: 0430e080 incb x0, vl4
--.*: 0430e080 incb x0, vl4
--.*: 0430e0a0 incb x0, vl5
--.*: 0430e0a0 incb x0, vl5
--.*: 0430e0a0 incb x0, vl5
--.*: 0430e0c0 incb x0, vl6
--.*: 0430e0c0 incb x0, vl6
--.*: 0430e0c0 incb x0, vl6
--.*: 0430e0e0 incb x0, vl7
--.*: 0430e0e0 incb x0, vl7
--.*: 0430e0e0 incb x0, vl7
--.*: 0430e100 incb x0, vl8
--.*: 0430e100 incb x0, vl8
--.*: 0430e100 incb x0, vl8
--.*: 0430e120 incb x0, vl16
--.*: 0430e120 incb x0, vl16
--.*: 0430e120 incb x0, vl16
--.*: 0430e140 incb x0, vl32
--.*: 0430e140 incb x0, vl32
--.*: 0430e140 incb x0, vl32
--.*: 0430e160 incb x0, vl64
--.*: 0430e160 incb x0, vl64
--.*: 0430e160 incb x0, vl64
--.*: 0430e180 incb x0, vl128
--.*: 0430e180 incb x0, vl128
--.*: 0430e180 incb x0, vl128
--.*: 0430e1a0 incb x0, vl256
--.*: 0430e1a0 incb x0, vl256
--.*: 0430e1a0 incb x0, vl256
--.*: 0430e1c0 incb x0, #14
--.*: 0430e1c0 incb x0, #14
--.*: 0430e1c0 incb x0, #14
--.*: 0430e1e0 incb x0, #15
--.*: 0430e1e0 incb x0, #15
--.*: 0430e1e0 incb x0, #15
--.*: 0430e200 incb x0, #16
--.*: 0430e200 incb x0, #16
--.*: 0430e200 incb x0, #16
--.*: 0430e220 incb x0, #17
--.*: 0430e220 incb x0, #17
--.*: 0430e220 incb x0, #17
--.*: 0430e240 incb x0, #18
--.*: 0430e240 incb x0, #18
--.*: 0430e240 incb x0, #18
--.*: 0430e260 incb x0, #19
--.*: 0430e260 incb x0, #19
--.*: 0430e260 incb x0, #19
--.*: 0430e280 incb x0, #20
--.*: 0430e280 incb x0, #20
--.*: 0430e280 incb x0, #20
--.*: 0430e2a0 incb x0, #21
--.*: 0430e2a0 incb x0, #21
--.*: 0430e2a0 incb x0, #21
--.*: 0430e2c0 incb x0, #22
--.*: 0430e2c0 incb x0, #22
--.*: 0430e2c0 incb x0, #22
--.*: 0430e2e0 incb x0, #23
--.*: 0430e2e0 incb x0, #23
--.*: 0430e2e0 incb x0, #23
--.*: 0430e300 incb x0, #24
--.*: 0430e300 incb x0, #24
--.*: 0430e300 incb x0, #24
--.*: 0430e320 incb x0, #25
--.*: 0430e320 incb x0, #25
--.*: 0430e320 incb x0, #25
--.*: 0430e340 incb x0, #26
--.*: 0430e340 incb x0, #26
--.*: 0430e340 incb x0, #26
--.*: 0430e360 incb x0, #27
--.*: 0430e360 incb x0, #27
--.*: 0430e360 incb x0, #27
--.*: 0430e380 incb x0, #28
--.*: 0430e380 incb x0, #28
--.*: 0430e380 incb x0, #28
--.*: 0430e3a0 incb x0, mul4
--.*: 0430e3a0 incb x0, mul4
--.*: 0430e3a0 incb x0, mul4
--.*: 0430e3c0 incb x0, mul3
--.*: 0430e3c0 incb x0, mul3
--.*: 0430e3c0 incb x0, mul3
--.*: 0430e3e0 incb x0
--.*: 0430e3e0 incb x0
--.*: 0430e3e0 incb x0
--.*: 0430e3e0 incb x0
--.*: 0437e000 incb x0, pow2, mul #8
--.*: 0437e000 incb x0, pow2, mul #8
--.*: 0438e000 incb x0, pow2, mul #9
--.*: 0438e000 incb x0, pow2, mul #9
--.*: 0439e000 incb x0, pow2, mul #10
--.*: 0439e000 incb x0, pow2, mul #10
--.*: 043fe000 incb x0, pow2, mul #16
--.*: 043fe000 incb x0, pow2, mul #16
--.*: 04f0c000 incd z0\.d, pow2
--.*: 04f0c000 incd z0\.d, pow2
--.*: 04f0c000 incd z0\.d, pow2
--.*: 04f0c001 incd z1\.d, pow2
--.*: 04f0c001 incd z1\.d, pow2
--.*: 04f0c001 incd z1\.d, pow2
--.*: 04f0c01f incd z31\.d, pow2
--.*: 04f0c01f incd z31\.d, pow2
--.*: 04f0c01f incd z31\.d, pow2
--.*: 04f0c020 incd z0\.d, vl1
--.*: 04f0c020 incd z0\.d, vl1
--.*: 04f0c020 incd z0\.d, vl1
--.*: 04f0c040 incd z0\.d, vl2
--.*: 04f0c040 incd z0\.d, vl2
--.*: 04f0c040 incd z0\.d, vl2
--.*: 04f0c060 incd z0\.d, vl3
--.*: 04f0c060 incd z0\.d, vl3
--.*: 04f0c060 incd z0\.d, vl3
--.*: 04f0c080 incd z0\.d, vl4
--.*: 04f0c080 incd z0\.d, vl4
--.*: 04f0c080 incd z0\.d, vl4
--.*: 04f0c0a0 incd z0\.d, vl5
--.*: 04f0c0a0 incd z0\.d, vl5
--.*: 04f0c0a0 incd z0\.d, vl5
--.*: 04f0c0c0 incd z0\.d, vl6
--.*: 04f0c0c0 incd z0\.d, vl6
--.*: 04f0c0c0 incd z0\.d, vl6
--.*: 04f0c0e0 incd z0\.d, vl7
--.*: 04f0c0e0 incd z0\.d, vl7
--.*: 04f0c0e0 incd z0\.d, vl7
--.*: 04f0c100 incd z0\.d, vl8
--.*: 04f0c100 incd z0\.d, vl8
--.*: 04f0c100 incd z0\.d, vl8
--.*: 04f0c120 incd z0\.d, vl16
--.*: 04f0c120 incd z0\.d, vl16
--.*: 04f0c120 incd z0\.d, vl16
--.*: 04f0c140 incd z0\.d, vl32
--.*: 04f0c140 incd z0\.d, vl32
--.*: 04f0c140 incd z0\.d, vl32
--.*: 04f0c160 incd z0\.d, vl64
--.*: 04f0c160 incd z0\.d, vl64
--.*: 04f0c160 incd z0\.d, vl64
--.*: 04f0c180 incd z0\.d, vl128
--.*: 04f0c180 incd z0\.d, vl128
--.*: 04f0c180 incd z0\.d, vl128
--.*: 04f0c1a0 incd z0\.d, vl256
--.*: 04f0c1a0 incd z0\.d, vl256
--.*: 04f0c1a0 incd z0\.d, vl256
--.*: 04f0c1c0 incd z0\.d, #14
--.*: 04f0c1c0 incd z0\.d, #14
--.*: 04f0c1c0 incd z0\.d, #14
--.*: 04f0c1e0 incd z0\.d, #15
--.*: 04f0c1e0 incd z0\.d, #15
--.*: 04f0c1e0 incd z0\.d, #15
--.*: 04f0c200 incd z0\.d, #16
--.*: 04f0c200 incd z0\.d, #16
--.*: 04f0c200 incd z0\.d, #16
--.*: 04f0c220 incd z0\.d, #17
--.*: 04f0c220 incd z0\.d, #17
--.*: 04f0c220 incd z0\.d, #17
--.*: 04f0c240 incd z0\.d, #18
--.*: 04f0c240 incd z0\.d, #18
--.*: 04f0c240 incd z0\.d, #18
--.*: 04f0c260 incd z0\.d, #19
--.*: 04f0c260 incd z0\.d, #19
--.*: 04f0c260 incd z0\.d, #19
--.*: 04f0c280 incd z0\.d, #20
--.*: 04f0c280 incd z0\.d, #20
--.*: 04f0c280 incd z0\.d, #20
--.*: 04f0c2a0 incd z0\.d, #21
--.*: 04f0c2a0 incd z0\.d, #21
--.*: 04f0c2a0 incd z0\.d, #21
--.*: 04f0c2c0 incd z0\.d, #22
--.*: 04f0c2c0 incd z0\.d, #22
--.*: 04f0c2c0 incd z0\.d, #22
--.*: 04f0c2e0 incd z0\.d, #23
--.*: 04f0c2e0 incd z0\.d, #23
--.*: 04f0c2e0 incd z0\.d, #23
--.*: 04f0c300 incd z0\.d, #24
--.*: 04f0c300 incd z0\.d, #24
--.*: 04f0c300 incd z0\.d, #24
--.*: 04f0c320 incd z0\.d, #25
--.*: 04f0c320 incd z0\.d, #25
--.*: 04f0c320 incd z0\.d, #25
--.*: 04f0c340 incd z0\.d, #26
--.*: 04f0c340 incd z0\.d, #26
--.*: 04f0c340 incd z0\.d, #26
--.*: 04f0c360 incd z0\.d, #27
--.*: 04f0c360 incd z0\.d, #27
--.*: 04f0c360 incd z0\.d, #27
--.*: 04f0c380 incd z0\.d, #28
--.*: 04f0c380 incd z0\.d, #28
--.*: 04f0c380 incd z0\.d, #28
--.*: 04f0c3a0 incd z0\.d, mul4
--.*: 04f0c3a0 incd z0\.d, mul4
--.*: 04f0c3a0 incd z0\.d, mul4
--.*: 04f0c3c0 incd z0\.d, mul3
--.*: 04f0c3c0 incd z0\.d, mul3
--.*: 04f0c3c0 incd z0\.d, mul3
--.*: 04f0c3e0 incd z0\.d
--.*: 04f0c3e0 incd z0\.d
--.*: 04f0c3e0 incd z0\.d
--.*: 04f0c3e0 incd z0\.d
--.*: 04f7c000 incd z0\.d, pow2, mul #8
--.*: 04f7c000 incd z0\.d, pow2, mul #8
--.*: 04f8c000 incd z0\.d, pow2, mul #9
--.*: 04f8c000 incd z0\.d, pow2, mul #9
--.*: 04f9c000 incd z0\.d, pow2, mul #10
--.*: 04f9c000 incd z0\.d, pow2, mul #10
--.*: 04ffc000 incd z0\.d, pow2, mul #16
--.*: 04ffc000 incd z0\.d, pow2, mul #16
--.*: 04f0e000 incd x0, pow2
--.*: 04f0e000 incd x0, pow2
--.*: 04f0e000 incd x0, pow2
--.*: 04f0e001 incd x1, pow2
--.*: 04f0e001 incd x1, pow2
--.*: 04f0e001 incd x1, pow2
--.*: 04f0e01f incd xzr, pow2
--.*: 04f0e01f incd xzr, pow2
--.*: 04f0e01f incd xzr, pow2
--.*: 04f0e020 incd x0, vl1
--.*: 04f0e020 incd x0, vl1
--.*: 04f0e020 incd x0, vl1
--.*: 04f0e040 incd x0, vl2
--.*: 04f0e040 incd x0, vl2
--.*: 04f0e040 incd x0, vl2
--.*: 04f0e060 incd x0, vl3
--.*: 04f0e060 incd x0, vl3
--.*: 04f0e060 incd x0, vl3
--.*: 04f0e080 incd x0, vl4
--.*: 04f0e080 incd x0, vl4
--.*: 04f0e080 incd x0, vl4
--.*: 04f0e0a0 incd x0, vl5
--.*: 04f0e0a0 incd x0, vl5
--.*: 04f0e0a0 incd x0, vl5
--.*: 04f0e0c0 incd x0, vl6
--.*: 04f0e0c0 incd x0, vl6
--.*: 04f0e0c0 incd x0, vl6
--.*: 04f0e0e0 incd x0, vl7
--.*: 04f0e0e0 incd x0, vl7
--.*: 04f0e0e0 incd x0, vl7
--.*: 04f0e100 incd x0, vl8
--.*: 04f0e100 incd x0, vl8
--.*: 04f0e100 incd x0, vl8
--.*: 04f0e120 incd x0, vl16
--.*: 04f0e120 incd x0, vl16
--.*: 04f0e120 incd x0, vl16
--.*: 04f0e140 incd x0, vl32
--.*: 04f0e140 incd x0, vl32
--.*: 04f0e140 incd x0, vl32
--.*: 04f0e160 incd x0, vl64
--.*: 04f0e160 incd x0, vl64
--.*: 04f0e160 incd x0, vl64
--.*: 04f0e180 incd x0, vl128
--.*: 04f0e180 incd x0, vl128
--.*: 04f0e180 incd x0, vl128
--.*: 04f0e1a0 incd x0, vl256
--.*: 04f0e1a0 incd x0, vl256
--.*: 04f0e1a0 incd x0, vl256
--.*: 04f0e1c0 incd x0, #14
--.*: 04f0e1c0 incd x0, #14
--.*: 04f0e1c0 incd x0, #14
--.*: 04f0e1e0 incd x0, #15
--.*: 04f0e1e0 incd x0, #15
--.*: 04f0e1e0 incd x0, #15
--.*: 04f0e200 incd x0, #16
--.*: 04f0e200 incd x0, #16
--.*: 04f0e200 incd x0, #16
--.*: 04f0e220 incd x0, #17
--.*: 04f0e220 incd x0, #17
--.*: 04f0e220 incd x0, #17
--.*: 04f0e240 incd x0, #18
--.*: 04f0e240 incd x0, #18
--.*: 04f0e240 incd x0, #18
--.*: 04f0e260 incd x0, #19
--.*: 04f0e260 incd x0, #19
--.*: 04f0e260 incd x0, #19
--.*: 04f0e280 incd x0, #20
--.*: 04f0e280 incd x0, #20
--.*: 04f0e280 incd x0, #20
--.*: 04f0e2a0 incd x0, #21
--.*: 04f0e2a0 incd x0, #21
--.*: 04f0e2a0 incd x0, #21
--.*: 04f0e2c0 incd x0, #22
--.*: 04f0e2c0 incd x0, #22
--.*: 04f0e2c0 incd x0, #22
--.*: 04f0e2e0 incd x0, #23
--.*: 04f0e2e0 incd x0, #23
--.*: 04f0e2e0 incd x0, #23
--.*: 04f0e300 incd x0, #24
--.*: 04f0e300 incd x0, #24
--.*: 04f0e300 incd x0, #24
--.*: 04f0e320 incd x0, #25
--.*: 04f0e320 incd x0, #25
--.*: 04f0e320 incd x0, #25
--.*: 04f0e340 incd x0, #26
--.*: 04f0e340 incd x0, #26
--.*: 04f0e340 incd x0, #26
--.*: 04f0e360 incd x0, #27
--.*: 04f0e360 incd x0, #27
--.*: 04f0e360 incd x0, #27
--.*: 04f0e380 incd x0, #28
--.*: 04f0e380 incd x0, #28
--.*: 04f0e380 incd x0, #28
--.*: 04f0e3a0 incd x0, mul4
--.*: 04f0e3a0 incd x0, mul4
--.*: 04f0e3a0 incd x0, mul4
--.*: 04f0e3c0 incd x0, mul3
--.*: 04f0e3c0 incd x0, mul3
--.*: 04f0e3c0 incd x0, mul3
--.*: 04f0e3e0 incd x0
--.*: 04f0e3e0 incd x0
--.*: 04f0e3e0 incd x0
--.*: 04f0e3e0 incd x0
--.*: 04f7e000 incd x0, pow2, mul #8
--.*: 04f7e000 incd x0, pow2, mul #8
--.*: 04f8e000 incd x0, pow2, mul #9
--.*: 04f8e000 incd x0, pow2, mul #9
--.*: 04f9e000 incd x0, pow2, mul #10
--.*: 04f9e000 incd x0, pow2, mul #10
--.*: 04ffe000 incd x0, pow2, mul #16
--.*: 04ffe000 incd x0, pow2, mul #16
--.*: 0470c000 inch z0\.h, pow2
--.*: 0470c000 inch z0\.h, pow2
--.*: 0470c000 inch z0\.h, pow2
--.*: 0470c001 inch z1\.h, pow2
--.*: 0470c001 inch z1\.h, pow2
--.*: 0470c001 inch z1\.h, pow2
--.*: 0470c01f inch z31\.h, pow2
--.*: 0470c01f inch z31\.h, pow2
--.*: 0470c01f inch z31\.h, pow2
--.*: 0470c020 inch z0\.h, vl1
--.*: 0470c020 inch z0\.h, vl1
--.*: 0470c020 inch z0\.h, vl1
--.*: 0470c040 inch z0\.h, vl2
--.*: 0470c040 inch z0\.h, vl2
--.*: 0470c040 inch z0\.h, vl2
--.*: 0470c060 inch z0\.h, vl3
--.*: 0470c060 inch z0\.h, vl3
--.*: 0470c060 inch z0\.h, vl3
--.*: 0470c080 inch z0\.h, vl4
--.*: 0470c080 inch z0\.h, vl4
--.*: 0470c080 inch z0\.h, vl4
--.*: 0470c0a0 inch z0\.h, vl5
--.*: 0470c0a0 inch z0\.h, vl5
--.*: 0470c0a0 inch z0\.h, vl5
--.*: 0470c0c0 inch z0\.h, vl6
--.*: 0470c0c0 inch z0\.h, vl6
--.*: 0470c0c0 inch z0\.h, vl6
--.*: 0470c0e0 inch z0\.h, vl7
--.*: 0470c0e0 inch z0\.h, vl7
--.*: 0470c0e0 inch z0\.h, vl7
--.*: 0470c100 inch z0\.h, vl8
--.*: 0470c100 inch z0\.h, vl8
--.*: 0470c100 inch z0\.h, vl8
--.*: 0470c120 inch z0\.h, vl16
--.*: 0470c120 inch z0\.h, vl16
--.*: 0470c120 inch z0\.h, vl16
--.*: 0470c140 inch z0\.h, vl32
--.*: 0470c140 inch z0\.h, vl32
--.*: 0470c140 inch z0\.h, vl32
--.*: 0470c160 inch z0\.h, vl64
--.*: 0470c160 inch z0\.h, vl64
--.*: 0470c160 inch z0\.h, vl64
--.*: 0470c180 inch z0\.h, vl128
--.*: 0470c180 inch z0\.h, vl128
--.*: 0470c180 inch z0\.h, vl128
--.*: 0470c1a0 inch z0\.h, vl256
--.*: 0470c1a0 inch z0\.h, vl256
--.*: 0470c1a0 inch z0\.h, vl256
--.*: 0470c1c0 inch z0\.h, #14
--.*: 0470c1c0 inch z0\.h, #14
--.*: 0470c1c0 inch z0\.h, #14
--.*: 0470c1e0 inch z0\.h, #15
--.*: 0470c1e0 inch z0\.h, #15
--.*: 0470c1e0 inch z0\.h, #15
--.*: 0470c200 inch z0\.h, #16
--.*: 0470c200 inch z0\.h, #16
--.*: 0470c200 inch z0\.h, #16
--.*: 0470c220 inch z0\.h, #17
--.*: 0470c220 inch z0\.h, #17
--.*: 0470c220 inch z0\.h, #17
--.*: 0470c240 inch z0\.h, #18
--.*: 0470c240 inch z0\.h, #18
--.*: 0470c240 inch z0\.h, #18
--.*: 0470c260 inch z0\.h, #19
--.*: 0470c260 inch z0\.h, #19
--.*: 0470c260 inch z0\.h, #19
--.*: 0470c280 inch z0\.h, #20
--.*: 0470c280 inch z0\.h, #20
--.*: 0470c280 inch z0\.h, #20
--.*: 0470c2a0 inch z0\.h, #21
--.*: 0470c2a0 inch z0\.h, #21
--.*: 0470c2a0 inch z0\.h, #21
--.*: 0470c2c0 inch z0\.h, #22
--.*: 0470c2c0 inch z0\.h, #22
--.*: 0470c2c0 inch z0\.h, #22
--.*: 0470c2e0 inch z0\.h, #23
--.*: 0470c2e0 inch z0\.h, #23
--.*: 0470c2e0 inch z0\.h, #23
--.*: 0470c300 inch z0\.h, #24
--.*: 0470c300 inch z0\.h, #24
--.*: 0470c300 inch z0\.h, #24
--.*: 0470c320 inch z0\.h, #25
--.*: 0470c320 inch z0\.h, #25
--.*: 0470c320 inch z0\.h, #25
--.*: 0470c340 inch z0\.h, #26
--.*: 0470c340 inch z0\.h, #26
--.*: 0470c340 inch z0\.h, #26
--.*: 0470c360 inch z0\.h, #27
--.*: 0470c360 inch z0\.h, #27
--.*: 0470c360 inch z0\.h, #27
--.*: 0470c380 inch z0\.h, #28
--.*: 0470c380 inch z0\.h, #28
--.*: 0470c380 inch z0\.h, #28
--.*: 0470c3a0 inch z0\.h, mul4
--.*: 0470c3a0 inch z0\.h, mul4
--.*: 0470c3a0 inch z0\.h, mul4
--.*: 0470c3c0 inch z0\.h, mul3
--.*: 0470c3c0 inch z0\.h, mul3
--.*: 0470c3c0 inch z0\.h, mul3
--.*: 0470c3e0 inch z0\.h
--.*: 0470c3e0 inch z0\.h
--.*: 0470c3e0 inch z0\.h
--.*: 0470c3e0 inch z0\.h
--.*: 0477c000 inch z0\.h, pow2, mul #8
--.*: 0477c000 inch z0\.h, pow2, mul #8
--.*: 0478c000 inch z0\.h, pow2, mul #9
--.*: 0478c000 inch z0\.h, pow2, mul #9
--.*: 0479c000 inch z0\.h, pow2, mul #10
--.*: 0479c000 inch z0\.h, pow2, mul #10
--.*: 047fc000 inch z0\.h, pow2, mul #16
--.*: 047fc000 inch z0\.h, pow2, mul #16
--.*: 0470e000 inch x0, pow2
--.*: 0470e000 inch x0, pow2
--.*: 0470e000 inch x0, pow2
--.*: 0470e001 inch x1, pow2
--.*: 0470e001 inch x1, pow2
--.*: 0470e001 inch x1, pow2
--.*: 0470e01f inch xzr, pow2
--.*: 0470e01f inch xzr, pow2
--.*: 0470e01f inch xzr, pow2
--.*: 0470e020 inch x0, vl1
--.*: 0470e020 inch x0, vl1
--.*: 0470e020 inch x0, vl1
--.*: 0470e040 inch x0, vl2
--.*: 0470e040 inch x0, vl2
--.*: 0470e040 inch x0, vl2
--.*: 0470e060 inch x0, vl3
--.*: 0470e060 inch x0, vl3
--.*: 0470e060 inch x0, vl3
--.*: 0470e080 inch x0, vl4
--.*: 0470e080 inch x0, vl4
--.*: 0470e080 inch x0, vl4
--.*: 0470e0a0 inch x0, vl5
--.*: 0470e0a0 inch x0, vl5
--.*: 0470e0a0 inch x0, vl5
--.*: 0470e0c0 inch x0, vl6
--.*: 0470e0c0 inch x0, vl6
--.*: 0470e0c0 inch x0, vl6
--.*: 0470e0e0 inch x0, vl7
--.*: 0470e0e0 inch x0, vl7
--.*: 0470e0e0 inch x0, vl7
--.*: 0470e100 inch x0, vl8
--.*: 0470e100 inch x0, vl8
--.*: 0470e100 inch x0, vl8
--.*: 0470e120 inch x0, vl16
--.*: 0470e120 inch x0, vl16
--.*: 0470e120 inch x0, vl16
--.*: 0470e140 inch x0, vl32
--.*: 0470e140 inch x0, vl32
--.*: 0470e140 inch x0, vl32
--.*: 0470e160 inch x0, vl64
--.*: 0470e160 inch x0, vl64
--.*: 0470e160 inch x0, vl64
--.*: 0470e180 inch x0, vl128
--.*: 0470e180 inch x0, vl128
--.*: 0470e180 inch x0, vl128
--.*: 0470e1a0 inch x0, vl256
--.*: 0470e1a0 inch x0, vl256
--.*: 0470e1a0 inch x0, vl256
--.*: 0470e1c0 inch x0, #14
--.*: 0470e1c0 inch x0, #14
--.*: 0470e1c0 inch x0, #14
--.*: 0470e1e0 inch x0, #15
--.*: 0470e1e0 inch x0, #15
--.*: 0470e1e0 inch x0, #15
--.*: 0470e200 inch x0, #16
--.*: 0470e200 inch x0, #16
--.*: 0470e200 inch x0, #16
--.*: 0470e220 inch x0, #17
--.*: 0470e220 inch x0, #17
--.*: 0470e220 inch x0, #17
--.*: 0470e240 inch x0, #18
--.*: 0470e240 inch x0, #18
--.*: 0470e240 inch x0, #18
--.*: 0470e260 inch x0, #19
--.*: 0470e260 inch x0, #19
--.*: 0470e260 inch x0, #19
--.*: 0470e280 inch x0, #20
--.*: 0470e280 inch x0, #20
--.*: 0470e280 inch x0, #20
--.*: 0470e2a0 inch x0, #21
--.*: 0470e2a0 inch x0, #21
--.*: 0470e2a0 inch x0, #21
--.*: 0470e2c0 inch x0, #22
--.*: 0470e2c0 inch x0, #22
--.*: 0470e2c0 inch x0, #22
--.*: 0470e2e0 inch x0, #23
--.*: 0470e2e0 inch x0, #23
--.*: 0470e2e0 inch x0, #23
--.*: 0470e300 inch x0, #24
--.*: 0470e300 inch x0, #24
--.*: 0470e300 inch x0, #24
--.*: 0470e320 inch x0, #25
--.*: 0470e320 inch x0, #25
--.*: 0470e320 inch x0, #25
--.*: 0470e340 inch x0, #26
--.*: 0470e340 inch x0, #26
--.*: 0470e340 inch x0, #26
--.*: 0470e360 inch x0, #27
--.*: 0470e360 inch x0, #27
--.*: 0470e360 inch x0, #27
--.*: 0470e380 inch x0, #28
--.*: 0470e380 inch x0, #28
--.*: 0470e380 inch x0, #28
--.*: 0470e3a0 inch x0, mul4
--.*: 0470e3a0 inch x0, mul4
--.*: 0470e3a0 inch x0, mul4
--.*: 0470e3c0 inch x0, mul3
--.*: 0470e3c0 inch x0, mul3
--.*: 0470e3c0 inch x0, mul3
--.*: 0470e3e0 inch x0
--.*: 0470e3e0 inch x0
--.*: 0470e3e0 inch x0
--.*: 0470e3e0 inch x0
--.*: 0477e000 inch x0, pow2, mul #8
--.*: 0477e000 inch x0, pow2, mul #8
--.*: 0478e000 inch x0, pow2, mul #9
--.*: 0478e000 inch x0, pow2, mul #9
--.*: 0479e000 inch x0, pow2, mul #10
--.*: 0479e000 inch x0, pow2, mul #10
--.*: 047fe000 inch x0, pow2, mul #16
--.*: 047fe000 inch x0, pow2, mul #16
--.*: 256c8000 incp z0\.h, p0
--.*: 256c8000 incp z0\.h, p0
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--.*: 256c8001 incp z1\.h, p0
--.*: 256c801f incp z31\.h, p0
--.*: 256c801f incp z31\.h, p0
--.*: 256c8040 incp z0\.h, p2
--.*: 256c8040 incp z0\.h, p2
--.*: 256c81e0 incp z0\.h, p15
--.*: 256c81e0 incp z0\.h, p15
--.*: 25ac8000 incp z0\.s, p0
--.*: 25ac8000 incp z0\.s, p0
--.*: 25ac8001 incp z1\.s, p0
--.*: 25ac8001 incp z1\.s, p0
--.*: 25ac801f incp z31\.s, p0
--.*: 25ac801f incp z31\.s, p0
--.*: 25ac8040 incp z0\.s, p2
--.*: 25ac8040 incp z0\.s, p2
--.*: 25ac81e0 incp z0\.s, p15
--.*: 25ac81e0 incp z0\.s, p15
--.*: 25ec8000 incp z0\.d, p0
--.*: 25ec8000 incp z0\.d, p0
--.*: 25ec8001 incp z1\.d, p0
--.*: 25ec8001 incp z1\.d, p0
--.*: 25ec801f incp z31\.d, p0
--.*: 25ec801f incp z31\.d, p0
--.*: 25ec8040 incp z0\.d, p2
--.*: 25ec8040 incp z0\.d, p2
--.*: 25ec81e0 incp z0\.d, p15
--.*: 25ec81e0 incp z0\.d, p15
--.*: 252c8800 incp x0, p0\.b
--.*: 252c8800 incp x0, p0\.b
--.*: 252c8801 incp x1, p0\.b
--.*: 252c8801 incp x1, p0\.b
--.*: 252c881f incp xzr, p0\.b
--.*: 252c881f incp xzr, p0\.b
--.*: 252c8840 incp x0, p2\.b
--.*: 252c8840 incp x0, p2\.b
--.*: 252c89e0 incp x0, p15\.b
--.*: 252c89e0 incp x0, p15\.b
--.*: 256c8800 incp x0, p0\.h
--.*: 256c8800 incp x0, p0\.h
--.*: 256c8801 incp x1, p0\.h
--.*: 256c8801 incp x1, p0\.h
--.*: 256c881f incp xzr, p0\.h
--.*: 256c881f incp xzr, p0\.h
--.*: 256c8840 incp x0, p2\.h
--.*: 256c8840 incp x0, p2\.h
--.*: 256c89e0 incp x0, p15\.h
--.*: 256c89e0 incp x0, p15\.h
--.*: 25ac8800 incp x0, p0\.s
--.*: 25ac8800 incp x0, p0\.s
--.*: 25ac8801 incp x1, p0\.s
--.*: 25ac8801 incp x1, p0\.s
--.*: 25ac881f incp xzr, p0\.s
--.*: 25ac881f incp xzr, p0\.s
--.*: 25ac8840 incp x0, p2\.s
--.*: 25ac8840 incp x0, p2\.s
--.*: 25ac89e0 incp x0, p15\.s
--.*: 25ac89e0 incp x0, p15\.s
--.*: 25ec8800 incp x0, p0\.d
--.*: 25ec8800 incp x0, p0\.d
--.*: 25ec8801 incp x1, p0\.d
--.*: 25ec8801 incp x1, p0\.d
--.*: 25ec881f incp xzr, p0\.d
--.*: 25ec881f incp xzr, p0\.d
--.*: 25ec8840 incp x0, p2\.d
--.*: 25ec8840 incp x0, p2\.d
--.*: 25ec89e0 incp x0, p15\.d
--.*: 25ec89e0 incp x0, p15\.d
--.*: 04b0c000 incw z0\.s, pow2
--.*: 04b0c000 incw z0\.s, pow2
--.*: 04b0c000 incw z0\.s, pow2
--.*: 04b0c001 incw z1\.s, pow2
--.*: 04b0c001 incw z1\.s, pow2
--.*: 04b0c001 incw z1\.s, pow2
--.*: 04b0c01f incw z31\.s, pow2
--.*: 04b0c01f incw z31\.s, pow2
--.*: 04b0c01f incw z31\.s, pow2
--.*: 04b0c020 incw z0\.s, vl1
--.*: 04b0c020 incw z0\.s, vl1
--.*: 04b0c020 incw z0\.s, vl1
--.*: 04b0c040 incw z0\.s, vl2
--.*: 04b0c040 incw z0\.s, vl2
--.*: 04b0c040 incw z0\.s, vl2
--.*: 04b0c060 incw z0\.s, vl3
--.*: 04b0c060 incw z0\.s, vl3
--.*: 04b0c060 incw z0\.s, vl3
--.*: 04b0c080 incw z0\.s, vl4
--.*: 04b0c080 incw z0\.s, vl4
--.*: 04b0c080 incw z0\.s, vl4
--.*: 04b0c0a0 incw z0\.s, vl5
--.*: 04b0c0a0 incw z0\.s, vl5
--.*: 04b0c0a0 incw z0\.s, vl5
--.*: 04b0c0c0 incw z0\.s, vl6
--.*: 04b0c0c0 incw z0\.s, vl6
--.*: 04b0c0c0 incw z0\.s, vl6
--.*: 04b0c0e0 incw z0\.s, vl7
--.*: 04b0c0e0 incw z0\.s, vl7
--.*: 04b0c0e0 incw z0\.s, vl7
--.*: 04b0c100 incw z0\.s, vl8
--.*: 04b0c100 incw z0\.s, vl8
--.*: 04b0c100 incw z0\.s, vl8
--.*: 04b0c120 incw z0\.s, vl16
--.*: 04b0c120 incw z0\.s, vl16
--.*: 04b0c120 incw z0\.s, vl16
--.*: 04b0c140 incw z0\.s, vl32
--.*: 04b0c140 incw z0\.s, vl32
--.*: 04b0c140 incw z0\.s, vl32
--.*: 04b0c160 incw z0\.s, vl64
--.*: 04b0c160 incw z0\.s, vl64
--.*: 04b0c160 incw z0\.s, vl64
--.*: 04b0c180 incw z0\.s, vl128
--.*: 04b0c180 incw z0\.s, vl128
--.*: 04b0c180 incw z0\.s, vl128
--.*: 04b0c1a0 incw z0\.s, vl256
--.*: 04b0c1a0 incw z0\.s, vl256
--.*: 04b0c1a0 incw z0\.s, vl256
--.*: 04b0c1c0 incw z0\.s, #14
--.*: 04b0c1c0 incw z0\.s, #14
--.*: 04b0c1c0 incw z0\.s, #14
--.*: 04b0c1e0 incw z0\.s, #15
--.*: 04b0c1e0 incw z0\.s, #15
--.*: 04b0c1e0 incw z0\.s, #15
--.*: 04b0c200 incw z0\.s, #16
--.*: 04b0c200 incw z0\.s, #16
--.*: 04b0c200 incw z0\.s, #16
--.*: 04b0c220 incw z0\.s, #17
--.*: 04b0c220 incw z0\.s, #17
--.*: 04b0c220 incw z0\.s, #17
--.*: 04b0c240 incw z0\.s, #18
--.*: 04b0c240 incw z0\.s, #18
--.*: 04b0c240 incw z0\.s, #18
--.*: 04b0c260 incw z0\.s, #19
--.*: 04b0c260 incw z0\.s, #19
--.*: 04b0c260 incw z0\.s, #19
--.*: 04b0c280 incw z0\.s, #20
--.*: 04b0c280 incw z0\.s, #20
--.*: 04b0c280 incw z0\.s, #20
--.*: 04b0c2a0 incw z0\.s, #21
--.*: 04b0c2a0 incw z0\.s, #21
--.*: 04b0c2a0 incw z0\.s, #21
--.*: 04b0c2c0 incw z0\.s, #22
--.*: 04b0c2c0 incw z0\.s, #22
--.*: 04b0c2c0 incw z0\.s, #22
--.*: 04b0c2e0 incw z0\.s, #23
--.*: 04b0c2e0 incw z0\.s, #23
--.*: 04b0c2e0 incw z0\.s, #23
--.*: 04b0c300 incw z0\.s, #24
--.*: 04b0c300 incw z0\.s, #24
--.*: 04b0c300 incw z0\.s, #24
--.*: 04b0c320 incw z0\.s, #25
--.*: 04b0c320 incw z0\.s, #25
--.*: 04b0c320 incw z0\.s, #25
--.*: 04b0c340 incw z0\.s, #26
--.*: 04b0c340 incw z0\.s, #26
--.*: 04b0c340 incw z0\.s, #26
--.*: 04b0c360 incw z0\.s, #27
--.*: 04b0c360 incw z0\.s, #27
--.*: 04b0c360 incw z0\.s, #27
--.*: 04b0c380 incw z0\.s, #28
--.*: 04b0c380 incw z0\.s, #28
--.*: 04b0c380 incw z0\.s, #28
--.*: 04b0c3a0 incw z0\.s, mul4
--.*: 04b0c3a0 incw z0\.s, mul4
--.*: 04b0c3a0 incw z0\.s, mul4
--.*: 04b0c3c0 incw z0\.s, mul3
--.*: 04b0c3c0 incw z0\.s, mul3
--.*: 04b0c3c0 incw z0\.s, mul3
--.*: 04b0c3e0 incw z0\.s
--.*: 04b0c3e0 incw z0\.s
--.*: 04b0c3e0 incw z0\.s
--.*: 04b0c3e0 incw z0\.s
--.*: 04b7c000 incw z0\.s, pow2, mul #8
--.*: 04b7c000 incw z0\.s, pow2, mul #8
--.*: 04b8c000 incw z0\.s, pow2, mul #9
--.*: 04b8c000 incw z0\.s, pow2, mul #9
--.*: 04b9c000 incw z0\.s, pow2, mul #10
--.*: 04b9c000 incw z0\.s, pow2, mul #10
--.*: 04bfc000 incw z0\.s, pow2, mul #16
--.*: 04bfc000 incw z0\.s, pow2, mul #16
--.*: 04b0e000 incw x0, pow2
--.*: 04b0e000 incw x0, pow2
--.*: 04b0e000 incw x0, pow2
--.*: 04b0e001 incw x1, pow2
--.*: 04b0e001 incw x1, pow2
--.*: 04b0e001 incw x1, pow2
--.*: 04b0e01f incw xzr, pow2
--.*: 04b0e01f incw xzr, pow2
--.*: 04b0e01f incw xzr, pow2
--.*: 04b0e020 incw x0, vl1
--.*: 04b0e020 incw x0, vl1
--.*: 04b0e020 incw x0, vl1
--.*: 04b0e040 incw x0, vl2
--.*: 04b0e040 incw x0, vl2
--.*: 04b0e040 incw x0, vl2
--.*: 04b0e060 incw x0, vl3
--.*: 04b0e060 incw x0, vl3
--.*: 04b0e060 incw x0, vl3
--.*: 04b0e080 incw x0, vl4
--.*: 04b0e080 incw x0, vl4
--.*: 04b0e080 incw x0, vl4
--.*: 04b0e0a0 incw x0, vl5
--.*: 04b0e0a0 incw x0, vl5
--.*: 04b0e0a0 incw x0, vl5
--.*: 04b0e0c0 incw x0, vl6
--.*: 04b0e0c0 incw x0, vl6
--.*: 04b0e0c0 incw x0, vl6
--.*: 04b0e0e0 incw x0, vl7
--.*: 04b0e0e0 incw x0, vl7
--.*: 04b0e0e0 incw x0, vl7
--.*: 04b0e100 incw x0, vl8
--.*: 04b0e100 incw x0, vl8
--.*: 04b0e100 incw x0, vl8
--.*: 04b0e120 incw x0, vl16
--.*: 04b0e120 incw x0, vl16
--.*: 04b0e120 incw x0, vl16
--.*: 04b0e140 incw x0, vl32
--.*: 04b0e140 incw x0, vl32
--.*: 04b0e140 incw x0, vl32
--.*: 04b0e160 incw x0, vl64
--.*: 04b0e160 incw x0, vl64
--.*: 04b0e160 incw x0, vl64
--.*: 04b0e180 incw x0, vl128
--.*: 04b0e180 incw x0, vl128
--.*: 04b0e180 incw x0, vl128
--.*: 04b0e1a0 incw x0, vl256
--.*: 04b0e1a0 incw x0, vl256
--.*: 04b0e1a0 incw x0, vl256
--.*: 04b0e1c0 incw x0, #14
--.*: 04b0e1c0 incw x0, #14
--.*: 04b0e1c0 incw x0, #14
--.*: 04b0e1e0 incw x0, #15
--.*: 04b0e1e0 incw x0, #15
--.*: 04b0e1e0 incw x0, #15
--.*: 04b0e200 incw x0, #16
--.*: 04b0e200 incw x0, #16
--.*: 04b0e200 incw x0, #16
--.*: 04b0e220 incw x0, #17
--.*: 04b0e220 incw x0, #17
--.*: 04b0e220 incw x0, #17
--.*: 04b0e240 incw x0, #18
--.*: 04b0e240 incw x0, #18
--.*: 04b0e240 incw x0, #18
--.*: 04b0e260 incw x0, #19
--.*: 04b0e260 incw x0, #19
--.*: 04b0e260 incw x0, #19
--.*: 04b0e280 incw x0, #20
--.*: 04b0e280 incw x0, #20
--.*: 04b0e280 incw x0, #20
--.*: 04b0e2a0 incw x0, #21
--.*: 04b0e2a0 incw x0, #21
--.*: 04b0e2a0 incw x0, #21
--.*: 04b0e2c0 incw x0, #22
--.*: 04b0e2c0 incw x0, #22
--.*: 04b0e2c0 incw x0, #22
--.*: 04b0e2e0 incw x0, #23
--.*: 04b0e2e0 incw x0, #23
--.*: 04b0e2e0 incw x0, #23
--.*: 04b0e300 incw x0, #24
--.*: 04b0e300 incw x0, #24
--.*: 04b0e300 incw x0, #24
--.*: 04b0e320 incw x0, #25
--.*: 04b0e320 incw x0, #25
--.*: 04b0e320 incw x0, #25
--.*: 04b0e340 incw x0, #26
--.*: 04b0e340 incw x0, #26
--.*: 04b0e340 incw x0, #26
--.*: 04b0e360 incw x0, #27
--.*: 04b0e360 incw x0, #27
--.*: 04b0e360 incw x0, #27
--.*: 04b0e380 incw x0, #28
--.*: 04b0e380 incw x0, #28
--.*: 04b0e380 incw x0, #28
--.*: 04b0e3a0 incw x0, mul4
--.*: 04b0e3a0 incw x0, mul4
--.*: 04b0e3a0 incw x0, mul4
--.*: 04b0e3c0 incw x0, mul3
--.*: 04b0e3c0 incw x0, mul3
--.*: 04b0e3c0 incw x0, mul3
--.*: 04b0e3e0 incw x0
--.*: 04b0e3e0 incw x0
--.*: 04b0e3e0 incw x0
--.*: 04b0e3e0 incw x0
--.*: 04b7e000 incw x0, pow2, mul #8
--.*: 04b7e000 incw x0, pow2, mul #8
--.*: 04b8e000 incw x0, pow2, mul #9
--.*: 04b8e000 incw x0, pow2, mul #9
--.*: 04b9e000 incw x0, pow2, mul #10
--.*: 04b9e000 incw x0, pow2, mul #10
--.*: 04bfe000 incw x0, pow2, mul #16
--.*: 04bfe000 incw x0, pow2, mul #16
--.*: 04204c00 index z0\.b, w0, w0
--.*: 04204c00 index z0\.b, w0, w0
--.*: 04204c01 index z1\.b, w0, w0
--.*: 04204c01 index z1\.b, w0, w0
--.*: 04204c1f index z31\.b, w0, w0
--.*: 04204c1f index z31\.b, w0, w0
--.*: 04204c40 index z0\.b, w2, w0
--.*: 04204c40 index z0\.b, w2, w0
--.*: 04204fe0 index z0\.b, wzr, w0
--.*: 04204fe0 index z0\.b, wzr, w0
--.*: 04234c00 index z0\.b, w0, w3
--.*: 04234c00 index z0\.b, w0, w3
--.*: 043f4c00 index z0\.b, w0, wzr
--.*: 043f4c00 index z0\.b, w0, wzr
--.*: 04604c00 index z0\.h, w0, w0
--.*: 04604c00 index z0\.h, w0, w0
--.*: 04604c01 index z1\.h, w0, w0
--.*: 04604c01 index z1\.h, w0, w0
--.*: 04604c1f index z31\.h, w0, w0
--.*: 04604c1f index z31\.h, w0, w0
--.*: 04604c40 index z0\.h, w2, w0
--.*: 04604c40 index z0\.h, w2, w0
--.*: 04604fe0 index z0\.h, wzr, w0
--.*: 04604fe0 index z0\.h, wzr, w0
--.*: 04634c00 index z0\.h, w0, w3
--.*: 04634c00 index z0\.h, w0, w3
--.*: 047f4c00 index z0\.h, w0, wzr
--.*: 047f4c00 index z0\.h, w0, wzr
--.*: 04a04c00 index z0\.s, w0, w0
--.*: 04a04c00 index z0\.s, w0, w0
--.*: 04a04c01 index z1\.s, w0, w0
--.*: 04a04c01 index z1\.s, w0, w0
--.*: 04a04c1f index z31\.s, w0, w0
--.*: 04a04c1f index z31\.s, w0, w0
--.*: 04a04c40 index z0\.s, w2, w0
--.*: 04a04c40 index z0\.s, w2, w0
--.*: 04a04fe0 index z0\.s, wzr, w0
--.*: 04a04fe0 index z0\.s, wzr, w0
--.*: 04a34c00 index z0\.s, w0, w3
--.*: 04a34c00 index z0\.s, w0, w3
--.*: 04bf4c00 index z0\.s, w0, wzr
--.*: 04bf4c00 index z0\.s, w0, wzr
--.*: 04e04c00 index z0\.d, x0, x0
--.*: 04e04c00 index z0\.d, x0, x0
--.*: 04e04c01 index z1\.d, x0, x0
--.*: 04e04c01 index z1\.d, x0, x0
--.*: 04e04c1f index z31\.d, x0, x0
--.*: 04e04c1f index z31\.d, x0, x0
--.*: 04e04c40 index z0\.d, x2, x0
--.*: 04e04c40 index z0\.d, x2, x0
--.*: 04e04fe0 index z0\.d, xzr, x0
--.*: 04e04fe0 index z0\.d, xzr, x0
--.*: 04e34c00 index z0\.d, x0, x3
--.*: 04e34c00 index z0\.d, x0, x3
--.*: 04ff4c00 index z0\.d, x0, xzr
--.*: 04ff4c00 index z0\.d, x0, xzr
--.*: 04204000 index z0\.b, #0, #0
--.*: 04204000 index z0\.b, #0, #0
--.*: 04204001 index z1\.b, #0, #0
--.*: 04204001 index z1\.b, #0, #0
--.*: 0420401f index z31\.b, #0, #0
--.*: 0420401f index z31\.b, #0, #0
--.*: 042041e0 index z0\.b, #15, #0
--.*: 042041e0 index z0\.b, #15, #0
--.*: 04204200 index z0\.b, #-16, #0
--.*: 04204200 index z0\.b, #-16, #0
--.*: 04204220 index z0\.b, #-15, #0
--.*: 04204220 index z0\.b, #-15, #0
--.*: 042043e0 index z0\.b, #-1, #0
--.*: 042043e0 index z0\.b, #-1, #0
--.*: 042f4000 index z0\.b, #0, #15
--.*: 042f4000 index z0\.b, #0, #15
--.*: 04304000 index z0\.b, #0, #-16
--.*: 04304000 index z0\.b, #0, #-16
--.*: 04314000 index z0\.b, #0, #-15
--.*: 04314000 index z0\.b, #0, #-15
--.*: 043f4000 index z0\.b, #0, #-1
--.*: 043f4000 index z0\.b, #0, #-1
--.*: 04604000 index z0\.h, #0, #0
--.*: 04604000 index z0\.h, #0, #0
--.*: 04604001 index z1\.h, #0, #0
--.*: 04604001 index z1\.h, #0, #0
--.*: 0460401f index z31\.h, #0, #0
--.*: 0460401f index z31\.h, #0, #0
--.*: 046041e0 index z0\.h, #15, #0
--.*: 046041e0 index z0\.h, #15, #0
--.*: 04604200 index z0\.h, #-16, #0
--.*: 04604200 index z0\.h, #-16, #0
--.*: 04604220 index z0\.h, #-15, #0
--.*: 04604220 index z0\.h, #-15, #0
--.*: 046043e0 index z0\.h, #-1, #0
--.*: 046043e0 index z0\.h, #-1, #0
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--.*: 0521a3e0 lastb w0, p0, z31\.b
--.*: 0521a3e0 lastb w0, p0, z31\.b
--.*: 0561a000 lastb w0, p0, z0\.h
--.*: 0561a000 lastb w0, p0, z0\.h
--.*: 0561a001 lastb w1, p0, z0\.h
--.*: 0561a001 lastb w1, p0, z0\.h
--.*: 0561a01f lastb wzr, p0, z0\.h
--.*: 0561a01f lastb wzr, p0, z0\.h
--.*: 0561a800 lastb w0, p2, z0\.h
--.*: 0561a800 lastb w0, p2, z0\.h
--.*: 0561bc00 lastb w0, p7, z0\.h
--.*: 0561bc00 lastb w0, p7, z0\.h
--.*: 0561a060 lastb w0, p0, z3\.h
--.*: 0561a060 lastb w0, p0, z3\.h
--.*: 0561a3e0 lastb w0, p0, z31\.h
--.*: 0561a3e0 lastb w0, p0, z31\.h
--.*: 05a1a000 lastb w0, p0, z0\.s
--.*: 05a1a000 lastb w0, p0, z0\.s
--.*: 05a1a001 lastb w1, p0, z0\.s
--.*: 05a1a001 lastb w1, p0, z0\.s
--.*: 05a1a01f lastb wzr, p0, z0\.s
--.*: 05a1a01f lastb wzr, p0, z0\.s
--.*: 05a1a800 lastb w0, p2, z0\.s
--.*: 05a1a800 lastb w0, p2, z0\.s
--.*: 05a1bc00 lastb w0, p7, z0\.s
--.*: 05a1bc00 lastb w0, p7, z0\.s
--.*: 05a1a060 lastb w0, p0, z3\.s
--.*: 05a1a060 lastb w0, p0, z3\.s
--.*: 05a1a3e0 lastb w0, p0, z31\.s
--.*: 05a1a3e0 lastb w0, p0, z31\.s
--.*: 05e1a000 lastb x0, p0, z0\.d
--.*: 05e1a000 lastb x0, p0, z0\.d
--.*: 05e1a001 lastb x1, p0, z0\.d
--.*: 05e1a001 lastb x1, p0, z0\.d
--.*: 05e1a01f lastb xzr, p0, z0\.d
--.*: 05e1a01f lastb xzr, p0, z0\.d
--.*: 05e1a800 lastb x0, p2, z0\.d
--.*: 05e1a800 lastb x0, p2, z0\.d
--.*: 05e1bc00 lastb x0, p7, z0\.d
--.*: 05e1bc00 lastb x0, p7, z0\.d
--.*: 05e1a060 lastb x0, p0, z3\.d
--.*: 05e1a060 lastb x0, p0, z3\.d
--.*: 05e1a3e0 lastb x0, p0, z31\.d
--.*: 05e1a3e0 lastb x0, p0, z31\.d
--.*: 05238000 lastb b0, p0, z0\.b
--.*: 05238000 lastb b0, p0, z0\.b
--.*: 05238001 lastb b1, p0, z0\.b
--.*: 05238001 lastb b1, p0, z0\.b
--.*: 0523801f lastb b31, p0, z0\.b
--.*: 0523801f lastb b31, p0, z0\.b
--.*: 05238800 lastb b0, p2, z0\.b
--.*: 05238800 lastb b0, p2, z0\.b
--.*: 05239c00 lastb b0, p7, z0\.b
--.*: 05239c00 lastb b0, p7, z0\.b
--.*: 05238060 lastb b0, p0, z3\.b
--.*: 05238060 lastb b0, p0, z3\.b
--.*: 052383e0 lastb b0, p0, z31\.b
--.*: 052383e0 lastb b0, p0, z31\.b
--.*: 05638000 lastb h0, p0, z0\.h
--.*: 05638000 lastb h0, p0, z0\.h
--.*: 05638001 lastb h1, p0, z0\.h
--.*: 05638001 lastb h1, p0, z0\.h
--.*: 0563801f lastb h31, p0, z0\.h
--.*: 0563801f lastb h31, p0, z0\.h
--.*: 05638800 lastb h0, p2, z0\.h
--.*: 05638800 lastb h0, p2, z0\.h
--.*: 05639c00 lastb h0, p7, z0\.h
--.*: 05639c00 lastb h0, p7, z0\.h
--.*: 05638060 lastb h0, p0, z3\.h
--.*: 05638060 lastb h0, p0, z3\.h
--.*: 056383e0 lastb h0, p0, z31\.h
--.*: 056383e0 lastb h0, p0, z31\.h
--.*: 05a38000 lastb s0, p0, z0\.s
--.*: 05a38000 lastb s0, p0, z0\.s
--.*: 05a38001 lastb s1, p0, z0\.s
--.*: 05a38001 lastb s1, p0, z0\.s
--.*: 05a3801f lastb s31, p0, z0\.s
--.*: 05a3801f lastb s31, p0, z0\.s
--.*: 05a38800 lastb s0, p2, z0\.s
--.*: 05a38800 lastb s0, p2, z0\.s
--.*: 05a39c00 lastb s0, p7, z0\.s
--.*: 05a39c00 lastb s0, p7, z0\.s
--.*: 05a38060 lastb s0, p0, z3\.s
--.*: 05a38060 lastb s0, p0, z3\.s
--.*: 05a383e0 lastb s0, p0, z31\.s
--.*: 05a383e0 lastb s0, p0, z31\.s
--.*: 05e38000 lastb d0, p0, z0\.d
--.*: 05e38000 lastb d0, p0, z0\.d
--.*: 05e38001 lastb d1, p0, z0\.d
--.*: 05e38001 lastb d1, p0, z0\.d
--.*: 05e3801f lastb d31, p0, z0\.d
--.*: 05e3801f lastb d31, p0, z0\.d
--.*: 05e38800 lastb d0, p2, z0\.d
--.*: 05e38800 lastb d0, p2, z0\.d
--.*: 05e39c00 lastb d0, p7, z0\.d
--.*: 05e39c00 lastb d0, p7, z0\.d
--.*: 05e38060 lastb d0, p0, z3\.d
--.*: 05e38060 lastb d0, p0, z3\.d
--.*: 05e383e0 lastb d0, p0, z31\.d
--.*: 05e383e0 lastb d0, p0, z31\.d
--.*: 84004000 ld1b \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 84004000 ld1b \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 84004000 ld1b \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 84004000 ld1b \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 84004001 ld1b \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 84004001 ld1b \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 84004001 ld1b \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 84004001 ld1b \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 8400401f ld1b \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 8400401f ld1b \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 8400401f ld1b \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 8400401f ld1b \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 84004800 ld1b \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\]
--.*: 84004800 ld1b \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\]
--.*: 84004800 ld1b \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\]
--.*: 84005c00 ld1b \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\]
--.*: 84005c00 ld1b \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\]
--.*: 84005c00 ld1b \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\]
--.*: 84004060 ld1b \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\]
--.*: 84004060 ld1b \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\]
--.*: 84004060 ld1b \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\]
--.*: 840043e0 ld1b \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\]
--.*: 840043e0 ld1b \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\]
--.*: 840043e0 ld1b \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\]
--.*: 84044000 ld1b \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\]
--.*: 84044000 ld1b \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\]
--.*: 84044000 ld1b \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\]
--.*: 841f4000 ld1b \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\]
--.*: 841f4000 ld1b \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\]
--.*: 841f4000 ld1b \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\]
--.*: 84404000 ld1b \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 84404000 ld1b \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 84404000 ld1b \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 84404000 ld1b \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 84404001 ld1b \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 84404001 ld1b \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 84404001 ld1b \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 84404001 ld1b \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 8440401f ld1b \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 8440401f ld1b \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 8440401f ld1b \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 8440401f ld1b \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 84404800 ld1b \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\]
--.*: 84404800 ld1b \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\]
--.*: 84404800 ld1b \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\]
--.*: 84405c00 ld1b \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\]
--.*: 84405c00 ld1b \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\]
--.*: 84405c00 ld1b \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\]
--.*: 84404060 ld1b \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\]
--.*: 84404060 ld1b \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\]
--.*: 84404060 ld1b \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\]
--.*: 844043e0 ld1b \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\]
--.*: 844043e0 ld1b \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\]
--.*: 844043e0 ld1b \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\]
--.*: 84444000 ld1b \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\]
--.*: 84444000 ld1b \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\]
--.*: 84444000 ld1b \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\]
--.*: 845f4000 ld1b \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\]
--.*: 845f4000 ld1b \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\]
--.*: 845f4000 ld1b \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\]
--.*: a4004000 ld1b \{z0\.b\}, p0/z, \[x0, x0\]
--.*: a4004000 ld1b \{z0\.b\}, p0/z, \[x0, x0\]
--.*: a4004000 ld1b \{z0\.b\}, p0/z, \[x0, x0\]
--.*: a4004000 ld1b \{z0\.b\}, p0/z, \[x0, x0\]
--.*: a4004001 ld1b \{z1\.b\}, p0/z, \[x0, x0\]
--.*: a4004001 ld1b \{z1\.b\}, p0/z, \[x0, x0\]
--.*: a4004001 ld1b \{z1\.b\}, p0/z, \[x0, x0\]
--.*: a4004001 ld1b \{z1\.b\}, p0/z, \[x0, x0\]
--.*: a400401f ld1b \{z31\.b\}, p0/z, \[x0, x0\]
--.*: a400401f ld1b \{z31\.b\}, p0/z, \[x0, x0\]
--.*: a400401f ld1b \{z31\.b\}, p0/z, \[x0, x0\]
--.*: a400401f ld1b \{z31\.b\}, p0/z, \[x0, x0\]
--.*: a4004800 ld1b \{z0\.b\}, p2/z, \[x0, x0\]
--.*: a4004800 ld1b \{z0\.b\}, p2/z, \[x0, x0\]
--.*: a4004800 ld1b \{z0\.b\}, p2/z, \[x0, x0\]
--.*: a4005c00 ld1b \{z0\.b\}, p7/z, \[x0, x0\]
--.*: a4005c00 ld1b \{z0\.b\}, p7/z, \[x0, x0\]
--.*: a4005c00 ld1b \{z0\.b\}, p7/z, \[x0, x0\]
--.*: a4004060 ld1b \{z0\.b\}, p0/z, \[x3, x0\]
--.*: a4004060 ld1b \{z0\.b\}, p0/z, \[x3, x0\]
--.*: a4004060 ld1b \{z0\.b\}, p0/z, \[x3, x0\]
--.*: a40043e0 ld1b \{z0\.b\}, p0/z, \[sp, x0\]
--.*: a40043e0 ld1b \{z0\.b\}, p0/z, \[sp, x0\]
--.*: a40043e0 ld1b \{z0\.b\}, p0/z, \[sp, x0\]
--.*: a4044000 ld1b \{z0\.b\}, p0/z, \[x0, x4\]
--.*: a4044000 ld1b \{z0\.b\}, p0/z, \[x0, x4\]
--.*: a4044000 ld1b \{z0\.b\}, p0/z, \[x0, x4\]
--.*: a41e4000 ld1b \{z0\.b\}, p0/z, \[x0, x30\]
--.*: a41e4000 ld1b \{z0\.b\}, p0/z, \[x0, x30\]
--.*: a41e4000 ld1b \{z0\.b\}, p0/z, \[x0, x30\]
--.*: a4204000 ld1b \{z0\.h\}, p0/z, \[x0, x0\]
--.*: a4204000 ld1b \{z0\.h\}, p0/z, \[x0, x0\]
--.*: a4204000 ld1b \{z0\.h\}, p0/z, \[x0, x0\]
--.*: a4204000 ld1b \{z0\.h\}, p0/z, \[x0, x0\]
--.*: a4204001 ld1b \{z1\.h\}, p0/z, \[x0, x0\]
--.*: a4204001 ld1b \{z1\.h\}, p0/z, \[x0, x0\]
--.*: a4204001 ld1b \{z1\.h\}, p0/z, \[x0, x0\]
--.*: a4204001 ld1b \{z1\.h\}, p0/z, \[x0, x0\]
--.*: a420401f ld1b \{z31\.h\}, p0/z, \[x0, x0\]
--.*: a420401f ld1b \{z31\.h\}, p0/z, \[x0, x0\]
--.*: a420401f ld1b \{z31\.h\}, p0/z, \[x0, x0\]
--.*: a420401f ld1b \{z31\.h\}, p0/z, \[x0, x0\]
--.*: a4204800 ld1b \{z0\.h\}, p2/z, \[x0, x0\]
--.*: a4204800 ld1b \{z0\.h\}, p2/z, \[x0, x0\]
--.*: a4204800 ld1b \{z0\.h\}, p2/z, \[x0, x0\]
--.*: a4205c00 ld1b \{z0\.h\}, p7/z, \[x0, x0\]
--.*: a4205c00 ld1b \{z0\.h\}, p7/z, \[x0, x0\]
--.*: a4205c00 ld1b \{z0\.h\}, p7/z, \[x0, x0\]
--.*: a4204060 ld1b \{z0\.h\}, p0/z, \[x3, x0\]
--.*: a4204060 ld1b \{z0\.h\}, p0/z, \[x3, x0\]
--.*: a4204060 ld1b \{z0\.h\}, p0/z, \[x3, x0\]
--.*: a42043e0 ld1b \{z0\.h\}, p0/z, \[sp, x0\]
--.*: a42043e0 ld1b \{z0\.h\}, p0/z, \[sp, x0\]
--.*: a42043e0 ld1b \{z0\.h\}, p0/z, \[sp, x0\]
--.*: a4244000 ld1b \{z0\.h\}, p0/z, \[x0, x4\]
--.*: a4244000 ld1b \{z0\.h\}, p0/z, \[x0, x4\]
--.*: a4244000 ld1b \{z0\.h\}, p0/z, \[x0, x4\]
--.*: a43e4000 ld1b \{z0\.h\}, p0/z, \[x0, x30\]
--.*: a43e4000 ld1b \{z0\.h\}, p0/z, \[x0, x30\]
--.*: a43e4000 ld1b \{z0\.h\}, p0/z, \[x0, x30\]
--.*: a4404000 ld1b \{z0\.s\}, p0/z, \[x0, x0\]
--.*: a4404000 ld1b \{z0\.s\}, p0/z, \[x0, x0\]
--.*: a4404000 ld1b \{z0\.s\}, p0/z, \[x0, x0\]
--.*: a4404000 ld1b \{z0\.s\}, p0/z, \[x0, x0\]
--.*: a4404001 ld1b \{z1\.s\}, p0/z, \[x0, x0\]
--.*: a4404001 ld1b \{z1\.s\}, p0/z, \[x0, x0\]
--.*: a4404001 ld1b \{z1\.s\}, p0/z, \[x0, x0\]
--.*: a4404001 ld1b \{z1\.s\}, p0/z, \[x0, x0\]
--.*: a440401f ld1b \{z31\.s\}, p0/z, \[x0, x0\]
--.*: a440401f ld1b \{z31\.s\}, p0/z, \[x0, x0\]
--.*: a440401f ld1b \{z31\.s\}, p0/z, \[x0, x0\]
--.*: a440401f ld1b \{z31\.s\}, p0/z, \[x0, x0\]
--.*: a4404800 ld1b \{z0\.s\}, p2/z, \[x0, x0\]
--.*: a4404800 ld1b \{z0\.s\}, p2/z, \[x0, x0\]
--.*: a4404800 ld1b \{z0\.s\}, p2/z, \[x0, x0\]
--.*: a4405c00 ld1b \{z0\.s\}, p7/z, \[x0, x0\]
--.*: a4405c00 ld1b \{z0\.s\}, p7/z, \[x0, x0\]
--.*: a4405c00 ld1b \{z0\.s\}, p7/z, \[x0, x0\]
--.*: a4404060 ld1b \{z0\.s\}, p0/z, \[x3, x0\]
--.*: a4404060 ld1b \{z0\.s\}, p0/z, \[x3, x0\]
--.*: a4404060 ld1b \{z0\.s\}, p0/z, \[x3, x0\]
--.*: a44043e0 ld1b \{z0\.s\}, p0/z, \[sp, x0\]
--.*: a44043e0 ld1b \{z0\.s\}, p0/z, \[sp, x0\]
--.*: a44043e0 ld1b \{z0\.s\}, p0/z, \[sp, x0\]
--.*: a4444000 ld1b \{z0\.s\}, p0/z, \[x0, x4\]
--.*: a4444000 ld1b \{z0\.s\}, p0/z, \[x0, x4\]
--.*: a4444000 ld1b \{z0\.s\}, p0/z, \[x0, x4\]
--.*: a45e4000 ld1b \{z0\.s\}, p0/z, \[x0, x30\]
--.*: a45e4000 ld1b \{z0\.s\}, p0/z, \[x0, x30\]
--.*: a45e4000 ld1b \{z0\.s\}, p0/z, \[x0, x30\]
--.*: a4604000 ld1b \{z0\.d\}, p0/z, \[x0, x0\]
--.*: a4604000 ld1b \{z0\.d\}, p0/z, \[x0, x0\]
--.*: a4604000 ld1b \{z0\.d\}, p0/z, \[x0, x0\]
--.*: a4604000 ld1b \{z0\.d\}, p0/z, \[x0, x0\]
--.*: a4604001 ld1b \{z1\.d\}, p0/z, \[x0, x0\]
--.*: a4604001 ld1b \{z1\.d\}, p0/z, \[x0, x0\]
--.*: a4604001 ld1b \{z1\.d\}, p0/z, \[x0, x0\]
--.*: a4604001 ld1b \{z1\.d\}, p0/z, \[x0, x0\]
--.*: a460401f ld1b \{z31\.d\}, p0/z, \[x0, x0\]
--.*: a460401f ld1b \{z31\.d\}, p0/z, \[x0, x0\]
--.*: a460401f ld1b \{z31\.d\}, p0/z, \[x0, x0\]
--.*: a460401f ld1b \{z31\.d\}, p0/z, \[x0, x0\]
--.*: a4604800 ld1b \{z0\.d\}, p2/z, \[x0, x0\]
--.*: a4604800 ld1b \{z0\.d\}, p2/z, \[x0, x0\]
--.*: a4604800 ld1b \{z0\.d\}, p2/z, \[x0, x0\]
--.*: a4605c00 ld1b \{z0\.d\}, p7/z, \[x0, x0\]
--.*: a4605c00 ld1b \{z0\.d\}, p7/z, \[x0, x0\]
--.*: a4605c00 ld1b \{z0\.d\}, p7/z, \[x0, x0\]
--.*: a4604060 ld1b \{z0\.d\}, p0/z, \[x3, x0\]
--.*: a4604060 ld1b \{z0\.d\}, p0/z, \[x3, x0\]
--.*: a4604060 ld1b \{z0\.d\}, p0/z, \[x3, x0\]
--.*: a46043e0 ld1b \{z0\.d\}, p0/z, \[sp, x0\]
--.*: a46043e0 ld1b \{z0\.d\}, p0/z, \[sp, x0\]
--.*: a46043e0 ld1b \{z0\.d\}, p0/z, \[sp, x0\]
--.*: a4644000 ld1b \{z0\.d\}, p0/z, \[x0, x4\]
--.*: a4644000 ld1b \{z0\.d\}, p0/z, \[x0, x4\]
--.*: a4644000 ld1b \{z0\.d\}, p0/z, \[x0, x4\]
--.*: a47e4000 ld1b \{z0\.d\}, p0/z, \[x0, x30\]
--.*: a47e4000 ld1b \{z0\.d\}, p0/z, \[x0, x30\]
--.*: a47e4000 ld1b \{z0\.d\}, p0/z, \[x0, x30\]
--.*: c4004000 ld1b \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c4004000 ld1b \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c4004000 ld1b \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c4004000 ld1b \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c4004001 ld1b \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c4004001 ld1b \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c4004001 ld1b \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c4004001 ld1b \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c400401f ld1b \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c400401f ld1b \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c400401f ld1b \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c400401f ld1b \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c4004800 ld1b \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\]
--.*: c4004800 ld1b \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\]
--.*: c4004800 ld1b \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\]
--.*: c4005c00 ld1b \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\]
--.*: c4005c00 ld1b \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\]
--.*: c4005c00 ld1b \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\]
--.*: c4004060 ld1b \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\]
--.*: c4004060 ld1b \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\]
--.*: c4004060 ld1b \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\]
--.*: c40043e0 ld1b \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\]
--.*: c40043e0 ld1b \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\]
--.*: c40043e0 ld1b \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\]
--.*: c4044000 ld1b \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\]
--.*: c4044000 ld1b \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\]
--.*: c4044000 ld1b \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\]
--.*: c41f4000 ld1b \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\]
--.*: c41f4000 ld1b \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\]
--.*: c41f4000 ld1b \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\]
--.*: c4404000 ld1b \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c4404000 ld1b \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c4404000 ld1b \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c4404000 ld1b \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c4404001 ld1b \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c4404001 ld1b \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c4404001 ld1b \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c4404001 ld1b \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c440401f ld1b \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c440401f ld1b \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c440401f ld1b \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c440401f ld1b \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c4404800 ld1b \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\]
--.*: c4404800 ld1b \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\]
--.*: c4404800 ld1b \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\]
--.*: c4405c00 ld1b \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\]
--.*: c4405c00 ld1b \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\]
--.*: c4405c00 ld1b \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\]
--.*: c4404060 ld1b \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\]
--.*: c4404060 ld1b \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\]
--.*: c4404060 ld1b \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\]
--.*: c44043e0 ld1b \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\]
--.*: c44043e0 ld1b \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\]
--.*: c44043e0 ld1b \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\]
--.*: c4444000 ld1b \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\]
--.*: c4444000 ld1b \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\]
--.*: c4444000 ld1b \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\]
--.*: c45f4000 ld1b \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\]
--.*: c45f4000 ld1b \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\]
--.*: c45f4000 ld1b \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\]
--.*: c440c000 ld1b \{z0\.d\}, p0/z, \[x0, z0\.d\]
--.*: c440c000 ld1b \{z0\.d\}, p0/z, \[x0, z0\.d\]
--.*: c440c000 ld1b \{z0\.d\}, p0/z, \[x0, z0\.d\]
--.*: c440c000 ld1b \{z0\.d\}, p0/z, \[x0, z0\.d\]
--.*: c440c001 ld1b \{z1\.d\}, p0/z, \[x0, z0\.d\]
--.*: c440c001 ld1b \{z1\.d\}, p0/z, \[x0, z0\.d\]
--.*: c440c001 ld1b \{z1\.d\}, p0/z, \[x0, z0\.d\]
--.*: c440c001 ld1b \{z1\.d\}, p0/z, \[x0, z0\.d\]
--.*: c440c01f ld1b \{z31\.d\}, p0/z, \[x0, z0\.d\]
--.*: c440c01f ld1b \{z31\.d\}, p0/z, \[x0, z0\.d\]
--.*: c440c01f ld1b \{z31\.d\}, p0/z, \[x0, z0\.d\]
--.*: c440c01f ld1b \{z31\.d\}, p0/z, \[x0, z0\.d\]
--.*: c440c800 ld1b \{z0\.d\}, p2/z, \[x0, z0\.d\]
--.*: c440c800 ld1b \{z0\.d\}, p2/z, \[x0, z0\.d\]
--.*: c440c800 ld1b \{z0\.d\}, p2/z, \[x0, z0\.d\]
--.*: c440dc00 ld1b \{z0\.d\}, p7/z, \[x0, z0\.d\]
--.*: c440dc00 ld1b \{z0\.d\}, p7/z, \[x0, z0\.d\]
--.*: c440dc00 ld1b \{z0\.d\}, p7/z, \[x0, z0\.d\]
--.*: c440c060 ld1b \{z0\.d\}, p0/z, \[x3, z0\.d\]
--.*: c440c060 ld1b \{z0\.d\}, p0/z, \[x3, z0\.d\]
--.*: c440c060 ld1b \{z0\.d\}, p0/z, \[x3, z0\.d\]
--.*: c440c3e0 ld1b \{z0\.d\}, p0/z, \[sp, z0\.d\]
--.*: c440c3e0 ld1b \{z0\.d\}, p0/z, \[sp, z0\.d\]
--.*: c440c3e0 ld1b \{z0\.d\}, p0/z, \[sp, z0\.d\]
--.*: c444c000 ld1b \{z0\.d\}, p0/z, \[x0, z4\.d\]
--.*: c444c000 ld1b \{z0\.d\}, p0/z, \[x0, z4\.d\]
--.*: c444c000 ld1b \{z0\.d\}, p0/z, \[x0, z4\.d\]
--.*: c45fc000 ld1b \{z0\.d\}, p0/z, \[x0, z31\.d\]
--.*: c45fc000 ld1b \{z0\.d\}, p0/z, \[x0, z31\.d\]
--.*: c45fc000 ld1b \{z0\.d\}, p0/z, \[x0, z31\.d\]
--.*: 8420c000 ld1b \{z0\.s\}, p0/z, \[z0\.s\]
--.*: 8420c000 ld1b \{z0\.s\}, p0/z, \[z0\.s\]
--.*: 8420c000 ld1b \{z0\.s\}, p0/z, \[z0\.s\]
--.*: 8420c000 ld1b \{z0\.s\}, p0/z, \[z0\.s\]
--.*: 8420c001 ld1b \{z1\.s\}, p0/z, \[z0\.s\]
--.*: 8420c001 ld1b \{z1\.s\}, p0/z, \[z0\.s\]
--.*: 8420c001 ld1b \{z1\.s\}, p0/z, \[z0\.s\]
--.*: 8420c001 ld1b \{z1\.s\}, p0/z, \[z0\.s\]
--.*: 8420c01f ld1b \{z31\.s\}, p0/z, \[z0\.s\]
--.*: 8420c01f ld1b \{z31\.s\}, p0/z, \[z0\.s\]
--.*: 8420c01f ld1b \{z31\.s\}, p0/z, \[z0\.s\]
--.*: 8420c01f ld1b \{z31\.s\}, p0/z, \[z0\.s\]
--.*: 8420c800 ld1b \{z0\.s\}, p2/z, \[z0\.s\]
--.*: 8420c800 ld1b \{z0\.s\}, p2/z, \[z0\.s\]
--.*: 8420c800 ld1b \{z0\.s\}, p2/z, \[z0\.s\]
--.*: 8420dc00 ld1b \{z0\.s\}, p7/z, \[z0\.s\]
--.*: 8420dc00 ld1b \{z0\.s\}, p7/z, \[z0\.s\]
--.*: 8420dc00 ld1b \{z0\.s\}, p7/z, \[z0\.s\]
--.*: 8420c060 ld1b \{z0\.s\}, p0/z, \[z3\.s\]
--.*: 8420c060 ld1b \{z0\.s\}, p0/z, \[z3\.s\]
--.*: 8420c060 ld1b \{z0\.s\}, p0/z, \[z3\.s\]
--.*: 8420c3e0 ld1b \{z0\.s\}, p0/z, \[z31\.s\]
--.*: 8420c3e0 ld1b \{z0\.s\}, p0/z, \[z31\.s\]
--.*: 8420c3e0 ld1b \{z0\.s\}, p0/z, \[z31\.s\]
--.*: 842fc000 ld1b \{z0\.s\}, p0/z, \[z0\.s, #15\]
--.*: 842fc000 ld1b \{z0\.s\}, p0/z, \[z0\.s, #15\]
--.*: 8430c000 ld1b \{z0\.s\}, p0/z, \[z0\.s, #16\]
--.*: 8430c000 ld1b \{z0\.s\}, p0/z, \[z0\.s, #16\]
--.*: 8431c000 ld1b \{z0\.s\}, p0/z, \[z0\.s, #17\]
--.*: 8431c000 ld1b \{z0\.s\}, p0/z, \[z0\.s, #17\]
--.*: 843fc000 ld1b \{z0\.s\}, p0/z, \[z0\.s, #31\]
--.*: 843fc000 ld1b \{z0\.s\}, p0/z, \[z0\.s, #31\]
--.*: a400a000 ld1b \{z0\.b\}, p0/z, \[x0\]
--.*: a400a000 ld1b \{z0\.b\}, p0/z, \[x0\]
--.*: a400a000 ld1b \{z0\.b\}, p0/z, \[x0\]
--.*: a400a000 ld1b \{z0\.b\}, p0/z, \[x0\]
--.*: a400a000 ld1b \{z0\.b\}, p0/z, \[x0\]
--.*: a400a001 ld1b \{z1\.b\}, p0/z, \[x0\]
--.*: a400a001 ld1b \{z1\.b\}, p0/z, \[x0\]
--.*: a400a001 ld1b \{z1\.b\}, p0/z, \[x0\]
--.*: a400a001 ld1b \{z1\.b\}, p0/z, \[x0\]
--.*: a400a001 ld1b \{z1\.b\}, p0/z, \[x0\]
--.*: a400a01f ld1b \{z31\.b\}, p0/z, \[x0\]
--.*: a400a01f ld1b \{z31\.b\}, p0/z, \[x0\]
--.*: a400a01f ld1b \{z31\.b\}, p0/z, \[x0\]
--.*: a400a01f ld1b \{z31\.b\}, p0/z, \[x0\]
--.*: a400a01f ld1b \{z31\.b\}, p0/z, \[x0\]
--.*: a400a800 ld1b \{z0\.b\}, p2/z, \[x0\]
--.*: a400a800 ld1b \{z0\.b\}, p2/z, \[x0\]
--.*: a400a800 ld1b \{z0\.b\}, p2/z, \[x0\]
--.*: a400a800 ld1b \{z0\.b\}, p2/z, \[x0\]
--.*: a400bc00 ld1b \{z0\.b\}, p7/z, \[x0\]
--.*: a400bc00 ld1b \{z0\.b\}, p7/z, \[x0\]
--.*: a400bc00 ld1b \{z0\.b\}, p7/z, \[x0\]
--.*: a400bc00 ld1b \{z0\.b\}, p7/z, \[x0\]
--.*: a400a060 ld1b \{z0\.b\}, p0/z, \[x3\]
--.*: a400a060 ld1b \{z0\.b\}, p0/z, \[x3\]
--.*: a400a060 ld1b \{z0\.b\}, p0/z, \[x3\]
--.*: a400a060 ld1b \{z0\.b\}, p0/z, \[x3\]
--.*: a400a3e0 ld1b \{z0\.b\}, p0/z, \[sp\]
--.*: a400a3e0 ld1b \{z0\.b\}, p0/z, \[sp\]
--.*: a400a3e0 ld1b \{z0\.b\}, p0/z, \[sp\]
--.*: a400a3e0 ld1b \{z0\.b\}, p0/z, \[sp\]
--.*: a407a000 ld1b \{z0\.b\}, p0/z, \[x0, #7, mul vl\]
--.*: a407a000 ld1b \{z0\.b\}, p0/z, \[x0, #7, mul vl\]
--.*: a408a000 ld1b \{z0\.b\}, p0/z, \[x0, #-8, mul vl\]
--.*: a408a000 ld1b \{z0\.b\}, p0/z, \[x0, #-8, mul vl\]
--.*: a409a000 ld1b \{z0\.b\}, p0/z, \[x0, #-7, mul vl\]
--.*: a409a000 ld1b \{z0\.b\}, p0/z, \[x0, #-7, mul vl\]
--.*: a40fa000 ld1b \{z0\.b\}, p0/z, \[x0, #-1, mul vl\]
--.*: a40fa000 ld1b \{z0\.b\}, p0/z, \[x0, #-1, mul vl\]
--.*: a420a000 ld1b \{z0\.h\}, p0/z, \[x0\]
--.*: a420a000 ld1b \{z0\.h\}, p0/z, \[x0\]
--.*: a420a000 ld1b \{z0\.h\}, p0/z, \[x0\]
--.*: a420a000 ld1b \{z0\.h\}, p0/z, \[x0\]
--.*: a420a000 ld1b \{z0\.h\}, p0/z, \[x0\]
--.*: a420a001 ld1b \{z1\.h\}, p0/z, \[x0\]
--.*: a420a001 ld1b \{z1\.h\}, p0/z, \[x0\]
--.*: a420a001 ld1b \{z1\.h\}, p0/z, \[x0\]
--.*: a420a001 ld1b \{z1\.h\}, p0/z, \[x0\]
--.*: a420a001 ld1b \{z1\.h\}, p0/z, \[x0\]
--.*: a420a01f ld1b \{z31\.h\}, p0/z, \[x0\]
--.*: a420a01f ld1b \{z31\.h\}, p0/z, \[x0\]
--.*: a420a01f ld1b \{z31\.h\}, p0/z, \[x0\]
--.*: a420a01f ld1b \{z31\.h\}, p0/z, \[x0\]
--.*: a420a01f ld1b \{z31\.h\}, p0/z, \[x0\]
--.*: a420a800 ld1b \{z0\.h\}, p2/z, \[x0\]
--.*: a420a800 ld1b \{z0\.h\}, p2/z, \[x0\]
--.*: a420a800 ld1b \{z0\.h\}, p2/z, \[x0\]
--.*: a420a800 ld1b \{z0\.h\}, p2/z, \[x0\]
--.*: a420bc00 ld1b \{z0\.h\}, p7/z, \[x0\]
--.*: a420bc00 ld1b \{z0\.h\}, p7/z, \[x0\]
--.*: a420bc00 ld1b \{z0\.h\}, p7/z, \[x0\]
--.*: a420bc00 ld1b \{z0\.h\}, p7/z, \[x0\]
--.*: a420a060 ld1b \{z0\.h\}, p0/z, \[x3\]
--.*: a420a060 ld1b \{z0\.h\}, p0/z, \[x3\]
--.*: a420a060 ld1b \{z0\.h\}, p0/z, \[x3\]
--.*: a420a060 ld1b \{z0\.h\}, p0/z, \[x3\]
--.*: a420a3e0 ld1b \{z0\.h\}, p0/z, \[sp\]
--.*: a420a3e0 ld1b \{z0\.h\}, p0/z, \[sp\]
--.*: a420a3e0 ld1b \{z0\.h\}, p0/z, \[sp\]
--.*: a420a3e0 ld1b \{z0\.h\}, p0/z, \[sp\]
--.*: a427a000 ld1b \{z0\.h\}, p0/z, \[x0, #7, mul vl\]
--.*: a427a000 ld1b \{z0\.h\}, p0/z, \[x0, #7, mul vl\]
--.*: a428a000 ld1b \{z0\.h\}, p0/z, \[x0, #-8, mul vl\]
--.*: a428a000 ld1b \{z0\.h\}, p0/z, \[x0, #-8, mul vl\]
--.*: a429a000 ld1b \{z0\.h\}, p0/z, \[x0, #-7, mul vl\]
--.*: a429a000 ld1b \{z0\.h\}, p0/z, \[x0, #-7, mul vl\]
--.*: a42fa000 ld1b \{z0\.h\}, p0/z, \[x0, #-1, mul vl\]
--.*: a42fa000 ld1b \{z0\.h\}, p0/z, \[x0, #-1, mul vl\]
--.*: a440a000 ld1b \{z0\.s\}, p0/z, \[x0\]
--.*: a440a000 ld1b \{z0\.s\}, p0/z, \[x0\]
--.*: a440a000 ld1b \{z0\.s\}, p0/z, \[x0\]
--.*: a440a000 ld1b \{z0\.s\}, p0/z, \[x0\]
--.*: a440a000 ld1b \{z0\.s\}, p0/z, \[x0\]
--.*: a440a001 ld1b \{z1\.s\}, p0/z, \[x0\]
--.*: a440a001 ld1b \{z1\.s\}, p0/z, \[x0\]
--.*: a440a001 ld1b \{z1\.s\}, p0/z, \[x0\]
--.*: a440a001 ld1b \{z1\.s\}, p0/z, \[x0\]
--.*: a440a001 ld1b \{z1\.s\}, p0/z, \[x0\]
--.*: a440a01f ld1b \{z31\.s\}, p0/z, \[x0\]
--.*: a440a01f ld1b \{z31\.s\}, p0/z, \[x0\]
--.*: a440a01f ld1b \{z31\.s\}, p0/z, \[x0\]
--.*: a440a01f ld1b \{z31\.s\}, p0/z, \[x0\]
--.*: a440a01f ld1b \{z31\.s\}, p0/z, \[x0\]
--.*: a440a800 ld1b \{z0\.s\}, p2/z, \[x0\]
--.*: a440a800 ld1b \{z0\.s\}, p2/z, \[x0\]
--.*: a440a800 ld1b \{z0\.s\}, p2/z, \[x0\]
--.*: a440a800 ld1b \{z0\.s\}, p2/z, \[x0\]
--.*: a440bc00 ld1b \{z0\.s\}, p7/z, \[x0\]
--.*: a440bc00 ld1b \{z0\.s\}, p7/z, \[x0\]
--.*: a440bc00 ld1b \{z0\.s\}, p7/z, \[x0\]
--.*: a440bc00 ld1b \{z0\.s\}, p7/z, \[x0\]
--.*: a440a060 ld1b \{z0\.s\}, p0/z, \[x3\]
--.*: a440a060 ld1b \{z0\.s\}, p0/z, \[x3\]
--.*: a440a060 ld1b \{z0\.s\}, p0/z, \[x3\]
--.*: a440a060 ld1b \{z0\.s\}, p0/z, \[x3\]
--.*: a440a3e0 ld1b \{z0\.s\}, p0/z, \[sp\]
--.*: a440a3e0 ld1b \{z0\.s\}, p0/z, \[sp\]
--.*: a440a3e0 ld1b \{z0\.s\}, p0/z, \[sp\]
--.*: a440a3e0 ld1b \{z0\.s\}, p0/z, \[sp\]
--.*: a447a000 ld1b \{z0\.s\}, p0/z, \[x0, #7, mul vl\]
--.*: a447a000 ld1b \{z0\.s\}, p0/z, \[x0, #7, mul vl\]
--.*: a448a000 ld1b \{z0\.s\}, p0/z, \[x0, #-8, mul vl\]
--.*: a448a000 ld1b \{z0\.s\}, p0/z, \[x0, #-8, mul vl\]
--.*: a449a000 ld1b \{z0\.s\}, p0/z, \[x0, #-7, mul vl\]
--.*: a449a000 ld1b \{z0\.s\}, p0/z, \[x0, #-7, mul vl\]
--.*: a44fa000 ld1b \{z0\.s\}, p0/z, \[x0, #-1, mul vl\]
--.*: a44fa000 ld1b \{z0\.s\}, p0/z, \[x0, #-1, mul vl\]
--.*: a460a000 ld1b \{z0\.d\}, p0/z, \[x0\]
--.*: a460a000 ld1b \{z0\.d\}, p0/z, \[x0\]
--.*: a460a000 ld1b \{z0\.d\}, p0/z, \[x0\]
--.*: a460a000 ld1b \{z0\.d\}, p0/z, \[x0\]
--.*: a460a000 ld1b \{z0\.d\}, p0/z, \[x0\]
--.*: a460a001 ld1b \{z1\.d\}, p0/z, \[x0\]
--.*: a460a001 ld1b \{z1\.d\}, p0/z, \[x0\]
--.*: a460a001 ld1b \{z1\.d\}, p0/z, \[x0\]
--.*: a460a001 ld1b \{z1\.d\}, p0/z, \[x0\]
--.*: a460a001 ld1b \{z1\.d\}, p0/z, \[x0\]
--.*: a460a01f ld1b \{z31\.d\}, p0/z, \[x0\]
--.*: a460a01f ld1b \{z31\.d\}, p0/z, \[x0\]
--.*: a460a01f ld1b \{z31\.d\}, p0/z, \[x0\]
--.*: a460a01f ld1b \{z31\.d\}, p0/z, \[x0\]
--.*: a460a01f ld1b \{z31\.d\}, p0/z, \[x0\]
--.*: a460a800 ld1b \{z0\.d\}, p2/z, \[x0\]
--.*: a460a800 ld1b \{z0\.d\}, p2/z, \[x0\]
--.*: a460a800 ld1b \{z0\.d\}, p2/z, \[x0\]
--.*: a460a800 ld1b \{z0\.d\}, p2/z, \[x0\]
--.*: a460bc00 ld1b \{z0\.d\}, p7/z, \[x0\]
--.*: a460bc00 ld1b \{z0\.d\}, p7/z, \[x0\]
--.*: a460bc00 ld1b \{z0\.d\}, p7/z, \[x0\]
--.*: a460bc00 ld1b \{z0\.d\}, p7/z, \[x0\]
--.*: a460a060 ld1b \{z0\.d\}, p0/z, \[x3\]
--.*: a460a060 ld1b \{z0\.d\}, p0/z, \[x3\]
--.*: a460a060 ld1b \{z0\.d\}, p0/z, \[x3\]
--.*: a460a060 ld1b \{z0\.d\}, p0/z, \[x3\]
--.*: a460a3e0 ld1b \{z0\.d\}, p0/z, \[sp\]
--.*: a460a3e0 ld1b \{z0\.d\}, p0/z, \[sp\]
--.*: a460a3e0 ld1b \{z0\.d\}, p0/z, \[sp\]
--.*: a460a3e0 ld1b \{z0\.d\}, p0/z, \[sp\]
--.*: a467a000 ld1b \{z0\.d\}, p0/z, \[x0, #7, mul vl\]
--.*: a467a000 ld1b \{z0\.d\}, p0/z, \[x0, #7, mul vl\]
--.*: a468a000 ld1b \{z0\.d\}, p0/z, \[x0, #-8, mul vl\]
--.*: a468a000 ld1b \{z0\.d\}, p0/z, \[x0, #-8, mul vl\]
--.*: a469a000 ld1b \{z0\.d\}, p0/z, \[x0, #-7, mul vl\]
--.*: a469a000 ld1b \{z0\.d\}, p0/z, \[x0, #-7, mul vl\]
--.*: a46fa000 ld1b \{z0\.d\}, p0/z, \[x0, #-1, mul vl\]
--.*: a46fa000 ld1b \{z0\.d\}, p0/z, \[x0, #-1, mul vl\]
--.*: c420c000 ld1b \{z0\.d\}, p0/z, \[z0\.d\]
--.*: c420c000 ld1b \{z0\.d\}, p0/z, \[z0\.d\]
--.*: c420c000 ld1b \{z0\.d\}, p0/z, \[z0\.d\]
--.*: c420c000 ld1b \{z0\.d\}, p0/z, \[z0\.d\]
--.*: c420c001 ld1b \{z1\.d\}, p0/z, \[z0\.d\]
--.*: c420c001 ld1b \{z1\.d\}, p0/z, \[z0\.d\]
--.*: c420c001 ld1b \{z1\.d\}, p0/z, \[z0\.d\]
--.*: c420c001 ld1b \{z1\.d\}, p0/z, \[z0\.d\]
--.*: c420c01f ld1b \{z31\.d\}, p0/z, \[z0\.d\]
--.*: c420c01f ld1b \{z31\.d\}, p0/z, \[z0\.d\]
--.*: c420c01f ld1b \{z31\.d\}, p0/z, \[z0\.d\]
--.*: c420c01f ld1b \{z31\.d\}, p0/z, \[z0\.d\]
--.*: c420c800 ld1b \{z0\.d\}, p2/z, \[z0\.d\]
--.*: c420c800 ld1b \{z0\.d\}, p2/z, \[z0\.d\]
--.*: c420c800 ld1b \{z0\.d\}, p2/z, \[z0\.d\]
--.*: c420dc00 ld1b \{z0\.d\}, p7/z, \[z0\.d\]
--.*: c420dc00 ld1b \{z0\.d\}, p7/z, \[z0\.d\]
--.*: c420dc00 ld1b \{z0\.d\}, p7/z, \[z0\.d\]
--.*: c420c060 ld1b \{z0\.d\}, p0/z, \[z3\.d\]
--.*: c420c060 ld1b \{z0\.d\}, p0/z, \[z3\.d\]
--.*: c420c060 ld1b \{z0\.d\}, p0/z, \[z3\.d\]
--.*: c420c3e0 ld1b \{z0\.d\}, p0/z, \[z31\.d\]
--.*: c420c3e0 ld1b \{z0\.d\}, p0/z, \[z31\.d\]
--.*: c420c3e0 ld1b \{z0\.d\}, p0/z, \[z31\.d\]
--.*: c42fc000 ld1b \{z0\.d\}, p0/z, \[z0\.d, #15\]
--.*: c42fc000 ld1b \{z0\.d\}, p0/z, \[z0\.d, #15\]
--.*: c430c000 ld1b \{z0\.d\}, p0/z, \[z0\.d, #16\]
--.*: c430c000 ld1b \{z0\.d\}, p0/z, \[z0\.d, #16\]
--.*: c431c000 ld1b \{z0\.d\}, p0/z, \[z0\.d, #17\]
--.*: c431c000 ld1b \{z0\.d\}, p0/z, \[z0\.d, #17\]
--.*: c43fc000 ld1b \{z0\.d\}, p0/z, \[z0\.d, #31\]
--.*: c43fc000 ld1b \{z0\.d\}, p0/z, \[z0\.d, #31\]
--.*: a5e04000 ld1d \{z0\.d\}, p0/z, \[x0, x0, lsl #3\]
--.*: a5e04000 ld1d \{z0\.d\}, p0/z, \[x0, x0, lsl #3\]
--.*: a5e04000 ld1d \{z0\.d\}, p0/z, \[x0, x0, lsl #3\]
--.*: a5e04001 ld1d \{z1\.d\}, p0/z, \[x0, x0, lsl #3\]
--.*: a5e04001 ld1d \{z1\.d\}, p0/z, \[x0, x0, lsl #3\]
--.*: a5e04001 ld1d \{z1\.d\}, p0/z, \[x0, x0, lsl #3\]
--.*: a5e0401f ld1d \{z31\.d\}, p0/z, \[x0, x0, lsl #3\]
--.*: a5e0401f ld1d \{z31\.d\}, p0/z, \[x0, x0, lsl #3\]
--.*: a5e0401f ld1d \{z31\.d\}, p0/z, \[x0, x0, lsl #3\]
--.*: a5e04800 ld1d \{z0\.d\}, p2/z, \[x0, x0, lsl #3\]
--.*: a5e04800 ld1d \{z0\.d\}, p2/z, \[x0, x0, lsl #3\]
--.*: a5e05c00 ld1d \{z0\.d\}, p7/z, \[x0, x0, lsl #3\]
--.*: a5e05c00 ld1d \{z0\.d\}, p7/z, \[x0, x0, lsl #3\]
--.*: a5e04060 ld1d \{z0\.d\}, p0/z, \[x3, x0, lsl #3\]
--.*: a5e04060 ld1d \{z0\.d\}, p0/z, \[x3, x0, lsl #3\]
--.*: a5e043e0 ld1d \{z0\.d\}, p0/z, \[sp, x0, lsl #3\]
--.*: a5e043e0 ld1d \{z0\.d\}, p0/z, \[sp, x0, lsl #3\]
--.*: a5e44000 ld1d \{z0\.d\}, p0/z, \[x0, x4, lsl #3\]
--.*: a5e44000 ld1d \{z0\.d\}, p0/z, \[x0, x4, lsl #3\]
--.*: a5fe4000 ld1d \{z0\.d\}, p0/z, \[x0, x30, lsl #3\]
--.*: a5fe4000 ld1d \{z0\.d\}, p0/z, \[x0, x30, lsl #3\]
--.*: c5804000 ld1d \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c5804000 ld1d \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c5804000 ld1d \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c5804000 ld1d \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c5804001 ld1d \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c5804001 ld1d \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c5804001 ld1d \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c5804001 ld1d \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c580401f ld1d \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c580401f ld1d \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c580401f ld1d \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c580401f ld1d \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c5804800 ld1d \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\]
--.*: c5804800 ld1d \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\]
--.*: c5804800 ld1d \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\]
--.*: c5805c00 ld1d \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\]
--.*: c5805c00 ld1d \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\]
--.*: c5805c00 ld1d \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\]
--.*: c5804060 ld1d \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\]
--.*: c5804060 ld1d \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\]
--.*: c5804060 ld1d \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\]
--.*: c58043e0 ld1d \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\]
--.*: c58043e0 ld1d \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\]
--.*: c58043e0 ld1d \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\]
--.*: c5844000 ld1d \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\]
--.*: c5844000 ld1d \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\]
--.*: c5844000 ld1d \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\]
--.*: c59f4000 ld1d \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\]
--.*: c59f4000 ld1d \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\]
--.*: c59f4000 ld1d \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\]
--.*: c5c04000 ld1d \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c5c04000 ld1d \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c5c04000 ld1d \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c5c04000 ld1d \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c5c04001 ld1d \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c5c04001 ld1d \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c5c04001 ld1d \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c5c04001 ld1d \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c5c0401f ld1d \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c5c0401f ld1d \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c5c0401f ld1d \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c5c0401f ld1d \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c5c04800 ld1d \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\]
--.*: c5c04800 ld1d \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\]
--.*: c5c04800 ld1d \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\]
--.*: c5c05c00 ld1d \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\]
--.*: c5c05c00 ld1d \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\]
--.*: c5c05c00 ld1d \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\]
--.*: c5c04060 ld1d \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\]
--.*: c5c04060 ld1d \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\]
--.*: c5c04060 ld1d \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\]
--.*: c5c043e0 ld1d \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\]
--.*: c5c043e0 ld1d \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\]
--.*: c5c043e0 ld1d \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\]
--.*: c5c44000 ld1d \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\]
--.*: c5c44000 ld1d \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\]
--.*: c5c44000 ld1d \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\]
--.*: c5df4000 ld1d \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\]
--.*: c5df4000 ld1d \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\]
--.*: c5df4000 ld1d \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\]
--.*: c5a04000 ld1d \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #3\]
--.*: c5a04000 ld1d \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #3\]
--.*: c5a04000 ld1d \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #3\]
--.*: c5a04001 ld1d \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #3\]
--.*: c5a04001 ld1d \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #3\]
--.*: c5a04001 ld1d \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #3\]
--.*: c5a0401f ld1d \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #3\]
--.*: c5a0401f ld1d \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #3\]
--.*: c5a0401f ld1d \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #3\]
--.*: c5a04800 ld1d \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw #3\]
--.*: c5a04800 ld1d \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw #3\]
--.*: c5a05c00 ld1d \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw #3\]
--.*: c5a05c00 ld1d \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw #3\]
--.*: c5a04060 ld1d \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw #3\]
--.*: c5a04060 ld1d \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw #3\]
--.*: c5a043e0 ld1d \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw #3\]
--.*: c5a043e0 ld1d \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw #3\]
--.*: c5a44000 ld1d \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw #3\]
--.*: c5a44000 ld1d \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw #3\]
--.*: c5bf4000 ld1d \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw #3\]
--.*: c5bf4000 ld1d \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw #3\]
--.*: c5e04000 ld1d \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #3\]
--.*: c5e04000 ld1d \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #3\]
--.*: c5e04000 ld1d \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #3\]
--.*: c5e04001 ld1d \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #3\]
--.*: c5e04001 ld1d \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #3\]
--.*: c5e04001 ld1d \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #3\]
--.*: c5e0401f ld1d \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #3\]
--.*: c5e0401f ld1d \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #3\]
--.*: c5e0401f ld1d \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #3\]
--.*: c5e04800 ld1d \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw #3\]
--.*: c5e04800 ld1d \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw #3\]
--.*: c5e05c00 ld1d \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw #3\]
--.*: c5e05c00 ld1d \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw #3\]
--.*: c5e04060 ld1d \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw #3\]
--.*: c5e04060 ld1d \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw #3\]
--.*: c5e043e0 ld1d \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw #3\]
--.*: c5e043e0 ld1d \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw #3\]
--.*: c5e44000 ld1d \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw #3\]
--.*: c5e44000 ld1d \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw #3\]
--.*: c5ff4000 ld1d \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw #3\]
--.*: c5ff4000 ld1d \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw #3\]
--.*: c5c0c000 ld1d \{z0\.d\}, p0/z, \[x0, z0\.d\]
--.*: c5c0c000 ld1d \{z0\.d\}, p0/z, \[x0, z0\.d\]
--.*: c5c0c000 ld1d \{z0\.d\}, p0/z, \[x0, z0\.d\]
--.*: c5c0c000 ld1d \{z0\.d\}, p0/z, \[x0, z0\.d\]
--.*: c5c0c001 ld1d \{z1\.d\}, p0/z, \[x0, z0\.d\]
--.*: c5c0c001 ld1d \{z1\.d\}, p0/z, \[x0, z0\.d\]
--.*: c5c0c001 ld1d \{z1\.d\}, p0/z, \[x0, z0\.d\]
--.*: c5c0c001 ld1d \{z1\.d\}, p0/z, \[x0, z0\.d\]
--.*: c5c0c01f ld1d \{z31\.d\}, p0/z, \[x0, z0\.d\]
--.*: c5c0c01f ld1d \{z31\.d\}, p0/z, \[x0, z0\.d\]
--.*: c5c0c01f ld1d \{z31\.d\}, p0/z, \[x0, z0\.d\]
--.*: c5c0c01f ld1d \{z31\.d\}, p0/z, \[x0, z0\.d\]
--.*: c5c0c800 ld1d \{z0\.d\}, p2/z, \[x0, z0\.d\]
--.*: c5c0c800 ld1d \{z0\.d\}, p2/z, \[x0, z0\.d\]
--.*: c5c0c800 ld1d \{z0\.d\}, p2/z, \[x0, z0\.d\]
--.*: c5c0dc00 ld1d \{z0\.d\}, p7/z, \[x0, z0\.d\]
--.*: c5c0dc00 ld1d \{z0\.d\}, p7/z, \[x0, z0\.d\]
--.*: c5c0dc00 ld1d \{z0\.d\}, p7/z, \[x0, z0\.d\]
--.*: c5c0c060 ld1d \{z0\.d\}, p0/z, \[x3, z0\.d\]
--.*: c5c0c060 ld1d \{z0\.d\}, p0/z, \[x3, z0\.d\]
--.*: c5c0c060 ld1d \{z0\.d\}, p0/z, \[x3, z0\.d\]
--.*: c5c0c3e0 ld1d \{z0\.d\}, p0/z, \[sp, z0\.d\]
--.*: c5c0c3e0 ld1d \{z0\.d\}, p0/z, \[sp, z0\.d\]
--.*: c5c0c3e0 ld1d \{z0\.d\}, p0/z, \[sp, z0\.d\]
--.*: c5c4c000 ld1d \{z0\.d\}, p0/z, \[x0, z4\.d\]
--.*: c5c4c000 ld1d \{z0\.d\}, p0/z, \[x0, z4\.d\]
--.*: c5c4c000 ld1d \{z0\.d\}, p0/z, \[x0, z4\.d\]
--.*: c5dfc000 ld1d \{z0\.d\}, p0/z, \[x0, z31\.d\]
--.*: c5dfc000 ld1d \{z0\.d\}, p0/z, \[x0, z31\.d\]
--.*: c5dfc000 ld1d \{z0\.d\}, p0/z, \[x0, z31\.d\]
--.*: c5e0c000 ld1d \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #3\]
--.*: c5e0c000 ld1d \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #3\]
--.*: c5e0c000 ld1d \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #3\]
--.*: c5e0c001 ld1d \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #3\]
--.*: c5e0c001 ld1d \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #3\]
--.*: c5e0c001 ld1d \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #3\]
--.*: c5e0c01f ld1d \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #3\]
--.*: c5e0c01f ld1d \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #3\]
--.*: c5e0c01f ld1d \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #3\]
--.*: c5e0c800 ld1d \{z0\.d\}, p2/z, \[x0, z0\.d, lsl #3\]
--.*: c5e0c800 ld1d \{z0\.d\}, p2/z, \[x0, z0\.d, lsl #3\]
--.*: c5e0dc00 ld1d \{z0\.d\}, p7/z, \[x0, z0\.d, lsl #3\]
--.*: c5e0dc00 ld1d \{z0\.d\}, p7/z, \[x0, z0\.d, lsl #3\]
--.*: c5e0c060 ld1d \{z0\.d\}, p0/z, \[x3, z0\.d, lsl #3\]
--.*: c5e0c060 ld1d \{z0\.d\}, p0/z, \[x3, z0\.d, lsl #3\]
--.*: c5e0c3e0 ld1d \{z0\.d\}, p0/z, \[sp, z0\.d, lsl #3\]
--.*: c5e0c3e0 ld1d \{z0\.d\}, p0/z, \[sp, z0\.d, lsl #3\]
--.*: c5e4c000 ld1d \{z0\.d\}, p0/z, \[x0, z4\.d, lsl #3\]
--.*: c5e4c000 ld1d \{z0\.d\}, p0/z, \[x0, z4\.d, lsl #3\]
--.*: c5ffc000 ld1d \{z0\.d\}, p0/z, \[x0, z31\.d, lsl #3\]
--.*: c5ffc000 ld1d \{z0\.d\}, p0/z, \[x0, z31\.d, lsl #3\]
--.*: a5e0a000 ld1d \{z0\.d\}, p0/z, \[x0\]
--.*: a5e0a000 ld1d \{z0\.d\}, p0/z, \[x0\]
--.*: a5e0a000 ld1d \{z0\.d\}, p0/z, \[x0\]
--.*: a5e0a000 ld1d \{z0\.d\}, p0/z, \[x0\]
--.*: a5e0a000 ld1d \{z0\.d\}, p0/z, \[x0\]
--.*: a5e0a001 ld1d \{z1\.d\}, p0/z, \[x0\]
--.*: a5e0a001 ld1d \{z1\.d\}, p0/z, \[x0\]
--.*: a5e0a001 ld1d \{z1\.d\}, p0/z, \[x0\]
--.*: a5e0a001 ld1d \{z1\.d\}, p0/z, \[x0\]
--.*: a5e0a001 ld1d \{z1\.d\}, p0/z, \[x0\]
--.*: a5e0a01f ld1d \{z31\.d\}, p0/z, \[x0\]
--.*: a5e0a01f ld1d \{z31\.d\}, p0/z, \[x0\]
--.*: a5e0a01f ld1d \{z31\.d\}, p0/z, \[x0\]
--.*: a5e0a01f ld1d \{z31\.d\}, p0/z, \[x0\]
--.*: a5e0a01f ld1d \{z31\.d\}, p0/z, \[x0\]
--.*: a5e0a800 ld1d \{z0\.d\}, p2/z, \[x0\]
--.*: a5e0a800 ld1d \{z0\.d\}, p2/z, \[x0\]
--.*: a5e0a800 ld1d \{z0\.d\}, p2/z, \[x0\]
--.*: a5e0a800 ld1d \{z0\.d\}, p2/z, \[x0\]
--.*: a5e0bc00 ld1d \{z0\.d\}, p7/z, \[x0\]
--.*: a5e0bc00 ld1d \{z0\.d\}, p7/z, \[x0\]
--.*: a5e0bc00 ld1d \{z0\.d\}, p7/z, \[x0\]
--.*: a5e0bc00 ld1d \{z0\.d\}, p7/z, \[x0\]
--.*: a5e0a060 ld1d \{z0\.d\}, p0/z, \[x3\]
--.*: a5e0a060 ld1d \{z0\.d\}, p0/z, \[x3\]
--.*: a5e0a060 ld1d \{z0\.d\}, p0/z, \[x3\]
--.*: a5e0a060 ld1d \{z0\.d\}, p0/z, \[x3\]
--.*: a5e0a3e0 ld1d \{z0\.d\}, p0/z, \[sp\]
--.*: a5e0a3e0 ld1d \{z0\.d\}, p0/z, \[sp\]
--.*: a5e0a3e0 ld1d \{z0\.d\}, p0/z, \[sp\]
--.*: a5e0a3e0 ld1d \{z0\.d\}, p0/z, \[sp\]
--.*: a5e7a000 ld1d \{z0\.d\}, p0/z, \[x0, #7, mul vl\]
--.*: a5e7a000 ld1d \{z0\.d\}, p0/z, \[x0, #7, mul vl\]
--.*: a5e8a000 ld1d \{z0\.d\}, p0/z, \[x0, #-8, mul vl\]
--.*: a5e8a000 ld1d \{z0\.d\}, p0/z, \[x0, #-8, mul vl\]
--.*: a5e9a000 ld1d \{z0\.d\}, p0/z, \[x0, #-7, mul vl\]
--.*: a5e9a000 ld1d \{z0\.d\}, p0/z, \[x0, #-7, mul vl\]
--.*: a5efa000 ld1d \{z0\.d\}, p0/z, \[x0, #-1, mul vl\]
--.*: a5efa000 ld1d \{z0\.d\}, p0/z, \[x0, #-1, mul vl\]
--.*: c5a0c000 ld1d \{z0\.d\}, p0/z, \[z0\.d\]
--.*: c5a0c000 ld1d \{z0\.d\}, p0/z, \[z0\.d\]
--.*: c5a0c000 ld1d \{z0\.d\}, p0/z, \[z0\.d\]
--.*: c5a0c000 ld1d \{z0\.d\}, p0/z, \[z0\.d\]
--.*: c5a0c001 ld1d \{z1\.d\}, p0/z, \[z0\.d\]
--.*: c5a0c001 ld1d \{z1\.d\}, p0/z, \[z0\.d\]
--.*: c5a0c001 ld1d \{z1\.d\}, p0/z, \[z0\.d\]
--.*: c5a0c001 ld1d \{z1\.d\}, p0/z, \[z0\.d\]
--.*: c5a0c01f ld1d \{z31\.d\}, p0/z, \[z0\.d\]
--.*: c5a0c01f ld1d \{z31\.d\}, p0/z, \[z0\.d\]
--.*: c5a0c01f ld1d \{z31\.d\}, p0/z, \[z0\.d\]
--.*: c5a0c01f ld1d \{z31\.d\}, p0/z, \[z0\.d\]
--.*: c5a0c800 ld1d \{z0\.d\}, p2/z, \[z0\.d\]
--.*: c5a0c800 ld1d \{z0\.d\}, p2/z, \[z0\.d\]
--.*: c5a0c800 ld1d \{z0\.d\}, p2/z, \[z0\.d\]
--.*: c5a0dc00 ld1d \{z0\.d\}, p7/z, \[z0\.d\]
--.*: c5a0dc00 ld1d \{z0\.d\}, p7/z, \[z0\.d\]
--.*: c5a0dc00 ld1d \{z0\.d\}, p7/z, \[z0\.d\]
--.*: c5a0c060 ld1d \{z0\.d\}, p0/z, \[z3\.d\]
--.*: c5a0c060 ld1d \{z0\.d\}, p0/z, \[z3\.d\]
--.*: c5a0c060 ld1d \{z0\.d\}, p0/z, \[z3\.d\]
--.*: c5a0c3e0 ld1d \{z0\.d\}, p0/z, \[z31\.d\]
--.*: c5a0c3e0 ld1d \{z0\.d\}, p0/z, \[z31\.d\]
--.*: c5a0c3e0 ld1d \{z0\.d\}, p0/z, \[z31\.d\]
--.*: c5afc000 ld1d \{z0\.d\}, p0/z, \[z0\.d, #120\]
--.*: c5afc000 ld1d \{z0\.d\}, p0/z, \[z0\.d, #120\]
--.*: c5b0c000 ld1d \{z0\.d\}, p0/z, \[z0\.d, #128\]
--.*: c5b0c000 ld1d \{z0\.d\}, p0/z, \[z0\.d, #128\]
--.*: c5b1c000 ld1d \{z0\.d\}, p0/z, \[z0\.d, #136\]
--.*: c5b1c000 ld1d \{z0\.d\}, p0/z, \[z0\.d, #136\]
--.*: c5bfc000 ld1d \{z0\.d\}, p0/z, \[z0\.d, #248\]
--.*: c5bfc000 ld1d \{z0\.d\}, p0/z, \[z0\.d, #248\]
--.*: 84804000 ld1h \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 84804000 ld1h \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 84804000 ld1h \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 84804000 ld1h \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 84804001 ld1h \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 84804001 ld1h \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 84804001 ld1h \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 84804001 ld1h \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 8480401f ld1h \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 8480401f ld1h \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 8480401f ld1h \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 8480401f ld1h \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 84804800 ld1h \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\]
--.*: 84804800 ld1h \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\]
--.*: 84804800 ld1h \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\]
--.*: 84805c00 ld1h \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\]
--.*: 84805c00 ld1h \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\]
--.*: 84805c00 ld1h \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\]
--.*: 84804060 ld1h \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\]
--.*: 84804060 ld1h \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\]
--.*: 84804060 ld1h \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\]
--.*: 848043e0 ld1h \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\]
--.*: 848043e0 ld1h \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\]
--.*: 848043e0 ld1h \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\]
--.*: 84844000 ld1h \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\]
--.*: 84844000 ld1h \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\]
--.*: 84844000 ld1h \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\]
--.*: 849f4000 ld1h \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\]
--.*: 849f4000 ld1h \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\]
--.*: 849f4000 ld1h \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\]
--.*: 84c04000 ld1h \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 84c04000 ld1h \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 84c04000 ld1h \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 84c04000 ld1h \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 84c04001 ld1h \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 84c04001 ld1h \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 84c04001 ld1h \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 84c04001 ld1h \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 84c0401f ld1h \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 84c0401f ld1h \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 84c0401f ld1h \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 84c0401f ld1h \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 84c04800 ld1h \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\]
--.*: 84c04800 ld1h \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\]
--.*: 84c04800 ld1h \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\]
--.*: 84c05c00 ld1h \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\]
--.*: 84c05c00 ld1h \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\]
--.*: 84c05c00 ld1h \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\]
--.*: 84c04060 ld1h \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\]
--.*: 84c04060 ld1h \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\]
--.*: 84c04060 ld1h \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\]
--.*: 84c043e0 ld1h \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\]
--.*: 84c043e0 ld1h \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\]
--.*: 84c043e0 ld1h \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\]
--.*: 84c44000 ld1h \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\]
--.*: 84c44000 ld1h \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\]
--.*: 84c44000 ld1h \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\]
--.*: 84df4000 ld1h \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\]
--.*: 84df4000 ld1h \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\]
--.*: 84df4000 ld1h \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\]
--.*: 84a04000 ld1h \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw #1\]
--.*: 84a04000 ld1h \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw #1\]
--.*: 84a04000 ld1h \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw #1\]
--.*: 84a04001 ld1h \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw #1\]
--.*: 84a04001 ld1h \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw #1\]
--.*: 84a04001 ld1h \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw #1\]
--.*: 84a0401f ld1h \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw #1\]
--.*: 84a0401f ld1h \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw #1\]
--.*: 84a0401f ld1h \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw #1\]
--.*: 84a04800 ld1h \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw #1\]
--.*: 84a04800 ld1h \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw #1\]
--.*: 84a05c00 ld1h \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw #1\]
--.*: 84a05c00 ld1h \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw #1\]
--.*: 84a04060 ld1h \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw #1\]
--.*: 84a04060 ld1h \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw #1\]
--.*: 84a043e0 ld1h \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw #1\]
--.*: 84a043e0 ld1h \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw #1\]
--.*: 84a44000 ld1h \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw #1\]
--.*: 84a44000 ld1h \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw #1\]
--.*: 84bf4000 ld1h \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw #1\]
--.*: 84bf4000 ld1h \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw #1\]
--.*: 84e04000 ld1h \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw #1\]
--.*: 84e04000 ld1h \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw #1\]
--.*: 84e04000 ld1h \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw #1\]
--.*: 84e04001 ld1h \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw #1\]
--.*: 84e04001 ld1h \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw #1\]
--.*: 84e04001 ld1h \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw #1\]
--.*: 84e0401f ld1h \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw #1\]
--.*: 84e0401f ld1h \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw #1\]
--.*: 84e0401f ld1h \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw #1\]
--.*: 84e04800 ld1h \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw #1\]
--.*: 84e04800 ld1h \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw #1\]
--.*: 84e05c00 ld1h \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw #1\]
--.*: 84e05c00 ld1h \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw #1\]
--.*: 84e04060 ld1h \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw #1\]
--.*: 84e04060 ld1h \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw #1\]
--.*: 84e043e0 ld1h \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw #1\]
--.*: 84e043e0 ld1h \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw #1\]
--.*: 84e44000 ld1h \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw #1\]
--.*: 84e44000 ld1h \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw #1\]
--.*: 84ff4000 ld1h \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw #1\]
--.*: 84ff4000 ld1h \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw #1\]
--.*: a4a04000 ld1h \{z0\.h\}, p0/z, \[x0, x0, lsl #1\]
--.*: a4a04000 ld1h \{z0\.h\}, p0/z, \[x0, x0, lsl #1\]
--.*: a4a04000 ld1h \{z0\.h\}, p0/z, \[x0, x0, lsl #1\]
--.*: a4a04001 ld1h \{z1\.h\}, p0/z, \[x0, x0, lsl #1\]
--.*: a4a04001 ld1h \{z1\.h\}, p0/z, \[x0, x0, lsl #1\]
--.*: a4a04001 ld1h \{z1\.h\}, p0/z, \[x0, x0, lsl #1\]
--.*: a4a0401f ld1h \{z31\.h\}, p0/z, \[x0, x0, lsl #1\]
--.*: a4a0401f ld1h \{z31\.h\}, p0/z, \[x0, x0, lsl #1\]
--.*: a4a0401f ld1h \{z31\.h\}, p0/z, \[x0, x0, lsl #1\]
--.*: a4a04800 ld1h \{z0\.h\}, p2/z, \[x0, x0, lsl #1\]
--.*: a4a04800 ld1h \{z0\.h\}, p2/z, \[x0, x0, lsl #1\]
--.*: a4a05c00 ld1h \{z0\.h\}, p7/z, \[x0, x0, lsl #1\]
--.*: a4a05c00 ld1h \{z0\.h\}, p7/z, \[x0, x0, lsl #1\]
--.*: a4a04060 ld1h \{z0\.h\}, p0/z, \[x3, x0, lsl #1\]
--.*: a4a04060 ld1h \{z0\.h\}, p0/z, \[x3, x0, lsl #1\]
--.*: a4a043e0 ld1h \{z0\.h\}, p0/z, \[sp, x0, lsl #1\]
--.*: a4a043e0 ld1h \{z0\.h\}, p0/z, \[sp, x0, lsl #1\]
--.*: a4a44000 ld1h \{z0\.h\}, p0/z, \[x0, x4, lsl #1\]
--.*: a4a44000 ld1h \{z0\.h\}, p0/z, \[x0, x4, lsl #1\]
--.*: a4be4000 ld1h \{z0\.h\}, p0/z, \[x0, x30, lsl #1\]
--.*: a4be4000 ld1h \{z0\.h\}, p0/z, \[x0, x30, lsl #1\]
--.*: a4c04000 ld1h \{z0\.s\}, p0/z, \[x0, x0, lsl #1\]
--.*: a4c04000 ld1h \{z0\.s\}, p0/z, \[x0, x0, lsl #1\]
--.*: a4c04000 ld1h \{z0\.s\}, p0/z, \[x0, x0, lsl #1\]
--.*: a4c04001 ld1h \{z1\.s\}, p0/z, \[x0, x0, lsl #1\]
--.*: a4c04001 ld1h \{z1\.s\}, p0/z, \[x0, x0, lsl #1\]
--.*: a4c04001 ld1h \{z1\.s\}, p0/z, \[x0, x0, lsl #1\]
--.*: a4c0401f ld1h \{z31\.s\}, p0/z, \[x0, x0, lsl #1\]
--.*: a4c0401f ld1h \{z31\.s\}, p0/z, \[x0, x0, lsl #1\]
--.*: a4c0401f ld1h \{z31\.s\}, p0/z, \[x0, x0, lsl #1\]
--.*: a4c04800 ld1h \{z0\.s\}, p2/z, \[x0, x0, lsl #1\]
--.*: a4c04800 ld1h \{z0\.s\}, p2/z, \[x0, x0, lsl #1\]
--.*: a4c05c00 ld1h \{z0\.s\}, p7/z, \[x0, x0, lsl #1\]
--.*: a4c05c00 ld1h \{z0\.s\}, p7/z, \[x0, x0, lsl #1\]
--.*: a4c04060 ld1h \{z0\.s\}, p0/z, \[x3, x0, lsl #1\]
--.*: a4c04060 ld1h \{z0\.s\}, p0/z, \[x3, x0, lsl #1\]
--.*: a4c043e0 ld1h \{z0\.s\}, p0/z, \[sp, x0, lsl #1\]
--.*: a4c043e0 ld1h \{z0\.s\}, p0/z, \[sp, x0, lsl #1\]
--.*: a4c44000 ld1h \{z0\.s\}, p0/z, \[x0, x4, lsl #1\]
--.*: a4c44000 ld1h \{z0\.s\}, p0/z, \[x0, x4, lsl #1\]
--.*: a4de4000 ld1h \{z0\.s\}, p0/z, \[x0, x30, lsl #1\]
--.*: a4de4000 ld1h \{z0\.s\}, p0/z, \[x0, x30, lsl #1\]
--.*: a4e04000 ld1h \{z0\.d\}, p0/z, \[x0, x0, lsl #1\]
--.*: a4e04000 ld1h \{z0\.d\}, p0/z, \[x0, x0, lsl #1\]
--.*: a4e04000 ld1h \{z0\.d\}, p0/z, \[x0, x0, lsl #1\]
--.*: a4e04001 ld1h \{z1\.d\}, p0/z, \[x0, x0, lsl #1\]
--.*: a4e04001 ld1h \{z1\.d\}, p0/z, \[x0, x0, lsl #1\]
--.*: a4e04001 ld1h \{z1\.d\}, p0/z, \[x0, x0, lsl #1\]
--.*: a4e0401f ld1h \{z31\.d\}, p0/z, \[x0, x0, lsl #1\]
--.*: a4e0401f ld1h \{z31\.d\}, p0/z, \[x0, x0, lsl #1\]
--.*: a4e0401f ld1h \{z31\.d\}, p0/z, \[x0, x0, lsl #1\]
--.*: a4e04800 ld1h \{z0\.d\}, p2/z, \[x0, x0, lsl #1\]
--.*: a4e04800 ld1h \{z0\.d\}, p2/z, \[x0, x0, lsl #1\]
--.*: a4e05c00 ld1h \{z0\.d\}, p7/z, \[x0, x0, lsl #1\]
--.*: a4e05c00 ld1h \{z0\.d\}, p7/z, \[x0, x0, lsl #1\]
--.*: a4e04060 ld1h \{z0\.d\}, p0/z, \[x3, x0, lsl #1\]
--.*: a4e04060 ld1h \{z0\.d\}, p0/z, \[x3, x0, lsl #1\]
--.*: a4e043e0 ld1h \{z0\.d\}, p0/z, \[sp, x0, lsl #1\]
--.*: a4e043e0 ld1h \{z0\.d\}, p0/z, \[sp, x0, lsl #1\]
--.*: a4e44000 ld1h \{z0\.d\}, p0/z, \[x0, x4, lsl #1\]
--.*: a4e44000 ld1h \{z0\.d\}, p0/z, \[x0, x4, lsl #1\]
--.*: a4fe4000 ld1h \{z0\.d\}, p0/z, \[x0, x30, lsl #1\]
--.*: a4fe4000 ld1h \{z0\.d\}, p0/z, \[x0, x30, lsl #1\]
--.*: c4804000 ld1h \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c4804000 ld1h \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c4804000 ld1h \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c4804000 ld1h \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c4804001 ld1h \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c4804001 ld1h \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c4804001 ld1h \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c4804001 ld1h \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c480401f ld1h \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c480401f ld1h \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c480401f ld1h \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c480401f ld1h \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c4804800 ld1h \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\]
--.*: c4804800 ld1h \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\]
--.*: c4804800 ld1h \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\]
--.*: c4805c00 ld1h \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\]
--.*: c4805c00 ld1h \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\]
--.*: c4805c00 ld1h \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\]
--.*: c4804060 ld1h \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\]
--.*: c4804060 ld1h \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\]
--.*: c4804060 ld1h \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\]
--.*: c48043e0 ld1h \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\]
--.*: c48043e0 ld1h \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\]
--.*: c48043e0 ld1h \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\]
--.*: c4844000 ld1h \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\]
--.*: c4844000 ld1h \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\]
--.*: c4844000 ld1h \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\]
--.*: c49f4000 ld1h \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\]
--.*: c49f4000 ld1h \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\]
--.*: c49f4000 ld1h \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\]
--.*: c4c04000 ld1h \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c4c04000 ld1h \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c4c04000 ld1h \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c4c04000 ld1h \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c4c04001 ld1h \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c4c04001 ld1h \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c4c04001 ld1h \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c4c04001 ld1h \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c4c0401f ld1h \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c4c0401f ld1h \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c4c0401f ld1h \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c4c0401f ld1h \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c4c04800 ld1h \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\]
--.*: c4c04800 ld1h \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\]
--.*: c4c04800 ld1h \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\]
--.*: c4c05c00 ld1h \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\]
--.*: c4c05c00 ld1h \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\]
--.*: c4c05c00 ld1h \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\]
--.*: c4c04060 ld1h \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\]
--.*: c4c04060 ld1h \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\]
--.*: c4c04060 ld1h \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\]
--.*: c4c043e0 ld1h \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\]
--.*: c4c043e0 ld1h \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\]
--.*: c4c043e0 ld1h \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\]
--.*: c4c44000 ld1h \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\]
--.*: c4c44000 ld1h \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\]
--.*: c4c44000 ld1h \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\]
--.*: c4df4000 ld1h \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\]
--.*: c4df4000 ld1h \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\]
--.*: c4df4000 ld1h \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\]
--.*: c4a04000 ld1h \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #1\]
--.*: c4a04000 ld1h \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #1\]
--.*: c4a04000 ld1h \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #1\]
--.*: c4a04001 ld1h \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #1\]
--.*: c4a04001 ld1h \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #1\]
--.*: c4a04001 ld1h \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #1\]
--.*: c4a0401f ld1h \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #1\]
--.*: c4a0401f ld1h \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #1\]
--.*: c4a0401f ld1h \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #1\]
--.*: c4a04800 ld1h \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw #1\]
--.*: c4a04800 ld1h \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw #1\]
--.*: c4a05c00 ld1h \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw #1\]
--.*: c4a05c00 ld1h \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw #1\]
--.*: c4a04060 ld1h \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw #1\]
--.*: c4a04060 ld1h \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw #1\]
--.*: c4a043e0 ld1h \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw #1\]
--.*: c4a043e0 ld1h \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw #1\]
--.*: c4a44000 ld1h \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw #1\]
--.*: c4a44000 ld1h \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw #1\]
--.*: c4bf4000 ld1h \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw #1\]
--.*: c4bf4000 ld1h \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw #1\]
--.*: c4e04000 ld1h \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #1\]
--.*: c4e04000 ld1h \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #1\]
--.*: c4e04000 ld1h \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #1\]
--.*: c4e04001 ld1h \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #1\]
--.*: c4e04001 ld1h \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #1\]
--.*: c4e04001 ld1h \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #1\]
--.*: c4e0401f ld1h \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #1\]
--.*: c4e0401f ld1h \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #1\]
--.*: c4e0401f ld1h \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #1\]
--.*: c4e04800 ld1h \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw #1\]
--.*: c4e04800 ld1h \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw #1\]
--.*: c4e05c00 ld1h \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw #1\]
--.*: c4e05c00 ld1h \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw #1\]
--.*: c4e04060 ld1h \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw #1\]
--.*: c4e04060 ld1h \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw #1\]
--.*: c4e043e0 ld1h \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw #1\]
--.*: c4e043e0 ld1h \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw #1\]
--.*: c4e44000 ld1h \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw #1\]
--.*: c4e44000 ld1h \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw #1\]
--.*: c4ff4000 ld1h \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw #1\]
--.*: c4ff4000 ld1h \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw #1\]
--.*: c4c0c000 ld1h \{z0\.d\}, p0/z, \[x0, z0\.d\]
--.*: c4c0c000 ld1h \{z0\.d\}, p0/z, \[x0, z0\.d\]
--.*: c4c0c000 ld1h \{z0\.d\}, p0/z, \[x0, z0\.d\]
--.*: c4c0c000 ld1h \{z0\.d\}, p0/z, \[x0, z0\.d\]
--.*: c4c0c001 ld1h \{z1\.d\}, p0/z, \[x0, z0\.d\]
--.*: c4c0c001 ld1h \{z1\.d\}, p0/z, \[x0, z0\.d\]
--.*: c4c0c001 ld1h \{z1\.d\}, p0/z, \[x0, z0\.d\]
--.*: c4c0c001 ld1h \{z1\.d\}, p0/z, \[x0, z0\.d\]
--.*: c4c0c01f ld1h \{z31\.d\}, p0/z, \[x0, z0\.d\]
--.*: c4c0c01f ld1h \{z31\.d\}, p0/z, \[x0, z0\.d\]
--.*: c4c0c01f ld1h \{z31\.d\}, p0/z, \[x0, z0\.d\]
--.*: c4c0c01f ld1h \{z31\.d\}, p0/z, \[x0, z0\.d\]
--.*: c4c0c800 ld1h \{z0\.d\}, p2/z, \[x0, z0\.d\]
--.*: c4c0c800 ld1h \{z0\.d\}, p2/z, \[x0, z0\.d\]
--.*: c4c0c800 ld1h \{z0\.d\}, p2/z, \[x0, z0\.d\]
--.*: c4c0dc00 ld1h \{z0\.d\}, p7/z, \[x0, z0\.d\]
--.*: c4c0dc00 ld1h \{z0\.d\}, p7/z, \[x0, z0\.d\]
--.*: c4c0dc00 ld1h \{z0\.d\}, p7/z, \[x0, z0\.d\]
--.*: c4c0c060 ld1h \{z0\.d\}, p0/z, \[x3, z0\.d\]
--.*: c4c0c060 ld1h \{z0\.d\}, p0/z, \[x3, z0\.d\]
--.*: c4c0c060 ld1h \{z0\.d\}, p0/z, \[x3, z0\.d\]
--.*: c4c0c3e0 ld1h \{z0\.d\}, p0/z, \[sp, z0\.d\]
--.*: c4c0c3e0 ld1h \{z0\.d\}, p0/z, \[sp, z0\.d\]
--.*: c4c0c3e0 ld1h \{z0\.d\}, p0/z, \[sp, z0\.d\]
--.*: c4c4c000 ld1h \{z0\.d\}, p0/z, \[x0, z4\.d\]
--.*: c4c4c000 ld1h \{z0\.d\}, p0/z, \[x0, z4\.d\]
--.*: c4c4c000 ld1h \{z0\.d\}, p0/z, \[x0, z4\.d\]
--.*: c4dfc000 ld1h \{z0\.d\}, p0/z, \[x0, z31\.d\]
--.*: c4dfc000 ld1h \{z0\.d\}, p0/z, \[x0, z31\.d\]
--.*: c4dfc000 ld1h \{z0\.d\}, p0/z, \[x0, z31\.d\]
--.*: c4e0c000 ld1h \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #1\]
--.*: c4e0c000 ld1h \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #1\]
--.*: c4e0c000 ld1h \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #1\]
--.*: c4e0c001 ld1h \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #1\]
--.*: c4e0c001 ld1h \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #1\]
--.*: c4e0c001 ld1h \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #1\]
--.*: c4e0c01f ld1h \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #1\]
--.*: c4e0c01f ld1h \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #1\]
--.*: c4e0c01f ld1h \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #1\]
--.*: c4e0c800 ld1h \{z0\.d\}, p2/z, \[x0, z0\.d, lsl #1\]
--.*: c4e0c800 ld1h \{z0\.d\}, p2/z, \[x0, z0\.d, lsl #1\]
--.*: c4e0dc00 ld1h \{z0\.d\}, p7/z, \[x0, z0\.d, lsl #1\]
--.*: c4e0dc00 ld1h \{z0\.d\}, p7/z, \[x0, z0\.d, lsl #1\]
--.*: c4e0c060 ld1h \{z0\.d\}, p0/z, \[x3, z0\.d, lsl #1\]
--.*: c4e0c060 ld1h \{z0\.d\}, p0/z, \[x3, z0\.d, lsl #1\]
--.*: c4e0c3e0 ld1h \{z0\.d\}, p0/z, \[sp, z0\.d, lsl #1\]
--.*: c4e0c3e0 ld1h \{z0\.d\}, p0/z, \[sp, z0\.d, lsl #1\]
--.*: c4e4c000 ld1h \{z0\.d\}, p0/z, \[x0, z4\.d, lsl #1\]
--.*: c4e4c000 ld1h \{z0\.d\}, p0/z, \[x0, z4\.d, lsl #1\]
--.*: c4ffc000 ld1h \{z0\.d\}, p0/z, \[x0, z31\.d, lsl #1\]
--.*: c4ffc000 ld1h \{z0\.d\}, p0/z, \[x0, z31\.d, lsl #1\]
--.*: 84a0c000 ld1h \{z0\.s\}, p0/z, \[z0\.s\]
--.*: 84a0c000 ld1h \{z0\.s\}, p0/z, \[z0\.s\]
--.*: 84a0c000 ld1h \{z0\.s\}, p0/z, \[z0\.s\]
--.*: 84a0c000 ld1h \{z0\.s\}, p0/z, \[z0\.s\]
--.*: 84a0c001 ld1h \{z1\.s\}, p0/z, \[z0\.s\]
--.*: 84a0c001 ld1h \{z1\.s\}, p0/z, \[z0\.s\]
--.*: 84a0c001 ld1h \{z1\.s\}, p0/z, \[z0\.s\]
--.*: 84a0c001 ld1h \{z1\.s\}, p0/z, \[z0\.s\]
--.*: 84a0c01f ld1h \{z31\.s\}, p0/z, \[z0\.s\]
--.*: 84a0c01f ld1h \{z31\.s\}, p0/z, \[z0\.s\]
--.*: 84a0c01f ld1h \{z31\.s\}, p0/z, \[z0\.s\]
--.*: 84a0c01f ld1h \{z31\.s\}, p0/z, \[z0\.s\]
--.*: 84a0c800 ld1h \{z0\.s\}, p2/z, \[z0\.s\]
--.*: 84a0c800 ld1h \{z0\.s\}, p2/z, \[z0\.s\]
--.*: 84a0c800 ld1h \{z0\.s\}, p2/z, \[z0\.s\]
--.*: 84a0dc00 ld1h \{z0\.s\}, p7/z, \[z0\.s\]
--.*: 84a0dc00 ld1h \{z0\.s\}, p7/z, \[z0\.s\]
--.*: 84a0dc00 ld1h \{z0\.s\}, p7/z, \[z0\.s\]
--.*: 84a0c060 ld1h \{z0\.s\}, p0/z, \[z3\.s\]
--.*: 84a0c060 ld1h \{z0\.s\}, p0/z, \[z3\.s\]
--.*: 84a0c060 ld1h \{z0\.s\}, p0/z, \[z3\.s\]
--.*: 84a0c3e0 ld1h \{z0\.s\}, p0/z, \[z31\.s\]
--.*: 84a0c3e0 ld1h \{z0\.s\}, p0/z, \[z31\.s\]
--.*: 84a0c3e0 ld1h \{z0\.s\}, p0/z, \[z31\.s\]
--.*: 84afc000 ld1h \{z0\.s\}, p0/z, \[z0\.s, #30\]
--.*: 84afc000 ld1h \{z0\.s\}, p0/z, \[z0\.s, #30\]
--.*: 84b0c000 ld1h \{z0\.s\}, p0/z, \[z0\.s, #32\]
--.*: 84b0c000 ld1h \{z0\.s\}, p0/z, \[z0\.s, #32\]
--.*: 84b1c000 ld1h \{z0\.s\}, p0/z, \[z0\.s, #34\]
--.*: 84b1c000 ld1h \{z0\.s\}, p0/z, \[z0\.s, #34\]
--.*: 84bfc000 ld1h \{z0\.s\}, p0/z, \[z0\.s, #62\]
--.*: 84bfc000 ld1h \{z0\.s\}, p0/z, \[z0\.s, #62\]
--.*: a4a0a000 ld1h \{z0\.h\}, p0/z, \[x0\]
--.*: a4a0a000 ld1h \{z0\.h\}, p0/z, \[x0\]
--.*: a4a0a000 ld1h \{z0\.h\}, p0/z, \[x0\]
--.*: a4a0a000 ld1h \{z0\.h\}, p0/z, \[x0\]
--.*: a4a0a000 ld1h \{z0\.h\}, p0/z, \[x0\]
--.*: a4a0a001 ld1h \{z1\.h\}, p0/z, \[x0\]
--.*: a4a0a001 ld1h \{z1\.h\}, p0/z, \[x0\]
--.*: a4a0a001 ld1h \{z1\.h\}, p0/z, \[x0\]
--.*: a4a0a001 ld1h \{z1\.h\}, p0/z, \[x0\]
--.*: a4a0a001 ld1h \{z1\.h\}, p0/z, \[x0\]
--.*: a4a0a01f ld1h \{z31\.h\}, p0/z, \[x0\]
--.*: a4a0a01f ld1h \{z31\.h\}, p0/z, \[x0\]
--.*: a4a0a01f ld1h \{z31\.h\}, p0/z, \[x0\]
--.*: a4a0a01f ld1h \{z31\.h\}, p0/z, \[x0\]
--.*: a4a0a01f ld1h \{z31\.h\}, p0/z, \[x0\]
--.*: a4a0a800 ld1h \{z0\.h\}, p2/z, \[x0\]
--.*: a4a0a800 ld1h \{z0\.h\}, p2/z, \[x0\]
--.*: a4a0a800 ld1h \{z0\.h\}, p2/z, \[x0\]
--.*: a4a0a800 ld1h \{z0\.h\}, p2/z, \[x0\]
--.*: a4a0bc00 ld1h \{z0\.h\}, p7/z, \[x0\]
--.*: a4a0bc00 ld1h \{z0\.h\}, p7/z, \[x0\]
--.*: a4a0bc00 ld1h \{z0\.h\}, p7/z, \[x0\]
--.*: a4a0bc00 ld1h \{z0\.h\}, p7/z, \[x0\]
--.*: a4a0a060 ld1h \{z0\.h\}, p0/z, \[x3\]
--.*: a4a0a060 ld1h \{z0\.h\}, p0/z, \[x3\]
--.*: a4a0a060 ld1h \{z0\.h\}, p0/z, \[x3\]
--.*: a4a0a060 ld1h \{z0\.h\}, p0/z, \[x3\]
--.*: a4a0a3e0 ld1h \{z0\.h\}, p0/z, \[sp\]
--.*: a4a0a3e0 ld1h \{z0\.h\}, p0/z, \[sp\]
--.*: a4a0a3e0 ld1h \{z0\.h\}, p0/z, \[sp\]
--.*: a4a0a3e0 ld1h \{z0\.h\}, p0/z, \[sp\]
--.*: a4a7a000 ld1h \{z0\.h\}, p0/z, \[x0, #7, mul vl\]
--.*: a4a7a000 ld1h \{z0\.h\}, p0/z, \[x0, #7, mul vl\]
--.*: a4a8a000 ld1h \{z0\.h\}, p0/z, \[x0, #-8, mul vl\]
--.*: a4a8a000 ld1h \{z0\.h\}, p0/z, \[x0, #-8, mul vl\]
--.*: a4a9a000 ld1h \{z0\.h\}, p0/z, \[x0, #-7, mul vl\]
--.*: a4a9a000 ld1h \{z0\.h\}, p0/z, \[x0, #-7, mul vl\]
--.*: a4afa000 ld1h \{z0\.h\}, p0/z, \[x0, #-1, mul vl\]
--.*: a4afa000 ld1h \{z0\.h\}, p0/z, \[x0, #-1, mul vl\]
--.*: a4c0a000 ld1h \{z0\.s\}, p0/z, \[x0\]
--.*: a4c0a000 ld1h \{z0\.s\}, p0/z, \[x0\]
--.*: a4c0a000 ld1h \{z0\.s\}, p0/z, \[x0\]
--.*: a4c0a000 ld1h \{z0\.s\}, p0/z, \[x0\]
--.*: a4c0a000 ld1h \{z0\.s\}, p0/z, \[x0\]
--.*: a4c0a001 ld1h \{z1\.s\}, p0/z, \[x0\]
--.*: a4c0a001 ld1h \{z1\.s\}, p0/z, \[x0\]
--.*: a4c0a001 ld1h \{z1\.s\}, p0/z, \[x0\]
--.*: a4c0a001 ld1h \{z1\.s\}, p0/z, \[x0\]
--.*: a4c0a001 ld1h \{z1\.s\}, p0/z, \[x0\]
--.*: a4c0a01f ld1h \{z31\.s\}, p0/z, \[x0\]
--.*: a4c0a01f ld1h \{z31\.s\}, p0/z, \[x0\]
--.*: a4c0a01f ld1h \{z31\.s\}, p0/z, \[x0\]
--.*: a4c0a01f ld1h \{z31\.s\}, p0/z, \[x0\]
--.*: a4c0a01f ld1h \{z31\.s\}, p0/z, \[x0\]
--.*: a4c0a800 ld1h \{z0\.s\}, p2/z, \[x0\]
--.*: a4c0a800 ld1h \{z0\.s\}, p2/z, \[x0\]
--.*: a4c0a800 ld1h \{z0\.s\}, p2/z, \[x0\]
--.*: a4c0a800 ld1h \{z0\.s\}, p2/z, \[x0\]
--.*: a4c0bc00 ld1h \{z0\.s\}, p7/z, \[x0\]
--.*: a4c0bc00 ld1h \{z0\.s\}, p7/z, \[x0\]
--.*: a4c0bc00 ld1h \{z0\.s\}, p7/z, \[x0\]
--.*: a4c0bc00 ld1h \{z0\.s\}, p7/z, \[x0\]
--.*: a4c0a060 ld1h \{z0\.s\}, p0/z, \[x3\]
--.*: a4c0a060 ld1h \{z0\.s\}, p0/z, \[x3\]
--.*: a4c0a060 ld1h \{z0\.s\}, p0/z, \[x3\]
--.*: a4c0a060 ld1h \{z0\.s\}, p0/z, \[x3\]
--.*: a4c0a3e0 ld1h \{z0\.s\}, p0/z, \[sp\]
--.*: a4c0a3e0 ld1h \{z0\.s\}, p0/z, \[sp\]
--.*: a4c0a3e0 ld1h \{z0\.s\}, p0/z, \[sp\]
--.*: a4c0a3e0 ld1h \{z0\.s\}, p0/z, \[sp\]
--.*: a4c7a000 ld1h \{z0\.s\}, p0/z, \[x0, #7, mul vl\]
--.*: a4c7a000 ld1h \{z0\.s\}, p0/z, \[x0, #7, mul vl\]
--.*: a4c8a000 ld1h \{z0\.s\}, p0/z, \[x0, #-8, mul vl\]
--.*: a4c8a000 ld1h \{z0\.s\}, p0/z, \[x0, #-8, mul vl\]
--.*: a4c9a000 ld1h \{z0\.s\}, p0/z, \[x0, #-7, mul vl\]
--.*: a4c9a000 ld1h \{z0\.s\}, p0/z, \[x0, #-7, mul vl\]
--.*: a4cfa000 ld1h \{z0\.s\}, p0/z, \[x0, #-1, mul vl\]
--.*: a4cfa000 ld1h \{z0\.s\}, p0/z, \[x0, #-1, mul vl\]
--.*: a4e0a000 ld1h \{z0\.d\}, p0/z, \[x0\]
--.*: a4e0a000 ld1h \{z0\.d\}, p0/z, \[x0\]
--.*: a4e0a000 ld1h \{z0\.d\}, p0/z, \[x0\]
--.*: a4e0a000 ld1h \{z0\.d\}, p0/z, \[x0\]
--.*: a4e0a000 ld1h \{z0\.d\}, p0/z, \[x0\]
--.*: a4e0a001 ld1h \{z1\.d\}, p0/z, \[x0\]
--.*: a4e0a001 ld1h \{z1\.d\}, p0/z, \[x0\]
--.*: a4e0a001 ld1h \{z1\.d\}, p0/z, \[x0\]
--.*: a4e0a001 ld1h \{z1\.d\}, p0/z, \[x0\]
--.*: a4e0a001 ld1h \{z1\.d\}, p0/z, \[x0\]
--.*: a4e0a01f ld1h \{z31\.d\}, p0/z, \[x0\]
--.*: a4e0a01f ld1h \{z31\.d\}, p0/z, \[x0\]
--.*: a4e0a01f ld1h \{z31\.d\}, p0/z, \[x0\]
--.*: a4e0a01f ld1h \{z31\.d\}, p0/z, \[x0\]
--.*: a4e0a01f ld1h \{z31\.d\}, p0/z, \[x0\]
--.*: a4e0a800 ld1h \{z0\.d\}, p2/z, \[x0\]
--.*: a4e0a800 ld1h \{z0\.d\}, p2/z, \[x0\]
--.*: a4e0a800 ld1h \{z0\.d\}, p2/z, \[x0\]
--.*: a4e0a800 ld1h \{z0\.d\}, p2/z, \[x0\]
--.*: a4e0bc00 ld1h \{z0\.d\}, p7/z, \[x0\]
--.*: a4e0bc00 ld1h \{z0\.d\}, p7/z, \[x0\]
--.*: a4e0bc00 ld1h \{z0\.d\}, p7/z, \[x0\]
--.*: a4e0bc00 ld1h \{z0\.d\}, p7/z, \[x0\]
--.*: a4e0a060 ld1h \{z0\.d\}, p0/z, \[x3\]
--.*: a4e0a060 ld1h \{z0\.d\}, p0/z, \[x3\]
--.*: a4e0a060 ld1h \{z0\.d\}, p0/z, \[x3\]
--.*: a4e0a060 ld1h \{z0\.d\}, p0/z, \[x3\]
--.*: a4e0a3e0 ld1h \{z0\.d\}, p0/z, \[sp\]
--.*: a4e0a3e0 ld1h \{z0\.d\}, p0/z, \[sp\]
--.*: a4e0a3e0 ld1h \{z0\.d\}, p0/z, \[sp\]
--.*: a4e0a3e0 ld1h \{z0\.d\}, p0/z, \[sp\]
--.*: a4e7a000 ld1h \{z0\.d\}, p0/z, \[x0, #7, mul vl\]
--.*: a4e7a000 ld1h \{z0\.d\}, p0/z, \[x0, #7, mul vl\]
--.*: a4e8a000 ld1h \{z0\.d\}, p0/z, \[x0, #-8, mul vl\]
--.*: a4e8a000 ld1h \{z0\.d\}, p0/z, \[x0, #-8, mul vl\]
--.*: a4e9a000 ld1h \{z0\.d\}, p0/z, \[x0, #-7, mul vl\]
--.*: a4e9a000 ld1h \{z0\.d\}, p0/z, \[x0, #-7, mul vl\]
--.*: a4efa000 ld1h \{z0\.d\}, p0/z, \[x0, #-1, mul vl\]
--.*: a4efa000 ld1h \{z0\.d\}, p0/z, \[x0, #-1, mul vl\]
--.*: c4a0c000 ld1h \{z0\.d\}, p0/z, \[z0\.d\]
--.*: c4a0c000 ld1h \{z0\.d\}, p0/z, \[z0\.d\]
--.*: c4a0c000 ld1h \{z0\.d\}, p0/z, \[z0\.d\]
--.*: c4a0c000 ld1h \{z0\.d\}, p0/z, \[z0\.d\]
--.*: c4a0c001 ld1h \{z1\.d\}, p0/z, \[z0\.d\]
--.*: c4a0c001 ld1h \{z1\.d\}, p0/z, \[z0\.d\]
--.*: c4a0c001 ld1h \{z1\.d\}, p0/z, \[z0\.d\]
--.*: c4a0c001 ld1h \{z1\.d\}, p0/z, \[z0\.d\]
--.*: c4a0c01f ld1h \{z31\.d\}, p0/z, \[z0\.d\]
--.*: c4a0c01f ld1h \{z31\.d\}, p0/z, \[z0\.d\]
--.*: c4a0c01f ld1h \{z31\.d\}, p0/z, \[z0\.d\]
--.*: c4a0c01f ld1h \{z31\.d\}, p0/z, \[z0\.d\]
--.*: c4a0c800 ld1h \{z0\.d\}, p2/z, \[z0\.d\]
--.*: c4a0c800 ld1h \{z0\.d\}, p2/z, \[z0\.d\]
--.*: c4a0c800 ld1h \{z0\.d\}, p2/z, \[z0\.d\]
--.*: c4a0dc00 ld1h \{z0\.d\}, p7/z, \[z0\.d\]
--.*: c4a0dc00 ld1h \{z0\.d\}, p7/z, \[z0\.d\]
--.*: c4a0dc00 ld1h \{z0\.d\}, p7/z, \[z0\.d\]
--.*: c4a0c060 ld1h \{z0\.d\}, p0/z, \[z3\.d\]
--.*: c4a0c060 ld1h \{z0\.d\}, p0/z, \[z3\.d\]
--.*: c4a0c060 ld1h \{z0\.d\}, p0/z, \[z3\.d\]
--.*: c4a0c3e0 ld1h \{z0\.d\}, p0/z, \[z31\.d\]
--.*: c4a0c3e0 ld1h \{z0\.d\}, p0/z, \[z31\.d\]
--.*: c4a0c3e0 ld1h \{z0\.d\}, p0/z, \[z31\.d\]
--.*: c4afc000 ld1h \{z0\.d\}, p0/z, \[z0\.d, #30\]
--.*: c4afc000 ld1h \{z0\.d\}, p0/z, \[z0\.d, #30\]
--.*: c4b0c000 ld1h \{z0\.d\}, p0/z, \[z0\.d, #32\]
--.*: c4b0c000 ld1h \{z0\.d\}, p0/z, \[z0\.d, #32\]
--.*: c4b1c000 ld1h \{z0\.d\}, p0/z, \[z0\.d, #34\]
--.*: c4b1c000 ld1h \{z0\.d\}, p0/z, \[z0\.d, #34\]
--.*: c4bfc000 ld1h \{z0\.d\}, p0/z, \[z0\.d, #62\]
--.*: c4bfc000 ld1h \{z0\.d\}, p0/z, \[z0\.d, #62\]
--.*: 84408000 ld1rb \{z0\.b\}, p0/z, \[x0\]
--.*: 84408000 ld1rb \{z0\.b\}, p0/z, \[x0\]
--.*: 84408000 ld1rb \{z0\.b\}, p0/z, \[x0\]
--.*: 84408000 ld1rb \{z0\.b\}, p0/z, \[x0\]
--.*: 84408001 ld1rb \{z1\.b\}, p0/z, \[x0\]
--.*: 84408001 ld1rb \{z1\.b\}, p0/z, \[x0\]
--.*: 84408001 ld1rb \{z1\.b\}, p0/z, \[x0\]
--.*: 84408001 ld1rb \{z1\.b\}, p0/z, \[x0\]
--.*: 8440801f ld1rb \{z31\.b\}, p0/z, \[x0\]
--.*: 8440801f ld1rb \{z31\.b\}, p0/z, \[x0\]
--.*: 8440801f ld1rb \{z31\.b\}, p0/z, \[x0\]
--.*: 8440801f ld1rb \{z31\.b\}, p0/z, \[x0\]
--.*: 84408800 ld1rb \{z0\.b\}, p2/z, \[x0\]
--.*: 84408800 ld1rb \{z0\.b\}, p2/z, \[x0\]
--.*: 84408800 ld1rb \{z0\.b\}, p2/z, \[x0\]
--.*: 84409c00 ld1rb \{z0\.b\}, p7/z, \[x0\]
--.*: 84409c00 ld1rb \{z0\.b\}, p7/z, \[x0\]
--.*: 84409c00 ld1rb \{z0\.b\}, p7/z, \[x0\]
--.*: 84408060 ld1rb \{z0\.b\}, p0/z, \[x3\]
--.*: 84408060 ld1rb \{z0\.b\}, p0/z, \[x3\]
--.*: 84408060 ld1rb \{z0\.b\}, p0/z, \[x3\]
--.*: 844083e0 ld1rb \{z0\.b\}, p0/z, \[sp\]
--.*: 844083e0 ld1rb \{z0\.b\}, p0/z, \[sp\]
--.*: 844083e0 ld1rb \{z0\.b\}, p0/z, \[sp\]
--.*: 845f8000 ld1rb \{z0\.b\}, p0/z, \[x0, #31\]
--.*: 845f8000 ld1rb \{z0\.b\}, p0/z, \[x0, #31\]
--.*: 84608000 ld1rb \{z0\.b\}, p0/z, \[x0, #32\]
--.*: 84608000 ld1rb \{z0\.b\}, p0/z, \[x0, #32\]
--.*: 84618000 ld1rb \{z0\.b\}, p0/z, \[x0, #33\]
--.*: 84618000 ld1rb \{z0\.b\}, p0/z, \[x0, #33\]
--.*: 847f8000 ld1rb \{z0\.b\}, p0/z, \[x0, #63\]
--.*: 847f8000 ld1rb \{z0\.b\}, p0/z, \[x0, #63\]
--.*: 8440a000 ld1rb \{z0\.h\}, p0/z, \[x0\]
--.*: 8440a000 ld1rb \{z0\.h\}, p0/z, \[x0\]
--.*: 8440a000 ld1rb \{z0\.h\}, p0/z, \[x0\]
--.*: 8440a000 ld1rb \{z0\.h\}, p0/z, \[x0\]
--.*: 8440a001 ld1rb \{z1\.h\}, p0/z, \[x0\]
--.*: 8440a001 ld1rb \{z1\.h\}, p0/z, \[x0\]
--.*: 8440a001 ld1rb \{z1\.h\}, p0/z, \[x0\]
--.*: 8440a001 ld1rb \{z1\.h\}, p0/z, \[x0\]
--.*: 8440a01f ld1rb \{z31\.h\}, p0/z, \[x0\]
--.*: 8440a01f ld1rb \{z31\.h\}, p0/z, \[x0\]
--.*: 8440a01f ld1rb \{z31\.h\}, p0/z, \[x0\]
--.*: 8440a01f ld1rb \{z31\.h\}, p0/z, \[x0\]
--.*: 8440a800 ld1rb \{z0\.h\}, p2/z, \[x0\]
--.*: 8440a800 ld1rb \{z0\.h\}, p2/z, \[x0\]
--.*: 8440a800 ld1rb \{z0\.h\}, p2/z, \[x0\]
--.*: 8440bc00 ld1rb \{z0\.h\}, p7/z, \[x0\]
--.*: 8440bc00 ld1rb \{z0\.h\}, p7/z, \[x0\]
--.*: 8440bc00 ld1rb \{z0\.h\}, p7/z, \[x0\]
--.*: 8440a060 ld1rb \{z0\.h\}, p0/z, \[x3\]
--.*: 8440a060 ld1rb \{z0\.h\}, p0/z, \[x3\]
--.*: 8440a060 ld1rb \{z0\.h\}, p0/z, \[x3\]
--.*: 8440a3e0 ld1rb \{z0\.h\}, p0/z, \[sp\]
--.*: 8440a3e0 ld1rb \{z0\.h\}, p0/z, \[sp\]
--.*: 8440a3e0 ld1rb \{z0\.h\}, p0/z, \[sp\]
--.*: 845fa000 ld1rb \{z0\.h\}, p0/z, \[x0, #31\]
--.*: 845fa000 ld1rb \{z0\.h\}, p0/z, \[x0, #31\]
--.*: 8460a000 ld1rb \{z0\.h\}, p0/z, \[x0, #32\]
--.*: 8460a000 ld1rb \{z0\.h\}, p0/z, \[x0, #32\]
--.*: 8461a000 ld1rb \{z0\.h\}, p0/z, \[x0, #33\]
--.*: 8461a000 ld1rb \{z0\.h\}, p0/z, \[x0, #33\]
--.*: 847fa000 ld1rb \{z0\.h\}, p0/z, \[x0, #63\]
--.*: 847fa000 ld1rb \{z0\.h\}, p0/z, \[x0, #63\]
--.*: 8440c000 ld1rb \{z0\.s\}, p0/z, \[x0\]
--.*: 8440c000 ld1rb \{z0\.s\}, p0/z, \[x0\]
--.*: 8440c000 ld1rb \{z0\.s\}, p0/z, \[x0\]
--.*: 8440c000 ld1rb \{z0\.s\}, p0/z, \[x0\]
--.*: 8440c001 ld1rb \{z1\.s\}, p0/z, \[x0\]
--.*: 8440c001 ld1rb \{z1\.s\}, p0/z, \[x0\]
--.*: 8440c001 ld1rb \{z1\.s\}, p0/z, \[x0\]
--.*: 8440c001 ld1rb \{z1\.s\}, p0/z, \[x0\]
--.*: 8440c01f ld1rb \{z31\.s\}, p0/z, \[x0\]
--.*: 8440c01f ld1rb \{z31\.s\}, p0/z, \[x0\]
--.*: 8440c01f ld1rb \{z31\.s\}, p0/z, \[x0\]
--.*: 8440c01f ld1rb \{z31\.s\}, p0/z, \[x0\]
--.*: 8440c800 ld1rb \{z0\.s\}, p2/z, \[x0\]
--.*: 8440c800 ld1rb \{z0\.s\}, p2/z, \[x0\]
--.*: 8440c800 ld1rb \{z0\.s\}, p2/z, \[x0\]
--.*: 8440dc00 ld1rb \{z0\.s\}, p7/z, \[x0\]
--.*: 8440dc00 ld1rb \{z0\.s\}, p7/z, \[x0\]
--.*: 8440dc00 ld1rb \{z0\.s\}, p7/z, \[x0\]
--.*: 8440c060 ld1rb \{z0\.s\}, p0/z, \[x3\]
--.*: 8440c060 ld1rb \{z0\.s\}, p0/z, \[x3\]
--.*: 8440c060 ld1rb \{z0\.s\}, p0/z, \[x3\]
--.*: 8440c3e0 ld1rb \{z0\.s\}, p0/z, \[sp\]
--.*: 8440c3e0 ld1rb \{z0\.s\}, p0/z, \[sp\]
--.*: 8440c3e0 ld1rb \{z0\.s\}, p0/z, \[sp\]
--.*: 845fc000 ld1rb \{z0\.s\}, p0/z, \[x0, #31\]
--.*: 845fc000 ld1rb \{z0\.s\}, p0/z, \[x0, #31\]
--.*: 8460c000 ld1rb \{z0\.s\}, p0/z, \[x0, #32\]
--.*: 8460c000 ld1rb \{z0\.s\}, p0/z, \[x0, #32\]
--.*: 8461c000 ld1rb \{z0\.s\}, p0/z, \[x0, #33\]
--.*: 8461c000 ld1rb \{z0\.s\}, p0/z, \[x0, #33\]
--.*: 847fc000 ld1rb \{z0\.s\}, p0/z, \[x0, #63\]
--.*: 847fc000 ld1rb \{z0\.s\}, p0/z, \[x0, #63\]
--.*: 8440e000 ld1rb \{z0\.d\}, p0/z, \[x0\]
--.*: 8440e000 ld1rb \{z0\.d\}, p0/z, \[x0\]
--.*: 8440e000 ld1rb \{z0\.d\}, p0/z, \[x0\]
--.*: 8440e000 ld1rb \{z0\.d\}, p0/z, \[x0\]
--.*: 8440e001 ld1rb \{z1\.d\}, p0/z, \[x0\]
--.*: 8440e001 ld1rb \{z1\.d\}, p0/z, \[x0\]
--.*: 8440e001 ld1rb \{z1\.d\}, p0/z, \[x0\]
--.*: 8440e001 ld1rb \{z1\.d\}, p0/z, \[x0\]
--.*: 8440e01f ld1rb \{z31\.d\}, p0/z, \[x0\]
--.*: 8440e01f ld1rb \{z31\.d\}, p0/z, \[x0\]
--.*: 8440e01f ld1rb \{z31\.d\}, p0/z, \[x0\]
--.*: 8440e01f ld1rb \{z31\.d\}, p0/z, \[x0\]
--.*: 8440e800 ld1rb \{z0\.d\}, p2/z, \[x0\]
--.*: 8440e800 ld1rb \{z0\.d\}, p2/z, \[x0\]
--.*: 8440e800 ld1rb \{z0\.d\}, p2/z, \[x0\]
--.*: 8440fc00 ld1rb \{z0\.d\}, p7/z, \[x0\]
--.*: 8440fc00 ld1rb \{z0\.d\}, p7/z, \[x0\]
--.*: 8440fc00 ld1rb \{z0\.d\}, p7/z, \[x0\]
--.*: 8440e060 ld1rb \{z0\.d\}, p0/z, \[x3\]
--.*: 8440e060 ld1rb \{z0\.d\}, p0/z, \[x3\]
--.*: 8440e060 ld1rb \{z0\.d\}, p0/z, \[x3\]
--.*: 8440e3e0 ld1rb \{z0\.d\}, p0/z, \[sp\]
--.*: 8440e3e0 ld1rb \{z0\.d\}, p0/z, \[sp\]
--.*: 8440e3e0 ld1rb \{z0\.d\}, p0/z, \[sp\]
--.*: 845fe000 ld1rb \{z0\.d\}, p0/z, \[x0, #31\]
--.*: 845fe000 ld1rb \{z0\.d\}, p0/z, \[x0, #31\]
--.*: 8460e000 ld1rb \{z0\.d\}, p0/z, \[x0, #32\]
--.*: 8460e000 ld1rb \{z0\.d\}, p0/z, \[x0, #32\]
--.*: 8461e000 ld1rb \{z0\.d\}, p0/z, \[x0, #33\]
--.*: 8461e000 ld1rb \{z0\.d\}, p0/z, \[x0, #33\]
--.*: 847fe000 ld1rb \{z0\.d\}, p0/z, \[x0, #63\]
--.*: 847fe000 ld1rb \{z0\.d\}, p0/z, \[x0, #63\]
--.*: 85c0e000 ld1rd \{z0\.d\}, p0/z, \[x0\]
--.*: 85c0e000 ld1rd \{z0\.d\}, p0/z, \[x0\]
--.*: 85c0e000 ld1rd \{z0\.d\}, p0/z, \[x0\]
--.*: 85c0e000 ld1rd \{z0\.d\}, p0/z, \[x0\]
--.*: 85c0e001 ld1rd \{z1\.d\}, p0/z, \[x0\]
--.*: 85c0e001 ld1rd \{z1\.d\}, p0/z, \[x0\]
--.*: 85c0e001 ld1rd \{z1\.d\}, p0/z, \[x0\]
--.*: 85c0e001 ld1rd \{z1\.d\}, p0/z, \[x0\]
--.*: 85c0e01f ld1rd \{z31\.d\}, p0/z, \[x0\]
--.*: 85c0e01f ld1rd \{z31\.d\}, p0/z, \[x0\]
--.*: 85c0e01f ld1rd \{z31\.d\}, p0/z, \[x0\]
--.*: 85c0e01f ld1rd \{z31\.d\}, p0/z, \[x0\]
--.*: 85c0e800 ld1rd \{z0\.d\}, p2/z, \[x0\]
--.*: 85c0e800 ld1rd \{z0\.d\}, p2/z, \[x0\]
--.*: 85c0e800 ld1rd \{z0\.d\}, p2/z, \[x0\]
--.*: 85c0fc00 ld1rd \{z0\.d\}, p7/z, \[x0\]
--.*: 85c0fc00 ld1rd \{z0\.d\}, p7/z, \[x0\]
--.*: 85c0fc00 ld1rd \{z0\.d\}, p7/z, \[x0\]
--.*: 85c0e060 ld1rd \{z0\.d\}, p0/z, \[x3\]
--.*: 85c0e060 ld1rd \{z0\.d\}, p0/z, \[x3\]
--.*: 85c0e060 ld1rd \{z0\.d\}, p0/z, \[x3\]
--.*: 85c0e3e0 ld1rd \{z0\.d\}, p0/z, \[sp\]
--.*: 85c0e3e0 ld1rd \{z0\.d\}, p0/z, \[sp\]
--.*: 85c0e3e0 ld1rd \{z0\.d\}, p0/z, \[sp\]
--.*: 85dfe000 ld1rd \{z0\.d\}, p0/z, \[x0, #248\]
--.*: 85dfe000 ld1rd \{z0\.d\}, p0/z, \[x0, #248\]
--.*: 85e0e000 ld1rd \{z0\.d\}, p0/z, \[x0, #256\]
--.*: 85e0e000 ld1rd \{z0\.d\}, p0/z, \[x0, #256\]
--.*: 85e1e000 ld1rd \{z0\.d\}, p0/z, \[x0, #264\]
--.*: 85e1e000 ld1rd \{z0\.d\}, p0/z, \[x0, #264\]
--.*: 85ffe000 ld1rd \{z0\.d\}, p0/z, \[x0, #504\]
--.*: 85ffe000 ld1rd \{z0\.d\}, p0/z, \[x0, #504\]
--.*: 84c0a000 ld1rh \{z0\.h\}, p0/z, \[x0\]
--.*: 84c0a000 ld1rh \{z0\.h\}, p0/z, \[x0\]
--.*: 84c0a000 ld1rh \{z0\.h\}, p0/z, \[x0\]
--.*: 84c0a000 ld1rh \{z0\.h\}, p0/z, \[x0\]
--.*: 84c0a001 ld1rh \{z1\.h\}, p0/z, \[x0\]
--.*: 84c0a001 ld1rh \{z1\.h\}, p0/z, \[x0\]
--.*: 84c0a001 ld1rh \{z1\.h\}, p0/z, \[x0\]
--.*: 84c0a001 ld1rh \{z1\.h\}, p0/z, \[x0\]
--.*: 84c0a01f ld1rh \{z31\.h\}, p0/z, \[x0\]
--.*: 84c0a01f ld1rh \{z31\.h\}, p0/z, \[x0\]
--.*: 84c0a01f ld1rh \{z31\.h\}, p0/z, \[x0\]
--.*: 84c0a01f ld1rh \{z31\.h\}, p0/z, \[x0\]
--.*: 84c0a800 ld1rh \{z0\.h\}, p2/z, \[x0\]
--.*: 84c0a800 ld1rh \{z0\.h\}, p2/z, \[x0\]
--.*: 84c0a800 ld1rh \{z0\.h\}, p2/z, \[x0\]
--.*: 84c0bc00 ld1rh \{z0\.h\}, p7/z, \[x0\]
--.*: 84c0bc00 ld1rh \{z0\.h\}, p7/z, \[x0\]
--.*: 84c0bc00 ld1rh \{z0\.h\}, p7/z, \[x0\]
--.*: 84c0a060 ld1rh \{z0\.h\}, p0/z, \[x3\]
--.*: 84c0a060 ld1rh \{z0\.h\}, p0/z, \[x3\]
--.*: 84c0a060 ld1rh \{z0\.h\}, p0/z, \[x3\]
--.*: 84c0a3e0 ld1rh \{z0\.h\}, p0/z, \[sp\]
--.*: 84c0a3e0 ld1rh \{z0\.h\}, p0/z, \[sp\]
--.*: 84c0a3e0 ld1rh \{z0\.h\}, p0/z, \[sp\]
--.*: 84dfa000 ld1rh \{z0\.h\}, p0/z, \[x0, #62\]
--.*: 84dfa000 ld1rh \{z0\.h\}, p0/z, \[x0, #62\]
--.*: 84e0a000 ld1rh \{z0\.h\}, p0/z, \[x0, #64\]
--.*: 84e0a000 ld1rh \{z0\.h\}, p0/z, \[x0, #64\]
--.*: 84e1a000 ld1rh \{z0\.h\}, p0/z, \[x0, #66\]
--.*: 84e1a000 ld1rh \{z0\.h\}, p0/z, \[x0, #66\]
--.*: 84ffa000 ld1rh \{z0\.h\}, p0/z, \[x0, #126\]
--.*: 84ffa000 ld1rh \{z0\.h\}, p0/z, \[x0, #126\]
--.*: 84c0c000 ld1rh \{z0\.s\}, p0/z, \[x0\]
--.*: 84c0c000 ld1rh \{z0\.s\}, p0/z, \[x0\]
--.*: 84c0c000 ld1rh \{z0\.s\}, p0/z, \[x0\]
--.*: 84c0c000 ld1rh \{z0\.s\}, p0/z, \[x0\]
--.*: 84c0c001 ld1rh \{z1\.s\}, p0/z, \[x0\]
--.*: 84c0c001 ld1rh \{z1\.s\}, p0/z, \[x0\]
--.*: 84c0c001 ld1rh \{z1\.s\}, p0/z, \[x0\]
--.*: 84c0c001 ld1rh \{z1\.s\}, p0/z, \[x0\]
--.*: 84c0c01f ld1rh \{z31\.s\}, p0/z, \[x0\]
--.*: 84c0c01f ld1rh \{z31\.s\}, p0/z, \[x0\]
--.*: 84c0c01f ld1rh \{z31\.s\}, p0/z, \[x0\]
--.*: 84c0c01f ld1rh \{z31\.s\}, p0/z, \[x0\]
--.*: 84c0c800 ld1rh \{z0\.s\}, p2/z, \[x0\]
--.*: 84c0c800 ld1rh \{z0\.s\}, p2/z, \[x0\]
--.*: 84c0c800 ld1rh \{z0\.s\}, p2/z, \[x0\]
--.*: 84c0dc00 ld1rh \{z0\.s\}, p7/z, \[x0\]
--.*: 84c0dc00 ld1rh \{z0\.s\}, p7/z, \[x0\]
--.*: 84c0dc00 ld1rh \{z0\.s\}, p7/z, \[x0\]
--.*: 84c0c060 ld1rh \{z0\.s\}, p0/z, \[x3\]
--.*: 84c0c060 ld1rh \{z0\.s\}, p0/z, \[x3\]
--.*: 84c0c060 ld1rh \{z0\.s\}, p0/z, \[x3\]
--.*: 84c0c3e0 ld1rh \{z0\.s\}, p0/z, \[sp\]
--.*: 84c0c3e0 ld1rh \{z0\.s\}, p0/z, \[sp\]
--.*: 84c0c3e0 ld1rh \{z0\.s\}, p0/z, \[sp\]
--.*: 84dfc000 ld1rh \{z0\.s\}, p0/z, \[x0, #62\]
--.*: 84dfc000 ld1rh \{z0\.s\}, p0/z, \[x0, #62\]
--.*: 84e0c000 ld1rh \{z0\.s\}, p0/z, \[x0, #64\]
--.*: 84e0c000 ld1rh \{z0\.s\}, p0/z, \[x0, #64\]
--.*: 84e1c000 ld1rh \{z0\.s\}, p0/z, \[x0, #66\]
--.*: 84e1c000 ld1rh \{z0\.s\}, p0/z, \[x0, #66\]
--.*: 84ffc000 ld1rh \{z0\.s\}, p0/z, \[x0, #126\]
--.*: 84ffc000 ld1rh \{z0\.s\}, p0/z, \[x0, #126\]
--.*: 84c0e000 ld1rh \{z0\.d\}, p0/z, \[x0\]
--.*: 84c0e000 ld1rh \{z0\.d\}, p0/z, \[x0\]
--.*: 84c0e000 ld1rh \{z0\.d\}, p0/z, \[x0\]
--.*: 84c0e000 ld1rh \{z0\.d\}, p0/z, \[x0\]
--.*: 84c0e001 ld1rh \{z1\.d\}, p0/z, \[x0\]
--.*: 84c0e001 ld1rh \{z1\.d\}, p0/z, \[x0\]
--.*: 84c0e001 ld1rh \{z1\.d\}, p0/z, \[x0\]
--.*: 84c0e001 ld1rh \{z1\.d\}, p0/z, \[x0\]
--.*: 84c0e01f ld1rh \{z31\.d\}, p0/z, \[x0\]
--.*: 84c0e01f ld1rh \{z31\.d\}, p0/z, \[x0\]
--.*: 84c0e01f ld1rh \{z31\.d\}, p0/z, \[x0\]
--.*: 84c0e01f ld1rh \{z31\.d\}, p0/z, \[x0\]
--.*: 84c0e800 ld1rh \{z0\.d\}, p2/z, \[x0\]
--.*: 84c0e800 ld1rh \{z0\.d\}, p2/z, \[x0\]
--.*: 84c0e800 ld1rh \{z0\.d\}, p2/z, \[x0\]
--.*: 84c0fc00 ld1rh \{z0\.d\}, p7/z, \[x0\]
--.*: 84c0fc00 ld1rh \{z0\.d\}, p7/z, \[x0\]
--.*: 84c0fc00 ld1rh \{z0\.d\}, p7/z, \[x0\]
--.*: 84c0e060 ld1rh \{z0\.d\}, p0/z, \[x3\]
--.*: 84c0e060 ld1rh \{z0\.d\}, p0/z, \[x3\]
--.*: 84c0e060 ld1rh \{z0\.d\}, p0/z, \[x3\]
--.*: 84c0e3e0 ld1rh \{z0\.d\}, p0/z, \[sp\]
--.*: 84c0e3e0 ld1rh \{z0\.d\}, p0/z, \[sp\]
--.*: 84c0e3e0 ld1rh \{z0\.d\}, p0/z, \[sp\]
--.*: 84dfe000 ld1rh \{z0\.d\}, p0/z, \[x0, #62\]
--.*: 84dfe000 ld1rh \{z0\.d\}, p0/z, \[x0, #62\]
--.*: 84e0e000 ld1rh \{z0\.d\}, p0/z, \[x0, #64\]
--.*: 84e0e000 ld1rh \{z0\.d\}, p0/z, \[x0, #64\]
--.*: 84e1e000 ld1rh \{z0\.d\}, p0/z, \[x0, #66\]
--.*: 84e1e000 ld1rh \{z0\.d\}, p0/z, \[x0, #66\]
--.*: 84ffe000 ld1rh \{z0\.d\}, p0/z, \[x0, #126\]
--.*: 84ffe000 ld1rh \{z0\.d\}, p0/z, \[x0, #126\]
--.*: 85c08000 ld1rsb \{z0\.d\}, p0/z, \[x0\]
--.*: 85c08000 ld1rsb \{z0\.d\}, p0/z, \[x0\]
--.*: 85c08000 ld1rsb \{z0\.d\}, p0/z, \[x0\]
--.*: 85c08000 ld1rsb \{z0\.d\}, p0/z, \[x0\]
--.*: 85c08001 ld1rsb \{z1\.d\}, p0/z, \[x0\]
--.*: 85c08001 ld1rsb \{z1\.d\}, p0/z, \[x0\]
--.*: 85c08001 ld1rsb \{z1\.d\}, p0/z, \[x0\]
--.*: 85c08001 ld1rsb \{z1\.d\}, p0/z, \[x0\]
--.*: 85c0801f ld1rsb \{z31\.d\}, p0/z, \[x0\]
--.*: 85c0801f ld1rsb \{z31\.d\}, p0/z, \[x0\]
--.*: 85c0801f ld1rsb \{z31\.d\}, p0/z, \[x0\]
--.*: 85c0801f ld1rsb \{z31\.d\}, p0/z, \[x0\]
--.*: 85c08800 ld1rsb \{z0\.d\}, p2/z, \[x0\]
--.*: 85c08800 ld1rsb \{z0\.d\}, p2/z, \[x0\]
--.*: 85c08800 ld1rsb \{z0\.d\}, p2/z, \[x0\]
--.*: 85c09c00 ld1rsb \{z0\.d\}, p7/z, \[x0\]
--.*: 85c09c00 ld1rsb \{z0\.d\}, p7/z, \[x0\]
--.*: 85c09c00 ld1rsb \{z0\.d\}, p7/z, \[x0\]
--.*: 85c08060 ld1rsb \{z0\.d\}, p0/z, \[x3\]
--.*: 85c08060 ld1rsb \{z0\.d\}, p0/z, \[x3\]
--.*: 85c08060 ld1rsb \{z0\.d\}, p0/z, \[x3\]
--.*: 85c083e0 ld1rsb \{z0\.d\}, p0/z, \[sp\]
--.*: 85c083e0 ld1rsb \{z0\.d\}, p0/z, \[sp\]
--.*: 85c083e0 ld1rsb \{z0\.d\}, p0/z, \[sp\]
--.*: 85df8000 ld1rsb \{z0\.d\}, p0/z, \[x0, #31\]
--.*: 85df8000 ld1rsb \{z0\.d\}, p0/z, \[x0, #31\]
--.*: 85e08000 ld1rsb \{z0\.d\}, p0/z, \[x0, #32\]
--.*: 85e08000 ld1rsb \{z0\.d\}, p0/z, \[x0, #32\]
--.*: 85e18000 ld1rsb \{z0\.d\}, p0/z, \[x0, #33\]
--.*: 85e18000 ld1rsb \{z0\.d\}, p0/z, \[x0, #33\]
--.*: 85ff8000 ld1rsb \{z0\.d\}, p0/z, \[x0, #63\]
--.*: 85ff8000 ld1rsb \{z0\.d\}, p0/z, \[x0, #63\]
--.*: 85c0a000 ld1rsb \{z0\.s\}, p0/z, \[x0\]
--.*: 85c0a000 ld1rsb \{z0\.s\}, p0/z, \[x0\]
--.*: 85c0a000 ld1rsb \{z0\.s\}, p0/z, \[x0\]
--.*: 85c0a000 ld1rsb \{z0\.s\}, p0/z, \[x0\]
--.*: 85c0a001 ld1rsb \{z1\.s\}, p0/z, \[x0\]
--.*: 85c0a001 ld1rsb \{z1\.s\}, p0/z, \[x0\]
--.*: 85c0a001 ld1rsb \{z1\.s\}, p0/z, \[x0\]
--.*: 85c0a001 ld1rsb \{z1\.s\}, p0/z, \[x0\]
--.*: 85c0a01f ld1rsb \{z31\.s\}, p0/z, \[x0\]
--.*: 85c0a01f ld1rsb \{z31\.s\}, p0/z, \[x0\]
--.*: 85c0a01f ld1rsb \{z31\.s\}, p0/z, \[x0\]
--.*: 85c0a01f ld1rsb \{z31\.s\}, p0/z, \[x0\]
--.*: 85c0a800 ld1rsb \{z0\.s\}, p2/z, \[x0\]
--.*: 85c0a800 ld1rsb \{z0\.s\}, p2/z, \[x0\]
--.*: 85c0a800 ld1rsb \{z0\.s\}, p2/z, \[x0\]
--.*: 85c0bc00 ld1rsb \{z0\.s\}, p7/z, \[x0\]
--.*: 85c0bc00 ld1rsb \{z0\.s\}, p7/z, \[x0\]
--.*: 85c0bc00 ld1rsb \{z0\.s\}, p7/z, \[x0\]
--.*: 85c0a060 ld1rsb \{z0\.s\}, p0/z, \[x3\]
--.*: 85c0a060 ld1rsb \{z0\.s\}, p0/z, \[x3\]
--.*: 85c0a060 ld1rsb \{z0\.s\}, p0/z, \[x3\]
--.*: 85c0a3e0 ld1rsb \{z0\.s\}, p0/z, \[sp\]
--.*: 85c0a3e0 ld1rsb \{z0\.s\}, p0/z, \[sp\]
--.*: 85c0a3e0 ld1rsb \{z0\.s\}, p0/z, \[sp\]
--.*: 85dfa000 ld1rsb \{z0\.s\}, p0/z, \[x0, #31\]
--.*: 85dfa000 ld1rsb \{z0\.s\}, p0/z, \[x0, #31\]
--.*: 85e0a000 ld1rsb \{z0\.s\}, p0/z, \[x0, #32\]
--.*: 85e0a000 ld1rsb \{z0\.s\}, p0/z, \[x0, #32\]
--.*: 85e1a000 ld1rsb \{z0\.s\}, p0/z, \[x0, #33\]
--.*: 85e1a000 ld1rsb \{z0\.s\}, p0/z, \[x0, #33\]
--.*: 85ffa000 ld1rsb \{z0\.s\}, p0/z, \[x0, #63\]
--.*: 85ffa000 ld1rsb \{z0\.s\}, p0/z, \[x0, #63\]
--.*: 85c0c000 ld1rsb \{z0\.h\}, p0/z, \[x0\]
--.*: 85c0c000 ld1rsb \{z0\.h\}, p0/z, \[x0\]
--.*: 85c0c000 ld1rsb \{z0\.h\}, p0/z, \[x0\]
--.*: 85c0c000 ld1rsb \{z0\.h\}, p0/z, \[x0\]
--.*: 85c0c001 ld1rsb \{z1\.h\}, p0/z, \[x0\]
--.*: 85c0c001 ld1rsb \{z1\.h\}, p0/z, \[x0\]
--.*: 85c0c001 ld1rsb \{z1\.h\}, p0/z, \[x0\]
--.*: 85c0c001 ld1rsb \{z1\.h\}, p0/z, \[x0\]
--.*: 85c0c01f ld1rsb \{z31\.h\}, p0/z, \[x0\]
--.*: 85c0c01f ld1rsb \{z31\.h\}, p0/z, \[x0\]
--.*: 85c0c01f ld1rsb \{z31\.h\}, p0/z, \[x0\]
--.*: 85c0c01f ld1rsb \{z31\.h\}, p0/z, \[x0\]
--.*: 85c0c800 ld1rsb \{z0\.h\}, p2/z, \[x0\]
--.*: 85c0c800 ld1rsb \{z0\.h\}, p2/z, \[x0\]
--.*: 85c0c800 ld1rsb \{z0\.h\}, p2/z, \[x0\]
--.*: 85c0dc00 ld1rsb \{z0\.h\}, p7/z, \[x0\]
--.*: 85c0dc00 ld1rsb \{z0\.h\}, p7/z, \[x0\]
--.*: 85c0dc00 ld1rsb \{z0\.h\}, p7/z, \[x0\]
--.*: 85c0c060 ld1rsb \{z0\.h\}, p0/z, \[x3\]
--.*: 85c0c060 ld1rsb \{z0\.h\}, p0/z, \[x3\]
--.*: 85c0c060 ld1rsb \{z0\.h\}, p0/z, \[x3\]
--.*: 85c0c3e0 ld1rsb \{z0\.h\}, p0/z, \[sp\]
--.*: 85c0c3e0 ld1rsb \{z0\.h\}, p0/z, \[sp\]
--.*: 85c0c3e0 ld1rsb \{z0\.h\}, p0/z, \[sp\]
--.*: 85dfc000 ld1rsb \{z0\.h\}, p0/z, \[x0, #31\]
--.*: 85dfc000 ld1rsb \{z0\.h\}, p0/z, \[x0, #31\]
--.*: 85e0c000 ld1rsb \{z0\.h\}, p0/z, \[x0, #32\]
--.*: 85e0c000 ld1rsb \{z0\.h\}, p0/z, \[x0, #32\]
--.*: 85e1c000 ld1rsb \{z0\.h\}, p0/z, \[x0, #33\]
--.*: 85e1c000 ld1rsb \{z0\.h\}, p0/z, \[x0, #33\]
--.*: 85ffc000 ld1rsb \{z0\.h\}, p0/z, \[x0, #63\]
--.*: 85ffc000 ld1rsb \{z0\.h\}, p0/z, \[x0, #63\]
--.*: 85408000 ld1rsh \{z0\.d\}, p0/z, \[x0\]
--.*: 85408000 ld1rsh \{z0\.d\}, p0/z, \[x0\]
--.*: 85408000 ld1rsh \{z0\.d\}, p0/z, \[x0\]
--.*: 85408000 ld1rsh \{z0\.d\}, p0/z, \[x0\]
--.*: 85408001 ld1rsh \{z1\.d\}, p0/z, \[x0\]
--.*: 85408001 ld1rsh \{z1\.d\}, p0/z, \[x0\]
--.*: 85408001 ld1rsh \{z1\.d\}, p0/z, \[x0\]
--.*: 85408001 ld1rsh \{z1\.d\}, p0/z, \[x0\]
--.*: 8540801f ld1rsh \{z31\.d\}, p0/z, \[x0\]
--.*: 8540801f ld1rsh \{z31\.d\}, p0/z, \[x0\]
--.*: 8540801f ld1rsh \{z31\.d\}, p0/z, \[x0\]
--.*: 8540801f ld1rsh \{z31\.d\}, p0/z, \[x0\]
--.*: 85408800 ld1rsh \{z0\.d\}, p2/z, \[x0\]
--.*: 85408800 ld1rsh \{z0\.d\}, p2/z, \[x0\]
--.*: 85408800 ld1rsh \{z0\.d\}, p2/z, \[x0\]
--.*: 85409c00 ld1rsh \{z0\.d\}, p7/z, \[x0\]
--.*: 85409c00 ld1rsh \{z0\.d\}, p7/z, \[x0\]
--.*: 85409c00 ld1rsh \{z0\.d\}, p7/z, \[x0\]
--.*: 85408060 ld1rsh \{z0\.d\}, p0/z, \[x3\]
--.*: 85408060 ld1rsh \{z0\.d\}, p0/z, \[x3\]
--.*: 85408060 ld1rsh \{z0\.d\}, p0/z, \[x3\]
--.*: 854083e0 ld1rsh \{z0\.d\}, p0/z, \[sp\]
--.*: 854083e0 ld1rsh \{z0\.d\}, p0/z, \[sp\]
--.*: 854083e0 ld1rsh \{z0\.d\}, p0/z, \[sp\]
--.*: 855f8000 ld1rsh \{z0\.d\}, p0/z, \[x0, #62\]
--.*: 855f8000 ld1rsh \{z0\.d\}, p0/z, \[x0, #62\]
--.*: 85608000 ld1rsh \{z0\.d\}, p0/z, \[x0, #64\]
--.*: 85608000 ld1rsh \{z0\.d\}, p0/z, \[x0, #64\]
--.*: 85618000 ld1rsh \{z0\.d\}, p0/z, \[x0, #66\]
--.*: 85618000 ld1rsh \{z0\.d\}, p0/z, \[x0, #66\]
--.*: 857f8000 ld1rsh \{z0\.d\}, p0/z, \[x0, #126\]
--.*: 857f8000 ld1rsh \{z0\.d\}, p0/z, \[x0, #126\]
--.*: 8540a000 ld1rsh \{z0\.s\}, p0/z, \[x0\]
--.*: 8540a000 ld1rsh \{z0\.s\}, p0/z, \[x0\]
--.*: 8540a000 ld1rsh \{z0\.s\}, p0/z, \[x0\]
--.*: 8540a000 ld1rsh \{z0\.s\}, p0/z, \[x0\]
--.*: 8540a001 ld1rsh \{z1\.s\}, p0/z, \[x0\]
--.*: 8540a001 ld1rsh \{z1\.s\}, p0/z, \[x0\]
--.*: 8540a001 ld1rsh \{z1\.s\}, p0/z, \[x0\]
--.*: 8540a001 ld1rsh \{z1\.s\}, p0/z, \[x0\]
--.*: 8540a01f ld1rsh \{z31\.s\}, p0/z, \[x0\]
--.*: 8540a01f ld1rsh \{z31\.s\}, p0/z, \[x0\]
--.*: 8540a01f ld1rsh \{z31\.s\}, p0/z, \[x0\]
--.*: 8540a01f ld1rsh \{z31\.s\}, p0/z, \[x0\]
--.*: 8540a800 ld1rsh \{z0\.s\}, p2/z, \[x0\]
--.*: 8540a800 ld1rsh \{z0\.s\}, p2/z, \[x0\]
--.*: 8540a800 ld1rsh \{z0\.s\}, p2/z, \[x0\]
--.*: 8540bc00 ld1rsh \{z0\.s\}, p7/z, \[x0\]
--.*: 8540bc00 ld1rsh \{z0\.s\}, p7/z, \[x0\]
--.*: 8540bc00 ld1rsh \{z0\.s\}, p7/z, \[x0\]
--.*: 8540a060 ld1rsh \{z0\.s\}, p0/z, \[x3\]
--.*: 8540a060 ld1rsh \{z0\.s\}, p0/z, \[x3\]
--.*: 8540a060 ld1rsh \{z0\.s\}, p0/z, \[x3\]
--.*: 8540a3e0 ld1rsh \{z0\.s\}, p0/z, \[sp\]
--.*: 8540a3e0 ld1rsh \{z0\.s\}, p0/z, \[sp\]
--.*: 8540a3e0 ld1rsh \{z0\.s\}, p0/z, \[sp\]
--.*: 855fa000 ld1rsh \{z0\.s\}, p0/z, \[x0, #62\]
--.*: 855fa000 ld1rsh \{z0\.s\}, p0/z, \[x0, #62\]
--.*: 8560a000 ld1rsh \{z0\.s\}, p0/z, \[x0, #64\]
--.*: 8560a000 ld1rsh \{z0\.s\}, p0/z, \[x0, #64\]
--.*: 8561a000 ld1rsh \{z0\.s\}, p0/z, \[x0, #66\]
--.*: 8561a000 ld1rsh \{z0\.s\}, p0/z, \[x0, #66\]
--.*: 857fa000 ld1rsh \{z0\.s\}, p0/z, \[x0, #126\]
--.*: 857fa000 ld1rsh \{z0\.s\}, p0/z, \[x0, #126\]
--.*: 84c08000 ld1rsw \{z0\.d\}, p0/z, \[x0\]
--.*: 84c08000 ld1rsw \{z0\.d\}, p0/z, \[x0\]
--.*: 84c08000 ld1rsw \{z0\.d\}, p0/z, \[x0\]
--.*: 84c08000 ld1rsw \{z0\.d\}, p0/z, \[x0\]
--.*: 84c08001 ld1rsw \{z1\.d\}, p0/z, \[x0\]
--.*: 84c08001 ld1rsw \{z1\.d\}, p0/z, \[x0\]
--.*: 84c08001 ld1rsw \{z1\.d\}, p0/z, \[x0\]
--.*: 84c08001 ld1rsw \{z1\.d\}, p0/z, \[x0\]
--.*: 84c0801f ld1rsw \{z31\.d\}, p0/z, \[x0\]
--.*: 84c0801f ld1rsw \{z31\.d\}, p0/z, \[x0\]
--.*: 84c0801f ld1rsw \{z31\.d\}, p0/z, \[x0\]
--.*: 84c0801f ld1rsw \{z31\.d\}, p0/z, \[x0\]
--.*: 84c08800 ld1rsw \{z0\.d\}, p2/z, \[x0\]
--.*: 84c08800 ld1rsw \{z0\.d\}, p2/z, \[x0\]
--.*: 84c08800 ld1rsw \{z0\.d\}, p2/z, \[x0\]
--.*: 84c09c00 ld1rsw \{z0\.d\}, p7/z, \[x0\]
--.*: 84c09c00 ld1rsw \{z0\.d\}, p7/z, \[x0\]
--.*: 84c09c00 ld1rsw \{z0\.d\}, p7/z, \[x0\]
--.*: 84c08060 ld1rsw \{z0\.d\}, p0/z, \[x3\]
--.*: 84c08060 ld1rsw \{z0\.d\}, p0/z, \[x3\]
--.*: 84c08060 ld1rsw \{z0\.d\}, p0/z, \[x3\]
--.*: 84c083e0 ld1rsw \{z0\.d\}, p0/z, \[sp\]
--.*: 84c083e0 ld1rsw \{z0\.d\}, p0/z, \[sp\]
--.*: 84c083e0 ld1rsw \{z0\.d\}, p0/z, \[sp\]
--.*: 84df8000 ld1rsw \{z0\.d\}, p0/z, \[x0, #124\]
--.*: 84df8000 ld1rsw \{z0\.d\}, p0/z, \[x0, #124\]
--.*: 84e08000 ld1rsw \{z0\.d\}, p0/z, \[x0, #128\]
--.*: 84e08000 ld1rsw \{z0\.d\}, p0/z, \[x0, #128\]
--.*: 84e18000 ld1rsw \{z0\.d\}, p0/z, \[x0, #132\]
--.*: 84e18000 ld1rsw \{z0\.d\}, p0/z, \[x0, #132\]
--.*: 84ff8000 ld1rsw \{z0\.d\}, p0/z, \[x0, #252\]
--.*: 84ff8000 ld1rsw \{z0\.d\}, p0/z, \[x0, #252\]
--.*: a4002000 ld1rqb \{z0\.b\}, p0/z, \[x0\]
--.*: a4002000 ld1rqb \{z0\.b\}, p0/z, \[x0\]
--.*: a4002000 ld1rqb \{z0\.b\}, p0/z, \[x0\]
--.*: a4002000 ld1rqb \{z0\.b\}, p0/z, \[x0\]
--.*: a4002001 ld1rqb \{z1\.b\}, p0/z, \[x0\]
--.*: a4002001 ld1rqb \{z1\.b\}, p0/z, \[x0\]
--.*: a4002001 ld1rqb \{z1\.b\}, p0/z, \[x0\]
--.*: a4002001 ld1rqb \{z1\.b\}, p0/z, \[x0\]
--.*: a400201f ld1rqb \{z31\.b\}, p0/z, \[x0\]
--.*: a400201f ld1rqb \{z31\.b\}, p0/z, \[x0\]
--.*: a400201f ld1rqb \{z31\.b\}, p0/z, \[x0\]
--.*: a400201f ld1rqb \{z31\.b\}, p0/z, \[x0\]
--.*: a4002800 ld1rqb \{z0\.b\}, p2/z, \[x0\]
--.*: a4002800 ld1rqb \{z0\.b\}, p2/z, \[x0\]
--.*: a4002800 ld1rqb \{z0\.b\}, p2/z, \[x0\]
--.*: a4003c00 ld1rqb \{z0\.b\}, p7/z, \[x0\]
--.*: a4003c00 ld1rqb \{z0\.b\}, p7/z, \[x0\]
--.*: a4003c00 ld1rqb \{z0\.b\}, p7/z, \[x0\]
--.*: a4002060 ld1rqb \{z0\.b\}, p0/z, \[x3\]
--.*: a4002060 ld1rqb \{z0\.b\}, p0/z, \[x3\]
--.*: a4002060 ld1rqb \{z0\.b\}, p0/z, \[x3\]
--.*: a40023e0 ld1rqb \{z0\.b\}, p0/z, \[sp\]
--.*: a40023e0 ld1rqb \{z0\.b\}, p0/z, \[sp\]
--.*: a40023e0 ld1rqb \{z0\.b\}, p0/z, \[sp\]
--.*: a4082000 ld1rqb \{z0\.b\}, p0/z, \[x0, #-128\]
--.*: a4082000 ld1rqb \{z0\.b\}, p0/z, \[x0, #-128\]
--.*: a40f2000 ld1rqb \{z0\.b\}, p0/z, \[x0, #-16\]
--.*: a40f2000 ld1rqb \{z0\.b\}, p0/z, \[x0, #-16\]
--.*: a4012000 ld1rqb \{z0\.b\}, p0/z, \[x0, #16\]
--.*: a4012000 ld1rqb \{z0\.b\}, p0/z, \[x0, #16\]
--.*: a4072000 ld1rqb \{z0\.b\}, p0/z, \[x0, #112\]
--.*: a4072000 ld1rqb \{z0\.b\}, p0/z, \[x0, #112\]
--.*: a4000000 ld1rqb \{z0\.b\}, p0/z, \[x0, x0\]
--.*: a4000000 ld1rqb \{z0\.b\}, p0/z, \[x0, x0\]
--.*: a4000000 ld1rqb \{z0\.b\}, p0/z, \[x0, x0\]
--.*: a4000000 ld1rqb \{z0\.b\}, p0/z, \[x0, x0\]
--.*: a4000001 ld1rqb \{z1\.b\}, p0/z, \[x0, x0\]
--.*: a4000001 ld1rqb \{z1\.b\}, p0/z, \[x0, x0\]
--.*: a4000001 ld1rqb \{z1\.b\}, p0/z, \[x0, x0\]
--.*: a4000001 ld1rqb \{z1\.b\}, p0/z, \[x0, x0\]
--.*: a400001f ld1rqb \{z31\.b\}, p0/z, \[x0, x0\]
--.*: a400001f ld1rqb \{z31\.b\}, p0/z, \[x0, x0\]
--.*: a400001f ld1rqb \{z31\.b\}, p0/z, \[x0, x0\]
--.*: a400001f ld1rqb \{z31\.b\}, p0/z, \[x0, x0\]
--.*: a4000800 ld1rqb \{z0\.b\}, p2/z, \[x0, x0\]
--.*: a4000800 ld1rqb \{z0\.b\}, p2/z, \[x0, x0\]
--.*: a4000800 ld1rqb \{z0\.b\}, p2/z, \[x0, x0\]
--.*: a4001c00 ld1rqb \{z0\.b\}, p7/z, \[x0, x0\]
--.*: a4001c00 ld1rqb \{z0\.b\}, p7/z, \[x0, x0\]
--.*: a4001c00 ld1rqb \{z0\.b\}, p7/z, \[x0, x0\]
--.*: a4000060 ld1rqb \{z0\.b\}, p0/z, \[x3, x0\]
--.*: a4000060 ld1rqb \{z0\.b\}, p0/z, \[x3, x0\]
--.*: a4000060 ld1rqb \{z0\.b\}, p0/z, \[x3, x0\]
--.*: a40003e0 ld1rqb \{z0\.b\}, p0/z, \[sp, x0\]
--.*: a40003e0 ld1rqb \{z0\.b\}, p0/z, \[sp, x0\]
--.*: a40003e0 ld1rqb \{z0\.b\}, p0/z, \[sp, x0\]
--.*: a4040000 ld1rqb \{z0\.b\}, p0/z, \[x0, x4\]
--.*: a4040000 ld1rqb \{z0\.b\}, p0/z, \[x0, x4\]
--.*: a4040000 ld1rqb \{z0\.b\}, p0/z, \[x0, x4\]
--.*: a41e0000 ld1rqb \{z0\.b\}, p0/z, \[x0, x30\]
--.*: a41e0000 ld1rqb \{z0\.b\}, p0/z, \[x0, x30\]
--.*: a41e0000 ld1rqb \{z0\.b\}, p0/z, \[x0, x30\]
--.*: a5802000 ld1rqd \{z0\.d\}, p0/z, \[x0\]
--.*: a5802000 ld1rqd \{z0\.d\}, p0/z, \[x0\]
--.*: a5802000 ld1rqd \{z0\.d\}, p0/z, \[x0\]
--.*: a5802000 ld1rqd \{z0\.d\}, p0/z, \[x0\]
--.*: a5802001 ld1rqd \{z1\.d\}, p0/z, \[x0\]
--.*: a5802001 ld1rqd \{z1\.d\}, p0/z, \[x0\]
--.*: a5802001 ld1rqd \{z1\.d\}, p0/z, \[x0\]
--.*: a5802001 ld1rqd \{z1\.d\}, p0/z, \[x0\]
--.*: a580201f ld1rqd \{z31\.d\}, p0/z, \[x0\]
--.*: a580201f ld1rqd \{z31\.d\}, p0/z, \[x0\]
--.*: a580201f ld1rqd \{z31\.d\}, p0/z, \[x0\]
--.*: a580201f ld1rqd \{z31\.d\}, p0/z, \[x0\]
--.*: a5802800 ld1rqd \{z0\.d\}, p2/z, \[x0\]
--.*: a5802800 ld1rqd \{z0\.d\}, p2/z, \[x0\]
--.*: a5802800 ld1rqd \{z0\.d\}, p2/z, \[x0\]
--.*: a5803c00 ld1rqd \{z0\.d\}, p7/z, \[x0\]
--.*: a5803c00 ld1rqd \{z0\.d\}, p7/z, \[x0\]
--.*: a5803c00 ld1rqd \{z0\.d\}, p7/z, \[x0\]
--.*: a5802060 ld1rqd \{z0\.d\}, p0/z, \[x3\]
--.*: a5802060 ld1rqd \{z0\.d\}, p0/z, \[x3\]
--.*: a5802060 ld1rqd \{z0\.d\}, p0/z, \[x3\]
--.*: a58023e0 ld1rqd \{z0\.d\}, p0/z, \[sp\]
--.*: a58023e0 ld1rqd \{z0\.d\}, p0/z, \[sp\]
--.*: a58023e0 ld1rqd \{z0\.d\}, p0/z, \[sp\]
--.*: a5882000 ld1rqd \{z0\.d\}, p0/z, \[x0, #-128\]
--.*: a5882000 ld1rqd \{z0\.d\}, p0/z, \[x0, #-128\]
--.*: a58f2000 ld1rqd \{z0\.d\}, p0/z, \[x0, #-16\]
--.*: a58f2000 ld1rqd \{z0\.d\}, p0/z, \[x0, #-16\]
--.*: a5812000 ld1rqd \{z0\.d\}, p0/z, \[x0, #16\]
--.*: a5812000 ld1rqd \{z0\.d\}, p0/z, \[x0, #16\]
--.*: a5872000 ld1rqd \{z0\.d\}, p0/z, \[x0, #112\]
--.*: a5872000 ld1rqd \{z0\.d\}, p0/z, \[x0, #112\]
--.*: a5800000 ld1rqd \{z0\.d\}, p0/z, \[x0, x0, lsl #3\]
--.*: a5800000 ld1rqd \{z0\.d\}, p0/z, \[x0, x0, lsl #3\]
--.*: a5800000 ld1rqd \{z0\.d\}, p0/z, \[x0, x0, lsl #3\]
--.*: a5800001 ld1rqd \{z1\.d\}, p0/z, \[x0, x0, lsl #3\]
--.*: a5800001 ld1rqd \{z1\.d\}, p0/z, \[x0, x0, lsl #3\]
--.*: a5800001 ld1rqd \{z1\.d\}, p0/z, \[x0, x0, lsl #3\]
--.*: a580001f ld1rqd \{z31\.d\}, p0/z, \[x0, x0, lsl #3\]
--.*: a580001f ld1rqd \{z31\.d\}, p0/z, \[x0, x0, lsl #3\]
--.*: a580001f ld1rqd \{z31\.d\}, p0/z, \[x0, x0, lsl #3\]
--.*: a5800800 ld1rqd \{z0\.d\}, p2/z, \[x0, x0, lsl #3\]
--.*: a5800800 ld1rqd \{z0\.d\}, p2/z, \[x0, x0, lsl #3\]
--.*: a5801c00 ld1rqd \{z0\.d\}, p7/z, \[x0, x0, lsl #3\]
--.*: a5801c00 ld1rqd \{z0\.d\}, p7/z, \[x0, x0, lsl #3\]
--.*: a5800060 ld1rqd \{z0\.d\}, p0/z, \[x3, x0, lsl #3\]
--.*: a5800060 ld1rqd \{z0\.d\}, p0/z, \[x3, x0, lsl #3\]
--.*: a58003e0 ld1rqd \{z0\.d\}, p0/z, \[sp, x0, lsl #3\]
--.*: a58003e0 ld1rqd \{z0\.d\}, p0/z, \[sp, x0, lsl #3\]
--.*: a5840000 ld1rqd \{z0\.d\}, p0/z, \[x0, x4, lsl #3\]
--.*: a5840000 ld1rqd \{z0\.d\}, p0/z, \[x0, x4, lsl #3\]
--.*: a59e0000 ld1rqd \{z0\.d\}, p0/z, \[x0, x30, lsl #3\]
--.*: a59e0000 ld1rqd \{z0\.d\}, p0/z, \[x0, x30, lsl #3\]
--.*: a4802000 ld1rqh \{z0\.h\}, p0/z, \[x0\]
--.*: a4802000 ld1rqh \{z0\.h\}, p0/z, \[x0\]
--.*: a4802000 ld1rqh \{z0\.h\}, p0/z, \[x0\]
--.*: a4802000 ld1rqh \{z0\.h\}, p0/z, \[x0\]
--.*: a4802001 ld1rqh \{z1\.h\}, p0/z, \[x0\]
--.*: a4802001 ld1rqh \{z1\.h\}, p0/z, \[x0\]
--.*: a4802001 ld1rqh \{z1\.h\}, p0/z, \[x0\]
--.*: a4802001 ld1rqh \{z1\.h\}, p0/z, \[x0\]
--.*: a480201f ld1rqh \{z31\.h\}, p0/z, \[x0\]
--.*: a480201f ld1rqh \{z31\.h\}, p0/z, \[x0\]
--.*: a480201f ld1rqh \{z31\.h\}, p0/z, \[x0\]
--.*: a480201f ld1rqh \{z31\.h\}, p0/z, \[x0\]
--.*: a4802800 ld1rqh \{z0\.h\}, p2/z, \[x0\]
--.*: a4802800 ld1rqh \{z0\.h\}, p2/z, \[x0\]
--.*: a4802800 ld1rqh \{z0\.h\}, p2/z, \[x0\]
--.*: a4803c00 ld1rqh \{z0\.h\}, p7/z, \[x0\]
--.*: a4803c00 ld1rqh \{z0\.h\}, p7/z, \[x0\]
--.*: a4803c00 ld1rqh \{z0\.h\}, p7/z, \[x0\]
--.*: a4802060 ld1rqh \{z0\.h\}, p0/z, \[x3\]
--.*: a4802060 ld1rqh \{z0\.h\}, p0/z, \[x3\]
--.*: a4802060 ld1rqh \{z0\.h\}, p0/z, \[x3\]
--.*: a48023e0 ld1rqh \{z0\.h\}, p0/z, \[sp\]
--.*: a48023e0 ld1rqh \{z0\.h\}, p0/z, \[sp\]
--.*: a48023e0 ld1rqh \{z0\.h\}, p0/z, \[sp\]
--.*: a4882000 ld1rqh \{z0\.h\}, p0/z, \[x0, #-128\]
--.*: a4882000 ld1rqh \{z0\.h\}, p0/z, \[x0, #-128\]
--.*: a48f2000 ld1rqh \{z0\.h\}, p0/z, \[x0, #-16\]
--.*: a48f2000 ld1rqh \{z0\.h\}, p0/z, \[x0, #-16\]
--.*: a4812000 ld1rqh \{z0\.h\}, p0/z, \[x0, #16\]
--.*: a4812000 ld1rqh \{z0\.h\}, p0/z, \[x0, #16\]
--.*: a4872000 ld1rqh \{z0\.h\}, p0/z, \[x0, #112\]
--.*: a4872000 ld1rqh \{z0\.h\}, p0/z, \[x0, #112\]
--.*: a4800000 ld1rqh \{z0\.h\}, p0/z, \[x0, x0, lsl #1\]
--.*: a4800000 ld1rqh \{z0\.h\}, p0/z, \[x0, x0, lsl #1\]
--.*: a4800000 ld1rqh \{z0\.h\}, p0/z, \[x0, x0, lsl #1\]
--.*: a4800001 ld1rqh \{z1\.h\}, p0/z, \[x0, x0, lsl #1\]
--.*: a4800001 ld1rqh \{z1\.h\}, p0/z, \[x0, x0, lsl #1\]
--.*: a4800001 ld1rqh \{z1\.h\}, p0/z, \[x0, x0, lsl #1\]
--.*: a480001f ld1rqh \{z31\.h\}, p0/z, \[x0, x0, lsl #1\]
--.*: a480001f ld1rqh \{z31\.h\}, p0/z, \[x0, x0, lsl #1\]
--.*: a480001f ld1rqh \{z31\.h\}, p0/z, \[x0, x0, lsl #1\]
--.*: a4800800 ld1rqh \{z0\.h\}, p2/z, \[x0, x0, lsl #1\]
--.*: a4800800 ld1rqh \{z0\.h\}, p2/z, \[x0, x0, lsl #1\]
--.*: a4801c00 ld1rqh \{z0\.h\}, p7/z, \[x0, x0, lsl #1\]
--.*: a4801c00 ld1rqh \{z0\.h\}, p7/z, \[x0, x0, lsl #1\]
--.*: a4800060 ld1rqh \{z0\.h\}, p0/z, \[x3, x0, lsl #1\]
--.*: a4800060 ld1rqh \{z0\.h\}, p0/z, \[x3, x0, lsl #1\]
--.*: a48003e0 ld1rqh \{z0\.h\}, p0/z, \[sp, x0, lsl #1\]
--.*: a48003e0 ld1rqh \{z0\.h\}, p0/z, \[sp, x0, lsl #1\]
--.*: a4840000 ld1rqh \{z0\.h\}, p0/z, \[x0, x4, lsl #1\]
--.*: a4840000 ld1rqh \{z0\.h\}, p0/z, \[x0, x4, lsl #1\]
--.*: a49e0000 ld1rqh \{z0\.h\}, p0/z, \[x0, x30, lsl #1\]
--.*: a49e0000 ld1rqh \{z0\.h\}, p0/z, \[x0, x30, lsl #1\]
--.*: a5002000 ld1rqw \{z0\.s\}, p0/z, \[x0\]
--.*: a5002000 ld1rqw \{z0\.s\}, p0/z, \[x0\]
--.*: a5002000 ld1rqw \{z0\.s\}, p0/z, \[x0\]
--.*: a5002000 ld1rqw \{z0\.s\}, p0/z, \[x0\]
--.*: a5002001 ld1rqw \{z1\.s\}, p0/z, \[x0\]
--.*: a5002001 ld1rqw \{z1\.s\}, p0/z, \[x0\]
--.*: a5002001 ld1rqw \{z1\.s\}, p0/z, \[x0\]
--.*: a5002001 ld1rqw \{z1\.s\}, p0/z, \[x0\]
--.*: a500201f ld1rqw \{z31\.s\}, p0/z, \[x0\]
--.*: a500201f ld1rqw \{z31\.s\}, p0/z, \[x0\]
--.*: a500201f ld1rqw \{z31\.s\}, p0/z, \[x0\]
--.*: a500201f ld1rqw \{z31\.s\}, p0/z, \[x0\]
--.*: a5002800 ld1rqw \{z0\.s\}, p2/z, \[x0\]
--.*: a5002800 ld1rqw \{z0\.s\}, p2/z, \[x0\]
--.*: a5002800 ld1rqw \{z0\.s\}, p2/z, \[x0\]
--.*: a5003c00 ld1rqw \{z0\.s\}, p7/z, \[x0\]
--.*: a5003c00 ld1rqw \{z0\.s\}, p7/z, \[x0\]
--.*: a5003c00 ld1rqw \{z0\.s\}, p7/z, \[x0\]
--.*: a5002060 ld1rqw \{z0\.s\}, p0/z, \[x3\]
--.*: a5002060 ld1rqw \{z0\.s\}, p0/z, \[x3\]
--.*: a5002060 ld1rqw \{z0\.s\}, p0/z, \[x3\]
--.*: a50023e0 ld1rqw \{z0\.s\}, p0/z, \[sp\]
--.*: a50023e0 ld1rqw \{z0\.s\}, p0/z, \[sp\]
--.*: a50023e0 ld1rqw \{z0\.s\}, p0/z, \[sp\]
--.*: a5082000 ld1rqw \{z0\.s\}, p0/z, \[x0, #-128\]
--.*: a5082000 ld1rqw \{z0\.s\}, p0/z, \[x0, #-128\]
--.*: a50f2000 ld1rqw \{z0\.s\}, p0/z, \[x0, #-16\]
--.*: a50f2000 ld1rqw \{z0\.s\}, p0/z, \[x0, #-16\]
--.*: a5012000 ld1rqw \{z0\.s\}, p0/z, \[x0, #16\]
--.*: a5012000 ld1rqw \{z0\.s\}, p0/z, \[x0, #16\]
--.*: a5072000 ld1rqw \{z0\.s\}, p0/z, \[x0, #112\]
--.*: a5072000 ld1rqw \{z0\.s\}, p0/z, \[x0, #112\]
--.*: a5000000 ld1rqw \{z0\.s\}, p0/z, \[x0, x0, lsl #2\]
--.*: a5000000 ld1rqw \{z0\.s\}, p0/z, \[x0, x0, lsl #2\]
--.*: a5000000 ld1rqw \{z0\.s\}, p0/z, \[x0, x0, lsl #2\]
--.*: a5000001 ld1rqw \{z1\.s\}, p0/z, \[x0, x0, lsl #2\]
--.*: a5000001 ld1rqw \{z1\.s\}, p0/z, \[x0, x0, lsl #2\]
--.*: a5000001 ld1rqw \{z1\.s\}, p0/z, \[x0, x0, lsl #2\]
--.*: a500001f ld1rqw \{z31\.s\}, p0/z, \[x0, x0, lsl #2\]
--.*: a500001f ld1rqw \{z31\.s\}, p0/z, \[x0, x0, lsl #2\]
--.*: a500001f ld1rqw \{z31\.s\}, p0/z, \[x0, x0, lsl #2\]
--.*: a5000800 ld1rqw \{z0\.s\}, p2/z, \[x0, x0, lsl #2\]
--.*: a5000800 ld1rqw \{z0\.s\}, p2/z, \[x0, x0, lsl #2\]
--.*: a5001c00 ld1rqw \{z0\.s\}, p7/z, \[x0, x0, lsl #2\]
--.*: a5001c00 ld1rqw \{z0\.s\}, p7/z, \[x0, x0, lsl #2\]
--.*: a5000060 ld1rqw \{z0\.s\}, p0/z, \[x3, x0, lsl #2\]
--.*: a5000060 ld1rqw \{z0\.s\}, p0/z, \[x3, x0, lsl #2\]
--.*: a50003e0 ld1rqw \{z0\.s\}, p0/z, \[sp, x0, lsl #2\]
--.*: a50003e0 ld1rqw \{z0\.s\}, p0/z, \[sp, x0, lsl #2\]
--.*: a5040000 ld1rqw \{z0\.s\}, p0/z, \[x0, x4, lsl #2\]
--.*: a5040000 ld1rqw \{z0\.s\}, p0/z, \[x0, x4, lsl #2\]
--.*: a51e0000 ld1rqw \{z0\.s\}, p0/z, \[x0, x30, lsl #2\]
--.*: a51e0000 ld1rqw \{z0\.s\}, p0/z, \[x0, x30, lsl #2\]
--.*: 8540c000 ld1rw \{z0\.s\}, p0/z, \[x0\]
--.*: 8540c000 ld1rw \{z0\.s\}, p0/z, \[x0\]
--.*: 8540c000 ld1rw \{z0\.s\}, p0/z, \[x0\]
--.*: 8540c000 ld1rw \{z0\.s\}, p0/z, \[x0\]
--.*: 8540c001 ld1rw \{z1\.s\}, p0/z, \[x0\]
--.*: 8540c001 ld1rw \{z1\.s\}, p0/z, \[x0\]
--.*: 8540c001 ld1rw \{z1\.s\}, p0/z, \[x0\]
--.*: 8540c001 ld1rw \{z1\.s\}, p0/z, \[x0\]
--.*: 8540c01f ld1rw \{z31\.s\}, p0/z, \[x0\]
--.*: 8540c01f ld1rw \{z31\.s\}, p0/z, \[x0\]
--.*: 8540c01f ld1rw \{z31\.s\}, p0/z, \[x0\]
--.*: 8540c01f ld1rw \{z31\.s\}, p0/z, \[x0\]
--.*: 8540c800 ld1rw \{z0\.s\}, p2/z, \[x0\]
--.*: 8540c800 ld1rw \{z0\.s\}, p2/z, \[x0\]
--.*: 8540c800 ld1rw \{z0\.s\}, p2/z, \[x0\]
--.*: 8540dc00 ld1rw \{z0\.s\}, p7/z, \[x0\]
--.*: 8540dc00 ld1rw \{z0\.s\}, p7/z, \[x0\]
--.*: 8540dc00 ld1rw \{z0\.s\}, p7/z, \[x0\]
--.*: 8540c060 ld1rw \{z0\.s\}, p0/z, \[x3\]
--.*: 8540c060 ld1rw \{z0\.s\}, p0/z, \[x3\]
--.*: 8540c060 ld1rw \{z0\.s\}, p0/z, \[x3\]
--.*: 8540c3e0 ld1rw \{z0\.s\}, p0/z, \[sp\]
--.*: 8540c3e0 ld1rw \{z0\.s\}, p0/z, \[sp\]
--.*: 8540c3e0 ld1rw \{z0\.s\}, p0/z, \[sp\]
--.*: 855fc000 ld1rw \{z0\.s\}, p0/z, \[x0, #124\]
--.*: 855fc000 ld1rw \{z0\.s\}, p0/z, \[x0, #124\]
--.*: 8560c000 ld1rw \{z0\.s\}, p0/z, \[x0, #128\]
--.*: 8560c000 ld1rw \{z0\.s\}, p0/z, \[x0, #128\]
--.*: 8561c000 ld1rw \{z0\.s\}, p0/z, \[x0, #132\]
--.*: 8561c000 ld1rw \{z0\.s\}, p0/z, \[x0, #132\]
--.*: 857fc000 ld1rw \{z0\.s\}, p0/z, \[x0, #252\]
--.*: 857fc000 ld1rw \{z0\.s\}, p0/z, \[x0, #252\]
--.*: 8540e000 ld1rw \{z0\.d\}, p0/z, \[x0\]
--.*: 8540e000 ld1rw \{z0\.d\}, p0/z, \[x0\]
--.*: 8540e000 ld1rw \{z0\.d\}, p0/z, \[x0\]
--.*: 8540e000 ld1rw \{z0\.d\}, p0/z, \[x0\]
--.*: 8540e001 ld1rw \{z1\.d\}, p0/z, \[x0\]
--.*: 8540e001 ld1rw \{z1\.d\}, p0/z, \[x0\]
--.*: 8540e001 ld1rw \{z1\.d\}, p0/z, \[x0\]
--.*: 8540e001 ld1rw \{z1\.d\}, p0/z, \[x0\]
--.*: 8540e01f ld1rw \{z31\.d\}, p0/z, \[x0\]
--.*: 8540e01f ld1rw \{z31\.d\}, p0/z, \[x0\]
--.*: 8540e01f ld1rw \{z31\.d\}, p0/z, \[x0\]
--.*: 8540e01f ld1rw \{z31\.d\}, p0/z, \[x0\]
--.*: 8540e800 ld1rw \{z0\.d\}, p2/z, \[x0\]
--.*: 8540e800 ld1rw \{z0\.d\}, p2/z, \[x0\]
--.*: 8540e800 ld1rw \{z0\.d\}, p2/z, \[x0\]
--.*: 8540fc00 ld1rw \{z0\.d\}, p7/z, \[x0\]
--.*: 8540fc00 ld1rw \{z0\.d\}, p7/z, \[x0\]
--.*: 8540fc00 ld1rw \{z0\.d\}, p7/z, \[x0\]
--.*: 8540e060 ld1rw \{z0\.d\}, p0/z, \[x3\]
--.*: 8540e060 ld1rw \{z0\.d\}, p0/z, \[x3\]
--.*: 8540e060 ld1rw \{z0\.d\}, p0/z, \[x3\]
--.*: 8540e3e0 ld1rw \{z0\.d\}, p0/z, \[sp\]
--.*: 8540e3e0 ld1rw \{z0\.d\}, p0/z, \[sp\]
--.*: 8540e3e0 ld1rw \{z0\.d\}, p0/z, \[sp\]
--.*: 855fe000 ld1rw \{z0\.d\}, p0/z, \[x0, #124\]
--.*: 855fe000 ld1rw \{z0\.d\}, p0/z, \[x0, #124\]
--.*: 8560e000 ld1rw \{z0\.d\}, p0/z, \[x0, #128\]
--.*: 8560e000 ld1rw \{z0\.d\}, p0/z, \[x0, #128\]
--.*: 8561e000 ld1rw \{z0\.d\}, p0/z, \[x0, #132\]
--.*: 8561e000 ld1rw \{z0\.d\}, p0/z, \[x0, #132\]
--.*: 857fe000 ld1rw \{z0\.d\}, p0/z, \[x0, #252\]
--.*: 857fe000 ld1rw \{z0\.d\}, p0/z, \[x0, #252\]
--.*: 84000000 ld1sb \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 84000000 ld1sb \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 84000000 ld1sb \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 84000000 ld1sb \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 84000001 ld1sb \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 84000001 ld1sb \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 84000001 ld1sb \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 84000001 ld1sb \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 8400001f ld1sb \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 8400001f ld1sb \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 8400001f ld1sb \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 8400001f ld1sb \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 84000800 ld1sb \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\]
--.*: 84000800 ld1sb \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\]
--.*: 84000800 ld1sb \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\]
--.*: 84001c00 ld1sb \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\]
--.*: 84001c00 ld1sb \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\]
--.*: 84001c00 ld1sb \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\]
--.*: 84000060 ld1sb \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\]
--.*: 84000060 ld1sb \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\]
--.*: 84000060 ld1sb \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\]
--.*: 840003e0 ld1sb \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\]
--.*: 840003e0 ld1sb \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\]
--.*: 840003e0 ld1sb \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\]
--.*: 84040000 ld1sb \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\]
--.*: 84040000 ld1sb \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\]
--.*: 84040000 ld1sb \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\]
--.*: 841f0000 ld1sb \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\]
--.*: 841f0000 ld1sb \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\]
--.*: 841f0000 ld1sb \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\]
--.*: 84400000 ld1sb \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 84400000 ld1sb \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 84400000 ld1sb \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 84400000 ld1sb \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 84400001 ld1sb \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 84400001 ld1sb \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 84400001 ld1sb \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 84400001 ld1sb \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 8440001f ld1sb \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 8440001f ld1sb \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 8440001f ld1sb \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 8440001f ld1sb \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 84400800 ld1sb \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\]
--.*: 84400800 ld1sb \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\]
--.*: 84400800 ld1sb \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\]
--.*: 84401c00 ld1sb \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\]
--.*: 84401c00 ld1sb \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\]
--.*: 84401c00 ld1sb \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\]
--.*: 84400060 ld1sb \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\]
--.*: 84400060 ld1sb \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\]
--.*: 84400060 ld1sb \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\]
--.*: 844003e0 ld1sb \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\]
--.*: 844003e0 ld1sb \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\]
--.*: 844003e0 ld1sb \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\]
--.*: 84440000 ld1sb \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\]
--.*: 84440000 ld1sb \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\]
--.*: 84440000 ld1sb \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\]
--.*: 845f0000 ld1sb \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\]
--.*: 845f0000 ld1sb \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\]
--.*: 845f0000 ld1sb \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\]
--.*: a5804000 ld1sb \{z0\.d\}, p0/z, \[x0, x0\]
--.*: a5804000 ld1sb \{z0\.d\}, p0/z, \[x0, x0\]
--.*: a5804000 ld1sb \{z0\.d\}, p0/z, \[x0, x0\]
--.*: a5804000 ld1sb \{z0\.d\}, p0/z, \[x0, x0\]
--.*: a5804001 ld1sb \{z1\.d\}, p0/z, \[x0, x0\]
--.*: a5804001 ld1sb \{z1\.d\}, p0/z, \[x0, x0\]
--.*: a5804001 ld1sb \{z1\.d\}, p0/z, \[x0, x0\]
--.*: a5804001 ld1sb \{z1\.d\}, p0/z, \[x0, x0\]
--.*: a580401f ld1sb \{z31\.d\}, p0/z, \[x0, x0\]
--.*: a580401f ld1sb \{z31\.d\}, p0/z, \[x0, x0\]
--.*: a580401f ld1sb \{z31\.d\}, p0/z, \[x0, x0\]
--.*: a580401f ld1sb \{z31\.d\}, p0/z, \[x0, x0\]
--.*: a5804800 ld1sb \{z0\.d\}, p2/z, \[x0, x0\]
--.*: a5804800 ld1sb \{z0\.d\}, p2/z, \[x0, x0\]
--.*: a5804800 ld1sb \{z0\.d\}, p2/z, \[x0, x0\]
--.*: a5805c00 ld1sb \{z0\.d\}, p7/z, \[x0, x0\]
--.*: a5805c00 ld1sb \{z0\.d\}, p7/z, \[x0, x0\]
--.*: a5805c00 ld1sb \{z0\.d\}, p7/z, \[x0, x0\]
--.*: a5804060 ld1sb \{z0\.d\}, p0/z, \[x3, x0\]
--.*: a5804060 ld1sb \{z0\.d\}, p0/z, \[x3, x0\]
--.*: a5804060 ld1sb \{z0\.d\}, p0/z, \[x3, x0\]
--.*: a58043e0 ld1sb \{z0\.d\}, p0/z, \[sp, x0\]
--.*: a58043e0 ld1sb \{z0\.d\}, p0/z, \[sp, x0\]
--.*: a58043e0 ld1sb \{z0\.d\}, p0/z, \[sp, x0\]
--.*: a5844000 ld1sb \{z0\.d\}, p0/z, \[x0, x4\]
--.*: a5844000 ld1sb \{z0\.d\}, p0/z, \[x0, x4\]
--.*: a5844000 ld1sb \{z0\.d\}, p0/z, \[x0, x4\]
--.*: a59e4000 ld1sb \{z0\.d\}, p0/z, \[x0, x30\]
--.*: a59e4000 ld1sb \{z0\.d\}, p0/z, \[x0, x30\]
--.*: a59e4000 ld1sb \{z0\.d\}, p0/z, \[x0, x30\]
--.*: a5a04000 ld1sb \{z0\.s\}, p0/z, \[x0, x0\]
--.*: a5a04000 ld1sb \{z0\.s\}, p0/z, \[x0, x0\]
--.*: a5a04000 ld1sb \{z0\.s\}, p0/z, \[x0, x0\]
--.*: a5a04000 ld1sb \{z0\.s\}, p0/z, \[x0, x0\]
--.*: a5a04001 ld1sb \{z1\.s\}, p0/z, \[x0, x0\]
--.*: a5a04001 ld1sb \{z1\.s\}, p0/z, \[x0, x0\]
--.*: a5a04001 ld1sb \{z1\.s\}, p0/z, \[x0, x0\]
--.*: a5a04001 ld1sb \{z1\.s\}, p0/z, \[x0, x0\]
--.*: a5a0401f ld1sb \{z31\.s\}, p0/z, \[x0, x0\]
--.*: a5a0401f ld1sb \{z31\.s\}, p0/z, \[x0, x0\]
--.*: a5a0401f ld1sb \{z31\.s\}, p0/z, \[x0, x0\]
--.*: a5a0401f ld1sb \{z31\.s\}, p0/z, \[x0, x0\]
--.*: a5a04800 ld1sb \{z0\.s\}, p2/z, \[x0, x0\]
--.*: a5a04800 ld1sb \{z0\.s\}, p2/z, \[x0, x0\]
--.*: a5a04800 ld1sb \{z0\.s\}, p2/z, \[x0, x0\]
--.*: a5a05c00 ld1sb \{z0\.s\}, p7/z, \[x0, x0\]
--.*: a5a05c00 ld1sb \{z0\.s\}, p7/z, \[x0, x0\]
--.*: a5a05c00 ld1sb \{z0\.s\}, p7/z, \[x0, x0\]
--.*: a5a04060 ld1sb \{z0\.s\}, p0/z, \[x3, x0\]
--.*: a5a04060 ld1sb \{z0\.s\}, p0/z, \[x3, x0\]
--.*: a5a04060 ld1sb \{z0\.s\}, p0/z, \[x3, x0\]
--.*: a5a043e0 ld1sb \{z0\.s\}, p0/z, \[sp, x0\]
--.*: a5a043e0 ld1sb \{z0\.s\}, p0/z, \[sp, x0\]
--.*: a5a043e0 ld1sb \{z0\.s\}, p0/z, \[sp, x0\]
--.*: a5a44000 ld1sb \{z0\.s\}, p0/z, \[x0, x4\]
--.*: a5a44000 ld1sb \{z0\.s\}, p0/z, \[x0, x4\]
--.*: a5a44000 ld1sb \{z0\.s\}, p0/z, \[x0, x4\]
--.*: a5be4000 ld1sb \{z0\.s\}, p0/z, \[x0, x30\]
--.*: a5be4000 ld1sb \{z0\.s\}, p0/z, \[x0, x30\]
--.*: a5be4000 ld1sb \{z0\.s\}, p0/z, \[x0, x30\]
--.*: a5c04000 ld1sb \{z0\.h\}, p0/z, \[x0, x0\]
--.*: a5c04000 ld1sb \{z0\.h\}, p0/z, \[x0, x0\]
--.*: a5c04000 ld1sb \{z0\.h\}, p0/z, \[x0, x0\]
--.*: a5c04000 ld1sb \{z0\.h\}, p0/z, \[x0, x0\]
--.*: a5c04001 ld1sb \{z1\.h\}, p0/z, \[x0, x0\]
--.*: a5c04001 ld1sb \{z1\.h\}, p0/z, \[x0, x0\]
--.*: a5c04001 ld1sb \{z1\.h\}, p0/z, \[x0, x0\]
--.*: a5c04001 ld1sb \{z1\.h\}, p0/z, \[x0, x0\]
--.*: a5c0401f ld1sb \{z31\.h\}, p0/z, \[x0, x0\]
--.*: a5c0401f ld1sb \{z31\.h\}, p0/z, \[x0, x0\]
--.*: a5c0401f ld1sb \{z31\.h\}, p0/z, \[x0, x0\]
--.*: a5c0401f ld1sb \{z31\.h\}, p0/z, \[x0, x0\]
--.*: a5c04800 ld1sb \{z0\.h\}, p2/z, \[x0, x0\]
--.*: a5c04800 ld1sb \{z0\.h\}, p2/z, \[x0, x0\]
--.*: a5c04800 ld1sb \{z0\.h\}, p2/z, \[x0, x0\]
--.*: a5c05c00 ld1sb \{z0\.h\}, p7/z, \[x0, x0\]
--.*: a5c05c00 ld1sb \{z0\.h\}, p7/z, \[x0, x0\]
--.*: a5c05c00 ld1sb \{z0\.h\}, p7/z, \[x0, x0\]
--.*: a5c04060 ld1sb \{z0\.h\}, p0/z, \[x3, x0\]
--.*: a5c04060 ld1sb \{z0\.h\}, p0/z, \[x3, x0\]
--.*: a5c04060 ld1sb \{z0\.h\}, p0/z, \[x3, x0\]
--.*: a5c043e0 ld1sb \{z0\.h\}, p0/z, \[sp, x0\]
--.*: a5c043e0 ld1sb \{z0\.h\}, p0/z, \[sp, x0\]
--.*: a5c043e0 ld1sb \{z0\.h\}, p0/z, \[sp, x0\]
--.*: a5c44000 ld1sb \{z0\.h\}, p0/z, \[x0, x4\]
--.*: a5c44000 ld1sb \{z0\.h\}, p0/z, \[x0, x4\]
--.*: a5c44000 ld1sb \{z0\.h\}, p0/z, \[x0, x4\]
--.*: a5de4000 ld1sb \{z0\.h\}, p0/z, \[x0, x30\]
--.*: a5de4000 ld1sb \{z0\.h\}, p0/z, \[x0, x30\]
--.*: a5de4000 ld1sb \{z0\.h\}, p0/z, \[x0, x30\]
--.*: c4000000 ld1sb \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c4000000 ld1sb \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c4000000 ld1sb \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c4000000 ld1sb \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c4000001 ld1sb \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c4000001 ld1sb \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c4000001 ld1sb \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c4000001 ld1sb \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c400001f ld1sb \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c400001f ld1sb \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c400001f ld1sb \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c400001f ld1sb \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c4000800 ld1sb \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\]
--.*: c4000800 ld1sb \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\]
--.*: c4000800 ld1sb \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\]
--.*: c4001c00 ld1sb \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\]
--.*: c4001c00 ld1sb \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\]
--.*: c4001c00 ld1sb \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\]
--.*: c4000060 ld1sb \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\]
--.*: c4000060 ld1sb \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\]
--.*: c4000060 ld1sb \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\]
--.*: c40003e0 ld1sb \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\]
--.*: c40003e0 ld1sb \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\]
--.*: c40003e0 ld1sb \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\]
--.*: c4040000 ld1sb \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\]
--.*: c4040000 ld1sb \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\]
--.*: c4040000 ld1sb \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\]
--.*: c41f0000 ld1sb \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\]
--.*: c41f0000 ld1sb \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\]
--.*: c41f0000 ld1sb \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\]
--.*: c4400000 ld1sb \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c4400000 ld1sb \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c4400000 ld1sb \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c4400000 ld1sb \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c4400001 ld1sb \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c4400001 ld1sb \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c4400001 ld1sb \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c4400001 ld1sb \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c440001f ld1sb \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c440001f ld1sb \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c440001f ld1sb \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c440001f ld1sb \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c4400800 ld1sb \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\]
--.*: c4400800 ld1sb \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\]
--.*: c4400800 ld1sb \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\]
--.*: c4401c00 ld1sb \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\]
--.*: c4401c00 ld1sb \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\]
--.*: c4401c00 ld1sb \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\]
--.*: c4400060 ld1sb \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\]
--.*: c4400060 ld1sb \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\]
--.*: c4400060 ld1sb \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\]
--.*: c44003e0 ld1sb \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\]
--.*: c44003e0 ld1sb \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\]
--.*: c44003e0 ld1sb \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\]
--.*: c4440000 ld1sb \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\]
--.*: c4440000 ld1sb \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\]
--.*: c4440000 ld1sb \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\]
--.*: c45f0000 ld1sb \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\]
--.*: c45f0000 ld1sb \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\]
--.*: c45f0000 ld1sb \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\]
--.*: c4408000 ld1sb \{z0\.d\}, p0/z, \[x0, z0\.d\]
--.*: c4408000 ld1sb \{z0\.d\}, p0/z, \[x0, z0\.d\]
--.*: c4408000 ld1sb \{z0\.d\}, p0/z, \[x0, z0\.d\]
--.*: c4408000 ld1sb \{z0\.d\}, p0/z, \[x0, z0\.d\]
--.*: c4408001 ld1sb \{z1\.d\}, p0/z, \[x0, z0\.d\]
--.*: c4408001 ld1sb \{z1\.d\}, p0/z, \[x0, z0\.d\]
--.*: c4408001 ld1sb \{z1\.d\}, p0/z, \[x0, z0\.d\]
--.*: c4408001 ld1sb \{z1\.d\}, p0/z, \[x0, z0\.d\]
--.*: c440801f ld1sb \{z31\.d\}, p0/z, \[x0, z0\.d\]
--.*: c440801f ld1sb \{z31\.d\}, p0/z, \[x0, z0\.d\]
--.*: c440801f ld1sb \{z31\.d\}, p0/z, \[x0, z0\.d\]
--.*: c440801f ld1sb \{z31\.d\}, p0/z, \[x0, z0\.d\]
--.*: c4408800 ld1sb \{z0\.d\}, p2/z, \[x0, z0\.d\]
--.*: c4408800 ld1sb \{z0\.d\}, p2/z, \[x0, z0\.d\]
--.*: c4408800 ld1sb \{z0\.d\}, p2/z, \[x0, z0\.d\]
--.*: c4409c00 ld1sb \{z0\.d\}, p7/z, \[x0, z0\.d\]
--.*: c4409c00 ld1sb \{z0\.d\}, p7/z, \[x0, z0\.d\]
--.*: c4409c00 ld1sb \{z0\.d\}, p7/z, \[x0, z0\.d\]
--.*: c4408060 ld1sb \{z0\.d\}, p0/z, \[x3, z0\.d\]
--.*: c4408060 ld1sb \{z0\.d\}, p0/z, \[x3, z0\.d\]
--.*: c4408060 ld1sb \{z0\.d\}, p0/z, \[x3, z0\.d\]
--.*: c44083e0 ld1sb \{z0\.d\}, p0/z, \[sp, z0\.d\]
--.*: c44083e0 ld1sb \{z0\.d\}, p0/z, \[sp, z0\.d\]
--.*: c44083e0 ld1sb \{z0\.d\}, p0/z, \[sp, z0\.d\]
--.*: c4448000 ld1sb \{z0\.d\}, p0/z, \[x0, z4\.d\]
--.*: c4448000 ld1sb \{z0\.d\}, p0/z, \[x0, z4\.d\]
--.*: c4448000 ld1sb \{z0\.d\}, p0/z, \[x0, z4\.d\]
--.*: c45f8000 ld1sb \{z0\.d\}, p0/z, \[x0, z31\.d\]
--.*: c45f8000 ld1sb \{z0\.d\}, p0/z, \[x0, z31\.d\]
--.*: c45f8000 ld1sb \{z0\.d\}, p0/z, \[x0, z31\.d\]
--.*: 84208000 ld1sb \{z0\.s\}, p0/z, \[z0\.s\]
--.*: 84208000 ld1sb \{z0\.s\}, p0/z, \[z0\.s\]
--.*: 84208000 ld1sb \{z0\.s\}, p0/z, \[z0\.s\]
--.*: 84208000 ld1sb \{z0\.s\}, p0/z, \[z0\.s\]
--.*: 84208001 ld1sb \{z1\.s\}, p0/z, \[z0\.s\]
--.*: 84208001 ld1sb \{z1\.s\}, p0/z, \[z0\.s\]
--.*: 84208001 ld1sb \{z1\.s\}, p0/z, \[z0\.s\]
--.*: 84208001 ld1sb \{z1\.s\}, p0/z, \[z0\.s\]
--.*: 8420801f ld1sb \{z31\.s\}, p0/z, \[z0\.s\]
--.*: 8420801f ld1sb \{z31\.s\}, p0/z, \[z0\.s\]
--.*: 8420801f ld1sb \{z31\.s\}, p0/z, \[z0\.s\]
--.*: 8420801f ld1sb \{z31\.s\}, p0/z, \[z0\.s\]
--.*: 84208800 ld1sb \{z0\.s\}, p2/z, \[z0\.s\]
--.*: 84208800 ld1sb \{z0\.s\}, p2/z, \[z0\.s\]
--.*: 84208800 ld1sb \{z0\.s\}, p2/z, \[z0\.s\]
--.*: 84209c00 ld1sb \{z0\.s\}, p7/z, \[z0\.s\]
--.*: 84209c00 ld1sb \{z0\.s\}, p7/z, \[z0\.s\]
--.*: 84209c00 ld1sb \{z0\.s\}, p7/z, \[z0\.s\]
--.*: 84208060 ld1sb \{z0\.s\}, p0/z, \[z3\.s\]
--.*: 84208060 ld1sb \{z0\.s\}, p0/z, \[z3\.s\]
--.*: 84208060 ld1sb \{z0\.s\}, p0/z, \[z3\.s\]
--.*: 842083e0 ld1sb \{z0\.s\}, p0/z, \[z31\.s\]
--.*: 842083e0 ld1sb \{z0\.s\}, p0/z, \[z31\.s\]
--.*: 842083e0 ld1sb \{z0\.s\}, p0/z, \[z31\.s\]
--.*: 842f8000 ld1sb \{z0\.s\}, p0/z, \[z0\.s, #15\]
--.*: 842f8000 ld1sb \{z0\.s\}, p0/z, \[z0\.s, #15\]
--.*: 84308000 ld1sb \{z0\.s\}, p0/z, \[z0\.s, #16\]
--.*: 84308000 ld1sb \{z0\.s\}, p0/z, \[z0\.s, #16\]
--.*: 84318000 ld1sb \{z0\.s\}, p0/z, \[z0\.s, #17\]
--.*: 84318000 ld1sb \{z0\.s\}, p0/z, \[z0\.s, #17\]
--.*: 843f8000 ld1sb \{z0\.s\}, p0/z, \[z0\.s, #31\]
--.*: 843f8000 ld1sb \{z0\.s\}, p0/z, \[z0\.s, #31\]
--.*: a580a000 ld1sb \{z0\.d\}, p0/z, \[x0\]
--.*: a580a000 ld1sb \{z0\.d\}, p0/z, \[x0\]
--.*: a580a000 ld1sb \{z0\.d\}, p0/z, \[x0\]
--.*: a580a000 ld1sb \{z0\.d\}, p0/z, \[x0\]
--.*: a580a000 ld1sb \{z0\.d\}, p0/z, \[x0\]
--.*: a580a001 ld1sb \{z1\.d\}, p0/z, \[x0\]
--.*: a580a001 ld1sb \{z1\.d\}, p0/z, \[x0\]
--.*: a580a001 ld1sb \{z1\.d\}, p0/z, \[x0\]
--.*: a580a001 ld1sb \{z1\.d\}, p0/z, \[x0\]
--.*: a580a001 ld1sb \{z1\.d\}, p0/z, \[x0\]
--.*: a580a01f ld1sb \{z31\.d\}, p0/z, \[x0\]
--.*: a580a01f ld1sb \{z31\.d\}, p0/z, \[x0\]
--.*: a580a01f ld1sb \{z31\.d\}, p0/z, \[x0\]
--.*: a580a01f ld1sb \{z31\.d\}, p0/z, \[x0\]
--.*: a580a01f ld1sb \{z31\.d\}, p0/z, \[x0\]
--.*: a580a800 ld1sb \{z0\.d\}, p2/z, \[x0\]
--.*: a580a800 ld1sb \{z0\.d\}, p2/z, \[x0\]
--.*: a580a800 ld1sb \{z0\.d\}, p2/z, \[x0\]
--.*: a580a800 ld1sb \{z0\.d\}, p2/z, \[x0\]
--.*: a580bc00 ld1sb \{z0\.d\}, p7/z, \[x0\]
--.*: a580bc00 ld1sb \{z0\.d\}, p7/z, \[x0\]
--.*: a580bc00 ld1sb \{z0\.d\}, p7/z, \[x0\]
--.*: a580bc00 ld1sb \{z0\.d\}, p7/z, \[x0\]
--.*: a580a060 ld1sb \{z0\.d\}, p0/z, \[x3\]
--.*: a580a060 ld1sb \{z0\.d\}, p0/z, \[x3\]
--.*: a580a060 ld1sb \{z0\.d\}, p0/z, \[x3\]
--.*: a580a060 ld1sb \{z0\.d\}, p0/z, \[x3\]
--.*: a580a3e0 ld1sb \{z0\.d\}, p0/z, \[sp\]
--.*: a580a3e0 ld1sb \{z0\.d\}, p0/z, \[sp\]
--.*: a580a3e0 ld1sb \{z0\.d\}, p0/z, \[sp\]
--.*: a580a3e0 ld1sb \{z0\.d\}, p0/z, \[sp\]
--.*: a587a000 ld1sb \{z0\.d\}, p0/z, \[x0, #7, mul vl\]
--.*: a587a000 ld1sb \{z0\.d\}, p0/z, \[x0, #7, mul vl\]
--.*: a588a000 ld1sb \{z0\.d\}, p0/z, \[x0, #-8, mul vl\]
--.*: a588a000 ld1sb \{z0\.d\}, p0/z, \[x0, #-8, mul vl\]
--.*: a589a000 ld1sb \{z0\.d\}, p0/z, \[x0, #-7, mul vl\]
--.*: a589a000 ld1sb \{z0\.d\}, p0/z, \[x0, #-7, mul vl\]
--.*: a58fa000 ld1sb \{z0\.d\}, p0/z, \[x0, #-1, mul vl\]
--.*: a58fa000 ld1sb \{z0\.d\}, p0/z, \[x0, #-1, mul vl\]
--.*: a5a0a000 ld1sb \{z0\.s\}, p0/z, \[x0\]
--.*: a5a0a000 ld1sb \{z0\.s\}, p0/z, \[x0\]
--.*: a5a0a000 ld1sb \{z0\.s\}, p0/z, \[x0\]
--.*: a5a0a000 ld1sb \{z0\.s\}, p0/z, \[x0\]
--.*: a5a0a000 ld1sb \{z0\.s\}, p0/z, \[x0\]
--.*: a5a0a001 ld1sb \{z1\.s\}, p0/z, \[x0\]
--.*: a5a0a001 ld1sb \{z1\.s\}, p0/z, \[x0\]
--.*: a5a0a001 ld1sb \{z1\.s\}, p0/z, \[x0\]
--.*: a5a0a001 ld1sb \{z1\.s\}, p0/z, \[x0\]
--.*: a5a0a001 ld1sb \{z1\.s\}, p0/z, \[x0\]
--.*: a5a0a01f ld1sb \{z31\.s\}, p0/z, \[x0\]
--.*: a5a0a01f ld1sb \{z31\.s\}, p0/z, \[x0\]
--.*: a5a0a01f ld1sb \{z31\.s\}, p0/z, \[x0\]
--.*: a5a0a01f ld1sb \{z31\.s\}, p0/z, \[x0\]
--.*: a5a0a01f ld1sb \{z31\.s\}, p0/z, \[x0\]
--.*: a5a0a800 ld1sb \{z0\.s\}, p2/z, \[x0\]
--.*: a5a0a800 ld1sb \{z0\.s\}, p2/z, \[x0\]
--.*: a5a0a800 ld1sb \{z0\.s\}, p2/z, \[x0\]
--.*: a5a0a800 ld1sb \{z0\.s\}, p2/z, \[x0\]
--.*: a5a0bc00 ld1sb \{z0\.s\}, p7/z, \[x0\]
--.*: a5a0bc00 ld1sb \{z0\.s\}, p7/z, \[x0\]
--.*: a5a0bc00 ld1sb \{z0\.s\}, p7/z, \[x0\]
--.*: a5a0bc00 ld1sb \{z0\.s\}, p7/z, \[x0\]
--.*: a5a0a060 ld1sb \{z0\.s\}, p0/z, \[x3\]
--.*: a5a0a060 ld1sb \{z0\.s\}, p0/z, \[x3\]
--.*: a5a0a060 ld1sb \{z0\.s\}, p0/z, \[x3\]
--.*: a5a0a060 ld1sb \{z0\.s\}, p0/z, \[x3\]
--.*: a5a0a3e0 ld1sb \{z0\.s\}, p0/z, \[sp\]
--.*: a5a0a3e0 ld1sb \{z0\.s\}, p0/z, \[sp\]
--.*: a5a0a3e0 ld1sb \{z0\.s\}, p0/z, \[sp\]
--.*: a5a0a3e0 ld1sb \{z0\.s\}, p0/z, \[sp\]
--.*: a5a7a000 ld1sb \{z0\.s\}, p0/z, \[x0, #7, mul vl\]
--.*: a5a7a000 ld1sb \{z0\.s\}, p0/z, \[x0, #7, mul vl\]
--.*: a5a8a000 ld1sb \{z0\.s\}, p0/z, \[x0, #-8, mul vl\]
--.*: a5a8a000 ld1sb \{z0\.s\}, p0/z, \[x0, #-8, mul vl\]
--.*: a5a9a000 ld1sb \{z0\.s\}, p0/z, \[x0, #-7, mul vl\]
--.*: a5a9a000 ld1sb \{z0\.s\}, p0/z, \[x0, #-7, mul vl\]
--.*: a5afa000 ld1sb \{z0\.s\}, p0/z, \[x0, #-1, mul vl\]
--.*: a5afa000 ld1sb \{z0\.s\}, p0/z, \[x0, #-1, mul vl\]
--.*: a5c0a000 ld1sb \{z0\.h\}, p0/z, \[x0\]
--.*: a5c0a000 ld1sb \{z0\.h\}, p0/z, \[x0\]
--.*: a5c0a000 ld1sb \{z0\.h\}, p0/z, \[x0\]
--.*: a5c0a000 ld1sb \{z0\.h\}, p0/z, \[x0\]
--.*: a5c0a000 ld1sb \{z0\.h\}, p0/z, \[x0\]
--.*: a5c0a001 ld1sb \{z1\.h\}, p0/z, \[x0\]
--.*: a5c0a001 ld1sb \{z1\.h\}, p0/z, \[x0\]
--.*: a5c0a001 ld1sb \{z1\.h\}, p0/z, \[x0\]
--.*: a5c0a001 ld1sb \{z1\.h\}, p0/z, \[x0\]
--.*: a5c0a001 ld1sb \{z1\.h\}, p0/z, \[x0\]
--.*: a5c0a01f ld1sb \{z31\.h\}, p0/z, \[x0\]
--.*: a5c0a01f ld1sb \{z31\.h\}, p0/z, \[x0\]
--.*: a5c0a01f ld1sb \{z31\.h\}, p0/z, \[x0\]
--.*: a5c0a01f ld1sb \{z31\.h\}, p0/z, \[x0\]
--.*: a5c0a01f ld1sb \{z31\.h\}, p0/z, \[x0\]
--.*: a5c0a800 ld1sb \{z0\.h\}, p2/z, \[x0\]
--.*: a5c0a800 ld1sb \{z0\.h\}, p2/z, \[x0\]
--.*: a5c0a800 ld1sb \{z0\.h\}, p2/z, \[x0\]
--.*: a5c0a800 ld1sb \{z0\.h\}, p2/z, \[x0\]
--.*: a5c0bc00 ld1sb \{z0\.h\}, p7/z, \[x0\]
--.*: a5c0bc00 ld1sb \{z0\.h\}, p7/z, \[x0\]
--.*: a5c0bc00 ld1sb \{z0\.h\}, p7/z, \[x0\]
--.*: a5c0bc00 ld1sb \{z0\.h\}, p7/z, \[x0\]
--.*: a5c0a060 ld1sb \{z0\.h\}, p0/z, \[x3\]
--.*: a5c0a060 ld1sb \{z0\.h\}, p0/z, \[x3\]
--.*: a5c0a060 ld1sb \{z0\.h\}, p0/z, \[x3\]
--.*: a5c0a060 ld1sb \{z0\.h\}, p0/z, \[x3\]
--.*: a5c0a3e0 ld1sb \{z0\.h\}, p0/z, \[sp\]
--.*: a5c0a3e0 ld1sb \{z0\.h\}, p0/z, \[sp\]
--.*: a5c0a3e0 ld1sb \{z0\.h\}, p0/z, \[sp\]
--.*: a5c0a3e0 ld1sb \{z0\.h\}, p0/z, \[sp\]
--.*: a5c7a000 ld1sb \{z0\.h\}, p0/z, \[x0, #7, mul vl\]
--.*: a5c7a000 ld1sb \{z0\.h\}, p0/z, \[x0, #7, mul vl\]
--.*: a5c8a000 ld1sb \{z0\.h\}, p0/z, \[x0, #-8, mul vl\]
--.*: a5c8a000 ld1sb \{z0\.h\}, p0/z, \[x0, #-8, mul vl\]
--.*: a5c9a000 ld1sb \{z0\.h\}, p0/z, \[x0, #-7, mul vl\]
--.*: a5c9a000 ld1sb \{z0\.h\}, p0/z, \[x0, #-7, mul vl\]
--.*: a5cfa000 ld1sb \{z0\.h\}, p0/z, \[x0, #-1, mul vl\]
--.*: a5cfa000 ld1sb \{z0\.h\}, p0/z, \[x0, #-1, mul vl\]
--.*: c4208000 ld1sb \{z0\.d\}, p0/z, \[z0\.d\]
--.*: c4208000 ld1sb \{z0\.d\}, p0/z, \[z0\.d\]
--.*: c4208000 ld1sb \{z0\.d\}, p0/z, \[z0\.d\]
--.*: c4208000 ld1sb \{z0\.d\}, p0/z, \[z0\.d\]
--.*: c4208001 ld1sb \{z1\.d\}, p0/z, \[z0\.d\]
--.*: c4208001 ld1sb \{z1\.d\}, p0/z, \[z0\.d\]
--.*: c4208001 ld1sb \{z1\.d\}, p0/z, \[z0\.d\]
--.*: c4208001 ld1sb \{z1\.d\}, p0/z, \[z0\.d\]
--.*: c420801f ld1sb \{z31\.d\}, p0/z, \[z0\.d\]
--.*: c420801f ld1sb \{z31\.d\}, p0/z, \[z0\.d\]
--.*: c420801f ld1sb \{z31\.d\}, p0/z, \[z0\.d\]
--.*: c420801f ld1sb \{z31\.d\}, p0/z, \[z0\.d\]
--.*: c4208800 ld1sb \{z0\.d\}, p2/z, \[z0\.d\]
--.*: c4208800 ld1sb \{z0\.d\}, p2/z, \[z0\.d\]
--.*: c4208800 ld1sb \{z0\.d\}, p2/z, \[z0\.d\]
--.*: c4209c00 ld1sb \{z0\.d\}, p7/z, \[z0\.d\]
--.*: c4209c00 ld1sb \{z0\.d\}, p7/z, \[z0\.d\]
--.*: c4209c00 ld1sb \{z0\.d\}, p7/z, \[z0\.d\]
--.*: c4208060 ld1sb \{z0\.d\}, p0/z, \[z3\.d\]
--.*: c4208060 ld1sb \{z0\.d\}, p0/z, \[z3\.d\]
--.*: c4208060 ld1sb \{z0\.d\}, p0/z, \[z3\.d\]
--.*: c42083e0 ld1sb \{z0\.d\}, p0/z, \[z31\.d\]
--.*: c42083e0 ld1sb \{z0\.d\}, p0/z, \[z31\.d\]
--.*: c42083e0 ld1sb \{z0\.d\}, p0/z, \[z31\.d\]
--.*: c42f8000 ld1sb \{z0\.d\}, p0/z, \[z0\.d, #15\]
--.*: c42f8000 ld1sb \{z0\.d\}, p0/z, \[z0\.d, #15\]
--.*: c4308000 ld1sb \{z0\.d\}, p0/z, \[z0\.d, #16\]
--.*: c4308000 ld1sb \{z0\.d\}, p0/z, \[z0\.d, #16\]
--.*: c4318000 ld1sb \{z0\.d\}, p0/z, \[z0\.d, #17\]
--.*: c4318000 ld1sb \{z0\.d\}, p0/z, \[z0\.d, #17\]
--.*: c43f8000 ld1sb \{z0\.d\}, p0/z, \[z0\.d, #31\]
--.*: c43f8000 ld1sb \{z0\.d\}, p0/z, \[z0\.d, #31\]
--.*: 84800000 ld1sh \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 84800000 ld1sh \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 84800000 ld1sh \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 84800000 ld1sh \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 84800001 ld1sh \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 84800001 ld1sh \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 84800001 ld1sh \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 84800001 ld1sh \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 8480001f ld1sh \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 8480001f ld1sh \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 8480001f ld1sh \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 8480001f ld1sh \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 84800800 ld1sh \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\]
--.*: 84800800 ld1sh \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\]
--.*: 84800800 ld1sh \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\]
--.*: 84801c00 ld1sh \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\]
--.*: 84801c00 ld1sh \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\]
--.*: 84801c00 ld1sh \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\]
--.*: 84800060 ld1sh \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\]
--.*: 84800060 ld1sh \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\]
--.*: 84800060 ld1sh \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\]
--.*: 848003e0 ld1sh \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\]
--.*: 848003e0 ld1sh \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\]
--.*: 848003e0 ld1sh \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\]
--.*: 84840000 ld1sh \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\]
--.*: 84840000 ld1sh \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\]
--.*: 84840000 ld1sh \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\]
--.*: 849f0000 ld1sh \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\]
--.*: 849f0000 ld1sh \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\]
--.*: 849f0000 ld1sh \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\]
--.*: 84c00000 ld1sh \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 84c00000 ld1sh \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 84c00000 ld1sh \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 84c00000 ld1sh \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 84c00001 ld1sh \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 84c00001 ld1sh \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 84c00001 ld1sh \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 84c00001 ld1sh \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 84c0001f ld1sh \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 84c0001f ld1sh \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 84c0001f ld1sh \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 84c0001f ld1sh \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 84c00800 ld1sh \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\]
--.*: 84c00800 ld1sh \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\]
--.*: 84c00800 ld1sh \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\]
--.*: 84c01c00 ld1sh \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\]
--.*: 84c01c00 ld1sh \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\]
--.*: 84c01c00 ld1sh \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\]
--.*: 84c00060 ld1sh \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\]
--.*: 84c00060 ld1sh \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\]
--.*: 84c00060 ld1sh \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\]
--.*: 84c003e0 ld1sh \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\]
--.*: 84c003e0 ld1sh \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\]
--.*: 84c003e0 ld1sh \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\]
--.*: 84c40000 ld1sh \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\]
--.*: 84c40000 ld1sh \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\]
--.*: 84c40000 ld1sh \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\]
--.*: 84df0000 ld1sh \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\]
--.*: 84df0000 ld1sh \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\]
--.*: 84df0000 ld1sh \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\]
--.*: 84a00000 ld1sh \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw #1\]
--.*: 84a00000 ld1sh \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw #1\]
--.*: 84a00000 ld1sh \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw #1\]
--.*: 84a00001 ld1sh \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw #1\]
--.*: 84a00001 ld1sh \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw #1\]
--.*: 84a00001 ld1sh \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw #1\]
--.*: 84a0001f ld1sh \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw #1\]
--.*: 84a0001f ld1sh \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw #1\]
--.*: 84a0001f ld1sh \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw #1\]
--.*: 84a00800 ld1sh \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw #1\]
--.*: 84a00800 ld1sh \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw #1\]
--.*: 84a01c00 ld1sh \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw #1\]
--.*: 84a01c00 ld1sh \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw #1\]
--.*: 84a00060 ld1sh \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw #1\]
--.*: 84a00060 ld1sh \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw #1\]
--.*: 84a003e0 ld1sh \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw #1\]
--.*: 84a003e0 ld1sh \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw #1\]
--.*: 84a40000 ld1sh \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw #1\]
--.*: 84a40000 ld1sh \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw #1\]
--.*: 84bf0000 ld1sh \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw #1\]
--.*: 84bf0000 ld1sh \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw #1\]
--.*: 84e00000 ld1sh \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw #1\]
--.*: 84e00000 ld1sh \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw #1\]
--.*: 84e00000 ld1sh \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw #1\]
--.*: 84e00001 ld1sh \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw #1\]
--.*: 84e00001 ld1sh \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw #1\]
--.*: 84e00001 ld1sh \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw #1\]
--.*: 84e0001f ld1sh \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw #1\]
--.*: 84e0001f ld1sh \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw #1\]
--.*: 84e0001f ld1sh \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw #1\]
--.*: 84e00800 ld1sh \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw #1\]
--.*: 84e00800 ld1sh \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw #1\]
--.*: 84e01c00 ld1sh \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw #1\]
--.*: 84e01c00 ld1sh \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw #1\]
--.*: 84e00060 ld1sh \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw #1\]
--.*: 84e00060 ld1sh \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw #1\]
--.*: 84e003e0 ld1sh \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw #1\]
--.*: 84e003e0 ld1sh \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw #1\]
--.*: 84e40000 ld1sh \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw #1\]
--.*: 84e40000 ld1sh \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw #1\]
--.*: 84ff0000 ld1sh \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw #1\]
--.*: 84ff0000 ld1sh \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw #1\]
--.*: a5004000 ld1sh \{z0\.d\}, p0/z, \[x0, x0, lsl #1\]
--.*: a5004000 ld1sh \{z0\.d\}, p0/z, \[x0, x0, lsl #1\]
--.*: a5004000 ld1sh \{z0\.d\}, p0/z, \[x0, x0, lsl #1\]
--.*: a5004001 ld1sh \{z1\.d\}, p0/z, \[x0, x0, lsl #1\]
--.*: a5004001 ld1sh \{z1\.d\}, p0/z, \[x0, x0, lsl #1\]
--.*: a5004001 ld1sh \{z1\.d\}, p0/z, \[x0, x0, lsl #1\]
--.*: a500401f ld1sh \{z31\.d\}, p0/z, \[x0, x0, lsl #1\]
--.*: a500401f ld1sh \{z31\.d\}, p0/z, \[x0, x0, lsl #1\]
--.*: a500401f ld1sh \{z31\.d\}, p0/z, \[x0, x0, lsl #1\]
--.*: a5004800 ld1sh \{z0\.d\}, p2/z, \[x0, x0, lsl #1\]
--.*: a5004800 ld1sh \{z0\.d\}, p2/z, \[x0, x0, lsl #1\]
--.*: a5005c00 ld1sh \{z0\.d\}, p7/z, \[x0, x0, lsl #1\]
--.*: a5005c00 ld1sh \{z0\.d\}, p7/z, \[x0, x0, lsl #1\]
--.*: a5004060 ld1sh \{z0\.d\}, p0/z, \[x3, x0, lsl #1\]
--.*: a5004060 ld1sh \{z0\.d\}, p0/z, \[x3, x0, lsl #1\]
--.*: a50043e0 ld1sh \{z0\.d\}, p0/z, \[sp, x0, lsl #1\]
--.*: a50043e0 ld1sh \{z0\.d\}, p0/z, \[sp, x0, lsl #1\]
--.*: a5044000 ld1sh \{z0\.d\}, p0/z, \[x0, x4, lsl #1\]
--.*: a5044000 ld1sh \{z0\.d\}, p0/z, \[x0, x4, lsl #1\]
--.*: a51e4000 ld1sh \{z0\.d\}, p0/z, \[x0, x30, lsl #1\]
--.*: a51e4000 ld1sh \{z0\.d\}, p0/z, \[x0, x30, lsl #1\]
--.*: a5204000 ld1sh \{z0\.s\}, p0/z, \[x0, x0, lsl #1\]
--.*: a5204000 ld1sh \{z0\.s\}, p0/z, \[x0, x0, lsl #1\]
--.*: a5204000 ld1sh \{z0\.s\}, p0/z, \[x0, x0, lsl #1\]
--.*: a5204001 ld1sh \{z1\.s\}, p0/z, \[x0, x0, lsl #1\]
--.*: a5204001 ld1sh \{z1\.s\}, p0/z, \[x0, x0, lsl #1\]
--.*: a5204001 ld1sh \{z1\.s\}, p0/z, \[x0, x0, lsl #1\]
--.*: a520401f ld1sh \{z31\.s\}, p0/z, \[x0, x0, lsl #1\]
--.*: a520401f ld1sh \{z31\.s\}, p0/z, \[x0, x0, lsl #1\]
--.*: a520401f ld1sh \{z31\.s\}, p0/z, \[x0, x0, lsl #1\]
--.*: a5204800 ld1sh \{z0\.s\}, p2/z, \[x0, x0, lsl #1\]
--.*: a5204800 ld1sh \{z0\.s\}, p2/z, \[x0, x0, lsl #1\]
--.*: a5205c00 ld1sh \{z0\.s\}, p7/z, \[x0, x0, lsl #1\]
--.*: a5205c00 ld1sh \{z0\.s\}, p7/z, \[x0, x0, lsl #1\]
--.*: a5204060 ld1sh \{z0\.s\}, p0/z, \[x3, x0, lsl #1\]
--.*: a5204060 ld1sh \{z0\.s\}, p0/z, \[x3, x0, lsl #1\]
--.*: a52043e0 ld1sh \{z0\.s\}, p0/z, \[sp, x0, lsl #1\]
--.*: a52043e0 ld1sh \{z0\.s\}, p0/z, \[sp, x0, lsl #1\]
--.*: a5244000 ld1sh \{z0\.s\}, p0/z, \[x0, x4, lsl #1\]
--.*: a5244000 ld1sh \{z0\.s\}, p0/z, \[x0, x4, lsl #1\]
--.*: a53e4000 ld1sh \{z0\.s\}, p0/z, \[x0, x30, lsl #1\]
--.*: a53e4000 ld1sh \{z0\.s\}, p0/z, \[x0, x30, lsl #1\]
--.*: c4800000 ld1sh \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c4800000 ld1sh \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c4800000 ld1sh \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c4800000 ld1sh \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c4800001 ld1sh \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c4800001 ld1sh \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c4800001 ld1sh \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c4800001 ld1sh \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c480001f ld1sh \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c480001f ld1sh \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c480001f ld1sh \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c480001f ld1sh \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c4800800 ld1sh \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\]
--.*: c4800800 ld1sh \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\]
--.*: c4800800 ld1sh \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\]
--.*: c4801c00 ld1sh \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\]
--.*: c4801c00 ld1sh \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\]
--.*: c4801c00 ld1sh \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\]
--.*: c4800060 ld1sh \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\]
--.*: c4800060 ld1sh \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\]
--.*: c4800060 ld1sh \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\]
--.*: c48003e0 ld1sh \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\]
--.*: c48003e0 ld1sh \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\]
--.*: c48003e0 ld1sh \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\]
--.*: c4840000 ld1sh \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\]
--.*: c4840000 ld1sh \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\]
--.*: c4840000 ld1sh \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\]
--.*: c49f0000 ld1sh \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\]
--.*: c49f0000 ld1sh \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\]
--.*: c49f0000 ld1sh \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\]
--.*: c4c00000 ld1sh \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c4c00000 ld1sh \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c4c00000 ld1sh \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c4c00000 ld1sh \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c4c00001 ld1sh \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c4c00001 ld1sh \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c4c00001 ld1sh \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c4c00001 ld1sh \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c4c0001f ld1sh \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c4c0001f ld1sh \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c4c0001f ld1sh \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c4c0001f ld1sh \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c4c00800 ld1sh \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\]
--.*: c4c00800 ld1sh \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\]
--.*: c4c00800 ld1sh \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\]
--.*: c4c01c00 ld1sh \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\]
--.*: c4c01c00 ld1sh \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\]
--.*: c4c01c00 ld1sh \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\]
--.*: c4c00060 ld1sh \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\]
--.*: c4c00060 ld1sh \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\]
--.*: c4c00060 ld1sh \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\]
--.*: c4c003e0 ld1sh \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\]
--.*: c4c003e0 ld1sh \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\]
--.*: c4c003e0 ld1sh \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\]
--.*: c4c40000 ld1sh \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\]
--.*: c4c40000 ld1sh \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\]
--.*: c4c40000 ld1sh \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\]
--.*: c4df0000 ld1sh \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\]
--.*: c4df0000 ld1sh \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\]
--.*: c4df0000 ld1sh \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\]
--.*: c4a00000 ld1sh \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #1\]
--.*: c4a00000 ld1sh \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #1\]
--.*: c4a00000 ld1sh \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #1\]
--.*: c4a00001 ld1sh \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #1\]
--.*: c4a00001 ld1sh \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #1\]
--.*: c4a00001 ld1sh \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #1\]
--.*: c4a0001f ld1sh \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #1\]
--.*: c4a0001f ld1sh \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #1\]
--.*: c4a0001f ld1sh \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #1\]
--.*: c4a00800 ld1sh \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw #1\]
--.*: c4a00800 ld1sh \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw #1\]
--.*: c4a01c00 ld1sh \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw #1\]
--.*: c4a01c00 ld1sh \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw #1\]
--.*: c4a00060 ld1sh \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw #1\]
--.*: c4a00060 ld1sh \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw #1\]
--.*: c4a003e0 ld1sh \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw #1\]
--.*: c4a003e0 ld1sh \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw #1\]
--.*: c4a40000 ld1sh \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw #1\]
--.*: c4a40000 ld1sh \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw #1\]
--.*: c4bf0000 ld1sh \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw #1\]
--.*: c4bf0000 ld1sh \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw #1\]
--.*: c4e00000 ld1sh \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #1\]
--.*: c4e00000 ld1sh \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #1\]
--.*: c4e00000 ld1sh \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #1\]
--.*: c4e00001 ld1sh \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #1\]
--.*: c4e00001 ld1sh \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #1\]
--.*: c4e00001 ld1sh \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #1\]
--.*: c4e0001f ld1sh \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #1\]
--.*: c4e0001f ld1sh \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #1\]
--.*: c4e0001f ld1sh \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #1\]
--.*: c4e00800 ld1sh \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw #1\]
--.*: c4e00800 ld1sh \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw #1\]
--.*: c4e01c00 ld1sh \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw #1\]
--.*: c4e01c00 ld1sh \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw #1\]
--.*: c4e00060 ld1sh \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw #1\]
--.*: c4e00060 ld1sh \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw #1\]
--.*: c4e003e0 ld1sh \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw #1\]
--.*: c4e003e0 ld1sh \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw #1\]
--.*: c4e40000 ld1sh \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw #1\]
--.*: c4e40000 ld1sh \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw #1\]
--.*: c4ff0000 ld1sh \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw #1\]
--.*: c4ff0000 ld1sh \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw #1\]
--.*: c4c08000 ld1sh \{z0\.d\}, p0/z, \[x0, z0\.d\]
--.*: c4c08000 ld1sh \{z0\.d\}, p0/z, \[x0, z0\.d\]
--.*: c4c08000 ld1sh \{z0\.d\}, p0/z, \[x0, z0\.d\]
--.*: c4c08000 ld1sh \{z0\.d\}, p0/z, \[x0, z0\.d\]
--.*: c4c08001 ld1sh \{z1\.d\}, p0/z, \[x0, z0\.d\]
--.*: c4c08001 ld1sh \{z1\.d\}, p0/z, \[x0, z0\.d\]
--.*: c4c08001 ld1sh \{z1\.d\}, p0/z, \[x0, z0\.d\]
--.*: c4c08001 ld1sh \{z1\.d\}, p0/z, \[x0, z0\.d\]
--.*: c4c0801f ld1sh \{z31\.d\}, p0/z, \[x0, z0\.d\]
--.*: c4c0801f ld1sh \{z31\.d\}, p0/z, \[x0, z0\.d\]
--.*: c4c0801f ld1sh \{z31\.d\}, p0/z, \[x0, z0\.d\]
--.*: c4c0801f ld1sh \{z31\.d\}, p0/z, \[x0, z0\.d\]
--.*: c4c08800 ld1sh \{z0\.d\}, p2/z, \[x0, z0\.d\]
--.*: c4c08800 ld1sh \{z0\.d\}, p2/z, \[x0, z0\.d\]
--.*: c4c08800 ld1sh \{z0\.d\}, p2/z, \[x0, z0\.d\]
--.*: c4c09c00 ld1sh \{z0\.d\}, p7/z, \[x0, z0\.d\]
--.*: c4c09c00 ld1sh \{z0\.d\}, p7/z, \[x0, z0\.d\]
--.*: c4c09c00 ld1sh \{z0\.d\}, p7/z, \[x0, z0\.d\]
--.*: c4c08060 ld1sh \{z0\.d\}, p0/z, \[x3, z0\.d\]
--.*: c4c08060 ld1sh \{z0\.d\}, p0/z, \[x3, z0\.d\]
--.*: c4c08060 ld1sh \{z0\.d\}, p0/z, \[x3, z0\.d\]
--.*: c4c083e0 ld1sh \{z0\.d\}, p0/z, \[sp, z0\.d\]
--.*: c4c083e0 ld1sh \{z0\.d\}, p0/z, \[sp, z0\.d\]
--.*: c4c083e0 ld1sh \{z0\.d\}, p0/z, \[sp, z0\.d\]
--.*: c4c48000 ld1sh \{z0\.d\}, p0/z, \[x0, z4\.d\]
--.*: c4c48000 ld1sh \{z0\.d\}, p0/z, \[x0, z4\.d\]
--.*: c4c48000 ld1sh \{z0\.d\}, p0/z, \[x0, z4\.d\]
--.*: c4df8000 ld1sh \{z0\.d\}, p0/z, \[x0, z31\.d\]
--.*: c4df8000 ld1sh \{z0\.d\}, p0/z, \[x0, z31\.d\]
--.*: c4df8000 ld1sh \{z0\.d\}, p0/z, \[x0, z31\.d\]
--.*: c4e08000 ld1sh \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #1\]
--.*: c4e08000 ld1sh \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #1\]
--.*: c4e08000 ld1sh \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #1\]
--.*: c4e08001 ld1sh \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #1\]
--.*: c4e08001 ld1sh \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #1\]
--.*: c4e08001 ld1sh \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #1\]
--.*: c4e0801f ld1sh \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #1\]
--.*: c4e0801f ld1sh \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #1\]
--.*: c4e0801f ld1sh \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #1\]
--.*: c4e08800 ld1sh \{z0\.d\}, p2/z, \[x0, z0\.d, lsl #1\]
--.*: c4e08800 ld1sh \{z0\.d\}, p2/z, \[x0, z0\.d, lsl #1\]
--.*: c4e09c00 ld1sh \{z0\.d\}, p7/z, \[x0, z0\.d, lsl #1\]
--.*: c4e09c00 ld1sh \{z0\.d\}, p7/z, \[x0, z0\.d, lsl #1\]
--.*: c4e08060 ld1sh \{z0\.d\}, p0/z, \[x3, z0\.d, lsl #1\]
--.*: c4e08060 ld1sh \{z0\.d\}, p0/z, \[x3, z0\.d, lsl #1\]
--.*: c4e083e0 ld1sh \{z0\.d\}, p0/z, \[sp, z0\.d, lsl #1\]
--.*: c4e083e0 ld1sh \{z0\.d\}, p0/z, \[sp, z0\.d, lsl #1\]
--.*: c4e48000 ld1sh \{z0\.d\}, p0/z, \[x0, z4\.d, lsl #1\]
--.*: c4e48000 ld1sh \{z0\.d\}, p0/z, \[x0, z4\.d, lsl #1\]
--.*: c4ff8000 ld1sh \{z0\.d\}, p0/z, \[x0, z31\.d, lsl #1\]
--.*: c4ff8000 ld1sh \{z0\.d\}, p0/z, \[x0, z31\.d, lsl #1\]
--.*: 84a08000 ld1sh \{z0\.s\}, p0/z, \[z0\.s\]
--.*: 84a08000 ld1sh \{z0\.s\}, p0/z, \[z0\.s\]
--.*: 84a08000 ld1sh \{z0\.s\}, p0/z, \[z0\.s\]
--.*: 84a08000 ld1sh \{z0\.s\}, p0/z, \[z0\.s\]
--.*: 84a08001 ld1sh \{z1\.s\}, p0/z, \[z0\.s\]
--.*: 84a08001 ld1sh \{z1\.s\}, p0/z, \[z0\.s\]
--.*: 84a08001 ld1sh \{z1\.s\}, p0/z, \[z0\.s\]
--.*: 84a08001 ld1sh \{z1\.s\}, p0/z, \[z0\.s\]
--.*: 84a0801f ld1sh \{z31\.s\}, p0/z, \[z0\.s\]
--.*: 84a0801f ld1sh \{z31\.s\}, p0/z, \[z0\.s\]
--.*: 84a0801f ld1sh \{z31\.s\}, p0/z, \[z0\.s\]
--.*: 84a0801f ld1sh \{z31\.s\}, p0/z, \[z0\.s\]
--.*: 84a08800 ld1sh \{z0\.s\}, p2/z, \[z0\.s\]
--.*: 84a08800 ld1sh \{z0\.s\}, p2/z, \[z0\.s\]
--.*: 84a08800 ld1sh \{z0\.s\}, p2/z, \[z0\.s\]
--.*: 84a09c00 ld1sh \{z0\.s\}, p7/z, \[z0\.s\]
--.*: 84a09c00 ld1sh \{z0\.s\}, p7/z, \[z0\.s\]
--.*: 84a09c00 ld1sh \{z0\.s\}, p7/z, \[z0\.s\]
--.*: 84a08060 ld1sh \{z0\.s\}, p0/z, \[z3\.s\]
--.*: 84a08060 ld1sh \{z0\.s\}, p0/z, \[z3\.s\]
--.*: 84a08060 ld1sh \{z0\.s\}, p0/z, \[z3\.s\]
--.*: 84a083e0 ld1sh \{z0\.s\}, p0/z, \[z31\.s\]
--.*: 84a083e0 ld1sh \{z0\.s\}, p0/z, \[z31\.s\]
--.*: 84a083e0 ld1sh \{z0\.s\}, p0/z, \[z31\.s\]
--.*: 84af8000 ld1sh \{z0\.s\}, p0/z, \[z0\.s, #30\]
--.*: 84af8000 ld1sh \{z0\.s\}, p0/z, \[z0\.s, #30\]
--.*: 84b08000 ld1sh \{z0\.s\}, p0/z, \[z0\.s, #32\]
--.*: 84b08000 ld1sh \{z0\.s\}, p0/z, \[z0\.s, #32\]
--.*: 84b18000 ld1sh \{z0\.s\}, p0/z, \[z0\.s, #34\]
--.*: 84b18000 ld1sh \{z0\.s\}, p0/z, \[z0\.s, #34\]
--.*: 84bf8000 ld1sh \{z0\.s\}, p0/z, \[z0\.s, #62\]
--.*: 84bf8000 ld1sh \{z0\.s\}, p0/z, \[z0\.s, #62\]
--.*: a500a000 ld1sh \{z0\.d\}, p0/z, \[x0\]
--.*: a500a000 ld1sh \{z0\.d\}, p0/z, \[x0\]
--.*: a500a000 ld1sh \{z0\.d\}, p0/z, \[x0\]
--.*: a500a000 ld1sh \{z0\.d\}, p0/z, \[x0\]
--.*: a500a000 ld1sh \{z0\.d\}, p0/z, \[x0\]
--.*: a500a001 ld1sh \{z1\.d\}, p0/z, \[x0\]
--.*: a500a001 ld1sh \{z1\.d\}, p0/z, \[x0\]
--.*: a500a001 ld1sh \{z1\.d\}, p0/z, \[x0\]
--.*: a500a001 ld1sh \{z1\.d\}, p0/z, \[x0\]
--.*: a500a001 ld1sh \{z1\.d\}, p0/z, \[x0\]
--.*: a500a01f ld1sh \{z31\.d\}, p0/z, \[x0\]
--.*: a500a01f ld1sh \{z31\.d\}, p0/z, \[x0\]
--.*: a500a01f ld1sh \{z31\.d\}, p0/z, \[x0\]
--.*: a500a01f ld1sh \{z31\.d\}, p0/z, \[x0\]
--.*: a500a01f ld1sh \{z31\.d\}, p0/z, \[x0\]
--.*: a500a800 ld1sh \{z0\.d\}, p2/z, \[x0\]
--.*: a500a800 ld1sh \{z0\.d\}, p2/z, \[x0\]
--.*: a500a800 ld1sh \{z0\.d\}, p2/z, \[x0\]
--.*: a500a800 ld1sh \{z0\.d\}, p2/z, \[x0\]
--.*: a500bc00 ld1sh \{z0\.d\}, p7/z, \[x0\]
--.*: a500bc00 ld1sh \{z0\.d\}, p7/z, \[x0\]
--.*: a500bc00 ld1sh \{z0\.d\}, p7/z, \[x0\]
--.*: a500bc00 ld1sh \{z0\.d\}, p7/z, \[x0\]
--.*: a500a060 ld1sh \{z0\.d\}, p0/z, \[x3\]
--.*: a500a060 ld1sh \{z0\.d\}, p0/z, \[x3\]
--.*: a500a060 ld1sh \{z0\.d\}, p0/z, \[x3\]
--.*: a500a060 ld1sh \{z0\.d\}, p0/z, \[x3\]
--.*: a500a3e0 ld1sh \{z0\.d\}, p0/z, \[sp\]
--.*: a500a3e0 ld1sh \{z0\.d\}, p0/z, \[sp\]
--.*: a500a3e0 ld1sh \{z0\.d\}, p0/z, \[sp\]
--.*: a500a3e0 ld1sh \{z0\.d\}, p0/z, \[sp\]
--.*: a507a000 ld1sh \{z0\.d\}, p0/z, \[x0, #7, mul vl\]
--.*: a507a000 ld1sh \{z0\.d\}, p0/z, \[x0, #7, mul vl\]
--.*: a508a000 ld1sh \{z0\.d\}, p0/z, \[x0, #-8, mul vl\]
--.*: a508a000 ld1sh \{z0\.d\}, p0/z, \[x0, #-8, mul vl\]
--.*: a509a000 ld1sh \{z0\.d\}, p0/z, \[x0, #-7, mul vl\]
--.*: a509a000 ld1sh \{z0\.d\}, p0/z, \[x0, #-7, mul vl\]
--.*: a50fa000 ld1sh \{z0\.d\}, p0/z, \[x0, #-1, mul vl\]
--.*: a50fa000 ld1sh \{z0\.d\}, p0/z, \[x0, #-1, mul vl\]
--.*: a520a000 ld1sh \{z0\.s\}, p0/z, \[x0\]
--.*: a520a000 ld1sh \{z0\.s\}, p0/z, \[x0\]
--.*: a520a000 ld1sh \{z0\.s\}, p0/z, \[x0\]
--.*: a520a000 ld1sh \{z0\.s\}, p0/z, \[x0\]
--.*: a520a000 ld1sh \{z0\.s\}, p0/z, \[x0\]
--.*: a520a001 ld1sh \{z1\.s\}, p0/z, \[x0\]
--.*: a520a001 ld1sh \{z1\.s\}, p0/z, \[x0\]
--.*: a520a001 ld1sh \{z1\.s\}, p0/z, \[x0\]
--.*: a520a001 ld1sh \{z1\.s\}, p0/z, \[x0\]
--.*: a520a001 ld1sh \{z1\.s\}, p0/z, \[x0\]
--.*: a520a01f ld1sh \{z31\.s\}, p0/z, \[x0\]
--.*: a520a01f ld1sh \{z31\.s\}, p0/z, \[x0\]
--.*: a520a01f ld1sh \{z31\.s\}, p0/z, \[x0\]
--.*: a520a01f ld1sh \{z31\.s\}, p0/z, \[x0\]
--.*: a520a01f ld1sh \{z31\.s\}, p0/z, \[x0\]
--.*: a520a800 ld1sh \{z0\.s\}, p2/z, \[x0\]
--.*: a520a800 ld1sh \{z0\.s\}, p2/z, \[x0\]
--.*: a520a800 ld1sh \{z0\.s\}, p2/z, \[x0\]
--.*: a520a800 ld1sh \{z0\.s\}, p2/z, \[x0\]
--.*: a520bc00 ld1sh \{z0\.s\}, p7/z, \[x0\]
--.*: a520bc00 ld1sh \{z0\.s\}, p7/z, \[x0\]
--.*: a520bc00 ld1sh \{z0\.s\}, p7/z, \[x0\]
--.*: a520bc00 ld1sh \{z0\.s\}, p7/z, \[x0\]
--.*: a520a060 ld1sh \{z0\.s\}, p0/z, \[x3\]
--.*: a520a060 ld1sh \{z0\.s\}, p0/z, \[x3\]
--.*: a520a060 ld1sh \{z0\.s\}, p0/z, \[x3\]
--.*: a520a060 ld1sh \{z0\.s\}, p0/z, \[x3\]
--.*: a520a3e0 ld1sh \{z0\.s\}, p0/z, \[sp\]
--.*: a520a3e0 ld1sh \{z0\.s\}, p0/z, \[sp\]
--.*: a520a3e0 ld1sh \{z0\.s\}, p0/z, \[sp\]
--.*: a520a3e0 ld1sh \{z0\.s\}, p0/z, \[sp\]
--.*: a527a000 ld1sh \{z0\.s\}, p0/z, \[x0, #7, mul vl\]
--.*: a527a000 ld1sh \{z0\.s\}, p0/z, \[x0, #7, mul vl\]
--.*: a528a000 ld1sh \{z0\.s\}, p0/z, \[x0, #-8, mul vl\]
--.*: a528a000 ld1sh \{z0\.s\}, p0/z, \[x0, #-8, mul vl\]
--.*: a529a000 ld1sh \{z0\.s\}, p0/z, \[x0, #-7, mul vl\]
--.*: a529a000 ld1sh \{z0\.s\}, p0/z, \[x0, #-7, mul vl\]
--.*: a52fa000 ld1sh \{z0\.s\}, p0/z, \[x0, #-1, mul vl\]
--.*: a52fa000 ld1sh \{z0\.s\}, p0/z, \[x0, #-1, mul vl\]
--.*: c4a08000 ld1sh \{z0\.d\}, p0/z, \[z0\.d\]
--.*: c4a08000 ld1sh \{z0\.d\}, p0/z, \[z0\.d\]
--.*: c4a08000 ld1sh \{z0\.d\}, p0/z, \[z0\.d\]
--.*: c4a08000 ld1sh \{z0\.d\}, p0/z, \[z0\.d\]
--.*: c4a08001 ld1sh \{z1\.d\}, p0/z, \[z0\.d\]
--.*: c4a08001 ld1sh \{z1\.d\}, p0/z, \[z0\.d\]
--.*: c4a08001 ld1sh \{z1\.d\}, p0/z, \[z0\.d\]
--.*: c4a08001 ld1sh \{z1\.d\}, p0/z, \[z0\.d\]
--.*: c4a0801f ld1sh \{z31\.d\}, p0/z, \[z0\.d\]
--.*: c4a0801f ld1sh \{z31\.d\}, p0/z, \[z0\.d\]
--.*: c4a0801f ld1sh \{z31\.d\}, p0/z, \[z0\.d\]
--.*: c4a0801f ld1sh \{z31\.d\}, p0/z, \[z0\.d\]
--.*: c4a08800 ld1sh \{z0\.d\}, p2/z, \[z0\.d\]
--.*: c4a08800 ld1sh \{z0\.d\}, p2/z, \[z0\.d\]
--.*: c4a08800 ld1sh \{z0\.d\}, p2/z, \[z0\.d\]
--.*: c4a09c00 ld1sh \{z0\.d\}, p7/z, \[z0\.d\]
--.*: c4a09c00 ld1sh \{z0\.d\}, p7/z, \[z0\.d\]
--.*: c4a09c00 ld1sh \{z0\.d\}, p7/z, \[z0\.d\]
--.*: c4a08060 ld1sh \{z0\.d\}, p0/z, \[z3\.d\]
--.*: c4a08060 ld1sh \{z0\.d\}, p0/z, \[z3\.d\]
--.*: c4a08060 ld1sh \{z0\.d\}, p0/z, \[z3\.d\]
--.*: c4a083e0 ld1sh \{z0\.d\}, p0/z, \[z31\.d\]
--.*: c4a083e0 ld1sh \{z0\.d\}, p0/z, \[z31\.d\]
--.*: c4a083e0 ld1sh \{z0\.d\}, p0/z, \[z31\.d\]
--.*: c4af8000 ld1sh \{z0\.d\}, p0/z, \[z0\.d, #30\]
--.*: c4af8000 ld1sh \{z0\.d\}, p0/z, \[z0\.d, #30\]
--.*: c4b08000 ld1sh \{z0\.d\}, p0/z, \[z0\.d, #32\]
--.*: c4b08000 ld1sh \{z0\.d\}, p0/z, \[z0\.d, #32\]
--.*: c4b18000 ld1sh \{z0\.d\}, p0/z, \[z0\.d, #34\]
--.*: c4b18000 ld1sh \{z0\.d\}, p0/z, \[z0\.d, #34\]
--.*: c4bf8000 ld1sh \{z0\.d\}, p0/z, \[z0\.d, #62\]
--.*: c4bf8000 ld1sh \{z0\.d\}, p0/z, \[z0\.d, #62\]
--.*: a4804000 ld1sw \{z0\.d\}, p0/z, \[x0, x0, lsl #2\]
--.*: a4804000 ld1sw \{z0\.d\}, p0/z, \[x0, x0, lsl #2\]
--.*: a4804000 ld1sw \{z0\.d\}, p0/z, \[x0, x0, lsl #2\]
--.*: a4804001 ld1sw \{z1\.d\}, p0/z, \[x0, x0, lsl #2\]
--.*: a4804001 ld1sw \{z1\.d\}, p0/z, \[x0, x0, lsl #2\]
--.*: a4804001 ld1sw \{z1\.d\}, p0/z, \[x0, x0, lsl #2\]
--.*: a480401f ld1sw \{z31\.d\}, p0/z, \[x0, x0, lsl #2\]
--.*: a480401f ld1sw \{z31\.d\}, p0/z, \[x0, x0, lsl #2\]
--.*: a480401f ld1sw \{z31\.d\}, p0/z, \[x0, x0, lsl #2\]
--.*: a4804800 ld1sw \{z0\.d\}, p2/z, \[x0, x0, lsl #2\]
--.*: a4804800 ld1sw \{z0\.d\}, p2/z, \[x0, x0, lsl #2\]
--.*: a4805c00 ld1sw \{z0\.d\}, p7/z, \[x0, x0, lsl #2\]
--.*: a4805c00 ld1sw \{z0\.d\}, p7/z, \[x0, x0, lsl #2\]
--.*: a4804060 ld1sw \{z0\.d\}, p0/z, \[x3, x0, lsl #2\]
--.*: a4804060 ld1sw \{z0\.d\}, p0/z, \[x3, x0, lsl #2\]
--.*: a48043e0 ld1sw \{z0\.d\}, p0/z, \[sp, x0, lsl #2\]
--.*: a48043e0 ld1sw \{z0\.d\}, p0/z, \[sp, x0, lsl #2\]
--.*: a4844000 ld1sw \{z0\.d\}, p0/z, \[x0, x4, lsl #2\]
--.*: a4844000 ld1sw \{z0\.d\}, p0/z, \[x0, x4, lsl #2\]
--.*: a49e4000 ld1sw \{z0\.d\}, p0/z, \[x0, x30, lsl #2\]
--.*: a49e4000 ld1sw \{z0\.d\}, p0/z, \[x0, x30, lsl #2\]
--.*: c5000000 ld1sw \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c5000000 ld1sw \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c5000000 ld1sw \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c5000000 ld1sw \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c5000001 ld1sw \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c5000001 ld1sw \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c5000001 ld1sw \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c5000001 ld1sw \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c500001f ld1sw \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c500001f ld1sw \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c500001f ld1sw \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c500001f ld1sw \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c5000800 ld1sw \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\]
--.*: c5000800 ld1sw \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\]
--.*: c5000800 ld1sw \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\]
--.*: c5001c00 ld1sw \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\]
--.*: c5001c00 ld1sw \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\]
--.*: c5001c00 ld1sw \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\]
--.*: c5000060 ld1sw \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\]
--.*: c5000060 ld1sw \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\]
--.*: c5000060 ld1sw \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\]
--.*: c50003e0 ld1sw \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\]
--.*: c50003e0 ld1sw \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\]
--.*: c50003e0 ld1sw \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\]
--.*: c5040000 ld1sw \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\]
--.*: c5040000 ld1sw \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\]
--.*: c5040000 ld1sw \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\]
--.*: c51f0000 ld1sw \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\]
--.*: c51f0000 ld1sw \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\]
--.*: c51f0000 ld1sw \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\]
--.*: c5400000 ld1sw \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c5400000 ld1sw \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c5400000 ld1sw \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c5400000 ld1sw \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c5400001 ld1sw \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c5400001 ld1sw \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c5400001 ld1sw \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c5400001 ld1sw \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c540001f ld1sw \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c540001f ld1sw \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c540001f ld1sw \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c540001f ld1sw \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c5400800 ld1sw \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\]
--.*: c5400800 ld1sw \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\]
--.*: c5400800 ld1sw \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\]
--.*: c5401c00 ld1sw \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\]
--.*: c5401c00 ld1sw \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\]
--.*: c5401c00 ld1sw \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\]
--.*: c5400060 ld1sw \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\]
--.*: c5400060 ld1sw \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\]
--.*: c5400060 ld1sw \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\]
--.*: c54003e0 ld1sw \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\]
--.*: c54003e0 ld1sw \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\]
--.*: c54003e0 ld1sw \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\]
--.*: c5440000 ld1sw \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\]
--.*: c5440000 ld1sw \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\]
--.*: c5440000 ld1sw \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\]
--.*: c55f0000 ld1sw \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\]
--.*: c55f0000 ld1sw \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\]
--.*: c55f0000 ld1sw \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\]
--.*: c5200000 ld1sw \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #2\]
--.*: c5200000 ld1sw \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #2\]
--.*: c5200000 ld1sw \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #2\]
--.*: c5200001 ld1sw \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #2\]
--.*: c5200001 ld1sw \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #2\]
--.*: c5200001 ld1sw \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #2\]
--.*: c520001f ld1sw \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #2\]
--.*: c520001f ld1sw \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #2\]
--.*: c520001f ld1sw \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #2\]
--.*: c5200800 ld1sw \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw #2\]
--.*: c5200800 ld1sw \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw #2\]
--.*: c5201c00 ld1sw \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw #2\]
--.*: c5201c00 ld1sw \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw #2\]
--.*: c5200060 ld1sw \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw #2\]
--.*: c5200060 ld1sw \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw #2\]
--.*: c52003e0 ld1sw \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw #2\]
--.*: c52003e0 ld1sw \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw #2\]
--.*: c5240000 ld1sw \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw #2\]
--.*: c5240000 ld1sw \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw #2\]
--.*: c53f0000 ld1sw \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw #2\]
--.*: c53f0000 ld1sw \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw #2\]
--.*: c5600000 ld1sw \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #2\]
--.*: c5600000 ld1sw \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #2\]
--.*: c5600000 ld1sw \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #2\]
--.*: c5600001 ld1sw \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #2\]
--.*: c5600001 ld1sw \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #2\]
--.*: c5600001 ld1sw \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #2\]
--.*: c560001f ld1sw \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #2\]
--.*: c560001f ld1sw \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #2\]
--.*: c560001f ld1sw \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #2\]
--.*: c5600800 ld1sw \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw #2\]
--.*: c5600800 ld1sw \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw #2\]
--.*: c5601c00 ld1sw \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw #2\]
--.*: c5601c00 ld1sw \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw #2\]
--.*: c5600060 ld1sw \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw #2\]
--.*: c5600060 ld1sw \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw #2\]
--.*: c56003e0 ld1sw \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw #2\]
--.*: c56003e0 ld1sw \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw #2\]
--.*: c5640000 ld1sw \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw #2\]
--.*: c5640000 ld1sw \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw #2\]
--.*: c57f0000 ld1sw \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw #2\]
--.*: c57f0000 ld1sw \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw #2\]
--.*: c5408000 ld1sw \{z0\.d\}, p0/z, \[x0, z0\.d\]
--.*: c5408000 ld1sw \{z0\.d\}, p0/z, \[x0, z0\.d\]
--.*: c5408000 ld1sw \{z0\.d\}, p0/z, \[x0, z0\.d\]
--.*: c5408000 ld1sw \{z0\.d\}, p0/z, \[x0, z0\.d\]
--.*: c5408001 ld1sw \{z1\.d\}, p0/z, \[x0, z0\.d\]
--.*: c5408001 ld1sw \{z1\.d\}, p0/z, \[x0, z0\.d\]
--.*: c5408001 ld1sw \{z1\.d\}, p0/z, \[x0, z0\.d\]
--.*: c5408001 ld1sw \{z1\.d\}, p0/z, \[x0, z0\.d\]
--.*: c540801f ld1sw \{z31\.d\}, p0/z, \[x0, z0\.d\]
--.*: c540801f ld1sw \{z31\.d\}, p0/z, \[x0, z0\.d\]
--.*: c540801f ld1sw \{z31\.d\}, p0/z, \[x0, z0\.d\]
--.*: c540801f ld1sw \{z31\.d\}, p0/z, \[x0, z0\.d\]
--.*: c5408800 ld1sw \{z0\.d\}, p2/z, \[x0, z0\.d\]
--.*: c5408800 ld1sw \{z0\.d\}, p2/z, \[x0, z0\.d\]
--.*: c5408800 ld1sw \{z0\.d\}, p2/z, \[x0, z0\.d\]
--.*: c5409c00 ld1sw \{z0\.d\}, p7/z, \[x0, z0\.d\]
--.*: c5409c00 ld1sw \{z0\.d\}, p7/z, \[x0, z0\.d\]
--.*: c5409c00 ld1sw \{z0\.d\}, p7/z, \[x0, z0\.d\]
--.*: c5408060 ld1sw \{z0\.d\}, p0/z, \[x3, z0\.d\]
--.*: c5408060 ld1sw \{z0\.d\}, p0/z, \[x3, z0\.d\]
--.*: c5408060 ld1sw \{z0\.d\}, p0/z, \[x3, z0\.d\]
--.*: c54083e0 ld1sw \{z0\.d\}, p0/z, \[sp, z0\.d\]
--.*: c54083e0 ld1sw \{z0\.d\}, p0/z, \[sp, z0\.d\]
--.*: c54083e0 ld1sw \{z0\.d\}, p0/z, \[sp, z0\.d\]
--.*: c5448000 ld1sw \{z0\.d\}, p0/z, \[x0, z4\.d\]
--.*: c5448000 ld1sw \{z0\.d\}, p0/z, \[x0, z4\.d\]
--.*: c5448000 ld1sw \{z0\.d\}, p0/z, \[x0, z4\.d\]
--.*: c55f8000 ld1sw \{z0\.d\}, p0/z, \[x0, z31\.d\]
--.*: c55f8000 ld1sw \{z0\.d\}, p0/z, \[x0, z31\.d\]
--.*: c55f8000 ld1sw \{z0\.d\}, p0/z, \[x0, z31\.d\]
--.*: c5608000 ld1sw \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #2\]
--.*: c5608000 ld1sw \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #2\]
--.*: c5608000 ld1sw \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #2\]
--.*: c5608001 ld1sw \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #2\]
--.*: c5608001 ld1sw \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #2\]
--.*: c5608001 ld1sw \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #2\]
--.*: c560801f ld1sw \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #2\]
--.*: c560801f ld1sw \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #2\]
--.*: c560801f ld1sw \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #2\]
--.*: c5608800 ld1sw \{z0\.d\}, p2/z, \[x0, z0\.d, lsl #2\]
--.*: c5608800 ld1sw \{z0\.d\}, p2/z, \[x0, z0\.d, lsl #2\]
--.*: c5609c00 ld1sw \{z0\.d\}, p7/z, \[x0, z0\.d, lsl #2\]
--.*: c5609c00 ld1sw \{z0\.d\}, p7/z, \[x0, z0\.d, lsl #2\]
--.*: c5608060 ld1sw \{z0\.d\}, p0/z, \[x3, z0\.d, lsl #2\]
--.*: c5608060 ld1sw \{z0\.d\}, p0/z, \[x3, z0\.d, lsl #2\]
--.*: c56083e0 ld1sw \{z0\.d\}, p0/z, \[sp, z0\.d, lsl #2\]
--.*: c56083e0 ld1sw \{z0\.d\}, p0/z, \[sp, z0\.d, lsl #2\]
--.*: c5648000 ld1sw \{z0\.d\}, p0/z, \[x0, z4\.d, lsl #2\]
--.*: c5648000 ld1sw \{z0\.d\}, p0/z, \[x0, z4\.d, lsl #2\]
--.*: c57f8000 ld1sw \{z0\.d\}, p0/z, \[x0, z31\.d, lsl #2\]
--.*: c57f8000 ld1sw \{z0\.d\}, p0/z, \[x0, z31\.d, lsl #2\]
--.*: a480a000 ld1sw \{z0\.d\}, p0/z, \[x0\]
--.*: a480a000 ld1sw \{z0\.d\}, p0/z, \[x0\]
--.*: a480a000 ld1sw \{z0\.d\}, p0/z, \[x0\]
--.*: a480a000 ld1sw \{z0\.d\}, p0/z, \[x0\]
--.*: a480a000 ld1sw \{z0\.d\}, p0/z, \[x0\]
--.*: a480a001 ld1sw \{z1\.d\}, p0/z, \[x0\]
--.*: a480a001 ld1sw \{z1\.d\}, p0/z, \[x0\]
--.*: a480a001 ld1sw \{z1\.d\}, p0/z, \[x0\]
--.*: a480a001 ld1sw \{z1\.d\}, p0/z, \[x0\]
--.*: a480a001 ld1sw \{z1\.d\}, p0/z, \[x0\]
--.*: a480a01f ld1sw \{z31\.d\}, p0/z, \[x0\]
--.*: a480a01f ld1sw \{z31\.d\}, p0/z, \[x0\]
--.*: a480a01f ld1sw \{z31\.d\}, p0/z, \[x0\]
--.*: a480a01f ld1sw \{z31\.d\}, p0/z, \[x0\]
--.*: a480a01f ld1sw \{z31\.d\}, p0/z, \[x0\]
--.*: a480a800 ld1sw \{z0\.d\}, p2/z, \[x0\]
--.*: a480a800 ld1sw \{z0\.d\}, p2/z, \[x0\]
--.*: a480a800 ld1sw \{z0\.d\}, p2/z, \[x0\]
--.*: a480a800 ld1sw \{z0\.d\}, p2/z, \[x0\]
--.*: a480bc00 ld1sw \{z0\.d\}, p7/z, \[x0\]
--.*: a480bc00 ld1sw \{z0\.d\}, p7/z, \[x0\]
--.*: a480bc00 ld1sw \{z0\.d\}, p7/z, \[x0\]
--.*: a480bc00 ld1sw \{z0\.d\}, p7/z, \[x0\]
--.*: a480a060 ld1sw \{z0\.d\}, p0/z, \[x3\]
--.*: a480a060 ld1sw \{z0\.d\}, p0/z, \[x3\]
--.*: a480a060 ld1sw \{z0\.d\}, p0/z, \[x3\]
--.*: a480a060 ld1sw \{z0\.d\}, p0/z, \[x3\]
--.*: a480a3e0 ld1sw \{z0\.d\}, p0/z, \[sp\]
--.*: a480a3e0 ld1sw \{z0\.d\}, p0/z, \[sp\]
--.*: a480a3e0 ld1sw \{z0\.d\}, p0/z, \[sp\]
--.*: a480a3e0 ld1sw \{z0\.d\}, p0/z, \[sp\]
--.*: a487a000 ld1sw \{z0\.d\}, p0/z, \[x0, #7, mul vl\]
--.*: a487a000 ld1sw \{z0\.d\}, p0/z, \[x0, #7, mul vl\]
--.*: a488a000 ld1sw \{z0\.d\}, p0/z, \[x0, #-8, mul vl\]
--.*: a488a000 ld1sw \{z0\.d\}, p0/z, \[x0, #-8, mul vl\]
--.*: a489a000 ld1sw \{z0\.d\}, p0/z, \[x0, #-7, mul vl\]
--.*: a489a000 ld1sw \{z0\.d\}, p0/z, \[x0, #-7, mul vl\]
--.*: a48fa000 ld1sw \{z0\.d\}, p0/z, \[x0, #-1, mul vl\]
--.*: a48fa000 ld1sw \{z0\.d\}, p0/z, \[x0, #-1, mul vl\]
--.*: c5208000 ld1sw \{z0\.d\}, p0/z, \[z0\.d\]
--.*: c5208000 ld1sw \{z0\.d\}, p0/z, \[z0\.d\]
--.*: c5208000 ld1sw \{z0\.d\}, p0/z, \[z0\.d\]
--.*: c5208000 ld1sw \{z0\.d\}, p0/z, \[z0\.d\]
--.*: c5208001 ld1sw \{z1\.d\}, p0/z, \[z0\.d\]
--.*: c5208001 ld1sw \{z1\.d\}, p0/z, \[z0\.d\]
--.*: c5208001 ld1sw \{z1\.d\}, p0/z, \[z0\.d\]
--.*: c5208001 ld1sw \{z1\.d\}, p0/z, \[z0\.d\]
--.*: c520801f ld1sw \{z31\.d\}, p0/z, \[z0\.d\]
--.*: c520801f ld1sw \{z31\.d\}, p0/z, \[z0\.d\]
--.*: c520801f ld1sw \{z31\.d\}, p0/z, \[z0\.d\]
--.*: c520801f ld1sw \{z31\.d\}, p0/z, \[z0\.d\]
--.*: c5208800 ld1sw \{z0\.d\}, p2/z, \[z0\.d\]
--.*: c5208800 ld1sw \{z0\.d\}, p2/z, \[z0\.d\]
--.*: c5208800 ld1sw \{z0\.d\}, p2/z, \[z0\.d\]
--.*: c5209c00 ld1sw \{z0\.d\}, p7/z, \[z0\.d\]
--.*: c5209c00 ld1sw \{z0\.d\}, p7/z, \[z0\.d\]
--.*: c5209c00 ld1sw \{z0\.d\}, p7/z, \[z0\.d\]
--.*: c5208060 ld1sw \{z0\.d\}, p0/z, \[z3\.d\]
--.*: c5208060 ld1sw \{z0\.d\}, p0/z, \[z3\.d\]
--.*: c5208060 ld1sw \{z0\.d\}, p0/z, \[z3\.d\]
--.*: c52083e0 ld1sw \{z0\.d\}, p0/z, \[z31\.d\]
--.*: c52083e0 ld1sw \{z0\.d\}, p0/z, \[z31\.d\]
--.*: c52083e0 ld1sw \{z0\.d\}, p0/z, \[z31\.d\]
--.*: c52f8000 ld1sw \{z0\.d\}, p0/z, \[z0\.d, #60\]
--.*: c52f8000 ld1sw \{z0\.d\}, p0/z, \[z0\.d, #60\]
--.*: c5308000 ld1sw \{z0\.d\}, p0/z, \[z0\.d, #64\]
--.*: c5308000 ld1sw \{z0\.d\}, p0/z, \[z0\.d, #64\]
--.*: c5318000 ld1sw \{z0\.d\}, p0/z, \[z0\.d, #68\]
--.*: c5318000 ld1sw \{z0\.d\}, p0/z, \[z0\.d, #68\]
--.*: c53f8000 ld1sw \{z0\.d\}, p0/z, \[z0\.d, #124\]
--.*: c53f8000 ld1sw \{z0\.d\}, p0/z, \[z0\.d, #124\]
--.*: 85004000 ld1w \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 85004000 ld1w \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 85004000 ld1w \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 85004000 ld1w \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 85004001 ld1w \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 85004001 ld1w \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 85004001 ld1w \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 85004001 ld1w \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 8500401f ld1w \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 8500401f ld1w \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 8500401f ld1w \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 8500401f ld1w \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 85004800 ld1w \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\]
--.*: 85004800 ld1w \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\]
--.*: 85004800 ld1w \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\]
--.*: 85005c00 ld1w \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\]
--.*: 85005c00 ld1w \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\]
--.*: 85005c00 ld1w \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\]
--.*: 85004060 ld1w \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\]
--.*: 85004060 ld1w \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\]
--.*: 85004060 ld1w \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\]
--.*: 850043e0 ld1w \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\]
--.*: 850043e0 ld1w \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\]
--.*: 850043e0 ld1w \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\]
--.*: 85044000 ld1w \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\]
--.*: 85044000 ld1w \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\]
--.*: 85044000 ld1w \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\]
--.*: 851f4000 ld1w \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\]
--.*: 851f4000 ld1w \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\]
--.*: 851f4000 ld1w \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\]
--.*: 85404000 ld1w \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 85404000 ld1w \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 85404000 ld1w \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 85404000 ld1w \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 85404001 ld1w \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 85404001 ld1w \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 85404001 ld1w \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 85404001 ld1w \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 8540401f ld1w \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 8540401f ld1w \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 8540401f ld1w \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 8540401f ld1w \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 85404800 ld1w \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\]
--.*: 85404800 ld1w \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\]
--.*: 85404800 ld1w \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\]
--.*: 85405c00 ld1w \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\]
--.*: 85405c00 ld1w \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\]
--.*: 85405c00 ld1w \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\]
--.*: 85404060 ld1w \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\]
--.*: 85404060 ld1w \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\]
--.*: 85404060 ld1w \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\]
--.*: 854043e0 ld1w \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\]
--.*: 854043e0 ld1w \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\]
--.*: 854043e0 ld1w \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\]
--.*: 85444000 ld1w \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\]
--.*: 85444000 ld1w \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\]
--.*: 85444000 ld1w \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\]
--.*: 855f4000 ld1w \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\]
--.*: 855f4000 ld1w \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\]
--.*: 855f4000 ld1w \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\]
--.*: 85204000 ld1w \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw #2\]
--.*: 85204000 ld1w \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw #2\]
--.*: 85204000 ld1w \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw #2\]
--.*: 85204001 ld1w \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw #2\]
--.*: 85204001 ld1w \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw #2\]
--.*: 85204001 ld1w \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw #2\]
--.*: 8520401f ld1w \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw #2\]
--.*: 8520401f ld1w \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw #2\]
--.*: 8520401f ld1w \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw #2\]
--.*: 85204800 ld1w \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw #2\]
--.*: 85204800 ld1w \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw #2\]
--.*: 85205c00 ld1w \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw #2\]
--.*: 85205c00 ld1w \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw #2\]
--.*: 85204060 ld1w \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw #2\]
--.*: 85204060 ld1w \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw #2\]
--.*: 852043e0 ld1w \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw #2\]
--.*: 852043e0 ld1w \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw #2\]
--.*: 85244000 ld1w \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw #2\]
--.*: 85244000 ld1w \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw #2\]
--.*: 853f4000 ld1w \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw #2\]
--.*: 853f4000 ld1w \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw #2\]
--.*: 85604000 ld1w \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw #2\]
--.*: 85604000 ld1w \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw #2\]
--.*: 85604000 ld1w \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw #2\]
--.*: 85604001 ld1w \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw #2\]
--.*: 85604001 ld1w \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw #2\]
--.*: 85604001 ld1w \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw #2\]
--.*: 8560401f ld1w \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw #2\]
--.*: 8560401f ld1w \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw #2\]
--.*: 8560401f ld1w \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw #2\]
--.*: 85604800 ld1w \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw #2\]
--.*: 85604800 ld1w \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw #2\]
--.*: 85605c00 ld1w \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw #2\]
--.*: 85605c00 ld1w \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw #2\]
--.*: 85604060 ld1w \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw #2\]
--.*: 85604060 ld1w \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw #2\]
--.*: 856043e0 ld1w \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw #2\]
--.*: 856043e0 ld1w \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw #2\]
--.*: 85644000 ld1w \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw #2\]
--.*: 85644000 ld1w \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw #2\]
--.*: 857f4000 ld1w \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw #2\]
--.*: 857f4000 ld1w \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw #2\]
--.*: a5404000 ld1w \{z0\.s\}, p0/z, \[x0, x0, lsl #2\]
--.*: a5404000 ld1w \{z0\.s\}, p0/z, \[x0, x0, lsl #2\]
--.*: a5404000 ld1w \{z0\.s\}, p0/z, \[x0, x0, lsl #2\]
--.*: a5404001 ld1w \{z1\.s\}, p0/z, \[x0, x0, lsl #2\]
--.*: a5404001 ld1w \{z1\.s\}, p0/z, \[x0, x0, lsl #2\]
--.*: a5404001 ld1w \{z1\.s\}, p0/z, \[x0, x0, lsl #2\]
--.*: a540401f ld1w \{z31\.s\}, p0/z, \[x0, x0, lsl #2\]
--.*: a540401f ld1w \{z31\.s\}, p0/z, \[x0, x0, lsl #2\]
--.*: a540401f ld1w \{z31\.s\}, p0/z, \[x0, x0, lsl #2\]
--.*: a5404800 ld1w \{z0\.s\}, p2/z, \[x0, x0, lsl #2\]
--.*: a5404800 ld1w \{z0\.s\}, p2/z, \[x0, x0, lsl #2\]
--.*: a5405c00 ld1w \{z0\.s\}, p7/z, \[x0, x0, lsl #2\]
--.*: a5405c00 ld1w \{z0\.s\}, p7/z, \[x0, x0, lsl #2\]
--.*: a5404060 ld1w \{z0\.s\}, p0/z, \[x3, x0, lsl #2\]
--.*: a5404060 ld1w \{z0\.s\}, p0/z, \[x3, x0, lsl #2\]
--.*: a54043e0 ld1w \{z0\.s\}, p0/z, \[sp, x0, lsl #2\]
--.*: a54043e0 ld1w \{z0\.s\}, p0/z, \[sp, x0, lsl #2\]
--.*: a5444000 ld1w \{z0\.s\}, p0/z, \[x0, x4, lsl #2\]
--.*: a5444000 ld1w \{z0\.s\}, p0/z, \[x0, x4, lsl #2\]
--.*: a55e4000 ld1w \{z0\.s\}, p0/z, \[x0, x30, lsl #2\]
--.*: a55e4000 ld1w \{z0\.s\}, p0/z, \[x0, x30, lsl #2\]
--.*: a5604000 ld1w \{z0\.d\}, p0/z, \[x0, x0, lsl #2\]
--.*: a5604000 ld1w \{z0\.d\}, p0/z, \[x0, x0, lsl #2\]
--.*: a5604000 ld1w \{z0\.d\}, p0/z, \[x0, x0, lsl #2\]
--.*: a5604001 ld1w \{z1\.d\}, p0/z, \[x0, x0, lsl #2\]
--.*: a5604001 ld1w \{z1\.d\}, p0/z, \[x0, x0, lsl #2\]
--.*: a5604001 ld1w \{z1\.d\}, p0/z, \[x0, x0, lsl #2\]
--.*: a560401f ld1w \{z31\.d\}, p0/z, \[x0, x0, lsl #2\]
--.*: a560401f ld1w \{z31\.d\}, p0/z, \[x0, x0, lsl #2\]
--.*: a560401f ld1w \{z31\.d\}, p0/z, \[x0, x0, lsl #2\]
--.*: a5604800 ld1w \{z0\.d\}, p2/z, \[x0, x0, lsl #2\]
--.*: a5604800 ld1w \{z0\.d\}, p2/z, \[x0, x0, lsl #2\]
--.*: a5605c00 ld1w \{z0\.d\}, p7/z, \[x0, x0, lsl #2\]
--.*: a5605c00 ld1w \{z0\.d\}, p7/z, \[x0, x0, lsl #2\]
--.*: a5604060 ld1w \{z0\.d\}, p0/z, \[x3, x0, lsl #2\]
--.*: a5604060 ld1w \{z0\.d\}, p0/z, \[x3, x0, lsl #2\]
--.*: a56043e0 ld1w \{z0\.d\}, p0/z, \[sp, x0, lsl #2\]
--.*: a56043e0 ld1w \{z0\.d\}, p0/z, \[sp, x0, lsl #2\]
--.*: a5644000 ld1w \{z0\.d\}, p0/z, \[x0, x4, lsl #2\]
--.*: a5644000 ld1w \{z0\.d\}, p0/z, \[x0, x4, lsl #2\]
--.*: a57e4000 ld1w \{z0\.d\}, p0/z, \[x0, x30, lsl #2\]
--.*: a57e4000 ld1w \{z0\.d\}, p0/z, \[x0, x30, lsl #2\]
--.*: c5004000 ld1w \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c5004000 ld1w \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c5004000 ld1w \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c5004000 ld1w \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c5004001 ld1w \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c5004001 ld1w \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c5004001 ld1w \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c5004001 ld1w \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c500401f ld1w \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c500401f ld1w \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c500401f ld1w \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c500401f ld1w \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c5004800 ld1w \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\]
--.*: c5004800 ld1w \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\]
--.*: c5004800 ld1w \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\]
--.*: c5005c00 ld1w \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\]
--.*: c5005c00 ld1w \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\]
--.*: c5005c00 ld1w \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\]
--.*: c5004060 ld1w \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\]
--.*: c5004060 ld1w \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\]
--.*: c5004060 ld1w \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\]
--.*: c50043e0 ld1w \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\]
--.*: c50043e0 ld1w \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\]
--.*: c50043e0 ld1w \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\]
--.*: c5044000 ld1w \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\]
--.*: c5044000 ld1w \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\]
--.*: c5044000 ld1w \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\]
--.*: c51f4000 ld1w \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\]
--.*: c51f4000 ld1w \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\]
--.*: c51f4000 ld1w \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\]
--.*: c5404000 ld1w \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c5404000 ld1w \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c5404000 ld1w \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c5404000 ld1w \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c5404001 ld1w \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c5404001 ld1w \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c5404001 ld1w \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c5404001 ld1w \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c540401f ld1w \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c540401f ld1w \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c540401f ld1w \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c540401f ld1w \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c5404800 ld1w \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\]
--.*: c5404800 ld1w \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\]
--.*: c5404800 ld1w \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\]
--.*: c5405c00 ld1w \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\]
--.*: c5405c00 ld1w \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\]
--.*: c5405c00 ld1w \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\]
--.*: c5404060 ld1w \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\]
--.*: c5404060 ld1w \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\]
--.*: c5404060 ld1w \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\]
--.*: c54043e0 ld1w \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\]
--.*: c54043e0 ld1w \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\]
--.*: c54043e0 ld1w \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\]
--.*: c5444000 ld1w \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\]
--.*: c5444000 ld1w \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\]
--.*: c5444000 ld1w \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\]
--.*: c55f4000 ld1w \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\]
--.*: c55f4000 ld1w \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\]
--.*: c55f4000 ld1w \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\]
--.*: c5204000 ld1w \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #2\]
--.*: c5204000 ld1w \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #2\]
--.*: c5204000 ld1w \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #2\]
--.*: c5204001 ld1w \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #2\]
--.*: c5204001 ld1w \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #2\]
--.*: c5204001 ld1w \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #2\]
--.*: c520401f ld1w \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #2\]
--.*: c520401f ld1w \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #2\]
--.*: c520401f ld1w \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #2\]
--.*: c5204800 ld1w \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw #2\]
--.*: c5204800 ld1w \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw #2\]
--.*: c5205c00 ld1w \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw #2\]
--.*: c5205c00 ld1w \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw #2\]
--.*: c5204060 ld1w \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw #2\]
--.*: c5204060 ld1w \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw #2\]
--.*: c52043e0 ld1w \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw #2\]
--.*: c52043e0 ld1w \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw #2\]
--.*: c5244000 ld1w \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw #2\]
--.*: c5244000 ld1w \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw #2\]
--.*: c53f4000 ld1w \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw #2\]
--.*: c53f4000 ld1w \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw #2\]
--.*: c5604000 ld1w \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #2\]
--.*: c5604000 ld1w \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #2\]
--.*: c5604000 ld1w \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #2\]
--.*: c5604001 ld1w \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #2\]
--.*: c5604001 ld1w \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #2\]
--.*: c5604001 ld1w \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #2\]
--.*: c560401f ld1w \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #2\]
--.*: c560401f ld1w \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #2\]
--.*: c560401f ld1w \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #2\]
--.*: c5604800 ld1w \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw #2\]
--.*: c5604800 ld1w \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw #2\]
--.*: c5605c00 ld1w \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw #2\]
--.*: c5605c00 ld1w \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw #2\]
--.*: c5604060 ld1w \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw #2\]
--.*: c5604060 ld1w \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw #2\]
--.*: c56043e0 ld1w \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw #2\]
--.*: c56043e0 ld1w \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw #2\]
--.*: c5644000 ld1w \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw #2\]
--.*: c5644000 ld1w \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw #2\]
--.*: c57f4000 ld1w \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw #2\]
--.*: c57f4000 ld1w \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw #2\]
--.*: c540c000 ld1w \{z0\.d\}, p0/z, \[x0, z0\.d\]
--.*: c540c000 ld1w \{z0\.d\}, p0/z, \[x0, z0\.d\]
--.*: c540c000 ld1w \{z0\.d\}, p0/z, \[x0, z0\.d\]
--.*: c540c000 ld1w \{z0\.d\}, p0/z, \[x0, z0\.d\]
--.*: c540c001 ld1w \{z1\.d\}, p0/z, \[x0, z0\.d\]
--.*: c540c001 ld1w \{z1\.d\}, p0/z, \[x0, z0\.d\]
--.*: c540c001 ld1w \{z1\.d\}, p0/z, \[x0, z0\.d\]
--.*: c540c001 ld1w \{z1\.d\}, p0/z, \[x0, z0\.d\]
--.*: c540c01f ld1w \{z31\.d\}, p0/z, \[x0, z0\.d\]
--.*: c540c01f ld1w \{z31\.d\}, p0/z, \[x0, z0\.d\]
--.*: c540c01f ld1w \{z31\.d\}, p0/z, \[x0, z0\.d\]
--.*: c540c01f ld1w \{z31\.d\}, p0/z, \[x0, z0\.d\]
--.*: c540c800 ld1w \{z0\.d\}, p2/z, \[x0, z0\.d\]
--.*: c540c800 ld1w \{z0\.d\}, p2/z, \[x0, z0\.d\]
--.*: c540c800 ld1w \{z0\.d\}, p2/z, \[x0, z0\.d\]
--.*: c540dc00 ld1w \{z0\.d\}, p7/z, \[x0, z0\.d\]
--.*: c540dc00 ld1w \{z0\.d\}, p7/z, \[x0, z0\.d\]
--.*: c540dc00 ld1w \{z0\.d\}, p7/z, \[x0, z0\.d\]
--.*: c540c060 ld1w \{z0\.d\}, p0/z, \[x3, z0\.d\]
--.*: c540c060 ld1w \{z0\.d\}, p0/z, \[x3, z0\.d\]
--.*: c540c060 ld1w \{z0\.d\}, p0/z, \[x3, z0\.d\]
--.*: c540c3e0 ld1w \{z0\.d\}, p0/z, \[sp, z0\.d\]
--.*: c540c3e0 ld1w \{z0\.d\}, p0/z, \[sp, z0\.d\]
--.*: c540c3e0 ld1w \{z0\.d\}, p0/z, \[sp, z0\.d\]
--.*: c544c000 ld1w \{z0\.d\}, p0/z, \[x0, z4\.d\]
--.*: c544c000 ld1w \{z0\.d\}, p0/z, \[x0, z4\.d\]
--.*: c544c000 ld1w \{z0\.d\}, p0/z, \[x0, z4\.d\]
--.*: c55fc000 ld1w \{z0\.d\}, p0/z, \[x0, z31\.d\]
--.*: c55fc000 ld1w \{z0\.d\}, p0/z, \[x0, z31\.d\]
--.*: c55fc000 ld1w \{z0\.d\}, p0/z, \[x0, z31\.d\]
--.*: c560c000 ld1w \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #2\]
--.*: c560c000 ld1w \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #2\]
--.*: c560c000 ld1w \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #2\]
--.*: c560c001 ld1w \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #2\]
--.*: c560c001 ld1w \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #2\]
--.*: c560c001 ld1w \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #2\]
--.*: c560c01f ld1w \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #2\]
--.*: c560c01f ld1w \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #2\]
--.*: c560c01f ld1w \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #2\]
--.*: c560c800 ld1w \{z0\.d\}, p2/z, \[x0, z0\.d, lsl #2\]
--.*: c560c800 ld1w \{z0\.d\}, p2/z, \[x0, z0\.d, lsl #2\]
--.*: c560dc00 ld1w \{z0\.d\}, p7/z, \[x0, z0\.d, lsl #2\]
--.*: c560dc00 ld1w \{z0\.d\}, p7/z, \[x0, z0\.d, lsl #2\]
--.*: c560c060 ld1w \{z0\.d\}, p0/z, \[x3, z0\.d, lsl #2\]
--.*: c560c060 ld1w \{z0\.d\}, p0/z, \[x3, z0\.d, lsl #2\]
--.*: c560c3e0 ld1w \{z0\.d\}, p0/z, \[sp, z0\.d, lsl #2\]
--.*: c560c3e0 ld1w \{z0\.d\}, p0/z, \[sp, z0\.d, lsl #2\]
--.*: c564c000 ld1w \{z0\.d\}, p0/z, \[x0, z4\.d, lsl #2\]
--.*: c564c000 ld1w \{z0\.d\}, p0/z, \[x0, z4\.d, lsl #2\]
--.*: c57fc000 ld1w \{z0\.d\}, p0/z, \[x0, z31\.d, lsl #2\]
--.*: c57fc000 ld1w \{z0\.d\}, p0/z, \[x0, z31\.d, lsl #2\]
--.*: 8520c000 ld1w \{z0\.s\}, p0/z, \[z0\.s\]
--.*: 8520c000 ld1w \{z0\.s\}, p0/z, \[z0\.s\]
--.*: 8520c000 ld1w \{z0\.s\}, p0/z, \[z0\.s\]
--.*: 8520c000 ld1w \{z0\.s\}, p0/z, \[z0\.s\]
--.*: 8520c001 ld1w \{z1\.s\}, p0/z, \[z0\.s\]
--.*: 8520c001 ld1w \{z1\.s\}, p0/z, \[z0\.s\]
--.*: 8520c001 ld1w \{z1\.s\}, p0/z, \[z0\.s\]
--.*: 8520c001 ld1w \{z1\.s\}, p0/z, \[z0\.s\]
--.*: 8520c01f ld1w \{z31\.s\}, p0/z, \[z0\.s\]
--.*: 8520c01f ld1w \{z31\.s\}, p0/z, \[z0\.s\]
--.*: 8520c01f ld1w \{z31\.s\}, p0/z, \[z0\.s\]
--.*: 8520c01f ld1w \{z31\.s\}, p0/z, \[z0\.s\]
--.*: 8520c800 ld1w \{z0\.s\}, p2/z, \[z0\.s\]
--.*: 8520c800 ld1w \{z0\.s\}, p2/z, \[z0\.s\]
--.*: 8520c800 ld1w \{z0\.s\}, p2/z, \[z0\.s\]
--.*: 8520dc00 ld1w \{z0\.s\}, p7/z, \[z0\.s\]
--.*: 8520dc00 ld1w \{z0\.s\}, p7/z, \[z0\.s\]
--.*: 8520dc00 ld1w \{z0\.s\}, p7/z, \[z0\.s\]
--.*: 8520c060 ld1w \{z0\.s\}, p0/z, \[z3\.s\]
--.*: 8520c060 ld1w \{z0\.s\}, p0/z, \[z3\.s\]
--.*: 8520c060 ld1w \{z0\.s\}, p0/z, \[z3\.s\]
--.*: 8520c3e0 ld1w \{z0\.s\}, p0/z, \[z31\.s\]
--.*: 8520c3e0 ld1w \{z0\.s\}, p0/z, \[z31\.s\]
--.*: 8520c3e0 ld1w \{z0\.s\}, p0/z, \[z31\.s\]
--.*: 852fc000 ld1w \{z0\.s\}, p0/z, \[z0\.s, #60\]
--.*: 852fc000 ld1w \{z0\.s\}, p0/z, \[z0\.s, #60\]
--.*: 8530c000 ld1w \{z0\.s\}, p0/z, \[z0\.s, #64\]
--.*: 8530c000 ld1w \{z0\.s\}, p0/z, \[z0\.s, #64\]
--.*: 8531c000 ld1w \{z0\.s\}, p0/z, \[z0\.s, #68\]
--.*: 8531c000 ld1w \{z0\.s\}, p0/z, \[z0\.s, #68\]
--.*: 853fc000 ld1w \{z0\.s\}, p0/z, \[z0\.s, #124\]
--.*: 853fc000 ld1w \{z0\.s\}, p0/z, \[z0\.s, #124\]
--.*: a540a000 ld1w \{z0\.s\}, p0/z, \[x0\]
--.*: a540a000 ld1w \{z0\.s\}, p0/z, \[x0\]
--.*: a540a000 ld1w \{z0\.s\}, p0/z, \[x0\]
--.*: a540a000 ld1w \{z0\.s\}, p0/z, \[x0\]
--.*: a540a000 ld1w \{z0\.s\}, p0/z, \[x0\]
--.*: a540a001 ld1w \{z1\.s\}, p0/z, \[x0\]
--.*: a540a001 ld1w \{z1\.s\}, p0/z, \[x0\]
--.*: a540a001 ld1w \{z1\.s\}, p0/z, \[x0\]
--.*: a540a001 ld1w \{z1\.s\}, p0/z, \[x0\]
--.*: a540a001 ld1w \{z1\.s\}, p0/z, \[x0\]
--.*: a540a01f ld1w \{z31\.s\}, p0/z, \[x0\]
--.*: a540a01f ld1w \{z31\.s\}, p0/z, \[x0\]
--.*: a540a01f ld1w \{z31\.s\}, p0/z, \[x0\]
--.*: a540a01f ld1w \{z31\.s\}, p0/z, \[x0\]
--.*: a540a01f ld1w \{z31\.s\}, p0/z, \[x0\]
--.*: a540a800 ld1w \{z0\.s\}, p2/z, \[x0\]
--.*: a540a800 ld1w \{z0\.s\}, p2/z, \[x0\]
--.*: a540a800 ld1w \{z0\.s\}, p2/z, \[x0\]
--.*: a540a800 ld1w \{z0\.s\}, p2/z, \[x0\]
--.*: a540bc00 ld1w \{z0\.s\}, p7/z, \[x0\]
--.*: a540bc00 ld1w \{z0\.s\}, p7/z, \[x0\]
--.*: a540bc00 ld1w \{z0\.s\}, p7/z, \[x0\]
--.*: a540bc00 ld1w \{z0\.s\}, p7/z, \[x0\]
--.*: a540a060 ld1w \{z0\.s\}, p0/z, \[x3\]
--.*: a540a060 ld1w \{z0\.s\}, p0/z, \[x3\]
--.*: a540a060 ld1w \{z0\.s\}, p0/z, \[x3\]
--.*: a540a060 ld1w \{z0\.s\}, p0/z, \[x3\]
--.*: a540a3e0 ld1w \{z0\.s\}, p0/z, \[sp\]
--.*: a540a3e0 ld1w \{z0\.s\}, p0/z, \[sp\]
--.*: a540a3e0 ld1w \{z0\.s\}, p0/z, \[sp\]
--.*: a540a3e0 ld1w \{z0\.s\}, p0/z, \[sp\]
--.*: a547a000 ld1w \{z0\.s\}, p0/z, \[x0, #7, mul vl\]
--.*: a547a000 ld1w \{z0\.s\}, p0/z, \[x0, #7, mul vl\]
--.*: a548a000 ld1w \{z0\.s\}, p0/z, \[x0, #-8, mul vl\]
--.*: a548a000 ld1w \{z0\.s\}, p0/z, \[x0, #-8, mul vl\]
--.*: a549a000 ld1w \{z0\.s\}, p0/z, \[x0, #-7, mul vl\]
--.*: a549a000 ld1w \{z0\.s\}, p0/z, \[x0, #-7, mul vl\]
--.*: a54fa000 ld1w \{z0\.s\}, p0/z, \[x0, #-1, mul vl\]
--.*: a54fa000 ld1w \{z0\.s\}, p0/z, \[x0, #-1, mul vl\]
--.*: a560a000 ld1w \{z0\.d\}, p0/z, \[x0\]
--.*: a560a000 ld1w \{z0\.d\}, p0/z, \[x0\]
--.*: a560a000 ld1w \{z0\.d\}, p0/z, \[x0\]
--.*: a560a000 ld1w \{z0\.d\}, p0/z, \[x0\]
--.*: a560a000 ld1w \{z0\.d\}, p0/z, \[x0\]
--.*: a560a001 ld1w \{z1\.d\}, p0/z, \[x0\]
--.*: a560a001 ld1w \{z1\.d\}, p0/z, \[x0\]
--.*: a560a001 ld1w \{z1\.d\}, p0/z, \[x0\]
--.*: a560a001 ld1w \{z1\.d\}, p0/z, \[x0\]
--.*: a560a001 ld1w \{z1\.d\}, p0/z, \[x0\]
--.*: a560a01f ld1w \{z31\.d\}, p0/z, \[x0\]
--.*: a560a01f ld1w \{z31\.d\}, p0/z, \[x0\]
--.*: a560a01f ld1w \{z31\.d\}, p0/z, \[x0\]
--.*: a560a01f ld1w \{z31\.d\}, p0/z, \[x0\]
--.*: a560a01f ld1w \{z31\.d\}, p0/z, \[x0\]
--.*: a560a800 ld1w \{z0\.d\}, p2/z, \[x0\]
--.*: a560a800 ld1w \{z0\.d\}, p2/z, \[x0\]
--.*: a560a800 ld1w \{z0\.d\}, p2/z, \[x0\]
--.*: a560a800 ld1w \{z0\.d\}, p2/z, \[x0\]
--.*: a560bc00 ld1w \{z0\.d\}, p7/z, \[x0\]
--.*: a560bc00 ld1w \{z0\.d\}, p7/z, \[x0\]
--.*: a560bc00 ld1w \{z0\.d\}, p7/z, \[x0\]
--.*: a560bc00 ld1w \{z0\.d\}, p7/z, \[x0\]
--.*: a560a060 ld1w \{z0\.d\}, p0/z, \[x3\]
--.*: a560a060 ld1w \{z0\.d\}, p0/z, \[x3\]
--.*: a560a060 ld1w \{z0\.d\}, p0/z, \[x3\]
--.*: a560a060 ld1w \{z0\.d\}, p0/z, \[x3\]
--.*: a560a3e0 ld1w \{z0\.d\}, p0/z, \[sp\]
--.*: a560a3e0 ld1w \{z0\.d\}, p0/z, \[sp\]
--.*: a560a3e0 ld1w \{z0\.d\}, p0/z, \[sp\]
--.*: a560a3e0 ld1w \{z0\.d\}, p0/z, \[sp\]
--.*: a567a000 ld1w \{z0\.d\}, p0/z, \[x0, #7, mul vl\]
--.*: a567a000 ld1w \{z0\.d\}, p0/z, \[x0, #7, mul vl\]
--.*: a568a000 ld1w \{z0\.d\}, p0/z, \[x0, #-8, mul vl\]
--.*: a568a000 ld1w \{z0\.d\}, p0/z, \[x0, #-8, mul vl\]
--.*: a569a000 ld1w \{z0\.d\}, p0/z, \[x0, #-7, mul vl\]
--.*: a569a000 ld1w \{z0\.d\}, p0/z, \[x0, #-7, mul vl\]
--.*: a56fa000 ld1w \{z0\.d\}, p0/z, \[x0, #-1, mul vl\]
--.*: a56fa000 ld1w \{z0\.d\}, p0/z, \[x0, #-1, mul vl\]
--.*: c520c000 ld1w \{z0\.d\}, p0/z, \[z0\.d\]
--.*: c520c000 ld1w \{z0\.d\}, p0/z, \[z0\.d\]
--.*: c520c000 ld1w \{z0\.d\}, p0/z, \[z0\.d\]
--.*: c520c000 ld1w \{z0\.d\}, p0/z, \[z0\.d\]
--.*: c520c001 ld1w \{z1\.d\}, p0/z, \[z0\.d\]
--.*: c520c001 ld1w \{z1\.d\}, p0/z, \[z0\.d\]
--.*: c520c001 ld1w \{z1\.d\}, p0/z, \[z0\.d\]
--.*: c520c001 ld1w \{z1\.d\}, p0/z, \[z0\.d\]
--.*: c520c01f ld1w \{z31\.d\}, p0/z, \[z0\.d\]
--.*: c520c01f ld1w \{z31\.d\}, p0/z, \[z0\.d\]
--.*: c520c01f ld1w \{z31\.d\}, p0/z, \[z0\.d\]
--.*: c520c01f ld1w \{z31\.d\}, p0/z, \[z0\.d\]
--.*: c520c800 ld1w \{z0\.d\}, p2/z, \[z0\.d\]
--.*: c520c800 ld1w \{z0\.d\}, p2/z, \[z0\.d\]
--.*: c520c800 ld1w \{z0\.d\}, p2/z, \[z0\.d\]
--.*: c520dc00 ld1w \{z0\.d\}, p7/z, \[z0\.d\]
--.*: c520dc00 ld1w \{z0\.d\}, p7/z, \[z0\.d\]
--.*: c520dc00 ld1w \{z0\.d\}, p7/z, \[z0\.d\]
--.*: c520c060 ld1w \{z0\.d\}, p0/z, \[z3\.d\]
--.*: c520c060 ld1w \{z0\.d\}, p0/z, \[z3\.d\]
--.*: c520c060 ld1w \{z0\.d\}, p0/z, \[z3\.d\]
--.*: c520c3e0 ld1w \{z0\.d\}, p0/z, \[z31\.d\]
--.*: c520c3e0 ld1w \{z0\.d\}, p0/z, \[z31\.d\]
--.*: c520c3e0 ld1w \{z0\.d\}, p0/z, \[z31\.d\]
--.*: c52fc000 ld1w \{z0\.d\}, p0/z, \[z0\.d, #60\]
--.*: c52fc000 ld1w \{z0\.d\}, p0/z, \[z0\.d, #60\]
--.*: c530c000 ld1w \{z0\.d\}, p0/z, \[z0\.d, #64\]
--.*: c530c000 ld1w \{z0\.d\}, p0/z, \[z0\.d, #64\]
--.*: c531c000 ld1w \{z0\.d\}, p0/z, \[z0\.d, #68\]
--.*: c531c000 ld1w \{z0\.d\}, p0/z, \[z0\.d, #68\]
--.*: c53fc000 ld1w \{z0\.d\}, p0/z, \[z0\.d, #124\]
--.*: c53fc000 ld1w \{z0\.d\}, p0/z, \[z0\.d, #124\]
--.*: a420c000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0, x0\]
--.*: a420c000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0, x0\]
--.*: a420c000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0, x0\]
--.*: a420c000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0, x0\]
--.*: a420c000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0, x0\]
--.*: a420c001 ld2b \{z1\.b, z2\.b\}, p0/z, \[x0, x0\]
--.*: a420c001 ld2b \{z1\.b, z2\.b\}, p0/z, \[x0, x0\]
--.*: a420c001 ld2b \{z1\.b, z2\.b\}, p0/z, \[x0, x0\]
--.*: a420c001 ld2b \{z1\.b, z2\.b\}, p0/z, \[x0, x0\]
--.*: a420c001 ld2b \{z1\.b, z2\.b\}, p0/z, \[x0, x0\]
--.*: a420c01f ld2b \{z31\.b, z0\.b\}, p0/z, \[x0, x0\]
--.*: a420c01f ld2b \{z31\.b, z0\.b\}, p0/z, \[x0, x0\]
--.*: a420c01f ld2b \{z31\.b, z0\.b\}, p0/z, \[x0, x0\]
--.*: a420c800 ld2b \{z0\.b, z1\.b\}, p2/z, \[x0, x0\]
--.*: a420c800 ld2b \{z0\.b, z1\.b\}, p2/z, \[x0, x0\]
--.*: a420c800 ld2b \{z0\.b, z1\.b\}, p2/z, \[x0, x0\]
--.*: a420c800 ld2b \{z0\.b, z1\.b\}, p2/z, \[x0, x0\]
--.*: a420c800 ld2b \{z0\.b, z1\.b\}, p2/z, \[x0, x0\]
--.*: a420dc00 ld2b \{z0\.b, z1\.b\}, p7/z, \[x0, x0\]
--.*: a420dc00 ld2b \{z0\.b, z1\.b\}, p7/z, \[x0, x0\]
--.*: a420dc00 ld2b \{z0\.b, z1\.b\}, p7/z, \[x0, x0\]
--.*: a420dc00 ld2b \{z0\.b, z1\.b\}, p7/z, \[x0, x0\]
--.*: a420dc00 ld2b \{z0\.b, z1\.b\}, p7/z, \[x0, x0\]
--.*: a420c060 ld2b \{z0\.b, z1\.b\}, p0/z, \[x3, x0\]
--.*: a420c060 ld2b \{z0\.b, z1\.b\}, p0/z, \[x3, x0\]
--.*: a420c060 ld2b \{z0\.b, z1\.b\}, p0/z, \[x3, x0\]
--.*: a420c060 ld2b \{z0\.b, z1\.b\}, p0/z, \[x3, x0\]
--.*: a420c060 ld2b \{z0\.b, z1\.b\}, p0/z, \[x3, x0\]
--.*: a420c3e0 ld2b \{z0\.b, z1\.b\}, p0/z, \[sp, x0\]
--.*: a420c3e0 ld2b \{z0\.b, z1\.b\}, p0/z, \[sp, x0\]
--.*: a420c3e0 ld2b \{z0\.b, z1\.b\}, p0/z, \[sp, x0\]
--.*: a420c3e0 ld2b \{z0\.b, z1\.b\}, p0/z, \[sp, x0\]
--.*: a420c3e0 ld2b \{z0\.b, z1\.b\}, p0/z, \[sp, x0\]
--.*: a424c000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0, x4\]
--.*: a424c000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0, x4\]
--.*: a424c000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0, x4\]
--.*: a424c000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0, x4\]
--.*: a424c000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0, x4\]
--.*: a43ec000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0, x30\]
--.*: a43ec000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0, x30\]
--.*: a43ec000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0, x30\]
--.*: a43ec000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0, x30\]
--.*: a43ec000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0, x30\]
--.*: a420e000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0\]
--.*: a420e000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0\]
--.*: a420e000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0\]
--.*: a420e000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0\]
--.*: a420e000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0\]
--.*: a420e000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0\]
--.*: a420e000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0\]
--.*: a420e001 ld2b \{z1\.b, z2\.b\}, p0/z, \[x0\]
--.*: a420e001 ld2b \{z1\.b, z2\.b\}, p0/z, \[x0\]
--.*: a420e001 ld2b \{z1\.b, z2\.b\}, p0/z, \[x0\]
--.*: a420e001 ld2b \{z1\.b, z2\.b\}, p0/z, \[x0\]
--.*: a420e001 ld2b \{z1\.b, z2\.b\}, p0/z, \[x0\]
--.*: a420e001 ld2b \{z1\.b, z2\.b\}, p0/z, \[x0\]
--.*: a420e001 ld2b \{z1\.b, z2\.b\}, p0/z, \[x0\]
--.*: a420e01f ld2b \{z31\.b, z0\.b\}, p0/z, \[x0\]
--.*: a420e01f ld2b \{z31\.b, z0\.b\}, p0/z, \[x0\]
--.*: a420e01f ld2b \{z31\.b, z0\.b\}, p0/z, \[x0\]
--.*: a420e01f ld2b \{z31\.b, z0\.b\}, p0/z, \[x0\]
--.*: a420e800 ld2b \{z0\.b, z1\.b\}, p2/z, \[x0\]
--.*: a420e800 ld2b \{z0\.b, z1\.b\}, p2/z, \[x0\]
--.*: a420e800 ld2b \{z0\.b, z1\.b\}, p2/z, \[x0\]
--.*: a420e800 ld2b \{z0\.b, z1\.b\}, p2/z, \[x0\]
--.*: a420e800 ld2b \{z0\.b, z1\.b\}, p2/z, \[x0\]
--.*: a420e800 ld2b \{z0\.b, z1\.b\}, p2/z, \[x0\]
--.*: a420e800 ld2b \{z0\.b, z1\.b\}, p2/z, \[x0\]
--.*: a420fc00 ld2b \{z0\.b, z1\.b\}, p7/z, \[x0\]
--.*: a420fc00 ld2b \{z0\.b, z1\.b\}, p7/z, \[x0\]
--.*: a420fc00 ld2b \{z0\.b, z1\.b\}, p7/z, \[x0\]
--.*: a420fc00 ld2b \{z0\.b, z1\.b\}, p7/z, \[x0\]
--.*: a420fc00 ld2b \{z0\.b, z1\.b\}, p7/z, \[x0\]
--.*: a420fc00 ld2b \{z0\.b, z1\.b\}, p7/z, \[x0\]
--.*: a420fc00 ld2b \{z0\.b, z1\.b\}, p7/z, \[x0\]
--.*: a420e060 ld2b \{z0\.b, z1\.b\}, p0/z, \[x3\]
--.*: a420e060 ld2b \{z0\.b, z1\.b\}, p0/z, \[x3\]
--.*: a420e060 ld2b \{z0\.b, z1\.b\}, p0/z, \[x3\]
--.*: a420e060 ld2b \{z0\.b, z1\.b\}, p0/z, \[x3\]
--.*: a420e060 ld2b \{z0\.b, z1\.b\}, p0/z, \[x3\]
--.*: a420e060 ld2b \{z0\.b, z1\.b\}, p0/z, \[x3\]
--.*: a420e060 ld2b \{z0\.b, z1\.b\}, p0/z, \[x3\]
--.*: a420e3e0 ld2b \{z0\.b, z1\.b\}, p0/z, \[sp\]
--.*: a420e3e0 ld2b \{z0\.b, z1\.b\}, p0/z, \[sp\]
--.*: a420e3e0 ld2b \{z0\.b, z1\.b\}, p0/z, \[sp\]
--.*: a420e3e0 ld2b \{z0\.b, z1\.b\}, p0/z, \[sp\]
--.*: a420e3e0 ld2b \{z0\.b, z1\.b\}, p0/z, \[sp\]
--.*: a420e3e0 ld2b \{z0\.b, z1\.b\}, p0/z, \[sp\]
--.*: a420e3e0 ld2b \{z0\.b, z1\.b\}, p0/z, \[sp\]
--.*: a427e000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0, #14, mul vl\]
--.*: a427e000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0, #14, mul vl\]
--.*: a427e000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0, #14, mul vl\]
--.*: a428e000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0, #-16, mul vl\]
--.*: a428e000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0, #-16, mul vl\]
--.*: a428e000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0, #-16, mul vl\]
--.*: a429e000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0, #-14, mul vl\]
--.*: a429e000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0, #-14, mul vl\]
--.*: a429e000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0, #-14, mul vl\]
--.*: a42fe000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0, #-2, mul vl\]
--.*: a42fe000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0, #-2, mul vl\]
--.*: a42fe000 ld2b \{z0\.b, z1\.b\}, p0/z, \[x0, #-2, mul vl\]
--.*: a5a0c000 ld2d \{z0\.d, z1\.d\}, p0/z, \[x0, x0, lsl #3\]
--.*: a5a0c000 ld2d \{z0\.d, z1\.d\}, p0/z, \[x0, x0, lsl #3\]
--.*: a5a0c000 ld2d \{z0\.d, z1\.d\}, p0/z, \[x0, x0, lsl #3\]
--.*: a5a0c001 ld2d \{z1\.d, z2\.d\}, p0/z, \[x0, x0, lsl #3\]
--.*: a5a0c001 ld2d \{z1\.d, z2\.d\}, p0/z, \[x0, x0, lsl #3\]
--.*: a5a0c001 ld2d \{z1\.d, z2\.d\}, p0/z, \[x0, x0, lsl #3\]
--.*: a5a0c01f ld2d \{z31\.d, z0\.d\}, p0/z, \[x0, x0, lsl #3\]
--.*: a5a0c01f ld2d \{z31\.d, z0\.d\}, p0/z, \[x0, x0, lsl #3\]
--.*: a5a0c800 ld2d \{z0\.d, z1\.d\}, p2/z, \[x0, x0, lsl #3\]
--.*: a5a0c800 ld2d \{z0\.d, z1\.d\}, p2/z, \[x0, x0, lsl #3\]
--.*: a5a0c800 ld2d \{z0\.d, z1\.d\}, p2/z, \[x0, x0, lsl #3\]
--.*: a5a0dc00 ld2d \{z0\.d, z1\.d\}, p7/z, \[x0, x0, lsl #3\]
--.*: a5a0dc00 ld2d \{z0\.d, z1\.d\}, p7/z, \[x0, x0, lsl #3\]
--.*: a5a0dc00 ld2d \{z0\.d, z1\.d\}, p7/z, \[x0, x0, lsl #3\]
--.*: a5a0c060 ld2d \{z0\.d, z1\.d\}, p0/z, \[x3, x0, lsl #3\]
--.*: a5a0c060 ld2d \{z0\.d, z1\.d\}, p0/z, \[x3, x0, lsl #3\]
--.*: a5a0c060 ld2d \{z0\.d, z1\.d\}, p0/z, \[x3, x0, lsl #3\]
--.*: a5a0c3e0 ld2d \{z0\.d, z1\.d\}, p0/z, \[sp, x0, lsl #3\]
--.*: a5a0c3e0 ld2d \{z0\.d, z1\.d\}, p0/z, \[sp, x0, lsl #3\]
--.*: a5a0c3e0 ld2d \{z0\.d, z1\.d\}, p0/z, \[sp, x0, lsl #3\]
--.*: a5a4c000 ld2d \{z0\.d, z1\.d\}, p0/z, \[x0, x4, lsl #3\]
--.*: a5a4c000 ld2d \{z0\.d, z1\.d\}, p0/z, \[x0, x4, lsl #3\]
--.*: a5a4c000 ld2d \{z0\.d, z1\.d\}, p0/z, \[x0, x4, lsl #3\]
--.*: a5bec000 ld2d \{z0\.d, z1\.d\}, p0/z, \[x0, x30, lsl #3\]
--.*: a5bec000 ld2d \{z0\.d, z1\.d\}, p0/z, \[x0, x30, lsl #3\]
--.*: a5bec000 ld2d \{z0\.d, z1\.d\}, p0/z, \[x0, x30, lsl #3\]
--.*: a5a0e000 ld2d \{z0\.d, z1\.d\}, p0/z, \[x0\]
--.*: a5a0e000 ld2d \{z0\.d, z1\.d\}, p0/z, \[x0\]
--.*: a5a0e000 ld2d \{z0\.d, z1\.d\}, p0/z, \[x0\]
--.*: a5a0e000 ld2d \{z0\.d, z1\.d\}, p0/z, \[x0\]
--.*: a5a0e000 ld2d \{z0\.d, z1\.d\}, p0/z, \[x0\]
--.*: a5a0e000 ld2d \{z0\.d, z1\.d\}, p0/z, \[x0\]
--.*: a5a0e000 ld2d \{z0\.d, z1\.d\}, p0/z, \[x0\]
--.*: a5a0e001 ld2d \{z1\.d, z2\.d\}, p0/z, \[x0\]
--.*: a5a0e001 ld2d \{z1\.d, z2\.d\}, p0/z, \[x0\]
--.*: a5a0e001 ld2d \{z1\.d, z2\.d\}, p0/z, \[x0\]
--.*: a5a0e001 ld2d \{z1\.d, z2\.d\}, p0/z, \[x0\]
--.*: a5a0e001 ld2d \{z1\.d, z2\.d\}, p0/z, \[x0\]
--.*: a5a0e001 ld2d \{z1\.d, z2\.d\}, p0/z, \[x0\]
--.*: a5a0e001 ld2d \{z1\.d, z2\.d\}, p0/z, \[x0\]
--.*: a5a0e01f ld2d \{z31\.d, z0\.d\}, p0/z, \[x0\]
--.*: a5a0e01f ld2d \{z31\.d, z0\.d\}, p0/z, \[x0\]
--.*: a5a0e01f ld2d \{z31\.d, z0\.d\}, p0/z, \[x0\]
--.*: a5a0e01f ld2d \{z31\.d, z0\.d\}, p0/z, \[x0\]
--.*: a5a0e800 ld2d \{z0\.d, z1\.d\}, p2/z, \[x0\]
--.*: a5a0e800 ld2d \{z0\.d, z1\.d\}, p2/z, \[x0\]
--.*: a5a0e800 ld2d \{z0\.d, z1\.d\}, p2/z, \[x0\]
--.*: a5a0e800 ld2d \{z0\.d, z1\.d\}, p2/z, \[x0\]
--.*: a5a0e800 ld2d \{z0\.d, z1\.d\}, p2/z, \[x0\]
--.*: a5a0e800 ld2d \{z0\.d, z1\.d\}, p2/z, \[x0\]
--.*: a5a0e800 ld2d \{z0\.d, z1\.d\}, p2/z, \[x0\]
--.*: a5a0fc00 ld2d \{z0\.d, z1\.d\}, p7/z, \[x0\]
--.*: a5a0fc00 ld2d \{z0\.d, z1\.d\}, p7/z, \[x0\]
--.*: a5a0fc00 ld2d \{z0\.d, z1\.d\}, p7/z, \[x0\]
--.*: a5a0fc00 ld2d \{z0\.d, z1\.d\}, p7/z, \[x0\]
--.*: a5a0fc00 ld2d \{z0\.d, z1\.d\}, p7/z, \[x0\]
--.*: a5a0fc00 ld2d \{z0\.d, z1\.d\}, p7/z, \[x0\]
--.*: a5a0fc00 ld2d \{z0\.d, z1\.d\}, p7/z, \[x0\]
--.*: a5a0e060 ld2d \{z0\.d, z1\.d\}, p0/z, \[x3\]
--.*: a5a0e060 ld2d \{z0\.d, z1\.d\}, p0/z, \[x3\]
--.*: a5a0e060 ld2d \{z0\.d, z1\.d\}, p0/z, \[x3\]
--.*: a5a0e060 ld2d \{z0\.d, z1\.d\}, p0/z, \[x3\]
--.*: a5a0e060 ld2d \{z0\.d, z1\.d\}, p0/z, \[x3\]
--.*: a5a0e060 ld2d \{z0\.d, z1\.d\}, p0/z, \[x3\]
--.*: a5a0e060 ld2d \{z0\.d, z1\.d\}, p0/z, \[x3\]
--.*: a5a0e3e0 ld2d \{z0\.d, z1\.d\}, p0/z, \[sp\]
--.*: a5a0e3e0 ld2d \{z0\.d, z1\.d\}, p0/z, \[sp\]
--.*: a5a0e3e0 ld2d \{z0\.d, z1\.d\}, p0/z, \[sp\]
--.*: a5a0e3e0 ld2d \{z0\.d, z1\.d\}, p0/z, \[sp\]
--.*: a5a0e3e0 ld2d \{z0\.d, z1\.d\}, p0/z, \[sp\]
--.*: a5a0e3e0 ld2d \{z0\.d, z1\.d\}, p0/z, \[sp\]
--.*: a5a0e3e0 ld2d \{z0\.d, z1\.d\}, p0/z, \[sp\]
--.*: a5a7e000 ld2d \{z0\.d, z1\.d\}, p0/z, \[x0, #14, mul vl\]
--.*: a5a7e000 ld2d \{z0\.d, z1\.d\}, p0/z, \[x0, #14, mul vl\]
--.*: a5a7e000 ld2d \{z0\.d, z1\.d\}, p0/z, \[x0, #14, mul vl\]
--.*: a5a8e000 ld2d \{z0\.d, z1\.d\}, p0/z, \[x0, #-16, mul vl\]
--.*: a5a8e000 ld2d \{z0\.d, z1\.d\}, p0/z, \[x0, #-16, mul vl\]
--.*: a5a8e000 ld2d \{z0\.d, z1\.d\}, p0/z, \[x0, #-16, mul vl\]
--.*: a5a9e000 ld2d \{z0\.d, z1\.d\}, p0/z, \[x0, #-14, mul vl\]
--.*: a5a9e000 ld2d \{z0\.d, z1\.d\}, p0/z, \[x0, #-14, mul vl\]
--.*: a5a9e000 ld2d \{z0\.d, z1\.d\}, p0/z, \[x0, #-14, mul vl\]
--.*: a5afe000 ld2d \{z0\.d, z1\.d\}, p0/z, \[x0, #-2, mul vl\]
--.*: a5afe000 ld2d \{z0\.d, z1\.d\}, p0/z, \[x0, #-2, mul vl\]
--.*: a5afe000 ld2d \{z0\.d, z1\.d\}, p0/z, \[x0, #-2, mul vl\]
--.*: a4a0c000 ld2h \{z0\.h, z1\.h\}, p0/z, \[x0, x0, lsl #1\]
--.*: a4a0c000 ld2h \{z0\.h, z1\.h\}, p0/z, \[x0, x0, lsl #1\]
--.*: a4a0c000 ld2h \{z0\.h, z1\.h\}, p0/z, \[x0, x0, lsl #1\]
--.*: a4a0c001 ld2h \{z1\.h, z2\.h\}, p0/z, \[x0, x0, lsl #1\]
--.*: a4a0c001 ld2h \{z1\.h, z2\.h\}, p0/z, \[x0, x0, lsl #1\]
--.*: a4a0c001 ld2h \{z1\.h, z2\.h\}, p0/z, \[x0, x0, lsl #1\]
--.*: a4a0c01f ld2h \{z31\.h, z0\.h\}, p0/z, \[x0, x0, lsl #1\]
--.*: a4a0c01f ld2h \{z31\.h, z0\.h\}, p0/z, \[x0, x0, lsl #1\]
--.*: a4a0c800 ld2h \{z0\.h, z1\.h\}, p2/z, \[x0, x0, lsl #1\]
--.*: a4a0c800 ld2h \{z0\.h, z1\.h\}, p2/z, \[x0, x0, lsl #1\]
--.*: a4a0c800 ld2h \{z0\.h, z1\.h\}, p2/z, \[x0, x0, lsl #1\]
--.*: a4a0dc00 ld2h \{z0\.h, z1\.h\}, p7/z, \[x0, x0, lsl #1\]
--.*: a4a0dc00 ld2h \{z0\.h, z1\.h\}, p7/z, \[x0, x0, lsl #1\]
--.*: a4a0dc00 ld2h \{z0\.h, z1\.h\}, p7/z, \[x0, x0, lsl #1\]
--.*: a4a0c060 ld2h \{z0\.h, z1\.h\}, p0/z, \[x3, x0, lsl #1\]
--.*: a4a0c060 ld2h \{z0\.h, z1\.h\}, p0/z, \[x3, x0, lsl #1\]
--.*: a4a0c060 ld2h \{z0\.h, z1\.h\}, p0/z, \[x3, x0, lsl #1\]
--.*: a4a0c3e0 ld2h \{z0\.h, z1\.h\}, p0/z, \[sp, x0, lsl #1\]
--.*: a4a0c3e0 ld2h \{z0\.h, z1\.h\}, p0/z, \[sp, x0, lsl #1\]
--.*: a4a0c3e0 ld2h \{z0\.h, z1\.h\}, p0/z, \[sp, x0, lsl #1\]
--.*: a4a4c000 ld2h \{z0\.h, z1\.h\}, p0/z, \[x0, x4, lsl #1\]
--.*: a4a4c000 ld2h \{z0\.h, z1\.h\}, p0/z, \[x0, x4, lsl #1\]
--.*: a4a4c000 ld2h \{z0\.h, z1\.h\}, p0/z, \[x0, x4, lsl #1\]
--.*: a4bec000 ld2h \{z0\.h, z1\.h\}, p0/z, \[x0, x30, lsl #1\]
--.*: a4bec000 ld2h \{z0\.h, z1\.h\}, p0/z, \[x0, x30, lsl #1\]
--.*: a4bec000 ld2h \{z0\.h, z1\.h\}, p0/z, \[x0, x30, lsl #1\]
--.*: a4a0e000 ld2h \{z0\.h, z1\.h\}, p0/z, \[x0\]
--.*: a4a0e000 ld2h \{z0\.h, z1\.h\}, p0/z, \[x0\]
--.*: a4a0e000 ld2h \{z0\.h, z1\.h\}, p0/z, \[x0\]
--.*: a4a0e000 ld2h \{z0\.h, z1\.h\}, p0/z, \[x0\]
--.*: a4a0e000 ld2h \{z0\.h, z1\.h\}, p0/z, \[x0\]
--.*: a4a0e000 ld2h \{z0\.h, z1\.h\}, p0/z, \[x0\]
--.*: a4a0e000 ld2h \{z0\.h, z1\.h\}, p0/z, \[x0\]
--.*: a4a0e001 ld2h \{z1\.h, z2\.h\}, p0/z, \[x0\]
--.*: a4a0e001 ld2h \{z1\.h, z2\.h\}, p0/z, \[x0\]
--.*: a4a0e001 ld2h \{z1\.h, z2\.h\}, p0/z, \[x0\]
--.*: a4a0e001 ld2h \{z1\.h, z2\.h\}, p0/z, \[x0\]
--.*: a4a0e001 ld2h \{z1\.h, z2\.h\}, p0/z, \[x0\]
--.*: a4a0e001 ld2h \{z1\.h, z2\.h\}, p0/z, \[x0\]
--.*: a4a0e001 ld2h \{z1\.h, z2\.h\}, p0/z, \[x0\]
--.*: a4a0e01f ld2h \{z31\.h, z0\.h\}, p0/z, \[x0\]
--.*: a4a0e01f ld2h \{z31\.h, z0\.h\}, p0/z, \[x0\]
--.*: a4a0e01f ld2h \{z31\.h, z0\.h\}, p0/z, \[x0\]
--.*: a4a0e01f ld2h \{z31\.h, z0\.h\}, p0/z, \[x0\]
--.*: a4a0e800 ld2h \{z0\.h, z1\.h\}, p2/z, \[x0\]
--.*: a4a0e800 ld2h \{z0\.h, z1\.h\}, p2/z, \[x0\]
--.*: a4a0e800 ld2h \{z0\.h, z1\.h\}, p2/z, \[x0\]
--.*: a4a0e800 ld2h \{z0\.h, z1\.h\}, p2/z, \[x0\]
--.*: a4a0e800 ld2h \{z0\.h, z1\.h\}, p2/z, \[x0\]
--.*: a4a0e800 ld2h \{z0\.h, z1\.h\}, p2/z, \[x0\]
--.*: a4a0e800 ld2h \{z0\.h, z1\.h\}, p2/z, \[x0\]
--.*: a4a0fc00 ld2h \{z0\.h, z1\.h\}, p7/z, \[x0\]
--.*: a4a0fc00 ld2h \{z0\.h, z1\.h\}, p7/z, \[x0\]
--.*: a4a0fc00 ld2h \{z0\.h, z1\.h\}, p7/z, \[x0\]
--.*: a4a0fc00 ld2h \{z0\.h, z1\.h\}, p7/z, \[x0\]
--.*: a4a0fc00 ld2h \{z0\.h, z1\.h\}, p7/z, \[x0\]
--.*: a4a0fc00 ld2h \{z0\.h, z1\.h\}, p7/z, \[x0\]
--.*: a4a0fc00 ld2h \{z0\.h, z1\.h\}, p7/z, \[x0\]
--.*: a4a0e060 ld2h \{z0\.h, z1\.h\}, p0/z, \[x3\]
--.*: a4a0e060 ld2h \{z0\.h, z1\.h\}, p0/z, \[x3\]
--.*: a4a0e060 ld2h \{z0\.h, z1\.h\}, p0/z, \[x3\]
--.*: a4a0e060 ld2h \{z0\.h, z1\.h\}, p0/z, \[x3\]
--.*: a4a0e060 ld2h \{z0\.h, z1\.h\}, p0/z, \[x3\]
--.*: a4a0e060 ld2h \{z0\.h, z1\.h\}, p0/z, \[x3\]
--.*: a4a0e060 ld2h \{z0\.h, z1\.h\}, p0/z, \[x3\]
--.*: a4a0e3e0 ld2h \{z0\.h, z1\.h\}, p0/z, \[sp\]
--.*: a4a0e3e0 ld2h \{z0\.h, z1\.h\}, p0/z, \[sp\]
--.*: a4a0e3e0 ld2h \{z0\.h, z1\.h\}, p0/z, \[sp\]
--.*: a4a0e3e0 ld2h \{z0\.h, z1\.h\}, p0/z, \[sp\]
--.*: a4a0e3e0 ld2h \{z0\.h, z1\.h\}, p0/z, \[sp\]
--.*: a4a0e3e0 ld2h \{z0\.h, z1\.h\}, p0/z, \[sp\]
--.*: a4a0e3e0 ld2h \{z0\.h, z1\.h\}, p0/z, \[sp\]
--.*: a4a7e000 ld2h \{z0\.h, z1\.h\}, p0/z, \[x0, #14, mul vl\]
--.*: a4a7e000 ld2h \{z0\.h, z1\.h\}, p0/z, \[x0, #14, mul vl\]
--.*: a4a7e000 ld2h \{z0\.h, z1\.h\}, p0/z, \[x0, #14, mul vl\]
--.*: a4a8e000 ld2h \{z0\.h, z1\.h\}, p0/z, \[x0, #-16, mul vl\]
--.*: a4a8e000 ld2h \{z0\.h, z1\.h\}, p0/z, \[x0, #-16, mul vl\]
--.*: a4a8e000 ld2h \{z0\.h, z1\.h\}, p0/z, \[x0, #-16, mul vl\]
--.*: a4a9e000 ld2h \{z0\.h, z1\.h\}, p0/z, \[x0, #-14, mul vl\]
--.*: a4a9e000 ld2h \{z0\.h, z1\.h\}, p0/z, \[x0, #-14, mul vl\]
--.*: a4a9e000 ld2h \{z0\.h, z1\.h\}, p0/z, \[x0, #-14, mul vl\]
--.*: a4afe000 ld2h \{z0\.h, z1\.h\}, p0/z, \[x0, #-2, mul vl\]
--.*: a4afe000 ld2h \{z0\.h, z1\.h\}, p0/z, \[x0, #-2, mul vl\]
--.*: a4afe000 ld2h \{z0\.h, z1\.h\}, p0/z, \[x0, #-2, mul vl\]
--.*: a520c000 ld2w \{z0\.s, z1\.s\}, p0/z, \[x0, x0, lsl #2\]
--.*: a520c000 ld2w \{z0\.s, z1\.s\}, p0/z, \[x0, x0, lsl #2\]
--.*: a520c000 ld2w \{z0\.s, z1\.s\}, p0/z, \[x0, x0, lsl #2\]
--.*: a520c001 ld2w \{z1\.s, z2\.s\}, p0/z, \[x0, x0, lsl #2\]
--.*: a520c001 ld2w \{z1\.s, z2\.s\}, p0/z, \[x0, x0, lsl #2\]
--.*: a520c001 ld2w \{z1\.s, z2\.s\}, p0/z, \[x0, x0, lsl #2\]
--.*: a520c01f ld2w \{z31\.s, z0\.s\}, p0/z, \[x0, x0, lsl #2\]
--.*: a520c01f ld2w \{z31\.s, z0\.s\}, p0/z, \[x0, x0, lsl #2\]
--.*: a520c800 ld2w \{z0\.s, z1\.s\}, p2/z, \[x0, x0, lsl #2\]
--.*: a520c800 ld2w \{z0\.s, z1\.s\}, p2/z, \[x0, x0, lsl #2\]
--.*: a520c800 ld2w \{z0\.s, z1\.s\}, p2/z, \[x0, x0, lsl #2\]
--.*: a520dc00 ld2w \{z0\.s, z1\.s\}, p7/z, \[x0, x0, lsl #2\]
--.*: a520dc00 ld2w \{z0\.s, z1\.s\}, p7/z, \[x0, x0, lsl #2\]
--.*: a520dc00 ld2w \{z0\.s, z1\.s\}, p7/z, \[x0, x0, lsl #2\]
--.*: a520c060 ld2w \{z0\.s, z1\.s\}, p0/z, \[x3, x0, lsl #2\]
--.*: a520c060 ld2w \{z0\.s, z1\.s\}, p0/z, \[x3, x0, lsl #2\]
--.*: a520c060 ld2w \{z0\.s, z1\.s\}, p0/z, \[x3, x0, lsl #2\]
--.*: a520c3e0 ld2w \{z0\.s, z1\.s\}, p0/z, \[sp, x0, lsl #2\]
--.*: a520c3e0 ld2w \{z0\.s, z1\.s\}, p0/z, \[sp, x0, lsl #2\]
--.*: a520c3e0 ld2w \{z0\.s, z1\.s\}, p0/z, \[sp, x0, lsl #2\]
--.*: a524c000 ld2w \{z0\.s, z1\.s\}, p0/z, \[x0, x4, lsl #2\]
--.*: a524c000 ld2w \{z0\.s, z1\.s\}, p0/z, \[x0, x4, lsl #2\]
--.*: a524c000 ld2w \{z0\.s, z1\.s\}, p0/z, \[x0, x4, lsl #2\]
--.*: a53ec000 ld2w \{z0\.s, z1\.s\}, p0/z, \[x0, x30, lsl #2\]
--.*: a53ec000 ld2w \{z0\.s, z1\.s\}, p0/z, \[x0, x30, lsl #2\]
--.*: a53ec000 ld2w \{z0\.s, z1\.s\}, p0/z, \[x0, x30, lsl #2\]
--.*: a520e000 ld2w \{z0\.s, z1\.s\}, p0/z, \[x0\]
--.*: a520e000 ld2w \{z0\.s, z1\.s\}, p0/z, \[x0\]
--.*: a520e000 ld2w \{z0\.s, z1\.s\}, p0/z, \[x0\]
--.*: a520e000 ld2w \{z0\.s, z1\.s\}, p0/z, \[x0\]
--.*: a520e000 ld2w \{z0\.s, z1\.s\}, p0/z, \[x0\]
--.*: a520e000 ld2w \{z0\.s, z1\.s\}, p0/z, \[x0\]
--.*: a520e000 ld2w \{z0\.s, z1\.s\}, p0/z, \[x0\]
--.*: a520e001 ld2w \{z1\.s, z2\.s\}, p0/z, \[x0\]
--.*: a520e001 ld2w \{z1\.s, z2\.s\}, p0/z, \[x0\]
--.*: a520e001 ld2w \{z1\.s, z2\.s\}, p0/z, \[x0\]
--.*: a520e001 ld2w \{z1\.s, z2\.s\}, p0/z, \[x0\]
--.*: a520e001 ld2w \{z1\.s, z2\.s\}, p0/z, \[x0\]
--.*: a520e001 ld2w \{z1\.s, z2\.s\}, p0/z, \[x0\]
--.*: a520e001 ld2w \{z1\.s, z2\.s\}, p0/z, \[x0\]
--.*: a520e01f ld2w \{z31\.s, z0\.s\}, p0/z, \[x0\]
--.*: a520e01f ld2w \{z31\.s, z0\.s\}, p0/z, \[x0\]
--.*: a520e01f ld2w \{z31\.s, z0\.s\}, p0/z, \[x0\]
--.*: a520e01f ld2w \{z31\.s, z0\.s\}, p0/z, \[x0\]
--.*: a520e800 ld2w \{z0\.s, z1\.s\}, p2/z, \[x0\]
--.*: a520e800 ld2w \{z0\.s, z1\.s\}, p2/z, \[x0\]
--.*: a520e800 ld2w \{z0\.s, z1\.s\}, p2/z, \[x0\]
--.*: a520e800 ld2w \{z0\.s, z1\.s\}, p2/z, \[x0\]
--.*: a520e800 ld2w \{z0\.s, z1\.s\}, p2/z, \[x0\]
--.*: a520e800 ld2w \{z0\.s, z1\.s\}, p2/z, \[x0\]
--.*: a520e800 ld2w \{z0\.s, z1\.s\}, p2/z, \[x0\]
--.*: a520fc00 ld2w \{z0\.s, z1\.s\}, p7/z, \[x0\]
--.*: a520fc00 ld2w \{z0\.s, z1\.s\}, p7/z, \[x0\]
--.*: a520fc00 ld2w \{z0\.s, z1\.s\}, p7/z, \[x0\]
--.*: a520fc00 ld2w \{z0\.s, z1\.s\}, p7/z, \[x0\]
--.*: a520fc00 ld2w \{z0\.s, z1\.s\}, p7/z, \[x0\]
--.*: a520fc00 ld2w \{z0\.s, z1\.s\}, p7/z, \[x0\]
--.*: a520fc00 ld2w \{z0\.s, z1\.s\}, p7/z, \[x0\]
--.*: a520e060 ld2w \{z0\.s, z1\.s\}, p0/z, \[x3\]
--.*: a520e060 ld2w \{z0\.s, z1\.s\}, p0/z, \[x3\]
--.*: a520e060 ld2w \{z0\.s, z1\.s\}, p0/z, \[x3\]
--.*: a520e060 ld2w \{z0\.s, z1\.s\}, p0/z, \[x3\]
--.*: a520e060 ld2w \{z0\.s, z1\.s\}, p0/z, \[x3\]
--.*: a520e060 ld2w \{z0\.s, z1\.s\}, p0/z, \[x3\]
--.*: a520e060 ld2w \{z0\.s, z1\.s\}, p0/z, \[x3\]
--.*: a520e3e0 ld2w \{z0\.s, z1\.s\}, p0/z, \[sp\]
--.*: a520e3e0 ld2w \{z0\.s, z1\.s\}, p0/z, \[sp\]
--.*: a520e3e0 ld2w \{z0\.s, z1\.s\}, p0/z, \[sp\]
--.*: a520e3e0 ld2w \{z0\.s, z1\.s\}, p0/z, \[sp\]
--.*: a520e3e0 ld2w \{z0\.s, z1\.s\}, p0/z, \[sp\]
--.*: a520e3e0 ld2w \{z0\.s, z1\.s\}, p0/z, \[sp\]
--.*: a520e3e0 ld2w \{z0\.s, z1\.s\}, p0/z, \[sp\]
--.*: a527e000 ld2w \{z0\.s, z1\.s\}, p0/z, \[x0, #14, mul vl\]
--.*: a527e000 ld2w \{z0\.s, z1\.s\}, p0/z, \[x0, #14, mul vl\]
--.*: a527e000 ld2w \{z0\.s, z1\.s\}, p0/z, \[x0, #14, mul vl\]
--.*: a528e000 ld2w \{z0\.s, z1\.s\}, p0/z, \[x0, #-16, mul vl\]
--.*: a528e000 ld2w \{z0\.s, z1\.s\}, p0/z, \[x0, #-16, mul vl\]
--.*: a528e000 ld2w \{z0\.s, z1\.s\}, p0/z, \[x0, #-16, mul vl\]
--.*: a529e000 ld2w \{z0\.s, z1\.s\}, p0/z, \[x0, #-14, mul vl\]
--.*: a529e000 ld2w \{z0\.s, z1\.s\}, p0/z, \[x0, #-14, mul vl\]
--.*: a529e000 ld2w \{z0\.s, z1\.s\}, p0/z, \[x0, #-14, mul vl\]
--.*: a52fe000 ld2w \{z0\.s, z1\.s\}, p0/z, \[x0, #-2, mul vl\]
--.*: a52fe000 ld2w \{z0\.s, z1\.s\}, p0/z, \[x0, #-2, mul vl\]
--.*: a52fe000 ld2w \{z0\.s, z1\.s\}, p0/z, \[x0, #-2, mul vl\]
--.*: a440c000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0, x0\]
--.*: a440c000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0, x0\]
--.*: a440c000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0, x0\]
--.*: a440c000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0, x0\]
--.*: a440c000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0, x0\]
--.*: a440c001 ld3b \{z1\.b-z3\.b\}, p0/z, \[x0, x0\]
--.*: a440c001 ld3b \{z1\.b-z3\.b\}, p0/z, \[x0, x0\]
--.*: a440c001 ld3b \{z1\.b-z3\.b\}, p0/z, \[x0, x0\]
--.*: a440c001 ld3b \{z1\.b-z3\.b\}, p0/z, \[x0, x0\]
--.*: a440c001 ld3b \{z1\.b-z3\.b\}, p0/z, \[x0, x0\]
--.*: a440c01f ld3b \{z31\.b, z0\.b, z1\.b\}, p0/z, \[x0, x0\]
--.*: a440c01f ld3b \{z31\.b, z0\.b, z1\.b\}, p0/z, \[x0, x0\]
--.*: a440c01f ld3b \{z31\.b, z0\.b, z1\.b\}, p0/z, \[x0, x0\]
--.*: a440c800 ld3b \{z0\.b-z2\.b\}, p2/z, \[x0, x0\]
--.*: a440c800 ld3b \{z0\.b-z2\.b\}, p2/z, \[x0, x0\]
--.*: a440c800 ld3b \{z0\.b-z2\.b\}, p2/z, \[x0, x0\]
--.*: a440c800 ld3b \{z0\.b-z2\.b\}, p2/z, \[x0, x0\]
--.*: a440c800 ld3b \{z0\.b-z2\.b\}, p2/z, \[x0, x0\]
--.*: a440dc00 ld3b \{z0\.b-z2\.b\}, p7/z, \[x0, x0\]
--.*: a440dc00 ld3b \{z0\.b-z2\.b\}, p7/z, \[x0, x0\]
--.*: a440dc00 ld3b \{z0\.b-z2\.b\}, p7/z, \[x0, x0\]
--.*: a440dc00 ld3b \{z0\.b-z2\.b\}, p7/z, \[x0, x0\]
--.*: a440dc00 ld3b \{z0\.b-z2\.b\}, p7/z, \[x0, x0\]
--.*: a440c060 ld3b \{z0\.b-z2\.b\}, p0/z, \[x3, x0\]
--.*: a440c060 ld3b \{z0\.b-z2\.b\}, p0/z, \[x3, x0\]
--.*: a440c060 ld3b \{z0\.b-z2\.b\}, p0/z, \[x3, x0\]
--.*: a440c060 ld3b \{z0\.b-z2\.b\}, p0/z, \[x3, x0\]
--.*: a440c060 ld3b \{z0\.b-z2\.b\}, p0/z, \[x3, x0\]
--.*: a440c3e0 ld3b \{z0\.b-z2\.b\}, p0/z, \[sp, x0\]
--.*: a440c3e0 ld3b \{z0\.b-z2\.b\}, p0/z, \[sp, x0\]
--.*: a440c3e0 ld3b \{z0\.b-z2\.b\}, p0/z, \[sp, x0\]
--.*: a440c3e0 ld3b \{z0\.b-z2\.b\}, p0/z, \[sp, x0\]
--.*: a440c3e0 ld3b \{z0\.b-z2\.b\}, p0/z, \[sp, x0\]
--.*: a444c000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0, x4\]
--.*: a444c000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0, x4\]
--.*: a444c000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0, x4\]
--.*: a444c000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0, x4\]
--.*: a444c000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0, x4\]
--.*: a45ec000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0, x30\]
--.*: a45ec000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0, x30\]
--.*: a45ec000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0, x30\]
--.*: a45ec000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0, x30\]
--.*: a45ec000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0, x30\]
--.*: a440e000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0\]
--.*: a440e000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0\]
--.*: a440e000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0\]
--.*: a440e000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0\]
--.*: a440e000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0\]
--.*: a440e000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0\]
--.*: a440e000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0\]
--.*: a440e001 ld3b \{z1\.b-z3\.b\}, p0/z, \[x0\]
--.*: a440e001 ld3b \{z1\.b-z3\.b\}, p0/z, \[x0\]
--.*: a440e001 ld3b \{z1\.b-z3\.b\}, p0/z, \[x0\]
--.*: a440e001 ld3b \{z1\.b-z3\.b\}, p0/z, \[x0\]
--.*: a440e001 ld3b \{z1\.b-z3\.b\}, p0/z, \[x0\]
--.*: a440e001 ld3b \{z1\.b-z3\.b\}, p0/z, \[x0\]
--.*: a440e001 ld3b \{z1\.b-z3\.b\}, p0/z, \[x0\]
--.*: a440e01f ld3b \{z31\.b, z0\.b, z1\.b\}, p0/z, \[x0\]
--.*: a440e01f ld3b \{z31\.b, z0\.b, z1\.b\}, p0/z, \[x0\]
--.*: a440e01f ld3b \{z31\.b, z0\.b, z1\.b\}, p0/z, \[x0\]
--.*: a440e01f ld3b \{z31\.b, z0\.b, z1\.b\}, p0/z, \[x0\]
--.*: a440e800 ld3b \{z0\.b-z2\.b\}, p2/z, \[x0\]
--.*: a440e800 ld3b \{z0\.b-z2\.b\}, p2/z, \[x0\]
--.*: a440e800 ld3b \{z0\.b-z2\.b\}, p2/z, \[x0\]
--.*: a440e800 ld3b \{z0\.b-z2\.b\}, p2/z, \[x0\]
--.*: a440e800 ld3b \{z0\.b-z2\.b\}, p2/z, \[x0\]
--.*: a440e800 ld3b \{z0\.b-z2\.b\}, p2/z, \[x0\]
--.*: a440e800 ld3b \{z0\.b-z2\.b\}, p2/z, \[x0\]
--.*: a440fc00 ld3b \{z0\.b-z2\.b\}, p7/z, \[x0\]
--.*: a440fc00 ld3b \{z0\.b-z2\.b\}, p7/z, \[x0\]
--.*: a440fc00 ld3b \{z0\.b-z2\.b\}, p7/z, \[x0\]
--.*: a440fc00 ld3b \{z0\.b-z2\.b\}, p7/z, \[x0\]
--.*: a440fc00 ld3b \{z0\.b-z2\.b\}, p7/z, \[x0\]
--.*: a440fc00 ld3b \{z0\.b-z2\.b\}, p7/z, \[x0\]
--.*: a440fc00 ld3b \{z0\.b-z2\.b\}, p7/z, \[x0\]
--.*: a440e060 ld3b \{z0\.b-z2\.b\}, p0/z, \[x3\]
--.*: a440e060 ld3b \{z0\.b-z2\.b\}, p0/z, \[x3\]
--.*: a440e060 ld3b \{z0\.b-z2\.b\}, p0/z, \[x3\]
--.*: a440e060 ld3b \{z0\.b-z2\.b\}, p0/z, \[x3\]
--.*: a440e060 ld3b \{z0\.b-z2\.b\}, p0/z, \[x3\]
--.*: a440e060 ld3b \{z0\.b-z2\.b\}, p0/z, \[x3\]
--.*: a440e060 ld3b \{z0\.b-z2\.b\}, p0/z, \[x3\]
--.*: a440e3e0 ld3b \{z0\.b-z2\.b\}, p0/z, \[sp\]
--.*: a440e3e0 ld3b \{z0\.b-z2\.b\}, p0/z, \[sp\]
--.*: a440e3e0 ld3b \{z0\.b-z2\.b\}, p0/z, \[sp\]
--.*: a440e3e0 ld3b \{z0\.b-z2\.b\}, p0/z, \[sp\]
--.*: a440e3e0 ld3b \{z0\.b-z2\.b\}, p0/z, \[sp\]
--.*: a440e3e0 ld3b \{z0\.b-z2\.b\}, p0/z, \[sp\]
--.*: a440e3e0 ld3b \{z0\.b-z2\.b\}, p0/z, \[sp\]
--.*: a447e000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0, #21, mul vl\]
--.*: a447e000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0, #21, mul vl\]
--.*: a447e000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0, #21, mul vl\]
--.*: a448e000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0, #-24, mul vl\]
--.*: a448e000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0, #-24, mul vl\]
--.*: a448e000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0, #-24, mul vl\]
--.*: a449e000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0, #-21, mul vl\]
--.*: a449e000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0, #-21, mul vl\]
--.*: a449e000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0, #-21, mul vl\]
--.*: a44fe000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0, #-3, mul vl\]
--.*: a44fe000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0, #-3, mul vl\]
--.*: a44fe000 ld3b \{z0\.b-z2\.b\}, p0/z, \[x0, #-3, mul vl\]
--.*: a5c0c000 ld3d \{z0\.d-z2\.d\}, p0/z, \[x0, x0, lsl #3\]
--.*: a5c0c000 ld3d \{z0\.d-z2\.d\}, p0/z, \[x0, x0, lsl #3\]
--.*: a5c0c000 ld3d \{z0\.d-z2\.d\}, p0/z, \[x0, x0, lsl #3\]
--.*: a5c0c001 ld3d \{z1\.d-z3\.d\}, p0/z, \[x0, x0, lsl #3\]
--.*: a5c0c001 ld3d \{z1\.d-z3\.d\}, p0/z, \[x0, x0, lsl #3\]
--.*: a5c0c001 ld3d \{z1\.d-z3\.d\}, p0/z, \[x0, x0, lsl #3\]
--.*: a5c0c01f ld3d \{z31\.d, z0\.d, z1\.d\}, p0/z, \[x0, x0, lsl #3\]
--.*: a5c0c01f ld3d \{z31\.d, z0\.d, z1\.d\}, p0/z, \[x0, x0, lsl #3\]
--.*: a5c0c800 ld3d \{z0\.d-z2\.d\}, p2/z, \[x0, x0, lsl #3\]
--.*: a5c0c800 ld3d \{z0\.d-z2\.d\}, p2/z, \[x0, x0, lsl #3\]
--.*: a5c0c800 ld3d \{z0\.d-z2\.d\}, p2/z, \[x0, x0, lsl #3\]
--.*: a5c0dc00 ld3d \{z0\.d-z2\.d\}, p7/z, \[x0, x0, lsl #3\]
--.*: a5c0dc00 ld3d \{z0\.d-z2\.d\}, p7/z, \[x0, x0, lsl #3\]
--.*: a5c0dc00 ld3d \{z0\.d-z2\.d\}, p7/z, \[x0, x0, lsl #3\]
--.*: a5c0c060 ld3d \{z0\.d-z2\.d\}, p0/z, \[x3, x0, lsl #3\]
--.*: a5c0c060 ld3d \{z0\.d-z2\.d\}, p0/z, \[x3, x0, lsl #3\]
--.*: a5c0c060 ld3d \{z0\.d-z2\.d\}, p0/z, \[x3, x0, lsl #3\]
--.*: a5c0c3e0 ld3d \{z0\.d-z2\.d\}, p0/z, \[sp, x0, lsl #3\]
--.*: a5c0c3e0 ld3d \{z0\.d-z2\.d\}, p0/z, \[sp, x0, lsl #3\]
--.*: a5c0c3e0 ld3d \{z0\.d-z2\.d\}, p0/z, \[sp, x0, lsl #3\]
--.*: a5c4c000 ld3d \{z0\.d-z2\.d\}, p0/z, \[x0, x4, lsl #3\]
--.*: a5c4c000 ld3d \{z0\.d-z2\.d\}, p0/z, \[x0, x4, lsl #3\]
--.*: a5c4c000 ld3d \{z0\.d-z2\.d\}, p0/z, \[x0, x4, lsl #3\]
--.*: a5dec000 ld3d \{z0\.d-z2\.d\}, p0/z, \[x0, x30, lsl #3\]
--.*: a5dec000 ld3d \{z0\.d-z2\.d\}, p0/z, \[x0, x30, lsl #3\]
--.*: a5dec000 ld3d \{z0\.d-z2\.d\}, p0/z, \[x0, x30, lsl #3\]
--.*: a5c0e000 ld3d \{z0\.d-z2\.d\}, p0/z, \[x0\]
--.*: a5c0e000 ld3d \{z0\.d-z2\.d\}, p0/z, \[x0\]
--.*: a5c0e000 ld3d \{z0\.d-z2\.d\}, p0/z, \[x0\]
--.*: a5c0e000 ld3d \{z0\.d-z2\.d\}, p0/z, \[x0\]
--.*: a5c0e000 ld3d \{z0\.d-z2\.d\}, p0/z, \[x0\]
--.*: a5c0e000 ld3d \{z0\.d-z2\.d\}, p0/z, \[x0\]
--.*: a5c0e000 ld3d \{z0\.d-z2\.d\}, p0/z, \[x0\]
--.*: a5c0e001 ld3d \{z1\.d-z3\.d\}, p0/z, \[x0\]
--.*: a5c0e001 ld3d \{z1\.d-z3\.d\}, p0/z, \[x0\]
--.*: a5c0e001 ld3d \{z1\.d-z3\.d\}, p0/z, \[x0\]
--.*: a5c0e001 ld3d \{z1\.d-z3\.d\}, p0/z, \[x0\]
--.*: a5c0e001 ld3d \{z1\.d-z3\.d\}, p0/z, \[x0\]
--.*: a5c0e001 ld3d \{z1\.d-z3\.d\}, p0/z, \[x0\]
--.*: a5c0e001 ld3d \{z1\.d-z3\.d\}, p0/z, \[x0\]
--.*: a5c0e01f ld3d \{z31\.d, z0\.d, z1\.d\}, p0/z, \[x0\]
--.*: a5c0e01f ld3d \{z31\.d, z0\.d, z1\.d\}, p0/z, \[x0\]
--.*: a5c0e01f ld3d \{z31\.d, z0\.d, z1\.d\}, p0/z, \[x0\]
--.*: a5c0e01f ld3d \{z31\.d, z0\.d, z1\.d\}, p0/z, \[x0\]
--.*: a5c0e800 ld3d \{z0\.d-z2\.d\}, p2/z, \[x0\]
--.*: a5c0e800 ld3d \{z0\.d-z2\.d\}, p2/z, \[x0\]
--.*: a5c0e800 ld3d \{z0\.d-z2\.d\}, p2/z, \[x0\]
--.*: a5c0e800 ld3d \{z0\.d-z2\.d\}, p2/z, \[x0\]
--.*: a5c0e800 ld3d \{z0\.d-z2\.d\}, p2/z, \[x0\]
--.*: a5c0e800 ld3d \{z0\.d-z2\.d\}, p2/z, \[x0\]
--.*: a5c0e800 ld3d \{z0\.d-z2\.d\}, p2/z, \[x0\]
--.*: a5c0fc00 ld3d \{z0\.d-z2\.d\}, p7/z, \[x0\]
--.*: a5c0fc00 ld3d \{z0\.d-z2\.d\}, p7/z, \[x0\]
--.*: a5c0fc00 ld3d \{z0\.d-z2\.d\}, p7/z, \[x0\]
--.*: a5c0fc00 ld3d \{z0\.d-z2\.d\}, p7/z, \[x0\]
--.*: a5c0fc00 ld3d \{z0\.d-z2\.d\}, p7/z, \[x0\]
--.*: a5c0fc00 ld3d \{z0\.d-z2\.d\}, p7/z, \[x0\]
--.*: a5c0fc00 ld3d \{z0\.d-z2\.d\}, p7/z, \[x0\]
--.*: a5c0e060 ld3d \{z0\.d-z2\.d\}, p0/z, \[x3\]
--.*: a5c0e060 ld3d \{z0\.d-z2\.d\}, p0/z, \[x3\]
--.*: a5c0e060 ld3d \{z0\.d-z2\.d\}, p0/z, \[x3\]
--.*: a5c0e060 ld3d \{z0\.d-z2\.d\}, p0/z, \[x3\]
--.*: a5c0e060 ld3d \{z0\.d-z2\.d\}, p0/z, \[x3\]
--.*: a5c0e060 ld3d \{z0\.d-z2\.d\}, p0/z, \[x3\]
--.*: a5c0e060 ld3d \{z0\.d-z2\.d\}, p0/z, \[x3\]
--.*: a5c0e3e0 ld3d \{z0\.d-z2\.d\}, p0/z, \[sp\]
--.*: a5c0e3e0 ld3d \{z0\.d-z2\.d\}, p0/z, \[sp\]
--.*: a5c0e3e0 ld3d \{z0\.d-z2\.d\}, p0/z, \[sp\]
--.*: a5c0e3e0 ld3d \{z0\.d-z2\.d\}, p0/z, \[sp\]
--.*: a5c0e3e0 ld3d \{z0\.d-z2\.d\}, p0/z, \[sp\]
--.*: a5c0e3e0 ld3d \{z0\.d-z2\.d\}, p0/z, \[sp\]
--.*: a5c0e3e0 ld3d \{z0\.d-z2\.d\}, p0/z, \[sp\]
--.*: a5c7e000 ld3d \{z0\.d-z2\.d\}, p0/z, \[x0, #21, mul vl\]
--.*: a5c7e000 ld3d \{z0\.d-z2\.d\}, p0/z, \[x0, #21, mul vl\]
--.*: a5c7e000 ld3d \{z0\.d-z2\.d\}, p0/z, \[x0, #21, mul vl\]
--.*: a5c8e000 ld3d \{z0\.d-z2\.d\}, p0/z, \[x0, #-24, mul vl\]
--.*: a5c8e000 ld3d \{z0\.d-z2\.d\}, p0/z, \[x0, #-24, mul vl\]
--.*: a5c8e000 ld3d \{z0\.d-z2\.d\}, p0/z, \[x0, #-24, mul vl\]
--.*: a5c9e000 ld3d \{z0\.d-z2\.d\}, p0/z, \[x0, #-21, mul vl\]
--.*: a5c9e000 ld3d \{z0\.d-z2\.d\}, p0/z, \[x0, #-21, mul vl\]
--.*: a5c9e000 ld3d \{z0\.d-z2\.d\}, p0/z, \[x0, #-21, mul vl\]
--.*: a5cfe000 ld3d \{z0\.d-z2\.d\}, p0/z, \[x0, #-3, mul vl\]
--.*: a5cfe000 ld3d \{z0\.d-z2\.d\}, p0/z, \[x0, #-3, mul vl\]
--.*: a5cfe000 ld3d \{z0\.d-z2\.d\}, p0/z, \[x0, #-3, mul vl\]
--.*: a4c0c000 ld3h \{z0\.h-z2\.h\}, p0/z, \[x0, x0, lsl #1\]
--.*: a4c0c000 ld3h \{z0\.h-z2\.h\}, p0/z, \[x0, x0, lsl #1\]
--.*: a4c0c000 ld3h \{z0\.h-z2\.h\}, p0/z, \[x0, x0, lsl #1\]
--.*: a4c0c001 ld3h \{z1\.h-z3\.h\}, p0/z, \[x0, x0, lsl #1\]
--.*: a4c0c001 ld3h \{z1\.h-z3\.h\}, p0/z, \[x0, x0, lsl #1\]
--.*: a4c0c001 ld3h \{z1\.h-z3\.h\}, p0/z, \[x0, x0, lsl #1\]
--.*: a4c0c01f ld3h \{z31\.h, z0\.h, z1\.h\}, p0/z, \[x0, x0, lsl #1\]
--.*: a4c0c01f ld3h \{z31\.h, z0\.h, z1\.h\}, p0/z, \[x0, x0, lsl #1\]
--.*: a4c0c800 ld3h \{z0\.h-z2\.h\}, p2/z, \[x0, x0, lsl #1\]
--.*: a4c0c800 ld3h \{z0\.h-z2\.h\}, p2/z, \[x0, x0, lsl #1\]
--.*: a4c0c800 ld3h \{z0\.h-z2\.h\}, p2/z, \[x0, x0, lsl #1\]
--.*: a4c0dc00 ld3h \{z0\.h-z2\.h\}, p7/z, \[x0, x0, lsl #1\]
--.*: a4c0dc00 ld3h \{z0\.h-z2\.h\}, p7/z, \[x0, x0, lsl #1\]
--.*: a4c0dc00 ld3h \{z0\.h-z2\.h\}, p7/z, \[x0, x0, lsl #1\]
--.*: a4c0c060 ld3h \{z0\.h-z2\.h\}, p0/z, \[x3, x0, lsl #1\]
--.*: a4c0c060 ld3h \{z0\.h-z2\.h\}, p0/z, \[x3, x0, lsl #1\]
--.*: a4c0c060 ld3h \{z0\.h-z2\.h\}, p0/z, \[x3, x0, lsl #1\]
--.*: a4c0c3e0 ld3h \{z0\.h-z2\.h\}, p0/z, \[sp, x0, lsl #1\]
--.*: a4c0c3e0 ld3h \{z0\.h-z2\.h\}, p0/z, \[sp, x0, lsl #1\]
--.*: a4c0c3e0 ld3h \{z0\.h-z2\.h\}, p0/z, \[sp, x0, lsl #1\]
--.*: a4c4c000 ld3h \{z0\.h-z2\.h\}, p0/z, \[x0, x4, lsl #1\]
--.*: a4c4c000 ld3h \{z0\.h-z2\.h\}, p0/z, \[x0, x4, lsl #1\]
--.*: a4c4c000 ld3h \{z0\.h-z2\.h\}, p0/z, \[x0, x4, lsl #1\]
--.*: a4dec000 ld3h \{z0\.h-z2\.h\}, p0/z, \[x0, x30, lsl #1\]
--.*: a4dec000 ld3h \{z0\.h-z2\.h\}, p0/z, \[x0, x30, lsl #1\]
--.*: a4dec000 ld3h \{z0\.h-z2\.h\}, p0/z, \[x0, x30, lsl #1\]
--.*: a4c0e000 ld3h \{z0\.h-z2\.h\}, p0/z, \[x0\]
--.*: a4c0e000 ld3h \{z0\.h-z2\.h\}, p0/z, \[x0\]
--.*: a4c0e000 ld3h \{z0\.h-z2\.h\}, p0/z, \[x0\]
--.*: a4c0e000 ld3h \{z0\.h-z2\.h\}, p0/z, \[x0\]
--.*: a4c0e000 ld3h \{z0\.h-z2\.h\}, p0/z, \[x0\]
--.*: a4c0e000 ld3h \{z0\.h-z2\.h\}, p0/z, \[x0\]
--.*: a4c0e000 ld3h \{z0\.h-z2\.h\}, p0/z, \[x0\]
--.*: a4c0e001 ld3h \{z1\.h-z3\.h\}, p0/z, \[x0\]
--.*: a4c0e001 ld3h \{z1\.h-z3\.h\}, p0/z, \[x0\]
--.*: a4c0e001 ld3h \{z1\.h-z3\.h\}, p0/z, \[x0\]
--.*: a4c0e001 ld3h \{z1\.h-z3\.h\}, p0/z, \[x0\]
--.*: a4c0e001 ld3h \{z1\.h-z3\.h\}, p0/z, \[x0\]
--.*: a4c0e001 ld3h \{z1\.h-z3\.h\}, p0/z, \[x0\]
--.*: a4c0e001 ld3h \{z1\.h-z3\.h\}, p0/z, \[x0\]
--.*: a4c0e01f ld3h \{z31\.h, z0\.h, z1\.h\}, p0/z, \[x0\]
--.*: a4c0e01f ld3h \{z31\.h, z0\.h, z1\.h\}, p0/z, \[x0\]
--.*: a4c0e01f ld3h \{z31\.h, z0\.h, z1\.h\}, p0/z, \[x0\]
--.*: a4c0e01f ld3h \{z31\.h, z0\.h, z1\.h\}, p0/z, \[x0\]
--.*: a4c0e800 ld3h \{z0\.h-z2\.h\}, p2/z, \[x0\]
--.*: a4c0e800 ld3h \{z0\.h-z2\.h\}, p2/z, \[x0\]
--.*: a4c0e800 ld3h \{z0\.h-z2\.h\}, p2/z, \[x0\]
--.*: a4c0e800 ld3h \{z0\.h-z2\.h\}, p2/z, \[x0\]
--.*: a4c0e800 ld3h \{z0\.h-z2\.h\}, p2/z, \[x0\]
--.*: a4c0e800 ld3h \{z0\.h-z2\.h\}, p2/z, \[x0\]
--.*: a4c0e800 ld3h \{z0\.h-z2\.h\}, p2/z, \[x0\]
--.*: a4c0fc00 ld3h \{z0\.h-z2\.h\}, p7/z, \[x0\]
--.*: a4c0fc00 ld3h \{z0\.h-z2\.h\}, p7/z, \[x0\]
--.*: a4c0fc00 ld3h \{z0\.h-z2\.h\}, p7/z, \[x0\]
--.*: a4c0fc00 ld3h \{z0\.h-z2\.h\}, p7/z, \[x0\]
--.*: a4c0fc00 ld3h \{z0\.h-z2\.h\}, p7/z, \[x0\]
--.*: a4c0fc00 ld3h \{z0\.h-z2\.h\}, p7/z, \[x0\]
--.*: a4c0fc00 ld3h \{z0\.h-z2\.h\}, p7/z, \[x0\]
--.*: a4c0e060 ld3h \{z0\.h-z2\.h\}, p0/z, \[x3\]
--.*: a4c0e060 ld3h \{z0\.h-z2\.h\}, p0/z, \[x3\]
--.*: a4c0e060 ld3h \{z0\.h-z2\.h\}, p0/z, \[x3\]
--.*: a4c0e060 ld3h \{z0\.h-z2\.h\}, p0/z, \[x3\]
--.*: a4c0e060 ld3h \{z0\.h-z2\.h\}, p0/z, \[x3\]
--.*: a4c0e060 ld3h \{z0\.h-z2\.h\}, p0/z, \[x3\]
--.*: a4c0e060 ld3h \{z0\.h-z2\.h\}, p0/z, \[x3\]
--.*: a4c0e3e0 ld3h \{z0\.h-z2\.h\}, p0/z, \[sp\]
--.*: a4c0e3e0 ld3h \{z0\.h-z2\.h\}, p0/z, \[sp\]
--.*: a4c0e3e0 ld3h \{z0\.h-z2\.h\}, p0/z, \[sp\]
--.*: a4c0e3e0 ld3h \{z0\.h-z2\.h\}, p0/z, \[sp\]
--.*: a4c0e3e0 ld3h \{z0\.h-z2\.h\}, p0/z, \[sp\]
--.*: a4c0e3e0 ld3h \{z0\.h-z2\.h\}, p0/z, \[sp\]
--.*: a4c0e3e0 ld3h \{z0\.h-z2\.h\}, p0/z, \[sp\]
--.*: a4c7e000 ld3h \{z0\.h-z2\.h\}, p0/z, \[x0, #21, mul vl\]
--.*: a4c7e000 ld3h \{z0\.h-z2\.h\}, p0/z, \[x0, #21, mul vl\]
--.*: a4c7e000 ld3h \{z0\.h-z2\.h\}, p0/z, \[x0, #21, mul vl\]
--.*: a4c8e000 ld3h \{z0\.h-z2\.h\}, p0/z, \[x0, #-24, mul vl\]
--.*: a4c8e000 ld3h \{z0\.h-z2\.h\}, p0/z, \[x0, #-24, mul vl\]
--.*: a4c8e000 ld3h \{z0\.h-z2\.h\}, p0/z, \[x0, #-24, mul vl\]
--.*: a4c9e000 ld3h \{z0\.h-z2\.h\}, p0/z, \[x0, #-21, mul vl\]
--.*: a4c9e000 ld3h \{z0\.h-z2\.h\}, p0/z, \[x0, #-21, mul vl\]
--.*: a4c9e000 ld3h \{z0\.h-z2\.h\}, p0/z, \[x0, #-21, mul vl\]
--.*: a4cfe000 ld3h \{z0\.h-z2\.h\}, p0/z, \[x0, #-3, mul vl\]
--.*: a4cfe000 ld3h \{z0\.h-z2\.h\}, p0/z, \[x0, #-3, mul vl\]
--.*: a4cfe000 ld3h \{z0\.h-z2\.h\}, p0/z, \[x0, #-3, mul vl\]
--.*: a540c000 ld3w \{z0\.s-z2\.s\}, p0/z, \[x0, x0, lsl #2\]
--.*: a540c000 ld3w \{z0\.s-z2\.s\}, p0/z, \[x0, x0, lsl #2\]
--.*: a540c000 ld3w \{z0\.s-z2\.s\}, p0/z, \[x0, x0, lsl #2\]
--.*: a540c001 ld3w \{z1\.s-z3\.s\}, p0/z, \[x0, x0, lsl #2\]
--.*: a540c001 ld3w \{z1\.s-z3\.s\}, p0/z, \[x0, x0, lsl #2\]
--.*: a540c001 ld3w \{z1\.s-z3\.s\}, p0/z, \[x0, x0, lsl #2\]
--.*: a540c01f ld3w \{z31\.s, z0\.s, z1\.s\}, p0/z, \[x0, x0, lsl #2\]
--.*: a540c01f ld3w \{z31\.s, z0\.s, z1\.s\}, p0/z, \[x0, x0, lsl #2\]
--.*: a540c800 ld3w \{z0\.s-z2\.s\}, p2/z, \[x0, x0, lsl #2\]
--.*: a540c800 ld3w \{z0\.s-z2\.s\}, p2/z, \[x0, x0, lsl #2\]
--.*: a540c800 ld3w \{z0\.s-z2\.s\}, p2/z, \[x0, x0, lsl #2\]
--.*: a540dc00 ld3w \{z0\.s-z2\.s\}, p7/z, \[x0, x0, lsl #2\]
--.*: a540dc00 ld3w \{z0\.s-z2\.s\}, p7/z, \[x0, x0, lsl #2\]
--.*: a540dc00 ld3w \{z0\.s-z2\.s\}, p7/z, \[x0, x0, lsl #2\]
--.*: a540c060 ld3w \{z0\.s-z2\.s\}, p0/z, \[x3, x0, lsl #2\]
--.*: a540c060 ld3w \{z0\.s-z2\.s\}, p0/z, \[x3, x0, lsl #2\]
--.*: a540c060 ld3w \{z0\.s-z2\.s\}, p0/z, \[x3, x0, lsl #2\]
--.*: a540c3e0 ld3w \{z0\.s-z2\.s\}, p0/z, \[sp, x0, lsl #2\]
--.*: a540c3e0 ld3w \{z0\.s-z2\.s\}, p0/z, \[sp, x0, lsl #2\]
--.*: a540c3e0 ld3w \{z0\.s-z2\.s\}, p0/z, \[sp, x0, lsl #2\]
--.*: a544c000 ld3w \{z0\.s-z2\.s\}, p0/z, \[x0, x4, lsl #2\]
--.*: a544c000 ld3w \{z0\.s-z2\.s\}, p0/z, \[x0, x4, lsl #2\]
--.*: a544c000 ld3w \{z0\.s-z2\.s\}, p0/z, \[x0, x4, lsl #2\]
--.*: a55ec000 ld3w \{z0\.s-z2\.s\}, p0/z, \[x0, x30, lsl #2\]
--.*: a55ec000 ld3w \{z0\.s-z2\.s\}, p0/z, \[x0, x30, lsl #2\]
--.*: a55ec000 ld3w \{z0\.s-z2\.s\}, p0/z, \[x0, x30, lsl #2\]
--.*: a540e000 ld3w \{z0\.s-z2\.s\}, p0/z, \[x0\]
--.*: a540e000 ld3w \{z0\.s-z2\.s\}, p0/z, \[x0\]
--.*: a540e000 ld3w \{z0\.s-z2\.s\}, p0/z, \[x0\]
--.*: a540e000 ld3w \{z0\.s-z2\.s\}, p0/z, \[x0\]
--.*: a540e000 ld3w \{z0\.s-z2\.s\}, p0/z, \[x0\]
--.*: a540e000 ld3w \{z0\.s-z2\.s\}, p0/z, \[x0\]
--.*: a540e000 ld3w \{z0\.s-z2\.s\}, p0/z, \[x0\]
--.*: a540e001 ld3w \{z1\.s-z3\.s\}, p0/z, \[x0\]
--.*: a540e001 ld3w \{z1\.s-z3\.s\}, p0/z, \[x0\]
--.*: a540e001 ld3w \{z1\.s-z3\.s\}, p0/z, \[x0\]
--.*: a540e001 ld3w \{z1\.s-z3\.s\}, p0/z, \[x0\]
--.*: a540e001 ld3w \{z1\.s-z3\.s\}, p0/z, \[x0\]
--.*: a540e001 ld3w \{z1\.s-z3\.s\}, p0/z, \[x0\]
--.*: a540e001 ld3w \{z1\.s-z3\.s\}, p0/z, \[x0\]
--.*: a540e01f ld3w \{z31\.s, z0\.s, z1\.s\}, p0/z, \[x0\]
--.*: a540e01f ld3w \{z31\.s, z0\.s, z1\.s\}, p0/z, \[x0\]
--.*: a540e01f ld3w \{z31\.s, z0\.s, z1\.s\}, p0/z, \[x0\]
--.*: a540e01f ld3w \{z31\.s, z0\.s, z1\.s\}, p0/z, \[x0\]
--.*: a540e800 ld3w \{z0\.s-z2\.s\}, p2/z, \[x0\]
--.*: a540e800 ld3w \{z0\.s-z2\.s\}, p2/z, \[x0\]
--.*: a540e800 ld3w \{z0\.s-z2\.s\}, p2/z, \[x0\]
--.*: a540e800 ld3w \{z0\.s-z2\.s\}, p2/z, \[x0\]
--.*: a540e800 ld3w \{z0\.s-z2\.s\}, p2/z, \[x0\]
--.*: a540e800 ld3w \{z0\.s-z2\.s\}, p2/z, \[x0\]
--.*: a540e800 ld3w \{z0\.s-z2\.s\}, p2/z, \[x0\]
--.*: a540fc00 ld3w \{z0\.s-z2\.s\}, p7/z, \[x0\]
--.*: a540fc00 ld3w \{z0\.s-z2\.s\}, p7/z, \[x0\]
--.*: a540fc00 ld3w \{z0\.s-z2\.s\}, p7/z, \[x0\]
--.*: a540fc00 ld3w \{z0\.s-z2\.s\}, p7/z, \[x0\]
--.*: a540fc00 ld3w \{z0\.s-z2\.s\}, p7/z, \[x0\]
--.*: a540fc00 ld3w \{z0\.s-z2\.s\}, p7/z, \[x0\]
--.*: a540fc00 ld3w \{z0\.s-z2\.s\}, p7/z, \[x0\]
--.*: a540e060 ld3w \{z0\.s-z2\.s\}, p0/z, \[x3\]
--.*: a540e060 ld3w \{z0\.s-z2\.s\}, p0/z, \[x3\]
--.*: a540e060 ld3w \{z0\.s-z2\.s\}, p0/z, \[x3\]
--.*: a540e060 ld3w \{z0\.s-z2\.s\}, p0/z, \[x3\]
--.*: a540e060 ld3w \{z0\.s-z2\.s\}, p0/z, \[x3\]
--.*: a540e060 ld3w \{z0\.s-z2\.s\}, p0/z, \[x3\]
--.*: a540e060 ld3w \{z0\.s-z2\.s\}, p0/z, \[x3\]
--.*: a540e3e0 ld3w \{z0\.s-z2\.s\}, p0/z, \[sp\]
--.*: a540e3e0 ld3w \{z0\.s-z2\.s\}, p0/z, \[sp\]
--.*: a540e3e0 ld3w \{z0\.s-z2\.s\}, p0/z, \[sp\]
--.*: a540e3e0 ld3w \{z0\.s-z2\.s\}, p0/z, \[sp\]
--.*: a540e3e0 ld3w \{z0\.s-z2\.s\}, p0/z, \[sp\]
--.*: a540e3e0 ld3w \{z0\.s-z2\.s\}, p0/z, \[sp\]
--.*: a540e3e0 ld3w \{z0\.s-z2\.s\}, p0/z, \[sp\]
--.*: a547e000 ld3w \{z0\.s-z2\.s\}, p0/z, \[x0, #21, mul vl\]
--.*: a547e000 ld3w \{z0\.s-z2\.s\}, p0/z, \[x0, #21, mul vl\]
--.*: a547e000 ld3w \{z0\.s-z2\.s\}, p0/z, \[x0, #21, mul vl\]
--.*: a548e000 ld3w \{z0\.s-z2\.s\}, p0/z, \[x0, #-24, mul vl\]
--.*: a548e000 ld3w \{z0\.s-z2\.s\}, p0/z, \[x0, #-24, mul vl\]
--.*: a548e000 ld3w \{z0\.s-z2\.s\}, p0/z, \[x0, #-24, mul vl\]
--.*: a549e000 ld3w \{z0\.s-z2\.s\}, p0/z, \[x0, #-21, mul vl\]
--.*: a549e000 ld3w \{z0\.s-z2\.s\}, p0/z, \[x0, #-21, mul vl\]
--.*: a549e000 ld3w \{z0\.s-z2\.s\}, p0/z, \[x0, #-21, mul vl\]
--.*: a54fe000 ld3w \{z0\.s-z2\.s\}, p0/z, \[x0, #-3, mul vl\]
--.*: a54fe000 ld3w \{z0\.s-z2\.s\}, p0/z, \[x0, #-3, mul vl\]
--.*: a54fe000 ld3w \{z0\.s-z2\.s\}, p0/z, \[x0, #-3, mul vl\]
--.*: a460c000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0, x0\]
--.*: a460c000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0, x0\]
--.*: a460c000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0, x0\]
--.*: a460c000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0, x0\]
--.*: a460c000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0, x0\]
--.*: a460c001 ld4b \{z1\.b-z4\.b\}, p0/z, \[x0, x0\]
--.*: a460c001 ld4b \{z1\.b-z4\.b\}, p0/z, \[x0, x0\]
--.*: a460c001 ld4b \{z1\.b-z4\.b\}, p0/z, \[x0, x0\]
--.*: a460c001 ld4b \{z1\.b-z4\.b\}, p0/z, \[x0, x0\]
--.*: a460c001 ld4b \{z1\.b-z4\.b\}, p0/z, \[x0, x0\]
--.*: a460c01f ld4b \{z31\.b, z0\.b, z1\.b, z2\.b\}, p0/z, \[x0, x0\]
--.*: a460c01f ld4b \{z31\.b, z0\.b, z1\.b, z2\.b\}, p0/z, \[x0, x0\]
--.*: a460c01f ld4b \{z31\.b, z0\.b, z1\.b, z2\.b\}, p0/z, \[x0, x0\]
--.*: a460c800 ld4b \{z0\.b-z3\.b\}, p2/z, \[x0, x0\]
--.*: a460c800 ld4b \{z0\.b-z3\.b\}, p2/z, \[x0, x0\]
--.*: a460c800 ld4b \{z0\.b-z3\.b\}, p2/z, \[x0, x0\]
--.*: a460c800 ld4b \{z0\.b-z3\.b\}, p2/z, \[x0, x0\]
--.*: a460c800 ld4b \{z0\.b-z3\.b\}, p2/z, \[x0, x0\]
--.*: a460dc00 ld4b \{z0\.b-z3\.b\}, p7/z, \[x0, x0\]
--.*: a460dc00 ld4b \{z0\.b-z3\.b\}, p7/z, \[x0, x0\]
--.*: a460dc00 ld4b \{z0\.b-z3\.b\}, p7/z, \[x0, x0\]
--.*: a460dc00 ld4b \{z0\.b-z3\.b\}, p7/z, \[x0, x0\]
--.*: a460dc00 ld4b \{z0\.b-z3\.b\}, p7/z, \[x0, x0\]
--.*: a460c060 ld4b \{z0\.b-z3\.b\}, p0/z, \[x3, x0\]
--.*: a460c060 ld4b \{z0\.b-z3\.b\}, p0/z, \[x3, x0\]
--.*: a460c060 ld4b \{z0\.b-z3\.b\}, p0/z, \[x3, x0\]
--.*: a460c060 ld4b \{z0\.b-z3\.b\}, p0/z, \[x3, x0\]
--.*: a460c060 ld4b \{z0\.b-z3\.b\}, p0/z, \[x3, x0\]
--.*: a460c3e0 ld4b \{z0\.b-z3\.b\}, p0/z, \[sp, x0\]
--.*: a460c3e0 ld4b \{z0\.b-z3\.b\}, p0/z, \[sp, x0\]
--.*: a460c3e0 ld4b \{z0\.b-z3\.b\}, p0/z, \[sp, x0\]
--.*: a460c3e0 ld4b \{z0\.b-z3\.b\}, p0/z, \[sp, x0\]
--.*: a460c3e0 ld4b \{z0\.b-z3\.b\}, p0/z, \[sp, x0\]
--.*: a464c000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0, x4\]
--.*: a464c000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0, x4\]
--.*: a464c000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0, x4\]
--.*: a464c000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0, x4\]
--.*: a464c000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0, x4\]
--.*: a47ec000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0, x30\]
--.*: a47ec000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0, x30\]
--.*: a47ec000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0, x30\]
--.*: a47ec000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0, x30\]
--.*: a47ec000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0, x30\]
--.*: a460e000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0\]
--.*: a460e000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0\]
--.*: a460e000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0\]
--.*: a460e000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0\]
--.*: a460e000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0\]
--.*: a460e000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0\]
--.*: a460e000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0\]
--.*: a460e001 ld4b \{z1\.b-z4\.b\}, p0/z, \[x0\]
--.*: a460e001 ld4b \{z1\.b-z4\.b\}, p0/z, \[x0\]
--.*: a460e001 ld4b \{z1\.b-z4\.b\}, p0/z, \[x0\]
--.*: a460e001 ld4b \{z1\.b-z4\.b\}, p0/z, \[x0\]
--.*: a460e001 ld4b \{z1\.b-z4\.b\}, p0/z, \[x0\]
--.*: a460e001 ld4b \{z1\.b-z4\.b\}, p0/z, \[x0\]
--.*: a460e001 ld4b \{z1\.b-z4\.b\}, p0/z, \[x0\]
--.*: a460e01f ld4b \{z31\.b, z0\.b, z1\.b, z2\.b\}, p0/z, \[x0\]
--.*: a460e01f ld4b \{z31\.b, z0\.b, z1\.b, z2\.b\}, p0/z, \[x0\]
--.*: a460e01f ld4b \{z31\.b, z0\.b, z1\.b, z2\.b\}, p0/z, \[x0\]
--.*: a460e01f ld4b \{z31\.b, z0\.b, z1\.b, z2\.b\}, p0/z, \[x0\]
--.*: a460e800 ld4b \{z0\.b-z3\.b\}, p2/z, \[x0\]
--.*: a460e800 ld4b \{z0\.b-z3\.b\}, p2/z, \[x0\]
--.*: a460e800 ld4b \{z0\.b-z3\.b\}, p2/z, \[x0\]
--.*: a460e800 ld4b \{z0\.b-z3\.b\}, p2/z, \[x0\]
--.*: a460e800 ld4b \{z0\.b-z3\.b\}, p2/z, \[x0\]
--.*: a460e800 ld4b \{z0\.b-z3\.b\}, p2/z, \[x0\]
--.*: a460e800 ld4b \{z0\.b-z3\.b\}, p2/z, \[x0\]
--.*: a460fc00 ld4b \{z0\.b-z3\.b\}, p7/z, \[x0\]
--.*: a460fc00 ld4b \{z0\.b-z3\.b\}, p7/z, \[x0\]
--.*: a460fc00 ld4b \{z0\.b-z3\.b\}, p7/z, \[x0\]
--.*: a460fc00 ld4b \{z0\.b-z3\.b\}, p7/z, \[x0\]
--.*: a460fc00 ld4b \{z0\.b-z3\.b\}, p7/z, \[x0\]
--.*: a460fc00 ld4b \{z0\.b-z3\.b\}, p7/z, \[x0\]
--.*: a460fc00 ld4b \{z0\.b-z3\.b\}, p7/z, \[x0\]
--.*: a460e060 ld4b \{z0\.b-z3\.b\}, p0/z, \[x3\]
--.*: a460e060 ld4b \{z0\.b-z3\.b\}, p0/z, \[x3\]
--.*: a460e060 ld4b \{z0\.b-z3\.b\}, p0/z, \[x3\]
--.*: a460e060 ld4b \{z0\.b-z3\.b\}, p0/z, \[x3\]
--.*: a460e060 ld4b \{z0\.b-z3\.b\}, p0/z, \[x3\]
--.*: a460e060 ld4b \{z0\.b-z3\.b\}, p0/z, \[x3\]
--.*: a460e060 ld4b \{z0\.b-z3\.b\}, p0/z, \[x3\]
--.*: a460e3e0 ld4b \{z0\.b-z3\.b\}, p0/z, \[sp\]
--.*: a460e3e0 ld4b \{z0\.b-z3\.b\}, p0/z, \[sp\]
--.*: a460e3e0 ld4b \{z0\.b-z3\.b\}, p0/z, \[sp\]
--.*: a460e3e0 ld4b \{z0\.b-z3\.b\}, p0/z, \[sp\]
--.*: a460e3e0 ld4b \{z0\.b-z3\.b\}, p0/z, \[sp\]
--.*: a460e3e0 ld4b \{z0\.b-z3\.b\}, p0/z, \[sp\]
--.*: a460e3e0 ld4b \{z0\.b-z3\.b\}, p0/z, \[sp\]
--.*: a467e000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0, #28, mul vl\]
--.*: a467e000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0, #28, mul vl\]
--.*: a467e000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0, #28, mul vl\]
--.*: a468e000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0, #-32, mul vl\]
--.*: a468e000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0, #-32, mul vl\]
--.*: a468e000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0, #-32, mul vl\]
--.*: a469e000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0, #-28, mul vl\]
--.*: a469e000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0, #-28, mul vl\]
--.*: a469e000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0, #-28, mul vl\]
--.*: a46fe000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0, #-4, mul vl\]
--.*: a46fe000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0, #-4, mul vl\]
--.*: a46fe000 ld4b \{z0\.b-z3\.b\}, p0/z, \[x0, #-4, mul vl\]
--.*: a5e0c000 ld4d \{z0\.d-z3\.d\}, p0/z, \[x0, x0, lsl #3\]
--.*: a5e0c000 ld4d \{z0\.d-z3\.d\}, p0/z, \[x0, x0, lsl #3\]
--.*: a5e0c000 ld4d \{z0\.d-z3\.d\}, p0/z, \[x0, x0, lsl #3\]
--.*: a5e0c001 ld4d \{z1\.d-z4\.d\}, p0/z, \[x0, x0, lsl #3\]
--.*: a5e0c001 ld4d \{z1\.d-z4\.d\}, p0/z, \[x0, x0, lsl #3\]
--.*: a5e0c001 ld4d \{z1\.d-z4\.d\}, p0/z, \[x0, x0, lsl #3\]
--.*: a5e0c01f ld4d \{z31\.d, z0\.d, z1\.d, z2\.d\}, p0/z, \[x0, x0, lsl #3\]
--.*: a5e0c01f ld4d \{z31\.d, z0\.d, z1\.d, z2\.d\}, p0/z, \[x0, x0, lsl #3\]
--.*: a5e0c800 ld4d \{z0\.d-z3\.d\}, p2/z, \[x0, x0, lsl #3\]
--.*: a5e0c800 ld4d \{z0\.d-z3\.d\}, p2/z, \[x0, x0, lsl #3\]
--.*: a5e0c800 ld4d \{z0\.d-z3\.d\}, p2/z, \[x0, x0, lsl #3\]
--.*: a5e0dc00 ld4d \{z0\.d-z3\.d\}, p7/z, \[x0, x0, lsl #3\]
--.*: a5e0dc00 ld4d \{z0\.d-z3\.d\}, p7/z, \[x0, x0, lsl #3\]
--.*: a5e0dc00 ld4d \{z0\.d-z3\.d\}, p7/z, \[x0, x0, lsl #3\]
--.*: a5e0c060 ld4d \{z0\.d-z3\.d\}, p0/z, \[x3, x0, lsl #3\]
--.*: a5e0c060 ld4d \{z0\.d-z3\.d\}, p0/z, \[x3, x0, lsl #3\]
--.*: a5e0c060 ld4d \{z0\.d-z3\.d\}, p0/z, \[x3, x0, lsl #3\]
--.*: a5e0c3e0 ld4d \{z0\.d-z3\.d\}, p0/z, \[sp, x0, lsl #3\]
--.*: a5e0c3e0 ld4d \{z0\.d-z3\.d\}, p0/z, \[sp, x0, lsl #3\]
--.*: a5e0c3e0 ld4d \{z0\.d-z3\.d\}, p0/z, \[sp, x0, lsl #3\]
--.*: a5e4c000 ld4d \{z0\.d-z3\.d\}, p0/z, \[x0, x4, lsl #3\]
--.*: a5e4c000 ld4d \{z0\.d-z3\.d\}, p0/z, \[x0, x4, lsl #3\]
--.*: a5e4c000 ld4d \{z0\.d-z3\.d\}, p0/z, \[x0, x4, lsl #3\]
--.*: a5fec000 ld4d \{z0\.d-z3\.d\}, p0/z, \[x0, x30, lsl #3\]
--.*: a5fec000 ld4d \{z0\.d-z3\.d\}, p0/z, \[x0, x30, lsl #3\]
--.*: a5fec000 ld4d \{z0\.d-z3\.d\}, p0/z, \[x0, x30, lsl #3\]
--.*: a5e0e000 ld4d \{z0\.d-z3\.d\}, p0/z, \[x0\]
--.*: a5e0e000 ld4d \{z0\.d-z3\.d\}, p0/z, \[x0\]
--.*: a5e0e000 ld4d \{z0\.d-z3\.d\}, p0/z, \[x0\]
--.*: a5e0e000 ld4d \{z0\.d-z3\.d\}, p0/z, \[x0\]
--.*: a5e0e000 ld4d \{z0\.d-z3\.d\}, p0/z, \[x0\]
--.*: a5e0e000 ld4d \{z0\.d-z3\.d\}, p0/z, \[x0\]
--.*: a5e0e000 ld4d \{z0\.d-z3\.d\}, p0/z, \[x0\]
--.*: a5e0e001 ld4d \{z1\.d-z4\.d\}, p0/z, \[x0\]
--.*: a5e0e001 ld4d \{z1\.d-z4\.d\}, p0/z, \[x0\]
--.*: a5e0e001 ld4d \{z1\.d-z4\.d\}, p0/z, \[x0\]
--.*: a5e0e001 ld4d \{z1\.d-z4\.d\}, p0/z, \[x0\]
--.*: a5e0e001 ld4d \{z1\.d-z4\.d\}, p0/z, \[x0\]
--.*: a5e0e001 ld4d \{z1\.d-z4\.d\}, p0/z, \[x0\]
--.*: a5e0e001 ld4d \{z1\.d-z4\.d\}, p0/z, \[x0\]
--.*: a5e0e01f ld4d \{z31\.d, z0\.d, z1\.d, z2\.d\}, p0/z, \[x0\]
--.*: a5e0e01f ld4d \{z31\.d, z0\.d, z1\.d, z2\.d\}, p0/z, \[x0\]
--.*: a5e0e01f ld4d \{z31\.d, z0\.d, z1\.d, z2\.d\}, p0/z, \[x0\]
--.*: a5e0e01f ld4d \{z31\.d, z0\.d, z1\.d, z2\.d\}, p0/z, \[x0\]
--.*: a5e0e800 ld4d \{z0\.d-z3\.d\}, p2/z, \[x0\]
--.*: a5e0e800 ld4d \{z0\.d-z3\.d\}, p2/z, \[x0\]
--.*: a5e0e800 ld4d \{z0\.d-z3\.d\}, p2/z, \[x0\]
--.*: a5e0e800 ld4d \{z0\.d-z3\.d\}, p2/z, \[x0\]
--.*: a5e0e800 ld4d \{z0\.d-z3\.d\}, p2/z, \[x0\]
--.*: a5e0e800 ld4d \{z0\.d-z3\.d\}, p2/z, \[x0\]
--.*: a5e0e800 ld4d \{z0\.d-z3\.d\}, p2/z, \[x0\]
--.*: a5e0fc00 ld4d \{z0\.d-z3\.d\}, p7/z, \[x0\]
--.*: a5e0fc00 ld4d \{z0\.d-z3\.d\}, p7/z, \[x0\]
--.*: a5e0fc00 ld4d \{z0\.d-z3\.d\}, p7/z, \[x0\]
--.*: a5e0fc00 ld4d \{z0\.d-z3\.d\}, p7/z, \[x0\]
--.*: a5e0fc00 ld4d \{z0\.d-z3\.d\}, p7/z, \[x0\]
--.*: a5e0fc00 ld4d \{z0\.d-z3\.d\}, p7/z, \[x0\]
--.*: a5e0fc00 ld4d \{z0\.d-z3\.d\}, p7/z, \[x0\]
--.*: a5e0e060 ld4d \{z0\.d-z3\.d\}, p0/z, \[x3\]
--.*: a5e0e060 ld4d \{z0\.d-z3\.d\}, p0/z, \[x3\]
--.*: a5e0e060 ld4d \{z0\.d-z3\.d\}, p0/z, \[x3\]
--.*: a5e0e060 ld4d \{z0\.d-z3\.d\}, p0/z, \[x3\]
--.*: a5e0e060 ld4d \{z0\.d-z3\.d\}, p0/z, \[x3\]
--.*: a5e0e060 ld4d \{z0\.d-z3\.d\}, p0/z, \[x3\]
--.*: a5e0e060 ld4d \{z0\.d-z3\.d\}, p0/z, \[x3\]
--.*: a5e0e3e0 ld4d \{z0\.d-z3\.d\}, p0/z, \[sp\]
--.*: a5e0e3e0 ld4d \{z0\.d-z3\.d\}, p0/z, \[sp\]
--.*: a5e0e3e0 ld4d \{z0\.d-z3\.d\}, p0/z, \[sp\]
--.*: a5e0e3e0 ld4d \{z0\.d-z3\.d\}, p0/z, \[sp\]
--.*: a5e0e3e0 ld4d \{z0\.d-z3\.d\}, p0/z, \[sp\]
--.*: a5e0e3e0 ld4d \{z0\.d-z3\.d\}, p0/z, \[sp\]
--.*: a5e0e3e0 ld4d \{z0\.d-z3\.d\}, p0/z, \[sp\]
--.*: a5e7e000 ld4d \{z0\.d-z3\.d\}, p0/z, \[x0, #28, mul vl\]
--.*: a5e7e000 ld4d \{z0\.d-z3\.d\}, p0/z, \[x0, #28, mul vl\]
--.*: a5e7e000 ld4d \{z0\.d-z3\.d\}, p0/z, \[x0, #28, mul vl\]
--.*: a5e8e000 ld4d \{z0\.d-z3\.d\}, p0/z, \[x0, #-32, mul vl\]
--.*: a5e8e000 ld4d \{z0\.d-z3\.d\}, p0/z, \[x0, #-32, mul vl\]
--.*: a5e8e000 ld4d \{z0\.d-z3\.d\}, p0/z, \[x0, #-32, mul vl\]
--.*: a5e9e000 ld4d \{z0\.d-z3\.d\}, p0/z, \[x0, #-28, mul vl\]
--.*: a5e9e000 ld4d \{z0\.d-z3\.d\}, p0/z, \[x0, #-28, mul vl\]
--.*: a5e9e000 ld4d \{z0\.d-z3\.d\}, p0/z, \[x0, #-28, mul vl\]
--.*: a5efe000 ld4d \{z0\.d-z3\.d\}, p0/z, \[x0, #-4, mul vl\]
--.*: a5efe000 ld4d \{z0\.d-z3\.d\}, p0/z, \[x0, #-4, mul vl\]
--.*: a5efe000 ld4d \{z0\.d-z3\.d\}, p0/z, \[x0, #-4, mul vl\]
--.*: a4e0c000 ld4h \{z0\.h-z3\.h\}, p0/z, \[x0, x0, lsl #1\]
--.*: a4e0c000 ld4h \{z0\.h-z3\.h\}, p0/z, \[x0, x0, lsl #1\]
--.*: a4e0c000 ld4h \{z0\.h-z3\.h\}, p0/z, \[x0, x0, lsl #1\]
--.*: a4e0c001 ld4h \{z1\.h-z4\.h\}, p0/z, \[x0, x0, lsl #1\]
--.*: a4e0c001 ld4h \{z1\.h-z4\.h\}, p0/z, \[x0, x0, lsl #1\]
--.*: a4e0c001 ld4h \{z1\.h-z4\.h\}, p0/z, \[x0, x0, lsl #1\]
--.*: a4e0c01f ld4h \{z31\.h, z0\.h, z1\.h, z2\.h\}, p0/z, \[x0, x0, lsl #1\]
--.*: a4e0c01f ld4h \{z31\.h, z0\.h, z1\.h, z2\.h\}, p0/z, \[x0, x0, lsl #1\]
--.*: a4e0c800 ld4h \{z0\.h-z3\.h\}, p2/z, \[x0, x0, lsl #1\]
--.*: a4e0c800 ld4h \{z0\.h-z3\.h\}, p2/z, \[x0, x0, lsl #1\]
--.*: a4e0c800 ld4h \{z0\.h-z3\.h\}, p2/z, \[x0, x0, lsl #1\]
--.*: a4e0dc00 ld4h \{z0\.h-z3\.h\}, p7/z, \[x0, x0, lsl #1\]
--.*: a4e0dc00 ld4h \{z0\.h-z3\.h\}, p7/z, \[x0, x0, lsl #1\]
--.*: a4e0dc00 ld4h \{z0\.h-z3\.h\}, p7/z, \[x0, x0, lsl #1\]
--.*: a4e0c060 ld4h \{z0\.h-z3\.h\}, p0/z, \[x3, x0, lsl #1\]
--.*: a4e0c060 ld4h \{z0\.h-z3\.h\}, p0/z, \[x3, x0, lsl #1\]
--.*: a4e0c060 ld4h \{z0\.h-z3\.h\}, p0/z, \[x3, x0, lsl #1\]
--.*: a4e0c3e0 ld4h \{z0\.h-z3\.h\}, p0/z, \[sp, x0, lsl #1\]
--.*: a4e0c3e0 ld4h \{z0\.h-z3\.h\}, p0/z, \[sp, x0, lsl #1\]
--.*: a4e0c3e0 ld4h \{z0\.h-z3\.h\}, p0/z, \[sp, x0, lsl #1\]
--.*: a4e4c000 ld4h \{z0\.h-z3\.h\}, p0/z, \[x0, x4, lsl #1\]
--.*: a4e4c000 ld4h \{z0\.h-z3\.h\}, p0/z, \[x0, x4, lsl #1\]
--.*: a4e4c000 ld4h \{z0\.h-z3\.h\}, p0/z, \[x0, x4, lsl #1\]
--.*: a4fec000 ld4h \{z0\.h-z3\.h\}, p0/z, \[x0, x30, lsl #1\]
--.*: a4fec000 ld4h \{z0\.h-z3\.h\}, p0/z, \[x0, x30, lsl #1\]
--.*: a4fec000 ld4h \{z0\.h-z3\.h\}, p0/z, \[x0, x30, lsl #1\]
--.*: a4e0e000 ld4h \{z0\.h-z3\.h\}, p0/z, \[x0\]
--.*: a4e0e000 ld4h \{z0\.h-z3\.h\}, p0/z, \[x0\]
--.*: a4e0e000 ld4h \{z0\.h-z3\.h\}, p0/z, \[x0\]
--.*: a4e0e000 ld4h \{z0\.h-z3\.h\}, p0/z, \[x0\]
--.*: a4e0e000 ld4h \{z0\.h-z3\.h\}, p0/z, \[x0\]
--.*: a4e0e000 ld4h \{z0\.h-z3\.h\}, p0/z, \[x0\]
--.*: a4e0e000 ld4h \{z0\.h-z3\.h\}, p0/z, \[x0\]
--.*: a4e0e001 ld4h \{z1\.h-z4\.h\}, p0/z, \[x0\]
--.*: a4e0e001 ld4h \{z1\.h-z4\.h\}, p0/z, \[x0\]
--.*: a4e0e001 ld4h \{z1\.h-z4\.h\}, p0/z, \[x0\]
--.*: a4e0e001 ld4h \{z1\.h-z4\.h\}, p0/z, \[x0\]
--.*: a4e0e001 ld4h \{z1\.h-z4\.h\}, p0/z, \[x0\]
--.*: a4e0e001 ld4h \{z1\.h-z4\.h\}, p0/z, \[x0\]
--.*: a4e0e001 ld4h \{z1\.h-z4\.h\}, p0/z, \[x0\]
--.*: a4e0e01f ld4h \{z31\.h, z0\.h, z1\.h, z2\.h\}, p0/z, \[x0\]
--.*: a4e0e01f ld4h \{z31\.h, z0\.h, z1\.h, z2\.h\}, p0/z, \[x0\]
--.*: a4e0e01f ld4h \{z31\.h, z0\.h, z1\.h, z2\.h\}, p0/z, \[x0\]
--.*: a4e0e01f ld4h \{z31\.h, z0\.h, z1\.h, z2\.h\}, p0/z, \[x0\]
--.*: a4e0e800 ld4h \{z0\.h-z3\.h\}, p2/z, \[x0\]
--.*: a4e0e800 ld4h \{z0\.h-z3\.h\}, p2/z, \[x0\]
--.*: a4e0e800 ld4h \{z0\.h-z3\.h\}, p2/z, \[x0\]
--.*: a4e0e800 ld4h \{z0\.h-z3\.h\}, p2/z, \[x0\]
--.*: a4e0e800 ld4h \{z0\.h-z3\.h\}, p2/z, \[x0\]
--.*: a4e0e800 ld4h \{z0\.h-z3\.h\}, p2/z, \[x0\]
--.*: a4e0e800 ld4h \{z0\.h-z3\.h\}, p2/z, \[x0\]
--.*: a4e0fc00 ld4h \{z0\.h-z3\.h\}, p7/z, \[x0\]
--.*: a4e0fc00 ld4h \{z0\.h-z3\.h\}, p7/z, \[x0\]
--.*: a4e0fc00 ld4h \{z0\.h-z3\.h\}, p7/z, \[x0\]
--.*: a4e0fc00 ld4h \{z0\.h-z3\.h\}, p7/z, \[x0\]
--.*: a4e0fc00 ld4h \{z0\.h-z3\.h\}, p7/z, \[x0\]
--.*: a4e0fc00 ld4h \{z0\.h-z3\.h\}, p7/z, \[x0\]
--.*: a4e0fc00 ld4h \{z0\.h-z3\.h\}, p7/z, \[x0\]
--.*: a4e0e060 ld4h \{z0\.h-z3\.h\}, p0/z, \[x3\]
--.*: a4e0e060 ld4h \{z0\.h-z3\.h\}, p0/z, \[x3\]
--.*: a4e0e060 ld4h \{z0\.h-z3\.h\}, p0/z, \[x3\]
--.*: a4e0e060 ld4h \{z0\.h-z3\.h\}, p0/z, \[x3\]
--.*: a4e0e060 ld4h \{z0\.h-z3\.h\}, p0/z, \[x3\]
--.*: a4e0e060 ld4h \{z0\.h-z3\.h\}, p0/z, \[x3\]
--.*: a4e0e060 ld4h \{z0\.h-z3\.h\}, p0/z, \[x3\]
--.*: a4e0e3e0 ld4h \{z0\.h-z3\.h\}, p0/z, \[sp\]
--.*: a4e0e3e0 ld4h \{z0\.h-z3\.h\}, p0/z, \[sp\]
--.*: a4e0e3e0 ld4h \{z0\.h-z3\.h\}, p0/z, \[sp\]
--.*: a4e0e3e0 ld4h \{z0\.h-z3\.h\}, p0/z, \[sp\]
--.*: a4e0e3e0 ld4h \{z0\.h-z3\.h\}, p0/z, \[sp\]
--.*: a4e0e3e0 ld4h \{z0\.h-z3\.h\}, p0/z, \[sp\]
--.*: a4e0e3e0 ld4h \{z0\.h-z3\.h\}, p0/z, \[sp\]
--.*: a4e7e000 ld4h \{z0\.h-z3\.h\}, p0/z, \[x0, #28, mul vl\]
--.*: a4e7e000 ld4h \{z0\.h-z3\.h\}, p0/z, \[x0, #28, mul vl\]
--.*: a4e7e000 ld4h \{z0\.h-z3\.h\}, p0/z, \[x0, #28, mul vl\]
--.*: a4e8e000 ld4h \{z0\.h-z3\.h\}, p0/z, \[x0, #-32, mul vl\]
--.*: a4e8e000 ld4h \{z0\.h-z3\.h\}, p0/z, \[x0, #-32, mul vl\]
--.*: a4e8e000 ld4h \{z0\.h-z3\.h\}, p0/z, \[x0, #-32, mul vl\]
--.*: a4e9e000 ld4h \{z0\.h-z3\.h\}, p0/z, \[x0, #-28, mul vl\]
--.*: a4e9e000 ld4h \{z0\.h-z3\.h\}, p0/z, \[x0, #-28, mul vl\]
--.*: a4e9e000 ld4h \{z0\.h-z3\.h\}, p0/z, \[x0, #-28, mul vl\]
--.*: a4efe000 ld4h \{z0\.h-z3\.h\}, p0/z, \[x0, #-4, mul vl\]
--.*: a4efe000 ld4h \{z0\.h-z3\.h\}, p0/z, \[x0, #-4, mul vl\]
--.*: a4efe000 ld4h \{z0\.h-z3\.h\}, p0/z, \[x0, #-4, mul vl\]
--.*: a560c000 ld4w \{z0\.s-z3\.s\}, p0/z, \[x0, x0, lsl #2\]
--.*: a560c000 ld4w \{z0\.s-z3\.s\}, p0/z, \[x0, x0, lsl #2\]
--.*: a560c000 ld4w \{z0\.s-z3\.s\}, p0/z, \[x0, x0, lsl #2\]
--.*: a560c001 ld4w \{z1\.s-z4\.s\}, p0/z, \[x0, x0, lsl #2\]
--.*: a560c001 ld4w \{z1\.s-z4\.s\}, p0/z, \[x0, x0, lsl #2\]
--.*: a560c001 ld4w \{z1\.s-z4\.s\}, p0/z, \[x0, x0, lsl #2\]
--.*: a560c01f ld4w \{z31\.s, z0\.s, z1\.s, z2\.s\}, p0/z, \[x0, x0, lsl #2\]
--.*: a560c01f ld4w \{z31\.s, z0\.s, z1\.s, z2\.s\}, p0/z, \[x0, x0, lsl #2\]
--.*: a560c800 ld4w \{z0\.s-z3\.s\}, p2/z, \[x0, x0, lsl #2\]
--.*: a560c800 ld4w \{z0\.s-z3\.s\}, p2/z, \[x0, x0, lsl #2\]
--.*: a560c800 ld4w \{z0\.s-z3\.s\}, p2/z, \[x0, x0, lsl #2\]
--.*: a560dc00 ld4w \{z0\.s-z3\.s\}, p7/z, \[x0, x0, lsl #2\]
--.*: a560dc00 ld4w \{z0\.s-z3\.s\}, p7/z, \[x0, x0, lsl #2\]
--.*: a560dc00 ld4w \{z0\.s-z3\.s\}, p7/z, \[x0, x0, lsl #2\]
--.*: a560c060 ld4w \{z0\.s-z3\.s\}, p0/z, \[x3, x0, lsl #2\]
--.*: a560c060 ld4w \{z0\.s-z3\.s\}, p0/z, \[x3, x0, lsl #2\]
--.*: a560c060 ld4w \{z0\.s-z3\.s\}, p0/z, \[x3, x0, lsl #2\]
--.*: a560c3e0 ld4w \{z0\.s-z3\.s\}, p0/z, \[sp, x0, lsl #2\]
--.*: a560c3e0 ld4w \{z0\.s-z3\.s\}, p0/z, \[sp, x0, lsl #2\]
--.*: a560c3e0 ld4w \{z0\.s-z3\.s\}, p0/z, \[sp, x0, lsl #2\]
--.*: a564c000 ld4w \{z0\.s-z3\.s\}, p0/z, \[x0, x4, lsl #2\]
--.*: a564c000 ld4w \{z0\.s-z3\.s\}, p0/z, \[x0, x4, lsl #2\]
--.*: a564c000 ld4w \{z0\.s-z3\.s\}, p0/z, \[x0, x4, lsl #2\]
--.*: a57ec000 ld4w \{z0\.s-z3\.s\}, p0/z, \[x0, x30, lsl #2\]
--.*: a57ec000 ld4w \{z0\.s-z3\.s\}, p0/z, \[x0, x30, lsl #2\]
--.*: a57ec000 ld4w \{z0\.s-z3\.s\}, p0/z, \[x0, x30, lsl #2\]
--.*: a560e000 ld4w \{z0\.s-z3\.s\}, p0/z, \[x0\]
--.*: a560e000 ld4w \{z0\.s-z3\.s\}, p0/z, \[x0\]
--.*: a560e000 ld4w \{z0\.s-z3\.s\}, p0/z, \[x0\]
--.*: a560e000 ld4w \{z0\.s-z3\.s\}, p0/z, \[x0\]
--.*: a560e000 ld4w \{z0\.s-z3\.s\}, p0/z, \[x0\]
--.*: a560e000 ld4w \{z0\.s-z3\.s\}, p0/z, \[x0\]
--.*: a560e000 ld4w \{z0\.s-z3\.s\}, p0/z, \[x0\]
--.*: a560e001 ld4w \{z1\.s-z4\.s\}, p0/z, \[x0\]
--.*: a560e001 ld4w \{z1\.s-z4\.s\}, p0/z, \[x0\]
--.*: a560e001 ld4w \{z1\.s-z4\.s\}, p0/z, \[x0\]
--.*: a560e001 ld4w \{z1\.s-z4\.s\}, p0/z, \[x0\]
--.*: a560e001 ld4w \{z1\.s-z4\.s\}, p0/z, \[x0\]
--.*: a560e001 ld4w \{z1\.s-z4\.s\}, p0/z, \[x0\]
--.*: a560e001 ld4w \{z1\.s-z4\.s\}, p0/z, \[x0\]
--.*: a560e01f ld4w \{z31\.s, z0\.s, z1\.s, z2\.s\}, p0/z, \[x0\]
--.*: a560e01f ld4w \{z31\.s, z0\.s, z1\.s, z2\.s\}, p0/z, \[x0\]
--.*: a560e01f ld4w \{z31\.s, z0\.s, z1\.s, z2\.s\}, p0/z, \[x0\]
--.*: a560e01f ld4w \{z31\.s, z0\.s, z1\.s, z2\.s\}, p0/z, \[x0\]
--.*: a560e800 ld4w \{z0\.s-z3\.s\}, p2/z, \[x0\]
--.*: a560e800 ld4w \{z0\.s-z3\.s\}, p2/z, \[x0\]
--.*: a560e800 ld4w \{z0\.s-z3\.s\}, p2/z, \[x0\]
--.*: a560e800 ld4w \{z0\.s-z3\.s\}, p2/z, \[x0\]
--.*: a560e800 ld4w \{z0\.s-z3\.s\}, p2/z, \[x0\]
--.*: a560e800 ld4w \{z0\.s-z3\.s\}, p2/z, \[x0\]
--.*: a560e800 ld4w \{z0\.s-z3\.s\}, p2/z, \[x0\]
--.*: a560fc00 ld4w \{z0\.s-z3\.s\}, p7/z, \[x0\]
--.*: a560fc00 ld4w \{z0\.s-z3\.s\}, p7/z, \[x0\]
--.*: a560fc00 ld4w \{z0\.s-z3\.s\}, p7/z, \[x0\]
--.*: a560fc00 ld4w \{z0\.s-z3\.s\}, p7/z, \[x0\]
--.*: a560fc00 ld4w \{z0\.s-z3\.s\}, p7/z, \[x0\]
--.*: a560fc00 ld4w \{z0\.s-z3\.s\}, p7/z, \[x0\]
--.*: a560fc00 ld4w \{z0\.s-z3\.s\}, p7/z, \[x0\]
--.*: a560e060 ld4w \{z0\.s-z3\.s\}, p0/z, \[x3\]
--.*: a560e060 ld4w \{z0\.s-z3\.s\}, p0/z, \[x3\]
--.*: a560e060 ld4w \{z0\.s-z3\.s\}, p0/z, \[x3\]
--.*: a560e060 ld4w \{z0\.s-z3\.s\}, p0/z, \[x3\]
--.*: a560e060 ld4w \{z0\.s-z3\.s\}, p0/z, \[x3\]
--.*: a560e060 ld4w \{z0\.s-z3\.s\}, p0/z, \[x3\]
--.*: a560e060 ld4w \{z0\.s-z3\.s\}, p0/z, \[x3\]
--.*: a560e3e0 ld4w \{z0\.s-z3\.s\}, p0/z, \[sp\]
--.*: a560e3e0 ld4w \{z0\.s-z3\.s\}, p0/z, \[sp\]
--.*: a560e3e0 ld4w \{z0\.s-z3\.s\}, p0/z, \[sp\]
--.*: a560e3e0 ld4w \{z0\.s-z3\.s\}, p0/z, \[sp\]
--.*: a560e3e0 ld4w \{z0\.s-z3\.s\}, p0/z, \[sp\]
--.*: a560e3e0 ld4w \{z0\.s-z3\.s\}, p0/z, \[sp\]
--.*: a560e3e0 ld4w \{z0\.s-z3\.s\}, p0/z, \[sp\]
--.*: a567e000 ld4w \{z0\.s-z3\.s\}, p0/z, \[x0, #28, mul vl\]
--.*: a567e000 ld4w \{z0\.s-z3\.s\}, p0/z, \[x0, #28, mul vl\]
--.*: a567e000 ld4w \{z0\.s-z3\.s\}, p0/z, \[x0, #28, mul vl\]
--.*: a568e000 ld4w \{z0\.s-z3\.s\}, p0/z, \[x0, #-32, mul vl\]
--.*: a568e000 ld4w \{z0\.s-z3\.s\}, p0/z, \[x0, #-32, mul vl\]
--.*: a568e000 ld4w \{z0\.s-z3\.s\}, p0/z, \[x0, #-32, mul vl\]
--.*: a569e000 ld4w \{z0\.s-z3\.s\}, p0/z, \[x0, #-28, mul vl\]
--.*: a569e000 ld4w \{z0\.s-z3\.s\}, p0/z, \[x0, #-28, mul vl\]
--.*: a569e000 ld4w \{z0\.s-z3\.s\}, p0/z, \[x0, #-28, mul vl\]
--.*: a56fe000 ld4w \{z0\.s-z3\.s\}, p0/z, \[x0, #-4, mul vl\]
--.*: a56fe000 ld4w \{z0\.s-z3\.s\}, p0/z, \[x0, #-4, mul vl\]
--.*: a56fe000 ld4w \{z0\.s-z3\.s\}, p0/z, \[x0, #-4, mul vl\]
--.*: 84006000 ldff1b \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 84006000 ldff1b \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 84006000 ldff1b \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 84006000 ldff1b \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 84006001 ldff1b \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 84006001 ldff1b \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 84006001 ldff1b \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 84006001 ldff1b \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 8400601f ldff1b \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 8400601f ldff1b \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 8400601f ldff1b \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 8400601f ldff1b \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 84006800 ldff1b \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\]
--.*: 84006800 ldff1b \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\]
--.*: 84006800 ldff1b \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\]
--.*: 84007c00 ldff1b \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\]
--.*: 84007c00 ldff1b \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\]
--.*: 84007c00 ldff1b \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\]
--.*: 84006060 ldff1b \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\]
--.*: 84006060 ldff1b \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\]
--.*: 84006060 ldff1b \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\]
--.*: 840063e0 ldff1b \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\]
--.*: 840063e0 ldff1b \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\]
--.*: 840063e0 ldff1b \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\]
--.*: 84046000 ldff1b \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\]
--.*: 84046000 ldff1b \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\]
--.*: 84046000 ldff1b \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\]
--.*: 841f6000 ldff1b \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\]
--.*: 841f6000 ldff1b \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\]
--.*: 841f6000 ldff1b \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\]
--.*: 84406000 ldff1b \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 84406000 ldff1b \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 84406000 ldff1b \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 84406000 ldff1b \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 84406001 ldff1b \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 84406001 ldff1b \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 84406001 ldff1b \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 84406001 ldff1b \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 8440601f ldff1b \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 8440601f ldff1b \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 8440601f ldff1b \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 8440601f ldff1b \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 84406800 ldff1b \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\]
--.*: 84406800 ldff1b \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\]
--.*: 84406800 ldff1b \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\]
--.*: 84407c00 ldff1b \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\]
--.*: 84407c00 ldff1b \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\]
--.*: 84407c00 ldff1b \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\]
--.*: 84406060 ldff1b \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\]
--.*: 84406060 ldff1b \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\]
--.*: 84406060 ldff1b \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\]
--.*: 844063e0 ldff1b \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\]
--.*: 844063e0 ldff1b \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\]
--.*: 844063e0 ldff1b \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\]
--.*: 84446000 ldff1b \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\]
--.*: 84446000 ldff1b \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\]
--.*: 84446000 ldff1b \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\]
--.*: 845f6000 ldff1b \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\]
--.*: 845f6000 ldff1b \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\]
--.*: 845f6000 ldff1b \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\]
--.*: a4006000 ldff1b \{z0\.b\}, p0/z, \[x0, x0\]
--.*: a4006000 ldff1b \{z0\.b\}, p0/z, \[x0, x0\]
--.*: a4006000 ldff1b \{z0\.b\}, p0/z, \[x0, x0\]
--.*: a4006000 ldff1b \{z0\.b\}, p0/z, \[x0, x0\]
--.*: a4006001 ldff1b \{z1\.b\}, p0/z, \[x0, x0\]
--.*: a4006001 ldff1b \{z1\.b\}, p0/z, \[x0, x0\]
--.*: a4006001 ldff1b \{z1\.b\}, p0/z, \[x0, x0\]
--.*: a4006001 ldff1b \{z1\.b\}, p0/z, \[x0, x0\]
--.*: a400601f ldff1b \{z31\.b\}, p0/z, \[x0, x0\]
--.*: a400601f ldff1b \{z31\.b\}, p0/z, \[x0, x0\]
--.*: a400601f ldff1b \{z31\.b\}, p0/z, \[x0, x0\]
--.*: a400601f ldff1b \{z31\.b\}, p0/z, \[x0, x0\]
--.*: a4006800 ldff1b \{z0\.b\}, p2/z, \[x0, x0\]
--.*: a4006800 ldff1b \{z0\.b\}, p2/z, \[x0, x0\]
--.*: a4006800 ldff1b \{z0\.b\}, p2/z, \[x0, x0\]
--.*: a4007c00 ldff1b \{z0\.b\}, p7/z, \[x0, x0\]
--.*: a4007c00 ldff1b \{z0\.b\}, p7/z, \[x0, x0\]
--.*: a4007c00 ldff1b \{z0\.b\}, p7/z, \[x0, x0\]
--.*: a4006060 ldff1b \{z0\.b\}, p0/z, \[x3, x0\]
--.*: a4006060 ldff1b \{z0\.b\}, p0/z, \[x3, x0\]
--.*: a4006060 ldff1b \{z0\.b\}, p0/z, \[x3, x0\]
--.*: a40063e0 ldff1b \{z0\.b\}, p0/z, \[sp, x0\]
--.*: a40063e0 ldff1b \{z0\.b\}, p0/z, \[sp, x0\]
--.*: a40063e0 ldff1b \{z0\.b\}, p0/z, \[sp, x0\]
--.*: a4046000 ldff1b \{z0\.b\}, p0/z, \[x0, x4\]
--.*: a4046000 ldff1b \{z0\.b\}, p0/z, \[x0, x4\]
--.*: a4046000 ldff1b \{z0\.b\}, p0/z, \[x0, x4\]
--.*: a41f6000 ldff1b \{z0\.b\}, p0/z, \[x0, xzr\]
--.*: a41f6000 ldff1b \{z0\.b\}, p0/z, \[x0, xzr\]
--.*: a41f6000 ldff1b \{z0\.b\}, p0/z, \[x0, xzr\]
--.*: a4206000 ldff1b \{z0\.h\}, p0/z, \[x0, x0\]
--.*: a4206000 ldff1b \{z0\.h\}, p0/z, \[x0, x0\]
--.*: a4206000 ldff1b \{z0\.h\}, p0/z, \[x0, x0\]
--.*: a4206000 ldff1b \{z0\.h\}, p0/z, \[x0, x0\]
--.*: a4206001 ldff1b \{z1\.h\}, p0/z, \[x0, x0\]
--.*: a4206001 ldff1b \{z1\.h\}, p0/z, \[x0, x0\]
--.*: a4206001 ldff1b \{z1\.h\}, p0/z, \[x0, x0\]
--.*: a4206001 ldff1b \{z1\.h\}, p0/z, \[x0, x0\]
--.*: a420601f ldff1b \{z31\.h\}, p0/z, \[x0, x0\]
--.*: a420601f ldff1b \{z31\.h\}, p0/z, \[x0, x0\]
--.*: a420601f ldff1b \{z31\.h\}, p0/z, \[x0, x0\]
--.*: a420601f ldff1b \{z31\.h\}, p0/z, \[x0, x0\]
--.*: a4206800 ldff1b \{z0\.h\}, p2/z, \[x0, x0\]
--.*: a4206800 ldff1b \{z0\.h\}, p2/z, \[x0, x0\]
--.*: a4206800 ldff1b \{z0\.h\}, p2/z, \[x0, x0\]
--.*: a4207c00 ldff1b \{z0\.h\}, p7/z, \[x0, x0\]
--.*: a4207c00 ldff1b \{z0\.h\}, p7/z, \[x0, x0\]
--.*: a4207c00 ldff1b \{z0\.h\}, p7/z, \[x0, x0\]
--.*: a4206060 ldff1b \{z0\.h\}, p0/z, \[x3, x0\]
--.*: a4206060 ldff1b \{z0\.h\}, p0/z, \[x3, x0\]
--.*: a4206060 ldff1b \{z0\.h\}, p0/z, \[x3, x0\]
--.*: a42063e0 ldff1b \{z0\.h\}, p0/z, \[sp, x0\]
--.*: a42063e0 ldff1b \{z0\.h\}, p0/z, \[sp, x0\]
--.*: a42063e0 ldff1b \{z0\.h\}, p0/z, \[sp, x0\]
--.*: a4246000 ldff1b \{z0\.h\}, p0/z, \[x0, x4\]
--.*: a4246000 ldff1b \{z0\.h\}, p0/z, \[x0, x4\]
--.*: a4246000 ldff1b \{z0\.h\}, p0/z, \[x0, x4\]
--.*: a43f6000 ldff1b \{z0\.h\}, p0/z, \[x0, xzr\]
--.*: a43f6000 ldff1b \{z0\.h\}, p0/z, \[x0, xzr\]
--.*: a43f6000 ldff1b \{z0\.h\}, p0/z, \[x0, xzr\]
--.*: a4406000 ldff1b \{z0\.s\}, p0/z, \[x0, x0\]
--.*: a4406000 ldff1b \{z0\.s\}, p0/z, \[x0, x0\]
--.*: a4406000 ldff1b \{z0\.s\}, p0/z, \[x0, x0\]
--.*: a4406000 ldff1b \{z0\.s\}, p0/z, \[x0, x0\]
--.*: a4406001 ldff1b \{z1\.s\}, p0/z, \[x0, x0\]
--.*: a4406001 ldff1b \{z1\.s\}, p0/z, \[x0, x0\]
--.*: a4406001 ldff1b \{z1\.s\}, p0/z, \[x0, x0\]
--.*: a4406001 ldff1b \{z1\.s\}, p0/z, \[x0, x0\]
--.*: a440601f ldff1b \{z31\.s\}, p0/z, \[x0, x0\]
--.*: a440601f ldff1b \{z31\.s\}, p0/z, \[x0, x0\]
--.*: a440601f ldff1b \{z31\.s\}, p0/z, \[x0, x0\]
--.*: a440601f ldff1b \{z31\.s\}, p0/z, \[x0, x0\]
--.*: a4406800 ldff1b \{z0\.s\}, p2/z, \[x0, x0\]
--.*: a4406800 ldff1b \{z0\.s\}, p2/z, \[x0, x0\]
--.*: a4406800 ldff1b \{z0\.s\}, p2/z, \[x0, x0\]
--.*: a4407c00 ldff1b \{z0\.s\}, p7/z, \[x0, x0\]
--.*: a4407c00 ldff1b \{z0\.s\}, p7/z, \[x0, x0\]
--.*: a4407c00 ldff1b \{z0\.s\}, p7/z, \[x0, x0\]
--.*: a4406060 ldff1b \{z0\.s\}, p0/z, \[x3, x0\]
--.*: a4406060 ldff1b \{z0\.s\}, p0/z, \[x3, x0\]
--.*: a4406060 ldff1b \{z0\.s\}, p0/z, \[x3, x0\]
--.*: a44063e0 ldff1b \{z0\.s\}, p0/z, \[sp, x0\]
--.*: a44063e0 ldff1b \{z0\.s\}, p0/z, \[sp, x0\]
--.*: a44063e0 ldff1b \{z0\.s\}, p0/z, \[sp, x0\]
--.*: a4446000 ldff1b \{z0\.s\}, p0/z, \[x0, x4\]
--.*: a4446000 ldff1b \{z0\.s\}, p0/z, \[x0, x4\]
--.*: a4446000 ldff1b \{z0\.s\}, p0/z, \[x0, x4\]
--.*: a45f6000 ldff1b \{z0\.s\}, p0/z, \[x0, xzr\]
--.*: a45f6000 ldff1b \{z0\.s\}, p0/z, \[x0, xzr\]
--.*: a45f6000 ldff1b \{z0\.s\}, p0/z, \[x0, xzr\]
--.*: a4606000 ldff1b \{z0\.d\}, p0/z, \[x0, x0\]
--.*: a4606000 ldff1b \{z0\.d\}, p0/z, \[x0, x0\]
--.*: a4606000 ldff1b \{z0\.d\}, p0/z, \[x0, x0\]
--.*: a4606000 ldff1b \{z0\.d\}, p0/z, \[x0, x0\]
--.*: a4606001 ldff1b \{z1\.d\}, p0/z, \[x0, x0\]
--.*: a4606001 ldff1b \{z1\.d\}, p0/z, \[x0, x0\]
--.*: a4606001 ldff1b \{z1\.d\}, p0/z, \[x0, x0\]
--.*: a4606001 ldff1b \{z1\.d\}, p0/z, \[x0, x0\]
--.*: a460601f ldff1b \{z31\.d\}, p0/z, \[x0, x0\]
--.*: a460601f ldff1b \{z31\.d\}, p0/z, \[x0, x0\]
--.*: a460601f ldff1b \{z31\.d\}, p0/z, \[x0, x0\]
--.*: a460601f ldff1b \{z31\.d\}, p0/z, \[x0, x0\]
--.*: a4606800 ldff1b \{z0\.d\}, p2/z, \[x0, x0\]
--.*: a4606800 ldff1b \{z0\.d\}, p2/z, \[x0, x0\]
--.*: a4606800 ldff1b \{z0\.d\}, p2/z, \[x0, x0\]
--.*: a4607c00 ldff1b \{z0\.d\}, p7/z, \[x0, x0\]
--.*: a4607c00 ldff1b \{z0\.d\}, p7/z, \[x0, x0\]
--.*: a4607c00 ldff1b \{z0\.d\}, p7/z, \[x0, x0\]
--.*: a4606060 ldff1b \{z0\.d\}, p0/z, \[x3, x0\]
--.*: a4606060 ldff1b \{z0\.d\}, p0/z, \[x3, x0\]
--.*: a4606060 ldff1b \{z0\.d\}, p0/z, \[x3, x0\]
--.*: a46063e0 ldff1b \{z0\.d\}, p0/z, \[sp, x0\]
--.*: a46063e0 ldff1b \{z0\.d\}, p0/z, \[sp, x0\]
--.*: a46063e0 ldff1b \{z0\.d\}, p0/z, \[sp, x0\]
--.*: a4646000 ldff1b \{z0\.d\}, p0/z, \[x0, x4\]
--.*: a4646000 ldff1b \{z0\.d\}, p0/z, \[x0, x4\]
--.*: a4646000 ldff1b \{z0\.d\}, p0/z, \[x0, x4\]
--.*: a47f6000 ldff1b \{z0\.d\}, p0/z, \[x0, xzr\]
--.*: a47f6000 ldff1b \{z0\.d\}, p0/z, \[x0, xzr\]
--.*: a47f6000 ldff1b \{z0\.d\}, p0/z, \[x0, xzr\]
--.*: c4006000 ldff1b \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c4006000 ldff1b \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c4006000 ldff1b \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c4006000 ldff1b \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c4006001 ldff1b \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c4006001 ldff1b \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c4006001 ldff1b \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c4006001 ldff1b \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c400601f ldff1b \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c400601f ldff1b \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c400601f ldff1b \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c400601f ldff1b \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c4006800 ldff1b \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\]
--.*: c4006800 ldff1b \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\]
--.*: c4006800 ldff1b \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\]
--.*: c4007c00 ldff1b \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\]
--.*: c4007c00 ldff1b \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\]
--.*: c4007c00 ldff1b \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\]
--.*: c4006060 ldff1b \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\]
--.*: c4006060 ldff1b \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\]
--.*: c4006060 ldff1b \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\]
--.*: c40063e0 ldff1b \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\]
--.*: c40063e0 ldff1b \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\]
--.*: c40063e0 ldff1b \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\]
--.*: c4046000 ldff1b \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\]
--.*: c4046000 ldff1b \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\]
--.*: c4046000 ldff1b \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\]
--.*: c41f6000 ldff1b \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\]
--.*: c41f6000 ldff1b \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\]
--.*: c41f6000 ldff1b \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\]
--.*: c4406000 ldff1b \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c4406000 ldff1b \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c4406000 ldff1b \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c4406000 ldff1b \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c4406001 ldff1b \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c4406001 ldff1b \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c4406001 ldff1b \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c4406001 ldff1b \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c440601f ldff1b \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c440601f ldff1b \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c440601f ldff1b \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c440601f ldff1b \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c4406800 ldff1b \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\]
--.*: c4406800 ldff1b \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\]
--.*: c4406800 ldff1b \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\]
--.*: c4407c00 ldff1b \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\]
--.*: c4407c00 ldff1b \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\]
--.*: c4407c00 ldff1b \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\]
--.*: c4406060 ldff1b \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\]
--.*: c4406060 ldff1b \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\]
--.*: c4406060 ldff1b \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\]
--.*: c44063e0 ldff1b \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\]
--.*: c44063e0 ldff1b \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\]
--.*: c44063e0 ldff1b \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\]
--.*: c4446000 ldff1b \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\]
--.*: c4446000 ldff1b \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\]
--.*: c4446000 ldff1b \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\]
--.*: c45f6000 ldff1b \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\]
--.*: c45f6000 ldff1b \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\]
--.*: c45f6000 ldff1b \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\]
--.*: c440e000 ldff1b \{z0\.d\}, p0/z, \[x0, z0\.d\]
--.*: c440e000 ldff1b \{z0\.d\}, p0/z, \[x0, z0\.d\]
--.*: c440e000 ldff1b \{z0\.d\}, p0/z, \[x0, z0\.d\]
--.*: c440e000 ldff1b \{z0\.d\}, p0/z, \[x0, z0\.d\]
--.*: c440e001 ldff1b \{z1\.d\}, p0/z, \[x0, z0\.d\]
--.*: c440e001 ldff1b \{z1\.d\}, p0/z, \[x0, z0\.d\]
--.*: c440e001 ldff1b \{z1\.d\}, p0/z, \[x0, z0\.d\]
--.*: c440e001 ldff1b \{z1\.d\}, p0/z, \[x0, z0\.d\]
--.*: c440e01f ldff1b \{z31\.d\}, p0/z, \[x0, z0\.d\]
--.*: c440e01f ldff1b \{z31\.d\}, p0/z, \[x0, z0\.d\]
--.*: c440e01f ldff1b \{z31\.d\}, p0/z, \[x0, z0\.d\]
--.*: c440e01f ldff1b \{z31\.d\}, p0/z, \[x0, z0\.d\]
--.*: c440e800 ldff1b \{z0\.d\}, p2/z, \[x0, z0\.d\]
--.*: c440e800 ldff1b \{z0\.d\}, p2/z, \[x0, z0\.d\]
--.*: c440e800 ldff1b \{z0\.d\}, p2/z, \[x0, z0\.d\]
--.*: c440fc00 ldff1b \{z0\.d\}, p7/z, \[x0, z0\.d\]
--.*: c440fc00 ldff1b \{z0\.d\}, p7/z, \[x0, z0\.d\]
--.*: c440fc00 ldff1b \{z0\.d\}, p7/z, \[x0, z0\.d\]
--.*: c440e060 ldff1b \{z0\.d\}, p0/z, \[x3, z0\.d\]
--.*: c440e060 ldff1b \{z0\.d\}, p0/z, \[x3, z0\.d\]
--.*: c440e060 ldff1b \{z0\.d\}, p0/z, \[x3, z0\.d\]
--.*: c440e3e0 ldff1b \{z0\.d\}, p0/z, \[sp, z0\.d\]
--.*: c440e3e0 ldff1b \{z0\.d\}, p0/z, \[sp, z0\.d\]
--.*: c440e3e0 ldff1b \{z0\.d\}, p0/z, \[sp, z0\.d\]
--.*: c444e000 ldff1b \{z0\.d\}, p0/z, \[x0, z4\.d\]
--.*: c444e000 ldff1b \{z0\.d\}, p0/z, \[x0, z4\.d\]
--.*: c444e000 ldff1b \{z0\.d\}, p0/z, \[x0, z4\.d\]
--.*: c45fe000 ldff1b \{z0\.d\}, p0/z, \[x0, z31\.d\]
--.*: c45fe000 ldff1b \{z0\.d\}, p0/z, \[x0, z31\.d\]
--.*: c45fe000 ldff1b \{z0\.d\}, p0/z, \[x0, z31\.d\]
--.*: 8420e000 ldff1b \{z0\.s\}, p0/z, \[z0\.s\]
--.*: 8420e000 ldff1b \{z0\.s\}, p0/z, \[z0\.s\]
--.*: 8420e000 ldff1b \{z0\.s\}, p0/z, \[z0\.s\]
--.*: 8420e000 ldff1b \{z0\.s\}, p0/z, \[z0\.s\]
--.*: 8420e001 ldff1b \{z1\.s\}, p0/z, \[z0\.s\]
--.*: 8420e001 ldff1b \{z1\.s\}, p0/z, \[z0\.s\]
--.*: 8420e001 ldff1b \{z1\.s\}, p0/z, \[z0\.s\]
--.*: 8420e001 ldff1b \{z1\.s\}, p0/z, \[z0\.s\]
--.*: 8420e01f ldff1b \{z31\.s\}, p0/z, \[z0\.s\]
--.*: 8420e01f ldff1b \{z31\.s\}, p0/z, \[z0\.s\]
--.*: 8420e01f ldff1b \{z31\.s\}, p0/z, \[z0\.s\]
--.*: 8420e01f ldff1b \{z31\.s\}, p0/z, \[z0\.s\]
--.*: 8420e800 ldff1b \{z0\.s\}, p2/z, \[z0\.s\]
--.*: 8420e800 ldff1b \{z0\.s\}, p2/z, \[z0\.s\]
--.*: 8420e800 ldff1b \{z0\.s\}, p2/z, \[z0\.s\]
--.*: 8420fc00 ldff1b \{z0\.s\}, p7/z, \[z0\.s\]
--.*: 8420fc00 ldff1b \{z0\.s\}, p7/z, \[z0\.s\]
--.*: 8420fc00 ldff1b \{z0\.s\}, p7/z, \[z0\.s\]
--.*: 8420e060 ldff1b \{z0\.s\}, p0/z, \[z3\.s\]
--.*: 8420e060 ldff1b \{z0\.s\}, p0/z, \[z3\.s\]
--.*: 8420e060 ldff1b \{z0\.s\}, p0/z, \[z3\.s\]
--.*: 8420e3e0 ldff1b \{z0\.s\}, p0/z, \[z31\.s\]
--.*: 8420e3e0 ldff1b \{z0\.s\}, p0/z, \[z31\.s\]
--.*: 8420e3e0 ldff1b \{z0\.s\}, p0/z, \[z31\.s\]
--.*: 842fe000 ldff1b \{z0\.s\}, p0/z, \[z0\.s, #15\]
--.*: 842fe000 ldff1b \{z0\.s\}, p0/z, \[z0\.s, #15\]
--.*: 8430e000 ldff1b \{z0\.s\}, p0/z, \[z0\.s, #16\]
--.*: 8430e000 ldff1b \{z0\.s\}, p0/z, \[z0\.s, #16\]
--.*: 8431e000 ldff1b \{z0\.s\}, p0/z, \[z0\.s, #17\]
--.*: 8431e000 ldff1b \{z0\.s\}, p0/z, \[z0\.s, #17\]
--.*: 843fe000 ldff1b \{z0\.s\}, p0/z, \[z0\.s, #31\]
--.*: 843fe000 ldff1b \{z0\.s\}, p0/z, \[z0\.s, #31\]
--.*: c420e000 ldff1b \{z0\.d\}, p0/z, \[z0\.d\]
--.*: c420e000 ldff1b \{z0\.d\}, p0/z, \[z0\.d\]
--.*: c420e000 ldff1b \{z0\.d\}, p0/z, \[z0\.d\]
--.*: c420e000 ldff1b \{z0\.d\}, p0/z, \[z0\.d\]
--.*: c420e001 ldff1b \{z1\.d\}, p0/z, \[z0\.d\]
--.*: c420e001 ldff1b \{z1\.d\}, p0/z, \[z0\.d\]
--.*: c420e001 ldff1b \{z1\.d\}, p0/z, \[z0\.d\]
--.*: c420e001 ldff1b \{z1\.d\}, p0/z, \[z0\.d\]
--.*: c420e01f ldff1b \{z31\.d\}, p0/z, \[z0\.d\]
--.*: c420e01f ldff1b \{z31\.d\}, p0/z, \[z0\.d\]
--.*: c420e01f ldff1b \{z31\.d\}, p0/z, \[z0\.d\]
--.*: c420e01f ldff1b \{z31\.d\}, p0/z, \[z0\.d\]
--.*: c420e800 ldff1b \{z0\.d\}, p2/z, \[z0\.d\]
--.*: c420e800 ldff1b \{z0\.d\}, p2/z, \[z0\.d\]
--.*: c420e800 ldff1b \{z0\.d\}, p2/z, \[z0\.d\]
--.*: c420fc00 ldff1b \{z0\.d\}, p7/z, \[z0\.d\]
--.*: c420fc00 ldff1b \{z0\.d\}, p7/z, \[z0\.d\]
--.*: c420fc00 ldff1b \{z0\.d\}, p7/z, \[z0\.d\]
--.*: c420e060 ldff1b \{z0\.d\}, p0/z, \[z3\.d\]
--.*: c420e060 ldff1b \{z0\.d\}, p0/z, \[z3\.d\]
--.*: c420e060 ldff1b \{z0\.d\}, p0/z, \[z3\.d\]
--.*: c420e3e0 ldff1b \{z0\.d\}, p0/z, \[z31\.d\]
--.*: c420e3e0 ldff1b \{z0\.d\}, p0/z, \[z31\.d\]
--.*: c420e3e0 ldff1b \{z0\.d\}, p0/z, \[z31\.d\]
--.*: c42fe000 ldff1b \{z0\.d\}, p0/z, \[z0\.d, #15\]
--.*: c42fe000 ldff1b \{z0\.d\}, p0/z, \[z0\.d, #15\]
--.*: c430e000 ldff1b \{z0\.d\}, p0/z, \[z0\.d, #16\]
--.*: c430e000 ldff1b \{z0\.d\}, p0/z, \[z0\.d, #16\]
--.*: c431e000 ldff1b \{z0\.d\}, p0/z, \[z0\.d, #17\]
--.*: c431e000 ldff1b \{z0\.d\}, p0/z, \[z0\.d, #17\]
--.*: c43fe000 ldff1b \{z0\.d\}, p0/z, \[z0\.d, #31\]
--.*: c43fe000 ldff1b \{z0\.d\}, p0/z, \[z0\.d, #31\]
--.*: a5e06000 ldff1d \{z0\.d\}, p0/z, \[x0, x0, lsl #3\]
--.*: a5e06000 ldff1d \{z0\.d\}, p0/z, \[x0, x0, lsl #3\]
--.*: a5e06000 ldff1d \{z0\.d\}, p0/z, \[x0, x0, lsl #3\]
--.*: a5e06001 ldff1d \{z1\.d\}, p0/z, \[x0, x0, lsl #3\]
--.*: a5e06001 ldff1d \{z1\.d\}, p0/z, \[x0, x0, lsl #3\]
--.*: a5e06001 ldff1d \{z1\.d\}, p0/z, \[x0, x0, lsl #3\]
--.*: a5e0601f ldff1d \{z31\.d\}, p0/z, \[x0, x0, lsl #3\]
--.*: a5e0601f ldff1d \{z31\.d\}, p0/z, \[x0, x0, lsl #3\]
--.*: a5e0601f ldff1d \{z31\.d\}, p0/z, \[x0, x0, lsl #3\]
--.*: a5e06800 ldff1d \{z0\.d\}, p2/z, \[x0, x0, lsl #3\]
--.*: a5e06800 ldff1d \{z0\.d\}, p2/z, \[x0, x0, lsl #3\]
--.*: a5e07c00 ldff1d \{z0\.d\}, p7/z, \[x0, x0, lsl #3\]
--.*: a5e07c00 ldff1d \{z0\.d\}, p7/z, \[x0, x0, lsl #3\]
--.*: a5e06060 ldff1d \{z0\.d\}, p0/z, \[x3, x0, lsl #3\]
--.*: a5e06060 ldff1d \{z0\.d\}, p0/z, \[x3, x0, lsl #3\]
--.*: a5e063e0 ldff1d \{z0\.d\}, p0/z, \[sp, x0, lsl #3\]
--.*: a5e063e0 ldff1d \{z0\.d\}, p0/z, \[sp, x0, lsl #3\]
--.*: a5e46000 ldff1d \{z0\.d\}, p0/z, \[x0, x4, lsl #3\]
--.*: a5e46000 ldff1d \{z0\.d\}, p0/z, \[x0, x4, lsl #3\]
--.*: a5ff6000 ldff1d \{z0\.d\}, p0/z, \[x0, xzr, lsl #3\]
--.*: a5ff6000 ldff1d \{z0\.d\}, p0/z, \[x0, xzr, lsl #3\]
--.*: c5806000 ldff1d \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c5806000 ldff1d \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c5806000 ldff1d \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c5806000 ldff1d \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c5806001 ldff1d \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c5806001 ldff1d \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c5806001 ldff1d \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c5806001 ldff1d \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c580601f ldff1d \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c580601f ldff1d \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c580601f ldff1d \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c580601f ldff1d \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c5806800 ldff1d \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\]
--.*: c5806800 ldff1d \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\]
--.*: c5806800 ldff1d \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\]
--.*: c5807c00 ldff1d \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\]
--.*: c5807c00 ldff1d \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\]
--.*: c5807c00 ldff1d \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\]
--.*: c5806060 ldff1d \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\]
--.*: c5806060 ldff1d \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\]
--.*: c5806060 ldff1d \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\]
--.*: c58063e0 ldff1d \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\]
--.*: c58063e0 ldff1d \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\]
--.*: c58063e0 ldff1d \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\]
--.*: c5846000 ldff1d \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\]
--.*: c5846000 ldff1d \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\]
--.*: c5846000 ldff1d \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\]
--.*: c59f6000 ldff1d \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\]
--.*: c59f6000 ldff1d \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\]
--.*: c59f6000 ldff1d \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\]
--.*: c5c06000 ldff1d \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c5c06000 ldff1d \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c5c06000 ldff1d \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c5c06000 ldff1d \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c5c06001 ldff1d \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c5c06001 ldff1d \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c5c06001 ldff1d \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c5c06001 ldff1d \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c5c0601f ldff1d \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c5c0601f ldff1d \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c5c0601f ldff1d \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c5c0601f ldff1d \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c5c06800 ldff1d \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\]
--.*: c5c06800 ldff1d \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\]
--.*: c5c06800 ldff1d \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\]
--.*: c5c07c00 ldff1d \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\]
--.*: c5c07c00 ldff1d \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\]
--.*: c5c07c00 ldff1d \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\]
--.*: c5c06060 ldff1d \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\]
--.*: c5c06060 ldff1d \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\]
--.*: c5c06060 ldff1d \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\]
--.*: c5c063e0 ldff1d \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\]
--.*: c5c063e0 ldff1d \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\]
--.*: c5c063e0 ldff1d \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\]
--.*: c5c46000 ldff1d \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\]
--.*: c5c46000 ldff1d \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\]
--.*: c5c46000 ldff1d \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\]
--.*: c5df6000 ldff1d \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\]
--.*: c5df6000 ldff1d \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\]
--.*: c5df6000 ldff1d \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\]
--.*: c5a06000 ldff1d \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #3\]
--.*: c5a06000 ldff1d \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #3\]
--.*: c5a06000 ldff1d \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #3\]
--.*: c5a06001 ldff1d \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #3\]
--.*: c5a06001 ldff1d \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #3\]
--.*: c5a06001 ldff1d \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #3\]
--.*: c5a0601f ldff1d \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #3\]
--.*: c5a0601f ldff1d \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #3\]
--.*: c5a0601f ldff1d \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #3\]
--.*: c5a06800 ldff1d \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw #3\]
--.*: c5a06800 ldff1d \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw #3\]
--.*: c5a07c00 ldff1d \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw #3\]
--.*: c5a07c00 ldff1d \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw #3\]
--.*: c5a06060 ldff1d \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw #3\]
--.*: c5a06060 ldff1d \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw #3\]
--.*: c5a063e0 ldff1d \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw #3\]
--.*: c5a063e0 ldff1d \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw #3\]
--.*: c5a46000 ldff1d \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw #3\]
--.*: c5a46000 ldff1d \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw #3\]
--.*: c5bf6000 ldff1d \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw #3\]
--.*: c5bf6000 ldff1d \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw #3\]
--.*: c5e06000 ldff1d \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #3\]
--.*: c5e06000 ldff1d \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #3\]
--.*: c5e06000 ldff1d \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #3\]
--.*: c5e06001 ldff1d \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #3\]
--.*: c5e06001 ldff1d \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #3\]
--.*: c5e06001 ldff1d \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #3\]
--.*: c5e0601f ldff1d \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #3\]
--.*: c5e0601f ldff1d \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #3\]
--.*: c5e0601f ldff1d \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #3\]
--.*: c5e06800 ldff1d \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw #3\]
--.*: c5e06800 ldff1d \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw #3\]
--.*: c5e07c00 ldff1d \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw #3\]
--.*: c5e07c00 ldff1d \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw #3\]
--.*: c5e06060 ldff1d \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw #3\]
--.*: c5e06060 ldff1d \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw #3\]
--.*: c5e063e0 ldff1d \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw #3\]
--.*: c5e063e0 ldff1d \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw #3\]
--.*: c5e46000 ldff1d \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw #3\]
--.*: c5e46000 ldff1d \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw #3\]
--.*: c5ff6000 ldff1d \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw #3\]
--.*: c5ff6000 ldff1d \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw #3\]
--.*: c5c0e000 ldff1d \{z0\.d\}, p0/z, \[x0, z0\.d\]
--.*: c5c0e000 ldff1d \{z0\.d\}, p0/z, \[x0, z0\.d\]
--.*: c5c0e000 ldff1d \{z0\.d\}, p0/z, \[x0, z0\.d\]
--.*: c5c0e000 ldff1d \{z0\.d\}, p0/z, \[x0, z0\.d\]
--.*: c5c0e001 ldff1d \{z1\.d\}, p0/z, \[x0, z0\.d\]
--.*: c5c0e001 ldff1d \{z1\.d\}, p0/z, \[x0, z0\.d\]
--.*: c5c0e001 ldff1d \{z1\.d\}, p0/z, \[x0, z0\.d\]
--.*: c5c0e001 ldff1d \{z1\.d\}, p0/z, \[x0, z0\.d\]
--.*: c5c0e01f ldff1d \{z31\.d\}, p0/z, \[x0, z0\.d\]
--.*: c5c0e01f ldff1d \{z31\.d\}, p0/z, \[x0, z0\.d\]
--.*: c5c0e01f ldff1d \{z31\.d\}, p0/z, \[x0, z0\.d\]
--.*: c5c0e01f ldff1d \{z31\.d\}, p0/z, \[x0, z0\.d\]
--.*: c5c0e800 ldff1d \{z0\.d\}, p2/z, \[x0, z0\.d\]
--.*: c5c0e800 ldff1d \{z0\.d\}, p2/z, \[x0, z0\.d\]
--.*: c5c0e800 ldff1d \{z0\.d\}, p2/z, \[x0, z0\.d\]
--.*: c5c0fc00 ldff1d \{z0\.d\}, p7/z, \[x0, z0\.d\]
--.*: c5c0fc00 ldff1d \{z0\.d\}, p7/z, \[x0, z0\.d\]
--.*: c5c0fc00 ldff1d \{z0\.d\}, p7/z, \[x0, z0\.d\]
--.*: c5c0e060 ldff1d \{z0\.d\}, p0/z, \[x3, z0\.d\]
--.*: c5c0e060 ldff1d \{z0\.d\}, p0/z, \[x3, z0\.d\]
--.*: c5c0e060 ldff1d \{z0\.d\}, p0/z, \[x3, z0\.d\]
--.*: c5c0e3e0 ldff1d \{z0\.d\}, p0/z, \[sp, z0\.d\]
--.*: c5c0e3e0 ldff1d \{z0\.d\}, p0/z, \[sp, z0\.d\]
--.*: c5c0e3e0 ldff1d \{z0\.d\}, p0/z, \[sp, z0\.d\]
--.*: c5c4e000 ldff1d \{z0\.d\}, p0/z, \[x0, z4\.d\]
--.*: c5c4e000 ldff1d \{z0\.d\}, p0/z, \[x0, z4\.d\]
--.*: c5c4e000 ldff1d \{z0\.d\}, p0/z, \[x0, z4\.d\]
--.*: c5dfe000 ldff1d \{z0\.d\}, p0/z, \[x0, z31\.d\]
--.*: c5dfe000 ldff1d \{z0\.d\}, p0/z, \[x0, z31\.d\]
--.*: c5dfe000 ldff1d \{z0\.d\}, p0/z, \[x0, z31\.d\]
--.*: c5e0e000 ldff1d \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #3\]
--.*: c5e0e000 ldff1d \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #3\]
--.*: c5e0e000 ldff1d \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #3\]
--.*: c5e0e001 ldff1d \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #3\]
--.*: c5e0e001 ldff1d \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #3\]
--.*: c5e0e001 ldff1d \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #3\]
--.*: c5e0e01f ldff1d \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #3\]
--.*: c5e0e01f ldff1d \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #3\]
--.*: c5e0e01f ldff1d \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #3\]
--.*: c5e0e800 ldff1d \{z0\.d\}, p2/z, \[x0, z0\.d, lsl #3\]
--.*: c5e0e800 ldff1d \{z0\.d\}, p2/z, \[x0, z0\.d, lsl #3\]
--.*: c5e0fc00 ldff1d \{z0\.d\}, p7/z, \[x0, z0\.d, lsl #3\]
--.*: c5e0fc00 ldff1d \{z0\.d\}, p7/z, \[x0, z0\.d, lsl #3\]
--.*: c5e0e060 ldff1d \{z0\.d\}, p0/z, \[x3, z0\.d, lsl #3\]
--.*: c5e0e060 ldff1d \{z0\.d\}, p0/z, \[x3, z0\.d, lsl #3\]
--.*: c5e0e3e0 ldff1d \{z0\.d\}, p0/z, \[sp, z0\.d, lsl #3\]
--.*: c5e0e3e0 ldff1d \{z0\.d\}, p0/z, \[sp, z0\.d, lsl #3\]
--.*: c5e4e000 ldff1d \{z0\.d\}, p0/z, \[x0, z4\.d, lsl #3\]
--.*: c5e4e000 ldff1d \{z0\.d\}, p0/z, \[x0, z4\.d, lsl #3\]
--.*: c5ffe000 ldff1d \{z0\.d\}, p0/z, \[x0, z31\.d, lsl #3\]
--.*: c5ffe000 ldff1d \{z0\.d\}, p0/z, \[x0, z31\.d, lsl #3\]
--.*: c5a0e000 ldff1d \{z0\.d\}, p0/z, \[z0\.d\]
--.*: c5a0e000 ldff1d \{z0\.d\}, p0/z, \[z0\.d\]
--.*: c5a0e000 ldff1d \{z0\.d\}, p0/z, \[z0\.d\]
--.*: c5a0e000 ldff1d \{z0\.d\}, p0/z, \[z0\.d\]
--.*: c5a0e001 ldff1d \{z1\.d\}, p0/z, \[z0\.d\]
--.*: c5a0e001 ldff1d \{z1\.d\}, p0/z, \[z0\.d\]
--.*: c5a0e001 ldff1d \{z1\.d\}, p0/z, \[z0\.d\]
--.*: c5a0e001 ldff1d \{z1\.d\}, p0/z, \[z0\.d\]
--.*: c5a0e01f ldff1d \{z31\.d\}, p0/z, \[z0\.d\]
--.*: c5a0e01f ldff1d \{z31\.d\}, p0/z, \[z0\.d\]
--.*: c5a0e01f ldff1d \{z31\.d\}, p0/z, \[z0\.d\]
--.*: c5a0e01f ldff1d \{z31\.d\}, p0/z, \[z0\.d\]
--.*: c5a0e800 ldff1d \{z0\.d\}, p2/z, \[z0\.d\]
--.*: c5a0e800 ldff1d \{z0\.d\}, p2/z, \[z0\.d\]
--.*: c5a0e800 ldff1d \{z0\.d\}, p2/z, \[z0\.d\]
--.*: c5a0fc00 ldff1d \{z0\.d\}, p7/z, \[z0\.d\]
--.*: c5a0fc00 ldff1d \{z0\.d\}, p7/z, \[z0\.d\]
--.*: c5a0fc00 ldff1d \{z0\.d\}, p7/z, \[z0\.d\]
--.*: c5a0e060 ldff1d \{z0\.d\}, p0/z, \[z3\.d\]
--.*: c5a0e060 ldff1d \{z0\.d\}, p0/z, \[z3\.d\]
--.*: c5a0e060 ldff1d \{z0\.d\}, p0/z, \[z3\.d\]
--.*: c5a0e3e0 ldff1d \{z0\.d\}, p0/z, \[z31\.d\]
--.*: c5a0e3e0 ldff1d \{z0\.d\}, p0/z, \[z31\.d\]
--.*: c5a0e3e0 ldff1d \{z0\.d\}, p0/z, \[z31\.d\]
--.*: c5afe000 ldff1d \{z0\.d\}, p0/z, \[z0\.d, #120\]
--.*: c5afe000 ldff1d \{z0\.d\}, p0/z, \[z0\.d, #120\]
--.*: c5b0e000 ldff1d \{z0\.d\}, p0/z, \[z0\.d, #128\]
--.*: c5b0e000 ldff1d \{z0\.d\}, p0/z, \[z0\.d, #128\]
--.*: c5b1e000 ldff1d \{z0\.d\}, p0/z, \[z0\.d, #136\]
--.*: c5b1e000 ldff1d \{z0\.d\}, p0/z, \[z0\.d, #136\]
--.*: c5bfe000 ldff1d \{z0\.d\}, p0/z, \[z0\.d, #248\]
--.*: c5bfe000 ldff1d \{z0\.d\}, p0/z, \[z0\.d, #248\]
--.*: 84806000 ldff1h \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 84806000 ldff1h \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 84806000 ldff1h \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 84806000 ldff1h \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 84806001 ldff1h \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 84806001 ldff1h \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 84806001 ldff1h \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 84806001 ldff1h \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 8480601f ldff1h \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 8480601f ldff1h \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 8480601f ldff1h \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 8480601f ldff1h \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 84806800 ldff1h \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\]
--.*: 84806800 ldff1h \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\]
--.*: 84806800 ldff1h \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\]
--.*: 84807c00 ldff1h \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\]
--.*: 84807c00 ldff1h \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\]
--.*: 84807c00 ldff1h \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\]
--.*: 84806060 ldff1h \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\]
--.*: 84806060 ldff1h \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\]
--.*: 84806060 ldff1h \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\]
--.*: 848063e0 ldff1h \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\]
--.*: 848063e0 ldff1h \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\]
--.*: 848063e0 ldff1h \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\]
--.*: 84846000 ldff1h \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\]
--.*: 84846000 ldff1h \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\]
--.*: 84846000 ldff1h \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\]
--.*: 849f6000 ldff1h \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\]
--.*: 849f6000 ldff1h \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\]
--.*: 849f6000 ldff1h \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\]
--.*: 84c06000 ldff1h \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 84c06000 ldff1h \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 84c06000 ldff1h \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 84c06000 ldff1h \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 84c06001 ldff1h \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 84c06001 ldff1h \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 84c06001 ldff1h \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 84c06001 ldff1h \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 84c0601f ldff1h \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 84c0601f ldff1h \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 84c0601f ldff1h \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 84c0601f ldff1h \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 84c06800 ldff1h \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\]
--.*: 84c06800 ldff1h \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\]
--.*: 84c06800 ldff1h \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\]
--.*: 84c07c00 ldff1h \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\]
--.*: 84c07c00 ldff1h \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\]
--.*: 84c07c00 ldff1h \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\]
--.*: 84c06060 ldff1h \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\]
--.*: 84c06060 ldff1h \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\]
--.*: 84c06060 ldff1h \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\]
--.*: 84c063e0 ldff1h \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\]
--.*: 84c063e0 ldff1h \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\]
--.*: 84c063e0 ldff1h \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\]
--.*: 84c46000 ldff1h \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\]
--.*: 84c46000 ldff1h \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\]
--.*: 84c46000 ldff1h \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\]
--.*: 84df6000 ldff1h \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\]
--.*: 84df6000 ldff1h \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\]
--.*: 84df6000 ldff1h \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\]
--.*: 84a06000 ldff1h \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw #1\]
--.*: 84a06000 ldff1h \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw #1\]
--.*: 84a06000 ldff1h \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw #1\]
--.*: 84a06001 ldff1h \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw #1\]
--.*: 84a06001 ldff1h \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw #1\]
--.*: 84a06001 ldff1h \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw #1\]
--.*: 84a0601f ldff1h \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw #1\]
--.*: 84a0601f ldff1h \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw #1\]
--.*: 84a0601f ldff1h \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw #1\]
--.*: 84a06800 ldff1h \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw #1\]
--.*: 84a06800 ldff1h \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw #1\]
--.*: 84a07c00 ldff1h \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw #1\]
--.*: 84a07c00 ldff1h \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw #1\]
--.*: 84a06060 ldff1h \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw #1\]
--.*: 84a06060 ldff1h \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw #1\]
--.*: 84a063e0 ldff1h \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw #1\]
--.*: 84a063e0 ldff1h \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw #1\]
--.*: 84a46000 ldff1h \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw #1\]
--.*: 84a46000 ldff1h \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw #1\]
--.*: 84bf6000 ldff1h \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw #1\]
--.*: 84bf6000 ldff1h \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw #1\]
--.*: 84e06000 ldff1h \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw #1\]
--.*: 84e06000 ldff1h \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw #1\]
--.*: 84e06000 ldff1h \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw #1\]
--.*: 84e06001 ldff1h \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw #1\]
--.*: 84e06001 ldff1h \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw #1\]
--.*: 84e06001 ldff1h \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw #1\]
--.*: 84e0601f ldff1h \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw #1\]
--.*: 84e0601f ldff1h \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw #1\]
--.*: 84e0601f ldff1h \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw #1\]
--.*: 84e06800 ldff1h \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw #1\]
--.*: 84e06800 ldff1h \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw #1\]
--.*: 84e07c00 ldff1h \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw #1\]
--.*: 84e07c00 ldff1h \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw #1\]
--.*: 84e06060 ldff1h \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw #1\]
--.*: 84e06060 ldff1h \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw #1\]
--.*: 84e063e0 ldff1h \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw #1\]
--.*: 84e063e0 ldff1h \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw #1\]
--.*: 84e46000 ldff1h \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw #1\]
--.*: 84e46000 ldff1h \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw #1\]
--.*: 84ff6000 ldff1h \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw #1\]
--.*: 84ff6000 ldff1h \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw #1\]
--.*: a4a06000 ldff1h \{z0\.h\}, p0/z, \[x0, x0, lsl #1\]
--.*: a4a06000 ldff1h \{z0\.h\}, p0/z, \[x0, x0, lsl #1\]
--.*: a4a06000 ldff1h \{z0\.h\}, p0/z, \[x0, x0, lsl #1\]
--.*: a4a06001 ldff1h \{z1\.h\}, p0/z, \[x0, x0, lsl #1\]
--.*: a4a06001 ldff1h \{z1\.h\}, p0/z, \[x0, x0, lsl #1\]
--.*: a4a06001 ldff1h \{z1\.h\}, p0/z, \[x0, x0, lsl #1\]
--.*: a4a0601f ldff1h \{z31\.h\}, p0/z, \[x0, x0, lsl #1\]
--.*: a4a0601f ldff1h \{z31\.h\}, p0/z, \[x0, x0, lsl #1\]
--.*: a4a0601f ldff1h \{z31\.h\}, p0/z, \[x0, x0, lsl #1\]
--.*: a4a06800 ldff1h \{z0\.h\}, p2/z, \[x0, x0, lsl #1\]
--.*: a4a06800 ldff1h \{z0\.h\}, p2/z, \[x0, x0, lsl #1\]
--.*: a4a07c00 ldff1h \{z0\.h\}, p7/z, \[x0, x0, lsl #1\]
--.*: a4a07c00 ldff1h \{z0\.h\}, p7/z, \[x0, x0, lsl #1\]
--.*: a4a06060 ldff1h \{z0\.h\}, p0/z, \[x3, x0, lsl #1\]
--.*: a4a06060 ldff1h \{z0\.h\}, p0/z, \[x3, x0, lsl #1\]
--.*: a4a063e0 ldff1h \{z0\.h\}, p0/z, \[sp, x0, lsl #1\]
--.*: a4a063e0 ldff1h \{z0\.h\}, p0/z, \[sp, x0, lsl #1\]
--.*: a4a46000 ldff1h \{z0\.h\}, p0/z, \[x0, x4, lsl #1\]
--.*: a4a46000 ldff1h \{z0\.h\}, p0/z, \[x0, x4, lsl #1\]
--.*: a4bf6000 ldff1h \{z0\.h\}, p0/z, \[x0, xzr, lsl #1\]
--.*: a4bf6000 ldff1h \{z0\.h\}, p0/z, \[x0, xzr, lsl #1\]
--.*: a4c06000 ldff1h \{z0\.s\}, p0/z, \[x0, x0, lsl #1\]
--.*: a4c06000 ldff1h \{z0\.s\}, p0/z, \[x0, x0, lsl #1\]
--.*: a4c06000 ldff1h \{z0\.s\}, p0/z, \[x0, x0, lsl #1\]
--.*: a4c06001 ldff1h \{z1\.s\}, p0/z, \[x0, x0, lsl #1\]
--.*: a4c06001 ldff1h \{z1\.s\}, p0/z, \[x0, x0, lsl #1\]
--.*: a4c06001 ldff1h \{z1\.s\}, p0/z, \[x0, x0, lsl #1\]
--.*: a4c0601f ldff1h \{z31\.s\}, p0/z, \[x0, x0, lsl #1\]
--.*: a4c0601f ldff1h \{z31\.s\}, p0/z, \[x0, x0, lsl #1\]
--.*: a4c0601f ldff1h \{z31\.s\}, p0/z, \[x0, x0, lsl #1\]
--.*: a4c06800 ldff1h \{z0\.s\}, p2/z, \[x0, x0, lsl #1\]
--.*: a4c06800 ldff1h \{z0\.s\}, p2/z, \[x0, x0, lsl #1\]
--.*: a4c07c00 ldff1h \{z0\.s\}, p7/z, \[x0, x0, lsl #1\]
--.*: a4c07c00 ldff1h \{z0\.s\}, p7/z, \[x0, x0, lsl #1\]
--.*: a4c06060 ldff1h \{z0\.s\}, p0/z, \[x3, x0, lsl #1\]
--.*: a4c06060 ldff1h \{z0\.s\}, p0/z, \[x3, x0, lsl #1\]
--.*: a4c063e0 ldff1h \{z0\.s\}, p0/z, \[sp, x0, lsl #1\]
--.*: a4c063e0 ldff1h \{z0\.s\}, p0/z, \[sp, x0, lsl #1\]
--.*: a4c46000 ldff1h \{z0\.s\}, p0/z, \[x0, x4, lsl #1\]
--.*: a4c46000 ldff1h \{z0\.s\}, p0/z, \[x0, x4, lsl #1\]
--.*: a4df6000 ldff1h \{z0\.s\}, p0/z, \[x0, xzr, lsl #1\]
--.*: a4df6000 ldff1h \{z0\.s\}, p0/z, \[x0, xzr, lsl #1\]
--.*: a4e06000 ldff1h \{z0\.d\}, p0/z, \[x0, x0, lsl #1\]
--.*: a4e06000 ldff1h \{z0\.d\}, p0/z, \[x0, x0, lsl #1\]
--.*: a4e06000 ldff1h \{z0\.d\}, p0/z, \[x0, x0, lsl #1\]
--.*: a4e06001 ldff1h \{z1\.d\}, p0/z, \[x0, x0, lsl #1\]
--.*: a4e06001 ldff1h \{z1\.d\}, p0/z, \[x0, x0, lsl #1\]
--.*: a4e06001 ldff1h \{z1\.d\}, p0/z, \[x0, x0, lsl #1\]
--.*: a4e0601f ldff1h \{z31\.d\}, p0/z, \[x0, x0, lsl #1\]
--.*: a4e0601f ldff1h \{z31\.d\}, p0/z, \[x0, x0, lsl #1\]
--.*: a4e0601f ldff1h \{z31\.d\}, p0/z, \[x0, x0, lsl #1\]
--.*: a4e06800 ldff1h \{z0\.d\}, p2/z, \[x0, x0, lsl #1\]
--.*: a4e06800 ldff1h \{z0\.d\}, p2/z, \[x0, x0, lsl #1\]
--.*: a4e07c00 ldff1h \{z0\.d\}, p7/z, \[x0, x0, lsl #1\]
--.*: a4e07c00 ldff1h \{z0\.d\}, p7/z, \[x0, x0, lsl #1\]
--.*: a4e06060 ldff1h \{z0\.d\}, p0/z, \[x3, x0, lsl #1\]
--.*: a4e06060 ldff1h \{z0\.d\}, p0/z, \[x3, x0, lsl #1\]
--.*: a4e063e0 ldff1h \{z0\.d\}, p0/z, \[sp, x0, lsl #1\]
--.*: a4e063e0 ldff1h \{z0\.d\}, p0/z, \[sp, x0, lsl #1\]
--.*: a4e46000 ldff1h \{z0\.d\}, p0/z, \[x0, x4, lsl #1\]
--.*: a4e46000 ldff1h \{z0\.d\}, p0/z, \[x0, x4, lsl #1\]
--.*: a4ff6000 ldff1h \{z0\.d\}, p0/z, \[x0, xzr, lsl #1\]
--.*: a4ff6000 ldff1h \{z0\.d\}, p0/z, \[x0, xzr, lsl #1\]
--.*: c4806000 ldff1h \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c4806000 ldff1h \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c4806000 ldff1h \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c4806000 ldff1h \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c4806001 ldff1h \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c4806001 ldff1h \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c4806001 ldff1h \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c4806001 ldff1h \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c480601f ldff1h \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c480601f ldff1h \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c480601f ldff1h \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c480601f ldff1h \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c4806800 ldff1h \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\]
--.*: c4806800 ldff1h \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\]
--.*: c4806800 ldff1h \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\]
--.*: c4807c00 ldff1h \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\]
--.*: c4807c00 ldff1h \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\]
--.*: c4807c00 ldff1h \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\]
--.*: c4806060 ldff1h \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\]
--.*: c4806060 ldff1h \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\]
--.*: c4806060 ldff1h \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\]
--.*: c48063e0 ldff1h \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\]
--.*: c48063e0 ldff1h \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\]
--.*: c48063e0 ldff1h \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\]
--.*: c4846000 ldff1h \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\]
--.*: c4846000 ldff1h \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\]
--.*: c4846000 ldff1h \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\]
--.*: c49f6000 ldff1h \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\]
--.*: c49f6000 ldff1h \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\]
--.*: c49f6000 ldff1h \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\]
--.*: c4c06000 ldff1h \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c4c06000 ldff1h \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c4c06000 ldff1h \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c4c06000 ldff1h \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c4c06001 ldff1h \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c4c06001 ldff1h \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c4c06001 ldff1h \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c4c06001 ldff1h \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c4c0601f ldff1h \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c4c0601f ldff1h \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c4c0601f ldff1h \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c4c0601f ldff1h \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c4c06800 ldff1h \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\]
--.*: c4c06800 ldff1h \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\]
--.*: c4c06800 ldff1h \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\]
--.*: c4c07c00 ldff1h \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\]
--.*: c4c07c00 ldff1h \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\]
--.*: c4c07c00 ldff1h \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\]
--.*: c4c06060 ldff1h \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\]
--.*: c4c06060 ldff1h \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\]
--.*: c4c06060 ldff1h \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\]
--.*: c4c063e0 ldff1h \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\]
--.*: c4c063e0 ldff1h \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\]
--.*: c4c063e0 ldff1h \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\]
--.*: c4c46000 ldff1h \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\]
--.*: c4c46000 ldff1h \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\]
--.*: c4c46000 ldff1h \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\]
--.*: c4df6000 ldff1h \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\]
--.*: c4df6000 ldff1h \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\]
--.*: c4df6000 ldff1h \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\]
--.*: c4a06000 ldff1h \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #1\]
--.*: c4a06000 ldff1h \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #1\]
--.*: c4a06000 ldff1h \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #1\]
--.*: c4a06001 ldff1h \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #1\]
--.*: c4a06001 ldff1h \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #1\]
--.*: c4a06001 ldff1h \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #1\]
--.*: c4a0601f ldff1h \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #1\]
--.*: c4a0601f ldff1h \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #1\]
--.*: c4a0601f ldff1h \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #1\]
--.*: c4a06800 ldff1h \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw #1\]
--.*: c4a06800 ldff1h \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw #1\]
--.*: c4a07c00 ldff1h \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw #1\]
--.*: c4a07c00 ldff1h \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw #1\]
--.*: c4a06060 ldff1h \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw #1\]
--.*: c4a06060 ldff1h \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw #1\]
--.*: c4a063e0 ldff1h \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw #1\]
--.*: c4a063e0 ldff1h \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw #1\]
--.*: c4a46000 ldff1h \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw #1\]
--.*: c4a46000 ldff1h \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw #1\]
--.*: c4bf6000 ldff1h \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw #1\]
--.*: c4bf6000 ldff1h \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw #1\]
--.*: c4e06000 ldff1h \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #1\]
--.*: c4e06000 ldff1h \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #1\]
--.*: c4e06000 ldff1h \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #1\]
--.*: c4e06001 ldff1h \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #1\]
--.*: c4e06001 ldff1h \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #1\]
--.*: c4e06001 ldff1h \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #1\]
--.*: c4e0601f ldff1h \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #1\]
--.*: c4e0601f ldff1h \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #1\]
--.*: c4e0601f ldff1h \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #1\]
--.*: c4e06800 ldff1h \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw #1\]
--.*: c4e06800 ldff1h \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw #1\]
--.*: c4e07c00 ldff1h \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw #1\]
--.*: c4e07c00 ldff1h \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw #1\]
--.*: c4e06060 ldff1h \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw #1\]
--.*: c4e06060 ldff1h \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw #1\]
--.*: c4e063e0 ldff1h \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw #1\]
--.*: c4e063e0 ldff1h \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw #1\]
--.*: c4e46000 ldff1h \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw #1\]
--.*: c4e46000 ldff1h \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw #1\]
--.*: c4ff6000 ldff1h \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw #1\]
--.*: c4ff6000 ldff1h \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw #1\]
--.*: c4c0e000 ldff1h \{z0\.d\}, p0/z, \[x0, z0\.d\]
--.*: c4c0e000 ldff1h \{z0\.d\}, p0/z, \[x0, z0\.d\]
--.*: c4c0e000 ldff1h \{z0\.d\}, p0/z, \[x0, z0\.d\]
--.*: c4c0e000 ldff1h \{z0\.d\}, p0/z, \[x0, z0\.d\]
--.*: c4c0e001 ldff1h \{z1\.d\}, p0/z, \[x0, z0\.d\]
--.*: c4c0e001 ldff1h \{z1\.d\}, p0/z, \[x0, z0\.d\]
--.*: c4c0e001 ldff1h \{z1\.d\}, p0/z, \[x0, z0\.d\]
--.*: c4c0e001 ldff1h \{z1\.d\}, p0/z, \[x0, z0\.d\]
--.*: c4c0e01f ldff1h \{z31\.d\}, p0/z, \[x0, z0\.d\]
--.*: c4c0e01f ldff1h \{z31\.d\}, p0/z, \[x0, z0\.d\]
--.*: c4c0e01f ldff1h \{z31\.d\}, p0/z, \[x0, z0\.d\]
--.*: c4c0e01f ldff1h \{z31\.d\}, p0/z, \[x0, z0\.d\]
--.*: c4c0e800 ldff1h \{z0\.d\}, p2/z, \[x0, z0\.d\]
--.*: c4c0e800 ldff1h \{z0\.d\}, p2/z, \[x0, z0\.d\]
--.*: c4c0e800 ldff1h \{z0\.d\}, p2/z, \[x0, z0\.d\]
--.*: c4c0fc00 ldff1h \{z0\.d\}, p7/z, \[x0, z0\.d\]
--.*: c4c0fc00 ldff1h \{z0\.d\}, p7/z, \[x0, z0\.d\]
--.*: c4c0fc00 ldff1h \{z0\.d\}, p7/z, \[x0, z0\.d\]
--.*: c4c0e060 ldff1h \{z0\.d\}, p0/z, \[x3, z0\.d\]
--.*: c4c0e060 ldff1h \{z0\.d\}, p0/z, \[x3, z0\.d\]
--.*: c4c0e060 ldff1h \{z0\.d\}, p0/z, \[x3, z0\.d\]
--.*: c4c0e3e0 ldff1h \{z0\.d\}, p0/z, \[sp, z0\.d\]
--.*: c4c0e3e0 ldff1h \{z0\.d\}, p0/z, \[sp, z0\.d\]
--.*: c4c0e3e0 ldff1h \{z0\.d\}, p0/z, \[sp, z0\.d\]
--.*: c4c4e000 ldff1h \{z0\.d\}, p0/z, \[x0, z4\.d\]
--.*: c4c4e000 ldff1h \{z0\.d\}, p0/z, \[x0, z4\.d\]
--.*: c4c4e000 ldff1h \{z0\.d\}, p0/z, \[x0, z4\.d\]
--.*: c4dfe000 ldff1h \{z0\.d\}, p0/z, \[x0, z31\.d\]
--.*: c4dfe000 ldff1h \{z0\.d\}, p0/z, \[x0, z31\.d\]
--.*: c4dfe000 ldff1h \{z0\.d\}, p0/z, \[x0, z31\.d\]
--.*: c4e0e000 ldff1h \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #1\]
--.*: c4e0e000 ldff1h \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #1\]
--.*: c4e0e000 ldff1h \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #1\]
--.*: c4e0e001 ldff1h \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #1\]
--.*: c4e0e001 ldff1h \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #1\]
--.*: c4e0e001 ldff1h \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #1\]
--.*: c4e0e01f ldff1h \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #1\]
--.*: c4e0e01f ldff1h \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #1\]
--.*: c4e0e01f ldff1h \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #1\]
--.*: c4e0e800 ldff1h \{z0\.d\}, p2/z, \[x0, z0\.d, lsl #1\]
--.*: c4e0e800 ldff1h \{z0\.d\}, p2/z, \[x0, z0\.d, lsl #1\]
--.*: c4e0fc00 ldff1h \{z0\.d\}, p7/z, \[x0, z0\.d, lsl #1\]
--.*: c4e0fc00 ldff1h \{z0\.d\}, p7/z, \[x0, z0\.d, lsl #1\]
--.*: c4e0e060 ldff1h \{z0\.d\}, p0/z, \[x3, z0\.d, lsl #1\]
--.*: c4e0e060 ldff1h \{z0\.d\}, p0/z, \[x3, z0\.d, lsl #1\]
--.*: c4e0e3e0 ldff1h \{z0\.d\}, p0/z, \[sp, z0\.d, lsl #1\]
--.*: c4e0e3e0 ldff1h \{z0\.d\}, p0/z, \[sp, z0\.d, lsl #1\]
--.*: c4e4e000 ldff1h \{z0\.d\}, p0/z, \[x0, z4\.d, lsl #1\]
--.*: c4e4e000 ldff1h \{z0\.d\}, p0/z, \[x0, z4\.d, lsl #1\]
--.*: c4ffe000 ldff1h \{z0\.d\}, p0/z, \[x0, z31\.d, lsl #1\]
--.*: c4ffe000 ldff1h \{z0\.d\}, p0/z, \[x0, z31\.d, lsl #1\]
--.*: 84a0e000 ldff1h \{z0\.s\}, p0/z, \[z0\.s\]
--.*: 84a0e000 ldff1h \{z0\.s\}, p0/z, \[z0\.s\]
--.*: 84a0e000 ldff1h \{z0\.s\}, p0/z, \[z0\.s\]
--.*: 84a0e000 ldff1h \{z0\.s\}, p0/z, \[z0\.s\]
--.*: 84a0e001 ldff1h \{z1\.s\}, p0/z, \[z0\.s\]
--.*: 84a0e001 ldff1h \{z1\.s\}, p0/z, \[z0\.s\]
--.*: 84a0e001 ldff1h \{z1\.s\}, p0/z, \[z0\.s\]
--.*: 84a0e001 ldff1h \{z1\.s\}, p0/z, \[z0\.s\]
--.*: 84a0e01f ldff1h \{z31\.s\}, p0/z, \[z0\.s\]
--.*: 84a0e01f ldff1h \{z31\.s\}, p0/z, \[z0\.s\]
--.*: 84a0e01f ldff1h \{z31\.s\}, p0/z, \[z0\.s\]
--.*: 84a0e01f ldff1h \{z31\.s\}, p0/z, \[z0\.s\]
--.*: 84a0e800 ldff1h \{z0\.s\}, p2/z, \[z0\.s\]
--.*: 84a0e800 ldff1h \{z0\.s\}, p2/z, \[z0\.s\]
--.*: 84a0e800 ldff1h \{z0\.s\}, p2/z, \[z0\.s\]
--.*: 84a0fc00 ldff1h \{z0\.s\}, p7/z, \[z0\.s\]
--.*: 84a0fc00 ldff1h \{z0\.s\}, p7/z, \[z0\.s\]
--.*: 84a0fc00 ldff1h \{z0\.s\}, p7/z, \[z0\.s\]
--.*: 84a0e060 ldff1h \{z0\.s\}, p0/z, \[z3\.s\]
--.*: 84a0e060 ldff1h \{z0\.s\}, p0/z, \[z3\.s\]
--.*: 84a0e060 ldff1h \{z0\.s\}, p0/z, \[z3\.s\]
--.*: 84a0e3e0 ldff1h \{z0\.s\}, p0/z, \[z31\.s\]
--.*: 84a0e3e0 ldff1h \{z0\.s\}, p0/z, \[z31\.s\]
--.*: 84a0e3e0 ldff1h \{z0\.s\}, p0/z, \[z31\.s\]
--.*: 84afe000 ldff1h \{z0\.s\}, p0/z, \[z0\.s, #30\]
--.*: 84afe000 ldff1h \{z0\.s\}, p0/z, \[z0\.s, #30\]
--.*: 84b0e000 ldff1h \{z0\.s\}, p0/z, \[z0\.s, #32\]
--.*: 84b0e000 ldff1h \{z0\.s\}, p0/z, \[z0\.s, #32\]
--.*: 84b1e000 ldff1h \{z0\.s\}, p0/z, \[z0\.s, #34\]
--.*: 84b1e000 ldff1h \{z0\.s\}, p0/z, \[z0\.s, #34\]
--.*: 84bfe000 ldff1h \{z0\.s\}, p0/z, \[z0\.s, #62\]
--.*: 84bfe000 ldff1h \{z0\.s\}, p0/z, \[z0\.s, #62\]
--.*: c4a0e000 ldff1h \{z0\.d\}, p0/z, \[z0\.d\]
--.*: c4a0e000 ldff1h \{z0\.d\}, p0/z, \[z0\.d\]
--.*: c4a0e000 ldff1h \{z0\.d\}, p0/z, \[z0\.d\]
--.*: c4a0e000 ldff1h \{z0\.d\}, p0/z, \[z0\.d\]
--.*: c4a0e001 ldff1h \{z1\.d\}, p0/z, \[z0\.d\]
--.*: c4a0e001 ldff1h \{z1\.d\}, p0/z, \[z0\.d\]
--.*: c4a0e001 ldff1h \{z1\.d\}, p0/z, \[z0\.d\]
--.*: c4a0e001 ldff1h \{z1\.d\}, p0/z, \[z0\.d\]
--.*: c4a0e01f ldff1h \{z31\.d\}, p0/z, \[z0\.d\]
--.*: c4a0e01f ldff1h \{z31\.d\}, p0/z, \[z0\.d\]
--.*: c4a0e01f ldff1h \{z31\.d\}, p0/z, \[z0\.d\]
--.*: c4a0e01f ldff1h \{z31\.d\}, p0/z, \[z0\.d\]
--.*: c4a0e800 ldff1h \{z0\.d\}, p2/z, \[z0\.d\]
--.*: c4a0e800 ldff1h \{z0\.d\}, p2/z, \[z0\.d\]
--.*: c4a0e800 ldff1h \{z0\.d\}, p2/z, \[z0\.d\]
--.*: c4a0fc00 ldff1h \{z0\.d\}, p7/z, \[z0\.d\]
--.*: c4a0fc00 ldff1h \{z0\.d\}, p7/z, \[z0\.d\]
--.*: c4a0fc00 ldff1h \{z0\.d\}, p7/z, \[z0\.d\]
--.*: c4a0e060 ldff1h \{z0\.d\}, p0/z, \[z3\.d\]
--.*: c4a0e060 ldff1h \{z0\.d\}, p0/z, \[z3\.d\]
--.*: c4a0e060 ldff1h \{z0\.d\}, p0/z, \[z3\.d\]
--.*: c4a0e3e0 ldff1h \{z0\.d\}, p0/z, \[z31\.d\]
--.*: c4a0e3e0 ldff1h \{z0\.d\}, p0/z, \[z31\.d\]
--.*: c4a0e3e0 ldff1h \{z0\.d\}, p0/z, \[z31\.d\]
--.*: c4afe000 ldff1h \{z0\.d\}, p0/z, \[z0\.d, #30\]
--.*: c4afe000 ldff1h \{z0\.d\}, p0/z, \[z0\.d, #30\]
--.*: c4b0e000 ldff1h \{z0\.d\}, p0/z, \[z0\.d, #32\]
--.*: c4b0e000 ldff1h \{z0\.d\}, p0/z, \[z0\.d, #32\]
--.*: c4b1e000 ldff1h \{z0\.d\}, p0/z, \[z0\.d, #34\]
--.*: c4b1e000 ldff1h \{z0\.d\}, p0/z, \[z0\.d, #34\]
--.*: c4bfe000 ldff1h \{z0\.d\}, p0/z, \[z0\.d, #62\]
--.*: c4bfe000 ldff1h \{z0\.d\}, p0/z, \[z0\.d, #62\]
--.*: 84002000 ldff1sb \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 84002000 ldff1sb \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 84002000 ldff1sb \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 84002000 ldff1sb \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 84002001 ldff1sb \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 84002001 ldff1sb \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 84002001 ldff1sb \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 84002001 ldff1sb \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 8400201f ldff1sb \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 8400201f ldff1sb \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 8400201f ldff1sb \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 8400201f ldff1sb \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 84002800 ldff1sb \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\]
--.*: 84002800 ldff1sb \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\]
--.*: 84002800 ldff1sb \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\]
--.*: 84003c00 ldff1sb \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\]
--.*: 84003c00 ldff1sb \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\]
--.*: 84003c00 ldff1sb \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\]
--.*: 84002060 ldff1sb \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\]
--.*: 84002060 ldff1sb \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\]
--.*: 84002060 ldff1sb \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\]
--.*: 840023e0 ldff1sb \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\]
--.*: 840023e0 ldff1sb \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\]
--.*: 840023e0 ldff1sb \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\]
--.*: 84042000 ldff1sb \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\]
--.*: 84042000 ldff1sb \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\]
--.*: 84042000 ldff1sb \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\]
--.*: 841f2000 ldff1sb \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\]
--.*: 841f2000 ldff1sb \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\]
--.*: 841f2000 ldff1sb \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\]
--.*: 84402000 ldff1sb \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 84402000 ldff1sb \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 84402000 ldff1sb \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 84402000 ldff1sb \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 84402001 ldff1sb \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 84402001 ldff1sb \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 84402001 ldff1sb \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 84402001 ldff1sb \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 8440201f ldff1sb \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 8440201f ldff1sb \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 8440201f ldff1sb \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 8440201f ldff1sb \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 84402800 ldff1sb \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\]
--.*: 84402800 ldff1sb \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\]
--.*: 84402800 ldff1sb \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\]
--.*: 84403c00 ldff1sb \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\]
--.*: 84403c00 ldff1sb \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\]
--.*: 84403c00 ldff1sb \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\]
--.*: 84402060 ldff1sb \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\]
--.*: 84402060 ldff1sb \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\]
--.*: 84402060 ldff1sb \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\]
--.*: 844023e0 ldff1sb \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\]
--.*: 844023e0 ldff1sb \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\]
--.*: 844023e0 ldff1sb \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\]
--.*: 84442000 ldff1sb \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\]
--.*: 84442000 ldff1sb \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\]
--.*: 84442000 ldff1sb \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\]
--.*: 845f2000 ldff1sb \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\]
--.*: 845f2000 ldff1sb \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\]
--.*: 845f2000 ldff1sb \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\]
--.*: a5806000 ldff1sb \{z0\.d\}, p0/z, \[x0, x0\]
--.*: a5806000 ldff1sb \{z0\.d\}, p0/z, \[x0, x0\]
--.*: a5806000 ldff1sb \{z0\.d\}, p0/z, \[x0, x0\]
--.*: a5806000 ldff1sb \{z0\.d\}, p0/z, \[x0, x0\]
--.*: a5806001 ldff1sb \{z1\.d\}, p0/z, \[x0, x0\]
--.*: a5806001 ldff1sb \{z1\.d\}, p0/z, \[x0, x0\]
--.*: a5806001 ldff1sb \{z1\.d\}, p0/z, \[x0, x0\]
--.*: a5806001 ldff1sb \{z1\.d\}, p0/z, \[x0, x0\]
--.*: a580601f ldff1sb \{z31\.d\}, p0/z, \[x0, x0\]
--.*: a580601f ldff1sb \{z31\.d\}, p0/z, \[x0, x0\]
--.*: a580601f ldff1sb \{z31\.d\}, p0/z, \[x0, x0\]
--.*: a580601f ldff1sb \{z31\.d\}, p0/z, \[x0, x0\]
--.*: a5806800 ldff1sb \{z0\.d\}, p2/z, \[x0, x0\]
--.*: a5806800 ldff1sb \{z0\.d\}, p2/z, \[x0, x0\]
--.*: a5806800 ldff1sb \{z0\.d\}, p2/z, \[x0, x0\]
--.*: a5807c00 ldff1sb \{z0\.d\}, p7/z, \[x0, x0\]
--.*: a5807c00 ldff1sb \{z0\.d\}, p7/z, \[x0, x0\]
--.*: a5807c00 ldff1sb \{z0\.d\}, p7/z, \[x0, x0\]
--.*: a5806060 ldff1sb \{z0\.d\}, p0/z, \[x3, x0\]
--.*: a5806060 ldff1sb \{z0\.d\}, p0/z, \[x3, x0\]
--.*: a5806060 ldff1sb \{z0\.d\}, p0/z, \[x3, x0\]
--.*: a58063e0 ldff1sb \{z0\.d\}, p0/z, \[sp, x0\]
--.*: a58063e0 ldff1sb \{z0\.d\}, p0/z, \[sp, x0\]
--.*: a58063e0 ldff1sb \{z0\.d\}, p0/z, \[sp, x0\]
--.*: a5846000 ldff1sb \{z0\.d\}, p0/z, \[x0, x4\]
--.*: a5846000 ldff1sb \{z0\.d\}, p0/z, \[x0, x4\]
--.*: a5846000 ldff1sb \{z0\.d\}, p0/z, \[x0, x4\]
--.*: a59f6000 ldff1sb \{z0\.d\}, p0/z, \[x0, xzr\]
--.*: a59f6000 ldff1sb \{z0\.d\}, p0/z, \[x0, xzr\]
--.*: a59f6000 ldff1sb \{z0\.d\}, p0/z, \[x0, xzr\]
--.*: a5a06000 ldff1sb \{z0\.s\}, p0/z, \[x0, x0\]
--.*: a5a06000 ldff1sb \{z0\.s\}, p0/z, \[x0, x0\]
--.*: a5a06000 ldff1sb \{z0\.s\}, p0/z, \[x0, x0\]
--.*: a5a06000 ldff1sb \{z0\.s\}, p0/z, \[x0, x0\]
--.*: a5a06001 ldff1sb \{z1\.s\}, p0/z, \[x0, x0\]
--.*: a5a06001 ldff1sb \{z1\.s\}, p0/z, \[x0, x0\]
--.*: a5a06001 ldff1sb \{z1\.s\}, p0/z, \[x0, x0\]
--.*: a5a06001 ldff1sb \{z1\.s\}, p0/z, \[x0, x0\]
--.*: a5a0601f ldff1sb \{z31\.s\}, p0/z, \[x0, x0\]
--.*: a5a0601f ldff1sb \{z31\.s\}, p0/z, \[x0, x0\]
--.*: a5a0601f ldff1sb \{z31\.s\}, p0/z, \[x0, x0\]
--.*: a5a0601f ldff1sb \{z31\.s\}, p0/z, \[x0, x0\]
--.*: a5a06800 ldff1sb \{z0\.s\}, p2/z, \[x0, x0\]
--.*: a5a06800 ldff1sb \{z0\.s\}, p2/z, \[x0, x0\]
--.*: a5a06800 ldff1sb \{z0\.s\}, p2/z, \[x0, x0\]
--.*: a5a07c00 ldff1sb \{z0\.s\}, p7/z, \[x0, x0\]
--.*: a5a07c00 ldff1sb \{z0\.s\}, p7/z, \[x0, x0\]
--.*: a5a07c00 ldff1sb \{z0\.s\}, p7/z, \[x0, x0\]
--.*: a5a06060 ldff1sb \{z0\.s\}, p0/z, \[x3, x0\]
--.*: a5a06060 ldff1sb \{z0\.s\}, p0/z, \[x3, x0\]
--.*: a5a06060 ldff1sb \{z0\.s\}, p0/z, \[x3, x0\]
--.*: a5a063e0 ldff1sb \{z0\.s\}, p0/z, \[sp, x0\]
--.*: a5a063e0 ldff1sb \{z0\.s\}, p0/z, \[sp, x0\]
--.*: a5a063e0 ldff1sb \{z0\.s\}, p0/z, \[sp, x0\]
--.*: a5a46000 ldff1sb \{z0\.s\}, p0/z, \[x0, x4\]
--.*: a5a46000 ldff1sb \{z0\.s\}, p0/z, \[x0, x4\]
--.*: a5a46000 ldff1sb \{z0\.s\}, p0/z, \[x0, x4\]
--.*: a5bf6000 ldff1sb \{z0\.s\}, p0/z, \[x0, xzr\]
--.*: a5bf6000 ldff1sb \{z0\.s\}, p0/z, \[x0, xzr\]
--.*: a5bf6000 ldff1sb \{z0\.s\}, p0/z, \[x0, xzr\]
--.*: a5c06000 ldff1sb \{z0\.h\}, p0/z, \[x0, x0\]
--.*: a5c06000 ldff1sb \{z0\.h\}, p0/z, \[x0, x0\]
--.*: a5c06000 ldff1sb \{z0\.h\}, p0/z, \[x0, x0\]
--.*: a5c06000 ldff1sb \{z0\.h\}, p0/z, \[x0, x0\]
--.*: a5c06001 ldff1sb \{z1\.h\}, p0/z, \[x0, x0\]
--.*: a5c06001 ldff1sb \{z1\.h\}, p0/z, \[x0, x0\]
--.*: a5c06001 ldff1sb \{z1\.h\}, p0/z, \[x0, x0\]
--.*: a5c06001 ldff1sb \{z1\.h\}, p0/z, \[x0, x0\]
--.*: a5c0601f ldff1sb \{z31\.h\}, p0/z, \[x0, x0\]
--.*: a5c0601f ldff1sb \{z31\.h\}, p0/z, \[x0, x0\]
--.*: a5c0601f ldff1sb \{z31\.h\}, p0/z, \[x0, x0\]
--.*: a5c0601f ldff1sb \{z31\.h\}, p0/z, \[x0, x0\]
--.*: a5c06800 ldff1sb \{z0\.h\}, p2/z, \[x0, x0\]
--.*: a5c06800 ldff1sb \{z0\.h\}, p2/z, \[x0, x0\]
--.*: a5c06800 ldff1sb \{z0\.h\}, p2/z, \[x0, x0\]
--.*: a5c07c00 ldff1sb \{z0\.h\}, p7/z, \[x0, x0\]
--.*: a5c07c00 ldff1sb \{z0\.h\}, p7/z, \[x0, x0\]
--.*: a5c07c00 ldff1sb \{z0\.h\}, p7/z, \[x0, x0\]
--.*: a5c06060 ldff1sb \{z0\.h\}, p0/z, \[x3, x0\]
--.*: a5c06060 ldff1sb \{z0\.h\}, p0/z, \[x3, x0\]
--.*: a5c06060 ldff1sb \{z0\.h\}, p0/z, \[x3, x0\]
--.*: a5c063e0 ldff1sb \{z0\.h\}, p0/z, \[sp, x0\]
--.*: a5c063e0 ldff1sb \{z0\.h\}, p0/z, \[sp, x0\]
--.*: a5c063e0 ldff1sb \{z0\.h\}, p0/z, \[sp, x0\]
--.*: a5c46000 ldff1sb \{z0\.h\}, p0/z, \[x0, x4\]
--.*: a5c46000 ldff1sb \{z0\.h\}, p0/z, \[x0, x4\]
--.*: a5c46000 ldff1sb \{z0\.h\}, p0/z, \[x0, x4\]
--.*: a5df6000 ldff1sb \{z0\.h\}, p0/z, \[x0, xzr\]
--.*: a5df6000 ldff1sb \{z0\.h\}, p0/z, \[x0, xzr\]
--.*: a5df6000 ldff1sb \{z0\.h\}, p0/z, \[x0, xzr\]
--.*: c4002000 ldff1sb \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c4002000 ldff1sb \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c4002000 ldff1sb \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c4002000 ldff1sb \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c4002001 ldff1sb \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c4002001 ldff1sb \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c4002001 ldff1sb \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c4002001 ldff1sb \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c400201f ldff1sb \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c400201f ldff1sb \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c400201f ldff1sb \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c400201f ldff1sb \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c4002800 ldff1sb \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\]
--.*: c4002800 ldff1sb \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\]
--.*: c4002800 ldff1sb \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\]
--.*: c4003c00 ldff1sb \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\]
--.*: c4003c00 ldff1sb \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\]
--.*: c4003c00 ldff1sb \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\]
--.*: c4002060 ldff1sb \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\]
--.*: c4002060 ldff1sb \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\]
--.*: c4002060 ldff1sb \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\]
--.*: c40023e0 ldff1sb \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\]
--.*: c40023e0 ldff1sb \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\]
--.*: c40023e0 ldff1sb \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\]
--.*: c4042000 ldff1sb \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\]
--.*: c4042000 ldff1sb \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\]
--.*: c4042000 ldff1sb \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\]
--.*: c41f2000 ldff1sb \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\]
--.*: c41f2000 ldff1sb \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\]
--.*: c41f2000 ldff1sb \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\]
--.*: c4402000 ldff1sb \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c4402000 ldff1sb \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c4402000 ldff1sb \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c4402000 ldff1sb \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c4402001 ldff1sb \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c4402001 ldff1sb \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c4402001 ldff1sb \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c4402001 ldff1sb \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c440201f ldff1sb \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c440201f ldff1sb \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c440201f ldff1sb \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c440201f ldff1sb \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c4402800 ldff1sb \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\]
--.*: c4402800 ldff1sb \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\]
--.*: c4402800 ldff1sb \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\]
--.*: c4403c00 ldff1sb \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\]
--.*: c4403c00 ldff1sb \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\]
--.*: c4403c00 ldff1sb \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\]
--.*: c4402060 ldff1sb \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\]
--.*: c4402060 ldff1sb \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\]
--.*: c4402060 ldff1sb \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\]
--.*: c44023e0 ldff1sb \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\]
--.*: c44023e0 ldff1sb \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\]
--.*: c44023e0 ldff1sb \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\]
--.*: c4442000 ldff1sb \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\]
--.*: c4442000 ldff1sb \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\]
--.*: c4442000 ldff1sb \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\]
--.*: c45f2000 ldff1sb \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\]
--.*: c45f2000 ldff1sb \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\]
--.*: c45f2000 ldff1sb \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\]
--.*: c440a000 ldff1sb \{z0\.d\}, p0/z, \[x0, z0\.d\]
--.*: c440a000 ldff1sb \{z0\.d\}, p0/z, \[x0, z0\.d\]
--.*: c440a000 ldff1sb \{z0\.d\}, p0/z, \[x0, z0\.d\]
--.*: c440a000 ldff1sb \{z0\.d\}, p0/z, \[x0, z0\.d\]
--.*: c440a001 ldff1sb \{z1\.d\}, p0/z, \[x0, z0\.d\]
--.*: c440a001 ldff1sb \{z1\.d\}, p0/z, \[x0, z0\.d\]
--.*: c440a001 ldff1sb \{z1\.d\}, p0/z, \[x0, z0\.d\]
--.*: c440a001 ldff1sb \{z1\.d\}, p0/z, \[x0, z0\.d\]
--.*: c440a01f ldff1sb \{z31\.d\}, p0/z, \[x0, z0\.d\]
--.*: c440a01f ldff1sb \{z31\.d\}, p0/z, \[x0, z0\.d\]
--.*: c440a01f ldff1sb \{z31\.d\}, p0/z, \[x0, z0\.d\]
--.*: c440a01f ldff1sb \{z31\.d\}, p0/z, \[x0, z0\.d\]
--.*: c440a800 ldff1sb \{z0\.d\}, p2/z, \[x0, z0\.d\]
--.*: c440a800 ldff1sb \{z0\.d\}, p2/z, \[x0, z0\.d\]
--.*: c440a800 ldff1sb \{z0\.d\}, p2/z, \[x0, z0\.d\]
--.*: c440bc00 ldff1sb \{z0\.d\}, p7/z, \[x0, z0\.d\]
--.*: c440bc00 ldff1sb \{z0\.d\}, p7/z, \[x0, z0\.d\]
--.*: c440bc00 ldff1sb \{z0\.d\}, p7/z, \[x0, z0\.d\]
--.*: c440a060 ldff1sb \{z0\.d\}, p0/z, \[x3, z0\.d\]
--.*: c440a060 ldff1sb \{z0\.d\}, p0/z, \[x3, z0\.d\]
--.*: c440a060 ldff1sb \{z0\.d\}, p0/z, \[x3, z0\.d\]
--.*: c440a3e0 ldff1sb \{z0\.d\}, p0/z, \[sp, z0\.d\]
--.*: c440a3e0 ldff1sb \{z0\.d\}, p0/z, \[sp, z0\.d\]
--.*: c440a3e0 ldff1sb \{z0\.d\}, p0/z, \[sp, z0\.d\]
--.*: c444a000 ldff1sb \{z0\.d\}, p0/z, \[x0, z4\.d\]
--.*: c444a000 ldff1sb \{z0\.d\}, p0/z, \[x0, z4\.d\]
--.*: c444a000 ldff1sb \{z0\.d\}, p0/z, \[x0, z4\.d\]
--.*: c45fa000 ldff1sb \{z0\.d\}, p0/z, \[x0, z31\.d\]
--.*: c45fa000 ldff1sb \{z0\.d\}, p0/z, \[x0, z31\.d\]
--.*: c45fa000 ldff1sb \{z0\.d\}, p0/z, \[x0, z31\.d\]
--.*: 8420a000 ldff1sb \{z0\.s\}, p0/z, \[z0\.s\]
--.*: 8420a000 ldff1sb \{z0\.s\}, p0/z, \[z0\.s\]
--.*: 8420a000 ldff1sb \{z0\.s\}, p0/z, \[z0\.s\]
--.*: 8420a000 ldff1sb \{z0\.s\}, p0/z, \[z0\.s\]
--.*: 8420a001 ldff1sb \{z1\.s\}, p0/z, \[z0\.s\]
--.*: 8420a001 ldff1sb \{z1\.s\}, p0/z, \[z0\.s\]
--.*: 8420a001 ldff1sb \{z1\.s\}, p0/z, \[z0\.s\]
--.*: 8420a001 ldff1sb \{z1\.s\}, p0/z, \[z0\.s\]
--.*: 8420a01f ldff1sb \{z31\.s\}, p0/z, \[z0\.s\]
--.*: 8420a01f ldff1sb \{z31\.s\}, p0/z, \[z0\.s\]
--.*: 8420a01f ldff1sb \{z31\.s\}, p0/z, \[z0\.s\]
--.*: 8420a01f ldff1sb \{z31\.s\}, p0/z, \[z0\.s\]
--.*: 8420a800 ldff1sb \{z0\.s\}, p2/z, \[z0\.s\]
--.*: 8420a800 ldff1sb \{z0\.s\}, p2/z, \[z0\.s\]
--.*: 8420a800 ldff1sb \{z0\.s\}, p2/z, \[z0\.s\]
--.*: 8420bc00 ldff1sb \{z0\.s\}, p7/z, \[z0\.s\]
--.*: 8420bc00 ldff1sb \{z0\.s\}, p7/z, \[z0\.s\]
--.*: 8420bc00 ldff1sb \{z0\.s\}, p7/z, \[z0\.s\]
--.*: 8420a060 ldff1sb \{z0\.s\}, p0/z, \[z3\.s\]
--.*: 8420a060 ldff1sb \{z0\.s\}, p0/z, \[z3\.s\]
--.*: 8420a060 ldff1sb \{z0\.s\}, p0/z, \[z3\.s\]
--.*: 8420a3e0 ldff1sb \{z0\.s\}, p0/z, \[z31\.s\]
--.*: 8420a3e0 ldff1sb \{z0\.s\}, p0/z, \[z31\.s\]
--.*: 8420a3e0 ldff1sb \{z0\.s\}, p0/z, \[z31\.s\]
--.*: 842fa000 ldff1sb \{z0\.s\}, p0/z, \[z0\.s, #15\]
--.*: 842fa000 ldff1sb \{z0\.s\}, p0/z, \[z0\.s, #15\]
--.*: 8430a000 ldff1sb \{z0\.s\}, p0/z, \[z0\.s, #16\]
--.*: 8430a000 ldff1sb \{z0\.s\}, p0/z, \[z0\.s, #16\]
--.*: 8431a000 ldff1sb \{z0\.s\}, p0/z, \[z0\.s, #17\]
--.*: 8431a000 ldff1sb \{z0\.s\}, p0/z, \[z0\.s, #17\]
--.*: 843fa000 ldff1sb \{z0\.s\}, p0/z, \[z0\.s, #31\]
--.*: 843fa000 ldff1sb \{z0\.s\}, p0/z, \[z0\.s, #31\]
--.*: c420a000 ldff1sb \{z0\.d\}, p0/z, \[z0\.d\]
--.*: c420a000 ldff1sb \{z0\.d\}, p0/z, \[z0\.d\]
--.*: c420a000 ldff1sb \{z0\.d\}, p0/z, \[z0\.d\]
--.*: c420a000 ldff1sb \{z0\.d\}, p0/z, \[z0\.d\]
--.*: c420a001 ldff1sb \{z1\.d\}, p0/z, \[z0\.d\]
--.*: c420a001 ldff1sb \{z1\.d\}, p0/z, \[z0\.d\]
--.*: c420a001 ldff1sb \{z1\.d\}, p0/z, \[z0\.d\]
--.*: c420a001 ldff1sb \{z1\.d\}, p0/z, \[z0\.d\]
--.*: c420a01f ldff1sb \{z31\.d\}, p0/z, \[z0\.d\]
--.*: c420a01f ldff1sb \{z31\.d\}, p0/z, \[z0\.d\]
--.*: c420a01f ldff1sb \{z31\.d\}, p0/z, \[z0\.d\]
--.*: c420a01f ldff1sb \{z31\.d\}, p0/z, \[z0\.d\]
--.*: c420a800 ldff1sb \{z0\.d\}, p2/z, \[z0\.d\]
--.*: c420a800 ldff1sb \{z0\.d\}, p2/z, \[z0\.d\]
--.*: c420a800 ldff1sb \{z0\.d\}, p2/z, \[z0\.d\]
--.*: c420bc00 ldff1sb \{z0\.d\}, p7/z, \[z0\.d\]
--.*: c420bc00 ldff1sb \{z0\.d\}, p7/z, \[z0\.d\]
--.*: c420bc00 ldff1sb \{z0\.d\}, p7/z, \[z0\.d\]
--.*: c420a060 ldff1sb \{z0\.d\}, p0/z, \[z3\.d\]
--.*: c420a060 ldff1sb \{z0\.d\}, p0/z, \[z3\.d\]
--.*: c420a060 ldff1sb \{z0\.d\}, p0/z, \[z3\.d\]
--.*: c420a3e0 ldff1sb \{z0\.d\}, p0/z, \[z31\.d\]
--.*: c420a3e0 ldff1sb \{z0\.d\}, p0/z, \[z31\.d\]
--.*: c420a3e0 ldff1sb \{z0\.d\}, p0/z, \[z31\.d\]
--.*: c42fa000 ldff1sb \{z0\.d\}, p0/z, \[z0\.d, #15\]
--.*: c42fa000 ldff1sb \{z0\.d\}, p0/z, \[z0\.d, #15\]
--.*: c430a000 ldff1sb \{z0\.d\}, p0/z, \[z0\.d, #16\]
--.*: c430a000 ldff1sb \{z0\.d\}, p0/z, \[z0\.d, #16\]
--.*: c431a000 ldff1sb \{z0\.d\}, p0/z, \[z0\.d, #17\]
--.*: c431a000 ldff1sb \{z0\.d\}, p0/z, \[z0\.d, #17\]
--.*: c43fa000 ldff1sb \{z0\.d\}, p0/z, \[z0\.d, #31\]
--.*: c43fa000 ldff1sb \{z0\.d\}, p0/z, \[z0\.d, #31\]
--.*: 84802000 ldff1sh \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 84802000 ldff1sh \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 84802000 ldff1sh \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 84802000 ldff1sh \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 84802001 ldff1sh \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 84802001 ldff1sh \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 84802001 ldff1sh \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 84802001 ldff1sh \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 8480201f ldff1sh \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 8480201f ldff1sh \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 8480201f ldff1sh \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 8480201f ldff1sh \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 84802800 ldff1sh \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\]
--.*: 84802800 ldff1sh \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\]
--.*: 84802800 ldff1sh \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\]
--.*: 84803c00 ldff1sh \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\]
--.*: 84803c00 ldff1sh \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\]
--.*: 84803c00 ldff1sh \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\]
--.*: 84802060 ldff1sh \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\]
--.*: 84802060 ldff1sh \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\]
--.*: 84802060 ldff1sh \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\]
--.*: 848023e0 ldff1sh \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\]
--.*: 848023e0 ldff1sh \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\]
--.*: 848023e0 ldff1sh \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\]
--.*: 84842000 ldff1sh \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\]
--.*: 84842000 ldff1sh \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\]
--.*: 84842000 ldff1sh \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\]
--.*: 849f2000 ldff1sh \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\]
--.*: 849f2000 ldff1sh \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\]
--.*: 849f2000 ldff1sh \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\]
--.*: 84c02000 ldff1sh \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 84c02000 ldff1sh \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 84c02000 ldff1sh \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 84c02000 ldff1sh \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 84c02001 ldff1sh \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 84c02001 ldff1sh \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 84c02001 ldff1sh \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 84c02001 ldff1sh \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 84c0201f ldff1sh \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 84c0201f ldff1sh \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 84c0201f ldff1sh \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 84c0201f ldff1sh \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 84c02800 ldff1sh \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\]
--.*: 84c02800 ldff1sh \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\]
--.*: 84c02800 ldff1sh \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\]
--.*: 84c03c00 ldff1sh \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\]
--.*: 84c03c00 ldff1sh \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\]
--.*: 84c03c00 ldff1sh \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\]
--.*: 84c02060 ldff1sh \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\]
--.*: 84c02060 ldff1sh \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\]
--.*: 84c02060 ldff1sh \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\]
--.*: 84c023e0 ldff1sh \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\]
--.*: 84c023e0 ldff1sh \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\]
--.*: 84c023e0 ldff1sh \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\]
--.*: 84c42000 ldff1sh \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\]
--.*: 84c42000 ldff1sh \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\]
--.*: 84c42000 ldff1sh \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\]
--.*: 84df2000 ldff1sh \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\]
--.*: 84df2000 ldff1sh \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\]
--.*: 84df2000 ldff1sh \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\]
--.*: 84a02000 ldff1sh \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw #1\]
--.*: 84a02000 ldff1sh \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw #1\]
--.*: 84a02000 ldff1sh \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw #1\]
--.*: 84a02001 ldff1sh \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw #1\]
--.*: 84a02001 ldff1sh \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw #1\]
--.*: 84a02001 ldff1sh \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw #1\]
--.*: 84a0201f ldff1sh \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw #1\]
--.*: 84a0201f ldff1sh \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw #1\]
--.*: 84a0201f ldff1sh \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw #1\]
--.*: 84a02800 ldff1sh \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw #1\]
--.*: 84a02800 ldff1sh \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw #1\]
--.*: 84a03c00 ldff1sh \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw #1\]
--.*: 84a03c00 ldff1sh \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw #1\]
--.*: 84a02060 ldff1sh \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw #1\]
--.*: 84a02060 ldff1sh \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw #1\]
--.*: 84a023e0 ldff1sh \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw #1\]
--.*: 84a023e0 ldff1sh \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw #1\]
--.*: 84a42000 ldff1sh \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw #1\]
--.*: 84a42000 ldff1sh \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw #1\]
--.*: 84bf2000 ldff1sh \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw #1\]
--.*: 84bf2000 ldff1sh \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw #1\]
--.*: 84e02000 ldff1sh \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw #1\]
--.*: 84e02000 ldff1sh \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw #1\]
--.*: 84e02000 ldff1sh \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw #1\]
--.*: 84e02001 ldff1sh \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw #1\]
--.*: 84e02001 ldff1sh \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw #1\]
--.*: 84e02001 ldff1sh \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw #1\]
--.*: 84e0201f ldff1sh \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw #1\]
--.*: 84e0201f ldff1sh \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw #1\]
--.*: 84e0201f ldff1sh \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw #1\]
--.*: 84e02800 ldff1sh \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw #1\]
--.*: 84e02800 ldff1sh \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw #1\]
--.*: 84e03c00 ldff1sh \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw #1\]
--.*: 84e03c00 ldff1sh \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw #1\]
--.*: 84e02060 ldff1sh \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw #1\]
--.*: 84e02060 ldff1sh \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw #1\]
--.*: 84e023e0 ldff1sh \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw #1\]
--.*: 84e023e0 ldff1sh \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw #1\]
--.*: 84e42000 ldff1sh \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw #1\]
--.*: 84e42000 ldff1sh \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw #1\]
--.*: 84ff2000 ldff1sh \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw #1\]
--.*: 84ff2000 ldff1sh \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw #1\]
--.*: a5006000 ldff1sh \{z0\.d\}, p0/z, \[x0, x0, lsl #1\]
--.*: a5006000 ldff1sh \{z0\.d\}, p0/z, \[x0, x0, lsl #1\]
--.*: a5006000 ldff1sh \{z0\.d\}, p0/z, \[x0, x0, lsl #1\]
--.*: a5006001 ldff1sh \{z1\.d\}, p0/z, \[x0, x0, lsl #1\]
--.*: a5006001 ldff1sh \{z1\.d\}, p0/z, \[x0, x0, lsl #1\]
--.*: a5006001 ldff1sh \{z1\.d\}, p0/z, \[x0, x0, lsl #1\]
--.*: a500601f ldff1sh \{z31\.d\}, p0/z, \[x0, x0, lsl #1\]
--.*: a500601f ldff1sh \{z31\.d\}, p0/z, \[x0, x0, lsl #1\]
--.*: a500601f ldff1sh \{z31\.d\}, p0/z, \[x0, x0, lsl #1\]
--.*: a5006800 ldff1sh \{z0\.d\}, p2/z, \[x0, x0, lsl #1\]
--.*: a5006800 ldff1sh \{z0\.d\}, p2/z, \[x0, x0, lsl #1\]
--.*: a5007c00 ldff1sh \{z0\.d\}, p7/z, \[x0, x0, lsl #1\]
--.*: a5007c00 ldff1sh \{z0\.d\}, p7/z, \[x0, x0, lsl #1\]
--.*: a5006060 ldff1sh \{z0\.d\}, p0/z, \[x3, x0, lsl #1\]
--.*: a5006060 ldff1sh \{z0\.d\}, p0/z, \[x3, x0, lsl #1\]
--.*: a50063e0 ldff1sh \{z0\.d\}, p0/z, \[sp, x0, lsl #1\]
--.*: a50063e0 ldff1sh \{z0\.d\}, p0/z, \[sp, x0, lsl #1\]
--.*: a5046000 ldff1sh \{z0\.d\}, p0/z, \[x0, x4, lsl #1\]
--.*: a5046000 ldff1sh \{z0\.d\}, p0/z, \[x0, x4, lsl #1\]
--.*: a51f6000 ldff1sh \{z0\.d\}, p0/z, \[x0, xzr, lsl #1\]
--.*: a51f6000 ldff1sh \{z0\.d\}, p0/z, \[x0, xzr, lsl #1\]
--.*: a5206000 ldff1sh \{z0\.s\}, p0/z, \[x0, x0, lsl #1\]
--.*: a5206000 ldff1sh \{z0\.s\}, p0/z, \[x0, x0, lsl #1\]
--.*: a5206000 ldff1sh \{z0\.s\}, p0/z, \[x0, x0, lsl #1\]
--.*: a5206001 ldff1sh \{z1\.s\}, p0/z, \[x0, x0, lsl #1\]
--.*: a5206001 ldff1sh \{z1\.s\}, p0/z, \[x0, x0, lsl #1\]
--.*: a5206001 ldff1sh \{z1\.s\}, p0/z, \[x0, x0, lsl #1\]
--.*: a520601f ldff1sh \{z31\.s\}, p0/z, \[x0, x0, lsl #1\]
--.*: a520601f ldff1sh \{z31\.s\}, p0/z, \[x0, x0, lsl #1\]
--.*: a520601f ldff1sh \{z31\.s\}, p0/z, \[x0, x0, lsl #1\]
--.*: a5206800 ldff1sh \{z0\.s\}, p2/z, \[x0, x0, lsl #1\]
--.*: a5206800 ldff1sh \{z0\.s\}, p2/z, \[x0, x0, lsl #1\]
--.*: a5207c00 ldff1sh \{z0\.s\}, p7/z, \[x0, x0, lsl #1\]
--.*: a5207c00 ldff1sh \{z0\.s\}, p7/z, \[x0, x0, lsl #1\]
--.*: a5206060 ldff1sh \{z0\.s\}, p0/z, \[x3, x0, lsl #1\]
--.*: a5206060 ldff1sh \{z0\.s\}, p0/z, \[x3, x0, lsl #1\]
--.*: a52063e0 ldff1sh \{z0\.s\}, p0/z, \[sp, x0, lsl #1\]
--.*: a52063e0 ldff1sh \{z0\.s\}, p0/z, \[sp, x0, lsl #1\]
--.*: a5246000 ldff1sh \{z0\.s\}, p0/z, \[x0, x4, lsl #1\]
--.*: a5246000 ldff1sh \{z0\.s\}, p0/z, \[x0, x4, lsl #1\]
--.*: a53f6000 ldff1sh \{z0\.s\}, p0/z, \[x0, xzr, lsl #1\]
--.*: a53f6000 ldff1sh \{z0\.s\}, p0/z, \[x0, xzr, lsl #1\]
--.*: c4802000 ldff1sh \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c4802000 ldff1sh \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c4802000 ldff1sh \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c4802000 ldff1sh \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c4802001 ldff1sh \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c4802001 ldff1sh \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c4802001 ldff1sh \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c4802001 ldff1sh \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c480201f ldff1sh \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c480201f ldff1sh \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c480201f ldff1sh \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c480201f ldff1sh \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c4802800 ldff1sh \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\]
--.*: c4802800 ldff1sh \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\]
--.*: c4802800 ldff1sh \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\]
--.*: c4803c00 ldff1sh \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\]
--.*: c4803c00 ldff1sh \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\]
--.*: c4803c00 ldff1sh \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\]
--.*: c4802060 ldff1sh \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\]
--.*: c4802060 ldff1sh \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\]
--.*: c4802060 ldff1sh \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\]
--.*: c48023e0 ldff1sh \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\]
--.*: c48023e0 ldff1sh \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\]
--.*: c48023e0 ldff1sh \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\]
--.*: c4842000 ldff1sh \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\]
--.*: c4842000 ldff1sh \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\]
--.*: c4842000 ldff1sh \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\]
--.*: c49f2000 ldff1sh \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\]
--.*: c49f2000 ldff1sh \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\]
--.*: c49f2000 ldff1sh \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\]
--.*: c4c02000 ldff1sh \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c4c02000 ldff1sh \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c4c02000 ldff1sh \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c4c02000 ldff1sh \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c4c02001 ldff1sh \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c4c02001 ldff1sh \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c4c02001 ldff1sh \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c4c02001 ldff1sh \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c4c0201f ldff1sh \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c4c0201f ldff1sh \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c4c0201f ldff1sh \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c4c0201f ldff1sh \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c4c02800 ldff1sh \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\]
--.*: c4c02800 ldff1sh \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\]
--.*: c4c02800 ldff1sh \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\]
--.*: c4c03c00 ldff1sh \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\]
--.*: c4c03c00 ldff1sh \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\]
--.*: c4c03c00 ldff1sh \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\]
--.*: c4c02060 ldff1sh \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\]
--.*: c4c02060 ldff1sh \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\]
--.*: c4c02060 ldff1sh \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\]
--.*: c4c023e0 ldff1sh \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\]
--.*: c4c023e0 ldff1sh \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\]
--.*: c4c023e0 ldff1sh \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\]
--.*: c4c42000 ldff1sh \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\]
--.*: c4c42000 ldff1sh \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\]
--.*: c4c42000 ldff1sh \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\]
--.*: c4df2000 ldff1sh \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\]
--.*: c4df2000 ldff1sh \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\]
--.*: c4df2000 ldff1sh \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\]
--.*: c4a02000 ldff1sh \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #1\]
--.*: c4a02000 ldff1sh \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #1\]
--.*: c4a02000 ldff1sh \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #1\]
--.*: c4a02001 ldff1sh \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #1\]
--.*: c4a02001 ldff1sh \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #1\]
--.*: c4a02001 ldff1sh \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #1\]
--.*: c4a0201f ldff1sh \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #1\]
--.*: c4a0201f ldff1sh \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #1\]
--.*: c4a0201f ldff1sh \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #1\]
--.*: c4a02800 ldff1sh \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw #1\]
--.*: c4a02800 ldff1sh \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw #1\]
--.*: c4a03c00 ldff1sh \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw #1\]
--.*: c4a03c00 ldff1sh \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw #1\]
--.*: c4a02060 ldff1sh \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw #1\]
--.*: c4a02060 ldff1sh \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw #1\]
--.*: c4a023e0 ldff1sh \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw #1\]
--.*: c4a023e0 ldff1sh \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw #1\]
--.*: c4a42000 ldff1sh \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw #1\]
--.*: c4a42000 ldff1sh \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw #1\]
--.*: c4bf2000 ldff1sh \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw #1\]
--.*: c4bf2000 ldff1sh \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw #1\]
--.*: c4e02000 ldff1sh \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #1\]
--.*: c4e02000 ldff1sh \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #1\]
--.*: c4e02000 ldff1sh \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #1\]
--.*: c4e02001 ldff1sh \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #1\]
--.*: c4e02001 ldff1sh \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #1\]
--.*: c4e02001 ldff1sh \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #1\]
--.*: c4e0201f ldff1sh \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #1\]
--.*: c4e0201f ldff1sh \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #1\]
--.*: c4e0201f ldff1sh \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #1\]
--.*: c4e02800 ldff1sh \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw #1\]
--.*: c4e02800 ldff1sh \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw #1\]
--.*: c4e03c00 ldff1sh \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw #1\]
--.*: c4e03c00 ldff1sh \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw #1\]
--.*: c4e02060 ldff1sh \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw #1\]
--.*: c4e02060 ldff1sh \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw #1\]
--.*: c4e023e0 ldff1sh \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw #1\]
--.*: c4e023e0 ldff1sh \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw #1\]
--.*: c4e42000 ldff1sh \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw #1\]
--.*: c4e42000 ldff1sh \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw #1\]
--.*: c4ff2000 ldff1sh \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw #1\]
--.*: c4ff2000 ldff1sh \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw #1\]
--.*: c4c0a000 ldff1sh \{z0\.d\}, p0/z, \[x0, z0\.d\]
--.*: c4c0a000 ldff1sh \{z0\.d\}, p0/z, \[x0, z0\.d\]
--.*: c4c0a000 ldff1sh \{z0\.d\}, p0/z, \[x0, z0\.d\]
--.*: c4c0a000 ldff1sh \{z0\.d\}, p0/z, \[x0, z0\.d\]
--.*: c4c0a001 ldff1sh \{z1\.d\}, p0/z, \[x0, z0\.d\]
--.*: c4c0a001 ldff1sh \{z1\.d\}, p0/z, \[x0, z0\.d\]
--.*: c4c0a001 ldff1sh \{z1\.d\}, p0/z, \[x0, z0\.d\]
--.*: c4c0a001 ldff1sh \{z1\.d\}, p0/z, \[x0, z0\.d\]
--.*: c4c0a01f ldff1sh \{z31\.d\}, p0/z, \[x0, z0\.d\]
--.*: c4c0a01f ldff1sh \{z31\.d\}, p0/z, \[x0, z0\.d\]
--.*: c4c0a01f ldff1sh \{z31\.d\}, p0/z, \[x0, z0\.d\]
--.*: c4c0a01f ldff1sh \{z31\.d\}, p0/z, \[x0, z0\.d\]
--.*: c4c0a800 ldff1sh \{z0\.d\}, p2/z, \[x0, z0\.d\]
--.*: c4c0a800 ldff1sh \{z0\.d\}, p2/z, \[x0, z0\.d\]
--.*: c4c0a800 ldff1sh \{z0\.d\}, p2/z, \[x0, z0\.d\]
--.*: c4c0bc00 ldff1sh \{z0\.d\}, p7/z, \[x0, z0\.d\]
--.*: c4c0bc00 ldff1sh \{z0\.d\}, p7/z, \[x0, z0\.d\]
--.*: c4c0bc00 ldff1sh \{z0\.d\}, p7/z, \[x0, z0\.d\]
--.*: c4c0a060 ldff1sh \{z0\.d\}, p0/z, \[x3, z0\.d\]
--.*: c4c0a060 ldff1sh \{z0\.d\}, p0/z, \[x3, z0\.d\]
--.*: c4c0a060 ldff1sh \{z0\.d\}, p0/z, \[x3, z0\.d\]
--.*: c4c0a3e0 ldff1sh \{z0\.d\}, p0/z, \[sp, z0\.d\]
--.*: c4c0a3e0 ldff1sh \{z0\.d\}, p0/z, \[sp, z0\.d\]
--.*: c4c0a3e0 ldff1sh \{z0\.d\}, p0/z, \[sp, z0\.d\]
--.*: c4c4a000 ldff1sh \{z0\.d\}, p0/z, \[x0, z4\.d\]
--.*: c4c4a000 ldff1sh \{z0\.d\}, p0/z, \[x0, z4\.d\]
--.*: c4c4a000 ldff1sh \{z0\.d\}, p0/z, \[x0, z4\.d\]
--.*: c4dfa000 ldff1sh \{z0\.d\}, p0/z, \[x0, z31\.d\]
--.*: c4dfa000 ldff1sh \{z0\.d\}, p0/z, \[x0, z31\.d\]
--.*: c4dfa000 ldff1sh \{z0\.d\}, p0/z, \[x0, z31\.d\]
--.*: c4e0a000 ldff1sh \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #1\]
--.*: c4e0a000 ldff1sh \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #1\]
--.*: c4e0a000 ldff1sh \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #1\]
--.*: c4e0a001 ldff1sh \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #1\]
--.*: c4e0a001 ldff1sh \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #1\]
--.*: c4e0a001 ldff1sh \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #1\]
--.*: c4e0a01f ldff1sh \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #1\]
--.*: c4e0a01f ldff1sh \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #1\]
--.*: c4e0a01f ldff1sh \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #1\]
--.*: c4e0a800 ldff1sh \{z0\.d\}, p2/z, \[x0, z0\.d, lsl #1\]
--.*: c4e0a800 ldff1sh \{z0\.d\}, p2/z, \[x0, z0\.d, lsl #1\]
--.*: c4e0bc00 ldff1sh \{z0\.d\}, p7/z, \[x0, z0\.d, lsl #1\]
--.*: c4e0bc00 ldff1sh \{z0\.d\}, p7/z, \[x0, z0\.d, lsl #1\]
--.*: c4e0a060 ldff1sh \{z0\.d\}, p0/z, \[x3, z0\.d, lsl #1\]
--.*: c4e0a060 ldff1sh \{z0\.d\}, p0/z, \[x3, z0\.d, lsl #1\]
--.*: c4e0a3e0 ldff1sh \{z0\.d\}, p0/z, \[sp, z0\.d, lsl #1\]
--.*: c4e0a3e0 ldff1sh \{z0\.d\}, p0/z, \[sp, z0\.d, lsl #1\]
--.*: c4e4a000 ldff1sh \{z0\.d\}, p0/z, \[x0, z4\.d, lsl #1\]
--.*: c4e4a000 ldff1sh \{z0\.d\}, p0/z, \[x0, z4\.d, lsl #1\]
--.*: c4ffa000 ldff1sh \{z0\.d\}, p0/z, \[x0, z31\.d, lsl #1\]
--.*: c4ffa000 ldff1sh \{z0\.d\}, p0/z, \[x0, z31\.d, lsl #1\]
--.*: 84a0a000 ldff1sh \{z0\.s\}, p0/z, \[z0\.s\]
--.*: 84a0a000 ldff1sh \{z0\.s\}, p0/z, \[z0\.s\]
--.*: 84a0a000 ldff1sh \{z0\.s\}, p0/z, \[z0\.s\]
--.*: 84a0a000 ldff1sh \{z0\.s\}, p0/z, \[z0\.s\]
--.*: 84a0a001 ldff1sh \{z1\.s\}, p0/z, \[z0\.s\]
--.*: 84a0a001 ldff1sh \{z1\.s\}, p0/z, \[z0\.s\]
--.*: 84a0a001 ldff1sh \{z1\.s\}, p0/z, \[z0\.s\]
--.*: 84a0a001 ldff1sh \{z1\.s\}, p0/z, \[z0\.s\]
--.*: 84a0a01f ldff1sh \{z31\.s\}, p0/z, \[z0\.s\]
--.*: 84a0a01f ldff1sh \{z31\.s\}, p0/z, \[z0\.s\]
--.*: 84a0a01f ldff1sh \{z31\.s\}, p0/z, \[z0\.s\]
--.*: 84a0a01f ldff1sh \{z31\.s\}, p0/z, \[z0\.s\]
--.*: 84a0a800 ldff1sh \{z0\.s\}, p2/z, \[z0\.s\]
--.*: 84a0a800 ldff1sh \{z0\.s\}, p2/z, \[z0\.s\]
--.*: 84a0a800 ldff1sh \{z0\.s\}, p2/z, \[z0\.s\]
--.*: 84a0bc00 ldff1sh \{z0\.s\}, p7/z, \[z0\.s\]
--.*: 84a0bc00 ldff1sh \{z0\.s\}, p7/z, \[z0\.s\]
--.*: 84a0bc00 ldff1sh \{z0\.s\}, p7/z, \[z0\.s\]
--.*: 84a0a060 ldff1sh \{z0\.s\}, p0/z, \[z3\.s\]
--.*: 84a0a060 ldff1sh \{z0\.s\}, p0/z, \[z3\.s\]
--.*: 84a0a060 ldff1sh \{z0\.s\}, p0/z, \[z3\.s\]
--.*: 84a0a3e0 ldff1sh \{z0\.s\}, p0/z, \[z31\.s\]
--.*: 84a0a3e0 ldff1sh \{z0\.s\}, p0/z, \[z31\.s\]
--.*: 84a0a3e0 ldff1sh \{z0\.s\}, p0/z, \[z31\.s\]
--.*: 84afa000 ldff1sh \{z0\.s\}, p0/z, \[z0\.s, #30\]
--.*: 84afa000 ldff1sh \{z0\.s\}, p0/z, \[z0\.s, #30\]
--.*: 84b0a000 ldff1sh \{z0\.s\}, p0/z, \[z0\.s, #32\]
--.*: 84b0a000 ldff1sh \{z0\.s\}, p0/z, \[z0\.s, #32\]
--.*: 84b1a000 ldff1sh \{z0\.s\}, p0/z, \[z0\.s, #34\]
--.*: 84b1a000 ldff1sh \{z0\.s\}, p0/z, \[z0\.s, #34\]
--.*: 84bfa000 ldff1sh \{z0\.s\}, p0/z, \[z0\.s, #62\]
--.*: 84bfa000 ldff1sh \{z0\.s\}, p0/z, \[z0\.s, #62\]
--.*: c4a0a000 ldff1sh \{z0\.d\}, p0/z, \[z0\.d\]
--.*: c4a0a000 ldff1sh \{z0\.d\}, p0/z, \[z0\.d\]
--.*: c4a0a000 ldff1sh \{z0\.d\}, p0/z, \[z0\.d\]
--.*: c4a0a000 ldff1sh \{z0\.d\}, p0/z, \[z0\.d\]
--.*: c4a0a001 ldff1sh \{z1\.d\}, p0/z, \[z0\.d\]
--.*: c4a0a001 ldff1sh \{z1\.d\}, p0/z, \[z0\.d\]
--.*: c4a0a001 ldff1sh \{z1\.d\}, p0/z, \[z0\.d\]
--.*: c4a0a001 ldff1sh \{z1\.d\}, p0/z, \[z0\.d\]
--.*: c4a0a01f ldff1sh \{z31\.d\}, p0/z, \[z0\.d\]
--.*: c4a0a01f ldff1sh \{z31\.d\}, p0/z, \[z0\.d\]
--.*: c4a0a01f ldff1sh \{z31\.d\}, p0/z, \[z0\.d\]
--.*: c4a0a01f ldff1sh \{z31\.d\}, p0/z, \[z0\.d\]
--.*: c4a0a800 ldff1sh \{z0\.d\}, p2/z, \[z0\.d\]
--.*: c4a0a800 ldff1sh \{z0\.d\}, p2/z, \[z0\.d\]
--.*: c4a0a800 ldff1sh \{z0\.d\}, p2/z, \[z0\.d\]
--.*: c4a0bc00 ldff1sh \{z0\.d\}, p7/z, \[z0\.d\]
--.*: c4a0bc00 ldff1sh \{z0\.d\}, p7/z, \[z0\.d\]
--.*: c4a0bc00 ldff1sh \{z0\.d\}, p7/z, \[z0\.d\]
--.*: c4a0a060 ldff1sh \{z0\.d\}, p0/z, \[z3\.d\]
--.*: c4a0a060 ldff1sh \{z0\.d\}, p0/z, \[z3\.d\]
--.*: c4a0a060 ldff1sh \{z0\.d\}, p0/z, \[z3\.d\]
--.*: c4a0a3e0 ldff1sh \{z0\.d\}, p0/z, \[z31\.d\]
--.*: c4a0a3e0 ldff1sh \{z0\.d\}, p0/z, \[z31\.d\]
--.*: c4a0a3e0 ldff1sh \{z0\.d\}, p0/z, \[z31\.d\]
--.*: c4afa000 ldff1sh \{z0\.d\}, p0/z, \[z0\.d, #30\]
--.*: c4afa000 ldff1sh \{z0\.d\}, p0/z, \[z0\.d, #30\]
--.*: c4b0a000 ldff1sh \{z0\.d\}, p0/z, \[z0\.d, #32\]
--.*: c4b0a000 ldff1sh \{z0\.d\}, p0/z, \[z0\.d, #32\]
--.*: c4b1a000 ldff1sh \{z0\.d\}, p0/z, \[z0\.d, #34\]
--.*: c4b1a000 ldff1sh \{z0\.d\}, p0/z, \[z0\.d, #34\]
--.*: c4bfa000 ldff1sh \{z0\.d\}, p0/z, \[z0\.d, #62\]
--.*: c4bfa000 ldff1sh \{z0\.d\}, p0/z, \[z0\.d, #62\]
--.*: a4806000 ldff1sw \{z0\.d\}, p0/z, \[x0, x0, lsl #2\]
--.*: a4806000 ldff1sw \{z0\.d\}, p0/z, \[x0, x0, lsl #2\]
--.*: a4806000 ldff1sw \{z0\.d\}, p0/z, \[x0, x0, lsl #2\]
--.*: a4806001 ldff1sw \{z1\.d\}, p0/z, \[x0, x0, lsl #2\]
--.*: a4806001 ldff1sw \{z1\.d\}, p0/z, \[x0, x0, lsl #2\]
--.*: a4806001 ldff1sw \{z1\.d\}, p0/z, \[x0, x0, lsl #2\]
--.*: a480601f ldff1sw \{z31\.d\}, p0/z, \[x0, x0, lsl #2\]
--.*: a480601f ldff1sw \{z31\.d\}, p0/z, \[x0, x0, lsl #2\]
--.*: a480601f ldff1sw \{z31\.d\}, p0/z, \[x0, x0, lsl #2\]
--.*: a4806800 ldff1sw \{z0\.d\}, p2/z, \[x0, x0, lsl #2\]
--.*: a4806800 ldff1sw \{z0\.d\}, p2/z, \[x0, x0, lsl #2\]
--.*: a4807c00 ldff1sw \{z0\.d\}, p7/z, \[x0, x0, lsl #2\]
--.*: a4807c00 ldff1sw \{z0\.d\}, p7/z, \[x0, x0, lsl #2\]
--.*: a4806060 ldff1sw \{z0\.d\}, p0/z, \[x3, x0, lsl #2\]
--.*: a4806060 ldff1sw \{z0\.d\}, p0/z, \[x3, x0, lsl #2\]
--.*: a48063e0 ldff1sw \{z0\.d\}, p0/z, \[sp, x0, lsl #2\]
--.*: a48063e0 ldff1sw \{z0\.d\}, p0/z, \[sp, x0, lsl #2\]
--.*: a4846000 ldff1sw \{z0\.d\}, p0/z, \[x0, x4, lsl #2\]
--.*: a4846000 ldff1sw \{z0\.d\}, p0/z, \[x0, x4, lsl #2\]
--.*: a49f6000 ldff1sw \{z0\.d\}, p0/z, \[x0, xzr, lsl #2\]
--.*: a49f6000 ldff1sw \{z0\.d\}, p0/z, \[x0, xzr, lsl #2\]
--.*: c5002000 ldff1sw \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c5002000 ldff1sw \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c5002000 ldff1sw \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c5002000 ldff1sw \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c5002001 ldff1sw \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c5002001 ldff1sw \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c5002001 ldff1sw \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c5002001 ldff1sw \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c500201f ldff1sw \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c500201f ldff1sw \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c500201f ldff1sw \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c500201f ldff1sw \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c5002800 ldff1sw \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\]
--.*: c5002800 ldff1sw \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\]
--.*: c5002800 ldff1sw \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\]
--.*: c5003c00 ldff1sw \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\]
--.*: c5003c00 ldff1sw \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\]
--.*: c5003c00 ldff1sw \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\]
--.*: c5002060 ldff1sw \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\]
--.*: c5002060 ldff1sw \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\]
--.*: c5002060 ldff1sw \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\]
--.*: c50023e0 ldff1sw \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\]
--.*: c50023e0 ldff1sw \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\]
--.*: c50023e0 ldff1sw \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\]
--.*: c5042000 ldff1sw \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\]
--.*: c5042000 ldff1sw \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\]
--.*: c5042000 ldff1sw \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\]
--.*: c51f2000 ldff1sw \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\]
--.*: c51f2000 ldff1sw \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\]
--.*: c51f2000 ldff1sw \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\]
--.*: c5402000 ldff1sw \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c5402000 ldff1sw \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c5402000 ldff1sw \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c5402000 ldff1sw \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c5402001 ldff1sw \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c5402001 ldff1sw \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c5402001 ldff1sw \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c5402001 ldff1sw \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c540201f ldff1sw \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c540201f ldff1sw \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c540201f ldff1sw \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c540201f ldff1sw \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c5402800 ldff1sw \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\]
--.*: c5402800 ldff1sw \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\]
--.*: c5402800 ldff1sw \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\]
--.*: c5403c00 ldff1sw \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\]
--.*: c5403c00 ldff1sw \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\]
--.*: c5403c00 ldff1sw \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\]
--.*: c5402060 ldff1sw \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\]
--.*: c5402060 ldff1sw \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\]
--.*: c5402060 ldff1sw \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\]
--.*: c54023e0 ldff1sw \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\]
--.*: c54023e0 ldff1sw \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\]
--.*: c54023e0 ldff1sw \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\]
--.*: c5442000 ldff1sw \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\]
--.*: c5442000 ldff1sw \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\]
--.*: c5442000 ldff1sw \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\]
--.*: c55f2000 ldff1sw \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\]
--.*: c55f2000 ldff1sw \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\]
--.*: c55f2000 ldff1sw \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\]
--.*: c5202000 ldff1sw \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #2\]
--.*: c5202000 ldff1sw \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #2\]
--.*: c5202000 ldff1sw \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #2\]
--.*: c5202001 ldff1sw \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #2\]
--.*: c5202001 ldff1sw \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #2\]
--.*: c5202001 ldff1sw \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #2\]
--.*: c520201f ldff1sw \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #2\]
--.*: c520201f ldff1sw \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #2\]
--.*: c520201f ldff1sw \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #2\]
--.*: c5202800 ldff1sw \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw #2\]
--.*: c5202800 ldff1sw \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw #2\]
--.*: c5203c00 ldff1sw \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw #2\]
--.*: c5203c00 ldff1sw \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw #2\]
--.*: c5202060 ldff1sw \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw #2\]
--.*: c5202060 ldff1sw \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw #2\]
--.*: c52023e0 ldff1sw \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw #2\]
--.*: c52023e0 ldff1sw \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw #2\]
--.*: c5242000 ldff1sw \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw #2\]
--.*: c5242000 ldff1sw \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw #2\]
--.*: c53f2000 ldff1sw \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw #2\]
--.*: c53f2000 ldff1sw \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw #2\]
--.*: c5602000 ldff1sw \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #2\]
--.*: c5602000 ldff1sw \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #2\]
--.*: c5602000 ldff1sw \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #2\]
--.*: c5602001 ldff1sw \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #2\]
--.*: c5602001 ldff1sw \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #2\]
--.*: c5602001 ldff1sw \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #2\]
--.*: c560201f ldff1sw \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #2\]
--.*: c560201f ldff1sw \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #2\]
--.*: c560201f ldff1sw \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #2\]
--.*: c5602800 ldff1sw \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw #2\]
--.*: c5602800 ldff1sw \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw #2\]
--.*: c5603c00 ldff1sw \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw #2\]
--.*: c5603c00 ldff1sw \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw #2\]
--.*: c5602060 ldff1sw \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw #2\]
--.*: c5602060 ldff1sw \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw #2\]
--.*: c56023e0 ldff1sw \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw #2\]
--.*: c56023e0 ldff1sw \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw #2\]
--.*: c5642000 ldff1sw \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw #2\]
--.*: c5642000 ldff1sw \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw #2\]
--.*: c57f2000 ldff1sw \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw #2\]
--.*: c57f2000 ldff1sw \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw #2\]
--.*: c540a000 ldff1sw \{z0\.d\}, p0/z, \[x0, z0\.d\]
--.*: c540a000 ldff1sw \{z0\.d\}, p0/z, \[x0, z0\.d\]
--.*: c540a000 ldff1sw \{z0\.d\}, p0/z, \[x0, z0\.d\]
--.*: c540a000 ldff1sw \{z0\.d\}, p0/z, \[x0, z0\.d\]
--.*: c540a001 ldff1sw \{z1\.d\}, p0/z, \[x0, z0\.d\]
--.*: c540a001 ldff1sw \{z1\.d\}, p0/z, \[x0, z0\.d\]
--.*: c540a001 ldff1sw \{z1\.d\}, p0/z, \[x0, z0\.d\]
--.*: c540a001 ldff1sw \{z1\.d\}, p0/z, \[x0, z0\.d\]
--.*: c540a01f ldff1sw \{z31\.d\}, p0/z, \[x0, z0\.d\]
--.*: c540a01f ldff1sw \{z31\.d\}, p0/z, \[x0, z0\.d\]
--.*: c540a01f ldff1sw \{z31\.d\}, p0/z, \[x0, z0\.d\]
--.*: c540a01f ldff1sw \{z31\.d\}, p0/z, \[x0, z0\.d\]
--.*: c540a800 ldff1sw \{z0\.d\}, p2/z, \[x0, z0\.d\]
--.*: c540a800 ldff1sw \{z0\.d\}, p2/z, \[x0, z0\.d\]
--.*: c540a800 ldff1sw \{z0\.d\}, p2/z, \[x0, z0\.d\]
--.*: c540bc00 ldff1sw \{z0\.d\}, p7/z, \[x0, z0\.d\]
--.*: c540bc00 ldff1sw \{z0\.d\}, p7/z, \[x0, z0\.d\]
--.*: c540bc00 ldff1sw \{z0\.d\}, p7/z, \[x0, z0\.d\]
--.*: c540a060 ldff1sw \{z0\.d\}, p0/z, \[x3, z0\.d\]
--.*: c540a060 ldff1sw \{z0\.d\}, p0/z, \[x3, z0\.d\]
--.*: c540a060 ldff1sw \{z0\.d\}, p0/z, \[x3, z0\.d\]
--.*: c540a3e0 ldff1sw \{z0\.d\}, p0/z, \[sp, z0\.d\]
--.*: c540a3e0 ldff1sw \{z0\.d\}, p0/z, \[sp, z0\.d\]
--.*: c540a3e0 ldff1sw \{z0\.d\}, p0/z, \[sp, z0\.d\]
--.*: c544a000 ldff1sw \{z0\.d\}, p0/z, \[x0, z4\.d\]
--.*: c544a000 ldff1sw \{z0\.d\}, p0/z, \[x0, z4\.d\]
--.*: c544a000 ldff1sw \{z0\.d\}, p0/z, \[x0, z4\.d\]
--.*: c55fa000 ldff1sw \{z0\.d\}, p0/z, \[x0, z31\.d\]
--.*: c55fa000 ldff1sw \{z0\.d\}, p0/z, \[x0, z31\.d\]
--.*: c55fa000 ldff1sw \{z0\.d\}, p0/z, \[x0, z31\.d\]
--.*: c560a000 ldff1sw \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #2\]
--.*: c560a000 ldff1sw \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #2\]
--.*: c560a000 ldff1sw \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #2\]
--.*: c560a001 ldff1sw \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #2\]
--.*: c560a001 ldff1sw \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #2\]
--.*: c560a001 ldff1sw \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #2\]
--.*: c560a01f ldff1sw \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #2\]
--.*: c560a01f ldff1sw \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #2\]
--.*: c560a01f ldff1sw \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #2\]
--.*: c560a800 ldff1sw \{z0\.d\}, p2/z, \[x0, z0\.d, lsl #2\]
--.*: c560a800 ldff1sw \{z0\.d\}, p2/z, \[x0, z0\.d, lsl #2\]
--.*: c560bc00 ldff1sw \{z0\.d\}, p7/z, \[x0, z0\.d, lsl #2\]
--.*: c560bc00 ldff1sw \{z0\.d\}, p7/z, \[x0, z0\.d, lsl #2\]
--.*: c560a060 ldff1sw \{z0\.d\}, p0/z, \[x3, z0\.d, lsl #2\]
--.*: c560a060 ldff1sw \{z0\.d\}, p0/z, \[x3, z0\.d, lsl #2\]
--.*: c560a3e0 ldff1sw \{z0\.d\}, p0/z, \[sp, z0\.d, lsl #2\]
--.*: c560a3e0 ldff1sw \{z0\.d\}, p0/z, \[sp, z0\.d, lsl #2\]
--.*: c564a000 ldff1sw \{z0\.d\}, p0/z, \[x0, z4\.d, lsl #2\]
--.*: c564a000 ldff1sw \{z0\.d\}, p0/z, \[x0, z4\.d, lsl #2\]
--.*: c57fa000 ldff1sw \{z0\.d\}, p0/z, \[x0, z31\.d, lsl #2\]
--.*: c57fa000 ldff1sw \{z0\.d\}, p0/z, \[x0, z31\.d, lsl #2\]
--.*: c520a000 ldff1sw \{z0\.d\}, p0/z, \[z0\.d\]
--.*: c520a000 ldff1sw \{z0\.d\}, p0/z, \[z0\.d\]
--.*: c520a000 ldff1sw \{z0\.d\}, p0/z, \[z0\.d\]
--.*: c520a000 ldff1sw \{z0\.d\}, p0/z, \[z0\.d\]
--.*: c520a001 ldff1sw \{z1\.d\}, p0/z, \[z0\.d\]
--.*: c520a001 ldff1sw \{z1\.d\}, p0/z, \[z0\.d\]
--.*: c520a001 ldff1sw \{z1\.d\}, p0/z, \[z0\.d\]
--.*: c520a001 ldff1sw \{z1\.d\}, p0/z, \[z0\.d\]
--.*: c520a01f ldff1sw \{z31\.d\}, p0/z, \[z0\.d\]
--.*: c520a01f ldff1sw \{z31\.d\}, p0/z, \[z0\.d\]
--.*: c520a01f ldff1sw \{z31\.d\}, p0/z, \[z0\.d\]
--.*: c520a01f ldff1sw \{z31\.d\}, p0/z, \[z0\.d\]
--.*: c520a800 ldff1sw \{z0\.d\}, p2/z, \[z0\.d\]
--.*: c520a800 ldff1sw \{z0\.d\}, p2/z, \[z0\.d\]
--.*: c520a800 ldff1sw \{z0\.d\}, p2/z, \[z0\.d\]
--.*: c520bc00 ldff1sw \{z0\.d\}, p7/z, \[z0\.d\]
--.*: c520bc00 ldff1sw \{z0\.d\}, p7/z, \[z0\.d\]
--.*: c520bc00 ldff1sw \{z0\.d\}, p7/z, \[z0\.d\]
--.*: c520a060 ldff1sw \{z0\.d\}, p0/z, \[z3\.d\]
--.*: c520a060 ldff1sw \{z0\.d\}, p0/z, \[z3\.d\]
--.*: c520a060 ldff1sw \{z0\.d\}, p0/z, \[z3\.d\]
--.*: c520a3e0 ldff1sw \{z0\.d\}, p0/z, \[z31\.d\]
--.*: c520a3e0 ldff1sw \{z0\.d\}, p0/z, \[z31\.d\]
--.*: c520a3e0 ldff1sw \{z0\.d\}, p0/z, \[z31\.d\]
--.*: c52fa000 ldff1sw \{z0\.d\}, p0/z, \[z0\.d, #60\]
--.*: c52fa000 ldff1sw \{z0\.d\}, p0/z, \[z0\.d, #60\]
--.*: c530a000 ldff1sw \{z0\.d\}, p0/z, \[z0\.d, #64\]
--.*: c530a000 ldff1sw \{z0\.d\}, p0/z, \[z0\.d, #64\]
--.*: c531a000 ldff1sw \{z0\.d\}, p0/z, \[z0\.d, #68\]
--.*: c531a000 ldff1sw \{z0\.d\}, p0/z, \[z0\.d, #68\]
--.*: c53fa000 ldff1sw \{z0\.d\}, p0/z, \[z0\.d, #124\]
--.*: c53fa000 ldff1sw \{z0\.d\}, p0/z, \[z0\.d, #124\]
--.*: 85006000 ldff1w \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 85006000 ldff1w \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 85006000 ldff1w \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 85006000 ldff1w \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 85006001 ldff1w \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 85006001 ldff1w \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 85006001 ldff1w \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 85006001 ldff1w \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 8500601f ldff1w \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 8500601f ldff1w \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 8500601f ldff1w \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 8500601f ldff1w \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw\]
--.*: 85006800 ldff1w \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\]
--.*: 85006800 ldff1w \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\]
--.*: 85006800 ldff1w \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw\]
--.*: 85007c00 ldff1w \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\]
--.*: 85007c00 ldff1w \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\]
--.*: 85007c00 ldff1w \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw\]
--.*: 85006060 ldff1w \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\]
--.*: 85006060 ldff1w \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\]
--.*: 85006060 ldff1w \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw\]
--.*: 850063e0 ldff1w \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\]
--.*: 850063e0 ldff1w \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\]
--.*: 850063e0 ldff1w \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw\]
--.*: 85046000 ldff1w \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\]
--.*: 85046000 ldff1w \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\]
--.*: 85046000 ldff1w \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw\]
--.*: 851f6000 ldff1w \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\]
--.*: 851f6000 ldff1w \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\]
--.*: 851f6000 ldff1w \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw\]
--.*: 85406000 ldff1w \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 85406000 ldff1w \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 85406000 ldff1w \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 85406000 ldff1w \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 85406001 ldff1w \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 85406001 ldff1w \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 85406001 ldff1w \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 85406001 ldff1w \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 8540601f ldff1w \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 8540601f ldff1w \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 8540601f ldff1w \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 8540601f ldff1w \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw\]
--.*: 85406800 ldff1w \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\]
--.*: 85406800 ldff1w \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\]
--.*: 85406800 ldff1w \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw\]
--.*: 85407c00 ldff1w \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\]
--.*: 85407c00 ldff1w \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\]
--.*: 85407c00 ldff1w \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw\]
--.*: 85406060 ldff1w \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\]
--.*: 85406060 ldff1w \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\]
--.*: 85406060 ldff1w \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw\]
--.*: 854063e0 ldff1w \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\]
--.*: 854063e0 ldff1w \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\]
--.*: 854063e0 ldff1w \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw\]
--.*: 85446000 ldff1w \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\]
--.*: 85446000 ldff1w \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\]
--.*: 85446000 ldff1w \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw\]
--.*: 855f6000 ldff1w \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\]
--.*: 855f6000 ldff1w \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\]
--.*: 855f6000 ldff1w \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw\]
--.*: 85206000 ldff1w \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw #2\]
--.*: 85206000 ldff1w \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw #2\]
--.*: 85206000 ldff1w \{z0\.s\}, p0/z, \[x0, z0\.s, uxtw #2\]
--.*: 85206001 ldff1w \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw #2\]
--.*: 85206001 ldff1w \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw #2\]
--.*: 85206001 ldff1w \{z1\.s\}, p0/z, \[x0, z0\.s, uxtw #2\]
--.*: 8520601f ldff1w \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw #2\]
--.*: 8520601f ldff1w \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw #2\]
--.*: 8520601f ldff1w \{z31\.s\}, p0/z, \[x0, z0\.s, uxtw #2\]
--.*: 85206800 ldff1w \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw #2\]
--.*: 85206800 ldff1w \{z0\.s\}, p2/z, \[x0, z0\.s, uxtw #2\]
--.*: 85207c00 ldff1w \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw #2\]
--.*: 85207c00 ldff1w \{z0\.s\}, p7/z, \[x0, z0\.s, uxtw #2\]
--.*: 85206060 ldff1w \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw #2\]
--.*: 85206060 ldff1w \{z0\.s\}, p0/z, \[x3, z0\.s, uxtw #2\]
--.*: 852063e0 ldff1w \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw #2\]
--.*: 852063e0 ldff1w \{z0\.s\}, p0/z, \[sp, z0\.s, uxtw #2\]
--.*: 85246000 ldff1w \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw #2\]
--.*: 85246000 ldff1w \{z0\.s\}, p0/z, \[x0, z4\.s, uxtw #2\]
--.*: 853f6000 ldff1w \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw #2\]
--.*: 853f6000 ldff1w \{z0\.s\}, p0/z, \[x0, z31\.s, uxtw #2\]
--.*: 85606000 ldff1w \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw #2\]
--.*: 85606000 ldff1w \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw #2\]
--.*: 85606000 ldff1w \{z0\.s\}, p0/z, \[x0, z0\.s, sxtw #2\]
--.*: 85606001 ldff1w \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw #2\]
--.*: 85606001 ldff1w \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw #2\]
--.*: 85606001 ldff1w \{z1\.s\}, p0/z, \[x0, z0\.s, sxtw #2\]
--.*: 8560601f ldff1w \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw #2\]
--.*: 8560601f ldff1w \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw #2\]
--.*: 8560601f ldff1w \{z31\.s\}, p0/z, \[x0, z0\.s, sxtw #2\]
--.*: 85606800 ldff1w \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw #2\]
--.*: 85606800 ldff1w \{z0\.s\}, p2/z, \[x0, z0\.s, sxtw #2\]
--.*: 85607c00 ldff1w \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw #2\]
--.*: 85607c00 ldff1w \{z0\.s\}, p7/z, \[x0, z0\.s, sxtw #2\]
--.*: 85606060 ldff1w \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw #2\]
--.*: 85606060 ldff1w \{z0\.s\}, p0/z, \[x3, z0\.s, sxtw #2\]
--.*: 856063e0 ldff1w \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw #2\]
--.*: 856063e0 ldff1w \{z0\.s\}, p0/z, \[sp, z0\.s, sxtw #2\]
--.*: 85646000 ldff1w \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw #2\]
--.*: 85646000 ldff1w \{z0\.s\}, p0/z, \[x0, z4\.s, sxtw #2\]
--.*: 857f6000 ldff1w \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw #2\]
--.*: 857f6000 ldff1w \{z0\.s\}, p0/z, \[x0, z31\.s, sxtw #2\]
--.*: a5406000 ldff1w \{z0\.s\}, p0/z, \[x0, x0, lsl #2\]
--.*: a5406000 ldff1w \{z0\.s\}, p0/z, \[x0, x0, lsl #2\]
--.*: a5406000 ldff1w \{z0\.s\}, p0/z, \[x0, x0, lsl #2\]
--.*: a5406001 ldff1w \{z1\.s\}, p0/z, \[x0, x0, lsl #2\]
--.*: a5406001 ldff1w \{z1\.s\}, p0/z, \[x0, x0, lsl #2\]
--.*: a5406001 ldff1w \{z1\.s\}, p0/z, \[x0, x0, lsl #2\]
--.*: a540601f ldff1w \{z31\.s\}, p0/z, \[x0, x0, lsl #2\]
--.*: a540601f ldff1w \{z31\.s\}, p0/z, \[x0, x0, lsl #2\]
--.*: a540601f ldff1w \{z31\.s\}, p0/z, \[x0, x0, lsl #2\]
--.*: a5406800 ldff1w \{z0\.s\}, p2/z, \[x0, x0, lsl #2\]
--.*: a5406800 ldff1w \{z0\.s\}, p2/z, \[x0, x0, lsl #2\]
--.*: a5407c00 ldff1w \{z0\.s\}, p7/z, \[x0, x0, lsl #2\]
--.*: a5407c00 ldff1w \{z0\.s\}, p7/z, \[x0, x0, lsl #2\]
--.*: a5406060 ldff1w \{z0\.s\}, p0/z, \[x3, x0, lsl #2\]
--.*: a5406060 ldff1w \{z0\.s\}, p0/z, \[x3, x0, lsl #2\]
--.*: a54063e0 ldff1w \{z0\.s\}, p0/z, \[sp, x0, lsl #2\]
--.*: a54063e0 ldff1w \{z0\.s\}, p0/z, \[sp, x0, lsl #2\]
--.*: a5446000 ldff1w \{z0\.s\}, p0/z, \[x0, x4, lsl #2\]
--.*: a5446000 ldff1w \{z0\.s\}, p0/z, \[x0, x4, lsl #2\]
--.*: a55f6000 ldff1w \{z0\.s\}, p0/z, \[x0, xzr, lsl #2\]
--.*: a55f6000 ldff1w \{z0\.s\}, p0/z, \[x0, xzr, lsl #2\]
--.*: a5606000 ldff1w \{z0\.d\}, p0/z, \[x0, x0, lsl #2\]
--.*: a5606000 ldff1w \{z0\.d\}, p0/z, \[x0, x0, lsl #2\]
--.*: a5606000 ldff1w \{z0\.d\}, p0/z, \[x0, x0, lsl #2\]
--.*: a5606001 ldff1w \{z1\.d\}, p0/z, \[x0, x0, lsl #2\]
--.*: a5606001 ldff1w \{z1\.d\}, p0/z, \[x0, x0, lsl #2\]
--.*: a5606001 ldff1w \{z1\.d\}, p0/z, \[x0, x0, lsl #2\]
--.*: a560601f ldff1w \{z31\.d\}, p0/z, \[x0, x0, lsl #2\]
--.*: a560601f ldff1w \{z31\.d\}, p0/z, \[x0, x0, lsl #2\]
--.*: a560601f ldff1w \{z31\.d\}, p0/z, \[x0, x0, lsl #2\]
--.*: a5606800 ldff1w \{z0\.d\}, p2/z, \[x0, x0, lsl #2\]
--.*: a5606800 ldff1w \{z0\.d\}, p2/z, \[x0, x0, lsl #2\]
--.*: a5607c00 ldff1w \{z0\.d\}, p7/z, \[x0, x0, lsl #2\]
--.*: a5607c00 ldff1w \{z0\.d\}, p7/z, \[x0, x0, lsl #2\]
--.*: a5606060 ldff1w \{z0\.d\}, p0/z, \[x3, x0, lsl #2\]
--.*: a5606060 ldff1w \{z0\.d\}, p0/z, \[x3, x0, lsl #2\]
--.*: a56063e0 ldff1w \{z0\.d\}, p0/z, \[sp, x0, lsl #2\]
--.*: a56063e0 ldff1w \{z0\.d\}, p0/z, \[sp, x0, lsl #2\]
--.*: a5646000 ldff1w \{z0\.d\}, p0/z, \[x0, x4, lsl #2\]
--.*: a5646000 ldff1w \{z0\.d\}, p0/z, \[x0, x4, lsl #2\]
--.*: a57f6000 ldff1w \{z0\.d\}, p0/z, \[x0, xzr, lsl #2\]
--.*: a57f6000 ldff1w \{z0\.d\}, p0/z, \[x0, xzr, lsl #2\]
--.*: c5006000 ldff1w \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c5006000 ldff1w \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c5006000 ldff1w \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c5006000 ldff1w \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c5006001 ldff1w \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c5006001 ldff1w \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c5006001 ldff1w \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c5006001 ldff1w \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c500601f ldff1w \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c500601f ldff1w \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c500601f ldff1w \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c500601f ldff1w \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw\]
--.*: c5006800 ldff1w \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\]
--.*: c5006800 ldff1w \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\]
--.*: c5006800 ldff1w \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw\]
--.*: c5007c00 ldff1w \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\]
--.*: c5007c00 ldff1w \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\]
--.*: c5007c00 ldff1w \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw\]
--.*: c5006060 ldff1w \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\]
--.*: c5006060 ldff1w \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\]
--.*: c5006060 ldff1w \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw\]
--.*: c50063e0 ldff1w \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\]
--.*: c50063e0 ldff1w \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\]
--.*: c50063e0 ldff1w \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw\]
--.*: c5046000 ldff1w \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\]
--.*: c5046000 ldff1w \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\]
--.*: c5046000 ldff1w \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw\]
--.*: c51f6000 ldff1w \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\]
--.*: c51f6000 ldff1w \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\]
--.*: c51f6000 ldff1w \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw\]
--.*: c5406000 ldff1w \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c5406000 ldff1w \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c5406000 ldff1w \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c5406000 ldff1w \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c5406001 ldff1w \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c5406001 ldff1w \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c5406001 ldff1w \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c5406001 ldff1w \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c540601f ldff1w \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c540601f ldff1w \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c540601f ldff1w \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c540601f ldff1w \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw\]
--.*: c5406800 ldff1w \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\]
--.*: c5406800 ldff1w \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\]
--.*: c5406800 ldff1w \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw\]
--.*: c5407c00 ldff1w \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\]
--.*: c5407c00 ldff1w \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\]
--.*: c5407c00 ldff1w \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw\]
--.*: c5406060 ldff1w \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\]
--.*: c5406060 ldff1w \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\]
--.*: c5406060 ldff1w \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw\]
--.*: c54063e0 ldff1w \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\]
--.*: c54063e0 ldff1w \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\]
--.*: c54063e0 ldff1w \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw\]
--.*: c5446000 ldff1w \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\]
--.*: c5446000 ldff1w \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\]
--.*: c5446000 ldff1w \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw\]
--.*: c55f6000 ldff1w \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\]
--.*: c55f6000 ldff1w \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\]
--.*: c55f6000 ldff1w \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw\]
--.*: c5206000 ldff1w \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #2\]
--.*: c5206000 ldff1w \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #2\]
--.*: c5206000 ldff1w \{z0\.d\}, p0/z, \[x0, z0\.d, uxtw #2\]
--.*: c5206001 ldff1w \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #2\]
--.*: c5206001 ldff1w \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #2\]
--.*: c5206001 ldff1w \{z1\.d\}, p0/z, \[x0, z0\.d, uxtw #2\]
--.*: c520601f ldff1w \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #2\]
--.*: c520601f ldff1w \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #2\]
--.*: c520601f ldff1w \{z31\.d\}, p0/z, \[x0, z0\.d, uxtw #2\]
--.*: c5206800 ldff1w \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw #2\]
--.*: c5206800 ldff1w \{z0\.d\}, p2/z, \[x0, z0\.d, uxtw #2\]
--.*: c5207c00 ldff1w \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw #2\]
--.*: c5207c00 ldff1w \{z0\.d\}, p7/z, \[x0, z0\.d, uxtw #2\]
--.*: c5206060 ldff1w \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw #2\]
--.*: c5206060 ldff1w \{z0\.d\}, p0/z, \[x3, z0\.d, uxtw #2\]
--.*: c52063e0 ldff1w \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw #2\]
--.*: c52063e0 ldff1w \{z0\.d\}, p0/z, \[sp, z0\.d, uxtw #2\]
--.*: c5246000 ldff1w \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw #2\]
--.*: c5246000 ldff1w \{z0\.d\}, p0/z, \[x0, z4\.d, uxtw #2\]
--.*: c53f6000 ldff1w \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw #2\]
--.*: c53f6000 ldff1w \{z0\.d\}, p0/z, \[x0, z31\.d, uxtw #2\]
--.*: c5606000 ldff1w \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #2\]
--.*: c5606000 ldff1w \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #2\]
--.*: c5606000 ldff1w \{z0\.d\}, p0/z, \[x0, z0\.d, sxtw #2\]
--.*: c5606001 ldff1w \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #2\]
--.*: c5606001 ldff1w \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #2\]
--.*: c5606001 ldff1w \{z1\.d\}, p0/z, \[x0, z0\.d, sxtw #2\]
--.*: c560601f ldff1w \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #2\]
--.*: c560601f ldff1w \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #2\]
--.*: c560601f ldff1w \{z31\.d\}, p0/z, \[x0, z0\.d, sxtw #2\]
--.*: c5606800 ldff1w \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw #2\]
--.*: c5606800 ldff1w \{z0\.d\}, p2/z, \[x0, z0\.d, sxtw #2\]
--.*: c5607c00 ldff1w \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw #2\]
--.*: c5607c00 ldff1w \{z0\.d\}, p7/z, \[x0, z0\.d, sxtw #2\]
--.*: c5606060 ldff1w \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw #2\]
--.*: c5606060 ldff1w \{z0\.d\}, p0/z, \[x3, z0\.d, sxtw #2\]
--.*: c56063e0 ldff1w \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw #2\]
--.*: c56063e0 ldff1w \{z0\.d\}, p0/z, \[sp, z0\.d, sxtw #2\]
--.*: c5646000 ldff1w \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw #2\]
--.*: c5646000 ldff1w \{z0\.d\}, p0/z, \[x0, z4\.d, sxtw #2\]
--.*: c57f6000 ldff1w \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw #2\]
--.*: c57f6000 ldff1w \{z0\.d\}, p0/z, \[x0, z31\.d, sxtw #2\]
--.*: c540e000 ldff1w \{z0\.d\}, p0/z, \[x0, z0\.d\]
--.*: c540e000 ldff1w \{z0\.d\}, p0/z, \[x0, z0\.d\]
--.*: c540e000 ldff1w \{z0\.d\}, p0/z, \[x0, z0\.d\]
--.*: c540e000 ldff1w \{z0\.d\}, p0/z, \[x0, z0\.d\]
--.*: c540e001 ldff1w \{z1\.d\}, p0/z, \[x0, z0\.d\]
--.*: c540e001 ldff1w \{z1\.d\}, p0/z, \[x0, z0\.d\]
--.*: c540e001 ldff1w \{z1\.d\}, p0/z, \[x0, z0\.d\]
--.*: c540e001 ldff1w \{z1\.d\}, p0/z, \[x0, z0\.d\]
--.*: c540e01f ldff1w \{z31\.d\}, p0/z, \[x0, z0\.d\]
--.*: c540e01f ldff1w \{z31\.d\}, p0/z, \[x0, z0\.d\]
--.*: c540e01f ldff1w \{z31\.d\}, p0/z, \[x0, z0\.d\]
--.*: c540e01f ldff1w \{z31\.d\}, p0/z, \[x0, z0\.d\]
--.*: c540e800 ldff1w \{z0\.d\}, p2/z, \[x0, z0\.d\]
--.*: c540e800 ldff1w \{z0\.d\}, p2/z, \[x0, z0\.d\]
--.*: c540e800 ldff1w \{z0\.d\}, p2/z, \[x0, z0\.d\]
--.*: c540fc00 ldff1w \{z0\.d\}, p7/z, \[x0, z0\.d\]
--.*: c540fc00 ldff1w \{z0\.d\}, p7/z, \[x0, z0\.d\]
--.*: c540fc00 ldff1w \{z0\.d\}, p7/z, \[x0, z0\.d\]
--.*: c540e060 ldff1w \{z0\.d\}, p0/z, \[x3, z0\.d\]
--.*: c540e060 ldff1w \{z0\.d\}, p0/z, \[x3, z0\.d\]
--.*: c540e060 ldff1w \{z0\.d\}, p0/z, \[x3, z0\.d\]
--.*: c540e3e0 ldff1w \{z0\.d\}, p0/z, \[sp, z0\.d\]
--.*: c540e3e0 ldff1w \{z0\.d\}, p0/z, \[sp, z0\.d\]
--.*: c540e3e0 ldff1w \{z0\.d\}, p0/z, \[sp, z0\.d\]
--.*: c544e000 ldff1w \{z0\.d\}, p0/z, \[x0, z4\.d\]
--.*: c544e000 ldff1w \{z0\.d\}, p0/z, \[x0, z4\.d\]
--.*: c544e000 ldff1w \{z0\.d\}, p0/z, \[x0, z4\.d\]
--.*: c55fe000 ldff1w \{z0\.d\}, p0/z, \[x0, z31\.d\]
--.*: c55fe000 ldff1w \{z0\.d\}, p0/z, \[x0, z31\.d\]
--.*: c55fe000 ldff1w \{z0\.d\}, p0/z, \[x0, z31\.d\]
--.*: c560e000 ldff1w \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #2\]
--.*: c560e000 ldff1w \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #2\]
--.*: c560e000 ldff1w \{z0\.d\}, p0/z, \[x0, z0\.d, lsl #2\]
--.*: c560e001 ldff1w \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #2\]
--.*: c560e001 ldff1w \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #2\]
--.*: c560e001 ldff1w \{z1\.d\}, p0/z, \[x0, z0\.d, lsl #2\]
--.*: c560e01f ldff1w \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #2\]
--.*: c560e01f ldff1w \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #2\]
--.*: c560e01f ldff1w \{z31\.d\}, p0/z, \[x0, z0\.d, lsl #2\]
--.*: c560e800 ldff1w \{z0\.d\}, p2/z, \[x0, z0\.d, lsl #2\]
--.*: c560e800 ldff1w \{z0\.d\}, p2/z, \[x0, z0\.d, lsl #2\]
--.*: c560fc00 ldff1w \{z0\.d\}, p7/z, \[x0, z0\.d, lsl #2\]
--.*: c560fc00 ldff1w \{z0\.d\}, p7/z, \[x0, z0\.d, lsl #2\]
--.*: c560e060 ldff1w \{z0\.d\}, p0/z, \[x3, z0\.d, lsl #2\]
--.*: c560e060 ldff1w \{z0\.d\}, p0/z, \[x3, z0\.d, lsl #2\]
--.*: c560e3e0 ldff1w \{z0\.d\}, p0/z, \[sp, z0\.d, lsl #2\]
--.*: c560e3e0 ldff1w \{z0\.d\}, p0/z, \[sp, z0\.d, lsl #2\]
--.*: c564e000 ldff1w \{z0\.d\}, p0/z, \[x0, z4\.d, lsl #2\]
--.*: c564e000 ldff1w \{z0\.d\}, p0/z, \[x0, z4\.d, lsl #2\]
--.*: c57fe000 ldff1w \{z0\.d\}, p0/z, \[x0, z31\.d, lsl #2\]
--.*: c57fe000 ldff1w \{z0\.d\}, p0/z, \[x0, z31\.d, lsl #2\]
--.*: 8520e000 ldff1w \{z0\.s\}, p0/z, \[z0\.s\]
--.*: 8520e000 ldff1w \{z0\.s\}, p0/z, \[z0\.s\]
--.*: 8520e000 ldff1w \{z0\.s\}, p0/z, \[z0\.s\]
--.*: 8520e000 ldff1w \{z0\.s\}, p0/z, \[z0\.s\]
--.*: 8520e001 ldff1w \{z1\.s\}, p0/z, \[z0\.s\]
--.*: 8520e001 ldff1w \{z1\.s\}, p0/z, \[z0\.s\]
--.*: 8520e001 ldff1w \{z1\.s\}, p0/z, \[z0\.s\]
--.*: 8520e001 ldff1w \{z1\.s\}, p0/z, \[z0\.s\]
--.*: 8520e01f ldff1w \{z31\.s\}, p0/z, \[z0\.s\]
--.*: 8520e01f ldff1w \{z31\.s\}, p0/z, \[z0\.s\]
--.*: 8520e01f ldff1w \{z31\.s\}, p0/z, \[z0\.s\]
--.*: 8520e01f ldff1w \{z31\.s\}, p0/z, \[z0\.s\]
--.*: 8520e800 ldff1w \{z0\.s\}, p2/z, \[z0\.s\]
--.*: 8520e800 ldff1w \{z0\.s\}, p2/z, \[z0\.s\]
--.*: 8520e800 ldff1w \{z0\.s\}, p2/z, \[z0\.s\]
--.*: 8520fc00 ldff1w \{z0\.s\}, p7/z, \[z0\.s\]
--.*: 8520fc00 ldff1w \{z0\.s\}, p7/z, \[z0\.s\]
--.*: 8520fc00 ldff1w \{z0\.s\}, p7/z, \[z0\.s\]
--.*: 8520e060 ldff1w \{z0\.s\}, p0/z, \[z3\.s\]
--.*: 8520e060 ldff1w \{z0\.s\}, p0/z, \[z3\.s\]
--.*: 8520e060 ldff1w \{z0\.s\}, p0/z, \[z3\.s\]
--.*: 8520e3e0 ldff1w \{z0\.s\}, p0/z, \[z31\.s\]
--.*: 8520e3e0 ldff1w \{z0\.s\}, p0/z, \[z31\.s\]
--.*: 8520e3e0 ldff1w \{z0\.s\}, p0/z, \[z31\.s\]
--.*: 852fe000 ldff1w \{z0\.s\}, p0/z, \[z0\.s, #60\]
--.*: 852fe000 ldff1w \{z0\.s\}, p0/z, \[z0\.s, #60\]
--.*: 8530e000 ldff1w \{z0\.s\}, p0/z, \[z0\.s, #64\]
--.*: 8530e000 ldff1w \{z0\.s\}, p0/z, \[z0\.s, #64\]
--.*: 8531e000 ldff1w \{z0\.s\}, p0/z, \[z0\.s, #68\]
--.*: 8531e000 ldff1w \{z0\.s\}, p0/z, \[z0\.s, #68\]
--.*: 853fe000 ldff1w \{z0\.s\}, p0/z, \[z0\.s, #124\]
--.*: 853fe000 ldff1w \{z0\.s\}, p0/z, \[z0\.s, #124\]
--.*: c520e000 ldff1w \{z0\.d\}, p0/z, \[z0\.d\]
--.*: c520e000 ldff1w \{z0\.d\}, p0/z, \[z0\.d\]
--.*: c520e000 ldff1w \{z0\.d\}, p0/z, \[z0\.d\]
--.*: c520e000 ldff1w \{z0\.d\}, p0/z, \[z0\.d\]
--.*: c520e001 ldff1w \{z1\.d\}, p0/z, \[z0\.d\]
--.*: c520e001 ldff1w \{z1\.d\}, p0/z, \[z0\.d\]
--.*: c520e001 ldff1w \{z1\.d\}, p0/z, \[z0\.d\]
--.*: c520e001 ldff1w \{z1\.d\}, p0/z, \[z0\.d\]
--.*: c520e01f ldff1w \{z31\.d\}, p0/z, \[z0\.d\]
--.*: c520e01f ldff1w \{z31\.d\}, p0/z, \[z0\.d\]
--.*: c520e01f ldff1w \{z31\.d\}, p0/z, \[z0\.d\]
--.*: c520e01f ldff1w \{z31\.d\}, p0/z, \[z0\.d\]
--.*: c520e800 ldff1w \{z0\.d\}, p2/z, \[z0\.d\]
--.*: c520e800 ldff1w \{z0\.d\}, p2/z, \[z0\.d\]
--.*: c520e800 ldff1w \{z0\.d\}, p2/z, \[z0\.d\]
--.*: c520fc00 ldff1w \{z0\.d\}, p7/z, \[z0\.d\]
--.*: c520fc00 ldff1w \{z0\.d\}, p7/z, \[z0\.d\]
--.*: c520fc00 ldff1w \{z0\.d\}, p7/z, \[z0\.d\]
--.*: c520e060 ldff1w \{z0\.d\}, p0/z, \[z3\.d\]
--.*: c520e060 ldff1w \{z0\.d\}, p0/z, \[z3\.d\]
--.*: c520e060 ldff1w \{z0\.d\}, p0/z, \[z3\.d\]
--.*: c520e3e0 ldff1w \{z0\.d\}, p0/z, \[z31\.d\]
--.*: c520e3e0 ldff1w \{z0\.d\}, p0/z, \[z31\.d\]
--.*: c520e3e0 ldff1w \{z0\.d\}, p0/z, \[z31\.d\]
--.*: c52fe000 ldff1w \{z0\.d\}, p0/z, \[z0\.d, #60\]
--.*: c52fe000 ldff1w \{z0\.d\}, p0/z, \[z0\.d, #60\]
--.*: c530e000 ldff1w \{z0\.d\}, p0/z, \[z0\.d, #64\]
--.*: c530e000 ldff1w \{z0\.d\}, p0/z, \[z0\.d, #64\]
--.*: c531e000 ldff1w \{z0\.d\}, p0/z, \[z0\.d, #68\]
--.*: c531e000 ldff1w \{z0\.d\}, p0/z, \[z0\.d, #68\]
--.*: c53fe000 ldff1w \{z0\.d\}, p0/z, \[z0\.d, #124\]
--.*: c53fe000 ldff1w \{z0\.d\}, p0/z, \[z0\.d, #124\]
--.*: a410a000 ldnf1b \{z0\.b\}, p0/z, \[x0\]
--.*: a410a000 ldnf1b \{z0\.b\}, p0/z, \[x0\]
--.*: a410a000 ldnf1b \{z0\.b\}, p0/z, \[x0\]
--.*: a410a000 ldnf1b \{z0\.b\}, p0/z, \[x0\]
--.*: a410a000 ldnf1b \{z0\.b\}, p0/z, \[x0\]
--.*: a410a001 ldnf1b \{z1\.b\}, p0/z, \[x0\]
--.*: a410a001 ldnf1b \{z1\.b\}, p0/z, \[x0\]
--.*: a410a001 ldnf1b \{z1\.b\}, p0/z, \[x0\]
--.*: a410a001 ldnf1b \{z1\.b\}, p0/z, \[x0\]
--.*: a410a001 ldnf1b \{z1\.b\}, p0/z, \[x0\]
--.*: a410a01f ldnf1b \{z31\.b\}, p0/z, \[x0\]
--.*: a410a01f ldnf1b \{z31\.b\}, p0/z, \[x0\]
--.*: a410a01f ldnf1b \{z31\.b\}, p0/z, \[x0\]
--.*: a410a01f ldnf1b \{z31\.b\}, p0/z, \[x0\]
--.*: a410a01f ldnf1b \{z31\.b\}, p0/z, \[x0\]
--.*: a410a800 ldnf1b \{z0\.b\}, p2/z, \[x0\]
--.*: a410a800 ldnf1b \{z0\.b\}, p2/z, \[x0\]
--.*: a410a800 ldnf1b \{z0\.b\}, p2/z, \[x0\]
--.*: a410a800 ldnf1b \{z0\.b\}, p2/z, \[x0\]
--.*: a410bc00 ldnf1b \{z0\.b\}, p7/z, \[x0\]
--.*: a410bc00 ldnf1b \{z0\.b\}, p7/z, \[x0\]
--.*: a410bc00 ldnf1b \{z0\.b\}, p7/z, \[x0\]
--.*: a410bc00 ldnf1b \{z0\.b\}, p7/z, \[x0\]
--.*: a410a060 ldnf1b \{z0\.b\}, p0/z, \[x3\]
--.*: a410a060 ldnf1b \{z0\.b\}, p0/z, \[x3\]
--.*: a410a060 ldnf1b \{z0\.b\}, p0/z, \[x3\]
--.*: a410a060 ldnf1b \{z0\.b\}, p0/z, \[x3\]
--.*: a410a3e0 ldnf1b \{z0\.b\}, p0/z, \[sp\]
--.*: a410a3e0 ldnf1b \{z0\.b\}, p0/z, \[sp\]
--.*: a410a3e0 ldnf1b \{z0\.b\}, p0/z, \[sp\]
--.*: a410a3e0 ldnf1b \{z0\.b\}, p0/z, \[sp\]
--.*: a417a000 ldnf1b \{z0\.b\}, p0/z, \[x0, #7, mul vl\]
--.*: a417a000 ldnf1b \{z0\.b\}, p0/z, \[x0, #7, mul vl\]
--.*: a418a000 ldnf1b \{z0\.b\}, p0/z, \[x0, #-8, mul vl\]
--.*: a418a000 ldnf1b \{z0\.b\}, p0/z, \[x0, #-8, mul vl\]
--.*: a419a000 ldnf1b \{z0\.b\}, p0/z, \[x0, #-7, mul vl\]
--.*: a419a000 ldnf1b \{z0\.b\}, p0/z, \[x0, #-7, mul vl\]
--.*: a41fa000 ldnf1b \{z0\.b\}, p0/z, \[x0, #-1, mul vl\]
--.*: a41fa000 ldnf1b \{z0\.b\}, p0/z, \[x0, #-1, mul vl\]
--.*: a430a000 ldnf1b \{z0\.h\}, p0/z, \[x0\]
--.*: a430a000 ldnf1b \{z0\.h\}, p0/z, \[x0\]
--.*: a430a000 ldnf1b \{z0\.h\}, p0/z, \[x0\]
--.*: a430a000 ldnf1b \{z0\.h\}, p0/z, \[x0\]
--.*: a430a000 ldnf1b \{z0\.h\}, p0/z, \[x0\]
--.*: a430a001 ldnf1b \{z1\.h\}, p0/z, \[x0\]
--.*: a430a001 ldnf1b \{z1\.h\}, p0/z, \[x0\]
--.*: a430a001 ldnf1b \{z1\.h\}, p0/z, \[x0\]
--.*: a430a001 ldnf1b \{z1\.h\}, p0/z, \[x0\]
--.*: a430a001 ldnf1b \{z1\.h\}, p0/z, \[x0\]
--.*: a430a01f ldnf1b \{z31\.h\}, p0/z, \[x0\]
--.*: a430a01f ldnf1b \{z31\.h\}, p0/z, \[x0\]
--.*: a430a01f ldnf1b \{z31\.h\}, p0/z, \[x0\]
--.*: a430a01f ldnf1b \{z31\.h\}, p0/z, \[x0\]
--.*: a430a01f ldnf1b \{z31\.h\}, p0/z, \[x0\]
--.*: a430a800 ldnf1b \{z0\.h\}, p2/z, \[x0\]
--.*: a430a800 ldnf1b \{z0\.h\}, p2/z, \[x0\]
--.*: a430a800 ldnf1b \{z0\.h\}, p2/z, \[x0\]
--.*: a430a800 ldnf1b \{z0\.h\}, p2/z, \[x0\]
--.*: a430bc00 ldnf1b \{z0\.h\}, p7/z, \[x0\]
--.*: a430bc00 ldnf1b \{z0\.h\}, p7/z, \[x0\]
--.*: a430bc00 ldnf1b \{z0\.h\}, p7/z, \[x0\]
--.*: a430bc00 ldnf1b \{z0\.h\}, p7/z, \[x0\]
--.*: a430a060 ldnf1b \{z0\.h\}, p0/z, \[x3\]
--.*: a430a060 ldnf1b \{z0\.h\}, p0/z, \[x3\]
--.*: a430a060 ldnf1b \{z0\.h\}, p0/z, \[x3\]
--.*: a430a060 ldnf1b \{z0\.h\}, p0/z, \[x3\]
--.*: a430a3e0 ldnf1b \{z0\.h\}, p0/z, \[sp\]
--.*: a430a3e0 ldnf1b \{z0\.h\}, p0/z, \[sp\]
--.*: a430a3e0 ldnf1b \{z0\.h\}, p0/z, \[sp\]
--.*: a430a3e0 ldnf1b \{z0\.h\}, p0/z, \[sp\]
--.*: a437a000 ldnf1b \{z0\.h\}, p0/z, \[x0, #7, mul vl\]
--.*: a437a000 ldnf1b \{z0\.h\}, p0/z, \[x0, #7, mul vl\]
--.*: a438a000 ldnf1b \{z0\.h\}, p0/z, \[x0, #-8, mul vl\]
--.*: a438a000 ldnf1b \{z0\.h\}, p0/z, \[x0, #-8, mul vl\]
--.*: a439a000 ldnf1b \{z0\.h\}, p0/z, \[x0, #-7, mul vl\]
--.*: a439a000 ldnf1b \{z0\.h\}, p0/z, \[x0, #-7, mul vl\]
--.*: a43fa000 ldnf1b \{z0\.h\}, p0/z, \[x0, #-1, mul vl\]
--.*: a43fa000 ldnf1b \{z0\.h\}, p0/z, \[x0, #-1, mul vl\]
--.*: a450a000 ldnf1b \{z0\.s\}, p0/z, \[x0\]
--.*: a450a000 ldnf1b \{z0\.s\}, p0/z, \[x0\]
--.*: a450a000 ldnf1b \{z0\.s\}, p0/z, \[x0\]
--.*: a450a000 ldnf1b \{z0\.s\}, p0/z, \[x0\]
--.*: a450a000 ldnf1b \{z0\.s\}, p0/z, \[x0\]
--.*: a450a001 ldnf1b \{z1\.s\}, p0/z, \[x0\]
--.*: a450a001 ldnf1b \{z1\.s\}, p0/z, \[x0\]
--.*: a450a001 ldnf1b \{z1\.s\}, p0/z, \[x0\]
--.*: a450a001 ldnf1b \{z1\.s\}, p0/z, \[x0\]
--.*: a450a001 ldnf1b \{z1\.s\}, p0/z, \[x0\]
--.*: a450a01f ldnf1b \{z31\.s\}, p0/z, \[x0\]
--.*: a450a01f ldnf1b \{z31\.s\}, p0/z, \[x0\]
--.*: a450a01f ldnf1b \{z31\.s\}, p0/z, \[x0\]
--.*: a450a01f ldnf1b \{z31\.s\}, p0/z, \[x0\]
--.*: a450a01f ldnf1b \{z31\.s\}, p0/z, \[x0\]
--.*: a450a800 ldnf1b \{z0\.s\}, p2/z, \[x0\]
--.*: a450a800 ldnf1b \{z0\.s\}, p2/z, \[x0\]
--.*: a450a800 ldnf1b \{z0\.s\}, p2/z, \[x0\]
--.*: a450a800 ldnf1b \{z0\.s\}, p2/z, \[x0\]
--.*: a450bc00 ldnf1b \{z0\.s\}, p7/z, \[x0\]
--.*: a450bc00 ldnf1b \{z0\.s\}, p7/z, \[x0\]
--.*: a450bc00 ldnf1b \{z0\.s\}, p7/z, \[x0\]
--.*: a450bc00 ldnf1b \{z0\.s\}, p7/z, \[x0\]
--.*: a450a060 ldnf1b \{z0\.s\}, p0/z, \[x3\]
--.*: a450a060 ldnf1b \{z0\.s\}, p0/z, \[x3\]
--.*: a450a060 ldnf1b \{z0\.s\}, p0/z, \[x3\]
--.*: a450a060 ldnf1b \{z0\.s\}, p0/z, \[x3\]
--.*: a450a3e0 ldnf1b \{z0\.s\}, p0/z, \[sp\]
--.*: a450a3e0 ldnf1b \{z0\.s\}, p0/z, \[sp\]
--.*: a450a3e0 ldnf1b \{z0\.s\}, p0/z, \[sp\]
--.*: a450a3e0 ldnf1b \{z0\.s\}, p0/z, \[sp\]
--.*: a457a000 ldnf1b \{z0\.s\}, p0/z, \[x0, #7, mul vl\]
--.*: a457a000 ldnf1b \{z0\.s\}, p0/z, \[x0, #7, mul vl\]
--.*: a458a000 ldnf1b \{z0\.s\}, p0/z, \[x0, #-8, mul vl\]
--.*: a458a000 ldnf1b \{z0\.s\}, p0/z, \[x0, #-8, mul vl\]
--.*: a459a000 ldnf1b \{z0\.s\}, p0/z, \[x0, #-7, mul vl\]
--.*: a459a000 ldnf1b \{z0\.s\}, p0/z, \[x0, #-7, mul vl\]
--.*: a45fa000 ldnf1b \{z0\.s\}, p0/z, \[x0, #-1, mul vl\]
--.*: a45fa000 ldnf1b \{z0\.s\}, p0/z, \[x0, #-1, mul vl\]
--.*: a470a000 ldnf1b \{z0\.d\}, p0/z, \[x0\]
--.*: a470a000 ldnf1b \{z0\.d\}, p0/z, \[x0\]
--.*: a470a000 ldnf1b \{z0\.d\}, p0/z, \[x0\]
--.*: a470a000 ldnf1b \{z0\.d\}, p0/z, \[x0\]
--.*: a470a000 ldnf1b \{z0\.d\}, p0/z, \[x0\]
--.*: a470a001 ldnf1b \{z1\.d\}, p0/z, \[x0\]
--.*: a470a001 ldnf1b \{z1\.d\}, p0/z, \[x0\]
--.*: a470a001 ldnf1b \{z1\.d\}, p0/z, \[x0\]
--.*: a470a001 ldnf1b \{z1\.d\}, p0/z, \[x0\]
--.*: a470a001 ldnf1b \{z1\.d\}, p0/z, \[x0\]
--.*: a470a01f ldnf1b \{z31\.d\}, p0/z, \[x0\]
--.*: a470a01f ldnf1b \{z31\.d\}, p0/z, \[x0\]
--.*: a470a01f ldnf1b \{z31\.d\}, p0/z, \[x0\]
--.*: a470a01f ldnf1b \{z31\.d\}, p0/z, \[x0\]
--.*: a470a01f ldnf1b \{z31\.d\}, p0/z, \[x0\]
--.*: a470a800 ldnf1b \{z0\.d\}, p2/z, \[x0\]
--.*: a470a800 ldnf1b \{z0\.d\}, p2/z, \[x0\]
--.*: a470a800 ldnf1b \{z0\.d\}, p2/z, \[x0\]
--.*: a470a800 ldnf1b \{z0\.d\}, p2/z, \[x0\]
--.*: a470bc00 ldnf1b \{z0\.d\}, p7/z, \[x0\]
--.*: a470bc00 ldnf1b \{z0\.d\}, p7/z, \[x0\]
--.*: a470bc00 ldnf1b \{z0\.d\}, p7/z, \[x0\]
--.*: a470bc00 ldnf1b \{z0\.d\}, p7/z, \[x0\]
--.*: a470a060 ldnf1b \{z0\.d\}, p0/z, \[x3\]
--.*: a470a060 ldnf1b \{z0\.d\}, p0/z, \[x3\]
--.*: a470a060 ldnf1b \{z0\.d\}, p0/z, \[x3\]
--.*: a470a060 ldnf1b \{z0\.d\}, p0/z, \[x3\]
--.*: a470a3e0 ldnf1b \{z0\.d\}, p0/z, \[sp\]
--.*: a470a3e0 ldnf1b \{z0\.d\}, p0/z, \[sp\]
--.*: a470a3e0 ldnf1b \{z0\.d\}, p0/z, \[sp\]
--.*: a470a3e0 ldnf1b \{z0\.d\}, p0/z, \[sp\]
--.*: a477a000 ldnf1b \{z0\.d\}, p0/z, \[x0, #7, mul vl\]
--.*: a477a000 ldnf1b \{z0\.d\}, p0/z, \[x0, #7, mul vl\]
--.*: a478a000 ldnf1b \{z0\.d\}, p0/z, \[x0, #-8, mul vl\]
--.*: a478a000 ldnf1b \{z0\.d\}, p0/z, \[x0, #-8, mul vl\]
--.*: a479a000 ldnf1b \{z0\.d\}, p0/z, \[x0, #-7, mul vl\]
--.*: a479a000 ldnf1b \{z0\.d\}, p0/z, \[x0, #-7, mul vl\]
--.*: a47fa000 ldnf1b \{z0\.d\}, p0/z, \[x0, #-1, mul vl\]
--.*: a47fa000 ldnf1b \{z0\.d\}, p0/z, \[x0, #-1, mul vl\]
--.*: a5f0a000 ldnf1d \{z0\.d\}, p0/z, \[x0\]
--.*: a5f0a000 ldnf1d \{z0\.d\}, p0/z, \[x0\]
--.*: a5f0a000 ldnf1d \{z0\.d\}, p0/z, \[x0\]
--.*: a5f0a000 ldnf1d \{z0\.d\}, p0/z, \[x0\]
--.*: a5f0a000 ldnf1d \{z0\.d\}, p0/z, \[x0\]
--.*: a5f0a001 ldnf1d \{z1\.d\}, p0/z, \[x0\]
--.*: a5f0a001 ldnf1d \{z1\.d\}, p0/z, \[x0\]
--.*: a5f0a001 ldnf1d \{z1\.d\}, p0/z, \[x0\]
--.*: a5f0a001 ldnf1d \{z1\.d\}, p0/z, \[x0\]
--.*: a5f0a001 ldnf1d \{z1\.d\}, p0/z, \[x0\]
--.*: a5f0a01f ldnf1d \{z31\.d\}, p0/z, \[x0\]
--.*: a5f0a01f ldnf1d \{z31\.d\}, p0/z, \[x0\]
--.*: a5f0a01f ldnf1d \{z31\.d\}, p0/z, \[x0\]
--.*: a5f0a01f ldnf1d \{z31\.d\}, p0/z, \[x0\]
--.*: a5f0a01f ldnf1d \{z31\.d\}, p0/z, \[x0\]
--.*: a5f0a800 ldnf1d \{z0\.d\}, p2/z, \[x0\]
--.*: a5f0a800 ldnf1d \{z0\.d\}, p2/z, \[x0\]
--.*: a5f0a800 ldnf1d \{z0\.d\}, p2/z, \[x0\]
--.*: a5f0a800 ldnf1d \{z0\.d\}, p2/z, \[x0\]
--.*: a5f0bc00 ldnf1d \{z0\.d\}, p7/z, \[x0\]
--.*: a5f0bc00 ldnf1d \{z0\.d\}, p7/z, \[x0\]
--.*: a5f0bc00 ldnf1d \{z0\.d\}, p7/z, \[x0\]
--.*: a5f0bc00 ldnf1d \{z0\.d\}, p7/z, \[x0\]
--.*: a5f0a060 ldnf1d \{z0\.d\}, p0/z, \[x3\]
--.*: a5f0a060 ldnf1d \{z0\.d\}, p0/z, \[x3\]
--.*: a5f0a060 ldnf1d \{z0\.d\}, p0/z, \[x3\]
--.*: a5f0a060 ldnf1d \{z0\.d\}, p0/z, \[x3\]
--.*: a5f0a3e0 ldnf1d \{z0\.d\}, p0/z, \[sp\]
--.*: a5f0a3e0 ldnf1d \{z0\.d\}, p0/z, \[sp\]
--.*: a5f0a3e0 ldnf1d \{z0\.d\}, p0/z, \[sp\]
--.*: a5f0a3e0 ldnf1d \{z0\.d\}, p0/z, \[sp\]
--.*: a5f7a000 ldnf1d \{z0\.d\}, p0/z, \[x0, #7, mul vl\]
--.*: a5f7a000 ldnf1d \{z0\.d\}, p0/z, \[x0, #7, mul vl\]
--.*: a5f8a000 ldnf1d \{z0\.d\}, p0/z, \[x0, #-8, mul vl\]
--.*: a5f8a000 ldnf1d \{z0\.d\}, p0/z, \[x0, #-8, mul vl\]
--.*: a5f9a000 ldnf1d \{z0\.d\}, p0/z, \[x0, #-7, mul vl\]
--.*: a5f9a000 ldnf1d \{z0\.d\}, p0/z, \[x0, #-7, mul vl\]
--.*: a5ffa000 ldnf1d \{z0\.d\}, p0/z, \[x0, #-1, mul vl\]
--.*: a5ffa000 ldnf1d \{z0\.d\}, p0/z, \[x0, #-1, mul vl\]
--.*: a4b0a000 ldnf1h \{z0\.h\}, p0/z, \[x0\]
--.*: a4b0a000 ldnf1h \{z0\.h\}, p0/z, \[x0\]
--.*: a4b0a000 ldnf1h \{z0\.h\}, p0/z, \[x0\]
--.*: a4b0a000 ldnf1h \{z0\.h\}, p0/z, \[x0\]
--.*: a4b0a000 ldnf1h \{z0\.h\}, p0/z, \[x0\]
--.*: a4b0a001 ldnf1h \{z1\.h\}, p0/z, \[x0\]
--.*: a4b0a001 ldnf1h \{z1\.h\}, p0/z, \[x0\]
--.*: a4b0a001 ldnf1h \{z1\.h\}, p0/z, \[x0\]
--.*: a4b0a001 ldnf1h \{z1\.h\}, p0/z, \[x0\]
--.*: a4b0a001 ldnf1h \{z1\.h\}, p0/z, \[x0\]
--.*: a4b0a01f ldnf1h \{z31\.h\}, p0/z, \[x0\]
--.*: a4b0a01f ldnf1h \{z31\.h\}, p0/z, \[x0\]
--.*: a4b0a01f ldnf1h \{z31\.h\}, p0/z, \[x0\]
--.*: a4b0a01f ldnf1h \{z31\.h\}, p0/z, \[x0\]
--.*: a4b0a01f ldnf1h \{z31\.h\}, p0/z, \[x0\]
--.*: a4b0a800 ldnf1h \{z0\.h\}, p2/z, \[x0\]
--.*: a4b0a800 ldnf1h \{z0\.h\}, p2/z, \[x0\]
--.*: a4b0a800 ldnf1h \{z0\.h\}, p2/z, \[x0\]
--.*: a4b0a800 ldnf1h \{z0\.h\}, p2/z, \[x0\]
--.*: a4b0bc00 ldnf1h \{z0\.h\}, p7/z, \[x0\]
--.*: a4b0bc00 ldnf1h \{z0\.h\}, p7/z, \[x0\]
--.*: a4b0bc00 ldnf1h \{z0\.h\}, p7/z, \[x0\]
--.*: a4b0bc00 ldnf1h \{z0\.h\}, p7/z, \[x0\]
--.*: a4b0a060 ldnf1h \{z0\.h\}, p0/z, \[x3\]
--.*: a4b0a060 ldnf1h \{z0\.h\}, p0/z, \[x3\]
--.*: a4b0a060 ldnf1h \{z0\.h\}, p0/z, \[x3\]
--.*: a4b0a060 ldnf1h \{z0\.h\}, p0/z, \[x3\]
--.*: a4b0a3e0 ldnf1h \{z0\.h\}, p0/z, \[sp\]
--.*: a4b0a3e0 ldnf1h \{z0\.h\}, p0/z, \[sp\]
--.*: a4b0a3e0 ldnf1h \{z0\.h\}, p0/z, \[sp\]
--.*: a4b0a3e0 ldnf1h \{z0\.h\}, p0/z, \[sp\]
--.*: a4b7a000 ldnf1h \{z0\.h\}, p0/z, \[x0, #7, mul vl\]
--.*: a4b7a000 ldnf1h \{z0\.h\}, p0/z, \[x0, #7, mul vl\]
--.*: a4b8a000 ldnf1h \{z0\.h\}, p0/z, \[x0, #-8, mul vl\]
--.*: a4b8a000 ldnf1h \{z0\.h\}, p0/z, \[x0, #-8, mul vl\]
--.*: a4b9a000 ldnf1h \{z0\.h\}, p0/z, \[x0, #-7, mul vl\]
--.*: a4b9a000 ldnf1h \{z0\.h\}, p0/z, \[x0, #-7, mul vl\]
--.*: a4bfa000 ldnf1h \{z0\.h\}, p0/z, \[x0, #-1, mul vl\]
--.*: a4bfa000 ldnf1h \{z0\.h\}, p0/z, \[x0, #-1, mul vl\]
--.*: a4d0a000 ldnf1h \{z0\.s\}, p0/z, \[x0\]
--.*: a4d0a000 ldnf1h \{z0\.s\}, p0/z, \[x0\]
--.*: a4d0a000 ldnf1h \{z0\.s\}, p0/z, \[x0\]
--.*: a4d0a000 ldnf1h \{z0\.s\}, p0/z, \[x0\]
--.*: a4d0a000 ldnf1h \{z0\.s\}, p0/z, \[x0\]
--.*: a4d0a001 ldnf1h \{z1\.s\}, p0/z, \[x0\]
--.*: a4d0a001 ldnf1h \{z1\.s\}, p0/z, \[x0\]
--.*: a4d0a001 ldnf1h \{z1\.s\}, p0/z, \[x0\]
--.*: a4d0a001 ldnf1h \{z1\.s\}, p0/z, \[x0\]
--.*: a4d0a001 ldnf1h \{z1\.s\}, p0/z, \[x0\]
--.*: a4d0a01f ldnf1h \{z31\.s\}, p0/z, \[x0\]
--.*: a4d0a01f ldnf1h \{z31\.s\}, p0/z, \[x0\]
--.*: a4d0a01f ldnf1h \{z31\.s\}, p0/z, \[x0\]
--.*: a4d0a01f ldnf1h \{z31\.s\}, p0/z, \[x0\]
--.*: a4d0a01f ldnf1h \{z31\.s\}, p0/z, \[x0\]
--.*: a4d0a800 ldnf1h \{z0\.s\}, p2/z, \[x0\]
--.*: a4d0a800 ldnf1h \{z0\.s\}, p2/z, \[x0\]
--.*: a4d0a800 ldnf1h \{z0\.s\}, p2/z, \[x0\]
--.*: a4d0a800 ldnf1h \{z0\.s\}, p2/z, \[x0\]
--.*: a4d0bc00 ldnf1h \{z0\.s\}, p7/z, \[x0\]
--.*: a4d0bc00 ldnf1h \{z0\.s\}, p7/z, \[x0\]
--.*: a4d0bc00 ldnf1h \{z0\.s\}, p7/z, \[x0\]
--.*: a4d0bc00 ldnf1h \{z0\.s\}, p7/z, \[x0\]
--.*: a4d0a060 ldnf1h \{z0\.s\}, p0/z, \[x3\]
--.*: a4d0a060 ldnf1h \{z0\.s\}, p0/z, \[x3\]
--.*: a4d0a060 ldnf1h \{z0\.s\}, p0/z, \[x3\]
--.*: a4d0a060 ldnf1h \{z0\.s\}, p0/z, \[x3\]
--.*: a4d0a3e0 ldnf1h \{z0\.s\}, p0/z, \[sp\]
--.*: a4d0a3e0 ldnf1h \{z0\.s\}, p0/z, \[sp\]
--.*: a4d0a3e0 ldnf1h \{z0\.s\}, p0/z, \[sp\]
--.*: a4d0a3e0 ldnf1h \{z0\.s\}, p0/z, \[sp\]
--.*: a4d7a000 ldnf1h \{z0\.s\}, p0/z, \[x0, #7, mul vl\]
--.*: a4d7a000 ldnf1h \{z0\.s\}, p0/z, \[x0, #7, mul vl\]
--.*: a4d8a000 ldnf1h \{z0\.s\}, p0/z, \[x0, #-8, mul vl\]
--.*: a4d8a000 ldnf1h \{z0\.s\}, p0/z, \[x0, #-8, mul vl\]
--.*: a4d9a000 ldnf1h \{z0\.s\}, p0/z, \[x0, #-7, mul vl\]
--.*: a4d9a000 ldnf1h \{z0\.s\}, p0/z, \[x0, #-7, mul vl\]
--.*: a4dfa000 ldnf1h \{z0\.s\}, p0/z, \[x0, #-1, mul vl\]
--.*: a4dfa000 ldnf1h \{z0\.s\}, p0/z, \[x0, #-1, mul vl\]
--.*: a4f0a000 ldnf1h \{z0\.d\}, p0/z, \[x0\]
--.*: a4f0a000 ldnf1h \{z0\.d\}, p0/z, \[x0\]
--.*: a4f0a000 ldnf1h \{z0\.d\}, p0/z, \[x0\]
--.*: a4f0a000 ldnf1h \{z0\.d\}, p0/z, \[x0\]
--.*: a4f0a000 ldnf1h \{z0\.d\}, p0/z, \[x0\]
--.*: a4f0a001 ldnf1h \{z1\.d\}, p0/z, \[x0\]
--.*: a4f0a001 ldnf1h \{z1\.d\}, p0/z, \[x0\]
--.*: a4f0a001 ldnf1h \{z1\.d\}, p0/z, \[x0\]
--.*: a4f0a001 ldnf1h \{z1\.d\}, p0/z, \[x0\]
--.*: a4f0a001 ldnf1h \{z1\.d\}, p0/z, \[x0\]
--.*: a4f0a01f ldnf1h \{z31\.d\}, p0/z, \[x0\]
--.*: a4f0a01f ldnf1h \{z31\.d\}, p0/z, \[x0\]
--.*: a4f0a01f ldnf1h \{z31\.d\}, p0/z, \[x0\]
--.*: a4f0a01f ldnf1h \{z31\.d\}, p0/z, \[x0\]
--.*: a4f0a01f ldnf1h \{z31\.d\}, p0/z, \[x0\]
--.*: a4f0a800 ldnf1h \{z0\.d\}, p2/z, \[x0\]
--.*: a4f0a800 ldnf1h \{z0\.d\}, p2/z, \[x0\]
--.*: a4f0a800 ldnf1h \{z0\.d\}, p2/z, \[x0\]
--.*: a4f0a800 ldnf1h \{z0\.d\}, p2/z, \[x0\]
--.*: a4f0bc00 ldnf1h \{z0\.d\}, p7/z, \[x0\]
--.*: a4f0bc00 ldnf1h \{z0\.d\}, p7/z, \[x0\]
--.*: a4f0bc00 ldnf1h \{z0\.d\}, p7/z, \[x0\]
--.*: a4f0bc00 ldnf1h \{z0\.d\}, p7/z, \[x0\]
--.*: a4f0a060 ldnf1h \{z0\.d\}, p0/z, \[x3\]
--.*: a4f0a060 ldnf1h \{z0\.d\}, p0/z, \[x3\]
--.*: a4f0a060 ldnf1h \{z0\.d\}, p0/z, \[x3\]
--.*: a4f0a060 ldnf1h \{z0\.d\}, p0/z, \[x3\]
--.*: a4f0a3e0 ldnf1h \{z0\.d\}, p0/z, \[sp\]
--.*: a4f0a3e0 ldnf1h \{z0\.d\}, p0/z, \[sp\]
--.*: a4f0a3e0 ldnf1h \{z0\.d\}, p0/z, \[sp\]
--.*: a4f0a3e0 ldnf1h \{z0\.d\}, p0/z, \[sp\]
--.*: a4f7a000 ldnf1h \{z0\.d\}, p0/z, \[x0, #7, mul vl\]
--.*: a4f7a000 ldnf1h \{z0\.d\}, p0/z, \[x0, #7, mul vl\]
--.*: a4f8a000 ldnf1h \{z0\.d\}, p0/z, \[x0, #-8, mul vl\]
--.*: a4f8a000 ldnf1h \{z0\.d\}, p0/z, \[x0, #-8, mul vl\]
--.*: a4f9a000 ldnf1h \{z0\.d\}, p0/z, \[x0, #-7, mul vl\]
--.*: a4f9a000 ldnf1h \{z0\.d\}, p0/z, \[x0, #-7, mul vl\]
--.*: a4ffa000 ldnf1h \{z0\.d\}, p0/z, \[x0, #-1, mul vl\]
--.*: a4ffa000 ldnf1h \{z0\.d\}, p0/z, \[x0, #-1, mul vl\]
--.*: a590a000 ldnf1sb \{z0\.d\}, p0/z, \[x0\]
--.*: a590a000 ldnf1sb \{z0\.d\}, p0/z, \[x0\]
--.*: a590a000 ldnf1sb \{z0\.d\}, p0/z, \[x0\]
--.*: a590a000 ldnf1sb \{z0\.d\}, p0/z, \[x0\]
--.*: a590a000 ldnf1sb \{z0\.d\}, p0/z, \[x0\]
--.*: a590a001 ldnf1sb \{z1\.d\}, p0/z, \[x0\]
--.*: a590a001 ldnf1sb \{z1\.d\}, p0/z, \[x0\]
--.*: a590a001 ldnf1sb \{z1\.d\}, p0/z, \[x0\]
--.*: a590a001 ldnf1sb \{z1\.d\}, p0/z, \[x0\]
--.*: a590a001 ldnf1sb \{z1\.d\}, p0/z, \[x0\]
--.*: a590a01f ldnf1sb \{z31\.d\}, p0/z, \[x0\]
--.*: a590a01f ldnf1sb \{z31\.d\}, p0/z, \[x0\]
--.*: a590a01f ldnf1sb \{z31\.d\}, p0/z, \[x0\]
--.*: a590a01f ldnf1sb \{z31\.d\}, p0/z, \[x0\]
--.*: a590a01f ldnf1sb \{z31\.d\}, p0/z, \[x0\]
--.*: a590a800 ldnf1sb \{z0\.d\}, p2/z, \[x0\]
--.*: a590a800 ldnf1sb \{z0\.d\}, p2/z, \[x0\]
--.*: a590a800 ldnf1sb \{z0\.d\}, p2/z, \[x0\]
--.*: a590a800 ldnf1sb \{z0\.d\}, p2/z, \[x0\]
--.*: a590bc00 ldnf1sb \{z0\.d\}, p7/z, \[x0\]
--.*: a590bc00 ldnf1sb \{z0\.d\}, p7/z, \[x0\]
--.*: a590bc00 ldnf1sb \{z0\.d\}, p7/z, \[x0\]
--.*: a590bc00 ldnf1sb \{z0\.d\}, p7/z, \[x0\]
--.*: a590a060 ldnf1sb \{z0\.d\}, p0/z, \[x3\]
--.*: a590a060 ldnf1sb \{z0\.d\}, p0/z, \[x3\]
--.*: a590a060 ldnf1sb \{z0\.d\}, p0/z, \[x3\]
--.*: a590a060 ldnf1sb \{z0\.d\}, p0/z, \[x3\]
--.*: a590a3e0 ldnf1sb \{z0\.d\}, p0/z, \[sp\]
--.*: a590a3e0 ldnf1sb \{z0\.d\}, p0/z, \[sp\]
--.*: a590a3e0 ldnf1sb \{z0\.d\}, p0/z, \[sp\]
--.*: a590a3e0 ldnf1sb \{z0\.d\}, p0/z, \[sp\]
--.*: a597a000 ldnf1sb \{z0\.d\}, p0/z, \[x0, #7, mul vl\]
--.*: a597a000 ldnf1sb \{z0\.d\}, p0/z, \[x0, #7, mul vl\]
--.*: a598a000 ldnf1sb \{z0\.d\}, p0/z, \[x0, #-8, mul vl\]
--.*: a598a000 ldnf1sb \{z0\.d\}, p0/z, \[x0, #-8, mul vl\]
--.*: a599a000 ldnf1sb \{z0\.d\}, p0/z, \[x0, #-7, mul vl\]
--.*: a599a000 ldnf1sb \{z0\.d\}, p0/z, \[x0, #-7, mul vl\]
--.*: a59fa000 ldnf1sb \{z0\.d\}, p0/z, \[x0, #-1, mul vl\]
--.*: a59fa000 ldnf1sb \{z0\.d\}, p0/z, \[x0, #-1, mul vl\]
--.*: a5b0a000 ldnf1sb \{z0\.s\}, p0/z, \[x0\]
--.*: a5b0a000 ldnf1sb \{z0\.s\}, p0/z, \[x0\]
--.*: a5b0a000 ldnf1sb \{z0\.s\}, p0/z, \[x0\]
--.*: a5b0a000 ldnf1sb \{z0\.s\}, p0/z, \[x0\]
--.*: a5b0a000 ldnf1sb \{z0\.s\}, p0/z, \[x0\]
--.*: a5b0a001 ldnf1sb \{z1\.s\}, p0/z, \[x0\]
--.*: a5b0a001 ldnf1sb \{z1\.s\}, p0/z, \[x0\]
--.*: a5b0a001 ldnf1sb \{z1\.s\}, p0/z, \[x0\]
--.*: a5b0a001 ldnf1sb \{z1\.s\}, p0/z, \[x0\]
--.*: a5b0a001 ldnf1sb \{z1\.s\}, p0/z, \[x0\]
--.*: a5b0a01f ldnf1sb \{z31\.s\}, p0/z, \[x0\]
--.*: a5b0a01f ldnf1sb \{z31\.s\}, p0/z, \[x0\]
--.*: a5b0a01f ldnf1sb \{z31\.s\}, p0/z, \[x0\]
--.*: a5b0a01f ldnf1sb \{z31\.s\}, p0/z, \[x0\]
--.*: a5b0a01f ldnf1sb \{z31\.s\}, p0/z, \[x0\]
--.*: a5b0a800 ldnf1sb \{z0\.s\}, p2/z, \[x0\]
--.*: a5b0a800 ldnf1sb \{z0\.s\}, p2/z, \[x0\]
--.*: a5b0a800 ldnf1sb \{z0\.s\}, p2/z, \[x0\]
--.*: a5b0a800 ldnf1sb \{z0\.s\}, p2/z, \[x0\]
--.*: a5b0bc00 ldnf1sb \{z0\.s\}, p7/z, \[x0\]
--.*: a5b0bc00 ldnf1sb \{z0\.s\}, p7/z, \[x0\]
--.*: a5b0bc00 ldnf1sb \{z0\.s\}, p7/z, \[x0\]
--.*: a5b0bc00 ldnf1sb \{z0\.s\}, p7/z, \[x0\]
--.*: a5b0a060 ldnf1sb \{z0\.s\}, p0/z, \[x3\]
--.*: a5b0a060 ldnf1sb \{z0\.s\}, p0/z, \[x3\]
--.*: a5b0a060 ldnf1sb \{z0\.s\}, p0/z, \[x3\]
--.*: a5b0a060 ldnf1sb \{z0\.s\}, p0/z, \[x3\]
--.*: a5b0a3e0 ldnf1sb \{z0\.s\}, p0/z, \[sp\]
--.*: a5b0a3e0 ldnf1sb \{z0\.s\}, p0/z, \[sp\]
--.*: a5b0a3e0 ldnf1sb \{z0\.s\}, p0/z, \[sp\]
--.*: a5b0a3e0 ldnf1sb \{z0\.s\}, p0/z, \[sp\]
--.*: a5b7a000 ldnf1sb \{z0\.s\}, p0/z, \[x0, #7, mul vl\]
--.*: a5b7a000 ldnf1sb \{z0\.s\}, p0/z, \[x0, #7, mul vl\]
--.*: a5b8a000 ldnf1sb \{z0\.s\}, p0/z, \[x0, #-8, mul vl\]
--.*: a5b8a000 ldnf1sb \{z0\.s\}, p0/z, \[x0, #-8, mul vl\]
--.*: a5b9a000 ldnf1sb \{z0\.s\}, p0/z, \[x0, #-7, mul vl\]
--.*: a5b9a000 ldnf1sb \{z0\.s\}, p0/z, \[x0, #-7, mul vl\]
--.*: a5bfa000 ldnf1sb \{z0\.s\}, p0/z, \[x0, #-1, mul vl\]
--.*: a5bfa000 ldnf1sb \{z0\.s\}, p0/z, \[x0, #-1, mul vl\]
--.*: a5d0a000 ldnf1sb \{z0\.h\}, p0/z, \[x0\]
--.*: a5d0a000 ldnf1sb \{z0\.h\}, p0/z, \[x0\]
--.*: a5d0a000 ldnf1sb \{z0\.h\}, p0/z, \[x0\]
--.*: a5d0a000 ldnf1sb \{z0\.h\}, p0/z, \[x0\]
--.*: a5d0a000 ldnf1sb \{z0\.h\}, p0/z, \[x0\]
--.*: a5d0a001 ldnf1sb \{z1\.h\}, p0/z, \[x0\]
--.*: a5d0a001 ldnf1sb \{z1\.h\}, p0/z, \[x0\]
--.*: a5d0a001 ldnf1sb \{z1\.h\}, p0/z, \[x0\]
--.*: a5d0a001 ldnf1sb \{z1\.h\}, p0/z, \[x0\]
--.*: a5d0a001 ldnf1sb \{z1\.h\}, p0/z, \[x0\]
--.*: a5d0a01f ldnf1sb \{z31\.h\}, p0/z, \[x0\]
--.*: a5d0a01f ldnf1sb \{z31\.h\}, p0/z, \[x0\]
--.*: a5d0a01f ldnf1sb \{z31\.h\}, p0/z, \[x0\]
--.*: a5d0a01f ldnf1sb \{z31\.h\}, p0/z, \[x0\]
--.*: a5d0a01f ldnf1sb \{z31\.h\}, p0/z, \[x0\]
--.*: a5d0a800 ldnf1sb \{z0\.h\}, p2/z, \[x0\]
--.*: a5d0a800 ldnf1sb \{z0\.h\}, p2/z, \[x0\]
--.*: a5d0a800 ldnf1sb \{z0\.h\}, p2/z, \[x0\]
--.*: a5d0a800 ldnf1sb \{z0\.h\}, p2/z, \[x0\]
--.*: a5d0bc00 ldnf1sb \{z0\.h\}, p7/z, \[x0\]
--.*: a5d0bc00 ldnf1sb \{z0\.h\}, p7/z, \[x0\]
--.*: a5d0bc00 ldnf1sb \{z0\.h\}, p7/z, \[x0\]
--.*: a5d0bc00 ldnf1sb \{z0\.h\}, p7/z, \[x0\]
--.*: a5d0a060 ldnf1sb \{z0\.h\}, p0/z, \[x3\]
--.*: a5d0a060 ldnf1sb \{z0\.h\}, p0/z, \[x3\]
--.*: a5d0a060 ldnf1sb \{z0\.h\}, p0/z, \[x3\]
--.*: a5d0a060 ldnf1sb \{z0\.h\}, p0/z, \[x3\]
--.*: a5d0a3e0 ldnf1sb \{z0\.h\}, p0/z, \[sp\]
--.*: a5d0a3e0 ldnf1sb \{z0\.h\}, p0/z, \[sp\]
--.*: a5d0a3e0 ldnf1sb \{z0\.h\}, p0/z, \[sp\]
--.*: a5d0a3e0 ldnf1sb \{z0\.h\}, p0/z, \[sp\]
--.*: a5d7a000 ldnf1sb \{z0\.h\}, p0/z, \[x0, #7, mul vl\]
--.*: a5d7a000 ldnf1sb \{z0\.h\}, p0/z, \[x0, #7, mul vl\]
--.*: a5d8a000 ldnf1sb \{z0\.h\}, p0/z, \[x0, #-8, mul vl\]
--.*: a5d8a000 ldnf1sb \{z0\.h\}, p0/z, \[x0, #-8, mul vl\]
--.*: a5d9a000 ldnf1sb \{z0\.h\}, p0/z, \[x0, #-7, mul vl\]
--.*: a5d9a000 ldnf1sb \{z0\.h\}, p0/z, \[x0, #-7, mul vl\]
--.*: a5dfa000 ldnf1sb \{z0\.h\}, p0/z, \[x0, #-1, mul vl\]
--.*: a5dfa000 ldnf1sb \{z0\.h\}, p0/z, \[x0, #-1, mul vl\]
--.*: a510a000 ldnf1sh \{z0\.d\}, p0/z, \[x0\]
--.*: a510a000 ldnf1sh \{z0\.d\}, p0/z, \[x0\]
--.*: a510a000 ldnf1sh \{z0\.d\}, p0/z, \[x0\]
--.*: a510a000 ldnf1sh \{z0\.d\}, p0/z, \[x0\]
--.*: a510a000 ldnf1sh \{z0\.d\}, p0/z, \[x0\]
--.*: a510a001 ldnf1sh \{z1\.d\}, p0/z, \[x0\]
--.*: a510a001 ldnf1sh \{z1\.d\}, p0/z, \[x0\]
--.*: a510a001 ldnf1sh \{z1\.d\}, p0/z, \[x0\]
--.*: a510a001 ldnf1sh \{z1\.d\}, p0/z, \[x0\]
--.*: a510a001 ldnf1sh \{z1\.d\}, p0/z, \[x0\]
--.*: a510a01f ldnf1sh \{z31\.d\}, p0/z, \[x0\]
--.*: a510a01f ldnf1sh \{z31\.d\}, p0/z, \[x0\]
--.*: a510a01f ldnf1sh \{z31\.d\}, p0/z, \[x0\]
--.*: a510a01f ldnf1sh \{z31\.d\}, p0/z, \[x0\]
--.*: a510a01f ldnf1sh \{z31\.d\}, p0/z, \[x0\]
--.*: a510a800 ldnf1sh \{z0\.d\}, p2/z, \[x0\]
--.*: a510a800 ldnf1sh \{z0\.d\}, p2/z, \[x0\]
--.*: a510a800 ldnf1sh \{z0\.d\}, p2/z, \[x0\]
--.*: a510a800 ldnf1sh \{z0\.d\}, p2/z, \[x0\]
--.*: a510bc00 ldnf1sh \{z0\.d\}, p7/z, \[x0\]
--.*: a510bc00 ldnf1sh \{z0\.d\}, p7/z, \[x0\]
--.*: a510bc00 ldnf1sh \{z0\.d\}, p7/z, \[x0\]
--.*: a510bc00 ldnf1sh \{z0\.d\}, p7/z, \[x0\]
--.*: a510a060 ldnf1sh \{z0\.d\}, p0/z, \[x3\]
--.*: a510a060 ldnf1sh \{z0\.d\}, p0/z, \[x3\]
--.*: a510a060 ldnf1sh \{z0\.d\}, p0/z, \[x3\]
--.*: a510a060 ldnf1sh \{z0\.d\}, p0/z, \[x3\]
--.*: a510a3e0 ldnf1sh \{z0\.d\}, p0/z, \[sp\]
--.*: a510a3e0 ldnf1sh \{z0\.d\}, p0/z, \[sp\]
--.*: a510a3e0 ldnf1sh \{z0\.d\}, p0/z, \[sp\]
--.*: a510a3e0 ldnf1sh \{z0\.d\}, p0/z, \[sp\]
--.*: a517a000 ldnf1sh \{z0\.d\}, p0/z, \[x0, #7, mul vl\]
--.*: a517a000 ldnf1sh \{z0\.d\}, p0/z, \[x0, #7, mul vl\]
--.*: a518a000 ldnf1sh \{z0\.d\}, p0/z, \[x0, #-8, mul vl\]
--.*: a518a000 ldnf1sh \{z0\.d\}, p0/z, \[x0, #-8, mul vl\]
--.*: a519a000 ldnf1sh \{z0\.d\}, p0/z, \[x0, #-7, mul vl\]
--.*: a519a000 ldnf1sh \{z0\.d\}, p0/z, \[x0, #-7, mul vl\]
--.*: a51fa000 ldnf1sh \{z0\.d\}, p0/z, \[x0, #-1, mul vl\]
--.*: a51fa000 ldnf1sh \{z0\.d\}, p0/z, \[x0, #-1, mul vl\]
--.*: a530a000 ldnf1sh \{z0\.s\}, p0/z, \[x0\]
--.*: a530a000 ldnf1sh \{z0\.s\}, p0/z, \[x0\]
--.*: a530a000 ldnf1sh \{z0\.s\}, p0/z, \[x0\]
--.*: a530a000 ldnf1sh \{z0\.s\}, p0/z, \[x0\]
--.*: a530a000 ldnf1sh \{z0\.s\}, p0/z, \[x0\]
--.*: a530a001 ldnf1sh \{z1\.s\}, p0/z, \[x0\]
--.*: a530a001 ldnf1sh \{z1\.s\}, p0/z, \[x0\]
--.*: a530a001 ldnf1sh \{z1\.s\}, p0/z, \[x0\]
--.*: a530a001 ldnf1sh \{z1\.s\}, p0/z, \[x0\]
--.*: a530a001 ldnf1sh \{z1\.s\}, p0/z, \[x0\]
--.*: a530a01f ldnf1sh \{z31\.s\}, p0/z, \[x0\]
--.*: a530a01f ldnf1sh \{z31\.s\}, p0/z, \[x0\]
--.*: a530a01f ldnf1sh \{z31\.s\}, p0/z, \[x0\]
--.*: a530a01f ldnf1sh \{z31\.s\}, p0/z, \[x0\]
--.*: a530a01f ldnf1sh \{z31\.s\}, p0/z, \[x0\]
--.*: a530a800 ldnf1sh \{z0\.s\}, p2/z, \[x0\]
--.*: a530a800 ldnf1sh \{z0\.s\}, p2/z, \[x0\]
--.*: a530a800 ldnf1sh \{z0\.s\}, p2/z, \[x0\]
--.*: a530a800 ldnf1sh \{z0\.s\}, p2/z, \[x0\]
--.*: a530bc00 ldnf1sh \{z0\.s\}, p7/z, \[x0\]
--.*: a530bc00 ldnf1sh \{z0\.s\}, p7/z, \[x0\]
--.*: a530bc00 ldnf1sh \{z0\.s\}, p7/z, \[x0\]
--.*: a530bc00 ldnf1sh \{z0\.s\}, p7/z, \[x0\]
--.*: a530a060 ldnf1sh \{z0\.s\}, p0/z, \[x3\]
--.*: a530a060 ldnf1sh \{z0\.s\}, p0/z, \[x3\]
--.*: a530a060 ldnf1sh \{z0\.s\}, p0/z, \[x3\]
--.*: a530a060 ldnf1sh \{z0\.s\}, p0/z, \[x3\]
--.*: a530a3e0 ldnf1sh \{z0\.s\}, p0/z, \[sp\]
--.*: a530a3e0 ldnf1sh \{z0\.s\}, p0/z, \[sp\]
--.*: a530a3e0 ldnf1sh \{z0\.s\}, p0/z, \[sp\]
--.*: a530a3e0 ldnf1sh \{z0\.s\}, p0/z, \[sp\]
--.*: a537a000 ldnf1sh \{z0\.s\}, p0/z, \[x0, #7, mul vl\]
--.*: a537a000 ldnf1sh \{z0\.s\}, p0/z, \[x0, #7, mul vl\]
--.*: a538a000 ldnf1sh \{z0\.s\}, p0/z, \[x0, #-8, mul vl\]
--.*: a538a000 ldnf1sh \{z0\.s\}, p0/z, \[x0, #-8, mul vl\]
--.*: a539a000 ldnf1sh \{z0\.s\}, p0/z, \[x0, #-7, mul vl\]
--.*: a539a000 ldnf1sh \{z0\.s\}, p0/z, \[x0, #-7, mul vl\]
--.*: a53fa000 ldnf1sh \{z0\.s\}, p0/z, \[x0, #-1, mul vl\]
--.*: a53fa000 ldnf1sh \{z0\.s\}, p0/z, \[x0, #-1, mul vl\]
--.*: a490a000 ldnf1sw \{z0\.d\}, p0/z, \[x0\]
--.*: a490a000 ldnf1sw \{z0\.d\}, p0/z, \[x0\]
--.*: a490a000 ldnf1sw \{z0\.d\}, p0/z, \[x0\]
--.*: a490a000 ldnf1sw \{z0\.d\}, p0/z, \[x0\]
--.*: a490a000 ldnf1sw \{z0\.d\}, p0/z, \[x0\]
--.*: a490a001 ldnf1sw \{z1\.d\}, p0/z, \[x0\]
--.*: a490a001 ldnf1sw \{z1\.d\}, p0/z, \[x0\]
--.*: a490a001 ldnf1sw \{z1\.d\}, p0/z, \[x0\]
--.*: a490a001 ldnf1sw \{z1\.d\}, p0/z, \[x0\]
--.*: a490a001 ldnf1sw \{z1\.d\}, p0/z, \[x0\]
--.*: a490a01f ldnf1sw \{z31\.d\}, p0/z, \[x0\]
--.*: a490a01f ldnf1sw \{z31\.d\}, p0/z, \[x0\]
--.*: a490a01f ldnf1sw \{z31\.d\}, p0/z, \[x0\]
--.*: a490a01f ldnf1sw \{z31\.d\}, p0/z, \[x0\]
--.*: a490a01f ldnf1sw \{z31\.d\}, p0/z, \[x0\]
--.*: a490a800 ldnf1sw \{z0\.d\}, p2/z, \[x0\]
--.*: a490a800 ldnf1sw \{z0\.d\}, p2/z, \[x0\]
--.*: a490a800 ldnf1sw \{z0\.d\}, p2/z, \[x0\]
--.*: a490a800 ldnf1sw \{z0\.d\}, p2/z, \[x0\]
--.*: a490bc00 ldnf1sw \{z0\.d\}, p7/z, \[x0\]
--.*: a490bc00 ldnf1sw \{z0\.d\}, p7/z, \[x0\]
--.*: a490bc00 ldnf1sw \{z0\.d\}, p7/z, \[x0\]
--.*: a490bc00 ldnf1sw \{z0\.d\}, p7/z, \[x0\]
--.*: a490a060 ldnf1sw \{z0\.d\}, p0/z, \[x3\]
--.*: a490a060 ldnf1sw \{z0\.d\}, p0/z, \[x3\]
--.*: a490a060 ldnf1sw \{z0\.d\}, p0/z, \[x3\]
--.*: a490a060 ldnf1sw \{z0\.d\}, p0/z, \[x3\]
--.*: a490a3e0 ldnf1sw \{z0\.d\}, p0/z, \[sp\]
--.*: a490a3e0 ldnf1sw \{z0\.d\}, p0/z, \[sp\]
--.*: a490a3e0 ldnf1sw \{z0\.d\}, p0/z, \[sp\]
--.*: a490a3e0 ldnf1sw \{z0\.d\}, p0/z, \[sp\]
--.*: a497a000 ldnf1sw \{z0\.d\}, p0/z, \[x0, #7, mul vl\]
--.*: a497a000 ldnf1sw \{z0\.d\}, p0/z, \[x0, #7, mul vl\]
--.*: a498a000 ldnf1sw \{z0\.d\}, p0/z, \[x0, #-8, mul vl\]
--.*: a498a000 ldnf1sw \{z0\.d\}, p0/z, \[x0, #-8, mul vl\]
--.*: a499a000 ldnf1sw \{z0\.d\}, p0/z, \[x0, #-7, mul vl\]
--.*: a499a000 ldnf1sw \{z0\.d\}, p0/z, \[x0, #-7, mul vl\]
--.*: a49fa000 ldnf1sw \{z0\.d\}, p0/z, \[x0, #-1, mul vl\]
--.*: a49fa000 ldnf1sw \{z0\.d\}, p0/z, \[x0, #-1, mul vl\]
--.*: a550a000 ldnf1w \{z0\.s\}, p0/z, \[x0\]
--.*: a550a000 ldnf1w \{z0\.s\}, p0/z, \[x0\]
--.*: a550a000 ldnf1w \{z0\.s\}, p0/z, \[x0\]
--.*: a550a000 ldnf1w \{z0\.s\}, p0/z, \[x0\]
--.*: a550a000 ldnf1w \{z0\.s\}, p0/z, \[x0\]
--.*: a550a001 ldnf1w \{z1\.s\}, p0/z, \[x0\]
--.*: a550a001 ldnf1w \{z1\.s\}, p0/z, \[x0\]
--.*: a550a001 ldnf1w \{z1\.s\}, p0/z, \[x0\]
--.*: a550a001 ldnf1w \{z1\.s\}, p0/z, \[x0\]
--.*: a550a001 ldnf1w \{z1\.s\}, p0/z, \[x0\]
--.*: a550a01f ldnf1w \{z31\.s\}, p0/z, \[x0\]
--.*: a550a01f ldnf1w \{z31\.s\}, p0/z, \[x0\]
--.*: a550a01f ldnf1w \{z31\.s\}, p0/z, \[x0\]
--.*: a550a01f ldnf1w \{z31\.s\}, p0/z, \[x0\]
--.*: a550a01f ldnf1w \{z31\.s\}, p0/z, \[x0\]
--.*: a550a800 ldnf1w \{z0\.s\}, p2/z, \[x0\]
--.*: a550a800 ldnf1w \{z0\.s\}, p2/z, \[x0\]
--.*: a550a800 ldnf1w \{z0\.s\}, p2/z, \[x0\]
--.*: a550a800 ldnf1w \{z0\.s\}, p2/z, \[x0\]
--.*: a550bc00 ldnf1w \{z0\.s\}, p7/z, \[x0\]
--.*: a550bc00 ldnf1w \{z0\.s\}, p7/z, \[x0\]
--.*: a550bc00 ldnf1w \{z0\.s\}, p7/z, \[x0\]
--.*: a550bc00 ldnf1w \{z0\.s\}, p7/z, \[x0\]
--.*: a550a060 ldnf1w \{z0\.s\}, p0/z, \[x3\]
--.*: a550a060 ldnf1w \{z0\.s\}, p0/z, \[x3\]
--.*: a550a060 ldnf1w \{z0\.s\}, p0/z, \[x3\]
--.*: a550a060 ldnf1w \{z0\.s\}, p0/z, \[x3\]
--.*: a550a3e0 ldnf1w \{z0\.s\}, p0/z, \[sp\]
--.*: a550a3e0 ldnf1w \{z0\.s\}, p0/z, \[sp\]
--.*: a550a3e0 ldnf1w \{z0\.s\}, p0/z, \[sp\]
--.*: a550a3e0 ldnf1w \{z0\.s\}, p0/z, \[sp\]
--.*: a557a000 ldnf1w \{z0\.s\}, p0/z, \[x0, #7, mul vl\]
--.*: a557a000 ldnf1w \{z0\.s\}, p0/z, \[x0, #7, mul vl\]
--.*: a558a000 ldnf1w \{z0\.s\}, p0/z, \[x0, #-8, mul vl\]
--.*: a558a000 ldnf1w \{z0\.s\}, p0/z, \[x0, #-8, mul vl\]
--.*: a559a000 ldnf1w \{z0\.s\}, p0/z, \[x0, #-7, mul vl\]
--.*: a559a000 ldnf1w \{z0\.s\}, p0/z, \[x0, #-7, mul vl\]
--.*: a55fa000 ldnf1w \{z0\.s\}, p0/z, \[x0, #-1, mul vl\]
--.*: a55fa000 ldnf1w \{z0\.s\}, p0/z, \[x0, #-1, mul vl\]
--.*: a570a000 ldnf1w \{z0\.d\}, p0/z, \[x0\]
--.*: a570a000 ldnf1w \{z0\.d\}, p0/z, \[x0\]
--.*: a570a000 ldnf1w \{z0\.d\}, p0/z, \[x0\]
--.*: a570a000 ldnf1w \{z0\.d\}, p0/z, \[x0\]
--.*: a570a000 ldnf1w \{z0\.d\}, p0/z, \[x0\]
--.*: a570a001 ldnf1w \{z1\.d\}, p0/z, \[x0\]
--.*: a570a001 ldnf1w \{z1\.d\}, p0/z, \[x0\]
--.*: a570a001 ldnf1w \{z1\.d\}, p0/z, \[x0\]
--.*: a570a001 ldnf1w \{z1\.d\}, p0/z, \[x0\]
--.*: a570a001 ldnf1w \{z1\.d\}, p0/z, \[x0\]
--.*: a570a01f ldnf1w \{z31\.d\}, p0/z, \[x0\]
--.*: a570a01f ldnf1w \{z31\.d\}, p0/z, \[x0\]
--.*: a570a01f ldnf1w \{z31\.d\}, p0/z, \[x0\]
--.*: a570a01f ldnf1w \{z31\.d\}, p0/z, \[x0\]
--.*: a570a01f ldnf1w \{z31\.d\}, p0/z, \[x0\]
--.*: a570a800 ldnf1w \{z0\.d\}, p2/z, \[x0\]
--.*: a570a800 ldnf1w \{z0\.d\}, p2/z, \[x0\]
--.*: a570a800 ldnf1w \{z0\.d\}, p2/z, \[x0\]
--.*: a570a800 ldnf1w \{z0\.d\}, p2/z, \[x0\]
--.*: a570bc00 ldnf1w \{z0\.d\}, p7/z, \[x0\]
--.*: a570bc00 ldnf1w \{z0\.d\}, p7/z, \[x0\]
--.*: a570bc00 ldnf1w \{z0\.d\}, p7/z, \[x0\]
--.*: a570bc00 ldnf1w \{z0\.d\}, p7/z, \[x0\]
--.*: a570a060 ldnf1w \{z0\.d\}, p0/z, \[x3\]
--.*: a570a060 ldnf1w \{z0\.d\}, p0/z, \[x3\]
--.*: a570a060 ldnf1w \{z0\.d\}, p0/z, \[x3\]
--.*: a570a060 ldnf1w \{z0\.d\}, p0/z, \[x3\]
--.*: a570a3e0 ldnf1w \{z0\.d\}, p0/z, \[sp\]
--.*: a570a3e0 ldnf1w \{z0\.d\}, p0/z, \[sp\]
--.*: a570a3e0 ldnf1w \{z0\.d\}, p0/z, \[sp\]
--.*: a570a3e0 ldnf1w \{z0\.d\}, p0/z, \[sp\]
--.*: a577a000 ldnf1w \{z0\.d\}, p0/z, \[x0, #7, mul vl\]
--.*: a577a000 ldnf1w \{z0\.d\}, p0/z, \[x0, #7, mul vl\]
--.*: a578a000 ldnf1w \{z0\.d\}, p0/z, \[x0, #-8, mul vl\]
--.*: a578a000 ldnf1w \{z0\.d\}, p0/z, \[x0, #-8, mul vl\]
--.*: a579a000 ldnf1w \{z0\.d\}, p0/z, \[x0, #-7, mul vl\]
--.*: a579a000 ldnf1w \{z0\.d\}, p0/z, \[x0, #-7, mul vl\]
--.*: a57fa000 ldnf1w \{z0\.d\}, p0/z, \[x0, #-1, mul vl\]
--.*: a57fa000 ldnf1w \{z0\.d\}, p0/z, \[x0, #-1, mul vl\]
--.*: a400c000 ldnt1b \{z0\.b\}, p0/z, \[x0, x0\]
--.*: a400c000 ldnt1b \{z0\.b\}, p0/z, \[x0, x0\]
--.*: a400c000 ldnt1b \{z0\.b\}, p0/z, \[x0, x0\]
--.*: a400c000 ldnt1b \{z0\.b\}, p0/z, \[x0, x0\]
--.*: a400c001 ldnt1b \{z1\.b\}, p0/z, \[x0, x0\]
--.*: a400c001 ldnt1b \{z1\.b\}, p0/z, \[x0, x0\]
--.*: a400c001 ldnt1b \{z1\.b\}, p0/z, \[x0, x0\]
--.*: a400c001 ldnt1b \{z1\.b\}, p0/z, \[x0, x0\]
--.*: a400c01f ldnt1b \{z31\.b\}, p0/z, \[x0, x0\]
--.*: a400c01f ldnt1b \{z31\.b\}, p0/z, \[x0, x0\]
--.*: a400c01f ldnt1b \{z31\.b\}, p0/z, \[x0, x0\]
--.*: a400c01f ldnt1b \{z31\.b\}, p0/z, \[x0, x0\]
--.*: a400c800 ldnt1b \{z0\.b\}, p2/z, \[x0, x0\]
--.*: a400c800 ldnt1b \{z0\.b\}, p2/z, \[x0, x0\]
--.*: a400c800 ldnt1b \{z0\.b\}, p2/z, \[x0, x0\]
--.*: a400dc00 ldnt1b \{z0\.b\}, p7/z, \[x0, x0\]
--.*: a400dc00 ldnt1b \{z0\.b\}, p7/z, \[x0, x0\]
--.*: a400dc00 ldnt1b \{z0\.b\}, p7/z, \[x0, x0\]
--.*: a400c060 ldnt1b \{z0\.b\}, p0/z, \[x3, x0\]
--.*: a400c060 ldnt1b \{z0\.b\}, p0/z, \[x3, x0\]
--.*: a400c060 ldnt1b \{z0\.b\}, p0/z, \[x3, x0\]
--.*: a400c3e0 ldnt1b \{z0\.b\}, p0/z, \[sp, x0\]
--.*: a400c3e0 ldnt1b \{z0\.b\}, p0/z, \[sp, x0\]
--.*: a400c3e0 ldnt1b \{z0\.b\}, p0/z, \[sp, x0\]
--.*: a404c000 ldnt1b \{z0\.b\}, p0/z, \[x0, x4\]
--.*: a404c000 ldnt1b \{z0\.b\}, p0/z, \[x0, x4\]
--.*: a404c000 ldnt1b \{z0\.b\}, p0/z, \[x0, x4\]
--.*: a41ec000 ldnt1b \{z0\.b\}, p0/z, \[x0, x30\]
--.*: a41ec000 ldnt1b \{z0\.b\}, p0/z, \[x0, x30\]
--.*: a41ec000 ldnt1b \{z0\.b\}, p0/z, \[x0, x30\]
--.*: a400e000 ldnt1b \{z0\.b\}, p0/z, \[x0\]
--.*: a400e000 ldnt1b \{z0\.b\}, p0/z, \[x0\]
--.*: a400e000 ldnt1b \{z0\.b\}, p0/z, \[x0\]
--.*: a400e000 ldnt1b \{z0\.b\}, p0/z, \[x0\]
--.*: a400e000 ldnt1b \{z0\.b\}, p0/z, \[x0\]
--.*: a400e001 ldnt1b \{z1\.b\}, p0/z, \[x0\]
--.*: a400e001 ldnt1b \{z1\.b\}, p0/z, \[x0\]
--.*: a400e001 ldnt1b \{z1\.b\}, p0/z, \[x0\]
--.*: a400e001 ldnt1b \{z1\.b\}, p0/z, \[x0\]
--.*: a400e001 ldnt1b \{z1\.b\}, p0/z, \[x0\]
--.*: a400e01f ldnt1b \{z31\.b\}, p0/z, \[x0\]
--.*: a400e01f ldnt1b \{z31\.b\}, p0/z, \[x0\]
--.*: a400e01f ldnt1b \{z31\.b\}, p0/z, \[x0\]
--.*: a400e01f ldnt1b \{z31\.b\}, p0/z, \[x0\]
--.*: a400e01f ldnt1b \{z31\.b\}, p0/z, \[x0\]
--.*: a400e800 ldnt1b \{z0\.b\}, p2/z, \[x0\]
--.*: a400e800 ldnt1b \{z0\.b\}, p2/z, \[x0\]
--.*: a400e800 ldnt1b \{z0\.b\}, p2/z, \[x0\]
--.*: a400e800 ldnt1b \{z0\.b\}, p2/z, \[x0\]
--.*: a400fc00 ldnt1b \{z0\.b\}, p7/z, \[x0\]
--.*: a400fc00 ldnt1b \{z0\.b\}, p7/z, \[x0\]
--.*: a400fc00 ldnt1b \{z0\.b\}, p7/z, \[x0\]
--.*: a400fc00 ldnt1b \{z0\.b\}, p7/z, \[x0\]
--.*: a400e060 ldnt1b \{z0\.b\}, p0/z, \[x3\]
--.*: a400e060 ldnt1b \{z0\.b\}, p0/z, \[x3\]
--.*: a400e060 ldnt1b \{z0\.b\}, p0/z, \[x3\]
--.*: a400e060 ldnt1b \{z0\.b\}, p0/z, \[x3\]
--.*: a400e3e0 ldnt1b \{z0\.b\}, p0/z, \[sp\]
--.*: a400e3e0 ldnt1b \{z0\.b\}, p0/z, \[sp\]
--.*: a400e3e0 ldnt1b \{z0\.b\}, p0/z, \[sp\]
--.*: a400e3e0 ldnt1b \{z0\.b\}, p0/z, \[sp\]
--.*: a407e000 ldnt1b \{z0\.b\}, p0/z, \[x0, #7, mul vl\]
--.*: a407e000 ldnt1b \{z0\.b\}, p0/z, \[x0, #7, mul vl\]
--.*: a408e000 ldnt1b \{z0\.b\}, p0/z, \[x0, #-8, mul vl\]
--.*: a408e000 ldnt1b \{z0\.b\}, p0/z, \[x0, #-8, mul vl\]
--.*: a409e000 ldnt1b \{z0\.b\}, p0/z, \[x0, #-7, mul vl\]
--.*: a409e000 ldnt1b \{z0\.b\}, p0/z, \[x0, #-7, mul vl\]
--.*: a40fe000 ldnt1b \{z0\.b\}, p0/z, \[x0, #-1, mul vl\]
--.*: a40fe000 ldnt1b \{z0\.b\}, p0/z, \[x0, #-1, mul vl\]
--.*: a580c000 ldnt1d \{z0\.d\}, p0/z, \[x0, x0, lsl #3\]
--.*: a580c000 ldnt1d \{z0\.d\}, p0/z, \[x0, x0, lsl #3\]
--.*: a580c000 ldnt1d \{z0\.d\}, p0/z, \[x0, x0, lsl #3\]
--.*: a580c001 ldnt1d \{z1\.d\}, p0/z, \[x0, x0, lsl #3\]
--.*: a580c001 ldnt1d \{z1\.d\}, p0/z, \[x0, x0, lsl #3\]
--.*: a580c001 ldnt1d \{z1\.d\}, p0/z, \[x0, x0, lsl #3\]
--.*: a580c01f ldnt1d \{z31\.d\}, p0/z, \[x0, x0, lsl #3\]
--.*: a580c01f ldnt1d \{z31\.d\}, p0/z, \[x0, x0, lsl #3\]
--.*: a580c01f ldnt1d \{z31\.d\}, p0/z, \[x0, x0, lsl #3\]
--.*: a580c800 ldnt1d \{z0\.d\}, p2/z, \[x0, x0, lsl #3\]
--.*: a580c800 ldnt1d \{z0\.d\}, p2/z, \[x0, x0, lsl #3\]
--.*: a580dc00 ldnt1d \{z0\.d\}, p7/z, \[x0, x0, lsl #3\]
--.*: a580dc00 ldnt1d \{z0\.d\}, p7/z, \[x0, x0, lsl #3\]
--.*: a580c060 ldnt1d \{z0\.d\}, p0/z, \[x3, x0, lsl #3\]
--.*: a580c060 ldnt1d \{z0\.d\}, p0/z, \[x3, x0, lsl #3\]
--.*: a580c3e0 ldnt1d \{z0\.d\}, p0/z, \[sp, x0, lsl #3\]
--.*: a580c3e0 ldnt1d \{z0\.d\}, p0/z, \[sp, x0, lsl #3\]
--.*: a584c000 ldnt1d \{z0\.d\}, p0/z, \[x0, x4, lsl #3\]
--.*: a584c000 ldnt1d \{z0\.d\}, p0/z, \[x0, x4, lsl #3\]
--.*: a59ec000 ldnt1d \{z0\.d\}, p0/z, \[x0, x30, lsl #3\]
--.*: a59ec000 ldnt1d \{z0\.d\}, p0/z, \[x0, x30, lsl #3\]
--.*: a580e000 ldnt1d \{z0\.d\}, p0/z, \[x0\]
--.*: a580e000 ldnt1d \{z0\.d\}, p0/z, \[x0\]
--.*: a580e000 ldnt1d \{z0\.d\}, p0/z, \[x0\]
--.*: a580e000 ldnt1d \{z0\.d\}, p0/z, \[x0\]
--.*: a580e000 ldnt1d \{z0\.d\}, p0/z, \[x0\]
--.*: a580e001 ldnt1d \{z1\.d\}, p0/z, \[x0\]
--.*: a580e001 ldnt1d \{z1\.d\}, p0/z, \[x0\]
--.*: a580e001 ldnt1d \{z1\.d\}, p0/z, \[x0\]
--.*: a580e001 ldnt1d \{z1\.d\}, p0/z, \[x0\]
--.*: a580e001 ldnt1d \{z1\.d\}, p0/z, \[x0\]
--.*: a580e01f ldnt1d \{z31\.d\}, p0/z, \[x0\]
--.*: a580e01f ldnt1d \{z31\.d\}, p0/z, \[x0\]
--.*: a580e01f ldnt1d \{z31\.d\}, p0/z, \[x0\]
--.*: a580e01f ldnt1d \{z31\.d\}, p0/z, \[x0\]
--.*: a580e01f ldnt1d \{z31\.d\}, p0/z, \[x0\]
--.*: a580e800 ldnt1d \{z0\.d\}, p2/z, \[x0\]
--.*: a580e800 ldnt1d \{z0\.d\}, p2/z, \[x0\]
--.*: a580e800 ldnt1d \{z0\.d\}, p2/z, \[x0\]
--.*: a580e800 ldnt1d \{z0\.d\}, p2/z, \[x0\]
--.*: a580fc00 ldnt1d \{z0\.d\}, p7/z, \[x0\]
--.*: a580fc00 ldnt1d \{z0\.d\}, p7/z, \[x0\]
--.*: a580fc00 ldnt1d \{z0\.d\}, p7/z, \[x0\]
--.*: a580fc00 ldnt1d \{z0\.d\}, p7/z, \[x0\]
--.*: a580e060 ldnt1d \{z0\.d\}, p0/z, \[x3\]
--.*: a580e060 ldnt1d \{z0\.d\}, p0/z, \[x3\]
--.*: a580e060 ldnt1d \{z0\.d\}, p0/z, \[x3\]
--.*: a580e060 ldnt1d \{z0\.d\}, p0/z, \[x3\]
--.*: a580e3e0 ldnt1d \{z0\.d\}, p0/z, \[sp\]
--.*: a580e3e0 ldnt1d \{z0\.d\}, p0/z, \[sp\]
--.*: a580e3e0 ldnt1d \{z0\.d\}, p0/z, \[sp\]
--.*: a580e3e0 ldnt1d \{z0\.d\}, p0/z, \[sp\]
--.*: a587e000 ldnt1d \{z0\.d\}, p0/z, \[x0, #7, mul vl\]
--.*: a587e000 ldnt1d \{z0\.d\}, p0/z, \[x0, #7, mul vl\]
--.*: a588e000 ldnt1d \{z0\.d\}, p0/z, \[x0, #-8, mul vl\]
--.*: a588e000 ldnt1d \{z0\.d\}, p0/z, \[x0, #-8, mul vl\]
--.*: a589e000 ldnt1d \{z0\.d\}, p0/z, \[x0, #-7, mul vl\]
--.*: a589e000 ldnt1d \{z0\.d\}, p0/z, \[x0, #-7, mul vl\]
--.*: a58fe000 ldnt1d \{z0\.d\}, p0/z, \[x0, #-1, mul vl\]
--.*: a58fe000 ldnt1d \{z0\.d\}, p0/z, \[x0, #-1, mul vl\]
--.*: a480c000 ldnt1h \{z0\.h\}, p0/z, \[x0, x0, lsl #1\]
--.*: a480c000 ldnt1h \{z0\.h\}, p0/z, \[x0, x0, lsl #1\]
--.*: a480c000 ldnt1h \{z0\.h\}, p0/z, \[x0, x0, lsl #1\]
--.*: a480c001 ldnt1h \{z1\.h\}, p0/z, \[x0, x0, lsl #1\]
--.*: a480c001 ldnt1h \{z1\.h\}, p0/z, \[x0, x0, lsl #1\]
--.*: a480c001 ldnt1h \{z1\.h\}, p0/z, \[x0, x0, lsl #1\]
--.*: a480c01f ldnt1h \{z31\.h\}, p0/z, \[x0, x0, lsl #1\]
--.*: a480c01f ldnt1h \{z31\.h\}, p0/z, \[x0, x0, lsl #1\]
--.*: a480c01f ldnt1h \{z31\.h\}, p0/z, \[x0, x0, lsl #1\]
--.*: a480c800 ldnt1h \{z0\.h\}, p2/z, \[x0, x0, lsl #1\]
--.*: a480c800 ldnt1h \{z0\.h\}, p2/z, \[x0, x0, lsl #1\]
--.*: a480dc00 ldnt1h \{z0\.h\}, p7/z, \[x0, x0, lsl #1\]
--.*: a480dc00 ldnt1h \{z0\.h\}, p7/z, \[x0, x0, lsl #1\]
--.*: a480c060 ldnt1h \{z0\.h\}, p0/z, \[x3, x0, lsl #1\]
--.*: a480c060 ldnt1h \{z0\.h\}, p0/z, \[x3, x0, lsl #1\]
--.*: a480c3e0 ldnt1h \{z0\.h\}, p0/z, \[sp, x0, lsl #1\]
--.*: a480c3e0 ldnt1h \{z0\.h\}, p0/z, \[sp, x0, lsl #1\]
--.*: a484c000 ldnt1h \{z0\.h\}, p0/z, \[x0, x4, lsl #1\]
--.*: a484c000 ldnt1h \{z0\.h\}, p0/z, \[x0, x4, lsl #1\]
--.*: a49ec000 ldnt1h \{z0\.h\}, p0/z, \[x0, x30, lsl #1\]
--.*: a49ec000 ldnt1h \{z0\.h\}, p0/z, \[x0, x30, lsl #1\]
--.*: a480e000 ldnt1h \{z0\.h\}, p0/z, \[x0\]
--.*: a480e000 ldnt1h \{z0\.h\}, p0/z, \[x0\]
--.*: a480e000 ldnt1h \{z0\.h\}, p0/z, \[x0\]
--.*: a480e000 ldnt1h \{z0\.h\}, p0/z, \[x0\]
--.*: a480e000 ldnt1h \{z0\.h\}, p0/z, \[x0\]
--.*: a480e001 ldnt1h \{z1\.h\}, p0/z, \[x0\]
--.*: a480e001 ldnt1h \{z1\.h\}, p0/z, \[x0\]
--.*: a480e001 ldnt1h \{z1\.h\}, p0/z, \[x0\]
--.*: a480e001 ldnt1h \{z1\.h\}, p0/z, \[x0\]
--.*: a480e001 ldnt1h \{z1\.h\}, p0/z, \[x0\]
--.*: a480e01f ldnt1h \{z31\.h\}, p0/z, \[x0\]
--.*: a480e01f ldnt1h \{z31\.h\}, p0/z, \[x0\]
--.*: a480e01f ldnt1h \{z31\.h\}, p0/z, \[x0\]
--.*: a480e01f ldnt1h \{z31\.h\}, p0/z, \[x0\]
--.*: a480e01f ldnt1h \{z31\.h\}, p0/z, \[x0\]
--.*: a480e800 ldnt1h \{z0\.h\}, p2/z, \[x0\]
--.*: a480e800 ldnt1h \{z0\.h\}, p2/z, \[x0\]
--.*: a480e800 ldnt1h \{z0\.h\}, p2/z, \[x0\]
--.*: a480e800 ldnt1h \{z0\.h\}, p2/z, \[x0\]
--.*: a480fc00 ldnt1h \{z0\.h\}, p7/z, \[x0\]
--.*: a480fc00 ldnt1h \{z0\.h\}, p7/z, \[x0\]
--.*: a480fc00 ldnt1h \{z0\.h\}, p7/z, \[x0\]
--.*: a480fc00 ldnt1h \{z0\.h\}, p7/z, \[x0\]
--.*: a480e060 ldnt1h \{z0\.h\}, p0/z, \[x3\]
--.*: a480e060 ldnt1h \{z0\.h\}, p0/z, \[x3\]
--.*: a480e060 ldnt1h \{z0\.h\}, p0/z, \[x3\]
--.*: a480e060 ldnt1h \{z0\.h\}, p0/z, \[x3\]
--.*: a480e3e0 ldnt1h \{z0\.h\}, p0/z, \[sp\]
--.*: a480e3e0 ldnt1h \{z0\.h\}, p0/z, \[sp\]
--.*: a480e3e0 ldnt1h \{z0\.h\}, p0/z, \[sp\]
--.*: a480e3e0 ldnt1h \{z0\.h\}, p0/z, \[sp\]
--.*: a487e000 ldnt1h \{z0\.h\}, p0/z, \[x0, #7, mul vl\]
--.*: a487e000 ldnt1h \{z0\.h\}, p0/z, \[x0, #7, mul vl\]
--.*: a488e000 ldnt1h \{z0\.h\}, p0/z, \[x0, #-8, mul vl\]
--.*: a488e000 ldnt1h \{z0\.h\}, p0/z, \[x0, #-8, mul vl\]
--.*: a489e000 ldnt1h \{z0\.h\}, p0/z, \[x0, #-7, mul vl\]
--.*: a489e000 ldnt1h \{z0\.h\}, p0/z, \[x0, #-7, mul vl\]
--.*: a48fe000 ldnt1h \{z0\.h\}, p0/z, \[x0, #-1, mul vl\]
--.*: a48fe000 ldnt1h \{z0\.h\}, p0/z, \[x0, #-1, mul vl\]
--.*: a500c000 ldnt1w \{z0\.s\}, p0/z, \[x0, x0, lsl #2\]
--.*: a500c000 ldnt1w \{z0\.s\}, p0/z, \[x0, x0, lsl #2\]
--.*: a500c000 ldnt1w \{z0\.s\}, p0/z, \[x0, x0, lsl #2\]
--.*: a500c001 ldnt1w \{z1\.s\}, p0/z, \[x0, x0, lsl #2\]
--.*: a500c001 ldnt1w \{z1\.s\}, p0/z, \[x0, x0, lsl #2\]
--.*: a500c001 ldnt1w \{z1\.s\}, p0/z, \[x0, x0, lsl #2\]
--.*: a500c01f ldnt1w \{z31\.s\}, p0/z, \[x0, x0, lsl #2\]
--.*: a500c01f ldnt1w \{z31\.s\}, p0/z, \[x0, x0, lsl #2\]
--.*: a500c01f ldnt1w \{z31\.s\}, p0/z, \[x0, x0, lsl #2\]
--.*: a500c800 ldnt1w \{z0\.s\}, p2/z, \[x0, x0, lsl #2\]
--.*: a500c800 ldnt1w \{z0\.s\}, p2/z, \[x0, x0, lsl #2\]
--.*: a500dc00 ldnt1w \{z0\.s\}, p7/z, \[x0, x0, lsl #2\]
--.*: a500dc00 ldnt1w \{z0\.s\}, p7/z, \[x0, x0, lsl #2\]
--.*: a500c060 ldnt1w \{z0\.s\}, p0/z, \[x3, x0, lsl #2\]
--.*: a500c060 ldnt1w \{z0\.s\}, p0/z, \[x3, x0, lsl #2\]
--.*: a500c3e0 ldnt1w \{z0\.s\}, p0/z, \[sp, x0, lsl #2\]
--.*: a500c3e0 ldnt1w \{z0\.s\}, p0/z, \[sp, x0, lsl #2\]
--.*: a504c000 ldnt1w \{z0\.s\}, p0/z, \[x0, x4, lsl #2\]
--.*: a504c000 ldnt1w \{z0\.s\}, p0/z, \[x0, x4, lsl #2\]
--.*: a51ec000 ldnt1w \{z0\.s\}, p0/z, \[x0, x30, lsl #2\]
--.*: a51ec000 ldnt1w \{z0\.s\}, p0/z, \[x0, x30, lsl #2\]
--.*: a500e000 ldnt1w \{z0\.s\}, p0/z, \[x0\]
--.*: a500e000 ldnt1w \{z0\.s\}, p0/z, \[x0\]
--.*: a500e000 ldnt1w \{z0\.s\}, p0/z, \[x0\]
--.*: a500e000 ldnt1w \{z0\.s\}, p0/z, \[x0\]
--.*: a500e000 ldnt1w \{z0\.s\}, p0/z, \[x0\]
--.*: a500e001 ldnt1w \{z1\.s\}, p0/z, \[x0\]
--.*: a500e001 ldnt1w \{z1\.s\}, p0/z, \[x0\]
--.*: a500e001 ldnt1w \{z1\.s\}, p0/z, \[x0\]
--.*: a500e001 ldnt1w \{z1\.s\}, p0/z, \[x0\]
--.*: a500e001 ldnt1w \{z1\.s\}, p0/z, \[x0\]
--.*: a500e01f ldnt1w \{z31\.s\}, p0/z, \[x0\]
--.*: a500e01f ldnt1w \{z31\.s\}, p0/z, \[x0\]
--.*: a500e01f ldnt1w \{z31\.s\}, p0/z, \[x0\]
--.*: a500e01f ldnt1w \{z31\.s\}, p0/z, \[x0\]
--.*: a500e01f ldnt1w \{z31\.s\}, p0/z, \[x0\]
--.*: a500e800 ldnt1w \{z0\.s\}, p2/z, \[x0\]
--.*: a500e800 ldnt1w \{z0\.s\}, p2/z, \[x0\]
--.*: a500e800 ldnt1w \{z0\.s\}, p2/z, \[x0\]
--.*: a500e800 ldnt1w \{z0\.s\}, p2/z, \[x0\]
--.*: a500fc00 ldnt1w \{z0\.s\}, p7/z, \[x0\]
--.*: a500fc00 ldnt1w \{z0\.s\}, p7/z, \[x0\]
--.*: a500fc00 ldnt1w \{z0\.s\}, p7/z, \[x0\]
--.*: a500fc00 ldnt1w \{z0\.s\}, p7/z, \[x0\]
--.*: a500e060 ldnt1w \{z0\.s\}, p0/z, \[x3\]
--.*: a500e060 ldnt1w \{z0\.s\}, p0/z, \[x3\]
--.*: a500e060 ldnt1w \{z0\.s\}, p0/z, \[x3\]
--.*: a500e060 ldnt1w \{z0\.s\}, p0/z, \[x3\]
--.*: a500e3e0 ldnt1w \{z0\.s\}, p0/z, \[sp\]
--.*: a500e3e0 ldnt1w \{z0\.s\}, p0/z, \[sp\]
--.*: a500e3e0 ldnt1w \{z0\.s\}, p0/z, \[sp\]
--.*: a500e3e0 ldnt1w \{z0\.s\}, p0/z, \[sp\]
--.*: a507e000 ldnt1w \{z0\.s\}, p0/z, \[x0, #7, mul vl\]
--.*: a507e000 ldnt1w \{z0\.s\}, p0/z, \[x0, #7, mul vl\]
--.*: a508e000 ldnt1w \{z0\.s\}, p0/z, \[x0, #-8, mul vl\]
--.*: a508e000 ldnt1w \{z0\.s\}, p0/z, \[x0, #-8, mul vl\]
--.*: a509e000 ldnt1w \{z0\.s\}, p0/z, \[x0, #-7, mul vl\]
--.*: a509e000 ldnt1w \{z0\.s\}, p0/z, \[x0, #-7, mul vl\]
--.*: a50fe000 ldnt1w \{z0\.s\}, p0/z, \[x0, #-1, mul vl\]
--.*: a50fe000 ldnt1w \{z0\.s\}, p0/z, \[x0, #-1, mul vl\]
--.*: 85800000 ldr p0, \[x0\]
--.*: 85800000 ldr p0, \[x0\]
--.*: 85800000 ldr p0, \[x0\]
--.*: 85800000 ldr p0, \[x0\]
--.*: 85800001 ldr p1, \[x0\]
--.*: 85800001 ldr p1, \[x0\]
--.*: 85800001 ldr p1, \[x0\]
--.*: 85800001 ldr p1, \[x0\]
--.*: 8580000f ldr p15, \[x0\]
--.*: 8580000f ldr p15, \[x0\]
--.*: 8580000f ldr p15, \[x0\]
--.*: 8580000f ldr p15, \[x0\]
--.*: 85800040 ldr p0, \[x2\]
--.*: 85800040 ldr p0, \[x2\]
--.*: 85800040 ldr p0, \[x2\]
--.*: 85800040 ldr p0, \[x2\]
--.*: 858003e0 ldr p0, \[sp\]
--.*: 858003e0 ldr p0, \[sp\]
--.*: 858003e0 ldr p0, \[sp\]
--.*: 858003e0 ldr p0, \[sp\]
--.*: 859f1c00 ldr p0, \[x0, #255, mul vl\]
--.*: 859f1c00 ldr p0, \[x0, #255, mul vl\]
--.*: 85a00000 ldr p0, \[x0, #-256, mul vl\]
--.*: 85a00000 ldr p0, \[x0, #-256, mul vl\]
--.*: 85a00400 ldr p0, \[x0, #-255, mul vl\]
--.*: 85a00400 ldr p0, \[x0, #-255, mul vl\]
--.*: 85bf1c00 ldr p0, \[x0, #-1, mul vl\]
--.*: 85bf1c00 ldr p0, \[x0, #-1, mul vl\]
--.*: 85804000 ldr z0, \[x0\]
--.*: 85804000 ldr z0, \[x0\]
--.*: 85804000 ldr z0, \[x0\]
--.*: 85804000 ldr z0, \[x0\]
--.*: 85804001 ldr z1, \[x0\]
--.*: 85804001 ldr z1, \[x0\]
--.*: 85804001 ldr z1, \[x0\]
--.*: 85804001 ldr z1, \[x0\]
--.*: 8580401f ldr z31, \[x0\]
--.*: 8580401f ldr z31, \[x0\]
--.*: 8580401f ldr z31, \[x0\]
--.*: 8580401f ldr z31, \[x0\]
--.*: 85804040 ldr z0, \[x2\]
--.*: 85804040 ldr z0, \[x2\]
--.*: 85804040 ldr z0, \[x2\]
--.*: 85804040 ldr z0, \[x2\]
--.*: 858043e0 ldr z0, \[sp\]
--.*: 858043e0 ldr z0, \[sp\]
--.*: 858043e0 ldr z0, \[sp\]
--.*: 858043e0 ldr z0, \[sp\]
--.*: 859f5c00 ldr z0, \[x0, #255, mul vl\]
--.*: 859f5c00 ldr z0, \[x0, #255, mul vl\]
--.*: 85a04000 ldr z0, \[x0, #-256, mul vl\]
--.*: 85a04000 ldr z0, \[x0, #-256, mul vl\]
--.*: 85a04400 ldr z0, \[x0, #-255, mul vl\]
--.*: 85a04400 ldr z0, \[x0, #-255, mul vl\]
--.*: 85bf5c00 ldr z0, \[x0, #-1, mul vl\]
--.*: 85bf5c00 ldr z0, \[x0, #-1, mul vl\]
--.*: 04208c00 lsl z0\.b, z0\.b, z0\.d
--.*: 04208c00 lsl z0\.b, z0\.b, z0\.d
--.*: 04208c01 lsl z1\.b, z0\.b, z0\.d
--.*: 04208c01 lsl z1\.b, z0\.b, z0\.d
--.*: 04208c1f lsl z31\.b, z0\.b, z0\.d
--.*: 04208c1f lsl z31\.b, z0\.b, z0\.d
--.*: 04208c40 lsl z0\.b, z2\.b, z0\.d
--.*: 04208c40 lsl z0\.b, z2\.b, z0\.d
--.*: 04208fe0 lsl z0\.b, z31\.b, z0\.d
--.*: 04208fe0 lsl z0\.b, z31\.b, z0\.d
--.*: 04238c00 lsl z0\.b, z0\.b, z3\.d
--.*: 04238c00 lsl z0\.b, z0\.b, z3\.d
--.*: 043f8c00 lsl z0\.b, z0\.b, z31\.d
--.*: 043f8c00 lsl z0\.b, z0\.b, z31\.d
--.*: 04608c00 lsl z0\.h, z0\.h, z0\.d
--.*: 04608c00 lsl z0\.h, z0\.h, z0\.d
--.*: 04608c01 lsl z1\.h, z0\.h, z0\.d
--.*: 04608c01 lsl z1\.h, z0\.h, z0\.d
--.*: 04608c1f lsl z31\.h, z0\.h, z0\.d
--.*: 04608c1f lsl z31\.h, z0\.h, z0\.d
--.*: 04608c40 lsl z0\.h, z2\.h, z0\.d
--.*: 04608c40 lsl z0\.h, z2\.h, z0\.d
--.*: 04608fe0 lsl z0\.h, z31\.h, z0\.d
--.*: 04608fe0 lsl z0\.h, z31\.h, z0\.d
--.*: 04638c00 lsl z0\.h, z0\.h, z3\.d
--.*: 04638c00 lsl z0\.h, z0\.h, z3\.d
--.*: 047f8c00 lsl z0\.h, z0\.h, z31\.d
--.*: 047f8c00 lsl z0\.h, z0\.h, z31\.d
--.*: 04a08c00 lsl z0\.s, z0\.s, z0\.d
--.*: 04a08c00 lsl z0\.s, z0\.s, z0\.d
--.*: 04a08c01 lsl z1\.s, z0\.s, z0\.d
--.*: 04a08c01 lsl z1\.s, z0\.s, z0\.d
--.*: 04a08c1f lsl z31\.s, z0\.s, z0\.d
--.*: 04a08c1f lsl z31\.s, z0\.s, z0\.d
--.*: 04a08c40 lsl z0\.s, z2\.s, z0\.d
--.*: 04a08c40 lsl z0\.s, z2\.s, z0\.d
--.*: 04a08fe0 lsl z0\.s, z31\.s, z0\.d
--.*: 04a08fe0 lsl z0\.s, z31\.s, z0\.d
--.*: 04a38c00 lsl z0\.s, z0\.s, z3\.d
--.*: 04a38c00 lsl z0\.s, z0\.s, z3\.d
--.*: 04bf8c00 lsl z0\.s, z0\.s, z31\.d
--.*: 04bf8c00 lsl z0\.s, z0\.s, z31\.d
--.*: 04289c00 lsl z0\.b, z0\.b, #0
--.*: 04289c00 lsl z0\.b, z0\.b, #0
--.*: 04289c01 lsl z1\.b, z0\.b, #0
--.*: 04289c01 lsl z1\.b, z0\.b, #0
--.*: 04289c1f lsl z31\.b, z0\.b, #0
--.*: 04289c1f lsl z31\.b, z0\.b, #0
--.*: 04289c40 lsl z0\.b, z2\.b, #0
--.*: 04289c40 lsl z0\.b, z2\.b, #0
--.*: 04289fe0 lsl z0\.b, z31\.b, #0
--.*: 04289fe0 lsl z0\.b, z31\.b, #0
--.*: 04299c00 lsl z0\.b, z0\.b, #1
--.*: 04299c00 lsl z0\.b, z0\.b, #1
--.*: 042e9c00 lsl z0\.b, z0\.b, #6
--.*: 042e9c00 lsl z0\.b, z0\.b, #6
--.*: 042f9c00 lsl z0\.b, z0\.b, #7
--.*: 042f9c00 lsl z0\.b, z0\.b, #7
--.*: 04309c00 lsl z0\.h, z0\.h, #0
--.*: 04309c00 lsl z0\.h, z0\.h, #0
--.*: 04309c01 lsl z1\.h, z0\.h, #0
--.*: 04309c01 lsl z1\.h, z0\.h, #0
--.*: 04309c1f lsl z31\.h, z0\.h, #0
--.*: 04309c1f lsl z31\.h, z0\.h, #0
--.*: 04309c40 lsl z0\.h, z2\.h, #0
--.*: 04309c40 lsl z0\.h, z2\.h, #0
--.*: 04309fe0 lsl z0\.h, z31\.h, #0
--.*: 04309fe0 lsl z0\.h, z31\.h, #0
--.*: 04319c00 lsl z0\.h, z0\.h, #1
--.*: 04319c00 lsl z0\.h, z0\.h, #1
--.*: 043e9c00 lsl z0\.h, z0\.h, #14
--.*: 043e9c00 lsl z0\.h, z0\.h, #14
--.*: 043f9c00 lsl z0\.h, z0\.h, #15
--.*: 043f9c00 lsl z0\.h, z0\.h, #15
--.*: 04389c00 lsl z0\.h, z0\.h, #8
--.*: 04389c00 lsl z0\.h, z0\.h, #8
--.*: 04389c01 lsl z1\.h, z0\.h, #8
--.*: 04389c01 lsl z1\.h, z0\.h, #8
--.*: 04389c1f lsl z31\.h, z0\.h, #8
--.*: 04389c1f lsl z31\.h, z0\.h, #8
--.*: 04389c40 lsl z0\.h, z2\.h, #8
--.*: 04389c40 lsl z0\.h, z2\.h, #8
--.*: 04389fe0 lsl z0\.h, z31\.h, #8
--.*: 04389fe0 lsl z0\.h, z31\.h, #8
--.*: 04399c00 lsl z0\.h, z0\.h, #9
--.*: 04399c00 lsl z0\.h, z0\.h, #9
--.*: 046e9c00 lsl z0\.s, z0\.s, #14
--.*: 046e9c00 lsl z0\.s, z0\.s, #14
--.*: 046f9c00 lsl z0\.s, z0\.s, #15
--.*: 046f9c00 lsl z0\.s, z0\.s, #15
--.*: 04609c00 lsl z0\.s, z0\.s, #0
--.*: 04609c00 lsl z0\.s, z0\.s, #0
--.*: 04609c01 lsl z1\.s, z0\.s, #0
--.*: 04609c01 lsl z1\.s, z0\.s, #0
--.*: 04609c1f lsl z31\.s, z0\.s, #0
--.*: 04609c1f lsl z31\.s, z0\.s, #0
--.*: 04609c40 lsl z0\.s, z2\.s, #0
--.*: 04609c40 lsl z0\.s, z2\.s, #0
--.*: 04609fe0 lsl z0\.s, z31\.s, #0
--.*: 04609fe0 lsl z0\.s, z31\.s, #0
--.*: 04619c00 lsl z0\.s, z0\.s, #1
--.*: 04619c00 lsl z0\.s, z0\.s, #1
--.*: 047e9c00 lsl z0\.s, z0\.s, #30
--.*: 047e9c00 lsl z0\.s, z0\.s, #30
--.*: 047f9c00 lsl z0\.s, z0\.s, #31
--.*: 047f9c00 lsl z0\.s, z0\.s, #31
--.*: 04689c00 lsl z0\.s, z0\.s, #8
--.*: 04689c00 lsl z0\.s, z0\.s, #8
--.*: 04689c01 lsl z1\.s, z0\.s, #8
--.*: 04689c01 lsl z1\.s, z0\.s, #8
--.*: 04689c1f lsl z31\.s, z0\.s, #8
--.*: 04689c1f lsl z31\.s, z0\.s, #8
--.*: 04689c40 lsl z0\.s, z2\.s, #8
--.*: 04689c40 lsl z0\.s, z2\.s, #8
--.*: 04689fe0 lsl z0\.s, z31\.s, #8
--.*: 04689fe0 lsl z0\.s, z31\.s, #8
--.*: 04699c00 lsl z0\.s, z0\.s, #9
--.*: 04699c00 lsl z0\.s, z0\.s, #9
--.*: 04ae9c00 lsl z0\.d, z0\.d, #14
--.*: 04ae9c00 lsl z0\.d, z0\.d, #14
--.*: 04af9c00 lsl z0\.d, z0\.d, #15
--.*: 04af9c00 lsl z0\.d, z0\.d, #15
--.*: 04709c00 lsl z0\.s, z0\.s, #16
--.*: 04709c00 lsl z0\.s, z0\.s, #16
--.*: 04709c01 lsl z1\.s, z0\.s, #16
--.*: 04709c01 lsl z1\.s, z0\.s, #16
--.*: 04709c1f lsl z31\.s, z0\.s, #16
--.*: 04709c1f lsl z31\.s, z0\.s, #16
--.*: 04709c40 lsl z0\.s, z2\.s, #16
--.*: 04709c40 lsl z0\.s, z2\.s, #16
--.*: 04709fe0 lsl z0\.s, z31\.s, #16
--.*: 04709fe0 lsl z0\.s, z31\.s, #16
--.*: 04719c00 lsl z0\.s, z0\.s, #17
--.*: 04719c00 lsl z0\.s, z0\.s, #17
--.*: 04be9c00 lsl z0\.d, z0\.d, #30
--.*: 04be9c00 lsl z0\.d, z0\.d, #30
--.*: 04bf9c00 lsl z0\.d, z0\.d, #31
--.*: 04bf9c00 lsl z0\.d, z0\.d, #31
--.*: 04789c00 lsl z0\.s, z0\.s, #24
--.*: 04789c00 lsl z0\.s, z0\.s, #24
--.*: 04789c01 lsl z1\.s, z0\.s, #24
--.*: 04789c01 lsl z1\.s, z0\.s, #24
--.*: 04789c1f lsl z31\.s, z0\.s, #24
--.*: 04789c1f lsl z31\.s, z0\.s, #24
--.*: 04789c40 lsl z0\.s, z2\.s, #24
--.*: 04789c40 lsl z0\.s, z2\.s, #24
--.*: 04789fe0 lsl z0\.s, z31\.s, #24
--.*: 04789fe0 lsl z0\.s, z31\.s, #24
--.*: 04799c00 lsl z0\.s, z0\.s, #25
--.*: 04799c00 lsl z0\.s, z0\.s, #25
--.*: 04ee9c00 lsl z0\.d, z0\.d, #46
--.*: 04ee9c00 lsl z0\.d, z0\.d, #46
--.*: 04ef9c00 lsl z0\.d, z0\.d, #47
--.*: 04ef9c00 lsl z0\.d, z0\.d, #47
--.*: 04a09c00 lsl z0\.d, z0\.d, #0
--.*: 04a09c00 lsl z0\.d, z0\.d, #0
--.*: 04a09c01 lsl z1\.d, z0\.d, #0
--.*: 04a09c01 lsl z1\.d, z0\.d, #0
--.*: 04a09c1f lsl z31\.d, z0\.d, #0
--.*: 04a09c1f lsl z31\.d, z0\.d, #0
--.*: 04a09c40 lsl z0\.d, z2\.d, #0
--.*: 04a09c40 lsl z0\.d, z2\.d, #0
--.*: 04a09fe0 lsl z0\.d, z31\.d, #0
--.*: 04a09fe0 lsl z0\.d, z31\.d, #0
--.*: 04a19c00 lsl z0\.d, z0\.d, #1
--.*: 04a19c00 lsl z0\.d, z0\.d, #1
--.*: 04fe9c00 lsl z0\.d, z0\.d, #62
--.*: 04fe9c00 lsl z0\.d, z0\.d, #62
--.*: 04ff9c00 lsl z0\.d, z0\.d, #63
--.*: 04ff9c00 lsl z0\.d, z0\.d, #63
--.*: 04a89c00 lsl z0\.d, z0\.d, #8
--.*: 04a89c00 lsl z0\.d, z0\.d, #8
--.*: 04a89c01 lsl z1\.d, z0\.d, #8
--.*: 04a89c01 lsl z1\.d, z0\.d, #8
--.*: 04a89c1f lsl z31\.d, z0\.d, #8
--.*: 04a89c1f lsl z31\.d, z0\.d, #8
--.*: 04a89c40 lsl z0\.d, z2\.d, #8
--.*: 04a89c40 lsl z0\.d, z2\.d, #8
--.*: 04a89fe0 lsl z0\.d, z31\.d, #8
--.*: 04a89fe0 lsl z0\.d, z31\.d, #8
--.*: 04a99c00 lsl z0\.d, z0\.d, #9
--.*: 04a99c00 lsl z0\.d, z0\.d, #9
--.*: 04b09c00 lsl z0\.d, z0\.d, #16
--.*: 04b09c00 lsl z0\.d, z0\.d, #16
--.*: 04b09c01 lsl z1\.d, z0\.d, #16
--.*: 04b09c01 lsl z1\.d, z0\.d, #16
--.*: 04b09c1f lsl z31\.d, z0\.d, #16
--.*: 04b09c1f lsl z31\.d, z0\.d, #16
--.*: 04b09c40 lsl z0\.d, z2\.d, #16
--.*: 04b09c40 lsl z0\.d, z2\.d, #16
--.*: 04b09fe0 lsl z0\.d, z31\.d, #16
--.*: 04b09fe0 lsl z0\.d, z31\.d, #16
--.*: 04b19c00 lsl z0\.d, z0\.d, #17
--.*: 04b19c00 lsl z0\.d, z0\.d, #17
--.*: 04b89c00 lsl z0\.d, z0\.d, #24
--.*: 04b89c00 lsl z0\.d, z0\.d, #24
--.*: 04b89c01 lsl z1\.d, z0\.d, #24
--.*: 04b89c01 lsl z1\.d, z0\.d, #24
--.*: 04b89c1f lsl z31\.d, z0\.d, #24
--.*: 04b89c1f lsl z31\.d, z0\.d, #24
--.*: 04b89c40 lsl z0\.d, z2\.d, #24
--.*: 04b89c40 lsl z0\.d, z2\.d, #24
--.*: 04b89fe0 lsl z0\.d, z31\.d, #24
--.*: 04b89fe0 lsl z0\.d, z31\.d, #24
--.*: 04b99c00 lsl z0\.d, z0\.d, #25
--.*: 04b99c00 lsl z0\.d, z0\.d, #25
--.*: 04e09c00 lsl z0\.d, z0\.d, #32
--.*: 04e09c00 lsl z0\.d, z0\.d, #32
--.*: 04e09c01 lsl z1\.d, z0\.d, #32
--.*: 04e09c01 lsl z1\.d, z0\.d, #32
--.*: 04e09c1f lsl z31\.d, z0\.d, #32
--.*: 04e09c1f lsl z31\.d, z0\.d, #32
--.*: 04e09c40 lsl z0\.d, z2\.d, #32
--.*: 04e09c40 lsl z0\.d, z2\.d, #32
--.*: 04e09fe0 lsl z0\.d, z31\.d, #32
--.*: 04e09fe0 lsl z0\.d, z31\.d, #32
--.*: 04e19c00 lsl z0\.d, z0\.d, #33
--.*: 04e19c00 lsl z0\.d, z0\.d, #33
--.*: 04e89c00 lsl z0\.d, z0\.d, #40
--.*: 04e89c00 lsl z0\.d, z0\.d, #40
--.*: 04e89c01 lsl z1\.d, z0\.d, #40
--.*: 04e89c01 lsl z1\.d, z0\.d, #40
--.*: 04e89c1f lsl z31\.d, z0\.d, #40
--.*: 04e89c1f lsl z31\.d, z0\.d, #40
--.*: 04e89c40 lsl z0\.d, z2\.d, #40
--.*: 04e89c40 lsl z0\.d, z2\.d, #40
--.*: 04e89fe0 lsl z0\.d, z31\.d, #40
--.*: 04e89fe0 lsl z0\.d, z31\.d, #40
--.*: 04e99c00 lsl z0\.d, z0\.d, #41
--.*: 04e99c00 lsl z0\.d, z0\.d, #41
--.*: 04f09c00 lsl z0\.d, z0\.d, #48
--.*: 04f09c00 lsl z0\.d, z0\.d, #48
--.*: 04f09c01 lsl z1\.d, z0\.d, #48
--.*: 04f09c01 lsl z1\.d, z0\.d, #48
--.*: 04f09c1f lsl z31\.d, z0\.d, #48
--.*: 04f09c1f lsl z31\.d, z0\.d, #48
--.*: 04f09c40 lsl z0\.d, z2\.d, #48
--.*: 04f09c40 lsl z0\.d, z2\.d, #48
--.*: 04f09fe0 lsl z0\.d, z31\.d, #48
--.*: 04f09fe0 lsl z0\.d, z31\.d, #48
--.*: 04f19c00 lsl z0\.d, z0\.d, #49
--.*: 04f19c00 lsl z0\.d, z0\.d, #49
--.*: 04f89c00 lsl z0\.d, z0\.d, #56
--.*: 04f89c00 lsl z0\.d, z0\.d, #56
--.*: 04f89c01 lsl z1\.d, z0\.d, #56
--.*: 04f89c01 lsl z1\.d, z0\.d, #56
--.*: 04f89c1f lsl z31\.d, z0\.d, #56
--.*: 04f89c1f lsl z31\.d, z0\.d, #56
--.*: 04f89c40 lsl z0\.d, z2\.d, #56
--.*: 04f89c40 lsl z0\.d, z2\.d, #56
--.*: 04f89fe0 lsl z0\.d, z31\.d, #56
--.*: 04f89fe0 lsl z0\.d, z31\.d, #56
--.*: 04f99c00 lsl z0\.d, z0\.d, #57
--.*: 04f99c00 lsl z0\.d, z0\.d, #57
--.*: 04138000 lsl z0\.b, p0/m, z0\.b, z0\.b
--.*: 04138000 lsl z0\.b, p0/m, z0\.b, z0\.b
--.*: 04138001 lsl z1\.b, p0/m, z1\.b, z0\.b
--.*: 04138001 lsl z1\.b, p0/m, z1\.b, z0\.b
--.*: 0413801f lsl z31\.b, p0/m, z31\.b, z0\.b
--.*: 0413801f lsl z31\.b, p0/m, z31\.b, z0\.b
--.*: 04138800 lsl z0\.b, p2/m, z0\.b, z0\.b
--.*: 04138800 lsl z0\.b, p2/m, z0\.b, z0\.b
--.*: 04139c00 lsl z0\.b, p7/m, z0\.b, z0\.b
--.*: 04139c00 lsl z0\.b, p7/m, z0\.b, z0\.b
--.*: 04138003 lsl z3\.b, p0/m, z3\.b, z0\.b
--.*: 04138003 lsl z3\.b, p0/m, z3\.b, z0\.b
--.*: 04138080 lsl z0\.b, p0/m, z0\.b, z4\.b
--.*: 04138080 lsl z0\.b, p0/m, z0\.b, z4\.b
--.*: 041383e0 lsl z0\.b, p0/m, z0\.b, z31\.b
--.*: 041383e0 lsl z0\.b, p0/m, z0\.b, z31\.b
--.*: 04538000 lsl z0\.h, p0/m, z0\.h, z0\.h
--.*: 04538000 lsl z0\.h, p0/m, z0\.h, z0\.h
--.*: 04538001 lsl z1\.h, p0/m, z1\.h, z0\.h
--.*: 04538001 lsl z1\.h, p0/m, z1\.h, z0\.h
--.*: 0453801f lsl z31\.h, p0/m, z31\.h, z0\.h
--.*: 0453801f lsl z31\.h, p0/m, z31\.h, z0\.h
--.*: 04538800 lsl z0\.h, p2/m, z0\.h, z0\.h
--.*: 04538800 lsl z0\.h, p2/m, z0\.h, z0\.h
--.*: 04539c00 lsl z0\.h, p7/m, z0\.h, z0\.h
--.*: 04539c00 lsl z0\.h, p7/m, z0\.h, z0\.h
--.*: 04538003 lsl z3\.h, p0/m, z3\.h, z0\.h
--.*: 04538003 lsl z3\.h, p0/m, z3\.h, z0\.h
--.*: 04538080 lsl z0\.h, p0/m, z0\.h, z4\.h
--.*: 04538080 lsl z0\.h, p0/m, z0\.h, z4\.h
--.*: 045383e0 lsl z0\.h, p0/m, z0\.h, z31\.h
--.*: 045383e0 lsl z0\.h, p0/m, z0\.h, z31\.h
--.*: 04938000 lsl z0\.s, p0/m, z0\.s, z0\.s
--.*: 04938000 lsl z0\.s, p0/m, z0\.s, z0\.s
--.*: 04938001 lsl z1\.s, p0/m, z1\.s, z0\.s
--.*: 04938001 lsl z1\.s, p0/m, z1\.s, z0\.s
--.*: 0493801f lsl z31\.s, p0/m, z31\.s, z0\.s
--.*: 0493801f lsl z31\.s, p0/m, z31\.s, z0\.s
--.*: 04938800 lsl z0\.s, p2/m, z0\.s, z0\.s
--.*: 04938800 lsl z0\.s, p2/m, z0\.s, z0\.s
--.*: 04939c00 lsl z0\.s, p7/m, z0\.s, z0\.s
--.*: 04939c00 lsl z0\.s, p7/m, z0\.s, z0\.s
--.*: 04938003 lsl z3\.s, p0/m, z3\.s, z0\.s
--.*: 04938003 lsl z3\.s, p0/m, z3\.s, z0\.s
--.*: 04938080 lsl z0\.s, p0/m, z0\.s, z4\.s
--.*: 04938080 lsl z0\.s, p0/m, z0\.s, z4\.s
--.*: 049383e0 lsl z0\.s, p0/m, z0\.s, z31\.s
--.*: 049383e0 lsl z0\.s, p0/m, z0\.s, z31\.s
--.*: 04d38000 lsl z0\.d, p0/m, z0\.d, z0\.d
--.*: 04d38000 lsl z0\.d, p0/m, z0\.d, z0\.d
--.*: 04d38001 lsl z1\.d, p0/m, z1\.d, z0\.d
--.*: 04d38001 lsl z1\.d, p0/m, z1\.d, z0\.d
--.*: 04d3801f lsl z31\.d, p0/m, z31\.d, z0\.d
--.*: 04d3801f lsl z31\.d, p0/m, z31\.d, z0\.d
--.*: 04d38800 lsl z0\.d, p2/m, z0\.d, z0\.d
--.*: 04d38800 lsl z0\.d, p2/m, z0\.d, z0\.d
--.*: 04d39c00 lsl z0\.d, p7/m, z0\.d, z0\.d
--.*: 04d39c00 lsl z0\.d, p7/m, z0\.d, z0\.d
--.*: 04d38003 lsl z3\.d, p0/m, z3\.d, z0\.d
--.*: 04d38003 lsl z3\.d, p0/m, z3\.d, z0\.d
--.*: 04d38080 lsl z0\.d, p0/m, z0\.d, z4\.d
--.*: 04d38080 lsl z0\.d, p0/m, z0\.d, z4\.d
--.*: 04d383e0 lsl z0\.d, p0/m, z0\.d, z31\.d
--.*: 04d383e0 lsl z0\.d, p0/m, z0\.d, z31\.d
--.*: 041b8000 lsl z0\.b, p0/m, z0\.b, z0\.d
--.*: 041b8000 lsl z0\.b, p0/m, z0\.b, z0\.d
--.*: 041b8001 lsl z1\.b, p0/m, z1\.b, z0\.d
--.*: 041b8001 lsl z1\.b, p0/m, z1\.b, z0\.d
--.*: 041b801f lsl z31\.b, p0/m, z31\.b, z0\.d
--.*: 041b801f lsl z31\.b, p0/m, z31\.b, z0\.d
--.*: 041b8800 lsl z0\.b, p2/m, z0\.b, z0\.d
--.*: 041b8800 lsl z0\.b, p2/m, z0\.b, z0\.d
--.*: 041b9c00 lsl z0\.b, p7/m, z0\.b, z0\.d
--.*: 041b9c00 lsl z0\.b, p7/m, z0\.b, z0\.d
--.*: 041b8003 lsl z3\.b, p0/m, z3\.b, z0\.d
--.*: 041b8003 lsl z3\.b, p0/m, z3\.b, z0\.d
--.*: 041b8080 lsl z0\.b, p0/m, z0\.b, z4\.d
--.*: 041b8080 lsl z0\.b, p0/m, z0\.b, z4\.d
--.*: 041b83e0 lsl z0\.b, p0/m, z0\.b, z31\.d
--.*: 041b83e0 lsl z0\.b, p0/m, z0\.b, z31\.d
--.*: 045b8000 lsl z0\.h, p0/m, z0\.h, z0\.d
--.*: 045b8000 lsl z0\.h, p0/m, z0\.h, z0\.d
--.*: 045b8001 lsl z1\.h, p0/m, z1\.h, z0\.d
--.*: 045b8001 lsl z1\.h, p0/m, z1\.h, z0\.d
--.*: 045b801f lsl z31\.h, p0/m, z31\.h, z0\.d
--.*: 045b801f lsl z31\.h, p0/m, z31\.h, z0\.d
--.*: 045b8800 lsl z0\.h, p2/m, z0\.h, z0\.d
--.*: 045b8800 lsl z0\.h, p2/m, z0\.h, z0\.d
--.*: 045b9c00 lsl z0\.h, p7/m, z0\.h, z0\.d
--.*: 045b9c00 lsl z0\.h, p7/m, z0\.h, z0\.d
--.*: 045b8003 lsl z3\.h, p0/m, z3\.h, z0\.d
--.*: 045b8003 lsl z3\.h, p0/m, z3\.h, z0\.d
--.*: 045b8080 lsl z0\.h, p0/m, z0\.h, z4\.d
--.*: 045b8080 lsl z0\.h, p0/m, z0\.h, z4\.d
--.*: 045b83e0 lsl z0\.h, p0/m, z0\.h, z31\.d
--.*: 045b83e0 lsl z0\.h, p0/m, z0\.h, z31\.d
--.*: 049b8000 lsl z0\.s, p0/m, z0\.s, z0\.d
--.*: 049b8000 lsl z0\.s, p0/m, z0\.s, z0\.d
--.*: 049b8001 lsl z1\.s, p0/m, z1\.s, z0\.d
--.*: 049b8001 lsl z1\.s, p0/m, z1\.s, z0\.d
--.*: 049b801f lsl z31\.s, p0/m, z31\.s, z0\.d
--.*: 049b801f lsl z31\.s, p0/m, z31\.s, z0\.d
--.*: 049b8800 lsl z0\.s, p2/m, z0\.s, z0\.d
--.*: 049b8800 lsl z0\.s, p2/m, z0\.s, z0\.d
--.*: 049b9c00 lsl z0\.s, p7/m, z0\.s, z0\.d
--.*: 049b9c00 lsl z0\.s, p7/m, z0\.s, z0\.d
--.*: 049b8003 lsl z3\.s, p0/m, z3\.s, z0\.d
--.*: 049b8003 lsl z3\.s, p0/m, z3\.s, z0\.d
--.*: 049b8080 lsl z0\.s, p0/m, z0\.s, z4\.d
--.*: 049b8080 lsl z0\.s, p0/m, z0\.s, z4\.d
--.*: 049b83e0 lsl z0\.s, p0/m, z0\.s, z31\.d
--.*: 049b83e0 lsl z0\.s, p0/m, z0\.s, z31\.d
--.*: 04038100 lsl z0\.b, p0/m, z0\.b, #0
--.*: 04038100 lsl z0\.b, p0/m, z0\.b, #0
--.*: 04038101 lsl z1\.b, p0/m, z1\.b, #0
--.*: 04038101 lsl z1\.b, p0/m, z1\.b, #0
--.*: 0403811f lsl z31\.b, p0/m, z31\.b, #0
--.*: 0403811f lsl z31\.b, p0/m, z31\.b, #0
--.*: 04038900 lsl z0\.b, p2/m, z0\.b, #0
--.*: 04038900 lsl z0\.b, p2/m, z0\.b, #0
--.*: 04039d00 lsl z0\.b, p7/m, z0\.b, #0
--.*: 04039d00 lsl z0\.b, p7/m, z0\.b, #0
--.*: 04038103 lsl z3\.b, p0/m, z3\.b, #0
--.*: 04038103 lsl z3\.b, p0/m, z3\.b, #0
--.*: 04038120 lsl z0\.b, p0/m, z0\.b, #1
--.*: 04038120 lsl z0\.b, p0/m, z0\.b, #1
--.*: 040381c0 lsl z0\.b, p0/m, z0\.b, #6
--.*: 040381c0 lsl z0\.b, p0/m, z0\.b, #6
--.*: 040381e0 lsl z0\.b, p0/m, z0\.b, #7
--.*: 040381e0 lsl z0\.b, p0/m, z0\.b, #7
--.*: 04038200 lsl z0\.h, p0/m, z0\.h, #0
--.*: 04038200 lsl z0\.h, p0/m, z0\.h, #0
--.*: 04038201 lsl z1\.h, p0/m, z1\.h, #0
--.*: 04038201 lsl z1\.h, p0/m, z1\.h, #0
--.*: 0403821f lsl z31\.h, p0/m, z31\.h, #0
--.*: 0403821f lsl z31\.h, p0/m, z31\.h, #0
--.*: 04038a00 lsl z0\.h, p2/m, z0\.h, #0
--.*: 04038a00 lsl z0\.h, p2/m, z0\.h, #0
--.*: 04039e00 lsl z0\.h, p7/m, z0\.h, #0
--.*: 04039e00 lsl z0\.h, p7/m, z0\.h, #0
--.*: 04038203 lsl z3\.h, p0/m, z3\.h, #0
--.*: 04038203 lsl z3\.h, p0/m, z3\.h, #0
--.*: 04038220 lsl z0\.h, p0/m, z0\.h, #1
--.*: 04038220 lsl z0\.h, p0/m, z0\.h, #1
--.*: 040383c0 lsl z0\.h, p0/m, z0\.h, #14
--.*: 040383c0 lsl z0\.h, p0/m, z0\.h, #14
--.*: 040383e0 lsl z0\.h, p0/m, z0\.h, #15
--.*: 040383e0 lsl z0\.h, p0/m, z0\.h, #15
--.*: 04038300 lsl z0\.h, p0/m, z0\.h, #8
--.*: 04038300 lsl z0\.h, p0/m, z0\.h, #8
--.*: 04038301 lsl z1\.h, p0/m, z1\.h, #8
--.*: 04038301 lsl z1\.h, p0/m, z1\.h, #8
--.*: 0403831f lsl z31\.h, p0/m, z31\.h, #8
--.*: 0403831f lsl z31\.h, p0/m, z31\.h, #8
--.*: 04038b00 lsl z0\.h, p2/m, z0\.h, #8
--.*: 04038b00 lsl z0\.h, p2/m, z0\.h, #8
--.*: 04039f00 lsl z0\.h, p7/m, z0\.h, #8
--.*: 04039f00 lsl z0\.h, p7/m, z0\.h, #8
--.*: 04038303 lsl z3\.h, p0/m, z3\.h, #8
--.*: 04038303 lsl z3\.h, p0/m, z3\.h, #8
--.*: 04038320 lsl z0\.h, p0/m, z0\.h, #9
--.*: 04038320 lsl z0\.h, p0/m, z0\.h, #9
--.*: 044381c0 lsl z0\.s, p0/m, z0\.s, #14
--.*: 044381c0 lsl z0\.s, p0/m, z0\.s, #14
--.*: 044381e0 lsl z0\.s, p0/m, z0\.s, #15
--.*: 044381e0 lsl z0\.s, p0/m, z0\.s, #15
--.*: 04438000 lsl z0\.s, p0/m, z0\.s, #0
--.*: 04438000 lsl z0\.s, p0/m, z0\.s, #0
--.*: 04438001 lsl z1\.s, p0/m, z1\.s, #0
--.*: 04438001 lsl z1\.s, p0/m, z1\.s, #0
--.*: 0443801f lsl z31\.s, p0/m, z31\.s, #0
--.*: 0443801f lsl z31\.s, p0/m, z31\.s, #0
--.*: 04438800 lsl z0\.s, p2/m, z0\.s, #0
--.*: 04438800 lsl z0\.s, p2/m, z0\.s, #0
--.*: 04439c00 lsl z0\.s, p7/m, z0\.s, #0
--.*: 04439c00 lsl z0\.s, p7/m, z0\.s, #0
--.*: 04438003 lsl z3\.s, p0/m, z3\.s, #0
--.*: 04438003 lsl z3\.s, p0/m, z3\.s, #0
--.*: 04438020 lsl z0\.s, p0/m, z0\.s, #1
--.*: 04438020 lsl z0\.s, p0/m, z0\.s, #1
--.*: 044383c0 lsl z0\.s, p0/m, z0\.s, #30
--.*: 044383c0 lsl z0\.s, p0/m, z0\.s, #30
--.*: 044383e0 lsl z0\.s, p0/m, z0\.s, #31
--.*: 044383e0 lsl z0\.s, p0/m, z0\.s, #31
--.*: 04438100 lsl z0\.s, p0/m, z0\.s, #8
--.*: 04438100 lsl z0\.s, p0/m, z0\.s, #8
--.*: 04438101 lsl z1\.s, p0/m, z1\.s, #8
--.*: 04438101 lsl z1\.s, p0/m, z1\.s, #8
--.*: 0443811f lsl z31\.s, p0/m, z31\.s, #8
--.*: 0443811f lsl z31\.s, p0/m, z31\.s, #8
--.*: 04438900 lsl z0\.s, p2/m, z0\.s, #8
--.*: 04438900 lsl z0\.s, p2/m, z0\.s, #8
--.*: 04439d00 lsl z0\.s, p7/m, z0\.s, #8
--.*: 04439d00 lsl z0\.s, p7/m, z0\.s, #8
--.*: 04438103 lsl z3\.s, p0/m, z3\.s, #8
--.*: 04438103 lsl z3\.s, p0/m, z3\.s, #8
--.*: 04438120 lsl z0\.s, p0/m, z0\.s, #9
--.*: 04438120 lsl z0\.s, p0/m, z0\.s, #9
--.*: 048381c0 lsl z0\.d, p0/m, z0\.d, #14
--.*: 048381c0 lsl z0\.d, p0/m, z0\.d, #14
--.*: 048381e0 lsl z0\.d, p0/m, z0\.d, #15
--.*: 048381e0 lsl z0\.d, p0/m, z0\.d, #15
--.*: 04438200 lsl z0\.s, p0/m, z0\.s, #16
--.*: 04438200 lsl z0\.s, p0/m, z0\.s, #16
--.*: 04438201 lsl z1\.s, p0/m, z1\.s, #16
--.*: 04438201 lsl z1\.s, p0/m, z1\.s, #16
--.*: 0443821f lsl z31\.s, p0/m, z31\.s, #16
--.*: 0443821f lsl z31\.s, p0/m, z31\.s, #16
--.*: 04438a00 lsl z0\.s, p2/m, z0\.s, #16
--.*: 04438a00 lsl z0\.s, p2/m, z0\.s, #16
--.*: 04439e00 lsl z0\.s, p7/m, z0\.s, #16
--.*: 04439e00 lsl z0\.s, p7/m, z0\.s, #16
--.*: 04438203 lsl z3\.s, p0/m, z3\.s, #16
--.*: 04438203 lsl z3\.s, p0/m, z3\.s, #16
--.*: 04438220 lsl z0\.s, p0/m, z0\.s, #17
--.*: 04438220 lsl z0\.s, p0/m, z0\.s, #17
--.*: 048383c0 lsl z0\.d, p0/m, z0\.d, #30
--.*: 048383c0 lsl z0\.d, p0/m, z0\.d, #30
--.*: 048383e0 lsl z0\.d, p0/m, z0\.d, #31
--.*: 048383e0 lsl z0\.d, p0/m, z0\.d, #31
--.*: 04438300 lsl z0\.s, p0/m, z0\.s, #24
--.*: 04438300 lsl z0\.s, p0/m, z0\.s, #24
--.*: 04438301 lsl z1\.s, p0/m, z1\.s, #24
--.*: 04438301 lsl z1\.s, p0/m, z1\.s, #24
--.*: 0443831f lsl z31\.s, p0/m, z31\.s, #24
--.*: 0443831f lsl z31\.s, p0/m, z31\.s, #24
--.*: 04438b00 lsl z0\.s, p2/m, z0\.s, #24
--.*: 04438b00 lsl z0\.s, p2/m, z0\.s, #24
--.*: 04439f00 lsl z0\.s, p7/m, z0\.s, #24
--.*: 04439f00 lsl z0\.s, p7/m, z0\.s, #24
--.*: 04438303 lsl z3\.s, p0/m, z3\.s, #24
--.*: 04438303 lsl z3\.s, p0/m, z3\.s, #24
--.*: 04438320 lsl z0\.s, p0/m, z0\.s, #25
--.*: 04438320 lsl z0\.s, p0/m, z0\.s, #25
--.*: 04c381c0 lsl z0\.d, p0/m, z0\.d, #46
--.*: 04c381c0 lsl z0\.d, p0/m, z0\.d, #46
--.*: 04c381e0 lsl z0\.d, p0/m, z0\.d, #47
--.*: 04c381e0 lsl z0\.d, p0/m, z0\.d, #47
--.*: 04838000 lsl z0\.d, p0/m, z0\.d, #0
--.*: 04838000 lsl z0\.d, p0/m, z0\.d, #0
--.*: 04838001 lsl z1\.d, p0/m, z1\.d, #0
--.*: 04838001 lsl z1\.d, p0/m, z1\.d, #0
--.*: 0483801f lsl z31\.d, p0/m, z31\.d, #0
--.*: 0483801f lsl z31\.d, p0/m, z31\.d, #0
--.*: 04838800 lsl z0\.d, p2/m, z0\.d, #0
--.*: 04838800 lsl z0\.d, p2/m, z0\.d, #0
--.*: 04839c00 lsl z0\.d, p7/m, z0\.d, #0
--.*: 04839c00 lsl z0\.d, p7/m, z0\.d, #0
--.*: 04838003 lsl z3\.d, p0/m, z3\.d, #0
--.*: 04838003 lsl z3\.d, p0/m, z3\.d, #0
--.*: 04838020 lsl z0\.d, p0/m, z0\.d, #1
--.*: 04838020 lsl z0\.d, p0/m, z0\.d, #1
--.*: 04c383c0 lsl z0\.d, p0/m, z0\.d, #62
--.*: 04c383c0 lsl z0\.d, p0/m, z0\.d, #62
--.*: 04c383e0 lsl z0\.d, p0/m, z0\.d, #63
--.*: 04c383e0 lsl z0\.d, p0/m, z0\.d, #63
--.*: 04838100 lsl z0\.d, p0/m, z0\.d, #8
--.*: 04838100 lsl z0\.d, p0/m, z0\.d, #8
--.*: 04838101 lsl z1\.d, p0/m, z1\.d, #8
--.*: 04838101 lsl z1\.d, p0/m, z1\.d, #8
--.*: 0483811f lsl z31\.d, p0/m, z31\.d, #8
--.*: 0483811f lsl z31\.d, p0/m, z31\.d, #8
--.*: 04838900 lsl z0\.d, p2/m, z0\.d, #8
--.*: 04838900 lsl z0\.d, p2/m, z0\.d, #8
--.*: 04839d00 lsl z0\.d, p7/m, z0\.d, #8
--.*: 04839d00 lsl z0\.d, p7/m, z0\.d, #8
--.*: 04838103 lsl z3\.d, p0/m, z3\.d, #8
--.*: 04838103 lsl z3\.d, p0/m, z3\.d, #8
--.*: 04838120 lsl z0\.d, p0/m, z0\.d, #9
--.*: 04838120 lsl z0\.d, p0/m, z0\.d, #9
--.*: 04838200 lsl z0\.d, p0/m, z0\.d, #16
--.*: 04838200 lsl z0\.d, p0/m, z0\.d, #16
--.*: 04838201 lsl z1\.d, p0/m, z1\.d, #16
--.*: 04838201 lsl z1\.d, p0/m, z1\.d, #16
--.*: 0483821f lsl z31\.d, p0/m, z31\.d, #16
--.*: 0483821f lsl z31\.d, p0/m, z31\.d, #16
--.*: 04838a00 lsl z0\.d, p2/m, z0\.d, #16
--.*: 04838a00 lsl z0\.d, p2/m, z0\.d, #16
--.*: 04839e00 lsl z0\.d, p7/m, z0\.d, #16
--.*: 04839e00 lsl z0\.d, p7/m, z0\.d, #16
--.*: 04838203 lsl z3\.d, p0/m, z3\.d, #16
--.*: 04838203 lsl z3\.d, p0/m, z3\.d, #16
--.*: 04838220 lsl z0\.d, p0/m, z0\.d, #17
--.*: 04838220 lsl z0\.d, p0/m, z0\.d, #17
--.*: 04838300 lsl z0\.d, p0/m, z0\.d, #24
--.*: 04838300 lsl z0\.d, p0/m, z0\.d, #24
--.*: 04838301 lsl z1\.d, p0/m, z1\.d, #24
--.*: 04838301 lsl z1\.d, p0/m, z1\.d, #24
--.*: 0483831f lsl z31\.d, p0/m, z31\.d, #24
--.*: 0483831f lsl z31\.d, p0/m, z31\.d, #24
--.*: 04838b00 lsl z0\.d, p2/m, z0\.d, #24
--.*: 04838b00 lsl z0\.d, p2/m, z0\.d, #24
--.*: 04839f00 lsl z0\.d, p7/m, z0\.d, #24
--.*: 04839f00 lsl z0\.d, p7/m, z0\.d, #24
--.*: 04838303 lsl z3\.d, p0/m, z3\.d, #24
--.*: 04838303 lsl z3\.d, p0/m, z3\.d, #24
--.*: 04838320 lsl z0\.d, p0/m, z0\.d, #25
--.*: 04838320 lsl z0\.d, p0/m, z0\.d, #25
--.*: 04c38000 lsl z0\.d, p0/m, z0\.d, #32
--.*: 04c38000 lsl z0\.d, p0/m, z0\.d, #32
--.*: 04c38001 lsl z1\.d, p0/m, z1\.d, #32
--.*: 04c38001 lsl z1\.d, p0/m, z1\.d, #32
--.*: 04c3801f lsl z31\.d, p0/m, z31\.d, #32
--.*: 04c3801f lsl z31\.d, p0/m, z31\.d, #32
--.*: 04c38800 lsl z0\.d, p2/m, z0\.d, #32
--.*: 04c38800 lsl z0\.d, p2/m, z0\.d, #32
--.*: 04c39c00 lsl z0\.d, p7/m, z0\.d, #32
--.*: 04c39c00 lsl z0\.d, p7/m, z0\.d, #32
--.*: 04c38003 lsl z3\.d, p0/m, z3\.d, #32
--.*: 04c38003 lsl z3\.d, p0/m, z3\.d, #32
--.*: 04c38020 lsl z0\.d, p0/m, z0\.d, #33
--.*: 04c38020 lsl z0\.d, p0/m, z0\.d, #33
--.*: 04c38100 lsl z0\.d, p0/m, z0\.d, #40
--.*: 04c38100 lsl z0\.d, p0/m, z0\.d, #40
--.*: 04c38101 lsl z1\.d, p0/m, z1\.d, #40
--.*: 04c38101 lsl z1\.d, p0/m, z1\.d, #40
--.*: 04c3811f lsl z31\.d, p0/m, z31\.d, #40
--.*: 04c3811f lsl z31\.d, p0/m, z31\.d, #40
--.*: 04c38900 lsl z0\.d, p2/m, z0\.d, #40
--.*: 04c38900 lsl z0\.d, p2/m, z0\.d, #40
--.*: 04c39d00 lsl z0\.d, p7/m, z0\.d, #40
--.*: 04c39d00 lsl z0\.d, p7/m, z0\.d, #40
--.*: 04c38103 lsl z3\.d, p0/m, z3\.d, #40
--.*: 04c38103 lsl z3\.d, p0/m, z3\.d, #40
--.*: 04c38120 lsl z0\.d, p0/m, z0\.d, #41
--.*: 04c38120 lsl z0\.d, p0/m, z0\.d, #41
--.*: 04c38200 lsl z0\.d, p0/m, z0\.d, #48
--.*: 04c38200 lsl z0\.d, p0/m, z0\.d, #48
--.*: 04c38201 lsl z1\.d, p0/m, z1\.d, #48
--.*: 04c38201 lsl z1\.d, p0/m, z1\.d, #48
--.*: 04c3821f lsl z31\.d, p0/m, z31\.d, #48
--.*: 04c3821f lsl z31\.d, p0/m, z31\.d, #48
--.*: 04c38a00 lsl z0\.d, p2/m, z0\.d, #48
--.*: 04c38a00 lsl z0\.d, p2/m, z0\.d, #48
--.*: 04c39e00 lsl z0\.d, p7/m, z0\.d, #48
--.*: 04c39e00 lsl z0\.d, p7/m, z0\.d, #48
--.*: 04c38203 lsl z3\.d, p0/m, z3\.d, #48
--.*: 04c38203 lsl z3\.d, p0/m, z3\.d, #48
--.*: 04c38220 lsl z0\.d, p0/m, z0\.d, #49
--.*: 04c38220 lsl z0\.d, p0/m, z0\.d, #49
--.*: 04c38300 lsl z0\.d, p0/m, z0\.d, #56
--.*: 04c38300 lsl z0\.d, p0/m, z0\.d, #56
--.*: 04c38301 lsl z1\.d, p0/m, z1\.d, #56
--.*: 04c38301 lsl z1\.d, p0/m, z1\.d, #56
--.*: 04c3831f lsl z31\.d, p0/m, z31\.d, #56
--.*: 04c3831f lsl z31\.d, p0/m, z31\.d, #56
--.*: 04c38b00 lsl z0\.d, p2/m, z0\.d, #56
--.*: 04c38b00 lsl z0\.d, p2/m, z0\.d, #56
--.*: 04c39f00 lsl z0\.d, p7/m, z0\.d, #56
--.*: 04c39f00 lsl z0\.d, p7/m, z0\.d, #56
--.*: 04c38303 lsl z3\.d, p0/m, z3\.d, #56
--.*: 04c38303 lsl z3\.d, p0/m, z3\.d, #56
--.*: 04c38320 lsl z0\.d, p0/m, z0\.d, #57
--.*: 04c38320 lsl z0\.d, p0/m, z0\.d, #57
--.*: 04178000 lslr z0\.b, p0/m, z0\.b, z0\.b
--.*: 04178000 lslr z0\.b, p0/m, z0\.b, z0\.b
--.*: 04178001 lslr z1\.b, p0/m, z1\.b, z0\.b
--.*: 04178001 lslr z1\.b, p0/m, z1\.b, z0\.b
--.*: 0417801f lslr z31\.b, p0/m, z31\.b, z0\.b
--.*: 0417801f lslr z31\.b, p0/m, z31\.b, z0\.b
--.*: 04178800 lslr z0\.b, p2/m, z0\.b, z0\.b
--.*: 04178800 lslr z0\.b, p2/m, z0\.b, z0\.b
--.*: 04179c00 lslr z0\.b, p7/m, z0\.b, z0\.b
--.*: 04179c00 lslr z0\.b, p7/m, z0\.b, z0\.b
--.*: 04178003 lslr z3\.b, p0/m, z3\.b, z0\.b
--.*: 04178003 lslr z3\.b, p0/m, z3\.b, z0\.b
--.*: 04178080 lslr z0\.b, p0/m, z0\.b, z4\.b
--.*: 04178080 lslr z0\.b, p0/m, z0\.b, z4\.b
--.*: 041783e0 lslr z0\.b, p0/m, z0\.b, z31\.b
--.*: 041783e0 lslr z0\.b, p0/m, z0\.b, z31\.b
--.*: 04578000 lslr z0\.h, p0/m, z0\.h, z0\.h
--.*: 04578000 lslr z0\.h, p0/m, z0\.h, z0\.h
--.*: 04578001 lslr z1\.h, p0/m, z1\.h, z0\.h
--.*: 04578001 lslr z1\.h, p0/m, z1\.h, z0\.h
--.*: 0457801f lslr z31\.h, p0/m, z31\.h, z0\.h
--.*: 0457801f lslr z31\.h, p0/m, z31\.h, z0\.h
--.*: 04578800 lslr z0\.h, p2/m, z0\.h, z0\.h
--.*: 04578800 lslr z0\.h, p2/m, z0\.h, z0\.h
--.*: 04579c00 lslr z0\.h, p7/m, z0\.h, z0\.h
--.*: 04579c00 lslr z0\.h, p7/m, z0\.h, z0\.h
--.*: 04578003 lslr z3\.h, p0/m, z3\.h, z0\.h
--.*: 04578003 lslr z3\.h, p0/m, z3\.h, z0\.h
--.*: 04578080 lslr z0\.h, p0/m, z0\.h, z4\.h
--.*: 04578080 lslr z0\.h, p0/m, z0\.h, z4\.h
--.*: 045783e0 lslr z0\.h, p0/m, z0\.h, z31\.h
--.*: 045783e0 lslr z0\.h, p0/m, z0\.h, z31\.h
--.*: 04978000 lslr z0\.s, p0/m, z0\.s, z0\.s
--.*: 04978000 lslr z0\.s, p0/m, z0\.s, z0\.s
--.*: 04978001 lslr z1\.s, p0/m, z1\.s, z0\.s
--.*: 04978001 lslr z1\.s, p0/m, z1\.s, z0\.s
--.*: 0497801f lslr z31\.s, p0/m, z31\.s, z0\.s
--.*: 0497801f lslr z31\.s, p0/m, z31\.s, z0\.s
--.*: 04978800 lslr z0\.s, p2/m, z0\.s, z0\.s
--.*: 04978800 lslr z0\.s, p2/m, z0\.s, z0\.s
--.*: 04979c00 lslr z0\.s, p7/m, z0\.s, z0\.s
--.*: 04979c00 lslr z0\.s, p7/m, z0\.s, z0\.s
--.*: 04978003 lslr z3\.s, p0/m, z3\.s, z0\.s
--.*: 04978003 lslr z3\.s, p0/m, z3\.s, z0\.s
--.*: 04978080 lslr z0\.s, p0/m, z0\.s, z4\.s
--.*: 04978080 lslr z0\.s, p0/m, z0\.s, z4\.s
--.*: 049783e0 lslr z0\.s, p0/m, z0\.s, z31\.s
--.*: 049783e0 lslr z0\.s, p0/m, z0\.s, z31\.s
--.*: 04d78000 lslr z0\.d, p0/m, z0\.d, z0\.d
--.*: 04d78000 lslr z0\.d, p0/m, z0\.d, z0\.d
--.*: 04d78001 lslr z1\.d, p0/m, z1\.d, z0\.d
--.*: 04d78001 lslr z1\.d, p0/m, z1\.d, z0\.d
--.*: 04d7801f lslr z31\.d, p0/m, z31\.d, z0\.d
--.*: 04d7801f lslr z31\.d, p0/m, z31\.d, z0\.d
--.*: 04d78800 lslr z0\.d, p2/m, z0\.d, z0\.d
--.*: 04d78800 lslr z0\.d, p2/m, z0\.d, z0\.d
--.*: 04d79c00 lslr z0\.d, p7/m, z0\.d, z0\.d
--.*: 04d79c00 lslr z0\.d, p7/m, z0\.d, z0\.d
--.*: 04d78003 lslr z3\.d, p0/m, z3\.d, z0\.d
--.*: 04d78003 lslr z3\.d, p0/m, z3\.d, z0\.d
--.*: 04d78080 lslr z0\.d, p0/m, z0\.d, z4\.d
--.*: 04d78080 lslr z0\.d, p0/m, z0\.d, z4\.d
--.*: 04d783e0 lslr z0\.d, p0/m, z0\.d, z31\.d
--.*: 04d783e0 lslr z0\.d, p0/m, z0\.d, z31\.d
--.*: 04208400 lsr z0\.b, z0\.b, z0\.d
--.*: 04208400 lsr z0\.b, z0\.b, z0\.d
--.*: 04208401 lsr z1\.b, z0\.b, z0\.d
--.*: 04208401 lsr z1\.b, z0\.b, z0\.d
--.*: 0420841f lsr z31\.b, z0\.b, z0\.d
--.*: 0420841f lsr z31\.b, z0\.b, z0\.d
--.*: 04208440 lsr z0\.b, z2\.b, z0\.d
--.*: 04208440 lsr z0\.b, z2\.b, z0\.d
--.*: 042087e0 lsr z0\.b, z31\.b, z0\.d
--.*: 042087e0 lsr z0\.b, z31\.b, z0\.d
--.*: 04238400 lsr z0\.b, z0\.b, z3\.d
--.*: 04238400 lsr z0\.b, z0\.b, z3\.d
--.*: 043f8400 lsr z0\.b, z0\.b, z31\.d
--.*: 043f8400 lsr z0\.b, z0\.b, z31\.d
--.*: 04608400 lsr z0\.h, z0\.h, z0\.d
--.*: 04608400 lsr z0\.h, z0\.h, z0\.d
--.*: 04608401 lsr z1\.h, z0\.h, z0\.d
--.*: 04608401 lsr z1\.h, z0\.h, z0\.d
--.*: 0460841f lsr z31\.h, z0\.h, z0\.d
--.*: 0460841f lsr z31\.h, z0\.h, z0\.d
--.*: 04608440 lsr z0\.h, z2\.h, z0\.d
--.*: 04608440 lsr z0\.h, z2\.h, z0\.d
--.*: 046087e0 lsr z0\.h, z31\.h, z0\.d
--.*: 046087e0 lsr z0\.h, z31\.h, z0\.d
--.*: 04638400 lsr z0\.h, z0\.h, z3\.d
--.*: 04638400 lsr z0\.h, z0\.h, z3\.d
--.*: 047f8400 lsr z0\.h, z0\.h, z31\.d
--.*: 047f8400 lsr z0\.h, z0\.h, z31\.d
--.*: 04a08400 lsr z0\.s, z0\.s, z0\.d
--.*: 04a08400 lsr z0\.s, z0\.s, z0\.d
--.*: 04a08401 lsr z1\.s, z0\.s, z0\.d
--.*: 04a08401 lsr z1\.s, z0\.s, z0\.d
--.*: 04a0841f lsr z31\.s, z0\.s, z0\.d
--.*: 04a0841f lsr z31\.s, z0\.s, z0\.d
--.*: 04a08440 lsr z0\.s, z2\.s, z0\.d
--.*: 04a08440 lsr z0\.s, z2\.s, z0\.d
--.*: 04a087e0 lsr z0\.s, z31\.s, z0\.d
--.*: 04a087e0 lsr z0\.s, z31\.s, z0\.d
--.*: 04a38400 lsr z0\.s, z0\.s, z3\.d
--.*: 04a38400 lsr z0\.s, z0\.s, z3\.d
--.*: 04bf8400 lsr z0\.s, z0\.s, z31\.d
--.*: 04bf8400 lsr z0\.s, z0\.s, z31\.d
--.*: 04289400 lsr z0\.b, z0\.b, #8
--.*: 04289400 lsr z0\.b, z0\.b, #8
--.*: 04289401 lsr z1\.b, z0\.b, #8
--.*: 04289401 lsr z1\.b, z0\.b, #8
--.*: 0428941f lsr z31\.b, z0\.b, #8
--.*: 0428941f lsr z31\.b, z0\.b, #8
--.*: 04289440 lsr z0\.b, z2\.b, #8
--.*: 04289440 lsr z0\.b, z2\.b, #8
--.*: 042897e0 lsr z0\.b, z31\.b, #8
--.*: 042897e0 lsr z0\.b, z31\.b, #8
--.*: 04299400 lsr z0\.b, z0\.b, #7
--.*: 04299400 lsr z0\.b, z0\.b, #7
--.*: 042e9400 lsr z0\.b, z0\.b, #2
--.*: 042e9400 lsr z0\.b, z0\.b, #2
--.*: 042f9400 lsr z0\.b, z0\.b, #1
--.*: 042f9400 lsr z0\.b, z0\.b, #1
--.*: 04309400 lsr z0\.h, z0\.h, #16
--.*: 04309400 lsr z0\.h, z0\.h, #16
--.*: 04309401 lsr z1\.h, z0\.h, #16
--.*: 04309401 lsr z1\.h, z0\.h, #16
--.*: 0430941f lsr z31\.h, z0\.h, #16
--.*: 0430941f lsr z31\.h, z0\.h, #16
--.*: 04309440 lsr z0\.h, z2\.h, #16
--.*: 04309440 lsr z0\.h, z2\.h, #16
--.*: 043097e0 lsr z0\.h, z31\.h, #16
--.*: 043097e0 lsr z0\.h, z31\.h, #16
--.*: 04319400 lsr z0\.h, z0\.h, #15
--.*: 04319400 lsr z0\.h, z0\.h, #15
--.*: 043e9400 lsr z0\.h, z0\.h, #2
--.*: 043e9400 lsr z0\.h, z0\.h, #2
--.*: 043f9400 lsr z0\.h, z0\.h, #1
--.*: 043f9400 lsr z0\.h, z0\.h, #1
--.*: 04389400 lsr z0\.h, z0\.h, #8
--.*: 04389400 lsr z0\.h, z0\.h, #8
--.*: 04389401 lsr z1\.h, z0\.h, #8
--.*: 04389401 lsr z1\.h, z0\.h, #8
--.*: 0438941f lsr z31\.h, z0\.h, #8
--.*: 0438941f lsr z31\.h, z0\.h, #8
--.*: 04389440 lsr z0\.h, z2\.h, #8
--.*: 04389440 lsr z0\.h, z2\.h, #8
--.*: 043897e0 lsr z0\.h, z31\.h, #8
--.*: 043897e0 lsr z0\.h, z31\.h, #8
--.*: 04399400 lsr z0\.h, z0\.h, #7
--.*: 04399400 lsr z0\.h, z0\.h, #7
--.*: 046e9400 lsr z0\.s, z0\.s, #18
--.*: 046e9400 lsr z0\.s, z0\.s, #18
--.*: 046f9400 lsr z0\.s, z0\.s, #17
--.*: 046f9400 lsr z0\.s, z0\.s, #17
--.*: 04609400 lsr z0\.s, z0\.s, #32
--.*: 04609400 lsr z0\.s, z0\.s, #32
--.*: 04609401 lsr z1\.s, z0\.s, #32
--.*: 04609401 lsr z1\.s, z0\.s, #32
--.*: 0460941f lsr z31\.s, z0\.s, #32
--.*: 0460941f lsr z31\.s, z0\.s, #32
--.*: 04609440 lsr z0\.s, z2\.s, #32
--.*: 04609440 lsr z0\.s, z2\.s, #32
--.*: 046097e0 lsr z0\.s, z31\.s, #32
--.*: 046097e0 lsr z0\.s, z31\.s, #32
--.*: 04619400 lsr z0\.s, z0\.s, #31
--.*: 04619400 lsr z0\.s, z0\.s, #31
--.*: 047e9400 lsr z0\.s, z0\.s, #2
--.*: 047e9400 lsr z0\.s, z0\.s, #2
--.*: 047f9400 lsr z0\.s, z0\.s, #1
--.*: 047f9400 lsr z0\.s, z0\.s, #1
--.*: 04689400 lsr z0\.s, z0\.s, #24
--.*: 04689400 lsr z0\.s, z0\.s, #24
--.*: 04689401 lsr z1\.s, z0\.s, #24
--.*: 04689401 lsr z1\.s, z0\.s, #24
--.*: 0468941f lsr z31\.s, z0\.s, #24
--.*: 0468941f lsr z31\.s, z0\.s, #24
--.*: 04689440 lsr z0\.s, z2\.s, #24
--.*: 04689440 lsr z0\.s, z2\.s, #24
--.*: 046897e0 lsr z0\.s, z31\.s, #24
--.*: 046897e0 lsr z0\.s, z31\.s, #24
--.*: 04699400 lsr z0\.s, z0\.s, #23
--.*: 04699400 lsr z0\.s, z0\.s, #23
--.*: 04ae9400 lsr z0\.d, z0\.d, #50
--.*: 04ae9400 lsr z0\.d, z0\.d, #50
--.*: 04af9400 lsr z0\.d, z0\.d, #49
--.*: 04af9400 lsr z0\.d, z0\.d, #49
--.*: 04709400 lsr z0\.s, z0\.s, #16
--.*: 04709400 lsr z0\.s, z0\.s, #16
--.*: 04709401 lsr z1\.s, z0\.s, #16
--.*: 04709401 lsr z1\.s, z0\.s, #16
--.*: 0470941f lsr z31\.s, z0\.s, #16
--.*: 0470941f lsr z31\.s, z0\.s, #16
--.*: 04709440 lsr z0\.s, z2\.s, #16
--.*: 04709440 lsr z0\.s, z2\.s, #16
--.*: 047097e0 lsr z0\.s, z31\.s, #16
--.*: 047097e0 lsr z0\.s, z31\.s, #16
--.*: 04719400 lsr z0\.s, z0\.s, #15
--.*: 04719400 lsr z0\.s, z0\.s, #15
--.*: 04be9400 lsr z0\.d, z0\.d, #34
--.*: 04be9400 lsr z0\.d, z0\.d, #34
--.*: 04bf9400 lsr z0\.d, z0\.d, #33
--.*: 04bf9400 lsr z0\.d, z0\.d, #33
--.*: 04789400 lsr z0\.s, z0\.s, #8
--.*: 04789400 lsr z0\.s, z0\.s, #8
--.*: 04789401 lsr z1\.s, z0\.s, #8
--.*: 04789401 lsr z1\.s, z0\.s, #8
--.*: 0478941f lsr z31\.s, z0\.s, #8
--.*: 0478941f lsr z31\.s, z0\.s, #8
--.*: 04789440 lsr z0\.s, z2\.s, #8
--.*: 04789440 lsr z0\.s, z2\.s, #8
--.*: 047897e0 lsr z0\.s, z31\.s, #8
--.*: 047897e0 lsr z0\.s, z31\.s, #8
--.*: 04799400 lsr z0\.s, z0\.s, #7
--.*: 04799400 lsr z0\.s, z0\.s, #7
--.*: 04ee9400 lsr z0\.d, z0\.d, #18
--.*: 04ee9400 lsr z0\.d, z0\.d, #18
--.*: 04ef9400 lsr z0\.d, z0\.d, #17
--.*: 04ef9400 lsr z0\.d, z0\.d, #17
--.*: 04a09400 lsr z0\.d, z0\.d, #64
--.*: 04a09400 lsr z0\.d, z0\.d, #64
--.*: 04a09401 lsr z1\.d, z0\.d, #64
--.*: 04a09401 lsr z1\.d, z0\.d, #64
--.*: 04a0941f lsr z31\.d, z0\.d, #64
--.*: 04a0941f lsr z31\.d, z0\.d, #64
--.*: 04a09440 lsr z0\.d, z2\.d, #64
--.*: 04a09440 lsr z0\.d, z2\.d, #64
--.*: 04a097e0 lsr z0\.d, z31\.d, #64
--.*: 04a097e0 lsr z0\.d, z31\.d, #64
--.*: 04a19400 lsr z0\.d, z0\.d, #63
--.*: 04a19400 lsr z0\.d, z0\.d, #63
--.*: 04fe9400 lsr z0\.d, z0\.d, #2
--.*: 04fe9400 lsr z0\.d, z0\.d, #2
--.*: 04ff9400 lsr z0\.d, z0\.d, #1
--.*: 04ff9400 lsr z0\.d, z0\.d, #1
--.*: 04a89400 lsr z0\.d, z0\.d, #56
--.*: 04a89400 lsr z0\.d, z0\.d, #56
--.*: 04a89401 lsr z1\.d, z0\.d, #56
--.*: 04a89401 lsr z1\.d, z0\.d, #56
--.*: 04a8941f lsr z31\.d, z0\.d, #56
--.*: 04a8941f lsr z31\.d, z0\.d, #56
--.*: 04a89440 lsr z0\.d, z2\.d, #56
--.*: 04a89440 lsr z0\.d, z2\.d, #56
--.*: 04a897e0 lsr z0\.d, z31\.d, #56
--.*: 04a897e0 lsr z0\.d, z31\.d, #56
--.*: 04a99400 lsr z0\.d, z0\.d, #55
--.*: 04a99400 lsr z0\.d, z0\.d, #55
--.*: 04b09400 lsr z0\.d, z0\.d, #48
--.*: 04b09400 lsr z0\.d, z0\.d, #48
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--.*: 04b09401 lsr z1\.d, z0\.d, #48
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--.*: 04b09440 lsr z0\.d, z2\.d, #48
--.*: 04b09440 lsr z0\.d, z2\.d, #48
--.*: 04b097e0 lsr z0\.d, z31\.d, #48
--.*: 04b097e0 lsr z0\.d, z31\.d, #48
--.*: 04b19400 lsr z0\.d, z0\.d, #47
--.*: 04b19400 lsr z0\.d, z0\.d, #47
--.*: 04b89400 lsr z0\.d, z0\.d, #40
--.*: 04b89400 lsr z0\.d, z0\.d, #40
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--.*: 04b89401 lsr z1\.d, z0\.d, #40
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--.*: 04b89440 lsr z0\.d, z2\.d, #40
--.*: 04b897e0 lsr z0\.d, z31\.d, #40
--.*: 04b897e0 lsr z0\.d, z31\.d, #40
--.*: 04b99400 lsr z0\.d, z0\.d, #39
--.*: 04b99400 lsr z0\.d, z0\.d, #39
--.*: 04e09400 lsr z0\.d, z0\.d, #32
--.*: 04e09400 lsr z0\.d, z0\.d, #32
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--.*: 04e09401 lsr z1\.d, z0\.d, #32
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--.*: 04e0941f lsr z31\.d, z0\.d, #32
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--.*: 04e09440 lsr z0\.d, z2\.d, #32
--.*: 04e097e0 lsr z0\.d, z31\.d, #32
--.*: 04e097e0 lsr z0\.d, z31\.d, #32
--.*: 04e19400 lsr z0\.d, z0\.d, #31
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--.*: 04e89400 lsr z0\.d, z0\.d, #24
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--.*: 04e897e0 lsr z0\.d, z31\.d, #24
--.*: 04e897e0 lsr z0\.d, z31\.d, #24
--.*: 04e99400 lsr z0\.d, z0\.d, #23
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--.*: 04f097e0 lsr z0\.d, z31\.d, #16
--.*: 04f19400 lsr z0\.d, z0\.d, #15
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--.*: 04918080 lsr z0\.s, p0/m, z0\.s, z4\.s
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--.*: 04d19c00 lsr z0\.d, p7/m, z0\.d, z0\.d
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--.*: 04d18003 lsr z3\.d, p0/m, z3\.d, z0\.d
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--.*: 04d18080 lsr z0\.d, p0/m, z0\.d, z4\.d
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--.*: 04198000 lsr z0\.b, p0/m, z0\.b, z0\.d
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--.*: 04198001 lsr z1\.b, p0/m, z1\.b, z0\.d
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--.*: 04198800 lsr z0\.b, p2/m, z0\.b, z0\.d
--.*: 04198800 lsr z0\.b, p2/m, z0\.b, z0\.d
--.*: 04199c00 lsr z0\.b, p7/m, z0\.b, z0\.d
--.*: 04199c00 lsr z0\.b, p7/m, z0\.b, z0\.d
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--.*: 04598001 lsr z1\.h, p0/m, z1\.h, z0\.d
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--.*: 04598080 lsr z0\.h, p0/m, z0\.h, z4\.d
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--.*: 040183c0 lsr z0\.h, p0/m, z0\.h, #2
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--.*: 04018300 lsr z0\.h, p0/m, z0\.h, #8
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--.*: 04019f00 lsr z0\.h, p7/m, z0\.h, #8
--.*: 04018303 lsr z3\.h, p0/m, z3\.h, #8
--.*: 04018303 lsr z3\.h, p0/m, z3\.h, #8
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--.*: 04418000 lsr z0\.s, p0/m, z0\.s, #32
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--.*: 0440e080 msb z0\.h, p0/m, z0\.h, z4\.h
--.*: 0440e080 msb z0\.h, p0/m, z0\.h, z4\.h
--.*: 0440e3e0 msb z0\.h, p0/m, z0\.h, z31\.h
--.*: 0440e3e0 msb z0\.h, p0/m, z0\.h, z31\.h
--.*: 0480e000 msb z0\.s, p0/m, z0\.s, z0\.s
--.*: 0480e000 msb z0\.s, p0/m, z0\.s, z0\.s
--.*: 0480e001 msb z1\.s, p0/m, z0\.s, z0\.s
--.*: 0480e001 msb z1\.s, p0/m, z0\.s, z0\.s
--.*: 0480e01f msb z31\.s, p0/m, z0\.s, z0\.s
--.*: 0480e01f msb z31\.s, p0/m, z0\.s, z0\.s
--.*: 0480e800 msb z0\.s, p2/m, z0\.s, z0\.s
--.*: 0480e800 msb z0\.s, p2/m, z0\.s, z0\.s
--.*: 0480fc00 msb z0\.s, p7/m, z0\.s, z0\.s
--.*: 0480fc00 msb z0\.s, p7/m, z0\.s, z0\.s
--.*: 0483e000 msb z0\.s, p0/m, z3\.s, z0\.s
--.*: 0483e000 msb z0\.s, p0/m, z3\.s, z0\.s
--.*: 049fe000 msb z0\.s, p0/m, z31\.s, z0\.s
--.*: 049fe000 msb z0\.s, p0/m, z31\.s, z0\.s
--.*: 0480e080 msb z0\.s, p0/m, z0\.s, z4\.s
--.*: 0480e080 msb z0\.s, p0/m, z0\.s, z4\.s
--.*: 0480e3e0 msb z0\.s, p0/m, z0\.s, z31\.s
--.*: 0480e3e0 msb z0\.s, p0/m, z0\.s, z31\.s
--.*: 04c0e000 msb z0\.d, p0/m, z0\.d, z0\.d
--.*: 04c0e000 msb z0\.d, p0/m, z0\.d, z0\.d
--.*: 04c0e001 msb z1\.d, p0/m, z0\.d, z0\.d
--.*: 04c0e001 msb z1\.d, p0/m, z0\.d, z0\.d
--.*: 04c0e01f msb z31\.d, p0/m, z0\.d, z0\.d
--.*: 04c0e01f msb z31\.d, p0/m, z0\.d, z0\.d
--.*: 04c0e800 msb z0\.d, p2/m, z0\.d, z0\.d
--.*: 04c0e800 msb z0\.d, p2/m, z0\.d, z0\.d
--.*: 04c0fc00 msb z0\.d, p7/m, z0\.d, z0\.d
--.*: 04c0fc00 msb z0\.d, p7/m, z0\.d, z0\.d
--.*: 04c3e000 msb z0\.d, p0/m, z3\.d, z0\.d
--.*: 04c3e000 msb z0\.d, p0/m, z3\.d, z0\.d
--.*: 04dfe000 msb z0\.d, p0/m, z31\.d, z0\.d
--.*: 04dfe000 msb z0\.d, p0/m, z31\.d, z0\.d
--.*: 04c0e080 msb z0\.d, p0/m, z0\.d, z4\.d
--.*: 04c0e080 msb z0\.d, p0/m, z0\.d, z4\.d
--.*: 04c0e3e0 msb z0\.d, p0/m, z0\.d, z31\.d
--.*: 04c0e3e0 msb z0\.d, p0/m, z0\.d, z31\.d
--.*: 2530c000 mul z0\.b, z0\.b, #0
--.*: 2530c000 mul z0\.b, z0\.b, #0
--.*: 2530c001 mul z1\.b, z1\.b, #0
--.*: 2530c001 mul z1\.b, z1\.b, #0
--.*: 2530c01f mul z31\.b, z31\.b, #0
--.*: 2530c01f mul z31\.b, z31\.b, #0
--.*: 2530c002 mul z2\.b, z2\.b, #0
--.*: 2530c002 mul z2\.b, z2\.b, #0
--.*: 2530cfe0 mul z0\.b, z0\.b, #127
--.*: 2530cfe0 mul z0\.b, z0\.b, #127
--.*: 2530d000 mul z0\.b, z0\.b, #-128
--.*: 2530d000 mul z0\.b, z0\.b, #-128
--.*: 2530d020 mul z0\.b, z0\.b, #-127
--.*: 2530d020 mul z0\.b, z0\.b, #-127
--.*: 2530dfe0 mul z0\.b, z0\.b, #-1
--.*: 2530dfe0 mul z0\.b, z0\.b, #-1
--.*: 2570c000 mul z0\.h, z0\.h, #0
--.*: 2570c000 mul z0\.h, z0\.h, #0
--.*: 2570c001 mul z1\.h, z1\.h, #0
--.*: 2570c001 mul z1\.h, z1\.h, #0
--.*: 2570c01f mul z31\.h, z31\.h, #0
--.*: 2570c01f mul z31\.h, z31\.h, #0
--.*: 2570c002 mul z2\.h, z2\.h, #0
--.*: 2570c002 mul z2\.h, z2\.h, #0
--.*: 2570cfe0 mul z0\.h, z0\.h, #127
--.*: 2570cfe0 mul z0\.h, z0\.h, #127
--.*: 2570d000 mul z0\.h, z0\.h, #-128
--.*: 2570d000 mul z0\.h, z0\.h, #-128
--.*: 2570d020 mul z0\.h, z0\.h, #-127
--.*: 2570d020 mul z0\.h, z0\.h, #-127
--.*: 2570dfe0 mul z0\.h, z0\.h, #-1
--.*: 2570dfe0 mul z0\.h, z0\.h, #-1
--.*: 25b0c000 mul z0\.s, z0\.s, #0
--.*: 25b0c000 mul z0\.s, z0\.s, #0
--.*: 25b0c001 mul z1\.s, z1\.s, #0
--.*: 25b0c001 mul z1\.s, z1\.s, #0
--.*: 25b0c01f mul z31\.s, z31\.s, #0
--.*: 25b0c01f mul z31\.s, z31\.s, #0
--.*: 25b0c002 mul z2\.s, z2\.s, #0
--.*: 25b0c002 mul z2\.s, z2\.s, #0
--.*: 25b0cfe0 mul z0\.s, z0\.s, #127
--.*: 25b0cfe0 mul z0\.s, z0\.s, #127
--.*: 25b0d000 mul z0\.s, z0\.s, #-128
--.*: 25b0d000 mul z0\.s, z0\.s, #-128
--.*: 25b0d020 mul z0\.s, z0\.s, #-127
--.*: 25b0d020 mul z0\.s, z0\.s, #-127
--.*: 25b0dfe0 mul z0\.s, z0\.s, #-1
--.*: 25b0dfe0 mul z0\.s, z0\.s, #-1
--.*: 25f0c000 mul z0\.d, z0\.d, #0
--.*: 25f0c000 mul z0\.d, z0\.d, #0
--.*: 25f0c001 mul z1\.d, z1\.d, #0
--.*: 25f0c001 mul z1\.d, z1\.d, #0
--.*: 25f0c01f mul z31\.d, z31\.d, #0
--.*: 25f0c01f mul z31\.d, z31\.d, #0
--.*: 25f0c002 mul z2\.d, z2\.d, #0
--.*: 25f0c002 mul z2\.d, z2\.d, #0
--.*: 25f0cfe0 mul z0\.d, z0\.d, #127
--.*: 25f0cfe0 mul z0\.d, z0\.d, #127
--.*: 25f0d000 mul z0\.d, z0\.d, #-128
--.*: 25f0d000 mul z0\.d, z0\.d, #-128
--.*: 25f0d020 mul z0\.d, z0\.d, #-127
--.*: 25f0d020 mul z0\.d, z0\.d, #-127
--.*: 25f0dfe0 mul z0\.d, z0\.d, #-1
--.*: 25f0dfe0 mul z0\.d, z0\.d, #-1
--.*: 04100000 mul z0\.b, p0/m, z0\.b, z0\.b
--.*: 04100000 mul z0\.b, p0/m, z0\.b, z0\.b
--.*: 04100001 mul z1\.b, p0/m, z1\.b, z0\.b
--.*: 04100001 mul z1\.b, p0/m, z1\.b, z0\.b
--.*: 0410001f mul z31\.b, p0/m, z31\.b, z0\.b
--.*: 0410001f mul z31\.b, p0/m, z31\.b, z0\.b
--.*: 04100800 mul z0\.b, p2/m, z0\.b, z0\.b
--.*: 04100800 mul z0\.b, p2/m, z0\.b, z0\.b
--.*: 04101c00 mul z0\.b, p7/m, z0\.b, z0\.b
--.*: 04101c00 mul z0\.b, p7/m, z0\.b, z0\.b
--.*: 04100003 mul z3\.b, p0/m, z3\.b, z0\.b
--.*: 04100003 mul z3\.b, p0/m, z3\.b, z0\.b
--.*: 04100080 mul z0\.b, p0/m, z0\.b, z4\.b
--.*: 04100080 mul z0\.b, p0/m, z0\.b, z4\.b
--.*: 041003e0 mul z0\.b, p0/m, z0\.b, z31\.b
--.*: 041003e0 mul z0\.b, p0/m, z0\.b, z31\.b
--.*: 04500000 mul z0\.h, p0/m, z0\.h, z0\.h
--.*: 04500000 mul z0\.h, p0/m, z0\.h, z0\.h
--.*: 04500001 mul z1\.h, p0/m, z1\.h, z0\.h
--.*: 04500001 mul z1\.h, p0/m, z1\.h, z0\.h
--.*: 0450001f mul z31\.h, p0/m, z31\.h, z0\.h
--.*: 0450001f mul z31\.h, p0/m, z31\.h, z0\.h
--.*: 04500800 mul z0\.h, p2/m, z0\.h, z0\.h
--.*: 04500800 mul z0\.h, p2/m, z0\.h, z0\.h
--.*: 04501c00 mul z0\.h, p7/m, z0\.h, z0\.h
--.*: 04501c00 mul z0\.h, p7/m, z0\.h, z0\.h
--.*: 04500003 mul z3\.h, p0/m, z3\.h, z0\.h
--.*: 04500003 mul z3\.h, p0/m, z3\.h, z0\.h
--.*: 04500080 mul z0\.h, p0/m, z0\.h, z4\.h
--.*: 04500080 mul z0\.h, p0/m, z0\.h, z4\.h
--.*: 045003e0 mul z0\.h, p0/m, z0\.h, z31\.h
--.*: 045003e0 mul z0\.h, p0/m, z0\.h, z31\.h
--.*: 04900000 mul z0\.s, p0/m, z0\.s, z0\.s
--.*: 04900000 mul z0\.s, p0/m, z0\.s, z0\.s
--.*: 04900001 mul z1\.s, p0/m, z1\.s, z0\.s
--.*: 04900001 mul z1\.s, p0/m, z1\.s, z0\.s
--.*: 0490001f mul z31\.s, p0/m, z31\.s, z0\.s
--.*: 0490001f mul z31\.s, p0/m, z31\.s, z0\.s
--.*: 04900800 mul z0\.s, p2/m, z0\.s, z0\.s
--.*: 04900800 mul z0\.s, p2/m, z0\.s, z0\.s
--.*: 04901c00 mul z0\.s, p7/m, z0\.s, z0\.s
--.*: 04901c00 mul z0\.s, p7/m, z0\.s, z0\.s
--.*: 04900003 mul z3\.s, p0/m, z3\.s, z0\.s
--.*: 04900003 mul z3\.s, p0/m, z3\.s, z0\.s
--.*: 04900080 mul z0\.s, p0/m, z0\.s, z4\.s
--.*: 04900080 mul z0\.s, p0/m, z0\.s, z4\.s
--.*: 049003e0 mul z0\.s, p0/m, z0\.s, z31\.s
--.*: 049003e0 mul z0\.s, p0/m, z0\.s, z31\.s
--.*: 04d00000 mul z0\.d, p0/m, z0\.d, z0\.d
--.*: 04d00000 mul z0\.d, p0/m, z0\.d, z0\.d
--.*: 04d00001 mul z1\.d, p0/m, z1\.d, z0\.d
--.*: 04d00001 mul z1\.d, p0/m, z1\.d, z0\.d
--.*: 04d0001f mul z31\.d, p0/m, z31\.d, z0\.d
--.*: 04d0001f mul z31\.d, p0/m, z31\.d, z0\.d
--.*: 04d00800 mul z0\.d, p2/m, z0\.d, z0\.d
--.*: 04d00800 mul z0\.d, p2/m, z0\.d, z0\.d
--.*: 04d01c00 mul z0\.d, p7/m, z0\.d, z0\.d
--.*: 04d01c00 mul z0\.d, p7/m, z0\.d, z0\.d
--.*: 04d00003 mul z3\.d, p0/m, z3\.d, z0\.d
--.*: 04d00003 mul z3\.d, p0/m, z3\.d, z0\.d
--.*: 04d00080 mul z0\.d, p0/m, z0\.d, z4\.d
--.*: 04d00080 mul z0\.d, p0/m, z0\.d, z4\.d
--.*: 04d003e0 mul z0\.d, p0/m, z0\.d, z31\.d
--.*: 04d003e0 mul z0\.d, p0/m, z0\.d, z31\.d
--.*: 25804210 nand p0\.b, p0/z, p0\.b, p0\.b
--.*: 25804210 nand p0\.b, p0/z, p0\.b, p0\.b
--.*: 25804211 nand p1\.b, p0/z, p0\.b, p0\.b
--.*: 25804211 nand p1\.b, p0/z, p0\.b, p0\.b
--.*: 2580421f nand p15\.b, p0/z, p0\.b, p0\.b
--.*: 2580421f nand p15\.b, p0/z, p0\.b, p0\.b
--.*: 25804a10 nand p0\.b, p2/z, p0\.b, p0\.b
--.*: 25804a10 nand p0\.b, p2/z, p0\.b, p0\.b
--.*: 25807e10 nand p0\.b, p15/z, p0\.b, p0\.b
--.*: 25807e10 nand p0\.b, p15/z, p0\.b, p0\.b
--.*: 25804270 nand p0\.b, p0/z, p3\.b, p0\.b
--.*: 25804270 nand p0\.b, p0/z, p3\.b, p0\.b
--.*: 258043f0 nand p0\.b, p0/z, p15\.b, p0\.b
--.*: 258043f0 nand p0\.b, p0/z, p15\.b, p0\.b
--.*: 25844210 nand p0\.b, p0/z, p0\.b, p4\.b
--.*: 25844210 nand p0\.b, p0/z, p0\.b, p4\.b
--.*: 258f4210 nand p0\.b, p0/z, p0\.b, p15\.b
--.*: 258f4210 nand p0\.b, p0/z, p0\.b, p15\.b
--.*: 25c04210 nands p0\.b, p0/z, p0\.b, p0\.b
--.*: 25c04210 nands p0\.b, p0/z, p0\.b, p0\.b
--.*: 25c04211 nands p1\.b, p0/z, p0\.b, p0\.b
--.*: 25c04211 nands p1\.b, p0/z, p0\.b, p0\.b
--.*: 25c0421f nands p15\.b, p0/z, p0\.b, p0\.b
--.*: 25c0421f nands p15\.b, p0/z, p0\.b, p0\.b
--.*: 25c04a10 nands p0\.b, p2/z, p0\.b, p0\.b
--.*: 25c04a10 nands p0\.b, p2/z, p0\.b, p0\.b
--.*: 25c07e10 nands p0\.b, p15/z, p0\.b, p0\.b
--.*: 25c07e10 nands p0\.b, p15/z, p0\.b, p0\.b
--.*: 25c04270 nands p0\.b, p0/z, p3\.b, p0\.b
--.*: 25c04270 nands p0\.b, p0/z, p3\.b, p0\.b
--.*: 25c043f0 nands p0\.b, p0/z, p15\.b, p0\.b
--.*: 25c043f0 nands p0\.b, p0/z, p15\.b, p0\.b
--.*: 25c44210 nands p0\.b, p0/z, p0\.b, p4\.b
--.*: 25c44210 nands p0\.b, p0/z, p0\.b, p4\.b
--.*: 25cf4210 nands p0\.b, p0/z, p0\.b, p15\.b
--.*: 25cf4210 nands p0\.b, p0/z, p0\.b, p15\.b
--.*: 0417a000 neg z0\.b, p0/m, z0\.b
--.*: 0417a000 neg z0\.b, p0/m, z0\.b
--.*: 0417a001 neg z1\.b, p0/m, z0\.b
--.*: 0417a001 neg z1\.b, p0/m, z0\.b
--.*: 0417a01f neg z31\.b, p0/m, z0\.b
--.*: 0417a01f neg z31\.b, p0/m, z0\.b
--.*: 0417a800 neg z0\.b, p2/m, z0\.b
--.*: 0417a800 neg z0\.b, p2/m, z0\.b
--.*: 0417bc00 neg z0\.b, p7/m, z0\.b
--.*: 0417bc00 neg z0\.b, p7/m, z0\.b
--.*: 0417a060 neg z0\.b, p0/m, z3\.b
--.*: 0417a060 neg z0\.b, p0/m, z3\.b
--.*: 0417a3e0 neg z0\.b, p0/m, z31\.b
--.*: 0417a3e0 neg z0\.b, p0/m, z31\.b
--.*: 0457a000 neg z0\.h, p0/m, z0\.h
--.*: 0457a000 neg z0\.h, p0/m, z0\.h
--.*: 0457a001 neg z1\.h, p0/m, z0\.h
--.*: 0457a001 neg z1\.h, p0/m, z0\.h
--.*: 0457a01f neg z31\.h, p0/m, z0\.h
--.*: 0457a01f neg z31\.h, p0/m, z0\.h
--.*: 0457a800 neg z0\.h, p2/m, z0\.h
--.*: 0457a800 neg z0\.h, p2/m, z0\.h
--.*: 0457bc00 neg z0\.h, p7/m, z0\.h
--.*: 0457bc00 neg z0\.h, p7/m, z0\.h
--.*: 0457a060 neg z0\.h, p0/m, z3\.h
--.*: 0457a060 neg z0\.h, p0/m, z3\.h
--.*: 0457a3e0 neg z0\.h, p0/m, z31\.h
--.*: 0457a3e0 neg z0\.h, p0/m, z31\.h
--.*: 0497a000 neg z0\.s, p0/m, z0\.s
--.*: 0497a000 neg z0\.s, p0/m, z0\.s
--.*: 0497a001 neg z1\.s, p0/m, z0\.s
--.*: 0497a001 neg z1\.s, p0/m, z0\.s
--.*: 0497a01f neg z31\.s, p0/m, z0\.s
--.*: 0497a01f neg z31\.s, p0/m, z0\.s
--.*: 0497a800 neg z0\.s, p2/m, z0\.s
--.*: 0497a800 neg z0\.s, p2/m, z0\.s
--.*: 0497bc00 neg z0\.s, p7/m, z0\.s
--.*: 0497bc00 neg z0\.s, p7/m, z0\.s
--.*: 0497a060 neg z0\.s, p0/m, z3\.s
--.*: 0497a060 neg z0\.s, p0/m, z3\.s
--.*: 0497a3e0 neg z0\.s, p0/m, z31\.s
--.*: 0497a3e0 neg z0\.s, p0/m, z31\.s
--.*: 04d7a000 neg z0\.d, p0/m, z0\.d
--.*: 04d7a000 neg z0\.d, p0/m, z0\.d
--.*: 04d7a001 neg z1\.d, p0/m, z0\.d
--.*: 04d7a001 neg z1\.d, p0/m, z0\.d
--.*: 04d7a01f neg z31\.d, p0/m, z0\.d
--.*: 04d7a01f neg z31\.d, p0/m, z0\.d
--.*: 04d7a800 neg z0\.d, p2/m, z0\.d
--.*: 04d7a800 neg z0\.d, p2/m, z0\.d
--.*: 04d7bc00 neg z0\.d, p7/m, z0\.d
--.*: 04d7bc00 neg z0\.d, p7/m, z0\.d
--.*: 04d7a060 neg z0\.d, p0/m, z3\.d
--.*: 04d7a060 neg z0\.d, p0/m, z3\.d
--.*: 04d7a3e0 neg z0\.d, p0/m, z31\.d
--.*: 04d7a3e0 neg z0\.d, p0/m, z31\.d
--.*: 25804200 nor p0\.b, p0/z, p0\.b, p0\.b
--.*: 25804200 nor p0\.b, p0/z, p0\.b, p0\.b
--.*: 25804201 nor p1\.b, p0/z, p0\.b, p0\.b
--.*: 25804201 nor p1\.b, p0/z, p0\.b, p0\.b
--.*: 2580420f nor p15\.b, p0/z, p0\.b, p0\.b
--.*: 2580420f nor p15\.b, p0/z, p0\.b, p0\.b
--.*: 25804a00 nor p0\.b, p2/z, p0\.b, p0\.b
--.*: 25804a00 nor p0\.b, p2/z, p0\.b, p0\.b
--.*: 25807e00 nor p0\.b, p15/z, p0\.b, p0\.b
--.*: 25807e00 nor p0\.b, p15/z, p0\.b, p0\.b
--.*: 25804260 nor p0\.b, p0/z, p3\.b, p0\.b
--.*: 25804260 nor p0\.b, p0/z, p3\.b, p0\.b
--.*: 258043e0 nor p0\.b, p0/z, p15\.b, p0\.b
--.*: 258043e0 nor p0\.b, p0/z, p15\.b, p0\.b
--.*: 25844200 nor p0\.b, p0/z, p0\.b, p4\.b
--.*: 25844200 nor p0\.b, p0/z, p0\.b, p4\.b
--.*: 258f4200 nor p0\.b, p0/z, p0\.b, p15\.b
--.*: 258f4200 nor p0\.b, p0/z, p0\.b, p15\.b
--.*: 25c04200 nors p0\.b, p0/z, p0\.b, p0\.b
--.*: 25c04200 nors p0\.b, p0/z, p0\.b, p0\.b
--.*: 25c04201 nors p1\.b, p0/z, p0\.b, p0\.b
--.*: 25c04201 nors p1\.b, p0/z, p0\.b, p0\.b
--.*: 25c0420f nors p15\.b, p0/z, p0\.b, p0\.b
--.*: 25c0420f nors p15\.b, p0/z, p0\.b, p0\.b
--.*: 25c04a00 nors p0\.b, p2/z, p0\.b, p0\.b
--.*: 25c04a00 nors p0\.b, p2/z, p0\.b, p0\.b
--.*: 25c07e00 nors p0\.b, p15/z, p0\.b, p0\.b
--.*: 25c07e00 nors p0\.b, p15/z, p0\.b, p0\.b
--.*: 25c04260 nors p0\.b, p0/z, p3\.b, p0\.b
--.*: 25c04260 nors p0\.b, p0/z, p3\.b, p0\.b
--.*: 25c043e0 nors p0\.b, p0/z, p15\.b, p0\.b
--.*: 25c043e0 nors p0\.b, p0/z, p15\.b, p0\.b
--.*: 25c44200 nors p0\.b, p0/z, p0\.b, p4\.b
--.*: 25c44200 nors p0\.b, p0/z, p0\.b, p4\.b
--.*: 25cf4200 nors p0\.b, p0/z, p0\.b, p15\.b
--.*: 25cf4200 nors p0\.b, p0/z, p0\.b, p15\.b
--.*: 041ea000 not z0\.b, p0/m, z0\.b
--.*: 041ea000 not z0\.b, p0/m, z0\.b
--.*: 041ea001 not z1\.b, p0/m, z0\.b
--.*: 041ea001 not z1\.b, p0/m, z0\.b
--.*: 041ea01f not z31\.b, p0/m, z0\.b
--.*: 041ea01f not z31\.b, p0/m, z0\.b
--.*: 041ea800 not z0\.b, p2/m, z0\.b
--.*: 041ea800 not z0\.b, p2/m, z0\.b
--.*: 041ebc00 not z0\.b, p7/m, z0\.b
--.*: 041ebc00 not z0\.b, p7/m, z0\.b
--.*: 041ea060 not z0\.b, p0/m, z3\.b
--.*: 041ea060 not z0\.b, p0/m, z3\.b
--.*: 041ea3e0 not z0\.b, p0/m, z31\.b
--.*: 041ea3e0 not z0\.b, p0/m, z31\.b
--.*: 045ea000 not z0\.h, p0/m, z0\.h
--.*: 045ea000 not z0\.h, p0/m, z0\.h
--.*: 045ea001 not z1\.h, p0/m, z0\.h
--.*: 045ea001 not z1\.h, p0/m, z0\.h
--.*: 045ea01f not z31\.h, p0/m, z0\.h
--.*: 045ea01f not z31\.h, p0/m, z0\.h
--.*: 045ea800 not z0\.h, p2/m, z0\.h
--.*: 045ea800 not z0\.h, p2/m, z0\.h
--.*: 045ebc00 not z0\.h, p7/m, z0\.h
--.*: 045ebc00 not z0\.h, p7/m, z0\.h
--.*: 045ea060 not z0\.h, p0/m, z3\.h
--.*: 045ea060 not z0\.h, p0/m, z3\.h
--.*: 045ea3e0 not z0\.h, p0/m, z31\.h
--.*: 045ea3e0 not z0\.h, p0/m, z31\.h
--.*: 049ea000 not z0\.s, p0/m, z0\.s
--.*: 049ea000 not z0\.s, p0/m, z0\.s
--.*: 049ea001 not z1\.s, p0/m, z0\.s
--.*: 049ea001 not z1\.s, p0/m, z0\.s
--.*: 049ea01f not z31\.s, p0/m, z0\.s
--.*: 049ea01f not z31\.s, p0/m, z0\.s
--.*: 049ea800 not z0\.s, p2/m, z0\.s
--.*: 049ea800 not z0\.s, p2/m, z0\.s
--.*: 049ebc00 not z0\.s, p7/m, z0\.s
--.*: 049ebc00 not z0\.s, p7/m, z0\.s
--.*: 049ea060 not z0\.s, p0/m, z3\.s
--.*: 049ea060 not z0\.s, p0/m, z3\.s
--.*: 049ea3e0 not z0\.s, p0/m, z31\.s
--.*: 049ea3e0 not z0\.s, p0/m, z31\.s
--.*: 04dea000 not z0\.d, p0/m, z0\.d
--.*: 04dea000 not z0\.d, p0/m, z0\.d
--.*: 04dea001 not z1\.d, p0/m, z0\.d
--.*: 04dea001 not z1\.d, p0/m, z0\.d
--.*: 04dea01f not z31\.d, p0/m, z0\.d
--.*: 04dea01f not z31\.d, p0/m, z0\.d
--.*: 04dea800 not z0\.d, p2/m, z0\.d
--.*: 04dea800 not z0\.d, p2/m, z0\.d
--.*: 04debc00 not z0\.d, p7/m, z0\.d
--.*: 04debc00 not z0\.d, p7/m, z0\.d
--.*: 04dea060 not z0\.d, p0/m, z3\.d
--.*: 04dea060 not z0\.d, p0/m, z3\.d
--.*: 04dea3e0 not z0\.d, p0/m, z31\.d
--.*: 04dea3e0 not z0\.d, p0/m, z31\.d
--.*: 25804010 orn p0\.b, p0/z, p0\.b, p0\.b
--.*: 25804010 orn p0\.b, p0/z, p0\.b, p0\.b
--.*: 25804011 orn p1\.b, p0/z, p0\.b, p0\.b
--.*: 25804011 orn p1\.b, p0/z, p0\.b, p0\.b
--.*: 2580401f orn p15\.b, p0/z, p0\.b, p0\.b
--.*: 2580401f orn p15\.b, p0/z, p0\.b, p0\.b
--.*: 25804810 orn p0\.b, p2/z, p0\.b, p0\.b
--.*: 25804810 orn p0\.b, p2/z, p0\.b, p0\.b
--.*: 25807c10 orn p0\.b, p15/z, p0\.b, p0\.b
--.*: 25807c10 orn p0\.b, p15/z, p0\.b, p0\.b
--.*: 25804070 orn p0\.b, p0/z, p3\.b, p0\.b
--.*: 25804070 orn p0\.b, p0/z, p3\.b, p0\.b
--.*: 258041f0 orn p0\.b, p0/z, p15\.b, p0\.b
--.*: 258041f0 orn p0\.b, p0/z, p15\.b, p0\.b
--.*: 25844010 orn p0\.b, p0/z, p0\.b, p4\.b
--.*: 25844010 orn p0\.b, p0/z, p0\.b, p4\.b
--.*: 258f4010 orn p0\.b, p0/z, p0\.b, p15\.b
--.*: 258f4010 orn p0\.b, p0/z, p0\.b, p15\.b
--.*: 25c04010 orns p0\.b, p0/z, p0\.b, p0\.b
--.*: 25c04010 orns p0\.b, p0/z, p0\.b, p0\.b
--.*: 25c04011 orns p1\.b, p0/z, p0\.b, p0\.b
--.*: 25c04011 orns p1\.b, p0/z, p0\.b, p0\.b
--.*: 25c0401f orns p15\.b, p0/z, p0\.b, p0\.b
--.*: 25c0401f orns p15\.b, p0/z, p0\.b, p0\.b
--.*: 25c04810 orns p0\.b, p2/z, p0\.b, p0\.b
--.*: 25c04810 orns p0\.b, p2/z, p0\.b, p0\.b
--.*: 25c07c10 orns p0\.b, p15/z, p0\.b, p0\.b
--.*: 25c07c10 orns p0\.b, p15/z, p0\.b, p0\.b
--.*: 25c04070 orns p0\.b, p0/z, p3\.b, p0\.b
--.*: 25c04070 orns p0\.b, p0/z, p3\.b, p0\.b
--.*: 25c041f0 orns p0\.b, p0/z, p15\.b, p0\.b
--.*: 25c041f0 orns p0\.b, p0/z, p15\.b, p0\.b
--.*: 25c44010 orns p0\.b, p0/z, p0\.b, p4\.b
--.*: 25c44010 orns p0\.b, p0/z, p0\.b, p4\.b
--.*: 25cf4010 orns p0\.b, p0/z, p0\.b, p15\.b
--.*: 25cf4010 orns p0\.b, p0/z, p0\.b, p15\.b
--.*: 04603000 mov z0\.d, z0\.d
--.*: 04603000 mov z0\.d, z0\.d
--.*: 04603001 mov z1\.d, z0\.d
--.*: 04603001 mov z1\.d, z0\.d
--.*: 0460301f mov z31\.d, z0\.d
--.*: 0460301f mov z31\.d, z0\.d
--.*: 04603040 orr z0\.d, z2\.d, z0\.d
--.*: 04603040 orr z0\.d, z2\.d, z0\.d
--.*: 046033e0 orr z0\.d, z31\.d, z0\.d
--.*: 046033e0 orr z0\.d, z31\.d, z0\.d
--.*: 04633000 orr z0\.d, z0\.d, z3\.d
--.*: 04633000 orr z0\.d, z0\.d, z3\.d
--.*: 047f3000 orr z0\.d, z0\.d, z31\.d
--.*: 047f3000 orr z0\.d, z0\.d, z31\.d
--.*: 05000000 orr z0\.s, z0\.s, #0x1
--.*: 05000000 orr z0\.s, z0\.s, #0x1
--.*: 05000000 orr z0\.s, z0\.s, #0x1
--.*: 05000001 orr z1\.s, z1\.s, #0x1
--.*: 05000001 orr z1\.s, z1\.s, #0x1
--.*: 05000001 orr z1\.s, z1\.s, #0x1
--.*: 0500001f orr z31\.s, z31\.s, #0x1
--.*: 0500001f orr z31\.s, z31\.s, #0x1
--.*: 0500001f orr z31\.s, z31\.s, #0x1
--.*: 05000002 orr z2\.s, z2\.s, #0x1
--.*: 05000002 orr z2\.s, z2\.s, #0x1
--.*: 05000002 orr z2\.s, z2\.s, #0x1
--.*: 050000c0 orr z0\.s, z0\.s, #0x7f
--.*: 050000c0 orr z0\.s, z0\.s, #0x7f
--.*: 050000c0 orr z0\.s, z0\.s, #0x7f
--.*: 050003c0 orr z0\.s, z0\.s, #0x7fffffff
--.*: 050003c0 orr z0\.s, z0\.s, #0x7fffffff
--.*: 050003c0 orr z0\.s, z0\.s, #0x7fffffff
--.*: 05000400 orr z0\.h, z0\.h, #0x1
--.*: 05000400 orr z0\.h, z0\.h, #0x1
--.*: 05000400 orr z0\.h, z0\.h, #0x1
--.*: 05000400 orr z0\.h, z0\.h, #0x1
--.*: 050005c0 orr z0\.h, z0\.h, #0x7fff
--.*: 050005c0 orr z0\.h, z0\.h, #0x7fff
--.*: 050005c0 orr z0\.h, z0\.h, #0x7fff
--.*: 050005c0 orr z0\.h, z0\.h, #0x7fff
--.*: 05000600 orr z0\.b, z0\.b, #0x1
--.*: 05000600 orr z0\.b, z0\.b, #0x1
--.*: 05000600 orr z0\.b, z0\.b, #0x1
--.*: 05000600 orr z0\.b, z0\.b, #0x1
--.*: 05000600 orr z0\.b, z0\.b, #0x1
--.*: 05000780 orr z0\.b, z0\.b, #0x55
--.*: 05000780 orr z0\.b, z0\.b, #0x55
--.*: 05000780 orr z0\.b, z0\.b, #0x55
--.*: 05000780 orr z0\.b, z0\.b, #0x55
--.*: 05000780 orr z0\.b, z0\.b, #0x55
--.*: 05000800 orr z0\.s, z0\.s, #0x80000000
--.*: 05000800 orr z0\.s, z0\.s, #0x80000000
--.*: 05000800 orr z0\.s, z0\.s, #0x80000000
--.*: 05000bc0 orr z0\.s, z0\.s, #0xbfffffff
--.*: 05000bc0 orr z0\.s, z0\.s, #0xbfffffff
--.*: 05000bc0 orr z0\.s, z0\.s, #0xbfffffff
--.*: 05000c00 orr z0\.h, z0\.h, #0x8000
--.*: 05000c00 orr z0\.h, z0\.h, #0x8000
--.*: 05000c00 orr z0\.h, z0\.h, #0x8000
--.*: 05000c00 orr z0\.h, z0\.h, #0x8000
--.*: 05000ec0 orr z0\.b, z0\.b, #0xbf
--.*: 05000ec0 orr z0\.b, z0\.b, #0xbf
--.*: 05000ec0 orr z0\.b, z0\.b, #0xbf
--.*: 05000ec0 orr z0\.b, z0\.b, #0xbf
--.*: 05000ec0 orr z0\.b, z0\.b, #0xbf
--.*: 05001e80 orr z0\.b, z0\.b, #0xe3
--.*: 05001e80 orr z0\.b, z0\.b, #0xe3
--.*: 05001e80 orr z0\.b, z0\.b, #0xe3
--.*: 05001e80 orr z0\.b, z0\.b, #0xe3
--.*: 05001e80 orr z0\.b, z0\.b, #0xe3
--.*: 0500bbc0 orr z0\.s, z0\.s, #0xfffffeff
--.*: 0500bbc0 orr z0\.s, z0\.s, #0xfffffeff
--.*: 0500bbc0 orr z0\.s, z0\.s, #0xfffffeff
--.*: 0503ffc0 orr z0\.d, z0\.d, #0xfffffffffffffffe
--.*: 0503ffc0 orr z0\.d, z0\.d, #0xfffffffffffffffe
--.*: 04180000 orr z0\.b, p0/m, z0\.b, z0\.b
--.*: 04180000 orr z0\.b, p0/m, z0\.b, z0\.b
--.*: 04180001 orr z1\.b, p0/m, z1\.b, z0\.b
--.*: 04180001 orr z1\.b, p0/m, z1\.b, z0\.b
--.*: 0418001f orr z31\.b, p0/m, z31\.b, z0\.b
--.*: 0418001f orr z31\.b, p0/m, z31\.b, z0\.b
--.*: 04180800 orr z0\.b, p2/m, z0\.b, z0\.b
--.*: 04180800 orr z0\.b, p2/m, z0\.b, z0\.b
--.*: 04181c00 orr z0\.b, p7/m, z0\.b, z0\.b
--.*: 04181c00 orr z0\.b, p7/m, z0\.b, z0\.b
--.*: 04180003 orr z3\.b, p0/m, z3\.b, z0\.b
--.*: 04180003 orr z3\.b, p0/m, z3\.b, z0\.b
--.*: 04180080 orr z0\.b, p0/m, z0\.b, z4\.b
--.*: 04180080 orr z0\.b, p0/m, z0\.b, z4\.b
--.*: 041803e0 orr z0\.b, p0/m, z0\.b, z31\.b
--.*: 041803e0 orr z0\.b, p0/m, z0\.b, z31\.b
--.*: 04580000 orr z0\.h, p0/m, z0\.h, z0\.h
--.*: 04580000 orr z0\.h, p0/m, z0\.h, z0\.h
--.*: 04580001 orr z1\.h, p0/m, z1\.h, z0\.h
--.*: 04580001 orr z1\.h, p0/m, z1\.h, z0\.h
--.*: 0458001f orr z31\.h, p0/m, z31\.h, z0\.h
--.*: 0458001f orr z31\.h, p0/m, z31\.h, z0\.h
--.*: 04580800 orr z0\.h, p2/m, z0\.h, z0\.h
--.*: 04580800 orr z0\.h, p2/m, z0\.h, z0\.h
--.*: 04581c00 orr z0\.h, p7/m, z0\.h, z0\.h
--.*: 04581c00 orr z0\.h, p7/m, z0\.h, z0\.h
--.*: 04580003 orr z3\.h, p0/m, z3\.h, z0\.h
--.*: 04580003 orr z3\.h, p0/m, z3\.h, z0\.h
--.*: 04580080 orr z0\.h, p0/m, z0\.h, z4\.h
--.*: 04580080 orr z0\.h, p0/m, z0\.h, z4\.h
--.*: 045803e0 orr z0\.h, p0/m, z0\.h, z31\.h
--.*: 045803e0 orr z0\.h, p0/m, z0\.h, z31\.h
--.*: 04980000 orr z0\.s, p0/m, z0\.s, z0\.s
--.*: 04980000 orr z0\.s, p0/m, z0\.s, z0\.s
--.*: 04980001 orr z1\.s, p0/m, z1\.s, z0\.s
--.*: 04980001 orr z1\.s, p0/m, z1\.s, z0\.s
--.*: 0498001f orr z31\.s, p0/m, z31\.s, z0\.s
--.*: 0498001f orr z31\.s, p0/m, z31\.s, z0\.s
--.*: 04980800 orr z0\.s, p2/m, z0\.s, z0\.s
--.*: 04980800 orr z0\.s, p2/m, z0\.s, z0\.s
--.*: 04981c00 orr z0\.s, p7/m, z0\.s, z0\.s
--.*: 04981c00 orr z0\.s, p7/m, z0\.s, z0\.s
--.*: 04980003 orr z3\.s, p0/m, z3\.s, z0\.s
--.*: 04980003 orr z3\.s, p0/m, z3\.s, z0\.s
--.*: 04980080 orr z0\.s, p0/m, z0\.s, z4\.s
--.*: 04980080 orr z0\.s, p0/m, z0\.s, z4\.s
--.*: 049803e0 orr z0\.s, p0/m, z0\.s, z31\.s
--.*: 049803e0 orr z0\.s, p0/m, z0\.s, z31\.s
--.*: 04d80000 orr z0\.d, p0/m, z0\.d, z0\.d
--.*: 04d80000 orr z0\.d, p0/m, z0\.d, z0\.d
--.*: 04d80001 orr z1\.d, p0/m, z1\.d, z0\.d
--.*: 04d80001 orr z1\.d, p0/m, z1\.d, z0\.d
--.*: 04d8001f orr z31\.d, p0/m, z31\.d, z0\.d
--.*: 04d8001f orr z31\.d, p0/m, z31\.d, z0\.d
--.*: 04d80800 orr z0\.d, p2/m, z0\.d, z0\.d
--.*: 04d80800 orr z0\.d, p2/m, z0\.d, z0\.d
--.*: 04d81c00 orr z0\.d, p7/m, z0\.d, z0\.d
--.*: 04d81c00 orr z0\.d, p7/m, z0\.d, z0\.d
--.*: 04d80003 orr z3\.d, p0/m, z3\.d, z0\.d
--.*: 04d80003 orr z3\.d, p0/m, z3\.d, z0\.d
--.*: 04d80080 orr z0\.d, p0/m, z0\.d, z4\.d
--.*: 04d80080 orr z0\.d, p0/m, z0\.d, z4\.d
--.*: 04d803e0 orr z0\.d, p0/m, z0\.d, z31\.d
--.*: 04d803e0 orr z0\.d, p0/m, z0\.d, z31\.d
--.*: 25804000 mov p0\.b, p0\.b
--.*: 25804000 mov p0\.b, p0\.b
--.*: 25804001 mov p1\.b, p0\.b
--.*: 25804001 mov p1\.b, p0\.b
--.*: 2580400f mov p15\.b, p0\.b
--.*: 2580400f mov p15\.b, p0\.b
--.*: 25804800 orr p0\.b, p2/z, p0\.b, p0\.b
--.*: 25804800 orr p0\.b, p2/z, p0\.b, p0\.b
--.*: 25807c00 orr p0\.b, p15/z, p0\.b, p0\.b
--.*: 25807c00 orr p0\.b, p15/z, p0\.b, p0\.b
--.*: 25804060 orr p0\.b, p0/z, p3\.b, p0\.b
--.*: 25804060 orr p0\.b, p0/z, p3\.b, p0\.b
--.*: 258041e0 orr p0\.b, p0/z, p15\.b, p0\.b
--.*: 258041e0 orr p0\.b, p0/z, p15\.b, p0\.b
--.*: 25844000 orr p0\.b, p0/z, p0\.b, p4\.b
--.*: 25844000 orr p0\.b, p0/z, p0\.b, p4\.b
--.*: 258f4000 orr p0\.b, p0/z, p0\.b, p15\.b
--.*: 258f4000 orr p0\.b, p0/z, p0\.b, p15\.b
--.*: 25c04000 movs p0\.b, p0\.b
--.*: 25c04000 movs p0\.b, p0\.b
--.*: 25c04001 movs p1\.b, p0\.b
--.*: 25c04001 movs p1\.b, p0\.b
--.*: 25c0400f movs p15\.b, p0\.b
--.*: 25c0400f movs p15\.b, p0\.b
--.*: 25c04800 orrs p0\.b, p2/z, p0\.b, p0\.b
--.*: 25c04800 orrs p0\.b, p2/z, p0\.b, p0\.b
--.*: 25c07c00 orrs p0\.b, p15/z, p0\.b, p0\.b
--.*: 25c07c00 orrs p0\.b, p15/z, p0\.b, p0\.b
--.*: 25c04060 orrs p0\.b, p0/z, p3\.b, p0\.b
--.*: 25c04060 orrs p0\.b, p0/z, p3\.b, p0\.b
--.*: 25c041e0 orrs p0\.b, p0/z, p15\.b, p0\.b
--.*: 25c041e0 orrs p0\.b, p0/z, p15\.b, p0\.b
--.*: 25c44000 orrs p0\.b, p0/z, p0\.b, p4\.b
--.*: 25c44000 orrs p0\.b, p0/z, p0\.b, p4\.b
--.*: 25cf4000 orrs p0\.b, p0/z, p0\.b, p15\.b
--.*: 25cf4000 orrs p0\.b, p0/z, p0\.b, p15\.b
--.*: 04182000 orv b0, p0, z0\.b
--.*: 04182000 orv b0, p0, z0\.b
--.*: 04182001 orv b1, p0, z0\.b
--.*: 04182001 orv b1, p0, z0\.b
--.*: 0418201f orv b31, p0, z0\.b
--.*: 0418201f orv b31, p0, z0\.b
--.*: 04182800 orv b0, p2, z0\.b
--.*: 04182800 orv b0, p2, z0\.b
--.*: 04183c00 orv b0, p7, z0\.b
--.*: 04183c00 orv b0, p7, z0\.b
--.*: 04182060 orv b0, p0, z3\.b
--.*: 04182060 orv b0, p0, z3\.b
--.*: 041823e0 orv b0, p0, z31\.b
--.*: 041823e0 orv b0, p0, z31\.b
--.*: 04582000 orv h0, p0, z0\.h
--.*: 04582000 orv h0, p0, z0\.h
--.*: 04582001 orv h1, p0, z0\.h
--.*: 04582001 orv h1, p0, z0\.h
--.*: 0458201f orv h31, p0, z0\.h
--.*: 0458201f orv h31, p0, z0\.h
--.*: 04582800 orv h0, p2, z0\.h
--.*: 04582800 orv h0, p2, z0\.h
--.*: 04583c00 orv h0, p7, z0\.h
--.*: 04583c00 orv h0, p7, z0\.h
--.*: 04582060 orv h0, p0, z3\.h
--.*: 04582060 orv h0, p0, z3\.h
--.*: 045823e0 orv h0, p0, z31\.h
--.*: 045823e0 orv h0, p0, z31\.h
--.*: 04982000 orv s0, p0, z0\.s
--.*: 04982000 orv s0, p0, z0\.s
--.*: 04982001 orv s1, p0, z0\.s
--.*: 04982001 orv s1, p0, z0\.s
--.*: 0498201f orv s31, p0, z0\.s
--.*: 0498201f orv s31, p0, z0\.s
--.*: 04982800 orv s0, p2, z0\.s
--.*: 04982800 orv s0, p2, z0\.s
--.*: 04983c00 orv s0, p7, z0\.s
--.*: 04983c00 orv s0, p7, z0\.s
--.*: 04982060 orv s0, p0, z3\.s
--.*: 04982060 orv s0, p0, z3\.s
--.*: 049823e0 orv s0, p0, z31\.s
--.*: 049823e0 orv s0, p0, z31\.s
--.*: 04d82000 orv d0, p0, z0\.d
--.*: 04d82000 orv d0, p0, z0\.d
--.*: 04d82001 orv d1, p0, z0\.d
--.*: 04d82001 orv d1, p0, z0\.d
--.*: 04d8201f orv d31, p0, z0\.d
--.*: 04d8201f orv d31, p0, z0\.d
--.*: 04d82800 orv d0, p2, z0\.d
--.*: 04d82800 orv d0, p2, z0\.d
--.*: 04d83c00 orv d0, p7, z0\.d
--.*: 04d83c00 orv d0, p7, z0\.d
--.*: 04d82060 orv d0, p0, z3\.d
--.*: 04d82060 orv d0, p0, z3\.d
--.*: 04d823e0 orv d0, p0, z31\.d
--.*: 04d823e0 orv d0, p0, z31\.d
--.*: 2518e400 pfalse p0\.b
--.*: 2518e400 pfalse p0\.b
--.*: 2518e401 pfalse p1\.b
--.*: 2518e401 pfalse p1\.b
--.*: 2518e40f pfalse p15\.b
--.*: 2518e40f pfalse p15\.b
--.*: 2558c000 pfirst p0\.b, p0, p0\.b
--.*: 2558c000 pfirst p0\.b, p0, p0\.b
--.*: 2558c001 pfirst p1\.b, p0, p1\.b
--.*: 2558c001 pfirst p1\.b, p0, p1\.b
--.*: 2558c00f pfirst p15\.b, p0, p15\.b
--.*: 2558c00f pfirst p15\.b, p0, p15\.b
--.*: 2558c040 pfirst p0\.b, p2, p0\.b
--.*: 2558c040 pfirst p0\.b, p2, p0\.b
--.*: 2558c1e0 pfirst p0\.b, p15, p0\.b
--.*: 2558c1e0 pfirst p0\.b, p15, p0\.b
--.*: 2558c003 pfirst p3\.b, p0, p3\.b
--.*: 2558c003 pfirst p3\.b, p0, p3\.b
--.*: 2519c400 pnext p0\.b, p0, p0\.b
--.*: 2519c400 pnext p0\.b, p0, p0\.b
--.*: 2519c401 pnext p1\.b, p0, p1\.b
--.*: 2519c401 pnext p1\.b, p0, p1\.b
--.*: 2519c40f pnext p15\.b, p0, p15\.b
--.*: 2519c40f pnext p15\.b, p0, p15\.b
--.*: 2519c440 pnext p0\.b, p2, p0\.b
--.*: 2519c440 pnext p0\.b, p2, p0\.b
--.*: 2519c5e0 pnext p0\.b, p15, p0\.b
--.*: 2519c5e0 pnext p0\.b, p15, p0\.b
--.*: 2519c403 pnext p3\.b, p0, p3\.b
--.*: 2519c403 pnext p3\.b, p0, p3\.b
--.*: 2559c400 pnext p0\.h, p0, p0\.h
--.*: 2559c400 pnext p0\.h, p0, p0\.h
--.*: 2559c401 pnext p1\.h, p0, p1\.h
--.*: 2559c401 pnext p1\.h, p0, p1\.h
--.*: 2559c40f pnext p15\.h, p0, p15\.h
--.*: 2559c40f pnext p15\.h, p0, p15\.h
--.*: 2559c440 pnext p0\.h, p2, p0\.h
--.*: 2559c440 pnext p0\.h, p2, p0\.h
--.*: 2559c5e0 pnext p0\.h, p15, p0\.h
--.*: 2559c5e0 pnext p0\.h, p15, p0\.h
--.*: 2559c403 pnext p3\.h, p0, p3\.h
--.*: 2559c403 pnext p3\.h, p0, p3\.h
--.*: 2599c400 pnext p0\.s, p0, p0\.s
--.*: 2599c400 pnext p0\.s, p0, p0\.s
--.*: 2599c401 pnext p1\.s, p0, p1\.s
--.*: 2599c401 pnext p1\.s, p0, p1\.s
--.*: 2599c40f pnext p15\.s, p0, p15\.s
--.*: 2599c40f pnext p15\.s, p0, p15\.s
--.*: 2599c440 pnext p0\.s, p2, p0\.s
--.*: 2599c440 pnext p0\.s, p2, p0\.s
--.*: 2599c5e0 pnext p0\.s, p15, p0\.s
--.*: 2599c5e0 pnext p0\.s, p15, p0\.s
--.*: 2599c403 pnext p3\.s, p0, p3\.s
--.*: 2599c403 pnext p3\.s, p0, p3\.s
--.*: 25d9c400 pnext p0\.d, p0, p0\.d
--.*: 25d9c400 pnext p0\.d, p0, p0\.d
--.*: 25d9c401 pnext p1\.d, p0, p1\.d
--.*: 25d9c401 pnext p1\.d, p0, p1\.d
--.*: 25d9c40f pnext p15\.d, p0, p15\.d
--.*: 25d9c40f pnext p15\.d, p0, p15\.d
--.*: 25d9c440 pnext p0\.d, p2, p0\.d
--.*: 25d9c440 pnext p0\.d, p2, p0\.d
--.*: 25d9c5e0 pnext p0\.d, p15, p0\.d
--.*: 25d9c5e0 pnext p0\.d, p15, p0\.d
--.*: 25d9c403 pnext p3\.d, p0, p3\.d
--.*: 25d9c403 pnext p3\.d, p0, p3\.d
--.*: 8400c000 prfb pldl1keep, p0, \[x0, x0\]
--.*: 8400c000 prfb pldl1keep, p0, \[x0, x0\]
--.*: 8400c000 prfb pldl1keep, p0, \[x0, x0\]
--.*: 8400c001 prfb pldl1strm, p0, \[x0, x0\]
--.*: 8400c001 prfb pldl1strm, p0, \[x0, x0\]
--.*: 8400c001 prfb pldl1strm, p0, \[x0, x0\]
--.*: 8400c002 prfb pldl2keep, p0, \[x0, x0\]
--.*: 8400c002 prfb pldl2keep, p0, \[x0, x0\]
--.*: 8400c002 prfb pldl2keep, p0, \[x0, x0\]
--.*: 8400c003 prfb pldl2strm, p0, \[x0, x0\]
--.*: 8400c003 prfb pldl2strm, p0, \[x0, x0\]
--.*: 8400c003 prfb pldl2strm, p0, \[x0, x0\]
--.*: 8400c004 prfb pldl3keep, p0, \[x0, x0\]
--.*: 8400c004 prfb pldl3keep, p0, \[x0, x0\]
--.*: 8400c004 prfb pldl3keep, p0, \[x0, x0\]
--.*: 8400c005 prfb pldl3strm, p0, \[x0, x0\]
--.*: 8400c005 prfb pldl3strm, p0, \[x0, x0\]
--.*: 8400c005 prfb pldl3strm, p0, \[x0, x0\]
--.*: 8400c006 prfb #6, p0, \[x0, x0\]
--.*: 8400c006 prfb #6, p0, \[x0, x0\]
--.*: 8400c006 prfb #6, p0, \[x0, x0\]
--.*: 8400c007 prfb #7, p0, \[x0, x0\]
--.*: 8400c007 prfb #7, p0, \[x0, x0\]
--.*: 8400c007 prfb #7, p0, \[x0, x0\]
--.*: 8400c008 prfb pstl1keep, p0, \[x0, x0\]
--.*: 8400c008 prfb pstl1keep, p0, \[x0, x0\]
--.*: 8400c008 prfb pstl1keep, p0, \[x0, x0\]
--.*: 8400c009 prfb pstl1strm, p0, \[x0, x0\]
--.*: 8400c009 prfb pstl1strm, p0, \[x0, x0\]
--.*: 8400c009 prfb pstl1strm, p0, \[x0, x0\]
--.*: 8400c00a prfb pstl2keep, p0, \[x0, x0\]
--.*: 8400c00a prfb pstl2keep, p0, \[x0, x0\]
--.*: 8400c00a prfb pstl2keep, p0, \[x0, x0\]
--.*: 8400c00b prfb pstl2strm, p0, \[x0, x0\]
--.*: 8400c00b prfb pstl2strm, p0, \[x0, x0\]
--.*: 8400c00b prfb pstl2strm, p0, \[x0, x0\]
--.*: 8400c00c prfb pstl3keep, p0, \[x0, x0\]
--.*: 8400c00c prfb pstl3keep, p0, \[x0, x0\]
--.*: 8400c00c prfb pstl3keep, p0, \[x0, x0\]
--.*: 8400c00d prfb pstl3strm, p0, \[x0, x0\]
--.*: 8400c00d prfb pstl3strm, p0, \[x0, x0\]
--.*: 8400c00d prfb pstl3strm, p0, \[x0, x0\]
--.*: 8400c00e prfb #14, p0, \[x0, x0\]
--.*: 8400c00e prfb #14, p0, \[x0, x0\]
--.*: 8400c00e prfb #14, p0, \[x0, x0\]
--.*: 8400c00f prfb #15, p0, \[x0, x0\]
--.*: 8400c00f prfb #15, p0, \[x0, x0\]
--.*: 8400c00f prfb #15, p0, \[x0, x0\]
--.*: 8400c800 prfb pldl1keep, p2, \[x0, x0\]
--.*: 8400c800 prfb pldl1keep, p2, \[x0, x0\]
--.*: 8400c800 prfb pldl1keep, p2, \[x0, x0\]
--.*: 8400dc00 prfb pldl1keep, p7, \[x0, x0\]
--.*: 8400dc00 prfb pldl1keep, p7, \[x0, x0\]
--.*: 8400dc00 prfb pldl1keep, p7, \[x0, x0\]
--.*: 8400c060 prfb pldl1keep, p0, \[x3, x0\]
--.*: 8400c060 prfb pldl1keep, p0, \[x3, x0\]
--.*: 8400c060 prfb pldl1keep, p0, \[x3, x0\]
--.*: 8400c3e0 prfb pldl1keep, p0, \[sp, x0\]
--.*: 8400c3e0 prfb pldl1keep, p0, \[sp, x0\]
--.*: 8400c3e0 prfb pldl1keep, p0, \[sp, x0\]
--.*: 8404c000 prfb pldl1keep, p0, \[x0, x4\]
--.*: 8404c000 prfb pldl1keep, p0, \[x0, x4\]
--.*: 8404c000 prfb pldl1keep, p0, \[x0, x4\]
--.*: 841ec000 prfb pldl1keep, p0, \[x0, x30\]
--.*: 841ec000 prfb pldl1keep, p0, \[x0, x30\]
--.*: 841ec000 prfb pldl1keep, p0, \[x0, x30\]
--.*: 84200000 prfb pldl1keep, p0, \[x0, z0\.s, uxtw\]
--.*: 84200000 prfb pldl1keep, p0, \[x0, z0\.s, uxtw\]
--.*: 84200000 prfb pldl1keep, p0, \[x0, z0\.s, uxtw\]
--.*: 84200001 prfb pldl1strm, p0, \[x0, z0\.s, uxtw\]
--.*: 84200001 prfb pldl1strm, p0, \[x0, z0\.s, uxtw\]
--.*: 84200001 prfb pldl1strm, p0, \[x0, z0\.s, uxtw\]
--.*: 84200002 prfb pldl2keep, p0, \[x0, z0\.s, uxtw\]
--.*: 84200002 prfb pldl2keep, p0, \[x0, z0\.s, uxtw\]
--.*: 84200002 prfb pldl2keep, p0, \[x0, z0\.s, uxtw\]
--.*: 84200003 prfb pldl2strm, p0, \[x0, z0\.s, uxtw\]
--.*: 84200003 prfb pldl2strm, p0, \[x0, z0\.s, uxtw\]
--.*: 84200003 prfb pldl2strm, p0, \[x0, z0\.s, uxtw\]
--.*: 84200004 prfb pldl3keep, p0, \[x0, z0\.s, uxtw\]
--.*: 84200004 prfb pldl3keep, p0, \[x0, z0\.s, uxtw\]
--.*: 84200004 prfb pldl3keep, p0, \[x0, z0\.s, uxtw\]
--.*: 84200005 prfb pldl3strm, p0, \[x0, z0\.s, uxtw\]
--.*: 84200005 prfb pldl3strm, p0, \[x0, z0\.s, uxtw\]
--.*: 84200005 prfb pldl3strm, p0, \[x0, z0\.s, uxtw\]
--.*: 84200006 prfb #6, p0, \[x0, z0\.s, uxtw\]
--.*: 84200006 prfb #6, p0, \[x0, z0\.s, uxtw\]
--.*: 84200006 prfb #6, p0, \[x0, z0\.s, uxtw\]
--.*: 84200007 prfb #7, p0, \[x0, z0\.s, uxtw\]
--.*: 84200007 prfb #7, p0, \[x0, z0\.s, uxtw\]
--.*: 84200007 prfb #7, p0, \[x0, z0\.s, uxtw\]
--.*: 84200008 prfb pstl1keep, p0, \[x0, z0\.s, uxtw\]
--.*: 84200008 prfb pstl1keep, p0, \[x0, z0\.s, uxtw\]
--.*: 84200008 prfb pstl1keep, p0, \[x0, z0\.s, uxtw\]
--.*: 84200009 prfb pstl1strm, p0, \[x0, z0\.s, uxtw\]
--.*: 84200009 prfb pstl1strm, p0, \[x0, z0\.s, uxtw\]
--.*: 84200009 prfb pstl1strm, p0, \[x0, z0\.s, uxtw\]
--.*: 8420000a prfb pstl2keep, p0, \[x0, z0\.s, uxtw\]
--.*: 8420000a prfb pstl2keep, p0, \[x0, z0\.s, uxtw\]
--.*: 8420000a prfb pstl2keep, p0, \[x0, z0\.s, uxtw\]
--.*: 8420000b prfb pstl2strm, p0, \[x0, z0\.s, uxtw\]
--.*: 8420000b prfb pstl2strm, p0, \[x0, z0\.s, uxtw\]
--.*: 8420000b prfb pstl2strm, p0, \[x0, z0\.s, uxtw\]
--.*: 8420000c prfb pstl3keep, p0, \[x0, z0\.s, uxtw\]
--.*: 8420000c prfb pstl3keep, p0, \[x0, z0\.s, uxtw\]
--.*: 8420000c prfb pstl3keep, p0, \[x0, z0\.s, uxtw\]
--.*: 8420000d prfb pstl3strm, p0, \[x0, z0\.s, uxtw\]
--.*: 8420000d prfb pstl3strm, p0, \[x0, z0\.s, uxtw\]
--.*: 8420000d prfb pstl3strm, p0, \[x0, z0\.s, uxtw\]
--.*: 8420000e prfb #14, p0, \[x0, z0\.s, uxtw\]
--.*: 8420000e prfb #14, p0, \[x0, z0\.s, uxtw\]
--.*: 8420000e prfb #14, p0, \[x0, z0\.s, uxtw\]
--.*: 8420000f prfb #15, p0, \[x0, z0\.s, uxtw\]
--.*: 8420000f prfb #15, p0, \[x0, z0\.s, uxtw\]
--.*: 8420000f prfb #15, p0, \[x0, z0\.s, uxtw\]
--.*: 84200800 prfb pldl1keep, p2, \[x0, z0\.s, uxtw\]
--.*: 84200800 prfb pldl1keep, p2, \[x0, z0\.s, uxtw\]
--.*: 84200800 prfb pldl1keep, p2, \[x0, z0\.s, uxtw\]
--.*: 84201c00 prfb pldl1keep, p7, \[x0, z0\.s, uxtw\]
--.*: 84201c00 prfb pldl1keep, p7, \[x0, z0\.s, uxtw\]
--.*: 84201c00 prfb pldl1keep, p7, \[x0, z0\.s, uxtw\]
--.*: 84200060 prfb pldl1keep, p0, \[x3, z0\.s, uxtw\]
--.*: 84200060 prfb pldl1keep, p0, \[x3, z0\.s, uxtw\]
--.*: 84200060 prfb pldl1keep, p0, \[x3, z0\.s, uxtw\]
--.*: 842003e0 prfb pldl1keep, p0, \[sp, z0\.s, uxtw\]
--.*: 842003e0 prfb pldl1keep, p0, \[sp, z0\.s, uxtw\]
--.*: 842003e0 prfb pldl1keep, p0, \[sp, z0\.s, uxtw\]
--.*: 84240000 prfb pldl1keep, p0, \[x0, z4\.s, uxtw\]
--.*: 84240000 prfb pldl1keep, p0, \[x0, z4\.s, uxtw\]
--.*: 84240000 prfb pldl1keep, p0, \[x0, z4\.s, uxtw\]
--.*: 843f0000 prfb pldl1keep, p0, \[x0, z31\.s, uxtw\]
--.*: 843f0000 prfb pldl1keep, p0, \[x0, z31\.s, uxtw\]
--.*: 843f0000 prfb pldl1keep, p0, \[x0, z31\.s, uxtw\]
--.*: 84600000 prfb pldl1keep, p0, \[x0, z0\.s, sxtw\]
--.*: 84600000 prfb pldl1keep, p0, \[x0, z0\.s, sxtw\]
--.*: 84600000 prfb pldl1keep, p0, \[x0, z0\.s, sxtw\]
--.*: 84600001 prfb pldl1strm, p0, \[x0, z0\.s, sxtw\]
--.*: 84600001 prfb pldl1strm, p0, \[x0, z0\.s, sxtw\]
--.*: 84600001 prfb pldl1strm, p0, \[x0, z0\.s, sxtw\]
--.*: 84600002 prfb pldl2keep, p0, \[x0, z0\.s, sxtw\]
--.*: 84600002 prfb pldl2keep, p0, \[x0, z0\.s, sxtw\]
--.*: 84600002 prfb pldl2keep, p0, \[x0, z0\.s, sxtw\]
--.*: 84600003 prfb pldl2strm, p0, \[x0, z0\.s, sxtw\]
--.*: 84600003 prfb pldl2strm, p0, \[x0, z0\.s, sxtw\]
--.*: 84600003 prfb pldl2strm, p0, \[x0, z0\.s, sxtw\]
--.*: 84600004 prfb pldl3keep, p0, \[x0, z0\.s, sxtw\]
--.*: 84600004 prfb pldl3keep, p0, \[x0, z0\.s, sxtw\]
--.*: 84600004 prfb pldl3keep, p0, \[x0, z0\.s, sxtw\]
--.*: 84600005 prfb pldl3strm, p0, \[x0, z0\.s, sxtw\]
--.*: 84600005 prfb pldl3strm, p0, \[x0, z0\.s, sxtw\]
--.*: 84600005 prfb pldl3strm, p0, \[x0, z0\.s, sxtw\]
--.*: 84600006 prfb #6, p0, \[x0, z0\.s, sxtw\]
--.*: 84600006 prfb #6, p0, \[x0, z0\.s, sxtw\]
--.*: 84600006 prfb #6, p0, \[x0, z0\.s, sxtw\]
--.*: 84600007 prfb #7, p0, \[x0, z0\.s, sxtw\]
--.*: 84600007 prfb #7, p0, \[x0, z0\.s, sxtw\]
--.*: 84600007 prfb #7, p0, \[x0, z0\.s, sxtw\]
--.*: 84600008 prfb pstl1keep, p0, \[x0, z0\.s, sxtw\]
--.*: 84600008 prfb pstl1keep, p0, \[x0, z0\.s, sxtw\]
--.*: 84600008 prfb pstl1keep, p0, \[x0, z0\.s, sxtw\]
--.*: 84600009 prfb pstl1strm, p0, \[x0, z0\.s, sxtw\]
--.*: 84600009 prfb pstl1strm, p0, \[x0, z0\.s, sxtw\]
--.*: 84600009 prfb pstl1strm, p0, \[x0, z0\.s, sxtw\]
--.*: 8460000a prfb pstl2keep, p0, \[x0, z0\.s, sxtw\]
--.*: 8460000a prfb pstl2keep, p0, \[x0, z0\.s, sxtw\]
--.*: 8460000a prfb pstl2keep, p0, \[x0, z0\.s, sxtw\]
--.*: 8460000b prfb pstl2strm, p0, \[x0, z0\.s, sxtw\]
--.*: 8460000b prfb pstl2strm, p0, \[x0, z0\.s, sxtw\]
--.*: 8460000b prfb pstl2strm, p0, \[x0, z0\.s, sxtw\]
--.*: 8460000c prfb pstl3keep, p0, \[x0, z0\.s, sxtw\]
--.*: 8460000c prfb pstl3keep, p0, \[x0, z0\.s, sxtw\]
--.*: 8460000c prfb pstl3keep, p0, \[x0, z0\.s, sxtw\]
--.*: 8460000d prfb pstl3strm, p0, \[x0, z0\.s, sxtw\]
--.*: 8460000d prfb pstl3strm, p0, \[x0, z0\.s, sxtw\]
--.*: 8460000d prfb pstl3strm, p0, \[x0, z0\.s, sxtw\]
--.*: 8460000e prfb #14, p0, \[x0, z0\.s, sxtw\]
--.*: 8460000e prfb #14, p0, \[x0, z0\.s, sxtw\]
--.*: 8460000e prfb #14, p0, \[x0, z0\.s, sxtw\]
--.*: 8460000f prfb #15, p0, \[x0, z0\.s, sxtw\]
--.*: 8460000f prfb #15, p0, \[x0, z0\.s, sxtw\]
--.*: 8460000f prfb #15, p0, \[x0, z0\.s, sxtw\]
--.*: 84600800 prfb pldl1keep, p2, \[x0, z0\.s, sxtw\]
--.*: 84600800 prfb pldl1keep, p2, \[x0, z0\.s, sxtw\]
--.*: 84600800 prfb pldl1keep, p2, \[x0, z0\.s, sxtw\]
--.*: 84601c00 prfb pldl1keep, p7, \[x0, z0\.s, sxtw\]
--.*: 84601c00 prfb pldl1keep, p7, \[x0, z0\.s, sxtw\]
--.*: 84601c00 prfb pldl1keep, p7, \[x0, z0\.s, sxtw\]
--.*: 84600060 prfb pldl1keep, p0, \[x3, z0\.s, sxtw\]
--.*: 84600060 prfb pldl1keep, p0, \[x3, z0\.s, sxtw\]
--.*: 84600060 prfb pldl1keep, p0, \[x3, z0\.s, sxtw\]
--.*: 846003e0 prfb pldl1keep, p0, \[sp, z0\.s, sxtw\]
--.*: 846003e0 prfb pldl1keep, p0, \[sp, z0\.s, sxtw\]
--.*: 846003e0 prfb pldl1keep, p0, \[sp, z0\.s, sxtw\]
--.*: 84640000 prfb pldl1keep, p0, \[x0, z4\.s, sxtw\]
--.*: 84640000 prfb pldl1keep, p0, \[x0, z4\.s, sxtw\]
--.*: 84640000 prfb pldl1keep, p0, \[x0, z4\.s, sxtw\]
--.*: 847f0000 prfb pldl1keep, p0, \[x0, z31\.s, sxtw\]
--.*: 847f0000 prfb pldl1keep, p0, \[x0, z31\.s, sxtw\]
--.*: 847f0000 prfb pldl1keep, p0, \[x0, z31\.s, sxtw\]
--.*: c4200000 prfb pldl1keep, p0, \[x0, z0\.d, uxtw\]
--.*: c4200000 prfb pldl1keep, p0, \[x0, z0\.d, uxtw\]
--.*: c4200000 prfb pldl1keep, p0, \[x0, z0\.d, uxtw\]
--.*: c4200001 prfb pldl1strm, p0, \[x0, z0\.d, uxtw\]
--.*: c4200001 prfb pldl1strm, p0, \[x0, z0\.d, uxtw\]
--.*: c4200001 prfb pldl1strm, p0, \[x0, z0\.d, uxtw\]
--.*: c4200002 prfb pldl2keep, p0, \[x0, z0\.d, uxtw\]
--.*: c4200002 prfb pldl2keep, p0, \[x0, z0\.d, uxtw\]
--.*: c4200002 prfb pldl2keep, p0, \[x0, z0\.d, uxtw\]
--.*: c4200003 prfb pldl2strm, p0, \[x0, z0\.d, uxtw\]
--.*: c4200003 prfb pldl2strm, p0, \[x0, z0\.d, uxtw\]
--.*: c4200003 prfb pldl2strm, p0, \[x0, z0\.d, uxtw\]
--.*: c4200004 prfb pldl3keep, p0, \[x0, z0\.d, uxtw\]
--.*: c4200004 prfb pldl3keep, p0, \[x0, z0\.d, uxtw\]
--.*: c4200004 prfb pldl3keep, p0, \[x0, z0\.d, uxtw\]
--.*: c4200005 prfb pldl3strm, p0, \[x0, z0\.d, uxtw\]
--.*: c4200005 prfb pldl3strm, p0, \[x0, z0\.d, uxtw\]
--.*: c4200005 prfb pldl3strm, p0, \[x0, z0\.d, uxtw\]
--.*: c4200006 prfb #6, p0, \[x0, z0\.d, uxtw\]
--.*: c4200006 prfb #6, p0, \[x0, z0\.d, uxtw\]
--.*: c4200006 prfb #6, p0, \[x0, z0\.d, uxtw\]
--.*: c4200007 prfb #7, p0, \[x0, z0\.d, uxtw\]
--.*: c4200007 prfb #7, p0, \[x0, z0\.d, uxtw\]
--.*: c4200007 prfb #7, p0, \[x0, z0\.d, uxtw\]
--.*: c4200008 prfb pstl1keep, p0, \[x0, z0\.d, uxtw\]
--.*: c4200008 prfb pstl1keep, p0, \[x0, z0\.d, uxtw\]
--.*: c4200008 prfb pstl1keep, p0, \[x0, z0\.d, uxtw\]
--.*: c4200009 prfb pstl1strm, p0, \[x0, z0\.d, uxtw\]
--.*: c4200009 prfb pstl1strm, p0, \[x0, z0\.d, uxtw\]
--.*: c4200009 prfb pstl1strm, p0, \[x0, z0\.d, uxtw\]
--.*: c420000a prfb pstl2keep, p0, \[x0, z0\.d, uxtw\]
--.*: c420000a prfb pstl2keep, p0, \[x0, z0\.d, uxtw\]
--.*: c420000a prfb pstl2keep, p0, \[x0, z0\.d, uxtw\]
--.*: c420000b prfb pstl2strm, p0, \[x0, z0\.d, uxtw\]
--.*: c420000b prfb pstl2strm, p0, \[x0, z0\.d, uxtw\]
--.*: c420000b prfb pstl2strm, p0, \[x0, z0\.d, uxtw\]
--.*: c420000c prfb pstl3keep, p0, \[x0, z0\.d, uxtw\]
--.*: c420000c prfb pstl3keep, p0, \[x0, z0\.d, uxtw\]
--.*: c420000c prfb pstl3keep, p0, \[x0, z0\.d, uxtw\]
--.*: c420000d prfb pstl3strm, p0, \[x0, z0\.d, uxtw\]
--.*: c420000d prfb pstl3strm, p0, \[x0, z0\.d, uxtw\]
--.*: c420000d prfb pstl3strm, p0, \[x0, z0\.d, uxtw\]
--.*: c420000e prfb #14, p0, \[x0, z0\.d, uxtw\]
--.*: c420000e prfb #14, p0, \[x0, z0\.d, uxtw\]
--.*: c420000e prfb #14, p0, \[x0, z0\.d, uxtw\]
--.*: c420000f prfb #15, p0, \[x0, z0\.d, uxtw\]
--.*: c420000f prfb #15, p0, \[x0, z0\.d, uxtw\]
--.*: c420000f prfb #15, p0, \[x0, z0\.d, uxtw\]
--.*: c4200800 prfb pldl1keep, p2, \[x0, z0\.d, uxtw\]
--.*: c4200800 prfb pldl1keep, p2, \[x0, z0\.d, uxtw\]
--.*: c4200800 prfb pldl1keep, p2, \[x0, z0\.d, uxtw\]
--.*: c4201c00 prfb pldl1keep, p7, \[x0, z0\.d, uxtw\]
--.*: c4201c00 prfb pldl1keep, p7, \[x0, z0\.d, uxtw\]
--.*: c4201c00 prfb pldl1keep, p7, \[x0, z0\.d, uxtw\]
--.*: c4200060 prfb pldl1keep, p0, \[x3, z0\.d, uxtw\]
--.*: c4200060 prfb pldl1keep, p0, \[x3, z0\.d, uxtw\]
--.*: c4200060 prfb pldl1keep, p0, \[x3, z0\.d, uxtw\]
--.*: c42003e0 prfb pldl1keep, p0, \[sp, z0\.d, uxtw\]
--.*: c42003e0 prfb pldl1keep, p0, \[sp, z0\.d, uxtw\]
--.*: c42003e0 prfb pldl1keep, p0, \[sp, z0\.d, uxtw\]
--.*: c4240000 prfb pldl1keep, p0, \[x0, z4\.d, uxtw\]
--.*: c4240000 prfb pldl1keep, p0, \[x0, z4\.d, uxtw\]
--.*: c4240000 prfb pldl1keep, p0, \[x0, z4\.d, uxtw\]
--.*: c43f0000 prfb pldl1keep, p0, \[x0, z31\.d, uxtw\]
--.*: c43f0000 prfb pldl1keep, p0, \[x0, z31\.d, uxtw\]
--.*: c43f0000 prfb pldl1keep, p0, \[x0, z31\.d, uxtw\]
--.*: c4600000 prfb pldl1keep, p0, \[x0, z0\.d, sxtw\]
--.*: c4600000 prfb pldl1keep, p0, \[x0, z0\.d, sxtw\]
--.*: c4600000 prfb pldl1keep, p0, \[x0, z0\.d, sxtw\]
--.*: c4600001 prfb pldl1strm, p0, \[x0, z0\.d, sxtw\]
--.*: c4600001 prfb pldl1strm, p0, \[x0, z0\.d, sxtw\]
--.*: c4600001 prfb pldl1strm, p0, \[x0, z0\.d, sxtw\]
--.*: c4600002 prfb pldl2keep, p0, \[x0, z0\.d, sxtw\]
--.*: c4600002 prfb pldl2keep, p0, \[x0, z0\.d, sxtw\]
--.*: c4600002 prfb pldl2keep, p0, \[x0, z0\.d, sxtw\]
--.*: c4600003 prfb pldl2strm, p0, \[x0, z0\.d, sxtw\]
--.*: c4600003 prfb pldl2strm, p0, \[x0, z0\.d, sxtw\]
--.*: c4600003 prfb pldl2strm, p0, \[x0, z0\.d, sxtw\]
--.*: c4600004 prfb pldl3keep, p0, \[x0, z0\.d, sxtw\]
--.*: c4600004 prfb pldl3keep, p0, \[x0, z0\.d, sxtw\]
--.*: c4600004 prfb pldl3keep, p0, \[x0, z0\.d, sxtw\]
--.*: c4600005 prfb pldl3strm, p0, \[x0, z0\.d, sxtw\]
--.*: c4600005 prfb pldl3strm, p0, \[x0, z0\.d, sxtw\]
--.*: c4600005 prfb pldl3strm, p0, \[x0, z0\.d, sxtw\]
--.*: c4600006 prfb #6, p0, \[x0, z0\.d, sxtw\]
--.*: c4600006 prfb #6, p0, \[x0, z0\.d, sxtw\]
--.*: c4600006 prfb #6, p0, \[x0, z0\.d, sxtw\]
--.*: c4600007 prfb #7, p0, \[x0, z0\.d, sxtw\]
--.*: c4600007 prfb #7, p0, \[x0, z0\.d, sxtw\]
--.*: c4600007 prfb #7, p0, \[x0, z0\.d, sxtw\]
--.*: c4600008 prfb pstl1keep, p0, \[x0, z0\.d, sxtw\]
--.*: c4600008 prfb pstl1keep, p0, \[x0, z0\.d, sxtw\]
--.*: c4600008 prfb pstl1keep, p0, \[x0, z0\.d, sxtw\]
--.*: c4600009 prfb pstl1strm, p0, \[x0, z0\.d, sxtw\]
--.*: c4600009 prfb pstl1strm, p0, \[x0, z0\.d, sxtw\]
--.*: c4600009 prfb pstl1strm, p0, \[x0, z0\.d, sxtw\]
--.*: c460000a prfb pstl2keep, p0, \[x0, z0\.d, sxtw\]
--.*: c460000a prfb pstl2keep, p0, \[x0, z0\.d, sxtw\]
--.*: c460000a prfb pstl2keep, p0, \[x0, z0\.d, sxtw\]
--.*: c460000b prfb pstl2strm, p0, \[x0, z0\.d, sxtw\]
--.*: c460000b prfb pstl2strm, p0, \[x0, z0\.d, sxtw\]
--.*: c460000b prfb pstl2strm, p0, \[x0, z0\.d, sxtw\]
--.*: c460000c prfb pstl3keep, p0, \[x0, z0\.d, sxtw\]
--.*: c460000c prfb pstl3keep, p0, \[x0, z0\.d, sxtw\]
--.*: c460000c prfb pstl3keep, p0, \[x0, z0\.d, sxtw\]
--.*: c460000d prfb pstl3strm, p0, \[x0, z0\.d, sxtw\]
--.*: c460000d prfb pstl3strm, p0, \[x0, z0\.d, sxtw\]
--.*: c460000d prfb pstl3strm, p0, \[x0, z0\.d, sxtw\]
--.*: c460000e prfb #14, p0, \[x0, z0\.d, sxtw\]
--.*: c460000e prfb #14, p0, \[x0, z0\.d, sxtw\]
--.*: c460000e prfb #14, p0, \[x0, z0\.d, sxtw\]
--.*: c460000f prfb #15, p0, \[x0, z0\.d, sxtw\]
--.*: c460000f prfb #15, p0, \[x0, z0\.d, sxtw\]
--.*: c460000f prfb #15, p0, \[x0, z0\.d, sxtw\]
--.*: c4600800 prfb pldl1keep, p2, \[x0, z0\.d, sxtw\]
--.*: c4600800 prfb pldl1keep, p2, \[x0, z0\.d, sxtw\]
--.*: c4600800 prfb pldl1keep, p2, \[x0, z0\.d, sxtw\]
--.*: c4601c00 prfb pldl1keep, p7, \[x0, z0\.d, sxtw\]
--.*: c4601c00 prfb pldl1keep, p7, \[x0, z0\.d, sxtw\]
--.*: c4601c00 prfb pldl1keep, p7, \[x0, z0\.d, sxtw\]
--.*: c4600060 prfb pldl1keep, p0, \[x3, z0\.d, sxtw\]
--.*: c4600060 prfb pldl1keep, p0, \[x3, z0\.d, sxtw\]
--.*: c4600060 prfb pldl1keep, p0, \[x3, z0\.d, sxtw\]
--.*: c46003e0 prfb pldl1keep, p0, \[sp, z0\.d, sxtw\]
--.*: c46003e0 prfb pldl1keep, p0, \[sp, z0\.d, sxtw\]
--.*: c46003e0 prfb pldl1keep, p0, \[sp, z0\.d, sxtw\]
--.*: c4640000 prfb pldl1keep, p0, \[x0, z4\.d, sxtw\]
--.*: c4640000 prfb pldl1keep, p0, \[x0, z4\.d, sxtw\]
--.*: c4640000 prfb pldl1keep, p0, \[x0, z4\.d, sxtw\]
--.*: c47f0000 prfb pldl1keep, p0, \[x0, z31\.d, sxtw\]
--.*: c47f0000 prfb pldl1keep, p0, \[x0, z31\.d, sxtw\]
--.*: c47f0000 prfb pldl1keep, p0, \[x0, z31\.d, sxtw\]
--.*: c4608000 prfb pldl1keep, p0, \[x0, z0\.d\]
--.*: c4608000 prfb pldl1keep, p0, \[x0, z0\.d\]
--.*: c4608000 prfb pldl1keep, p0, \[x0, z0\.d\]
--.*: c4608001 prfb pldl1strm, p0, \[x0, z0\.d\]
--.*: c4608001 prfb pldl1strm, p0, \[x0, z0\.d\]
--.*: c4608001 prfb pldl1strm, p0, \[x0, z0\.d\]
--.*: c4608002 prfb pldl2keep, p0, \[x0, z0\.d\]
--.*: c4608002 prfb pldl2keep, p0, \[x0, z0\.d\]
--.*: c4608002 prfb pldl2keep, p0, \[x0, z0\.d\]
--.*: c4608003 prfb pldl2strm, p0, \[x0, z0\.d\]
--.*: c4608003 prfb pldl2strm, p0, \[x0, z0\.d\]
--.*: c4608003 prfb pldl2strm, p0, \[x0, z0\.d\]
--.*: c4608004 prfb pldl3keep, p0, \[x0, z0\.d\]
--.*: c4608004 prfb pldl3keep, p0, \[x0, z0\.d\]
--.*: c4608004 prfb pldl3keep, p0, \[x0, z0\.d\]
--.*: c4608005 prfb pldl3strm, p0, \[x0, z0\.d\]
--.*: c4608005 prfb pldl3strm, p0, \[x0, z0\.d\]
--.*: c4608005 prfb pldl3strm, p0, \[x0, z0\.d\]
--.*: c4608006 prfb #6, p0, \[x0, z0\.d\]
--.*: c4608006 prfb #6, p0, \[x0, z0\.d\]
--.*: c4608006 prfb #6, p0, \[x0, z0\.d\]
--.*: c4608007 prfb #7, p0, \[x0, z0\.d\]
--.*: c4608007 prfb #7, p0, \[x0, z0\.d\]
--.*: c4608007 prfb #7, p0, \[x0, z0\.d\]
--.*: c4608008 prfb pstl1keep, p0, \[x0, z0\.d\]
--.*: c4608008 prfb pstl1keep, p0, \[x0, z0\.d\]
--.*: c4608008 prfb pstl1keep, p0, \[x0, z0\.d\]
--.*: c4608009 prfb pstl1strm, p0, \[x0, z0\.d\]
--.*: c4608009 prfb pstl1strm, p0, \[x0, z0\.d\]
--.*: c4608009 prfb pstl1strm, p0, \[x0, z0\.d\]
--.*: c460800a prfb pstl2keep, p0, \[x0, z0\.d\]
--.*: c460800a prfb pstl2keep, p0, \[x0, z0\.d\]
--.*: c460800a prfb pstl2keep, p0, \[x0, z0\.d\]
--.*: c460800b prfb pstl2strm, p0, \[x0, z0\.d\]
--.*: c460800b prfb pstl2strm, p0, \[x0, z0\.d\]
--.*: c460800b prfb pstl2strm, p0, \[x0, z0\.d\]
--.*: c460800c prfb pstl3keep, p0, \[x0, z0\.d\]
--.*: c460800c prfb pstl3keep, p0, \[x0, z0\.d\]
--.*: c460800c prfb pstl3keep, p0, \[x0, z0\.d\]
--.*: c460800d prfb pstl3strm, p0, \[x0, z0\.d\]
--.*: c460800d prfb pstl3strm, p0, \[x0, z0\.d\]
--.*: c460800d prfb pstl3strm, p0, \[x0, z0\.d\]
--.*: c460800e prfb #14, p0, \[x0, z0\.d\]
--.*: c460800e prfb #14, p0, \[x0, z0\.d\]
--.*: c460800e prfb #14, p0, \[x0, z0\.d\]
--.*: c460800f prfb #15, p0, \[x0, z0\.d\]
--.*: c460800f prfb #15, p0, \[x0, z0\.d\]
--.*: c460800f prfb #15, p0, \[x0, z0\.d\]
--.*: c4608800 prfb pldl1keep, p2, \[x0, z0\.d\]
--.*: c4608800 prfb pldl1keep, p2, \[x0, z0\.d\]
--.*: c4608800 prfb pldl1keep, p2, \[x0, z0\.d\]
--.*: c4609c00 prfb pldl1keep, p7, \[x0, z0\.d\]
--.*: c4609c00 prfb pldl1keep, p7, \[x0, z0\.d\]
--.*: c4609c00 prfb pldl1keep, p7, \[x0, z0\.d\]
--.*: c4608060 prfb pldl1keep, p0, \[x3, z0\.d\]
--.*: c4608060 prfb pldl1keep, p0, \[x3, z0\.d\]
--.*: c4608060 prfb pldl1keep, p0, \[x3, z0\.d\]
--.*: c46083e0 prfb pldl1keep, p0, \[sp, z0\.d\]
--.*: c46083e0 prfb pldl1keep, p0, \[sp, z0\.d\]
--.*: c46083e0 prfb pldl1keep, p0, \[sp, z0\.d\]
--.*: c4648000 prfb pldl1keep, p0, \[x0, z4\.d\]
--.*: c4648000 prfb pldl1keep, p0, \[x0, z4\.d\]
--.*: c4648000 prfb pldl1keep, p0, \[x0, z4\.d\]
--.*: c47f8000 prfb pldl1keep, p0, \[x0, z31\.d\]
--.*: c47f8000 prfb pldl1keep, p0, \[x0, z31\.d\]
--.*: c47f8000 prfb pldl1keep, p0, \[x0, z31\.d\]
--.*: 8400e000 prfb pldl1keep, p0, \[z0\.s\]
--.*: 8400e000 prfb pldl1keep, p0, \[z0\.s\]
--.*: 8400e000 prfb pldl1keep, p0, \[z0\.s\]
--.*: 8400e001 prfb pldl1strm, p0, \[z0\.s\]
--.*: 8400e001 prfb pldl1strm, p0, \[z0\.s\]
--.*: 8400e001 prfb pldl1strm, p0, \[z0\.s\]
--.*: 8400e002 prfb pldl2keep, p0, \[z0\.s\]
--.*: 8400e002 prfb pldl2keep, p0, \[z0\.s\]
--.*: 8400e002 prfb pldl2keep, p0, \[z0\.s\]
--.*: 8400e003 prfb pldl2strm, p0, \[z0\.s\]
--.*: 8400e003 prfb pldl2strm, p0, \[z0\.s\]
--.*: 8400e003 prfb pldl2strm, p0, \[z0\.s\]
--.*: 8400e004 prfb pldl3keep, p0, \[z0\.s\]
--.*: 8400e004 prfb pldl3keep, p0, \[z0\.s\]
--.*: 8400e004 prfb pldl3keep, p0, \[z0\.s\]
--.*: 8400e005 prfb pldl3strm, p0, \[z0\.s\]
--.*: 8400e005 prfb pldl3strm, p0, \[z0\.s\]
--.*: 8400e005 prfb pldl3strm, p0, \[z0\.s\]
--.*: 8400e006 prfb #6, p0, \[z0\.s\]
--.*: 8400e006 prfb #6, p0, \[z0\.s\]
--.*: 8400e006 prfb #6, p0, \[z0\.s\]
--.*: 8400e007 prfb #7, p0, \[z0\.s\]
--.*: 8400e007 prfb #7, p0, \[z0\.s\]
--.*: 8400e007 prfb #7, p0, \[z0\.s\]
--.*: 8400e008 prfb pstl1keep, p0, \[z0\.s\]
--.*: 8400e008 prfb pstl1keep, p0, \[z0\.s\]
--.*: 8400e008 prfb pstl1keep, p0, \[z0\.s\]
--.*: 8400e009 prfb pstl1strm, p0, \[z0\.s\]
--.*: 8400e009 prfb pstl1strm, p0, \[z0\.s\]
--.*: 8400e009 prfb pstl1strm, p0, \[z0\.s\]
--.*: 8400e00a prfb pstl2keep, p0, \[z0\.s\]
--.*: 8400e00a prfb pstl2keep, p0, \[z0\.s\]
--.*: 8400e00a prfb pstl2keep, p0, \[z0\.s\]
--.*: 8400e00b prfb pstl2strm, p0, \[z0\.s\]
--.*: 8400e00b prfb pstl2strm, p0, \[z0\.s\]
--.*: 8400e00b prfb pstl2strm, p0, \[z0\.s\]
--.*: 8400e00c prfb pstl3keep, p0, \[z0\.s\]
--.*: 8400e00c prfb pstl3keep, p0, \[z0\.s\]
--.*: 8400e00c prfb pstl3keep, p0, \[z0\.s\]
--.*: 8400e00d prfb pstl3strm, p0, \[z0\.s\]
--.*: 8400e00d prfb pstl3strm, p0, \[z0\.s\]
--.*: 8400e00d prfb pstl3strm, p0, \[z0\.s\]
--.*: 8400e00e prfb #14, p0, \[z0\.s\]
--.*: 8400e00e prfb #14, p0, \[z0\.s\]
--.*: 8400e00e prfb #14, p0, \[z0\.s\]
--.*: 8400e00f prfb #15, p0, \[z0\.s\]
--.*: 8400e00f prfb #15, p0, \[z0\.s\]
--.*: 8400e00f prfb #15, p0, \[z0\.s\]
--.*: 8400e800 prfb pldl1keep, p2, \[z0\.s\]
--.*: 8400e800 prfb pldl1keep, p2, \[z0\.s\]
--.*: 8400e800 prfb pldl1keep, p2, \[z0\.s\]
--.*: 8400fc00 prfb pldl1keep, p7, \[z0\.s\]
--.*: 8400fc00 prfb pldl1keep, p7, \[z0\.s\]
--.*: 8400fc00 prfb pldl1keep, p7, \[z0\.s\]
--.*: 8400e060 prfb pldl1keep, p0, \[z3\.s\]
--.*: 8400e060 prfb pldl1keep, p0, \[z3\.s\]
--.*: 8400e060 prfb pldl1keep, p0, \[z3\.s\]
--.*: 8400e3e0 prfb pldl1keep, p0, \[z31\.s\]
--.*: 8400e3e0 prfb pldl1keep, p0, \[z31\.s\]
--.*: 8400e3e0 prfb pldl1keep, p0, \[z31\.s\]
--.*: 840fe000 prfb pldl1keep, p0, \[z0\.s, #15\]
--.*: 840fe000 prfb pldl1keep, p0, \[z0\.s, #15\]
--.*: 8410e000 prfb pldl1keep, p0, \[z0\.s, #16\]
--.*: 8410e000 prfb pldl1keep, p0, \[z0\.s, #16\]
--.*: 8411e000 prfb pldl1keep, p0, \[z0\.s, #17\]
--.*: 8411e000 prfb pldl1keep, p0, \[z0\.s, #17\]
--.*: 841fe000 prfb pldl1keep, p0, \[z0\.s, #31\]
--.*: 841fe000 prfb pldl1keep, p0, \[z0\.s, #31\]
--.*: 85c00000 prfb pldl1keep, p0, \[x0\]
--.*: 85c00000 prfb pldl1keep, p0, \[x0\]
--.*: 85c00000 prfb pldl1keep, p0, \[x0\]
--.*: 85c00000 prfb pldl1keep, p0, \[x0\]
--.*: 85c00001 prfb pldl1strm, p0, \[x0\]
--.*: 85c00001 prfb pldl1strm, p0, \[x0\]
--.*: 85c00001 prfb pldl1strm, p0, \[x0\]
--.*: 85c00001 prfb pldl1strm, p0, \[x0\]
--.*: 85c00002 prfb pldl2keep, p0, \[x0\]
--.*: 85c00002 prfb pldl2keep, p0, \[x0\]
--.*: 85c00002 prfb pldl2keep, p0, \[x0\]
--.*: 85c00002 prfb pldl2keep, p0, \[x0\]
--.*: 85c00003 prfb pldl2strm, p0, \[x0\]
--.*: 85c00003 prfb pldl2strm, p0, \[x0\]
--.*: 85c00003 prfb pldl2strm, p0, \[x0\]
--.*: 85c00003 prfb pldl2strm, p0, \[x0\]
--.*: 85c00004 prfb pldl3keep, p0, \[x0\]
--.*: 85c00004 prfb pldl3keep, p0, \[x0\]
--.*: 85c00004 prfb pldl3keep, p0, \[x0\]
--.*: 85c00004 prfb pldl3keep, p0, \[x0\]
--.*: 85c00005 prfb pldl3strm, p0, \[x0\]
--.*: 85c00005 prfb pldl3strm, p0, \[x0\]
--.*: 85c00005 prfb pldl3strm, p0, \[x0\]
--.*: 85c00005 prfb pldl3strm, p0, \[x0\]
--.*: 85c00006 prfb #6, p0, \[x0\]
--.*: 85c00006 prfb #6, p0, \[x0\]
--.*: 85c00006 prfb #6, p0, \[x0\]
--.*: 85c00006 prfb #6, p0, \[x0\]
--.*: 85c00007 prfb #7, p0, \[x0\]
--.*: 85c00007 prfb #7, p0, \[x0\]
--.*: 85c00007 prfb #7, p0, \[x0\]
--.*: 85c00007 prfb #7, p0, \[x0\]
--.*: 85c00008 prfb pstl1keep, p0, \[x0\]
--.*: 85c00008 prfb pstl1keep, p0, \[x0\]
--.*: 85c00008 prfb pstl1keep, p0, \[x0\]
--.*: 85c00008 prfb pstl1keep, p0, \[x0\]
--.*: 85c00009 prfb pstl1strm, p0, \[x0\]
--.*: 85c00009 prfb pstl1strm, p0, \[x0\]
--.*: 85c00009 prfb pstl1strm, p0, \[x0\]
--.*: 85c00009 prfb pstl1strm, p0, \[x0\]
--.*: 85c0000a prfb pstl2keep, p0, \[x0\]
--.*: 85c0000a prfb pstl2keep, p0, \[x0\]
--.*: 85c0000a prfb pstl2keep, p0, \[x0\]
--.*: 85c0000a prfb pstl2keep, p0, \[x0\]
--.*: 85c0000b prfb pstl2strm, p0, \[x0\]
--.*: 85c0000b prfb pstl2strm, p0, \[x0\]
--.*: 85c0000b prfb pstl2strm, p0, \[x0\]
--.*: 85c0000b prfb pstl2strm, p0, \[x0\]
--.*: 85c0000c prfb pstl3keep, p0, \[x0\]
--.*: 85c0000c prfb pstl3keep, p0, \[x0\]
--.*: 85c0000c prfb pstl3keep, p0, \[x0\]
--.*: 85c0000c prfb pstl3keep, p0, \[x0\]
--.*: 85c0000d prfb pstl3strm, p0, \[x0\]
--.*: 85c0000d prfb pstl3strm, p0, \[x0\]
--.*: 85c0000d prfb pstl3strm, p0, \[x0\]
--.*: 85c0000d prfb pstl3strm, p0, \[x0\]
--.*: 85c0000e prfb #14, p0, \[x0\]
--.*: 85c0000e prfb #14, p0, \[x0\]
--.*: 85c0000e prfb #14, p0, \[x0\]
--.*: 85c0000e prfb #14, p0, \[x0\]
--.*: 85c0000f prfb #15, p0, \[x0\]
--.*: 85c0000f prfb #15, p0, \[x0\]
--.*: 85c0000f prfb #15, p0, \[x0\]
--.*: 85c0000f prfb #15, p0, \[x0\]
--.*: 85c00800 prfb pldl1keep, p2, \[x0\]
--.*: 85c00800 prfb pldl1keep, p2, \[x0\]
--.*: 85c00800 prfb pldl1keep, p2, \[x0\]
--.*: 85c00800 prfb pldl1keep, p2, \[x0\]
--.*: 85c01c00 prfb pldl1keep, p7, \[x0\]
--.*: 85c01c00 prfb pldl1keep, p7, \[x0\]
--.*: 85c01c00 prfb pldl1keep, p7, \[x0\]
--.*: 85c01c00 prfb pldl1keep, p7, \[x0\]
--.*: 85c00060 prfb pldl1keep, p0, \[x3\]
--.*: 85c00060 prfb pldl1keep, p0, \[x3\]
--.*: 85c00060 prfb pldl1keep, p0, \[x3\]
--.*: 85c00060 prfb pldl1keep, p0, \[x3\]
--.*: 85c003e0 prfb pldl1keep, p0, \[sp\]
--.*: 85c003e0 prfb pldl1keep, p0, \[sp\]
--.*: 85c003e0 prfb pldl1keep, p0, \[sp\]
--.*: 85c003e0 prfb pldl1keep, p0, \[sp\]
--.*: 85df0000 prfb pldl1keep, p0, \[x0, #31, mul vl\]
--.*: 85df0000 prfb pldl1keep, p0, \[x0, #31, mul vl\]
--.*: 85e00000 prfb pldl1keep, p0, \[x0, #-32, mul vl\]
--.*: 85e00000 prfb pldl1keep, p0, \[x0, #-32, mul vl\]
--.*: 85e10000 prfb pldl1keep, p0, \[x0, #-31, mul vl\]
--.*: 85e10000 prfb pldl1keep, p0, \[x0, #-31, mul vl\]
--.*: 85ff0000 prfb pldl1keep, p0, \[x0, #-1, mul vl\]
--.*: 85ff0000 prfb pldl1keep, p0, \[x0, #-1, mul vl\]
--.*: c400e000 prfb pldl1keep, p0, \[z0\.d\]
--.*: c400e000 prfb pldl1keep, p0, \[z0\.d\]
--.*: c400e000 prfb pldl1keep, p0, \[z0\.d\]
--.*: c400e001 prfb pldl1strm, p0, \[z0\.d\]
--.*: c400e001 prfb pldl1strm, p0, \[z0\.d\]
--.*: c400e001 prfb pldl1strm, p0, \[z0\.d\]
--.*: c400e002 prfb pldl2keep, p0, \[z0\.d\]
--.*: c400e002 prfb pldl2keep, p0, \[z0\.d\]
--.*: c400e002 prfb pldl2keep, p0, \[z0\.d\]
--.*: c400e003 prfb pldl2strm, p0, \[z0\.d\]
--.*: c400e003 prfb pldl2strm, p0, \[z0\.d\]
--.*: c400e003 prfb pldl2strm, p0, \[z0\.d\]
--.*: c400e004 prfb pldl3keep, p0, \[z0\.d\]
--.*: c400e004 prfb pldl3keep, p0, \[z0\.d\]
--.*: c400e004 prfb pldl3keep, p0, \[z0\.d\]
--.*: c400e005 prfb pldl3strm, p0, \[z0\.d\]
--.*: c400e005 prfb pldl3strm, p0, \[z0\.d\]
--.*: c400e005 prfb pldl3strm, p0, \[z0\.d\]
--.*: c400e006 prfb #6, p0, \[z0\.d\]
--.*: c400e006 prfb #6, p0, \[z0\.d\]
--.*: c400e006 prfb #6, p0, \[z0\.d\]
--.*: c400e007 prfb #7, p0, \[z0\.d\]
--.*: c400e007 prfb #7, p0, \[z0\.d\]
--.*: c400e007 prfb #7, p0, \[z0\.d\]
--.*: c400e008 prfb pstl1keep, p0, \[z0\.d\]
--.*: c400e008 prfb pstl1keep, p0, \[z0\.d\]
--.*: c400e008 prfb pstl1keep, p0, \[z0\.d\]
--.*: c400e009 prfb pstl1strm, p0, \[z0\.d\]
--.*: c400e009 prfb pstl1strm, p0, \[z0\.d\]
--.*: c400e009 prfb pstl1strm, p0, \[z0\.d\]
--.*: c400e00a prfb pstl2keep, p0, \[z0\.d\]
--.*: c400e00a prfb pstl2keep, p0, \[z0\.d\]
--.*: c400e00a prfb pstl2keep, p0, \[z0\.d\]
--.*: c400e00b prfb pstl2strm, p0, \[z0\.d\]
--.*: c400e00b prfb pstl2strm, p0, \[z0\.d\]
--.*: c400e00b prfb pstl2strm, p0, \[z0\.d\]
--.*: c400e00c prfb pstl3keep, p0, \[z0\.d\]
--.*: c400e00c prfb pstl3keep, p0, \[z0\.d\]
--.*: c400e00c prfb pstl3keep, p0, \[z0\.d\]
--.*: c400e00d prfb pstl3strm, p0, \[z0\.d\]
--.*: c400e00d prfb pstl3strm, p0, \[z0\.d\]
--.*: c400e00d prfb pstl3strm, p0, \[z0\.d\]
--.*: c400e00e prfb #14, p0, \[z0\.d\]
--.*: c400e00e prfb #14, p0, \[z0\.d\]
--.*: c400e00e prfb #14, p0, \[z0\.d\]
--.*: c400e00f prfb #15, p0, \[z0\.d\]
--.*: c400e00f prfb #15, p0, \[z0\.d\]
--.*: c400e00f prfb #15, p0, \[z0\.d\]
--.*: c400e800 prfb pldl1keep, p2, \[z0\.d\]
--.*: c400e800 prfb pldl1keep, p2, \[z0\.d\]
--.*: c400e800 prfb pldl1keep, p2, \[z0\.d\]
--.*: c400fc00 prfb pldl1keep, p7, \[z0\.d\]
--.*: c400fc00 prfb pldl1keep, p7, \[z0\.d\]
--.*: c400fc00 prfb pldl1keep, p7, \[z0\.d\]
--.*: c400e060 prfb pldl1keep, p0, \[z3\.d\]
--.*: c400e060 prfb pldl1keep, p0, \[z3\.d\]
--.*: c400e060 prfb pldl1keep, p0, \[z3\.d\]
--.*: c400e3e0 prfb pldl1keep, p0, \[z31\.d\]
--.*: c400e3e0 prfb pldl1keep, p0, \[z31\.d\]
--.*: c400e3e0 prfb pldl1keep, p0, \[z31\.d\]
--.*: c40fe000 prfb pldl1keep, p0, \[z0\.d, #15\]
--.*: c40fe000 prfb pldl1keep, p0, \[z0\.d, #15\]
--.*: c410e000 prfb pldl1keep, p0, \[z0\.d, #16\]
--.*: c410e000 prfb pldl1keep, p0, \[z0\.d, #16\]
--.*: c411e000 prfb pldl1keep, p0, \[z0\.d, #17\]
--.*: c411e000 prfb pldl1keep, p0, \[z0\.d, #17\]
--.*: c41fe000 prfb pldl1keep, p0, \[z0\.d, #31\]
--.*: c41fe000 prfb pldl1keep, p0, \[z0\.d, #31\]
--.*: 84206000 prfd pldl1keep, p0, \[x0, z0\.s, uxtw #3\]
--.*: 84206000 prfd pldl1keep, p0, \[x0, z0\.s, uxtw #3\]
--.*: 84206001 prfd pldl1strm, p0, \[x0, z0\.s, uxtw #3\]
--.*: 84206001 prfd pldl1strm, p0, \[x0, z0\.s, uxtw #3\]
--.*: 84206002 prfd pldl2keep, p0, \[x0, z0\.s, uxtw #3\]
--.*: 84206002 prfd pldl2keep, p0, \[x0, z0\.s, uxtw #3\]
--.*: 84206003 prfd pldl2strm, p0, \[x0, z0\.s, uxtw #3\]
--.*: 84206003 prfd pldl2strm, p0, \[x0, z0\.s, uxtw #3\]
--.*: 84206004 prfd pldl3keep, p0, \[x0, z0\.s, uxtw #3\]
--.*: 84206004 prfd pldl3keep, p0, \[x0, z0\.s, uxtw #3\]
--.*: 84206005 prfd pldl3strm, p0, \[x0, z0\.s, uxtw #3\]
--.*: 84206005 prfd pldl3strm, p0, \[x0, z0\.s, uxtw #3\]
--.*: 84206006 prfd #6, p0, \[x0, z0\.s, uxtw #3\]
--.*: 84206006 prfd #6, p0, \[x0, z0\.s, uxtw #3\]
--.*: 84206007 prfd #7, p0, \[x0, z0\.s, uxtw #3\]
--.*: 84206007 prfd #7, p0, \[x0, z0\.s, uxtw #3\]
--.*: 84206008 prfd pstl1keep, p0, \[x0, z0\.s, uxtw #3\]
--.*: 84206008 prfd pstl1keep, p0, \[x0, z0\.s, uxtw #3\]
--.*: 84206009 prfd pstl1strm, p0, \[x0, z0\.s, uxtw #3\]
--.*: 84206009 prfd pstl1strm, p0, \[x0, z0\.s, uxtw #3\]
--.*: 8420600a prfd pstl2keep, p0, \[x0, z0\.s, uxtw #3\]
--.*: 8420600a prfd pstl2keep, p0, \[x0, z0\.s, uxtw #3\]
--.*: 8420600b prfd pstl2strm, p0, \[x0, z0\.s, uxtw #3\]
--.*: 8420600b prfd pstl2strm, p0, \[x0, z0\.s, uxtw #3\]
--.*: 8420600c prfd pstl3keep, p0, \[x0, z0\.s, uxtw #3\]
--.*: 8420600c prfd pstl3keep, p0, \[x0, z0\.s, uxtw #3\]
--.*: 8420600d prfd pstl3strm, p0, \[x0, z0\.s, uxtw #3\]
--.*: 8420600d prfd pstl3strm, p0, \[x0, z0\.s, uxtw #3\]
--.*: 8420600e prfd #14, p0, \[x0, z0\.s, uxtw #3\]
--.*: 8420600e prfd #14, p0, \[x0, z0\.s, uxtw #3\]
--.*: 8420600f prfd #15, p0, \[x0, z0\.s, uxtw #3\]
--.*: 8420600f prfd #15, p0, \[x0, z0\.s, uxtw #3\]
--.*: 84206800 prfd pldl1keep, p2, \[x0, z0\.s, uxtw #3\]
--.*: 84206800 prfd pldl1keep, p2, \[x0, z0\.s, uxtw #3\]
--.*: 84207c00 prfd pldl1keep, p7, \[x0, z0\.s, uxtw #3\]
--.*: 84207c00 prfd pldl1keep, p7, \[x0, z0\.s, uxtw #3\]
--.*: 84206060 prfd pldl1keep, p0, \[x3, z0\.s, uxtw #3\]
--.*: 84206060 prfd pldl1keep, p0, \[x3, z0\.s, uxtw #3\]
--.*: 842063e0 prfd pldl1keep, p0, \[sp, z0\.s, uxtw #3\]
--.*: 842063e0 prfd pldl1keep, p0, \[sp, z0\.s, uxtw #3\]
--.*: 84246000 prfd pldl1keep, p0, \[x0, z4\.s, uxtw #3\]
--.*: 84246000 prfd pldl1keep, p0, \[x0, z4\.s, uxtw #3\]
--.*: 843f6000 prfd pldl1keep, p0, \[x0, z31\.s, uxtw #3\]
--.*: 843f6000 prfd pldl1keep, p0, \[x0, z31\.s, uxtw #3\]
--.*: 84606000 prfd pldl1keep, p0, \[x0, z0\.s, sxtw #3\]
--.*: 84606000 prfd pldl1keep, p0, \[x0, z0\.s, sxtw #3\]
--.*: 84606001 prfd pldl1strm, p0, \[x0, z0\.s, sxtw #3\]
--.*: 84606001 prfd pldl1strm, p0, \[x0, z0\.s, sxtw #3\]
--.*: 84606002 prfd pldl2keep, p0, \[x0, z0\.s, sxtw #3\]
--.*: 84606002 prfd pldl2keep, p0, \[x0, z0\.s, sxtw #3\]
--.*: 84606003 prfd pldl2strm, p0, \[x0, z0\.s, sxtw #3\]
--.*: 84606003 prfd pldl2strm, p0, \[x0, z0\.s, sxtw #3\]
--.*: 84606004 prfd pldl3keep, p0, \[x0, z0\.s, sxtw #3\]
--.*: 84606004 prfd pldl3keep, p0, \[x0, z0\.s, sxtw #3\]
--.*: 84606005 prfd pldl3strm, p0, \[x0, z0\.s, sxtw #3\]
--.*: 84606005 prfd pldl3strm, p0, \[x0, z0\.s, sxtw #3\]
--.*: 84606006 prfd #6, p0, \[x0, z0\.s, sxtw #3\]
--.*: 84606006 prfd #6, p0, \[x0, z0\.s, sxtw #3\]
--.*: 84606007 prfd #7, p0, \[x0, z0\.s, sxtw #3\]
--.*: 84606007 prfd #7, p0, \[x0, z0\.s, sxtw #3\]
--.*: 84606008 prfd pstl1keep, p0, \[x0, z0\.s, sxtw #3\]
--.*: 84606008 prfd pstl1keep, p0, \[x0, z0\.s, sxtw #3\]
--.*: 84606009 prfd pstl1strm, p0, \[x0, z0\.s, sxtw #3\]
--.*: 84606009 prfd pstl1strm, p0, \[x0, z0\.s, sxtw #3\]
--.*: 8460600a prfd pstl2keep, p0, \[x0, z0\.s, sxtw #3\]
--.*: 8460600a prfd pstl2keep, p0, \[x0, z0\.s, sxtw #3\]
--.*: 8460600b prfd pstl2strm, p0, \[x0, z0\.s, sxtw #3\]
--.*: 8460600b prfd pstl2strm, p0, \[x0, z0\.s, sxtw #3\]
--.*: 8460600c prfd pstl3keep, p0, \[x0, z0\.s, sxtw #3\]
--.*: 8460600c prfd pstl3keep, p0, \[x0, z0\.s, sxtw #3\]
--.*: 8460600d prfd pstl3strm, p0, \[x0, z0\.s, sxtw #3\]
--.*: 8460600d prfd pstl3strm, p0, \[x0, z0\.s, sxtw #3\]
--.*: 8460600e prfd #14, p0, \[x0, z0\.s, sxtw #3\]
--.*: 8460600e prfd #14, p0, \[x0, z0\.s, sxtw #3\]
--.*: 8460600f prfd #15, p0, \[x0, z0\.s, sxtw #3\]
--.*: 8460600f prfd #15, p0, \[x0, z0\.s, sxtw #3\]
--.*: 84606800 prfd pldl1keep, p2, \[x0, z0\.s, sxtw #3\]
--.*: 84606800 prfd pldl1keep, p2, \[x0, z0\.s, sxtw #3\]
--.*: 84607c00 prfd pldl1keep, p7, \[x0, z0\.s, sxtw #3\]
--.*: 84607c00 prfd pldl1keep, p7, \[x0, z0\.s, sxtw #3\]
--.*: 84606060 prfd pldl1keep, p0, \[x3, z0\.s, sxtw #3\]
--.*: 84606060 prfd pldl1keep, p0, \[x3, z0\.s, sxtw #3\]
--.*: 846063e0 prfd pldl1keep, p0, \[sp, z0\.s, sxtw #3\]
--.*: 846063e0 prfd pldl1keep, p0, \[sp, z0\.s, sxtw #3\]
--.*: 84646000 prfd pldl1keep, p0, \[x0, z4\.s, sxtw #3\]
--.*: 84646000 prfd pldl1keep, p0, \[x0, z4\.s, sxtw #3\]
--.*: 847f6000 prfd pldl1keep, p0, \[x0, z31\.s, sxtw #3\]
--.*: 847f6000 prfd pldl1keep, p0, \[x0, z31\.s, sxtw #3\]
--.*: 8580c000 prfd pldl1keep, p0, \[x0, x0, lsl #3\]
--.*: 8580c000 prfd pldl1keep, p0, \[x0, x0, lsl #3\]
--.*: 8580c001 prfd pldl1strm, p0, \[x0, x0, lsl #3\]
--.*: 8580c001 prfd pldl1strm, p0, \[x0, x0, lsl #3\]
--.*: 8580c002 prfd pldl2keep, p0, \[x0, x0, lsl #3\]
--.*: 8580c002 prfd pldl2keep, p0, \[x0, x0, lsl #3\]
--.*: 8580c003 prfd pldl2strm, p0, \[x0, x0, lsl #3\]
--.*: 8580c003 prfd pldl2strm, p0, \[x0, x0, lsl #3\]
--.*: 8580c004 prfd pldl3keep, p0, \[x0, x0, lsl #3\]
--.*: 8580c004 prfd pldl3keep, p0, \[x0, x0, lsl #3\]
--.*: 8580c005 prfd pldl3strm, p0, \[x0, x0, lsl #3\]
--.*: 8580c005 prfd pldl3strm, p0, \[x0, x0, lsl #3\]
--.*: 8580c006 prfd #6, p0, \[x0, x0, lsl #3\]
--.*: 8580c006 prfd #6, p0, \[x0, x0, lsl #3\]
--.*: 8580c007 prfd #7, p0, \[x0, x0, lsl #3\]
--.*: 8580c007 prfd #7, p0, \[x0, x0, lsl #3\]
--.*: 8580c008 prfd pstl1keep, p0, \[x0, x0, lsl #3\]
--.*: 8580c008 prfd pstl1keep, p0, \[x0, x0, lsl #3\]
--.*: 8580c009 prfd pstl1strm, p0, \[x0, x0, lsl #3\]
--.*: 8580c009 prfd pstl1strm, p0, \[x0, x0, lsl #3\]
--.*: 8580c00a prfd pstl2keep, p0, \[x0, x0, lsl #3\]
--.*: 8580c00a prfd pstl2keep, p0, \[x0, x0, lsl #3\]
--.*: 8580c00b prfd pstl2strm, p0, \[x0, x0, lsl #3\]
--.*: 8580c00b prfd pstl2strm, p0, \[x0, x0, lsl #3\]
--.*: 8580c00c prfd pstl3keep, p0, \[x0, x0, lsl #3\]
--.*: 8580c00c prfd pstl3keep, p0, \[x0, x0, lsl #3\]
--.*: 8580c00d prfd pstl3strm, p0, \[x0, x0, lsl #3\]
--.*: 8580c00d prfd pstl3strm, p0, \[x0, x0, lsl #3\]
--.*: 8580c00e prfd #14, p0, \[x0, x0, lsl #3\]
--.*: 8580c00e prfd #14, p0, \[x0, x0, lsl #3\]
--.*: 8580c00f prfd #15, p0, \[x0, x0, lsl #3\]
--.*: 8580c00f prfd #15, p0, \[x0, x0, lsl #3\]
--.*: 8580c800 prfd pldl1keep, p2, \[x0, x0, lsl #3\]
--.*: 8580c800 prfd pldl1keep, p2, \[x0, x0, lsl #3\]
--.*: 8580dc00 prfd pldl1keep, p7, \[x0, x0, lsl #3\]
--.*: 8580dc00 prfd pldl1keep, p7, \[x0, x0, lsl #3\]
--.*: 8580c060 prfd pldl1keep, p0, \[x3, x0, lsl #3\]
--.*: 8580c060 prfd pldl1keep, p0, \[x3, x0, lsl #3\]
--.*: 8580c3e0 prfd pldl1keep, p0, \[sp, x0, lsl #3\]
--.*: 8580c3e0 prfd pldl1keep, p0, \[sp, x0, lsl #3\]
--.*: 8584c000 prfd pldl1keep, p0, \[x0, x4, lsl #3\]
--.*: 8584c000 prfd pldl1keep, p0, \[x0, x4, lsl #3\]
--.*: 859ec000 prfd pldl1keep, p0, \[x0, x30, lsl #3\]
--.*: 859ec000 prfd pldl1keep, p0, \[x0, x30, lsl #3\]
--.*: c4206000 prfd pldl1keep, p0, \[x0, z0\.d, uxtw #3\]
--.*: c4206000 prfd pldl1keep, p0, \[x0, z0\.d, uxtw #3\]
--.*: c4206001 prfd pldl1strm, p0, \[x0, z0\.d, uxtw #3\]
--.*: c4206001 prfd pldl1strm, p0, \[x0, z0\.d, uxtw #3\]
--.*: c4206002 prfd pldl2keep, p0, \[x0, z0\.d, uxtw #3\]
--.*: c4206002 prfd pldl2keep, p0, \[x0, z0\.d, uxtw #3\]
--.*: c4206003 prfd pldl2strm, p0, \[x0, z0\.d, uxtw #3\]
--.*: c4206003 prfd pldl2strm, p0, \[x0, z0\.d, uxtw #3\]
--.*: c4206004 prfd pldl3keep, p0, \[x0, z0\.d, uxtw #3\]
--.*: c4206004 prfd pldl3keep, p0, \[x0, z0\.d, uxtw #3\]
--.*: c4206005 prfd pldl3strm, p0, \[x0, z0\.d, uxtw #3\]
--.*: c4206005 prfd pldl3strm, p0, \[x0, z0\.d, uxtw #3\]
--.*: c4206006 prfd #6, p0, \[x0, z0\.d, uxtw #3\]
--.*: c4206006 prfd #6, p0, \[x0, z0\.d, uxtw #3\]
--.*: c4206007 prfd #7, p0, \[x0, z0\.d, uxtw #3\]
--.*: c4206007 prfd #7, p0, \[x0, z0\.d, uxtw #3\]
--.*: c4206008 prfd pstl1keep, p0, \[x0, z0\.d, uxtw #3\]
--.*: c4206008 prfd pstl1keep, p0, \[x0, z0\.d, uxtw #3\]
--.*: c4206009 prfd pstl1strm, p0, \[x0, z0\.d, uxtw #3\]
--.*: c4206009 prfd pstl1strm, p0, \[x0, z0\.d, uxtw #3\]
--.*: c420600a prfd pstl2keep, p0, \[x0, z0\.d, uxtw #3\]
--.*: c420600a prfd pstl2keep, p0, \[x0, z0\.d, uxtw #3\]
--.*: c420600b prfd pstl2strm, p0, \[x0, z0\.d, uxtw #3\]
--.*: c420600b prfd pstl2strm, p0, \[x0, z0\.d, uxtw #3\]
--.*: c420600c prfd pstl3keep, p0, \[x0, z0\.d, uxtw #3\]
--.*: c420600c prfd pstl3keep, p0, \[x0, z0\.d, uxtw #3\]
--.*: c420600d prfd pstl3strm, p0, \[x0, z0\.d, uxtw #3\]
--.*: c420600d prfd pstl3strm, p0, \[x0, z0\.d, uxtw #3\]
--.*: c420600e prfd #14, p0, \[x0, z0\.d, uxtw #3\]
--.*: c420600e prfd #14, p0, \[x0, z0\.d, uxtw #3\]
--.*: c420600f prfd #15, p0, \[x0, z0\.d, uxtw #3\]
--.*: c420600f prfd #15, p0, \[x0, z0\.d, uxtw #3\]
--.*: c4206800 prfd pldl1keep, p2, \[x0, z0\.d, uxtw #3\]
--.*: c4206800 prfd pldl1keep, p2, \[x0, z0\.d, uxtw #3\]
--.*: c4207c00 prfd pldl1keep, p7, \[x0, z0\.d, uxtw #3\]
--.*: c4207c00 prfd pldl1keep, p7, \[x0, z0\.d, uxtw #3\]
--.*: c4206060 prfd pldl1keep, p0, \[x3, z0\.d, uxtw #3\]
--.*: c4206060 prfd pldl1keep, p0, \[x3, z0\.d, uxtw #3\]
--.*: c42063e0 prfd pldl1keep, p0, \[sp, z0\.d, uxtw #3\]
--.*: c42063e0 prfd pldl1keep, p0, \[sp, z0\.d, uxtw #3\]
--.*: c4246000 prfd pldl1keep, p0, \[x0, z4\.d, uxtw #3\]
--.*: c4246000 prfd pldl1keep, p0, \[x0, z4\.d, uxtw #3\]
--.*: c43f6000 prfd pldl1keep, p0, \[x0, z31\.d, uxtw #3\]
--.*: c43f6000 prfd pldl1keep, p0, \[x0, z31\.d, uxtw #3\]
--.*: c4606000 prfd pldl1keep, p0, \[x0, z0\.d, sxtw #3\]
--.*: c4606000 prfd pldl1keep, p0, \[x0, z0\.d, sxtw #3\]
--.*: c4606001 prfd pldl1strm, p0, \[x0, z0\.d, sxtw #3\]
--.*: c4606001 prfd pldl1strm, p0, \[x0, z0\.d, sxtw #3\]
--.*: c4606002 prfd pldl2keep, p0, \[x0, z0\.d, sxtw #3\]
--.*: c4606002 prfd pldl2keep, p0, \[x0, z0\.d, sxtw #3\]
--.*: c4606003 prfd pldl2strm, p0, \[x0, z0\.d, sxtw #3\]
--.*: c4606003 prfd pldl2strm, p0, \[x0, z0\.d, sxtw #3\]
--.*: c4606004 prfd pldl3keep, p0, \[x0, z0\.d, sxtw #3\]
--.*: c4606004 prfd pldl3keep, p0, \[x0, z0\.d, sxtw #3\]
--.*: c4606005 prfd pldl3strm, p0, \[x0, z0\.d, sxtw #3\]
--.*: c4606005 prfd pldl3strm, p0, \[x0, z0\.d, sxtw #3\]
--.*: c4606006 prfd #6, p0, \[x0, z0\.d, sxtw #3\]
--.*: c4606006 prfd #6, p0, \[x0, z0\.d, sxtw #3\]
--.*: c4606007 prfd #7, p0, \[x0, z0\.d, sxtw #3\]
--.*: c4606007 prfd #7, p0, \[x0, z0\.d, sxtw #3\]
--.*: c4606008 prfd pstl1keep, p0, \[x0, z0\.d, sxtw #3\]
--.*: c4606008 prfd pstl1keep, p0, \[x0, z0\.d, sxtw #3\]
--.*: c4606009 prfd pstl1strm, p0, \[x0, z0\.d, sxtw #3\]
--.*: c4606009 prfd pstl1strm, p0, \[x0, z0\.d, sxtw #3\]
--.*: c460600a prfd pstl2keep, p0, \[x0, z0\.d, sxtw #3\]
--.*: c460600a prfd pstl2keep, p0, \[x0, z0\.d, sxtw #3\]
--.*: c460600b prfd pstl2strm, p0, \[x0, z0\.d, sxtw #3\]
--.*: c460600b prfd pstl2strm, p0, \[x0, z0\.d, sxtw #3\]
--.*: c460600c prfd pstl3keep, p0, \[x0, z0\.d, sxtw #3\]
--.*: c460600c prfd pstl3keep, p0, \[x0, z0\.d, sxtw #3\]
--.*: c460600d prfd pstl3strm, p0, \[x0, z0\.d, sxtw #3\]
--.*: c460600d prfd pstl3strm, p0, \[x0, z0\.d, sxtw #3\]
--.*: c460600e prfd #14, p0, \[x0, z0\.d, sxtw #3\]
--.*: c460600e prfd #14, p0, \[x0, z0\.d, sxtw #3\]
--.*: c460600f prfd #15, p0, \[x0, z0\.d, sxtw #3\]
--.*: c460600f prfd #15, p0, \[x0, z0\.d, sxtw #3\]
--.*: c4606800 prfd pldl1keep, p2, \[x0, z0\.d, sxtw #3\]
--.*: c4606800 prfd pldl1keep, p2, \[x0, z0\.d, sxtw #3\]
--.*: c4607c00 prfd pldl1keep, p7, \[x0, z0\.d, sxtw #3\]
--.*: c4607c00 prfd pldl1keep, p7, \[x0, z0\.d, sxtw #3\]
--.*: c4606060 prfd pldl1keep, p0, \[x3, z0\.d, sxtw #3\]
--.*: c4606060 prfd pldl1keep, p0, \[x3, z0\.d, sxtw #3\]
--.*: c46063e0 prfd pldl1keep, p0, \[sp, z0\.d, sxtw #3\]
--.*: c46063e0 prfd pldl1keep, p0, \[sp, z0\.d, sxtw #3\]
--.*: c4646000 prfd pldl1keep, p0, \[x0, z4\.d, sxtw #3\]
--.*: c4646000 prfd pldl1keep, p0, \[x0, z4\.d, sxtw #3\]
--.*: c47f6000 prfd pldl1keep, p0, \[x0, z31\.d, sxtw #3\]
--.*: c47f6000 prfd pldl1keep, p0, \[x0, z31\.d, sxtw #3\]
--.*: c460e000 prfd pldl1keep, p0, \[x0, z0\.d, lsl #3\]
--.*: c460e000 prfd pldl1keep, p0, \[x0, z0\.d, lsl #3\]
--.*: c460e001 prfd pldl1strm, p0, \[x0, z0\.d, lsl #3\]
--.*: c460e001 prfd pldl1strm, p0, \[x0, z0\.d, lsl #3\]
--.*: c460e002 prfd pldl2keep, p0, \[x0, z0\.d, lsl #3\]
--.*: c460e002 prfd pldl2keep, p0, \[x0, z0\.d, lsl #3\]
--.*: c460e003 prfd pldl2strm, p0, \[x0, z0\.d, lsl #3\]
--.*: c460e003 prfd pldl2strm, p0, \[x0, z0\.d, lsl #3\]
--.*: c460e004 prfd pldl3keep, p0, \[x0, z0\.d, lsl #3\]
--.*: c460e004 prfd pldl3keep, p0, \[x0, z0\.d, lsl #3\]
--.*: c460e005 prfd pldl3strm, p0, \[x0, z0\.d, lsl #3\]
--.*: c460e005 prfd pldl3strm, p0, \[x0, z0\.d, lsl #3\]
--.*: c460e006 prfd #6, p0, \[x0, z0\.d, lsl #3\]
--.*: c460e006 prfd #6, p0, \[x0, z0\.d, lsl #3\]
--.*: c460e007 prfd #7, p0, \[x0, z0\.d, lsl #3\]
--.*: c460e007 prfd #7, p0, \[x0, z0\.d, lsl #3\]
--.*: c460e008 prfd pstl1keep, p0, \[x0, z0\.d, lsl #3\]
--.*: c460e008 prfd pstl1keep, p0, \[x0, z0\.d, lsl #3\]
--.*: c460e009 prfd pstl1strm, p0, \[x0, z0\.d, lsl #3\]
--.*: c460e009 prfd pstl1strm, p0, \[x0, z0\.d, lsl #3\]
--.*: c460e00a prfd pstl2keep, p0, \[x0, z0\.d, lsl #3\]
--.*: c460e00a prfd pstl2keep, p0, \[x0, z0\.d, lsl #3\]
--.*: c460e00b prfd pstl2strm, p0, \[x0, z0\.d, lsl #3\]
--.*: c460e00b prfd pstl2strm, p0, \[x0, z0\.d, lsl #3\]
--.*: c460e00c prfd pstl3keep, p0, \[x0, z0\.d, lsl #3\]
--.*: c460e00c prfd pstl3keep, p0, \[x0, z0\.d, lsl #3\]
--.*: c460e00d prfd pstl3strm, p0, \[x0, z0\.d, lsl #3\]
--.*: c460e00d prfd pstl3strm, p0, \[x0, z0\.d, lsl #3\]
--.*: c460e00e prfd #14, p0, \[x0, z0\.d, lsl #3\]
--.*: c460e00e prfd #14, p0, \[x0, z0\.d, lsl #3\]
--.*: c460e00f prfd #15, p0, \[x0, z0\.d, lsl #3\]
--.*: c460e00f prfd #15, p0, \[x0, z0\.d, lsl #3\]
--.*: c460e800 prfd pldl1keep, p2, \[x0, z0\.d, lsl #3\]
--.*: c460e800 prfd pldl1keep, p2, \[x0, z0\.d, lsl #3\]
--.*: c460fc00 prfd pldl1keep, p7, \[x0, z0\.d, lsl #3\]
--.*: c460fc00 prfd pldl1keep, p7, \[x0, z0\.d, lsl #3\]
--.*: c460e060 prfd pldl1keep, p0, \[x3, z0\.d, lsl #3\]
--.*: c460e060 prfd pldl1keep, p0, \[x3, z0\.d, lsl #3\]
--.*: c460e3e0 prfd pldl1keep, p0, \[sp, z0\.d, lsl #3\]
--.*: c460e3e0 prfd pldl1keep, p0, \[sp, z0\.d, lsl #3\]
--.*: c464e000 prfd pldl1keep, p0, \[x0, z4\.d, lsl #3\]
--.*: c464e000 prfd pldl1keep, p0, \[x0, z4\.d, lsl #3\]
--.*: c47fe000 prfd pldl1keep, p0, \[x0, z31\.d, lsl #3\]
--.*: c47fe000 prfd pldl1keep, p0, \[x0, z31\.d, lsl #3\]
--.*: 8580e000 prfd pldl1keep, p0, \[z0\.s\]
--.*: 8580e000 prfd pldl1keep, p0, \[z0\.s\]
--.*: 8580e000 prfd pldl1keep, p0, \[z0\.s\]
--.*: 8580e001 prfd pldl1strm, p0, \[z0\.s\]
--.*: 8580e001 prfd pldl1strm, p0, \[z0\.s\]
--.*: 8580e001 prfd pldl1strm, p0, \[z0\.s\]
--.*: 8580e002 prfd pldl2keep, p0, \[z0\.s\]
--.*: 8580e002 prfd pldl2keep, p0, \[z0\.s\]
--.*: 8580e002 prfd pldl2keep, p0, \[z0\.s\]
--.*: 8580e003 prfd pldl2strm, p0, \[z0\.s\]
--.*: 8580e003 prfd pldl2strm, p0, \[z0\.s\]
--.*: 8580e003 prfd pldl2strm, p0, \[z0\.s\]
--.*: 8580e004 prfd pldl3keep, p0, \[z0\.s\]
--.*: 8580e004 prfd pldl3keep, p0, \[z0\.s\]
--.*: 8580e004 prfd pldl3keep, p0, \[z0\.s\]
--.*: 8580e005 prfd pldl3strm, p0, \[z0\.s\]
--.*: 8580e005 prfd pldl3strm, p0, \[z0\.s\]
--.*: 8580e005 prfd pldl3strm, p0, \[z0\.s\]
--.*: 8580e006 prfd #6, p0, \[z0\.s\]
--.*: 8580e006 prfd #6, p0, \[z0\.s\]
--.*: 8580e006 prfd #6, p0, \[z0\.s\]
--.*: 8580e007 prfd #7, p0, \[z0\.s\]
--.*: 8580e007 prfd #7, p0, \[z0\.s\]
--.*: 8580e007 prfd #7, p0, \[z0\.s\]
--.*: 8580e008 prfd pstl1keep, p0, \[z0\.s\]
--.*: 8580e008 prfd pstl1keep, p0, \[z0\.s\]
--.*: 8580e008 prfd pstl1keep, p0, \[z0\.s\]
--.*: 8580e009 prfd pstl1strm, p0, \[z0\.s\]
--.*: 8580e009 prfd pstl1strm, p0, \[z0\.s\]
--.*: 8580e009 prfd pstl1strm, p0, \[z0\.s\]
--.*: 8580e00a prfd pstl2keep, p0, \[z0\.s\]
--.*: 8580e00a prfd pstl2keep, p0, \[z0\.s\]
--.*: 8580e00a prfd pstl2keep, p0, \[z0\.s\]
--.*: 8580e00b prfd pstl2strm, p0, \[z0\.s\]
--.*: 8580e00b prfd pstl2strm, p0, \[z0\.s\]
--.*: 8580e00b prfd pstl2strm, p0, \[z0\.s\]
--.*: 8580e00c prfd pstl3keep, p0, \[z0\.s\]
--.*: 8580e00c prfd pstl3keep, p0, \[z0\.s\]
--.*: 8580e00c prfd pstl3keep, p0, \[z0\.s\]
--.*: 8580e00d prfd pstl3strm, p0, \[z0\.s\]
--.*: 8580e00d prfd pstl3strm, p0, \[z0\.s\]
--.*: 8580e00d prfd pstl3strm, p0, \[z0\.s\]
--.*: 8580e00e prfd #14, p0, \[z0\.s\]
--.*: 8580e00e prfd #14, p0, \[z0\.s\]
--.*: 8580e00e prfd #14, p0, \[z0\.s\]
--.*: 8580e00f prfd #15, p0, \[z0\.s\]
--.*: 8580e00f prfd #15, p0, \[z0\.s\]
--.*: 8580e00f prfd #15, p0, \[z0\.s\]
--.*: 8580e800 prfd pldl1keep, p2, \[z0\.s\]
--.*: 8580e800 prfd pldl1keep, p2, \[z0\.s\]
--.*: 8580e800 prfd pldl1keep, p2, \[z0\.s\]
--.*: 8580fc00 prfd pldl1keep, p7, \[z0\.s\]
--.*: 8580fc00 prfd pldl1keep, p7, \[z0\.s\]
--.*: 8580fc00 prfd pldl1keep, p7, \[z0\.s\]
--.*: 8580e060 prfd pldl1keep, p0, \[z3\.s\]
--.*: 8580e060 prfd pldl1keep, p0, \[z3\.s\]
--.*: 8580e060 prfd pldl1keep, p0, \[z3\.s\]
--.*: 8580e3e0 prfd pldl1keep, p0, \[z31\.s\]
--.*: 8580e3e0 prfd pldl1keep, p0, \[z31\.s\]
--.*: 8580e3e0 prfd pldl1keep, p0, \[z31\.s\]
--.*: 858fe000 prfd pldl1keep, p0, \[z0\.s, #120\]
--.*: 858fe000 prfd pldl1keep, p0, \[z0\.s, #120\]
--.*: 8590e000 prfd pldl1keep, p0, \[z0\.s, #128\]
--.*: 8590e000 prfd pldl1keep, p0, \[z0\.s, #128\]
--.*: 8591e000 prfd pldl1keep, p0, \[z0\.s, #136\]
--.*: 8591e000 prfd pldl1keep, p0, \[z0\.s, #136\]
--.*: 859fe000 prfd pldl1keep, p0, \[z0\.s, #248\]
--.*: 859fe000 prfd pldl1keep, p0, \[z0\.s, #248\]
--.*: 85c06000 prfd pldl1keep, p0, \[x0\]
--.*: 85c06000 prfd pldl1keep, p0, \[x0\]
--.*: 85c06000 prfd pldl1keep, p0, \[x0\]
--.*: 85c06000 prfd pldl1keep, p0, \[x0\]
--.*: 85c06001 prfd pldl1strm, p0, \[x0\]
--.*: 85c06001 prfd pldl1strm, p0, \[x0\]
--.*: 85c06001 prfd pldl1strm, p0, \[x0\]
--.*: 85c06001 prfd pldl1strm, p0, \[x0\]
--.*: 85c06002 prfd pldl2keep, p0, \[x0\]
--.*: 85c06002 prfd pldl2keep, p0, \[x0\]
--.*: 85c06002 prfd pldl2keep, p0, \[x0\]
--.*: 85c06002 prfd pldl2keep, p0, \[x0\]
--.*: 85c06003 prfd pldl2strm, p0, \[x0\]
--.*: 85c06003 prfd pldl2strm, p0, \[x0\]
--.*: 85c06003 prfd pldl2strm, p0, \[x0\]
--.*: 85c06003 prfd pldl2strm, p0, \[x0\]
--.*: 85c06004 prfd pldl3keep, p0, \[x0\]
--.*: 85c06004 prfd pldl3keep, p0, \[x0\]
--.*: 85c06004 prfd pldl3keep, p0, \[x0\]
--.*: 85c06004 prfd pldl3keep, p0, \[x0\]
--.*: 85c06005 prfd pldl3strm, p0, \[x0\]
--.*: 85c06005 prfd pldl3strm, p0, \[x0\]
--.*: 85c06005 prfd pldl3strm, p0, \[x0\]
--.*: 85c06005 prfd pldl3strm, p0, \[x0\]
--.*: 85c06006 prfd #6, p0, \[x0\]
--.*: 85c06006 prfd #6, p0, \[x0\]
--.*: 85c06006 prfd #6, p0, \[x0\]
--.*: 85c06006 prfd #6, p0, \[x0\]
--.*: 85c06007 prfd #7, p0, \[x0\]
--.*: 85c06007 prfd #7, p0, \[x0\]
--.*: 85c06007 prfd #7, p0, \[x0\]
--.*: 85c06007 prfd #7, p0, \[x0\]
--.*: 85c06008 prfd pstl1keep, p0, \[x0\]
--.*: 85c06008 prfd pstl1keep, p0, \[x0\]
--.*: 85c06008 prfd pstl1keep, p0, \[x0\]
--.*: 85c06008 prfd pstl1keep, p0, \[x0\]
--.*: 85c06009 prfd pstl1strm, p0, \[x0\]
--.*: 85c06009 prfd pstl1strm, p0, \[x0\]
--.*: 85c06009 prfd pstl1strm, p0, \[x0\]
--.*: 85c06009 prfd pstl1strm, p0, \[x0\]
--.*: 85c0600a prfd pstl2keep, p0, \[x0\]
--.*: 85c0600a prfd pstl2keep, p0, \[x0\]
--.*: 85c0600a prfd pstl2keep, p0, \[x0\]
--.*: 85c0600a prfd pstl2keep, p0, \[x0\]
--.*: 85c0600b prfd pstl2strm, p0, \[x0\]
--.*: 85c0600b prfd pstl2strm, p0, \[x0\]
--.*: 85c0600b prfd pstl2strm, p0, \[x0\]
--.*: 85c0600b prfd pstl2strm, p0, \[x0\]
--.*: 85c0600c prfd pstl3keep, p0, \[x0\]
--.*: 85c0600c prfd pstl3keep, p0, \[x0\]
--.*: 85c0600c prfd pstl3keep, p0, \[x0\]
--.*: 85c0600c prfd pstl3keep, p0, \[x0\]
--.*: 85c0600d prfd pstl3strm, p0, \[x0\]
--.*: 85c0600d prfd pstl3strm, p0, \[x0\]
--.*: 85c0600d prfd pstl3strm, p0, \[x0\]
--.*: 85c0600d prfd pstl3strm, p0, \[x0\]
--.*: 85c0600e prfd #14, p0, \[x0\]
--.*: 85c0600e prfd #14, p0, \[x0\]
--.*: 85c0600e prfd #14, p0, \[x0\]
--.*: 85c0600e prfd #14, p0, \[x0\]
--.*: 85c0600f prfd #15, p0, \[x0\]
--.*: 85c0600f prfd #15, p0, \[x0\]
--.*: 85c0600f prfd #15, p0, \[x0\]
--.*: 85c0600f prfd #15, p0, \[x0\]
--.*: 85c06800 prfd pldl1keep, p2, \[x0\]
--.*: 85c06800 prfd pldl1keep, p2, \[x0\]
--.*: 85c06800 prfd pldl1keep, p2, \[x0\]
--.*: 85c06800 prfd pldl1keep, p2, \[x0\]
--.*: 85c07c00 prfd pldl1keep, p7, \[x0\]
--.*: 85c07c00 prfd pldl1keep, p7, \[x0\]
--.*: 85c07c00 prfd pldl1keep, p7, \[x0\]
--.*: 85c07c00 prfd pldl1keep, p7, \[x0\]
--.*: 85c06060 prfd pldl1keep, p0, \[x3\]
--.*: 85c06060 prfd pldl1keep, p0, \[x3\]
--.*: 85c06060 prfd pldl1keep, p0, \[x3\]
--.*: 85c06060 prfd pldl1keep, p0, \[x3\]
--.*: 85c063e0 prfd pldl1keep, p0, \[sp\]
--.*: 85c063e0 prfd pldl1keep, p0, \[sp\]
--.*: 85c063e0 prfd pldl1keep, p0, \[sp\]
--.*: 85c063e0 prfd pldl1keep, p0, \[sp\]
--.*: 85df6000 prfd pldl1keep, p0, \[x0, #31, mul vl\]
--.*: 85df6000 prfd pldl1keep, p0, \[x0, #31, mul vl\]
--.*: 85e06000 prfd pldl1keep, p0, \[x0, #-32, mul vl\]
--.*: 85e06000 prfd pldl1keep, p0, \[x0, #-32, mul vl\]
--.*: 85e16000 prfd pldl1keep, p0, \[x0, #-31, mul vl\]
--.*: 85e16000 prfd pldl1keep, p0, \[x0, #-31, mul vl\]
--.*: 85ff6000 prfd pldl1keep, p0, \[x0, #-1, mul vl\]
--.*: 85ff6000 prfd pldl1keep, p0, \[x0, #-1, mul vl\]
--.*: c580e000 prfd pldl1keep, p0, \[z0\.d\]
--.*: c580e000 prfd pldl1keep, p0, \[z0\.d\]
--.*: c580e000 prfd pldl1keep, p0, \[z0\.d\]
--.*: c580e001 prfd pldl1strm, p0, \[z0\.d\]
--.*: c580e001 prfd pldl1strm, p0, \[z0\.d\]
--.*: c580e001 prfd pldl1strm, p0, \[z0\.d\]
--.*: c580e002 prfd pldl2keep, p0, \[z0\.d\]
--.*: c580e002 prfd pldl2keep, p0, \[z0\.d\]
--.*: c580e002 prfd pldl2keep, p0, \[z0\.d\]
--.*: c580e003 prfd pldl2strm, p0, \[z0\.d\]
--.*: c580e003 prfd pldl2strm, p0, \[z0\.d\]
--.*: c580e003 prfd pldl2strm, p0, \[z0\.d\]
--.*: c580e004 prfd pldl3keep, p0, \[z0\.d\]
--.*: c580e004 prfd pldl3keep, p0, \[z0\.d\]
--.*: c580e004 prfd pldl3keep, p0, \[z0\.d\]
--.*: c580e005 prfd pldl3strm, p0, \[z0\.d\]
--.*: c580e005 prfd pldl3strm, p0, \[z0\.d\]
--.*: c580e005 prfd pldl3strm, p0, \[z0\.d\]
--.*: c580e006 prfd #6, p0, \[z0\.d\]
--.*: c580e006 prfd #6, p0, \[z0\.d\]
--.*: c580e006 prfd #6, p0, \[z0\.d\]
--.*: c580e007 prfd #7, p0, \[z0\.d\]
--.*: c580e007 prfd #7, p0, \[z0\.d\]
--.*: c580e007 prfd #7, p0, \[z0\.d\]
--.*: c580e008 prfd pstl1keep, p0, \[z0\.d\]
--.*: c580e008 prfd pstl1keep, p0, \[z0\.d\]
--.*: c580e008 prfd pstl1keep, p0, \[z0\.d\]
--.*: c580e009 prfd pstl1strm, p0, \[z0\.d\]
--.*: c580e009 prfd pstl1strm, p0, \[z0\.d\]
--.*: c580e009 prfd pstl1strm, p0, \[z0\.d\]
--.*: c580e00a prfd pstl2keep, p0, \[z0\.d\]
--.*: c580e00a prfd pstl2keep, p0, \[z0\.d\]
--.*: c580e00a prfd pstl2keep, p0, \[z0\.d\]
--.*: c580e00b prfd pstl2strm, p0, \[z0\.d\]
--.*: c580e00b prfd pstl2strm, p0, \[z0\.d\]
--.*: c580e00b prfd pstl2strm, p0, \[z0\.d\]
--.*: c580e00c prfd pstl3keep, p0, \[z0\.d\]
--.*: c580e00c prfd pstl3keep, p0, \[z0\.d\]
--.*: c580e00c prfd pstl3keep, p0, \[z0\.d\]
--.*: c580e00d prfd pstl3strm, p0, \[z0\.d\]
--.*: c580e00d prfd pstl3strm, p0, \[z0\.d\]
--.*: c580e00d prfd pstl3strm, p0, \[z0\.d\]
--.*: c580e00e prfd #14, p0, \[z0\.d\]
--.*: c580e00e prfd #14, p0, \[z0\.d\]
--.*: c580e00e prfd #14, p0, \[z0\.d\]
--.*: c580e00f prfd #15, p0, \[z0\.d\]
--.*: c580e00f prfd #15, p0, \[z0\.d\]
--.*: c580e00f prfd #15, p0, \[z0\.d\]
--.*: c580e800 prfd pldl1keep, p2, \[z0\.d\]
--.*: c580e800 prfd pldl1keep, p2, \[z0\.d\]
--.*: c580e800 prfd pldl1keep, p2, \[z0\.d\]
--.*: c580fc00 prfd pldl1keep, p7, \[z0\.d\]
--.*: c580fc00 prfd pldl1keep, p7, \[z0\.d\]
--.*: c580fc00 prfd pldl1keep, p7, \[z0\.d\]
--.*: c580e060 prfd pldl1keep, p0, \[z3\.d\]
--.*: c580e060 prfd pldl1keep, p0, \[z3\.d\]
--.*: c580e060 prfd pldl1keep, p0, \[z3\.d\]
--.*: c580e3e0 prfd pldl1keep, p0, \[z31\.d\]
--.*: c580e3e0 prfd pldl1keep, p0, \[z31\.d\]
--.*: c580e3e0 prfd pldl1keep, p0, \[z31\.d\]
--.*: c58fe000 prfd pldl1keep, p0, \[z0\.d, #120\]
--.*: c58fe000 prfd pldl1keep, p0, \[z0\.d, #120\]
--.*: c590e000 prfd pldl1keep, p0, \[z0\.d, #128\]
--.*: c590e000 prfd pldl1keep, p0, \[z0\.d, #128\]
--.*: c591e000 prfd pldl1keep, p0, \[z0\.d, #136\]
--.*: c591e000 prfd pldl1keep, p0, \[z0\.d, #136\]
--.*: c59fe000 prfd pldl1keep, p0, \[z0\.d, #248\]
--.*: c59fe000 prfd pldl1keep, p0, \[z0\.d, #248\]
--.*: 84202000 prfh pldl1keep, p0, \[x0, z0\.s, uxtw #1\]
--.*: 84202000 prfh pldl1keep, p0, \[x0, z0\.s, uxtw #1\]
--.*: 84202001 prfh pldl1strm, p0, \[x0, z0\.s, uxtw #1\]
--.*: 84202001 prfh pldl1strm, p0, \[x0, z0\.s, uxtw #1\]
--.*: 84202002 prfh pldl2keep, p0, \[x0, z0\.s, uxtw #1\]
--.*: 84202002 prfh pldl2keep, p0, \[x0, z0\.s, uxtw #1\]
--.*: 84202003 prfh pldl2strm, p0, \[x0, z0\.s, uxtw #1\]
--.*: 84202003 prfh pldl2strm, p0, \[x0, z0\.s, uxtw #1\]
--.*: 84202004 prfh pldl3keep, p0, \[x0, z0\.s, uxtw #1\]
--.*: 84202004 prfh pldl3keep, p0, \[x0, z0\.s, uxtw #1\]
--.*: 84202005 prfh pldl3strm, p0, \[x0, z0\.s, uxtw #1\]
--.*: 84202005 prfh pldl3strm, p0, \[x0, z0\.s, uxtw #1\]
--.*: 84202006 prfh #6, p0, \[x0, z0\.s, uxtw #1\]
--.*: 84202006 prfh #6, p0, \[x0, z0\.s, uxtw #1\]
--.*: 84202007 prfh #7, p0, \[x0, z0\.s, uxtw #1\]
--.*: 84202007 prfh #7, p0, \[x0, z0\.s, uxtw #1\]
--.*: 84202008 prfh pstl1keep, p0, \[x0, z0\.s, uxtw #1\]
--.*: 84202008 prfh pstl1keep, p0, \[x0, z0\.s, uxtw #1\]
--.*: 84202009 prfh pstl1strm, p0, \[x0, z0\.s, uxtw #1\]
--.*: 84202009 prfh pstl1strm, p0, \[x0, z0\.s, uxtw #1\]
--.*: 8420200a prfh pstl2keep, p0, \[x0, z0\.s, uxtw #1\]
--.*: 8420200a prfh pstl2keep, p0, \[x0, z0\.s, uxtw #1\]
--.*: 8420200b prfh pstl2strm, p0, \[x0, z0\.s, uxtw #1\]
--.*: 8420200b prfh pstl2strm, p0, \[x0, z0\.s, uxtw #1\]
--.*: 8420200c prfh pstl3keep, p0, \[x0, z0\.s, uxtw #1\]
--.*: 8420200c prfh pstl3keep, p0, \[x0, z0\.s, uxtw #1\]
--.*: 8420200d prfh pstl3strm, p0, \[x0, z0\.s, uxtw #1\]
--.*: 8420200d prfh pstl3strm, p0, \[x0, z0\.s, uxtw #1\]
--.*: 8420200e prfh #14, p0, \[x0, z0\.s, uxtw #1\]
--.*: 8420200e prfh #14, p0, \[x0, z0\.s, uxtw #1\]
--.*: 8420200f prfh #15, p0, \[x0, z0\.s, uxtw #1\]
--.*: 8420200f prfh #15, p0, \[x0, z0\.s, uxtw #1\]
--.*: 84202800 prfh pldl1keep, p2, \[x0, z0\.s, uxtw #1\]
--.*: 84202800 prfh pldl1keep, p2, \[x0, z0\.s, uxtw #1\]
--.*: 84203c00 prfh pldl1keep, p7, \[x0, z0\.s, uxtw #1\]
--.*: 84203c00 prfh pldl1keep, p7, \[x0, z0\.s, uxtw #1\]
--.*: 84202060 prfh pldl1keep, p0, \[x3, z0\.s, uxtw #1\]
--.*: 84202060 prfh pldl1keep, p0, \[x3, z0\.s, uxtw #1\]
--.*: 842023e0 prfh pldl1keep, p0, \[sp, z0\.s, uxtw #1\]
--.*: 842023e0 prfh pldl1keep, p0, \[sp, z0\.s, uxtw #1\]
--.*: 84242000 prfh pldl1keep, p0, \[x0, z4\.s, uxtw #1\]
--.*: 84242000 prfh pldl1keep, p0, \[x0, z4\.s, uxtw #1\]
--.*: 843f2000 prfh pldl1keep, p0, \[x0, z31\.s, uxtw #1\]
--.*: 843f2000 prfh pldl1keep, p0, \[x0, z31\.s, uxtw #1\]
--.*: 84602000 prfh pldl1keep, p0, \[x0, z0\.s, sxtw #1\]
--.*: 84602000 prfh pldl1keep, p0, \[x0, z0\.s, sxtw #1\]
--.*: 84602001 prfh pldl1strm, p0, \[x0, z0\.s, sxtw #1\]
--.*: 84602001 prfh pldl1strm, p0, \[x0, z0\.s, sxtw #1\]
--.*: 84602002 prfh pldl2keep, p0, \[x0, z0\.s, sxtw #1\]
--.*: 84602002 prfh pldl2keep, p0, \[x0, z0\.s, sxtw #1\]
--.*: 84602003 prfh pldl2strm, p0, \[x0, z0\.s, sxtw #1\]
--.*: 84602003 prfh pldl2strm, p0, \[x0, z0\.s, sxtw #1\]
--.*: 84602004 prfh pldl3keep, p0, \[x0, z0\.s, sxtw #1\]
--.*: 84602004 prfh pldl3keep, p0, \[x0, z0\.s, sxtw #1\]
--.*: 84602005 prfh pldl3strm, p0, \[x0, z0\.s, sxtw #1\]
--.*: 84602005 prfh pldl3strm, p0, \[x0, z0\.s, sxtw #1\]
--.*: 84602006 prfh #6, p0, \[x0, z0\.s, sxtw #1\]
--.*: 84602006 prfh #6, p0, \[x0, z0\.s, sxtw #1\]
--.*: 84602007 prfh #7, p0, \[x0, z0\.s, sxtw #1\]
--.*: 84602007 prfh #7, p0, \[x0, z0\.s, sxtw #1\]
--.*: 84602008 prfh pstl1keep, p0, \[x0, z0\.s, sxtw #1\]
--.*: 84602008 prfh pstl1keep, p0, \[x0, z0\.s, sxtw #1\]
--.*: 84602009 prfh pstl1strm, p0, \[x0, z0\.s, sxtw #1\]
--.*: 84602009 prfh pstl1strm, p0, \[x0, z0\.s, sxtw #1\]
--.*: 8460200a prfh pstl2keep, p0, \[x0, z0\.s, sxtw #1\]
--.*: 8460200a prfh pstl2keep, p0, \[x0, z0\.s, sxtw #1\]
--.*: 8460200b prfh pstl2strm, p0, \[x0, z0\.s, sxtw #1\]
--.*: 8460200b prfh pstl2strm, p0, \[x0, z0\.s, sxtw #1\]
--.*: 8460200c prfh pstl3keep, p0, \[x0, z0\.s, sxtw #1\]
--.*: 8460200c prfh pstl3keep, p0, \[x0, z0\.s, sxtw #1\]
--.*: 8460200d prfh pstl3strm, p0, \[x0, z0\.s, sxtw #1\]
--.*: 8460200d prfh pstl3strm, p0, \[x0, z0\.s, sxtw #1\]
--.*: 8460200e prfh #14, p0, \[x0, z0\.s, sxtw #1\]
--.*: 8460200e prfh #14, p0, \[x0, z0\.s, sxtw #1\]
--.*: 8460200f prfh #15, p0, \[x0, z0\.s, sxtw #1\]
--.*: 8460200f prfh #15, p0, \[x0, z0\.s, sxtw #1\]
--.*: 84602800 prfh pldl1keep, p2, \[x0, z0\.s, sxtw #1\]
--.*: 84602800 prfh pldl1keep, p2, \[x0, z0\.s, sxtw #1\]
--.*: 84603c00 prfh pldl1keep, p7, \[x0, z0\.s, sxtw #1\]
--.*: 84603c00 prfh pldl1keep, p7, \[x0, z0\.s, sxtw #1\]
--.*: 84602060 prfh pldl1keep, p0, \[x3, z0\.s, sxtw #1\]
--.*: 84602060 prfh pldl1keep, p0, \[x3, z0\.s, sxtw #1\]
--.*: 846023e0 prfh pldl1keep, p0, \[sp, z0\.s, sxtw #1\]
--.*: 846023e0 prfh pldl1keep, p0, \[sp, z0\.s, sxtw #1\]
--.*: 84642000 prfh pldl1keep, p0, \[x0, z4\.s, sxtw #1\]
--.*: 84642000 prfh pldl1keep, p0, \[x0, z4\.s, sxtw #1\]
--.*: 847f2000 prfh pldl1keep, p0, \[x0, z31\.s, sxtw #1\]
--.*: 847f2000 prfh pldl1keep, p0, \[x0, z31\.s, sxtw #1\]
--.*: 8480c000 prfh pldl1keep, p0, \[x0, x0, lsl #1\]
--.*: 8480c000 prfh pldl1keep, p0, \[x0, x0, lsl #1\]
--.*: 8480c001 prfh pldl1strm, p0, \[x0, x0, lsl #1\]
--.*: 8480c001 prfh pldl1strm, p0, \[x0, x0, lsl #1\]
--.*: 8480c002 prfh pldl2keep, p0, \[x0, x0, lsl #1\]
--.*: 8480c002 prfh pldl2keep, p0, \[x0, x0, lsl #1\]
--.*: 8480c003 prfh pldl2strm, p0, \[x0, x0, lsl #1\]
--.*: 8480c003 prfh pldl2strm, p0, \[x0, x0, lsl #1\]
--.*: 8480c004 prfh pldl3keep, p0, \[x0, x0, lsl #1\]
--.*: 8480c004 prfh pldl3keep, p0, \[x0, x0, lsl #1\]
--.*: 8480c005 prfh pldl3strm, p0, \[x0, x0, lsl #1\]
--.*: 8480c005 prfh pldl3strm, p0, \[x0, x0, lsl #1\]
--.*: 8480c006 prfh #6, p0, \[x0, x0, lsl #1\]
--.*: 8480c006 prfh #6, p0, \[x0, x0, lsl #1\]
--.*: 8480c007 prfh #7, p0, \[x0, x0, lsl #1\]
--.*: 8480c007 prfh #7, p0, \[x0, x0, lsl #1\]
--.*: 8480c008 prfh pstl1keep, p0, \[x0, x0, lsl #1\]
--.*: 8480c008 prfh pstl1keep, p0, \[x0, x0, lsl #1\]
--.*: 8480c009 prfh pstl1strm, p0, \[x0, x0, lsl #1\]
--.*: 8480c009 prfh pstl1strm, p0, \[x0, x0, lsl #1\]
--.*: 8480c00a prfh pstl2keep, p0, \[x0, x0, lsl #1\]
--.*: 8480c00a prfh pstl2keep, p0, \[x0, x0, lsl #1\]
--.*: 8480c00b prfh pstl2strm, p0, \[x0, x0, lsl #1\]
--.*: 8480c00b prfh pstl2strm, p0, \[x0, x0, lsl #1\]
--.*: 8480c00c prfh pstl3keep, p0, \[x0, x0, lsl #1\]
--.*: 8480c00c prfh pstl3keep, p0, \[x0, x0, lsl #1\]
--.*: 8480c00d prfh pstl3strm, p0, \[x0, x0, lsl #1\]
--.*: 8480c00d prfh pstl3strm, p0, \[x0, x0, lsl #1\]
--.*: 8480c00e prfh #14, p0, \[x0, x0, lsl #1\]
--.*: 8480c00e prfh #14, p0, \[x0, x0, lsl #1\]
--.*: 8480c00f prfh #15, p0, \[x0, x0, lsl #1\]
--.*: 8480c00f prfh #15, p0, \[x0, x0, lsl #1\]
--.*: 8480c800 prfh pldl1keep, p2, \[x0, x0, lsl #1\]
--.*: 8480c800 prfh pldl1keep, p2, \[x0, x0, lsl #1\]
--.*: 8480dc00 prfh pldl1keep, p7, \[x0, x0, lsl #1\]
--.*: 8480dc00 prfh pldl1keep, p7, \[x0, x0, lsl #1\]
--.*: 8480c060 prfh pldl1keep, p0, \[x3, x0, lsl #1\]
--.*: 8480c060 prfh pldl1keep, p0, \[x3, x0, lsl #1\]
--.*: 8480c3e0 prfh pldl1keep, p0, \[sp, x0, lsl #1\]
--.*: 8480c3e0 prfh pldl1keep, p0, \[sp, x0, lsl #1\]
--.*: 8484c000 prfh pldl1keep, p0, \[x0, x4, lsl #1\]
--.*: 8484c000 prfh pldl1keep, p0, \[x0, x4, lsl #1\]
--.*: 849ec000 prfh pldl1keep, p0, \[x0, x30, lsl #1\]
--.*: 849ec000 prfh pldl1keep, p0, \[x0, x30, lsl #1\]
--.*: c4202000 prfh pldl1keep, p0, \[x0, z0\.d, uxtw #1\]
--.*: c4202000 prfh pldl1keep, p0, \[x0, z0\.d, uxtw #1\]
--.*: c4202001 prfh pldl1strm, p0, \[x0, z0\.d, uxtw #1\]
--.*: c4202001 prfh pldl1strm, p0, \[x0, z0\.d, uxtw #1\]
--.*: c4202002 prfh pldl2keep, p0, \[x0, z0\.d, uxtw #1\]
--.*: c4202002 prfh pldl2keep, p0, \[x0, z0\.d, uxtw #1\]
--.*: c4202003 prfh pldl2strm, p0, \[x0, z0\.d, uxtw #1\]
--.*: c4202003 prfh pldl2strm, p0, \[x0, z0\.d, uxtw #1\]
--.*: c4202004 prfh pldl3keep, p0, \[x0, z0\.d, uxtw #1\]
--.*: c4202004 prfh pldl3keep, p0, \[x0, z0\.d, uxtw #1\]
--.*: c4202005 prfh pldl3strm, p0, \[x0, z0\.d, uxtw #1\]
--.*: c4202005 prfh pldl3strm, p0, \[x0, z0\.d, uxtw #1\]
--.*: c4202006 prfh #6, p0, \[x0, z0\.d, uxtw #1\]
--.*: c4202006 prfh #6, p0, \[x0, z0\.d, uxtw #1\]
--.*: c4202007 prfh #7, p0, \[x0, z0\.d, uxtw #1\]
--.*: c4202007 prfh #7, p0, \[x0, z0\.d, uxtw #1\]
--.*: c4202008 prfh pstl1keep, p0, \[x0, z0\.d, uxtw #1\]
--.*: c4202008 prfh pstl1keep, p0, \[x0, z0\.d, uxtw #1\]
--.*: c4202009 prfh pstl1strm, p0, \[x0, z0\.d, uxtw #1\]
--.*: c4202009 prfh pstl1strm, p0, \[x0, z0\.d, uxtw #1\]
--.*: c420200a prfh pstl2keep, p0, \[x0, z0\.d, uxtw #1\]
--.*: c420200a prfh pstl2keep, p0, \[x0, z0\.d, uxtw #1\]
--.*: c420200b prfh pstl2strm, p0, \[x0, z0\.d, uxtw #1\]
--.*: c420200b prfh pstl2strm, p0, \[x0, z0\.d, uxtw #1\]
--.*: c420200c prfh pstl3keep, p0, \[x0, z0\.d, uxtw #1\]
--.*: c420200c prfh pstl3keep, p0, \[x0, z0\.d, uxtw #1\]
--.*: c420200d prfh pstl3strm, p0, \[x0, z0\.d, uxtw #1\]
--.*: c420200d prfh pstl3strm, p0, \[x0, z0\.d, uxtw #1\]
--.*: c420200e prfh #14, p0, \[x0, z0\.d, uxtw #1\]
--.*: c420200e prfh #14, p0, \[x0, z0\.d, uxtw #1\]
--.*: c420200f prfh #15, p0, \[x0, z0\.d, uxtw #1\]
--.*: c420200f prfh #15, p0, \[x0, z0\.d, uxtw #1\]
--.*: c4202800 prfh pldl1keep, p2, \[x0, z0\.d, uxtw #1\]
--.*: c4202800 prfh pldl1keep, p2, \[x0, z0\.d, uxtw #1\]
--.*: c4203c00 prfh pldl1keep, p7, \[x0, z0\.d, uxtw #1\]
--.*: c4203c00 prfh pldl1keep, p7, \[x0, z0\.d, uxtw #1\]
--.*: c4202060 prfh pldl1keep, p0, \[x3, z0\.d, uxtw #1\]
--.*: c4202060 prfh pldl1keep, p0, \[x3, z0\.d, uxtw #1\]
--.*: c42023e0 prfh pldl1keep, p0, \[sp, z0\.d, uxtw #1\]
--.*: c42023e0 prfh pldl1keep, p0, \[sp, z0\.d, uxtw #1\]
--.*: c4242000 prfh pldl1keep, p0, \[x0, z4\.d, uxtw #1\]
--.*: c4242000 prfh pldl1keep, p0, \[x0, z4\.d, uxtw #1\]
--.*: c43f2000 prfh pldl1keep, p0, \[x0, z31\.d, uxtw #1\]
--.*: c43f2000 prfh pldl1keep, p0, \[x0, z31\.d, uxtw #1\]
--.*: c4602000 prfh pldl1keep, p0, \[x0, z0\.d, sxtw #1\]
--.*: c4602000 prfh pldl1keep, p0, \[x0, z0\.d, sxtw #1\]
--.*: c4602001 prfh pldl1strm, p0, \[x0, z0\.d, sxtw #1\]
--.*: c4602001 prfh pldl1strm, p0, \[x0, z0\.d, sxtw #1\]
--.*: c4602002 prfh pldl2keep, p0, \[x0, z0\.d, sxtw #1\]
--.*: c4602002 prfh pldl2keep, p0, \[x0, z0\.d, sxtw #1\]
--.*: c4602003 prfh pldl2strm, p0, \[x0, z0\.d, sxtw #1\]
--.*: c4602003 prfh pldl2strm, p0, \[x0, z0\.d, sxtw #1\]
--.*: c4602004 prfh pldl3keep, p0, \[x0, z0\.d, sxtw #1\]
--.*: c4602004 prfh pldl3keep, p0, \[x0, z0\.d, sxtw #1\]
--.*: c4602005 prfh pldl3strm, p0, \[x0, z0\.d, sxtw #1\]
--.*: c4602005 prfh pldl3strm, p0, \[x0, z0\.d, sxtw #1\]
--.*: c4602006 prfh #6, p0, \[x0, z0\.d, sxtw #1\]
--.*: c4602006 prfh #6, p0, \[x0, z0\.d, sxtw #1\]
--.*: c4602007 prfh #7, p0, \[x0, z0\.d, sxtw #1\]
--.*: c4602007 prfh #7, p0, \[x0, z0\.d, sxtw #1\]
--.*: c4602008 prfh pstl1keep, p0, \[x0, z0\.d, sxtw #1\]
--.*: c4602008 prfh pstl1keep, p0, \[x0, z0\.d, sxtw #1\]
--.*: c4602009 prfh pstl1strm, p0, \[x0, z0\.d, sxtw #1\]
--.*: c4602009 prfh pstl1strm, p0, \[x0, z0\.d, sxtw #1\]
--.*: c460200a prfh pstl2keep, p0, \[x0, z0\.d, sxtw #1\]
--.*: c460200a prfh pstl2keep, p0, \[x0, z0\.d, sxtw #1\]
--.*: c460200b prfh pstl2strm, p0, \[x0, z0\.d, sxtw #1\]
--.*: c460200b prfh pstl2strm, p0, \[x0, z0\.d, sxtw #1\]
--.*: c460200c prfh pstl3keep, p0, \[x0, z0\.d, sxtw #1\]
--.*: c460200c prfh pstl3keep, p0, \[x0, z0\.d, sxtw #1\]
--.*: c460200d prfh pstl3strm, p0, \[x0, z0\.d, sxtw #1\]
--.*: c460200d prfh pstl3strm, p0, \[x0, z0\.d, sxtw #1\]
--.*: c460200e prfh #14, p0, \[x0, z0\.d, sxtw #1\]
--.*: c460200e prfh #14, p0, \[x0, z0\.d, sxtw #1\]
--.*: c460200f prfh #15, p0, \[x0, z0\.d, sxtw #1\]
--.*: c460200f prfh #15, p0, \[x0, z0\.d, sxtw #1\]
--.*: c4602800 prfh pldl1keep, p2, \[x0, z0\.d, sxtw #1\]
--.*: c4602800 prfh pldl1keep, p2, \[x0, z0\.d, sxtw #1\]
--.*: c4603c00 prfh pldl1keep, p7, \[x0, z0\.d, sxtw #1\]
--.*: c4603c00 prfh pldl1keep, p7, \[x0, z0\.d, sxtw #1\]
--.*: c4602060 prfh pldl1keep, p0, \[x3, z0\.d, sxtw #1\]
--.*: c4602060 prfh pldl1keep, p0, \[x3, z0\.d, sxtw #1\]
--.*: c46023e0 prfh pldl1keep, p0, \[sp, z0\.d, sxtw #1\]
--.*: c46023e0 prfh pldl1keep, p0, \[sp, z0\.d, sxtw #1\]
--.*: c4642000 prfh pldl1keep, p0, \[x0, z4\.d, sxtw #1\]
--.*: c4642000 prfh pldl1keep, p0, \[x0, z4\.d, sxtw #1\]
--.*: c47f2000 prfh pldl1keep, p0, \[x0, z31\.d, sxtw #1\]
--.*: c47f2000 prfh pldl1keep, p0, \[x0, z31\.d, sxtw #1\]
--.*: c460a000 prfh pldl1keep, p0, \[x0, z0\.d, lsl #1\]
--.*: c460a000 prfh pldl1keep, p0, \[x0, z0\.d, lsl #1\]
--.*: c460a001 prfh pldl1strm, p0, \[x0, z0\.d, lsl #1\]
--.*: c460a001 prfh pldl1strm, p0, \[x0, z0\.d, lsl #1\]
--.*: c460a002 prfh pldl2keep, p0, \[x0, z0\.d, lsl #1\]
--.*: c460a002 prfh pldl2keep, p0, \[x0, z0\.d, lsl #1\]
--.*: c460a003 prfh pldl2strm, p0, \[x0, z0\.d, lsl #1\]
--.*: c460a003 prfh pldl2strm, p0, \[x0, z0\.d, lsl #1\]
--.*: c460a004 prfh pldl3keep, p0, \[x0, z0\.d, lsl #1\]
--.*: c460a004 prfh pldl3keep, p0, \[x0, z0\.d, lsl #1\]
--.*: c460a005 prfh pldl3strm, p0, \[x0, z0\.d, lsl #1\]
--.*: c460a005 prfh pldl3strm, p0, \[x0, z0\.d, lsl #1\]
--.*: c460a006 prfh #6, p0, \[x0, z0\.d, lsl #1\]
--.*: c460a006 prfh #6, p0, \[x0, z0\.d, lsl #1\]
--.*: c460a007 prfh #7, p0, \[x0, z0\.d, lsl #1\]
--.*: c460a007 prfh #7, p0, \[x0, z0\.d, lsl #1\]
--.*: c460a008 prfh pstl1keep, p0, \[x0, z0\.d, lsl #1\]
--.*: c460a008 prfh pstl1keep, p0, \[x0, z0\.d, lsl #1\]
--.*: c460a009 prfh pstl1strm, p0, \[x0, z0\.d, lsl #1\]
--.*: c460a009 prfh pstl1strm, p0, \[x0, z0\.d, lsl #1\]
--.*: c460a00a prfh pstl2keep, p0, \[x0, z0\.d, lsl #1\]
--.*: c460a00a prfh pstl2keep, p0, \[x0, z0\.d, lsl #1\]
--.*: c460a00b prfh pstl2strm, p0, \[x0, z0\.d, lsl #1\]
--.*: c460a00b prfh pstl2strm, p0, \[x0, z0\.d, lsl #1\]
--.*: c460a00c prfh pstl3keep, p0, \[x0, z0\.d, lsl #1\]
--.*: c460a00c prfh pstl3keep, p0, \[x0, z0\.d, lsl #1\]
--.*: c460a00d prfh pstl3strm, p0, \[x0, z0\.d, lsl #1\]
--.*: c460a00d prfh pstl3strm, p0, \[x0, z0\.d, lsl #1\]
--.*: c460a00e prfh #14, p0, \[x0, z0\.d, lsl #1\]
--.*: c460a00e prfh #14, p0, \[x0, z0\.d, lsl #1\]
--.*: c460a00f prfh #15, p0, \[x0, z0\.d, lsl #1\]
--.*: c460a00f prfh #15, p0, \[x0, z0\.d, lsl #1\]
--.*: c460a800 prfh pldl1keep, p2, \[x0, z0\.d, lsl #1\]
--.*: c460a800 prfh pldl1keep, p2, \[x0, z0\.d, lsl #1\]
--.*: c460bc00 prfh pldl1keep, p7, \[x0, z0\.d, lsl #1\]
--.*: c460bc00 prfh pldl1keep, p7, \[x0, z0\.d, lsl #1\]
--.*: c460a060 prfh pldl1keep, p0, \[x3, z0\.d, lsl #1\]
--.*: c460a060 prfh pldl1keep, p0, \[x3, z0\.d, lsl #1\]
--.*: c460a3e0 prfh pldl1keep, p0, \[sp, z0\.d, lsl #1\]
--.*: c460a3e0 prfh pldl1keep, p0, \[sp, z0\.d, lsl #1\]
--.*: c464a000 prfh pldl1keep, p0, \[x0, z4\.d, lsl #1\]
--.*: c464a000 prfh pldl1keep, p0, \[x0, z4\.d, lsl #1\]
--.*: c47fa000 prfh pldl1keep, p0, \[x0, z31\.d, lsl #1\]
--.*: c47fa000 prfh pldl1keep, p0, \[x0, z31\.d, lsl #1\]
--.*: 8480e000 prfh pldl1keep, p0, \[z0\.s\]
--.*: 8480e000 prfh pldl1keep, p0, \[z0\.s\]
--.*: 8480e000 prfh pldl1keep, p0, \[z0\.s\]
--.*: 8480e001 prfh pldl1strm, p0, \[z0\.s\]
--.*: 8480e001 prfh pldl1strm, p0, \[z0\.s\]
--.*: 8480e001 prfh pldl1strm, p0, \[z0\.s\]
--.*: 8480e002 prfh pldl2keep, p0, \[z0\.s\]
--.*: 8480e002 prfh pldl2keep, p0, \[z0\.s\]
--.*: 8480e002 prfh pldl2keep, p0, \[z0\.s\]
--.*: 8480e003 prfh pldl2strm, p0, \[z0\.s\]
--.*: 8480e003 prfh pldl2strm, p0, \[z0\.s\]
--.*: 8480e003 prfh pldl2strm, p0, \[z0\.s\]
--.*: 8480e004 prfh pldl3keep, p0, \[z0\.s\]
--.*: 8480e004 prfh pldl3keep, p0, \[z0\.s\]
--.*: 8480e004 prfh pldl3keep, p0, \[z0\.s\]
--.*: 8480e005 prfh pldl3strm, p0, \[z0\.s\]
--.*: 8480e005 prfh pldl3strm, p0, \[z0\.s\]
--.*: 8480e005 prfh pldl3strm, p0, \[z0\.s\]
--.*: 8480e006 prfh #6, p0, \[z0\.s\]
--.*: 8480e006 prfh #6, p0, \[z0\.s\]
--.*: 8480e006 prfh #6, p0, \[z0\.s\]
--.*: 8480e007 prfh #7, p0, \[z0\.s\]
--.*: 8480e007 prfh #7, p0, \[z0\.s\]
--.*: 8480e007 prfh #7, p0, \[z0\.s\]
--.*: 8480e008 prfh pstl1keep, p0, \[z0\.s\]
--.*: 8480e008 prfh pstl1keep, p0, \[z0\.s\]
--.*: 8480e008 prfh pstl1keep, p0, \[z0\.s\]
--.*: 8480e009 prfh pstl1strm, p0, \[z0\.s\]
--.*: 8480e009 prfh pstl1strm, p0, \[z0\.s\]
--.*: 8480e009 prfh pstl1strm, p0, \[z0\.s\]
--.*: 8480e00a prfh pstl2keep, p0, \[z0\.s\]
--.*: 8480e00a prfh pstl2keep, p0, \[z0\.s\]
--.*: 8480e00a prfh pstl2keep, p0, \[z0\.s\]
--.*: 8480e00b prfh pstl2strm, p0, \[z0\.s\]
--.*: 8480e00b prfh pstl2strm, p0, \[z0\.s\]
--.*: 8480e00b prfh pstl2strm, p0, \[z0\.s\]
--.*: 8480e00c prfh pstl3keep, p0, \[z0\.s\]
--.*: 8480e00c prfh pstl3keep, p0, \[z0\.s\]
--.*: 8480e00c prfh pstl3keep, p0, \[z0\.s\]
--.*: 8480e00d prfh pstl3strm, p0, \[z0\.s\]
--.*: 8480e00d prfh pstl3strm, p0, \[z0\.s\]
--.*: 8480e00d prfh pstl3strm, p0, \[z0\.s\]
--.*: 8480e00e prfh #14, p0, \[z0\.s\]
--.*: 8480e00e prfh #14, p0, \[z0\.s\]
--.*: 8480e00e prfh #14, p0, \[z0\.s\]
--.*: 8480e00f prfh #15, p0, \[z0\.s\]
--.*: 8480e00f prfh #15, p0, \[z0\.s\]
--.*: 8480e00f prfh #15, p0, \[z0\.s\]
--.*: 8480e800 prfh pldl1keep, p2, \[z0\.s\]
--.*: 8480e800 prfh pldl1keep, p2, \[z0\.s\]
--.*: 8480e800 prfh pldl1keep, p2, \[z0\.s\]
--.*: 8480fc00 prfh pldl1keep, p7, \[z0\.s\]
--.*: 8480fc00 prfh pldl1keep, p7, \[z0\.s\]
--.*: 8480fc00 prfh pldl1keep, p7, \[z0\.s\]
--.*: 8480e060 prfh pldl1keep, p0, \[z3\.s\]
--.*: 8480e060 prfh pldl1keep, p0, \[z3\.s\]
--.*: 8480e060 prfh pldl1keep, p0, \[z3\.s\]
--.*: 8480e3e0 prfh pldl1keep, p0, \[z31\.s\]
--.*: 8480e3e0 prfh pldl1keep, p0, \[z31\.s\]
--.*: 8480e3e0 prfh pldl1keep, p0, \[z31\.s\]
--.*: 848fe000 prfh pldl1keep, p0, \[z0\.s, #30\]
--.*: 848fe000 prfh pldl1keep, p0, \[z0\.s, #30\]
--.*: 8490e000 prfh pldl1keep, p0, \[z0\.s, #32\]
--.*: 8490e000 prfh pldl1keep, p0, \[z0\.s, #32\]
--.*: 8491e000 prfh pldl1keep, p0, \[z0\.s, #34\]
--.*: 8491e000 prfh pldl1keep, p0, \[z0\.s, #34\]
--.*: 849fe000 prfh pldl1keep, p0, \[z0\.s, #62\]
--.*: 849fe000 prfh pldl1keep, p0, \[z0\.s, #62\]
--.*: 85c02000 prfh pldl1keep, p0, \[x0\]
--.*: 85c02000 prfh pldl1keep, p0, \[x0\]
--.*: 85c02000 prfh pldl1keep, p0, \[x0\]
--.*: 85c02000 prfh pldl1keep, p0, \[x0\]
--.*: 85c02001 prfh pldl1strm, p0, \[x0\]
--.*: 85c02001 prfh pldl1strm, p0, \[x0\]
--.*: 85c02001 prfh pldl1strm, p0, \[x0\]
--.*: 85c02001 prfh pldl1strm, p0, \[x0\]
--.*: 85c02002 prfh pldl2keep, p0, \[x0\]
--.*: 85c02002 prfh pldl2keep, p0, \[x0\]
--.*: 85c02002 prfh pldl2keep, p0, \[x0\]
--.*: 85c02002 prfh pldl2keep, p0, \[x0\]
--.*: 85c02003 prfh pldl2strm, p0, \[x0\]
--.*: 85c02003 prfh pldl2strm, p0, \[x0\]
--.*: 85c02003 prfh pldl2strm, p0, \[x0\]
--.*: 85c02003 prfh pldl2strm, p0, \[x0\]
--.*: 85c02004 prfh pldl3keep, p0, \[x0\]
--.*: 85c02004 prfh pldl3keep, p0, \[x0\]
--.*: 85c02004 prfh pldl3keep, p0, \[x0\]
--.*: 85c02004 prfh pldl3keep, p0, \[x0\]
--.*: 85c02005 prfh pldl3strm, p0, \[x0\]
--.*: 85c02005 prfh pldl3strm, p0, \[x0\]
--.*: 85c02005 prfh pldl3strm, p0, \[x0\]
--.*: 85c02005 prfh pldl3strm, p0, \[x0\]
--.*: 85c02006 prfh #6, p0, \[x0\]
--.*: 85c02006 prfh #6, p0, \[x0\]
--.*: 85c02006 prfh #6, p0, \[x0\]
--.*: 85c02006 prfh #6, p0, \[x0\]
--.*: 85c02007 prfh #7, p0, \[x0\]
--.*: 85c02007 prfh #7, p0, \[x0\]
--.*: 85c02007 prfh #7, p0, \[x0\]
--.*: 85c02007 prfh #7, p0, \[x0\]
--.*: 85c02008 prfh pstl1keep, p0, \[x0\]
--.*: 85c02008 prfh pstl1keep, p0, \[x0\]
--.*: 85c02008 prfh pstl1keep, p0, \[x0\]
--.*: 85c02008 prfh pstl1keep, p0, \[x0\]
--.*: 85c02009 prfh pstl1strm, p0, \[x0\]
--.*: 85c02009 prfh pstl1strm, p0, \[x0\]
--.*: 85c02009 prfh pstl1strm, p0, \[x0\]
--.*: 85c02009 prfh pstl1strm, p0, \[x0\]
--.*: 85c0200a prfh pstl2keep, p0, \[x0\]
--.*: 85c0200a prfh pstl2keep, p0, \[x0\]
--.*: 85c0200a prfh pstl2keep, p0, \[x0\]
--.*: 85c0200a prfh pstl2keep, p0, \[x0\]
--.*: 85c0200b prfh pstl2strm, p0, \[x0\]
--.*: 85c0200b prfh pstl2strm, p0, \[x0\]
--.*: 85c0200b prfh pstl2strm, p0, \[x0\]
--.*: 85c0200b prfh pstl2strm, p0, \[x0\]
--.*: 85c0200c prfh pstl3keep, p0, \[x0\]
--.*: 85c0200c prfh pstl3keep, p0, \[x0\]
--.*: 85c0200c prfh pstl3keep, p0, \[x0\]
--.*: 85c0200c prfh pstl3keep, p0, \[x0\]
--.*: 85c0200d prfh pstl3strm, p0, \[x0\]
--.*: 85c0200d prfh pstl3strm, p0, \[x0\]
--.*: 85c0200d prfh pstl3strm, p0, \[x0\]
--.*: 85c0200d prfh pstl3strm, p0, \[x0\]
--.*: 85c0200e prfh #14, p0, \[x0\]
--.*: 85c0200e prfh #14, p0, \[x0\]
--.*: 85c0200e prfh #14, p0, \[x0\]
--.*: 85c0200e prfh #14, p0, \[x0\]
--.*: 85c0200f prfh #15, p0, \[x0\]
--.*: 85c0200f prfh #15, p0, \[x0\]
--.*: 85c0200f prfh #15, p0, \[x0\]
--.*: 85c0200f prfh #15, p0, \[x0\]
--.*: 85c02800 prfh pldl1keep, p2, \[x0\]
--.*: 85c02800 prfh pldl1keep, p2, \[x0\]
--.*: 85c02800 prfh pldl1keep, p2, \[x0\]
--.*: 85c02800 prfh pldl1keep, p2, \[x0\]
--.*: 85c03c00 prfh pldl1keep, p7, \[x0\]
--.*: 85c03c00 prfh pldl1keep, p7, \[x0\]
--.*: 85c03c00 prfh pldl1keep, p7, \[x0\]
--.*: 85c03c00 prfh pldl1keep, p7, \[x0\]
--.*: 85c02060 prfh pldl1keep, p0, \[x3\]
--.*: 85c02060 prfh pldl1keep, p0, \[x3\]
--.*: 85c02060 prfh pldl1keep, p0, \[x3\]
--.*: 85c02060 prfh pldl1keep, p0, \[x3\]
--.*: 85c023e0 prfh pldl1keep, p0, \[sp\]
--.*: 85c023e0 prfh pldl1keep, p0, \[sp\]
--.*: 85c023e0 prfh pldl1keep, p0, \[sp\]
--.*: 85c023e0 prfh pldl1keep, p0, \[sp\]
--.*: 85df2000 prfh pldl1keep, p0, \[x0, #31, mul vl\]
--.*: 85df2000 prfh pldl1keep, p0, \[x0, #31, mul vl\]
--.*: 85e02000 prfh pldl1keep, p0, \[x0, #-32, mul vl\]
--.*: 85e02000 prfh pldl1keep, p0, \[x0, #-32, mul vl\]
--.*: 85e12000 prfh pldl1keep, p0, \[x0, #-31, mul vl\]
--.*: 85e12000 prfh pldl1keep, p0, \[x0, #-31, mul vl\]
--.*: 85ff2000 prfh pldl1keep, p0, \[x0, #-1, mul vl\]
--.*: 85ff2000 prfh pldl1keep, p0, \[x0, #-1, mul vl\]
--.*: c480e000 prfh pldl1keep, p0, \[z0\.d\]
--.*: c480e000 prfh pldl1keep, p0, \[z0\.d\]
--.*: c480e000 prfh pldl1keep, p0, \[z0\.d\]
--.*: c480e001 prfh pldl1strm, p0, \[z0\.d\]
--.*: c480e001 prfh pldl1strm, p0, \[z0\.d\]
--.*: c480e001 prfh pldl1strm, p0, \[z0\.d\]
--.*: c480e002 prfh pldl2keep, p0, \[z0\.d\]
--.*: c480e002 prfh pldl2keep, p0, \[z0\.d\]
--.*: c480e002 prfh pldl2keep, p0, \[z0\.d\]
--.*: c480e003 prfh pldl2strm, p0, \[z0\.d\]
--.*: c480e003 prfh pldl2strm, p0, \[z0\.d\]
--.*: c480e003 prfh pldl2strm, p0, \[z0\.d\]
--.*: c480e004 prfh pldl3keep, p0, \[z0\.d\]
--.*: c480e004 prfh pldl3keep, p0, \[z0\.d\]
--.*: c480e004 prfh pldl3keep, p0, \[z0\.d\]
--.*: c480e005 prfh pldl3strm, p0, \[z0\.d\]
--.*: c480e005 prfh pldl3strm, p0, \[z0\.d\]
--.*: c480e005 prfh pldl3strm, p0, \[z0\.d\]
--.*: c480e006 prfh #6, p0, \[z0\.d\]
--.*: c480e006 prfh #6, p0, \[z0\.d\]
--.*: c480e006 prfh #6, p0, \[z0\.d\]
--.*: c480e007 prfh #7, p0, \[z0\.d\]
--.*: c480e007 prfh #7, p0, \[z0\.d\]
--.*: c480e007 prfh #7, p0, \[z0\.d\]
--.*: c480e008 prfh pstl1keep, p0, \[z0\.d\]
--.*: c480e008 prfh pstl1keep, p0, \[z0\.d\]
--.*: c480e008 prfh pstl1keep, p0, \[z0\.d\]
--.*: c480e009 prfh pstl1strm, p0, \[z0\.d\]
--.*: c480e009 prfh pstl1strm, p0, \[z0\.d\]
--.*: c480e009 prfh pstl1strm, p0, \[z0\.d\]
--.*: c480e00a prfh pstl2keep, p0, \[z0\.d\]
--.*: c480e00a prfh pstl2keep, p0, \[z0\.d\]
--.*: c480e00a prfh pstl2keep, p0, \[z0\.d\]
--.*: c480e00b prfh pstl2strm, p0, \[z0\.d\]
--.*: c480e00b prfh pstl2strm, p0, \[z0\.d\]
--.*: c480e00b prfh pstl2strm, p0, \[z0\.d\]
--.*: c480e00c prfh pstl3keep, p0, \[z0\.d\]
--.*: c480e00c prfh pstl3keep, p0, \[z0\.d\]
--.*: c480e00c prfh pstl3keep, p0, \[z0\.d\]
--.*: c480e00d prfh pstl3strm, p0, \[z0\.d\]
--.*: c480e00d prfh pstl3strm, p0, \[z0\.d\]
--.*: c480e00d prfh pstl3strm, p0, \[z0\.d\]
--.*: c480e00e prfh #14, p0, \[z0\.d\]
--.*: c480e00e prfh #14, p0, \[z0\.d\]
--.*: c480e00e prfh #14, p0, \[z0\.d\]
--.*: c480e00f prfh #15, p0, \[z0\.d\]
--.*: c480e00f prfh #15, p0, \[z0\.d\]
--.*: c480e00f prfh #15, p0, \[z0\.d\]
--.*: c480e800 prfh pldl1keep, p2, \[z0\.d\]
--.*: c480e800 prfh pldl1keep, p2, \[z0\.d\]
--.*: c480e800 prfh pldl1keep, p2, \[z0\.d\]
--.*: c480fc00 prfh pldl1keep, p7, \[z0\.d\]
--.*: c480fc00 prfh pldl1keep, p7, \[z0\.d\]
--.*: c480fc00 prfh pldl1keep, p7, \[z0\.d\]
--.*: c480e060 prfh pldl1keep, p0, \[z3\.d\]
--.*: c480e060 prfh pldl1keep, p0, \[z3\.d\]
--.*: c480e060 prfh pldl1keep, p0, \[z3\.d\]
--.*: c480e3e0 prfh pldl1keep, p0, \[z31\.d\]
--.*: c480e3e0 prfh pldl1keep, p0, \[z31\.d\]
--.*: c480e3e0 prfh pldl1keep, p0, \[z31\.d\]
--.*: c48fe000 prfh pldl1keep, p0, \[z0\.d, #30\]
--.*: c48fe000 prfh pldl1keep, p0, \[z0\.d, #30\]
--.*: c490e000 prfh pldl1keep, p0, \[z0\.d, #32\]
--.*: c490e000 prfh pldl1keep, p0, \[z0\.d, #32\]
--.*: c491e000 prfh pldl1keep, p0, \[z0\.d, #34\]
--.*: c491e000 prfh pldl1keep, p0, \[z0\.d, #34\]
--.*: c49fe000 prfh pldl1keep, p0, \[z0\.d, #62\]
--.*: c49fe000 prfh pldl1keep, p0, \[z0\.d, #62\]
--.*: 84204000 prfw pldl1keep, p0, \[x0, z0\.s, uxtw #2\]
--.*: 84204000 prfw pldl1keep, p0, \[x0, z0\.s, uxtw #2\]
--.*: 84204001 prfw pldl1strm, p0, \[x0, z0\.s, uxtw #2\]
--.*: 84204001 prfw pldl1strm, p0, \[x0, z0\.s, uxtw #2\]
--.*: 84204002 prfw pldl2keep, p0, \[x0, z0\.s, uxtw #2\]
--.*: 84204002 prfw pldl2keep, p0, \[x0, z0\.s, uxtw #2\]
--.*: 84204003 prfw pldl2strm, p0, \[x0, z0\.s, uxtw #2\]
--.*: 84204003 prfw pldl2strm, p0, \[x0, z0\.s, uxtw #2\]
--.*: 84204004 prfw pldl3keep, p0, \[x0, z0\.s, uxtw #2\]
--.*: 84204004 prfw pldl3keep, p0, \[x0, z0\.s, uxtw #2\]
--.*: 84204005 prfw pldl3strm, p0, \[x0, z0\.s, uxtw #2\]
--.*: 84204005 prfw pldl3strm, p0, \[x0, z0\.s, uxtw #2\]
--.*: 84204006 prfw #6, p0, \[x0, z0\.s, uxtw #2\]
--.*: 84204006 prfw #6, p0, \[x0, z0\.s, uxtw #2\]
--.*: 84204007 prfw #7, p0, \[x0, z0\.s, uxtw #2\]
--.*: 84204007 prfw #7, p0, \[x0, z0\.s, uxtw #2\]
--.*: 84204008 prfw pstl1keep, p0, \[x0, z0\.s, uxtw #2\]
--.*: 84204008 prfw pstl1keep, p0, \[x0, z0\.s, uxtw #2\]
--.*: 84204009 prfw pstl1strm, p0, \[x0, z0\.s, uxtw #2\]
--.*: 84204009 prfw pstl1strm, p0, \[x0, z0\.s, uxtw #2\]
--.*: 8420400a prfw pstl2keep, p0, \[x0, z0\.s, uxtw #2\]
--.*: 8420400a prfw pstl2keep, p0, \[x0, z0\.s, uxtw #2\]
--.*: 8420400b prfw pstl2strm, p0, \[x0, z0\.s, uxtw #2\]
--.*: 8420400b prfw pstl2strm, p0, \[x0, z0\.s, uxtw #2\]
--.*: 8420400c prfw pstl3keep, p0, \[x0, z0\.s, uxtw #2\]
--.*: 8420400c prfw pstl3keep, p0, \[x0, z0\.s, uxtw #2\]
--.*: 8420400d prfw pstl3strm, p0, \[x0, z0\.s, uxtw #2\]
--.*: 8420400d prfw pstl3strm, p0, \[x0, z0\.s, uxtw #2\]
--.*: 8420400e prfw #14, p0, \[x0, z0\.s, uxtw #2\]
--.*: 8420400e prfw #14, p0, \[x0, z0\.s, uxtw #2\]
--.*: 8420400f prfw #15, p0, \[x0, z0\.s, uxtw #2\]
--.*: 8420400f prfw #15, p0, \[x0, z0\.s, uxtw #2\]
--.*: 84204800 prfw pldl1keep, p2, \[x0, z0\.s, uxtw #2\]
--.*: 84204800 prfw pldl1keep, p2, \[x0, z0\.s, uxtw #2\]
--.*: 84205c00 prfw pldl1keep, p7, \[x0, z0\.s, uxtw #2\]
--.*: 84205c00 prfw pldl1keep, p7, \[x0, z0\.s, uxtw #2\]
--.*: 84204060 prfw pldl1keep, p0, \[x3, z0\.s, uxtw #2\]
--.*: 84204060 prfw pldl1keep, p0, \[x3, z0\.s, uxtw #2\]
--.*: 842043e0 prfw pldl1keep, p0, \[sp, z0\.s, uxtw #2\]
--.*: 842043e0 prfw pldl1keep, p0, \[sp, z0\.s, uxtw #2\]
--.*: 84244000 prfw pldl1keep, p0, \[x0, z4\.s, uxtw #2\]
--.*: 84244000 prfw pldl1keep, p0, \[x0, z4\.s, uxtw #2\]
--.*: 843f4000 prfw pldl1keep, p0, \[x0, z31\.s, uxtw #2\]
--.*: 843f4000 prfw pldl1keep, p0, \[x0, z31\.s, uxtw #2\]
--.*: 84604000 prfw pldl1keep, p0, \[x0, z0\.s, sxtw #2\]
--.*: 84604000 prfw pldl1keep, p0, \[x0, z0\.s, sxtw #2\]
--.*: 84604001 prfw pldl1strm, p0, \[x0, z0\.s, sxtw #2\]
--.*: 84604001 prfw pldl1strm, p0, \[x0, z0\.s, sxtw #2\]
--.*: 84604002 prfw pldl2keep, p0, \[x0, z0\.s, sxtw #2\]
--.*: 84604002 prfw pldl2keep, p0, \[x0, z0\.s, sxtw #2\]
--.*: 84604003 prfw pldl2strm, p0, \[x0, z0\.s, sxtw #2\]
--.*: 84604003 prfw pldl2strm, p0, \[x0, z0\.s, sxtw #2\]
--.*: 84604004 prfw pldl3keep, p0, \[x0, z0\.s, sxtw #2\]
--.*: 84604004 prfw pldl3keep, p0, \[x0, z0\.s, sxtw #2\]
--.*: 84604005 prfw pldl3strm, p0, \[x0, z0\.s, sxtw #2\]
--.*: 84604005 prfw pldl3strm, p0, \[x0, z0\.s, sxtw #2\]
--.*: 84604006 prfw #6, p0, \[x0, z0\.s, sxtw #2\]
--.*: 84604006 prfw #6, p0, \[x0, z0\.s, sxtw #2\]
--.*: 84604007 prfw #7, p0, \[x0, z0\.s, sxtw #2\]
--.*: 84604007 prfw #7, p0, \[x0, z0\.s, sxtw #2\]
--.*: 84604008 prfw pstl1keep, p0, \[x0, z0\.s, sxtw #2\]
--.*: 84604008 prfw pstl1keep, p0, \[x0, z0\.s, sxtw #2\]
--.*: 84604009 prfw pstl1strm, p0, \[x0, z0\.s, sxtw #2\]
--.*: 84604009 prfw pstl1strm, p0, \[x0, z0\.s, sxtw #2\]
--.*: 8460400a prfw pstl2keep, p0, \[x0, z0\.s, sxtw #2\]
--.*: 8460400a prfw pstl2keep, p0, \[x0, z0\.s, sxtw #2\]
--.*: 8460400b prfw pstl2strm, p0, \[x0, z0\.s, sxtw #2\]
--.*: 8460400b prfw pstl2strm, p0, \[x0, z0\.s, sxtw #2\]
--.*: 8460400c prfw pstl3keep, p0, \[x0, z0\.s, sxtw #2\]
--.*: 8460400c prfw pstl3keep, p0, \[x0, z0\.s, sxtw #2\]
--.*: 8460400d prfw pstl3strm, p0, \[x0, z0\.s, sxtw #2\]
--.*: 8460400d prfw pstl3strm, p0, \[x0, z0\.s, sxtw #2\]
--.*: 8460400e prfw #14, p0, \[x0, z0\.s, sxtw #2\]
--.*: 8460400e prfw #14, p0, \[x0, z0\.s, sxtw #2\]
--.*: 8460400f prfw #15, p0, \[x0, z0\.s, sxtw #2\]
--.*: 8460400f prfw #15, p0, \[x0, z0\.s, sxtw #2\]
--.*: 84604800 prfw pldl1keep, p2, \[x0, z0\.s, sxtw #2\]
--.*: 84604800 prfw pldl1keep, p2, \[x0, z0\.s, sxtw #2\]
--.*: 84605c00 prfw pldl1keep, p7, \[x0, z0\.s, sxtw #2\]
--.*: 84605c00 prfw pldl1keep, p7, \[x0, z0\.s, sxtw #2\]
--.*: 84604060 prfw pldl1keep, p0, \[x3, z0\.s, sxtw #2\]
--.*: 84604060 prfw pldl1keep, p0, \[x3, z0\.s, sxtw #2\]
--.*: 846043e0 prfw pldl1keep, p0, \[sp, z0\.s, sxtw #2\]
--.*: 846043e0 prfw pldl1keep, p0, \[sp, z0\.s, sxtw #2\]
--.*: 84644000 prfw pldl1keep, p0, \[x0, z4\.s, sxtw #2\]
--.*: 84644000 prfw pldl1keep, p0, \[x0, z4\.s, sxtw #2\]
--.*: 847f4000 prfw pldl1keep, p0, \[x0, z31\.s, sxtw #2\]
--.*: 847f4000 prfw pldl1keep, p0, \[x0, z31\.s, sxtw #2\]
--.*: 8500c000 prfw pldl1keep, p0, \[x0, x0, lsl #2\]
--.*: 8500c000 prfw pldl1keep, p0, \[x0, x0, lsl #2\]
--.*: 8500c001 prfw pldl1strm, p0, \[x0, x0, lsl #2\]
--.*: 8500c001 prfw pldl1strm, p0, \[x0, x0, lsl #2\]
--.*: 8500c002 prfw pldl2keep, p0, \[x0, x0, lsl #2\]
--.*: 8500c002 prfw pldl2keep, p0, \[x0, x0, lsl #2\]
--.*: 8500c003 prfw pldl2strm, p0, \[x0, x0, lsl #2\]
--.*: 8500c003 prfw pldl2strm, p0, \[x0, x0, lsl #2\]
--.*: 8500c004 prfw pldl3keep, p0, \[x0, x0, lsl #2\]
--.*: 8500c004 prfw pldl3keep, p0, \[x0, x0, lsl #2\]
--.*: 8500c005 prfw pldl3strm, p0, \[x0, x0, lsl #2\]
--.*: 8500c005 prfw pldl3strm, p0, \[x0, x0, lsl #2\]
--.*: 8500c006 prfw #6, p0, \[x0, x0, lsl #2\]
--.*: 8500c006 prfw #6, p0, \[x0, x0, lsl #2\]
--.*: 8500c007 prfw #7, p0, \[x0, x0, lsl #2\]
--.*: 8500c007 prfw #7, p0, \[x0, x0, lsl #2\]
--.*: 8500c008 prfw pstl1keep, p0, \[x0, x0, lsl #2\]
--.*: 8500c008 prfw pstl1keep, p0, \[x0, x0, lsl #2\]
--.*: 8500c009 prfw pstl1strm, p0, \[x0, x0, lsl #2\]
--.*: 8500c009 prfw pstl1strm, p0, \[x0, x0, lsl #2\]
--.*: 8500c00a prfw pstl2keep, p0, \[x0, x0, lsl #2\]
--.*: 8500c00a prfw pstl2keep, p0, \[x0, x0, lsl #2\]
--.*: 8500c00b prfw pstl2strm, p0, \[x0, x0, lsl #2\]
--.*: 8500c00b prfw pstl2strm, p0, \[x0, x0, lsl #2\]
--.*: 8500c00c prfw pstl3keep, p0, \[x0, x0, lsl #2\]
--.*: 8500c00c prfw pstl3keep, p0, \[x0, x0, lsl #2\]
--.*: 8500c00d prfw pstl3strm, p0, \[x0, x0, lsl #2\]
--.*: 8500c00d prfw pstl3strm, p0, \[x0, x0, lsl #2\]
--.*: 8500c00e prfw #14, p0, \[x0, x0, lsl #2\]
--.*: 8500c00e prfw #14, p0, \[x0, x0, lsl #2\]
--.*: 8500c00f prfw #15, p0, \[x0, x0, lsl #2\]
--.*: 8500c00f prfw #15, p0, \[x0, x0, lsl #2\]
--.*: 8500c800 prfw pldl1keep, p2, \[x0, x0, lsl #2\]
--.*: 8500c800 prfw pldl1keep, p2, \[x0, x0, lsl #2\]
--.*: 8500dc00 prfw pldl1keep, p7, \[x0, x0, lsl #2\]
--.*: 8500dc00 prfw pldl1keep, p7, \[x0, x0, lsl #2\]
--.*: 8500c060 prfw pldl1keep, p0, \[x3, x0, lsl #2\]
--.*: 8500c060 prfw pldl1keep, p0, \[x3, x0, lsl #2\]
--.*: 8500c3e0 prfw pldl1keep, p0, \[sp, x0, lsl #2\]
--.*: 8500c3e0 prfw pldl1keep, p0, \[sp, x0, lsl #2\]
--.*: 8504c000 prfw pldl1keep, p0, \[x0, x4, lsl #2\]
--.*: 8504c000 prfw pldl1keep, p0, \[x0, x4, lsl #2\]
--.*: 851ec000 prfw pldl1keep, p0, \[x0, x30, lsl #2\]
--.*: 851ec000 prfw pldl1keep, p0, \[x0, x30, lsl #2\]
--.*: c4204000 prfw pldl1keep, p0, \[x0, z0\.d, uxtw #2\]
--.*: c4204000 prfw pldl1keep, p0, \[x0, z0\.d, uxtw #2\]
--.*: c4204001 prfw pldl1strm, p0, \[x0, z0\.d, uxtw #2\]
--.*: c4204001 prfw pldl1strm, p0, \[x0, z0\.d, uxtw #2\]
--.*: c4204002 prfw pldl2keep, p0, \[x0, z0\.d, uxtw #2\]
--.*: c4204002 prfw pldl2keep, p0, \[x0, z0\.d, uxtw #2\]
--.*: c4204003 prfw pldl2strm, p0, \[x0, z0\.d, uxtw #2\]
--.*: c4204003 prfw pldl2strm, p0, \[x0, z0\.d, uxtw #2\]
--.*: c4204004 prfw pldl3keep, p0, \[x0, z0\.d, uxtw #2\]
--.*: c4204004 prfw pldl3keep, p0, \[x0, z0\.d, uxtw #2\]
--.*: c4204005 prfw pldl3strm, p0, \[x0, z0\.d, uxtw #2\]
--.*: c4204005 prfw pldl3strm, p0, \[x0, z0\.d, uxtw #2\]
--.*: c4204006 prfw #6, p0, \[x0, z0\.d, uxtw #2\]
--.*: c4204006 prfw #6, p0, \[x0, z0\.d, uxtw #2\]
--.*: c4204007 prfw #7, p0, \[x0, z0\.d, uxtw #2\]
--.*: c4204007 prfw #7, p0, \[x0, z0\.d, uxtw #2\]
--.*: c4204008 prfw pstl1keep, p0, \[x0, z0\.d, uxtw #2\]
--.*: c4204008 prfw pstl1keep, p0, \[x0, z0\.d, uxtw #2\]
--.*: c4204009 prfw pstl1strm, p0, \[x0, z0\.d, uxtw #2\]
--.*: c4204009 prfw pstl1strm, p0, \[x0, z0\.d, uxtw #2\]
--.*: c420400a prfw pstl2keep, p0, \[x0, z0\.d, uxtw #2\]
--.*: c420400a prfw pstl2keep, p0, \[x0, z0\.d, uxtw #2\]
--.*: c420400b prfw pstl2strm, p0, \[x0, z0\.d, uxtw #2\]
--.*: c420400b prfw pstl2strm, p0, \[x0, z0\.d, uxtw #2\]
--.*: c420400c prfw pstl3keep, p0, \[x0, z0\.d, uxtw #2\]
--.*: c420400c prfw pstl3keep, p0, \[x0, z0\.d, uxtw #2\]
--.*: c420400d prfw pstl3strm, p0, \[x0, z0\.d, uxtw #2\]
--.*: c420400d prfw pstl3strm, p0, \[x0, z0\.d, uxtw #2\]
--.*: c420400e prfw #14, p0, \[x0, z0\.d, uxtw #2\]
--.*: c420400e prfw #14, p0, \[x0, z0\.d, uxtw #2\]
--.*: c420400f prfw #15, p0, \[x0, z0\.d, uxtw #2\]
--.*: c420400f prfw #15, p0, \[x0, z0\.d, uxtw #2\]
--.*: c4204800 prfw pldl1keep, p2, \[x0, z0\.d, uxtw #2\]
--.*: c4204800 prfw pldl1keep, p2, \[x0, z0\.d, uxtw #2\]
--.*: c4205c00 prfw pldl1keep, p7, \[x0, z0\.d, uxtw #2\]
--.*: c4205c00 prfw pldl1keep, p7, \[x0, z0\.d, uxtw #2\]
--.*: c4204060 prfw pldl1keep, p0, \[x3, z0\.d, uxtw #2\]
--.*: c4204060 prfw pldl1keep, p0, \[x3, z0\.d, uxtw #2\]
--.*: c42043e0 prfw pldl1keep, p0, \[sp, z0\.d, uxtw #2\]
--.*: c42043e0 prfw pldl1keep, p0, \[sp, z0\.d, uxtw #2\]
--.*: c4244000 prfw pldl1keep, p0, \[x0, z4\.d, uxtw #2\]
--.*: c4244000 prfw pldl1keep, p0, \[x0, z4\.d, uxtw #2\]
--.*: c43f4000 prfw pldl1keep, p0, \[x0, z31\.d, uxtw #2\]
--.*: c43f4000 prfw pldl1keep, p0, \[x0, z31\.d, uxtw #2\]
--.*: c4604000 prfw pldl1keep, p0, \[x0, z0\.d, sxtw #2\]
--.*: c4604000 prfw pldl1keep, p0, \[x0, z0\.d, sxtw #2\]
--.*: c4604001 prfw pldl1strm, p0, \[x0, z0\.d, sxtw #2\]
--.*: c4604001 prfw pldl1strm, p0, \[x0, z0\.d, sxtw #2\]
--.*: c4604002 prfw pldl2keep, p0, \[x0, z0\.d, sxtw #2\]
--.*: c4604002 prfw pldl2keep, p0, \[x0, z0\.d, sxtw #2\]
--.*: c4604003 prfw pldl2strm, p0, \[x0, z0\.d, sxtw #2\]
--.*: c4604003 prfw pldl2strm, p0, \[x0, z0\.d, sxtw #2\]
--.*: c4604004 prfw pldl3keep, p0, \[x0, z0\.d, sxtw #2\]
--.*: c4604004 prfw pldl3keep, p0, \[x0, z0\.d, sxtw #2\]
--.*: c4604005 prfw pldl3strm, p0, \[x0, z0\.d, sxtw #2\]
--.*: c4604005 prfw pldl3strm, p0, \[x0, z0\.d, sxtw #2\]
--.*: c4604006 prfw #6, p0, \[x0, z0\.d, sxtw #2\]
--.*: c4604006 prfw #6, p0, \[x0, z0\.d, sxtw #2\]
--.*: c4604007 prfw #7, p0, \[x0, z0\.d, sxtw #2\]
--.*: c4604007 prfw #7, p0, \[x0, z0\.d, sxtw #2\]
--.*: c4604008 prfw pstl1keep, p0, \[x0, z0\.d, sxtw #2\]
--.*: c4604008 prfw pstl1keep, p0, \[x0, z0\.d, sxtw #2\]
--.*: c4604009 prfw pstl1strm, p0, \[x0, z0\.d, sxtw #2\]
--.*: c4604009 prfw pstl1strm, p0, \[x0, z0\.d, sxtw #2\]
--.*: c460400a prfw pstl2keep, p0, \[x0, z0\.d, sxtw #2\]
--.*: c460400a prfw pstl2keep, p0, \[x0, z0\.d, sxtw #2\]
--.*: c460400b prfw pstl2strm, p0, \[x0, z0\.d, sxtw #2\]
--.*: c460400b prfw pstl2strm, p0, \[x0, z0\.d, sxtw #2\]
--.*: c460400c prfw pstl3keep, p0, \[x0, z0\.d, sxtw #2\]
--.*: c460400c prfw pstl3keep, p0, \[x0, z0\.d, sxtw #2\]
--.*: c460400d prfw pstl3strm, p0, \[x0, z0\.d, sxtw #2\]
--.*: c460400d prfw pstl3strm, p0, \[x0, z0\.d, sxtw #2\]
--.*: c460400e prfw #14, p0, \[x0, z0\.d, sxtw #2\]
--.*: c460400e prfw #14, p0, \[x0, z0\.d, sxtw #2\]
--.*: c460400f prfw #15, p0, \[x0, z0\.d, sxtw #2\]
--.*: c460400f prfw #15, p0, \[x0, z0\.d, sxtw #2\]
--.*: c4604800 prfw pldl1keep, p2, \[x0, z0\.d, sxtw #2\]
--.*: c4604800 prfw pldl1keep, p2, \[x0, z0\.d, sxtw #2\]
--.*: c4605c00 prfw pldl1keep, p7, \[x0, z0\.d, sxtw #2\]
--.*: c4605c00 prfw pldl1keep, p7, \[x0, z0\.d, sxtw #2\]
--.*: c4604060 prfw pldl1keep, p0, \[x3, z0\.d, sxtw #2\]
--.*: c4604060 prfw pldl1keep, p0, \[x3, z0\.d, sxtw #2\]
--.*: c46043e0 prfw pldl1keep, p0, \[sp, z0\.d, sxtw #2\]
--.*: c46043e0 prfw pldl1keep, p0, \[sp, z0\.d, sxtw #2\]
--.*: c4644000 prfw pldl1keep, p0, \[x0, z4\.d, sxtw #2\]
--.*: c4644000 prfw pldl1keep, p0, \[x0, z4\.d, sxtw #2\]
--.*: c47f4000 prfw pldl1keep, p0, \[x0, z31\.d, sxtw #2\]
--.*: c47f4000 prfw pldl1keep, p0, \[x0, z31\.d, sxtw #2\]
--.*: c460c000 prfw pldl1keep, p0, \[x0, z0\.d, lsl #2\]
--.*: c460c000 prfw pldl1keep, p0, \[x0, z0\.d, lsl #2\]
--.*: c460c001 prfw pldl1strm, p0, \[x0, z0\.d, lsl #2\]
--.*: c460c001 prfw pldl1strm, p0, \[x0, z0\.d, lsl #2\]
--.*: c460c002 prfw pldl2keep, p0, \[x0, z0\.d, lsl #2\]
--.*: c460c002 prfw pldl2keep, p0, \[x0, z0\.d, lsl #2\]
--.*: c460c003 prfw pldl2strm, p0, \[x0, z0\.d, lsl #2\]
--.*: c460c003 prfw pldl2strm, p0, \[x0, z0\.d, lsl #2\]
--.*: c460c004 prfw pldl3keep, p0, \[x0, z0\.d, lsl #2\]
--.*: c460c004 prfw pldl3keep, p0, \[x0, z0\.d, lsl #2\]
--.*: c460c005 prfw pldl3strm, p0, \[x0, z0\.d, lsl #2\]
--.*: c460c005 prfw pldl3strm, p0, \[x0, z0\.d, lsl #2\]
--.*: c460c006 prfw #6, p0, \[x0, z0\.d, lsl #2\]
--.*: c460c006 prfw #6, p0, \[x0, z0\.d, lsl #2\]
--.*: c460c007 prfw #7, p0, \[x0, z0\.d, lsl #2\]
--.*: c460c007 prfw #7, p0, \[x0, z0\.d, lsl #2\]
--.*: c460c008 prfw pstl1keep, p0, \[x0, z0\.d, lsl #2\]
--.*: c460c008 prfw pstl1keep, p0, \[x0, z0\.d, lsl #2\]
--.*: c460c009 prfw pstl1strm, p0, \[x0, z0\.d, lsl #2\]
--.*: c460c009 prfw pstl1strm, p0, \[x0, z0\.d, lsl #2\]
--.*: c460c00a prfw pstl2keep, p0, \[x0, z0\.d, lsl #2\]
--.*: c460c00a prfw pstl2keep, p0, \[x0, z0\.d, lsl #2\]
--.*: c460c00b prfw pstl2strm, p0, \[x0, z0\.d, lsl #2\]
--.*: c460c00b prfw pstl2strm, p0, \[x0, z0\.d, lsl #2\]
--.*: c460c00c prfw pstl3keep, p0, \[x0, z0\.d, lsl #2\]
--.*: c460c00c prfw pstl3keep, p0, \[x0, z0\.d, lsl #2\]
--.*: c460c00d prfw pstl3strm, p0, \[x0, z0\.d, lsl #2\]
--.*: c460c00d prfw pstl3strm, p0, \[x0, z0\.d, lsl #2\]
--.*: c460c00e prfw #14, p0, \[x0, z0\.d, lsl #2\]
--.*: c460c00e prfw #14, p0, \[x0, z0\.d, lsl #2\]
--.*: c460c00f prfw #15, p0, \[x0, z0\.d, lsl #2\]
--.*: c460c00f prfw #15, p0, \[x0, z0\.d, lsl #2\]
--.*: c460c800 prfw pldl1keep, p2, \[x0, z0\.d, lsl #2\]
--.*: c460c800 prfw pldl1keep, p2, \[x0, z0\.d, lsl #2\]
--.*: c460dc00 prfw pldl1keep, p7, \[x0, z0\.d, lsl #2\]
--.*: c460dc00 prfw pldl1keep, p7, \[x0, z0\.d, lsl #2\]
--.*: c460c060 prfw pldl1keep, p0, \[x3, z0\.d, lsl #2\]
--.*: c460c060 prfw pldl1keep, p0, \[x3, z0\.d, lsl #2\]
--.*: c460c3e0 prfw pldl1keep, p0, \[sp, z0\.d, lsl #2\]
--.*: c460c3e0 prfw pldl1keep, p0, \[sp, z0\.d, lsl #2\]
--.*: c464c000 prfw pldl1keep, p0, \[x0, z4\.d, lsl #2\]
--.*: c464c000 prfw pldl1keep, p0, \[x0, z4\.d, lsl #2\]
--.*: c47fc000 prfw pldl1keep, p0, \[x0, z31\.d, lsl #2\]
--.*: c47fc000 prfw pldl1keep, p0, \[x0, z31\.d, lsl #2\]
--.*: 8500e000 prfw pldl1keep, p0, \[z0\.s\]
--.*: 8500e000 prfw pldl1keep, p0, \[z0\.s\]
--.*: 8500e000 prfw pldl1keep, p0, \[z0\.s\]
--.*: 8500e001 prfw pldl1strm, p0, \[z0\.s\]
--.*: 8500e001 prfw pldl1strm, p0, \[z0\.s\]
--.*: 8500e001 prfw pldl1strm, p0, \[z0\.s\]
--.*: 8500e002 prfw pldl2keep, p0, \[z0\.s\]
--.*: 8500e002 prfw pldl2keep, p0, \[z0\.s\]
--.*: 8500e002 prfw pldl2keep, p0, \[z0\.s\]
--.*: 8500e003 prfw pldl2strm, p0, \[z0\.s\]
--.*: 8500e003 prfw pldl2strm, p0, \[z0\.s\]
--.*: 8500e003 prfw pldl2strm, p0, \[z0\.s\]
--.*: 8500e004 prfw pldl3keep, p0, \[z0\.s\]
--.*: 8500e004 prfw pldl3keep, p0, \[z0\.s\]
--.*: 8500e004 prfw pldl3keep, p0, \[z0\.s\]
--.*: 8500e005 prfw pldl3strm, p0, \[z0\.s\]
--.*: 8500e005 prfw pldl3strm, p0, \[z0\.s\]
--.*: 8500e005 prfw pldl3strm, p0, \[z0\.s\]
--.*: 8500e006 prfw #6, p0, \[z0\.s\]
--.*: 8500e006 prfw #6, p0, \[z0\.s\]
--.*: 8500e006 prfw #6, p0, \[z0\.s\]
--.*: 8500e007 prfw #7, p0, \[z0\.s\]
--.*: 8500e007 prfw #7, p0, \[z0\.s\]
--.*: 8500e007 prfw #7, p0, \[z0\.s\]
--.*: 8500e008 prfw pstl1keep, p0, \[z0\.s\]
--.*: 8500e008 prfw pstl1keep, p0, \[z0\.s\]
--.*: 8500e008 prfw pstl1keep, p0, \[z0\.s\]
--.*: 8500e009 prfw pstl1strm, p0, \[z0\.s\]
--.*: 8500e009 prfw pstl1strm, p0, \[z0\.s\]
--.*: 8500e009 prfw pstl1strm, p0, \[z0\.s\]
--.*: 8500e00a prfw pstl2keep, p0, \[z0\.s\]
--.*: 8500e00a prfw pstl2keep, p0, \[z0\.s\]
--.*: 8500e00a prfw pstl2keep, p0, \[z0\.s\]
--.*: 8500e00b prfw pstl2strm, p0, \[z0\.s\]
--.*: 8500e00b prfw pstl2strm, p0, \[z0\.s\]
--.*: 8500e00b prfw pstl2strm, p0, \[z0\.s\]
--.*: 8500e00c prfw pstl3keep, p0, \[z0\.s\]
--.*: 8500e00c prfw pstl3keep, p0, \[z0\.s\]
--.*: 8500e00c prfw pstl3keep, p0, \[z0\.s\]
--.*: 8500e00d prfw pstl3strm, p0, \[z0\.s\]
--.*: 8500e00d prfw pstl3strm, p0, \[z0\.s\]
--.*: 8500e00d prfw pstl3strm, p0, \[z0\.s\]
--.*: 8500e00e prfw #14, p0, \[z0\.s\]
--.*: 8500e00e prfw #14, p0, \[z0\.s\]
--.*: 8500e00e prfw #14, p0, \[z0\.s\]
--.*: 8500e00f prfw #15, p0, \[z0\.s\]
--.*: 8500e00f prfw #15, p0, \[z0\.s\]
--.*: 8500e00f prfw #15, p0, \[z0\.s\]
--.*: 8500e800 prfw pldl1keep, p2, \[z0\.s\]
--.*: 8500e800 prfw pldl1keep, p2, \[z0\.s\]
--.*: 8500e800 prfw pldl1keep, p2, \[z0\.s\]
--.*: 8500fc00 prfw pldl1keep, p7, \[z0\.s\]
--.*: 8500fc00 prfw pldl1keep, p7, \[z0\.s\]
--.*: 8500fc00 prfw pldl1keep, p7, \[z0\.s\]
--.*: 8500e060 prfw pldl1keep, p0, \[z3\.s\]
--.*: 8500e060 prfw pldl1keep, p0, \[z3\.s\]
--.*: 8500e060 prfw pldl1keep, p0, \[z3\.s\]
--.*: 8500e3e0 prfw pldl1keep, p0, \[z31\.s\]
--.*: 8500e3e0 prfw pldl1keep, p0, \[z31\.s\]
--.*: 8500e3e0 prfw pldl1keep, p0, \[z31\.s\]
--.*: 850fe000 prfw pldl1keep, p0, \[z0\.s, #60\]
--.*: 850fe000 prfw pldl1keep, p0, \[z0\.s, #60\]
--.*: 8510e000 prfw pldl1keep, p0, \[z0\.s, #64\]
--.*: 8510e000 prfw pldl1keep, p0, \[z0\.s, #64\]
--.*: 8511e000 prfw pldl1keep, p0, \[z0\.s, #68\]
--.*: 8511e000 prfw pldl1keep, p0, \[z0\.s, #68\]
--.*: 851fe000 prfw pldl1keep, p0, \[z0\.s, #124\]
--.*: 851fe000 prfw pldl1keep, p0, \[z0\.s, #124\]
--.*: 85c04000 prfw pldl1keep, p0, \[x0\]
--.*: 85c04000 prfw pldl1keep, p0, \[x0\]
--.*: 85c04000 prfw pldl1keep, p0, \[x0\]
--.*: 85c04000 prfw pldl1keep, p0, \[x0\]
--.*: 85c04001 prfw pldl1strm, p0, \[x0\]
--.*: 85c04001 prfw pldl1strm, p0, \[x0\]
--.*: 85c04001 prfw pldl1strm, p0, \[x0\]
--.*: 85c04001 prfw pldl1strm, p0, \[x0\]
--.*: 85c04002 prfw pldl2keep, p0, \[x0\]
--.*: 85c04002 prfw pldl2keep, p0, \[x0\]
--.*: 85c04002 prfw pldl2keep, p0, \[x0\]
--.*: 85c04002 prfw pldl2keep, p0, \[x0\]
--.*: 85c04003 prfw pldl2strm, p0, \[x0\]
--.*: 85c04003 prfw pldl2strm, p0, \[x0\]
--.*: 85c04003 prfw pldl2strm, p0, \[x0\]
--.*: 85c04003 prfw pldl2strm, p0, \[x0\]
--.*: 85c04004 prfw pldl3keep, p0, \[x0\]
--.*: 85c04004 prfw pldl3keep, p0, \[x0\]
--.*: 85c04004 prfw pldl3keep, p0, \[x0\]
--.*: 85c04004 prfw pldl3keep, p0, \[x0\]
--.*: 85c04005 prfw pldl3strm, p0, \[x0\]
--.*: 85c04005 prfw pldl3strm, p0, \[x0\]
--.*: 85c04005 prfw pldl3strm, p0, \[x0\]
--.*: 85c04005 prfw pldl3strm, p0, \[x0\]
--.*: 85c04006 prfw #6, p0, \[x0\]
--.*: 85c04006 prfw #6, p0, \[x0\]
--.*: 85c04006 prfw #6, p0, \[x0\]
--.*: 85c04006 prfw #6, p0, \[x0\]
--.*: 85c04007 prfw #7, p0, \[x0\]
--.*: 85c04007 prfw #7, p0, \[x0\]
--.*: 85c04007 prfw #7, p0, \[x0\]
--.*: 85c04007 prfw #7, p0, \[x0\]
--.*: 85c04008 prfw pstl1keep, p0, \[x0\]
--.*: 85c04008 prfw pstl1keep, p0, \[x0\]
--.*: 85c04008 prfw pstl1keep, p0, \[x0\]
--.*: 85c04008 prfw pstl1keep, p0, \[x0\]
--.*: 85c04009 prfw pstl1strm, p0, \[x0\]
--.*: 85c04009 prfw pstl1strm, p0, \[x0\]
--.*: 85c04009 prfw pstl1strm, p0, \[x0\]
--.*: 85c04009 prfw pstl1strm, p0, \[x0\]
--.*: 85c0400a prfw pstl2keep, p0, \[x0\]
--.*: 85c0400a prfw pstl2keep, p0, \[x0\]
--.*: 85c0400a prfw pstl2keep, p0, \[x0\]
--.*: 85c0400a prfw pstl2keep, p0, \[x0\]
--.*: 85c0400b prfw pstl2strm, p0, \[x0\]
--.*: 85c0400b prfw pstl2strm, p0, \[x0\]
--.*: 85c0400b prfw pstl2strm, p0, \[x0\]
--.*: 85c0400b prfw pstl2strm, p0, \[x0\]
--.*: 85c0400c prfw pstl3keep, p0, \[x0\]
--.*: 85c0400c prfw pstl3keep, p0, \[x0\]
--.*: 85c0400c prfw pstl3keep, p0, \[x0\]
--.*: 85c0400c prfw pstl3keep, p0, \[x0\]
--.*: 85c0400d prfw pstl3strm, p0, \[x0\]
--.*: 85c0400d prfw pstl3strm, p0, \[x0\]
--.*: 85c0400d prfw pstl3strm, p0, \[x0\]
--.*: 85c0400d prfw pstl3strm, p0, \[x0\]
--.*: 85c0400e prfw #14, p0, \[x0\]
--.*: 85c0400e prfw #14, p0, \[x0\]
--.*: 85c0400e prfw #14, p0, \[x0\]
--.*: 85c0400e prfw #14, p0, \[x0\]
--.*: 85c0400f prfw #15, p0, \[x0\]
--.*: 85c0400f prfw #15, p0, \[x0\]
--.*: 85c0400f prfw #15, p0, \[x0\]
--.*: 85c0400f prfw #15, p0, \[x0\]
--.*: 85c04800 prfw pldl1keep, p2, \[x0\]
--.*: 85c04800 prfw pldl1keep, p2, \[x0\]
--.*: 85c04800 prfw pldl1keep, p2, \[x0\]
--.*: 85c04800 prfw pldl1keep, p2, \[x0\]
--.*: 85c05c00 prfw pldl1keep, p7, \[x0\]
--.*: 85c05c00 prfw pldl1keep, p7, \[x0\]
--.*: 85c05c00 prfw pldl1keep, p7, \[x0\]
--.*: 85c05c00 prfw pldl1keep, p7, \[x0\]
--.*: 85c04060 prfw pldl1keep, p0, \[x3\]
--.*: 85c04060 prfw pldl1keep, p0, \[x3\]
--.*: 85c04060 prfw pldl1keep, p0, \[x3\]
--.*: 85c04060 prfw pldl1keep, p0, \[x3\]
--.*: 85c043e0 prfw pldl1keep, p0, \[sp\]
--.*: 85c043e0 prfw pldl1keep, p0, \[sp\]
--.*: 85c043e0 prfw pldl1keep, p0, \[sp\]
--.*: 85c043e0 prfw pldl1keep, p0, \[sp\]
--.*: 85df4000 prfw pldl1keep, p0, \[x0, #31, mul vl\]
--.*: 85df4000 prfw pldl1keep, p0, \[x0, #31, mul vl\]
--.*: 85e04000 prfw pldl1keep, p0, \[x0, #-32, mul vl\]
--.*: 85e04000 prfw pldl1keep, p0, \[x0, #-32, mul vl\]
--.*: 85e14000 prfw pldl1keep, p0, \[x0, #-31, mul vl\]
--.*: 85e14000 prfw pldl1keep, p0, \[x0, #-31, mul vl\]
--.*: 85ff4000 prfw pldl1keep, p0, \[x0, #-1, mul vl\]
--.*: 85ff4000 prfw pldl1keep, p0, \[x0, #-1, mul vl\]
--.*: c500e000 prfw pldl1keep, p0, \[z0\.d\]
--.*: c500e000 prfw pldl1keep, p0, \[z0\.d\]
--.*: c500e000 prfw pldl1keep, p0, \[z0\.d\]
--.*: c500e001 prfw pldl1strm, p0, \[z0\.d\]
--.*: c500e001 prfw pldl1strm, p0, \[z0\.d\]
--.*: c500e001 prfw pldl1strm, p0, \[z0\.d\]
--.*: c500e002 prfw pldl2keep, p0, \[z0\.d\]
--.*: c500e002 prfw pldl2keep, p0, \[z0\.d\]
--.*: c500e002 prfw pldl2keep, p0, \[z0\.d\]
--.*: c500e003 prfw pldl2strm, p0, \[z0\.d\]
--.*: c500e003 prfw pldl2strm, p0, \[z0\.d\]
--.*: c500e003 prfw pldl2strm, p0, \[z0\.d\]
--.*: c500e004 prfw pldl3keep, p0, \[z0\.d\]
--.*: c500e004 prfw pldl3keep, p0, \[z0\.d\]
--.*: c500e004 prfw pldl3keep, p0, \[z0\.d\]
--.*: c500e005 prfw pldl3strm, p0, \[z0\.d\]
--.*: c500e005 prfw pldl3strm, p0, \[z0\.d\]
--.*: c500e005 prfw pldl3strm, p0, \[z0\.d\]
--.*: c500e006 prfw #6, p0, \[z0\.d\]
--.*: c500e006 prfw #6, p0, \[z0\.d\]
--.*: c500e006 prfw #6, p0, \[z0\.d\]
--.*: c500e007 prfw #7, p0, \[z0\.d\]
--.*: c500e007 prfw #7, p0, \[z0\.d\]
--.*: c500e007 prfw #7, p0, \[z0\.d\]
--.*: c500e008 prfw pstl1keep, p0, \[z0\.d\]
--.*: c500e008 prfw pstl1keep, p0, \[z0\.d\]
--.*: c500e008 prfw pstl1keep, p0, \[z0\.d\]
--.*: c500e009 prfw pstl1strm, p0, \[z0\.d\]
--.*: c500e009 prfw pstl1strm, p0, \[z0\.d\]
--.*: c500e009 prfw pstl1strm, p0, \[z0\.d\]
--.*: c500e00a prfw pstl2keep, p0, \[z0\.d\]
--.*: c500e00a prfw pstl2keep, p0, \[z0\.d\]
--.*: c500e00a prfw pstl2keep, p0, \[z0\.d\]
--.*: c500e00b prfw pstl2strm, p0, \[z0\.d\]
--.*: c500e00b prfw pstl2strm, p0, \[z0\.d\]
--.*: c500e00b prfw pstl2strm, p0, \[z0\.d\]
--.*: c500e00c prfw pstl3keep, p0, \[z0\.d\]
--.*: c500e00c prfw pstl3keep, p0, \[z0\.d\]
--.*: c500e00c prfw pstl3keep, p0, \[z0\.d\]
--.*: c500e00d prfw pstl3strm, p0, \[z0\.d\]
--.*: c500e00d prfw pstl3strm, p0, \[z0\.d\]
--.*: c500e00d prfw pstl3strm, p0, \[z0\.d\]
--.*: c500e00e prfw #14, p0, \[z0\.d\]
--.*: c500e00e prfw #14, p0, \[z0\.d\]
--.*: c500e00e prfw #14, p0, \[z0\.d\]
--.*: c500e00f prfw #15, p0, \[z0\.d\]
--.*: c500e00f prfw #15, p0, \[z0\.d\]
--.*: c500e00f prfw #15, p0, \[z0\.d\]
--.*: c500e800 prfw pldl1keep, p2, \[z0\.d\]
--.*: c500e800 prfw pldl1keep, p2, \[z0\.d\]
--.*: c500e800 prfw pldl1keep, p2, \[z0\.d\]
--.*: c500fc00 prfw pldl1keep, p7, \[z0\.d\]
--.*: c500fc00 prfw pldl1keep, p7, \[z0\.d\]
--.*: c500fc00 prfw pldl1keep, p7, \[z0\.d\]
--.*: c500e060 prfw pldl1keep, p0, \[z3\.d\]
--.*: c500e060 prfw pldl1keep, p0, \[z3\.d\]
--.*: c500e060 prfw pldl1keep, p0, \[z3\.d\]
--.*: c500e3e0 prfw pldl1keep, p0, \[z31\.d\]
--.*: c500e3e0 prfw pldl1keep, p0, \[z31\.d\]
--.*: c500e3e0 prfw pldl1keep, p0, \[z31\.d\]
--.*: c50fe000 prfw pldl1keep, p0, \[z0\.d, #60\]
--.*: c50fe000 prfw pldl1keep, p0, \[z0\.d, #60\]
--.*: c510e000 prfw pldl1keep, p0, \[z0\.d, #64\]
--.*: c510e000 prfw pldl1keep, p0, \[z0\.d, #64\]
--.*: c511e000 prfw pldl1keep, p0, \[z0\.d, #68\]
--.*: c511e000 prfw pldl1keep, p0, \[z0\.d, #68\]
--.*: c51fe000 prfw pldl1keep, p0, \[z0\.d, #124\]
--.*: c51fe000 prfw pldl1keep, p0, \[z0\.d, #124\]
--.*: 2550c000 ptest p0, p0\.b
--.*: 2550c000 ptest p0, p0\.b
--.*: 2550c400 ptest p1, p0\.b
--.*: 2550c400 ptest p1, p0\.b
--.*: 2550fc00 ptest p15, p0\.b
--.*: 2550fc00 ptest p15, p0\.b
--.*: 2550c040 ptest p0, p2\.b
--.*: 2550c040 ptest p0, p2\.b
--.*: 2550c1e0 ptest p0, p15\.b
--.*: 2550c1e0 ptest p0, p15\.b
--.*: 2518e000 ptrue p0\.b, pow2
--.*: 2518e000 ptrue p0\.b, pow2
--.*: 2518e001 ptrue p1\.b, pow2
--.*: 2518e001 ptrue p1\.b, pow2
--.*: 2518e00f ptrue p15\.b, pow2
--.*: 2518e00f ptrue p15\.b, pow2
--.*: 2518e020 ptrue p0\.b, vl1
--.*: 2518e020 ptrue p0\.b, vl1
--.*: 2518e040 ptrue p0\.b, vl2
--.*: 2518e040 ptrue p0\.b, vl2
--.*: 2518e060 ptrue p0\.b, vl3
--.*: 2518e060 ptrue p0\.b, vl3
--.*: 2518e080 ptrue p0\.b, vl4
--.*: 2518e080 ptrue p0\.b, vl4
--.*: 2518e0a0 ptrue p0\.b, vl5
--.*: 2518e0a0 ptrue p0\.b, vl5
--.*: 2518e0c0 ptrue p0\.b, vl6
--.*: 2518e0c0 ptrue p0\.b, vl6
--.*: 2518e0e0 ptrue p0\.b, vl7
--.*: 2518e0e0 ptrue p0\.b, vl7
--.*: 2518e100 ptrue p0\.b, vl8
--.*: 2518e100 ptrue p0\.b, vl8
--.*: 2518e120 ptrue p0\.b, vl16
--.*: 2518e120 ptrue p0\.b, vl16
--.*: 2518e140 ptrue p0\.b, vl32
--.*: 2518e140 ptrue p0\.b, vl32
--.*: 2518e160 ptrue p0\.b, vl64
--.*: 2518e160 ptrue p0\.b, vl64
--.*: 2518e180 ptrue p0\.b, vl128
--.*: 2518e180 ptrue p0\.b, vl128
--.*: 2518e1a0 ptrue p0\.b, vl256
--.*: 2518e1a0 ptrue p0\.b, vl256
--.*: 2518e1c0 ptrue p0\.b, #14
--.*: 2518e1c0 ptrue p0\.b, #14
--.*: 2518e1e0 ptrue p0\.b, #15
--.*: 2518e1e0 ptrue p0\.b, #15
--.*: 2518e200 ptrue p0\.b, #16
--.*: 2518e200 ptrue p0\.b, #16
--.*: 2518e220 ptrue p0\.b, #17
--.*: 2518e220 ptrue p0\.b, #17
--.*: 2518e240 ptrue p0\.b, #18
--.*: 2518e240 ptrue p0\.b, #18
--.*: 2518e260 ptrue p0\.b, #19
--.*: 2518e260 ptrue p0\.b, #19
--.*: 2518e280 ptrue p0\.b, #20
--.*: 2518e280 ptrue p0\.b, #20
--.*: 2518e2a0 ptrue p0\.b, #21
--.*: 2518e2a0 ptrue p0\.b, #21
--.*: 2518e2c0 ptrue p0\.b, #22
--.*: 2518e2c0 ptrue p0\.b, #22
--.*: 2518e2e0 ptrue p0\.b, #23
--.*: 2518e2e0 ptrue p0\.b, #23
--.*: 2518e300 ptrue p0\.b, #24
--.*: 2518e300 ptrue p0\.b, #24
--.*: 2518e320 ptrue p0\.b, #25
--.*: 2518e320 ptrue p0\.b, #25
--.*: 2518e340 ptrue p0\.b, #26
--.*: 2518e340 ptrue p0\.b, #26
--.*: 2518e360 ptrue p0\.b, #27
--.*: 2518e360 ptrue p0\.b, #27
--.*: 2518e380 ptrue p0\.b, #28
--.*: 2518e380 ptrue p0\.b, #28
--.*: 2518e3a0 ptrue p0\.b, mul4
--.*: 2518e3a0 ptrue p0\.b, mul4
--.*: 2518e3c0 ptrue p0\.b, mul3
--.*: 2518e3c0 ptrue p0\.b, mul3
--.*: 2518e3e0 ptrue p0\.b
--.*: 2518e3e0 ptrue p0\.b
--.*: 2518e3e0 ptrue p0\.b
--.*: 2558e000 ptrue p0\.h, pow2
--.*: 2558e000 ptrue p0\.h, pow2
--.*: 2558e001 ptrue p1\.h, pow2
--.*: 2558e001 ptrue p1\.h, pow2
--.*: 2558e00f ptrue p15\.h, pow2
--.*: 2558e00f ptrue p15\.h, pow2
--.*: 2558e020 ptrue p0\.h, vl1
--.*: 2558e020 ptrue p0\.h, vl1
--.*: 2558e040 ptrue p0\.h, vl2
--.*: 2558e040 ptrue p0\.h, vl2
--.*: 2558e060 ptrue p0\.h, vl3
--.*: 2558e060 ptrue p0\.h, vl3
--.*: 2558e080 ptrue p0\.h, vl4
--.*: 2558e080 ptrue p0\.h, vl4
--.*: 2558e0a0 ptrue p0\.h, vl5
--.*: 2558e0a0 ptrue p0\.h, vl5
--.*: 2558e0c0 ptrue p0\.h, vl6
--.*: 2558e0c0 ptrue p0\.h, vl6
--.*: 2558e0e0 ptrue p0\.h, vl7
--.*: 2558e0e0 ptrue p0\.h, vl7
--.*: 2558e100 ptrue p0\.h, vl8
--.*: 2558e100 ptrue p0\.h, vl8
--.*: 2558e120 ptrue p0\.h, vl16
--.*: 2558e120 ptrue p0\.h, vl16
--.*: 2558e140 ptrue p0\.h, vl32
--.*: 2558e140 ptrue p0\.h, vl32
--.*: 2558e160 ptrue p0\.h, vl64
--.*: 2558e160 ptrue p0\.h, vl64
--.*: 2558e180 ptrue p0\.h, vl128
--.*: 2558e180 ptrue p0\.h, vl128
--.*: 2558e1a0 ptrue p0\.h, vl256
--.*: 2558e1a0 ptrue p0\.h, vl256
--.*: 2558e1c0 ptrue p0\.h, #14
--.*: 2558e1c0 ptrue p0\.h, #14
--.*: 2558e1e0 ptrue p0\.h, #15
--.*: 2558e1e0 ptrue p0\.h, #15
--.*: 2558e200 ptrue p0\.h, #16
--.*: 2558e200 ptrue p0\.h, #16
--.*: 2558e220 ptrue p0\.h, #17
--.*: 2558e220 ptrue p0\.h, #17
--.*: 2558e240 ptrue p0\.h, #18
--.*: 2558e240 ptrue p0\.h, #18
--.*: 2558e260 ptrue p0\.h, #19
--.*: 2558e260 ptrue p0\.h, #19
--.*: 2558e280 ptrue p0\.h, #20
--.*: 2558e280 ptrue p0\.h, #20
--.*: 2558e2a0 ptrue p0\.h, #21
--.*: 2558e2a0 ptrue p0\.h, #21
--.*: 2558e2c0 ptrue p0\.h, #22
--.*: 2558e2c0 ptrue p0\.h, #22
--.*: 2558e2e0 ptrue p0\.h, #23
--.*: 2558e2e0 ptrue p0\.h, #23
--.*: 2558e300 ptrue p0\.h, #24
--.*: 2558e300 ptrue p0\.h, #24
--.*: 2558e320 ptrue p0\.h, #25
--.*: 2558e320 ptrue p0\.h, #25
--.*: 2558e340 ptrue p0\.h, #26
--.*: 2558e340 ptrue p0\.h, #26
--.*: 2558e360 ptrue p0\.h, #27
--.*: 2558e360 ptrue p0\.h, #27
--.*: 2558e380 ptrue p0\.h, #28
--.*: 2558e380 ptrue p0\.h, #28
--.*: 2558e3a0 ptrue p0\.h, mul4
--.*: 2558e3a0 ptrue p0\.h, mul4
--.*: 2558e3c0 ptrue p0\.h, mul3
--.*: 2558e3c0 ptrue p0\.h, mul3
--.*: 2558e3e0 ptrue p0\.h
--.*: 2558e3e0 ptrue p0\.h
--.*: 2558e3e0 ptrue p0\.h
--.*: 2598e000 ptrue p0\.s, pow2
--.*: 2598e000 ptrue p0\.s, pow2
--.*: 2598e001 ptrue p1\.s, pow2
--.*: 2598e001 ptrue p1\.s, pow2
--.*: 2598e00f ptrue p15\.s, pow2
--.*: 2598e00f ptrue p15\.s, pow2
--.*: 2598e020 ptrue p0\.s, vl1
--.*: 2598e020 ptrue p0\.s, vl1
--.*: 2598e040 ptrue p0\.s, vl2
--.*: 2598e040 ptrue p0\.s, vl2
--.*: 2598e060 ptrue p0\.s, vl3
--.*: 2598e060 ptrue p0\.s, vl3
--.*: 2598e080 ptrue p0\.s, vl4
--.*: 2598e080 ptrue p0\.s, vl4
--.*: 2598e0a0 ptrue p0\.s, vl5
--.*: 2598e0a0 ptrue p0\.s, vl5
--.*: 2598e0c0 ptrue p0\.s, vl6
--.*: 2598e0c0 ptrue p0\.s, vl6
--.*: 2598e0e0 ptrue p0\.s, vl7
--.*: 2598e0e0 ptrue p0\.s, vl7
--.*: 2598e100 ptrue p0\.s, vl8
--.*: 2598e100 ptrue p0\.s, vl8
--.*: 2598e120 ptrue p0\.s, vl16
--.*: 2598e120 ptrue p0\.s, vl16
--.*: 2598e140 ptrue p0\.s, vl32
--.*: 2598e140 ptrue p0\.s, vl32
--.*: 2598e160 ptrue p0\.s, vl64
--.*: 2598e160 ptrue p0\.s, vl64
--.*: 2598e180 ptrue p0\.s, vl128
--.*: 2598e180 ptrue p0\.s, vl128
--.*: 2598e1a0 ptrue p0\.s, vl256
--.*: 2598e1a0 ptrue p0\.s, vl256
--.*: 2598e1c0 ptrue p0\.s, #14
--.*: 2598e1c0 ptrue p0\.s, #14
--.*: 2598e1e0 ptrue p0\.s, #15
--.*: 2598e1e0 ptrue p0\.s, #15
--.*: 2598e200 ptrue p0\.s, #16
--.*: 2598e200 ptrue p0\.s, #16
--.*: 2598e220 ptrue p0\.s, #17
--.*: 2598e220 ptrue p0\.s, #17
--.*: 2598e240 ptrue p0\.s, #18
--.*: 2598e240 ptrue p0\.s, #18
--.*: 2598e260 ptrue p0\.s, #19
--.*: 2598e260 ptrue p0\.s, #19
--.*: 2598e280 ptrue p0\.s, #20
--.*: 2598e280 ptrue p0\.s, #20
--.*: 2598e2a0 ptrue p0\.s, #21
--.*: 2598e2a0 ptrue p0\.s, #21
--.*: 2598e2c0 ptrue p0\.s, #22
--.*: 2598e2c0 ptrue p0\.s, #22
--.*: 2598e2e0 ptrue p0\.s, #23
--.*: 2598e2e0 ptrue p0\.s, #23
--.*: 2598e300 ptrue p0\.s, #24
--.*: 2598e300 ptrue p0\.s, #24
--.*: 2598e320 ptrue p0\.s, #25
--.*: 2598e320 ptrue p0\.s, #25
--.*: 2598e340 ptrue p0\.s, #26
--.*: 2598e340 ptrue p0\.s, #26
--.*: 2598e360 ptrue p0\.s, #27
--.*: 2598e360 ptrue p0\.s, #27
--.*: 2598e380 ptrue p0\.s, #28
--.*: 2598e380 ptrue p0\.s, #28
--.*: 2598e3a0 ptrue p0\.s, mul4
--.*: 2598e3a0 ptrue p0\.s, mul4
--.*: 2598e3c0 ptrue p0\.s, mul3
--.*: 2598e3c0 ptrue p0\.s, mul3
--.*: 2598e3e0 ptrue p0\.s
--.*: 2598e3e0 ptrue p0\.s
--.*: 2598e3e0 ptrue p0\.s
--.*: 25d8e000 ptrue p0\.d, pow2
--.*: 25d8e000 ptrue p0\.d, pow2
--.*: 25d8e001 ptrue p1\.d, pow2
--.*: 25d8e001 ptrue p1\.d, pow2
--.*: 25d8e00f ptrue p15\.d, pow2
--.*: 25d8e00f ptrue p15\.d, pow2
--.*: 25d8e020 ptrue p0\.d, vl1
--.*: 25d8e020 ptrue p0\.d, vl1
--.*: 25d8e040 ptrue p0\.d, vl2
--.*: 25d8e040 ptrue p0\.d, vl2
--.*: 25d8e060 ptrue p0\.d, vl3
--.*: 25d8e060 ptrue p0\.d, vl3
--.*: 25d8e080 ptrue p0\.d, vl4
--.*: 25d8e080 ptrue p0\.d, vl4
--.*: 25d8e0a0 ptrue p0\.d, vl5
--.*: 25d8e0a0 ptrue p0\.d, vl5
--.*: 25d8e0c0 ptrue p0\.d, vl6
--.*: 25d8e0c0 ptrue p0\.d, vl6
--.*: 25d8e0e0 ptrue p0\.d, vl7
--.*: 25d8e0e0 ptrue p0\.d, vl7
--.*: 25d8e100 ptrue p0\.d, vl8
--.*: 25d8e100 ptrue p0\.d, vl8
--.*: 25d8e120 ptrue p0\.d, vl16
--.*: 25d8e120 ptrue p0\.d, vl16
--.*: 25d8e140 ptrue p0\.d, vl32
--.*: 25d8e140 ptrue p0\.d, vl32
--.*: 25d8e160 ptrue p0\.d, vl64
--.*: 25d8e160 ptrue p0\.d, vl64
--.*: 25d8e180 ptrue p0\.d, vl128
--.*: 25d8e180 ptrue p0\.d, vl128
--.*: 25d8e1a0 ptrue p0\.d, vl256
--.*: 25d8e1a0 ptrue p0\.d, vl256
--.*: 25d8e1c0 ptrue p0\.d, #14
--.*: 25d8e1c0 ptrue p0\.d, #14
--.*: 25d8e1e0 ptrue p0\.d, #15
--.*: 25d8e1e0 ptrue p0\.d, #15
--.*: 25d8e200 ptrue p0\.d, #16
--.*: 25d8e200 ptrue p0\.d, #16
--.*: 25d8e220 ptrue p0\.d, #17
--.*: 25d8e220 ptrue p0\.d, #17
--.*: 25d8e240 ptrue p0\.d, #18
--.*: 25d8e240 ptrue p0\.d, #18
--.*: 25d8e260 ptrue p0\.d, #19
--.*: 25d8e260 ptrue p0\.d, #19
--.*: 25d8e280 ptrue p0\.d, #20
--.*: 25d8e280 ptrue p0\.d, #20
--.*: 25d8e2a0 ptrue p0\.d, #21
--.*: 25d8e2a0 ptrue p0\.d, #21
--.*: 25d8e2c0 ptrue p0\.d, #22
--.*: 25d8e2c0 ptrue p0\.d, #22
--.*: 25d8e2e0 ptrue p0\.d, #23
--.*: 25d8e2e0 ptrue p0\.d, #23
--.*: 25d8e300 ptrue p0\.d, #24
--.*: 25d8e300 ptrue p0\.d, #24
--.*: 25d8e320 ptrue p0\.d, #25
--.*: 25d8e320 ptrue p0\.d, #25
--.*: 25d8e340 ptrue p0\.d, #26
--.*: 25d8e340 ptrue p0\.d, #26
--.*: 25d8e360 ptrue p0\.d, #27
--.*: 25d8e360 ptrue p0\.d, #27
--.*: 25d8e380 ptrue p0\.d, #28
--.*: 25d8e380 ptrue p0\.d, #28
--.*: 25d8e3a0 ptrue p0\.d, mul4
--.*: 25d8e3a0 ptrue p0\.d, mul4
--.*: 25d8e3c0 ptrue p0\.d, mul3
--.*: 25d8e3c0 ptrue p0\.d, mul3
--.*: 25d8e3e0 ptrue p0\.d
--.*: 25d8e3e0 ptrue p0\.d
--.*: 25d8e3e0 ptrue p0\.d
--.*: 2519e000 ptrues p0\.b, pow2
--.*: 2519e000 ptrues p0\.b, pow2
--.*: 2519e001 ptrues p1\.b, pow2
--.*: 2519e001 ptrues p1\.b, pow2
--.*: 2519e00f ptrues p15\.b, pow2
--.*: 2519e00f ptrues p15\.b, pow2
--.*: 2519e020 ptrues p0\.b, vl1
--.*: 2519e020 ptrues p0\.b, vl1
--.*: 2519e040 ptrues p0\.b, vl2
--.*: 2519e040 ptrues p0\.b, vl2
--.*: 2519e060 ptrues p0\.b, vl3
--.*: 2519e060 ptrues p0\.b, vl3
--.*: 2519e080 ptrues p0\.b, vl4
--.*: 2519e080 ptrues p0\.b, vl4
--.*: 2519e0a0 ptrues p0\.b, vl5
--.*: 2519e0a0 ptrues p0\.b, vl5
--.*: 2519e0c0 ptrues p0\.b, vl6
--.*: 2519e0c0 ptrues p0\.b, vl6
--.*: 2519e0e0 ptrues p0\.b, vl7
--.*: 2519e0e0 ptrues p0\.b, vl7
--.*: 2519e100 ptrues p0\.b, vl8
--.*: 2519e100 ptrues p0\.b, vl8
--.*: 2519e120 ptrues p0\.b, vl16
--.*: 2519e120 ptrues p0\.b, vl16
--.*: 2519e140 ptrues p0\.b, vl32
--.*: 2519e140 ptrues p0\.b, vl32
--.*: 2519e160 ptrues p0\.b, vl64
--.*: 2519e160 ptrues p0\.b, vl64
--.*: 2519e180 ptrues p0\.b, vl128
--.*: 2519e180 ptrues p0\.b, vl128
--.*: 2519e1a0 ptrues p0\.b, vl256
--.*: 2519e1a0 ptrues p0\.b, vl256
--.*: 2519e1c0 ptrues p0\.b, #14
--.*: 2519e1c0 ptrues p0\.b, #14
--.*: 2519e1e0 ptrues p0\.b, #15
--.*: 2519e1e0 ptrues p0\.b, #15
--.*: 2519e200 ptrues p0\.b, #16
--.*: 2519e200 ptrues p0\.b, #16
--.*: 2519e220 ptrues p0\.b, #17
--.*: 2519e220 ptrues p0\.b, #17
--.*: 2519e240 ptrues p0\.b, #18
--.*: 2519e240 ptrues p0\.b, #18
--.*: 2519e260 ptrues p0\.b, #19
--.*: 2519e260 ptrues p0\.b, #19
--.*: 2519e280 ptrues p0\.b, #20
--.*: 2519e280 ptrues p0\.b, #20
--.*: 2519e2a0 ptrues p0\.b, #21
--.*: 2519e2a0 ptrues p0\.b, #21
--.*: 2519e2c0 ptrues p0\.b, #22
--.*: 2519e2c0 ptrues p0\.b, #22
--.*: 2519e2e0 ptrues p0\.b, #23
--.*: 2519e2e0 ptrues p0\.b, #23
--.*: 2519e300 ptrues p0\.b, #24
--.*: 2519e300 ptrues p0\.b, #24
--.*: 2519e320 ptrues p0\.b, #25
--.*: 2519e320 ptrues p0\.b, #25
--.*: 2519e340 ptrues p0\.b, #26
--.*: 2519e340 ptrues p0\.b, #26
--.*: 2519e360 ptrues p0\.b, #27
--.*: 2519e360 ptrues p0\.b, #27
--.*: 2519e380 ptrues p0\.b, #28
--.*: 2519e380 ptrues p0\.b, #28
--.*: 2519e3a0 ptrues p0\.b, mul4
--.*: 2519e3a0 ptrues p0\.b, mul4
--.*: 2519e3c0 ptrues p0\.b, mul3
--.*: 2519e3c0 ptrues p0\.b, mul3
--.*: 2519e3e0 ptrues p0\.b
--.*: 2519e3e0 ptrues p0\.b
--.*: 2519e3e0 ptrues p0\.b
--.*: 2559e000 ptrues p0\.h, pow2
--.*: 2559e000 ptrues p0\.h, pow2
--.*: 2559e001 ptrues p1\.h, pow2
--.*: 2559e001 ptrues p1\.h, pow2
--.*: 2559e00f ptrues p15\.h, pow2
--.*: 2559e00f ptrues p15\.h, pow2
--.*: 2559e020 ptrues p0\.h, vl1
--.*: 2559e020 ptrues p0\.h, vl1
--.*: 2559e040 ptrues p0\.h, vl2
--.*: 2559e040 ptrues p0\.h, vl2
--.*: 2559e060 ptrues p0\.h, vl3
--.*: 2559e060 ptrues p0\.h, vl3
--.*: 2559e080 ptrues p0\.h, vl4
--.*: 2559e080 ptrues p0\.h, vl4
--.*: 2559e0a0 ptrues p0\.h, vl5
--.*: 2559e0a0 ptrues p0\.h, vl5
--.*: 2559e0c0 ptrues p0\.h, vl6
--.*: 2559e0c0 ptrues p0\.h, vl6
--.*: 2559e0e0 ptrues p0\.h, vl7
--.*: 2559e0e0 ptrues p0\.h, vl7
--.*: 2559e100 ptrues p0\.h, vl8
--.*: 2559e100 ptrues p0\.h, vl8
--.*: 2559e120 ptrues p0\.h, vl16
--.*: 2559e120 ptrues p0\.h, vl16
--.*: 2559e140 ptrues p0\.h, vl32
--.*: 2559e140 ptrues p0\.h, vl32
--.*: 2559e160 ptrues p0\.h, vl64
--.*: 2559e160 ptrues p0\.h, vl64
--.*: 2559e180 ptrues p0\.h, vl128
--.*: 2559e180 ptrues p0\.h, vl128
--.*: 2559e1a0 ptrues p0\.h, vl256
--.*: 2559e1a0 ptrues p0\.h, vl256
--.*: 2559e1c0 ptrues p0\.h, #14
--.*: 2559e1c0 ptrues p0\.h, #14
--.*: 2559e1e0 ptrues p0\.h, #15
--.*: 2559e1e0 ptrues p0\.h, #15
--.*: 2559e200 ptrues p0\.h, #16
--.*: 2559e200 ptrues p0\.h, #16
--.*: 2559e220 ptrues p0\.h, #17
--.*: 2559e220 ptrues p0\.h, #17
--.*: 2559e240 ptrues p0\.h, #18
--.*: 2559e240 ptrues p0\.h, #18
--.*: 2559e260 ptrues p0\.h, #19
--.*: 2559e260 ptrues p0\.h, #19
--.*: 2559e280 ptrues p0\.h, #20
--.*: 2559e280 ptrues p0\.h, #20
--.*: 2559e2a0 ptrues p0\.h, #21
--.*: 2559e2a0 ptrues p0\.h, #21
--.*: 2559e2c0 ptrues p0\.h, #22
--.*: 2559e2c0 ptrues p0\.h, #22
--.*: 2559e2e0 ptrues p0\.h, #23
--.*: 2559e2e0 ptrues p0\.h, #23
--.*: 2559e300 ptrues p0\.h, #24
--.*: 2559e300 ptrues p0\.h, #24
--.*: 2559e320 ptrues p0\.h, #25
--.*: 2559e320 ptrues p0\.h, #25
--.*: 2559e340 ptrues p0\.h, #26
--.*: 2559e340 ptrues p0\.h, #26
--.*: 2559e360 ptrues p0\.h, #27
--.*: 2559e360 ptrues p0\.h, #27
--.*: 2559e380 ptrues p0\.h, #28
--.*: 2559e380 ptrues p0\.h, #28
--.*: 2559e3a0 ptrues p0\.h, mul4
--.*: 2559e3a0 ptrues p0\.h, mul4
--.*: 2559e3c0 ptrues p0\.h, mul3
--.*: 2559e3c0 ptrues p0\.h, mul3
--.*: 2559e3e0 ptrues p0\.h
--.*: 2559e3e0 ptrues p0\.h
--.*: 2559e3e0 ptrues p0\.h
--.*: 2599e000 ptrues p0\.s, pow2
--.*: 2599e000 ptrues p0\.s, pow2
--.*: 2599e001 ptrues p1\.s, pow2
--.*: 2599e001 ptrues p1\.s, pow2
--.*: 2599e00f ptrues p15\.s, pow2
--.*: 2599e00f ptrues p15\.s, pow2
--.*: 2599e020 ptrues p0\.s, vl1
--.*: 2599e020 ptrues p0\.s, vl1
--.*: 2599e040 ptrues p0\.s, vl2
--.*: 2599e040 ptrues p0\.s, vl2
--.*: 2599e060 ptrues p0\.s, vl3
--.*: 2599e060 ptrues p0\.s, vl3
--.*: 2599e080 ptrues p0\.s, vl4
--.*: 2599e080 ptrues p0\.s, vl4
--.*: 2599e0a0 ptrues p0\.s, vl5
--.*: 2599e0a0 ptrues p0\.s, vl5
--.*: 2599e0c0 ptrues p0\.s, vl6
--.*: 2599e0c0 ptrues p0\.s, vl6
--.*: 2599e0e0 ptrues p0\.s, vl7
--.*: 2599e0e0 ptrues p0\.s, vl7
--.*: 2599e100 ptrues p0\.s, vl8
--.*: 2599e100 ptrues p0\.s, vl8
--.*: 2599e120 ptrues p0\.s, vl16
--.*: 2599e120 ptrues p0\.s, vl16
--.*: 2599e140 ptrues p0\.s, vl32
--.*: 2599e140 ptrues p0\.s, vl32
--.*: 2599e160 ptrues p0\.s, vl64
--.*: 2599e160 ptrues p0\.s, vl64
--.*: 2599e180 ptrues p0\.s, vl128
--.*: 2599e180 ptrues p0\.s, vl128
--.*: 2599e1a0 ptrues p0\.s, vl256
--.*: 2599e1a0 ptrues p0\.s, vl256
--.*: 2599e1c0 ptrues p0\.s, #14
--.*: 2599e1c0 ptrues p0\.s, #14
--.*: 2599e1e0 ptrues p0\.s, #15
--.*: 2599e1e0 ptrues p0\.s, #15
--.*: 2599e200 ptrues p0\.s, #16
--.*: 2599e200 ptrues p0\.s, #16
--.*: 2599e220 ptrues p0\.s, #17
--.*: 2599e220 ptrues p0\.s, #17
--.*: 2599e240 ptrues p0\.s, #18
--.*: 2599e240 ptrues p0\.s, #18
--.*: 2599e260 ptrues p0\.s, #19
--.*: 2599e260 ptrues p0\.s, #19
--.*: 2599e280 ptrues p0\.s, #20
--.*: 2599e280 ptrues p0\.s, #20
--.*: 2599e2a0 ptrues p0\.s, #21
--.*: 2599e2a0 ptrues p0\.s, #21
--.*: 2599e2c0 ptrues p0\.s, #22
--.*: 2599e2c0 ptrues p0\.s, #22
--.*: 2599e2e0 ptrues p0\.s, #23
--.*: 2599e2e0 ptrues p0\.s, #23
--.*: 2599e300 ptrues p0\.s, #24
--.*: 2599e300 ptrues p0\.s, #24
--.*: 2599e320 ptrues p0\.s, #25
--.*: 2599e320 ptrues p0\.s, #25
--.*: 2599e340 ptrues p0\.s, #26
--.*: 2599e340 ptrues p0\.s, #26
--.*: 2599e360 ptrues p0\.s, #27
--.*: 2599e360 ptrues p0\.s, #27
--.*: 2599e380 ptrues p0\.s, #28
--.*: 2599e380 ptrues p0\.s, #28
--.*: 2599e3a0 ptrues p0\.s, mul4
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--.*: 2599e3c0 ptrues p0\.s, mul3
--.*: 2599e3c0 ptrues p0\.s, mul3
--.*: 2599e3e0 ptrues p0\.s
--.*: 2599e3e0 ptrues p0\.s
--.*: 2599e3e0 ptrues p0\.s
--.*: 25d9e000 ptrues p0\.d, pow2
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--.*: 25d9e00f ptrues p15\.d, pow2
--.*: 25d9e020 ptrues p0\.d, vl1
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--.*: 25d9e120 ptrues p0\.d, vl16
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--.*: 25d9e140 ptrues p0\.d, vl32
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--.*: 25d9e160 ptrues p0\.d, vl64
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--.*: 25d9e180 ptrues p0\.d, vl128
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--.*: 25d9e1c0 ptrues p0\.d, #14
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--.*: 25d9e380 ptrues p0\.d, #28
--.*: 25d9e3a0 ptrues p0\.d, mul4
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--.*: 25d9e3c0 ptrues p0\.d, mul3
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--.*: 25d9e3e0 ptrues p0\.d
--.*: 25d9e3e0 ptrues p0\.d
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--.*: 0531400f punpkhi p15\.h, p0\.b
--.*: 05314040 punpkhi p0\.h, p2\.b
--.*: 05314040 punpkhi p0\.h, p2\.b
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--.*: 053141e0 punpkhi p0\.h, p15\.b
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--.*: 05304040 punpklo p0\.h, p2\.b
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--.*: 053041e0 punpklo p0\.h, p15\.b
--.*: 05278000 rbit z0\.b, p0/m, z0\.b
--.*: 05278000 rbit z0\.b, p0/m, z0\.b
--.*: 05278001 rbit z1\.b, p0/m, z0\.b
--.*: 05278001 rbit z1\.b, p0/m, z0\.b
--.*: 0527801f rbit z31\.b, p0/m, z0\.b
--.*: 0527801f rbit z31\.b, p0/m, z0\.b
--.*: 05278800 rbit z0\.b, p2/m, z0\.b
--.*: 05278800 rbit z0\.b, p2/m, z0\.b
--.*: 05279c00 rbit z0\.b, p7/m, z0\.b
--.*: 05279c00 rbit z0\.b, p7/m, z0\.b
--.*: 05278060 rbit z0\.b, p0/m, z3\.b
--.*: 05278060 rbit z0\.b, p0/m, z3\.b
--.*: 052783e0 rbit z0\.b, p0/m, z31\.b
--.*: 052783e0 rbit z0\.b, p0/m, z31\.b
--.*: 05678000 rbit z0\.h, p0/m, z0\.h
--.*: 05678000 rbit z0\.h, p0/m, z0\.h
--.*: 05678001 rbit z1\.h, p0/m, z0\.h
--.*: 05678001 rbit z1\.h, p0/m, z0\.h
--.*: 0567801f rbit z31\.h, p0/m, z0\.h
--.*: 0567801f rbit z31\.h, p0/m, z0\.h
--.*: 05678800 rbit z0\.h, p2/m, z0\.h
--.*: 05678800 rbit z0\.h, p2/m, z0\.h
--.*: 05679c00 rbit z0\.h, p7/m, z0\.h
--.*: 05679c00 rbit z0\.h, p7/m, z0\.h
--.*: 05678060 rbit z0\.h, p0/m, z3\.h
--.*: 05678060 rbit z0\.h, p0/m, z3\.h
--.*: 056783e0 rbit z0\.h, p0/m, z31\.h
--.*: 056783e0 rbit z0\.h, p0/m, z31\.h
--.*: 05a78000 rbit z0\.s, p0/m, z0\.s
--.*: 05a78000 rbit z0\.s, p0/m, z0\.s
--.*: 05a78001 rbit z1\.s, p0/m, z0\.s
--.*: 05a78001 rbit z1\.s, p0/m, z0\.s
--.*: 05a7801f rbit z31\.s, p0/m, z0\.s
--.*: 05a7801f rbit z31\.s, p0/m, z0\.s
--.*: 05a78800 rbit z0\.s, p2/m, z0\.s
--.*: 05a78800 rbit z0\.s, p2/m, z0\.s
--.*: 05a79c00 rbit z0\.s, p7/m, z0\.s
--.*: 05a79c00 rbit z0\.s, p7/m, z0\.s
--.*: 05a78060 rbit z0\.s, p0/m, z3\.s
--.*: 05a78060 rbit z0\.s, p0/m, z3\.s
--.*: 05a783e0 rbit z0\.s, p0/m, z31\.s
--.*: 05a783e0 rbit z0\.s, p0/m, z31\.s
--.*: 05e78000 rbit z0\.d, p0/m, z0\.d
--.*: 05e78000 rbit z0\.d, p0/m, z0\.d
--.*: 05e78001 rbit z1\.d, p0/m, z0\.d
--.*: 05e78001 rbit z1\.d, p0/m, z0\.d
--.*: 05e7801f rbit z31\.d, p0/m, z0\.d
--.*: 05e7801f rbit z31\.d, p0/m, z0\.d
--.*: 05e78800 rbit z0\.d, p2/m, z0\.d
--.*: 05e78800 rbit z0\.d, p2/m, z0\.d
--.*: 05e79c00 rbit z0\.d, p7/m, z0\.d
--.*: 05e79c00 rbit z0\.d, p7/m, z0\.d
--.*: 05e78060 rbit z0\.d, p0/m, z3\.d
--.*: 05e78060 rbit z0\.d, p0/m, z3\.d
--.*: 05e783e0 rbit z0\.d, p0/m, z31\.d
--.*: 05e783e0 rbit z0\.d, p0/m, z31\.d
--.*: 2519f000 rdffr p0\.b
--.*: 2519f000 rdffr p0\.b
--.*: 2519f001 rdffr p1\.b
--.*: 2519f001 rdffr p1\.b
--.*: 2519f00f rdffr p15\.b
--.*: 2519f00f rdffr p15\.b
--.*: 2518f000 rdffr p0\.b, p0/z
--.*: 2518f000 rdffr p0\.b, p0/z
--.*: 2518f001 rdffr p1\.b, p0/z
--.*: 2518f001 rdffr p1\.b, p0/z
--.*: 2518f00f rdffr p15\.b, p0/z
--.*: 2518f00f rdffr p15\.b, p0/z
--.*: 2518f040 rdffr p0\.b, p2/z
--.*: 2518f040 rdffr p0\.b, p2/z
--.*: 2518f1e0 rdffr p0\.b, p15/z
--.*: 2518f1e0 rdffr p0\.b, p15/z
--.*: 2558f000 rdffrs p0\.b, p0/z
--.*: 2558f000 rdffrs p0\.b, p0/z
--.*: 2558f001 rdffrs p1\.b, p0/z
--.*: 2558f001 rdffrs p1\.b, p0/z
--.*: 2558f00f rdffrs p15\.b, p0/z
--.*: 2558f00f rdffrs p15\.b, p0/z
--.*: 2558f040 rdffrs p0\.b, p2/z
--.*: 2558f040 rdffrs p0\.b, p2/z
--.*: 2558f1e0 rdffrs p0\.b, p15/z
--.*: 2558f1e0 rdffrs p0\.b, p15/z
--.*: 04bf5000 rdvl x0, #0
--.*: 04bf5000 rdvl x0, #0
--.*: 04bf5001 rdvl x1, #0
--.*: 04bf5001 rdvl x1, #0
--.*: 04bf501f rdvl xzr, #0
--.*: 04bf501f rdvl xzr, #0
--.*: 04bf53e0 rdvl x0, #31
--.*: 04bf53e0 rdvl x0, #31
--.*: 04bf5400 rdvl x0, #-32
--.*: 04bf5400 rdvl x0, #-32
--.*: 04bf5420 rdvl x0, #-31
--.*: 04bf5420 rdvl x0, #-31
--.*: 04bf57e0 rdvl x0, #-1
--.*: 04bf57e0 rdvl x0, #-1
--.*: 05344000 rev p0\.b, p0\.b
--.*: 05344000 rev p0\.b, p0\.b
--.*: 05344001 rev p1\.b, p0\.b
--.*: 05344001 rev p1\.b, p0\.b
--.*: 0534400f rev p15\.b, p0\.b
--.*: 0534400f rev p15\.b, p0\.b
--.*: 05344040 rev p0\.b, p2\.b
--.*: 05344040 rev p0\.b, p2\.b
--.*: 053441e0 rev p0\.b, p15\.b
--.*: 053441e0 rev p0\.b, p15\.b
--.*: 05744000 rev p0\.h, p0\.h
--.*: 05744000 rev p0\.h, p0\.h
--.*: 05744001 rev p1\.h, p0\.h
--.*: 05744001 rev p1\.h, p0\.h
--.*: 0574400f rev p15\.h, p0\.h
--.*: 0574400f rev p15\.h, p0\.h
--.*: 05744040 rev p0\.h, p2\.h
--.*: 05744040 rev p0\.h, p2\.h
--.*: 057441e0 rev p0\.h, p15\.h
--.*: 057441e0 rev p0\.h, p15\.h
--.*: 05b44000 rev p0\.s, p0\.s
--.*: 05b44000 rev p0\.s, p0\.s
--.*: 05b44001 rev p1\.s, p0\.s
--.*: 05b44001 rev p1\.s, p0\.s
--.*: 05b4400f rev p15\.s, p0\.s
--.*: 05b4400f rev p15\.s, p0\.s
--.*: 05b44040 rev p0\.s, p2\.s
--.*: 05b44040 rev p0\.s, p2\.s
--.*: 05b441e0 rev p0\.s, p15\.s
--.*: 05b441e0 rev p0\.s, p15\.s
--.*: 05f44000 rev p0\.d, p0\.d
--.*: 05f44000 rev p0\.d, p0\.d
--.*: 05f44001 rev p1\.d, p0\.d
--.*: 05f44001 rev p1\.d, p0\.d
--.*: 05f4400f rev p15\.d, p0\.d
--.*: 05f4400f rev p15\.d, p0\.d
--.*: 05f44040 rev p0\.d, p2\.d
--.*: 05f44040 rev p0\.d, p2\.d
--.*: 05f441e0 rev p0\.d, p15\.d
--.*: 05f441e0 rev p0\.d, p15\.d
--.*: 05383800 rev z0\.b, z0\.b
--.*: 05383800 rev z0\.b, z0\.b
--.*: 05383801 rev z1\.b, z0\.b
--.*: 05383801 rev z1\.b, z0\.b
--.*: 0538381f rev z31\.b, z0\.b
--.*: 0538381f rev z31\.b, z0\.b
--.*: 05383840 rev z0\.b, z2\.b
--.*: 05383840 rev z0\.b, z2\.b
--.*: 05383be0 rev z0\.b, z31\.b
--.*: 05383be0 rev z0\.b, z31\.b
--.*: 05783800 rev z0\.h, z0\.h
--.*: 05783800 rev z0\.h, z0\.h
--.*: 05783801 rev z1\.h, z0\.h
--.*: 05783801 rev z1\.h, z0\.h
--.*: 0578381f rev z31\.h, z0\.h
--.*: 0578381f rev z31\.h, z0\.h
--.*: 05783840 rev z0\.h, z2\.h
--.*: 05783840 rev z0\.h, z2\.h
--.*: 05783be0 rev z0\.h, z31\.h
--.*: 05783be0 rev z0\.h, z31\.h
--.*: 05b83800 rev z0\.s, z0\.s
--.*: 05b83800 rev z0\.s, z0\.s
--.*: 05b83801 rev z1\.s, z0\.s
--.*: 05b83801 rev z1\.s, z0\.s
--.*: 05b8381f rev z31\.s, z0\.s
--.*: 05b8381f rev z31\.s, z0\.s
--.*: 05b83840 rev z0\.s, z2\.s
--.*: 05b83840 rev z0\.s, z2\.s
--.*: 05b83be0 rev z0\.s, z31\.s
--.*: 05b83be0 rev z0\.s, z31\.s
--.*: 05f83800 rev z0\.d, z0\.d
--.*: 05f83800 rev z0\.d, z0\.d
--.*: 05f83801 rev z1\.d, z0\.d
--.*: 05f83801 rev z1\.d, z0\.d
--.*: 05f8381f rev z31\.d, z0\.d
--.*: 05f8381f rev z31\.d, z0\.d
--.*: 05f83840 rev z0\.d, z2\.d
--.*: 05f83840 rev z0\.d, z2\.d
--.*: 05f83be0 rev z0\.d, z31\.d
--.*: 05f83be0 rev z0\.d, z31\.d
--.*: 05648000 revb z0\.h, p0/m, z0\.h
--.*: 05648000 revb z0\.h, p0/m, z0\.h
--.*: 05648001 revb z1\.h, p0/m, z0\.h
--.*: 05648001 revb z1\.h, p0/m, z0\.h
--.*: 0564801f revb z31\.h, p0/m, z0\.h
--.*: 0564801f revb z31\.h, p0/m, z0\.h
--.*: 05648800 revb z0\.h, p2/m, z0\.h
--.*: 05648800 revb z0\.h, p2/m, z0\.h
--.*: 05649c00 revb z0\.h, p7/m, z0\.h
--.*: 05649c00 revb z0\.h, p7/m, z0\.h
--.*: 05648060 revb z0\.h, p0/m, z3\.h
--.*: 05648060 revb z0\.h, p0/m, z3\.h
--.*: 056483e0 revb z0\.h, p0/m, z31\.h
--.*: 056483e0 revb z0\.h, p0/m, z31\.h
--.*: 05a48000 revb z0\.s, p0/m, z0\.s
--.*: 05a48000 revb z0\.s, p0/m, z0\.s
--.*: 05a48001 revb z1\.s, p0/m, z0\.s
--.*: 05a48001 revb z1\.s, p0/m, z0\.s
--.*: 05a4801f revb z31\.s, p0/m, z0\.s
--.*: 05a4801f revb z31\.s, p0/m, z0\.s
--.*: 05a48800 revb z0\.s, p2/m, z0\.s
--.*: 05a48800 revb z0\.s, p2/m, z0\.s
--.*: 05a49c00 revb z0\.s, p7/m, z0\.s
--.*: 05a49c00 revb z0\.s, p7/m, z0\.s
--.*: 05a48060 revb z0\.s, p0/m, z3\.s
--.*: 05a48060 revb z0\.s, p0/m, z3\.s
--.*: 05a483e0 revb z0\.s, p0/m, z31\.s
--.*: 05a483e0 revb z0\.s, p0/m, z31\.s
--.*: 05e48000 revb z0\.d, p0/m, z0\.d
--.*: 05e48000 revb z0\.d, p0/m, z0\.d
--.*: 05e48001 revb z1\.d, p0/m, z0\.d
--.*: 05e48001 revb z1\.d, p0/m, z0\.d
--.*: 05e4801f revb z31\.d, p0/m, z0\.d
--.*: 05e4801f revb z31\.d, p0/m, z0\.d
--.*: 05e48800 revb z0\.d, p2/m, z0\.d
--.*: 05e48800 revb z0\.d, p2/m, z0\.d
--.*: 05e49c00 revb z0\.d, p7/m, z0\.d
--.*: 05e49c00 revb z0\.d, p7/m, z0\.d
--.*: 05e48060 revb z0\.d, p0/m, z3\.d
--.*: 05e48060 revb z0\.d, p0/m, z3\.d
--.*: 05e483e0 revb z0\.d, p0/m, z31\.d
--.*: 05e483e0 revb z0\.d, p0/m, z31\.d
--.*: 05a58000 revh z0\.s, p0/m, z0\.s
--.*: 05a58000 revh z0\.s, p0/m, z0\.s
--.*: 05a58001 revh z1\.s, p0/m, z0\.s
--.*: 05a58001 revh z1\.s, p0/m, z0\.s
--.*: 05a5801f revh z31\.s, p0/m, z0\.s
--.*: 05a5801f revh z31\.s, p0/m, z0\.s
--.*: 05a58800 revh z0\.s, p2/m, z0\.s
--.*: 05a58800 revh z0\.s, p2/m, z0\.s
--.*: 05a59c00 revh z0\.s, p7/m, z0\.s
--.*: 05a59c00 revh z0\.s, p7/m, z0\.s
--.*: 05a58060 revh z0\.s, p0/m, z3\.s
--.*: 05a58060 revh z0\.s, p0/m, z3\.s
--.*: 05a583e0 revh z0\.s, p0/m, z31\.s
--.*: 05a583e0 revh z0\.s, p0/m, z31\.s
--.*: 05e58000 revh z0\.d, p0/m, z0\.d
--.*: 05e58000 revh z0\.d, p0/m, z0\.d
--.*: 05e58001 revh z1\.d, p0/m, z0\.d
--.*: 05e58001 revh z1\.d, p0/m, z0\.d
--.*: 05e5801f revh z31\.d, p0/m, z0\.d
--.*: 05e5801f revh z31\.d, p0/m, z0\.d
--.*: 05e58800 revh z0\.d, p2/m, z0\.d
--.*: 05e58800 revh z0\.d, p2/m, z0\.d
--.*: 05e59c00 revh z0\.d, p7/m, z0\.d
--.*: 05e59c00 revh z0\.d, p7/m, z0\.d
--.*: 05e58060 revh z0\.d, p0/m, z3\.d
--.*: 05e58060 revh z0\.d, p0/m, z3\.d
--.*: 05e583e0 revh z0\.d, p0/m, z31\.d
--.*: 05e583e0 revh z0\.d, p0/m, z31\.d
--.*: 05e68000 revw z0\.d, p0/m, z0\.d
--.*: 05e68000 revw z0\.d, p0/m, z0\.d
--.*: 05e68001 revw z1\.d, p0/m, z0\.d
--.*: 05e68001 revw z1\.d, p0/m, z0\.d
--.*: 05e6801f revw z31\.d, p0/m, z0\.d
--.*: 05e6801f revw z31\.d, p0/m, z0\.d
--.*: 05e68800 revw z0\.d, p2/m, z0\.d
--.*: 05e68800 revw z0\.d, p2/m, z0\.d
--.*: 05e69c00 revw z0\.d, p7/m, z0\.d
--.*: 05e69c00 revw z0\.d, p7/m, z0\.d
--.*: 05e68060 revw z0\.d, p0/m, z3\.d
--.*: 05e68060 revw z0\.d, p0/m, z3\.d
--.*: 05e683e0 revw z0\.d, p0/m, z31\.d
--.*: 05e683e0 revw z0\.d, p0/m, z31\.d
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--.*: 44df0000 sdot z0\.d, z0\.h, z31\.h
--.*: 44a00000 sdot z0\.s, z0\.b, z0\.b\[0\]
--.*: 44a00000 sdot z0\.s, z0\.b, z0\.b\[0\]
--.*: 44a00001 sdot z1\.s, z0\.b, z0\.b\[0\]
--.*: 44a00001 sdot z1\.s, z0\.b, z0\.b\[0\]
--.*: 44a0001f sdot z31\.s, z0\.b, z0\.b\[0\]
--.*: 44a0001f sdot z31\.s, z0\.b, z0\.b\[0\]
--.*: 44a00040 sdot z0\.s, z2\.b, z0\.b\[0\]
--.*: 44a00040 sdot z0\.s, z2\.b, z0\.b\[0\]
--.*: 44a003e0 sdot z0\.s, z31\.b, z0\.b\[0\]
--.*: 44a003e0 sdot z0\.s, z31\.b, z0\.b\[0\]
--.*: 44a30000 sdot z0\.s, z0\.b, z3\.b\[0\]
--.*: 44a30000 sdot z0\.s, z0\.b, z3\.b\[0\]
--.*: 44a70000 sdot z0\.s, z0\.b, z7\.b\[0\]
--.*: 44a70000 sdot z0\.s, z0\.b, z7\.b\[0\]
--.*: 44a80000 sdot z0\.s, z0\.b, z0\.b\[1\]
--.*: 44a80000 sdot z0\.s, z0\.b, z0\.b\[1\]
--.*: 44ac0000 sdot z0\.s, z0\.b, z4\.b\[1\]
--.*: 44ac0000 sdot z0\.s, z0\.b, z4\.b\[1\]
--.*: 44b30000 sdot z0\.s, z0\.b, z3\.b\[2\]
--.*: 44b30000 sdot z0\.s, z0\.b, z3\.b\[2\]
--.*: 44b80000 sdot z0\.s, z0\.b, z0\.b\[3\]
--.*: 44b80000 sdot z0\.s, z0\.b, z0\.b\[3\]
--.*: 44bd0000 sdot z0\.s, z0\.b, z5\.b\[3\]
--.*: 44bd0000 sdot z0\.s, z0\.b, z5\.b\[3\]
--.*: 44e00000 sdot z0\.d, z0\.h, z0\.h\[0\]
--.*: 44e00000 sdot z0\.d, z0\.h, z0\.h\[0\]
--.*: 44e00001 sdot z1\.d, z0\.h, z0\.h\[0\]
--.*: 44e00001 sdot z1\.d, z0\.h, z0\.h\[0\]
--.*: 44e0001f sdot z31\.d, z0\.h, z0\.h\[0\]
--.*: 44e0001f sdot z31\.d, z0\.h, z0\.h\[0\]
--.*: 44e00040 sdot z0\.d, z2\.h, z0\.h\[0\]
--.*: 44e00040 sdot z0\.d, z2\.h, z0\.h\[0\]
--.*: 44e003e0 sdot z0\.d, z31\.h, z0\.h\[0\]
--.*: 44e003e0 sdot z0\.d, z31\.h, z0\.h\[0\]
--.*: 44e30000 sdot z0\.d, z0\.h, z3\.h\[0\]
--.*: 44e30000 sdot z0\.d, z0\.h, z3\.h\[0\]
--.*: 44ef0000 sdot z0\.d, z0\.h, z15\.h\[0\]
--.*: 44ef0000 sdot z0\.d, z0\.h, z15\.h\[0\]
--.*: 44f00000 sdot z0\.d, z0\.h, z0\.h\[1\]
--.*: 44f00000 sdot z0\.d, z0\.h, z0\.h\[1\]
--.*: 44fb0000 sdot z0\.d, z0\.h, z11\.h\[1\]
--.*: 44fb0000 sdot z0\.d, z0\.h, z11\.h\[1\]
--.*: 0520c000 mov z0\.b, p0/m, z0\.b
--.*: 0520c000 mov z0\.b, p0/m, z0\.b
--.*: 0520c001 sel z1\.b, p0, z0\.b, z0\.b
--.*: 0520c001 sel z1\.b, p0, z0\.b, z0\.b
--.*: 0520c01f sel z31\.b, p0, z0\.b, z0\.b
--.*: 0520c01f sel z31\.b, p0, z0\.b, z0\.b
--.*: 0520c800 mov z0\.b, p2/m, z0\.b
--.*: 0520c800 mov z0\.b, p2/m, z0\.b
--.*: 0520fc00 mov z0\.b, p15/m, z0\.b
--.*: 0520fc00 mov z0\.b, p15/m, z0\.b
--.*: 0520c060 mov z0\.b, p0/m, z3\.b
--.*: 0520c060 mov z0\.b, p0/m, z3\.b
--.*: 0520c3e0 mov z0\.b, p0/m, z31\.b
--.*: 0520c3e0 mov z0\.b, p0/m, z31\.b
--.*: 0524c000 sel z0\.b, p0, z0\.b, z4\.b
--.*: 0524c000 sel z0\.b, p0, z0\.b, z4\.b
--.*: 053fc000 sel z0\.b, p0, z0\.b, z31\.b
--.*: 053fc000 sel z0\.b, p0, z0\.b, z31\.b
--.*: 0560c000 mov z0\.h, p0/m, z0\.h
--.*: 0560c000 mov z0\.h, p0/m, z0\.h
--.*: 0560c001 sel z1\.h, p0, z0\.h, z0\.h
--.*: 0560c001 sel z1\.h, p0, z0\.h, z0\.h
--.*: 0560c01f sel z31\.h, p0, z0\.h, z0\.h
--.*: 0560c01f sel z31\.h, p0, z0\.h, z0\.h
--.*: 0560c800 mov z0\.h, p2/m, z0\.h
--.*: 0560c800 mov z0\.h, p2/m, z0\.h
--.*: 0560fc00 mov z0\.h, p15/m, z0\.h
--.*: 0560fc00 mov z0\.h, p15/m, z0\.h
--.*: 0560c060 mov z0\.h, p0/m, z3\.h
--.*: 0560c060 mov z0\.h, p0/m, z3\.h
--.*: 0560c3e0 mov z0\.h, p0/m, z31\.h
--.*: 0560c3e0 mov z0\.h, p0/m, z31\.h
--.*: 0564c000 sel z0\.h, p0, z0\.h, z4\.h
--.*: 0564c000 sel z0\.h, p0, z0\.h, z4\.h
--.*: 057fc000 sel z0\.h, p0, z0\.h, z31\.h
--.*: 057fc000 sel z0\.h, p0, z0\.h, z31\.h
--.*: 05a0c000 mov z0\.s, p0/m, z0\.s
--.*: 05a0c000 mov z0\.s, p0/m, z0\.s
--.*: 05a0c001 sel z1\.s, p0, z0\.s, z0\.s
--.*: 05a0c001 sel z1\.s, p0, z0\.s, z0\.s
--.*: 05a0c01f sel z31\.s, p0, z0\.s, z0\.s
--.*: 05a0c01f sel z31\.s, p0, z0\.s, z0\.s
--.*: 05a0c800 mov z0\.s, p2/m, z0\.s
--.*: 05a0c800 mov z0\.s, p2/m, z0\.s
--.*: 05a0fc00 mov z0\.s, p15/m, z0\.s
--.*: 05a0fc00 mov z0\.s, p15/m, z0\.s
--.*: 05a0c060 mov z0\.s, p0/m, z3\.s
--.*: 05a0c060 mov z0\.s, p0/m, z3\.s
--.*: 05a0c3e0 mov z0\.s, p0/m, z31\.s
--.*: 05a0c3e0 mov z0\.s, p0/m, z31\.s
--.*: 05a4c000 sel z0\.s, p0, z0\.s, z4\.s
--.*: 05a4c000 sel z0\.s, p0, z0\.s, z4\.s
--.*: 05bfc000 sel z0\.s, p0, z0\.s, z31\.s
--.*: 05bfc000 sel z0\.s, p0, z0\.s, z31\.s
--.*: 05e0c000 mov z0\.d, p0/m, z0\.d
--.*: 05e0c000 mov z0\.d, p0/m, z0\.d
--.*: 05e0c001 sel z1\.d, p0, z0\.d, z0\.d
--.*: 05e0c001 sel z1\.d, p0, z0\.d, z0\.d
--.*: 05e0c01f sel z31\.d, p0, z0\.d, z0\.d
--.*: 05e0c01f sel z31\.d, p0, z0\.d, z0\.d
--.*: 05e0c800 mov z0\.d, p2/m, z0\.d
--.*: 05e0c800 mov z0\.d, p2/m, z0\.d
--.*: 05e0fc00 mov z0\.d, p15/m, z0\.d
--.*: 05e0fc00 mov z0\.d, p15/m, z0\.d
--.*: 05e0c060 mov z0\.d, p0/m, z3\.d
--.*: 05e0c060 mov z0\.d, p0/m, z3\.d
--.*: 05e0c3e0 mov z0\.d, p0/m, z31\.d
--.*: 05e0c3e0 mov z0\.d, p0/m, z31\.d
--.*: 05e4c000 sel z0\.d, p0, z0\.d, z4\.d
--.*: 05e4c000 sel z0\.d, p0, z0\.d, z4\.d
--.*: 05ffc000 sel z0\.d, p0, z0\.d, z31\.d
--.*: 05ffc000 sel z0\.d, p0, z0\.d, z31\.d
--.*: 25004210 mov p0\.b, p0/m, p0\.b
--.*: 25004210 mov p0\.b, p0/m, p0\.b
--.*: 25004211 sel p1\.b, p0, p0\.b, p0\.b
--.*: 25004211 sel p1\.b, p0, p0\.b, p0\.b
--.*: 2500421f sel p15\.b, p0, p0\.b, p0\.b
--.*: 2500421f sel p15\.b, p0, p0\.b, p0\.b
--.*: 25004a10 mov p0\.b, p2/m, p0\.b
--.*: 25004a10 mov p0\.b, p2/m, p0\.b
--.*: 25007e10 mov p0\.b, p15/m, p0\.b
--.*: 25007e10 mov p0\.b, p15/m, p0\.b
--.*: 25004270 mov p0\.b, p0/m, p3\.b
--.*: 25004270 mov p0\.b, p0/m, p3\.b
--.*: 250043f0 mov p0\.b, p0/m, p15\.b
--.*: 250043f0 mov p0\.b, p0/m, p15\.b
--.*: 25044210 sel p0\.b, p0, p0\.b, p4\.b
--.*: 25044210 sel p0\.b, p0, p0\.b, p4\.b
--.*: 250f4210 sel p0\.b, p0, p0\.b, p15\.b
--.*: 250f4210 sel p0\.b, p0, p0\.b, p15\.b
--.*: 252c9000 setffr
--.*: 252c9000 setffr
--.*: 2528c000 smax z0\.b, z0\.b, #0
--.*: 2528c000 smax z0\.b, z0\.b, #0
--.*: 2528c001 smax z1\.b, z1\.b, #0
--.*: 2528c001 smax z1\.b, z1\.b, #0
--.*: 2528c01f smax z31\.b, z31\.b, #0
--.*: 2528c01f smax z31\.b, z31\.b, #0
--.*: 2528c002 smax z2\.b, z2\.b, #0
--.*: 2528c002 smax z2\.b, z2\.b, #0
--.*: 2528cfe0 smax z0\.b, z0\.b, #127
--.*: 2528cfe0 smax z0\.b, z0\.b, #127
--.*: 2528d000 smax z0\.b, z0\.b, #-128
--.*: 2528d000 smax z0\.b, z0\.b, #-128
--.*: 2528d020 smax z0\.b, z0\.b, #-127
--.*: 2528d020 smax z0\.b, z0\.b, #-127
--.*: 2528dfe0 smax z0\.b, z0\.b, #-1
--.*: 2528dfe0 smax z0\.b, z0\.b, #-1
--.*: 2568c000 smax z0\.h, z0\.h, #0
--.*: 2568c000 smax z0\.h, z0\.h, #0
--.*: 2568c001 smax z1\.h, z1\.h, #0
--.*: 2568c001 smax z1\.h, z1\.h, #0
--.*: 2568c01f smax z31\.h, z31\.h, #0
--.*: 2568c01f smax z31\.h, z31\.h, #0
--.*: 2568c002 smax z2\.h, z2\.h, #0
--.*: 2568c002 smax z2\.h, z2\.h, #0
--.*: 2568cfe0 smax z0\.h, z0\.h, #127
--.*: 2568cfe0 smax z0\.h, z0\.h, #127
--.*: 2568d000 smax z0\.h, z0\.h, #-128
--.*: 2568d000 smax z0\.h, z0\.h, #-128
--.*: 2568d020 smax z0\.h, z0\.h, #-127
--.*: 2568d020 smax z0\.h, z0\.h, #-127
--.*: 2568dfe0 smax z0\.h, z0\.h, #-1
--.*: 2568dfe0 smax z0\.h, z0\.h, #-1
--.*: 25a8c000 smax z0\.s, z0\.s, #0
--.*: 25a8c000 smax z0\.s, z0\.s, #0
--.*: 25a8c001 smax z1\.s, z1\.s, #0
--.*: 25a8c001 smax z1\.s, z1\.s, #0
--.*: 25a8c01f smax z31\.s, z31\.s, #0
--.*: 25a8c01f smax z31\.s, z31\.s, #0
--.*: 25a8c002 smax z2\.s, z2\.s, #0
--.*: 25a8c002 smax z2\.s, z2\.s, #0
--.*: 25a8cfe0 smax z0\.s, z0\.s, #127
--.*: 25a8cfe0 smax z0\.s, z0\.s, #127
--.*: 25a8d000 smax z0\.s, z0\.s, #-128
--.*: 25a8d000 smax z0\.s, z0\.s, #-128
--.*: 25a8d020 smax z0\.s, z0\.s, #-127
--.*: 25a8d020 smax z0\.s, z0\.s, #-127
--.*: 25a8dfe0 smax z0\.s, z0\.s, #-1
--.*: 25a8dfe0 smax z0\.s, z0\.s, #-1
--.*: 25e8c000 smax z0\.d, z0\.d, #0
--.*: 25e8c000 smax z0\.d, z0\.d, #0
--.*: 25e8c001 smax z1\.d, z1\.d, #0
--.*: 25e8c001 smax z1\.d, z1\.d, #0
--.*: 25e8c01f smax z31\.d, z31\.d, #0
--.*: 25e8c01f smax z31\.d, z31\.d, #0
--.*: 25e8c002 smax z2\.d, z2\.d, #0
--.*: 25e8c002 smax z2\.d, z2\.d, #0
--.*: 25e8cfe0 smax z0\.d, z0\.d, #127
--.*: 25e8cfe0 smax z0\.d, z0\.d, #127
--.*: 25e8d000 smax z0\.d, z0\.d, #-128
--.*: 25e8d000 smax z0\.d, z0\.d, #-128
--.*: 25e8d020 smax z0\.d, z0\.d, #-127
--.*: 25e8d020 smax z0\.d, z0\.d, #-127
--.*: 25e8dfe0 smax z0\.d, z0\.d, #-1
--.*: 25e8dfe0 smax z0\.d, z0\.d, #-1
--.*: 04080000 smax z0\.b, p0/m, z0\.b, z0\.b
--.*: 04080000 smax z0\.b, p0/m, z0\.b, z0\.b
--.*: 04080001 smax z1\.b, p0/m, z1\.b, z0\.b
--.*: 04080001 smax z1\.b, p0/m, z1\.b, z0\.b
--.*: 0408001f smax z31\.b, p0/m, z31\.b, z0\.b
--.*: 0408001f smax z31\.b, p0/m, z31\.b, z0\.b
--.*: 04080800 smax z0\.b, p2/m, z0\.b, z0\.b
--.*: 04080800 smax z0\.b, p2/m, z0\.b, z0\.b
--.*: 04081c00 smax z0\.b, p7/m, z0\.b, z0\.b
--.*: 04081c00 smax z0\.b, p7/m, z0\.b, z0\.b
--.*: 04080003 smax z3\.b, p0/m, z3\.b, z0\.b
--.*: 04080003 smax z3\.b, p0/m, z3\.b, z0\.b
--.*: 04080080 smax z0\.b, p0/m, z0\.b, z4\.b
--.*: 04080080 smax z0\.b, p0/m, z0\.b, z4\.b
--.*: 040803e0 smax z0\.b, p0/m, z0\.b, z31\.b
--.*: 040803e0 smax z0\.b, p0/m, z0\.b, z31\.b
--.*: 04480000 smax z0\.h, p0/m, z0\.h, z0\.h
--.*: 04480000 smax z0\.h, p0/m, z0\.h, z0\.h
--.*: 04480001 smax z1\.h, p0/m, z1\.h, z0\.h
--.*: 04480001 smax z1\.h, p0/m, z1\.h, z0\.h
--.*: 0448001f smax z31\.h, p0/m, z31\.h, z0\.h
--.*: 0448001f smax z31\.h, p0/m, z31\.h, z0\.h
--.*: 04480800 smax z0\.h, p2/m, z0\.h, z0\.h
--.*: 04480800 smax z0\.h, p2/m, z0\.h, z0\.h
--.*: 04481c00 smax z0\.h, p7/m, z0\.h, z0\.h
--.*: 04481c00 smax z0\.h, p7/m, z0\.h, z0\.h
--.*: 04480003 smax z3\.h, p0/m, z3\.h, z0\.h
--.*: 04480003 smax z3\.h, p0/m, z3\.h, z0\.h
--.*: 04480080 smax z0\.h, p0/m, z0\.h, z4\.h
--.*: 04480080 smax z0\.h, p0/m, z0\.h, z4\.h
--.*: 044803e0 smax z0\.h, p0/m, z0\.h, z31\.h
--.*: 044803e0 smax z0\.h, p0/m, z0\.h, z31\.h
--.*: 04880000 smax z0\.s, p0/m, z0\.s, z0\.s
--.*: 04880000 smax z0\.s, p0/m, z0\.s, z0\.s
--.*: 04880001 smax z1\.s, p0/m, z1\.s, z0\.s
--.*: 04880001 smax z1\.s, p0/m, z1\.s, z0\.s
--.*: 0488001f smax z31\.s, p0/m, z31\.s, z0\.s
--.*: 0488001f smax z31\.s, p0/m, z31\.s, z0\.s
--.*: 04880800 smax z0\.s, p2/m, z0\.s, z0\.s
--.*: 04880800 smax z0\.s, p2/m, z0\.s, z0\.s
--.*: 04881c00 smax z0\.s, p7/m, z0\.s, z0\.s
--.*: 04881c00 smax z0\.s, p7/m, z0\.s, z0\.s
--.*: 04880003 smax z3\.s, p0/m, z3\.s, z0\.s
--.*: 04880003 smax z3\.s, p0/m, z3\.s, z0\.s
--.*: 04880080 smax z0\.s, p0/m, z0\.s, z4\.s
--.*: 04880080 smax z0\.s, p0/m, z0\.s, z4\.s
--.*: 048803e0 smax z0\.s, p0/m, z0\.s, z31\.s
--.*: 048803e0 smax z0\.s, p0/m, z0\.s, z31\.s
--.*: 04c80000 smax z0\.d, p0/m, z0\.d, z0\.d
--.*: 04c80000 smax z0\.d, p0/m, z0\.d, z0\.d
--.*: 04c80001 smax z1\.d, p0/m, z1\.d, z0\.d
--.*: 04c80001 smax z1\.d, p0/m, z1\.d, z0\.d
--.*: 04c8001f smax z31\.d, p0/m, z31\.d, z0\.d
--.*: 04c8001f smax z31\.d, p0/m, z31\.d, z0\.d
--.*: 04c80800 smax z0\.d, p2/m, z0\.d, z0\.d
--.*: 04c80800 smax z0\.d, p2/m, z0\.d, z0\.d
--.*: 04c81c00 smax z0\.d, p7/m, z0\.d, z0\.d
--.*: 04c81c00 smax z0\.d, p7/m, z0\.d, z0\.d
--.*: 04c80003 smax z3\.d, p0/m, z3\.d, z0\.d
--.*: 04c80003 smax z3\.d, p0/m, z3\.d, z0\.d
--.*: 04c80080 smax z0\.d, p0/m, z0\.d, z4\.d
--.*: 04c80080 smax z0\.d, p0/m, z0\.d, z4\.d
--.*: 04c803e0 smax z0\.d, p0/m, z0\.d, z31\.d
--.*: 04c803e0 smax z0\.d, p0/m, z0\.d, z31\.d
--.*: 04082000 smaxv b0, p0, z0\.b
--.*: 04082000 smaxv b0, p0, z0\.b
--.*: 04082001 smaxv b1, p0, z0\.b
--.*: 04082001 smaxv b1, p0, z0\.b
--.*: 0408201f smaxv b31, p0, z0\.b
--.*: 0408201f smaxv b31, p0, z0\.b
--.*: 04082800 smaxv b0, p2, z0\.b
--.*: 04082800 smaxv b0, p2, z0\.b
--.*: 04083c00 smaxv b0, p7, z0\.b
--.*: 04083c00 smaxv b0, p7, z0\.b
--.*: 04082060 smaxv b0, p0, z3\.b
--.*: 04082060 smaxv b0, p0, z3\.b
--.*: 040823e0 smaxv b0, p0, z31\.b
--.*: 040823e0 smaxv b0, p0, z31\.b
--.*: 04482000 smaxv h0, p0, z0\.h
--.*: 04482000 smaxv h0, p0, z0\.h
--.*: 04482001 smaxv h1, p0, z0\.h
--.*: 04482001 smaxv h1, p0, z0\.h
--.*: 0448201f smaxv h31, p0, z0\.h
--.*: 0448201f smaxv h31, p0, z0\.h
--.*: 04482800 smaxv h0, p2, z0\.h
--.*: 04482800 smaxv h0, p2, z0\.h
--.*: 04483c00 smaxv h0, p7, z0\.h
--.*: 04483c00 smaxv h0, p7, z0\.h
--.*: 04482060 smaxv h0, p0, z3\.h
--.*: 04482060 smaxv h0, p0, z3\.h
--.*: 044823e0 smaxv h0, p0, z31\.h
--.*: 044823e0 smaxv h0, p0, z31\.h
--.*: 04882000 smaxv s0, p0, z0\.s
--.*: 04882000 smaxv s0, p0, z0\.s
--.*: 04882001 smaxv s1, p0, z0\.s
--.*: 04882001 smaxv s1, p0, z0\.s
--.*: 0488201f smaxv s31, p0, z0\.s
--.*: 0488201f smaxv s31, p0, z0\.s
--.*: 04882800 smaxv s0, p2, z0\.s
--.*: 04882800 smaxv s0, p2, z0\.s
--.*: 04883c00 smaxv s0, p7, z0\.s
--.*: 04883c00 smaxv s0, p7, z0\.s
--.*: 04882060 smaxv s0, p0, z3\.s
--.*: 04882060 smaxv s0, p0, z3\.s
--.*: 048823e0 smaxv s0, p0, z31\.s
--.*: 048823e0 smaxv s0, p0, z31\.s
--.*: 04c82000 smaxv d0, p0, z0\.d
--.*: 04c82000 smaxv d0, p0, z0\.d
--.*: 04c82001 smaxv d1, p0, z0\.d
--.*: 04c82001 smaxv d1, p0, z0\.d
--.*: 04c8201f smaxv d31, p0, z0\.d
--.*: 04c8201f smaxv d31, p0, z0\.d
--.*: 04c82800 smaxv d0, p2, z0\.d
--.*: 04c82800 smaxv d0, p2, z0\.d
--.*: 04c83c00 smaxv d0, p7, z0\.d
--.*: 04c83c00 smaxv d0, p7, z0\.d
--.*: 04c82060 smaxv d0, p0, z3\.d
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--.*: 04c823e0 smaxv d0, p0, z31\.d
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--.*: 252ac002 smin z2\.b, z2\.b, #0
--.*: 252acfe0 smin z0\.b, z0\.b, #127
--.*: 252acfe0 smin z0\.b, z0\.b, #127
--.*: 252ad000 smin z0\.b, z0\.b, #-128
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--.*: 252ad020 smin z0\.b, z0\.b, #-127
--.*: 252adfe0 smin z0\.b, z0\.b, #-1
--.*: 252adfe0 smin z0\.b, z0\.b, #-1
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--.*: 256ac000 smin z0\.h, z0\.h, #0
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--.*: 256ac001 smin z1\.h, z1\.h, #0
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--.*: 256ac01f smin z31\.h, z31\.h, #0
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--.*: 256ac002 smin z2\.h, z2\.h, #0
--.*: 256acfe0 smin z0\.h, z0\.h, #127
--.*: 256acfe0 smin z0\.h, z0\.h, #127
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--.*: 256ad020 smin z0\.h, z0\.h, #-127
--.*: 256adfe0 smin z0\.h, z0\.h, #-1
--.*: 256adfe0 smin z0\.h, z0\.h, #-1
--.*: 25aac000 smin z0\.s, z0\.s, #0
--.*: 25aac000 smin z0\.s, z0\.s, #0
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--.*: 25aac001 smin z1\.s, z1\.s, #0
--.*: 25aac01f smin z31\.s, z31\.s, #0
--.*: 25aac01f smin z31\.s, z31\.s, #0
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--.*: 25aac002 smin z2\.s, z2\.s, #0
--.*: 25aacfe0 smin z0\.s, z0\.s, #127
--.*: 25aacfe0 smin z0\.s, z0\.s, #127
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--.*: 25aad020 smin z0\.s, z0\.s, #-127
--.*: 25aadfe0 smin z0\.s, z0\.s, #-1
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--.*: 25eac000 smin z0\.d, z0\.d, #0
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--.*: 25eac001 smin z1\.d, z1\.d, #0
--.*: 25eac01f smin z31\.d, z31\.d, #0
--.*: 25eac01f smin z31\.d, z31\.d, #0
--.*: 25eac002 smin z2\.d, z2\.d, #0
--.*: 25eac002 smin z2\.d, z2\.d, #0
--.*: 25eacfe0 smin z0\.d, z0\.d, #127
--.*: 25eacfe0 smin z0\.d, z0\.d, #127
--.*: 25ead000 smin z0\.d, z0\.d, #-128
--.*: 25ead000 smin z0\.d, z0\.d, #-128
--.*: 25ead020 smin z0\.d, z0\.d, #-127
--.*: 25ead020 smin z0\.d, z0\.d, #-127
--.*: 25eadfe0 smin z0\.d, z0\.d, #-1
--.*: 25eadfe0 smin z0\.d, z0\.d, #-1
--.*: 040a0000 smin z0\.b, p0/m, z0\.b, z0\.b
--.*: 040a0000 smin z0\.b, p0/m, z0\.b, z0\.b
--.*: 040a0001 smin z1\.b, p0/m, z1\.b, z0\.b
--.*: 040a0001 smin z1\.b, p0/m, z1\.b, z0\.b
--.*: 040a001f smin z31\.b, p0/m, z31\.b, z0\.b
--.*: 040a001f smin z31\.b, p0/m, z31\.b, z0\.b
--.*: 040a0800 smin z0\.b, p2/m, z0\.b, z0\.b
--.*: 040a0800 smin z0\.b, p2/m, z0\.b, z0\.b
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--.*: 040a1c00 smin z0\.b, p7/m, z0\.b, z0\.b
--.*: 040a0003 smin z3\.b, p0/m, z3\.b, z0\.b
--.*: 040a0003 smin z3\.b, p0/m, z3\.b, z0\.b
--.*: 040a0080 smin z0\.b, p0/m, z0\.b, z4\.b
--.*: 040a0080 smin z0\.b, p0/m, z0\.b, z4\.b
--.*: 040a03e0 smin z0\.b, p0/m, z0\.b, z31\.b
--.*: 040a03e0 smin z0\.b, p0/m, z0\.b, z31\.b
--.*: 044a0000 smin z0\.h, p0/m, z0\.h, z0\.h
--.*: 044a0000 smin z0\.h, p0/m, z0\.h, z0\.h
--.*: 044a0001 smin z1\.h, p0/m, z1\.h, z0\.h
--.*: 044a0001 smin z1\.h, p0/m, z1\.h, z0\.h
--.*: 044a001f smin z31\.h, p0/m, z31\.h, z0\.h
--.*: 044a001f smin z31\.h, p0/m, z31\.h, z0\.h
--.*: 044a0800 smin z0\.h, p2/m, z0\.h, z0\.h
--.*: 044a0800 smin z0\.h, p2/m, z0\.h, z0\.h
--.*: 044a1c00 smin z0\.h, p7/m, z0\.h, z0\.h
--.*: 044a1c00 smin z0\.h, p7/m, z0\.h, z0\.h
--.*: 044a0003 smin z3\.h, p0/m, z3\.h, z0\.h
--.*: 044a0003 smin z3\.h, p0/m, z3\.h, z0\.h
--.*: 044a0080 smin z0\.h, p0/m, z0\.h, z4\.h
--.*: 044a0080 smin z0\.h, p0/m, z0\.h, z4\.h
--.*: 044a03e0 smin z0\.h, p0/m, z0\.h, z31\.h
--.*: 044a03e0 smin z0\.h, p0/m, z0\.h, z31\.h
--.*: 048a0000 smin z0\.s, p0/m, z0\.s, z0\.s
--.*: 048a0000 smin z0\.s, p0/m, z0\.s, z0\.s
--.*: 048a0001 smin z1\.s, p0/m, z1\.s, z0\.s
--.*: 048a0001 smin z1\.s, p0/m, z1\.s, z0\.s
--.*: 048a001f smin z31\.s, p0/m, z31\.s, z0\.s
--.*: 048a001f smin z31\.s, p0/m, z31\.s, z0\.s
--.*: 048a0800 smin z0\.s, p2/m, z0\.s, z0\.s
--.*: 048a0800 smin z0\.s, p2/m, z0\.s, z0\.s
--.*: 048a1c00 smin z0\.s, p7/m, z0\.s, z0\.s
--.*: 048a1c00 smin z0\.s, p7/m, z0\.s, z0\.s
--.*: 048a0003 smin z3\.s, p0/m, z3\.s, z0\.s
--.*: 048a0003 smin z3\.s, p0/m, z3\.s, z0\.s
--.*: 048a0080 smin z0\.s, p0/m, z0\.s, z4\.s
--.*: 048a0080 smin z0\.s, p0/m, z0\.s, z4\.s
--.*: 048a03e0 smin z0\.s, p0/m, z0\.s, z31\.s
--.*: 048a03e0 smin z0\.s, p0/m, z0\.s, z31\.s
--.*: 04ca0000 smin z0\.d, p0/m, z0\.d, z0\.d
--.*: 04ca0000 smin z0\.d, p0/m, z0\.d, z0\.d
--.*: 04ca0001 smin z1\.d, p0/m, z1\.d, z0\.d
--.*: 04ca0001 smin z1\.d, p0/m, z1\.d, z0\.d
--.*: 04ca001f smin z31\.d, p0/m, z31\.d, z0\.d
--.*: 04ca001f smin z31\.d, p0/m, z31\.d, z0\.d
--.*: 04ca0800 smin z0\.d, p2/m, z0\.d, z0\.d
--.*: 04ca0800 smin z0\.d, p2/m, z0\.d, z0\.d
--.*: 04ca1c00 smin z0\.d, p7/m, z0\.d, z0\.d
--.*: 04ca1c00 smin z0\.d, p7/m, z0\.d, z0\.d
--.*: 04ca0003 smin z3\.d, p0/m, z3\.d, z0\.d
--.*: 04ca0003 smin z3\.d, p0/m, z3\.d, z0\.d
--.*: 04ca0080 smin z0\.d, p0/m, z0\.d, z4\.d
--.*: 04ca0080 smin z0\.d, p0/m, z0\.d, z4\.d
--.*: 04ca03e0 smin z0\.d, p0/m, z0\.d, z31\.d
--.*: 04ca03e0 smin z0\.d, p0/m, z0\.d, z31\.d
--.*: 040a2000 sminv b0, p0, z0\.b
--.*: 040a2000 sminv b0, p0, z0\.b
--.*: 040a2001 sminv b1, p0, z0\.b
--.*: 040a2001 sminv b1, p0, z0\.b
--.*: 040a201f sminv b31, p0, z0\.b
--.*: 040a201f sminv b31, p0, z0\.b
--.*: 040a2800 sminv b0, p2, z0\.b
--.*: 040a2800 sminv b0, p2, z0\.b
--.*: 040a3c00 sminv b0, p7, z0\.b
--.*: 040a3c00 sminv b0, p7, z0\.b
--.*: 040a2060 sminv b0, p0, z3\.b
--.*: 040a2060 sminv b0, p0, z3\.b
--.*: 040a23e0 sminv b0, p0, z31\.b
--.*: 040a23e0 sminv b0, p0, z31\.b
--.*: 044a2000 sminv h0, p0, z0\.h
--.*: 044a2000 sminv h0, p0, z0\.h
--.*: 044a2001 sminv h1, p0, z0\.h
--.*: 044a2001 sminv h1, p0, z0\.h
--.*: 044a201f sminv h31, p0, z0\.h
--.*: 044a201f sminv h31, p0, z0\.h
--.*: 044a2800 sminv h0, p2, z0\.h
--.*: 044a2800 sminv h0, p2, z0\.h
--.*: 044a3c00 sminv h0, p7, z0\.h
--.*: 044a3c00 sminv h0, p7, z0\.h
--.*: 044a2060 sminv h0, p0, z3\.h
--.*: 044a2060 sminv h0, p0, z3\.h
--.*: 044a23e0 sminv h0, p0, z31\.h
--.*: 044a23e0 sminv h0, p0, z31\.h
--.*: 048a2000 sminv s0, p0, z0\.s
--.*: 048a2000 sminv s0, p0, z0\.s
--.*: 048a2001 sminv s1, p0, z0\.s
--.*: 048a2001 sminv s1, p0, z0\.s
--.*: 048a201f sminv s31, p0, z0\.s
--.*: 048a201f sminv s31, p0, z0\.s
--.*: 048a2800 sminv s0, p2, z0\.s
--.*: 048a2800 sminv s0, p2, z0\.s
--.*: 048a3c00 sminv s0, p7, z0\.s
--.*: 048a3c00 sminv s0, p7, z0\.s
--.*: 048a2060 sminv s0, p0, z3\.s
--.*: 048a2060 sminv s0, p0, z3\.s
--.*: 048a23e0 sminv s0, p0, z31\.s
--.*: 048a23e0 sminv s0, p0, z31\.s
--.*: 04ca2000 sminv d0, p0, z0\.d
--.*: 04ca2000 sminv d0, p0, z0\.d
--.*: 04ca2001 sminv d1, p0, z0\.d
--.*: 04ca2001 sminv d1, p0, z0\.d
--.*: 04ca201f sminv d31, p0, z0\.d
--.*: 04ca201f sminv d31, p0, z0\.d
--.*: 04ca2800 sminv d0, p2, z0\.d
--.*: 04ca2800 sminv d0, p2, z0\.d
--.*: 04ca3c00 sminv d0, p7, z0\.d
--.*: 04ca3c00 sminv d0, p7, z0\.d
--.*: 04ca2060 sminv d0, p0, z3\.d
--.*: 04ca2060 sminv d0, p0, z3\.d
--.*: 04ca23e0 sminv d0, p0, z31\.d
--.*: 04ca23e0 sminv d0, p0, z31\.d
--.*: 04120000 smulh z0\.b, p0/m, z0\.b, z0\.b
--.*: 04120000 smulh z0\.b, p0/m, z0\.b, z0\.b
--.*: 04120001 smulh z1\.b, p0/m, z1\.b, z0\.b
--.*: 04120001 smulh z1\.b, p0/m, z1\.b, z0\.b
--.*: 0412001f smulh z31\.b, p0/m, z31\.b, z0\.b
--.*: 0412001f smulh z31\.b, p0/m, z31\.b, z0\.b
--.*: 04120800 smulh z0\.b, p2/m, z0\.b, z0\.b
--.*: 04120800 smulh z0\.b, p2/m, z0\.b, z0\.b
--.*: 04121c00 smulh z0\.b, p7/m, z0\.b, z0\.b
--.*: 04121c00 smulh z0\.b, p7/m, z0\.b, z0\.b
--.*: 04120003 smulh z3\.b, p0/m, z3\.b, z0\.b
--.*: 04120003 smulh z3\.b, p0/m, z3\.b, z0\.b
--.*: 04120080 smulh z0\.b, p0/m, z0\.b, z4\.b
--.*: 04120080 smulh z0\.b, p0/m, z0\.b, z4\.b
--.*: 041203e0 smulh z0\.b, p0/m, z0\.b, z31\.b
--.*: 041203e0 smulh z0\.b, p0/m, z0\.b, z31\.b
--.*: 04520000 smulh z0\.h, p0/m, z0\.h, z0\.h
--.*: 04520000 smulh z0\.h, p0/m, z0\.h, z0\.h
--.*: 04520001 smulh z1\.h, p0/m, z1\.h, z0\.h
--.*: 04520001 smulh z1\.h, p0/m, z1\.h, z0\.h
--.*: 0452001f smulh z31\.h, p0/m, z31\.h, z0\.h
--.*: 0452001f smulh z31\.h, p0/m, z31\.h, z0\.h
--.*: 04520800 smulh z0\.h, p2/m, z0\.h, z0\.h
--.*: 04520800 smulh z0\.h, p2/m, z0\.h, z0\.h
--.*: 04521c00 smulh z0\.h, p7/m, z0\.h, z0\.h
--.*: 04521c00 smulh z0\.h, p7/m, z0\.h, z0\.h
--.*: 04520003 smulh z3\.h, p0/m, z3\.h, z0\.h
--.*: 04520003 smulh z3\.h, p0/m, z3\.h, z0\.h
--.*: 04520080 smulh z0\.h, p0/m, z0\.h, z4\.h
--.*: 04520080 smulh z0\.h, p0/m, z0\.h, z4\.h
--.*: 045203e0 smulh z0\.h, p0/m, z0\.h, z31\.h
--.*: 045203e0 smulh z0\.h, p0/m, z0\.h, z31\.h
--.*: 04920000 smulh z0\.s, p0/m, z0\.s, z0\.s
--.*: 04920000 smulh z0\.s, p0/m, z0\.s, z0\.s
--.*: 04920001 smulh z1\.s, p0/m, z1\.s, z0\.s
--.*: 04920001 smulh z1\.s, p0/m, z1\.s, z0\.s
--.*: 0492001f smulh z31\.s, p0/m, z31\.s, z0\.s
--.*: 0492001f smulh z31\.s, p0/m, z31\.s, z0\.s
--.*: 04920800 smulh z0\.s, p2/m, z0\.s, z0\.s
--.*: 04920800 smulh z0\.s, p2/m, z0\.s, z0\.s
--.*: 04921c00 smulh z0\.s, p7/m, z0\.s, z0\.s
--.*: 04921c00 smulh z0\.s, p7/m, z0\.s, z0\.s
--.*: 04920003 smulh z3\.s, p0/m, z3\.s, z0\.s
--.*: 04920003 smulh z3\.s, p0/m, z3\.s, z0\.s
--.*: 04920080 smulh z0\.s, p0/m, z0\.s, z4\.s
--.*: 04920080 smulh z0\.s, p0/m, z0\.s, z4\.s
--.*: 049203e0 smulh z0\.s, p0/m, z0\.s, z31\.s
--.*: 049203e0 smulh z0\.s, p0/m, z0\.s, z31\.s
--.*: 04d20000 smulh z0\.d, p0/m, z0\.d, z0\.d
--.*: 04d20000 smulh z0\.d, p0/m, z0\.d, z0\.d
--.*: 04d20001 smulh z1\.d, p0/m, z1\.d, z0\.d
--.*: 04d20001 smulh z1\.d, p0/m, z1\.d, z0\.d
--.*: 04d2001f smulh z31\.d, p0/m, z31\.d, z0\.d
--.*: 04d2001f smulh z31\.d, p0/m, z31\.d, z0\.d
--.*: 04d20800 smulh z0\.d, p2/m, z0\.d, z0\.d
--.*: 04d20800 smulh z0\.d, p2/m, z0\.d, z0\.d
--.*: 04d21c00 smulh z0\.d, p7/m, z0\.d, z0\.d
--.*: 04d21c00 smulh z0\.d, p7/m, z0\.d, z0\.d
--.*: 04d20003 smulh z3\.d, p0/m, z3\.d, z0\.d
--.*: 04d20003 smulh z3\.d, p0/m, z3\.d, z0\.d
--.*: 04d20080 smulh z0\.d, p0/m, z0\.d, z4\.d
--.*: 04d20080 smulh z0\.d, p0/m, z0\.d, z4\.d
--.*: 04d203e0 smulh z0\.d, p0/m, z0\.d, z31\.d
--.*: 04d203e0 smulh z0\.d, p0/m, z0\.d, z31\.d
--.*: 052c8000 splice z0\.b, p0, z0\.b, z0\.b
--.*: 052c8000 splice z0\.b, p0, z0\.b, z0\.b
--.*: 052c8001 splice z1\.b, p0, z1\.b, z0\.b
--.*: 052c8001 splice z1\.b, p0, z1\.b, z0\.b
--.*: 052c801f splice z31\.b, p0, z31\.b, z0\.b
--.*: 052c801f splice z31\.b, p0, z31\.b, z0\.b
--.*: 052c8800 splice z0\.b, p2, z0\.b, z0\.b
--.*: 052c8800 splice z0\.b, p2, z0\.b, z0\.b
--.*: 052c9c00 splice z0\.b, p7, z0\.b, z0\.b
--.*: 052c9c00 splice z0\.b, p7, z0\.b, z0\.b
--.*: 052c8003 splice z3\.b, p0, z3\.b, z0\.b
--.*: 052c8003 splice z3\.b, p0, z3\.b, z0\.b
--.*: 052c8080 splice z0\.b, p0, z0\.b, z4\.b
--.*: 052c8080 splice z0\.b, p0, z0\.b, z4\.b
--.*: 052c83e0 splice z0\.b, p0, z0\.b, z31\.b
--.*: 052c83e0 splice z0\.b, p0, z0\.b, z31\.b
--.*: 056c8000 splice z0\.h, p0, z0\.h, z0\.h
--.*: 056c8000 splice z0\.h, p0, z0\.h, z0\.h
--.*: 056c8001 splice z1\.h, p0, z1\.h, z0\.h
--.*: 056c8001 splice z1\.h, p0, z1\.h, z0\.h
--.*: 056c801f splice z31\.h, p0, z31\.h, z0\.h
--.*: 056c801f splice z31\.h, p0, z31\.h, z0\.h
--.*: 056c8800 splice z0\.h, p2, z0\.h, z0\.h
--.*: 056c8800 splice z0\.h, p2, z0\.h, z0\.h
--.*: 056c9c00 splice z0\.h, p7, z0\.h, z0\.h
--.*: 056c9c00 splice z0\.h, p7, z0\.h, z0\.h
--.*: 056c8003 splice z3\.h, p0, z3\.h, z0\.h
--.*: 056c8003 splice z3\.h, p0, z3\.h, z0\.h
--.*: 056c8080 splice z0\.h, p0, z0\.h, z4\.h
--.*: 056c8080 splice z0\.h, p0, z0\.h, z4\.h
--.*: 056c83e0 splice z0\.h, p0, z0\.h, z31\.h
--.*: 056c83e0 splice z0\.h, p0, z0\.h, z31\.h
--.*: 05ac8000 splice z0\.s, p0, z0\.s, z0\.s
--.*: 05ac8000 splice z0\.s, p0, z0\.s, z0\.s
--.*: 05ac8001 splice z1\.s, p0, z1\.s, z0\.s
--.*: 05ac8001 splice z1\.s, p0, z1\.s, z0\.s
--.*: 05ac801f splice z31\.s, p0, z31\.s, z0\.s
--.*: 05ac801f splice z31\.s, p0, z31\.s, z0\.s
--.*: 05ac8800 splice z0\.s, p2, z0\.s, z0\.s
--.*: 05ac8800 splice z0\.s, p2, z0\.s, z0\.s
--.*: 05ac9c00 splice z0\.s, p7, z0\.s, z0\.s
--.*: 05ac9c00 splice z0\.s, p7, z0\.s, z0\.s
--.*: 05ac8003 splice z3\.s, p0, z3\.s, z0\.s
--.*: 05ac8003 splice z3\.s, p0, z3\.s, z0\.s
--.*: 05ac8080 splice z0\.s, p0, z0\.s, z4\.s
--.*: 05ac8080 splice z0\.s, p0, z0\.s, z4\.s
--.*: 05ac83e0 splice z0\.s, p0, z0\.s, z31\.s
--.*: 05ac83e0 splice z0\.s, p0, z0\.s, z31\.s
--.*: 05ec8000 splice z0\.d, p0, z0\.d, z0\.d
--.*: 05ec8000 splice z0\.d, p0, z0\.d, z0\.d
--.*: 05ec8001 splice z1\.d, p0, z1\.d, z0\.d
--.*: 05ec8001 splice z1\.d, p0, z1\.d, z0\.d
--.*: 05ec801f splice z31\.d, p0, z31\.d, z0\.d
--.*: 05ec801f splice z31\.d, p0, z31\.d, z0\.d
--.*: 05ec8800 splice z0\.d, p2, z0\.d, z0\.d
--.*: 05ec8800 splice z0\.d, p2, z0\.d, z0\.d
--.*: 05ec9c00 splice z0\.d, p7, z0\.d, z0\.d
--.*: 05ec9c00 splice z0\.d, p7, z0\.d, z0\.d
--.*: 05ec8003 splice z3\.d, p0, z3\.d, z0\.d
--.*: 05ec8003 splice z3\.d, p0, z3\.d, z0\.d
--.*: 05ec8080 splice z0\.d, p0, z0\.d, z4\.d
--.*: 05ec8080 splice z0\.d, p0, z0\.d, z4\.d
--.*: 05ec83e0 splice z0\.d, p0, z0\.d, z31\.d
--.*: 05ec83e0 splice z0\.d, p0, z0\.d, z31\.d
--.*: 04201000 sqadd z0\.b, z0\.b, z0\.b
--.*: 04201000 sqadd z0\.b, z0\.b, z0\.b
--.*: 04201001 sqadd z1\.b, z0\.b, z0\.b
--.*: 04201001 sqadd z1\.b, z0\.b, z0\.b
--.*: 0420101f sqadd z31\.b, z0\.b, z0\.b
--.*: 0420101f sqadd z31\.b, z0\.b, z0\.b
--.*: 04201040 sqadd z0\.b, z2\.b, z0\.b
--.*: 04201040 sqadd z0\.b, z2\.b, z0\.b
--.*: 042013e0 sqadd z0\.b, z31\.b, z0\.b
--.*: 042013e0 sqadd z0\.b, z31\.b, z0\.b
--.*: 04231000 sqadd z0\.b, z0\.b, z3\.b
--.*: 04231000 sqadd z0\.b, z0\.b, z3\.b
--.*: 043f1000 sqadd z0\.b, z0\.b, z31\.b
--.*: 043f1000 sqadd z0\.b, z0\.b, z31\.b
--.*: 04601000 sqadd z0\.h, z0\.h, z0\.h
--.*: 04601000 sqadd z0\.h, z0\.h, z0\.h
--.*: 04601001 sqadd z1\.h, z0\.h, z0\.h
--.*: 04601001 sqadd z1\.h, z0\.h, z0\.h
--.*: 0460101f sqadd z31\.h, z0\.h, z0\.h
--.*: 0460101f sqadd z31\.h, z0\.h, z0\.h
--.*: 04601040 sqadd z0\.h, z2\.h, z0\.h
--.*: 04601040 sqadd z0\.h, z2\.h, z0\.h
--.*: 046013e0 sqadd z0\.h, z31\.h, z0\.h
--.*: 046013e0 sqadd z0\.h, z31\.h, z0\.h
--.*: 04631000 sqadd z0\.h, z0\.h, z3\.h
--.*: 04631000 sqadd z0\.h, z0\.h, z3\.h
--.*: 047f1000 sqadd z0\.h, z0\.h, z31\.h
--.*: 047f1000 sqadd z0\.h, z0\.h, z31\.h
--.*: 04a01000 sqadd z0\.s, z0\.s, z0\.s
--.*: 04a01000 sqadd z0\.s, z0\.s, z0\.s
--.*: 04a01001 sqadd z1\.s, z0\.s, z0\.s
--.*: 04a01001 sqadd z1\.s, z0\.s, z0\.s
--.*: 04a0101f sqadd z31\.s, z0\.s, z0\.s
--.*: 04a0101f sqadd z31\.s, z0\.s, z0\.s
--.*: 04a01040 sqadd z0\.s, z2\.s, z0\.s
--.*: 04a01040 sqadd z0\.s, z2\.s, z0\.s
--.*: 04a013e0 sqadd z0\.s, z31\.s, z0\.s
--.*: 04a013e0 sqadd z0\.s, z31\.s, z0\.s
--.*: 04a31000 sqadd z0\.s, z0\.s, z3\.s
--.*: 04a31000 sqadd z0\.s, z0\.s, z3\.s
--.*: 04bf1000 sqadd z0\.s, z0\.s, z31\.s
--.*: 04bf1000 sqadd z0\.s, z0\.s, z31\.s
--.*: 04e01000 sqadd z0\.d, z0\.d, z0\.d
--.*: 04e01000 sqadd z0\.d, z0\.d, z0\.d
--.*: 04e01001 sqadd z1\.d, z0\.d, z0\.d
--.*: 04e01001 sqadd z1\.d, z0\.d, z0\.d
--.*: 04e0101f sqadd z31\.d, z0\.d, z0\.d
--.*: 04e0101f sqadd z31\.d, z0\.d, z0\.d
--.*: 04e01040 sqadd z0\.d, z2\.d, z0\.d
--.*: 04e01040 sqadd z0\.d, z2\.d, z0\.d
--.*: 04e013e0 sqadd z0\.d, z31\.d, z0\.d
--.*: 04e013e0 sqadd z0\.d, z31\.d, z0\.d
--.*: 04e31000 sqadd z0\.d, z0\.d, z3\.d
--.*: 04e31000 sqadd z0\.d, z0\.d, z3\.d
--.*: 04ff1000 sqadd z0\.d, z0\.d, z31\.d
--.*: 04ff1000 sqadd z0\.d, z0\.d, z31\.d
--.*: 2524c000 sqadd z0\.b, z0\.b, #0
--.*: 2524c000 sqadd z0\.b, z0\.b, #0
--.*: 2524c000 sqadd z0\.b, z0\.b, #0
--.*: 2524c001 sqadd z1\.b, z1\.b, #0
--.*: 2524c001 sqadd z1\.b, z1\.b, #0
--.*: 2524c001 sqadd z1\.b, z1\.b, #0
--.*: 2524c01f sqadd z31\.b, z31\.b, #0
--.*: 2524c01f sqadd z31\.b, z31\.b, #0
--.*: 2524c01f sqadd z31\.b, z31\.b, #0
--.*: 2524c002 sqadd z2\.b, z2\.b, #0
--.*: 2524c002 sqadd z2\.b, z2\.b, #0
--.*: 2524c002 sqadd z2\.b, z2\.b, #0
--.*: 2524cfe0 sqadd z0\.b, z0\.b, #127
--.*: 2524cfe0 sqadd z0\.b, z0\.b, #127
--.*: 2524cfe0 sqadd z0\.b, z0\.b, #127
--.*: 2524d000 sqadd z0\.b, z0\.b, #128
--.*: 2524d000 sqadd z0\.b, z0\.b, #128
--.*: 2524d000 sqadd z0\.b, z0\.b, #128
--.*: 2524d020 sqadd z0\.b, z0\.b, #129
--.*: 2524d020 sqadd z0\.b, z0\.b, #129
--.*: 2524d020 sqadd z0\.b, z0\.b, #129
--.*: 2524dfe0 sqadd z0\.b, z0\.b, #255
--.*: 2524dfe0 sqadd z0\.b, z0\.b, #255
--.*: 2524dfe0 sqadd z0\.b, z0\.b, #255
--.*: 2564c000 sqadd z0\.h, z0\.h, #0
--.*: 2564c000 sqadd z0\.h, z0\.h, #0
--.*: 2564c000 sqadd z0\.h, z0\.h, #0
--.*: 2564c001 sqadd z1\.h, z1\.h, #0
--.*: 2564c001 sqadd z1\.h, z1\.h, #0
--.*: 2564c001 sqadd z1\.h, z1\.h, #0
--.*: 2564c01f sqadd z31\.h, z31\.h, #0
--.*: 2564c01f sqadd z31\.h, z31\.h, #0
--.*: 2564c01f sqadd z31\.h, z31\.h, #0
--.*: 2564c002 sqadd z2\.h, z2\.h, #0
--.*: 2564c002 sqadd z2\.h, z2\.h, #0
--.*: 2564c002 sqadd z2\.h, z2\.h, #0
--.*: 2564cfe0 sqadd z0\.h, z0\.h, #127
--.*: 2564cfe0 sqadd z0\.h, z0\.h, #127
--.*: 2564cfe0 sqadd z0\.h, z0\.h, #127
--.*: 2564d000 sqadd z0\.h, z0\.h, #128
--.*: 2564d000 sqadd z0\.h, z0\.h, #128
--.*: 2564d000 sqadd z0\.h, z0\.h, #128
--.*: 2564d020 sqadd z0\.h, z0\.h, #129
--.*: 2564d020 sqadd z0\.h, z0\.h, #129
--.*: 2564d020 sqadd z0\.h, z0\.h, #129
--.*: 2564dfe0 sqadd z0\.h, z0\.h, #255
--.*: 2564dfe0 sqadd z0\.h, z0\.h, #255
--.*: 2564dfe0 sqadd z0\.h, z0\.h, #255
--.*: 2564e000 sqadd z0\.h, z0\.h, #0, lsl #8
--.*: 2564e000 sqadd z0\.h, z0\.h, #0, lsl #8
--.*: 2564efe0 sqadd z0\.h, z0\.h, #32512
--.*: 2564efe0 sqadd z0\.h, z0\.h, #32512
--.*: 2564efe0 sqadd z0\.h, z0\.h, #32512
--.*: 2564efe0 sqadd z0\.h, z0\.h, #32512
--.*: 2564f000 sqadd z0\.h, z0\.h, #32768
--.*: 2564f000 sqadd z0\.h, z0\.h, #32768
--.*: 2564f000 sqadd z0\.h, z0\.h, #32768
--.*: 2564f000 sqadd z0\.h, z0\.h, #32768
--.*: 2564f020 sqadd z0\.h, z0\.h, #33024
--.*: 2564f020 sqadd z0\.h, z0\.h, #33024
--.*: 2564f020 sqadd z0\.h, z0\.h, #33024
--.*: 2564f020 sqadd z0\.h, z0\.h, #33024
--.*: 2564ffe0 sqadd z0\.h, z0\.h, #65280
--.*: 2564ffe0 sqadd z0\.h, z0\.h, #65280
--.*: 2564ffe0 sqadd z0\.h, z0\.h, #65280
--.*: 2564ffe0 sqadd z0\.h, z0\.h, #65280
--.*: 25a4c000 sqadd z0\.s, z0\.s, #0
--.*: 25a4c000 sqadd z0\.s, z0\.s, #0
--.*: 25a4c000 sqadd z0\.s, z0\.s, #0
--.*: 25a4c001 sqadd z1\.s, z1\.s, #0
--.*: 25a4c001 sqadd z1\.s, z1\.s, #0
--.*: 25a4c001 sqadd z1\.s, z1\.s, #0
--.*: 25a4c01f sqadd z31\.s, z31\.s, #0
--.*: 25a4c01f sqadd z31\.s, z31\.s, #0
--.*: 25a4c01f sqadd z31\.s, z31\.s, #0
--.*: 25a4c002 sqadd z2\.s, z2\.s, #0
--.*: 25a4c002 sqadd z2\.s, z2\.s, #0
--.*: 25a4c002 sqadd z2\.s, z2\.s, #0
--.*: 25a4cfe0 sqadd z0\.s, z0\.s, #127
--.*: 25a4cfe0 sqadd z0\.s, z0\.s, #127
--.*: 25a4cfe0 sqadd z0\.s, z0\.s, #127
--.*: 25a4d000 sqadd z0\.s, z0\.s, #128
--.*: 25a4d000 sqadd z0\.s, z0\.s, #128
--.*: 25a4d000 sqadd z0\.s, z0\.s, #128
--.*: 25a4d020 sqadd z0\.s, z0\.s, #129
--.*: 25a4d020 sqadd z0\.s, z0\.s, #129
--.*: 25a4d020 sqadd z0\.s, z0\.s, #129
--.*: 25a4dfe0 sqadd z0\.s, z0\.s, #255
--.*: 25a4dfe0 sqadd z0\.s, z0\.s, #255
--.*: 25a4dfe0 sqadd z0\.s, z0\.s, #255
--.*: 25a4e000 sqadd z0\.s, z0\.s, #0, lsl #8
--.*: 25a4e000 sqadd z0\.s, z0\.s, #0, lsl #8
--.*: 25a4efe0 sqadd z0\.s, z0\.s, #32512
--.*: 25a4efe0 sqadd z0\.s, z0\.s, #32512
--.*: 25a4efe0 sqadd z0\.s, z0\.s, #32512
--.*: 25a4efe0 sqadd z0\.s, z0\.s, #32512
--.*: 25a4f000 sqadd z0\.s, z0\.s, #32768
--.*: 25a4f000 sqadd z0\.s, z0\.s, #32768
--.*: 25a4f000 sqadd z0\.s, z0\.s, #32768
--.*: 25a4f000 sqadd z0\.s, z0\.s, #32768
--.*: 25a4f020 sqadd z0\.s, z0\.s, #33024
--.*: 25a4f020 sqadd z0\.s, z0\.s, #33024
--.*: 25a4f020 sqadd z0\.s, z0\.s, #33024
--.*: 25a4f020 sqadd z0\.s, z0\.s, #33024
--.*: 25a4ffe0 sqadd z0\.s, z0\.s, #65280
--.*: 25a4ffe0 sqadd z0\.s, z0\.s, #65280
--.*: 25a4ffe0 sqadd z0\.s, z0\.s, #65280
--.*: 25a4ffe0 sqadd z0\.s, z0\.s, #65280
--.*: 25e4c000 sqadd z0\.d, z0\.d, #0
--.*: 25e4c000 sqadd z0\.d, z0\.d, #0
--.*: 25e4c000 sqadd z0\.d, z0\.d, #0
--.*: 25e4c001 sqadd z1\.d, z1\.d, #0
--.*: 25e4c001 sqadd z1\.d, z1\.d, #0
--.*: 25e4c001 sqadd z1\.d, z1\.d, #0
--.*: 25e4c01f sqadd z31\.d, z31\.d, #0
--.*: 25e4c01f sqadd z31\.d, z31\.d, #0
--.*: 25e4c01f sqadd z31\.d, z31\.d, #0
--.*: 25e4c002 sqadd z2\.d, z2\.d, #0
--.*: 25e4c002 sqadd z2\.d, z2\.d, #0
--.*: 25e4c002 sqadd z2\.d, z2\.d, #0
--.*: 25e4cfe0 sqadd z0\.d, z0\.d, #127
--.*: 25e4cfe0 sqadd z0\.d, z0\.d, #127
--.*: 25e4cfe0 sqadd z0\.d, z0\.d, #127
--.*: 25e4d000 sqadd z0\.d, z0\.d, #128
--.*: 25e4d000 sqadd z0\.d, z0\.d, #128
--.*: 25e4d000 sqadd z0\.d, z0\.d, #128
--.*: 25e4d020 sqadd z0\.d, z0\.d, #129
--.*: 25e4d020 sqadd z0\.d, z0\.d, #129
--.*: 25e4d020 sqadd z0\.d, z0\.d, #129
--.*: 25e4dfe0 sqadd z0\.d, z0\.d, #255
--.*: 25e4dfe0 sqadd z0\.d, z0\.d, #255
--.*: 25e4dfe0 sqadd z0\.d, z0\.d, #255
--.*: 25e4e000 sqadd z0\.d, z0\.d, #0, lsl #8
--.*: 25e4e000 sqadd z0\.d, z0\.d, #0, lsl #8
--.*: 25e4efe0 sqadd z0\.d, z0\.d, #32512
--.*: 25e4efe0 sqadd z0\.d, z0\.d, #32512
--.*: 25e4efe0 sqadd z0\.d, z0\.d, #32512
--.*: 25e4efe0 sqadd z0\.d, z0\.d, #32512
--.*: 25e4f000 sqadd z0\.d, z0\.d, #32768
--.*: 25e4f000 sqadd z0\.d, z0\.d, #32768
--.*: 25e4f000 sqadd z0\.d, z0\.d, #32768
--.*: 25e4f000 sqadd z0\.d, z0\.d, #32768
--.*: 25e4f020 sqadd z0\.d, z0\.d, #33024
--.*: 25e4f020 sqadd z0\.d, z0\.d, #33024
--.*: 25e4f020 sqadd z0\.d, z0\.d, #33024
--.*: 25e4f020 sqadd z0\.d, z0\.d, #33024
--.*: 25e4ffe0 sqadd z0\.d, z0\.d, #65280
--.*: 25e4ffe0 sqadd z0\.d, z0\.d, #65280
--.*: 25e4ffe0 sqadd z0\.d, z0\.d, #65280
--.*: 25e4ffe0 sqadd z0\.d, z0\.d, #65280
--.*: 0430f800 sqdecb x0, pow2
--.*: 0430f800 sqdecb x0, pow2
--.*: 0430f800 sqdecb x0, pow2
--.*: 0430f801 sqdecb x1, pow2
--.*: 0430f801 sqdecb x1, pow2
--.*: 0430f801 sqdecb x1, pow2
--.*: 0430f81f sqdecb xzr, pow2
--.*: 0430f81f sqdecb xzr, pow2
--.*: 0430f81f sqdecb xzr, pow2
--.*: 0430f820 sqdecb x0, vl1
--.*: 0430f820 sqdecb x0, vl1
--.*: 0430f820 sqdecb x0, vl1
--.*: 0430f840 sqdecb x0, vl2
--.*: 0430f840 sqdecb x0, vl2
--.*: 0430f840 sqdecb x0, vl2
--.*: 0430f860 sqdecb x0, vl3
--.*: 0430f860 sqdecb x0, vl3
--.*: 0430f860 sqdecb x0, vl3
--.*: 0430f880 sqdecb x0, vl4
--.*: 0430f880 sqdecb x0, vl4
--.*: 0430f880 sqdecb x0, vl4
--.*: 0430f8a0 sqdecb x0, vl5
--.*: 0430f8a0 sqdecb x0, vl5
--.*: 0430f8a0 sqdecb x0, vl5
--.*: 0430f8c0 sqdecb x0, vl6
--.*: 0430f8c0 sqdecb x0, vl6
--.*: 0430f8c0 sqdecb x0, vl6
--.*: 0430f8e0 sqdecb x0, vl7
--.*: 0430f8e0 sqdecb x0, vl7
--.*: 0430f8e0 sqdecb x0, vl7
--.*: 0430f900 sqdecb x0, vl8
--.*: 0430f900 sqdecb x0, vl8
--.*: 0430f900 sqdecb x0, vl8
--.*: 0430f920 sqdecb x0, vl16
--.*: 0430f920 sqdecb x0, vl16
--.*: 0430f920 sqdecb x0, vl16
--.*: 0430f940 sqdecb x0, vl32
--.*: 0430f940 sqdecb x0, vl32
--.*: 0430f940 sqdecb x0, vl32
--.*: 0430f960 sqdecb x0, vl64
--.*: 0430f960 sqdecb x0, vl64
--.*: 0430f960 sqdecb x0, vl64
--.*: 0430f980 sqdecb x0, vl128
--.*: 0430f980 sqdecb x0, vl128
--.*: 0430f980 sqdecb x0, vl128
--.*: 0430f9a0 sqdecb x0, vl256
--.*: 0430f9a0 sqdecb x0, vl256
--.*: 0430f9a0 sqdecb x0, vl256
--.*: 0430f9c0 sqdecb x0, #14
--.*: 0430f9c0 sqdecb x0, #14
--.*: 0430f9c0 sqdecb x0, #14
--.*: 0430f9e0 sqdecb x0, #15
--.*: 0430f9e0 sqdecb x0, #15
--.*: 0430f9e0 sqdecb x0, #15
--.*: 0430fa00 sqdecb x0, #16
--.*: 0430fa00 sqdecb x0, #16
--.*: 0430fa00 sqdecb x0, #16
--.*: 0430fa20 sqdecb x0, #17
--.*: 0430fa20 sqdecb x0, #17
--.*: 0430fa20 sqdecb x0, #17
--.*: 0430fa40 sqdecb x0, #18
--.*: 0430fa40 sqdecb x0, #18
--.*: 0430fa40 sqdecb x0, #18
--.*: 0430fa60 sqdecb x0, #19
--.*: 0430fa60 sqdecb x0, #19
--.*: 0430fa60 sqdecb x0, #19
--.*: 0430fa80 sqdecb x0, #20
--.*: 0430fa80 sqdecb x0, #20
--.*: 0430fa80 sqdecb x0, #20
--.*: 0430faa0 sqdecb x0, #21
--.*: 0430faa0 sqdecb x0, #21
--.*: 0430faa0 sqdecb x0, #21
--.*: 0430fac0 sqdecb x0, #22
--.*: 0430fac0 sqdecb x0, #22
--.*: 0430fac0 sqdecb x0, #22
--.*: 0430fae0 sqdecb x0, #23
--.*: 0430fae0 sqdecb x0, #23
--.*: 0430fae0 sqdecb x0, #23
--.*: 0430fb00 sqdecb x0, #24
--.*: 0430fb00 sqdecb x0, #24
--.*: 0430fb00 sqdecb x0, #24
--.*: 0430fb20 sqdecb x0, #25
--.*: 0430fb20 sqdecb x0, #25
--.*: 0430fb20 sqdecb x0, #25
--.*: 0430fb40 sqdecb x0, #26
--.*: 0430fb40 sqdecb x0, #26
--.*: 0430fb40 sqdecb x0, #26
--.*: 0430fb60 sqdecb x0, #27
--.*: 0430fb60 sqdecb x0, #27
--.*: 0430fb60 sqdecb x0, #27
--.*: 0430fb80 sqdecb x0, #28
--.*: 0430fb80 sqdecb x0, #28
--.*: 0430fb80 sqdecb x0, #28
--.*: 0430fba0 sqdecb x0, mul4
--.*: 0430fba0 sqdecb x0, mul4
--.*: 0430fba0 sqdecb x0, mul4
--.*: 0430fbc0 sqdecb x0, mul3
--.*: 0430fbc0 sqdecb x0, mul3
--.*: 0430fbc0 sqdecb x0, mul3
--.*: 0430fbe0 sqdecb x0
--.*: 0430fbe0 sqdecb x0
--.*: 0430fbe0 sqdecb x0
--.*: 0430fbe0 sqdecb x0
--.*: 0437f800 sqdecb x0, pow2, mul #8
--.*: 0437f800 sqdecb x0, pow2, mul #8
--.*: 0438f800 sqdecb x0, pow2, mul #9
--.*: 0438f800 sqdecb x0, pow2, mul #9
--.*: 0439f800 sqdecb x0, pow2, mul #10
--.*: 0439f800 sqdecb x0, pow2, mul #10
--.*: 043ff800 sqdecb x0, pow2, mul #16
--.*: 043ff800 sqdecb x0, pow2, mul #16
--.*: 0420f800 sqdecb x0, w0, pow2
--.*: 0420f800 sqdecb x0, w0, pow2
--.*: 0420f800 sqdecb x0, w0, pow2
--.*: 0420f801 sqdecb x1, w1, pow2
--.*: 0420f801 sqdecb x1, w1, pow2
--.*: 0420f801 sqdecb x1, w1, pow2
--.*: 0420f81f sqdecb xzr, wzr, pow2
--.*: 0420f81f sqdecb xzr, wzr, pow2
--.*: 0420f81f sqdecb xzr, wzr, pow2
--.*: 0420f802 sqdecb x2, w2, pow2
--.*: 0420f802 sqdecb x2, w2, pow2
--.*: 0420f802 sqdecb x2, w2, pow2
--.*: 0420f820 sqdecb x0, w0, vl1
--.*: 0420f820 sqdecb x0, w0, vl1
--.*: 0420f820 sqdecb x0, w0, vl1
--.*: 0420f840 sqdecb x0, w0, vl2
--.*: 0420f840 sqdecb x0, w0, vl2
--.*: 0420f840 sqdecb x0, w0, vl2
--.*: 0420f860 sqdecb x0, w0, vl3
--.*: 0420f860 sqdecb x0, w0, vl3
--.*: 0420f860 sqdecb x0, w0, vl3
--.*: 0420f880 sqdecb x0, w0, vl4
--.*: 0420f880 sqdecb x0, w0, vl4
--.*: 0420f880 sqdecb x0, w0, vl4
--.*: 0420f8a0 sqdecb x0, w0, vl5
--.*: 0420f8a0 sqdecb x0, w0, vl5
--.*: 0420f8a0 sqdecb x0, w0, vl5
--.*: 0420f8c0 sqdecb x0, w0, vl6
--.*: 0420f8c0 sqdecb x0, w0, vl6
--.*: 0420f8c0 sqdecb x0, w0, vl6
--.*: 0420f8e0 sqdecb x0, w0, vl7
--.*: 0420f8e0 sqdecb x0, w0, vl7
--.*: 0420f8e0 sqdecb x0, w0, vl7
--.*: 0420f900 sqdecb x0, w0, vl8
--.*: 0420f900 sqdecb x0, w0, vl8
--.*: 0420f900 sqdecb x0, w0, vl8
--.*: 0420f920 sqdecb x0, w0, vl16
--.*: 0420f920 sqdecb x0, w0, vl16
--.*: 0420f920 sqdecb x0, w0, vl16
--.*: 0420f940 sqdecb x0, w0, vl32
--.*: 0420f940 sqdecb x0, w0, vl32
--.*: 0420f940 sqdecb x0, w0, vl32
--.*: 0420f960 sqdecb x0, w0, vl64
--.*: 0420f960 sqdecb x0, w0, vl64
--.*: 0420f960 sqdecb x0, w0, vl64
--.*: 0420f980 sqdecb x0, w0, vl128
--.*: 0420f980 sqdecb x0, w0, vl128
--.*: 0420f980 sqdecb x0, w0, vl128
--.*: 0420f9a0 sqdecb x0, w0, vl256
--.*: 0420f9a0 sqdecb x0, w0, vl256
--.*: 0420f9a0 sqdecb x0, w0, vl256
--.*: 0420f9c0 sqdecb x0, w0, #14
--.*: 0420f9c0 sqdecb x0, w0, #14
--.*: 0420f9c0 sqdecb x0, w0, #14
--.*: 0420f9e0 sqdecb x0, w0, #15
--.*: 0420f9e0 sqdecb x0, w0, #15
--.*: 0420f9e0 sqdecb x0, w0, #15
--.*: 0420fa00 sqdecb x0, w0, #16
--.*: 0420fa00 sqdecb x0, w0, #16
--.*: 0420fa00 sqdecb x0, w0, #16
--.*: 0420fa20 sqdecb x0, w0, #17
--.*: 0420fa20 sqdecb x0, w0, #17
--.*: 0420fa20 sqdecb x0, w0, #17
--.*: 0420fa40 sqdecb x0, w0, #18
--.*: 0420fa40 sqdecb x0, w0, #18
--.*: 0420fa40 sqdecb x0, w0, #18
--.*: 0420fa60 sqdecb x0, w0, #19
--.*: 0420fa60 sqdecb x0, w0, #19
--.*: 0420fa60 sqdecb x0, w0, #19
--.*: 0420fa80 sqdecb x0, w0, #20
--.*: 0420fa80 sqdecb x0, w0, #20
--.*: 0420fa80 sqdecb x0, w0, #20
--.*: 0420faa0 sqdecb x0, w0, #21
--.*: 0420faa0 sqdecb x0, w0, #21
--.*: 0420faa0 sqdecb x0, w0, #21
--.*: 0420fac0 sqdecb x0, w0, #22
--.*: 0420fac0 sqdecb x0, w0, #22
--.*: 0420fac0 sqdecb x0, w0, #22
--.*: 0420fae0 sqdecb x0, w0, #23
--.*: 0420fae0 sqdecb x0, w0, #23
--.*: 0420fae0 sqdecb x0, w0, #23
--.*: 0420fb00 sqdecb x0, w0, #24
--.*: 0420fb00 sqdecb x0, w0, #24
--.*: 0420fb00 sqdecb x0, w0, #24
--.*: 0420fb20 sqdecb x0, w0, #25
--.*: 0420fb20 sqdecb x0, w0, #25
--.*: 0420fb20 sqdecb x0, w0, #25
--.*: 0420fb40 sqdecb x0, w0, #26
--.*: 0420fb40 sqdecb x0, w0, #26
--.*: 0420fb40 sqdecb x0, w0, #26
--.*: 0420fb60 sqdecb x0, w0, #27
--.*: 0420fb60 sqdecb x0, w0, #27
--.*: 0420fb60 sqdecb x0, w0, #27
--.*: 0420fb80 sqdecb x0, w0, #28
--.*: 0420fb80 sqdecb x0, w0, #28
--.*: 0420fb80 sqdecb x0, w0, #28
--.*: 0420fba0 sqdecb x0, w0, mul4
--.*: 0420fba0 sqdecb x0, w0, mul4
--.*: 0420fba0 sqdecb x0, w0, mul4
--.*: 0420fbc0 sqdecb x0, w0, mul3
--.*: 0420fbc0 sqdecb x0, w0, mul3
--.*: 0420fbc0 sqdecb x0, w0, mul3
--.*: 0420fbe0 sqdecb x0, w0
--.*: 0420fbe0 sqdecb x0, w0
--.*: 0420fbe0 sqdecb x0, w0
--.*: 0420fbe0 sqdecb x0, w0
--.*: 0427f800 sqdecb x0, w0, pow2, mul #8
--.*: 0427f800 sqdecb x0, w0, pow2, mul #8
--.*: 0428f800 sqdecb x0, w0, pow2, mul #9
--.*: 0428f800 sqdecb x0, w0, pow2, mul #9
--.*: 0429f800 sqdecb x0, w0, pow2, mul #10
--.*: 0429f800 sqdecb x0, w0, pow2, mul #10
--.*: 042ff800 sqdecb x0, w0, pow2, mul #16
--.*: 042ff800 sqdecb x0, w0, pow2, mul #16
--.*: 04e0c800 sqdecd z0\.d, pow2
--.*: 04e0c800 sqdecd z0\.d, pow2
--.*: 04e0c800 sqdecd z0\.d, pow2
--.*: 04e0c801 sqdecd z1\.d, pow2
--.*: 04e0c801 sqdecd z1\.d, pow2
--.*: 04e0c801 sqdecd z1\.d, pow2
--.*: 04e0c81f sqdecd z31\.d, pow2
--.*: 04e0c81f sqdecd z31\.d, pow2
--.*: 04e0c81f sqdecd z31\.d, pow2
--.*: 04e0c820 sqdecd z0\.d, vl1
--.*: 04e0c820 sqdecd z0\.d, vl1
--.*: 04e0c820 sqdecd z0\.d, vl1
--.*: 04e0c840 sqdecd z0\.d, vl2
--.*: 04e0c840 sqdecd z0\.d, vl2
--.*: 04e0c840 sqdecd z0\.d, vl2
--.*: 04e0c860 sqdecd z0\.d, vl3
--.*: 04e0c860 sqdecd z0\.d, vl3
--.*: 04e0c860 sqdecd z0\.d, vl3
--.*: 04e0c880 sqdecd z0\.d, vl4
--.*: 04e0c880 sqdecd z0\.d, vl4
--.*: 04e0c880 sqdecd z0\.d, vl4
--.*: 04e0c8a0 sqdecd z0\.d, vl5
--.*: 04e0c8a0 sqdecd z0\.d, vl5
--.*: 04e0c8a0 sqdecd z0\.d, vl5
--.*: 04e0c8c0 sqdecd z0\.d, vl6
--.*: 04e0c8c0 sqdecd z0\.d, vl6
--.*: 04e0c8c0 sqdecd z0\.d, vl6
--.*: 04e0c8e0 sqdecd z0\.d, vl7
--.*: 04e0c8e0 sqdecd z0\.d, vl7
--.*: 04e0c8e0 sqdecd z0\.d, vl7
--.*: 04e0c900 sqdecd z0\.d, vl8
--.*: 04e0c900 sqdecd z0\.d, vl8
--.*: 04e0c900 sqdecd z0\.d, vl8
--.*: 04e0c920 sqdecd z0\.d, vl16
--.*: 04e0c920 sqdecd z0\.d, vl16
--.*: 04e0c920 sqdecd z0\.d, vl16
--.*: 04e0c940 sqdecd z0\.d, vl32
--.*: 04e0c940 sqdecd z0\.d, vl32
--.*: 04e0c940 sqdecd z0\.d, vl32
--.*: 04e0c960 sqdecd z0\.d, vl64
--.*: 04e0c960 sqdecd z0\.d, vl64
--.*: 04e0c960 sqdecd z0\.d, vl64
--.*: 04e0c980 sqdecd z0\.d, vl128
--.*: 04e0c980 sqdecd z0\.d, vl128
--.*: 04e0c980 sqdecd z0\.d, vl128
--.*: 04e0c9a0 sqdecd z0\.d, vl256
--.*: 04e0c9a0 sqdecd z0\.d, vl256
--.*: 04e0c9a0 sqdecd z0\.d, vl256
--.*: 04e0c9c0 sqdecd z0\.d, #14
--.*: 04e0c9c0 sqdecd z0\.d, #14
--.*: 04e0c9c0 sqdecd z0\.d, #14
--.*: 04e0c9e0 sqdecd z0\.d, #15
--.*: 04e0c9e0 sqdecd z0\.d, #15
--.*: 04e0c9e0 sqdecd z0\.d, #15
--.*: 04e0ca00 sqdecd z0\.d, #16
--.*: 04e0ca00 sqdecd z0\.d, #16
--.*: 04e0ca00 sqdecd z0\.d, #16
--.*: 04e0ca20 sqdecd z0\.d, #17
--.*: 04e0ca20 sqdecd z0\.d, #17
--.*: 04e0ca20 sqdecd z0\.d, #17
--.*: 04e0ca40 sqdecd z0\.d, #18
--.*: 04e0ca40 sqdecd z0\.d, #18
--.*: 04e0ca40 sqdecd z0\.d, #18
--.*: 04e0ca60 sqdecd z0\.d, #19
--.*: 04e0ca60 sqdecd z0\.d, #19
--.*: 04e0ca60 sqdecd z0\.d, #19
--.*: 04e0ca80 sqdecd z0\.d, #20
--.*: 04e0ca80 sqdecd z0\.d, #20
--.*: 04e0ca80 sqdecd z0\.d, #20
--.*: 04e0caa0 sqdecd z0\.d, #21
--.*: 04e0caa0 sqdecd z0\.d, #21
--.*: 04e0caa0 sqdecd z0\.d, #21
--.*: 04e0cac0 sqdecd z0\.d, #22
--.*: 04e0cac0 sqdecd z0\.d, #22
--.*: 04e0cac0 sqdecd z0\.d, #22
--.*: 04e0cae0 sqdecd z0\.d, #23
--.*: 04e0cae0 sqdecd z0\.d, #23
--.*: 04e0cae0 sqdecd z0\.d, #23
--.*: 04e0cb00 sqdecd z0\.d, #24
--.*: 04e0cb00 sqdecd z0\.d, #24
--.*: 04e0cb00 sqdecd z0\.d, #24
--.*: 04e0cb20 sqdecd z0\.d, #25
--.*: 04e0cb20 sqdecd z0\.d, #25
--.*: 04e0cb20 sqdecd z0\.d, #25
--.*: 04e0cb40 sqdecd z0\.d, #26
--.*: 04e0cb40 sqdecd z0\.d, #26
--.*: 04e0cb40 sqdecd z0\.d, #26
--.*: 04e0cb60 sqdecd z0\.d, #27
--.*: 04e0cb60 sqdecd z0\.d, #27
--.*: 04e0cb60 sqdecd z0\.d, #27
--.*: 04e0cb80 sqdecd z0\.d, #28
--.*: 04e0cb80 sqdecd z0\.d, #28
--.*: 04e0cb80 sqdecd z0\.d, #28
--.*: 04e0cba0 sqdecd z0\.d, mul4
--.*: 04e0cba0 sqdecd z0\.d, mul4
--.*: 04e0cba0 sqdecd z0\.d, mul4
--.*: 04e0cbc0 sqdecd z0\.d, mul3
--.*: 04e0cbc0 sqdecd z0\.d, mul3
--.*: 04e0cbc0 sqdecd z0\.d, mul3
--.*: 04e0cbe0 sqdecd z0\.d
--.*: 04e0cbe0 sqdecd z0\.d
--.*: 04e0cbe0 sqdecd z0\.d
--.*: 04e0cbe0 sqdecd z0\.d
--.*: 04e7c800 sqdecd z0\.d, pow2, mul #8
--.*: 04e7c800 sqdecd z0\.d, pow2, mul #8
--.*: 04e8c800 sqdecd z0\.d, pow2, mul #9
--.*: 04e8c800 sqdecd z0\.d, pow2, mul #9
--.*: 04e9c800 sqdecd z0\.d, pow2, mul #10
--.*: 04e9c800 sqdecd z0\.d, pow2, mul #10
--.*: 04efc800 sqdecd z0\.d, pow2, mul #16
--.*: 04efc800 sqdecd z0\.d, pow2, mul #16
--.*: 04f0f800 sqdecd x0, pow2
--.*: 04f0f800 sqdecd x0, pow2
--.*: 04f0f800 sqdecd x0, pow2
--.*: 04f0f801 sqdecd x1, pow2
--.*: 04f0f801 sqdecd x1, pow2
--.*: 04f0f801 sqdecd x1, pow2
--.*: 04f0f81f sqdecd xzr, pow2
--.*: 04f0f81f sqdecd xzr, pow2
--.*: 04f0f81f sqdecd xzr, pow2
--.*: 04f0f820 sqdecd x0, vl1
--.*: 04f0f820 sqdecd x0, vl1
--.*: 04f0f820 sqdecd x0, vl1
--.*: 04f0f840 sqdecd x0, vl2
--.*: 04f0f840 sqdecd x0, vl2
--.*: 04f0f840 sqdecd x0, vl2
--.*: 04f0f860 sqdecd x0, vl3
--.*: 04f0f860 sqdecd x0, vl3
--.*: 04f0f860 sqdecd x0, vl3
--.*: 04f0f880 sqdecd x0, vl4
--.*: 04f0f880 sqdecd x0, vl4
--.*: 04f0f880 sqdecd x0, vl4
--.*: 04f0f8a0 sqdecd x0, vl5
--.*: 04f0f8a0 sqdecd x0, vl5
--.*: 04f0f8a0 sqdecd x0, vl5
--.*: 04f0f8c0 sqdecd x0, vl6
--.*: 04f0f8c0 sqdecd x0, vl6
--.*: 04f0f8c0 sqdecd x0, vl6
--.*: 04f0f8e0 sqdecd x0, vl7
--.*: 04f0f8e0 sqdecd x0, vl7
--.*: 04f0f8e0 sqdecd x0, vl7
--.*: 04f0f900 sqdecd x0, vl8
--.*: 04f0f900 sqdecd x0, vl8
--.*: 04f0f900 sqdecd x0, vl8
--.*: 04f0f920 sqdecd x0, vl16
--.*: 04f0f920 sqdecd x0, vl16
--.*: 04f0f920 sqdecd x0, vl16
--.*: 04f0f940 sqdecd x0, vl32
--.*: 04f0f940 sqdecd x0, vl32
--.*: 04f0f940 sqdecd x0, vl32
--.*: 04f0f960 sqdecd x0, vl64
--.*: 04f0f960 sqdecd x0, vl64
--.*: 04f0f960 sqdecd x0, vl64
--.*: 04f0f980 sqdecd x0, vl128
--.*: 04f0f980 sqdecd x0, vl128
--.*: 04f0f980 sqdecd x0, vl128
--.*: 04f0f9a0 sqdecd x0, vl256
--.*: 04f0f9a0 sqdecd x0, vl256
--.*: 04f0f9a0 sqdecd x0, vl256
--.*: 04f0f9c0 sqdecd x0, #14
--.*: 04f0f9c0 sqdecd x0, #14
--.*: 04f0f9c0 sqdecd x0, #14
--.*: 04f0f9e0 sqdecd x0, #15
--.*: 04f0f9e0 sqdecd x0, #15
--.*: 04f0f9e0 sqdecd x0, #15
--.*: 04f0fa00 sqdecd x0, #16
--.*: 04f0fa00 sqdecd x0, #16
--.*: 04f0fa00 sqdecd x0, #16
--.*: 04f0fa20 sqdecd x0, #17
--.*: 04f0fa20 sqdecd x0, #17
--.*: 04f0fa20 sqdecd x0, #17
--.*: 04f0fa40 sqdecd x0, #18
--.*: 04f0fa40 sqdecd x0, #18
--.*: 04f0fa40 sqdecd x0, #18
--.*: 04f0fa60 sqdecd x0, #19
--.*: 04f0fa60 sqdecd x0, #19
--.*: 04f0fa60 sqdecd x0, #19
--.*: 04f0fa80 sqdecd x0, #20
--.*: 04f0fa80 sqdecd x0, #20
--.*: 04f0fa80 sqdecd x0, #20
--.*: 04f0faa0 sqdecd x0, #21
--.*: 04f0faa0 sqdecd x0, #21
--.*: 04f0faa0 sqdecd x0, #21
--.*: 04f0fac0 sqdecd x0, #22
--.*: 04f0fac0 sqdecd x0, #22
--.*: 04f0fac0 sqdecd x0, #22
--.*: 04f0fae0 sqdecd x0, #23
--.*: 04f0fae0 sqdecd x0, #23
--.*: 04f0fae0 sqdecd x0, #23
--.*: 04f0fb00 sqdecd x0, #24
--.*: 04f0fb00 sqdecd x0, #24
--.*: 04f0fb00 sqdecd x0, #24
--.*: 04f0fb20 sqdecd x0, #25
--.*: 04f0fb20 sqdecd x0, #25
--.*: 04f0fb20 sqdecd x0, #25
--.*: 04f0fb40 sqdecd x0, #26
--.*: 04f0fb40 sqdecd x0, #26
--.*: 04f0fb40 sqdecd x0, #26
--.*: 04f0fb60 sqdecd x0, #27
--.*: 04f0fb60 sqdecd x0, #27
--.*: 04f0fb60 sqdecd x0, #27
--.*: 04f0fb80 sqdecd x0, #28
--.*: 04f0fb80 sqdecd x0, #28
--.*: 04f0fb80 sqdecd x0, #28
--.*: 04f0fba0 sqdecd x0, mul4
--.*: 04f0fba0 sqdecd x0, mul4
--.*: 04f0fba0 sqdecd x0, mul4
--.*: 04f0fbc0 sqdecd x0, mul3
--.*: 04f0fbc0 sqdecd x0, mul3
--.*: 04f0fbc0 sqdecd x0, mul3
--.*: 04f0fbe0 sqdecd x0
--.*: 04f0fbe0 sqdecd x0
--.*: 04f0fbe0 sqdecd x0
--.*: 04f0fbe0 sqdecd x0
--.*: 04f7f800 sqdecd x0, pow2, mul #8
--.*: 04f7f800 sqdecd x0, pow2, mul #8
--.*: 04f8f800 sqdecd x0, pow2, mul #9
--.*: 04f8f800 sqdecd x0, pow2, mul #9
--.*: 04f9f800 sqdecd x0, pow2, mul #10
--.*: 04f9f800 sqdecd x0, pow2, mul #10
--.*: 04fff800 sqdecd x0, pow2, mul #16
--.*: 04fff800 sqdecd x0, pow2, mul #16
--.*: 04e0f800 sqdecd x0, w0, pow2
--.*: 04e0f800 sqdecd x0, w0, pow2
--.*: 04e0f800 sqdecd x0, w0, pow2
--.*: 04e0f801 sqdecd x1, w1, pow2
--.*: 04e0f801 sqdecd x1, w1, pow2
--.*: 04e0f801 sqdecd x1, w1, pow2
--.*: 04e0f81f sqdecd xzr, wzr, pow2
--.*: 04e0f81f sqdecd xzr, wzr, pow2
--.*: 04e0f81f sqdecd xzr, wzr, pow2
--.*: 04e0f802 sqdecd x2, w2, pow2
--.*: 04e0f802 sqdecd x2, w2, pow2
--.*: 04e0f802 sqdecd x2, w2, pow2
--.*: 04e0f820 sqdecd x0, w0, vl1
--.*: 04e0f820 sqdecd x0, w0, vl1
--.*: 04e0f820 sqdecd x0, w0, vl1
--.*: 04e0f840 sqdecd x0, w0, vl2
--.*: 04e0f840 sqdecd x0, w0, vl2
--.*: 04e0f840 sqdecd x0, w0, vl2
--.*: 04e0f860 sqdecd x0, w0, vl3
--.*: 04e0f860 sqdecd x0, w0, vl3
--.*: 04e0f860 sqdecd x0, w0, vl3
--.*: 04e0f880 sqdecd x0, w0, vl4
--.*: 04e0f880 sqdecd x0, w0, vl4
--.*: 04e0f880 sqdecd x0, w0, vl4
--.*: 04e0f8a0 sqdecd x0, w0, vl5
--.*: 04e0f8a0 sqdecd x0, w0, vl5
--.*: 04e0f8a0 sqdecd x0, w0, vl5
--.*: 04e0f8c0 sqdecd x0, w0, vl6
--.*: 04e0f8c0 sqdecd x0, w0, vl6
--.*: 04e0f8c0 sqdecd x0, w0, vl6
--.*: 04e0f8e0 sqdecd x0, w0, vl7
--.*: 04e0f8e0 sqdecd x0, w0, vl7
--.*: 04e0f8e0 sqdecd x0, w0, vl7
--.*: 04e0f900 sqdecd x0, w0, vl8
--.*: 04e0f900 sqdecd x0, w0, vl8
--.*: 04e0f900 sqdecd x0, w0, vl8
--.*: 04e0f920 sqdecd x0, w0, vl16
--.*: 04e0f920 sqdecd x0, w0, vl16
--.*: 04e0f920 sqdecd x0, w0, vl16
--.*: 04e0f940 sqdecd x0, w0, vl32
--.*: 04e0f940 sqdecd x0, w0, vl32
--.*: 04e0f940 sqdecd x0, w0, vl32
--.*: 04e0f960 sqdecd x0, w0, vl64
--.*: 04e0f960 sqdecd x0, w0, vl64
--.*: 04e0f960 sqdecd x0, w0, vl64
--.*: 04e0f980 sqdecd x0, w0, vl128
--.*: 04e0f980 sqdecd x0, w0, vl128
--.*: 04e0f980 sqdecd x0, w0, vl128
--.*: 04e0f9a0 sqdecd x0, w0, vl256
--.*: 04e0f9a0 sqdecd x0, w0, vl256
--.*: 04e0f9a0 sqdecd x0, w0, vl256
--.*: 04e0f9c0 sqdecd x0, w0, #14
--.*: 04e0f9c0 sqdecd x0, w0, #14
--.*: 04e0f9c0 sqdecd x0, w0, #14
--.*: 04e0f9e0 sqdecd x0, w0, #15
--.*: 04e0f9e0 sqdecd x0, w0, #15
--.*: 04e0f9e0 sqdecd x0, w0, #15
--.*: 04e0fa00 sqdecd x0, w0, #16
--.*: 04e0fa00 sqdecd x0, w0, #16
--.*: 04e0fa00 sqdecd x0, w0, #16
--.*: 04e0fa20 sqdecd x0, w0, #17
--.*: 04e0fa20 sqdecd x0, w0, #17
--.*: 04e0fa20 sqdecd x0, w0, #17
--.*: 04e0fa40 sqdecd x0, w0, #18
--.*: 04e0fa40 sqdecd x0, w0, #18
--.*: 04e0fa40 sqdecd x0, w0, #18
--.*: 04e0fa60 sqdecd x0, w0, #19
--.*: 04e0fa60 sqdecd x0, w0, #19
--.*: 04e0fa60 sqdecd x0, w0, #19
--.*: 04e0fa80 sqdecd x0, w0, #20
--.*: 04e0fa80 sqdecd x0, w0, #20
--.*: 04e0fa80 sqdecd x0, w0, #20
--.*: 04e0faa0 sqdecd x0, w0, #21
--.*: 04e0faa0 sqdecd x0, w0, #21
--.*: 04e0faa0 sqdecd x0, w0, #21
--.*: 04e0fac0 sqdecd x0, w0, #22
--.*: 04e0fac0 sqdecd x0, w0, #22
--.*: 04e0fac0 sqdecd x0, w0, #22
--.*: 04e0fae0 sqdecd x0, w0, #23
--.*: 04e0fae0 sqdecd x0, w0, #23
--.*: 04e0fae0 sqdecd x0, w0, #23
--.*: 04e0fb00 sqdecd x0, w0, #24
--.*: 04e0fb00 sqdecd x0, w0, #24
--.*: 04e0fb00 sqdecd x0, w0, #24
--.*: 04e0fb20 sqdecd x0, w0, #25
--.*: 04e0fb20 sqdecd x0, w0, #25
--.*: 04e0fb20 sqdecd x0, w0, #25
--.*: 04e0fb40 sqdecd x0, w0, #26
--.*: 04e0fb40 sqdecd x0, w0, #26
--.*: 04e0fb40 sqdecd x0, w0, #26
--.*: 04e0fb60 sqdecd x0, w0, #27
--.*: 04e0fb60 sqdecd x0, w0, #27
--.*: 04e0fb60 sqdecd x0, w0, #27
--.*: 04e0fb80 sqdecd x0, w0, #28
--.*: 04e0fb80 sqdecd x0, w0, #28
--.*: 04e0fb80 sqdecd x0, w0, #28
--.*: 04e0fba0 sqdecd x0, w0, mul4
--.*: 04e0fba0 sqdecd x0, w0, mul4
--.*: 04e0fba0 sqdecd x0, w0, mul4
--.*: 04e0fbc0 sqdecd x0, w0, mul3
--.*: 04e0fbc0 sqdecd x0, w0, mul3
--.*: 04e0fbc0 sqdecd x0, w0, mul3
--.*: 04e0fbe0 sqdecd x0, w0
--.*: 04e0fbe0 sqdecd x0, w0
--.*: 04e0fbe0 sqdecd x0, w0
--.*: 04e0fbe0 sqdecd x0, w0
--.*: 04e7f800 sqdecd x0, w0, pow2, mul #8
--.*: 04e7f800 sqdecd x0, w0, pow2, mul #8
--.*: 04e8f800 sqdecd x0, w0, pow2, mul #9
--.*: 04e8f800 sqdecd x0, w0, pow2, mul #9
--.*: 04e9f800 sqdecd x0, w0, pow2, mul #10
--.*: 04e9f800 sqdecd x0, w0, pow2, mul #10
--.*: 04eff800 sqdecd x0, w0, pow2, mul #16
--.*: 04eff800 sqdecd x0, w0, pow2, mul #16
--.*: 0460c800 sqdech z0\.h, pow2
--.*: 0460c800 sqdech z0\.h, pow2
--.*: 0460c800 sqdech z0\.h, pow2
--.*: 0460c801 sqdech z1\.h, pow2
--.*: 0460c801 sqdech z1\.h, pow2
--.*: 0460c801 sqdech z1\.h, pow2
--.*: 0460c81f sqdech z31\.h, pow2
--.*: 0460c81f sqdech z31\.h, pow2
--.*: 0460c81f sqdech z31\.h, pow2
--.*: 0460c820 sqdech z0\.h, vl1
--.*: 0460c820 sqdech z0\.h, vl1
--.*: 0460c820 sqdech z0\.h, vl1
--.*: 0460c840 sqdech z0\.h, vl2
--.*: 0460c840 sqdech z0\.h, vl2
--.*: 0460c840 sqdech z0\.h, vl2
--.*: 0460c860 sqdech z0\.h, vl3
--.*: 0460c860 sqdech z0\.h, vl3
--.*: 0460c860 sqdech z0\.h, vl3
--.*: 0460c880 sqdech z0\.h, vl4
--.*: 0460c880 sqdech z0\.h, vl4
--.*: 0460c880 sqdech z0\.h, vl4
--.*: 0460c8a0 sqdech z0\.h, vl5
--.*: 0460c8a0 sqdech z0\.h, vl5
--.*: 0460c8a0 sqdech z0\.h, vl5
--.*: 0460c8c0 sqdech z0\.h, vl6
--.*: 0460c8c0 sqdech z0\.h, vl6
--.*: 0460c8c0 sqdech z0\.h, vl6
--.*: 0460c8e0 sqdech z0\.h, vl7
--.*: 0460c8e0 sqdech z0\.h, vl7
--.*: 0460c8e0 sqdech z0\.h, vl7
--.*: 0460c900 sqdech z0\.h, vl8
--.*: 0460c900 sqdech z0\.h, vl8
--.*: 0460c900 sqdech z0\.h, vl8
--.*: 0460c920 sqdech z0\.h, vl16
--.*: 0460c920 sqdech z0\.h, vl16
--.*: 0460c920 sqdech z0\.h, vl16
--.*: 0460c940 sqdech z0\.h, vl32
--.*: 0460c940 sqdech z0\.h, vl32
--.*: 0460c940 sqdech z0\.h, vl32
--.*: 0460c960 sqdech z0\.h, vl64
--.*: 0460c960 sqdech z0\.h, vl64
--.*: 0460c960 sqdech z0\.h, vl64
--.*: 0460c980 sqdech z0\.h, vl128
--.*: 0460c980 sqdech z0\.h, vl128
--.*: 0460c980 sqdech z0\.h, vl128
--.*: 0460c9a0 sqdech z0\.h, vl256
--.*: 0460c9a0 sqdech z0\.h, vl256
--.*: 0460c9a0 sqdech z0\.h, vl256
--.*: 0460c9c0 sqdech z0\.h, #14
--.*: 0460c9c0 sqdech z0\.h, #14
--.*: 0460c9c0 sqdech z0\.h, #14
--.*: 0460c9e0 sqdech z0\.h, #15
--.*: 0460c9e0 sqdech z0\.h, #15
--.*: 0460c9e0 sqdech z0\.h, #15
--.*: 0460ca00 sqdech z0\.h, #16
--.*: 0460ca00 sqdech z0\.h, #16
--.*: 0460ca00 sqdech z0\.h, #16
--.*: 0460ca20 sqdech z0\.h, #17
--.*: 0460ca20 sqdech z0\.h, #17
--.*: 0460ca20 sqdech z0\.h, #17
--.*: 0460ca40 sqdech z0\.h, #18
--.*: 0460ca40 sqdech z0\.h, #18
--.*: 0460ca40 sqdech z0\.h, #18
--.*: 0460ca60 sqdech z0\.h, #19
--.*: 0460ca60 sqdech z0\.h, #19
--.*: 0460ca60 sqdech z0\.h, #19
--.*: 0460ca80 sqdech z0\.h, #20
--.*: 0460ca80 sqdech z0\.h, #20
--.*: 0460ca80 sqdech z0\.h, #20
--.*: 0460caa0 sqdech z0\.h, #21
--.*: 0460caa0 sqdech z0\.h, #21
--.*: 0460caa0 sqdech z0\.h, #21
--.*: 0460cac0 sqdech z0\.h, #22
--.*: 0460cac0 sqdech z0\.h, #22
--.*: 0460cac0 sqdech z0\.h, #22
--.*: 0460cae0 sqdech z0\.h, #23
--.*: 0460cae0 sqdech z0\.h, #23
--.*: 0460cae0 sqdech z0\.h, #23
--.*: 0460cb00 sqdech z0\.h, #24
--.*: 0460cb00 sqdech z0\.h, #24
--.*: 0460cb00 sqdech z0\.h, #24
--.*: 0460cb20 sqdech z0\.h, #25
--.*: 0460cb20 sqdech z0\.h, #25
--.*: 0460cb20 sqdech z0\.h, #25
--.*: 0460cb40 sqdech z0\.h, #26
--.*: 0460cb40 sqdech z0\.h, #26
--.*: 0460cb40 sqdech z0\.h, #26
--.*: 0460cb60 sqdech z0\.h, #27
--.*: 0460cb60 sqdech z0\.h, #27
--.*: 0460cb60 sqdech z0\.h, #27
--.*: 0460cb80 sqdech z0\.h, #28
--.*: 0460cb80 sqdech z0\.h, #28
--.*: 0460cb80 sqdech z0\.h, #28
--.*: 0460cba0 sqdech z0\.h, mul4
--.*: 0460cba0 sqdech z0\.h, mul4
--.*: 0460cba0 sqdech z0\.h, mul4
--.*: 0460cbc0 sqdech z0\.h, mul3
--.*: 0460cbc0 sqdech z0\.h, mul3
--.*: 0460cbc0 sqdech z0\.h, mul3
--.*: 0460cbe0 sqdech z0\.h
--.*: 0460cbe0 sqdech z0\.h
--.*: 0460cbe0 sqdech z0\.h
--.*: 0460cbe0 sqdech z0\.h
--.*: 0467c800 sqdech z0\.h, pow2, mul #8
--.*: 0467c800 sqdech z0\.h, pow2, mul #8
--.*: 0468c800 sqdech z0\.h, pow2, mul #9
--.*: 0468c800 sqdech z0\.h, pow2, mul #9
--.*: 0469c800 sqdech z0\.h, pow2, mul #10
--.*: 0469c800 sqdech z0\.h, pow2, mul #10
--.*: 046fc800 sqdech z0\.h, pow2, mul #16
--.*: 046fc800 sqdech z0\.h, pow2, mul #16
--.*: 0470f800 sqdech x0, pow2
--.*: 0470f800 sqdech x0, pow2
--.*: 0470f800 sqdech x0, pow2
--.*: 0470f801 sqdech x1, pow2
--.*: 0470f801 sqdech x1, pow2
--.*: 0470f801 sqdech x1, pow2
--.*: 0470f81f sqdech xzr, pow2
--.*: 0470f81f sqdech xzr, pow2
--.*: 0470f81f sqdech xzr, pow2
--.*: 0470f820 sqdech x0, vl1
--.*: 0470f820 sqdech x0, vl1
--.*: 0470f820 sqdech x0, vl1
--.*: 0470f840 sqdech x0, vl2
--.*: 0470f840 sqdech x0, vl2
--.*: 0470f840 sqdech x0, vl2
--.*: 0470f860 sqdech x0, vl3
--.*: 0470f860 sqdech x0, vl3
--.*: 0470f860 sqdech x0, vl3
--.*: 0470f880 sqdech x0, vl4
--.*: 0470f880 sqdech x0, vl4
--.*: 0470f880 sqdech x0, vl4
--.*: 0470f8a0 sqdech x0, vl5
--.*: 0470f8a0 sqdech x0, vl5
--.*: 0470f8a0 sqdech x0, vl5
--.*: 0470f8c0 sqdech x0, vl6
--.*: 0470f8c0 sqdech x0, vl6
--.*: 0470f8c0 sqdech x0, vl6
--.*: 0470f8e0 sqdech x0, vl7
--.*: 0470f8e0 sqdech x0, vl7
--.*: 0470f8e0 sqdech x0, vl7
--.*: 0470f900 sqdech x0, vl8
--.*: 0470f900 sqdech x0, vl8
--.*: 0470f900 sqdech x0, vl8
--.*: 0470f920 sqdech x0, vl16
--.*: 0470f920 sqdech x0, vl16
--.*: 0470f920 sqdech x0, vl16
--.*: 0470f940 sqdech x0, vl32
--.*: 0470f940 sqdech x0, vl32
--.*: 0470f940 sqdech x0, vl32
--.*: 0470f960 sqdech x0, vl64
--.*: 0470f960 sqdech x0, vl64
--.*: 0470f960 sqdech x0, vl64
--.*: 0470f980 sqdech x0, vl128
--.*: 0470f980 sqdech x0, vl128
--.*: 0470f980 sqdech x0, vl128
--.*: 0470f9a0 sqdech x0, vl256
--.*: 0470f9a0 sqdech x0, vl256
--.*: 0470f9a0 sqdech x0, vl256
--.*: 0470f9c0 sqdech x0, #14
--.*: 0470f9c0 sqdech x0, #14
--.*: 0470f9c0 sqdech x0, #14
--.*: 0470f9e0 sqdech x0, #15
--.*: 0470f9e0 sqdech x0, #15
--.*: 0470f9e0 sqdech x0, #15
--.*: 0470fa00 sqdech x0, #16
--.*: 0470fa00 sqdech x0, #16
--.*: 0470fa00 sqdech x0, #16
--.*: 0470fa20 sqdech x0, #17
--.*: 0470fa20 sqdech x0, #17
--.*: 0470fa20 sqdech x0, #17
--.*: 0470fa40 sqdech x0, #18
--.*: 0470fa40 sqdech x0, #18
--.*: 0470fa40 sqdech x0, #18
--.*: 0470fa60 sqdech x0, #19
--.*: 0470fa60 sqdech x0, #19
--.*: 0470fa60 sqdech x0, #19
--.*: 0470fa80 sqdech x0, #20
--.*: 0470fa80 sqdech x0, #20
--.*: 0470fa80 sqdech x0, #20
--.*: 0470faa0 sqdech x0, #21
--.*: 0470faa0 sqdech x0, #21
--.*: 0470faa0 sqdech x0, #21
--.*: 0470fac0 sqdech x0, #22
--.*: 0470fac0 sqdech x0, #22
--.*: 0470fac0 sqdech x0, #22
--.*: 0470fae0 sqdech x0, #23
--.*: 0470fae0 sqdech x0, #23
--.*: 0470fae0 sqdech x0, #23
--.*: 0470fb00 sqdech x0, #24
--.*: 0470fb00 sqdech x0, #24
--.*: 0470fb00 sqdech x0, #24
--.*: 0470fb20 sqdech x0, #25
--.*: 0470fb20 sqdech x0, #25
--.*: 0470fb20 sqdech x0, #25
--.*: 0470fb40 sqdech x0, #26
--.*: 0470fb40 sqdech x0, #26
--.*: 0470fb40 sqdech x0, #26
--.*: 0470fb60 sqdech x0, #27
--.*: 0470fb60 sqdech x0, #27
--.*: 0470fb60 sqdech x0, #27
--.*: 0470fb80 sqdech x0, #28
--.*: 0470fb80 sqdech x0, #28
--.*: 0470fb80 sqdech x0, #28
--.*: 0470fba0 sqdech x0, mul4
--.*: 0470fba0 sqdech x0, mul4
--.*: 0470fba0 sqdech x0, mul4
--.*: 0470fbc0 sqdech x0, mul3
--.*: 0470fbc0 sqdech x0, mul3
--.*: 0470fbc0 sqdech x0, mul3
--.*: 0470fbe0 sqdech x0
--.*: 0470fbe0 sqdech x0
--.*: 0470fbe0 sqdech x0
--.*: 0470fbe0 sqdech x0
--.*: 0477f800 sqdech x0, pow2, mul #8
--.*: 0477f800 sqdech x0, pow2, mul #8
--.*: 0478f800 sqdech x0, pow2, mul #9
--.*: 0478f800 sqdech x0, pow2, mul #9
--.*: 0479f800 sqdech x0, pow2, mul #10
--.*: 0479f800 sqdech x0, pow2, mul #10
--.*: 047ff800 sqdech x0, pow2, mul #16
--.*: 047ff800 sqdech x0, pow2, mul #16
--.*: 0460f800 sqdech x0, w0, pow2
--.*: 0460f800 sqdech x0, w0, pow2
--.*: 0460f800 sqdech x0, w0, pow2
--.*: 0460f801 sqdech x1, w1, pow2
--.*: 0460f801 sqdech x1, w1, pow2
--.*: 0460f801 sqdech x1, w1, pow2
--.*: 0460f81f sqdech xzr, wzr, pow2
--.*: 0460f81f sqdech xzr, wzr, pow2
--.*: 0460f81f sqdech xzr, wzr, pow2
--.*: 0460f802 sqdech x2, w2, pow2
--.*: 0460f802 sqdech x2, w2, pow2
--.*: 0460f802 sqdech x2, w2, pow2
--.*: 0460f820 sqdech x0, w0, vl1
--.*: 0460f820 sqdech x0, w0, vl1
--.*: 0460f820 sqdech x0, w0, vl1
--.*: 0460f840 sqdech x0, w0, vl2
--.*: 0460f840 sqdech x0, w0, vl2
--.*: 0460f840 sqdech x0, w0, vl2
--.*: 0460f860 sqdech x0, w0, vl3
--.*: 0460f860 sqdech x0, w0, vl3
--.*: 0460f860 sqdech x0, w0, vl3
--.*: 0460f880 sqdech x0, w0, vl4
--.*: 0460f880 sqdech x0, w0, vl4
--.*: 0460f880 sqdech x0, w0, vl4
--.*: 0460f8a0 sqdech x0, w0, vl5
--.*: 0460f8a0 sqdech x0, w0, vl5
--.*: 0460f8a0 sqdech x0, w0, vl5
--.*: 0460f8c0 sqdech x0, w0, vl6
--.*: 0460f8c0 sqdech x0, w0, vl6
--.*: 0460f8c0 sqdech x0, w0, vl6
--.*: 0460f8e0 sqdech x0, w0, vl7
--.*: 0460f8e0 sqdech x0, w0, vl7
--.*: 0460f8e0 sqdech x0, w0, vl7
--.*: 0460f900 sqdech x0, w0, vl8
--.*: 0460f900 sqdech x0, w0, vl8
--.*: 0460f900 sqdech x0, w0, vl8
--.*: 0460f920 sqdech x0, w0, vl16
--.*: 0460f920 sqdech x0, w0, vl16
--.*: 0460f920 sqdech x0, w0, vl16
--.*: 0460f940 sqdech x0, w0, vl32
--.*: 0460f940 sqdech x0, w0, vl32
--.*: 0460f940 sqdech x0, w0, vl32
--.*: 0460f960 sqdech x0, w0, vl64
--.*: 0460f960 sqdech x0, w0, vl64
--.*: 0460f960 sqdech x0, w0, vl64
--.*: 0460f980 sqdech x0, w0, vl128
--.*: 0460f980 sqdech x0, w0, vl128
--.*: 0460f980 sqdech x0, w0, vl128
--.*: 0460f9a0 sqdech x0, w0, vl256
--.*: 0460f9a0 sqdech x0, w0, vl256
--.*: 0460f9a0 sqdech x0, w0, vl256
--.*: 0460f9c0 sqdech x0, w0, #14
--.*: 0460f9c0 sqdech x0, w0, #14
--.*: 0460f9c0 sqdech x0, w0, #14
--.*: 0460f9e0 sqdech x0, w0, #15
--.*: 0460f9e0 sqdech x0, w0, #15
--.*: 0460f9e0 sqdech x0, w0, #15
--.*: 0460fa00 sqdech x0, w0, #16
--.*: 0460fa00 sqdech x0, w0, #16
--.*: 0460fa00 sqdech x0, w0, #16
--.*: 0460fa20 sqdech x0, w0, #17
--.*: 0460fa20 sqdech x0, w0, #17
--.*: 0460fa20 sqdech x0, w0, #17
--.*: 0460fa40 sqdech x0, w0, #18
--.*: 0460fa40 sqdech x0, w0, #18
--.*: 0460fa40 sqdech x0, w0, #18
--.*: 0460fa60 sqdech x0, w0, #19
--.*: 0460fa60 sqdech x0, w0, #19
--.*: 0460fa60 sqdech x0, w0, #19
--.*: 0460fa80 sqdech x0, w0, #20
--.*: 0460fa80 sqdech x0, w0, #20
--.*: 0460fa80 sqdech x0, w0, #20
--.*: 0460faa0 sqdech x0, w0, #21
--.*: 0460faa0 sqdech x0, w0, #21
--.*: 0460faa0 sqdech x0, w0, #21
--.*: 0460fac0 sqdech x0, w0, #22
--.*: 0460fac0 sqdech x0, w0, #22
--.*: 0460fac0 sqdech x0, w0, #22
--.*: 0460fae0 sqdech x0, w0, #23
--.*: 0460fae0 sqdech x0, w0, #23
--.*: 0460fae0 sqdech x0, w0, #23
--.*: 0460fb00 sqdech x0, w0, #24
--.*: 0460fb00 sqdech x0, w0, #24
--.*: 0460fb00 sqdech x0, w0, #24
--.*: 0460fb20 sqdech x0, w0, #25
--.*: 0460fb20 sqdech x0, w0, #25
--.*: 0460fb20 sqdech x0, w0, #25
--.*: 0460fb40 sqdech x0, w0, #26
--.*: 0460fb40 sqdech x0, w0, #26
--.*: 0460fb40 sqdech x0, w0, #26
--.*: 0460fb60 sqdech x0, w0, #27
--.*: 0460fb60 sqdech x0, w0, #27
--.*: 0460fb60 sqdech x0, w0, #27
--.*: 0460fb80 sqdech x0, w0, #28
--.*: 0460fb80 sqdech x0, w0, #28
--.*: 0460fb80 sqdech x0, w0, #28
--.*: 0460fba0 sqdech x0, w0, mul4
--.*: 0460fba0 sqdech x0, w0, mul4
--.*: 0460fba0 sqdech x0, w0, mul4
--.*: 0460fbc0 sqdech x0, w0, mul3
--.*: 0460fbc0 sqdech x0, w0, mul3
--.*: 0460fbc0 sqdech x0, w0, mul3
--.*: 0460fbe0 sqdech x0, w0
--.*: 0460fbe0 sqdech x0, w0
--.*: 0460fbe0 sqdech x0, w0
--.*: 0460fbe0 sqdech x0, w0
--.*: 0467f800 sqdech x0, w0, pow2, mul #8
--.*: 0467f800 sqdech x0, w0, pow2, mul #8
--.*: 0468f800 sqdech x0, w0, pow2, mul #9
--.*: 0468f800 sqdech x0, w0, pow2, mul #9
--.*: 0469f800 sqdech x0, w0, pow2, mul #10
--.*: 0469f800 sqdech x0, w0, pow2, mul #10
--.*: 046ff800 sqdech x0, w0, pow2, mul #16
--.*: 046ff800 sqdech x0, w0, pow2, mul #16
--.*: 256a8000 sqdecp z0\.h, p0
--.*: 256a8000 sqdecp z0\.h, p0
--.*: 256a8001 sqdecp z1\.h, p0
--.*: 256a8001 sqdecp z1\.h, p0
--.*: 256a801f sqdecp z31\.h, p0
--.*: 256a801f sqdecp z31\.h, p0
--.*: 256a8040 sqdecp z0\.h, p2
--.*: 256a8040 sqdecp z0\.h, p2
--.*: 256a81e0 sqdecp z0\.h, p15
--.*: 256a81e0 sqdecp z0\.h, p15
--.*: 25aa8000 sqdecp z0\.s, p0
--.*: 25aa8000 sqdecp z0\.s, p0
--.*: 25aa8001 sqdecp z1\.s, p0
--.*: 25aa8001 sqdecp z1\.s, p0
--.*: 25aa801f sqdecp z31\.s, p0
--.*: 25aa801f sqdecp z31\.s, p0
--.*: 25aa8040 sqdecp z0\.s, p2
--.*: 25aa8040 sqdecp z0\.s, p2
--.*: 25aa81e0 sqdecp z0\.s, p15
--.*: 25aa81e0 sqdecp z0\.s, p15
--.*: 25ea8000 sqdecp z0\.d, p0
--.*: 25ea8000 sqdecp z0\.d, p0
--.*: 25ea8001 sqdecp z1\.d, p0
--.*: 25ea8001 sqdecp z1\.d, p0
--.*: 25ea801f sqdecp z31\.d, p0
--.*: 25ea801f sqdecp z31\.d, p0
--.*: 25ea8040 sqdecp z0\.d, p2
--.*: 25ea8040 sqdecp z0\.d, p2
--.*: 25ea81e0 sqdecp z0\.d, p15
--.*: 25ea81e0 sqdecp z0\.d, p15
--.*: 252a8c00 sqdecp x0, p0\.b
--.*: 252a8c00 sqdecp x0, p0\.b
--.*: 252a8c01 sqdecp x1, p0\.b
--.*: 252a8c01 sqdecp x1, p0\.b
--.*: 252a8c1f sqdecp xzr, p0\.b
--.*: 252a8c1f sqdecp xzr, p0\.b
--.*: 252a8c40 sqdecp x0, p2\.b
--.*: 252a8c40 sqdecp x0, p2\.b
--.*: 252a8de0 sqdecp x0, p15\.b
--.*: 252a8de0 sqdecp x0, p15\.b
--.*: 256a8c00 sqdecp x0, p0\.h
--.*: 256a8c00 sqdecp x0, p0\.h
--.*: 256a8c01 sqdecp x1, p0\.h
--.*: 256a8c01 sqdecp x1, p0\.h
--.*: 256a8c1f sqdecp xzr, p0\.h
--.*: 256a8c1f sqdecp xzr, p0\.h
--.*: 256a8c40 sqdecp x0, p2\.h
--.*: 256a8c40 sqdecp x0, p2\.h
--.*: 256a8de0 sqdecp x0, p15\.h
--.*: 256a8de0 sqdecp x0, p15\.h
--.*: 25aa8c00 sqdecp x0, p0\.s
--.*: 25aa8c00 sqdecp x0, p0\.s
--.*: 25aa8c01 sqdecp x1, p0\.s
--.*: 25aa8c01 sqdecp x1, p0\.s
--.*: 25aa8c1f sqdecp xzr, p0\.s
--.*: 25aa8c1f sqdecp xzr, p0\.s
--.*: 25aa8c40 sqdecp x0, p2\.s
--.*: 25aa8c40 sqdecp x0, p2\.s
--.*: 25aa8de0 sqdecp x0, p15\.s
--.*: 25aa8de0 sqdecp x0, p15\.s
--.*: 25ea8c00 sqdecp x0, p0\.d
--.*: 25ea8c00 sqdecp x0, p0\.d
--.*: 25ea8c01 sqdecp x1, p0\.d
--.*: 25ea8c01 sqdecp x1, p0\.d
--.*: 25ea8c1f sqdecp xzr, p0\.d
--.*: 25ea8c1f sqdecp xzr, p0\.d
--.*: 25ea8c40 sqdecp x0, p2\.d
--.*: 25ea8c40 sqdecp x0, p2\.d
--.*: 25ea8de0 sqdecp x0, p15\.d
--.*: 25ea8de0 sqdecp x0, p15\.d
--.*: 252a8800 sqdecp x0, p0\.b, w0
--.*: 252a8800 sqdecp x0, p0\.b, w0
--.*: 252a8801 sqdecp x1, p0\.b, w1
--.*: 252a8801 sqdecp x1, p0\.b, w1
--.*: 252a881f sqdecp xzr, p0\.b, wzr
--.*: 252a881f sqdecp xzr, p0\.b, wzr
--.*: 252a8840 sqdecp x0, p2\.b, w0
--.*: 252a8840 sqdecp x0, p2\.b, w0
--.*: 252a89e0 sqdecp x0, p15\.b, w0
--.*: 252a89e0 sqdecp x0, p15\.b, w0
--.*: 252a8803 sqdecp x3, p0\.b, w3
--.*: 252a8803 sqdecp x3, p0\.b, w3
--.*: 256a8800 sqdecp x0, p0\.h, w0
--.*: 256a8800 sqdecp x0, p0\.h, w0
--.*: 256a8801 sqdecp x1, p0\.h, w1
--.*: 256a8801 sqdecp x1, p0\.h, w1
--.*: 256a881f sqdecp xzr, p0\.h, wzr
--.*: 256a881f sqdecp xzr, p0\.h, wzr
--.*: 256a8840 sqdecp x0, p2\.h, w0
--.*: 256a8840 sqdecp x0, p2\.h, w0
--.*: 256a89e0 sqdecp x0, p15\.h, w0
--.*: 256a89e0 sqdecp x0, p15\.h, w0
--.*: 256a8803 sqdecp x3, p0\.h, w3
--.*: 256a8803 sqdecp x3, p0\.h, w3
--.*: 25aa8800 sqdecp x0, p0\.s, w0
--.*: 25aa8800 sqdecp x0, p0\.s, w0
--.*: 25aa8801 sqdecp x1, p0\.s, w1
--.*: 25aa8801 sqdecp x1, p0\.s, w1
--.*: 25aa881f sqdecp xzr, p0\.s, wzr
--.*: 25aa881f sqdecp xzr, p0\.s, wzr
--.*: 25aa8840 sqdecp x0, p2\.s, w0
--.*: 25aa8840 sqdecp x0, p2\.s, w0
--.*: 25aa89e0 sqdecp x0, p15\.s, w0
--.*: 25aa89e0 sqdecp x0, p15\.s, w0
--.*: 25aa8803 sqdecp x3, p0\.s, w3
--.*: 25aa8803 sqdecp x3, p0\.s, w3
--.*: 25ea8800 sqdecp x0, p0\.d, w0
--.*: 25ea8800 sqdecp x0, p0\.d, w0
--.*: 25ea8801 sqdecp x1, p0\.d, w1
--.*: 25ea8801 sqdecp x1, p0\.d, w1
--.*: 25ea881f sqdecp xzr, p0\.d, wzr
--.*: 25ea881f sqdecp xzr, p0\.d, wzr
--.*: 25ea8840 sqdecp x0, p2\.d, w0
--.*: 25ea8840 sqdecp x0, p2\.d, w0
--.*: 25ea89e0 sqdecp x0, p15\.d, w0
--.*: 25ea89e0 sqdecp x0, p15\.d, w0
--.*: 25ea8803 sqdecp x3, p0\.d, w3
--.*: 25ea8803 sqdecp x3, p0\.d, w3
--.*: 04a0c800 sqdecw z0\.s, pow2
--.*: 04a0c800 sqdecw z0\.s, pow2
--.*: 04a0c800 sqdecw z0\.s, pow2
--.*: 04a0c801 sqdecw z1\.s, pow2
--.*: 04a0c801 sqdecw z1\.s, pow2
--.*: 04a0c801 sqdecw z1\.s, pow2
--.*: 04a0c81f sqdecw z31\.s, pow2
--.*: 04a0c81f sqdecw z31\.s, pow2
--.*: 04a0c81f sqdecw z31\.s, pow2
--.*: 04a0c820 sqdecw z0\.s, vl1
--.*: 04a0c820 sqdecw z0\.s, vl1
--.*: 04a0c820 sqdecw z0\.s, vl1
--.*: 04a0c840 sqdecw z0\.s, vl2
--.*: 04a0c840 sqdecw z0\.s, vl2
--.*: 04a0c840 sqdecw z0\.s, vl2
--.*: 04a0c860 sqdecw z0\.s, vl3
--.*: 04a0c860 sqdecw z0\.s, vl3
--.*: 04a0c860 sqdecw z0\.s, vl3
--.*: 04a0c880 sqdecw z0\.s, vl4
--.*: 04a0c880 sqdecw z0\.s, vl4
--.*: 04a0c880 sqdecw z0\.s, vl4
--.*: 04a0c8a0 sqdecw z0\.s, vl5
--.*: 04a0c8a0 sqdecw z0\.s, vl5
--.*: 04a0c8a0 sqdecw z0\.s, vl5
--.*: 04a0c8c0 sqdecw z0\.s, vl6
--.*: 04a0c8c0 sqdecw z0\.s, vl6
--.*: 04a0c8c0 sqdecw z0\.s, vl6
--.*: 04a0c8e0 sqdecw z0\.s, vl7
--.*: 04a0c8e0 sqdecw z0\.s, vl7
--.*: 04a0c8e0 sqdecw z0\.s, vl7
--.*: 04a0c900 sqdecw z0\.s, vl8
--.*: 04a0c900 sqdecw z0\.s, vl8
--.*: 04a0c900 sqdecw z0\.s, vl8
--.*: 04a0c920 sqdecw z0\.s, vl16
--.*: 04a0c920 sqdecw z0\.s, vl16
--.*: 04a0c920 sqdecw z0\.s, vl16
--.*: 04a0c940 sqdecw z0\.s, vl32
--.*: 04a0c940 sqdecw z0\.s, vl32
--.*: 04a0c940 sqdecw z0\.s, vl32
--.*: 04a0c960 sqdecw z0\.s, vl64
--.*: 04a0c960 sqdecw z0\.s, vl64
--.*: 04a0c960 sqdecw z0\.s, vl64
--.*: 04a0c980 sqdecw z0\.s, vl128
--.*: 04a0c980 sqdecw z0\.s, vl128
--.*: 04a0c980 sqdecw z0\.s, vl128
--.*: 04a0c9a0 sqdecw z0\.s, vl256
--.*: 04a0c9a0 sqdecw z0\.s, vl256
--.*: 04a0c9a0 sqdecw z0\.s, vl256
--.*: 04a0c9c0 sqdecw z0\.s, #14
--.*: 04a0c9c0 sqdecw z0\.s, #14
--.*: 04a0c9c0 sqdecw z0\.s, #14
--.*: 04a0c9e0 sqdecw z0\.s, #15
--.*: 04a0c9e0 sqdecw z0\.s, #15
--.*: 04a0c9e0 sqdecw z0\.s, #15
--.*: 04a0ca00 sqdecw z0\.s, #16
--.*: 04a0ca00 sqdecw z0\.s, #16
--.*: 04a0ca00 sqdecw z0\.s, #16
--.*: 04a0ca20 sqdecw z0\.s, #17
--.*: 04a0ca20 sqdecw z0\.s, #17
--.*: 04a0ca20 sqdecw z0\.s, #17
--.*: 04a0ca40 sqdecw z0\.s, #18
--.*: 04a0ca40 sqdecw z0\.s, #18
--.*: 04a0ca40 sqdecw z0\.s, #18
--.*: 04a0ca60 sqdecw z0\.s, #19
--.*: 04a0ca60 sqdecw z0\.s, #19
--.*: 04a0ca60 sqdecw z0\.s, #19
--.*: 04a0ca80 sqdecw z0\.s, #20
--.*: 04a0ca80 sqdecw z0\.s, #20
--.*: 04a0ca80 sqdecw z0\.s, #20
--.*: 04a0caa0 sqdecw z0\.s, #21
--.*: 04a0caa0 sqdecw z0\.s, #21
--.*: 04a0caa0 sqdecw z0\.s, #21
--.*: 04a0cac0 sqdecw z0\.s, #22
--.*: 04a0cac0 sqdecw z0\.s, #22
--.*: 04a0cac0 sqdecw z0\.s, #22
--.*: 04a0cae0 sqdecw z0\.s, #23
--.*: 04a0cae0 sqdecw z0\.s, #23
--.*: 04a0cae0 sqdecw z0\.s, #23
--.*: 04a0cb00 sqdecw z0\.s, #24
--.*: 04a0cb00 sqdecw z0\.s, #24
--.*: 04a0cb00 sqdecw z0\.s, #24
--.*: 04a0cb20 sqdecw z0\.s, #25
--.*: 04a0cb20 sqdecw z0\.s, #25
--.*: 04a0cb20 sqdecw z0\.s, #25
--.*: 04a0cb40 sqdecw z0\.s, #26
--.*: 04a0cb40 sqdecw z0\.s, #26
--.*: 04a0cb40 sqdecw z0\.s, #26
--.*: 04a0cb60 sqdecw z0\.s, #27
--.*: 04a0cb60 sqdecw z0\.s, #27
--.*: 04a0cb60 sqdecw z0\.s, #27
--.*: 04a0cb80 sqdecw z0\.s, #28
--.*: 04a0cb80 sqdecw z0\.s, #28
--.*: 04a0cb80 sqdecw z0\.s, #28
--.*: 04a0cba0 sqdecw z0\.s, mul4
--.*: 04a0cba0 sqdecw z0\.s, mul4
--.*: 04a0cba0 sqdecw z0\.s, mul4
--.*: 04a0cbc0 sqdecw z0\.s, mul3
--.*: 04a0cbc0 sqdecw z0\.s, mul3
--.*: 04a0cbc0 sqdecw z0\.s, mul3
--.*: 04a0cbe0 sqdecw z0\.s
--.*: 04a0cbe0 sqdecw z0\.s
--.*: 04a0cbe0 sqdecw z0\.s
--.*: 04a0cbe0 sqdecw z0\.s
--.*: 04a7c800 sqdecw z0\.s, pow2, mul #8
--.*: 04a7c800 sqdecw z0\.s, pow2, mul #8
--.*: 04a8c800 sqdecw z0\.s, pow2, mul #9
--.*: 04a8c800 sqdecw z0\.s, pow2, mul #9
--.*: 04a9c800 sqdecw z0\.s, pow2, mul #10
--.*: 04a9c800 sqdecw z0\.s, pow2, mul #10
--.*: 04afc800 sqdecw z0\.s, pow2, mul #16
--.*: 04afc800 sqdecw z0\.s, pow2, mul #16
--.*: 04b0f800 sqdecw x0, pow2
--.*: 04b0f800 sqdecw x0, pow2
--.*: 04b0f800 sqdecw x0, pow2
--.*: 04b0f801 sqdecw x1, pow2
--.*: 04b0f801 sqdecw x1, pow2
--.*: 04b0f801 sqdecw x1, pow2
--.*: 04b0f81f sqdecw xzr, pow2
--.*: 04b0f81f sqdecw xzr, pow2
--.*: 04b0f81f sqdecw xzr, pow2
--.*: 04b0f820 sqdecw x0, vl1
--.*: 04b0f820 sqdecw x0, vl1
--.*: 04b0f820 sqdecw x0, vl1
--.*: 04b0f840 sqdecw x0, vl2
--.*: 04b0f840 sqdecw x0, vl2
--.*: 04b0f840 sqdecw x0, vl2
--.*: 04b0f860 sqdecw x0, vl3
--.*: 04b0f860 sqdecw x0, vl3
--.*: 04b0f860 sqdecw x0, vl3
--.*: 04b0f880 sqdecw x0, vl4
--.*: 04b0f880 sqdecw x0, vl4
--.*: 04b0f880 sqdecw x0, vl4
--.*: 04b0f8a0 sqdecw x0, vl5
--.*: 04b0f8a0 sqdecw x0, vl5
--.*: 04b0f8a0 sqdecw x0, vl5
--.*: 04b0f8c0 sqdecw x0, vl6
--.*: 04b0f8c0 sqdecw x0, vl6
--.*: 04b0f8c0 sqdecw x0, vl6
--.*: 04b0f8e0 sqdecw x0, vl7
--.*: 04b0f8e0 sqdecw x0, vl7
--.*: 04b0f8e0 sqdecw x0, vl7
--.*: 04b0f900 sqdecw x0, vl8
--.*: 04b0f900 sqdecw x0, vl8
--.*: 04b0f900 sqdecw x0, vl8
--.*: 04b0f920 sqdecw x0, vl16
--.*: 04b0f920 sqdecw x0, vl16
--.*: 04b0f920 sqdecw x0, vl16
--.*: 04b0f940 sqdecw x0, vl32
--.*: 04b0f940 sqdecw x0, vl32
--.*: 04b0f940 sqdecw x0, vl32
--.*: 04b0f960 sqdecw x0, vl64
--.*: 04b0f960 sqdecw x0, vl64
--.*: 04b0f960 sqdecw x0, vl64
--.*: 04b0f980 sqdecw x0, vl128
--.*: 04b0f980 sqdecw x0, vl128
--.*: 04b0f980 sqdecw x0, vl128
--.*: 04b0f9a0 sqdecw x0, vl256
--.*: 04b0f9a0 sqdecw x0, vl256
--.*: 04b0f9a0 sqdecw x0, vl256
--.*: 04b0f9c0 sqdecw x0, #14
--.*: 04b0f9c0 sqdecw x0, #14
--.*: 04b0f9c0 sqdecw x0, #14
--.*: 04b0f9e0 sqdecw x0, #15
--.*: 04b0f9e0 sqdecw x0, #15
--.*: 04b0f9e0 sqdecw x0, #15
--.*: 04b0fa00 sqdecw x0, #16
--.*: 04b0fa00 sqdecw x0, #16
--.*: 04b0fa00 sqdecw x0, #16
--.*: 04b0fa20 sqdecw x0, #17
--.*: 04b0fa20 sqdecw x0, #17
--.*: 04b0fa20 sqdecw x0, #17
--.*: 04b0fa40 sqdecw x0, #18
--.*: 04b0fa40 sqdecw x0, #18
--.*: 04b0fa40 sqdecw x0, #18
--.*: 04b0fa60 sqdecw x0, #19
--.*: 04b0fa60 sqdecw x0, #19
--.*: 04b0fa60 sqdecw x0, #19
--.*: 04b0fa80 sqdecw x0, #20
--.*: 04b0fa80 sqdecw x0, #20
--.*: 04b0fa80 sqdecw x0, #20
--.*: 04b0faa0 sqdecw x0, #21
--.*: 04b0faa0 sqdecw x0, #21
--.*: 04b0faa0 sqdecw x0, #21
--.*: 04b0fac0 sqdecw x0, #22
--.*: 04b0fac0 sqdecw x0, #22
--.*: 04b0fac0 sqdecw x0, #22
--.*: 04b0fae0 sqdecw x0, #23
--.*: 04b0fae0 sqdecw x0, #23
--.*: 04b0fae0 sqdecw x0, #23
--.*: 04b0fb00 sqdecw x0, #24
--.*: 04b0fb00 sqdecw x0, #24
--.*: 04b0fb00 sqdecw x0, #24
--.*: 04b0fb20 sqdecw x0, #25
--.*: 04b0fb20 sqdecw x0, #25
--.*: 04b0fb20 sqdecw x0, #25
--.*: 04b0fb40 sqdecw x0, #26
--.*: 04b0fb40 sqdecw x0, #26
--.*: 04b0fb40 sqdecw x0, #26
--.*: 04b0fb60 sqdecw x0, #27
--.*: 04b0fb60 sqdecw x0, #27
--.*: 04b0fb60 sqdecw x0, #27
--.*: 04b0fb80 sqdecw x0, #28
--.*: 04b0fb80 sqdecw x0, #28
--.*: 04b0fb80 sqdecw x0, #28
--.*: 04b0fba0 sqdecw x0, mul4
--.*: 04b0fba0 sqdecw x0, mul4
--.*: 04b0fba0 sqdecw x0, mul4
--.*: 04b0fbc0 sqdecw x0, mul3
--.*: 04b0fbc0 sqdecw x0, mul3
--.*: 04b0fbc0 sqdecw x0, mul3
--.*: 04b0fbe0 sqdecw x0
--.*: 04b0fbe0 sqdecw x0
--.*: 04b0fbe0 sqdecw x0
--.*: 04b0fbe0 sqdecw x0
--.*: 04b7f800 sqdecw x0, pow2, mul #8
--.*: 04b7f800 sqdecw x0, pow2, mul #8
--.*: 04b8f800 sqdecw x0, pow2, mul #9
--.*: 04b8f800 sqdecw x0, pow2, mul #9
--.*: 04b9f800 sqdecw x0, pow2, mul #10
--.*: 04b9f800 sqdecw x0, pow2, mul #10
--.*: 04bff800 sqdecw x0, pow2, mul #16
--.*: 04bff800 sqdecw x0, pow2, mul #16
--.*: 04a0f800 sqdecw x0, w0, pow2
--.*: 04a0f800 sqdecw x0, w0, pow2
--.*: 04a0f800 sqdecw x0, w0, pow2
--.*: 04a0f801 sqdecw x1, w1, pow2
--.*: 04a0f801 sqdecw x1, w1, pow2
--.*: 04a0f801 sqdecw x1, w1, pow2
--.*: 04a0f81f sqdecw xzr, wzr, pow2
--.*: 04a0f81f sqdecw xzr, wzr, pow2
--.*: 04a0f81f sqdecw xzr, wzr, pow2
--.*: 04a0f802 sqdecw x2, w2, pow2
--.*: 04a0f802 sqdecw x2, w2, pow2
--.*: 04a0f802 sqdecw x2, w2, pow2
--.*: 04a0f820 sqdecw x0, w0, vl1
--.*: 04a0f820 sqdecw x0, w0, vl1
--.*: 04a0f820 sqdecw x0, w0, vl1
--.*: 04a0f840 sqdecw x0, w0, vl2
--.*: 04a0f840 sqdecw x0, w0, vl2
--.*: 04a0f840 sqdecw x0, w0, vl2
--.*: 04a0f860 sqdecw x0, w0, vl3
--.*: 04a0f860 sqdecw x0, w0, vl3
--.*: 04a0f860 sqdecw x0, w0, vl3
--.*: 04a0f880 sqdecw x0, w0, vl4
--.*: 04a0f880 sqdecw x0, w0, vl4
--.*: 04a0f880 sqdecw x0, w0, vl4
--.*: 04a0f8a0 sqdecw x0, w0, vl5
--.*: 04a0f8a0 sqdecw x0, w0, vl5
--.*: 04a0f8a0 sqdecw x0, w0, vl5
--.*: 04a0f8c0 sqdecw x0, w0, vl6
--.*: 04a0f8c0 sqdecw x0, w0, vl6
--.*: 04a0f8c0 sqdecw x0, w0, vl6
--.*: 04a0f8e0 sqdecw x0, w0, vl7
--.*: 04a0f8e0 sqdecw x0, w0, vl7
--.*: 04a0f8e0 sqdecw x0, w0, vl7
--.*: 04a0f900 sqdecw x0, w0, vl8
--.*: 04a0f900 sqdecw x0, w0, vl8
--.*: 04a0f900 sqdecw x0, w0, vl8
--.*: 04a0f920 sqdecw x0, w0, vl16
--.*: 04a0f920 sqdecw x0, w0, vl16
--.*: 04a0f920 sqdecw x0, w0, vl16
--.*: 04a0f940 sqdecw x0, w0, vl32
--.*: 04a0f940 sqdecw x0, w0, vl32
--.*: 04a0f940 sqdecw x0, w0, vl32
--.*: 04a0f960 sqdecw x0, w0, vl64
--.*: 04a0f960 sqdecw x0, w0, vl64
--.*: 04a0f960 sqdecw x0, w0, vl64
--.*: 04a0f980 sqdecw x0, w0, vl128
--.*: 04a0f980 sqdecw x0, w0, vl128
--.*: 04a0f980 sqdecw x0, w0, vl128
--.*: 04a0f9a0 sqdecw x0, w0, vl256
--.*: 04a0f9a0 sqdecw x0, w0, vl256
--.*: 04a0f9a0 sqdecw x0, w0, vl256
--.*: 04a0f9c0 sqdecw x0, w0, #14
--.*: 04a0f9c0 sqdecw x0, w0, #14
--.*: 04a0f9c0 sqdecw x0, w0, #14
--.*: 04a0f9e0 sqdecw x0, w0, #15
--.*: 04a0f9e0 sqdecw x0, w0, #15
--.*: 04a0f9e0 sqdecw x0, w0, #15
--.*: 04a0fa00 sqdecw x0, w0, #16
--.*: 04a0fa00 sqdecw x0, w0, #16
--.*: 04a0fa00 sqdecw x0, w0, #16
--.*: 04a0fa20 sqdecw x0, w0, #17
--.*: 04a0fa20 sqdecw x0, w0, #17
--.*: 04a0fa20 sqdecw x0, w0, #17
--.*: 04a0fa40 sqdecw x0, w0, #18
--.*: 04a0fa40 sqdecw x0, w0, #18
--.*: 04a0fa40 sqdecw x0, w0, #18
--.*: 04a0fa60 sqdecw x0, w0, #19
--.*: 04a0fa60 sqdecw x0, w0, #19
--.*: 04a0fa60 sqdecw x0, w0, #19
--.*: 04a0fa80 sqdecw x0, w0, #20
--.*: 04a0fa80 sqdecw x0, w0, #20
--.*: 04a0fa80 sqdecw x0, w0, #20
--.*: 04a0faa0 sqdecw x0, w0, #21
--.*: 04a0faa0 sqdecw x0, w0, #21
--.*: 04a0faa0 sqdecw x0, w0, #21
--.*: 04a0fac0 sqdecw x0, w0, #22
--.*: 04a0fac0 sqdecw x0, w0, #22
--.*: 04a0fac0 sqdecw x0, w0, #22
--.*: 04a0fae0 sqdecw x0, w0, #23
--.*: 04a0fae0 sqdecw x0, w0, #23
--.*: 04a0fae0 sqdecw x0, w0, #23
--.*: 04a0fb00 sqdecw x0, w0, #24
--.*: 04a0fb00 sqdecw x0, w0, #24
--.*: 04a0fb00 sqdecw x0, w0, #24
--.*: 04a0fb20 sqdecw x0, w0, #25
--.*: 04a0fb20 sqdecw x0, w0, #25
--.*: 04a0fb20 sqdecw x0, w0, #25
--.*: 04a0fb40 sqdecw x0, w0, #26
--.*: 04a0fb40 sqdecw x0, w0, #26
--.*: 04a0fb40 sqdecw x0, w0, #26
--.*: 04a0fb60 sqdecw x0, w0, #27
--.*: 04a0fb60 sqdecw x0, w0, #27
--.*: 04a0fb60 sqdecw x0, w0, #27
--.*: 04a0fb80 sqdecw x0, w0, #28
--.*: 04a0fb80 sqdecw x0, w0, #28
--.*: 04a0fb80 sqdecw x0, w0, #28
--.*: 04a0fba0 sqdecw x0, w0, mul4
--.*: 04a0fba0 sqdecw x0, w0, mul4
--.*: 04a0fba0 sqdecw x0, w0, mul4
--.*: 04a0fbc0 sqdecw x0, w0, mul3
--.*: 04a0fbc0 sqdecw x0, w0, mul3
--.*: 04a0fbc0 sqdecw x0, w0, mul3
--.*: 04a0fbe0 sqdecw x0, w0
--.*: 04a0fbe0 sqdecw x0, w0
--.*: 04a0fbe0 sqdecw x0, w0
--.*: 04a0fbe0 sqdecw x0, w0
--.*: 04a7f800 sqdecw x0, w0, pow2, mul #8
--.*: 04a7f800 sqdecw x0, w0, pow2, mul #8
--.*: 04a8f800 sqdecw x0, w0, pow2, mul #9
--.*: 04a8f800 sqdecw x0, w0, pow2, mul #9
--.*: 04a9f800 sqdecw x0, w0, pow2, mul #10
--.*: 04a9f800 sqdecw x0, w0, pow2, mul #10
--.*: 04aff800 sqdecw x0, w0, pow2, mul #16
--.*: 04aff800 sqdecw x0, w0, pow2, mul #16
--.*: 0430f000 sqincb x0, pow2
--.*: 0430f000 sqincb x0, pow2
--.*: 0430f000 sqincb x0, pow2
--.*: 0430f001 sqincb x1, pow2
--.*: 0430f001 sqincb x1, pow2
--.*: 0430f001 sqincb x1, pow2
--.*: 0430f01f sqincb xzr, pow2
--.*: 0430f01f sqincb xzr, pow2
--.*: 0430f01f sqincb xzr, pow2
--.*: 0430f020 sqincb x0, vl1
--.*: 0430f020 sqincb x0, vl1
--.*: 0430f020 sqincb x0, vl1
--.*: 0430f040 sqincb x0, vl2
--.*: 0430f040 sqincb x0, vl2
--.*: 0430f040 sqincb x0, vl2
--.*: 0430f060 sqincb x0, vl3
--.*: 0430f060 sqincb x0, vl3
--.*: 0430f060 sqincb x0, vl3
--.*: 0430f080 sqincb x0, vl4
--.*: 0430f080 sqincb x0, vl4
--.*: 0430f080 sqincb x0, vl4
--.*: 0430f0a0 sqincb x0, vl5
--.*: 0430f0a0 sqincb x0, vl5
--.*: 0430f0a0 sqincb x0, vl5
--.*: 0430f0c0 sqincb x0, vl6
--.*: 0430f0c0 sqincb x0, vl6
--.*: 0430f0c0 sqincb x0, vl6
--.*: 0430f0e0 sqincb x0, vl7
--.*: 0430f0e0 sqincb x0, vl7
--.*: 0430f0e0 sqincb x0, vl7
--.*: 0430f100 sqincb x0, vl8
--.*: 0430f100 sqincb x0, vl8
--.*: 0430f100 sqincb x0, vl8
--.*: 0430f120 sqincb x0, vl16
--.*: 0430f120 sqincb x0, vl16
--.*: 0430f120 sqincb x0, vl16
--.*: 0430f140 sqincb x0, vl32
--.*: 0430f140 sqincb x0, vl32
--.*: 0430f140 sqincb x0, vl32
--.*: 0430f160 sqincb x0, vl64
--.*: 0430f160 sqincb x0, vl64
--.*: 0430f160 sqincb x0, vl64
--.*: 0430f180 sqincb x0, vl128
--.*: 0430f180 sqincb x0, vl128
--.*: 0430f180 sqincb x0, vl128
--.*: 0430f1a0 sqincb x0, vl256
--.*: 0430f1a0 sqincb x0, vl256
--.*: 0430f1a0 sqincb x0, vl256
--.*: 0430f1c0 sqincb x0, #14
--.*: 0430f1c0 sqincb x0, #14
--.*: 0430f1c0 sqincb x0, #14
--.*: 0430f1e0 sqincb x0, #15
--.*: 0430f1e0 sqincb x0, #15
--.*: 0430f1e0 sqincb x0, #15
--.*: 0430f200 sqincb x0, #16
--.*: 0430f200 sqincb x0, #16
--.*: 0430f200 sqincb x0, #16
--.*: 0430f220 sqincb x0, #17
--.*: 0430f220 sqincb x0, #17
--.*: 0430f220 sqincb x0, #17
--.*: 0430f240 sqincb x0, #18
--.*: 0430f240 sqincb x0, #18
--.*: 0430f240 sqincb x0, #18
--.*: 0430f260 sqincb x0, #19
--.*: 0430f260 sqincb x0, #19
--.*: 0430f260 sqincb x0, #19
--.*: 0430f280 sqincb x0, #20
--.*: 0430f280 sqincb x0, #20
--.*: 0430f280 sqincb x0, #20
--.*: 0430f2a0 sqincb x0, #21
--.*: 0430f2a0 sqincb x0, #21
--.*: 0430f2a0 sqincb x0, #21
--.*: 0430f2c0 sqincb x0, #22
--.*: 0430f2c0 sqincb x0, #22
--.*: 0430f2c0 sqincb x0, #22
--.*: 0430f2e0 sqincb x0, #23
--.*: 0430f2e0 sqincb x0, #23
--.*: 0430f2e0 sqincb x0, #23
--.*: 0430f300 sqincb x0, #24
--.*: 0430f300 sqincb x0, #24
--.*: 0430f300 sqincb x0, #24
--.*: 0430f320 sqincb x0, #25
--.*: 0430f320 sqincb x0, #25
--.*: 0430f320 sqincb x0, #25
--.*: 0430f340 sqincb x0, #26
--.*: 0430f340 sqincb x0, #26
--.*: 0430f340 sqincb x0, #26
--.*: 0430f360 sqincb x0, #27
--.*: 0430f360 sqincb x0, #27
--.*: 0430f360 sqincb x0, #27
--.*: 0430f380 sqincb x0, #28
--.*: 0430f380 sqincb x0, #28
--.*: 0430f380 sqincb x0, #28
--.*: 0430f3a0 sqincb x0, mul4
--.*: 0430f3a0 sqincb x0, mul4
--.*: 0430f3a0 sqincb x0, mul4
--.*: 0430f3c0 sqincb x0, mul3
--.*: 0430f3c0 sqincb x0, mul3
--.*: 0430f3c0 sqincb x0, mul3
--.*: 0430f3e0 sqincb x0
--.*: 0430f3e0 sqincb x0
--.*: 0430f3e0 sqincb x0
--.*: 0430f3e0 sqincb x0
--.*: 0437f000 sqincb x0, pow2, mul #8
--.*: 0437f000 sqincb x0, pow2, mul #8
--.*: 0438f000 sqincb x0, pow2, mul #9
--.*: 0438f000 sqincb x0, pow2, mul #9
--.*: 0439f000 sqincb x0, pow2, mul #10
--.*: 0439f000 sqincb x0, pow2, mul #10
--.*: 043ff000 sqincb x0, pow2, mul #16
--.*: 043ff000 sqincb x0, pow2, mul #16
--.*: 0420f000 sqincb x0, w0, pow2
--.*: 0420f000 sqincb x0, w0, pow2
--.*: 0420f000 sqincb x0, w0, pow2
--.*: 0420f001 sqincb x1, w1, pow2
--.*: 0420f001 sqincb x1, w1, pow2
--.*: 0420f001 sqincb x1, w1, pow2
--.*: 0420f01f sqincb xzr, wzr, pow2
--.*: 0420f01f sqincb xzr, wzr, pow2
--.*: 0420f01f sqincb xzr, wzr, pow2
--.*: 0420f002 sqincb x2, w2, pow2
--.*: 0420f002 sqincb x2, w2, pow2
--.*: 0420f002 sqincb x2, w2, pow2
--.*: 0420f020 sqincb x0, w0, vl1
--.*: 0420f020 sqincb x0, w0, vl1
--.*: 0420f020 sqincb x0, w0, vl1
--.*: 0420f040 sqincb x0, w0, vl2
--.*: 0420f040 sqincb x0, w0, vl2
--.*: 0420f040 sqincb x0, w0, vl2
--.*: 0420f060 sqincb x0, w0, vl3
--.*: 0420f060 sqincb x0, w0, vl3
--.*: 0420f060 sqincb x0, w0, vl3
--.*: 0420f080 sqincb x0, w0, vl4
--.*: 0420f080 sqincb x0, w0, vl4
--.*: 0420f080 sqincb x0, w0, vl4
--.*: 0420f0a0 sqincb x0, w0, vl5
--.*: 0420f0a0 sqincb x0, w0, vl5
--.*: 0420f0a0 sqincb x0, w0, vl5
--.*: 0420f0c0 sqincb x0, w0, vl6
--.*: 0420f0c0 sqincb x0, w0, vl6
--.*: 0420f0c0 sqincb x0, w0, vl6
--.*: 0420f0e0 sqincb x0, w0, vl7
--.*: 0420f0e0 sqincb x0, w0, vl7
--.*: 0420f0e0 sqincb x0, w0, vl7
--.*: 0420f100 sqincb x0, w0, vl8
--.*: 0420f100 sqincb x0, w0, vl8
--.*: 0420f100 sqincb x0, w0, vl8
--.*: 0420f120 sqincb x0, w0, vl16
--.*: 0420f120 sqincb x0, w0, vl16
--.*: 0420f120 sqincb x0, w0, vl16
--.*: 0420f140 sqincb x0, w0, vl32
--.*: 0420f140 sqincb x0, w0, vl32
--.*: 0420f140 sqincb x0, w0, vl32
--.*: 0420f160 sqincb x0, w0, vl64
--.*: 0420f160 sqincb x0, w0, vl64
--.*: 0420f160 sqincb x0, w0, vl64
--.*: 0420f180 sqincb x0, w0, vl128
--.*: 0420f180 sqincb x0, w0, vl128
--.*: 0420f180 sqincb x0, w0, vl128
--.*: 0420f1a0 sqincb x0, w0, vl256
--.*: 0420f1a0 sqincb x0, w0, vl256
--.*: 0420f1a0 sqincb x0, w0, vl256
--.*: 0420f1c0 sqincb x0, w0, #14
--.*: 0420f1c0 sqincb x0, w0, #14
--.*: 0420f1c0 sqincb x0, w0, #14
--.*: 0420f1e0 sqincb x0, w0, #15
--.*: 0420f1e0 sqincb x0, w0, #15
--.*: 0420f1e0 sqincb x0, w0, #15
--.*: 0420f200 sqincb x0, w0, #16
--.*: 0420f200 sqincb x0, w0, #16
--.*: 0420f200 sqincb x0, w0, #16
--.*: 0420f220 sqincb x0, w0, #17
--.*: 0420f220 sqincb x0, w0, #17
--.*: 0420f220 sqincb x0, w0, #17
--.*: 0420f240 sqincb x0, w0, #18
--.*: 0420f240 sqincb x0, w0, #18
--.*: 0420f240 sqincb x0, w0, #18
--.*: 0420f260 sqincb x0, w0, #19
--.*: 0420f260 sqincb x0, w0, #19
--.*: 0420f260 sqincb x0, w0, #19
--.*: 0420f280 sqincb x0, w0, #20
--.*: 0420f280 sqincb x0, w0, #20
--.*: 0420f280 sqincb x0, w0, #20
--.*: 0420f2a0 sqincb x0, w0, #21
--.*: 0420f2a0 sqincb x0, w0, #21
--.*: 0420f2a0 sqincb x0, w0, #21
--.*: 0420f2c0 sqincb x0, w0, #22
--.*: 0420f2c0 sqincb x0, w0, #22
--.*: 0420f2c0 sqincb x0, w0, #22
--.*: 0420f2e0 sqincb x0, w0, #23
--.*: 0420f2e0 sqincb x0, w0, #23
--.*: 0420f2e0 sqincb x0, w0, #23
--.*: 0420f300 sqincb x0, w0, #24
--.*: 0420f300 sqincb x0, w0, #24
--.*: 0420f300 sqincb x0, w0, #24
--.*: 0420f320 sqincb x0, w0, #25
--.*: 0420f320 sqincb x0, w0, #25
--.*: 0420f320 sqincb x0, w0, #25
--.*: 0420f340 sqincb x0, w0, #26
--.*: 0420f340 sqincb x0, w0, #26
--.*: 0420f340 sqincb x0, w0, #26
--.*: 0420f360 sqincb x0, w0, #27
--.*: 0420f360 sqincb x0, w0, #27
--.*: 0420f360 sqincb x0, w0, #27
--.*: 0420f380 sqincb x0, w0, #28
--.*: 0420f380 sqincb x0, w0, #28
--.*: 0420f380 sqincb x0, w0, #28
--.*: 0420f3a0 sqincb x0, w0, mul4
--.*: 0420f3a0 sqincb x0, w0, mul4
--.*: 0420f3a0 sqincb x0, w0, mul4
--.*: 0420f3c0 sqincb x0, w0, mul3
--.*: 0420f3c0 sqincb x0, w0, mul3
--.*: 0420f3c0 sqincb x0, w0, mul3
--.*: 0420f3e0 sqincb x0, w0
--.*: 0420f3e0 sqincb x0, w0
--.*: 0420f3e0 sqincb x0, w0
--.*: 0420f3e0 sqincb x0, w0
--.*: 0427f000 sqincb x0, w0, pow2, mul #8
--.*: 0427f000 sqincb x0, w0, pow2, mul #8
--.*: 0428f000 sqincb x0, w0, pow2, mul #9
--.*: 0428f000 sqincb x0, w0, pow2, mul #9
--.*: 0429f000 sqincb x0, w0, pow2, mul #10
--.*: 0429f000 sqincb x0, w0, pow2, mul #10
--.*: 042ff000 sqincb x0, w0, pow2, mul #16
--.*: 042ff000 sqincb x0, w0, pow2, mul #16
--.*: 04e0c000 sqincd z0\.d, pow2
--.*: 04e0c000 sqincd z0\.d, pow2
--.*: 04e0c000 sqincd z0\.d, pow2
--.*: 04e0c001 sqincd z1\.d, pow2
--.*: 04e0c001 sqincd z1\.d, pow2
--.*: 04e0c001 sqincd z1\.d, pow2
--.*: 04e0c01f sqincd z31\.d, pow2
--.*: 04e0c01f sqincd z31\.d, pow2
--.*: 04e0c01f sqincd z31\.d, pow2
--.*: 04e0c020 sqincd z0\.d, vl1
--.*: 04e0c020 sqincd z0\.d, vl1
--.*: 04e0c020 sqincd z0\.d, vl1
--.*: 04e0c040 sqincd z0\.d, vl2
--.*: 04e0c040 sqincd z0\.d, vl2
--.*: 04e0c040 sqincd z0\.d, vl2
--.*: 04e0c060 sqincd z0\.d, vl3
--.*: 04e0c060 sqincd z0\.d, vl3
--.*: 04e0c060 sqincd z0\.d, vl3
--.*: 04e0c080 sqincd z0\.d, vl4
--.*: 04e0c080 sqincd z0\.d, vl4
--.*: 04e0c080 sqincd z0\.d, vl4
--.*: 04e0c0a0 sqincd z0\.d, vl5
--.*: 04e0c0a0 sqincd z0\.d, vl5
--.*: 04e0c0a0 sqincd z0\.d, vl5
--.*: 04e0c0c0 sqincd z0\.d, vl6
--.*: 04e0c0c0 sqincd z0\.d, vl6
--.*: 04e0c0c0 sqincd z0\.d, vl6
--.*: 04e0c0e0 sqincd z0\.d, vl7
--.*: 04e0c0e0 sqincd z0\.d, vl7
--.*: 04e0c0e0 sqincd z0\.d, vl7
--.*: 04e0c100 sqincd z0\.d, vl8
--.*: 04e0c100 sqincd z0\.d, vl8
--.*: 04e0c100 sqincd z0\.d, vl8
--.*: 04e0c120 sqincd z0\.d, vl16
--.*: 04e0c120 sqincd z0\.d, vl16
--.*: 04e0c120 sqincd z0\.d, vl16
--.*: 04e0c140 sqincd z0\.d, vl32
--.*: 04e0c140 sqincd z0\.d, vl32
--.*: 04e0c140 sqincd z0\.d, vl32
--.*: 04e0c160 sqincd z0\.d, vl64
--.*: 04e0c160 sqincd z0\.d, vl64
--.*: 04e0c160 sqincd z0\.d, vl64
--.*: 04e0c180 sqincd z0\.d, vl128
--.*: 04e0c180 sqincd z0\.d, vl128
--.*: 04e0c180 sqincd z0\.d, vl128
--.*: 04e0c1a0 sqincd z0\.d, vl256
--.*: 04e0c1a0 sqincd z0\.d, vl256
--.*: 04e0c1a0 sqincd z0\.d, vl256
--.*: 04e0c1c0 sqincd z0\.d, #14
--.*: 04e0c1c0 sqincd z0\.d, #14
--.*: 04e0c1c0 sqincd z0\.d, #14
--.*: 04e0c1e0 sqincd z0\.d, #15
--.*: 04e0c1e0 sqincd z0\.d, #15
--.*: 04e0c1e0 sqincd z0\.d, #15
--.*: 04e0c200 sqincd z0\.d, #16
--.*: 04e0c200 sqincd z0\.d, #16
--.*: 04e0c200 sqincd z0\.d, #16
--.*: 04e0c220 sqincd z0\.d, #17
--.*: 04e0c220 sqincd z0\.d, #17
--.*: 04e0c220 sqincd z0\.d, #17
--.*: 04e0c240 sqincd z0\.d, #18
--.*: 04e0c240 sqincd z0\.d, #18
--.*: 04e0c240 sqincd z0\.d, #18
--.*: 04e0c260 sqincd z0\.d, #19
--.*: 04e0c260 sqincd z0\.d, #19
--.*: 04e0c260 sqincd z0\.d, #19
--.*: 04e0c280 sqincd z0\.d, #20
--.*: 04e0c280 sqincd z0\.d, #20
--.*: 04e0c280 sqincd z0\.d, #20
--.*: 04e0c2a0 sqincd z0\.d, #21
--.*: 04e0c2a0 sqincd z0\.d, #21
--.*: 04e0c2a0 sqincd z0\.d, #21
--.*: 04e0c2c0 sqincd z0\.d, #22
--.*: 04e0c2c0 sqincd z0\.d, #22
--.*: 04e0c2c0 sqincd z0\.d, #22
--.*: 04e0c2e0 sqincd z0\.d, #23
--.*: 04e0c2e0 sqincd z0\.d, #23
--.*: 04e0c2e0 sqincd z0\.d, #23
--.*: 04e0c300 sqincd z0\.d, #24
--.*: 04e0c300 sqincd z0\.d, #24
--.*: 04e0c300 sqincd z0\.d, #24
--.*: 04e0c320 sqincd z0\.d, #25
--.*: 04e0c320 sqincd z0\.d, #25
--.*: 04e0c320 sqincd z0\.d, #25
--.*: 04e0c340 sqincd z0\.d, #26
--.*: 04e0c340 sqincd z0\.d, #26
--.*: 04e0c340 sqincd z0\.d, #26
--.*: 04e0c360 sqincd z0\.d, #27
--.*: 04e0c360 sqincd z0\.d, #27
--.*: 04e0c360 sqincd z0\.d, #27
--.*: 04e0c380 sqincd z0\.d, #28
--.*: 04e0c380 sqincd z0\.d, #28
--.*: 04e0c380 sqincd z0\.d, #28
--.*: 04e0c3a0 sqincd z0\.d, mul4
--.*: 04e0c3a0 sqincd z0\.d, mul4
--.*: 04e0c3a0 sqincd z0\.d, mul4
--.*: 04e0c3c0 sqincd z0\.d, mul3
--.*: 04e0c3c0 sqincd z0\.d, mul3
--.*: 04e0c3c0 sqincd z0\.d, mul3
--.*: 04e0c3e0 sqincd z0\.d
--.*: 04e0c3e0 sqincd z0\.d
--.*: 04e0c3e0 sqincd z0\.d
--.*: 04e0c3e0 sqincd z0\.d
--.*: 04e7c000 sqincd z0\.d, pow2, mul #8
--.*: 04e7c000 sqincd z0\.d, pow2, mul #8
--.*: 04e8c000 sqincd z0\.d, pow2, mul #9
--.*: 04e8c000 sqincd z0\.d, pow2, mul #9
--.*: 04e9c000 sqincd z0\.d, pow2, mul #10
--.*: 04e9c000 sqincd z0\.d, pow2, mul #10
--.*: 04efc000 sqincd z0\.d, pow2, mul #16
--.*: 04efc000 sqincd z0\.d, pow2, mul #16
--.*: 04f0f000 sqincd x0, pow2
--.*: 04f0f000 sqincd x0, pow2
--.*: 04f0f000 sqincd x0, pow2
--.*: 04f0f001 sqincd x1, pow2
--.*: 04f0f001 sqincd x1, pow2
--.*: 04f0f001 sqincd x1, pow2
--.*: 04f0f01f sqincd xzr, pow2
--.*: 04f0f01f sqincd xzr, pow2
--.*: 04f0f01f sqincd xzr, pow2
--.*: 04f0f020 sqincd x0, vl1
--.*: 04f0f020 sqincd x0, vl1
--.*: 04f0f020 sqincd x0, vl1
--.*: 04f0f040 sqincd x0, vl2
--.*: 04f0f040 sqincd x0, vl2
--.*: 04f0f040 sqincd x0, vl2
--.*: 04f0f060 sqincd x0, vl3
--.*: 04f0f060 sqincd x0, vl3
--.*: 04f0f060 sqincd x0, vl3
--.*: 04f0f080 sqincd x0, vl4
--.*: 04f0f080 sqincd x0, vl4
--.*: 04f0f080 sqincd x0, vl4
--.*: 04f0f0a0 sqincd x0, vl5
--.*: 04f0f0a0 sqincd x0, vl5
--.*: 04f0f0a0 sqincd x0, vl5
--.*: 04f0f0c0 sqincd x0, vl6
--.*: 04f0f0c0 sqincd x0, vl6
--.*: 04f0f0c0 sqincd x0, vl6
--.*: 04f0f0e0 sqincd x0, vl7
--.*: 04f0f0e0 sqincd x0, vl7
--.*: 04f0f0e0 sqincd x0, vl7
--.*: 04f0f100 sqincd x0, vl8
--.*: 04f0f100 sqincd x0, vl8
--.*: 04f0f100 sqincd x0, vl8
--.*: 04f0f120 sqincd x0, vl16
--.*: 04f0f120 sqincd x0, vl16
--.*: 04f0f120 sqincd x0, vl16
--.*: 04f0f140 sqincd x0, vl32
--.*: 04f0f140 sqincd x0, vl32
--.*: 04f0f140 sqincd x0, vl32
--.*: 04f0f160 sqincd x0, vl64
--.*: 04f0f160 sqincd x0, vl64
--.*: 04f0f160 sqincd x0, vl64
--.*: 04f0f180 sqincd x0, vl128
--.*: 04f0f180 sqincd x0, vl128
--.*: 04f0f180 sqincd x0, vl128
--.*: 04f0f1a0 sqincd x0, vl256
--.*: 04f0f1a0 sqincd x0, vl256
--.*: 04f0f1a0 sqincd x0, vl256
--.*: 04f0f1c0 sqincd x0, #14
--.*: 04f0f1c0 sqincd x0, #14
--.*: 04f0f1c0 sqincd x0, #14
--.*: 04f0f1e0 sqincd x0, #15
--.*: 04f0f1e0 sqincd x0, #15
--.*: 04f0f1e0 sqincd x0, #15
--.*: 04f0f200 sqincd x0, #16
--.*: 04f0f200 sqincd x0, #16
--.*: 04f0f200 sqincd x0, #16
--.*: 04f0f220 sqincd x0, #17
--.*: 04f0f220 sqincd x0, #17
--.*: 04f0f220 sqincd x0, #17
--.*: 04f0f240 sqincd x0, #18
--.*: 04f0f240 sqincd x0, #18
--.*: 04f0f240 sqincd x0, #18
--.*: 04f0f260 sqincd x0, #19
--.*: 04f0f260 sqincd x0, #19
--.*: 04f0f260 sqincd x0, #19
--.*: 04f0f280 sqincd x0, #20
--.*: 04f0f280 sqincd x0, #20
--.*: 04f0f280 sqincd x0, #20
--.*: 04f0f2a0 sqincd x0, #21
--.*: 04f0f2a0 sqincd x0, #21
--.*: 04f0f2a0 sqincd x0, #21
--.*: 04f0f2c0 sqincd x0, #22
--.*: 04f0f2c0 sqincd x0, #22
--.*: 04f0f2c0 sqincd x0, #22
--.*: 04f0f2e0 sqincd x0, #23
--.*: 04f0f2e0 sqincd x0, #23
--.*: 04f0f2e0 sqincd x0, #23
--.*: 04f0f300 sqincd x0, #24
--.*: 04f0f300 sqincd x0, #24
--.*: 04f0f300 sqincd x0, #24
--.*: 04f0f320 sqincd x0, #25
--.*: 04f0f320 sqincd x0, #25
--.*: 04f0f320 sqincd x0, #25
--.*: 04f0f340 sqincd x0, #26
--.*: 04f0f340 sqincd x0, #26
--.*: 04f0f340 sqincd x0, #26
--.*: 04f0f360 sqincd x0, #27
--.*: 04f0f360 sqincd x0, #27
--.*: 04f0f360 sqincd x0, #27
--.*: 04f0f380 sqincd x0, #28
--.*: 04f0f380 sqincd x0, #28
--.*: 04f0f380 sqincd x0, #28
--.*: 04f0f3a0 sqincd x0, mul4
--.*: 04f0f3a0 sqincd x0, mul4
--.*: 04f0f3a0 sqincd x0, mul4
--.*: 04f0f3c0 sqincd x0, mul3
--.*: 04f0f3c0 sqincd x0, mul3
--.*: 04f0f3c0 sqincd x0, mul3
--.*: 04f0f3e0 sqincd x0
--.*: 04f0f3e0 sqincd x0
--.*: 04f0f3e0 sqincd x0
--.*: 04f0f3e0 sqincd x0
--.*: 04f7f000 sqincd x0, pow2, mul #8
--.*: 04f7f000 sqincd x0, pow2, mul #8
--.*: 04f8f000 sqincd x0, pow2, mul #9
--.*: 04f8f000 sqincd x0, pow2, mul #9
--.*: 04f9f000 sqincd x0, pow2, mul #10
--.*: 04f9f000 sqincd x0, pow2, mul #10
--.*: 04fff000 sqincd x0, pow2, mul #16
--.*: 04fff000 sqincd x0, pow2, mul #16
--.*: 04e0f000 sqincd x0, w0, pow2
--.*: 04e0f000 sqincd x0, w0, pow2
--.*: 04e0f000 sqincd x0, w0, pow2
--.*: 04e0f001 sqincd x1, w1, pow2
--.*: 04e0f001 sqincd x1, w1, pow2
--.*: 04e0f001 sqincd x1, w1, pow2
--.*: 04e0f01f sqincd xzr, wzr, pow2
--.*: 04e0f01f sqincd xzr, wzr, pow2
--.*: 04e0f01f sqincd xzr, wzr, pow2
--.*: 04e0f002 sqincd x2, w2, pow2
--.*: 04e0f002 sqincd x2, w2, pow2
--.*: 04e0f002 sqincd x2, w2, pow2
--.*: 04e0f020 sqincd x0, w0, vl1
--.*: 04e0f020 sqincd x0, w0, vl1
--.*: 04e0f020 sqincd x0, w0, vl1
--.*: 04e0f040 sqincd x0, w0, vl2
--.*: 04e0f040 sqincd x0, w0, vl2
--.*: 04e0f040 sqincd x0, w0, vl2
--.*: 04e0f060 sqincd x0, w0, vl3
--.*: 04e0f060 sqincd x0, w0, vl3
--.*: 04e0f060 sqincd x0, w0, vl3
--.*: 04e0f080 sqincd x0, w0, vl4
--.*: 04e0f080 sqincd x0, w0, vl4
--.*: 04e0f080 sqincd x0, w0, vl4
--.*: 04e0f0a0 sqincd x0, w0, vl5
--.*: 04e0f0a0 sqincd x0, w0, vl5
--.*: 04e0f0a0 sqincd x0, w0, vl5
--.*: 04e0f0c0 sqincd x0, w0, vl6
--.*: 04e0f0c0 sqincd x0, w0, vl6
--.*: 04e0f0c0 sqincd x0, w0, vl6
--.*: 04e0f0e0 sqincd x0, w0, vl7
--.*: 04e0f0e0 sqincd x0, w0, vl7
--.*: 04e0f0e0 sqincd x0, w0, vl7
--.*: 04e0f100 sqincd x0, w0, vl8
--.*: 04e0f100 sqincd x0, w0, vl8
--.*: 04e0f100 sqincd x0, w0, vl8
--.*: 04e0f120 sqincd x0, w0, vl16
--.*: 04e0f120 sqincd x0, w0, vl16
--.*: 04e0f120 sqincd x0, w0, vl16
--.*: 04e0f140 sqincd x0, w0, vl32
--.*: 04e0f140 sqincd x0, w0, vl32
--.*: 04e0f140 sqincd x0, w0, vl32
--.*: 04e0f160 sqincd x0, w0, vl64
--.*: 04e0f160 sqincd x0, w0, vl64
--.*: 04e0f160 sqincd x0, w0, vl64
--.*: 04e0f180 sqincd x0, w0, vl128
--.*: 04e0f180 sqincd x0, w0, vl128
--.*: 04e0f180 sqincd x0, w0, vl128
--.*: 04e0f1a0 sqincd x0, w0, vl256
--.*: 04e0f1a0 sqincd x0, w0, vl256
--.*: 04e0f1a0 sqincd x0, w0, vl256
--.*: 04e0f1c0 sqincd x0, w0, #14
--.*: 04e0f1c0 sqincd x0, w0, #14
--.*: 04e0f1c0 sqincd x0, w0, #14
--.*: 04e0f1e0 sqincd x0, w0, #15
--.*: 04e0f1e0 sqincd x0, w0, #15
--.*: 04e0f1e0 sqincd x0, w0, #15
--.*: 04e0f200 sqincd x0, w0, #16
--.*: 04e0f200 sqincd x0, w0, #16
--.*: 04e0f200 sqincd x0, w0, #16
--.*: 04e0f220 sqincd x0, w0, #17
--.*: 04e0f220 sqincd x0, w0, #17
--.*: 04e0f220 sqincd x0, w0, #17
--.*: 04e0f240 sqincd x0, w0, #18
--.*: 04e0f240 sqincd x0, w0, #18
--.*: 04e0f240 sqincd x0, w0, #18
--.*: 04e0f260 sqincd x0, w0, #19
--.*: 04e0f260 sqincd x0, w0, #19
--.*: 04e0f260 sqincd x0, w0, #19
--.*: 04e0f280 sqincd x0, w0, #20
--.*: 04e0f280 sqincd x0, w0, #20
--.*: 04e0f280 sqincd x0, w0, #20
--.*: 04e0f2a0 sqincd x0, w0, #21
--.*: 04e0f2a0 sqincd x0, w0, #21
--.*: 04e0f2a0 sqincd x0, w0, #21
--.*: 04e0f2c0 sqincd x0, w0, #22
--.*: 04e0f2c0 sqincd x0, w0, #22
--.*: 04e0f2c0 sqincd x0, w0, #22
--.*: 04e0f2e0 sqincd x0, w0, #23
--.*: 04e0f2e0 sqincd x0, w0, #23
--.*: 04e0f2e0 sqincd x0, w0, #23
--.*: 04e0f300 sqincd x0, w0, #24
--.*: 04e0f300 sqincd x0, w0, #24
--.*: 04e0f300 sqincd x0, w0, #24
--.*: 04e0f320 sqincd x0, w0, #25
--.*: 04e0f320 sqincd x0, w0, #25
--.*: 04e0f320 sqincd x0, w0, #25
--.*: 04e0f340 sqincd x0, w0, #26
--.*: 04e0f340 sqincd x0, w0, #26
--.*: 04e0f340 sqincd x0, w0, #26
--.*: 04e0f360 sqincd x0, w0, #27
--.*: 04e0f360 sqincd x0, w0, #27
--.*: 04e0f360 sqincd x0, w0, #27
--.*: 04e0f380 sqincd x0, w0, #28
--.*: 04e0f380 sqincd x0, w0, #28
--.*: 04e0f380 sqincd x0, w0, #28
--.*: 04e0f3a0 sqincd x0, w0, mul4
--.*: 04e0f3a0 sqincd x0, w0, mul4
--.*: 04e0f3a0 sqincd x0, w0, mul4
--.*: 04e0f3c0 sqincd x0, w0, mul3
--.*: 04e0f3c0 sqincd x0, w0, mul3
--.*: 04e0f3c0 sqincd x0, w0, mul3
--.*: 04e0f3e0 sqincd x0, w0
--.*: 04e0f3e0 sqincd x0, w0
--.*: 04e0f3e0 sqincd x0, w0
--.*: 04e0f3e0 sqincd x0, w0
--.*: 04e7f000 sqincd x0, w0, pow2, mul #8
--.*: 04e7f000 sqincd x0, w0, pow2, mul #8
--.*: 04e8f000 sqincd x0, w0, pow2, mul #9
--.*: 04e8f000 sqincd x0, w0, pow2, mul #9
--.*: 04e9f000 sqincd x0, w0, pow2, mul #10
--.*: 04e9f000 sqincd x0, w0, pow2, mul #10
--.*: 04eff000 sqincd x0, w0, pow2, mul #16
--.*: 04eff000 sqincd x0, w0, pow2, mul #16
--.*: 0460c000 sqinch z0\.h, pow2
--.*: 0460c000 sqinch z0\.h, pow2
--.*: 0460c000 sqinch z0\.h, pow2
--.*: 0460c001 sqinch z1\.h, pow2
--.*: 0460c001 sqinch z1\.h, pow2
--.*: 0460c001 sqinch z1\.h, pow2
--.*: 0460c01f sqinch z31\.h, pow2
--.*: 0460c01f sqinch z31\.h, pow2
--.*: 0460c01f sqinch z31\.h, pow2
--.*: 0460c020 sqinch z0\.h, vl1
--.*: 0460c020 sqinch z0\.h, vl1
--.*: 0460c020 sqinch z0\.h, vl1
--.*: 0460c040 sqinch z0\.h, vl2
--.*: 0460c040 sqinch z0\.h, vl2
--.*: 0460c040 sqinch z0\.h, vl2
--.*: 0460c060 sqinch z0\.h, vl3
--.*: 0460c060 sqinch z0\.h, vl3
--.*: 0460c060 sqinch z0\.h, vl3
--.*: 0460c080 sqinch z0\.h, vl4
--.*: 0460c080 sqinch z0\.h, vl4
--.*: 0460c080 sqinch z0\.h, vl4
--.*: 0460c0a0 sqinch z0\.h, vl5
--.*: 0460c0a0 sqinch z0\.h, vl5
--.*: 0460c0a0 sqinch z0\.h, vl5
--.*: 0460c0c0 sqinch z0\.h, vl6
--.*: 0460c0c0 sqinch z0\.h, vl6
--.*: 0460c0c0 sqinch z0\.h, vl6
--.*: 0460c0e0 sqinch z0\.h, vl7
--.*: 0460c0e0 sqinch z0\.h, vl7
--.*: 0460c0e0 sqinch z0\.h, vl7
--.*: 0460c100 sqinch z0\.h, vl8
--.*: 0460c100 sqinch z0\.h, vl8
--.*: 0460c100 sqinch z0\.h, vl8
--.*: 0460c120 sqinch z0\.h, vl16
--.*: 0460c120 sqinch z0\.h, vl16
--.*: 0460c120 sqinch z0\.h, vl16
--.*: 0460c140 sqinch z0\.h, vl32
--.*: 0460c140 sqinch z0\.h, vl32
--.*: 0460c140 sqinch z0\.h, vl32
--.*: 0460c160 sqinch z0\.h, vl64
--.*: 0460c160 sqinch z0\.h, vl64
--.*: 0460c160 sqinch z0\.h, vl64
--.*: 0460c180 sqinch z0\.h, vl128
--.*: 0460c180 sqinch z0\.h, vl128
--.*: 0460c180 sqinch z0\.h, vl128
--.*: 0460c1a0 sqinch z0\.h, vl256
--.*: 0460c1a0 sqinch z0\.h, vl256
--.*: 0460c1a0 sqinch z0\.h, vl256
--.*: 0460c1c0 sqinch z0\.h, #14
--.*: 0460c1c0 sqinch z0\.h, #14
--.*: 0460c1c0 sqinch z0\.h, #14
--.*: 0460c1e0 sqinch z0\.h, #15
--.*: 0460c1e0 sqinch z0\.h, #15
--.*: 0460c1e0 sqinch z0\.h, #15
--.*: 0460c200 sqinch z0\.h, #16
--.*: 0460c200 sqinch z0\.h, #16
--.*: 0460c200 sqinch z0\.h, #16
--.*: 0460c220 sqinch z0\.h, #17
--.*: 0460c220 sqinch z0\.h, #17
--.*: 0460c220 sqinch z0\.h, #17
--.*: 0460c240 sqinch z0\.h, #18
--.*: 0460c240 sqinch z0\.h, #18
--.*: 0460c240 sqinch z0\.h, #18
--.*: 0460c260 sqinch z0\.h, #19
--.*: 0460c260 sqinch z0\.h, #19
--.*: 0460c260 sqinch z0\.h, #19
--.*: 0460c280 sqinch z0\.h, #20
--.*: 0460c280 sqinch z0\.h, #20
--.*: 0460c280 sqinch z0\.h, #20
--.*: 0460c2a0 sqinch z0\.h, #21
--.*: 0460c2a0 sqinch z0\.h, #21
--.*: 0460c2a0 sqinch z0\.h, #21
--.*: 0460c2c0 sqinch z0\.h, #22
--.*: 0460c2c0 sqinch z0\.h, #22
--.*: 0460c2c0 sqinch z0\.h, #22
--.*: 0460c2e0 sqinch z0\.h, #23
--.*: 0460c2e0 sqinch z0\.h, #23
--.*: 0460c2e0 sqinch z0\.h, #23
--.*: 0460c300 sqinch z0\.h, #24
--.*: 0460c300 sqinch z0\.h, #24
--.*: 0460c300 sqinch z0\.h, #24
--.*: 0460c320 sqinch z0\.h, #25
--.*: 0460c320 sqinch z0\.h, #25
--.*: 0460c320 sqinch z0\.h, #25
--.*: 0460c340 sqinch z0\.h, #26
--.*: 0460c340 sqinch z0\.h, #26
--.*: 0460c340 sqinch z0\.h, #26
--.*: 0460c360 sqinch z0\.h, #27
--.*: 0460c360 sqinch z0\.h, #27
--.*: 0460c360 sqinch z0\.h, #27
--.*: 0460c380 sqinch z0\.h, #28
--.*: 0460c380 sqinch z0\.h, #28
--.*: 0460c380 sqinch z0\.h, #28
--.*: 0460c3a0 sqinch z0\.h, mul4
--.*: 0460c3a0 sqinch z0\.h, mul4
--.*: 0460c3a0 sqinch z0\.h, mul4
--.*: 0460c3c0 sqinch z0\.h, mul3
--.*: 0460c3c0 sqinch z0\.h, mul3
--.*: 0460c3c0 sqinch z0\.h, mul3
--.*: 0460c3e0 sqinch z0\.h
--.*: 0460c3e0 sqinch z0\.h
--.*: 0460c3e0 sqinch z0\.h
--.*: 0460c3e0 sqinch z0\.h
--.*: 0467c000 sqinch z0\.h, pow2, mul #8
--.*: 0467c000 sqinch z0\.h, pow2, mul #8
--.*: 0468c000 sqinch z0\.h, pow2, mul #9
--.*: 0468c000 sqinch z0\.h, pow2, mul #9
--.*: 0469c000 sqinch z0\.h, pow2, mul #10
--.*: 0469c000 sqinch z0\.h, pow2, mul #10
--.*: 046fc000 sqinch z0\.h, pow2, mul #16
--.*: 046fc000 sqinch z0\.h, pow2, mul #16
--.*: 0470f000 sqinch x0, pow2
--.*: 0470f000 sqinch x0, pow2
--.*: 0470f000 sqinch x0, pow2
--.*: 0470f001 sqinch x1, pow2
--.*: 0470f001 sqinch x1, pow2
--.*: 0470f001 sqinch x1, pow2
--.*: 0470f01f sqinch xzr, pow2
--.*: 0470f01f sqinch xzr, pow2
--.*: 0470f01f sqinch xzr, pow2
--.*: 0470f020 sqinch x0, vl1
--.*: 0470f020 sqinch x0, vl1
--.*: 0470f020 sqinch x0, vl1
--.*: 0470f040 sqinch x0, vl2
--.*: 0470f040 sqinch x0, vl2
--.*: 0470f040 sqinch x0, vl2
--.*: 0470f060 sqinch x0, vl3
--.*: 0470f060 sqinch x0, vl3
--.*: 0470f060 sqinch x0, vl3
--.*: 0470f080 sqinch x0, vl4
--.*: 0470f080 sqinch x0, vl4
--.*: 0470f080 sqinch x0, vl4
--.*: 0470f0a0 sqinch x0, vl5
--.*: 0470f0a0 sqinch x0, vl5
--.*: 0470f0a0 sqinch x0, vl5
--.*: 0470f0c0 sqinch x0, vl6
--.*: 0470f0c0 sqinch x0, vl6
--.*: 0470f0c0 sqinch x0, vl6
--.*: 0470f0e0 sqinch x0, vl7
--.*: 0470f0e0 sqinch x0, vl7
--.*: 0470f0e0 sqinch x0, vl7
--.*: 0470f100 sqinch x0, vl8
--.*: 0470f100 sqinch x0, vl8
--.*: 0470f100 sqinch x0, vl8
--.*: 0470f120 sqinch x0, vl16
--.*: 0470f120 sqinch x0, vl16
--.*: 0470f120 sqinch x0, vl16
--.*: 0470f140 sqinch x0, vl32
--.*: 0470f140 sqinch x0, vl32
--.*: 0470f140 sqinch x0, vl32
--.*: 0470f160 sqinch x0, vl64
--.*: 0470f160 sqinch x0, vl64
--.*: 0470f160 sqinch x0, vl64
--.*: 0470f180 sqinch x0, vl128
--.*: 0470f180 sqinch x0, vl128
--.*: 0470f180 sqinch x0, vl128
--.*: 0470f1a0 sqinch x0, vl256
--.*: 0470f1a0 sqinch x0, vl256
--.*: 0470f1a0 sqinch x0, vl256
--.*: 0470f1c0 sqinch x0, #14
--.*: 0470f1c0 sqinch x0, #14
--.*: 0470f1c0 sqinch x0, #14
--.*: 0470f1e0 sqinch x0, #15
--.*: 0470f1e0 sqinch x0, #15
--.*: 0470f1e0 sqinch x0, #15
--.*: 0470f200 sqinch x0, #16
--.*: 0470f200 sqinch x0, #16
--.*: 0470f200 sqinch x0, #16
--.*: 0470f220 sqinch x0, #17
--.*: 0470f220 sqinch x0, #17
--.*: 0470f220 sqinch x0, #17
--.*: 0470f240 sqinch x0, #18
--.*: 0470f240 sqinch x0, #18
--.*: 0470f240 sqinch x0, #18
--.*: 0470f260 sqinch x0, #19
--.*: 0470f260 sqinch x0, #19
--.*: 0470f260 sqinch x0, #19
--.*: 0470f280 sqinch x0, #20
--.*: 0470f280 sqinch x0, #20
--.*: 0470f280 sqinch x0, #20
--.*: 0470f2a0 sqinch x0, #21
--.*: 0470f2a0 sqinch x0, #21
--.*: 0470f2a0 sqinch x0, #21
--.*: 0470f2c0 sqinch x0, #22
--.*: 0470f2c0 sqinch x0, #22
--.*: 0470f2c0 sqinch x0, #22
--.*: 0470f2e0 sqinch x0, #23
--.*: 0470f2e0 sqinch x0, #23
--.*: 0470f2e0 sqinch x0, #23
--.*: 0470f300 sqinch x0, #24
--.*: 0470f300 sqinch x0, #24
--.*: 0470f300 sqinch x0, #24
--.*: 0470f320 sqinch x0, #25
--.*: 0470f320 sqinch x0, #25
--.*: 0470f320 sqinch x0, #25
--.*: 0470f340 sqinch x0, #26
--.*: 0470f340 sqinch x0, #26
--.*: 0470f340 sqinch x0, #26
--.*: 0470f360 sqinch x0, #27
--.*: 0470f360 sqinch x0, #27
--.*: 0470f360 sqinch x0, #27
--.*: 0470f380 sqinch x0, #28
--.*: 0470f380 sqinch x0, #28
--.*: 0470f380 sqinch x0, #28
--.*: 0470f3a0 sqinch x0, mul4
--.*: 0470f3a0 sqinch x0, mul4
--.*: 0470f3a0 sqinch x0, mul4
--.*: 0470f3c0 sqinch x0, mul3
--.*: 0470f3c0 sqinch x0, mul3
--.*: 0470f3c0 sqinch x0, mul3
--.*: 0470f3e0 sqinch x0
--.*: 0470f3e0 sqinch x0
--.*: 0470f3e0 sqinch x0
--.*: 0470f3e0 sqinch x0
--.*: 0477f000 sqinch x0, pow2, mul #8
--.*: 0477f000 sqinch x0, pow2, mul #8
--.*: 0478f000 sqinch x0, pow2, mul #9
--.*: 0478f000 sqinch x0, pow2, mul #9
--.*: 0479f000 sqinch x0, pow2, mul #10
--.*: 0479f000 sqinch x0, pow2, mul #10
--.*: 047ff000 sqinch x0, pow2, mul #16
--.*: 047ff000 sqinch x0, pow2, mul #16
--.*: 0460f000 sqinch x0, w0, pow2
--.*: 0460f000 sqinch x0, w0, pow2
--.*: 0460f000 sqinch x0, w0, pow2
--.*: 0460f001 sqinch x1, w1, pow2
--.*: 0460f001 sqinch x1, w1, pow2
--.*: 0460f001 sqinch x1, w1, pow2
--.*: 0460f01f sqinch xzr, wzr, pow2
--.*: 0460f01f sqinch xzr, wzr, pow2
--.*: 0460f01f sqinch xzr, wzr, pow2
--.*: 0460f002 sqinch x2, w2, pow2
--.*: 0460f002 sqinch x2, w2, pow2
--.*: 0460f002 sqinch x2, w2, pow2
--.*: 0460f020 sqinch x0, w0, vl1
--.*: 0460f020 sqinch x0, w0, vl1
--.*: 0460f020 sqinch x0, w0, vl1
--.*: 0460f040 sqinch x0, w0, vl2
--.*: 0460f040 sqinch x0, w0, vl2
--.*: 0460f040 sqinch x0, w0, vl2
--.*: 0460f060 sqinch x0, w0, vl3
--.*: 0460f060 sqinch x0, w0, vl3
--.*: 0460f060 sqinch x0, w0, vl3
--.*: 0460f080 sqinch x0, w0, vl4
--.*: 0460f080 sqinch x0, w0, vl4
--.*: 0460f080 sqinch x0, w0, vl4
--.*: 0460f0a0 sqinch x0, w0, vl5
--.*: 0460f0a0 sqinch x0, w0, vl5
--.*: 0460f0a0 sqinch x0, w0, vl5
--.*: 0460f0c0 sqinch x0, w0, vl6
--.*: 0460f0c0 sqinch x0, w0, vl6
--.*: 0460f0c0 sqinch x0, w0, vl6
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--.*: 04b0f340 sqincw x0, #26
--.*: 04b0f340 sqincw x0, #26
--.*: 04b0f360 sqincw x0, #27
--.*: 04b0f360 sqincw x0, #27
--.*: 04b0f360 sqincw x0, #27
--.*: 04b0f380 sqincw x0, #28
--.*: 04b0f380 sqincw x0, #28
--.*: 04b0f380 sqincw x0, #28
--.*: 04b0f3a0 sqincw x0, mul4
--.*: 04b0f3a0 sqincw x0, mul4
--.*: 04b0f3a0 sqincw x0, mul4
--.*: 04b0f3c0 sqincw x0, mul3
--.*: 04b0f3c0 sqincw x0, mul3
--.*: 04b0f3c0 sqincw x0, mul3
--.*: 04b0f3e0 sqincw x0
--.*: 04b0f3e0 sqincw x0
--.*: 04b0f3e0 sqincw x0
--.*: 04b0f3e0 sqincw x0
--.*: 04b7f000 sqincw x0, pow2, mul #8
--.*: 04b7f000 sqincw x0, pow2, mul #8
--.*: 04b8f000 sqincw x0, pow2, mul #9
--.*: 04b8f000 sqincw x0, pow2, mul #9
--.*: 04b9f000 sqincw x0, pow2, mul #10
--.*: 04b9f000 sqincw x0, pow2, mul #10
--.*: 04bff000 sqincw x0, pow2, mul #16
--.*: 04bff000 sqincw x0, pow2, mul #16
--.*: 04a0f000 sqincw x0, w0, pow2
--.*: 04a0f000 sqincw x0, w0, pow2
--.*: 04a0f000 sqincw x0, w0, pow2
--.*: 04a0f001 sqincw x1, w1, pow2
--.*: 04a0f001 sqincw x1, w1, pow2
--.*: 04a0f001 sqincw x1, w1, pow2
--.*: 04a0f01f sqincw xzr, wzr, pow2
--.*: 04a0f01f sqincw xzr, wzr, pow2
--.*: 04a0f01f sqincw xzr, wzr, pow2
--.*: 04a0f002 sqincw x2, w2, pow2
--.*: 04a0f002 sqincw x2, w2, pow2
--.*: 04a0f002 sqincw x2, w2, pow2
--.*: 04a0f020 sqincw x0, w0, vl1
--.*: 04a0f020 sqincw x0, w0, vl1
--.*: 04a0f020 sqincw x0, w0, vl1
--.*: 04a0f040 sqincw x0, w0, vl2
--.*: 04a0f040 sqincw x0, w0, vl2
--.*: 04a0f040 sqincw x0, w0, vl2
--.*: 04a0f060 sqincw x0, w0, vl3
--.*: 04a0f060 sqincw x0, w0, vl3
--.*: 04a0f060 sqincw x0, w0, vl3
--.*: 04a0f080 sqincw x0, w0, vl4
--.*: 04a0f080 sqincw x0, w0, vl4
--.*: 04a0f080 sqincw x0, w0, vl4
--.*: 04a0f0a0 sqincw x0, w0, vl5
--.*: 04a0f0a0 sqincw x0, w0, vl5
--.*: 04a0f0a0 sqincw x0, w0, vl5
--.*: 04a0f0c0 sqincw x0, w0, vl6
--.*: 04a0f0c0 sqincw x0, w0, vl6
--.*: 04a0f0c0 sqincw x0, w0, vl6
--.*: 04a0f0e0 sqincw x0, w0, vl7
--.*: 04a0f0e0 sqincw x0, w0, vl7
--.*: 04a0f0e0 sqincw x0, w0, vl7
--.*: 04a0f100 sqincw x0, w0, vl8
--.*: 04a0f100 sqincw x0, w0, vl8
--.*: 04a0f100 sqincw x0, w0, vl8
--.*: 04a0f120 sqincw x0, w0, vl16
--.*: 04a0f120 sqincw x0, w0, vl16
--.*: 04a0f120 sqincw x0, w0, vl16
--.*: 04a0f140 sqincw x0, w0, vl32
--.*: 04a0f140 sqincw x0, w0, vl32
--.*: 04a0f140 sqincw x0, w0, vl32
--.*: 04a0f160 sqincw x0, w0, vl64
--.*: 04a0f160 sqincw x0, w0, vl64
--.*: 04a0f160 sqincw x0, w0, vl64
--.*: 04a0f180 sqincw x0, w0, vl128
--.*: 04a0f180 sqincw x0, w0, vl128
--.*: 04a0f180 sqincw x0, w0, vl128
--.*: 04a0f1a0 sqincw x0, w0, vl256
--.*: 04a0f1a0 sqincw x0, w0, vl256
--.*: 04a0f1a0 sqincw x0, w0, vl256
--.*: 04a0f1c0 sqincw x0, w0, #14
--.*: 04a0f1c0 sqincw x0, w0, #14
--.*: 04a0f1c0 sqincw x0, w0, #14
--.*: 04a0f1e0 sqincw x0, w0, #15
--.*: 04a0f1e0 sqincw x0, w0, #15
--.*: 04a0f1e0 sqincw x0, w0, #15
--.*: 04a0f200 sqincw x0, w0, #16
--.*: 04a0f200 sqincw x0, w0, #16
--.*: 04a0f200 sqincw x0, w0, #16
--.*: 04a0f220 sqincw x0, w0, #17
--.*: 04a0f220 sqincw x0, w0, #17
--.*: 04a0f220 sqincw x0, w0, #17
--.*: 04a0f240 sqincw x0, w0, #18
--.*: 04a0f240 sqincw x0, w0, #18
--.*: 04a0f240 sqincw x0, w0, #18
--.*: 04a0f260 sqincw x0, w0, #19
--.*: 04a0f260 sqincw x0, w0, #19
--.*: 04a0f260 sqincw x0, w0, #19
--.*: 04a0f280 sqincw x0, w0, #20
--.*: 04a0f280 sqincw x0, w0, #20
--.*: 04a0f280 sqincw x0, w0, #20
--.*: 04a0f2a0 sqincw x0, w0, #21
--.*: 04a0f2a0 sqincw x0, w0, #21
--.*: 04a0f2a0 sqincw x0, w0, #21
--.*: 04a0f2c0 sqincw x0, w0, #22
--.*: 04a0f2c0 sqincw x0, w0, #22
--.*: 04a0f2c0 sqincw x0, w0, #22
--.*: 04a0f2e0 sqincw x0, w0, #23
--.*: 04a0f2e0 sqincw x0, w0, #23
--.*: 04a0f2e0 sqincw x0, w0, #23
--.*: 04a0f300 sqincw x0, w0, #24
--.*: 04a0f300 sqincw x0, w0, #24
--.*: 04a0f300 sqincw x0, w0, #24
--.*: 04a0f320 sqincw x0, w0, #25
--.*: 04a0f320 sqincw x0, w0, #25
--.*: 04a0f320 sqincw x0, w0, #25
--.*: 04a0f340 sqincw x0, w0, #26
--.*: 04a0f340 sqincw x0, w0, #26
--.*: 04a0f340 sqincw x0, w0, #26
--.*: 04a0f360 sqincw x0, w0, #27
--.*: 04a0f360 sqincw x0, w0, #27
--.*: 04a0f360 sqincw x0, w0, #27
--.*: 04a0f380 sqincw x0, w0, #28
--.*: 04a0f380 sqincw x0, w0, #28
--.*: 04a0f380 sqincw x0, w0, #28
--.*: 04a0f3a0 sqincw x0, w0, mul4
--.*: 04a0f3a0 sqincw x0, w0, mul4
--.*: 04a0f3a0 sqincw x0, w0, mul4
--.*: 04a0f3c0 sqincw x0, w0, mul3
--.*: 04a0f3c0 sqincw x0, w0, mul3
--.*: 04a0f3c0 sqincw x0, w0, mul3
--.*: 04a0f3e0 sqincw x0, w0
--.*: 04a0f3e0 sqincw x0, w0
--.*: 04a0f3e0 sqincw x0, w0
--.*: 04a0f3e0 sqincw x0, w0
--.*: 04a7f000 sqincw x0, w0, pow2, mul #8
--.*: 04a7f000 sqincw x0, w0, pow2, mul #8
--.*: 04a8f000 sqincw x0, w0, pow2, mul #9
--.*: 04a8f000 sqincw x0, w0, pow2, mul #9
--.*: 04a9f000 sqincw x0, w0, pow2, mul #10
--.*: 04a9f000 sqincw x0, w0, pow2, mul #10
--.*: 04aff000 sqincw x0, w0, pow2, mul #16
--.*: 04aff000 sqincw x0, w0, pow2, mul #16
--.*: 04201800 sqsub z0\.b, z0\.b, z0\.b
--.*: 04201800 sqsub z0\.b, z0\.b, z0\.b
--.*: 04201801 sqsub z1\.b, z0\.b, z0\.b
--.*: 04201801 sqsub z1\.b, z0\.b, z0\.b
--.*: 0420181f sqsub z31\.b, z0\.b, z0\.b
--.*: 0420181f sqsub z31\.b, z0\.b, z0\.b
--.*: 04201840 sqsub z0\.b, z2\.b, z0\.b
--.*: 04201840 sqsub z0\.b, z2\.b, z0\.b
--.*: 04201be0 sqsub z0\.b, z31\.b, z0\.b
--.*: 04201be0 sqsub z0\.b, z31\.b, z0\.b
--.*: 04231800 sqsub z0\.b, z0\.b, z3\.b
--.*: 04231800 sqsub z0\.b, z0\.b, z3\.b
--.*: 043f1800 sqsub z0\.b, z0\.b, z31\.b
--.*: 043f1800 sqsub z0\.b, z0\.b, z31\.b
--.*: 04601800 sqsub z0\.h, z0\.h, z0\.h
--.*: 04601800 sqsub z0\.h, z0\.h, z0\.h
--.*: 04601801 sqsub z1\.h, z0\.h, z0\.h
--.*: 04601801 sqsub z1\.h, z0\.h, z0\.h
--.*: 0460181f sqsub z31\.h, z0\.h, z0\.h
--.*: 0460181f sqsub z31\.h, z0\.h, z0\.h
--.*: 04601840 sqsub z0\.h, z2\.h, z0\.h
--.*: 04601840 sqsub z0\.h, z2\.h, z0\.h
--.*: 04601be0 sqsub z0\.h, z31\.h, z0\.h
--.*: 04601be0 sqsub z0\.h, z31\.h, z0\.h
--.*: 04631800 sqsub z0\.h, z0\.h, z3\.h
--.*: 04631800 sqsub z0\.h, z0\.h, z3\.h
--.*: 047f1800 sqsub z0\.h, z0\.h, z31\.h
--.*: 047f1800 sqsub z0\.h, z0\.h, z31\.h
--.*: 04a01800 sqsub z0\.s, z0\.s, z0\.s
--.*: 04a01800 sqsub z0\.s, z0\.s, z0\.s
--.*: 04a01801 sqsub z1\.s, z0\.s, z0\.s
--.*: 04a01801 sqsub z1\.s, z0\.s, z0\.s
--.*: 04a0181f sqsub z31\.s, z0\.s, z0\.s
--.*: 04a0181f sqsub z31\.s, z0\.s, z0\.s
--.*: 04a01840 sqsub z0\.s, z2\.s, z0\.s
--.*: 04a01840 sqsub z0\.s, z2\.s, z0\.s
--.*: 04a01be0 sqsub z0\.s, z31\.s, z0\.s
--.*: 04a01be0 sqsub z0\.s, z31\.s, z0\.s
--.*: 04a31800 sqsub z0\.s, z0\.s, z3\.s
--.*: 04a31800 sqsub z0\.s, z0\.s, z3\.s
--.*: 04bf1800 sqsub z0\.s, z0\.s, z31\.s
--.*: 04bf1800 sqsub z0\.s, z0\.s, z31\.s
--.*: 04e01800 sqsub z0\.d, z0\.d, z0\.d
--.*: 04e01800 sqsub z0\.d, z0\.d, z0\.d
--.*: 04e01801 sqsub z1\.d, z0\.d, z0\.d
--.*: 04e01801 sqsub z1\.d, z0\.d, z0\.d
--.*: 04e0181f sqsub z31\.d, z0\.d, z0\.d
--.*: 04e0181f sqsub z31\.d, z0\.d, z0\.d
--.*: 04e01840 sqsub z0\.d, z2\.d, z0\.d
--.*: 04e01840 sqsub z0\.d, z2\.d, z0\.d
--.*: 04e01be0 sqsub z0\.d, z31\.d, z0\.d
--.*: 04e01be0 sqsub z0\.d, z31\.d, z0\.d
--.*: 04e31800 sqsub z0\.d, z0\.d, z3\.d
--.*: 04e31800 sqsub z0\.d, z0\.d, z3\.d
--.*: 04ff1800 sqsub z0\.d, z0\.d, z31\.d
--.*: 04ff1800 sqsub z0\.d, z0\.d, z31\.d
--.*: 2526c000 sqsub z0\.b, z0\.b, #0
--.*: 2526c000 sqsub z0\.b, z0\.b, #0
--.*: 2526c000 sqsub z0\.b, z0\.b, #0
--.*: 2526c001 sqsub z1\.b, z1\.b, #0
--.*: 2526c001 sqsub z1\.b, z1\.b, #0
--.*: 2526c001 sqsub z1\.b, z1\.b, #0
--.*: 2526c01f sqsub z31\.b, z31\.b, #0
--.*: 2526c01f sqsub z31\.b, z31\.b, #0
--.*: 2526c01f sqsub z31\.b, z31\.b, #0
--.*: 2526c002 sqsub z2\.b, z2\.b, #0
--.*: 2526c002 sqsub z2\.b, z2\.b, #0
--.*: 2526c002 sqsub z2\.b, z2\.b, #0
--.*: 2526cfe0 sqsub z0\.b, z0\.b, #127
--.*: 2526cfe0 sqsub z0\.b, z0\.b, #127
--.*: 2526cfe0 sqsub z0\.b, z0\.b, #127
--.*: 2526d000 sqsub z0\.b, z0\.b, #128
--.*: 2526d000 sqsub z0\.b, z0\.b, #128
--.*: 2526d000 sqsub z0\.b, z0\.b, #128
--.*: 2526d020 sqsub z0\.b, z0\.b, #129
--.*: 2526d020 sqsub z0\.b, z0\.b, #129
--.*: 2526d020 sqsub z0\.b, z0\.b, #129
--.*: 2526dfe0 sqsub z0\.b, z0\.b, #255
--.*: 2526dfe0 sqsub z0\.b, z0\.b, #255
--.*: 2526dfe0 sqsub z0\.b, z0\.b, #255
--.*: 2566c000 sqsub z0\.h, z0\.h, #0
--.*: 2566c000 sqsub z0\.h, z0\.h, #0
--.*: 2566c000 sqsub z0\.h, z0\.h, #0
--.*: 2566c001 sqsub z1\.h, z1\.h, #0
--.*: 2566c001 sqsub z1\.h, z1\.h, #0
--.*: 2566c001 sqsub z1\.h, z1\.h, #0
--.*: 2566c01f sqsub z31\.h, z31\.h, #0
--.*: 2566c01f sqsub z31\.h, z31\.h, #0
--.*: 2566c01f sqsub z31\.h, z31\.h, #0
--.*: 2566c002 sqsub z2\.h, z2\.h, #0
--.*: 2566c002 sqsub z2\.h, z2\.h, #0
--.*: 2566c002 sqsub z2\.h, z2\.h, #0
--.*: 2566cfe0 sqsub z0\.h, z0\.h, #127
--.*: 2566cfe0 sqsub z0\.h, z0\.h, #127
--.*: 2566cfe0 sqsub z0\.h, z0\.h, #127
--.*: 2566d000 sqsub z0\.h, z0\.h, #128
--.*: 2566d000 sqsub z0\.h, z0\.h, #128
--.*: 2566d000 sqsub z0\.h, z0\.h, #128
--.*: 2566d020 sqsub z0\.h, z0\.h, #129
--.*: 2566d020 sqsub z0\.h, z0\.h, #129
--.*: 2566d020 sqsub z0\.h, z0\.h, #129
--.*: 2566dfe0 sqsub z0\.h, z0\.h, #255
--.*: 2566dfe0 sqsub z0\.h, z0\.h, #255
--.*: 2566dfe0 sqsub z0\.h, z0\.h, #255
--.*: 2566e000 sqsub z0\.h, z0\.h, #0, lsl #8
--.*: 2566e000 sqsub z0\.h, z0\.h, #0, lsl #8
--.*: 2566efe0 sqsub z0\.h, z0\.h, #32512
--.*: 2566efe0 sqsub z0\.h, z0\.h, #32512
--.*: 2566efe0 sqsub z0\.h, z0\.h, #32512
--.*: 2566efe0 sqsub z0\.h, z0\.h, #32512
--.*: 2566f000 sqsub z0\.h, z0\.h, #32768
--.*: 2566f000 sqsub z0\.h, z0\.h, #32768
--.*: 2566f000 sqsub z0\.h, z0\.h, #32768
--.*: 2566f000 sqsub z0\.h, z0\.h, #32768
--.*: 2566f020 sqsub z0\.h, z0\.h, #33024
--.*: 2566f020 sqsub z0\.h, z0\.h, #33024
--.*: 2566f020 sqsub z0\.h, z0\.h, #33024
--.*: 2566f020 sqsub z0\.h, z0\.h, #33024
--.*: 2566ffe0 sqsub z0\.h, z0\.h, #65280
--.*: 2566ffe0 sqsub z0\.h, z0\.h, #65280
--.*: 2566ffe0 sqsub z0\.h, z0\.h, #65280
--.*: 2566ffe0 sqsub z0\.h, z0\.h, #65280
--.*: 25a6c000 sqsub z0\.s, z0\.s, #0
--.*: 25a6c000 sqsub z0\.s, z0\.s, #0
--.*: 25a6c000 sqsub z0\.s, z0\.s, #0
--.*: 25a6c001 sqsub z1\.s, z1\.s, #0
--.*: 25a6c001 sqsub z1\.s, z1\.s, #0
--.*: 25a6c001 sqsub z1\.s, z1\.s, #0
--.*: 25a6c01f sqsub z31\.s, z31\.s, #0
--.*: 25a6c01f sqsub z31\.s, z31\.s, #0
--.*: 25a6c01f sqsub z31\.s, z31\.s, #0
--.*: 25a6c002 sqsub z2\.s, z2\.s, #0
--.*: 25a6c002 sqsub z2\.s, z2\.s, #0
--.*: 25a6c002 sqsub z2\.s, z2\.s, #0
--.*: 25a6cfe0 sqsub z0\.s, z0\.s, #127
--.*: 25a6cfe0 sqsub z0\.s, z0\.s, #127
--.*: 25a6cfe0 sqsub z0\.s, z0\.s, #127
--.*: 25a6d000 sqsub z0\.s, z0\.s, #128
--.*: 25a6d000 sqsub z0\.s, z0\.s, #128
--.*: 25a6d000 sqsub z0\.s, z0\.s, #128
--.*: 25a6d020 sqsub z0\.s, z0\.s, #129
--.*: 25a6d020 sqsub z0\.s, z0\.s, #129
--.*: 25a6d020 sqsub z0\.s, z0\.s, #129
--.*: 25a6dfe0 sqsub z0\.s, z0\.s, #255
--.*: 25a6dfe0 sqsub z0\.s, z0\.s, #255
--.*: 25a6dfe0 sqsub z0\.s, z0\.s, #255
--.*: 25a6e000 sqsub z0\.s, z0\.s, #0, lsl #8
--.*: 25a6e000 sqsub z0\.s, z0\.s, #0, lsl #8
--.*: 25a6efe0 sqsub z0\.s, z0\.s, #32512
--.*: 25a6efe0 sqsub z0\.s, z0\.s, #32512
--.*: 25a6efe0 sqsub z0\.s, z0\.s, #32512
--.*: 25a6efe0 sqsub z0\.s, z0\.s, #32512
--.*: 25a6f000 sqsub z0\.s, z0\.s, #32768
--.*: 25a6f000 sqsub z0\.s, z0\.s, #32768
--.*: 25a6f000 sqsub z0\.s, z0\.s, #32768
--.*: 25a6f000 sqsub z0\.s, z0\.s, #32768
--.*: 25a6f020 sqsub z0\.s, z0\.s, #33024
--.*: 25a6f020 sqsub z0\.s, z0\.s, #33024
--.*: 25a6f020 sqsub z0\.s, z0\.s, #33024
--.*: 25a6f020 sqsub z0\.s, z0\.s, #33024
--.*: 25a6ffe0 sqsub z0\.s, z0\.s, #65280
--.*: 25a6ffe0 sqsub z0\.s, z0\.s, #65280
--.*: 25a6ffe0 sqsub z0\.s, z0\.s, #65280
--.*: 25a6ffe0 sqsub z0\.s, z0\.s, #65280
--.*: 25e6c000 sqsub z0\.d, z0\.d, #0
--.*: 25e6c000 sqsub z0\.d, z0\.d, #0
--.*: 25e6c000 sqsub z0\.d, z0\.d, #0
--.*: 25e6c001 sqsub z1\.d, z1\.d, #0
--.*: 25e6c001 sqsub z1\.d, z1\.d, #0
--.*: 25e6c001 sqsub z1\.d, z1\.d, #0
--.*: 25e6c01f sqsub z31\.d, z31\.d, #0
--.*: 25e6c01f sqsub z31\.d, z31\.d, #0
--.*: 25e6c01f sqsub z31\.d, z31\.d, #0
--.*: 25e6c002 sqsub z2\.d, z2\.d, #0
--.*: 25e6c002 sqsub z2\.d, z2\.d, #0
--.*: 25e6c002 sqsub z2\.d, z2\.d, #0
--.*: 25e6cfe0 sqsub z0\.d, z0\.d, #127
--.*: 25e6cfe0 sqsub z0\.d, z0\.d, #127
--.*: 25e6cfe0 sqsub z0\.d, z0\.d, #127
--.*: 25e6d000 sqsub z0\.d, z0\.d, #128
--.*: 25e6d000 sqsub z0\.d, z0\.d, #128
--.*: 25e6d000 sqsub z0\.d, z0\.d, #128
--.*: 25e6d020 sqsub z0\.d, z0\.d, #129
--.*: 25e6d020 sqsub z0\.d, z0\.d, #129
--.*: 25e6d020 sqsub z0\.d, z0\.d, #129
--.*: 25e6dfe0 sqsub z0\.d, z0\.d, #255
--.*: 25e6dfe0 sqsub z0\.d, z0\.d, #255
--.*: 25e6dfe0 sqsub z0\.d, z0\.d, #255
--.*: 25e6e000 sqsub z0\.d, z0\.d, #0, lsl #8
--.*: 25e6e000 sqsub z0\.d, z0\.d, #0, lsl #8
--.*: 25e6efe0 sqsub z0\.d, z0\.d, #32512
--.*: 25e6efe0 sqsub z0\.d, z0\.d, #32512
--.*: 25e6efe0 sqsub z0\.d, z0\.d, #32512
--.*: 25e6efe0 sqsub z0\.d, z0\.d, #32512
--.*: 25e6f000 sqsub z0\.d, z0\.d, #32768
--.*: 25e6f000 sqsub z0\.d, z0\.d, #32768
--.*: 25e6f000 sqsub z0\.d, z0\.d, #32768
--.*: 25e6f000 sqsub z0\.d, z0\.d, #32768
--.*: 25e6f020 sqsub z0\.d, z0\.d, #33024
--.*: 25e6f020 sqsub z0\.d, z0\.d, #33024
--.*: 25e6f020 sqsub z0\.d, z0\.d, #33024
--.*: 25e6f020 sqsub z0\.d, z0\.d, #33024
--.*: 25e6ffe0 sqsub z0\.d, z0\.d, #65280
--.*: 25e6ffe0 sqsub z0\.d, z0\.d, #65280
--.*: 25e6ffe0 sqsub z0\.d, z0\.d, #65280
--.*: 25e6ffe0 sqsub z0\.d, z0\.d, #65280
--.*: e4004000 st1b \{z0\.b\}, p0, \[x0, x0\]
--.*: e4004000 st1b \{z0\.b\}, p0, \[x0, x0\]
--.*: e4004000 st1b \{z0\.b\}, p0, \[x0, x0\]
--.*: e4004000 st1b \{z0\.b\}, p0, \[x0, x0\]
--.*: e4004001 st1b \{z1\.b\}, p0, \[x0, x0\]
--.*: e4004001 st1b \{z1\.b\}, p0, \[x0, x0\]
--.*: e4004001 st1b \{z1\.b\}, p0, \[x0, x0\]
--.*: e4004001 st1b \{z1\.b\}, p0, \[x0, x0\]
--.*: e400401f st1b \{z31\.b\}, p0, \[x0, x0\]
--.*: e400401f st1b \{z31\.b\}, p0, \[x0, x0\]
--.*: e400401f st1b \{z31\.b\}, p0, \[x0, x0\]
--.*: e400401f st1b \{z31\.b\}, p0, \[x0, x0\]
--.*: e4004800 st1b \{z0\.b\}, p2, \[x0, x0\]
--.*: e4004800 st1b \{z0\.b\}, p2, \[x0, x0\]
--.*: e4004800 st1b \{z0\.b\}, p2, \[x0, x0\]
--.*: e4005c00 st1b \{z0\.b\}, p7, \[x0, x0\]
--.*: e4005c00 st1b \{z0\.b\}, p7, \[x0, x0\]
--.*: e4005c00 st1b \{z0\.b\}, p7, \[x0, x0\]
--.*: e4004060 st1b \{z0\.b\}, p0, \[x3, x0\]
--.*: e4004060 st1b \{z0\.b\}, p0, \[x3, x0\]
--.*: e4004060 st1b \{z0\.b\}, p0, \[x3, x0\]
--.*: e40043e0 st1b \{z0\.b\}, p0, \[sp, x0\]
--.*: e40043e0 st1b \{z0\.b\}, p0, \[sp, x0\]
--.*: e40043e0 st1b \{z0\.b\}, p0, \[sp, x0\]
--.*: e4044000 st1b \{z0\.b\}, p0, \[x0, x4\]
--.*: e4044000 st1b \{z0\.b\}, p0, \[x0, x4\]
--.*: e4044000 st1b \{z0\.b\}, p0, \[x0, x4\]
--.*: e41e4000 st1b \{z0\.b\}, p0, \[x0, x30\]
--.*: e41e4000 st1b \{z0\.b\}, p0, \[x0, x30\]
--.*: e41e4000 st1b \{z0\.b\}, p0, \[x0, x30\]
--.*: e4008000 st1b \{z0\.d\}, p0, \[x0, z0\.d, uxtw\]
--.*: e4008000 st1b \{z0\.d\}, p0, \[x0, z0\.d, uxtw\]
--.*: e4008000 st1b \{z0\.d\}, p0, \[x0, z0\.d, uxtw\]
--.*: e4008000 st1b \{z0\.d\}, p0, \[x0, z0\.d, uxtw\]
--.*: e4008001 st1b \{z1\.d\}, p0, \[x0, z0\.d, uxtw\]
--.*: e4008001 st1b \{z1\.d\}, p0, \[x0, z0\.d, uxtw\]
--.*: e4008001 st1b \{z1\.d\}, p0, \[x0, z0\.d, uxtw\]
--.*: e4008001 st1b \{z1\.d\}, p0, \[x0, z0\.d, uxtw\]
--.*: e400801f st1b \{z31\.d\}, p0, \[x0, z0\.d, uxtw\]
--.*: e400801f st1b \{z31\.d\}, p0, \[x0, z0\.d, uxtw\]
--.*: e400801f st1b \{z31\.d\}, p0, \[x0, z0\.d, uxtw\]
--.*: e400801f st1b \{z31\.d\}, p0, \[x0, z0\.d, uxtw\]
--.*: e4008800 st1b \{z0\.d\}, p2, \[x0, z0\.d, uxtw\]
--.*: e4008800 st1b \{z0\.d\}, p2, \[x0, z0\.d, uxtw\]
--.*: e4008800 st1b \{z0\.d\}, p2, \[x0, z0\.d, uxtw\]
--.*: e4009c00 st1b \{z0\.d\}, p7, \[x0, z0\.d, uxtw\]
--.*: e4009c00 st1b \{z0\.d\}, p7, \[x0, z0\.d, uxtw\]
--.*: e4009c00 st1b \{z0\.d\}, p7, \[x0, z0\.d, uxtw\]
--.*: e4008060 st1b \{z0\.d\}, p0, \[x3, z0\.d, uxtw\]
--.*: e4008060 st1b \{z0\.d\}, p0, \[x3, z0\.d, uxtw\]
--.*: e4008060 st1b \{z0\.d\}, p0, \[x3, z0\.d, uxtw\]
--.*: e40083e0 st1b \{z0\.d\}, p0, \[sp, z0\.d, uxtw\]
--.*: e40083e0 st1b \{z0\.d\}, p0, \[sp, z0\.d, uxtw\]
--.*: e40083e0 st1b \{z0\.d\}, p0, \[sp, z0\.d, uxtw\]
--.*: e4048000 st1b \{z0\.d\}, p0, \[x0, z4\.d, uxtw\]
--.*: e4048000 st1b \{z0\.d\}, p0, \[x0, z4\.d, uxtw\]
--.*: e4048000 st1b \{z0\.d\}, p0, \[x0, z4\.d, uxtw\]
--.*: e41f8000 st1b \{z0\.d\}, p0, \[x0, z31\.d, uxtw\]
--.*: e41f8000 st1b \{z0\.d\}, p0, \[x0, z31\.d, uxtw\]
--.*: e41f8000 st1b \{z0\.d\}, p0, \[x0, z31\.d, uxtw\]
--.*: e400c000 st1b \{z0\.d\}, p0, \[x0, z0\.d, sxtw\]
--.*: e400c000 st1b \{z0\.d\}, p0, \[x0, z0\.d, sxtw\]
--.*: e400c000 st1b \{z0\.d\}, p0, \[x0, z0\.d, sxtw\]
--.*: e400c000 st1b \{z0\.d\}, p0, \[x0, z0\.d, sxtw\]
--.*: e400c001 st1b \{z1\.d\}, p0, \[x0, z0\.d, sxtw\]
--.*: e400c001 st1b \{z1\.d\}, p0, \[x0, z0\.d, sxtw\]
--.*: e400c001 st1b \{z1\.d\}, p0, \[x0, z0\.d, sxtw\]
--.*: e400c001 st1b \{z1\.d\}, p0, \[x0, z0\.d, sxtw\]
--.*: e400c01f st1b \{z31\.d\}, p0, \[x0, z0\.d, sxtw\]
--.*: e400c01f st1b \{z31\.d\}, p0, \[x0, z0\.d, sxtw\]
--.*: e400c01f st1b \{z31\.d\}, p0, \[x0, z0\.d, sxtw\]
--.*: e400c01f st1b \{z31\.d\}, p0, \[x0, z0\.d, sxtw\]
--.*: e400c800 st1b \{z0\.d\}, p2, \[x0, z0\.d, sxtw\]
--.*: e400c800 st1b \{z0\.d\}, p2, \[x0, z0\.d, sxtw\]
--.*: e400c800 st1b \{z0\.d\}, p2, \[x0, z0\.d, sxtw\]
--.*: e400dc00 st1b \{z0\.d\}, p7, \[x0, z0\.d, sxtw\]
--.*: e400dc00 st1b \{z0\.d\}, p7, \[x0, z0\.d, sxtw\]
--.*: e400dc00 st1b \{z0\.d\}, p7, \[x0, z0\.d, sxtw\]
--.*: e400c060 st1b \{z0\.d\}, p0, \[x3, z0\.d, sxtw\]
--.*: e400c060 st1b \{z0\.d\}, p0, \[x3, z0\.d, sxtw\]
--.*: e400c060 st1b \{z0\.d\}, p0, \[x3, z0\.d, sxtw\]
--.*: e400c3e0 st1b \{z0\.d\}, p0, \[sp, z0\.d, sxtw\]
--.*: e400c3e0 st1b \{z0\.d\}, p0, \[sp, z0\.d, sxtw\]
--.*: e400c3e0 st1b \{z0\.d\}, p0, \[sp, z0\.d, sxtw\]
--.*: e404c000 st1b \{z0\.d\}, p0, \[x0, z4\.d, sxtw\]
--.*: e404c000 st1b \{z0\.d\}, p0, \[x0, z4\.d, sxtw\]
--.*: e404c000 st1b \{z0\.d\}, p0, \[x0, z4\.d, sxtw\]
--.*: e41fc000 st1b \{z0\.d\}, p0, \[x0, z31\.d, sxtw\]
--.*: e41fc000 st1b \{z0\.d\}, p0, \[x0, z31\.d, sxtw\]
--.*: e41fc000 st1b \{z0\.d\}, p0, \[x0, z31\.d, sxtw\]
--.*: e400a000 st1b \{z0\.d\}, p0, \[x0, z0\.d\]
--.*: e400a000 st1b \{z0\.d\}, p0, \[x0, z0\.d\]
--.*: e400a000 st1b \{z0\.d\}, p0, \[x0, z0\.d\]
--.*: e400a000 st1b \{z0\.d\}, p0, \[x0, z0\.d\]
--.*: e400a001 st1b \{z1\.d\}, p0, \[x0, z0\.d\]
--.*: e400a001 st1b \{z1\.d\}, p0, \[x0, z0\.d\]
--.*: e400a001 st1b \{z1\.d\}, p0, \[x0, z0\.d\]
--.*: e400a001 st1b \{z1\.d\}, p0, \[x0, z0\.d\]
--.*: e400a01f st1b \{z31\.d\}, p0, \[x0, z0\.d\]
--.*: e400a01f st1b \{z31\.d\}, p0, \[x0, z0\.d\]
--.*: e400a01f st1b \{z31\.d\}, p0, \[x0, z0\.d\]
--.*: e400a01f st1b \{z31\.d\}, p0, \[x0, z0\.d\]
--.*: e400a800 st1b \{z0\.d\}, p2, \[x0, z0\.d\]
--.*: e400a800 st1b \{z0\.d\}, p2, \[x0, z0\.d\]
--.*: e400a800 st1b \{z0\.d\}, p2, \[x0, z0\.d\]
--.*: e400bc00 st1b \{z0\.d\}, p7, \[x0, z0\.d\]
--.*: e400bc00 st1b \{z0\.d\}, p7, \[x0, z0\.d\]
--.*: e400bc00 st1b \{z0\.d\}, p7, \[x0, z0\.d\]
--.*: e400a060 st1b \{z0\.d\}, p0, \[x3, z0\.d\]
--.*: e400a060 st1b \{z0\.d\}, p0, \[x3, z0\.d\]
--.*: e400a060 st1b \{z0\.d\}, p0, \[x3, z0\.d\]
--.*: e400a3e0 st1b \{z0\.d\}, p0, \[sp, z0\.d\]
--.*: e400a3e0 st1b \{z0\.d\}, p0, \[sp, z0\.d\]
--.*: e400a3e0 st1b \{z0\.d\}, p0, \[sp, z0\.d\]
--.*: e404a000 st1b \{z0\.d\}, p0, \[x0, z4\.d\]
--.*: e404a000 st1b \{z0\.d\}, p0, \[x0, z4\.d\]
--.*: e404a000 st1b \{z0\.d\}, p0, \[x0, z4\.d\]
--.*: e41fa000 st1b \{z0\.d\}, p0, \[x0, z31\.d\]
--.*: e41fa000 st1b \{z0\.d\}, p0, \[x0, z31\.d\]
--.*: e41fa000 st1b \{z0\.d\}, p0, \[x0, z31\.d\]
--.*: e4204000 st1b \{z0\.h\}, p0, \[x0, x0\]
--.*: e4204000 st1b \{z0\.h\}, p0, \[x0, x0\]
--.*: e4204000 st1b \{z0\.h\}, p0, \[x0, x0\]
--.*: e4204000 st1b \{z0\.h\}, p0, \[x0, x0\]
--.*: e4204001 st1b \{z1\.h\}, p0, \[x0, x0\]
--.*: e4204001 st1b \{z1\.h\}, p0, \[x0, x0\]
--.*: e4204001 st1b \{z1\.h\}, p0, \[x0, x0\]
--.*: e4204001 st1b \{z1\.h\}, p0, \[x0, x0\]
--.*: e420401f st1b \{z31\.h\}, p0, \[x0, x0\]
--.*: e420401f st1b \{z31\.h\}, p0, \[x0, x0\]
--.*: e420401f st1b \{z31\.h\}, p0, \[x0, x0\]
--.*: e420401f st1b \{z31\.h\}, p0, \[x0, x0\]
--.*: e4204800 st1b \{z0\.h\}, p2, \[x0, x0\]
--.*: e4204800 st1b \{z0\.h\}, p2, \[x0, x0\]
--.*: e4204800 st1b \{z0\.h\}, p2, \[x0, x0\]
--.*: e4205c00 st1b \{z0\.h\}, p7, \[x0, x0\]
--.*: e4205c00 st1b \{z0\.h\}, p7, \[x0, x0\]
--.*: e4205c00 st1b \{z0\.h\}, p7, \[x0, x0\]
--.*: e4204060 st1b \{z0\.h\}, p0, \[x3, x0\]
--.*: e4204060 st1b \{z0\.h\}, p0, \[x3, x0\]
--.*: e4204060 st1b \{z0\.h\}, p0, \[x3, x0\]
--.*: e42043e0 st1b \{z0\.h\}, p0, \[sp, x0\]
--.*: e42043e0 st1b \{z0\.h\}, p0, \[sp, x0\]
--.*: e42043e0 st1b \{z0\.h\}, p0, \[sp, x0\]
--.*: e4244000 st1b \{z0\.h\}, p0, \[x0, x4\]
--.*: e4244000 st1b \{z0\.h\}, p0, \[x0, x4\]
--.*: e4244000 st1b \{z0\.h\}, p0, \[x0, x4\]
--.*: e43e4000 st1b \{z0\.h\}, p0, \[x0, x30\]
--.*: e43e4000 st1b \{z0\.h\}, p0, \[x0, x30\]
--.*: e43e4000 st1b \{z0\.h\}, p0, \[x0, x30\]
--.*: e4404000 st1b \{z0\.s\}, p0, \[x0, x0\]
--.*: e4404000 st1b \{z0\.s\}, p0, \[x0, x0\]
--.*: e4404000 st1b \{z0\.s\}, p0, \[x0, x0\]
--.*: e4404000 st1b \{z0\.s\}, p0, \[x0, x0\]
--.*: e4404001 st1b \{z1\.s\}, p0, \[x0, x0\]
--.*: e4404001 st1b \{z1\.s\}, p0, \[x0, x0\]
--.*: e4404001 st1b \{z1\.s\}, p0, \[x0, x0\]
--.*: e4404001 st1b \{z1\.s\}, p0, \[x0, x0\]
--.*: e440401f st1b \{z31\.s\}, p0, \[x0, x0\]
--.*: e440401f st1b \{z31\.s\}, p0, \[x0, x0\]
--.*: e440401f st1b \{z31\.s\}, p0, \[x0, x0\]
--.*: e440401f st1b \{z31\.s\}, p0, \[x0, x0\]
--.*: e4404800 st1b \{z0\.s\}, p2, \[x0, x0\]
--.*: e4404800 st1b \{z0\.s\}, p2, \[x0, x0\]
--.*: e4404800 st1b \{z0\.s\}, p2, \[x0, x0\]
--.*: e4405c00 st1b \{z0\.s\}, p7, \[x0, x0\]
--.*: e4405c00 st1b \{z0\.s\}, p7, \[x0, x0\]
--.*: e4405c00 st1b \{z0\.s\}, p7, \[x0, x0\]
--.*: e4404060 st1b \{z0\.s\}, p0, \[x3, x0\]
--.*: e4404060 st1b \{z0\.s\}, p0, \[x3, x0\]
--.*: e4404060 st1b \{z0\.s\}, p0, \[x3, x0\]
--.*: e44043e0 st1b \{z0\.s\}, p0, \[sp, x0\]
--.*: e44043e0 st1b \{z0\.s\}, p0, \[sp, x0\]
--.*: e44043e0 st1b \{z0\.s\}, p0, \[sp, x0\]
--.*: e4444000 st1b \{z0\.s\}, p0, \[x0, x4\]
--.*: e4444000 st1b \{z0\.s\}, p0, \[x0, x4\]
--.*: e4444000 st1b \{z0\.s\}, p0, \[x0, x4\]
--.*: e45e4000 st1b \{z0\.s\}, p0, \[x0, x30\]
--.*: e45e4000 st1b \{z0\.s\}, p0, \[x0, x30\]
--.*: e45e4000 st1b \{z0\.s\}, p0, \[x0, x30\]
--.*: e4408000 st1b \{z0\.s\}, p0, \[x0, z0\.s, uxtw\]
--.*: e4408000 st1b \{z0\.s\}, p0, \[x0, z0\.s, uxtw\]
--.*: e4408000 st1b \{z0\.s\}, p0, \[x0, z0\.s, uxtw\]
--.*: e4408000 st1b \{z0\.s\}, p0, \[x0, z0\.s, uxtw\]
--.*: e4408001 st1b \{z1\.s\}, p0, \[x0, z0\.s, uxtw\]
--.*: e4408001 st1b \{z1\.s\}, p0, \[x0, z0\.s, uxtw\]
--.*: e4408001 st1b \{z1\.s\}, p0, \[x0, z0\.s, uxtw\]
--.*: e4408001 st1b \{z1\.s\}, p0, \[x0, z0\.s, uxtw\]
--.*: e440801f st1b \{z31\.s\}, p0, \[x0, z0\.s, uxtw\]
--.*: e440801f st1b \{z31\.s\}, p0, \[x0, z0\.s, uxtw\]
--.*: e440801f st1b \{z31\.s\}, p0, \[x0, z0\.s, uxtw\]
--.*: e440801f st1b \{z31\.s\}, p0, \[x0, z0\.s, uxtw\]
--.*: e4408800 st1b \{z0\.s\}, p2, \[x0, z0\.s, uxtw\]
--.*: e4408800 st1b \{z0\.s\}, p2, \[x0, z0\.s, uxtw\]
--.*: e4408800 st1b \{z0\.s\}, p2, \[x0, z0\.s, uxtw\]
--.*: e4409c00 st1b \{z0\.s\}, p7, \[x0, z0\.s, uxtw\]
--.*: e4409c00 st1b \{z0\.s\}, p7, \[x0, z0\.s, uxtw\]
--.*: e4409c00 st1b \{z0\.s\}, p7, \[x0, z0\.s, uxtw\]
--.*: e4408060 st1b \{z0\.s\}, p0, \[x3, z0\.s, uxtw\]
--.*: e4408060 st1b \{z0\.s\}, p0, \[x3, z0\.s, uxtw\]
--.*: e4408060 st1b \{z0\.s\}, p0, \[x3, z0\.s, uxtw\]
--.*: e44083e0 st1b \{z0\.s\}, p0, \[sp, z0\.s, uxtw\]
--.*: e44083e0 st1b \{z0\.s\}, p0, \[sp, z0\.s, uxtw\]
--.*: e44083e0 st1b \{z0\.s\}, p0, \[sp, z0\.s, uxtw\]
--.*: e4448000 st1b \{z0\.s\}, p0, \[x0, z4\.s, uxtw\]
--.*: e4448000 st1b \{z0\.s\}, p0, \[x0, z4\.s, uxtw\]
--.*: e4448000 st1b \{z0\.s\}, p0, \[x0, z4\.s, uxtw\]
--.*: e45f8000 st1b \{z0\.s\}, p0, \[x0, z31\.s, uxtw\]
--.*: e45f8000 st1b \{z0\.s\}, p0, \[x0, z31\.s, uxtw\]
--.*: e45f8000 st1b \{z0\.s\}, p0, \[x0, z31\.s, uxtw\]
--.*: e440c000 st1b \{z0\.s\}, p0, \[x0, z0\.s, sxtw\]
--.*: e440c000 st1b \{z0\.s\}, p0, \[x0, z0\.s, sxtw\]
--.*: e440c000 st1b \{z0\.s\}, p0, \[x0, z0\.s, sxtw\]
--.*: e440c000 st1b \{z0\.s\}, p0, \[x0, z0\.s, sxtw\]
--.*: e440c001 st1b \{z1\.s\}, p0, \[x0, z0\.s, sxtw\]
--.*: e440c001 st1b \{z1\.s\}, p0, \[x0, z0\.s, sxtw\]
--.*: e440c001 st1b \{z1\.s\}, p0, \[x0, z0\.s, sxtw\]
--.*: e440c001 st1b \{z1\.s\}, p0, \[x0, z0\.s, sxtw\]
--.*: e440c01f st1b \{z31\.s\}, p0, \[x0, z0\.s, sxtw\]
--.*: e440c01f st1b \{z31\.s\}, p0, \[x0, z0\.s, sxtw\]
--.*: e440c01f st1b \{z31\.s\}, p0, \[x0, z0\.s, sxtw\]
--.*: e440c01f st1b \{z31\.s\}, p0, \[x0, z0\.s, sxtw\]
--.*: e440c800 st1b \{z0\.s\}, p2, \[x0, z0\.s, sxtw\]
--.*: e440c800 st1b \{z0\.s\}, p2, \[x0, z0\.s, sxtw\]
--.*: e440c800 st1b \{z0\.s\}, p2, \[x0, z0\.s, sxtw\]
--.*: e440dc00 st1b \{z0\.s\}, p7, \[x0, z0\.s, sxtw\]
--.*: e440dc00 st1b \{z0\.s\}, p7, \[x0, z0\.s, sxtw\]
--.*: e440dc00 st1b \{z0\.s\}, p7, \[x0, z0\.s, sxtw\]
--.*: e440c060 st1b \{z0\.s\}, p0, \[x3, z0\.s, sxtw\]
--.*: e440c060 st1b \{z0\.s\}, p0, \[x3, z0\.s, sxtw\]
--.*: e440c060 st1b \{z0\.s\}, p0, \[x3, z0\.s, sxtw\]
--.*: e440c3e0 st1b \{z0\.s\}, p0, \[sp, z0\.s, sxtw\]
--.*: e440c3e0 st1b \{z0\.s\}, p0, \[sp, z0\.s, sxtw\]
--.*: e440c3e0 st1b \{z0\.s\}, p0, \[sp, z0\.s, sxtw\]
--.*: e444c000 st1b \{z0\.s\}, p0, \[x0, z4\.s, sxtw\]
--.*: e444c000 st1b \{z0\.s\}, p0, \[x0, z4\.s, sxtw\]
--.*: e444c000 st1b \{z0\.s\}, p0, \[x0, z4\.s, sxtw\]
--.*: e45fc000 st1b \{z0\.s\}, p0, \[x0, z31\.s, sxtw\]
--.*: e45fc000 st1b \{z0\.s\}, p0, \[x0, z31\.s, sxtw\]
--.*: e45fc000 st1b \{z0\.s\}, p0, \[x0, z31\.s, sxtw\]
--.*: e4604000 st1b \{z0\.d\}, p0, \[x0, x0\]
--.*: e4604000 st1b \{z0\.d\}, p0, \[x0, x0\]
--.*: e4604000 st1b \{z0\.d\}, p0, \[x0, x0\]
--.*: e4604000 st1b \{z0\.d\}, p0, \[x0, x0\]
--.*: e4604001 st1b \{z1\.d\}, p0, \[x0, x0\]
--.*: e4604001 st1b \{z1\.d\}, p0, \[x0, x0\]
--.*: e4604001 st1b \{z1\.d\}, p0, \[x0, x0\]
--.*: e4604001 st1b \{z1\.d\}, p0, \[x0, x0\]
--.*: e460401f st1b \{z31\.d\}, p0, \[x0, x0\]
--.*: e460401f st1b \{z31\.d\}, p0, \[x0, x0\]
--.*: e460401f st1b \{z31\.d\}, p0, \[x0, x0\]
--.*: e460401f st1b \{z31\.d\}, p0, \[x0, x0\]
--.*: e4604800 st1b \{z0\.d\}, p2, \[x0, x0\]
--.*: e4604800 st1b \{z0\.d\}, p2, \[x0, x0\]
--.*: e4604800 st1b \{z0\.d\}, p2, \[x0, x0\]
--.*: e4605c00 st1b \{z0\.d\}, p7, \[x0, x0\]
--.*: e4605c00 st1b \{z0\.d\}, p7, \[x0, x0\]
--.*: e4605c00 st1b \{z0\.d\}, p7, \[x0, x0\]
--.*: e4604060 st1b \{z0\.d\}, p0, \[x3, x0\]
--.*: e4604060 st1b \{z0\.d\}, p0, \[x3, x0\]
--.*: e4604060 st1b \{z0\.d\}, p0, \[x3, x0\]
--.*: e46043e0 st1b \{z0\.d\}, p0, \[sp, x0\]
--.*: e46043e0 st1b \{z0\.d\}, p0, \[sp, x0\]
--.*: e46043e0 st1b \{z0\.d\}, p0, \[sp, x0\]
--.*: e4644000 st1b \{z0\.d\}, p0, \[x0, x4\]
--.*: e4644000 st1b \{z0\.d\}, p0, \[x0, x4\]
--.*: e4644000 st1b \{z0\.d\}, p0, \[x0, x4\]
--.*: e47e4000 st1b \{z0\.d\}, p0, \[x0, x30\]
--.*: e47e4000 st1b \{z0\.d\}, p0, \[x0, x30\]
--.*: e47e4000 st1b \{z0\.d\}, p0, \[x0, x30\]
--.*: e400e000 st1b \{z0\.b\}, p0, \[x0\]
--.*: e400e000 st1b \{z0\.b\}, p0, \[x0\]
--.*: e400e000 st1b \{z0\.b\}, p0, \[x0\]
--.*: e400e000 st1b \{z0\.b\}, p0, \[x0\]
--.*: e400e000 st1b \{z0\.b\}, p0, \[x0\]
--.*: e400e001 st1b \{z1\.b\}, p0, \[x0\]
--.*: e400e001 st1b \{z1\.b\}, p0, \[x0\]
--.*: e400e001 st1b \{z1\.b\}, p0, \[x0\]
--.*: e400e001 st1b \{z1\.b\}, p0, \[x0\]
--.*: e400e001 st1b \{z1\.b\}, p0, \[x0\]
--.*: e400e01f st1b \{z31\.b\}, p0, \[x0\]
--.*: e400e01f st1b \{z31\.b\}, p0, \[x0\]
--.*: e400e01f st1b \{z31\.b\}, p0, \[x0\]
--.*: e400e01f st1b \{z31\.b\}, p0, \[x0\]
--.*: e400e01f st1b \{z31\.b\}, p0, \[x0\]
--.*: e400e800 st1b \{z0\.b\}, p2, \[x0\]
--.*: e400e800 st1b \{z0\.b\}, p2, \[x0\]
--.*: e400e800 st1b \{z0\.b\}, p2, \[x0\]
--.*: e400e800 st1b \{z0\.b\}, p2, \[x0\]
--.*: e400fc00 st1b \{z0\.b\}, p7, \[x0\]
--.*: e400fc00 st1b \{z0\.b\}, p7, \[x0\]
--.*: e400fc00 st1b \{z0\.b\}, p7, \[x0\]
--.*: e400fc00 st1b \{z0\.b\}, p7, \[x0\]
--.*: e400e060 st1b \{z0\.b\}, p0, \[x3\]
--.*: e400e060 st1b \{z0\.b\}, p0, \[x3\]
--.*: e400e060 st1b \{z0\.b\}, p0, \[x3\]
--.*: e400e060 st1b \{z0\.b\}, p0, \[x3\]
--.*: e400e3e0 st1b \{z0\.b\}, p0, \[sp\]
--.*: e400e3e0 st1b \{z0\.b\}, p0, \[sp\]
--.*: e400e3e0 st1b \{z0\.b\}, p0, \[sp\]
--.*: e400e3e0 st1b \{z0\.b\}, p0, \[sp\]
--.*: e407e000 st1b \{z0\.b\}, p0, \[x0, #7, mul vl\]
--.*: e407e000 st1b \{z0\.b\}, p0, \[x0, #7, mul vl\]
--.*: e408e000 st1b \{z0\.b\}, p0, \[x0, #-8, mul vl\]
--.*: e408e000 st1b \{z0\.b\}, p0, \[x0, #-8, mul vl\]
--.*: e409e000 st1b \{z0\.b\}, p0, \[x0, #-7, mul vl\]
--.*: e409e000 st1b \{z0\.b\}, p0, \[x0, #-7, mul vl\]
--.*: e40fe000 st1b \{z0\.b\}, p0, \[x0, #-1, mul vl\]
--.*: e40fe000 st1b \{z0\.b\}, p0, \[x0, #-1, mul vl\]
--.*: e420e000 st1b \{z0\.h\}, p0, \[x0\]
--.*: e420e000 st1b \{z0\.h\}, p0, \[x0\]
--.*: e420e000 st1b \{z0\.h\}, p0, \[x0\]
--.*: e420e000 st1b \{z0\.h\}, p0, \[x0\]
--.*: e420e000 st1b \{z0\.h\}, p0, \[x0\]
--.*: e420e001 st1b \{z1\.h\}, p0, \[x0\]
--.*: e420e001 st1b \{z1\.h\}, p0, \[x0\]
--.*: e420e001 st1b \{z1\.h\}, p0, \[x0\]
--.*: e420e001 st1b \{z1\.h\}, p0, \[x0\]
--.*: e420e001 st1b \{z1\.h\}, p0, \[x0\]
--.*: e420e01f st1b \{z31\.h\}, p0, \[x0\]
--.*: e420e01f st1b \{z31\.h\}, p0, \[x0\]
--.*: e420e01f st1b \{z31\.h\}, p0, \[x0\]
--.*: e420e01f st1b \{z31\.h\}, p0, \[x0\]
--.*: e420e01f st1b \{z31\.h\}, p0, \[x0\]
--.*: e420e800 st1b \{z0\.h\}, p2, \[x0\]
--.*: e420e800 st1b \{z0\.h\}, p2, \[x0\]
--.*: e420e800 st1b \{z0\.h\}, p2, \[x0\]
--.*: e420e800 st1b \{z0\.h\}, p2, \[x0\]
--.*: e420fc00 st1b \{z0\.h\}, p7, \[x0\]
--.*: e420fc00 st1b \{z0\.h\}, p7, \[x0\]
--.*: e420fc00 st1b \{z0\.h\}, p7, \[x0\]
--.*: e420fc00 st1b \{z0\.h\}, p7, \[x0\]
--.*: e420e060 st1b \{z0\.h\}, p0, \[x3\]
--.*: e420e060 st1b \{z0\.h\}, p0, \[x3\]
--.*: e420e060 st1b \{z0\.h\}, p0, \[x3\]
--.*: e420e060 st1b \{z0\.h\}, p0, \[x3\]
--.*: e420e3e0 st1b \{z0\.h\}, p0, \[sp\]
--.*: e420e3e0 st1b \{z0\.h\}, p0, \[sp\]
--.*: e420e3e0 st1b \{z0\.h\}, p0, \[sp\]
--.*: e420e3e0 st1b \{z0\.h\}, p0, \[sp\]
--.*: e427e000 st1b \{z0\.h\}, p0, \[x0, #7, mul vl\]
--.*: e427e000 st1b \{z0\.h\}, p0, \[x0, #7, mul vl\]
--.*: e428e000 st1b \{z0\.h\}, p0, \[x0, #-8, mul vl\]
--.*: e428e000 st1b \{z0\.h\}, p0, \[x0, #-8, mul vl\]
--.*: e429e000 st1b \{z0\.h\}, p0, \[x0, #-7, mul vl\]
--.*: e429e000 st1b \{z0\.h\}, p0, \[x0, #-7, mul vl\]
--.*: e42fe000 st1b \{z0\.h\}, p0, \[x0, #-1, mul vl\]
--.*: e42fe000 st1b \{z0\.h\}, p0, \[x0, #-1, mul vl\]
--.*: e440a000 st1b \{z0\.d\}, p0, \[z0\.d\]
--.*: e440a000 st1b \{z0\.d\}, p0, \[z0\.d\]
--.*: e440a000 st1b \{z0\.d\}, p0, \[z0\.d\]
--.*: e440a000 st1b \{z0\.d\}, p0, \[z0\.d\]
--.*: e440a001 st1b \{z1\.d\}, p0, \[z0\.d\]
--.*: e440a001 st1b \{z1\.d\}, p0, \[z0\.d\]
--.*: e440a001 st1b \{z1\.d\}, p0, \[z0\.d\]
--.*: e440a001 st1b \{z1\.d\}, p0, \[z0\.d\]
--.*: e440a01f st1b \{z31\.d\}, p0, \[z0\.d\]
--.*: e440a01f st1b \{z31\.d\}, p0, \[z0\.d\]
--.*: e440a01f st1b \{z31\.d\}, p0, \[z0\.d\]
--.*: e440a01f st1b \{z31\.d\}, p0, \[z0\.d\]
--.*: e440a800 st1b \{z0\.d\}, p2, \[z0\.d\]
--.*: e440a800 st1b \{z0\.d\}, p2, \[z0\.d\]
--.*: e440a800 st1b \{z0\.d\}, p2, \[z0\.d\]
--.*: e440bc00 st1b \{z0\.d\}, p7, \[z0\.d\]
--.*: e440bc00 st1b \{z0\.d\}, p7, \[z0\.d\]
--.*: e440bc00 st1b \{z0\.d\}, p7, \[z0\.d\]
--.*: e440a060 st1b \{z0\.d\}, p0, \[z3\.d\]
--.*: e440a060 st1b \{z0\.d\}, p0, \[z3\.d\]
--.*: e440a060 st1b \{z0\.d\}, p0, \[z3\.d\]
--.*: e440a3e0 st1b \{z0\.d\}, p0, \[z31\.d\]
--.*: e440a3e0 st1b \{z0\.d\}, p0, \[z31\.d\]
--.*: e440a3e0 st1b \{z0\.d\}, p0, \[z31\.d\]
--.*: e44fa000 st1b \{z0\.d\}, p0, \[z0\.d, #15\]
--.*: e44fa000 st1b \{z0\.d\}, p0, \[z0\.d, #15\]
--.*: e450a000 st1b \{z0\.d\}, p0, \[z0\.d, #16\]
--.*: e450a000 st1b \{z0\.d\}, p0, \[z0\.d, #16\]
--.*: e451a000 st1b \{z0\.d\}, p0, \[z0\.d, #17\]
--.*: e451a000 st1b \{z0\.d\}, p0, \[z0\.d, #17\]
--.*: e45fa000 st1b \{z0\.d\}, p0, \[z0\.d, #31\]
--.*: e45fa000 st1b \{z0\.d\}, p0, \[z0\.d, #31\]
--.*: e440e000 st1b \{z0\.s\}, p0, \[x0\]
--.*: e440e000 st1b \{z0\.s\}, p0, \[x0\]
--.*: e440e000 st1b \{z0\.s\}, p0, \[x0\]
--.*: e440e000 st1b \{z0\.s\}, p0, \[x0\]
--.*: e440e000 st1b \{z0\.s\}, p0, \[x0\]
--.*: e440e001 st1b \{z1\.s\}, p0, \[x0\]
--.*: e440e001 st1b \{z1\.s\}, p0, \[x0\]
--.*: e440e001 st1b \{z1\.s\}, p0, \[x0\]
--.*: e440e001 st1b \{z1\.s\}, p0, \[x0\]
--.*: e440e001 st1b \{z1\.s\}, p0, \[x0\]
--.*: e440e01f st1b \{z31\.s\}, p0, \[x0\]
--.*: e440e01f st1b \{z31\.s\}, p0, \[x0\]
--.*: e440e01f st1b \{z31\.s\}, p0, \[x0\]
--.*: e440e01f st1b \{z31\.s\}, p0, \[x0\]
--.*: e440e01f st1b \{z31\.s\}, p0, \[x0\]
--.*: e440e800 st1b \{z0\.s\}, p2, \[x0\]
--.*: e440e800 st1b \{z0\.s\}, p2, \[x0\]
--.*: e440e800 st1b \{z0\.s\}, p2, \[x0\]
--.*: e440e800 st1b \{z0\.s\}, p2, \[x0\]
--.*: e440fc00 st1b \{z0\.s\}, p7, \[x0\]
--.*: e440fc00 st1b \{z0\.s\}, p7, \[x0\]
--.*: e440fc00 st1b \{z0\.s\}, p7, \[x0\]
--.*: e440fc00 st1b \{z0\.s\}, p7, \[x0\]
--.*: e440e060 st1b \{z0\.s\}, p0, \[x3\]
--.*: e440e060 st1b \{z0\.s\}, p0, \[x3\]
--.*: e440e060 st1b \{z0\.s\}, p0, \[x3\]
--.*: e440e060 st1b \{z0\.s\}, p0, \[x3\]
--.*: e440e3e0 st1b \{z0\.s\}, p0, \[sp\]
--.*: e440e3e0 st1b \{z0\.s\}, p0, \[sp\]
--.*: e440e3e0 st1b \{z0\.s\}, p0, \[sp\]
--.*: e440e3e0 st1b \{z0\.s\}, p0, \[sp\]
--.*: e447e000 st1b \{z0\.s\}, p0, \[x0, #7, mul vl\]
--.*: e447e000 st1b \{z0\.s\}, p0, \[x0, #7, mul vl\]
--.*: e448e000 st1b \{z0\.s\}, p0, \[x0, #-8, mul vl\]
--.*: e448e000 st1b \{z0\.s\}, p0, \[x0, #-8, mul vl\]
--.*: e449e000 st1b \{z0\.s\}, p0, \[x0, #-7, mul vl\]
--.*: e449e000 st1b \{z0\.s\}, p0, \[x0, #-7, mul vl\]
--.*: e44fe000 st1b \{z0\.s\}, p0, \[x0, #-1, mul vl\]
--.*: e44fe000 st1b \{z0\.s\}, p0, \[x0, #-1, mul vl\]
--.*: e460a000 st1b \{z0\.s\}, p0, \[z0\.s\]
--.*: e460a000 st1b \{z0\.s\}, p0, \[z0\.s\]
--.*: e460a000 st1b \{z0\.s\}, p0, \[z0\.s\]
--.*: e460a000 st1b \{z0\.s\}, p0, \[z0\.s\]
--.*: e460a001 st1b \{z1\.s\}, p0, \[z0\.s\]
--.*: e460a001 st1b \{z1\.s\}, p0, \[z0\.s\]
--.*: e460a001 st1b \{z1\.s\}, p0, \[z0\.s\]
--.*: e460a001 st1b \{z1\.s\}, p0, \[z0\.s\]
--.*: e460a01f st1b \{z31\.s\}, p0, \[z0\.s\]
--.*: e460a01f st1b \{z31\.s\}, p0, \[z0\.s\]
--.*: e460a01f st1b \{z31\.s\}, p0, \[z0\.s\]
--.*: e460a01f st1b \{z31\.s\}, p0, \[z0\.s\]
--.*: e460a800 st1b \{z0\.s\}, p2, \[z0\.s\]
--.*: e460a800 st1b \{z0\.s\}, p2, \[z0\.s\]
--.*: e460a800 st1b \{z0\.s\}, p2, \[z0\.s\]
--.*: e460bc00 st1b \{z0\.s\}, p7, \[z0\.s\]
--.*: e460bc00 st1b \{z0\.s\}, p7, \[z0\.s\]
--.*: e460bc00 st1b \{z0\.s\}, p7, \[z0\.s\]
--.*: e460a060 st1b \{z0\.s\}, p0, \[z3\.s\]
--.*: e460a060 st1b \{z0\.s\}, p0, \[z3\.s\]
--.*: e460a060 st1b \{z0\.s\}, p0, \[z3\.s\]
--.*: e460a3e0 st1b \{z0\.s\}, p0, \[z31\.s\]
--.*: e460a3e0 st1b \{z0\.s\}, p0, \[z31\.s\]
--.*: e460a3e0 st1b \{z0\.s\}, p0, \[z31\.s\]
--.*: e46fa000 st1b \{z0\.s\}, p0, \[z0\.s, #15\]
--.*: e46fa000 st1b \{z0\.s\}, p0, \[z0\.s, #15\]
--.*: e470a000 st1b \{z0\.s\}, p0, \[z0\.s, #16\]
--.*: e470a000 st1b \{z0\.s\}, p0, \[z0\.s, #16\]
--.*: e471a000 st1b \{z0\.s\}, p0, \[z0\.s, #17\]
--.*: e471a000 st1b \{z0\.s\}, p0, \[z0\.s, #17\]
--.*: e47fa000 st1b \{z0\.s\}, p0, \[z0\.s, #31\]
--.*: e47fa000 st1b \{z0\.s\}, p0, \[z0\.s, #31\]
--.*: e460e000 st1b \{z0\.d\}, p0, \[x0\]
--.*: e460e000 st1b \{z0\.d\}, p0, \[x0\]
--.*: e460e000 st1b \{z0\.d\}, p0, \[x0\]
--.*: e460e000 st1b \{z0\.d\}, p0, \[x0\]
--.*: e460e000 st1b \{z0\.d\}, p0, \[x0\]
--.*: e460e001 st1b \{z1\.d\}, p0, \[x0\]
--.*: e460e001 st1b \{z1\.d\}, p0, \[x0\]
--.*: e460e001 st1b \{z1\.d\}, p0, \[x0\]
--.*: e460e001 st1b \{z1\.d\}, p0, \[x0\]
--.*: e460e001 st1b \{z1\.d\}, p0, \[x0\]
--.*: e460e01f st1b \{z31\.d\}, p0, \[x0\]
--.*: e460e01f st1b \{z31\.d\}, p0, \[x0\]
--.*: e460e01f st1b \{z31\.d\}, p0, \[x0\]
--.*: e460e01f st1b \{z31\.d\}, p0, \[x0\]
--.*: e460e01f st1b \{z31\.d\}, p0, \[x0\]
--.*: e460e800 st1b \{z0\.d\}, p2, \[x0\]
--.*: e460e800 st1b \{z0\.d\}, p2, \[x0\]
--.*: e460e800 st1b \{z0\.d\}, p2, \[x0\]
--.*: e460e800 st1b \{z0\.d\}, p2, \[x0\]
--.*: e460fc00 st1b \{z0\.d\}, p7, \[x0\]
--.*: e460fc00 st1b \{z0\.d\}, p7, \[x0\]
--.*: e460fc00 st1b \{z0\.d\}, p7, \[x0\]
--.*: e460fc00 st1b \{z0\.d\}, p7, \[x0\]
--.*: e460e060 st1b \{z0\.d\}, p0, \[x3\]
--.*: e460e060 st1b \{z0\.d\}, p0, \[x3\]
--.*: e460e060 st1b \{z0\.d\}, p0, \[x3\]
--.*: e460e060 st1b \{z0\.d\}, p0, \[x3\]
--.*: e460e3e0 st1b \{z0\.d\}, p0, \[sp\]
--.*: e460e3e0 st1b \{z0\.d\}, p0, \[sp\]
--.*: e460e3e0 st1b \{z0\.d\}, p0, \[sp\]
--.*: e460e3e0 st1b \{z0\.d\}, p0, \[sp\]
--.*: e467e000 st1b \{z0\.d\}, p0, \[x0, #7, mul vl\]
--.*: e467e000 st1b \{z0\.d\}, p0, \[x0, #7, mul vl\]
--.*: e468e000 st1b \{z0\.d\}, p0, \[x0, #-8, mul vl\]
--.*: e468e000 st1b \{z0\.d\}, p0, \[x0, #-8, mul vl\]
--.*: e469e000 st1b \{z0\.d\}, p0, \[x0, #-7, mul vl\]
--.*: e469e000 st1b \{z0\.d\}, p0, \[x0, #-7, mul vl\]
--.*: e46fe000 st1b \{z0\.d\}, p0, \[x0, #-1, mul vl\]
--.*: e46fe000 st1b \{z0\.d\}, p0, \[x0, #-1, mul vl\]
--.*: e5808000 st1d \{z0\.d\}, p0, \[x0, z0\.d, uxtw\]
--.*: e5808000 st1d \{z0\.d\}, p0, \[x0, z0\.d, uxtw\]
--.*: e5808000 st1d \{z0\.d\}, p0, \[x0, z0\.d, uxtw\]
--.*: e5808000 st1d \{z0\.d\}, p0, \[x0, z0\.d, uxtw\]
--.*: e5808001 st1d \{z1\.d\}, p0, \[x0, z0\.d, uxtw\]
--.*: e5808001 st1d \{z1\.d\}, p0, \[x0, z0\.d, uxtw\]
--.*: e5808001 st1d \{z1\.d\}, p0, \[x0, z0\.d, uxtw\]
--.*: e5808001 st1d \{z1\.d\}, p0, \[x0, z0\.d, uxtw\]
--.*: e580801f st1d \{z31\.d\}, p0, \[x0, z0\.d, uxtw\]
--.*: e580801f st1d \{z31\.d\}, p0, \[x0, z0\.d, uxtw\]
--.*: e580801f st1d \{z31\.d\}, p0, \[x0, z0\.d, uxtw\]
--.*: e580801f st1d \{z31\.d\}, p0, \[x0, z0\.d, uxtw\]
--.*: e5808800 st1d \{z0\.d\}, p2, \[x0, z0\.d, uxtw\]
--.*: e5808800 st1d \{z0\.d\}, p2, \[x0, z0\.d, uxtw\]
--.*: e5808800 st1d \{z0\.d\}, p2, \[x0, z0\.d, uxtw\]
--.*: e5809c00 st1d \{z0\.d\}, p7, \[x0, z0\.d, uxtw\]
--.*: e5809c00 st1d \{z0\.d\}, p7, \[x0, z0\.d, uxtw\]
--.*: e5809c00 st1d \{z0\.d\}, p7, \[x0, z0\.d, uxtw\]
--.*: e5808060 st1d \{z0\.d\}, p0, \[x3, z0\.d, uxtw\]
--.*: e5808060 st1d \{z0\.d\}, p0, \[x3, z0\.d, uxtw\]
--.*: e5808060 st1d \{z0\.d\}, p0, \[x3, z0\.d, uxtw\]
--.*: e58083e0 st1d \{z0\.d\}, p0, \[sp, z0\.d, uxtw\]
--.*: e58083e0 st1d \{z0\.d\}, p0, \[sp, z0\.d, uxtw\]
--.*: e58083e0 st1d \{z0\.d\}, p0, \[sp, z0\.d, uxtw\]
--.*: e5848000 st1d \{z0\.d\}, p0, \[x0, z4\.d, uxtw\]
--.*: e5848000 st1d \{z0\.d\}, p0, \[x0, z4\.d, uxtw\]
--.*: e5848000 st1d \{z0\.d\}, p0, \[x0, z4\.d, uxtw\]
--.*: e59f8000 st1d \{z0\.d\}, p0, \[x0, z31\.d, uxtw\]
--.*: e59f8000 st1d \{z0\.d\}, p0, \[x0, z31\.d, uxtw\]
--.*: e59f8000 st1d \{z0\.d\}, p0, \[x0, z31\.d, uxtw\]
--.*: e580c000 st1d \{z0\.d\}, p0, \[x0, z0\.d, sxtw\]
--.*: e580c000 st1d \{z0\.d\}, p0, \[x0, z0\.d, sxtw\]
--.*: e580c000 st1d \{z0\.d\}, p0, \[x0, z0\.d, sxtw\]
--.*: e580c000 st1d \{z0\.d\}, p0, \[x0, z0\.d, sxtw\]
--.*: e580c001 st1d \{z1\.d\}, p0, \[x0, z0\.d, sxtw\]
--.*: e580c001 st1d \{z1\.d\}, p0, \[x0, z0\.d, sxtw\]
--.*: e580c001 st1d \{z1\.d\}, p0, \[x0, z0\.d, sxtw\]
--.*: e580c001 st1d \{z1\.d\}, p0, \[x0, z0\.d, sxtw\]
--.*: e580c01f st1d \{z31\.d\}, p0, \[x0, z0\.d, sxtw\]
--.*: e580c01f st1d \{z31\.d\}, p0, \[x0, z0\.d, sxtw\]
--.*: e580c01f st1d \{z31\.d\}, p0, \[x0, z0\.d, sxtw\]
--.*: e580c01f st1d \{z31\.d\}, p0, \[x0, z0\.d, sxtw\]
--.*: e580c800 st1d \{z0\.d\}, p2, \[x0, z0\.d, sxtw\]
--.*: e580c800 st1d \{z0\.d\}, p2, \[x0, z0\.d, sxtw\]
--.*: e580c800 st1d \{z0\.d\}, p2, \[x0, z0\.d, sxtw\]
--.*: e580dc00 st1d \{z0\.d\}, p7, \[x0, z0\.d, sxtw\]
--.*: e580dc00 st1d \{z0\.d\}, p7, \[x0, z0\.d, sxtw\]
--.*: e580dc00 st1d \{z0\.d\}, p7, \[x0, z0\.d, sxtw\]
--.*: e580c060 st1d \{z0\.d\}, p0, \[x3, z0\.d, sxtw\]
--.*: e580c060 st1d \{z0\.d\}, p0, \[x3, z0\.d, sxtw\]
--.*: e580c060 st1d \{z0\.d\}, p0, \[x3, z0\.d, sxtw\]
--.*: e580c3e0 st1d \{z0\.d\}, p0, \[sp, z0\.d, sxtw\]
--.*: e580c3e0 st1d \{z0\.d\}, p0, \[sp, z0\.d, sxtw\]
--.*: e580c3e0 st1d \{z0\.d\}, p0, \[sp, z0\.d, sxtw\]
--.*: e584c000 st1d \{z0\.d\}, p0, \[x0, z4\.d, sxtw\]
--.*: e584c000 st1d \{z0\.d\}, p0, \[x0, z4\.d, sxtw\]
--.*: e584c000 st1d \{z0\.d\}, p0, \[x0, z4\.d, sxtw\]
--.*: e59fc000 st1d \{z0\.d\}, p0, \[x0, z31\.d, sxtw\]
--.*: e59fc000 st1d \{z0\.d\}, p0, \[x0, z31\.d, sxtw\]
--.*: e59fc000 st1d \{z0\.d\}, p0, \[x0, z31\.d, sxtw\]
--.*: e580a000 st1d \{z0\.d\}, p0, \[x0, z0\.d\]
--.*: e580a000 st1d \{z0\.d\}, p0, \[x0, z0\.d\]
--.*: e580a000 st1d \{z0\.d\}, p0, \[x0, z0\.d\]
--.*: e580a000 st1d \{z0\.d\}, p0, \[x0, z0\.d\]
--.*: e580a001 st1d \{z1\.d\}, p0, \[x0, z0\.d\]
--.*: e580a001 st1d \{z1\.d\}, p0, \[x0, z0\.d\]
--.*: e580a001 st1d \{z1\.d\}, p0, \[x0, z0\.d\]
--.*: e580a001 st1d \{z1\.d\}, p0, \[x0, z0\.d\]
--.*: e580a01f st1d \{z31\.d\}, p0, \[x0, z0\.d\]
--.*: e580a01f st1d \{z31\.d\}, p0, \[x0, z0\.d\]
--.*: e580a01f st1d \{z31\.d\}, p0, \[x0, z0\.d\]
--.*: e580a01f st1d \{z31\.d\}, p0, \[x0, z0\.d\]
--.*: e580a800 st1d \{z0\.d\}, p2, \[x0, z0\.d\]
--.*: e580a800 st1d \{z0\.d\}, p2, \[x0, z0\.d\]
--.*: e580a800 st1d \{z0\.d\}, p2, \[x0, z0\.d\]
--.*: e580bc00 st1d \{z0\.d\}, p7, \[x0, z0\.d\]
--.*: e580bc00 st1d \{z0\.d\}, p7, \[x0, z0\.d\]
--.*: e580bc00 st1d \{z0\.d\}, p7, \[x0, z0\.d\]
--.*: e580a060 st1d \{z0\.d\}, p0, \[x3, z0\.d\]
--.*: e580a060 st1d \{z0\.d\}, p0, \[x3, z0\.d\]
--.*: e580a060 st1d \{z0\.d\}, p0, \[x3, z0\.d\]
--.*: e580a3e0 st1d \{z0\.d\}, p0, \[sp, z0\.d\]
--.*: e580a3e0 st1d \{z0\.d\}, p0, \[sp, z0\.d\]
--.*: e580a3e0 st1d \{z0\.d\}, p0, \[sp, z0\.d\]
--.*: e584a000 st1d \{z0\.d\}, p0, \[x0, z4\.d\]
--.*: e584a000 st1d \{z0\.d\}, p0, \[x0, z4\.d\]
--.*: e584a000 st1d \{z0\.d\}, p0, \[x0, z4\.d\]
--.*: e59fa000 st1d \{z0\.d\}, p0, \[x0, z31\.d\]
--.*: e59fa000 st1d \{z0\.d\}, p0, \[x0, z31\.d\]
--.*: e59fa000 st1d \{z0\.d\}, p0, \[x0, z31\.d\]
--.*: e5a08000 st1d \{z0\.d\}, p0, \[x0, z0\.d, uxtw #3\]
--.*: e5a08000 st1d \{z0\.d\}, p0, \[x0, z0\.d, uxtw #3\]
--.*: e5a08000 st1d \{z0\.d\}, p0, \[x0, z0\.d, uxtw #3\]
--.*: e5a08001 st1d \{z1\.d\}, p0, \[x0, z0\.d, uxtw #3\]
--.*: e5a08001 st1d \{z1\.d\}, p0, \[x0, z0\.d, uxtw #3\]
--.*: e5a08001 st1d \{z1\.d\}, p0, \[x0, z0\.d, uxtw #3\]
--.*: e5a0801f st1d \{z31\.d\}, p0, \[x0, z0\.d, uxtw #3\]
--.*: e5a0801f st1d \{z31\.d\}, p0, \[x0, z0\.d, uxtw #3\]
--.*: e5a0801f st1d \{z31\.d\}, p0, \[x0, z0\.d, uxtw #3\]
--.*: e5a08800 st1d \{z0\.d\}, p2, \[x0, z0\.d, uxtw #3\]
--.*: e5a08800 st1d \{z0\.d\}, p2, \[x0, z0\.d, uxtw #3\]
--.*: e5a09c00 st1d \{z0\.d\}, p7, \[x0, z0\.d, uxtw #3\]
--.*: e5a09c00 st1d \{z0\.d\}, p7, \[x0, z0\.d, uxtw #3\]
--.*: e5a08060 st1d \{z0\.d\}, p0, \[x3, z0\.d, uxtw #3\]
--.*: e5a08060 st1d \{z0\.d\}, p0, \[x3, z0\.d, uxtw #3\]
--.*: e5a083e0 st1d \{z0\.d\}, p0, \[sp, z0\.d, uxtw #3\]
--.*: e5a083e0 st1d \{z0\.d\}, p0, \[sp, z0\.d, uxtw #3\]
--.*: e5a48000 st1d \{z0\.d\}, p0, \[x0, z4\.d, uxtw #3\]
--.*: e5a48000 st1d \{z0\.d\}, p0, \[x0, z4\.d, uxtw #3\]
--.*: e5bf8000 st1d \{z0\.d\}, p0, \[x0, z31\.d, uxtw #3\]
--.*: e5bf8000 st1d \{z0\.d\}, p0, \[x0, z31\.d, uxtw #3\]
--.*: e5a0c000 st1d \{z0\.d\}, p0, \[x0, z0\.d, sxtw #3\]
--.*: e5a0c000 st1d \{z0\.d\}, p0, \[x0, z0\.d, sxtw #3\]
--.*: e5a0c000 st1d \{z0\.d\}, p0, \[x0, z0\.d, sxtw #3\]
--.*: e5a0c001 st1d \{z1\.d\}, p0, \[x0, z0\.d, sxtw #3\]
--.*: e5a0c001 st1d \{z1\.d\}, p0, \[x0, z0\.d, sxtw #3\]
--.*: e5a0c001 st1d \{z1\.d\}, p0, \[x0, z0\.d, sxtw #3\]
--.*: e5a0c01f st1d \{z31\.d\}, p0, \[x0, z0\.d, sxtw #3\]
--.*: e5a0c01f st1d \{z31\.d\}, p0, \[x0, z0\.d, sxtw #3\]
--.*: e5a0c01f st1d \{z31\.d\}, p0, \[x0, z0\.d, sxtw #3\]
--.*: e5a0c800 st1d \{z0\.d\}, p2, \[x0, z0\.d, sxtw #3\]
--.*: e5a0c800 st1d \{z0\.d\}, p2, \[x0, z0\.d, sxtw #3\]
--.*: e5a0dc00 st1d \{z0\.d\}, p7, \[x0, z0\.d, sxtw #3\]
--.*: e5a0dc00 st1d \{z0\.d\}, p7, \[x0, z0\.d, sxtw #3\]
--.*: e5a0c060 st1d \{z0\.d\}, p0, \[x3, z0\.d, sxtw #3\]
--.*: e5a0c060 st1d \{z0\.d\}, p0, \[x3, z0\.d, sxtw #3\]
--.*: e5a0c3e0 st1d \{z0\.d\}, p0, \[sp, z0\.d, sxtw #3\]
--.*: e5a0c3e0 st1d \{z0\.d\}, p0, \[sp, z0\.d, sxtw #3\]
--.*: e5a4c000 st1d \{z0\.d\}, p0, \[x0, z4\.d, sxtw #3\]
--.*: e5a4c000 st1d \{z0\.d\}, p0, \[x0, z4\.d, sxtw #3\]
--.*: e5bfc000 st1d \{z0\.d\}, p0, \[x0, z31\.d, sxtw #3\]
--.*: e5bfc000 st1d \{z0\.d\}, p0, \[x0, z31\.d, sxtw #3\]
--.*: e5a0a000 st1d \{z0\.d\}, p0, \[x0, z0\.d, lsl #3\]
--.*: e5a0a000 st1d \{z0\.d\}, p0, \[x0, z0\.d, lsl #3\]
--.*: e5a0a000 st1d \{z0\.d\}, p0, \[x0, z0\.d, lsl #3\]
--.*: e5a0a001 st1d \{z1\.d\}, p0, \[x0, z0\.d, lsl #3\]
--.*: e5a0a001 st1d \{z1\.d\}, p0, \[x0, z0\.d, lsl #3\]
--.*: e5a0a001 st1d \{z1\.d\}, p0, \[x0, z0\.d, lsl #3\]
--.*: e5a0a01f st1d \{z31\.d\}, p0, \[x0, z0\.d, lsl #3\]
--.*: e5a0a01f st1d \{z31\.d\}, p0, \[x0, z0\.d, lsl #3\]
--.*: e5a0a01f st1d \{z31\.d\}, p0, \[x0, z0\.d, lsl #3\]
--.*: e5a0a800 st1d \{z0\.d\}, p2, \[x0, z0\.d, lsl #3\]
--.*: e5a0a800 st1d \{z0\.d\}, p2, \[x0, z0\.d, lsl #3\]
--.*: e5a0bc00 st1d \{z0\.d\}, p7, \[x0, z0\.d, lsl #3\]
--.*: e5a0bc00 st1d \{z0\.d\}, p7, \[x0, z0\.d, lsl #3\]
--.*: e5a0a060 st1d \{z0\.d\}, p0, \[x3, z0\.d, lsl #3\]
--.*: e5a0a060 st1d \{z0\.d\}, p0, \[x3, z0\.d, lsl #3\]
--.*: e5a0a3e0 st1d \{z0\.d\}, p0, \[sp, z0\.d, lsl #3\]
--.*: e5a0a3e0 st1d \{z0\.d\}, p0, \[sp, z0\.d, lsl #3\]
--.*: e5a4a000 st1d \{z0\.d\}, p0, \[x0, z4\.d, lsl #3\]
--.*: e5a4a000 st1d \{z0\.d\}, p0, \[x0, z4\.d, lsl #3\]
--.*: e5bfa000 st1d \{z0\.d\}, p0, \[x0, z31\.d, lsl #3\]
--.*: e5bfa000 st1d \{z0\.d\}, p0, \[x0, z31\.d, lsl #3\]
--.*: e5e04000 st1d \{z0\.d\}, p0, \[x0, x0, lsl #3\]
--.*: e5e04000 st1d \{z0\.d\}, p0, \[x0, x0, lsl #3\]
--.*: e5e04000 st1d \{z0\.d\}, p0, \[x0, x0, lsl #3\]
--.*: e5e04001 st1d \{z1\.d\}, p0, \[x0, x0, lsl #3\]
--.*: e5e04001 st1d \{z1\.d\}, p0, \[x0, x0, lsl #3\]
--.*: e5e04001 st1d \{z1\.d\}, p0, \[x0, x0, lsl #3\]
--.*: e5e0401f st1d \{z31\.d\}, p0, \[x0, x0, lsl #3\]
--.*: e5e0401f st1d \{z31\.d\}, p0, \[x0, x0, lsl #3\]
--.*: e5e0401f st1d \{z31\.d\}, p0, \[x0, x0, lsl #3\]
--.*: e5e04800 st1d \{z0\.d\}, p2, \[x0, x0, lsl #3\]
--.*: e5e04800 st1d \{z0\.d\}, p2, \[x0, x0, lsl #3\]
--.*: e5e05c00 st1d \{z0\.d\}, p7, \[x0, x0, lsl #3\]
--.*: e5e05c00 st1d \{z0\.d\}, p7, \[x0, x0, lsl #3\]
--.*: e5e04060 st1d \{z0\.d\}, p0, \[x3, x0, lsl #3\]
--.*: e5e04060 st1d \{z0\.d\}, p0, \[x3, x0, lsl #3\]
--.*: e5e043e0 st1d \{z0\.d\}, p0, \[sp, x0, lsl #3\]
--.*: e5e043e0 st1d \{z0\.d\}, p0, \[sp, x0, lsl #3\]
--.*: e5e44000 st1d \{z0\.d\}, p0, \[x0, x4, lsl #3\]
--.*: e5e44000 st1d \{z0\.d\}, p0, \[x0, x4, lsl #3\]
--.*: e5fe4000 st1d \{z0\.d\}, p0, \[x0, x30, lsl #3\]
--.*: e5fe4000 st1d \{z0\.d\}, p0, \[x0, x30, lsl #3\]
--.*: e5c0a000 st1d \{z0\.d\}, p0, \[z0\.d\]
--.*: e5c0a000 st1d \{z0\.d\}, p0, \[z0\.d\]
--.*: e5c0a000 st1d \{z0\.d\}, p0, \[z0\.d\]
--.*: e5c0a000 st1d \{z0\.d\}, p0, \[z0\.d\]
--.*: e5c0a001 st1d \{z1\.d\}, p0, \[z0\.d\]
--.*: e5c0a001 st1d \{z1\.d\}, p0, \[z0\.d\]
--.*: e5c0a001 st1d \{z1\.d\}, p0, \[z0\.d\]
--.*: e5c0a001 st1d \{z1\.d\}, p0, \[z0\.d\]
--.*: e5c0a01f st1d \{z31\.d\}, p0, \[z0\.d\]
--.*: e5c0a01f st1d \{z31\.d\}, p0, \[z0\.d\]
--.*: e5c0a01f st1d \{z31\.d\}, p0, \[z0\.d\]
--.*: e5c0a01f st1d \{z31\.d\}, p0, \[z0\.d\]
--.*: e5c0a800 st1d \{z0\.d\}, p2, \[z0\.d\]
--.*: e5c0a800 st1d \{z0\.d\}, p2, \[z0\.d\]
--.*: e5c0a800 st1d \{z0\.d\}, p2, \[z0\.d\]
--.*: e5c0bc00 st1d \{z0\.d\}, p7, \[z0\.d\]
--.*: e5c0bc00 st1d \{z0\.d\}, p7, \[z0\.d\]
--.*: e5c0bc00 st1d \{z0\.d\}, p7, \[z0\.d\]
--.*: e5c0a060 st1d \{z0\.d\}, p0, \[z3\.d\]
--.*: e5c0a060 st1d \{z0\.d\}, p0, \[z3\.d\]
--.*: e5c0a060 st1d \{z0\.d\}, p0, \[z3\.d\]
--.*: e5c0a3e0 st1d \{z0\.d\}, p0, \[z31\.d\]
--.*: e5c0a3e0 st1d \{z0\.d\}, p0, \[z31\.d\]
--.*: e5c0a3e0 st1d \{z0\.d\}, p0, \[z31\.d\]
--.*: e5cfa000 st1d \{z0\.d\}, p0, \[z0\.d, #120\]
--.*: e5cfa000 st1d \{z0\.d\}, p0, \[z0\.d, #120\]
--.*: e5d0a000 st1d \{z0\.d\}, p0, \[z0\.d, #128\]
--.*: e5d0a000 st1d \{z0\.d\}, p0, \[z0\.d, #128\]
--.*: e5d1a000 st1d \{z0\.d\}, p0, \[z0\.d, #136\]
--.*: e5d1a000 st1d \{z0\.d\}, p0, \[z0\.d, #136\]
--.*: e5dfa000 st1d \{z0\.d\}, p0, \[z0\.d, #248\]
--.*: e5dfa000 st1d \{z0\.d\}, p0, \[z0\.d, #248\]
--.*: e5e0e000 st1d \{z0\.d\}, p0, \[x0\]
--.*: e5e0e000 st1d \{z0\.d\}, p0, \[x0\]
--.*: e5e0e000 st1d \{z0\.d\}, p0, \[x0\]
--.*: e5e0e000 st1d \{z0\.d\}, p0, \[x0\]
--.*: e5e0e000 st1d \{z0\.d\}, p0, \[x0\]
--.*: e5e0e001 st1d \{z1\.d\}, p0, \[x0\]
--.*: e5e0e001 st1d \{z1\.d\}, p0, \[x0\]
--.*: e5e0e001 st1d \{z1\.d\}, p0, \[x0\]
--.*: e5e0e001 st1d \{z1\.d\}, p0, \[x0\]
--.*: e5e0e001 st1d \{z1\.d\}, p0, \[x0\]
--.*: e5e0e01f st1d \{z31\.d\}, p0, \[x0\]
--.*: e5e0e01f st1d \{z31\.d\}, p0, \[x0\]
--.*: e5e0e01f st1d \{z31\.d\}, p0, \[x0\]
--.*: e5e0e01f st1d \{z31\.d\}, p0, \[x0\]
--.*: e5e0e01f st1d \{z31\.d\}, p0, \[x0\]
--.*: e5e0e800 st1d \{z0\.d\}, p2, \[x0\]
--.*: e5e0e800 st1d \{z0\.d\}, p2, \[x0\]
--.*: e5e0e800 st1d \{z0\.d\}, p2, \[x0\]
--.*: e5e0e800 st1d \{z0\.d\}, p2, \[x0\]
--.*: e5e0fc00 st1d \{z0\.d\}, p7, \[x0\]
--.*: e5e0fc00 st1d \{z0\.d\}, p7, \[x0\]
--.*: e5e0fc00 st1d \{z0\.d\}, p7, \[x0\]
--.*: e5e0fc00 st1d \{z0\.d\}, p7, \[x0\]
--.*: e5e0e060 st1d \{z0\.d\}, p0, \[x3\]
--.*: e5e0e060 st1d \{z0\.d\}, p0, \[x3\]
--.*: e5e0e060 st1d \{z0\.d\}, p0, \[x3\]
--.*: e5e0e060 st1d \{z0\.d\}, p0, \[x3\]
--.*: e5e0e3e0 st1d \{z0\.d\}, p0, \[sp\]
--.*: e5e0e3e0 st1d \{z0\.d\}, p0, \[sp\]
--.*: e5e0e3e0 st1d \{z0\.d\}, p0, \[sp\]
--.*: e5e0e3e0 st1d \{z0\.d\}, p0, \[sp\]
--.*: e5e7e000 st1d \{z0\.d\}, p0, \[x0, #7, mul vl\]
--.*: e5e7e000 st1d \{z0\.d\}, p0, \[x0, #7, mul vl\]
--.*: e5e8e000 st1d \{z0\.d\}, p0, \[x0, #-8, mul vl\]
--.*: e5e8e000 st1d \{z0\.d\}, p0, \[x0, #-8, mul vl\]
--.*: e5e9e000 st1d \{z0\.d\}, p0, \[x0, #-7, mul vl\]
--.*: e5e9e000 st1d \{z0\.d\}, p0, \[x0, #-7, mul vl\]
--.*: e5efe000 st1d \{z0\.d\}, p0, \[x0, #-1, mul vl\]
--.*: e5efe000 st1d \{z0\.d\}, p0, \[x0, #-1, mul vl\]
--.*: e4808000 st1h \{z0\.d\}, p0, \[x0, z0\.d, uxtw\]
--.*: e4808000 st1h \{z0\.d\}, p0, \[x0, z0\.d, uxtw\]
--.*: e4808000 st1h \{z0\.d\}, p0, \[x0, z0\.d, uxtw\]
--.*: e4808000 st1h \{z0\.d\}, p0, \[x0, z0\.d, uxtw\]
--.*: e4808001 st1h \{z1\.d\}, p0, \[x0, z0\.d, uxtw\]
--.*: e4808001 st1h \{z1\.d\}, p0, \[x0, z0\.d, uxtw\]
--.*: e4808001 st1h \{z1\.d\}, p0, \[x0, z0\.d, uxtw\]
--.*: e4808001 st1h \{z1\.d\}, p0, \[x0, z0\.d, uxtw\]
--.*: e480801f st1h \{z31\.d\}, p0, \[x0, z0\.d, uxtw\]
--.*: e480801f st1h \{z31\.d\}, p0, \[x0, z0\.d, uxtw\]
--.*: e480801f st1h \{z31\.d\}, p0, \[x0, z0\.d, uxtw\]
--.*: e480801f st1h \{z31\.d\}, p0, \[x0, z0\.d, uxtw\]
--.*: e4808800 st1h \{z0\.d\}, p2, \[x0, z0\.d, uxtw\]
--.*: e4808800 st1h \{z0\.d\}, p2, \[x0, z0\.d, uxtw\]
--.*: e4808800 st1h \{z0\.d\}, p2, \[x0, z0\.d, uxtw\]
--.*: e4809c00 st1h \{z0\.d\}, p7, \[x0, z0\.d, uxtw\]
--.*: e4809c00 st1h \{z0\.d\}, p7, \[x0, z0\.d, uxtw\]
--.*: e4809c00 st1h \{z0\.d\}, p7, \[x0, z0\.d, uxtw\]
--.*: e4808060 st1h \{z0\.d\}, p0, \[x3, z0\.d, uxtw\]
--.*: e4808060 st1h \{z0\.d\}, p0, \[x3, z0\.d, uxtw\]
--.*: e4808060 st1h \{z0\.d\}, p0, \[x3, z0\.d, uxtw\]
--.*: e48083e0 st1h \{z0\.d\}, p0, \[sp, z0\.d, uxtw\]
--.*: e48083e0 st1h \{z0\.d\}, p0, \[sp, z0\.d, uxtw\]
--.*: e48083e0 st1h \{z0\.d\}, p0, \[sp, z0\.d, uxtw\]
--.*: e4848000 st1h \{z0\.d\}, p0, \[x0, z4\.d, uxtw\]
--.*: e4848000 st1h \{z0\.d\}, p0, \[x0, z4\.d, uxtw\]
--.*: e4848000 st1h \{z0\.d\}, p0, \[x0, z4\.d, uxtw\]
--.*: e49f8000 st1h \{z0\.d\}, p0, \[x0, z31\.d, uxtw\]
--.*: e49f8000 st1h \{z0\.d\}, p0, \[x0, z31\.d, uxtw\]
--.*: e49f8000 st1h \{z0\.d\}, p0, \[x0, z31\.d, uxtw\]
--.*: e480c000 st1h \{z0\.d\}, p0, \[x0, z0\.d, sxtw\]
--.*: e480c000 st1h \{z0\.d\}, p0, \[x0, z0\.d, sxtw\]
--.*: e480c000 st1h \{z0\.d\}, p0, \[x0, z0\.d, sxtw\]
--.*: e480c000 st1h \{z0\.d\}, p0, \[x0, z0\.d, sxtw\]
--.*: e480c001 st1h \{z1\.d\}, p0, \[x0, z0\.d, sxtw\]
--.*: e480c001 st1h \{z1\.d\}, p0, \[x0, z0\.d, sxtw\]
--.*: e480c001 st1h \{z1\.d\}, p0, \[x0, z0\.d, sxtw\]
--.*: e480c001 st1h \{z1\.d\}, p0, \[x0, z0\.d, sxtw\]
--.*: e480c01f st1h \{z31\.d\}, p0, \[x0, z0\.d, sxtw\]
--.*: e480c01f st1h \{z31\.d\}, p0, \[x0, z0\.d, sxtw\]
--.*: e480c01f st1h \{z31\.d\}, p0, \[x0, z0\.d, sxtw\]
--.*: e480c01f st1h \{z31\.d\}, p0, \[x0, z0\.d, sxtw\]
--.*: e480c800 st1h \{z0\.d\}, p2, \[x0, z0\.d, sxtw\]
--.*: e480c800 st1h \{z0\.d\}, p2, \[x0, z0\.d, sxtw\]
--.*: e480c800 st1h \{z0\.d\}, p2, \[x0, z0\.d, sxtw\]
--.*: e480dc00 st1h \{z0\.d\}, p7, \[x0, z0\.d, sxtw\]
--.*: e480dc00 st1h \{z0\.d\}, p7, \[x0, z0\.d, sxtw\]
--.*: e480dc00 st1h \{z0\.d\}, p7, \[x0, z0\.d, sxtw\]
--.*: e480c060 st1h \{z0\.d\}, p0, \[x3, z0\.d, sxtw\]
--.*: e480c060 st1h \{z0\.d\}, p0, \[x3, z0\.d, sxtw\]
--.*: e480c060 st1h \{z0\.d\}, p0, \[x3, z0\.d, sxtw\]
--.*: e480c3e0 st1h \{z0\.d\}, p0, \[sp, z0\.d, sxtw\]
--.*: e480c3e0 st1h \{z0\.d\}, p0, \[sp, z0\.d, sxtw\]
--.*: e480c3e0 st1h \{z0\.d\}, p0, \[sp, z0\.d, sxtw\]
--.*: e484c000 st1h \{z0\.d\}, p0, \[x0, z4\.d, sxtw\]
--.*: e484c000 st1h \{z0\.d\}, p0, \[x0, z4\.d, sxtw\]
--.*: e484c000 st1h \{z0\.d\}, p0, \[x0, z4\.d, sxtw\]
--.*: e49fc000 st1h \{z0\.d\}, p0, \[x0, z31\.d, sxtw\]
--.*: e49fc000 st1h \{z0\.d\}, p0, \[x0, z31\.d, sxtw\]
--.*: e49fc000 st1h \{z0\.d\}, p0, \[x0, z31\.d, sxtw\]
--.*: e480a000 st1h \{z0\.d\}, p0, \[x0, z0\.d\]
--.*: e480a000 st1h \{z0\.d\}, p0, \[x0, z0\.d\]
--.*: e480a000 st1h \{z0\.d\}, p0, \[x0, z0\.d\]
--.*: e480a000 st1h \{z0\.d\}, p0, \[x0, z0\.d\]
--.*: e480a001 st1h \{z1\.d\}, p0, \[x0, z0\.d\]
--.*: e480a001 st1h \{z1\.d\}, p0, \[x0, z0\.d\]
--.*: e480a001 st1h \{z1\.d\}, p0, \[x0, z0\.d\]
--.*: e480a001 st1h \{z1\.d\}, p0, \[x0, z0\.d\]
--.*: e480a01f st1h \{z31\.d\}, p0, \[x0, z0\.d\]
--.*: e480a01f st1h \{z31\.d\}, p0, \[x0, z0\.d\]
--.*: e480a01f st1h \{z31\.d\}, p0, \[x0, z0\.d\]
--.*: e480a01f st1h \{z31\.d\}, p0, \[x0, z0\.d\]
--.*: e480a800 st1h \{z0\.d\}, p2, \[x0, z0\.d\]
--.*: e480a800 st1h \{z0\.d\}, p2, \[x0, z0\.d\]
--.*: e480a800 st1h \{z0\.d\}, p2, \[x0, z0\.d\]
--.*: e480bc00 st1h \{z0\.d\}, p7, \[x0, z0\.d\]
--.*: e480bc00 st1h \{z0\.d\}, p7, \[x0, z0\.d\]
--.*: e480bc00 st1h \{z0\.d\}, p7, \[x0, z0\.d\]
--.*: e480a060 st1h \{z0\.d\}, p0, \[x3, z0\.d\]
--.*: e480a060 st1h \{z0\.d\}, p0, \[x3, z0\.d\]
--.*: e480a060 st1h \{z0\.d\}, p0, \[x3, z0\.d\]
--.*: e480a3e0 st1h \{z0\.d\}, p0, \[sp, z0\.d\]
--.*: e480a3e0 st1h \{z0\.d\}, p0, \[sp, z0\.d\]
--.*: e480a3e0 st1h \{z0\.d\}, p0, \[sp, z0\.d\]
--.*: e484a000 st1h \{z0\.d\}, p0, \[x0, z4\.d\]
--.*: e484a000 st1h \{z0\.d\}, p0, \[x0, z4\.d\]
--.*: e484a000 st1h \{z0\.d\}, p0, \[x0, z4\.d\]
--.*: e49fa000 st1h \{z0\.d\}, p0, \[x0, z31\.d\]
--.*: e49fa000 st1h \{z0\.d\}, p0, \[x0, z31\.d\]
--.*: e49fa000 st1h \{z0\.d\}, p0, \[x0, z31\.d\]
--.*: e4a04000 st1h \{z0\.h\}, p0, \[x0, x0, lsl #1\]
--.*: e4a04000 st1h \{z0\.h\}, p0, \[x0, x0, lsl #1\]
--.*: e4a04000 st1h \{z0\.h\}, p0, \[x0, x0, lsl #1\]
--.*: e4a04001 st1h \{z1\.h\}, p0, \[x0, x0, lsl #1\]
--.*: e4a04001 st1h \{z1\.h\}, p0, \[x0, x0, lsl #1\]
--.*: e4a04001 st1h \{z1\.h\}, p0, \[x0, x0, lsl #1\]
--.*: e4a0401f st1h \{z31\.h\}, p0, \[x0, x0, lsl #1\]
--.*: e4a0401f st1h \{z31\.h\}, p0, \[x0, x0, lsl #1\]
--.*: e4a0401f st1h \{z31\.h\}, p0, \[x0, x0, lsl #1\]
--.*: e4a04800 st1h \{z0\.h\}, p2, \[x0, x0, lsl #1\]
--.*: e4a04800 st1h \{z0\.h\}, p2, \[x0, x0, lsl #1\]
--.*: e4a05c00 st1h \{z0\.h\}, p7, \[x0, x0, lsl #1\]
--.*: e4a05c00 st1h \{z0\.h\}, p7, \[x0, x0, lsl #1\]
--.*: e4a04060 st1h \{z0\.h\}, p0, \[x3, x0, lsl #1\]
--.*: e4a04060 st1h \{z0\.h\}, p0, \[x3, x0, lsl #1\]
--.*: e4a043e0 st1h \{z0\.h\}, p0, \[sp, x0, lsl #1\]
--.*: e4a043e0 st1h \{z0\.h\}, p0, \[sp, x0, lsl #1\]
--.*: e4a44000 st1h \{z0\.h\}, p0, \[x0, x4, lsl #1\]
--.*: e4a44000 st1h \{z0\.h\}, p0, \[x0, x4, lsl #1\]
--.*: e4be4000 st1h \{z0\.h\}, p0, \[x0, x30, lsl #1\]
--.*: e4be4000 st1h \{z0\.h\}, p0, \[x0, x30, lsl #1\]
--.*: e4a08000 st1h \{z0\.d\}, p0, \[x0, z0\.d, uxtw #1\]
--.*: e4a08000 st1h \{z0\.d\}, p0, \[x0, z0\.d, uxtw #1\]
--.*: e4a08000 st1h \{z0\.d\}, p0, \[x0, z0\.d, uxtw #1\]
--.*: e4a08001 st1h \{z1\.d\}, p0, \[x0, z0\.d, uxtw #1\]
--.*: e4a08001 st1h \{z1\.d\}, p0, \[x0, z0\.d, uxtw #1\]
--.*: e4a08001 st1h \{z1\.d\}, p0, \[x0, z0\.d, uxtw #1\]
--.*: e4a0801f st1h \{z31\.d\}, p0, \[x0, z0\.d, uxtw #1\]
--.*: e4a0801f st1h \{z31\.d\}, p0, \[x0, z0\.d, uxtw #1\]
--.*: e4a0801f st1h \{z31\.d\}, p0, \[x0, z0\.d, uxtw #1\]
--.*: e4a08800 st1h \{z0\.d\}, p2, \[x0, z0\.d, uxtw #1\]
--.*: e4a08800 st1h \{z0\.d\}, p2, \[x0, z0\.d, uxtw #1\]
--.*: e4a09c00 st1h \{z0\.d\}, p7, \[x0, z0\.d, uxtw #1\]
--.*: e4a09c00 st1h \{z0\.d\}, p7, \[x0, z0\.d, uxtw #1\]
--.*: e4a08060 st1h \{z0\.d\}, p0, \[x3, z0\.d, uxtw #1\]
--.*: e4a08060 st1h \{z0\.d\}, p0, \[x3, z0\.d, uxtw #1\]
--.*: e4a083e0 st1h \{z0\.d\}, p0, \[sp, z0\.d, uxtw #1\]
--.*: e4a083e0 st1h \{z0\.d\}, p0, \[sp, z0\.d, uxtw #1\]
--.*: e4a48000 st1h \{z0\.d\}, p0, \[x0, z4\.d, uxtw #1\]
--.*: e4a48000 st1h \{z0\.d\}, p0, \[x0, z4\.d, uxtw #1\]
--.*: e4bf8000 st1h \{z0\.d\}, p0, \[x0, z31\.d, uxtw #1\]
--.*: e4bf8000 st1h \{z0\.d\}, p0, \[x0, z31\.d, uxtw #1\]
--.*: e4a0c000 st1h \{z0\.d\}, p0, \[x0, z0\.d, sxtw #1\]
--.*: e4a0c000 st1h \{z0\.d\}, p0, \[x0, z0\.d, sxtw #1\]
--.*: e4a0c000 st1h \{z0\.d\}, p0, \[x0, z0\.d, sxtw #1\]
--.*: e4a0c001 st1h \{z1\.d\}, p0, \[x0, z0\.d, sxtw #1\]
--.*: e4a0c001 st1h \{z1\.d\}, p0, \[x0, z0\.d, sxtw #1\]
--.*: e4a0c001 st1h \{z1\.d\}, p0, \[x0, z0\.d, sxtw #1\]
--.*: e4a0c01f st1h \{z31\.d\}, p0, \[x0, z0\.d, sxtw #1\]
--.*: e4a0c01f st1h \{z31\.d\}, p0, \[x0, z0\.d, sxtw #1\]
--.*: e4a0c01f st1h \{z31\.d\}, p0, \[x0, z0\.d, sxtw #1\]
--.*: e4a0c800 st1h \{z0\.d\}, p2, \[x0, z0\.d, sxtw #1\]
--.*: e4a0c800 st1h \{z0\.d\}, p2, \[x0, z0\.d, sxtw #1\]
--.*: e4a0dc00 st1h \{z0\.d\}, p7, \[x0, z0\.d, sxtw #1\]
--.*: e4a0dc00 st1h \{z0\.d\}, p7, \[x0, z0\.d, sxtw #1\]
--.*: e4a0c060 st1h \{z0\.d\}, p0, \[x3, z0\.d, sxtw #1\]
--.*: e4a0c060 st1h \{z0\.d\}, p0, \[x3, z0\.d, sxtw #1\]
--.*: e4a0c3e0 st1h \{z0\.d\}, p0, \[sp, z0\.d, sxtw #1\]
--.*: e4a0c3e0 st1h \{z0\.d\}, p0, \[sp, z0\.d, sxtw #1\]
--.*: e4a4c000 st1h \{z0\.d\}, p0, \[x0, z4\.d, sxtw #1\]
--.*: e4a4c000 st1h \{z0\.d\}, p0, \[x0, z4\.d, sxtw #1\]
--.*: e4bfc000 st1h \{z0\.d\}, p0, \[x0, z31\.d, sxtw #1\]
--.*: e4bfc000 st1h \{z0\.d\}, p0, \[x0, z31\.d, sxtw #1\]
--.*: e4a0a000 st1h \{z0\.d\}, p0, \[x0, z0\.d, lsl #1\]
--.*: e4a0a000 st1h \{z0\.d\}, p0, \[x0, z0\.d, lsl #1\]
--.*: e4a0a000 st1h \{z0\.d\}, p0, \[x0, z0\.d, lsl #1\]
--.*: e4a0a001 st1h \{z1\.d\}, p0, \[x0, z0\.d, lsl #1\]
--.*: e4a0a001 st1h \{z1\.d\}, p0, \[x0, z0\.d, lsl #1\]
--.*: e4a0a001 st1h \{z1\.d\}, p0, \[x0, z0\.d, lsl #1\]
--.*: e4a0a01f st1h \{z31\.d\}, p0, \[x0, z0\.d, lsl #1\]
--.*: e4a0a01f st1h \{z31\.d\}, p0, \[x0, z0\.d, lsl #1\]
--.*: e4a0a01f st1h \{z31\.d\}, p0, \[x0, z0\.d, lsl #1\]
--.*: e4a0a800 st1h \{z0\.d\}, p2, \[x0, z0\.d, lsl #1\]
--.*: e4a0a800 st1h \{z0\.d\}, p2, \[x0, z0\.d, lsl #1\]
--.*: e4a0bc00 st1h \{z0\.d\}, p7, \[x0, z0\.d, lsl #1\]
--.*: e4a0bc00 st1h \{z0\.d\}, p7, \[x0, z0\.d, lsl #1\]
--.*: e4a0a060 st1h \{z0\.d\}, p0, \[x3, z0\.d, lsl #1\]
--.*: e4a0a060 st1h \{z0\.d\}, p0, \[x3, z0\.d, lsl #1\]
--.*: e4a0a3e0 st1h \{z0\.d\}, p0, \[sp, z0\.d, lsl #1\]
--.*: e4a0a3e0 st1h \{z0\.d\}, p0, \[sp, z0\.d, lsl #1\]
--.*: e4a4a000 st1h \{z0\.d\}, p0, \[x0, z4\.d, lsl #1\]
--.*: e4a4a000 st1h \{z0\.d\}, p0, \[x0, z4\.d, lsl #1\]
--.*: e4bfa000 st1h \{z0\.d\}, p0, \[x0, z31\.d, lsl #1\]
--.*: e4bfa000 st1h \{z0\.d\}, p0, \[x0, z31\.d, lsl #1\]
--.*: e4c04000 st1h \{z0\.s\}, p0, \[x0, x0, lsl #1\]
--.*: e4c04000 st1h \{z0\.s\}, p0, \[x0, x0, lsl #1\]
--.*: e4c04000 st1h \{z0\.s\}, p0, \[x0, x0, lsl #1\]
--.*: e4c04001 st1h \{z1\.s\}, p0, \[x0, x0, lsl #1\]
--.*: e4c04001 st1h \{z1\.s\}, p0, \[x0, x0, lsl #1\]
--.*: e4c04001 st1h \{z1\.s\}, p0, \[x0, x0, lsl #1\]
--.*: e4c0401f st1h \{z31\.s\}, p0, \[x0, x0, lsl #1\]
--.*: e4c0401f st1h \{z31\.s\}, p0, \[x0, x0, lsl #1\]
--.*: e4c0401f st1h \{z31\.s\}, p0, \[x0, x0, lsl #1\]
--.*: e4c04800 st1h \{z0\.s\}, p2, \[x0, x0, lsl #1\]
--.*: e4c04800 st1h \{z0\.s\}, p2, \[x0, x0, lsl #1\]
--.*: e4c05c00 st1h \{z0\.s\}, p7, \[x0, x0, lsl #1\]
--.*: e4c05c00 st1h \{z0\.s\}, p7, \[x0, x0, lsl #1\]
--.*: e4c04060 st1h \{z0\.s\}, p0, \[x3, x0, lsl #1\]
--.*: e4c04060 st1h \{z0\.s\}, p0, \[x3, x0, lsl #1\]
--.*: e4c043e0 st1h \{z0\.s\}, p0, \[sp, x0, lsl #1\]
--.*: e4c043e0 st1h \{z0\.s\}, p0, \[sp, x0, lsl #1\]
--.*: e4c44000 st1h \{z0\.s\}, p0, \[x0, x4, lsl #1\]
--.*: e4c44000 st1h \{z0\.s\}, p0, \[x0, x4, lsl #1\]
--.*: e4de4000 st1h \{z0\.s\}, p0, \[x0, x30, lsl #1\]
--.*: e4de4000 st1h \{z0\.s\}, p0, \[x0, x30, lsl #1\]
--.*: e4c08000 st1h \{z0\.s\}, p0, \[x0, z0\.s, uxtw\]
--.*: e4c08000 st1h \{z0\.s\}, p0, \[x0, z0\.s, uxtw\]
--.*: e4c08000 st1h \{z0\.s\}, p0, \[x0, z0\.s, uxtw\]
--.*: e4c08000 st1h \{z0\.s\}, p0, \[x0, z0\.s, uxtw\]
--.*: e4c08001 st1h \{z1\.s\}, p0, \[x0, z0\.s, uxtw\]
--.*: e4c08001 st1h \{z1\.s\}, p0, \[x0, z0\.s, uxtw\]
--.*: e4c08001 st1h \{z1\.s\}, p0, \[x0, z0\.s, uxtw\]
--.*: e4c08001 st1h \{z1\.s\}, p0, \[x0, z0\.s, uxtw\]
--.*: e4c0801f st1h \{z31\.s\}, p0, \[x0, z0\.s, uxtw\]
--.*: e4c0801f st1h \{z31\.s\}, p0, \[x0, z0\.s, uxtw\]
--.*: e4c0801f st1h \{z31\.s\}, p0, \[x0, z0\.s, uxtw\]
--.*: e4c0801f st1h \{z31\.s\}, p0, \[x0, z0\.s, uxtw\]
--.*: e4c08800 st1h \{z0\.s\}, p2, \[x0, z0\.s, uxtw\]
--.*: e4c08800 st1h \{z0\.s\}, p2, \[x0, z0\.s, uxtw\]
--.*: e4c08800 st1h \{z0\.s\}, p2, \[x0, z0\.s, uxtw\]
--.*: e4c09c00 st1h \{z0\.s\}, p7, \[x0, z0\.s, uxtw\]
--.*: e4c09c00 st1h \{z0\.s\}, p7, \[x0, z0\.s, uxtw\]
--.*: e4c09c00 st1h \{z0\.s\}, p7, \[x0, z0\.s, uxtw\]
--.*: e4c08060 st1h \{z0\.s\}, p0, \[x3, z0\.s, uxtw\]
--.*: e4c08060 st1h \{z0\.s\}, p0, \[x3, z0\.s, uxtw\]
--.*: e4c08060 st1h \{z0\.s\}, p0, \[x3, z0\.s, uxtw\]
--.*: e4c083e0 st1h \{z0\.s\}, p0, \[sp, z0\.s, uxtw\]
--.*: e4c083e0 st1h \{z0\.s\}, p0, \[sp, z0\.s, uxtw\]
--.*: e4c083e0 st1h \{z0\.s\}, p0, \[sp, z0\.s, uxtw\]
--.*: e4c48000 st1h \{z0\.s\}, p0, \[x0, z4\.s, uxtw\]
--.*: e4c48000 st1h \{z0\.s\}, p0, \[x0, z4\.s, uxtw\]
--.*: e4c48000 st1h \{z0\.s\}, p0, \[x0, z4\.s, uxtw\]
--.*: e4df8000 st1h \{z0\.s\}, p0, \[x0, z31\.s, uxtw\]
--.*: e4df8000 st1h \{z0\.s\}, p0, \[x0, z31\.s, uxtw\]
--.*: e4df8000 st1h \{z0\.s\}, p0, \[x0, z31\.s, uxtw\]
--.*: e4c0c000 st1h \{z0\.s\}, p0, \[x0, z0\.s, sxtw\]
--.*: e4c0c000 st1h \{z0\.s\}, p0, \[x0, z0\.s, sxtw\]
--.*: e4c0c000 st1h \{z0\.s\}, p0, \[x0, z0\.s, sxtw\]
--.*: e4c0c000 st1h \{z0\.s\}, p0, \[x0, z0\.s, sxtw\]
--.*: e4c0c001 st1h \{z1\.s\}, p0, \[x0, z0\.s, sxtw\]
--.*: e4c0c001 st1h \{z1\.s\}, p0, \[x0, z0\.s, sxtw\]
--.*: e4c0c001 st1h \{z1\.s\}, p0, \[x0, z0\.s, sxtw\]
--.*: e4c0c001 st1h \{z1\.s\}, p0, \[x0, z0\.s, sxtw\]
--.*: e4c0c01f st1h \{z31\.s\}, p0, \[x0, z0\.s, sxtw\]
--.*: e4c0c01f st1h \{z31\.s\}, p0, \[x0, z0\.s, sxtw\]
--.*: e4c0c01f st1h \{z31\.s\}, p0, \[x0, z0\.s, sxtw\]
--.*: e4c0c01f st1h \{z31\.s\}, p0, \[x0, z0\.s, sxtw\]
--.*: e4c0c800 st1h \{z0\.s\}, p2, \[x0, z0\.s, sxtw\]
--.*: e4c0c800 st1h \{z0\.s\}, p2, \[x0, z0\.s, sxtw\]
--.*: e4c0c800 st1h \{z0\.s\}, p2, \[x0, z0\.s, sxtw\]
--.*: e4c0dc00 st1h \{z0\.s\}, p7, \[x0, z0\.s, sxtw\]
--.*: e4c0dc00 st1h \{z0\.s\}, p7, \[x0, z0\.s, sxtw\]
--.*: e4c0dc00 st1h \{z0\.s\}, p7, \[x0, z0\.s, sxtw\]
--.*: e4c0c060 st1h \{z0\.s\}, p0, \[x3, z0\.s, sxtw\]
--.*: e4c0c060 st1h \{z0\.s\}, p0, \[x3, z0\.s, sxtw\]
--.*: e4c0c060 st1h \{z0\.s\}, p0, \[x3, z0\.s, sxtw\]
--.*: e4c0c3e0 st1h \{z0\.s\}, p0, \[sp, z0\.s, sxtw\]
--.*: e4c0c3e0 st1h \{z0\.s\}, p0, \[sp, z0\.s, sxtw\]
--.*: e4c0c3e0 st1h \{z0\.s\}, p0, \[sp, z0\.s, sxtw\]
--.*: e4c4c000 st1h \{z0\.s\}, p0, \[x0, z4\.s, sxtw\]
--.*: e4c4c000 st1h \{z0\.s\}, p0, \[x0, z4\.s, sxtw\]
--.*: e4c4c000 st1h \{z0\.s\}, p0, \[x0, z4\.s, sxtw\]
--.*: e4dfc000 st1h \{z0\.s\}, p0, \[x0, z31\.s, sxtw\]
--.*: e4dfc000 st1h \{z0\.s\}, p0, \[x0, z31\.s, sxtw\]
--.*: e4dfc000 st1h \{z0\.s\}, p0, \[x0, z31\.s, sxtw\]
--.*: e4e04000 st1h \{z0\.d\}, p0, \[x0, x0, lsl #1\]
--.*: e4e04000 st1h \{z0\.d\}, p0, \[x0, x0, lsl #1\]
--.*: e4e04000 st1h \{z0\.d\}, p0, \[x0, x0, lsl #1\]
--.*: e4e04001 st1h \{z1\.d\}, p0, \[x0, x0, lsl #1\]
--.*: e4e04001 st1h \{z1\.d\}, p0, \[x0, x0, lsl #1\]
--.*: e4e04001 st1h \{z1\.d\}, p0, \[x0, x0, lsl #1\]
--.*: e4e0401f st1h \{z31\.d\}, p0, \[x0, x0, lsl #1\]
--.*: e4e0401f st1h \{z31\.d\}, p0, \[x0, x0, lsl #1\]
--.*: e4e0401f st1h \{z31\.d\}, p0, \[x0, x0, lsl #1\]
--.*: e4e04800 st1h \{z0\.d\}, p2, \[x0, x0, lsl #1\]
--.*: e4e04800 st1h \{z0\.d\}, p2, \[x0, x0, lsl #1\]
--.*: e4e05c00 st1h \{z0\.d\}, p7, \[x0, x0, lsl #1\]
--.*: e4e05c00 st1h \{z0\.d\}, p7, \[x0, x0, lsl #1\]
--.*: e4e04060 st1h \{z0\.d\}, p0, \[x3, x0, lsl #1\]
--.*: e4e04060 st1h \{z0\.d\}, p0, \[x3, x0, lsl #1\]
--.*: e4e043e0 st1h \{z0\.d\}, p0, \[sp, x0, lsl #1\]
--.*: e4e043e0 st1h \{z0\.d\}, p0, \[sp, x0, lsl #1\]
--.*: e4e44000 st1h \{z0\.d\}, p0, \[x0, x4, lsl #1\]
--.*: e4e44000 st1h \{z0\.d\}, p0, \[x0, x4, lsl #1\]
--.*: e4fe4000 st1h \{z0\.d\}, p0, \[x0, x30, lsl #1\]
--.*: e4fe4000 st1h \{z0\.d\}, p0, \[x0, x30, lsl #1\]
--.*: e4e08000 st1h \{z0\.s\}, p0, \[x0, z0\.s, uxtw #1\]
--.*: e4e08000 st1h \{z0\.s\}, p0, \[x0, z0\.s, uxtw #1\]
--.*: e4e08000 st1h \{z0\.s\}, p0, \[x0, z0\.s, uxtw #1\]
--.*: e4e08001 st1h \{z1\.s\}, p0, \[x0, z0\.s, uxtw #1\]
--.*: e4e08001 st1h \{z1\.s\}, p0, \[x0, z0\.s, uxtw #1\]
--.*: e4e08001 st1h \{z1\.s\}, p0, \[x0, z0\.s, uxtw #1\]
--.*: e4e0801f st1h \{z31\.s\}, p0, \[x0, z0\.s, uxtw #1\]
--.*: e4e0801f st1h \{z31\.s\}, p0, \[x0, z0\.s, uxtw #1\]
--.*: e4e0801f st1h \{z31\.s\}, p0, \[x0, z0\.s, uxtw #1\]
--.*: e4e08800 st1h \{z0\.s\}, p2, \[x0, z0\.s, uxtw #1\]
--.*: e4e08800 st1h \{z0\.s\}, p2, \[x0, z0\.s, uxtw #1\]
--.*: e4e09c00 st1h \{z0\.s\}, p7, \[x0, z0\.s, uxtw #1\]
--.*: e4e09c00 st1h \{z0\.s\}, p7, \[x0, z0\.s, uxtw #1\]
--.*: e4e08060 st1h \{z0\.s\}, p0, \[x3, z0\.s, uxtw #1\]
--.*: e4e08060 st1h \{z0\.s\}, p0, \[x3, z0\.s, uxtw #1\]
--.*: e4e083e0 st1h \{z0\.s\}, p0, \[sp, z0\.s, uxtw #1\]
--.*: e4e083e0 st1h \{z0\.s\}, p0, \[sp, z0\.s, uxtw #1\]
--.*: e4e48000 st1h \{z0\.s\}, p0, \[x0, z4\.s, uxtw #1\]
--.*: e4e48000 st1h \{z0\.s\}, p0, \[x0, z4\.s, uxtw #1\]
--.*: e4ff8000 st1h \{z0\.s\}, p0, \[x0, z31\.s, uxtw #1\]
--.*: e4ff8000 st1h \{z0\.s\}, p0, \[x0, z31\.s, uxtw #1\]
--.*: e4e0c000 st1h \{z0\.s\}, p0, \[x0, z0\.s, sxtw #1\]
--.*: e4e0c000 st1h \{z0\.s\}, p0, \[x0, z0\.s, sxtw #1\]
--.*: e4e0c000 st1h \{z0\.s\}, p0, \[x0, z0\.s, sxtw #1\]
--.*: e4e0c001 st1h \{z1\.s\}, p0, \[x0, z0\.s, sxtw #1\]
--.*: e4e0c001 st1h \{z1\.s\}, p0, \[x0, z0\.s, sxtw #1\]
--.*: e4e0c001 st1h \{z1\.s\}, p0, \[x0, z0\.s, sxtw #1\]
--.*: e4e0c01f st1h \{z31\.s\}, p0, \[x0, z0\.s, sxtw #1\]
--.*: e4e0c01f st1h \{z31\.s\}, p0, \[x0, z0\.s, sxtw #1\]
--.*: e4e0c01f st1h \{z31\.s\}, p0, \[x0, z0\.s, sxtw #1\]
--.*: e4e0c800 st1h \{z0\.s\}, p2, \[x0, z0\.s, sxtw #1\]
--.*: e4e0c800 st1h \{z0\.s\}, p2, \[x0, z0\.s, sxtw #1\]
--.*: e4e0dc00 st1h \{z0\.s\}, p7, \[x0, z0\.s, sxtw #1\]
--.*: e4e0dc00 st1h \{z0\.s\}, p7, \[x0, z0\.s, sxtw #1\]
--.*: e4e0c060 st1h \{z0\.s\}, p0, \[x3, z0\.s, sxtw #1\]
--.*: e4e0c060 st1h \{z0\.s\}, p0, \[x3, z0\.s, sxtw #1\]
--.*: e4e0c3e0 st1h \{z0\.s\}, p0, \[sp, z0\.s, sxtw #1\]
--.*: e4e0c3e0 st1h \{z0\.s\}, p0, \[sp, z0\.s, sxtw #1\]
--.*: e4e4c000 st1h \{z0\.s\}, p0, \[x0, z4\.s, sxtw #1\]
--.*: e4e4c000 st1h \{z0\.s\}, p0, \[x0, z4\.s, sxtw #1\]
--.*: e4ffc000 st1h \{z0\.s\}, p0, \[x0, z31\.s, sxtw #1\]
--.*: e4ffc000 st1h \{z0\.s\}, p0, \[x0, z31\.s, sxtw #1\]
--.*: e4a0e000 st1h \{z0\.h\}, p0, \[x0\]
--.*: e4a0e000 st1h \{z0\.h\}, p0, \[x0\]
--.*: e4a0e000 st1h \{z0\.h\}, p0, \[x0\]
--.*: e4a0e000 st1h \{z0\.h\}, p0, \[x0\]
--.*: e4a0e000 st1h \{z0\.h\}, p0, \[x0\]
--.*: e4a0e001 st1h \{z1\.h\}, p0, \[x0\]
--.*: e4a0e001 st1h \{z1\.h\}, p0, \[x0\]
--.*: e4a0e001 st1h \{z1\.h\}, p0, \[x0\]
--.*: e4a0e001 st1h \{z1\.h\}, p0, \[x0\]
--.*: e4a0e001 st1h \{z1\.h\}, p0, \[x0\]
--.*: e4a0e01f st1h \{z31\.h\}, p0, \[x0\]
--.*: e4a0e01f st1h \{z31\.h\}, p0, \[x0\]
--.*: e4a0e01f st1h \{z31\.h\}, p0, \[x0\]
--.*: e4a0e01f st1h \{z31\.h\}, p0, \[x0\]
--.*: e4a0e01f st1h \{z31\.h\}, p0, \[x0\]
--.*: e4a0e800 st1h \{z0\.h\}, p2, \[x0\]
--.*: e4a0e800 st1h \{z0\.h\}, p2, \[x0\]
--.*: e4a0e800 st1h \{z0\.h\}, p2, \[x0\]
--.*: e4a0e800 st1h \{z0\.h\}, p2, \[x0\]
--.*: e4a0fc00 st1h \{z0\.h\}, p7, \[x0\]
--.*: e4a0fc00 st1h \{z0\.h\}, p7, \[x0\]
--.*: e4a0fc00 st1h \{z0\.h\}, p7, \[x0\]
--.*: e4a0fc00 st1h \{z0\.h\}, p7, \[x0\]
--.*: e4a0e060 st1h \{z0\.h\}, p0, \[x3\]
--.*: e4a0e060 st1h \{z0\.h\}, p0, \[x3\]
--.*: e4a0e060 st1h \{z0\.h\}, p0, \[x3\]
--.*: e4a0e060 st1h \{z0\.h\}, p0, \[x3\]
--.*: e4a0e3e0 st1h \{z0\.h\}, p0, \[sp\]
--.*: e4a0e3e0 st1h \{z0\.h\}, p0, \[sp\]
--.*: e4a0e3e0 st1h \{z0\.h\}, p0, \[sp\]
--.*: e4a0e3e0 st1h \{z0\.h\}, p0, \[sp\]
--.*: e4a7e000 st1h \{z0\.h\}, p0, \[x0, #7, mul vl\]
--.*: e4a7e000 st1h \{z0\.h\}, p0, \[x0, #7, mul vl\]
--.*: e4a8e000 st1h \{z0\.h\}, p0, \[x0, #-8, mul vl\]
--.*: e4a8e000 st1h \{z0\.h\}, p0, \[x0, #-8, mul vl\]
--.*: e4a9e000 st1h \{z0\.h\}, p0, \[x0, #-7, mul vl\]
--.*: e4a9e000 st1h \{z0\.h\}, p0, \[x0, #-7, mul vl\]
--.*: e4afe000 st1h \{z0\.h\}, p0, \[x0, #-1, mul vl\]
--.*: e4afe000 st1h \{z0\.h\}, p0, \[x0, #-1, mul vl\]
--.*: e4c0a000 st1h \{z0\.d\}, p0, \[z0\.d\]
--.*: e4c0a000 st1h \{z0\.d\}, p0, \[z0\.d\]
--.*: e4c0a000 st1h \{z0\.d\}, p0, \[z0\.d\]
--.*: e4c0a000 st1h \{z0\.d\}, p0, \[z0\.d\]
--.*: e4c0a001 st1h \{z1\.d\}, p0, \[z0\.d\]
--.*: e4c0a001 st1h \{z1\.d\}, p0, \[z0\.d\]
--.*: e4c0a001 st1h \{z1\.d\}, p0, \[z0\.d\]
--.*: e4c0a001 st1h \{z1\.d\}, p0, \[z0\.d\]
--.*: e4c0a01f st1h \{z31\.d\}, p0, \[z0\.d\]
--.*: e4c0a01f st1h \{z31\.d\}, p0, \[z0\.d\]
--.*: e4c0a01f st1h \{z31\.d\}, p0, \[z0\.d\]
--.*: e4c0a01f st1h \{z31\.d\}, p0, \[z0\.d\]
--.*: e4c0a800 st1h \{z0\.d\}, p2, \[z0\.d\]
--.*: e4c0a800 st1h \{z0\.d\}, p2, \[z0\.d\]
--.*: e4c0a800 st1h \{z0\.d\}, p2, \[z0\.d\]
--.*: e4c0bc00 st1h \{z0\.d\}, p7, \[z0\.d\]
--.*: e4c0bc00 st1h \{z0\.d\}, p7, \[z0\.d\]
--.*: e4c0bc00 st1h \{z0\.d\}, p7, \[z0\.d\]
--.*: e4c0a060 st1h \{z0\.d\}, p0, \[z3\.d\]
--.*: e4c0a060 st1h \{z0\.d\}, p0, \[z3\.d\]
--.*: e4c0a060 st1h \{z0\.d\}, p0, \[z3\.d\]
--.*: e4c0a3e0 st1h \{z0\.d\}, p0, \[z31\.d\]
--.*: e4c0a3e0 st1h \{z0\.d\}, p0, \[z31\.d\]
--.*: e4c0a3e0 st1h \{z0\.d\}, p0, \[z31\.d\]
--.*: e4cfa000 st1h \{z0\.d\}, p0, \[z0\.d, #30\]
--.*: e4cfa000 st1h \{z0\.d\}, p0, \[z0\.d, #30\]
--.*: e4d0a000 st1h \{z0\.d\}, p0, \[z0\.d, #32\]
--.*: e4d0a000 st1h \{z0\.d\}, p0, \[z0\.d, #32\]
--.*: e4d1a000 st1h \{z0\.d\}, p0, \[z0\.d, #34\]
--.*: e4d1a000 st1h \{z0\.d\}, p0, \[z0\.d, #34\]
--.*: e4dfa000 st1h \{z0\.d\}, p0, \[z0\.d, #62\]
--.*: e4dfa000 st1h \{z0\.d\}, p0, \[z0\.d, #62\]
--.*: e4c0e000 st1h \{z0\.s\}, p0, \[x0\]
--.*: e4c0e000 st1h \{z0\.s\}, p0, \[x0\]
--.*: e4c0e000 st1h \{z0\.s\}, p0, \[x0\]
--.*: e4c0e000 st1h \{z0\.s\}, p0, \[x0\]
--.*: e4c0e000 st1h \{z0\.s\}, p0, \[x0\]
--.*: e4c0e001 st1h \{z1\.s\}, p0, \[x0\]
--.*: e4c0e001 st1h \{z1\.s\}, p0, \[x0\]
--.*: e4c0e001 st1h \{z1\.s\}, p0, \[x0\]
--.*: e4c0e001 st1h \{z1\.s\}, p0, \[x0\]
--.*: e4c0e001 st1h \{z1\.s\}, p0, \[x0\]
--.*: e4c0e01f st1h \{z31\.s\}, p0, \[x0\]
--.*: e4c0e01f st1h \{z31\.s\}, p0, \[x0\]
--.*: e4c0e01f st1h \{z31\.s\}, p0, \[x0\]
--.*: e4c0e01f st1h \{z31\.s\}, p0, \[x0\]
--.*: e4c0e01f st1h \{z31\.s\}, p0, \[x0\]
--.*: e4c0e800 st1h \{z0\.s\}, p2, \[x0\]
--.*: e4c0e800 st1h \{z0\.s\}, p2, \[x0\]
--.*: e4c0e800 st1h \{z0\.s\}, p2, \[x0\]
--.*: e4c0e800 st1h \{z0\.s\}, p2, \[x0\]
--.*: e4c0fc00 st1h \{z0\.s\}, p7, \[x0\]
--.*: e4c0fc00 st1h \{z0\.s\}, p7, \[x0\]
--.*: e4c0fc00 st1h \{z0\.s\}, p7, \[x0\]
--.*: e4c0fc00 st1h \{z0\.s\}, p7, \[x0\]
--.*: e4c0e060 st1h \{z0\.s\}, p0, \[x3\]
--.*: e4c0e060 st1h \{z0\.s\}, p0, \[x3\]
--.*: e4c0e060 st1h \{z0\.s\}, p0, \[x3\]
--.*: e4c0e060 st1h \{z0\.s\}, p0, \[x3\]
--.*: e4c0e3e0 st1h \{z0\.s\}, p0, \[sp\]
--.*: e4c0e3e0 st1h \{z0\.s\}, p0, \[sp\]
--.*: e4c0e3e0 st1h \{z0\.s\}, p0, \[sp\]
--.*: e4c0e3e0 st1h \{z0\.s\}, p0, \[sp\]
--.*: e4c7e000 st1h \{z0\.s\}, p0, \[x0, #7, mul vl\]
--.*: e4c7e000 st1h \{z0\.s\}, p0, \[x0, #7, mul vl\]
--.*: e4c8e000 st1h \{z0\.s\}, p0, \[x0, #-8, mul vl\]
--.*: e4c8e000 st1h \{z0\.s\}, p0, \[x0, #-8, mul vl\]
--.*: e4c9e000 st1h \{z0\.s\}, p0, \[x0, #-7, mul vl\]
--.*: e4c9e000 st1h \{z0\.s\}, p0, \[x0, #-7, mul vl\]
--.*: e4cfe000 st1h \{z0\.s\}, p0, \[x0, #-1, mul vl\]
--.*: e4cfe000 st1h \{z0\.s\}, p0, \[x0, #-1, mul vl\]
--.*: e4e0a000 st1h \{z0\.s\}, p0, \[z0\.s\]
--.*: e4e0a000 st1h \{z0\.s\}, p0, \[z0\.s\]
--.*: e4e0a000 st1h \{z0\.s\}, p0, \[z0\.s\]
--.*: e4e0a000 st1h \{z0\.s\}, p0, \[z0\.s\]
--.*: e4e0a001 st1h \{z1\.s\}, p0, \[z0\.s\]
--.*: e4e0a001 st1h \{z1\.s\}, p0, \[z0\.s\]
--.*: e4e0a001 st1h \{z1\.s\}, p0, \[z0\.s\]
--.*: e4e0a001 st1h \{z1\.s\}, p0, \[z0\.s\]
--.*: e4e0a01f st1h \{z31\.s\}, p0, \[z0\.s\]
--.*: e4e0a01f st1h \{z31\.s\}, p0, \[z0\.s\]
--.*: e4e0a01f st1h \{z31\.s\}, p0, \[z0\.s\]
--.*: e4e0a01f st1h \{z31\.s\}, p0, \[z0\.s\]
--.*: e4e0a800 st1h \{z0\.s\}, p2, \[z0\.s\]
--.*: e4e0a800 st1h \{z0\.s\}, p2, \[z0\.s\]
--.*: e4e0a800 st1h \{z0\.s\}, p2, \[z0\.s\]
--.*: e4e0bc00 st1h \{z0\.s\}, p7, \[z0\.s\]
--.*: e4e0bc00 st1h \{z0\.s\}, p7, \[z0\.s\]
--.*: e4e0bc00 st1h \{z0\.s\}, p7, \[z0\.s\]
--.*: e4e0a060 st1h \{z0\.s\}, p0, \[z3\.s\]
--.*: e4e0a060 st1h \{z0\.s\}, p0, \[z3\.s\]
--.*: e4e0a060 st1h \{z0\.s\}, p0, \[z3\.s\]
--.*: e4e0a3e0 st1h \{z0\.s\}, p0, \[z31\.s\]
--.*: e4e0a3e0 st1h \{z0\.s\}, p0, \[z31\.s\]
--.*: e4e0a3e0 st1h \{z0\.s\}, p0, \[z31\.s\]
--.*: e4efa000 st1h \{z0\.s\}, p0, \[z0\.s, #30\]
--.*: e4efa000 st1h \{z0\.s\}, p0, \[z0\.s, #30\]
--.*: e4f0a000 st1h \{z0\.s\}, p0, \[z0\.s, #32\]
--.*: e4f0a000 st1h \{z0\.s\}, p0, \[z0\.s, #32\]
--.*: e4f1a000 st1h \{z0\.s\}, p0, \[z0\.s, #34\]
--.*: e4f1a000 st1h \{z0\.s\}, p0, \[z0\.s, #34\]
--.*: e4ffa000 st1h \{z0\.s\}, p0, \[z0\.s, #62\]
--.*: e4ffa000 st1h \{z0\.s\}, p0, \[z0\.s, #62\]
--.*: e4e0e000 st1h \{z0\.d\}, p0, \[x0\]
--.*: e4e0e000 st1h \{z0\.d\}, p0, \[x0\]
--.*: e4e0e000 st1h \{z0\.d\}, p0, \[x0\]
--.*: e4e0e000 st1h \{z0\.d\}, p0, \[x0\]
--.*: e4e0e000 st1h \{z0\.d\}, p0, \[x0\]
--.*: e4e0e001 st1h \{z1\.d\}, p0, \[x0\]
--.*: e4e0e001 st1h \{z1\.d\}, p0, \[x0\]
--.*: e4e0e001 st1h \{z1\.d\}, p0, \[x0\]
--.*: e4e0e001 st1h \{z1\.d\}, p0, \[x0\]
--.*: e4e0e001 st1h \{z1\.d\}, p0, \[x0\]
--.*: e4e0e01f st1h \{z31\.d\}, p0, \[x0\]
--.*: e4e0e01f st1h \{z31\.d\}, p0, \[x0\]
--.*: e4e0e01f st1h \{z31\.d\}, p0, \[x0\]
--.*: e4e0e01f st1h \{z31\.d\}, p0, \[x0\]
--.*: e4e0e01f st1h \{z31\.d\}, p0, \[x0\]
--.*: e4e0e800 st1h \{z0\.d\}, p2, \[x0\]
--.*: e4e0e800 st1h \{z0\.d\}, p2, \[x0\]
--.*: e4e0e800 st1h \{z0\.d\}, p2, \[x0\]
--.*: e4e0e800 st1h \{z0\.d\}, p2, \[x0\]
--.*: e4e0fc00 st1h \{z0\.d\}, p7, \[x0\]
--.*: e4e0fc00 st1h \{z0\.d\}, p7, \[x0\]
--.*: e4e0fc00 st1h \{z0\.d\}, p7, \[x0\]
--.*: e4e0fc00 st1h \{z0\.d\}, p7, \[x0\]
--.*: e4e0e060 st1h \{z0\.d\}, p0, \[x3\]
--.*: e4e0e060 st1h \{z0\.d\}, p0, \[x3\]
--.*: e4e0e060 st1h \{z0\.d\}, p0, \[x3\]
--.*: e4e0e060 st1h \{z0\.d\}, p0, \[x3\]
--.*: e4e0e3e0 st1h \{z0\.d\}, p0, \[sp\]
--.*: e4e0e3e0 st1h \{z0\.d\}, p0, \[sp\]
--.*: e4e0e3e0 st1h \{z0\.d\}, p0, \[sp\]
--.*: e4e0e3e0 st1h \{z0\.d\}, p0, \[sp\]
--.*: e4e7e000 st1h \{z0\.d\}, p0, \[x0, #7, mul vl\]
--.*: e4e7e000 st1h \{z0\.d\}, p0, \[x0, #7, mul vl\]
--.*: e4e8e000 st1h \{z0\.d\}, p0, \[x0, #-8, mul vl\]
--.*: e4e8e000 st1h \{z0\.d\}, p0, \[x0, #-8, mul vl\]
--.*: e4e9e000 st1h \{z0\.d\}, p0, \[x0, #-7, mul vl\]
--.*: e4e9e000 st1h \{z0\.d\}, p0, \[x0, #-7, mul vl\]
--.*: e4efe000 st1h \{z0\.d\}, p0, \[x0, #-1, mul vl\]
--.*: e4efe000 st1h \{z0\.d\}, p0, \[x0, #-1, mul vl\]
--.*: e5008000 st1w \{z0\.d\}, p0, \[x0, z0\.d, uxtw\]
--.*: e5008000 st1w \{z0\.d\}, p0, \[x0, z0\.d, uxtw\]
--.*: e5008000 st1w \{z0\.d\}, p0, \[x0, z0\.d, uxtw\]
--.*: e5008000 st1w \{z0\.d\}, p0, \[x0, z0\.d, uxtw\]
--.*: e5008001 st1w \{z1\.d\}, p0, \[x0, z0\.d, uxtw\]
--.*: e5008001 st1w \{z1\.d\}, p0, \[x0, z0\.d, uxtw\]
--.*: e5008001 st1w \{z1\.d\}, p0, \[x0, z0\.d, uxtw\]
--.*: e5008001 st1w \{z1\.d\}, p0, \[x0, z0\.d, uxtw\]
--.*: e500801f st1w \{z31\.d\}, p0, \[x0, z0\.d, uxtw\]
--.*: e500801f st1w \{z31\.d\}, p0, \[x0, z0\.d, uxtw\]
--.*: e500801f st1w \{z31\.d\}, p0, \[x0, z0\.d, uxtw\]
--.*: e500801f st1w \{z31\.d\}, p0, \[x0, z0\.d, uxtw\]
--.*: e5008800 st1w \{z0\.d\}, p2, \[x0, z0\.d, uxtw\]
--.*: e5008800 st1w \{z0\.d\}, p2, \[x0, z0\.d, uxtw\]
--.*: e5008800 st1w \{z0\.d\}, p2, \[x0, z0\.d, uxtw\]
--.*: e5009c00 st1w \{z0\.d\}, p7, \[x0, z0\.d, uxtw\]
--.*: e5009c00 st1w \{z0\.d\}, p7, \[x0, z0\.d, uxtw\]
--.*: e5009c00 st1w \{z0\.d\}, p7, \[x0, z0\.d, uxtw\]
--.*: e5008060 st1w \{z0\.d\}, p0, \[x3, z0\.d, uxtw\]
--.*: e5008060 st1w \{z0\.d\}, p0, \[x3, z0\.d, uxtw\]
--.*: e5008060 st1w \{z0\.d\}, p0, \[x3, z0\.d, uxtw\]
--.*: e50083e0 st1w \{z0\.d\}, p0, \[sp, z0\.d, uxtw\]
--.*: e50083e0 st1w \{z0\.d\}, p0, \[sp, z0\.d, uxtw\]
--.*: e50083e0 st1w \{z0\.d\}, p0, \[sp, z0\.d, uxtw\]
--.*: e5048000 st1w \{z0\.d\}, p0, \[x0, z4\.d, uxtw\]
--.*: e5048000 st1w \{z0\.d\}, p0, \[x0, z4\.d, uxtw\]
--.*: e5048000 st1w \{z0\.d\}, p0, \[x0, z4\.d, uxtw\]
--.*: e51f8000 st1w \{z0\.d\}, p0, \[x0, z31\.d, uxtw\]
--.*: e51f8000 st1w \{z0\.d\}, p0, \[x0, z31\.d, uxtw\]
--.*: e51f8000 st1w \{z0\.d\}, p0, \[x0, z31\.d, uxtw\]
--.*: e500c000 st1w \{z0\.d\}, p0, \[x0, z0\.d, sxtw\]
--.*: e500c000 st1w \{z0\.d\}, p0, \[x0, z0\.d, sxtw\]
--.*: e500c000 st1w \{z0\.d\}, p0, \[x0, z0\.d, sxtw\]
--.*: e500c000 st1w \{z0\.d\}, p0, \[x0, z0\.d, sxtw\]
--.*: e500c001 st1w \{z1\.d\}, p0, \[x0, z0\.d, sxtw\]
--.*: e500c001 st1w \{z1\.d\}, p0, \[x0, z0\.d, sxtw\]
--.*: e500c001 st1w \{z1\.d\}, p0, \[x0, z0\.d, sxtw\]
--.*: e500c001 st1w \{z1\.d\}, p0, \[x0, z0\.d, sxtw\]
--.*: e500c01f st1w \{z31\.d\}, p0, \[x0, z0\.d, sxtw\]
--.*: e500c01f st1w \{z31\.d\}, p0, \[x0, z0\.d, sxtw\]
--.*: e500c01f st1w \{z31\.d\}, p0, \[x0, z0\.d, sxtw\]
--.*: e500c01f st1w \{z31\.d\}, p0, \[x0, z0\.d, sxtw\]
--.*: e500c800 st1w \{z0\.d\}, p2, \[x0, z0\.d, sxtw\]
--.*: e500c800 st1w \{z0\.d\}, p2, \[x0, z0\.d, sxtw\]
--.*: e500c800 st1w \{z0\.d\}, p2, \[x0, z0\.d, sxtw\]
--.*: e500dc00 st1w \{z0\.d\}, p7, \[x0, z0\.d, sxtw\]
--.*: e500dc00 st1w \{z0\.d\}, p7, \[x0, z0\.d, sxtw\]
--.*: e500dc00 st1w \{z0\.d\}, p7, \[x0, z0\.d, sxtw\]
--.*: e500c060 st1w \{z0\.d\}, p0, \[x3, z0\.d, sxtw\]
--.*: e500c060 st1w \{z0\.d\}, p0, \[x3, z0\.d, sxtw\]
--.*: e500c060 st1w \{z0\.d\}, p0, \[x3, z0\.d, sxtw\]
--.*: e500c3e0 st1w \{z0\.d\}, p0, \[sp, z0\.d, sxtw\]
--.*: e500c3e0 st1w \{z0\.d\}, p0, \[sp, z0\.d, sxtw\]
--.*: e500c3e0 st1w \{z0\.d\}, p0, \[sp, z0\.d, sxtw\]
--.*: e504c000 st1w \{z0\.d\}, p0, \[x0, z4\.d, sxtw\]
--.*: e504c000 st1w \{z0\.d\}, p0, \[x0, z4\.d, sxtw\]
--.*: e504c000 st1w \{z0\.d\}, p0, \[x0, z4\.d, sxtw\]
--.*: e51fc000 st1w \{z0\.d\}, p0, \[x0, z31\.d, sxtw\]
--.*: e51fc000 st1w \{z0\.d\}, p0, \[x0, z31\.d, sxtw\]
--.*: e51fc000 st1w \{z0\.d\}, p0, \[x0, z31\.d, sxtw\]
--.*: e500a000 st1w \{z0\.d\}, p0, \[x0, z0\.d\]
--.*: e500a000 st1w \{z0\.d\}, p0, \[x0, z0\.d\]
--.*: e500a000 st1w \{z0\.d\}, p0, \[x0, z0\.d\]
--.*: e500a000 st1w \{z0\.d\}, p0, \[x0, z0\.d\]
--.*: e500a001 st1w \{z1\.d\}, p0, \[x0, z0\.d\]
--.*: e500a001 st1w \{z1\.d\}, p0, \[x0, z0\.d\]
--.*: e500a001 st1w \{z1\.d\}, p0, \[x0, z0\.d\]
--.*: e500a001 st1w \{z1\.d\}, p0, \[x0, z0\.d\]
--.*: e500a01f st1w \{z31\.d\}, p0, \[x0, z0\.d\]
--.*: e500a01f st1w \{z31\.d\}, p0, \[x0, z0\.d\]
--.*: e500a01f st1w \{z31\.d\}, p0, \[x0, z0\.d\]
--.*: e500a01f st1w \{z31\.d\}, p0, \[x0, z0\.d\]
--.*: e500a800 st1w \{z0\.d\}, p2, \[x0, z0\.d\]
--.*: e500a800 st1w \{z0\.d\}, p2, \[x0, z0\.d\]
--.*: e500a800 st1w \{z0\.d\}, p2, \[x0, z0\.d\]
--.*: e500bc00 st1w \{z0\.d\}, p7, \[x0, z0\.d\]
--.*: e500bc00 st1w \{z0\.d\}, p7, \[x0, z0\.d\]
--.*: e500bc00 st1w \{z0\.d\}, p7, \[x0, z0\.d\]
--.*: e500a060 st1w \{z0\.d\}, p0, \[x3, z0\.d\]
--.*: e500a060 st1w \{z0\.d\}, p0, \[x3, z0\.d\]
--.*: e500a060 st1w \{z0\.d\}, p0, \[x3, z0\.d\]
--.*: e500a3e0 st1w \{z0\.d\}, p0, \[sp, z0\.d\]
--.*: e500a3e0 st1w \{z0\.d\}, p0, \[sp, z0\.d\]
--.*: e500a3e0 st1w \{z0\.d\}, p0, \[sp, z0\.d\]
--.*: e504a000 st1w \{z0\.d\}, p0, \[x0, z4\.d\]
--.*: e504a000 st1w \{z0\.d\}, p0, \[x0, z4\.d\]
--.*: e504a000 st1w \{z0\.d\}, p0, \[x0, z4\.d\]
--.*: e51fa000 st1w \{z0\.d\}, p0, \[x0, z31\.d\]
--.*: e51fa000 st1w \{z0\.d\}, p0, \[x0, z31\.d\]
--.*: e51fa000 st1w \{z0\.d\}, p0, \[x0, z31\.d\]
--.*: e5208000 st1w \{z0\.d\}, p0, \[x0, z0\.d, uxtw #2\]
--.*: e5208000 st1w \{z0\.d\}, p0, \[x0, z0\.d, uxtw #2\]
--.*: e5208000 st1w \{z0\.d\}, p0, \[x0, z0\.d, uxtw #2\]
--.*: e5208001 st1w \{z1\.d\}, p0, \[x0, z0\.d, uxtw #2\]
--.*: e5208001 st1w \{z1\.d\}, p0, \[x0, z0\.d, uxtw #2\]
--.*: e5208001 st1w \{z1\.d\}, p0, \[x0, z0\.d, uxtw #2\]
--.*: e520801f st1w \{z31\.d\}, p0, \[x0, z0\.d, uxtw #2\]
--.*: e520801f st1w \{z31\.d\}, p0, \[x0, z0\.d, uxtw #2\]
--.*: e520801f st1w \{z31\.d\}, p0, \[x0, z0\.d, uxtw #2\]
--.*: e5208800 st1w \{z0\.d\}, p2, \[x0, z0\.d, uxtw #2\]
--.*: e5208800 st1w \{z0\.d\}, p2, \[x0, z0\.d, uxtw #2\]
--.*: e5209c00 st1w \{z0\.d\}, p7, \[x0, z0\.d, uxtw #2\]
--.*: e5209c00 st1w \{z0\.d\}, p7, \[x0, z0\.d, uxtw #2\]
--.*: e5208060 st1w \{z0\.d\}, p0, \[x3, z0\.d, uxtw #2\]
--.*: e5208060 st1w \{z0\.d\}, p0, \[x3, z0\.d, uxtw #2\]
--.*: e52083e0 st1w \{z0\.d\}, p0, \[sp, z0\.d, uxtw #2\]
--.*: e52083e0 st1w \{z0\.d\}, p0, \[sp, z0\.d, uxtw #2\]
--.*: e5248000 st1w \{z0\.d\}, p0, \[x0, z4\.d, uxtw #2\]
--.*: e5248000 st1w \{z0\.d\}, p0, \[x0, z4\.d, uxtw #2\]
--.*: e53f8000 st1w \{z0\.d\}, p0, \[x0, z31\.d, uxtw #2\]
--.*: e53f8000 st1w \{z0\.d\}, p0, \[x0, z31\.d, uxtw #2\]
--.*: e520c000 st1w \{z0\.d\}, p0, \[x0, z0\.d, sxtw #2\]
--.*: e520c000 st1w \{z0\.d\}, p0, \[x0, z0\.d, sxtw #2\]
--.*: e520c000 st1w \{z0\.d\}, p0, \[x0, z0\.d, sxtw #2\]
--.*: e520c001 st1w \{z1\.d\}, p0, \[x0, z0\.d, sxtw #2\]
--.*: e520c001 st1w \{z1\.d\}, p0, \[x0, z0\.d, sxtw #2\]
--.*: e520c001 st1w \{z1\.d\}, p0, \[x0, z0\.d, sxtw #2\]
--.*: e520c01f st1w \{z31\.d\}, p0, \[x0, z0\.d, sxtw #2\]
--.*: e520c01f st1w \{z31\.d\}, p0, \[x0, z0\.d, sxtw #2\]
--.*: e520c01f st1w \{z31\.d\}, p0, \[x0, z0\.d, sxtw #2\]
--.*: e520c800 st1w \{z0\.d\}, p2, \[x0, z0\.d, sxtw #2\]
--.*: e520c800 st1w \{z0\.d\}, p2, \[x0, z0\.d, sxtw #2\]
--.*: e520dc00 st1w \{z0\.d\}, p7, \[x0, z0\.d, sxtw #2\]
--.*: e520dc00 st1w \{z0\.d\}, p7, \[x0, z0\.d, sxtw #2\]
--.*: e520c060 st1w \{z0\.d\}, p0, \[x3, z0\.d, sxtw #2\]
--.*: e520c060 st1w \{z0\.d\}, p0, \[x3, z0\.d, sxtw #2\]
--.*: e520c3e0 st1w \{z0\.d\}, p0, \[sp, z0\.d, sxtw #2\]
--.*: e520c3e0 st1w \{z0\.d\}, p0, \[sp, z0\.d, sxtw #2\]
--.*: e524c000 st1w \{z0\.d\}, p0, \[x0, z4\.d, sxtw #2\]
--.*: e524c000 st1w \{z0\.d\}, p0, \[x0, z4\.d, sxtw #2\]
--.*: e53fc000 st1w \{z0\.d\}, p0, \[x0, z31\.d, sxtw #2\]
--.*: e53fc000 st1w \{z0\.d\}, p0, \[x0, z31\.d, sxtw #2\]
--.*: e520a000 st1w \{z0\.d\}, p0, \[x0, z0\.d, lsl #2\]
--.*: e520a000 st1w \{z0\.d\}, p0, \[x0, z0\.d, lsl #2\]
--.*: e520a000 st1w \{z0\.d\}, p0, \[x0, z0\.d, lsl #2\]
--.*: e520a001 st1w \{z1\.d\}, p0, \[x0, z0\.d, lsl #2\]
--.*: e520a001 st1w \{z1\.d\}, p0, \[x0, z0\.d, lsl #2\]
--.*: e520a001 st1w \{z1\.d\}, p0, \[x0, z0\.d, lsl #2\]
--.*: e520a01f st1w \{z31\.d\}, p0, \[x0, z0\.d, lsl #2\]
--.*: e520a01f st1w \{z31\.d\}, p0, \[x0, z0\.d, lsl #2\]
--.*: e520a01f st1w \{z31\.d\}, p0, \[x0, z0\.d, lsl #2\]
--.*: e520a800 st1w \{z0\.d\}, p2, \[x0, z0\.d, lsl #2\]
--.*: e520a800 st1w \{z0\.d\}, p2, \[x0, z0\.d, lsl #2\]
--.*: e520bc00 st1w \{z0\.d\}, p7, \[x0, z0\.d, lsl #2\]
--.*: e520bc00 st1w \{z0\.d\}, p7, \[x0, z0\.d, lsl #2\]
--.*: e520a060 st1w \{z0\.d\}, p0, \[x3, z0\.d, lsl #2\]
--.*: e520a060 st1w \{z0\.d\}, p0, \[x3, z0\.d, lsl #2\]
--.*: e520a3e0 st1w \{z0\.d\}, p0, \[sp, z0\.d, lsl #2\]
--.*: e520a3e0 st1w \{z0\.d\}, p0, \[sp, z0\.d, lsl #2\]
--.*: e524a000 st1w \{z0\.d\}, p0, \[x0, z4\.d, lsl #2\]
--.*: e524a000 st1w \{z0\.d\}, p0, \[x0, z4\.d, lsl #2\]
--.*: e53fa000 st1w \{z0\.d\}, p0, \[x0, z31\.d, lsl #2\]
--.*: e53fa000 st1w \{z0\.d\}, p0, \[x0, z31\.d, lsl #2\]
--.*: e5404000 st1w \{z0\.s\}, p0, \[x0, x0, lsl #2\]
--.*: e5404000 st1w \{z0\.s\}, p0, \[x0, x0, lsl #2\]
--.*: e5404000 st1w \{z0\.s\}, p0, \[x0, x0, lsl #2\]
--.*: e5404001 st1w \{z1\.s\}, p0, \[x0, x0, lsl #2\]
--.*: e5404001 st1w \{z1\.s\}, p0, \[x0, x0, lsl #2\]
--.*: e5404001 st1w \{z1\.s\}, p0, \[x0, x0, lsl #2\]
--.*: e540401f st1w \{z31\.s\}, p0, \[x0, x0, lsl #2\]
--.*: e540401f st1w \{z31\.s\}, p0, \[x0, x0, lsl #2\]
--.*: e540401f st1w \{z31\.s\}, p0, \[x0, x0, lsl #2\]
--.*: e5404800 st1w \{z0\.s\}, p2, \[x0, x0, lsl #2\]
--.*: e5404800 st1w \{z0\.s\}, p2, \[x0, x0, lsl #2\]
--.*: e5405c00 st1w \{z0\.s\}, p7, \[x0, x0, lsl #2\]
--.*: e5405c00 st1w \{z0\.s\}, p7, \[x0, x0, lsl #2\]
--.*: e5404060 st1w \{z0\.s\}, p0, \[x3, x0, lsl #2\]
--.*: e5404060 st1w \{z0\.s\}, p0, \[x3, x0, lsl #2\]
--.*: e54043e0 st1w \{z0\.s\}, p0, \[sp, x0, lsl #2\]
--.*: e54043e0 st1w \{z0\.s\}, p0, \[sp, x0, lsl #2\]
--.*: e5444000 st1w \{z0\.s\}, p0, \[x0, x4, lsl #2\]
--.*: e5444000 st1w \{z0\.s\}, p0, \[x0, x4, lsl #2\]
--.*: e55e4000 st1w \{z0\.s\}, p0, \[x0, x30, lsl #2\]
--.*: e55e4000 st1w \{z0\.s\}, p0, \[x0, x30, lsl #2\]
--.*: e5408000 st1w \{z0\.s\}, p0, \[x0, z0\.s, uxtw\]
--.*: e5408000 st1w \{z0\.s\}, p0, \[x0, z0\.s, uxtw\]
--.*: e5408000 st1w \{z0\.s\}, p0, \[x0, z0\.s, uxtw\]
--.*: e5408000 st1w \{z0\.s\}, p0, \[x0, z0\.s, uxtw\]
--.*: e5408001 st1w \{z1\.s\}, p0, \[x0, z0\.s, uxtw\]
--.*: e5408001 st1w \{z1\.s\}, p0, \[x0, z0\.s, uxtw\]
--.*: e5408001 st1w \{z1\.s\}, p0, \[x0, z0\.s, uxtw\]
--.*: e5408001 st1w \{z1\.s\}, p0, \[x0, z0\.s, uxtw\]
--.*: e540801f st1w \{z31\.s\}, p0, \[x0, z0\.s, uxtw\]
--.*: e540801f st1w \{z31\.s\}, p0, \[x0, z0\.s, uxtw\]
--.*: e540801f st1w \{z31\.s\}, p0, \[x0, z0\.s, uxtw\]
--.*: e540801f st1w \{z31\.s\}, p0, \[x0, z0\.s, uxtw\]
--.*: e5408800 st1w \{z0\.s\}, p2, \[x0, z0\.s, uxtw\]
--.*: e5408800 st1w \{z0\.s\}, p2, \[x0, z0\.s, uxtw\]
--.*: e5408800 st1w \{z0\.s\}, p2, \[x0, z0\.s, uxtw\]
--.*: e5409c00 st1w \{z0\.s\}, p7, \[x0, z0\.s, uxtw\]
--.*: e5409c00 st1w \{z0\.s\}, p7, \[x0, z0\.s, uxtw\]
--.*: e5409c00 st1w \{z0\.s\}, p7, \[x0, z0\.s, uxtw\]
--.*: e5408060 st1w \{z0\.s\}, p0, \[x3, z0\.s, uxtw\]
--.*: e5408060 st1w \{z0\.s\}, p0, \[x3, z0\.s, uxtw\]
--.*: e5408060 st1w \{z0\.s\}, p0, \[x3, z0\.s, uxtw\]
--.*: e54083e0 st1w \{z0\.s\}, p0, \[sp, z0\.s, uxtw\]
--.*: e54083e0 st1w \{z0\.s\}, p0, \[sp, z0\.s, uxtw\]
--.*: e54083e0 st1w \{z0\.s\}, p0, \[sp, z0\.s, uxtw\]
--.*: e5448000 st1w \{z0\.s\}, p0, \[x0, z4\.s, uxtw\]
--.*: e5448000 st1w \{z0\.s\}, p0, \[x0, z4\.s, uxtw\]
--.*: e5448000 st1w \{z0\.s\}, p0, \[x0, z4\.s, uxtw\]
--.*: e55f8000 st1w \{z0\.s\}, p0, \[x0, z31\.s, uxtw\]
--.*: e55f8000 st1w \{z0\.s\}, p0, \[x0, z31\.s, uxtw\]
--.*: e55f8000 st1w \{z0\.s\}, p0, \[x0, z31\.s, uxtw\]
--.*: e540c000 st1w \{z0\.s\}, p0, \[x0, z0\.s, sxtw\]
--.*: e540c000 st1w \{z0\.s\}, p0, \[x0, z0\.s, sxtw\]
--.*: e540c000 st1w \{z0\.s\}, p0, \[x0, z0\.s, sxtw\]
--.*: e540c000 st1w \{z0\.s\}, p0, \[x0, z0\.s, sxtw\]
--.*: e540c001 st1w \{z1\.s\}, p0, \[x0, z0\.s, sxtw\]
--.*: e540c001 st1w \{z1\.s\}, p0, \[x0, z0\.s, sxtw\]
--.*: e540c001 st1w \{z1\.s\}, p0, \[x0, z0\.s, sxtw\]
--.*: e540c001 st1w \{z1\.s\}, p0, \[x0, z0\.s, sxtw\]
--.*: e540c01f st1w \{z31\.s\}, p0, \[x0, z0\.s, sxtw\]
--.*: e540c01f st1w \{z31\.s\}, p0, \[x0, z0\.s, sxtw\]
--.*: e540c01f st1w \{z31\.s\}, p0, \[x0, z0\.s, sxtw\]
--.*: e540c01f st1w \{z31\.s\}, p0, \[x0, z0\.s, sxtw\]
--.*: e540c800 st1w \{z0\.s\}, p2, \[x0, z0\.s, sxtw\]
--.*: e540c800 st1w \{z0\.s\}, p2, \[x0, z0\.s, sxtw\]
--.*: e540c800 st1w \{z0\.s\}, p2, \[x0, z0\.s, sxtw\]
--.*: e540dc00 st1w \{z0\.s\}, p7, \[x0, z0\.s, sxtw\]
--.*: e540dc00 st1w \{z0\.s\}, p7, \[x0, z0\.s, sxtw\]
--.*: e540dc00 st1w \{z0\.s\}, p7, \[x0, z0\.s, sxtw\]
--.*: e540c060 st1w \{z0\.s\}, p0, \[x3, z0\.s, sxtw\]
--.*: e540c060 st1w \{z0\.s\}, p0, \[x3, z0\.s, sxtw\]
--.*: e540c060 st1w \{z0\.s\}, p0, \[x3, z0\.s, sxtw\]
--.*: e540c3e0 st1w \{z0\.s\}, p0, \[sp, z0\.s, sxtw\]
--.*: e540c3e0 st1w \{z0\.s\}, p0, \[sp, z0\.s, sxtw\]
--.*: e540c3e0 st1w \{z0\.s\}, p0, \[sp, z0\.s, sxtw\]
--.*: e544c000 st1w \{z0\.s\}, p0, \[x0, z4\.s, sxtw\]
--.*: e544c000 st1w \{z0\.s\}, p0, \[x0, z4\.s, sxtw\]
--.*: e544c000 st1w \{z0\.s\}, p0, \[x0, z4\.s, sxtw\]
--.*: e55fc000 st1w \{z0\.s\}, p0, \[x0, z31\.s, sxtw\]
--.*: e55fc000 st1w \{z0\.s\}, p0, \[x0, z31\.s, sxtw\]
--.*: e55fc000 st1w \{z0\.s\}, p0, \[x0, z31\.s, sxtw\]
--.*: e5604000 st1w \{z0\.d\}, p0, \[x0, x0, lsl #2\]
--.*: e5604000 st1w \{z0\.d\}, p0, \[x0, x0, lsl #2\]
--.*: e5604000 st1w \{z0\.d\}, p0, \[x0, x0, lsl #2\]
--.*: e5604001 st1w \{z1\.d\}, p0, \[x0, x0, lsl #2\]
--.*: e5604001 st1w \{z1\.d\}, p0, \[x0, x0, lsl #2\]
--.*: e5604001 st1w \{z1\.d\}, p0, \[x0, x0, lsl #2\]
--.*: e560401f st1w \{z31\.d\}, p0, \[x0, x0, lsl #2\]
--.*: e560401f st1w \{z31\.d\}, p0, \[x0, x0, lsl #2\]
--.*: e560401f st1w \{z31\.d\}, p0, \[x0, x0, lsl #2\]
--.*: e5604800 st1w \{z0\.d\}, p2, \[x0, x0, lsl #2\]
--.*: e5604800 st1w \{z0\.d\}, p2, \[x0, x0, lsl #2\]
--.*: e5605c00 st1w \{z0\.d\}, p7, \[x0, x0, lsl #2\]
--.*: e5605c00 st1w \{z0\.d\}, p7, \[x0, x0, lsl #2\]
--.*: e5604060 st1w \{z0\.d\}, p0, \[x3, x0, lsl #2\]
--.*: e5604060 st1w \{z0\.d\}, p0, \[x3, x0, lsl #2\]
--.*: e56043e0 st1w \{z0\.d\}, p0, \[sp, x0, lsl #2\]
--.*: e56043e0 st1w \{z0\.d\}, p0, \[sp, x0, lsl #2\]
--.*: e5644000 st1w \{z0\.d\}, p0, \[x0, x4, lsl #2\]
--.*: e5644000 st1w \{z0\.d\}, p0, \[x0, x4, lsl #2\]
--.*: e57e4000 st1w \{z0\.d\}, p0, \[x0, x30, lsl #2\]
--.*: e57e4000 st1w \{z0\.d\}, p0, \[x0, x30, lsl #2\]
--.*: e5608000 st1w \{z0\.s\}, p0, \[x0, z0\.s, uxtw #2\]
--.*: e5608000 st1w \{z0\.s\}, p0, \[x0, z0\.s, uxtw #2\]
--.*: e5608000 st1w \{z0\.s\}, p0, \[x0, z0\.s, uxtw #2\]
--.*: e5608001 st1w \{z1\.s\}, p0, \[x0, z0\.s, uxtw #2\]
--.*: e5608001 st1w \{z1\.s\}, p0, \[x0, z0\.s, uxtw #2\]
--.*: e5608001 st1w \{z1\.s\}, p0, \[x0, z0\.s, uxtw #2\]
--.*: e560801f st1w \{z31\.s\}, p0, \[x0, z0\.s, uxtw #2\]
--.*: e560801f st1w \{z31\.s\}, p0, \[x0, z0\.s, uxtw #2\]
--.*: e560801f st1w \{z31\.s\}, p0, \[x0, z0\.s, uxtw #2\]
--.*: e5608800 st1w \{z0\.s\}, p2, \[x0, z0\.s, uxtw #2\]
--.*: e5608800 st1w \{z0\.s\}, p2, \[x0, z0\.s, uxtw #2\]
--.*: e5609c00 st1w \{z0\.s\}, p7, \[x0, z0\.s, uxtw #2\]
--.*: e5609c00 st1w \{z0\.s\}, p7, \[x0, z0\.s, uxtw #2\]
--.*: e5608060 st1w \{z0\.s\}, p0, \[x3, z0\.s, uxtw #2\]
--.*: e5608060 st1w \{z0\.s\}, p0, \[x3, z0\.s, uxtw #2\]
--.*: e56083e0 st1w \{z0\.s\}, p0, \[sp, z0\.s, uxtw #2\]
--.*: e56083e0 st1w \{z0\.s\}, p0, \[sp, z0\.s, uxtw #2\]
--.*: e5648000 st1w \{z0\.s\}, p0, \[x0, z4\.s, uxtw #2\]
--.*: e5648000 st1w \{z0\.s\}, p0, \[x0, z4\.s, uxtw #2\]
--.*: e57f8000 st1w \{z0\.s\}, p0, \[x0, z31\.s, uxtw #2\]
--.*: e57f8000 st1w \{z0\.s\}, p0, \[x0, z31\.s, uxtw #2\]
--.*: e560c000 st1w \{z0\.s\}, p0, \[x0, z0\.s, sxtw #2\]
--.*: e560c000 st1w \{z0\.s\}, p0, \[x0, z0\.s, sxtw #2\]
--.*: e560c000 st1w \{z0\.s\}, p0, \[x0, z0\.s, sxtw #2\]
--.*: e560c001 st1w \{z1\.s\}, p0, \[x0, z0\.s, sxtw #2\]
--.*: e560c001 st1w \{z1\.s\}, p0, \[x0, z0\.s, sxtw #2\]
--.*: e560c001 st1w \{z1\.s\}, p0, \[x0, z0\.s, sxtw #2\]
--.*: e560c01f st1w \{z31\.s\}, p0, \[x0, z0\.s, sxtw #2\]
--.*: e560c01f st1w \{z31\.s\}, p0, \[x0, z0\.s, sxtw #2\]
--.*: e560c01f st1w \{z31\.s\}, p0, \[x0, z0\.s, sxtw #2\]
--.*: e560c800 st1w \{z0\.s\}, p2, \[x0, z0\.s, sxtw #2\]
--.*: e560c800 st1w \{z0\.s\}, p2, \[x0, z0\.s, sxtw #2\]
--.*: e560dc00 st1w \{z0\.s\}, p7, \[x0, z0\.s, sxtw #2\]
--.*: e560dc00 st1w \{z0\.s\}, p7, \[x0, z0\.s, sxtw #2\]
--.*: e560c060 st1w \{z0\.s\}, p0, \[x3, z0\.s, sxtw #2\]
--.*: e560c060 st1w \{z0\.s\}, p0, \[x3, z0\.s, sxtw #2\]
--.*: e560c3e0 st1w \{z0\.s\}, p0, \[sp, z0\.s, sxtw #2\]
--.*: e560c3e0 st1w \{z0\.s\}, p0, \[sp, z0\.s, sxtw #2\]
--.*: e564c000 st1w \{z0\.s\}, p0, \[x0, z4\.s, sxtw #2\]
--.*: e564c000 st1w \{z0\.s\}, p0, \[x0, z4\.s, sxtw #2\]
--.*: e57fc000 st1w \{z0\.s\}, p0, \[x0, z31\.s, sxtw #2\]
--.*: e57fc000 st1w \{z0\.s\}, p0, \[x0, z31\.s, sxtw #2\]
--.*: e540a000 st1w \{z0\.d\}, p0, \[z0\.d\]
--.*: e540a000 st1w \{z0\.d\}, p0, \[z0\.d\]
--.*: e540a000 st1w \{z0\.d\}, p0, \[z0\.d\]
--.*: e540a000 st1w \{z0\.d\}, p0, \[z0\.d\]
--.*: e540a001 st1w \{z1\.d\}, p0, \[z0\.d\]
--.*: e540a001 st1w \{z1\.d\}, p0, \[z0\.d\]
--.*: e540a001 st1w \{z1\.d\}, p0, \[z0\.d\]
--.*: e540a001 st1w \{z1\.d\}, p0, \[z0\.d\]
--.*: e540a01f st1w \{z31\.d\}, p0, \[z0\.d\]
--.*: e540a01f st1w \{z31\.d\}, p0, \[z0\.d\]
--.*: e540a01f st1w \{z31\.d\}, p0, \[z0\.d\]
--.*: e540a01f st1w \{z31\.d\}, p0, \[z0\.d\]
--.*: e540a800 st1w \{z0\.d\}, p2, \[z0\.d\]
--.*: e540a800 st1w \{z0\.d\}, p2, \[z0\.d\]
--.*: e540a800 st1w \{z0\.d\}, p2, \[z0\.d\]
--.*: e540bc00 st1w \{z0\.d\}, p7, \[z0\.d\]
--.*: e540bc00 st1w \{z0\.d\}, p7, \[z0\.d\]
--.*: e540bc00 st1w \{z0\.d\}, p7, \[z0\.d\]
--.*: e540a060 st1w \{z0\.d\}, p0, \[z3\.d\]
--.*: e540a060 st1w \{z0\.d\}, p0, \[z3\.d\]
--.*: e540a060 st1w \{z0\.d\}, p0, \[z3\.d\]
--.*: e540a3e0 st1w \{z0\.d\}, p0, \[z31\.d\]
--.*: e540a3e0 st1w \{z0\.d\}, p0, \[z31\.d\]
--.*: e540a3e0 st1w \{z0\.d\}, p0, \[z31\.d\]
--.*: e54fa000 st1w \{z0\.d\}, p0, \[z0\.d, #60\]
--.*: e54fa000 st1w \{z0\.d\}, p0, \[z0\.d, #60\]
--.*: e550a000 st1w \{z0\.d\}, p0, \[z0\.d, #64\]
--.*: e550a000 st1w \{z0\.d\}, p0, \[z0\.d, #64\]
--.*: e551a000 st1w \{z0\.d\}, p0, \[z0\.d, #68\]
--.*: e551a000 st1w \{z0\.d\}, p0, \[z0\.d, #68\]
--.*: e55fa000 st1w \{z0\.d\}, p0, \[z0\.d, #124\]
--.*: e55fa000 st1w \{z0\.d\}, p0, \[z0\.d, #124\]
--.*: e540e000 st1w \{z0\.s\}, p0, \[x0\]
--.*: e540e000 st1w \{z0\.s\}, p0, \[x0\]
--.*: e540e000 st1w \{z0\.s\}, p0, \[x0\]
--.*: e540e000 st1w \{z0\.s\}, p0, \[x0\]
--.*: e540e000 st1w \{z0\.s\}, p0, \[x0\]
--.*: e540e001 st1w \{z1\.s\}, p0, \[x0\]
--.*: e540e001 st1w \{z1\.s\}, p0, \[x0\]
--.*: e540e001 st1w \{z1\.s\}, p0, \[x0\]
--.*: e540e001 st1w \{z1\.s\}, p0, \[x0\]
--.*: e540e001 st1w \{z1\.s\}, p0, \[x0\]
--.*: e540e01f st1w \{z31\.s\}, p0, \[x0\]
--.*: e540e01f st1w \{z31\.s\}, p0, \[x0\]
--.*: e540e01f st1w \{z31\.s\}, p0, \[x0\]
--.*: e540e01f st1w \{z31\.s\}, p0, \[x0\]
--.*: e540e01f st1w \{z31\.s\}, p0, \[x0\]
--.*: e540e800 st1w \{z0\.s\}, p2, \[x0\]
--.*: e540e800 st1w \{z0\.s\}, p2, \[x0\]
--.*: e540e800 st1w \{z0\.s\}, p2, \[x0\]
--.*: e540e800 st1w \{z0\.s\}, p2, \[x0\]
--.*: e540fc00 st1w \{z0\.s\}, p7, \[x0\]
--.*: e540fc00 st1w \{z0\.s\}, p7, \[x0\]
--.*: e540fc00 st1w \{z0\.s\}, p7, \[x0\]
--.*: e540fc00 st1w \{z0\.s\}, p7, \[x0\]
--.*: e540e060 st1w \{z0\.s\}, p0, \[x3\]
--.*: e540e060 st1w \{z0\.s\}, p0, \[x3\]
--.*: e540e060 st1w \{z0\.s\}, p0, \[x3\]
--.*: e540e060 st1w \{z0\.s\}, p0, \[x3\]
--.*: e540e3e0 st1w \{z0\.s\}, p0, \[sp\]
--.*: e540e3e0 st1w \{z0\.s\}, p0, \[sp\]
--.*: e540e3e0 st1w \{z0\.s\}, p0, \[sp\]
--.*: e540e3e0 st1w \{z0\.s\}, p0, \[sp\]
--.*: e547e000 st1w \{z0\.s\}, p0, \[x0, #7, mul vl\]
--.*: e547e000 st1w \{z0\.s\}, p0, \[x0, #7, mul vl\]
--.*: e548e000 st1w \{z0\.s\}, p0, \[x0, #-8, mul vl\]
--.*: e548e000 st1w \{z0\.s\}, p0, \[x0, #-8, mul vl\]
--.*: e549e000 st1w \{z0\.s\}, p0, \[x0, #-7, mul vl\]
--.*: e549e000 st1w \{z0\.s\}, p0, \[x0, #-7, mul vl\]
--.*: e54fe000 st1w \{z0\.s\}, p0, \[x0, #-1, mul vl\]
--.*: e54fe000 st1w \{z0\.s\}, p0, \[x0, #-1, mul vl\]
--.*: e560a000 st1w \{z0\.s\}, p0, \[z0\.s\]
--.*: e560a000 st1w \{z0\.s\}, p0, \[z0\.s\]
--.*: e560a000 st1w \{z0\.s\}, p0, \[z0\.s\]
--.*: e560a000 st1w \{z0\.s\}, p0, \[z0\.s\]
--.*: e560a001 st1w \{z1\.s\}, p0, \[z0\.s\]
--.*: e560a001 st1w \{z1\.s\}, p0, \[z0\.s\]
--.*: e560a001 st1w \{z1\.s\}, p0, \[z0\.s\]
--.*: e560a001 st1w \{z1\.s\}, p0, \[z0\.s\]
--.*: e560a01f st1w \{z31\.s\}, p0, \[z0\.s\]
--.*: e560a01f st1w \{z31\.s\}, p0, \[z0\.s\]
--.*: e560a01f st1w \{z31\.s\}, p0, \[z0\.s\]
--.*: e560a01f st1w \{z31\.s\}, p0, \[z0\.s\]
--.*: e560a800 st1w \{z0\.s\}, p2, \[z0\.s\]
--.*: e560a800 st1w \{z0\.s\}, p2, \[z0\.s\]
--.*: e560a800 st1w \{z0\.s\}, p2, \[z0\.s\]
--.*: e560bc00 st1w \{z0\.s\}, p7, \[z0\.s\]
--.*: e560bc00 st1w \{z0\.s\}, p7, \[z0\.s\]
--.*: e560bc00 st1w \{z0\.s\}, p7, \[z0\.s\]
--.*: e560a060 st1w \{z0\.s\}, p0, \[z3\.s\]
--.*: e560a060 st1w \{z0\.s\}, p0, \[z3\.s\]
--.*: e560a060 st1w \{z0\.s\}, p0, \[z3\.s\]
--.*: e560a3e0 st1w \{z0\.s\}, p0, \[z31\.s\]
--.*: e560a3e0 st1w \{z0\.s\}, p0, \[z31\.s\]
--.*: e560a3e0 st1w \{z0\.s\}, p0, \[z31\.s\]
--.*: e56fa000 st1w \{z0\.s\}, p0, \[z0\.s, #60\]
--.*: e56fa000 st1w \{z0\.s\}, p0, \[z0\.s, #60\]
--.*: e570a000 st1w \{z0\.s\}, p0, \[z0\.s, #64\]
--.*: e570a000 st1w \{z0\.s\}, p0, \[z0\.s, #64\]
--.*: e571a000 st1w \{z0\.s\}, p0, \[z0\.s, #68\]
--.*: e571a000 st1w \{z0\.s\}, p0, \[z0\.s, #68\]
--.*: e57fa000 st1w \{z0\.s\}, p0, \[z0\.s, #124\]
--.*: e57fa000 st1w \{z0\.s\}, p0, \[z0\.s, #124\]
--.*: e560e000 st1w \{z0\.d\}, p0, \[x0\]
--.*: e560e000 st1w \{z0\.d\}, p0, \[x0\]
--.*: e560e000 st1w \{z0\.d\}, p0, \[x0\]
--.*: e560e000 st1w \{z0\.d\}, p0, \[x0\]
--.*: e560e000 st1w \{z0\.d\}, p0, \[x0\]
--.*: e560e001 st1w \{z1\.d\}, p0, \[x0\]
--.*: e560e001 st1w \{z1\.d\}, p0, \[x0\]
--.*: e560e001 st1w \{z1\.d\}, p0, \[x0\]
--.*: e560e001 st1w \{z1\.d\}, p0, \[x0\]
--.*: e560e001 st1w \{z1\.d\}, p0, \[x0\]
--.*: e560e01f st1w \{z31\.d\}, p0, \[x0\]
--.*: e560e01f st1w \{z31\.d\}, p0, \[x0\]
--.*: e560e01f st1w \{z31\.d\}, p0, \[x0\]
--.*: e560e01f st1w \{z31\.d\}, p0, \[x0\]
--.*: e560e01f st1w \{z31\.d\}, p0, \[x0\]
--.*: e560e800 st1w \{z0\.d\}, p2, \[x0\]
--.*: e560e800 st1w \{z0\.d\}, p2, \[x0\]
--.*: e560e800 st1w \{z0\.d\}, p2, \[x0\]
--.*: e560e800 st1w \{z0\.d\}, p2, \[x0\]
--.*: e560fc00 st1w \{z0\.d\}, p7, \[x0\]
--.*: e560fc00 st1w \{z0\.d\}, p7, \[x0\]
--.*: e560fc00 st1w \{z0\.d\}, p7, \[x0\]
--.*: e560fc00 st1w \{z0\.d\}, p7, \[x0\]
--.*: e560e060 st1w \{z0\.d\}, p0, \[x3\]
--.*: e560e060 st1w \{z0\.d\}, p0, \[x3\]
--.*: e560e060 st1w \{z0\.d\}, p0, \[x3\]
--.*: e560e060 st1w \{z0\.d\}, p0, \[x3\]
--.*: e560e3e0 st1w \{z0\.d\}, p0, \[sp\]
--.*: e560e3e0 st1w \{z0\.d\}, p0, \[sp\]
--.*: e560e3e0 st1w \{z0\.d\}, p0, \[sp\]
--.*: e560e3e0 st1w \{z0\.d\}, p0, \[sp\]
--.*: e567e000 st1w \{z0\.d\}, p0, \[x0, #7, mul vl\]
--.*: e567e000 st1w \{z0\.d\}, p0, \[x0, #7, mul vl\]
--.*: e568e000 st1w \{z0\.d\}, p0, \[x0, #-8, mul vl\]
--.*: e568e000 st1w \{z0\.d\}, p0, \[x0, #-8, mul vl\]
--.*: e569e000 st1w \{z0\.d\}, p0, \[x0, #-7, mul vl\]
--.*: e569e000 st1w \{z0\.d\}, p0, \[x0, #-7, mul vl\]
--.*: e56fe000 st1w \{z0\.d\}, p0, \[x0, #-1, mul vl\]
--.*: e56fe000 st1w \{z0\.d\}, p0, \[x0, #-1, mul vl\]
--.*: e4206000 st2b \{z0\.b, z1\.b\}, p0, \[x0, x0\]
--.*: e4206000 st2b \{z0\.b, z1\.b\}, p0, \[x0, x0\]
--.*: e4206000 st2b \{z0\.b, z1\.b\}, p0, \[x0, x0\]
--.*: e4206000 st2b \{z0\.b, z1\.b\}, p0, \[x0, x0\]
--.*: e4206000 st2b \{z0\.b, z1\.b\}, p0, \[x0, x0\]
--.*: e4206001 st2b \{z1\.b, z2\.b\}, p0, \[x0, x0\]
--.*: e4206001 st2b \{z1\.b, z2\.b\}, p0, \[x0, x0\]
--.*: e4206001 st2b \{z1\.b, z2\.b\}, p0, \[x0, x0\]
--.*: e4206001 st2b \{z1\.b, z2\.b\}, p0, \[x0, x0\]
--.*: e4206001 st2b \{z1\.b, z2\.b\}, p0, \[x0, x0\]
--.*: e420601f st2b \{z31\.b, z0\.b\}, p0, \[x0, x0\]
--.*: e420601f st2b \{z31\.b, z0\.b\}, p0, \[x0, x0\]
--.*: e420601f st2b \{z31\.b, z0\.b\}, p0, \[x0, x0\]
--.*: e4206800 st2b \{z0\.b, z1\.b\}, p2, \[x0, x0\]
--.*: e4206800 st2b \{z0\.b, z1\.b\}, p2, \[x0, x0\]
--.*: e4206800 st2b \{z0\.b, z1\.b\}, p2, \[x0, x0\]
--.*: e4206800 st2b \{z0\.b, z1\.b\}, p2, \[x0, x0\]
--.*: e4206800 st2b \{z0\.b, z1\.b\}, p2, \[x0, x0\]
--.*: e4207c00 st2b \{z0\.b, z1\.b\}, p7, \[x0, x0\]
--.*: e4207c00 st2b \{z0\.b, z1\.b\}, p7, \[x0, x0\]
--.*: e4207c00 st2b \{z0\.b, z1\.b\}, p7, \[x0, x0\]
--.*: e4207c00 st2b \{z0\.b, z1\.b\}, p7, \[x0, x0\]
--.*: e4207c00 st2b \{z0\.b, z1\.b\}, p7, \[x0, x0\]
--.*: e4206060 st2b \{z0\.b, z1\.b\}, p0, \[x3, x0\]
--.*: e4206060 st2b \{z0\.b, z1\.b\}, p0, \[x3, x0\]
--.*: e4206060 st2b \{z0\.b, z1\.b\}, p0, \[x3, x0\]
--.*: e4206060 st2b \{z0\.b, z1\.b\}, p0, \[x3, x0\]
--.*: e4206060 st2b \{z0\.b, z1\.b\}, p0, \[x3, x0\]
--.*: e42063e0 st2b \{z0\.b, z1\.b\}, p0, \[sp, x0\]
--.*: e42063e0 st2b \{z0\.b, z1\.b\}, p0, \[sp, x0\]
--.*: e42063e0 st2b \{z0\.b, z1\.b\}, p0, \[sp, x0\]
--.*: e42063e0 st2b \{z0\.b, z1\.b\}, p0, \[sp, x0\]
--.*: e42063e0 st2b \{z0\.b, z1\.b\}, p0, \[sp, x0\]
--.*: e4246000 st2b \{z0\.b, z1\.b\}, p0, \[x0, x4\]
--.*: e4246000 st2b \{z0\.b, z1\.b\}, p0, \[x0, x4\]
--.*: e4246000 st2b \{z0\.b, z1\.b\}, p0, \[x0, x4\]
--.*: e4246000 st2b \{z0\.b, z1\.b\}, p0, \[x0, x4\]
--.*: e4246000 st2b \{z0\.b, z1\.b\}, p0, \[x0, x4\]
--.*: e43e6000 st2b \{z0\.b, z1\.b\}, p0, \[x0, x30\]
--.*: e43e6000 st2b \{z0\.b, z1\.b\}, p0, \[x0, x30\]
--.*: e43e6000 st2b \{z0\.b, z1\.b\}, p0, \[x0, x30\]
--.*: e43e6000 st2b \{z0\.b, z1\.b\}, p0, \[x0, x30\]
--.*: e43e6000 st2b \{z0\.b, z1\.b\}, p0, \[x0, x30\]
--.*: e430e000 st2b \{z0\.b, z1\.b\}, p0, \[x0\]
--.*: e430e000 st2b \{z0\.b, z1\.b\}, p0, \[x0\]
--.*: e430e000 st2b \{z0\.b, z1\.b\}, p0, \[x0\]
--.*: e430e000 st2b \{z0\.b, z1\.b\}, p0, \[x0\]
--.*: e430e000 st2b \{z0\.b, z1\.b\}, p0, \[x0\]
--.*: e430e000 st2b \{z0\.b, z1\.b\}, p0, \[x0\]
--.*: e430e000 st2b \{z0\.b, z1\.b\}, p0, \[x0\]
--.*: e430e001 st2b \{z1\.b, z2\.b\}, p0, \[x0\]
--.*: e430e001 st2b \{z1\.b, z2\.b\}, p0, \[x0\]
--.*: e430e001 st2b \{z1\.b, z2\.b\}, p0, \[x0\]
--.*: e430e001 st2b \{z1\.b, z2\.b\}, p0, \[x0\]
--.*: e430e001 st2b \{z1\.b, z2\.b\}, p0, \[x0\]
--.*: e430e001 st2b \{z1\.b, z2\.b\}, p0, \[x0\]
--.*: e430e001 st2b \{z1\.b, z2\.b\}, p0, \[x0\]
--.*: e430e01f st2b \{z31\.b, z0\.b\}, p0, \[x0\]
--.*: e430e01f st2b \{z31\.b, z0\.b\}, p0, \[x0\]
--.*: e430e01f st2b \{z31\.b, z0\.b\}, p0, \[x0\]
--.*: e430e01f st2b \{z31\.b, z0\.b\}, p0, \[x0\]
--.*: e430e800 st2b \{z0\.b, z1\.b\}, p2, \[x0\]
--.*: e430e800 st2b \{z0\.b, z1\.b\}, p2, \[x0\]
--.*: e430e800 st2b \{z0\.b, z1\.b\}, p2, \[x0\]
--.*: e430e800 st2b \{z0\.b, z1\.b\}, p2, \[x0\]
--.*: e430e800 st2b \{z0\.b, z1\.b\}, p2, \[x0\]
--.*: e430e800 st2b \{z0\.b, z1\.b\}, p2, \[x0\]
--.*: e430e800 st2b \{z0\.b, z1\.b\}, p2, \[x0\]
--.*: e430fc00 st2b \{z0\.b, z1\.b\}, p7, \[x0\]
--.*: e430fc00 st2b \{z0\.b, z1\.b\}, p7, \[x0\]
--.*: e430fc00 st2b \{z0\.b, z1\.b\}, p7, \[x0\]
--.*: e430fc00 st2b \{z0\.b, z1\.b\}, p7, \[x0\]
--.*: e430fc00 st2b \{z0\.b, z1\.b\}, p7, \[x0\]
--.*: e430fc00 st2b \{z0\.b, z1\.b\}, p7, \[x0\]
--.*: e430fc00 st2b \{z0\.b, z1\.b\}, p7, \[x0\]
--.*: e430e060 st2b \{z0\.b, z1\.b\}, p0, \[x3\]
--.*: e430e060 st2b \{z0\.b, z1\.b\}, p0, \[x3\]
--.*: e430e060 st2b \{z0\.b, z1\.b\}, p0, \[x3\]
--.*: e430e060 st2b \{z0\.b, z1\.b\}, p0, \[x3\]
--.*: e430e060 st2b \{z0\.b, z1\.b\}, p0, \[x3\]
--.*: e430e060 st2b \{z0\.b, z1\.b\}, p0, \[x3\]
--.*: e430e060 st2b \{z0\.b, z1\.b\}, p0, \[x3\]
--.*: e430e3e0 st2b \{z0\.b, z1\.b\}, p0, \[sp\]
--.*: e430e3e0 st2b \{z0\.b, z1\.b\}, p0, \[sp\]
--.*: e430e3e0 st2b \{z0\.b, z1\.b\}, p0, \[sp\]
--.*: e430e3e0 st2b \{z0\.b, z1\.b\}, p0, \[sp\]
--.*: e430e3e0 st2b \{z0\.b, z1\.b\}, p0, \[sp\]
--.*: e430e3e0 st2b \{z0\.b, z1\.b\}, p0, \[sp\]
--.*: e430e3e0 st2b \{z0\.b, z1\.b\}, p0, \[sp\]
--.*: e437e000 st2b \{z0\.b, z1\.b\}, p0, \[x0, #14, mul vl\]
--.*: e437e000 st2b \{z0\.b, z1\.b\}, p0, \[x0, #14, mul vl\]
--.*: e437e000 st2b \{z0\.b, z1\.b\}, p0, \[x0, #14, mul vl\]
--.*: e438e000 st2b \{z0\.b, z1\.b\}, p0, \[x0, #-16, mul vl\]
--.*: e438e000 st2b \{z0\.b, z1\.b\}, p0, \[x0, #-16, mul vl\]
--.*: e438e000 st2b \{z0\.b, z1\.b\}, p0, \[x0, #-16, mul vl\]
--.*: e439e000 st2b \{z0\.b, z1\.b\}, p0, \[x0, #-14, mul vl\]
--.*: e439e000 st2b \{z0\.b, z1\.b\}, p0, \[x0, #-14, mul vl\]
--.*: e439e000 st2b \{z0\.b, z1\.b\}, p0, \[x0, #-14, mul vl\]
--.*: e43fe000 st2b \{z0\.b, z1\.b\}, p0, \[x0, #-2, mul vl\]
--.*: e43fe000 st2b \{z0\.b, z1\.b\}, p0, \[x0, #-2, mul vl\]
--.*: e43fe000 st2b \{z0\.b, z1\.b\}, p0, \[x0, #-2, mul vl\]
--.*: e5a06000 st2d \{z0\.d, z1\.d\}, p0, \[x0, x0, lsl #3\]
--.*: e5a06000 st2d \{z0\.d, z1\.d\}, p0, \[x0, x0, lsl #3\]
--.*: e5a06000 st2d \{z0\.d, z1\.d\}, p0, \[x0, x0, lsl #3\]
--.*: e5a06001 st2d \{z1\.d, z2\.d\}, p0, \[x0, x0, lsl #3\]
--.*: e5a06001 st2d \{z1\.d, z2\.d\}, p0, \[x0, x0, lsl #3\]
--.*: e5a06001 st2d \{z1\.d, z2\.d\}, p0, \[x0, x0, lsl #3\]
--.*: e5a0601f st2d \{z31\.d, z0\.d\}, p0, \[x0, x0, lsl #3\]
--.*: e5a0601f st2d \{z31\.d, z0\.d\}, p0, \[x0, x0, lsl #3\]
--.*: e5a06800 st2d \{z0\.d, z1\.d\}, p2, \[x0, x0, lsl #3\]
--.*: e5a06800 st2d \{z0\.d, z1\.d\}, p2, \[x0, x0, lsl #3\]
--.*: e5a06800 st2d \{z0\.d, z1\.d\}, p2, \[x0, x0, lsl #3\]
--.*: e5a07c00 st2d \{z0\.d, z1\.d\}, p7, \[x0, x0, lsl #3\]
--.*: e5a07c00 st2d \{z0\.d, z1\.d\}, p7, \[x0, x0, lsl #3\]
--.*: e5a07c00 st2d \{z0\.d, z1\.d\}, p7, \[x0, x0, lsl #3\]
--.*: e5a06060 st2d \{z0\.d, z1\.d\}, p0, \[x3, x0, lsl #3\]
--.*: e5a06060 st2d \{z0\.d, z1\.d\}, p0, \[x3, x0, lsl #3\]
--.*: e5a06060 st2d \{z0\.d, z1\.d\}, p0, \[x3, x0, lsl #3\]
--.*: e5a063e0 st2d \{z0\.d, z1\.d\}, p0, \[sp, x0, lsl #3\]
--.*: e5a063e0 st2d \{z0\.d, z1\.d\}, p0, \[sp, x0, lsl #3\]
--.*: e5a063e0 st2d \{z0\.d, z1\.d\}, p0, \[sp, x0, lsl #3\]
--.*: e5a46000 st2d \{z0\.d, z1\.d\}, p0, \[x0, x4, lsl #3\]
--.*: e5a46000 st2d \{z0\.d, z1\.d\}, p0, \[x0, x4, lsl #3\]
--.*: e5a46000 st2d \{z0\.d, z1\.d\}, p0, \[x0, x4, lsl #3\]
--.*: e5be6000 st2d \{z0\.d, z1\.d\}, p0, \[x0, x30, lsl #3\]
--.*: e5be6000 st2d \{z0\.d, z1\.d\}, p0, \[x0, x30, lsl #3\]
--.*: e5be6000 st2d \{z0\.d, z1\.d\}, p0, \[x0, x30, lsl #3\]
--.*: e5b0e000 st2d \{z0\.d, z1\.d\}, p0, \[x0\]
--.*: e5b0e000 st2d \{z0\.d, z1\.d\}, p0, \[x0\]
--.*: e5b0e000 st2d \{z0\.d, z1\.d\}, p0, \[x0\]
--.*: e5b0e000 st2d \{z0\.d, z1\.d\}, p0, \[x0\]
--.*: e5b0e000 st2d \{z0\.d, z1\.d\}, p0, \[x0\]
--.*: e5b0e000 st2d \{z0\.d, z1\.d\}, p0, \[x0\]
--.*: e5b0e000 st2d \{z0\.d, z1\.d\}, p0, \[x0\]
--.*: e5b0e001 st2d \{z1\.d, z2\.d\}, p0, \[x0\]
--.*: e5b0e001 st2d \{z1\.d, z2\.d\}, p0, \[x0\]
--.*: e5b0e001 st2d \{z1\.d, z2\.d\}, p0, \[x0\]
--.*: e5b0e001 st2d \{z1\.d, z2\.d\}, p0, \[x0\]
--.*: e5b0e001 st2d \{z1\.d, z2\.d\}, p0, \[x0\]
--.*: e5b0e001 st2d \{z1\.d, z2\.d\}, p0, \[x0\]
--.*: e5b0e001 st2d \{z1\.d, z2\.d\}, p0, \[x0\]
--.*: e5b0e01f st2d \{z31\.d, z0\.d\}, p0, \[x0\]
--.*: e5b0e01f st2d \{z31\.d, z0\.d\}, p0, \[x0\]
--.*: e5b0e01f st2d \{z31\.d, z0\.d\}, p0, \[x0\]
--.*: e5b0e01f st2d \{z31\.d, z0\.d\}, p0, \[x0\]
--.*: e5b0e800 st2d \{z0\.d, z1\.d\}, p2, \[x0\]
--.*: e5b0e800 st2d \{z0\.d, z1\.d\}, p2, \[x0\]
--.*: e5b0e800 st2d \{z0\.d, z1\.d\}, p2, \[x0\]
--.*: e5b0e800 st2d \{z0\.d, z1\.d\}, p2, \[x0\]
--.*: e5b0e800 st2d \{z0\.d, z1\.d\}, p2, \[x0\]
--.*: e5b0e800 st2d \{z0\.d, z1\.d\}, p2, \[x0\]
--.*: e5b0e800 st2d \{z0\.d, z1\.d\}, p2, \[x0\]
--.*: e5b0fc00 st2d \{z0\.d, z1\.d\}, p7, \[x0\]
--.*: e5b0fc00 st2d \{z0\.d, z1\.d\}, p7, \[x0\]
--.*: e5b0fc00 st2d \{z0\.d, z1\.d\}, p7, \[x0\]
--.*: e5b0fc00 st2d \{z0\.d, z1\.d\}, p7, \[x0\]
--.*: e5b0fc00 st2d \{z0\.d, z1\.d\}, p7, \[x0\]
--.*: e5b0fc00 st2d \{z0\.d, z1\.d\}, p7, \[x0\]
--.*: e5b0fc00 st2d \{z0\.d, z1\.d\}, p7, \[x0\]
--.*: e5b0e060 st2d \{z0\.d, z1\.d\}, p0, \[x3\]
--.*: e5b0e060 st2d \{z0\.d, z1\.d\}, p0, \[x3\]
--.*: e5b0e060 st2d \{z0\.d, z1\.d\}, p0, \[x3\]
--.*: e5b0e060 st2d \{z0\.d, z1\.d\}, p0, \[x3\]
--.*: e5b0e060 st2d \{z0\.d, z1\.d\}, p0, \[x3\]
--.*: e5b0e060 st2d \{z0\.d, z1\.d\}, p0, \[x3\]
--.*: e5b0e060 st2d \{z0\.d, z1\.d\}, p0, \[x3\]
--.*: e5b0e3e0 st2d \{z0\.d, z1\.d\}, p0, \[sp\]
--.*: e5b0e3e0 st2d \{z0\.d, z1\.d\}, p0, \[sp\]
--.*: e5b0e3e0 st2d \{z0\.d, z1\.d\}, p0, \[sp\]
--.*: e5b0e3e0 st2d \{z0\.d, z1\.d\}, p0, \[sp\]
--.*: e5b0e3e0 st2d \{z0\.d, z1\.d\}, p0, \[sp\]
--.*: e5b0e3e0 st2d \{z0\.d, z1\.d\}, p0, \[sp\]
--.*: e5b0e3e0 st2d \{z0\.d, z1\.d\}, p0, \[sp\]
--.*: e5b7e000 st2d \{z0\.d, z1\.d\}, p0, \[x0, #14, mul vl\]
--.*: e5b7e000 st2d \{z0\.d, z1\.d\}, p0, \[x0, #14, mul vl\]
--.*: e5b7e000 st2d \{z0\.d, z1\.d\}, p0, \[x0, #14, mul vl\]
--.*: e5b8e000 st2d \{z0\.d, z1\.d\}, p0, \[x0, #-16, mul vl\]
--.*: e5b8e000 st2d \{z0\.d, z1\.d\}, p0, \[x0, #-16, mul vl\]
--.*: e5b8e000 st2d \{z0\.d, z1\.d\}, p0, \[x0, #-16, mul vl\]
--.*: e5b9e000 st2d \{z0\.d, z1\.d\}, p0, \[x0, #-14, mul vl\]
--.*: e5b9e000 st2d \{z0\.d, z1\.d\}, p0, \[x0, #-14, mul vl\]
--.*: e5b9e000 st2d \{z0\.d, z1\.d\}, p0, \[x0, #-14, mul vl\]
--.*: e5bfe000 st2d \{z0\.d, z1\.d\}, p0, \[x0, #-2, mul vl\]
--.*: e5bfe000 st2d \{z0\.d, z1\.d\}, p0, \[x0, #-2, mul vl\]
--.*: e5bfe000 st2d \{z0\.d, z1\.d\}, p0, \[x0, #-2, mul vl\]
--.*: e4a06000 st2h \{z0\.h, z1\.h\}, p0, \[x0, x0, lsl #1\]
--.*: e4a06000 st2h \{z0\.h, z1\.h\}, p0, \[x0, x0, lsl #1\]
--.*: e4a06000 st2h \{z0\.h, z1\.h\}, p0, \[x0, x0, lsl #1\]
--.*: e4a06001 st2h \{z1\.h, z2\.h\}, p0, \[x0, x0, lsl #1\]
--.*: e4a06001 st2h \{z1\.h, z2\.h\}, p0, \[x0, x0, lsl #1\]
--.*: e4a06001 st2h \{z1\.h, z2\.h\}, p0, \[x0, x0, lsl #1\]
--.*: e4a0601f st2h \{z31\.h, z0\.h\}, p0, \[x0, x0, lsl #1\]
--.*: e4a0601f st2h \{z31\.h, z0\.h\}, p0, \[x0, x0, lsl #1\]
--.*: e4a06800 st2h \{z0\.h, z1\.h\}, p2, \[x0, x0, lsl #1\]
--.*: e4a06800 st2h \{z0\.h, z1\.h\}, p2, \[x0, x0, lsl #1\]
--.*: e4a06800 st2h \{z0\.h, z1\.h\}, p2, \[x0, x0, lsl #1\]
--.*: e4a07c00 st2h \{z0\.h, z1\.h\}, p7, \[x0, x0, lsl #1\]
--.*: e4a07c00 st2h \{z0\.h, z1\.h\}, p7, \[x0, x0, lsl #1\]
--.*: e4a07c00 st2h \{z0\.h, z1\.h\}, p7, \[x0, x0, lsl #1\]
--.*: e4a06060 st2h \{z0\.h, z1\.h\}, p0, \[x3, x0, lsl #1\]
--.*: e4a06060 st2h \{z0\.h, z1\.h\}, p0, \[x3, x0, lsl #1\]
--.*: e4a06060 st2h \{z0\.h, z1\.h\}, p0, \[x3, x0, lsl #1\]
--.*: e4a063e0 st2h \{z0\.h, z1\.h\}, p0, \[sp, x0, lsl #1\]
--.*: e4a063e0 st2h \{z0\.h, z1\.h\}, p0, \[sp, x0, lsl #1\]
--.*: e4a063e0 st2h \{z0\.h, z1\.h\}, p0, \[sp, x0, lsl #1\]
--.*: e4a46000 st2h \{z0\.h, z1\.h\}, p0, \[x0, x4, lsl #1\]
--.*: e4a46000 st2h \{z0\.h, z1\.h\}, p0, \[x0, x4, lsl #1\]
--.*: e4a46000 st2h \{z0\.h, z1\.h\}, p0, \[x0, x4, lsl #1\]
--.*: e4be6000 st2h \{z0\.h, z1\.h\}, p0, \[x0, x30, lsl #1\]
--.*: e4be6000 st2h \{z0\.h, z1\.h\}, p0, \[x0, x30, lsl #1\]
--.*: e4be6000 st2h \{z0\.h, z1\.h\}, p0, \[x0, x30, lsl #1\]
--.*: e4b0e000 st2h \{z0\.h, z1\.h\}, p0, \[x0\]
--.*: e4b0e000 st2h \{z0\.h, z1\.h\}, p0, \[x0\]
--.*: e4b0e000 st2h \{z0\.h, z1\.h\}, p0, \[x0\]
--.*: e4b0e000 st2h \{z0\.h, z1\.h\}, p0, \[x0\]
--.*: e4b0e000 st2h \{z0\.h, z1\.h\}, p0, \[x0\]
--.*: e4b0e000 st2h \{z0\.h, z1\.h\}, p0, \[x0\]
--.*: e4b0e000 st2h \{z0\.h, z1\.h\}, p0, \[x0\]
--.*: e4b0e001 st2h \{z1\.h, z2\.h\}, p0, \[x0\]
--.*: e4b0e001 st2h \{z1\.h, z2\.h\}, p0, \[x0\]
--.*: e4b0e001 st2h \{z1\.h, z2\.h\}, p0, \[x0\]
--.*: e4b0e001 st2h \{z1\.h, z2\.h\}, p0, \[x0\]
--.*: e4b0e001 st2h \{z1\.h, z2\.h\}, p0, \[x0\]
--.*: e4b0e001 st2h \{z1\.h, z2\.h\}, p0, \[x0\]
--.*: e4b0e001 st2h \{z1\.h, z2\.h\}, p0, \[x0\]
--.*: e4b0e01f st2h \{z31\.h, z0\.h\}, p0, \[x0\]
--.*: e4b0e01f st2h \{z31\.h, z0\.h\}, p0, \[x0\]
--.*: e4b0e01f st2h \{z31\.h, z0\.h\}, p0, \[x0\]
--.*: e4b0e01f st2h \{z31\.h, z0\.h\}, p0, \[x0\]
--.*: e4b0e800 st2h \{z0\.h, z1\.h\}, p2, \[x0\]
--.*: e4b0e800 st2h \{z0\.h, z1\.h\}, p2, \[x0\]
--.*: e4b0e800 st2h \{z0\.h, z1\.h\}, p2, \[x0\]
--.*: e4b0e800 st2h \{z0\.h, z1\.h\}, p2, \[x0\]
--.*: e4b0e800 st2h \{z0\.h, z1\.h\}, p2, \[x0\]
--.*: e4b0e800 st2h \{z0\.h, z1\.h\}, p2, \[x0\]
--.*: e4b0e800 st2h \{z0\.h, z1\.h\}, p2, \[x0\]
--.*: e4b0fc00 st2h \{z0\.h, z1\.h\}, p7, \[x0\]
--.*: e4b0fc00 st2h \{z0\.h, z1\.h\}, p7, \[x0\]
--.*: e4b0fc00 st2h \{z0\.h, z1\.h\}, p7, \[x0\]
--.*: e4b0fc00 st2h \{z0\.h, z1\.h\}, p7, \[x0\]
--.*: e4b0fc00 st2h \{z0\.h, z1\.h\}, p7, \[x0\]
--.*: e4b0fc00 st2h \{z0\.h, z1\.h\}, p7, \[x0\]
--.*: e4b0fc00 st2h \{z0\.h, z1\.h\}, p7, \[x0\]
--.*: e4b0e060 st2h \{z0\.h, z1\.h\}, p0, \[x3\]
--.*: e4b0e060 st2h \{z0\.h, z1\.h\}, p0, \[x3\]
--.*: e4b0e060 st2h \{z0\.h, z1\.h\}, p0, \[x3\]
--.*: e4b0e060 st2h \{z0\.h, z1\.h\}, p0, \[x3\]
--.*: e4b0e060 st2h \{z0\.h, z1\.h\}, p0, \[x3\]
--.*: e4b0e060 st2h \{z0\.h, z1\.h\}, p0, \[x3\]
--.*: e4b0e060 st2h \{z0\.h, z1\.h\}, p0, \[x3\]
--.*: e4b0e3e0 st2h \{z0\.h, z1\.h\}, p0, \[sp\]
--.*: e4b0e3e0 st2h \{z0\.h, z1\.h\}, p0, \[sp\]
--.*: e4b0e3e0 st2h \{z0\.h, z1\.h\}, p0, \[sp\]
--.*: e4b0e3e0 st2h \{z0\.h, z1\.h\}, p0, \[sp\]
--.*: e4b0e3e0 st2h \{z0\.h, z1\.h\}, p0, \[sp\]
--.*: e4b0e3e0 st2h \{z0\.h, z1\.h\}, p0, \[sp\]
--.*: e4b0e3e0 st2h \{z0\.h, z1\.h\}, p0, \[sp\]
--.*: e4b7e000 st2h \{z0\.h, z1\.h\}, p0, \[x0, #14, mul vl\]
--.*: e4b7e000 st2h \{z0\.h, z1\.h\}, p0, \[x0, #14, mul vl\]
--.*: e4b7e000 st2h \{z0\.h, z1\.h\}, p0, \[x0, #14, mul vl\]
--.*: e4b8e000 st2h \{z0\.h, z1\.h\}, p0, \[x0, #-16, mul vl\]
--.*: e4b8e000 st2h \{z0\.h, z1\.h\}, p0, \[x0, #-16, mul vl\]
--.*: e4b8e000 st2h \{z0\.h, z1\.h\}, p0, \[x0, #-16, mul vl\]
--.*: e4b9e000 st2h \{z0\.h, z1\.h\}, p0, \[x0, #-14, mul vl\]
--.*: e4b9e000 st2h \{z0\.h, z1\.h\}, p0, \[x0, #-14, mul vl\]
--.*: e4b9e000 st2h \{z0\.h, z1\.h\}, p0, \[x0, #-14, mul vl\]
--.*: e4bfe000 st2h \{z0\.h, z1\.h\}, p0, \[x0, #-2, mul vl\]
--.*: e4bfe000 st2h \{z0\.h, z1\.h\}, p0, \[x0, #-2, mul vl\]
--.*: e4bfe000 st2h \{z0\.h, z1\.h\}, p0, \[x0, #-2, mul vl\]
--.*: e5206000 st2w \{z0\.s, z1\.s\}, p0, \[x0, x0, lsl #2\]
--.*: e5206000 st2w \{z0\.s, z1\.s\}, p0, \[x0, x0, lsl #2\]
--.*: e5206000 st2w \{z0\.s, z1\.s\}, p0, \[x0, x0, lsl #2\]
--.*: e5206001 st2w \{z1\.s, z2\.s\}, p0, \[x0, x0, lsl #2\]
--.*: e5206001 st2w \{z1\.s, z2\.s\}, p0, \[x0, x0, lsl #2\]
--.*: e5206001 st2w \{z1\.s, z2\.s\}, p0, \[x0, x0, lsl #2\]
--.*: e520601f st2w \{z31\.s, z0\.s\}, p0, \[x0, x0, lsl #2\]
--.*: e520601f st2w \{z31\.s, z0\.s\}, p0, \[x0, x0, lsl #2\]
--.*: e5206800 st2w \{z0\.s, z1\.s\}, p2, \[x0, x0, lsl #2\]
--.*: e5206800 st2w \{z0\.s, z1\.s\}, p2, \[x0, x0, lsl #2\]
--.*: e5206800 st2w \{z0\.s, z1\.s\}, p2, \[x0, x0, lsl #2\]
--.*: e5207c00 st2w \{z0\.s, z1\.s\}, p7, \[x0, x0, lsl #2\]
--.*: e5207c00 st2w \{z0\.s, z1\.s\}, p7, \[x0, x0, lsl #2\]
--.*: e5207c00 st2w \{z0\.s, z1\.s\}, p7, \[x0, x0, lsl #2\]
--.*: e5206060 st2w \{z0\.s, z1\.s\}, p0, \[x3, x0, lsl #2\]
--.*: e5206060 st2w \{z0\.s, z1\.s\}, p0, \[x3, x0, lsl #2\]
--.*: e5206060 st2w \{z0\.s, z1\.s\}, p0, \[x3, x0, lsl #2\]
--.*: e52063e0 st2w \{z0\.s, z1\.s\}, p0, \[sp, x0, lsl #2\]
--.*: e52063e0 st2w \{z0\.s, z1\.s\}, p0, \[sp, x0, lsl #2\]
--.*: e52063e0 st2w \{z0\.s, z1\.s\}, p0, \[sp, x0, lsl #2\]
--.*: e5246000 st2w \{z0\.s, z1\.s\}, p0, \[x0, x4, lsl #2\]
--.*: e5246000 st2w \{z0\.s, z1\.s\}, p0, \[x0, x4, lsl #2\]
--.*: e5246000 st2w \{z0\.s, z1\.s\}, p0, \[x0, x4, lsl #2\]
--.*: e53e6000 st2w \{z0\.s, z1\.s\}, p0, \[x0, x30, lsl #2\]
--.*: e53e6000 st2w \{z0\.s, z1\.s\}, p0, \[x0, x30, lsl #2\]
--.*: e53e6000 st2w \{z0\.s, z1\.s\}, p0, \[x0, x30, lsl #2\]
--.*: e530e000 st2w \{z0\.s, z1\.s\}, p0, \[x0\]
--.*: e530e000 st2w \{z0\.s, z1\.s\}, p0, \[x0\]
--.*: e530e000 st2w \{z0\.s, z1\.s\}, p0, \[x0\]
--.*: e530e000 st2w \{z0\.s, z1\.s\}, p0, \[x0\]
--.*: e530e000 st2w \{z0\.s, z1\.s\}, p0, \[x0\]
--.*: e530e000 st2w \{z0\.s, z1\.s\}, p0, \[x0\]
--.*: e530e000 st2w \{z0\.s, z1\.s\}, p0, \[x0\]
--.*: e530e001 st2w \{z1\.s, z2\.s\}, p0, \[x0\]
--.*: e530e001 st2w \{z1\.s, z2\.s\}, p0, \[x0\]
--.*: e530e001 st2w \{z1\.s, z2\.s\}, p0, \[x0\]
--.*: e530e001 st2w \{z1\.s, z2\.s\}, p0, \[x0\]
--.*: e530e001 st2w \{z1\.s, z2\.s\}, p0, \[x0\]
--.*: e530e001 st2w \{z1\.s, z2\.s\}, p0, \[x0\]
--.*: e530e001 st2w \{z1\.s, z2\.s\}, p0, \[x0\]
--.*: e530e01f st2w \{z31\.s, z0\.s\}, p0, \[x0\]
--.*: e530e01f st2w \{z31\.s, z0\.s\}, p0, \[x0\]
--.*: e530e01f st2w \{z31\.s, z0\.s\}, p0, \[x0\]
--.*: e530e01f st2w \{z31\.s, z0\.s\}, p0, \[x0\]
--.*: e530e800 st2w \{z0\.s, z1\.s\}, p2, \[x0\]
--.*: e530e800 st2w \{z0\.s, z1\.s\}, p2, \[x0\]
--.*: e530e800 st2w \{z0\.s, z1\.s\}, p2, \[x0\]
--.*: e530e800 st2w \{z0\.s, z1\.s\}, p2, \[x0\]
--.*: e530e800 st2w \{z0\.s, z1\.s\}, p2, \[x0\]
--.*: e530e800 st2w \{z0\.s, z1\.s\}, p2, \[x0\]
--.*: e530e800 st2w \{z0\.s, z1\.s\}, p2, \[x0\]
--.*: e530fc00 st2w \{z0\.s, z1\.s\}, p7, \[x0\]
--.*: e530fc00 st2w \{z0\.s, z1\.s\}, p7, \[x0\]
--.*: e530fc00 st2w \{z0\.s, z1\.s\}, p7, \[x0\]
--.*: e530fc00 st2w \{z0\.s, z1\.s\}, p7, \[x0\]
--.*: e530fc00 st2w \{z0\.s, z1\.s\}, p7, \[x0\]
--.*: e530fc00 st2w \{z0\.s, z1\.s\}, p7, \[x0\]
--.*: e530fc00 st2w \{z0\.s, z1\.s\}, p7, \[x0\]
--.*: e530e060 st2w \{z0\.s, z1\.s\}, p0, \[x3\]
--.*: e530e060 st2w \{z0\.s, z1\.s\}, p0, \[x3\]
--.*: e530e060 st2w \{z0\.s, z1\.s\}, p0, \[x3\]
--.*: e530e060 st2w \{z0\.s, z1\.s\}, p0, \[x3\]
--.*: e530e060 st2w \{z0\.s, z1\.s\}, p0, \[x3\]
--.*: e530e060 st2w \{z0\.s, z1\.s\}, p0, \[x3\]
--.*: e530e060 st2w \{z0\.s, z1\.s\}, p0, \[x3\]
--.*: e530e3e0 st2w \{z0\.s, z1\.s\}, p0, \[sp\]
--.*: e530e3e0 st2w \{z0\.s, z1\.s\}, p0, \[sp\]
--.*: e530e3e0 st2w \{z0\.s, z1\.s\}, p0, \[sp\]
--.*: e530e3e0 st2w \{z0\.s, z1\.s\}, p0, \[sp\]
--.*: e530e3e0 st2w \{z0\.s, z1\.s\}, p0, \[sp\]
--.*: e530e3e0 st2w \{z0\.s, z1\.s\}, p0, \[sp\]
--.*: e530e3e0 st2w \{z0\.s, z1\.s\}, p0, \[sp\]
--.*: e537e000 st2w \{z0\.s, z1\.s\}, p0, \[x0, #14, mul vl\]
--.*: e537e000 st2w \{z0\.s, z1\.s\}, p0, \[x0, #14, mul vl\]
--.*: e537e000 st2w \{z0\.s, z1\.s\}, p0, \[x0, #14, mul vl\]
--.*: e538e000 st2w \{z0\.s, z1\.s\}, p0, \[x0, #-16, mul vl\]
--.*: e538e000 st2w \{z0\.s, z1\.s\}, p0, \[x0, #-16, mul vl\]
--.*: e538e000 st2w \{z0\.s, z1\.s\}, p0, \[x0, #-16, mul vl\]
--.*: e539e000 st2w \{z0\.s, z1\.s\}, p0, \[x0, #-14, mul vl\]
--.*: e539e000 st2w \{z0\.s, z1\.s\}, p0, \[x0, #-14, mul vl\]
--.*: e539e000 st2w \{z0\.s, z1\.s\}, p0, \[x0, #-14, mul vl\]
--.*: e53fe000 st2w \{z0\.s, z1\.s\}, p0, \[x0, #-2, mul vl\]
--.*: e53fe000 st2w \{z0\.s, z1\.s\}, p0, \[x0, #-2, mul vl\]
--.*: e53fe000 st2w \{z0\.s, z1\.s\}, p0, \[x0, #-2, mul vl\]
--.*: e4406000 st3b \{z0\.b-z2\.b\}, p0, \[x0, x0\]
--.*: e4406000 st3b \{z0\.b-z2\.b\}, p0, \[x0, x0\]
--.*: e4406000 st3b \{z0\.b-z2\.b\}, p0, \[x0, x0\]
--.*: e4406000 st3b \{z0\.b-z2\.b\}, p0, \[x0, x0\]
--.*: e4406000 st3b \{z0\.b-z2\.b\}, p0, \[x0, x0\]
--.*: e4406001 st3b \{z1\.b-z3\.b\}, p0, \[x0, x0\]
--.*: e4406001 st3b \{z1\.b-z3\.b\}, p0, \[x0, x0\]
--.*: e4406001 st3b \{z1\.b-z3\.b\}, p0, \[x0, x0\]
--.*: e4406001 st3b \{z1\.b-z3\.b\}, p0, \[x0, x0\]
--.*: e4406001 st3b \{z1\.b-z3\.b\}, p0, \[x0, x0\]
--.*: e440601f st3b \{z31\.b, z0\.b, z1\.b\}, p0, \[x0, x0\]
--.*: e440601f st3b \{z31\.b, z0\.b, z1\.b\}, p0, \[x0, x0\]
--.*: e440601f st3b \{z31\.b, z0\.b, z1\.b\}, p0, \[x0, x0\]
--.*: e4406800 st3b \{z0\.b-z2\.b\}, p2, \[x0, x0\]
--.*: e4406800 st3b \{z0\.b-z2\.b\}, p2, \[x0, x0\]
--.*: e4406800 st3b \{z0\.b-z2\.b\}, p2, \[x0, x0\]
--.*: e4406800 st3b \{z0\.b-z2\.b\}, p2, \[x0, x0\]
--.*: e4406800 st3b \{z0\.b-z2\.b\}, p2, \[x0, x0\]
--.*: e4407c00 st3b \{z0\.b-z2\.b\}, p7, \[x0, x0\]
--.*: e4407c00 st3b \{z0\.b-z2\.b\}, p7, \[x0, x0\]
--.*: e4407c00 st3b \{z0\.b-z2\.b\}, p7, \[x0, x0\]
--.*: e4407c00 st3b \{z0\.b-z2\.b\}, p7, \[x0, x0\]
--.*: e4407c00 st3b \{z0\.b-z2\.b\}, p7, \[x0, x0\]
--.*: e4406060 st3b \{z0\.b-z2\.b\}, p0, \[x3, x0\]
--.*: e4406060 st3b \{z0\.b-z2\.b\}, p0, \[x3, x0\]
--.*: e4406060 st3b \{z0\.b-z2\.b\}, p0, \[x3, x0\]
--.*: e4406060 st3b \{z0\.b-z2\.b\}, p0, \[x3, x0\]
--.*: e4406060 st3b \{z0\.b-z2\.b\}, p0, \[x3, x0\]
--.*: e44063e0 st3b \{z0\.b-z2\.b\}, p0, \[sp, x0\]
--.*: e44063e0 st3b \{z0\.b-z2\.b\}, p0, \[sp, x0\]
--.*: e44063e0 st3b \{z0\.b-z2\.b\}, p0, \[sp, x0\]
--.*: e44063e0 st3b \{z0\.b-z2\.b\}, p0, \[sp, x0\]
--.*: e44063e0 st3b \{z0\.b-z2\.b\}, p0, \[sp, x0\]
--.*: e4446000 st3b \{z0\.b-z2\.b\}, p0, \[x0, x4\]
--.*: e4446000 st3b \{z0\.b-z2\.b\}, p0, \[x0, x4\]
--.*: e4446000 st3b \{z0\.b-z2\.b\}, p0, \[x0, x4\]
--.*: e4446000 st3b \{z0\.b-z2\.b\}, p0, \[x0, x4\]
--.*: e4446000 st3b \{z0\.b-z2\.b\}, p0, \[x0, x4\]
--.*: e45e6000 st3b \{z0\.b-z2\.b\}, p0, \[x0, x30\]
--.*: e45e6000 st3b \{z0\.b-z2\.b\}, p0, \[x0, x30\]
--.*: e45e6000 st3b \{z0\.b-z2\.b\}, p0, \[x0, x30\]
--.*: e45e6000 st3b \{z0\.b-z2\.b\}, p0, \[x0, x30\]
--.*: e45e6000 st3b \{z0\.b-z2\.b\}, p0, \[x0, x30\]
--.*: e450e000 st3b \{z0\.b-z2\.b\}, p0, \[x0\]
--.*: e450e000 st3b \{z0\.b-z2\.b\}, p0, \[x0\]
--.*: e450e000 st3b \{z0\.b-z2\.b\}, p0, \[x0\]
--.*: e450e000 st3b \{z0\.b-z2\.b\}, p0, \[x0\]
--.*: e450e000 st3b \{z0\.b-z2\.b\}, p0, \[x0\]
--.*: e450e000 st3b \{z0\.b-z2\.b\}, p0, \[x0\]
--.*: e450e000 st3b \{z0\.b-z2\.b\}, p0, \[x0\]
--.*: e450e001 st3b \{z1\.b-z3\.b\}, p0, \[x0\]
--.*: e450e001 st3b \{z1\.b-z3\.b\}, p0, \[x0\]
--.*: e450e001 st3b \{z1\.b-z3\.b\}, p0, \[x0\]
--.*: e450e001 st3b \{z1\.b-z3\.b\}, p0, \[x0\]
--.*: e450e001 st3b \{z1\.b-z3\.b\}, p0, \[x0\]
--.*: e450e001 st3b \{z1\.b-z3\.b\}, p0, \[x0\]
--.*: e450e001 st3b \{z1\.b-z3\.b\}, p0, \[x0\]
--.*: e450e01f st3b \{z31\.b, z0\.b, z1\.b\}, p0, \[x0\]
--.*: e450e01f st3b \{z31\.b, z0\.b, z1\.b\}, p0, \[x0\]
--.*: e450e01f st3b \{z31\.b, z0\.b, z1\.b\}, p0, \[x0\]
--.*: e450e01f st3b \{z31\.b, z0\.b, z1\.b\}, p0, \[x0\]
--.*: e450e800 st3b \{z0\.b-z2\.b\}, p2, \[x0\]
--.*: e450e800 st3b \{z0\.b-z2\.b\}, p2, \[x0\]
--.*: e450e800 st3b \{z0\.b-z2\.b\}, p2, \[x0\]
--.*: e450e800 st3b \{z0\.b-z2\.b\}, p2, \[x0\]
--.*: e450e800 st3b \{z0\.b-z2\.b\}, p2, \[x0\]
--.*: e450e800 st3b \{z0\.b-z2\.b\}, p2, \[x0\]
--.*: e450e800 st3b \{z0\.b-z2\.b\}, p2, \[x0\]
--.*: e450fc00 st3b \{z0\.b-z2\.b\}, p7, \[x0\]
--.*: e450fc00 st3b \{z0\.b-z2\.b\}, p7, \[x0\]
--.*: e450fc00 st3b \{z0\.b-z2\.b\}, p7, \[x0\]
--.*: e450fc00 st3b \{z0\.b-z2\.b\}, p7, \[x0\]
--.*: e450fc00 st3b \{z0\.b-z2\.b\}, p7, \[x0\]
--.*: e450fc00 st3b \{z0\.b-z2\.b\}, p7, \[x0\]
--.*: e450fc00 st3b \{z0\.b-z2\.b\}, p7, \[x0\]
--.*: e450e060 st3b \{z0\.b-z2\.b\}, p0, \[x3\]
--.*: e450e060 st3b \{z0\.b-z2\.b\}, p0, \[x3\]
--.*: e450e060 st3b \{z0\.b-z2\.b\}, p0, \[x3\]
--.*: e450e060 st3b \{z0\.b-z2\.b\}, p0, \[x3\]
--.*: e450e060 st3b \{z0\.b-z2\.b\}, p0, \[x3\]
--.*: e450e060 st3b \{z0\.b-z2\.b\}, p0, \[x3\]
--.*: e450e060 st3b \{z0\.b-z2\.b\}, p0, \[x3\]
--.*: e450e3e0 st3b \{z0\.b-z2\.b\}, p0, \[sp\]
--.*: e450e3e0 st3b \{z0\.b-z2\.b\}, p0, \[sp\]
--.*: e450e3e0 st3b \{z0\.b-z2\.b\}, p0, \[sp\]
--.*: e450e3e0 st3b \{z0\.b-z2\.b\}, p0, \[sp\]
--.*: e450e3e0 st3b \{z0\.b-z2\.b\}, p0, \[sp\]
--.*: e450e3e0 st3b \{z0\.b-z2\.b\}, p0, \[sp\]
--.*: e450e3e0 st3b \{z0\.b-z2\.b\}, p0, \[sp\]
--.*: e457e000 st3b \{z0\.b-z2\.b\}, p0, \[x0, #21, mul vl\]
--.*: e457e000 st3b \{z0\.b-z2\.b\}, p0, \[x0, #21, mul vl\]
--.*: e457e000 st3b \{z0\.b-z2\.b\}, p0, \[x0, #21, mul vl\]
--.*: e458e000 st3b \{z0\.b-z2\.b\}, p0, \[x0, #-24, mul vl\]
--.*: e458e000 st3b \{z0\.b-z2\.b\}, p0, \[x0, #-24, mul vl\]
--.*: e458e000 st3b \{z0\.b-z2\.b\}, p0, \[x0, #-24, mul vl\]
--.*: e459e000 st3b \{z0\.b-z2\.b\}, p0, \[x0, #-21, mul vl\]
--.*: e459e000 st3b \{z0\.b-z2\.b\}, p0, \[x0, #-21, mul vl\]
--.*: e459e000 st3b \{z0\.b-z2\.b\}, p0, \[x0, #-21, mul vl\]
--.*: e45fe000 st3b \{z0\.b-z2\.b\}, p0, \[x0, #-3, mul vl\]
--.*: e45fe000 st3b \{z0\.b-z2\.b\}, p0, \[x0, #-3, mul vl\]
--.*: e45fe000 st3b \{z0\.b-z2\.b\}, p0, \[x0, #-3, mul vl\]
--.*: e5c06000 st3d \{z0\.d-z2\.d\}, p0, \[x0, x0, lsl #3\]
--.*: e5c06000 st3d \{z0\.d-z2\.d\}, p0, \[x0, x0, lsl #3\]
--.*: e5c06000 st3d \{z0\.d-z2\.d\}, p0, \[x0, x0, lsl #3\]
--.*: e5c06001 st3d \{z1\.d-z3\.d\}, p0, \[x0, x0, lsl #3\]
--.*: e5c06001 st3d \{z1\.d-z3\.d\}, p0, \[x0, x0, lsl #3\]
--.*: e5c06001 st3d \{z1\.d-z3\.d\}, p0, \[x0, x0, lsl #3\]
--.*: e5c0601f st3d \{z31\.d, z0\.d, z1\.d\}, p0, \[x0, x0, lsl #3\]
--.*: e5c0601f st3d \{z31\.d, z0\.d, z1\.d\}, p0, \[x0, x0, lsl #3\]
--.*: e5c06800 st3d \{z0\.d-z2\.d\}, p2, \[x0, x0, lsl #3\]
--.*: e5c06800 st3d \{z0\.d-z2\.d\}, p2, \[x0, x0, lsl #3\]
--.*: e5c06800 st3d \{z0\.d-z2\.d\}, p2, \[x0, x0, lsl #3\]
--.*: e5c07c00 st3d \{z0\.d-z2\.d\}, p7, \[x0, x0, lsl #3\]
--.*: e5c07c00 st3d \{z0\.d-z2\.d\}, p7, \[x0, x0, lsl #3\]
--.*: e5c07c00 st3d \{z0\.d-z2\.d\}, p7, \[x0, x0, lsl #3\]
--.*: e5c06060 st3d \{z0\.d-z2\.d\}, p0, \[x3, x0, lsl #3\]
--.*: e5c06060 st3d \{z0\.d-z2\.d\}, p0, \[x3, x0, lsl #3\]
--.*: e5c06060 st3d \{z0\.d-z2\.d\}, p0, \[x3, x0, lsl #3\]
--.*: e5c063e0 st3d \{z0\.d-z2\.d\}, p0, \[sp, x0, lsl #3\]
--.*: e5c063e0 st3d \{z0\.d-z2\.d\}, p0, \[sp, x0, lsl #3\]
--.*: e5c063e0 st3d \{z0\.d-z2\.d\}, p0, \[sp, x0, lsl #3\]
--.*: e5c46000 st3d \{z0\.d-z2\.d\}, p0, \[x0, x4, lsl #3\]
--.*: e5c46000 st3d \{z0\.d-z2\.d\}, p0, \[x0, x4, lsl #3\]
--.*: e5c46000 st3d \{z0\.d-z2\.d\}, p0, \[x0, x4, lsl #3\]
--.*: e5de6000 st3d \{z0\.d-z2\.d\}, p0, \[x0, x30, lsl #3\]
--.*: e5de6000 st3d \{z0\.d-z2\.d\}, p0, \[x0, x30, lsl #3\]
--.*: e5de6000 st3d \{z0\.d-z2\.d\}, p0, \[x0, x30, lsl #3\]
--.*: e5d0e000 st3d \{z0\.d-z2\.d\}, p0, \[x0\]
--.*: e5d0e000 st3d \{z0\.d-z2\.d\}, p0, \[x0\]
--.*: e5d0e000 st3d \{z0\.d-z2\.d\}, p0, \[x0\]
--.*: e5d0e000 st3d \{z0\.d-z2\.d\}, p0, \[x0\]
--.*: e5d0e000 st3d \{z0\.d-z2\.d\}, p0, \[x0\]
--.*: e5d0e000 st3d \{z0\.d-z2\.d\}, p0, \[x0\]
--.*: e5d0e000 st3d \{z0\.d-z2\.d\}, p0, \[x0\]
--.*: e5d0e001 st3d \{z1\.d-z3\.d\}, p0, \[x0\]
--.*: e5d0e001 st3d \{z1\.d-z3\.d\}, p0, \[x0\]
--.*: e5d0e001 st3d \{z1\.d-z3\.d\}, p0, \[x0\]
--.*: e5d0e001 st3d \{z1\.d-z3\.d\}, p0, \[x0\]
--.*: e5d0e001 st3d \{z1\.d-z3\.d\}, p0, \[x0\]
--.*: e5d0e001 st3d \{z1\.d-z3\.d\}, p0, \[x0\]
--.*: e5d0e001 st3d \{z1\.d-z3\.d\}, p0, \[x0\]
--.*: e5d0e01f st3d \{z31\.d, z0\.d, z1\.d\}, p0, \[x0\]
--.*: e5d0e01f st3d \{z31\.d, z0\.d, z1\.d\}, p0, \[x0\]
--.*: e5d0e01f st3d \{z31\.d, z0\.d, z1\.d\}, p0, \[x0\]
--.*: e5d0e01f st3d \{z31\.d, z0\.d, z1\.d\}, p0, \[x0\]
--.*: e5d0e800 st3d \{z0\.d-z2\.d\}, p2, \[x0\]
--.*: e5d0e800 st3d \{z0\.d-z2\.d\}, p2, \[x0\]
--.*: e5d0e800 st3d \{z0\.d-z2\.d\}, p2, \[x0\]
--.*: e5d0e800 st3d \{z0\.d-z2\.d\}, p2, \[x0\]
--.*: e5d0e800 st3d \{z0\.d-z2\.d\}, p2, \[x0\]
--.*: e5d0e800 st3d \{z0\.d-z2\.d\}, p2, \[x0\]
--.*: e5d0e800 st3d \{z0\.d-z2\.d\}, p2, \[x0\]
--.*: e5d0fc00 st3d \{z0\.d-z2\.d\}, p7, \[x0\]
--.*: e5d0fc00 st3d \{z0\.d-z2\.d\}, p7, \[x0\]
--.*: e5d0fc00 st3d \{z0\.d-z2\.d\}, p7, \[x0\]
--.*: e5d0fc00 st3d \{z0\.d-z2\.d\}, p7, \[x0\]
--.*: e5d0fc00 st3d \{z0\.d-z2\.d\}, p7, \[x0\]
--.*: e5d0fc00 st3d \{z0\.d-z2\.d\}, p7, \[x0\]
--.*: e5d0fc00 st3d \{z0\.d-z2\.d\}, p7, \[x0\]
--.*: e5d0e060 st3d \{z0\.d-z2\.d\}, p0, \[x3\]
--.*: e5d0e060 st3d \{z0\.d-z2\.d\}, p0, \[x3\]
--.*: e5d0e060 st3d \{z0\.d-z2\.d\}, p0, \[x3\]
--.*: e5d0e060 st3d \{z0\.d-z2\.d\}, p0, \[x3\]
--.*: e5d0e060 st3d \{z0\.d-z2\.d\}, p0, \[x3\]
--.*: e5d0e060 st3d \{z0\.d-z2\.d\}, p0, \[x3\]
--.*: e5d0e060 st3d \{z0\.d-z2\.d\}, p0, \[x3\]
--.*: e5d0e3e0 st3d \{z0\.d-z2\.d\}, p0, \[sp\]
--.*: e5d0e3e0 st3d \{z0\.d-z2\.d\}, p0, \[sp\]
--.*: e5d0e3e0 st3d \{z0\.d-z2\.d\}, p0, \[sp\]
--.*: e5d0e3e0 st3d \{z0\.d-z2\.d\}, p0, \[sp\]
--.*: e5d0e3e0 st3d \{z0\.d-z2\.d\}, p0, \[sp\]
--.*: e5d0e3e0 st3d \{z0\.d-z2\.d\}, p0, \[sp\]
--.*: e5d0e3e0 st3d \{z0\.d-z2\.d\}, p0, \[sp\]
--.*: e5d7e000 st3d \{z0\.d-z2\.d\}, p0, \[x0, #21, mul vl\]
--.*: e5d7e000 st3d \{z0\.d-z2\.d\}, p0, \[x0, #21, mul vl\]
--.*: e5d7e000 st3d \{z0\.d-z2\.d\}, p0, \[x0, #21, mul vl\]
--.*: e5d8e000 st3d \{z0\.d-z2\.d\}, p0, \[x0, #-24, mul vl\]
--.*: e5d8e000 st3d \{z0\.d-z2\.d\}, p0, \[x0, #-24, mul vl\]
--.*: e5d8e000 st3d \{z0\.d-z2\.d\}, p0, \[x0, #-24, mul vl\]
--.*: e5d9e000 st3d \{z0\.d-z2\.d\}, p0, \[x0, #-21, mul vl\]
--.*: e5d9e000 st3d \{z0\.d-z2\.d\}, p0, \[x0, #-21, mul vl\]
--.*: e5d9e000 st3d \{z0\.d-z2\.d\}, p0, \[x0, #-21, mul vl\]
--.*: e5dfe000 st3d \{z0\.d-z2\.d\}, p0, \[x0, #-3, mul vl\]
--.*: e5dfe000 st3d \{z0\.d-z2\.d\}, p0, \[x0, #-3, mul vl\]
--.*: e5dfe000 st3d \{z0\.d-z2\.d\}, p0, \[x0, #-3, mul vl\]
--.*: e4c06000 st3h \{z0\.h-z2\.h\}, p0, \[x0, x0, lsl #1\]
--.*: e4c06000 st3h \{z0\.h-z2\.h\}, p0, \[x0, x0, lsl #1\]
--.*: e4c06000 st3h \{z0\.h-z2\.h\}, p0, \[x0, x0, lsl #1\]
--.*: e4c06001 st3h \{z1\.h-z3\.h\}, p0, \[x0, x0, lsl #1\]
--.*: e4c06001 st3h \{z1\.h-z3\.h\}, p0, \[x0, x0, lsl #1\]
--.*: e4c06001 st3h \{z1\.h-z3\.h\}, p0, \[x0, x0, lsl #1\]
--.*: e4c0601f st3h \{z31\.h, z0\.h, z1\.h\}, p0, \[x0, x0, lsl #1\]
--.*: e4c0601f st3h \{z31\.h, z0\.h, z1\.h\}, p0, \[x0, x0, lsl #1\]
--.*: e4c06800 st3h \{z0\.h-z2\.h\}, p2, \[x0, x0, lsl #1\]
--.*: e4c06800 st3h \{z0\.h-z2\.h\}, p2, \[x0, x0, lsl #1\]
--.*: e4c06800 st3h \{z0\.h-z2\.h\}, p2, \[x0, x0, lsl #1\]
--.*: e4c07c00 st3h \{z0\.h-z2\.h\}, p7, \[x0, x0, lsl #1\]
--.*: e4c07c00 st3h \{z0\.h-z2\.h\}, p7, \[x0, x0, lsl #1\]
--.*: e4c07c00 st3h \{z0\.h-z2\.h\}, p7, \[x0, x0, lsl #1\]
--.*: e4c06060 st3h \{z0\.h-z2\.h\}, p0, \[x3, x0, lsl #1\]
--.*: e4c06060 st3h \{z0\.h-z2\.h\}, p0, \[x3, x0, lsl #1\]
--.*: e4c06060 st3h \{z0\.h-z2\.h\}, p0, \[x3, x0, lsl #1\]
--.*: e4c063e0 st3h \{z0\.h-z2\.h\}, p0, \[sp, x0, lsl #1\]
--.*: e4c063e0 st3h \{z0\.h-z2\.h\}, p0, \[sp, x0, lsl #1\]
--.*: e4c063e0 st3h \{z0\.h-z2\.h\}, p0, \[sp, x0, lsl #1\]
--.*: e4c46000 st3h \{z0\.h-z2\.h\}, p0, \[x0, x4, lsl #1\]
--.*: e4c46000 st3h \{z0\.h-z2\.h\}, p0, \[x0, x4, lsl #1\]
--.*: e4c46000 st3h \{z0\.h-z2\.h\}, p0, \[x0, x4, lsl #1\]
--.*: e4de6000 st3h \{z0\.h-z2\.h\}, p0, \[x0, x30, lsl #1\]
--.*: e4de6000 st3h \{z0\.h-z2\.h\}, p0, \[x0, x30, lsl #1\]
--.*: e4de6000 st3h \{z0\.h-z2\.h\}, p0, \[x0, x30, lsl #1\]
--.*: e4d0e000 st3h \{z0\.h-z2\.h\}, p0, \[x0\]
--.*: e4d0e000 st3h \{z0\.h-z2\.h\}, p0, \[x0\]
--.*: e4d0e000 st3h \{z0\.h-z2\.h\}, p0, \[x0\]
--.*: e4d0e000 st3h \{z0\.h-z2\.h\}, p0, \[x0\]
--.*: e4d0e000 st3h \{z0\.h-z2\.h\}, p0, \[x0\]
--.*: e4d0e000 st3h \{z0\.h-z2\.h\}, p0, \[x0\]
--.*: e4d0e000 st3h \{z0\.h-z2\.h\}, p0, \[x0\]
--.*: e4d0e001 st3h \{z1\.h-z3\.h\}, p0, \[x0\]
--.*: e4d0e001 st3h \{z1\.h-z3\.h\}, p0, \[x0\]
--.*: e4d0e001 st3h \{z1\.h-z3\.h\}, p0, \[x0\]
--.*: e4d0e001 st3h \{z1\.h-z3\.h\}, p0, \[x0\]
--.*: e4d0e001 st3h \{z1\.h-z3\.h\}, p0, \[x0\]
--.*: e4d0e001 st3h \{z1\.h-z3\.h\}, p0, \[x0\]
--.*: e4d0e001 st3h \{z1\.h-z3\.h\}, p0, \[x0\]
--.*: e4d0e01f st3h \{z31\.h, z0\.h, z1\.h\}, p0, \[x0\]
--.*: e4d0e01f st3h \{z31\.h, z0\.h, z1\.h\}, p0, \[x0\]
--.*: e4d0e01f st3h \{z31\.h, z0\.h, z1\.h\}, p0, \[x0\]
--.*: e4d0e01f st3h \{z31\.h, z0\.h, z1\.h\}, p0, \[x0\]
--.*: e4d0e800 st3h \{z0\.h-z2\.h\}, p2, \[x0\]
--.*: e4d0e800 st3h \{z0\.h-z2\.h\}, p2, \[x0\]
--.*: e4d0e800 st3h \{z0\.h-z2\.h\}, p2, \[x0\]
--.*: e4d0e800 st3h \{z0\.h-z2\.h\}, p2, \[x0\]
--.*: e4d0e800 st3h \{z0\.h-z2\.h\}, p2, \[x0\]
--.*: e4d0e800 st3h \{z0\.h-z2\.h\}, p2, \[x0\]
--.*: e4d0e800 st3h \{z0\.h-z2\.h\}, p2, \[x0\]
--.*: e4d0fc00 st3h \{z0\.h-z2\.h\}, p7, \[x0\]
--.*: e4d0fc00 st3h \{z0\.h-z2\.h\}, p7, \[x0\]
--.*: e4d0fc00 st3h \{z0\.h-z2\.h\}, p7, \[x0\]
--.*: e4d0fc00 st3h \{z0\.h-z2\.h\}, p7, \[x0\]
--.*: e4d0fc00 st3h \{z0\.h-z2\.h\}, p7, \[x0\]
--.*: e4d0fc00 st3h \{z0\.h-z2\.h\}, p7, \[x0\]
--.*: e4d0fc00 st3h \{z0\.h-z2\.h\}, p7, \[x0\]
--.*: e4d0e060 st3h \{z0\.h-z2\.h\}, p0, \[x3\]
--.*: e4d0e060 st3h \{z0\.h-z2\.h\}, p0, \[x3\]
--.*: e4d0e060 st3h \{z0\.h-z2\.h\}, p0, \[x3\]
--.*: e4d0e060 st3h \{z0\.h-z2\.h\}, p0, \[x3\]
--.*: e4d0e060 st3h \{z0\.h-z2\.h\}, p0, \[x3\]
--.*: e4d0e060 st3h \{z0\.h-z2\.h\}, p0, \[x3\]
--.*: e4d0e060 st3h \{z0\.h-z2\.h\}, p0, \[x3\]
--.*: e4d0e3e0 st3h \{z0\.h-z2\.h\}, p0, \[sp\]
--.*: e4d0e3e0 st3h \{z0\.h-z2\.h\}, p0, \[sp\]
--.*: e4d0e3e0 st3h \{z0\.h-z2\.h\}, p0, \[sp\]
--.*: e4d0e3e0 st3h \{z0\.h-z2\.h\}, p0, \[sp\]
--.*: e4d0e3e0 st3h \{z0\.h-z2\.h\}, p0, \[sp\]
--.*: e4d0e3e0 st3h \{z0\.h-z2\.h\}, p0, \[sp\]
--.*: e4d0e3e0 st3h \{z0\.h-z2\.h\}, p0, \[sp\]
--.*: e4d7e000 st3h \{z0\.h-z2\.h\}, p0, \[x0, #21, mul vl\]
--.*: e4d7e000 st3h \{z0\.h-z2\.h\}, p0, \[x0, #21, mul vl\]
--.*: e4d7e000 st3h \{z0\.h-z2\.h\}, p0, \[x0, #21, mul vl\]
--.*: e4d8e000 st3h \{z0\.h-z2\.h\}, p0, \[x0, #-24, mul vl\]
--.*: e4d8e000 st3h \{z0\.h-z2\.h\}, p0, \[x0, #-24, mul vl\]
--.*: e4d8e000 st3h \{z0\.h-z2\.h\}, p0, \[x0, #-24, mul vl\]
--.*: e4d9e000 st3h \{z0\.h-z2\.h\}, p0, \[x0, #-21, mul vl\]
--.*: e4d9e000 st3h \{z0\.h-z2\.h\}, p0, \[x0, #-21, mul vl\]
--.*: e4d9e000 st3h \{z0\.h-z2\.h\}, p0, \[x0, #-21, mul vl\]
--.*: e4dfe000 st3h \{z0\.h-z2\.h\}, p0, \[x0, #-3, mul vl\]
--.*: e4dfe000 st3h \{z0\.h-z2\.h\}, p0, \[x0, #-3, mul vl\]
--.*: e4dfe000 st3h \{z0\.h-z2\.h\}, p0, \[x0, #-3, mul vl\]
--.*: e5406000 st3w \{z0\.s-z2\.s\}, p0, \[x0, x0, lsl #2\]
--.*: e5406000 st3w \{z0\.s-z2\.s\}, p0, \[x0, x0, lsl #2\]
--.*: e5406000 st3w \{z0\.s-z2\.s\}, p0, \[x0, x0, lsl #2\]
--.*: e5406001 st3w \{z1\.s-z3\.s\}, p0, \[x0, x0, lsl #2\]
--.*: e5406001 st3w \{z1\.s-z3\.s\}, p0, \[x0, x0, lsl #2\]
--.*: e5406001 st3w \{z1\.s-z3\.s\}, p0, \[x0, x0, lsl #2\]
--.*: e540601f st3w \{z31\.s, z0\.s, z1\.s\}, p0, \[x0, x0, lsl #2\]
--.*: e540601f st3w \{z31\.s, z0\.s, z1\.s\}, p0, \[x0, x0, lsl #2\]
--.*: e5406800 st3w \{z0\.s-z2\.s\}, p2, \[x0, x0, lsl #2\]
--.*: e5406800 st3w \{z0\.s-z2\.s\}, p2, \[x0, x0, lsl #2\]
--.*: e5406800 st3w \{z0\.s-z2\.s\}, p2, \[x0, x0, lsl #2\]
--.*: e5407c00 st3w \{z0\.s-z2\.s\}, p7, \[x0, x0, lsl #2\]
--.*: e5407c00 st3w \{z0\.s-z2\.s\}, p7, \[x0, x0, lsl #2\]
--.*: e5407c00 st3w \{z0\.s-z2\.s\}, p7, \[x0, x0, lsl #2\]
--.*: e5406060 st3w \{z0\.s-z2\.s\}, p0, \[x3, x0, lsl #2\]
--.*: e5406060 st3w \{z0\.s-z2\.s\}, p0, \[x3, x0, lsl #2\]
--.*: e5406060 st3w \{z0\.s-z2\.s\}, p0, \[x3, x0, lsl #2\]
--.*: e54063e0 st3w \{z0\.s-z2\.s\}, p0, \[sp, x0, lsl #2\]
--.*: e54063e0 st3w \{z0\.s-z2\.s\}, p0, \[sp, x0, lsl #2\]
--.*: e54063e0 st3w \{z0\.s-z2\.s\}, p0, \[sp, x0, lsl #2\]
--.*: e5446000 st3w \{z0\.s-z2\.s\}, p0, \[x0, x4, lsl #2\]
--.*: e5446000 st3w \{z0\.s-z2\.s\}, p0, \[x0, x4, lsl #2\]
--.*: e5446000 st3w \{z0\.s-z2\.s\}, p0, \[x0, x4, lsl #2\]
--.*: e55e6000 st3w \{z0\.s-z2\.s\}, p0, \[x0, x30, lsl #2\]
--.*: e55e6000 st3w \{z0\.s-z2\.s\}, p0, \[x0, x30, lsl #2\]
--.*: e55e6000 st3w \{z0\.s-z2\.s\}, p0, \[x0, x30, lsl #2\]
--.*: e550e000 st3w \{z0\.s-z2\.s\}, p0, \[x0\]
--.*: e550e000 st3w \{z0\.s-z2\.s\}, p0, \[x0\]
--.*: e550e000 st3w \{z0\.s-z2\.s\}, p0, \[x0\]
--.*: e550e000 st3w \{z0\.s-z2\.s\}, p0, \[x0\]
--.*: e550e000 st3w \{z0\.s-z2\.s\}, p0, \[x0\]
--.*: e550e000 st3w \{z0\.s-z2\.s\}, p0, \[x0\]
--.*: e550e000 st3w \{z0\.s-z2\.s\}, p0, \[x0\]
--.*: e550e001 st3w \{z1\.s-z3\.s\}, p0, \[x0\]
--.*: e550e001 st3w \{z1\.s-z3\.s\}, p0, \[x0\]
--.*: e550e001 st3w \{z1\.s-z3\.s\}, p0, \[x0\]
--.*: e550e001 st3w \{z1\.s-z3\.s\}, p0, \[x0\]
--.*: e550e001 st3w \{z1\.s-z3\.s\}, p0, \[x0\]
--.*: e550e001 st3w \{z1\.s-z3\.s\}, p0, \[x0\]
--.*: e550e001 st3w \{z1\.s-z3\.s\}, p0, \[x0\]
--.*: e550e01f st3w \{z31\.s, z0\.s, z1\.s\}, p0, \[x0\]
--.*: e550e01f st3w \{z31\.s, z0\.s, z1\.s\}, p0, \[x0\]
--.*: e550e01f st3w \{z31\.s, z0\.s, z1\.s\}, p0, \[x0\]
--.*: e550e01f st3w \{z31\.s, z0\.s, z1\.s\}, p0, \[x0\]
--.*: e550e800 st3w \{z0\.s-z2\.s\}, p2, \[x0\]
--.*: e550e800 st3w \{z0\.s-z2\.s\}, p2, \[x0\]
--.*: e550e800 st3w \{z0\.s-z2\.s\}, p2, \[x0\]
--.*: e550e800 st3w \{z0\.s-z2\.s\}, p2, \[x0\]
--.*: e550e800 st3w \{z0\.s-z2\.s\}, p2, \[x0\]
--.*: e550e800 st3w \{z0\.s-z2\.s\}, p2, \[x0\]
--.*: e550e800 st3w \{z0\.s-z2\.s\}, p2, \[x0\]
--.*: e550fc00 st3w \{z0\.s-z2\.s\}, p7, \[x0\]
--.*: e550fc00 st3w \{z0\.s-z2\.s\}, p7, \[x0\]
--.*: e550fc00 st3w \{z0\.s-z2\.s\}, p7, \[x0\]
--.*: e550fc00 st3w \{z0\.s-z2\.s\}, p7, \[x0\]
--.*: e550fc00 st3w \{z0\.s-z2\.s\}, p7, \[x0\]
--.*: e550fc00 st3w \{z0\.s-z2\.s\}, p7, \[x0\]
--.*: e550fc00 st3w \{z0\.s-z2\.s\}, p7, \[x0\]
--.*: e550e060 st3w \{z0\.s-z2\.s\}, p0, \[x3\]
--.*: e550e060 st3w \{z0\.s-z2\.s\}, p0, \[x3\]
--.*: e550e060 st3w \{z0\.s-z2\.s\}, p0, \[x3\]
--.*: e550e060 st3w \{z0\.s-z2\.s\}, p0, \[x3\]
--.*: e550e060 st3w \{z0\.s-z2\.s\}, p0, \[x3\]
--.*: e550e060 st3w \{z0\.s-z2\.s\}, p0, \[x3\]
--.*: e550e060 st3w \{z0\.s-z2\.s\}, p0, \[x3\]
--.*: e550e3e0 st3w \{z0\.s-z2\.s\}, p0, \[sp\]
--.*: e550e3e0 st3w \{z0\.s-z2\.s\}, p0, \[sp\]
--.*: e550e3e0 st3w \{z0\.s-z2\.s\}, p0, \[sp\]
--.*: e550e3e0 st3w \{z0\.s-z2\.s\}, p0, \[sp\]
--.*: e550e3e0 st3w \{z0\.s-z2\.s\}, p0, \[sp\]
--.*: e550e3e0 st3w \{z0\.s-z2\.s\}, p0, \[sp\]
--.*: e550e3e0 st3w \{z0\.s-z2\.s\}, p0, \[sp\]
--.*: e557e000 st3w \{z0\.s-z2\.s\}, p0, \[x0, #21, mul vl\]
--.*: e557e000 st3w \{z0\.s-z2\.s\}, p0, \[x0, #21, mul vl\]
--.*: e557e000 st3w \{z0\.s-z2\.s\}, p0, \[x0, #21, mul vl\]
--.*: e558e000 st3w \{z0\.s-z2\.s\}, p0, \[x0, #-24, mul vl\]
--.*: e558e000 st3w \{z0\.s-z2\.s\}, p0, \[x0, #-24, mul vl\]
--.*: e558e000 st3w \{z0\.s-z2\.s\}, p0, \[x0, #-24, mul vl\]
--.*: e559e000 st3w \{z0\.s-z2\.s\}, p0, \[x0, #-21, mul vl\]
--.*: e559e000 st3w \{z0\.s-z2\.s\}, p0, \[x0, #-21, mul vl\]
--.*: e559e000 st3w \{z0\.s-z2\.s\}, p0, \[x0, #-21, mul vl\]
--.*: e55fe000 st3w \{z0\.s-z2\.s\}, p0, \[x0, #-3, mul vl\]
--.*: e55fe000 st3w \{z0\.s-z2\.s\}, p0, \[x0, #-3, mul vl\]
--.*: e55fe000 st3w \{z0\.s-z2\.s\}, p0, \[x0, #-3, mul vl\]
--.*: e4606000 st4b \{z0\.b-z3\.b\}, p0, \[x0, x0\]
--.*: e4606000 st4b \{z0\.b-z3\.b\}, p0, \[x0, x0\]
--.*: e4606000 st4b \{z0\.b-z3\.b\}, p0, \[x0, x0\]
--.*: e4606000 st4b \{z0\.b-z3\.b\}, p0, \[x0, x0\]
--.*: e4606000 st4b \{z0\.b-z3\.b\}, p0, \[x0, x0\]
--.*: e4606001 st4b \{z1\.b-z4\.b\}, p0, \[x0, x0\]
--.*: e4606001 st4b \{z1\.b-z4\.b\}, p0, \[x0, x0\]
--.*: e4606001 st4b \{z1\.b-z4\.b\}, p0, \[x0, x0\]
--.*: e4606001 st4b \{z1\.b-z4\.b\}, p0, \[x0, x0\]
--.*: e4606001 st4b \{z1\.b-z4\.b\}, p0, \[x0, x0\]
--.*: e460601f st4b \{z31\.b, z0\.b, z1\.b, z2\.b\}, p0, \[x0, x0\]
--.*: e460601f st4b \{z31\.b, z0\.b, z1\.b, z2\.b\}, p0, \[x0, x0\]
--.*: e460601f st4b \{z31\.b, z0\.b, z1\.b, z2\.b\}, p0, \[x0, x0\]
--.*: e4606800 st4b \{z0\.b-z3\.b\}, p2, \[x0, x0\]
--.*: e4606800 st4b \{z0\.b-z3\.b\}, p2, \[x0, x0\]
--.*: e4606800 st4b \{z0\.b-z3\.b\}, p2, \[x0, x0\]
--.*: e4606800 st4b \{z0\.b-z3\.b\}, p2, \[x0, x0\]
--.*: e4606800 st4b \{z0\.b-z3\.b\}, p2, \[x0, x0\]
--.*: e4607c00 st4b \{z0\.b-z3\.b\}, p7, \[x0, x0\]
--.*: e4607c00 st4b \{z0\.b-z3\.b\}, p7, \[x0, x0\]
--.*: e4607c00 st4b \{z0\.b-z3\.b\}, p7, \[x0, x0\]
--.*: e4607c00 st4b \{z0\.b-z3\.b\}, p7, \[x0, x0\]
--.*: e4607c00 st4b \{z0\.b-z3\.b\}, p7, \[x0, x0\]
--.*: e4606060 st4b \{z0\.b-z3\.b\}, p0, \[x3, x0\]
--.*: e4606060 st4b \{z0\.b-z3\.b\}, p0, \[x3, x0\]
--.*: e4606060 st4b \{z0\.b-z3\.b\}, p0, \[x3, x0\]
--.*: e4606060 st4b \{z0\.b-z3\.b\}, p0, \[x3, x0\]
--.*: e4606060 st4b \{z0\.b-z3\.b\}, p0, \[x3, x0\]
--.*: e46063e0 st4b \{z0\.b-z3\.b\}, p0, \[sp, x0\]
--.*: e46063e0 st4b \{z0\.b-z3\.b\}, p0, \[sp, x0\]
--.*: e46063e0 st4b \{z0\.b-z3\.b\}, p0, \[sp, x0\]
--.*: e46063e0 st4b \{z0\.b-z3\.b\}, p0, \[sp, x0\]
--.*: e46063e0 st4b \{z0\.b-z3\.b\}, p0, \[sp, x0\]
--.*: e4646000 st4b \{z0\.b-z3\.b\}, p0, \[x0, x4\]
--.*: e4646000 st4b \{z0\.b-z3\.b\}, p0, \[x0, x4\]
--.*: e4646000 st4b \{z0\.b-z3\.b\}, p0, \[x0, x4\]
--.*: e4646000 st4b \{z0\.b-z3\.b\}, p0, \[x0, x4\]
--.*: e4646000 st4b \{z0\.b-z3\.b\}, p0, \[x0, x4\]
--.*: e47e6000 st4b \{z0\.b-z3\.b\}, p0, \[x0, x30\]
--.*: e47e6000 st4b \{z0\.b-z3\.b\}, p0, \[x0, x30\]
--.*: e47e6000 st4b \{z0\.b-z3\.b\}, p0, \[x0, x30\]
--.*: e47e6000 st4b \{z0\.b-z3\.b\}, p0, \[x0, x30\]
--.*: e47e6000 st4b \{z0\.b-z3\.b\}, p0, \[x0, x30\]
--.*: e470e000 st4b \{z0\.b-z3\.b\}, p0, \[x0\]
--.*: e470e000 st4b \{z0\.b-z3\.b\}, p0, \[x0\]
--.*: e470e000 st4b \{z0\.b-z3\.b\}, p0, \[x0\]
--.*: e470e000 st4b \{z0\.b-z3\.b\}, p0, \[x0\]
--.*: e470e000 st4b \{z0\.b-z3\.b\}, p0, \[x0\]
--.*: e470e000 st4b \{z0\.b-z3\.b\}, p0, \[x0\]
--.*: e470e000 st4b \{z0\.b-z3\.b\}, p0, \[x0\]
--.*: e470e001 st4b \{z1\.b-z4\.b\}, p0, \[x0\]
--.*: e470e001 st4b \{z1\.b-z4\.b\}, p0, \[x0\]
--.*: e470e001 st4b \{z1\.b-z4\.b\}, p0, \[x0\]
--.*: e470e001 st4b \{z1\.b-z4\.b\}, p0, \[x0\]
--.*: e470e001 st4b \{z1\.b-z4\.b\}, p0, \[x0\]
--.*: e470e001 st4b \{z1\.b-z4\.b\}, p0, \[x0\]
--.*: e470e001 st4b \{z1\.b-z4\.b\}, p0, \[x0\]
--.*: e470e01f st4b \{z31\.b, z0\.b, z1\.b, z2\.b\}, p0, \[x0\]
--.*: e470e01f st4b \{z31\.b, z0\.b, z1\.b, z2\.b\}, p0, \[x0\]
--.*: e470e01f st4b \{z31\.b, z0\.b, z1\.b, z2\.b\}, p0, \[x0\]
--.*: e470e01f st4b \{z31\.b, z0\.b, z1\.b, z2\.b\}, p0, \[x0\]
--.*: e470e800 st4b \{z0\.b-z3\.b\}, p2, \[x0\]
--.*: e470e800 st4b \{z0\.b-z3\.b\}, p2, \[x0\]
--.*: e470e800 st4b \{z0\.b-z3\.b\}, p2, \[x0\]
--.*: e470e800 st4b \{z0\.b-z3\.b\}, p2, \[x0\]
--.*: e470e800 st4b \{z0\.b-z3\.b\}, p2, \[x0\]
--.*: e470e800 st4b \{z0\.b-z3\.b\}, p2, \[x0\]
--.*: e470e800 st4b \{z0\.b-z3\.b\}, p2, \[x0\]
--.*: e470fc00 st4b \{z0\.b-z3\.b\}, p7, \[x0\]
--.*: e470fc00 st4b \{z0\.b-z3\.b\}, p7, \[x0\]
--.*: e470fc00 st4b \{z0\.b-z3\.b\}, p7, \[x0\]
--.*: e470fc00 st4b \{z0\.b-z3\.b\}, p7, \[x0\]
--.*: e470fc00 st4b \{z0\.b-z3\.b\}, p7, \[x0\]
--.*: e470fc00 st4b \{z0\.b-z3\.b\}, p7, \[x0\]
--.*: e470fc00 st4b \{z0\.b-z3\.b\}, p7, \[x0\]
--.*: e470e060 st4b \{z0\.b-z3\.b\}, p0, \[x3\]
--.*: e470e060 st4b \{z0\.b-z3\.b\}, p0, \[x3\]
--.*: e470e060 st4b \{z0\.b-z3\.b\}, p0, \[x3\]
--.*: e470e060 st4b \{z0\.b-z3\.b\}, p0, \[x3\]
--.*: e470e060 st4b \{z0\.b-z3\.b\}, p0, \[x3\]
--.*: e470e060 st4b \{z0\.b-z3\.b\}, p0, \[x3\]
--.*: e470e060 st4b \{z0\.b-z3\.b\}, p0, \[x3\]
--.*: e470e3e0 st4b \{z0\.b-z3\.b\}, p0, \[sp\]
--.*: e470e3e0 st4b \{z0\.b-z3\.b\}, p0, \[sp\]
--.*: e470e3e0 st4b \{z0\.b-z3\.b\}, p0, \[sp\]
--.*: e470e3e0 st4b \{z0\.b-z3\.b\}, p0, \[sp\]
--.*: e470e3e0 st4b \{z0\.b-z3\.b\}, p0, \[sp\]
--.*: e470e3e0 st4b \{z0\.b-z3\.b\}, p0, \[sp\]
--.*: e470e3e0 st4b \{z0\.b-z3\.b\}, p0, \[sp\]
--.*: e477e000 st4b \{z0\.b-z3\.b\}, p0, \[x0, #28, mul vl\]
--.*: e477e000 st4b \{z0\.b-z3\.b\}, p0, \[x0, #28, mul vl\]
--.*: e477e000 st4b \{z0\.b-z3\.b\}, p0, \[x0, #28, mul vl\]
--.*: e478e000 st4b \{z0\.b-z3\.b\}, p0, \[x0, #-32, mul vl\]
--.*: e478e000 st4b \{z0\.b-z3\.b\}, p0, \[x0, #-32, mul vl\]
--.*: e478e000 st4b \{z0\.b-z3\.b\}, p0, \[x0, #-32, mul vl\]
--.*: e479e000 st4b \{z0\.b-z3\.b\}, p0, \[x0, #-28, mul vl\]
--.*: e479e000 st4b \{z0\.b-z3\.b\}, p0, \[x0, #-28, mul vl\]
--.*: e479e000 st4b \{z0\.b-z3\.b\}, p0, \[x0, #-28, mul vl\]
--.*: e47fe000 st4b \{z0\.b-z3\.b\}, p0, \[x0, #-4, mul vl\]
--.*: e47fe000 st4b \{z0\.b-z3\.b\}, p0, \[x0, #-4, mul vl\]
--.*: e47fe000 st4b \{z0\.b-z3\.b\}, p0, \[x0, #-4, mul vl\]
--.*: e5e06000 st4d \{z0\.d-z3\.d\}, p0, \[x0, x0, lsl #3\]
--.*: e5e06000 st4d \{z0\.d-z3\.d\}, p0, \[x0, x0, lsl #3\]
--.*: e5e06000 st4d \{z0\.d-z3\.d\}, p0, \[x0, x0, lsl #3\]
--.*: e5e06001 st4d \{z1\.d-z4\.d\}, p0, \[x0, x0, lsl #3\]
--.*: e5e06001 st4d \{z1\.d-z4\.d\}, p0, \[x0, x0, lsl #3\]
--.*: e5e06001 st4d \{z1\.d-z4\.d\}, p0, \[x0, x0, lsl #3\]
--.*: e5e0601f st4d \{z31\.d, z0\.d, z1\.d, z2\.d\}, p0, \[x0, x0, lsl #3\]
--.*: e5e0601f st4d \{z31\.d, z0\.d, z1\.d, z2\.d\}, p0, \[x0, x0, lsl #3\]
--.*: e5e06800 st4d \{z0\.d-z3\.d\}, p2, \[x0, x0, lsl #3\]
--.*: e5e06800 st4d \{z0\.d-z3\.d\}, p2, \[x0, x0, lsl #3\]
--.*: e5e06800 st4d \{z0\.d-z3\.d\}, p2, \[x0, x0, lsl #3\]
--.*: e5e07c00 st4d \{z0\.d-z3\.d\}, p7, \[x0, x0, lsl #3\]
--.*: e5e07c00 st4d \{z0\.d-z3\.d\}, p7, \[x0, x0, lsl #3\]
--.*: e5e07c00 st4d \{z0\.d-z3\.d\}, p7, \[x0, x0, lsl #3\]
--.*: e5e06060 st4d \{z0\.d-z3\.d\}, p0, \[x3, x0, lsl #3\]
--.*: e5e06060 st4d \{z0\.d-z3\.d\}, p0, \[x3, x0, lsl #3\]
--.*: e5e06060 st4d \{z0\.d-z3\.d\}, p0, \[x3, x0, lsl #3\]
--.*: e5e063e0 st4d \{z0\.d-z3\.d\}, p0, \[sp, x0, lsl #3\]
--.*: e5e063e0 st4d \{z0\.d-z3\.d\}, p0, \[sp, x0, lsl #3\]
--.*: e5e063e0 st4d \{z0\.d-z3\.d\}, p0, \[sp, x0, lsl #3\]
--.*: e5e46000 st4d \{z0\.d-z3\.d\}, p0, \[x0, x4, lsl #3\]
--.*: e5e46000 st4d \{z0\.d-z3\.d\}, p0, \[x0, x4, lsl #3\]
--.*: e5e46000 st4d \{z0\.d-z3\.d\}, p0, \[x0, x4, lsl #3\]
--.*: e5fe6000 st4d \{z0\.d-z3\.d\}, p0, \[x0, x30, lsl #3\]
--.*: e5fe6000 st4d \{z0\.d-z3\.d\}, p0, \[x0, x30, lsl #3\]
--.*: e5fe6000 st4d \{z0\.d-z3\.d\}, p0, \[x0, x30, lsl #3\]
--.*: e5f0e000 st4d \{z0\.d-z3\.d\}, p0, \[x0\]
--.*: e5f0e000 st4d \{z0\.d-z3\.d\}, p0, \[x0\]
--.*: e5f0e000 st4d \{z0\.d-z3\.d\}, p0, \[x0\]
--.*: e5f0e000 st4d \{z0\.d-z3\.d\}, p0, \[x0\]
--.*: e5f0e000 st4d \{z0\.d-z3\.d\}, p0, \[x0\]
--.*: e5f0e000 st4d \{z0\.d-z3\.d\}, p0, \[x0\]
--.*: e5f0e000 st4d \{z0\.d-z3\.d\}, p0, \[x0\]
--.*: e5f0e001 st4d \{z1\.d-z4\.d\}, p0, \[x0\]
--.*: e5f0e001 st4d \{z1\.d-z4\.d\}, p0, \[x0\]
--.*: e5f0e001 st4d \{z1\.d-z4\.d\}, p0, \[x0\]
--.*: e5f0e001 st4d \{z1\.d-z4\.d\}, p0, \[x0\]
--.*: e5f0e001 st4d \{z1\.d-z4\.d\}, p0, \[x0\]
--.*: e5f0e001 st4d \{z1\.d-z4\.d\}, p0, \[x0\]
--.*: e5f0e001 st4d \{z1\.d-z4\.d\}, p0, \[x0\]
--.*: e5f0e01f st4d \{z31\.d, z0\.d, z1\.d, z2\.d\}, p0, \[x0\]
--.*: e5f0e01f st4d \{z31\.d, z0\.d, z1\.d, z2\.d\}, p0, \[x0\]
--.*: e5f0e01f st4d \{z31\.d, z0\.d, z1\.d, z2\.d\}, p0, \[x0\]
--.*: e5f0e01f st4d \{z31\.d, z0\.d, z1\.d, z2\.d\}, p0, \[x0\]
--.*: e5f0e800 st4d \{z0\.d-z3\.d\}, p2, \[x0\]
--.*: e5f0e800 st4d \{z0\.d-z3\.d\}, p2, \[x0\]
--.*: e5f0e800 st4d \{z0\.d-z3\.d\}, p2, \[x0\]
--.*: e5f0e800 st4d \{z0\.d-z3\.d\}, p2, \[x0\]
--.*: e5f0e800 st4d \{z0\.d-z3\.d\}, p2, \[x0\]
--.*: e5f0e800 st4d \{z0\.d-z3\.d\}, p2, \[x0\]
--.*: e5f0e800 st4d \{z0\.d-z3\.d\}, p2, \[x0\]
--.*: e5f0fc00 st4d \{z0\.d-z3\.d\}, p7, \[x0\]
--.*: e5f0fc00 st4d \{z0\.d-z3\.d\}, p7, \[x0\]
--.*: e5f0fc00 st4d \{z0\.d-z3\.d\}, p7, \[x0\]
--.*: e5f0fc00 st4d \{z0\.d-z3\.d\}, p7, \[x0\]
--.*: e5f0fc00 st4d \{z0\.d-z3\.d\}, p7, \[x0\]
--.*: e5f0fc00 st4d \{z0\.d-z3\.d\}, p7, \[x0\]
--.*: e5f0fc00 st4d \{z0\.d-z3\.d\}, p7, \[x0\]
--.*: e5f0e060 st4d \{z0\.d-z3\.d\}, p0, \[x3\]
--.*: e5f0e060 st4d \{z0\.d-z3\.d\}, p0, \[x3\]
--.*: e5f0e060 st4d \{z0\.d-z3\.d\}, p0, \[x3\]
--.*: e5f0e060 st4d \{z0\.d-z3\.d\}, p0, \[x3\]
--.*: e5f0e060 st4d \{z0\.d-z3\.d\}, p0, \[x3\]
--.*: e5f0e060 st4d \{z0\.d-z3\.d\}, p0, \[x3\]
--.*: e5f0e060 st4d \{z0\.d-z3\.d\}, p0, \[x3\]
--.*: e5f0e3e0 st4d \{z0\.d-z3\.d\}, p0, \[sp\]
--.*: e5f0e3e0 st4d \{z0\.d-z3\.d\}, p0, \[sp\]
--.*: e5f0e3e0 st4d \{z0\.d-z3\.d\}, p0, \[sp\]
--.*: e5f0e3e0 st4d \{z0\.d-z3\.d\}, p0, \[sp\]
--.*: e5f0e3e0 st4d \{z0\.d-z3\.d\}, p0, \[sp\]
--.*: e5f0e3e0 st4d \{z0\.d-z3\.d\}, p0, \[sp\]
--.*: e5f0e3e0 st4d \{z0\.d-z3\.d\}, p0, \[sp\]
--.*: e5f7e000 st4d \{z0\.d-z3\.d\}, p0, \[x0, #28, mul vl\]
--.*: e5f7e000 st4d \{z0\.d-z3\.d\}, p0, \[x0, #28, mul vl\]
--.*: e5f7e000 st4d \{z0\.d-z3\.d\}, p0, \[x0, #28, mul vl\]
--.*: e5f8e000 st4d \{z0\.d-z3\.d\}, p0, \[x0, #-32, mul vl\]
--.*: e5f8e000 st4d \{z0\.d-z3\.d\}, p0, \[x0, #-32, mul vl\]
--.*: e5f8e000 st4d \{z0\.d-z3\.d\}, p0, \[x0, #-32, mul vl\]
--.*: e5f9e000 st4d \{z0\.d-z3\.d\}, p0, \[x0, #-28, mul vl\]
--.*: e5f9e000 st4d \{z0\.d-z3\.d\}, p0, \[x0, #-28, mul vl\]
--.*: e5f9e000 st4d \{z0\.d-z3\.d\}, p0, \[x0, #-28, mul vl\]
--.*: e5ffe000 st4d \{z0\.d-z3\.d\}, p0, \[x0, #-4, mul vl\]
--.*: e5ffe000 st4d \{z0\.d-z3\.d\}, p0, \[x0, #-4, mul vl\]
--.*: e5ffe000 st4d \{z0\.d-z3\.d\}, p0, \[x0, #-4, mul vl\]
--.*: e4e06000 st4h \{z0\.h-z3\.h\}, p0, \[x0, x0, lsl #1\]
--.*: e4e06000 st4h \{z0\.h-z3\.h\}, p0, \[x0, x0, lsl #1\]
--.*: e4e06000 st4h \{z0\.h-z3\.h\}, p0, \[x0, x0, lsl #1\]
--.*: e4e06001 st4h \{z1\.h-z4\.h\}, p0, \[x0, x0, lsl #1\]
--.*: e4e06001 st4h \{z1\.h-z4\.h\}, p0, \[x0, x0, lsl #1\]
--.*: e4e06001 st4h \{z1\.h-z4\.h\}, p0, \[x0, x0, lsl #1\]
--.*: e4e0601f st4h \{z31\.h, z0\.h, z1\.h, z2\.h\}, p0, \[x0, x0, lsl #1\]
--.*: e4e0601f st4h \{z31\.h, z0\.h, z1\.h, z2\.h\}, p0, \[x0, x0, lsl #1\]
--.*: e4e06800 st4h \{z0\.h-z3\.h\}, p2, \[x0, x0, lsl #1\]
--.*: e4e06800 st4h \{z0\.h-z3\.h\}, p2, \[x0, x0, lsl #1\]
--.*: e4e06800 st4h \{z0\.h-z3\.h\}, p2, \[x0, x0, lsl #1\]
--.*: e4e07c00 st4h \{z0\.h-z3\.h\}, p7, \[x0, x0, lsl #1\]
--.*: e4e07c00 st4h \{z0\.h-z3\.h\}, p7, \[x0, x0, lsl #1\]
--.*: e4e07c00 st4h \{z0\.h-z3\.h\}, p7, \[x0, x0, lsl #1\]
--.*: e4e06060 st4h \{z0\.h-z3\.h\}, p0, \[x3, x0, lsl #1\]
--.*: e4e06060 st4h \{z0\.h-z3\.h\}, p0, \[x3, x0, lsl #1\]
--.*: e4e06060 st4h \{z0\.h-z3\.h\}, p0, \[x3, x0, lsl #1\]
--.*: e4e063e0 st4h \{z0\.h-z3\.h\}, p0, \[sp, x0, lsl #1\]
--.*: e4e063e0 st4h \{z0\.h-z3\.h\}, p0, \[sp, x0, lsl #1\]
--.*: e4e063e0 st4h \{z0\.h-z3\.h\}, p0, \[sp, x0, lsl #1\]
--.*: e4e46000 st4h \{z0\.h-z3\.h\}, p0, \[x0, x4, lsl #1\]
--.*: e4e46000 st4h \{z0\.h-z3\.h\}, p0, \[x0, x4, lsl #1\]
--.*: e4e46000 st4h \{z0\.h-z3\.h\}, p0, \[x0, x4, lsl #1\]
--.*: e4fe6000 st4h \{z0\.h-z3\.h\}, p0, \[x0, x30, lsl #1\]
--.*: e4fe6000 st4h \{z0\.h-z3\.h\}, p0, \[x0, x30, lsl #1\]
--.*: e4fe6000 st4h \{z0\.h-z3\.h\}, p0, \[x0, x30, lsl #1\]
--.*: e4f0e000 st4h \{z0\.h-z3\.h\}, p0, \[x0\]
--.*: e4f0e000 st4h \{z0\.h-z3\.h\}, p0, \[x0\]
--.*: e4f0e000 st4h \{z0\.h-z3\.h\}, p0, \[x0\]
--.*: e4f0e000 st4h \{z0\.h-z3\.h\}, p0, \[x0\]
--.*: e4f0e000 st4h \{z0\.h-z3\.h\}, p0, \[x0\]
--.*: e4f0e000 st4h \{z0\.h-z3\.h\}, p0, \[x0\]
--.*: e4f0e000 st4h \{z0\.h-z3\.h\}, p0, \[x0\]
--.*: e4f0e001 st4h \{z1\.h-z4\.h\}, p0, \[x0\]
--.*: e4f0e001 st4h \{z1\.h-z4\.h\}, p0, \[x0\]
--.*: e4f0e001 st4h \{z1\.h-z4\.h\}, p0, \[x0\]
--.*: e4f0e001 st4h \{z1\.h-z4\.h\}, p0, \[x0\]
--.*: e4f0e001 st4h \{z1\.h-z4\.h\}, p0, \[x0\]
--.*: e4f0e001 st4h \{z1\.h-z4\.h\}, p0, \[x0\]
--.*: e4f0e001 st4h \{z1\.h-z4\.h\}, p0, \[x0\]
--.*: e4f0e01f st4h \{z31\.h, z0\.h, z1\.h, z2\.h\}, p0, \[x0\]
--.*: e4f0e01f st4h \{z31\.h, z0\.h, z1\.h, z2\.h\}, p0, \[x0\]
--.*: e4f0e01f st4h \{z31\.h, z0\.h, z1\.h, z2\.h\}, p0, \[x0\]
--.*: e4f0e01f st4h \{z31\.h, z0\.h, z1\.h, z2\.h\}, p0, \[x0\]
--.*: e4f0e800 st4h \{z0\.h-z3\.h\}, p2, \[x0\]
--.*: e4f0e800 st4h \{z0\.h-z3\.h\}, p2, \[x0\]
--.*: e4f0e800 st4h \{z0\.h-z3\.h\}, p2, \[x0\]
--.*: e4f0e800 st4h \{z0\.h-z3\.h\}, p2, \[x0\]
--.*: e4f0e800 st4h \{z0\.h-z3\.h\}, p2, \[x0\]
--.*: e4f0e800 st4h \{z0\.h-z3\.h\}, p2, \[x0\]
--.*: e4f0e800 st4h \{z0\.h-z3\.h\}, p2, \[x0\]
--.*: e4f0fc00 st4h \{z0\.h-z3\.h\}, p7, \[x0\]
--.*: e4f0fc00 st4h \{z0\.h-z3\.h\}, p7, \[x0\]
--.*: e4f0fc00 st4h \{z0\.h-z3\.h\}, p7, \[x0\]
--.*: e4f0fc00 st4h \{z0\.h-z3\.h\}, p7, \[x0\]
--.*: e4f0fc00 st4h \{z0\.h-z3\.h\}, p7, \[x0\]
--.*: e4f0fc00 st4h \{z0\.h-z3\.h\}, p7, \[x0\]
--.*: e4f0fc00 st4h \{z0\.h-z3\.h\}, p7, \[x0\]
--.*: e4f0e060 st4h \{z0\.h-z3\.h\}, p0, \[x3\]
--.*: e4f0e060 st4h \{z0\.h-z3\.h\}, p0, \[x3\]
--.*: e4f0e060 st4h \{z0\.h-z3\.h\}, p0, \[x3\]
--.*: e4f0e060 st4h \{z0\.h-z3\.h\}, p0, \[x3\]
--.*: e4f0e060 st4h \{z0\.h-z3\.h\}, p0, \[x3\]
--.*: e4f0e060 st4h \{z0\.h-z3\.h\}, p0, \[x3\]
--.*: e4f0e060 st4h \{z0\.h-z3\.h\}, p0, \[x3\]
--.*: e4f0e3e0 st4h \{z0\.h-z3\.h\}, p0, \[sp\]
--.*: e4f0e3e0 st4h \{z0\.h-z3\.h\}, p0, \[sp\]
--.*: e4f0e3e0 st4h \{z0\.h-z3\.h\}, p0, \[sp\]
--.*: e4f0e3e0 st4h \{z0\.h-z3\.h\}, p0, \[sp\]
--.*: e4f0e3e0 st4h \{z0\.h-z3\.h\}, p0, \[sp\]
--.*: e4f0e3e0 st4h \{z0\.h-z3\.h\}, p0, \[sp\]
--.*: e4f0e3e0 st4h \{z0\.h-z3\.h\}, p0, \[sp\]
--.*: e4f7e000 st4h \{z0\.h-z3\.h\}, p0, \[x0, #28, mul vl\]
--.*: e4f7e000 st4h \{z0\.h-z3\.h\}, p0, \[x0, #28, mul vl\]
--.*: e4f7e000 st4h \{z0\.h-z3\.h\}, p0, \[x0, #28, mul vl\]
--.*: e4f8e000 st4h \{z0\.h-z3\.h\}, p0, \[x0, #-32, mul vl\]
--.*: e4f8e000 st4h \{z0\.h-z3\.h\}, p0, \[x0, #-32, mul vl\]
--.*: e4f8e000 st4h \{z0\.h-z3\.h\}, p0, \[x0, #-32, mul vl\]
--.*: e4f9e000 st4h \{z0\.h-z3\.h\}, p0, \[x0, #-28, mul vl\]
--.*: e4f9e000 st4h \{z0\.h-z3\.h\}, p0, \[x0, #-28, mul vl\]
--.*: e4f9e000 st4h \{z0\.h-z3\.h\}, p0, \[x0, #-28, mul vl\]
--.*: e4ffe000 st4h \{z0\.h-z3\.h\}, p0, \[x0, #-4, mul vl\]
--.*: e4ffe000 st4h \{z0\.h-z3\.h\}, p0, \[x0, #-4, mul vl\]
--.*: e4ffe000 st4h \{z0\.h-z3\.h\}, p0, \[x0, #-4, mul vl\]
--.*: e5606000 st4w \{z0\.s-z3\.s\}, p0, \[x0, x0, lsl #2\]
--.*: e5606000 st4w \{z0\.s-z3\.s\}, p0, \[x0, x0, lsl #2\]
--.*: e5606000 st4w \{z0\.s-z3\.s\}, p0, \[x0, x0, lsl #2\]
--.*: e5606001 st4w \{z1\.s-z4\.s\}, p0, \[x0, x0, lsl #2\]
--.*: e5606001 st4w \{z1\.s-z4\.s\}, p0, \[x0, x0, lsl #2\]
--.*: e5606001 st4w \{z1\.s-z4\.s\}, p0, \[x0, x0, lsl #2\]
--.*: e560601f st4w \{z31\.s, z0\.s, z1\.s, z2\.s\}, p0, \[x0, x0, lsl #2\]
--.*: e560601f st4w \{z31\.s, z0\.s, z1\.s, z2\.s\}, p0, \[x0, x0, lsl #2\]
--.*: e5606800 st4w \{z0\.s-z3\.s\}, p2, \[x0, x0, lsl #2\]
--.*: e5606800 st4w \{z0\.s-z3\.s\}, p2, \[x0, x0, lsl #2\]
--.*: e5606800 st4w \{z0\.s-z3\.s\}, p2, \[x0, x0, lsl #2\]
--.*: e5607c00 st4w \{z0\.s-z3\.s\}, p7, \[x0, x0, lsl #2\]
--.*: e5607c00 st4w \{z0\.s-z3\.s\}, p7, \[x0, x0, lsl #2\]
--.*: e5607c00 st4w \{z0\.s-z3\.s\}, p7, \[x0, x0, lsl #2\]
--.*: e5606060 st4w \{z0\.s-z3\.s\}, p0, \[x3, x0, lsl #2\]
--.*: e5606060 st4w \{z0\.s-z3\.s\}, p0, \[x3, x0, lsl #2\]
--.*: e5606060 st4w \{z0\.s-z3\.s\}, p0, \[x3, x0, lsl #2\]
--.*: e56063e0 st4w \{z0\.s-z3\.s\}, p0, \[sp, x0, lsl #2\]
--.*: e56063e0 st4w \{z0\.s-z3\.s\}, p0, \[sp, x0, lsl #2\]
--.*: e56063e0 st4w \{z0\.s-z3\.s\}, p0, \[sp, x0, lsl #2\]
--.*: e5646000 st4w \{z0\.s-z3\.s\}, p0, \[x0, x4, lsl #2\]
--.*: e5646000 st4w \{z0\.s-z3\.s\}, p0, \[x0, x4, lsl #2\]
--.*: e5646000 st4w \{z0\.s-z3\.s\}, p0, \[x0, x4, lsl #2\]
--.*: e57e6000 st4w \{z0\.s-z3\.s\}, p0, \[x0, x30, lsl #2\]
--.*: e57e6000 st4w \{z0\.s-z3\.s\}, p0, \[x0, x30, lsl #2\]
--.*: e57e6000 st4w \{z0\.s-z3\.s\}, p0, \[x0, x30, lsl #2\]
--.*: e570e000 st4w \{z0\.s-z3\.s\}, p0, \[x0\]
--.*: e570e000 st4w \{z0\.s-z3\.s\}, p0, \[x0\]
--.*: e570e000 st4w \{z0\.s-z3\.s\}, p0, \[x0\]
--.*: e570e000 st4w \{z0\.s-z3\.s\}, p0, \[x0\]
--.*: e570e000 st4w \{z0\.s-z3\.s\}, p0, \[x0\]
--.*: e570e000 st4w \{z0\.s-z3\.s\}, p0, \[x0\]
--.*: e570e000 st4w \{z0\.s-z3\.s\}, p0, \[x0\]
--.*: e570e001 st4w \{z1\.s-z4\.s\}, p0, \[x0\]
--.*: e570e001 st4w \{z1\.s-z4\.s\}, p0, \[x0\]
--.*: e570e001 st4w \{z1\.s-z4\.s\}, p0, \[x0\]
--.*: e570e001 st4w \{z1\.s-z4\.s\}, p0, \[x0\]
--.*: e570e001 st4w \{z1\.s-z4\.s\}, p0, \[x0\]
--.*: e570e001 st4w \{z1\.s-z4\.s\}, p0, \[x0\]
--.*: e570e001 st4w \{z1\.s-z4\.s\}, p0, \[x0\]
--.*: e570e01f st4w \{z31\.s, z0\.s, z1\.s, z2\.s\}, p0, \[x0\]
--.*: e570e01f st4w \{z31\.s, z0\.s, z1\.s, z2\.s\}, p0, \[x0\]
--.*: e570e01f st4w \{z31\.s, z0\.s, z1\.s, z2\.s\}, p0, \[x0\]
--.*: e570e01f st4w \{z31\.s, z0\.s, z1\.s, z2\.s\}, p0, \[x0\]
--.*: e570e800 st4w \{z0\.s-z3\.s\}, p2, \[x0\]
--.*: e570e800 st4w \{z0\.s-z3\.s\}, p2, \[x0\]
--.*: e570e800 st4w \{z0\.s-z3\.s\}, p2, \[x0\]
--.*: e570e800 st4w \{z0\.s-z3\.s\}, p2, \[x0\]
--.*: e570e800 st4w \{z0\.s-z3\.s\}, p2, \[x0\]
--.*: e570e800 st4w \{z0\.s-z3\.s\}, p2, \[x0\]
--.*: e570e800 st4w \{z0\.s-z3\.s\}, p2, \[x0\]
--.*: e570fc00 st4w \{z0\.s-z3\.s\}, p7, \[x0\]
--.*: e570fc00 st4w \{z0\.s-z3\.s\}, p7, \[x0\]
--.*: e570fc00 st4w \{z0\.s-z3\.s\}, p7, \[x0\]
--.*: e570fc00 st4w \{z0\.s-z3\.s\}, p7, \[x0\]
--.*: e570fc00 st4w \{z0\.s-z3\.s\}, p7, \[x0\]
--.*: e570fc00 st4w \{z0\.s-z3\.s\}, p7, \[x0\]
--.*: e570fc00 st4w \{z0\.s-z3\.s\}, p7, \[x0\]
--.*: e570e060 st4w \{z0\.s-z3\.s\}, p0, \[x3\]
--.*: e570e060 st4w \{z0\.s-z3\.s\}, p0, \[x3\]
--.*: e570e060 st4w \{z0\.s-z3\.s\}, p0, \[x3\]
--.*: e570e060 st4w \{z0\.s-z3\.s\}, p0, \[x3\]
--.*: e570e060 st4w \{z0\.s-z3\.s\}, p0, \[x3\]
--.*: e570e060 st4w \{z0\.s-z3\.s\}, p0, \[x3\]
--.*: e570e060 st4w \{z0\.s-z3\.s\}, p0, \[x3\]
--.*: e570e3e0 st4w \{z0\.s-z3\.s\}, p0, \[sp\]
--.*: e570e3e0 st4w \{z0\.s-z3\.s\}, p0, \[sp\]
--.*: e570e3e0 st4w \{z0\.s-z3\.s\}, p0, \[sp\]
--.*: e570e3e0 st4w \{z0\.s-z3\.s\}, p0, \[sp\]
--.*: e570e3e0 st4w \{z0\.s-z3\.s\}, p0, \[sp\]
--.*: e570e3e0 st4w \{z0\.s-z3\.s\}, p0, \[sp\]
--.*: e570e3e0 st4w \{z0\.s-z3\.s\}, p0, \[sp\]
--.*: e577e000 st4w \{z0\.s-z3\.s\}, p0, \[x0, #28, mul vl\]
--.*: e577e000 st4w \{z0\.s-z3\.s\}, p0, \[x0, #28, mul vl\]
--.*: e577e000 st4w \{z0\.s-z3\.s\}, p0, \[x0, #28, mul vl\]
--.*: e578e000 st4w \{z0\.s-z3\.s\}, p0, \[x0, #-32, mul vl\]
--.*: e578e000 st4w \{z0\.s-z3\.s\}, p0, \[x0, #-32, mul vl\]
--.*: e578e000 st4w \{z0\.s-z3\.s\}, p0, \[x0, #-32, mul vl\]
--.*: e579e000 st4w \{z0\.s-z3\.s\}, p0, \[x0, #-28, mul vl\]
--.*: e579e000 st4w \{z0\.s-z3\.s\}, p0, \[x0, #-28, mul vl\]
--.*: e579e000 st4w \{z0\.s-z3\.s\}, p0, \[x0, #-28, mul vl\]
--.*: e57fe000 st4w \{z0\.s-z3\.s\}, p0, \[x0, #-4, mul vl\]
--.*: e57fe000 st4w \{z0\.s-z3\.s\}, p0, \[x0, #-4, mul vl\]
--.*: e57fe000 st4w \{z0\.s-z3\.s\}, p0, \[x0, #-4, mul vl\]
--.*: e4006000 stnt1b \{z0\.b\}, p0, \[x0, x0\]
--.*: e4006000 stnt1b \{z0\.b\}, p0, \[x0, x0\]
--.*: e4006000 stnt1b \{z0\.b\}, p0, \[x0, x0\]
--.*: e4006000 stnt1b \{z0\.b\}, p0, \[x0, x0\]
--.*: e4006001 stnt1b \{z1\.b\}, p0, \[x0, x0\]
--.*: e4006001 stnt1b \{z1\.b\}, p0, \[x0, x0\]
--.*: e4006001 stnt1b \{z1\.b\}, p0, \[x0, x0\]
--.*: e4006001 stnt1b \{z1\.b\}, p0, \[x0, x0\]
--.*: e400601f stnt1b \{z31\.b\}, p0, \[x0, x0\]
--.*: e400601f stnt1b \{z31\.b\}, p0, \[x0, x0\]
--.*: e400601f stnt1b \{z31\.b\}, p0, \[x0, x0\]
--.*: e400601f stnt1b \{z31\.b\}, p0, \[x0, x0\]
--.*: e4006800 stnt1b \{z0\.b\}, p2, \[x0, x0\]
--.*: e4006800 stnt1b \{z0\.b\}, p2, \[x0, x0\]
--.*: e4006800 stnt1b \{z0\.b\}, p2, \[x0, x0\]
--.*: e4007c00 stnt1b \{z0\.b\}, p7, \[x0, x0\]
--.*: e4007c00 stnt1b \{z0\.b\}, p7, \[x0, x0\]
--.*: e4007c00 stnt1b \{z0\.b\}, p7, \[x0, x0\]
--.*: e4006060 stnt1b \{z0\.b\}, p0, \[x3, x0\]
--.*: e4006060 stnt1b \{z0\.b\}, p0, \[x3, x0\]
--.*: e4006060 stnt1b \{z0\.b\}, p0, \[x3, x0\]
--.*: e40063e0 stnt1b \{z0\.b\}, p0, \[sp, x0\]
--.*: e40063e0 stnt1b \{z0\.b\}, p0, \[sp, x0\]
--.*: e40063e0 stnt1b \{z0\.b\}, p0, \[sp, x0\]
--.*: e4046000 stnt1b \{z0\.b\}, p0, \[x0, x4\]
--.*: e4046000 stnt1b \{z0\.b\}, p0, \[x0, x4\]
--.*: e4046000 stnt1b \{z0\.b\}, p0, \[x0, x4\]
--.*: e41e6000 stnt1b \{z0\.b\}, p0, \[x0, x30\]
--.*: e41e6000 stnt1b \{z0\.b\}, p0, \[x0, x30\]
--.*: e41e6000 stnt1b \{z0\.b\}, p0, \[x0, x30\]
--.*: e410e000 stnt1b \{z0\.b\}, p0, \[x0\]
--.*: e410e000 stnt1b \{z0\.b\}, p0, \[x0\]
--.*: e410e000 stnt1b \{z0\.b\}, p0, \[x0\]
--.*: e410e000 stnt1b \{z0\.b\}, p0, \[x0\]
--.*: e410e000 stnt1b \{z0\.b\}, p0, \[x0\]
--.*: e410e001 stnt1b \{z1\.b\}, p0, \[x0\]
--.*: e410e001 stnt1b \{z1\.b\}, p0, \[x0\]
--.*: e410e001 stnt1b \{z1\.b\}, p0, \[x0\]
--.*: e410e001 stnt1b \{z1\.b\}, p0, \[x0\]
--.*: e410e001 stnt1b \{z1\.b\}, p0, \[x0\]
--.*: e410e01f stnt1b \{z31\.b\}, p0, \[x0\]
--.*: e410e01f stnt1b \{z31\.b\}, p0, \[x0\]
--.*: e410e01f stnt1b \{z31\.b\}, p0, \[x0\]
--.*: e410e01f stnt1b \{z31\.b\}, p0, \[x0\]
--.*: e410e01f stnt1b \{z31\.b\}, p0, \[x0\]
--.*: e410e800 stnt1b \{z0\.b\}, p2, \[x0\]
--.*: e410e800 stnt1b \{z0\.b\}, p2, \[x0\]
--.*: e410e800 stnt1b \{z0\.b\}, p2, \[x0\]
--.*: e410e800 stnt1b \{z0\.b\}, p2, \[x0\]
--.*: e410fc00 stnt1b \{z0\.b\}, p7, \[x0\]
--.*: e410fc00 stnt1b \{z0\.b\}, p7, \[x0\]
--.*: e410fc00 stnt1b \{z0\.b\}, p7, \[x0\]
--.*: e410fc00 stnt1b \{z0\.b\}, p7, \[x0\]
--.*: e410e060 stnt1b \{z0\.b\}, p0, \[x3\]
--.*: e410e060 stnt1b \{z0\.b\}, p0, \[x3\]
--.*: e410e060 stnt1b \{z0\.b\}, p0, \[x3\]
--.*: e410e060 stnt1b \{z0\.b\}, p0, \[x3\]
--.*: e410e3e0 stnt1b \{z0\.b\}, p0, \[sp\]
--.*: e410e3e0 stnt1b \{z0\.b\}, p0, \[sp\]
--.*: e410e3e0 stnt1b \{z0\.b\}, p0, \[sp\]
--.*: e410e3e0 stnt1b \{z0\.b\}, p0, \[sp\]
--.*: e417e000 stnt1b \{z0\.b\}, p0, \[x0, #7, mul vl\]
--.*: e417e000 stnt1b \{z0\.b\}, p0, \[x0, #7, mul vl\]
--.*: e418e000 stnt1b \{z0\.b\}, p0, \[x0, #-8, mul vl\]
--.*: e418e000 stnt1b \{z0\.b\}, p0, \[x0, #-8, mul vl\]
--.*: e419e000 stnt1b \{z0\.b\}, p0, \[x0, #-7, mul vl\]
--.*: e419e000 stnt1b \{z0\.b\}, p0, \[x0, #-7, mul vl\]
--.*: e41fe000 stnt1b \{z0\.b\}, p0, \[x0, #-1, mul vl\]
--.*: e41fe000 stnt1b \{z0\.b\}, p0, \[x0, #-1, mul vl\]
--.*: e5806000 stnt1d \{z0\.d\}, p0, \[x0, x0, lsl #3\]
--.*: e5806000 stnt1d \{z0\.d\}, p0, \[x0, x0, lsl #3\]
--.*: e5806000 stnt1d \{z0\.d\}, p0, \[x0, x0, lsl #3\]
--.*: e5806001 stnt1d \{z1\.d\}, p0, \[x0, x0, lsl #3\]
--.*: e5806001 stnt1d \{z1\.d\}, p0, \[x0, x0, lsl #3\]
--.*: e5806001 stnt1d \{z1\.d\}, p0, \[x0, x0, lsl #3\]
--.*: e580601f stnt1d \{z31\.d\}, p0, \[x0, x0, lsl #3\]
--.*: e580601f stnt1d \{z31\.d\}, p0, \[x0, x0, lsl #3\]
--.*: e580601f stnt1d \{z31\.d\}, p0, \[x0, x0, lsl #3\]
--.*: e5806800 stnt1d \{z0\.d\}, p2, \[x0, x0, lsl #3\]
--.*: e5806800 stnt1d \{z0\.d\}, p2, \[x0, x0, lsl #3\]
--.*: e5807c00 stnt1d \{z0\.d\}, p7, \[x0, x0, lsl #3\]
--.*: e5807c00 stnt1d \{z0\.d\}, p7, \[x0, x0, lsl #3\]
--.*: e5806060 stnt1d \{z0\.d\}, p0, \[x3, x0, lsl #3\]
--.*: e5806060 stnt1d \{z0\.d\}, p0, \[x3, x0, lsl #3\]
--.*: e58063e0 stnt1d \{z0\.d\}, p0, \[sp, x0, lsl #3\]
--.*: e58063e0 stnt1d \{z0\.d\}, p0, \[sp, x0, lsl #3\]
--.*: e5846000 stnt1d \{z0\.d\}, p0, \[x0, x4, lsl #3\]
--.*: e5846000 stnt1d \{z0\.d\}, p0, \[x0, x4, lsl #3\]
--.*: e59e6000 stnt1d \{z0\.d\}, p0, \[x0, x30, lsl #3\]
--.*: e59e6000 stnt1d \{z0\.d\}, p0, \[x0, x30, lsl #3\]
--.*: e590e000 stnt1d \{z0\.d\}, p0, \[x0\]
--.*: e590e000 stnt1d \{z0\.d\}, p0, \[x0\]
--.*: e590e000 stnt1d \{z0\.d\}, p0, \[x0\]
--.*: e590e000 stnt1d \{z0\.d\}, p0, \[x0\]
--.*: e590e000 stnt1d \{z0\.d\}, p0, \[x0\]
--.*: e590e001 stnt1d \{z1\.d\}, p0, \[x0\]
--.*: e590e001 stnt1d \{z1\.d\}, p0, \[x0\]
--.*: e590e001 stnt1d \{z1\.d\}, p0, \[x0\]
--.*: e590e001 stnt1d \{z1\.d\}, p0, \[x0\]
--.*: e590e001 stnt1d \{z1\.d\}, p0, \[x0\]
--.*: e590e01f stnt1d \{z31\.d\}, p0, \[x0\]
--.*: e590e01f stnt1d \{z31\.d\}, p0, \[x0\]
--.*: e590e01f stnt1d \{z31\.d\}, p0, \[x0\]
--.*: e590e01f stnt1d \{z31\.d\}, p0, \[x0\]
--.*: e590e01f stnt1d \{z31\.d\}, p0, \[x0\]
--.*: e590e800 stnt1d \{z0\.d\}, p2, \[x0\]
--.*: e590e800 stnt1d \{z0\.d\}, p2, \[x0\]
--.*: e590e800 stnt1d \{z0\.d\}, p2, \[x0\]
--.*: e590e800 stnt1d \{z0\.d\}, p2, \[x0\]
--.*: e590fc00 stnt1d \{z0\.d\}, p7, \[x0\]
--.*: e590fc00 stnt1d \{z0\.d\}, p7, \[x0\]
--.*: e590fc00 stnt1d \{z0\.d\}, p7, \[x0\]
--.*: e590fc00 stnt1d \{z0\.d\}, p7, \[x0\]
--.*: e590e060 stnt1d \{z0\.d\}, p0, \[x3\]
--.*: e590e060 stnt1d \{z0\.d\}, p0, \[x3\]
--.*: e590e060 stnt1d \{z0\.d\}, p0, \[x3\]
--.*: e590e060 stnt1d \{z0\.d\}, p0, \[x3\]
--.*: e590e3e0 stnt1d \{z0\.d\}, p0, \[sp\]
--.*: e590e3e0 stnt1d \{z0\.d\}, p0, \[sp\]
--.*: e590e3e0 stnt1d \{z0\.d\}, p0, \[sp\]
--.*: e590e3e0 stnt1d \{z0\.d\}, p0, \[sp\]
--.*: e597e000 stnt1d \{z0\.d\}, p0, \[x0, #7, mul vl\]
--.*: e597e000 stnt1d \{z0\.d\}, p0, \[x0, #7, mul vl\]
--.*: e598e000 stnt1d \{z0\.d\}, p0, \[x0, #-8, mul vl\]
--.*: e598e000 stnt1d \{z0\.d\}, p0, \[x0, #-8, mul vl\]
--.*: e599e000 stnt1d \{z0\.d\}, p0, \[x0, #-7, mul vl\]
--.*: e599e000 stnt1d \{z0\.d\}, p0, \[x0, #-7, mul vl\]
--.*: e59fe000 stnt1d \{z0\.d\}, p0, \[x0, #-1, mul vl\]
--.*: e59fe000 stnt1d \{z0\.d\}, p0, \[x0, #-1, mul vl\]
--.*: e4806000 stnt1h \{z0\.h\}, p0, \[x0, x0, lsl #1\]
--.*: e4806000 stnt1h \{z0\.h\}, p0, \[x0, x0, lsl #1\]
--.*: e4806000 stnt1h \{z0\.h\}, p0, \[x0, x0, lsl #1\]
--.*: e4806001 stnt1h \{z1\.h\}, p0, \[x0, x0, lsl #1\]
--.*: e4806001 stnt1h \{z1\.h\}, p0, \[x0, x0, lsl #1\]
--.*: e4806001 stnt1h \{z1\.h\}, p0, \[x0, x0, lsl #1\]
--.*: e480601f stnt1h \{z31\.h\}, p0, \[x0, x0, lsl #1\]
--.*: e480601f stnt1h \{z31\.h\}, p0, \[x0, x0, lsl #1\]
--.*: e480601f stnt1h \{z31\.h\}, p0, \[x0, x0, lsl #1\]
--.*: e4806800 stnt1h \{z0\.h\}, p2, \[x0, x0, lsl #1\]
--.*: e4806800 stnt1h \{z0\.h\}, p2, \[x0, x0, lsl #1\]
--.*: e4807c00 stnt1h \{z0\.h\}, p7, \[x0, x0, lsl #1\]
--.*: e4807c00 stnt1h \{z0\.h\}, p7, \[x0, x0, lsl #1\]
--.*: e4806060 stnt1h \{z0\.h\}, p0, \[x3, x0, lsl #1\]
--.*: e4806060 stnt1h \{z0\.h\}, p0, \[x3, x0, lsl #1\]
--.*: e48063e0 stnt1h \{z0\.h\}, p0, \[sp, x0, lsl #1\]
--.*: e48063e0 stnt1h \{z0\.h\}, p0, \[sp, x0, lsl #1\]
--.*: e4846000 stnt1h \{z0\.h\}, p0, \[x0, x4, lsl #1\]
--.*: e4846000 stnt1h \{z0\.h\}, p0, \[x0, x4, lsl #1\]
--.*: e49e6000 stnt1h \{z0\.h\}, p0, \[x0, x30, lsl #1\]
--.*: e49e6000 stnt1h \{z0\.h\}, p0, \[x0, x30, lsl #1\]
--.*: e490e000 stnt1h \{z0\.h\}, p0, \[x0\]
--.*: e490e000 stnt1h \{z0\.h\}, p0, \[x0\]
--.*: e490e000 stnt1h \{z0\.h\}, p0, \[x0\]
--.*: e490e000 stnt1h \{z0\.h\}, p0, \[x0\]
--.*: e490e000 stnt1h \{z0\.h\}, p0, \[x0\]
--.*: e490e001 stnt1h \{z1\.h\}, p0, \[x0\]
--.*: e490e001 stnt1h \{z1\.h\}, p0, \[x0\]
--.*: e490e001 stnt1h \{z1\.h\}, p0, \[x0\]
--.*: e490e001 stnt1h \{z1\.h\}, p0, \[x0\]
--.*: e490e001 stnt1h \{z1\.h\}, p0, \[x0\]
--.*: e490e01f stnt1h \{z31\.h\}, p0, \[x0\]
--.*: e490e01f stnt1h \{z31\.h\}, p0, \[x0\]
--.*: e490e01f stnt1h \{z31\.h\}, p0, \[x0\]
--.*: e490e01f stnt1h \{z31\.h\}, p0, \[x0\]
--.*: e490e01f stnt1h \{z31\.h\}, p0, \[x0\]
--.*: e490e800 stnt1h \{z0\.h\}, p2, \[x0\]
--.*: e490e800 stnt1h \{z0\.h\}, p2, \[x0\]
--.*: e490e800 stnt1h \{z0\.h\}, p2, \[x0\]
--.*: e490e800 stnt1h \{z0\.h\}, p2, \[x0\]
--.*: e490fc00 stnt1h \{z0\.h\}, p7, \[x0\]
--.*: e490fc00 stnt1h \{z0\.h\}, p7, \[x0\]
--.*: e490fc00 stnt1h \{z0\.h\}, p7, \[x0\]
--.*: e490fc00 stnt1h \{z0\.h\}, p7, \[x0\]
--.*: e490e060 stnt1h \{z0\.h\}, p0, \[x3\]
--.*: e490e060 stnt1h \{z0\.h\}, p0, \[x3\]
--.*: e490e060 stnt1h \{z0\.h\}, p0, \[x3\]
--.*: e490e060 stnt1h \{z0\.h\}, p0, \[x3\]
--.*: e490e3e0 stnt1h \{z0\.h\}, p0, \[sp\]
--.*: e490e3e0 stnt1h \{z0\.h\}, p0, \[sp\]
--.*: e490e3e0 stnt1h \{z0\.h\}, p0, \[sp\]
--.*: e490e3e0 stnt1h \{z0\.h\}, p0, \[sp\]
--.*: e497e000 stnt1h \{z0\.h\}, p0, \[x0, #7, mul vl\]
--.*: e497e000 stnt1h \{z0\.h\}, p0, \[x0, #7, mul vl\]
--.*: e498e000 stnt1h \{z0\.h\}, p0, \[x0, #-8, mul vl\]
--.*: e498e000 stnt1h \{z0\.h\}, p0, \[x0, #-8, mul vl\]
--.*: e499e000 stnt1h \{z0\.h\}, p0, \[x0, #-7, mul vl\]
--.*: e499e000 stnt1h \{z0\.h\}, p0, \[x0, #-7, mul vl\]
--.*: e49fe000 stnt1h \{z0\.h\}, p0, \[x0, #-1, mul vl\]
--.*: e49fe000 stnt1h \{z0\.h\}, p0, \[x0, #-1, mul vl\]
--.*: e5006000 stnt1w \{z0\.s\}, p0, \[x0, x0, lsl #2\]
--.*: e5006000 stnt1w \{z0\.s\}, p0, \[x0, x0, lsl #2\]
--.*: e5006000 stnt1w \{z0\.s\}, p0, \[x0, x0, lsl #2\]
--.*: e5006001 stnt1w \{z1\.s\}, p0, \[x0, x0, lsl #2\]
--.*: e5006001 stnt1w \{z1\.s\}, p0, \[x0, x0, lsl #2\]
--.*: e5006001 stnt1w \{z1\.s\}, p0, \[x0, x0, lsl #2\]
--.*: e500601f stnt1w \{z31\.s\}, p0, \[x0, x0, lsl #2\]
--.*: e500601f stnt1w \{z31\.s\}, p0, \[x0, x0, lsl #2\]
--.*: e500601f stnt1w \{z31\.s\}, p0, \[x0, x0, lsl #2\]
--.*: e5006800 stnt1w \{z0\.s\}, p2, \[x0, x0, lsl #2\]
--.*: e5006800 stnt1w \{z0\.s\}, p2, \[x0, x0, lsl #2\]
--.*: e5007c00 stnt1w \{z0\.s\}, p7, \[x0, x0, lsl #2\]
--.*: e5007c00 stnt1w \{z0\.s\}, p7, \[x0, x0, lsl #2\]
--.*: e5006060 stnt1w \{z0\.s\}, p0, \[x3, x0, lsl #2\]
--.*: e5006060 stnt1w \{z0\.s\}, p0, \[x3, x0, lsl #2\]
--.*: e50063e0 stnt1w \{z0\.s\}, p0, \[sp, x0, lsl #2\]
--.*: e50063e0 stnt1w \{z0\.s\}, p0, \[sp, x0, lsl #2\]
--.*: e5046000 stnt1w \{z0\.s\}, p0, \[x0, x4, lsl #2\]
--.*: e5046000 stnt1w \{z0\.s\}, p0, \[x0, x4, lsl #2\]
--.*: e51e6000 stnt1w \{z0\.s\}, p0, \[x0, x30, lsl #2\]
--.*: e51e6000 stnt1w \{z0\.s\}, p0, \[x0, x30, lsl #2\]
--.*: e510e000 stnt1w \{z0\.s\}, p0, \[x0\]
--.*: e510e000 stnt1w \{z0\.s\}, p0, \[x0\]
--.*: e510e000 stnt1w \{z0\.s\}, p0, \[x0\]
--.*: e510e000 stnt1w \{z0\.s\}, p0, \[x0\]
--.*: e510e000 stnt1w \{z0\.s\}, p0, \[x0\]
--.*: e510e001 stnt1w \{z1\.s\}, p0, \[x0\]
--.*: e510e001 stnt1w \{z1\.s\}, p0, \[x0\]
--.*: e510e001 stnt1w \{z1\.s\}, p0, \[x0\]
--.*: e510e001 stnt1w \{z1\.s\}, p0, \[x0\]
--.*: e510e001 stnt1w \{z1\.s\}, p0, \[x0\]
--.*: e510e01f stnt1w \{z31\.s\}, p0, \[x0\]
--.*: e510e01f stnt1w \{z31\.s\}, p0, \[x0\]
--.*: e510e01f stnt1w \{z31\.s\}, p0, \[x0\]
--.*: e510e01f stnt1w \{z31\.s\}, p0, \[x0\]
--.*: e510e01f stnt1w \{z31\.s\}, p0, \[x0\]
--.*: e510e800 stnt1w \{z0\.s\}, p2, \[x0\]
--.*: e510e800 stnt1w \{z0\.s\}, p2, \[x0\]
--.*: e510e800 stnt1w \{z0\.s\}, p2, \[x0\]
--.*: e510e800 stnt1w \{z0\.s\}, p2, \[x0\]
--.*: e510fc00 stnt1w \{z0\.s\}, p7, \[x0\]
--.*: e510fc00 stnt1w \{z0\.s\}, p7, \[x0\]
--.*: e510fc00 stnt1w \{z0\.s\}, p7, \[x0\]
--.*: e510fc00 stnt1w \{z0\.s\}, p7, \[x0\]
--.*: e510e060 stnt1w \{z0\.s\}, p0, \[x3\]
--.*: e510e060 stnt1w \{z0\.s\}, p0, \[x3\]
--.*: e510e060 stnt1w \{z0\.s\}, p0, \[x3\]
--.*: e510e060 stnt1w \{z0\.s\}, p0, \[x3\]
--.*: e510e3e0 stnt1w \{z0\.s\}, p0, \[sp\]
--.*: e510e3e0 stnt1w \{z0\.s\}, p0, \[sp\]
--.*: e510e3e0 stnt1w \{z0\.s\}, p0, \[sp\]
--.*: e510e3e0 stnt1w \{z0\.s\}, p0, \[sp\]
--.*: e517e000 stnt1w \{z0\.s\}, p0, \[x0, #7, mul vl\]
--.*: e517e000 stnt1w \{z0\.s\}, p0, \[x0, #7, mul vl\]
--.*: e518e000 stnt1w \{z0\.s\}, p0, \[x0, #-8, mul vl\]
--.*: e518e000 stnt1w \{z0\.s\}, p0, \[x0, #-8, mul vl\]
--.*: e519e000 stnt1w \{z0\.s\}, p0, \[x0, #-7, mul vl\]
--.*: e519e000 stnt1w \{z0\.s\}, p0, \[x0, #-7, mul vl\]
--.*: e51fe000 stnt1w \{z0\.s\}, p0, \[x0, #-1, mul vl\]
--.*: e51fe000 stnt1w \{z0\.s\}, p0, \[x0, #-1, mul vl\]
--.*: e5800000 str p0, \[x0\]
--.*: e5800000 str p0, \[x0\]
--.*: e5800000 str p0, \[x0\]
--.*: e5800000 str p0, \[x0\]
--.*: e5800001 str p1, \[x0\]
--.*: e5800001 str p1, \[x0\]
--.*: e5800001 str p1, \[x0\]
--.*: e5800001 str p1, \[x0\]
--.*: e580000f str p15, \[x0\]
--.*: e580000f str p15, \[x0\]
--.*: e580000f str p15, \[x0\]
--.*: e580000f str p15, \[x0\]
--.*: e5800040 str p0, \[x2\]
--.*: e5800040 str p0, \[x2\]
--.*: e5800040 str p0, \[x2\]
--.*: e5800040 str p0, \[x2\]
--.*: e58003e0 str p0, \[sp\]
--.*: e58003e0 str p0, \[sp\]
--.*: e58003e0 str p0, \[sp\]
--.*: e58003e0 str p0, \[sp\]
--.*: e59f1c00 str p0, \[x0, #255, mul vl\]
--.*: e59f1c00 str p0, \[x0, #255, mul vl\]
--.*: e5a00000 str p0, \[x0, #-256, mul vl\]
--.*: e5a00000 str p0, \[x0, #-256, mul vl\]
--.*: e5a00400 str p0, \[x0, #-255, mul vl\]
--.*: e5a00400 str p0, \[x0, #-255, mul vl\]
--.*: e5bf1c00 str p0, \[x0, #-1, mul vl\]
--.*: e5bf1c00 str p0, \[x0, #-1, mul vl\]
--.*: e5804000 str z0, \[x0\]
--.*: e5804000 str z0, \[x0\]
--.*: e5804000 str z0, \[x0\]
--.*: e5804000 str z0, \[x0\]
--.*: e5804001 str z1, \[x0\]
--.*: e5804001 str z1, \[x0\]
--.*: e5804001 str z1, \[x0\]
--.*: e5804001 str z1, \[x0\]
--.*: e580401f str z31, \[x0\]
--.*: e580401f str z31, \[x0\]
--.*: e580401f str z31, \[x0\]
--.*: e580401f str z31, \[x0\]
--.*: e5804040 str z0, \[x2\]
--.*: e5804040 str z0, \[x2\]
--.*: e5804040 str z0, \[x2\]
--.*: e5804040 str z0, \[x2\]
--.*: e58043e0 str z0, \[sp\]
--.*: e58043e0 str z0, \[sp\]
--.*: e58043e0 str z0, \[sp\]
--.*: e58043e0 str z0, \[sp\]
--.*: e59f5c00 str z0, \[x0, #255, mul vl\]
--.*: e59f5c00 str z0, \[x0, #255, mul vl\]
--.*: e5a04000 str z0, \[x0, #-256, mul vl\]
--.*: e5a04000 str z0, \[x0, #-256, mul vl\]
--.*: e5a04400 str z0, \[x0, #-255, mul vl\]
--.*: e5a04400 str z0, \[x0, #-255, mul vl\]
--.*: e5bf5c00 str z0, \[x0, #-1, mul vl\]
--.*: e5bf5c00 str z0, \[x0, #-1, mul vl\]
--.*: 04200400 sub z0\.b, z0\.b, z0\.b
--.*: 04200400 sub z0\.b, z0\.b, z0\.b
--.*: 04200401 sub z1\.b, z0\.b, z0\.b
--.*: 04200401 sub z1\.b, z0\.b, z0\.b
--.*: 0420041f sub z31\.b, z0\.b, z0\.b
--.*: 0420041f sub z31\.b, z0\.b, z0\.b
--.*: 04200440 sub z0\.b, z2\.b, z0\.b
--.*: 04200440 sub z0\.b, z2\.b, z0\.b
--.*: 042007e0 sub z0\.b, z31\.b, z0\.b
--.*: 042007e0 sub z0\.b, z31\.b, z0\.b
--.*: 04230400 sub z0\.b, z0\.b, z3\.b
--.*: 04230400 sub z0\.b, z0\.b, z3\.b
--.*: 043f0400 sub z0\.b, z0\.b, z31\.b
--.*: 043f0400 sub z0\.b, z0\.b, z31\.b
--.*: 04600400 sub z0\.h, z0\.h, z0\.h
--.*: 04600400 sub z0\.h, z0\.h, z0\.h
--.*: 04600401 sub z1\.h, z0\.h, z0\.h
--.*: 04600401 sub z1\.h, z0\.h, z0\.h
--.*: 0460041f sub z31\.h, z0\.h, z0\.h
--.*: 0460041f sub z31\.h, z0\.h, z0\.h
--.*: 04600440 sub z0\.h, z2\.h, z0\.h
--.*: 04600440 sub z0\.h, z2\.h, z0\.h
--.*: 046007e0 sub z0\.h, z31\.h, z0\.h
--.*: 046007e0 sub z0\.h, z31\.h, z0\.h
--.*: 04630400 sub z0\.h, z0\.h, z3\.h
--.*: 04630400 sub z0\.h, z0\.h, z3\.h
--.*: 047f0400 sub z0\.h, z0\.h, z31\.h
--.*: 047f0400 sub z0\.h, z0\.h, z31\.h
--.*: 04a00400 sub z0\.s, z0\.s, z0\.s
--.*: 04a00400 sub z0\.s, z0\.s, z0\.s
--.*: 04a00401 sub z1\.s, z0\.s, z0\.s
--.*: 04a00401 sub z1\.s, z0\.s, z0\.s
--.*: 04a0041f sub z31\.s, z0\.s, z0\.s
--.*: 04a0041f sub z31\.s, z0\.s, z0\.s
--.*: 04a00440 sub z0\.s, z2\.s, z0\.s
--.*: 04a00440 sub z0\.s, z2\.s, z0\.s
--.*: 04a007e0 sub z0\.s, z31\.s, z0\.s
--.*: 04a007e0 sub z0\.s, z31\.s, z0\.s
--.*: 04a30400 sub z0\.s, z0\.s, z3\.s
--.*: 04a30400 sub z0\.s, z0\.s, z3\.s
--.*: 04bf0400 sub z0\.s, z0\.s, z31\.s
--.*: 04bf0400 sub z0\.s, z0\.s, z31\.s
--.*: 04e00400 sub z0\.d, z0\.d, z0\.d
--.*: 04e00400 sub z0\.d, z0\.d, z0\.d
--.*: 04e00401 sub z1\.d, z0\.d, z0\.d
--.*: 04e00401 sub z1\.d, z0\.d, z0\.d
--.*: 04e0041f sub z31\.d, z0\.d, z0\.d
--.*: 04e0041f sub z31\.d, z0\.d, z0\.d
--.*: 04e00440 sub z0\.d, z2\.d, z0\.d
--.*: 04e00440 sub z0\.d, z2\.d, z0\.d
--.*: 04e007e0 sub z0\.d, z31\.d, z0\.d
--.*: 04e007e0 sub z0\.d, z31\.d, z0\.d
--.*: 04e30400 sub z0\.d, z0\.d, z3\.d
--.*: 04e30400 sub z0\.d, z0\.d, z3\.d
--.*: 04ff0400 sub z0\.d, z0\.d, z31\.d
--.*: 04ff0400 sub z0\.d, z0\.d, z31\.d
--.*: 2521c000 sub z0\.b, z0\.b, #0
--.*: 2521c000 sub z0\.b, z0\.b, #0
--.*: 2521c000 sub z0\.b, z0\.b, #0
--.*: 2521c001 sub z1\.b, z1\.b, #0
--.*: 2521c001 sub z1\.b, z1\.b, #0
--.*: 2521c001 sub z1\.b, z1\.b, #0
--.*: 2521c01f sub z31\.b, z31\.b, #0
--.*: 2521c01f sub z31\.b, z31\.b, #0
--.*: 2521c01f sub z31\.b, z31\.b, #0
--.*: 2521c002 sub z2\.b, z2\.b, #0
--.*: 2521c002 sub z2\.b, z2\.b, #0
--.*: 2521c002 sub z2\.b, z2\.b, #0
--.*: 2521cfe0 sub z0\.b, z0\.b, #127
--.*: 2521cfe0 sub z0\.b, z0\.b, #127
--.*: 2521cfe0 sub z0\.b, z0\.b, #127
--.*: 2521d000 sub z0\.b, z0\.b, #128
--.*: 2521d000 sub z0\.b, z0\.b, #128
--.*: 2521d000 sub z0\.b, z0\.b, #128
--.*: 2521d020 sub z0\.b, z0\.b, #129
--.*: 2521d020 sub z0\.b, z0\.b, #129
--.*: 2521d020 sub z0\.b, z0\.b, #129
--.*: 2521dfe0 sub z0\.b, z0\.b, #255
--.*: 2521dfe0 sub z0\.b, z0\.b, #255
--.*: 2521dfe0 sub z0\.b, z0\.b, #255
--.*: 2561c000 sub z0\.h, z0\.h, #0
--.*: 2561c000 sub z0\.h, z0\.h, #0
--.*: 2561c000 sub z0\.h, z0\.h, #0
--.*: 2561c001 sub z1\.h, z1\.h, #0
--.*: 2561c001 sub z1\.h, z1\.h, #0
--.*: 2561c001 sub z1\.h, z1\.h, #0
--.*: 2561c01f sub z31\.h, z31\.h, #0
--.*: 2561c01f sub z31\.h, z31\.h, #0
--.*: 2561c01f sub z31\.h, z31\.h, #0
--.*: 2561c002 sub z2\.h, z2\.h, #0
--.*: 2561c002 sub z2\.h, z2\.h, #0
--.*: 2561c002 sub z2\.h, z2\.h, #0
--.*: 2561cfe0 sub z0\.h, z0\.h, #127
--.*: 2561cfe0 sub z0\.h, z0\.h, #127
--.*: 2561cfe0 sub z0\.h, z0\.h, #127
--.*: 2561d000 sub z0\.h, z0\.h, #128
--.*: 2561d000 sub z0\.h, z0\.h, #128
--.*: 2561d000 sub z0\.h, z0\.h, #128
--.*: 2561d020 sub z0\.h, z0\.h, #129
--.*: 2561d020 sub z0\.h, z0\.h, #129
--.*: 2561d020 sub z0\.h, z0\.h, #129
--.*: 2561dfe0 sub z0\.h, z0\.h, #255
--.*: 2561dfe0 sub z0\.h, z0\.h, #255
--.*: 2561dfe0 sub z0\.h, z0\.h, #255
--.*: 2561e000 sub z0\.h, z0\.h, #0, lsl #8
--.*: 2561e000 sub z0\.h, z0\.h, #0, lsl #8
--.*: 2561efe0 sub z0\.h, z0\.h, #32512
--.*: 2561efe0 sub z0\.h, z0\.h, #32512
--.*: 2561efe0 sub z0\.h, z0\.h, #32512
--.*: 2561efe0 sub z0\.h, z0\.h, #32512
--.*: 2561f000 sub z0\.h, z0\.h, #32768
--.*: 2561f000 sub z0\.h, z0\.h, #32768
--.*: 2561f000 sub z0\.h, z0\.h, #32768
--.*: 2561f000 sub z0\.h, z0\.h, #32768
--.*: 2561f020 sub z0\.h, z0\.h, #33024
--.*: 2561f020 sub z0\.h, z0\.h, #33024
--.*: 2561f020 sub z0\.h, z0\.h, #33024
--.*: 2561f020 sub z0\.h, z0\.h, #33024
--.*: 2561ffe0 sub z0\.h, z0\.h, #65280
--.*: 2561ffe0 sub z0\.h, z0\.h, #65280
--.*: 2561ffe0 sub z0\.h, z0\.h, #65280
--.*: 2561ffe0 sub z0\.h, z0\.h, #65280
--.*: 25a1c000 sub z0\.s, z0\.s, #0
--.*: 25a1c000 sub z0\.s, z0\.s, #0
--.*: 25a1c000 sub z0\.s, z0\.s, #0
--.*: 25a1c001 sub z1\.s, z1\.s, #0
--.*: 25a1c001 sub z1\.s, z1\.s, #0
--.*: 25a1c001 sub z1\.s, z1\.s, #0
--.*: 25a1c01f sub z31\.s, z31\.s, #0
--.*: 25a1c01f sub z31\.s, z31\.s, #0
--.*: 25a1c01f sub z31\.s, z31\.s, #0
--.*: 25a1c002 sub z2\.s, z2\.s, #0
--.*: 25a1c002 sub z2\.s, z2\.s, #0
--.*: 25a1c002 sub z2\.s, z2\.s, #0
--.*: 25a1cfe0 sub z0\.s, z0\.s, #127
--.*: 25a1cfe0 sub z0\.s, z0\.s, #127
--.*: 25a1cfe0 sub z0\.s, z0\.s, #127
--.*: 25a1d000 sub z0\.s, z0\.s, #128
--.*: 25a1d000 sub z0\.s, z0\.s, #128
--.*: 25a1d000 sub z0\.s, z0\.s, #128
--.*: 25a1d020 sub z0\.s, z0\.s, #129
--.*: 25a1d020 sub z0\.s, z0\.s, #129
--.*: 25a1d020 sub z0\.s, z0\.s, #129
--.*: 25a1dfe0 sub z0\.s, z0\.s, #255
--.*: 25a1dfe0 sub z0\.s, z0\.s, #255
--.*: 25a1dfe0 sub z0\.s, z0\.s, #255
--.*: 25a1e000 sub z0\.s, z0\.s, #0, lsl #8
--.*: 25a1e000 sub z0\.s, z0\.s, #0, lsl #8
--.*: 25a1efe0 sub z0\.s, z0\.s, #32512
--.*: 25a1efe0 sub z0\.s, z0\.s, #32512
--.*: 25a1efe0 sub z0\.s, z0\.s, #32512
--.*: 25a1efe0 sub z0\.s, z0\.s, #32512
--.*: 25a1f000 sub z0\.s, z0\.s, #32768
--.*: 25a1f000 sub z0\.s, z0\.s, #32768
--.*: 25a1f000 sub z0\.s, z0\.s, #32768
--.*: 25a1f000 sub z0\.s, z0\.s, #32768
--.*: 25a1f020 sub z0\.s, z0\.s, #33024
--.*: 25a1f020 sub z0\.s, z0\.s, #33024
--.*: 25a1f020 sub z0\.s, z0\.s, #33024
--.*: 25a1f020 sub z0\.s, z0\.s, #33024
--.*: 25a1ffe0 sub z0\.s, z0\.s, #65280
--.*: 25a1ffe0 sub z0\.s, z0\.s, #65280
--.*: 25a1ffe0 sub z0\.s, z0\.s, #65280
--.*: 25a1ffe0 sub z0\.s, z0\.s, #65280
--.*: 25e1c000 sub z0\.d, z0\.d, #0
--.*: 25e1c000 sub z0\.d, z0\.d, #0
--.*: 25e1c000 sub z0\.d, z0\.d, #0
--.*: 25e1c001 sub z1\.d, z1\.d, #0
--.*: 25e1c001 sub z1\.d, z1\.d, #0
--.*: 25e1c001 sub z1\.d, z1\.d, #0
--.*: 25e1c01f sub z31\.d, z31\.d, #0
--.*: 25e1c01f sub z31\.d, z31\.d, #0
--.*: 25e1c01f sub z31\.d, z31\.d, #0
--.*: 25e1c002 sub z2\.d, z2\.d, #0
--.*: 25e1c002 sub z2\.d, z2\.d, #0
--.*: 25e1c002 sub z2\.d, z2\.d, #0
--.*: 25e1cfe0 sub z0\.d, z0\.d, #127
--.*: 25e1cfe0 sub z0\.d, z0\.d, #127
--.*: 25e1cfe0 sub z0\.d, z0\.d, #127
--.*: 25e1d000 sub z0\.d, z0\.d, #128
--.*: 25e1d000 sub z0\.d, z0\.d, #128
--.*: 25e1d000 sub z0\.d, z0\.d, #128
--.*: 25e1d020 sub z0\.d, z0\.d, #129
--.*: 25e1d020 sub z0\.d, z0\.d, #129
--.*: 25e1d020 sub z0\.d, z0\.d, #129
--.*: 25e1dfe0 sub z0\.d, z0\.d, #255
--.*: 25e1dfe0 sub z0\.d, z0\.d, #255
--.*: 25e1dfe0 sub z0\.d, z0\.d, #255
--.*: 25e1e000 sub z0\.d, z0\.d, #0, lsl #8
--.*: 25e1e000 sub z0\.d, z0\.d, #0, lsl #8
--.*: 25e1efe0 sub z0\.d, z0\.d, #32512
--.*: 25e1efe0 sub z0\.d, z0\.d, #32512
--.*: 25e1efe0 sub z0\.d, z0\.d, #32512
--.*: 25e1efe0 sub z0\.d, z0\.d, #32512
--.*: 25e1f000 sub z0\.d, z0\.d, #32768
--.*: 25e1f000 sub z0\.d, z0\.d, #32768
--.*: 25e1f000 sub z0\.d, z0\.d, #32768
--.*: 25e1f000 sub z0\.d, z0\.d, #32768
--.*: 25e1f020 sub z0\.d, z0\.d, #33024
--.*: 25e1f020 sub z0\.d, z0\.d, #33024
--.*: 25e1f020 sub z0\.d, z0\.d, #33024
--.*: 25e1f020 sub z0\.d, z0\.d, #33024
--.*: 25e1ffe0 sub z0\.d, z0\.d, #65280
--.*: 25e1ffe0 sub z0\.d, z0\.d, #65280
--.*: 25e1ffe0 sub z0\.d, z0\.d, #65280
--.*: 25e1ffe0 sub z0\.d, z0\.d, #65280
--.*: 04010000 sub z0\.b, p0/m, z0\.b, z0\.b
--.*: 04010000 sub z0\.b, p0/m, z0\.b, z0\.b
--.*: 04010001 sub z1\.b, p0/m, z1\.b, z0\.b
--.*: 04010001 sub z1\.b, p0/m, z1\.b, z0\.b
--.*: 0401001f sub z31\.b, p0/m, z31\.b, z0\.b
--.*: 0401001f sub z31\.b, p0/m, z31\.b, z0\.b
--.*: 04010800 sub z0\.b, p2/m, z0\.b, z0\.b
--.*: 04010800 sub z0\.b, p2/m, z0\.b, z0\.b
--.*: 04011c00 sub z0\.b, p7/m, z0\.b, z0\.b
--.*: 04011c00 sub z0\.b, p7/m, z0\.b, z0\.b
--.*: 04010003 sub z3\.b, p0/m, z3\.b, z0\.b
--.*: 04010003 sub z3\.b, p0/m, z3\.b, z0\.b
--.*: 04010080 sub z0\.b, p0/m, z0\.b, z4\.b
--.*: 04010080 sub z0\.b, p0/m, z0\.b, z4\.b
--.*: 040103e0 sub z0\.b, p0/m, z0\.b, z31\.b
--.*: 040103e0 sub z0\.b, p0/m, z0\.b, z31\.b
--.*: 04410000 sub z0\.h, p0/m, z0\.h, z0\.h
--.*: 04410000 sub z0\.h, p0/m, z0\.h, z0\.h
--.*: 04410001 sub z1\.h, p0/m, z1\.h, z0\.h
--.*: 04410001 sub z1\.h, p0/m, z1\.h, z0\.h
--.*: 0441001f sub z31\.h, p0/m, z31\.h, z0\.h
--.*: 0441001f sub z31\.h, p0/m, z31\.h, z0\.h
--.*: 04410800 sub z0\.h, p2/m, z0\.h, z0\.h
--.*: 04410800 sub z0\.h, p2/m, z0\.h, z0\.h
--.*: 04411c00 sub z0\.h, p7/m, z0\.h, z0\.h
--.*: 04411c00 sub z0\.h, p7/m, z0\.h, z0\.h
--.*: 04410003 sub z3\.h, p0/m, z3\.h, z0\.h
--.*: 04410003 sub z3\.h, p0/m, z3\.h, z0\.h
--.*: 04410080 sub z0\.h, p0/m, z0\.h, z4\.h
--.*: 04410080 sub z0\.h, p0/m, z0\.h, z4\.h
--.*: 044103e0 sub z0\.h, p0/m, z0\.h, z31\.h
--.*: 044103e0 sub z0\.h, p0/m, z0\.h, z31\.h
--.*: 04810000 sub z0\.s, p0/m, z0\.s, z0\.s
--.*: 04810000 sub z0\.s, p0/m, z0\.s, z0\.s
--.*: 04810001 sub z1\.s, p0/m, z1\.s, z0\.s
--.*: 04810001 sub z1\.s, p0/m, z1\.s, z0\.s
--.*: 0481001f sub z31\.s, p0/m, z31\.s, z0\.s
--.*: 0481001f sub z31\.s, p0/m, z31\.s, z0\.s
--.*: 04810800 sub z0\.s, p2/m, z0\.s, z0\.s
--.*: 04810800 sub z0\.s, p2/m, z0\.s, z0\.s
--.*: 04811c00 sub z0\.s, p7/m, z0\.s, z0\.s
--.*: 04811c00 sub z0\.s, p7/m, z0\.s, z0\.s
--.*: 04810003 sub z3\.s, p0/m, z3\.s, z0\.s
--.*: 04810003 sub z3\.s, p0/m, z3\.s, z0\.s
--.*: 04810080 sub z0\.s, p0/m, z0\.s, z4\.s
--.*: 04810080 sub z0\.s, p0/m, z0\.s, z4\.s
--.*: 048103e0 sub z0\.s, p0/m, z0\.s, z31\.s
--.*: 048103e0 sub z0\.s, p0/m, z0\.s, z31\.s
--.*: 04c10000 sub z0\.d, p0/m, z0\.d, z0\.d
--.*: 04c10000 sub z0\.d, p0/m, z0\.d, z0\.d
--.*: 04c10001 sub z1\.d, p0/m, z1\.d, z0\.d
--.*: 04c10001 sub z1\.d, p0/m, z1\.d, z0\.d
--.*: 04c1001f sub z31\.d, p0/m, z31\.d, z0\.d
--.*: 04c1001f sub z31\.d, p0/m, z31\.d, z0\.d
--.*: 04c10800 sub z0\.d, p2/m, z0\.d, z0\.d
--.*: 04c10800 sub z0\.d, p2/m, z0\.d, z0\.d
--.*: 04c11c00 sub z0\.d, p7/m, z0\.d, z0\.d
--.*: 04c11c00 sub z0\.d, p7/m, z0\.d, z0\.d
--.*: 04c10003 sub z3\.d, p0/m, z3\.d, z0\.d
--.*: 04c10003 sub z3\.d, p0/m, z3\.d, z0\.d
--.*: 04c10080 sub z0\.d, p0/m, z0\.d, z4\.d
--.*: 04c10080 sub z0\.d, p0/m, z0\.d, z4\.d
--.*: 04c103e0 sub z0\.d, p0/m, z0\.d, z31\.d
--.*: 04c103e0 sub z0\.d, p0/m, z0\.d, z31\.d
--.*: 2523c000 subr z0\.b, z0\.b, #0
--.*: 2523c000 subr z0\.b, z0\.b, #0
--.*: 2523c000 subr z0\.b, z0\.b, #0
--.*: 2523c001 subr z1\.b, z1\.b, #0
--.*: 2523c001 subr z1\.b, z1\.b, #0
--.*: 2523c001 subr z1\.b, z1\.b, #0
--.*: 2523c01f subr z31\.b, z31\.b, #0
--.*: 2523c01f subr z31\.b, z31\.b, #0
--.*: 2523c01f subr z31\.b, z31\.b, #0
--.*: 2523c002 subr z2\.b, z2\.b, #0
--.*: 2523c002 subr z2\.b, z2\.b, #0
--.*: 2523c002 subr z2\.b, z2\.b, #0
--.*: 2523cfe0 subr z0\.b, z0\.b, #127
--.*: 2523cfe0 subr z0\.b, z0\.b, #127
--.*: 2523cfe0 subr z0\.b, z0\.b, #127
--.*: 2523d000 subr z0\.b, z0\.b, #128
--.*: 2523d000 subr z0\.b, z0\.b, #128
--.*: 2523d000 subr z0\.b, z0\.b, #128
--.*: 2523d020 subr z0\.b, z0\.b, #129
--.*: 2523d020 subr z0\.b, z0\.b, #129
--.*: 2523d020 subr z0\.b, z0\.b, #129
--.*: 2523dfe0 subr z0\.b, z0\.b, #255
--.*: 2523dfe0 subr z0\.b, z0\.b, #255
--.*: 2523dfe0 subr z0\.b, z0\.b, #255
--.*: 2563c000 subr z0\.h, z0\.h, #0
--.*: 2563c000 subr z0\.h, z0\.h, #0
--.*: 2563c000 subr z0\.h, z0\.h, #0
--.*: 2563c001 subr z1\.h, z1\.h, #0
--.*: 2563c001 subr z1\.h, z1\.h, #0
--.*: 2563c001 subr z1\.h, z1\.h, #0
--.*: 2563c01f subr z31\.h, z31\.h, #0
--.*: 2563c01f subr z31\.h, z31\.h, #0
--.*: 2563c01f subr z31\.h, z31\.h, #0
--.*: 2563c002 subr z2\.h, z2\.h, #0
--.*: 2563c002 subr z2\.h, z2\.h, #0
--.*: 2563c002 subr z2\.h, z2\.h, #0
--.*: 2563cfe0 subr z0\.h, z0\.h, #127
--.*: 2563cfe0 subr z0\.h, z0\.h, #127
--.*: 2563cfe0 subr z0\.h, z0\.h, #127
--.*: 2563d000 subr z0\.h, z0\.h, #128
--.*: 2563d000 subr z0\.h, z0\.h, #128
--.*: 2563d000 subr z0\.h, z0\.h, #128
--.*: 2563d020 subr z0\.h, z0\.h, #129
--.*: 2563d020 subr z0\.h, z0\.h, #129
--.*: 2563d020 subr z0\.h, z0\.h, #129
--.*: 2563dfe0 subr z0\.h, z0\.h, #255
--.*: 2563dfe0 subr z0\.h, z0\.h, #255
--.*: 2563dfe0 subr z0\.h, z0\.h, #255
--.*: 2563e000 subr z0\.h, z0\.h, #0, lsl #8
--.*: 2563e000 subr z0\.h, z0\.h, #0, lsl #8
--.*: 2563efe0 subr z0\.h, z0\.h, #32512
--.*: 2563efe0 subr z0\.h, z0\.h, #32512
--.*: 2563efe0 subr z0\.h, z0\.h, #32512
--.*: 2563efe0 subr z0\.h, z0\.h, #32512
--.*: 2563f000 subr z0\.h, z0\.h, #32768
--.*: 2563f000 subr z0\.h, z0\.h, #32768
--.*: 2563f000 subr z0\.h, z0\.h, #32768
--.*: 2563f000 subr z0\.h, z0\.h, #32768
--.*: 2563f020 subr z0\.h, z0\.h, #33024
--.*: 2563f020 subr z0\.h, z0\.h, #33024
--.*: 2563f020 subr z0\.h, z0\.h, #33024
--.*: 2563f020 subr z0\.h, z0\.h, #33024
--.*: 2563ffe0 subr z0\.h, z0\.h, #65280
--.*: 2563ffe0 subr z0\.h, z0\.h, #65280
--.*: 2563ffe0 subr z0\.h, z0\.h, #65280
--.*: 2563ffe0 subr z0\.h, z0\.h, #65280
--.*: 25a3c000 subr z0\.s, z0\.s, #0
--.*: 25a3c000 subr z0\.s, z0\.s, #0
--.*: 25a3c000 subr z0\.s, z0\.s, #0
--.*: 25a3c001 subr z1\.s, z1\.s, #0
--.*: 25a3c001 subr z1\.s, z1\.s, #0
--.*: 25a3c001 subr z1\.s, z1\.s, #0
--.*: 25a3c01f subr z31\.s, z31\.s, #0
--.*: 25a3c01f subr z31\.s, z31\.s, #0
--.*: 25a3c01f subr z31\.s, z31\.s, #0
--.*: 25a3c002 subr z2\.s, z2\.s, #0
--.*: 25a3c002 subr z2\.s, z2\.s, #0
--.*: 25a3c002 subr z2\.s, z2\.s, #0
--.*: 25a3cfe0 subr z0\.s, z0\.s, #127
--.*: 25a3cfe0 subr z0\.s, z0\.s, #127
--.*: 25a3cfe0 subr z0\.s, z0\.s, #127
--.*: 25a3d000 subr z0\.s, z0\.s, #128
--.*: 25a3d000 subr z0\.s, z0\.s, #128
--.*: 25a3d000 subr z0\.s, z0\.s, #128
--.*: 25a3d020 subr z0\.s, z0\.s, #129
--.*: 25a3d020 subr z0\.s, z0\.s, #129
--.*: 25a3d020 subr z0\.s, z0\.s, #129
--.*: 25a3dfe0 subr z0\.s, z0\.s, #255
--.*: 25a3dfe0 subr z0\.s, z0\.s, #255
--.*: 25a3dfe0 subr z0\.s, z0\.s, #255
--.*: 25a3e000 subr z0\.s, z0\.s, #0, lsl #8
--.*: 25a3e000 subr z0\.s, z0\.s, #0, lsl #8
--.*: 25a3efe0 subr z0\.s, z0\.s, #32512
--.*: 25a3efe0 subr z0\.s, z0\.s, #32512
--.*: 25a3efe0 subr z0\.s, z0\.s, #32512
--.*: 25a3efe0 subr z0\.s, z0\.s, #32512
--.*: 25a3f000 subr z0\.s, z0\.s, #32768
--.*: 25a3f000 subr z0\.s, z0\.s, #32768
--.*: 25a3f000 subr z0\.s, z0\.s, #32768
--.*: 25a3f000 subr z0\.s, z0\.s, #32768
--.*: 25a3f020 subr z0\.s, z0\.s, #33024
--.*: 25a3f020 subr z0\.s, z0\.s, #33024
--.*: 25a3f020 subr z0\.s, z0\.s, #33024
--.*: 25a3f020 subr z0\.s, z0\.s, #33024
--.*: 25a3ffe0 subr z0\.s, z0\.s, #65280
--.*: 25a3ffe0 subr z0\.s, z0\.s, #65280
--.*: 25a3ffe0 subr z0\.s, z0\.s, #65280
--.*: 25a3ffe0 subr z0\.s, z0\.s, #65280
--.*: 25e3c000 subr z0\.d, z0\.d, #0
--.*: 25e3c000 subr z0\.d, z0\.d, #0
--.*: 25e3c000 subr z0\.d, z0\.d, #0
--.*: 25e3c001 subr z1\.d, z1\.d, #0
--.*: 25e3c001 subr z1\.d, z1\.d, #0
--.*: 25e3c001 subr z1\.d, z1\.d, #0
--.*: 25e3c01f subr z31\.d, z31\.d, #0
--.*: 25e3c01f subr z31\.d, z31\.d, #0
--.*: 25e3c01f subr z31\.d, z31\.d, #0
--.*: 25e3c002 subr z2\.d, z2\.d, #0
--.*: 25e3c002 subr z2\.d, z2\.d, #0
--.*: 25e3c002 subr z2\.d, z2\.d, #0
--.*: 25e3cfe0 subr z0\.d, z0\.d, #127
--.*: 25e3cfe0 subr z0\.d, z0\.d, #127
--.*: 25e3cfe0 subr z0\.d, z0\.d, #127
--.*: 25e3d000 subr z0\.d, z0\.d, #128
--.*: 25e3d000 subr z0\.d, z0\.d, #128
--.*: 25e3d000 subr z0\.d, z0\.d, #128
--.*: 25e3d020 subr z0\.d, z0\.d, #129
--.*: 25e3d020 subr z0\.d, z0\.d, #129
--.*: 25e3d020 subr z0\.d, z0\.d, #129
--.*: 25e3dfe0 subr z0\.d, z0\.d, #255
--.*: 25e3dfe0 subr z0\.d, z0\.d, #255
--.*: 25e3dfe0 subr z0\.d, z0\.d, #255
--.*: 25e3e000 subr z0\.d, z0\.d, #0, lsl #8
--.*: 25e3e000 subr z0\.d, z0\.d, #0, lsl #8
--.*: 25e3efe0 subr z0\.d, z0\.d, #32512
--.*: 25e3efe0 subr z0\.d, z0\.d, #32512
--.*: 25e3efe0 subr z0\.d, z0\.d, #32512
--.*: 25e3efe0 subr z0\.d, z0\.d, #32512
--.*: 25e3f000 subr z0\.d, z0\.d, #32768
--.*: 25e3f000 subr z0\.d, z0\.d, #32768
--.*: 25e3f000 subr z0\.d, z0\.d, #32768
--.*: 25e3f000 subr z0\.d, z0\.d, #32768
--.*: 25e3f020 subr z0\.d, z0\.d, #33024
--.*: 25e3f020 subr z0\.d, z0\.d, #33024
--.*: 25e3f020 subr z0\.d, z0\.d, #33024
--.*: 25e3f020 subr z0\.d, z0\.d, #33024
--.*: 25e3ffe0 subr z0\.d, z0\.d, #65280
--.*: 25e3ffe0 subr z0\.d, z0\.d, #65280
--.*: 25e3ffe0 subr z0\.d, z0\.d, #65280
--.*: 25e3ffe0 subr z0\.d, z0\.d, #65280
--.*: 04030000 subr z0\.b, p0/m, z0\.b, z0\.b
--.*: 04030000 subr z0\.b, p0/m, z0\.b, z0\.b
--.*: 04030001 subr z1\.b, p0/m, z1\.b, z0\.b
--.*: 04030001 subr z1\.b, p0/m, z1\.b, z0\.b
--.*: 0403001f subr z31\.b, p0/m, z31\.b, z0\.b
--.*: 0403001f subr z31\.b, p0/m, z31\.b, z0\.b
--.*: 04030800 subr z0\.b, p2/m, z0\.b, z0\.b
--.*: 04030800 subr z0\.b, p2/m, z0\.b, z0\.b
--.*: 04031c00 subr z0\.b, p7/m, z0\.b, z0\.b
--.*: 04031c00 subr z0\.b, p7/m, z0\.b, z0\.b
--.*: 04030003 subr z3\.b, p0/m, z3\.b, z0\.b
--.*: 04030003 subr z3\.b, p0/m, z3\.b, z0\.b
--.*: 04030080 subr z0\.b, p0/m, z0\.b, z4\.b
--.*: 04030080 subr z0\.b, p0/m, z0\.b, z4\.b
--.*: 040303e0 subr z0\.b, p0/m, z0\.b, z31\.b
--.*: 040303e0 subr z0\.b, p0/m, z0\.b, z31\.b
--.*: 04430000 subr z0\.h, p0/m, z0\.h, z0\.h
--.*: 04430000 subr z0\.h, p0/m, z0\.h, z0\.h
--.*: 04430001 subr z1\.h, p0/m, z1\.h, z0\.h
--.*: 04430001 subr z1\.h, p0/m, z1\.h, z0\.h
--.*: 0443001f subr z31\.h, p0/m, z31\.h, z0\.h
--.*: 0443001f subr z31\.h, p0/m, z31\.h, z0\.h
--.*: 04430800 subr z0\.h, p2/m, z0\.h, z0\.h
--.*: 04430800 subr z0\.h, p2/m, z0\.h, z0\.h
--.*: 04431c00 subr z0\.h, p7/m, z0\.h, z0\.h
--.*: 04431c00 subr z0\.h, p7/m, z0\.h, z0\.h
--.*: 04430003 subr z3\.h, p0/m, z3\.h, z0\.h
--.*: 04430003 subr z3\.h, p0/m, z3\.h, z0\.h
--.*: 04430080 subr z0\.h, p0/m, z0\.h, z4\.h
--.*: 04430080 subr z0\.h, p0/m, z0\.h, z4\.h
--.*: 044303e0 subr z0\.h, p0/m, z0\.h, z31\.h
--.*: 044303e0 subr z0\.h, p0/m, z0\.h, z31\.h
--.*: 04830000 subr z0\.s, p0/m, z0\.s, z0\.s
--.*: 04830000 subr z0\.s, p0/m, z0\.s, z0\.s
--.*: 04830001 subr z1\.s, p0/m, z1\.s, z0\.s
--.*: 04830001 subr z1\.s, p0/m, z1\.s, z0\.s
--.*: 0483001f subr z31\.s, p0/m, z31\.s, z0\.s
--.*: 0483001f subr z31\.s, p0/m, z31\.s, z0\.s
--.*: 04830800 subr z0\.s, p2/m, z0\.s, z0\.s
--.*: 04830800 subr z0\.s, p2/m, z0\.s, z0\.s
--.*: 04831c00 subr z0\.s, p7/m, z0\.s, z0\.s
--.*: 04831c00 subr z0\.s, p7/m, z0\.s, z0\.s
--.*: 04830003 subr z3\.s, p0/m, z3\.s, z0\.s
--.*: 04830003 subr z3\.s, p0/m, z3\.s, z0\.s
--.*: 04830080 subr z0\.s, p0/m, z0\.s, z4\.s
--.*: 04830080 subr z0\.s, p0/m, z0\.s, z4\.s
--.*: 048303e0 subr z0\.s, p0/m, z0\.s, z31\.s
--.*: 048303e0 subr z0\.s, p0/m, z0\.s, z31\.s
--.*: 04c30000 subr z0\.d, p0/m, z0\.d, z0\.d
--.*: 04c30000 subr z0\.d, p0/m, z0\.d, z0\.d
--.*: 04c30001 subr z1\.d, p0/m, z1\.d, z0\.d
--.*: 04c30001 subr z1\.d, p0/m, z1\.d, z0\.d
--.*: 04c3001f subr z31\.d, p0/m, z31\.d, z0\.d
--.*: 04c3001f subr z31\.d, p0/m, z31\.d, z0\.d
--.*: 04c30800 subr z0\.d, p2/m, z0\.d, z0\.d
--.*: 04c30800 subr z0\.d, p2/m, z0\.d, z0\.d
--.*: 04c31c00 subr z0\.d, p7/m, z0\.d, z0\.d
--.*: 04c31c00 subr z0\.d, p7/m, z0\.d, z0\.d
--.*: 04c30003 subr z3\.d, p0/m, z3\.d, z0\.d
--.*: 04c30003 subr z3\.d, p0/m, z3\.d, z0\.d
--.*: 04c30080 subr z0\.d, p0/m, z0\.d, z4\.d
--.*: 04c30080 subr z0\.d, p0/m, z0\.d, z4\.d
--.*: 04c303e0 subr z0\.d, p0/m, z0\.d, z31\.d
--.*: 04c303e0 subr z0\.d, p0/m, z0\.d, z31\.d
--.*: 05713800 sunpkhi z0\.h, z0\.b
--.*: 05713800 sunpkhi z0\.h, z0\.b
--.*: 05713801 sunpkhi z1\.h, z0\.b
--.*: 05713801 sunpkhi z1\.h, z0\.b
--.*: 0571381f sunpkhi z31\.h, z0\.b
--.*: 0571381f sunpkhi z31\.h, z0\.b
--.*: 05713840 sunpkhi z0\.h, z2\.b
--.*: 05713840 sunpkhi z0\.h, z2\.b
--.*: 05713be0 sunpkhi z0\.h, z31\.b
--.*: 05713be0 sunpkhi z0\.h, z31\.b
--.*: 05b13800 sunpkhi z0\.s, z0\.h
--.*: 05b13800 sunpkhi z0\.s, z0\.h
--.*: 05b13801 sunpkhi z1\.s, z0\.h
--.*: 05b13801 sunpkhi z1\.s, z0\.h
--.*: 05b1381f sunpkhi z31\.s, z0\.h
--.*: 05b1381f sunpkhi z31\.s, z0\.h
--.*: 05b13840 sunpkhi z0\.s, z2\.h
--.*: 05b13840 sunpkhi z0\.s, z2\.h
--.*: 05b13be0 sunpkhi z0\.s, z31\.h
--.*: 05b13be0 sunpkhi z0\.s, z31\.h
--.*: 05f13800 sunpkhi z0\.d, z0\.s
--.*: 05f13800 sunpkhi z0\.d, z0\.s
--.*: 05f13801 sunpkhi z1\.d, z0\.s
--.*: 05f13801 sunpkhi z1\.d, z0\.s
--.*: 05f1381f sunpkhi z31\.d, z0\.s
--.*: 05f1381f sunpkhi z31\.d, z0\.s
--.*: 05f13840 sunpkhi z0\.d, z2\.s
--.*: 05f13840 sunpkhi z0\.d, z2\.s
--.*: 05f13be0 sunpkhi z0\.d, z31\.s
--.*: 05f13be0 sunpkhi z0\.d, z31\.s
--.*: 05703800 sunpklo z0\.h, z0\.b
--.*: 05703800 sunpklo z0\.h, z0\.b
--.*: 05703801 sunpklo z1\.h, z0\.b
--.*: 05703801 sunpklo z1\.h, z0\.b
--.*: 0570381f sunpklo z31\.h, z0\.b
--.*: 0570381f sunpklo z31\.h, z0\.b
--.*: 05703840 sunpklo z0\.h, z2\.b
--.*: 05703840 sunpklo z0\.h, z2\.b
--.*: 05703be0 sunpklo z0\.h, z31\.b
--.*: 05703be0 sunpklo z0\.h, z31\.b
--.*: 05b03800 sunpklo z0\.s, z0\.h
--.*: 05b03800 sunpklo z0\.s, z0\.h
--.*: 05b03801 sunpklo z1\.s, z0\.h
--.*: 05b03801 sunpklo z1\.s, z0\.h
--.*: 05b0381f sunpklo z31\.s, z0\.h
--.*: 05b0381f sunpklo z31\.s, z0\.h
--.*: 05b03840 sunpklo z0\.s, z2\.h
--.*: 05b03840 sunpklo z0\.s, z2\.h
--.*: 05b03be0 sunpklo z0\.s, z31\.h
--.*: 05b03be0 sunpklo z0\.s, z31\.h
--.*: 05f03800 sunpklo z0\.d, z0\.s
--.*: 05f03800 sunpklo z0\.d, z0\.s
--.*: 05f03801 sunpklo z1\.d, z0\.s
--.*: 05f03801 sunpklo z1\.d, z0\.s
--.*: 05f0381f sunpklo z31\.d, z0\.s
--.*: 05f0381f sunpklo z31\.d, z0\.s
--.*: 05f03840 sunpklo z0\.d, z2\.s
--.*: 05f03840 sunpklo z0\.d, z2\.s
--.*: 05f03be0 sunpklo z0\.d, z31\.s
--.*: 05f03be0 sunpklo z0\.d, z31\.s
--.*: 0450a000 sxtb z0\.h, p0/m, z0\.h
--.*: 0450a000 sxtb z0\.h, p0/m, z0\.h
--.*: 0450a001 sxtb z1\.h, p0/m, z0\.h
--.*: 0450a001 sxtb z1\.h, p0/m, z0\.h
--.*: 0450a01f sxtb z31\.h, p0/m, z0\.h
--.*: 0450a01f sxtb z31\.h, p0/m, z0\.h
--.*: 0450a800 sxtb z0\.h, p2/m, z0\.h
--.*: 0450a800 sxtb z0\.h, p2/m, z0\.h
--.*: 0450bc00 sxtb z0\.h, p7/m, z0\.h
--.*: 0450bc00 sxtb z0\.h, p7/m, z0\.h
--.*: 0450a060 sxtb z0\.h, p0/m, z3\.h
--.*: 0450a060 sxtb z0\.h, p0/m, z3\.h
--.*: 0450a3e0 sxtb z0\.h, p0/m, z31\.h
--.*: 0450a3e0 sxtb z0\.h, p0/m, z31\.h
--.*: 0490a000 sxtb z0\.s, p0/m, z0\.s
--.*: 0490a000 sxtb z0\.s, p0/m, z0\.s
--.*: 0490a001 sxtb z1\.s, p0/m, z0\.s
--.*: 0490a001 sxtb z1\.s, p0/m, z0\.s
--.*: 0490a01f sxtb z31\.s, p0/m, z0\.s
--.*: 0490a01f sxtb z31\.s, p0/m, z0\.s
--.*: 0490a800 sxtb z0\.s, p2/m, z0\.s
--.*: 0490a800 sxtb z0\.s, p2/m, z0\.s
--.*: 0490bc00 sxtb z0\.s, p7/m, z0\.s
--.*: 0490bc00 sxtb z0\.s, p7/m, z0\.s
--.*: 0490a060 sxtb z0\.s, p0/m, z3\.s
--.*: 0490a060 sxtb z0\.s, p0/m, z3\.s
--.*: 0490a3e0 sxtb z0\.s, p0/m, z31\.s
--.*: 0490a3e0 sxtb z0\.s, p0/m, z31\.s
--.*: 04d0a000 sxtb z0\.d, p0/m, z0\.d
--.*: 04d0a000 sxtb z0\.d, p0/m, z0\.d
--.*: 04d0a001 sxtb z1\.d, p0/m, z0\.d
--.*: 04d0a001 sxtb z1\.d, p0/m, z0\.d
--.*: 04d0a01f sxtb z31\.d, p0/m, z0\.d
--.*: 04d0a01f sxtb z31\.d, p0/m, z0\.d
--.*: 04d0a800 sxtb z0\.d, p2/m, z0\.d
--.*: 04d0a800 sxtb z0\.d, p2/m, z0\.d
--.*: 04d0bc00 sxtb z0\.d, p7/m, z0\.d
--.*: 04d0bc00 sxtb z0\.d, p7/m, z0\.d
--.*: 04d0a060 sxtb z0\.d, p0/m, z3\.d
--.*: 04d0a060 sxtb z0\.d, p0/m, z3\.d
--.*: 04d0a3e0 sxtb z0\.d, p0/m, z31\.d
--.*: 04d0a3e0 sxtb z0\.d, p0/m, z31\.d
--.*: 0492a000 sxth z0\.s, p0/m, z0\.s
--.*: 0492a000 sxth z0\.s, p0/m, z0\.s
--.*: 0492a001 sxth z1\.s, p0/m, z0\.s
--.*: 0492a001 sxth z1\.s, p0/m, z0\.s
--.*: 0492a01f sxth z31\.s, p0/m, z0\.s
--.*: 0492a01f sxth z31\.s, p0/m, z0\.s
--.*: 0492a800 sxth z0\.s, p2/m, z0\.s
--.*: 0492a800 sxth z0\.s, p2/m, z0\.s
--.*: 0492bc00 sxth z0\.s, p7/m, z0\.s
--.*: 0492bc00 sxth z0\.s, p7/m, z0\.s
--.*: 0492a060 sxth z0\.s, p0/m, z3\.s
--.*: 0492a060 sxth z0\.s, p0/m, z3\.s
--.*: 0492a3e0 sxth z0\.s, p0/m, z31\.s
--.*: 0492a3e0 sxth z0\.s, p0/m, z31\.s
--.*: 04d2a000 sxth z0\.d, p0/m, z0\.d
--.*: 04d2a000 sxth z0\.d, p0/m, z0\.d
--.*: 04d2a001 sxth z1\.d, p0/m, z0\.d
--.*: 04d2a001 sxth z1\.d, p0/m, z0\.d
--.*: 04d2a01f sxth z31\.d, p0/m, z0\.d
--.*: 04d2a01f sxth z31\.d, p0/m, z0\.d
--.*: 04d2a800 sxth z0\.d, p2/m, z0\.d
--.*: 04d2a800 sxth z0\.d, p2/m, z0\.d
--.*: 04d2bc00 sxth z0\.d, p7/m, z0\.d
--.*: 04d2bc00 sxth z0\.d, p7/m, z0\.d
--.*: 04d2a060 sxth z0\.d, p0/m, z3\.d
--.*: 04d2a060 sxth z0\.d, p0/m, z3\.d
--.*: 04d2a3e0 sxth z0\.d, p0/m, z31\.d
--.*: 04d2a3e0 sxth z0\.d, p0/m, z31\.d
--.*: 04d4a000 sxtw z0\.d, p0/m, z0\.d
--.*: 04d4a000 sxtw z0\.d, p0/m, z0\.d
--.*: 04d4a001 sxtw z1\.d, p0/m, z0\.d
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--.*: 044b001f umin z31\.h, p0/m, z31\.h, z0\.h
--.*: 044b001f umin z31\.h, p0/m, z31\.h, z0\.h
--.*: 044b0800 umin z0\.h, p2/m, z0\.h, z0\.h
--.*: 044b0800 umin z0\.h, p2/m, z0\.h, z0\.h
--.*: 044b1c00 umin z0\.h, p7/m, z0\.h, z0\.h
--.*: 044b1c00 umin z0\.h, p7/m, z0\.h, z0\.h
--.*: 044b0003 umin z3\.h, p0/m, z3\.h, z0\.h
--.*: 044b0003 umin z3\.h, p0/m, z3\.h, z0\.h
--.*: 044b0080 umin z0\.h, p0/m, z0\.h, z4\.h
--.*: 044b0080 umin z0\.h, p0/m, z0\.h, z4\.h
--.*: 044b03e0 umin z0\.h, p0/m, z0\.h, z31\.h
--.*: 044b03e0 umin z0\.h, p0/m, z0\.h, z31\.h
--.*: 048b0000 umin z0\.s, p0/m, z0\.s, z0\.s
--.*: 048b0000 umin z0\.s, p0/m, z0\.s, z0\.s
--.*: 048b0001 umin z1\.s, p0/m, z1\.s, z0\.s
--.*: 048b0001 umin z1\.s, p0/m, z1\.s, z0\.s
--.*: 048b001f umin z31\.s, p0/m, z31\.s, z0\.s
--.*: 048b001f umin z31\.s, p0/m, z31\.s, z0\.s
--.*: 048b0800 umin z0\.s, p2/m, z0\.s, z0\.s
--.*: 048b0800 umin z0\.s, p2/m, z0\.s, z0\.s
--.*: 048b1c00 umin z0\.s, p7/m, z0\.s, z0\.s
--.*: 048b1c00 umin z0\.s, p7/m, z0\.s, z0\.s
--.*: 048b0003 umin z3\.s, p0/m, z3\.s, z0\.s
--.*: 048b0003 umin z3\.s, p0/m, z3\.s, z0\.s
--.*: 048b0080 umin z0\.s, p0/m, z0\.s, z4\.s
--.*: 048b0080 umin z0\.s, p0/m, z0\.s, z4\.s
--.*: 048b03e0 umin z0\.s, p0/m, z0\.s, z31\.s
--.*: 048b03e0 umin z0\.s, p0/m, z0\.s, z31\.s
--.*: 04cb0000 umin z0\.d, p0/m, z0\.d, z0\.d
--.*: 04cb0000 umin z0\.d, p0/m, z0\.d, z0\.d
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--.*: 04cb0001 umin z1\.d, p0/m, z1\.d, z0\.d
--.*: 04cb001f umin z31\.d, p0/m, z31\.d, z0\.d
--.*: 04cb001f umin z31\.d, p0/m, z31\.d, z0\.d
--.*: 04cb0800 umin z0\.d, p2/m, z0\.d, z0\.d
--.*: 04cb0800 umin z0\.d, p2/m, z0\.d, z0\.d
--.*: 04cb1c00 umin z0\.d, p7/m, z0\.d, z0\.d
--.*: 04cb1c00 umin z0\.d, p7/m, z0\.d, z0\.d
--.*: 04cb0003 umin z3\.d, p0/m, z3\.d, z0\.d
--.*: 04cb0003 umin z3\.d, p0/m, z3\.d, z0\.d
--.*: 04cb0080 umin z0\.d, p0/m, z0\.d, z4\.d
--.*: 04cb0080 umin z0\.d, p0/m, z0\.d, z4\.d
--.*: 04cb03e0 umin z0\.d, p0/m, z0\.d, z31\.d
--.*: 04cb03e0 umin z0\.d, p0/m, z0\.d, z31\.d
--.*: 040b2000 uminv b0, p0, z0\.b
--.*: 040b2000 uminv b0, p0, z0\.b
--.*: 040b2001 uminv b1, p0, z0\.b
--.*: 040b2001 uminv b1, p0, z0\.b
--.*: 040b201f uminv b31, p0, z0\.b
--.*: 040b201f uminv b31, p0, z0\.b
--.*: 040b2800 uminv b0, p2, z0\.b
--.*: 040b2800 uminv b0, p2, z0\.b
--.*: 040b3c00 uminv b0, p7, z0\.b
--.*: 040b3c00 uminv b0, p7, z0\.b
--.*: 040b2060 uminv b0, p0, z3\.b
--.*: 040b2060 uminv b0, p0, z3\.b
--.*: 040b23e0 uminv b0, p0, z31\.b
--.*: 040b23e0 uminv b0, p0, z31\.b
--.*: 044b2000 uminv h0, p0, z0\.h
--.*: 044b2000 uminv h0, p0, z0\.h
--.*: 044b2001 uminv h1, p0, z0\.h
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--.*: 044b201f uminv h31, p0, z0\.h
--.*: 044b201f uminv h31, p0, z0\.h
--.*: 044b2800 uminv h0, p2, z0\.h
--.*: 044b2800 uminv h0, p2, z0\.h
--.*: 044b3c00 uminv h0, p7, z0\.h
--.*: 044b3c00 uminv h0, p7, z0\.h
--.*: 044b2060 uminv h0, p0, z3\.h
--.*: 044b2060 uminv h0, p0, z3\.h
--.*: 044b23e0 uminv h0, p0, z31\.h
--.*: 044b23e0 uminv h0, p0, z31\.h
--.*: 048b2000 uminv s0, p0, z0\.s
--.*: 048b2000 uminv s0, p0, z0\.s
--.*: 048b2001 uminv s1, p0, z0\.s
--.*: 048b2001 uminv s1, p0, z0\.s
--.*: 048b201f uminv s31, p0, z0\.s
--.*: 048b201f uminv s31, p0, z0\.s
--.*: 048b2800 uminv s0, p2, z0\.s
--.*: 048b2800 uminv s0, p2, z0\.s
--.*: 048b3c00 uminv s0, p7, z0\.s
--.*: 048b3c00 uminv s0, p7, z0\.s
--.*: 048b2060 uminv s0, p0, z3\.s
--.*: 048b2060 uminv s0, p0, z3\.s
--.*: 048b23e0 uminv s0, p0, z31\.s
--.*: 048b23e0 uminv s0, p0, z31\.s
--.*: 04cb2000 uminv d0, p0, z0\.d
--.*: 04cb2000 uminv d0, p0, z0\.d
--.*: 04cb2001 uminv d1, p0, z0\.d
--.*: 04cb2001 uminv d1, p0, z0\.d
--.*: 04cb201f uminv d31, p0, z0\.d
--.*: 04cb201f uminv d31, p0, z0\.d
--.*: 04cb2800 uminv d0, p2, z0\.d
--.*: 04cb2800 uminv d0, p2, z0\.d
--.*: 04cb3c00 uminv d0, p7, z0\.d
--.*: 04cb3c00 uminv d0, p7, z0\.d
--.*: 04cb2060 uminv d0, p0, z3\.d
--.*: 04cb2060 uminv d0, p0, z3\.d
--.*: 04cb23e0 uminv d0, p0, z31\.d
--.*: 04cb23e0 uminv d0, p0, z31\.d
--.*: 04130000 umulh z0\.b, p0/m, z0\.b, z0\.b
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--.*: 04130001 umulh z1\.b, p0/m, z1\.b, z0\.b
--.*: 0413001f umulh z31\.b, p0/m, z31\.b, z0\.b
--.*: 0413001f umulh z31\.b, p0/m, z31\.b, z0\.b
--.*: 04130800 umulh z0\.b, p2/m, z0\.b, z0\.b
--.*: 04130800 umulh z0\.b, p2/m, z0\.b, z0\.b
--.*: 04131c00 umulh z0\.b, p7/m, z0\.b, z0\.b
--.*: 04131c00 umulh z0\.b, p7/m, z0\.b, z0\.b
--.*: 04130003 umulh z3\.b, p0/m, z3\.b, z0\.b
--.*: 04130003 umulh z3\.b, p0/m, z3\.b, z0\.b
--.*: 04130080 umulh z0\.b, p0/m, z0\.b, z4\.b
--.*: 04130080 umulh z0\.b, p0/m, z0\.b, z4\.b
--.*: 041303e0 umulh z0\.b, p0/m, z0\.b, z31\.b
--.*: 041303e0 umulh z0\.b, p0/m, z0\.b, z31\.b
--.*: 04530000 umulh z0\.h, p0/m, z0\.h, z0\.h
--.*: 04530000 umulh z0\.h, p0/m, z0\.h, z0\.h
--.*: 04530001 umulh z1\.h, p0/m, z1\.h, z0\.h
--.*: 04530001 umulh z1\.h, p0/m, z1\.h, z0\.h
--.*: 0453001f umulh z31\.h, p0/m, z31\.h, z0\.h
--.*: 0453001f umulh z31\.h, p0/m, z31\.h, z0\.h
--.*: 04530800 umulh z0\.h, p2/m, z0\.h, z0\.h
--.*: 04530800 umulh z0\.h, p2/m, z0\.h, z0\.h
--.*: 04531c00 umulh z0\.h, p7/m, z0\.h, z0\.h
--.*: 04531c00 umulh z0\.h, p7/m, z0\.h, z0\.h
--.*: 04530003 umulh z3\.h, p0/m, z3\.h, z0\.h
--.*: 04530003 umulh z3\.h, p0/m, z3\.h, z0\.h
--.*: 04530080 umulh z0\.h, p0/m, z0\.h, z4\.h
--.*: 04530080 umulh z0\.h, p0/m, z0\.h, z4\.h
--.*: 045303e0 umulh z0\.h, p0/m, z0\.h, z31\.h
--.*: 045303e0 umulh z0\.h, p0/m, z0\.h, z31\.h
--.*: 04930000 umulh z0\.s, p0/m, z0\.s, z0\.s
--.*: 04930000 umulh z0\.s, p0/m, z0\.s, z0\.s
--.*: 04930001 umulh z1\.s, p0/m, z1\.s, z0\.s
--.*: 04930001 umulh z1\.s, p0/m, z1\.s, z0\.s
--.*: 0493001f umulh z31\.s, p0/m, z31\.s, z0\.s
--.*: 0493001f umulh z31\.s, p0/m, z31\.s, z0\.s
--.*: 04930800 umulh z0\.s, p2/m, z0\.s, z0\.s
--.*: 04930800 umulh z0\.s, p2/m, z0\.s, z0\.s
--.*: 04931c00 umulh z0\.s, p7/m, z0\.s, z0\.s
--.*: 04931c00 umulh z0\.s, p7/m, z0\.s, z0\.s
--.*: 04930003 umulh z3\.s, p0/m, z3\.s, z0\.s
--.*: 04930003 umulh z3\.s, p0/m, z3\.s, z0\.s
--.*: 04930080 umulh z0\.s, p0/m, z0\.s, z4\.s
--.*: 04930080 umulh z0\.s, p0/m, z0\.s, z4\.s
--.*: 049303e0 umulh z0\.s, p0/m, z0\.s, z31\.s
--.*: 049303e0 umulh z0\.s, p0/m, z0\.s, z31\.s
--.*: 04d30000 umulh z0\.d, p0/m, z0\.d, z0\.d
--.*: 04d30000 umulh z0\.d, p0/m, z0\.d, z0\.d
--.*: 04d30001 umulh z1\.d, p0/m, z1\.d, z0\.d
--.*: 04d30001 umulh z1\.d, p0/m, z1\.d, z0\.d
--.*: 04d3001f umulh z31\.d, p0/m, z31\.d, z0\.d
--.*: 04d3001f umulh z31\.d, p0/m, z31\.d, z0\.d
--.*: 04d30800 umulh z0\.d, p2/m, z0\.d, z0\.d
--.*: 04d30800 umulh z0\.d, p2/m, z0\.d, z0\.d
--.*: 04d31c00 umulh z0\.d, p7/m, z0\.d, z0\.d
--.*: 04d31c00 umulh z0\.d, p7/m, z0\.d, z0\.d
--.*: 04d30003 umulh z3\.d, p0/m, z3\.d, z0\.d
--.*: 04d30003 umulh z3\.d, p0/m, z3\.d, z0\.d
--.*: 04d30080 umulh z0\.d, p0/m, z0\.d, z4\.d
--.*: 04d30080 umulh z0\.d, p0/m, z0\.d, z4\.d
--.*: 04d303e0 umulh z0\.d, p0/m, z0\.d, z31\.d
--.*: 04d303e0 umulh z0\.d, p0/m, z0\.d, z31\.d
--.*: 04201400 uqadd z0\.b, z0\.b, z0\.b
--.*: 04201400 uqadd z0\.b, z0\.b, z0\.b
--.*: 04201401 uqadd z1\.b, z0\.b, z0\.b
--.*: 04201401 uqadd z1\.b, z0\.b, z0\.b
--.*: 0420141f uqadd z31\.b, z0\.b, z0\.b
--.*: 0420141f uqadd z31\.b, z0\.b, z0\.b
--.*: 04201440 uqadd z0\.b, z2\.b, z0\.b
--.*: 04201440 uqadd z0\.b, z2\.b, z0\.b
--.*: 042017e0 uqadd z0\.b, z31\.b, z0\.b
--.*: 042017e0 uqadd z0\.b, z31\.b, z0\.b
--.*: 04231400 uqadd z0\.b, z0\.b, z3\.b
--.*: 04231400 uqadd z0\.b, z0\.b, z3\.b
--.*: 043f1400 uqadd z0\.b, z0\.b, z31\.b
--.*: 043f1400 uqadd z0\.b, z0\.b, z31\.b
--.*: 04601400 uqadd z0\.h, z0\.h, z0\.h
--.*: 04601400 uqadd z0\.h, z0\.h, z0\.h
--.*: 04601401 uqadd z1\.h, z0\.h, z0\.h
--.*: 04601401 uqadd z1\.h, z0\.h, z0\.h
--.*: 0460141f uqadd z31\.h, z0\.h, z0\.h
--.*: 0460141f uqadd z31\.h, z0\.h, z0\.h
--.*: 04601440 uqadd z0\.h, z2\.h, z0\.h
--.*: 04601440 uqadd z0\.h, z2\.h, z0\.h
--.*: 046017e0 uqadd z0\.h, z31\.h, z0\.h
--.*: 046017e0 uqadd z0\.h, z31\.h, z0\.h
--.*: 04631400 uqadd z0\.h, z0\.h, z3\.h
--.*: 04631400 uqadd z0\.h, z0\.h, z3\.h
--.*: 047f1400 uqadd z0\.h, z0\.h, z31\.h
--.*: 047f1400 uqadd z0\.h, z0\.h, z31\.h
--.*: 04a01400 uqadd z0\.s, z0\.s, z0\.s
--.*: 04a01400 uqadd z0\.s, z0\.s, z0\.s
--.*: 04a01401 uqadd z1\.s, z0\.s, z0\.s
--.*: 04a01401 uqadd z1\.s, z0\.s, z0\.s
--.*: 04a0141f uqadd z31\.s, z0\.s, z0\.s
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--.*: 04a01440 uqadd z0\.s, z2\.s, z0\.s
--.*: 04a01440 uqadd z0\.s, z2\.s, z0\.s
--.*: 04a017e0 uqadd z0\.s, z31\.s, z0\.s
--.*: 04a017e0 uqadd z0\.s, z31\.s, z0\.s
--.*: 04a31400 uqadd z0\.s, z0\.s, z3\.s
--.*: 04a31400 uqadd z0\.s, z0\.s, z3\.s
--.*: 04bf1400 uqadd z0\.s, z0\.s, z31\.s
--.*: 04bf1400 uqadd z0\.s, z0\.s, z31\.s
--.*: 04e01400 uqadd z0\.d, z0\.d, z0\.d
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--.*: 04e01401 uqadd z1\.d, z0\.d, z0\.d
--.*: 04e01401 uqadd z1\.d, z0\.d, z0\.d
--.*: 04e0141f uqadd z31\.d, z0\.d, z0\.d
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--.*: 04e01440 uqadd z0\.d, z2\.d, z0\.d
--.*: 04e01440 uqadd z0\.d, z2\.d, z0\.d
--.*: 04e017e0 uqadd z0\.d, z31\.d, z0\.d
--.*: 04e017e0 uqadd z0\.d, z31\.d, z0\.d
--.*: 04e31400 uqadd z0\.d, z0\.d, z3\.d
--.*: 04e31400 uqadd z0\.d, z0\.d, z3\.d
--.*: 04ff1400 uqadd z0\.d, z0\.d, z31\.d
--.*: 04ff1400 uqadd z0\.d, z0\.d, z31\.d
--.*: 2525c000 uqadd z0\.b, z0\.b, #0
--.*: 2525c000 uqadd z0\.b, z0\.b, #0
--.*: 2525c000 uqadd z0\.b, z0\.b, #0
--.*: 2525c001 uqadd z1\.b, z1\.b, #0
--.*: 2525c001 uqadd z1\.b, z1\.b, #0
--.*: 2525c001 uqadd z1\.b, z1\.b, #0
--.*: 2525c01f uqadd z31\.b, z31\.b, #0
--.*: 2525c01f uqadd z31\.b, z31\.b, #0
--.*: 2525c01f uqadd z31\.b, z31\.b, #0
--.*: 2525c002 uqadd z2\.b, z2\.b, #0
--.*: 2525c002 uqadd z2\.b, z2\.b, #0
--.*: 2525c002 uqadd z2\.b, z2\.b, #0
--.*: 2525cfe0 uqadd z0\.b, z0\.b, #127
--.*: 2525cfe0 uqadd z0\.b, z0\.b, #127
--.*: 2525cfe0 uqadd z0\.b, z0\.b, #127
--.*: 2525d000 uqadd z0\.b, z0\.b, #128
--.*: 2525d000 uqadd z0\.b, z0\.b, #128
--.*: 2525d000 uqadd z0\.b, z0\.b, #128
--.*: 2525d020 uqadd z0\.b, z0\.b, #129
--.*: 2525d020 uqadd z0\.b, z0\.b, #129
--.*: 2525d020 uqadd z0\.b, z0\.b, #129
--.*: 2525dfe0 uqadd z0\.b, z0\.b, #255
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--.*: 2565c000 uqadd z0\.h, z0\.h, #0
--.*: 2565c000 uqadd z0\.h, z0\.h, #0
--.*: 2565c000 uqadd z0\.h, z0\.h, #0
--.*: 2565c001 uqadd z1\.h, z1\.h, #0
--.*: 2565c001 uqadd z1\.h, z1\.h, #0
--.*: 2565c001 uqadd z1\.h, z1\.h, #0
--.*: 2565c01f uqadd z31\.h, z31\.h, #0
--.*: 2565c01f uqadd z31\.h, z31\.h, #0
--.*: 2565c01f uqadd z31\.h, z31\.h, #0
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--.*: 2565c002 uqadd z2\.h, z2\.h, #0
--.*: 2565c002 uqadd z2\.h, z2\.h, #0
--.*: 2565cfe0 uqadd z0\.h, z0\.h, #127
--.*: 2565cfe0 uqadd z0\.h, z0\.h, #127
--.*: 2565cfe0 uqadd z0\.h, z0\.h, #127
--.*: 2565d000 uqadd z0\.h, z0\.h, #128
--.*: 2565d000 uqadd z0\.h, z0\.h, #128
--.*: 2565d000 uqadd z0\.h, z0\.h, #128
--.*: 2565d020 uqadd z0\.h, z0\.h, #129
--.*: 2565d020 uqadd z0\.h, z0\.h, #129
--.*: 2565d020 uqadd z0\.h, z0\.h, #129
--.*: 2565dfe0 uqadd z0\.h, z0\.h, #255
--.*: 2565dfe0 uqadd z0\.h, z0\.h, #255
--.*: 2565dfe0 uqadd z0\.h, z0\.h, #255
--.*: 2565e000 uqadd z0\.h, z0\.h, #0, lsl #8
--.*: 2565e000 uqadd z0\.h, z0\.h, #0, lsl #8
--.*: 2565efe0 uqadd z0\.h, z0\.h, #32512
--.*: 2565efe0 uqadd z0\.h, z0\.h, #32512
--.*: 2565efe0 uqadd z0\.h, z0\.h, #32512
--.*: 2565efe0 uqadd z0\.h, z0\.h, #32512
--.*: 2565f000 uqadd z0\.h, z0\.h, #32768
--.*: 2565f000 uqadd z0\.h, z0\.h, #32768
--.*: 2565f000 uqadd z0\.h, z0\.h, #32768
--.*: 2565f000 uqadd z0\.h, z0\.h, #32768
--.*: 2565f020 uqadd z0\.h, z0\.h, #33024
--.*: 2565f020 uqadd z0\.h, z0\.h, #33024
--.*: 2565f020 uqadd z0\.h, z0\.h, #33024
--.*: 2565f020 uqadd z0\.h, z0\.h, #33024
--.*: 2565ffe0 uqadd z0\.h, z0\.h, #65280
--.*: 2565ffe0 uqadd z0\.h, z0\.h, #65280
--.*: 2565ffe0 uqadd z0\.h, z0\.h, #65280
--.*: 2565ffe0 uqadd z0\.h, z0\.h, #65280
--.*: 25a5c000 uqadd z0\.s, z0\.s, #0
--.*: 25a5c000 uqadd z0\.s, z0\.s, #0
--.*: 25a5c000 uqadd z0\.s, z0\.s, #0
--.*: 25a5c001 uqadd z1\.s, z1\.s, #0
--.*: 25a5c001 uqadd z1\.s, z1\.s, #0
--.*: 25a5c001 uqadd z1\.s, z1\.s, #0
--.*: 25a5c01f uqadd z31\.s, z31\.s, #0
--.*: 25a5c01f uqadd z31\.s, z31\.s, #0
--.*: 25a5c01f uqadd z31\.s, z31\.s, #0
--.*: 25a5c002 uqadd z2\.s, z2\.s, #0
--.*: 25a5c002 uqadd z2\.s, z2\.s, #0
--.*: 25a5c002 uqadd z2\.s, z2\.s, #0
--.*: 25a5cfe0 uqadd z0\.s, z0\.s, #127
--.*: 25a5cfe0 uqadd z0\.s, z0\.s, #127
--.*: 25a5cfe0 uqadd z0\.s, z0\.s, #127
--.*: 25a5d000 uqadd z0\.s, z0\.s, #128
--.*: 25a5d000 uqadd z0\.s, z0\.s, #128
--.*: 25a5d000 uqadd z0\.s, z0\.s, #128
--.*: 25a5d020 uqadd z0\.s, z0\.s, #129
--.*: 25a5d020 uqadd z0\.s, z0\.s, #129
--.*: 25a5d020 uqadd z0\.s, z0\.s, #129
--.*: 25a5dfe0 uqadd z0\.s, z0\.s, #255
--.*: 25a5dfe0 uqadd z0\.s, z0\.s, #255
--.*: 25a5dfe0 uqadd z0\.s, z0\.s, #255
--.*: 25a5e000 uqadd z0\.s, z0\.s, #0, lsl #8
--.*: 25a5e000 uqadd z0\.s, z0\.s, #0, lsl #8
--.*: 25a5efe0 uqadd z0\.s, z0\.s, #32512
--.*: 25a5efe0 uqadd z0\.s, z0\.s, #32512
--.*: 25a5efe0 uqadd z0\.s, z0\.s, #32512
--.*: 25a5efe0 uqadd z0\.s, z0\.s, #32512
--.*: 25a5f000 uqadd z0\.s, z0\.s, #32768
--.*: 25a5f000 uqadd z0\.s, z0\.s, #32768
--.*: 25a5f000 uqadd z0\.s, z0\.s, #32768
--.*: 25a5f000 uqadd z0\.s, z0\.s, #32768
--.*: 25a5f020 uqadd z0\.s, z0\.s, #33024
--.*: 25a5f020 uqadd z0\.s, z0\.s, #33024
--.*: 25a5f020 uqadd z0\.s, z0\.s, #33024
--.*: 25a5f020 uqadd z0\.s, z0\.s, #33024
--.*: 25a5ffe0 uqadd z0\.s, z0\.s, #65280
--.*: 25a5ffe0 uqadd z0\.s, z0\.s, #65280
--.*: 25a5ffe0 uqadd z0\.s, z0\.s, #65280
--.*: 25a5ffe0 uqadd z0\.s, z0\.s, #65280
--.*: 25e5c000 uqadd z0\.d, z0\.d, #0
--.*: 25e5c000 uqadd z0\.d, z0\.d, #0
--.*: 25e5c000 uqadd z0\.d, z0\.d, #0
--.*: 25e5c001 uqadd z1\.d, z1\.d, #0
--.*: 25e5c001 uqadd z1\.d, z1\.d, #0
--.*: 25e5c001 uqadd z1\.d, z1\.d, #0
--.*: 25e5c01f uqadd z31\.d, z31\.d, #0
--.*: 25e5c01f uqadd z31\.d, z31\.d, #0
--.*: 25e5c01f uqadd z31\.d, z31\.d, #0
--.*: 25e5c002 uqadd z2\.d, z2\.d, #0
--.*: 25e5c002 uqadd z2\.d, z2\.d, #0
--.*: 25e5c002 uqadd z2\.d, z2\.d, #0
--.*: 25e5cfe0 uqadd z0\.d, z0\.d, #127
--.*: 25e5cfe0 uqadd z0\.d, z0\.d, #127
--.*: 25e5cfe0 uqadd z0\.d, z0\.d, #127
--.*: 25e5d000 uqadd z0\.d, z0\.d, #128
--.*: 25e5d000 uqadd z0\.d, z0\.d, #128
--.*: 25e5d000 uqadd z0\.d, z0\.d, #128
--.*: 25e5d020 uqadd z0\.d, z0\.d, #129
--.*: 25e5d020 uqadd z0\.d, z0\.d, #129
--.*: 25e5d020 uqadd z0\.d, z0\.d, #129
--.*: 25e5dfe0 uqadd z0\.d, z0\.d, #255
--.*: 25e5dfe0 uqadd z0\.d, z0\.d, #255
--.*: 25e5dfe0 uqadd z0\.d, z0\.d, #255
--.*: 25e5e000 uqadd z0\.d, z0\.d, #0, lsl #8
--.*: 25e5e000 uqadd z0\.d, z0\.d, #0, lsl #8
--.*: 25e5efe0 uqadd z0\.d, z0\.d, #32512
--.*: 25e5efe0 uqadd z0\.d, z0\.d, #32512
--.*: 25e5efe0 uqadd z0\.d, z0\.d, #32512
--.*: 25e5efe0 uqadd z0\.d, z0\.d, #32512
--.*: 25e5f000 uqadd z0\.d, z0\.d, #32768
--.*: 25e5f000 uqadd z0\.d, z0\.d, #32768
--.*: 25e5f000 uqadd z0\.d, z0\.d, #32768
--.*: 25e5f000 uqadd z0\.d, z0\.d, #32768
--.*: 25e5f020 uqadd z0\.d, z0\.d, #33024
--.*: 25e5f020 uqadd z0\.d, z0\.d, #33024
--.*: 25e5f020 uqadd z0\.d, z0\.d, #33024
--.*: 25e5f020 uqadd z0\.d, z0\.d, #33024
--.*: 25e5ffe0 uqadd z0\.d, z0\.d, #65280
--.*: 25e5ffe0 uqadd z0\.d, z0\.d, #65280
--.*: 25e5ffe0 uqadd z0\.d, z0\.d, #65280
--.*: 25e5ffe0 uqadd z0\.d, z0\.d, #65280
--.*: 0420fc00 uqdecb w0, pow2
--.*: 0420fc00 uqdecb w0, pow2
--.*: 0420fc00 uqdecb w0, pow2
--.*: 0420fc01 uqdecb w1, pow2
--.*: 0420fc01 uqdecb w1, pow2
--.*: 0420fc01 uqdecb w1, pow2
--.*: 0420fc1f uqdecb wzr, pow2
--.*: 0420fc1f uqdecb wzr, pow2
--.*: 0420fc1f uqdecb wzr, pow2
--.*: 0420fc20 uqdecb w0, vl1
--.*: 0420fc20 uqdecb w0, vl1
--.*: 0420fc20 uqdecb w0, vl1
--.*: 0420fc40 uqdecb w0, vl2
--.*: 0420fc40 uqdecb w0, vl2
--.*: 0420fc40 uqdecb w0, vl2
--.*: 0420fc60 uqdecb w0, vl3
--.*: 0420fc60 uqdecb w0, vl3
--.*: 0420fc60 uqdecb w0, vl3
--.*: 0420fc80 uqdecb w0, vl4
--.*: 0420fc80 uqdecb w0, vl4
--.*: 0420fc80 uqdecb w0, vl4
--.*: 0420fca0 uqdecb w0, vl5
--.*: 0420fca0 uqdecb w0, vl5
--.*: 0420fca0 uqdecb w0, vl5
--.*: 0420fcc0 uqdecb w0, vl6
--.*: 0420fcc0 uqdecb w0, vl6
--.*: 0420fcc0 uqdecb w0, vl6
--.*: 0420fce0 uqdecb w0, vl7
--.*: 0420fce0 uqdecb w0, vl7
--.*: 0420fce0 uqdecb w0, vl7
--.*: 0420fd00 uqdecb w0, vl8
--.*: 0420fd00 uqdecb w0, vl8
--.*: 0420fd00 uqdecb w0, vl8
--.*: 0420fd20 uqdecb w0, vl16
--.*: 0420fd20 uqdecb w0, vl16
--.*: 0420fd20 uqdecb w0, vl16
--.*: 0420fd40 uqdecb w0, vl32
--.*: 0420fd40 uqdecb w0, vl32
--.*: 0420fd40 uqdecb w0, vl32
--.*: 0420fd60 uqdecb w0, vl64
--.*: 0420fd60 uqdecb w0, vl64
--.*: 0420fd60 uqdecb w0, vl64
--.*: 0420fd80 uqdecb w0, vl128
--.*: 0420fd80 uqdecb w0, vl128
--.*: 0420fd80 uqdecb w0, vl128
--.*: 0420fda0 uqdecb w0, vl256
--.*: 0420fda0 uqdecb w0, vl256
--.*: 0420fda0 uqdecb w0, vl256
--.*: 0420fdc0 uqdecb w0, #14
--.*: 0420fdc0 uqdecb w0, #14
--.*: 0420fdc0 uqdecb w0, #14
--.*: 0420fde0 uqdecb w0, #15
--.*: 0420fde0 uqdecb w0, #15
--.*: 0420fde0 uqdecb w0, #15
--.*: 0420fe00 uqdecb w0, #16
--.*: 0420fe00 uqdecb w0, #16
--.*: 0420fe00 uqdecb w0, #16
--.*: 0420fe20 uqdecb w0, #17
--.*: 0420fe20 uqdecb w0, #17
--.*: 0420fe20 uqdecb w0, #17
--.*: 0420fe40 uqdecb w0, #18
--.*: 0420fe40 uqdecb w0, #18
--.*: 0420fe40 uqdecb w0, #18
--.*: 0420fe60 uqdecb w0, #19
--.*: 0420fe60 uqdecb w0, #19
--.*: 0420fe60 uqdecb w0, #19
--.*: 0420fe80 uqdecb w0, #20
--.*: 0420fe80 uqdecb w0, #20
--.*: 0420fe80 uqdecb w0, #20
--.*: 0420fea0 uqdecb w0, #21
--.*: 0420fea0 uqdecb w0, #21
--.*: 0420fea0 uqdecb w0, #21
--.*: 0420fec0 uqdecb w0, #22
--.*: 0420fec0 uqdecb w0, #22
--.*: 0420fec0 uqdecb w0, #22
--.*: 0420fee0 uqdecb w0, #23
--.*: 0420fee0 uqdecb w0, #23
--.*: 0420fee0 uqdecb w0, #23
--.*: 0420ff00 uqdecb w0, #24
--.*: 0420ff00 uqdecb w0, #24
--.*: 0420ff00 uqdecb w0, #24
--.*: 0420ff20 uqdecb w0, #25
--.*: 0420ff20 uqdecb w0, #25
--.*: 0420ff20 uqdecb w0, #25
--.*: 0420ff40 uqdecb w0, #26
--.*: 0420ff40 uqdecb w0, #26
--.*: 0420ff40 uqdecb w0, #26
--.*: 0420ff60 uqdecb w0, #27
--.*: 0420ff60 uqdecb w0, #27
--.*: 0420ff60 uqdecb w0, #27
--.*: 0420ff80 uqdecb w0, #28
--.*: 0420ff80 uqdecb w0, #28
--.*: 0420ff80 uqdecb w0, #28
--.*: 0420ffa0 uqdecb w0, mul4
--.*: 0420ffa0 uqdecb w0, mul4
--.*: 0420ffa0 uqdecb w0, mul4
--.*: 0420ffc0 uqdecb w0, mul3
--.*: 0420ffc0 uqdecb w0, mul3
--.*: 0420ffc0 uqdecb w0, mul3
--.*: 0420ffe0 uqdecb w0
--.*: 0420ffe0 uqdecb w0
--.*: 0420ffe0 uqdecb w0
--.*: 0420ffe0 uqdecb w0
--.*: 0427fc00 uqdecb w0, pow2, mul #8
--.*: 0427fc00 uqdecb w0, pow2, mul #8
--.*: 0428fc00 uqdecb w0, pow2, mul #9
--.*: 0428fc00 uqdecb w0, pow2, mul #9
--.*: 0429fc00 uqdecb w0, pow2, mul #10
--.*: 0429fc00 uqdecb w0, pow2, mul #10
--.*: 042ffc00 uqdecb w0, pow2, mul #16
--.*: 042ffc00 uqdecb w0, pow2, mul #16
--.*: 0430fc00 uqdecb x0, pow2
--.*: 0430fc00 uqdecb x0, pow2
--.*: 0430fc00 uqdecb x0, pow2
--.*: 0430fc01 uqdecb x1, pow2
--.*: 0430fc01 uqdecb x1, pow2
--.*: 0430fc01 uqdecb x1, pow2
--.*: 0430fc1f uqdecb xzr, pow2
--.*: 0430fc1f uqdecb xzr, pow2
--.*: 0430fc1f uqdecb xzr, pow2
--.*: 0430fc20 uqdecb x0, vl1
--.*: 0430fc20 uqdecb x0, vl1
--.*: 0430fc20 uqdecb x0, vl1
--.*: 0430fc40 uqdecb x0, vl2
--.*: 0430fc40 uqdecb x0, vl2
--.*: 0430fc40 uqdecb x0, vl2
--.*: 0430fc60 uqdecb x0, vl3
--.*: 0430fc60 uqdecb x0, vl3
--.*: 0430fc60 uqdecb x0, vl3
--.*: 0430fc80 uqdecb x0, vl4
--.*: 0430fc80 uqdecb x0, vl4
--.*: 0430fc80 uqdecb x0, vl4
--.*: 0430fca0 uqdecb x0, vl5
--.*: 0430fca0 uqdecb x0, vl5
--.*: 0430fca0 uqdecb x0, vl5
--.*: 0430fcc0 uqdecb x0, vl6
--.*: 0430fcc0 uqdecb x0, vl6
--.*: 0430fcc0 uqdecb x0, vl6
--.*: 0430fce0 uqdecb x0, vl7
--.*: 0430fce0 uqdecb x0, vl7
--.*: 0430fce0 uqdecb x0, vl7
--.*: 0430fd00 uqdecb x0, vl8
--.*: 0430fd00 uqdecb x0, vl8
--.*: 0430fd00 uqdecb x0, vl8
--.*: 0430fd20 uqdecb x0, vl16
--.*: 0430fd20 uqdecb x0, vl16
--.*: 0430fd20 uqdecb x0, vl16
--.*: 0430fd40 uqdecb x0, vl32
--.*: 0430fd40 uqdecb x0, vl32
--.*: 0430fd40 uqdecb x0, vl32
--.*: 0430fd60 uqdecb x0, vl64
--.*: 0430fd60 uqdecb x0, vl64
--.*: 0430fd60 uqdecb x0, vl64
--.*: 0430fd80 uqdecb x0, vl128
--.*: 0430fd80 uqdecb x0, vl128
--.*: 0430fd80 uqdecb x0, vl128
--.*: 0430fda0 uqdecb x0, vl256
--.*: 0430fda0 uqdecb x0, vl256
--.*: 0430fda0 uqdecb x0, vl256
--.*: 0430fdc0 uqdecb x0, #14
--.*: 0430fdc0 uqdecb x0, #14
--.*: 0430fdc0 uqdecb x0, #14
--.*: 0430fde0 uqdecb x0, #15
--.*: 0430fde0 uqdecb x0, #15
--.*: 0430fde0 uqdecb x0, #15
--.*: 0430fe00 uqdecb x0, #16
--.*: 0430fe00 uqdecb x0, #16
--.*: 0430fe00 uqdecb x0, #16
--.*: 0430fe20 uqdecb x0, #17
--.*: 0430fe20 uqdecb x0, #17
--.*: 0430fe20 uqdecb x0, #17
--.*: 0430fe40 uqdecb x0, #18
--.*: 0430fe40 uqdecb x0, #18
--.*: 0430fe40 uqdecb x0, #18
--.*: 0430fe60 uqdecb x0, #19
--.*: 0430fe60 uqdecb x0, #19
--.*: 0430fe60 uqdecb x0, #19
--.*: 0430fe80 uqdecb x0, #20
--.*: 0430fe80 uqdecb x0, #20
--.*: 0430fe80 uqdecb x0, #20
--.*: 0430fea0 uqdecb x0, #21
--.*: 0430fea0 uqdecb x0, #21
--.*: 0430fea0 uqdecb x0, #21
--.*: 0430fec0 uqdecb x0, #22
--.*: 0430fec0 uqdecb x0, #22
--.*: 0430fec0 uqdecb x0, #22
--.*: 0430fee0 uqdecb x0, #23
--.*: 0430fee0 uqdecb x0, #23
--.*: 0430fee0 uqdecb x0, #23
--.*: 0430ff00 uqdecb x0, #24
--.*: 0430ff00 uqdecb x0, #24
--.*: 0430ff00 uqdecb x0, #24
--.*: 0430ff20 uqdecb x0, #25
--.*: 0430ff20 uqdecb x0, #25
--.*: 0430ff20 uqdecb x0, #25
--.*: 0430ff40 uqdecb x0, #26
--.*: 0430ff40 uqdecb x0, #26
--.*: 0430ff40 uqdecb x0, #26
--.*: 0430ff60 uqdecb x0, #27
--.*: 0430ff60 uqdecb x0, #27
--.*: 0430ff60 uqdecb x0, #27
--.*: 0430ff80 uqdecb x0, #28
--.*: 0430ff80 uqdecb x0, #28
--.*: 0430ff80 uqdecb x0, #28
--.*: 0430ffa0 uqdecb x0, mul4
--.*: 0430ffa0 uqdecb x0, mul4
--.*: 0430ffa0 uqdecb x0, mul4
--.*: 0430ffc0 uqdecb x0, mul3
--.*: 0430ffc0 uqdecb x0, mul3
--.*: 0430ffc0 uqdecb x0, mul3
--.*: 0430ffe0 uqdecb x0
--.*: 0430ffe0 uqdecb x0
--.*: 0430ffe0 uqdecb x0
--.*: 0430ffe0 uqdecb x0
--.*: 0437fc00 uqdecb x0, pow2, mul #8
--.*: 0437fc00 uqdecb x0, pow2, mul #8
--.*: 0438fc00 uqdecb x0, pow2, mul #9
--.*: 0438fc00 uqdecb x0, pow2, mul #9
--.*: 0439fc00 uqdecb x0, pow2, mul #10
--.*: 0439fc00 uqdecb x0, pow2, mul #10
--.*: 043ffc00 uqdecb x0, pow2, mul #16
--.*: 043ffc00 uqdecb x0, pow2, mul #16
--.*: 04e0cc00 uqdecd z0\.d, pow2
--.*: 04e0cc00 uqdecd z0\.d, pow2
--.*: 04e0cc00 uqdecd z0\.d, pow2
--.*: 04e0cc01 uqdecd z1\.d, pow2
--.*: 04e0cc01 uqdecd z1\.d, pow2
--.*: 04e0cc01 uqdecd z1\.d, pow2
--.*: 04e0cc1f uqdecd z31\.d, pow2
--.*: 04e0cc1f uqdecd z31\.d, pow2
--.*: 04e0cc1f uqdecd z31\.d, pow2
--.*: 04e0cc20 uqdecd z0\.d, vl1
--.*: 04e0cc20 uqdecd z0\.d, vl1
--.*: 04e0cc20 uqdecd z0\.d, vl1
--.*: 04e0cc40 uqdecd z0\.d, vl2
--.*: 04e0cc40 uqdecd z0\.d, vl2
--.*: 04e0cc40 uqdecd z0\.d, vl2
--.*: 04e0cc60 uqdecd z0\.d, vl3
--.*: 04e0cc60 uqdecd z0\.d, vl3
--.*: 04e0cc60 uqdecd z0\.d, vl3
--.*: 04e0cc80 uqdecd z0\.d, vl4
--.*: 04e0cc80 uqdecd z0\.d, vl4
--.*: 04e0cc80 uqdecd z0\.d, vl4
--.*: 04e0cca0 uqdecd z0\.d, vl5
--.*: 04e0cca0 uqdecd z0\.d, vl5
--.*: 04e0cca0 uqdecd z0\.d, vl5
--.*: 04e0ccc0 uqdecd z0\.d, vl6
--.*: 04e0ccc0 uqdecd z0\.d, vl6
--.*: 04e0ccc0 uqdecd z0\.d, vl6
--.*: 04e0cce0 uqdecd z0\.d, vl7
--.*: 04e0cce0 uqdecd z0\.d, vl7
--.*: 04e0cce0 uqdecd z0\.d, vl7
--.*: 04e0cd00 uqdecd z0\.d, vl8
--.*: 04e0cd00 uqdecd z0\.d, vl8
--.*: 04e0cd00 uqdecd z0\.d, vl8
--.*: 04e0cd20 uqdecd z0\.d, vl16
--.*: 04e0cd20 uqdecd z0\.d, vl16
--.*: 04e0cd20 uqdecd z0\.d, vl16
--.*: 04e0cd40 uqdecd z0\.d, vl32
--.*: 04e0cd40 uqdecd z0\.d, vl32
--.*: 04e0cd40 uqdecd z0\.d, vl32
--.*: 04e0cd60 uqdecd z0\.d, vl64
--.*: 04e0cd60 uqdecd z0\.d, vl64
--.*: 04e0cd60 uqdecd z0\.d, vl64
--.*: 04e0cd80 uqdecd z0\.d, vl128
--.*: 04e0cd80 uqdecd z0\.d, vl128
--.*: 04e0cd80 uqdecd z0\.d, vl128
--.*: 04e0cda0 uqdecd z0\.d, vl256
--.*: 04e0cda0 uqdecd z0\.d, vl256
--.*: 04e0cda0 uqdecd z0\.d, vl256
--.*: 04e0cdc0 uqdecd z0\.d, #14
--.*: 04e0cdc0 uqdecd z0\.d, #14
--.*: 04e0cdc0 uqdecd z0\.d, #14
--.*: 04e0cde0 uqdecd z0\.d, #15
--.*: 04e0cde0 uqdecd z0\.d, #15
--.*: 04e0cde0 uqdecd z0\.d, #15
--.*: 04e0ce00 uqdecd z0\.d, #16
--.*: 04e0ce00 uqdecd z0\.d, #16
--.*: 04e0ce00 uqdecd z0\.d, #16
--.*: 04e0ce20 uqdecd z0\.d, #17
--.*: 04e0ce20 uqdecd z0\.d, #17
--.*: 04e0ce20 uqdecd z0\.d, #17
--.*: 04e0ce40 uqdecd z0\.d, #18
--.*: 04e0ce40 uqdecd z0\.d, #18
--.*: 04e0ce40 uqdecd z0\.d, #18
--.*: 04e0ce60 uqdecd z0\.d, #19
--.*: 04e0ce60 uqdecd z0\.d, #19
--.*: 04e0ce60 uqdecd z0\.d, #19
--.*: 04e0ce80 uqdecd z0\.d, #20
--.*: 04e0ce80 uqdecd z0\.d, #20
--.*: 04e0ce80 uqdecd z0\.d, #20
--.*: 04e0cea0 uqdecd z0\.d, #21
--.*: 04e0cea0 uqdecd z0\.d, #21
--.*: 04e0cea0 uqdecd z0\.d, #21
--.*: 04e0cec0 uqdecd z0\.d, #22
--.*: 04e0cec0 uqdecd z0\.d, #22
--.*: 04e0cec0 uqdecd z0\.d, #22
--.*: 04e0cee0 uqdecd z0\.d, #23
--.*: 04e0cee0 uqdecd z0\.d, #23
--.*: 04e0cee0 uqdecd z0\.d, #23
--.*: 04e0cf00 uqdecd z0\.d, #24
--.*: 04e0cf00 uqdecd z0\.d, #24
--.*: 04e0cf00 uqdecd z0\.d, #24
--.*: 04e0cf20 uqdecd z0\.d, #25
--.*: 04e0cf20 uqdecd z0\.d, #25
--.*: 04e0cf20 uqdecd z0\.d, #25
--.*: 04e0cf40 uqdecd z0\.d, #26
--.*: 04e0cf40 uqdecd z0\.d, #26
--.*: 04e0cf40 uqdecd z0\.d, #26
--.*: 04e0cf60 uqdecd z0\.d, #27
--.*: 04e0cf60 uqdecd z0\.d, #27
--.*: 04e0cf60 uqdecd z0\.d, #27
--.*: 04e0cf80 uqdecd z0\.d, #28
--.*: 04e0cf80 uqdecd z0\.d, #28
--.*: 04e0cf80 uqdecd z0\.d, #28
--.*: 04e0cfa0 uqdecd z0\.d, mul4
--.*: 04e0cfa0 uqdecd z0\.d, mul4
--.*: 04e0cfa0 uqdecd z0\.d, mul4
--.*: 04e0cfc0 uqdecd z0\.d, mul3
--.*: 04e0cfc0 uqdecd z0\.d, mul3
--.*: 04e0cfc0 uqdecd z0\.d, mul3
--.*: 04e0cfe0 uqdecd z0\.d
--.*: 04e0cfe0 uqdecd z0\.d
--.*: 04e0cfe0 uqdecd z0\.d
--.*: 04e0cfe0 uqdecd z0\.d
--.*: 04e7cc00 uqdecd z0\.d, pow2, mul #8
--.*: 04e7cc00 uqdecd z0\.d, pow2, mul #8
--.*: 04e8cc00 uqdecd z0\.d, pow2, mul #9
--.*: 04e8cc00 uqdecd z0\.d, pow2, mul #9
--.*: 04e9cc00 uqdecd z0\.d, pow2, mul #10
--.*: 04e9cc00 uqdecd z0\.d, pow2, mul #10
--.*: 04efcc00 uqdecd z0\.d, pow2, mul #16
--.*: 04efcc00 uqdecd z0\.d, pow2, mul #16
--.*: 04e0fc00 uqdecd w0, pow2
--.*: 04e0fc00 uqdecd w0, pow2
--.*: 04e0fc00 uqdecd w0, pow2
--.*: 04e0fc01 uqdecd w1, pow2
--.*: 04e0fc01 uqdecd w1, pow2
--.*: 04e0fc01 uqdecd w1, pow2
--.*: 04e0fc1f uqdecd wzr, pow2
--.*: 04e0fc1f uqdecd wzr, pow2
--.*: 04e0fc1f uqdecd wzr, pow2
--.*: 04e0fc20 uqdecd w0, vl1
--.*: 04e0fc20 uqdecd w0, vl1
--.*: 04e0fc20 uqdecd w0, vl1
--.*: 04e0fc40 uqdecd w0, vl2
--.*: 04e0fc40 uqdecd w0, vl2
--.*: 04e0fc40 uqdecd w0, vl2
--.*: 04e0fc60 uqdecd w0, vl3
--.*: 04e0fc60 uqdecd w0, vl3
--.*: 04e0fc60 uqdecd w0, vl3
--.*: 04e0fc80 uqdecd w0, vl4
--.*: 04e0fc80 uqdecd w0, vl4
--.*: 04e0fc80 uqdecd w0, vl4
--.*: 04e0fca0 uqdecd w0, vl5
--.*: 04e0fca0 uqdecd w0, vl5
--.*: 04e0fca0 uqdecd w0, vl5
--.*: 04e0fcc0 uqdecd w0, vl6
--.*: 04e0fcc0 uqdecd w0, vl6
--.*: 04e0fcc0 uqdecd w0, vl6
--.*: 04e0fce0 uqdecd w0, vl7
--.*: 04e0fce0 uqdecd w0, vl7
--.*: 04e0fce0 uqdecd w0, vl7
--.*: 04e0fd00 uqdecd w0, vl8
--.*: 04e0fd00 uqdecd w0, vl8
--.*: 04e0fd00 uqdecd w0, vl8
--.*: 04e0fd20 uqdecd w0, vl16
--.*: 04e0fd20 uqdecd w0, vl16
--.*: 04e0fd20 uqdecd w0, vl16
--.*: 04e0fd40 uqdecd w0, vl32
--.*: 04e0fd40 uqdecd w0, vl32
--.*: 04e0fd40 uqdecd w0, vl32
--.*: 04e0fd60 uqdecd w0, vl64
--.*: 04e0fd60 uqdecd w0, vl64
--.*: 04e0fd60 uqdecd w0, vl64
--.*: 04e0fd80 uqdecd w0, vl128
--.*: 04e0fd80 uqdecd w0, vl128
--.*: 04e0fd80 uqdecd w0, vl128
--.*: 04e0fda0 uqdecd w0, vl256
--.*: 04e0fda0 uqdecd w0, vl256
--.*: 04e0fda0 uqdecd w0, vl256
--.*: 04e0fdc0 uqdecd w0, #14
--.*: 04e0fdc0 uqdecd w0, #14
--.*: 04e0fdc0 uqdecd w0, #14
--.*: 04e0fde0 uqdecd w0, #15
--.*: 04e0fde0 uqdecd w0, #15
--.*: 04e0fde0 uqdecd w0, #15
--.*: 04e0fe00 uqdecd w0, #16
--.*: 04e0fe00 uqdecd w0, #16
--.*: 04e0fe00 uqdecd w0, #16
--.*: 04e0fe20 uqdecd w0, #17
--.*: 04e0fe20 uqdecd w0, #17
--.*: 04e0fe20 uqdecd w0, #17
--.*: 04e0fe40 uqdecd w0, #18
--.*: 04e0fe40 uqdecd w0, #18
--.*: 04e0fe40 uqdecd w0, #18
--.*: 04e0fe60 uqdecd w0, #19
--.*: 04e0fe60 uqdecd w0, #19
--.*: 04e0fe60 uqdecd w0, #19
--.*: 04e0fe80 uqdecd w0, #20
--.*: 04e0fe80 uqdecd w0, #20
--.*: 04e0fe80 uqdecd w0, #20
--.*: 04e0fea0 uqdecd w0, #21
--.*: 04e0fea0 uqdecd w0, #21
--.*: 04e0fea0 uqdecd w0, #21
--.*: 04e0fec0 uqdecd w0, #22
--.*: 04e0fec0 uqdecd w0, #22
--.*: 04e0fec0 uqdecd w0, #22
--.*: 04e0fee0 uqdecd w0, #23
--.*: 04e0fee0 uqdecd w0, #23
--.*: 04e0fee0 uqdecd w0, #23
--.*: 04e0ff00 uqdecd w0, #24
--.*: 04e0ff00 uqdecd w0, #24
--.*: 04e0ff00 uqdecd w0, #24
--.*: 04e0ff20 uqdecd w0, #25
--.*: 04e0ff20 uqdecd w0, #25
--.*: 04e0ff20 uqdecd w0, #25
--.*: 04e0ff40 uqdecd w0, #26
--.*: 04e0ff40 uqdecd w0, #26
--.*: 04e0ff40 uqdecd w0, #26
--.*: 04e0ff60 uqdecd w0, #27
--.*: 04e0ff60 uqdecd w0, #27
--.*: 04e0ff60 uqdecd w0, #27
--.*: 04e0ff80 uqdecd w0, #28
--.*: 04e0ff80 uqdecd w0, #28
--.*: 04e0ff80 uqdecd w0, #28
--.*: 04e0ffa0 uqdecd w0, mul4
--.*: 04e0ffa0 uqdecd w0, mul4
--.*: 04e0ffa0 uqdecd w0, mul4
--.*: 04e0ffc0 uqdecd w0, mul3
--.*: 04e0ffc0 uqdecd w0, mul3
--.*: 04e0ffc0 uqdecd w0, mul3
--.*: 04e0ffe0 uqdecd w0
--.*: 04e0ffe0 uqdecd w0
--.*: 04e0ffe0 uqdecd w0
--.*: 04e0ffe0 uqdecd w0
--.*: 04e7fc00 uqdecd w0, pow2, mul #8
--.*: 04e7fc00 uqdecd w0, pow2, mul #8
--.*: 04e8fc00 uqdecd w0, pow2, mul #9
--.*: 04e8fc00 uqdecd w0, pow2, mul #9
--.*: 04e9fc00 uqdecd w0, pow2, mul #10
--.*: 04e9fc00 uqdecd w0, pow2, mul #10
--.*: 04effc00 uqdecd w0, pow2, mul #16
--.*: 04effc00 uqdecd w0, pow2, mul #16
--.*: 04f0fc00 uqdecd x0, pow2
--.*: 04f0fc00 uqdecd x0, pow2
--.*: 04f0fc00 uqdecd x0, pow2
--.*: 04f0fc01 uqdecd x1, pow2
--.*: 04f0fc01 uqdecd x1, pow2
--.*: 04f0fc01 uqdecd x1, pow2
--.*: 04f0fc1f uqdecd xzr, pow2
--.*: 04f0fc1f uqdecd xzr, pow2
--.*: 04f0fc1f uqdecd xzr, pow2
--.*: 04f0fc20 uqdecd x0, vl1
--.*: 04f0fc20 uqdecd x0, vl1
--.*: 04f0fc20 uqdecd x0, vl1
--.*: 04f0fc40 uqdecd x0, vl2
--.*: 04f0fc40 uqdecd x0, vl2
--.*: 04f0fc40 uqdecd x0, vl2
--.*: 04f0fc60 uqdecd x0, vl3
--.*: 04f0fc60 uqdecd x0, vl3
--.*: 04f0fc60 uqdecd x0, vl3
--.*: 04f0fc80 uqdecd x0, vl4
--.*: 04f0fc80 uqdecd x0, vl4
--.*: 04f0fc80 uqdecd x0, vl4
--.*: 04f0fca0 uqdecd x0, vl5
--.*: 04f0fca0 uqdecd x0, vl5
--.*: 04f0fca0 uqdecd x0, vl5
--.*: 04f0fcc0 uqdecd x0, vl6
--.*: 04f0fcc0 uqdecd x0, vl6
--.*: 04f0fcc0 uqdecd x0, vl6
--.*: 04f0fce0 uqdecd x0, vl7
--.*: 04f0fce0 uqdecd x0, vl7
--.*: 04f0fce0 uqdecd x0, vl7
--.*: 04f0fd00 uqdecd x0, vl8
--.*: 04f0fd00 uqdecd x0, vl8
--.*: 04f0fd00 uqdecd x0, vl8
--.*: 04f0fd20 uqdecd x0, vl16
--.*: 04f0fd20 uqdecd x0, vl16
--.*: 04f0fd20 uqdecd x0, vl16
--.*: 04f0fd40 uqdecd x0, vl32
--.*: 04f0fd40 uqdecd x0, vl32
--.*: 04f0fd40 uqdecd x0, vl32
--.*: 04f0fd60 uqdecd x0, vl64
--.*: 04f0fd60 uqdecd x0, vl64
--.*: 04f0fd60 uqdecd x0, vl64
--.*: 04f0fd80 uqdecd x0, vl128
--.*: 04f0fd80 uqdecd x0, vl128
--.*: 04f0fd80 uqdecd x0, vl128
--.*: 04f0fda0 uqdecd x0, vl256
--.*: 04f0fda0 uqdecd x0, vl256
--.*: 04f0fda0 uqdecd x0, vl256
--.*: 04f0fdc0 uqdecd x0, #14
--.*: 04f0fdc0 uqdecd x0, #14
--.*: 04f0fdc0 uqdecd x0, #14
--.*: 04f0fde0 uqdecd x0, #15
--.*: 04f0fde0 uqdecd x0, #15
--.*: 04f0fde0 uqdecd x0, #15
--.*: 04f0fe00 uqdecd x0, #16
--.*: 04f0fe00 uqdecd x0, #16
--.*: 04f0fe00 uqdecd x0, #16
--.*: 04f0fe20 uqdecd x0, #17
--.*: 04f0fe20 uqdecd x0, #17
--.*: 04f0fe20 uqdecd x0, #17
--.*: 04f0fe40 uqdecd x0, #18
--.*: 04f0fe40 uqdecd x0, #18
--.*: 04f0fe40 uqdecd x0, #18
--.*: 04f0fe60 uqdecd x0, #19
--.*: 04f0fe60 uqdecd x0, #19
--.*: 04f0fe60 uqdecd x0, #19
--.*: 04f0fe80 uqdecd x0, #20
--.*: 04f0fe80 uqdecd x0, #20
--.*: 04f0fe80 uqdecd x0, #20
--.*: 04f0fea0 uqdecd x0, #21
--.*: 04f0fea0 uqdecd x0, #21
--.*: 04f0fea0 uqdecd x0, #21
--.*: 04f0fec0 uqdecd x0, #22
--.*: 04f0fec0 uqdecd x0, #22
--.*: 04f0fec0 uqdecd x0, #22
--.*: 04f0fee0 uqdecd x0, #23
--.*: 04f0fee0 uqdecd x0, #23
--.*: 04f0fee0 uqdecd x0, #23
--.*: 04f0ff00 uqdecd x0, #24
--.*: 04f0ff00 uqdecd x0, #24
--.*: 04f0ff00 uqdecd x0, #24
--.*: 04f0ff20 uqdecd x0, #25
--.*: 04f0ff20 uqdecd x0, #25
--.*: 04f0ff20 uqdecd x0, #25
--.*: 04f0ff40 uqdecd x0, #26
--.*: 04f0ff40 uqdecd x0, #26
--.*: 04f0ff40 uqdecd x0, #26
--.*: 04f0ff60 uqdecd x0, #27
--.*: 04f0ff60 uqdecd x0, #27
--.*: 04f0ff60 uqdecd x0, #27
--.*: 04f0ff80 uqdecd x0, #28
--.*: 04f0ff80 uqdecd x0, #28
--.*: 04f0ff80 uqdecd x0, #28
--.*: 04f0ffa0 uqdecd x0, mul4
--.*: 04f0ffa0 uqdecd x0, mul4
--.*: 04f0ffa0 uqdecd x0, mul4
--.*: 04f0ffc0 uqdecd x0, mul3
--.*: 04f0ffc0 uqdecd x0, mul3
--.*: 04f0ffc0 uqdecd x0, mul3
--.*: 04f0ffe0 uqdecd x0
--.*: 04f0ffe0 uqdecd x0
--.*: 04f0ffe0 uqdecd x0
--.*: 04f0ffe0 uqdecd x0
--.*: 04f7fc00 uqdecd x0, pow2, mul #8
--.*: 04f7fc00 uqdecd x0, pow2, mul #8
--.*: 04f8fc00 uqdecd x0, pow2, mul #9
--.*: 04f8fc00 uqdecd x0, pow2, mul #9
--.*: 04f9fc00 uqdecd x0, pow2, mul #10
--.*: 04f9fc00 uqdecd x0, pow2, mul #10
--.*: 04fffc00 uqdecd x0, pow2, mul #16
--.*: 04fffc00 uqdecd x0, pow2, mul #16
--.*: 0460cc00 uqdech z0\.h, pow2
--.*: 0460cc00 uqdech z0\.h, pow2
--.*: 0460cc00 uqdech z0\.h, pow2
--.*: 0460cc01 uqdech z1\.h, pow2
--.*: 0460cc01 uqdech z1\.h, pow2
--.*: 0460cc01 uqdech z1\.h, pow2
--.*: 0460cc1f uqdech z31\.h, pow2
--.*: 0460cc1f uqdech z31\.h, pow2
--.*: 0460cc1f uqdech z31\.h, pow2
--.*: 0460cc20 uqdech z0\.h, vl1
--.*: 0460cc20 uqdech z0\.h, vl1
--.*: 0460cc20 uqdech z0\.h, vl1
--.*: 0460cc40 uqdech z0\.h, vl2
--.*: 0460cc40 uqdech z0\.h, vl2
--.*: 0460cc40 uqdech z0\.h, vl2
--.*: 0460cc60 uqdech z0\.h, vl3
--.*: 0460cc60 uqdech z0\.h, vl3
--.*: 0460cc60 uqdech z0\.h, vl3
--.*: 0460cc80 uqdech z0\.h, vl4
--.*: 0460cc80 uqdech z0\.h, vl4
--.*: 0460cc80 uqdech z0\.h, vl4
--.*: 0460cca0 uqdech z0\.h, vl5
--.*: 0460cca0 uqdech z0\.h, vl5
--.*: 0460cca0 uqdech z0\.h, vl5
--.*: 0460ccc0 uqdech z0\.h, vl6
--.*: 0460ccc0 uqdech z0\.h, vl6
--.*: 0460ccc0 uqdech z0\.h, vl6
--.*: 0460cce0 uqdech z0\.h, vl7
--.*: 0460cce0 uqdech z0\.h, vl7
--.*: 0460cce0 uqdech z0\.h, vl7
--.*: 0460cd00 uqdech z0\.h, vl8
--.*: 0460cd00 uqdech z0\.h, vl8
--.*: 0460cd00 uqdech z0\.h, vl8
--.*: 0460cd20 uqdech z0\.h, vl16
--.*: 0460cd20 uqdech z0\.h, vl16
--.*: 0460cd20 uqdech z0\.h, vl16
--.*: 0460cd40 uqdech z0\.h, vl32
--.*: 0460cd40 uqdech z0\.h, vl32
--.*: 0460cd40 uqdech z0\.h, vl32
--.*: 0460cd60 uqdech z0\.h, vl64
--.*: 0460cd60 uqdech z0\.h, vl64
--.*: 0460cd60 uqdech z0\.h, vl64
--.*: 0460cd80 uqdech z0\.h, vl128
--.*: 0460cd80 uqdech z0\.h, vl128
--.*: 0460cd80 uqdech z0\.h, vl128
--.*: 0460cda0 uqdech z0\.h, vl256
--.*: 0460cda0 uqdech z0\.h, vl256
--.*: 0460cda0 uqdech z0\.h, vl256
--.*: 0460cdc0 uqdech z0\.h, #14
--.*: 0460cdc0 uqdech z0\.h, #14
--.*: 0460cdc0 uqdech z0\.h, #14
--.*: 0460cde0 uqdech z0\.h, #15
--.*: 0460cde0 uqdech z0\.h, #15
--.*: 0460cde0 uqdech z0\.h, #15
--.*: 0460ce00 uqdech z0\.h, #16
--.*: 0460ce00 uqdech z0\.h, #16
--.*: 0460ce00 uqdech z0\.h, #16
--.*: 0460ce20 uqdech z0\.h, #17
--.*: 0460ce20 uqdech z0\.h, #17
--.*: 0460ce20 uqdech z0\.h, #17
--.*: 0460ce40 uqdech z0\.h, #18
--.*: 0460ce40 uqdech z0\.h, #18
--.*: 0460ce40 uqdech z0\.h, #18
--.*: 0460ce60 uqdech z0\.h, #19
--.*: 0460ce60 uqdech z0\.h, #19
--.*: 0460ce60 uqdech z0\.h, #19
--.*: 0460ce80 uqdech z0\.h, #20
--.*: 0460ce80 uqdech z0\.h, #20
--.*: 0460ce80 uqdech z0\.h, #20
--.*: 0460cea0 uqdech z0\.h, #21
--.*: 0460cea0 uqdech z0\.h, #21
--.*: 0460cea0 uqdech z0\.h, #21
--.*: 0460cec0 uqdech z0\.h, #22
--.*: 0460cec0 uqdech z0\.h, #22
--.*: 0460cec0 uqdech z0\.h, #22
--.*: 0460cee0 uqdech z0\.h, #23
--.*: 0460cee0 uqdech z0\.h, #23
--.*: 0460cee0 uqdech z0\.h, #23
--.*: 0460cf00 uqdech z0\.h, #24
--.*: 0460cf00 uqdech z0\.h, #24
--.*: 0460cf00 uqdech z0\.h, #24
--.*: 0460cf20 uqdech z0\.h, #25
--.*: 0460cf20 uqdech z0\.h, #25
--.*: 0460cf20 uqdech z0\.h, #25
--.*: 0460cf40 uqdech z0\.h, #26
--.*: 0460cf40 uqdech z0\.h, #26
--.*: 0460cf40 uqdech z0\.h, #26
--.*: 0460cf60 uqdech z0\.h, #27
--.*: 0460cf60 uqdech z0\.h, #27
--.*: 0460cf60 uqdech z0\.h, #27
--.*: 0460cf80 uqdech z0\.h, #28
--.*: 0460cf80 uqdech z0\.h, #28
--.*: 0460cf80 uqdech z0\.h, #28
--.*: 0460cfa0 uqdech z0\.h, mul4
--.*: 0460cfa0 uqdech z0\.h, mul4
--.*: 0460cfa0 uqdech z0\.h, mul4
--.*: 0460cfc0 uqdech z0\.h, mul3
--.*: 0460cfc0 uqdech z0\.h, mul3
--.*: 0460cfc0 uqdech z0\.h, mul3
--.*: 0460cfe0 uqdech z0\.h
--.*: 0460cfe0 uqdech z0\.h
--.*: 0460cfe0 uqdech z0\.h
--.*: 0460cfe0 uqdech z0\.h
--.*: 0467cc00 uqdech z0\.h, pow2, mul #8
--.*: 0467cc00 uqdech z0\.h, pow2, mul #8
--.*: 0468cc00 uqdech z0\.h, pow2, mul #9
--.*: 0468cc00 uqdech z0\.h, pow2, mul #9
--.*: 0469cc00 uqdech z0\.h, pow2, mul #10
--.*: 0469cc00 uqdech z0\.h, pow2, mul #10
--.*: 046fcc00 uqdech z0\.h, pow2, mul #16
--.*: 046fcc00 uqdech z0\.h, pow2, mul #16
--.*: 0460fc00 uqdech w0, pow2
--.*: 0460fc00 uqdech w0, pow2
--.*: 0460fc00 uqdech w0, pow2
--.*: 0460fc01 uqdech w1, pow2
--.*: 0460fc01 uqdech w1, pow2
--.*: 0460fc01 uqdech w1, pow2
--.*: 0460fc1f uqdech wzr, pow2
--.*: 0460fc1f uqdech wzr, pow2
--.*: 0460fc1f uqdech wzr, pow2
--.*: 0460fc20 uqdech w0, vl1
--.*: 0460fc20 uqdech w0, vl1
--.*: 0460fc20 uqdech w0, vl1
--.*: 0460fc40 uqdech w0, vl2
--.*: 0460fc40 uqdech w0, vl2
--.*: 0460fc40 uqdech w0, vl2
--.*: 0460fc60 uqdech w0, vl3
--.*: 0460fc60 uqdech w0, vl3
--.*: 0460fc60 uqdech w0, vl3
--.*: 0460fc80 uqdech w0, vl4
--.*: 0460fc80 uqdech w0, vl4
--.*: 0460fc80 uqdech w0, vl4
--.*: 0460fca0 uqdech w0, vl5
--.*: 0460fca0 uqdech w0, vl5
--.*: 0460fca0 uqdech w0, vl5
--.*: 0460fcc0 uqdech w0, vl6
--.*: 0460fcc0 uqdech w0, vl6
--.*: 0460fcc0 uqdech w0, vl6
--.*: 0460fce0 uqdech w0, vl7
--.*: 0460fce0 uqdech w0, vl7
--.*: 0460fce0 uqdech w0, vl7
--.*: 0460fd00 uqdech w0, vl8
--.*: 0460fd00 uqdech w0, vl8
--.*: 0460fd00 uqdech w0, vl8
--.*: 0460fd20 uqdech w0, vl16
--.*: 0460fd20 uqdech w0, vl16
--.*: 0460fd20 uqdech w0, vl16
--.*: 0460fd40 uqdech w0, vl32
--.*: 0460fd40 uqdech w0, vl32
--.*: 0460fd40 uqdech w0, vl32
--.*: 0460fd60 uqdech w0, vl64
--.*: 0460fd60 uqdech w0, vl64
--.*: 0460fd60 uqdech w0, vl64
--.*: 0460fd80 uqdech w0, vl128
--.*: 0460fd80 uqdech w0, vl128
--.*: 0460fd80 uqdech w0, vl128
--.*: 0460fda0 uqdech w0, vl256
--.*: 0460fda0 uqdech w0, vl256
--.*: 0460fda0 uqdech w0, vl256
--.*: 0460fdc0 uqdech w0, #14
--.*: 0460fdc0 uqdech w0, #14
--.*: 0460fdc0 uqdech w0, #14
--.*: 0460fde0 uqdech w0, #15
--.*: 0460fde0 uqdech w0, #15
--.*: 0460fde0 uqdech w0, #15
--.*: 0460fe00 uqdech w0, #16
--.*: 0460fe00 uqdech w0, #16
--.*: 0460fe00 uqdech w0, #16
--.*: 0460fe20 uqdech w0, #17
--.*: 0460fe20 uqdech w0, #17
--.*: 0460fe20 uqdech w0, #17
--.*: 0460fe40 uqdech w0, #18
--.*: 0460fe40 uqdech w0, #18
--.*: 0460fe40 uqdech w0, #18
--.*: 0460fe60 uqdech w0, #19
--.*: 0460fe60 uqdech w0, #19
--.*: 0460fe60 uqdech w0, #19
--.*: 0460fe80 uqdech w0, #20
--.*: 0460fe80 uqdech w0, #20
--.*: 0460fe80 uqdech w0, #20
--.*: 0460fea0 uqdech w0, #21
--.*: 0460fea0 uqdech w0, #21
--.*: 0460fea0 uqdech w0, #21
--.*: 0460fec0 uqdech w0, #22
--.*: 0460fec0 uqdech w0, #22
--.*: 0460fec0 uqdech w0, #22
--.*: 0460fee0 uqdech w0, #23
--.*: 0460fee0 uqdech w0, #23
--.*: 0460fee0 uqdech w0, #23
--.*: 0460ff00 uqdech w0, #24
--.*: 0460ff00 uqdech w0, #24
--.*: 0460ff00 uqdech w0, #24
--.*: 0460ff20 uqdech w0, #25
--.*: 0460ff20 uqdech w0, #25
--.*: 0460ff20 uqdech w0, #25
--.*: 0460ff40 uqdech w0, #26
--.*: 0460ff40 uqdech w0, #26
--.*: 0460ff40 uqdech w0, #26
--.*: 0460ff60 uqdech w0, #27
--.*: 0460ff60 uqdech w0, #27
--.*: 0460ff60 uqdech w0, #27
--.*: 0460ff80 uqdech w0, #28
--.*: 0460ff80 uqdech w0, #28
--.*: 0460ff80 uqdech w0, #28
--.*: 0460ffa0 uqdech w0, mul4
--.*: 0460ffa0 uqdech w0, mul4
--.*: 0460ffa0 uqdech w0, mul4
--.*: 0460ffc0 uqdech w0, mul3
--.*: 0460ffc0 uqdech w0, mul3
--.*: 0460ffc0 uqdech w0, mul3
--.*: 0460ffe0 uqdech w0
--.*: 0460ffe0 uqdech w0
--.*: 0460ffe0 uqdech w0
--.*: 0460ffe0 uqdech w0
--.*: 0467fc00 uqdech w0, pow2, mul #8
--.*: 0467fc00 uqdech w0, pow2, mul #8
--.*: 0468fc00 uqdech w0, pow2, mul #9
--.*: 0468fc00 uqdech w0, pow2, mul #9
--.*: 0469fc00 uqdech w0, pow2, mul #10
--.*: 0469fc00 uqdech w0, pow2, mul #10
--.*: 046ffc00 uqdech w0, pow2, mul #16
--.*: 046ffc00 uqdech w0, pow2, mul #16
--.*: 0470fc00 uqdech x0, pow2
--.*: 0470fc00 uqdech x0, pow2
--.*: 0470fc00 uqdech x0, pow2
--.*: 0470fc01 uqdech x1, pow2
--.*: 0470fc01 uqdech x1, pow2
--.*: 0470fc01 uqdech x1, pow2
--.*: 0470fc1f uqdech xzr, pow2
--.*: 0470fc1f uqdech xzr, pow2
--.*: 0470fc1f uqdech xzr, pow2
--.*: 0470fc20 uqdech x0, vl1
--.*: 0470fc20 uqdech x0, vl1
--.*: 0470fc20 uqdech x0, vl1
--.*: 0470fc40 uqdech x0, vl2
--.*: 0470fc40 uqdech x0, vl2
--.*: 0470fc40 uqdech x0, vl2
--.*: 0470fc60 uqdech x0, vl3
--.*: 0470fc60 uqdech x0, vl3
--.*: 0470fc60 uqdech x0, vl3
--.*: 0470fc80 uqdech x0, vl4
--.*: 0470fc80 uqdech x0, vl4
--.*: 0470fc80 uqdech x0, vl4
--.*: 0470fca0 uqdech x0, vl5
--.*: 0470fca0 uqdech x0, vl5
--.*: 0470fca0 uqdech x0, vl5
--.*: 0470fcc0 uqdech x0, vl6
--.*: 0470fcc0 uqdech x0, vl6
--.*: 0470fcc0 uqdech x0, vl6
--.*: 0470fce0 uqdech x0, vl7
--.*: 0470fce0 uqdech x0, vl7
--.*: 0470fce0 uqdech x0, vl7
--.*: 0470fd00 uqdech x0, vl8
--.*: 0470fd00 uqdech x0, vl8
--.*: 0470fd00 uqdech x0, vl8
--.*: 0470fd20 uqdech x0, vl16
--.*: 0470fd20 uqdech x0, vl16
--.*: 0470fd20 uqdech x0, vl16
--.*: 0470fd40 uqdech x0, vl32
--.*: 0470fd40 uqdech x0, vl32
--.*: 0470fd40 uqdech x0, vl32
--.*: 0470fd60 uqdech x0, vl64
--.*: 0470fd60 uqdech x0, vl64
--.*: 0470fd60 uqdech x0, vl64
--.*: 0470fd80 uqdech x0, vl128
--.*: 0470fd80 uqdech x0, vl128
--.*: 0470fd80 uqdech x0, vl128
--.*: 0470fda0 uqdech x0, vl256
--.*: 0470fda0 uqdech x0, vl256
--.*: 0470fda0 uqdech x0, vl256
--.*: 0470fdc0 uqdech x0, #14
--.*: 0470fdc0 uqdech x0, #14
--.*: 0470fdc0 uqdech x0, #14
--.*: 0470fde0 uqdech x0, #15
--.*: 0470fde0 uqdech x0, #15
--.*: 0470fde0 uqdech x0, #15
--.*: 0470fe00 uqdech x0, #16
--.*: 0470fe00 uqdech x0, #16
--.*: 0470fe00 uqdech x0, #16
--.*: 0470fe20 uqdech x0, #17
--.*: 0470fe20 uqdech x0, #17
--.*: 0470fe20 uqdech x0, #17
--.*: 0470fe40 uqdech x0, #18
--.*: 0470fe40 uqdech x0, #18
--.*: 0470fe40 uqdech x0, #18
--.*: 0470fe60 uqdech x0, #19
--.*: 0470fe60 uqdech x0, #19
--.*: 0470fe60 uqdech x0, #19
--.*: 0470fe80 uqdech x0, #20
--.*: 0470fe80 uqdech x0, #20
--.*: 0470fe80 uqdech x0, #20
--.*: 0470fea0 uqdech x0, #21
--.*: 0470fea0 uqdech x0, #21
--.*: 0470fea0 uqdech x0, #21
--.*: 0470fec0 uqdech x0, #22
--.*: 0470fec0 uqdech x0, #22
--.*: 0470fec0 uqdech x0, #22
--.*: 0470fee0 uqdech x0, #23
--.*: 0470fee0 uqdech x0, #23
--.*: 0470fee0 uqdech x0, #23
--.*: 0470ff00 uqdech x0, #24
--.*: 0470ff00 uqdech x0, #24
--.*: 0470ff00 uqdech x0, #24
--.*: 0470ff20 uqdech x0, #25
--.*: 0470ff20 uqdech x0, #25
--.*: 0470ff20 uqdech x0, #25
--.*: 0470ff40 uqdech x0, #26
--.*: 0470ff40 uqdech x0, #26
--.*: 0470ff40 uqdech x0, #26
--.*: 0470ff60 uqdech x0, #27
--.*: 0470ff60 uqdech x0, #27
--.*: 0470ff60 uqdech x0, #27
--.*: 0470ff80 uqdech x0, #28
--.*: 0470ff80 uqdech x0, #28
--.*: 0470ff80 uqdech x0, #28
--.*: 0470ffa0 uqdech x0, mul4
--.*: 0470ffa0 uqdech x0, mul4
--.*: 0470ffa0 uqdech x0, mul4
--.*: 0470ffc0 uqdech x0, mul3
--.*: 0470ffc0 uqdech x0, mul3
--.*: 0470ffc0 uqdech x0, mul3
--.*: 0470ffe0 uqdech x0
--.*: 0470ffe0 uqdech x0
--.*: 0470ffe0 uqdech x0
--.*: 0470ffe0 uqdech x0
--.*: 0477fc00 uqdech x0, pow2, mul #8
--.*: 0477fc00 uqdech x0, pow2, mul #8
--.*: 0478fc00 uqdech x0, pow2, mul #9
--.*: 0478fc00 uqdech x0, pow2, mul #9
--.*: 0479fc00 uqdech x0, pow2, mul #10
--.*: 0479fc00 uqdech x0, pow2, mul #10
--.*: 047ffc00 uqdech x0, pow2, mul #16
--.*: 047ffc00 uqdech x0, pow2, mul #16
--.*: 256b8000 uqdecp z0\.h, p0
--.*: 256b8000 uqdecp z0\.h, p0
--.*: 256b8001 uqdecp z1\.h, p0
--.*: 256b8001 uqdecp z1\.h, p0
--.*: 256b801f uqdecp z31\.h, p0
--.*: 256b801f uqdecp z31\.h, p0
--.*: 256b8040 uqdecp z0\.h, p2
--.*: 256b8040 uqdecp z0\.h, p2
--.*: 256b81e0 uqdecp z0\.h, p15
--.*: 256b81e0 uqdecp z0\.h, p15
--.*: 25ab8000 uqdecp z0\.s, p0
--.*: 25ab8000 uqdecp z0\.s, p0
--.*: 25ab8001 uqdecp z1\.s, p0
--.*: 25ab8001 uqdecp z1\.s, p0
--.*: 25ab801f uqdecp z31\.s, p0
--.*: 25ab801f uqdecp z31\.s, p0
--.*: 25ab8040 uqdecp z0\.s, p2
--.*: 25ab8040 uqdecp z0\.s, p2
--.*: 25ab81e0 uqdecp z0\.s, p15
--.*: 25ab81e0 uqdecp z0\.s, p15
--.*: 25eb8000 uqdecp z0\.d, p0
--.*: 25eb8000 uqdecp z0\.d, p0
--.*: 25eb8001 uqdecp z1\.d, p0
--.*: 25eb8001 uqdecp z1\.d, p0
--.*: 25eb801f uqdecp z31\.d, p0
--.*: 25eb801f uqdecp z31\.d, p0
--.*: 25eb8040 uqdecp z0\.d, p2
--.*: 25eb8040 uqdecp z0\.d, p2
--.*: 25eb81e0 uqdecp z0\.d, p15
--.*: 25eb81e0 uqdecp z0\.d, p15
--.*: 252b8800 uqdecp w0, p0\.b
--.*: 252b8800 uqdecp w0, p0\.b
--.*: 252b8801 uqdecp w1, p0\.b
--.*: 252b8801 uqdecp w1, p0\.b
--.*: 252b881f uqdecp wzr, p0\.b
--.*: 252b881f uqdecp wzr, p0\.b
--.*: 252b8840 uqdecp w0, p2\.b
--.*: 252b8840 uqdecp w0, p2\.b
--.*: 252b89e0 uqdecp w0, p15\.b
--.*: 252b89e0 uqdecp w0, p15\.b
--.*: 256b8800 uqdecp w0, p0\.h
--.*: 256b8800 uqdecp w0, p0\.h
--.*: 256b8801 uqdecp w1, p0\.h
--.*: 256b8801 uqdecp w1, p0\.h
--.*: 256b881f uqdecp wzr, p0\.h
--.*: 256b881f uqdecp wzr, p0\.h
--.*: 256b8840 uqdecp w0, p2\.h
--.*: 256b8840 uqdecp w0, p2\.h
--.*: 256b89e0 uqdecp w0, p15\.h
--.*: 256b89e0 uqdecp w0, p15\.h
--.*: 25ab8800 uqdecp w0, p0\.s
--.*: 25ab8800 uqdecp w0, p0\.s
--.*: 25ab8801 uqdecp w1, p0\.s
--.*: 25ab8801 uqdecp w1, p0\.s
--.*: 25ab881f uqdecp wzr, p0\.s
--.*: 25ab881f uqdecp wzr, p0\.s
--.*: 25ab8840 uqdecp w0, p2\.s
--.*: 25ab8840 uqdecp w0, p2\.s
--.*: 25ab89e0 uqdecp w0, p15\.s
--.*: 25ab89e0 uqdecp w0, p15\.s
--.*: 25eb8800 uqdecp w0, p0\.d
--.*: 25eb8800 uqdecp w0, p0\.d
--.*: 25eb8801 uqdecp w1, p0\.d
--.*: 25eb8801 uqdecp w1, p0\.d
--.*: 25eb881f uqdecp wzr, p0\.d
--.*: 25eb881f uqdecp wzr, p0\.d
--.*: 25eb8840 uqdecp w0, p2\.d
--.*: 25eb8840 uqdecp w0, p2\.d
--.*: 25eb89e0 uqdecp w0, p15\.d
--.*: 25eb89e0 uqdecp w0, p15\.d
--.*: 252b8c00 uqdecp x0, p0\.b
--.*: 252b8c00 uqdecp x0, p0\.b
--.*: 252b8c01 uqdecp x1, p0\.b
--.*: 252b8c01 uqdecp x1, p0\.b
--.*: 252b8c1f uqdecp xzr, p0\.b
--.*: 252b8c1f uqdecp xzr, p0\.b
--.*: 252b8c40 uqdecp x0, p2\.b
--.*: 252b8c40 uqdecp x0, p2\.b
--.*: 252b8de0 uqdecp x0, p15\.b
--.*: 252b8de0 uqdecp x0, p15\.b
--.*: 256b8c00 uqdecp x0, p0\.h
--.*: 256b8c00 uqdecp x0, p0\.h
--.*: 256b8c01 uqdecp x1, p0\.h
--.*: 256b8c01 uqdecp x1, p0\.h
--.*: 256b8c1f uqdecp xzr, p0\.h
--.*: 256b8c1f uqdecp xzr, p0\.h
--.*: 256b8c40 uqdecp x0, p2\.h
--.*: 256b8c40 uqdecp x0, p2\.h
--.*: 256b8de0 uqdecp x0, p15\.h
--.*: 256b8de0 uqdecp x0, p15\.h
--.*: 25ab8c00 uqdecp x0, p0\.s
--.*: 25ab8c00 uqdecp x0, p0\.s
--.*: 25ab8c01 uqdecp x1, p0\.s
--.*: 25ab8c01 uqdecp x1, p0\.s
--.*: 25ab8c1f uqdecp xzr, p0\.s
--.*: 25ab8c1f uqdecp xzr, p0\.s
--.*: 25ab8c40 uqdecp x0, p2\.s
--.*: 25ab8c40 uqdecp x0, p2\.s
--.*: 25ab8de0 uqdecp x0, p15\.s
--.*: 25ab8de0 uqdecp x0, p15\.s
--.*: 25eb8c00 uqdecp x0, p0\.d
--.*: 25eb8c00 uqdecp x0, p0\.d
--.*: 25eb8c01 uqdecp x1, p0\.d
--.*: 25eb8c01 uqdecp x1, p0\.d
--.*: 25eb8c1f uqdecp xzr, p0\.d
--.*: 25eb8c1f uqdecp xzr, p0\.d
--.*: 25eb8c40 uqdecp x0, p2\.d
--.*: 25eb8c40 uqdecp x0, p2\.d
--.*: 25eb8de0 uqdecp x0, p15\.d
--.*: 25eb8de0 uqdecp x0, p15\.d
--.*: 04a0cc00 uqdecw z0\.s, pow2
--.*: 04a0cc00 uqdecw z0\.s, pow2
--.*: 04a0cc00 uqdecw z0\.s, pow2
--.*: 04a0cc01 uqdecw z1\.s, pow2
--.*: 04a0cc01 uqdecw z1\.s, pow2
--.*: 04a0cc01 uqdecw z1\.s, pow2
--.*: 04a0cc1f uqdecw z31\.s, pow2
--.*: 04a0cc1f uqdecw z31\.s, pow2
--.*: 04a0cc1f uqdecw z31\.s, pow2
--.*: 04a0cc20 uqdecw z0\.s, vl1
--.*: 04a0cc20 uqdecw z0\.s, vl1
--.*: 04a0cc20 uqdecw z0\.s, vl1
--.*: 04a0cc40 uqdecw z0\.s, vl2
--.*: 04a0cc40 uqdecw z0\.s, vl2
--.*: 04a0cc40 uqdecw z0\.s, vl2
--.*: 04a0cc60 uqdecw z0\.s, vl3
--.*: 04a0cc60 uqdecw z0\.s, vl3
--.*: 04a0cc60 uqdecw z0\.s, vl3
--.*: 04a0cc80 uqdecw z0\.s, vl4
--.*: 04a0cc80 uqdecw z0\.s, vl4
--.*: 04a0cc80 uqdecw z0\.s, vl4
--.*: 04a0cca0 uqdecw z0\.s, vl5
--.*: 04a0cca0 uqdecw z0\.s, vl5
--.*: 04a0cca0 uqdecw z0\.s, vl5
--.*: 04a0ccc0 uqdecw z0\.s, vl6
--.*: 04a0ccc0 uqdecw z0\.s, vl6
--.*: 04a0ccc0 uqdecw z0\.s, vl6
--.*: 04a0cce0 uqdecw z0\.s, vl7
--.*: 04a0cce0 uqdecw z0\.s, vl7
--.*: 04a0cce0 uqdecw z0\.s, vl7
--.*: 04a0cd00 uqdecw z0\.s, vl8
--.*: 04a0cd00 uqdecw z0\.s, vl8
--.*: 04a0cd00 uqdecw z0\.s, vl8
--.*: 04a0cd20 uqdecw z0\.s, vl16
--.*: 04a0cd20 uqdecw z0\.s, vl16
--.*: 04a0cd20 uqdecw z0\.s, vl16
--.*: 04a0cd40 uqdecw z0\.s, vl32
--.*: 04a0cd40 uqdecw z0\.s, vl32
--.*: 04a0cd40 uqdecw z0\.s, vl32
--.*: 04a0cd60 uqdecw z0\.s, vl64
--.*: 04a0cd60 uqdecw z0\.s, vl64
--.*: 04a0cd60 uqdecw z0\.s, vl64
--.*: 04a0cd80 uqdecw z0\.s, vl128
--.*: 04a0cd80 uqdecw z0\.s, vl128
--.*: 04a0cd80 uqdecw z0\.s, vl128
--.*: 04a0cda0 uqdecw z0\.s, vl256
--.*: 04a0cda0 uqdecw z0\.s, vl256
--.*: 04a0cda0 uqdecw z0\.s, vl256
--.*: 04a0cdc0 uqdecw z0\.s, #14
--.*: 04a0cdc0 uqdecw z0\.s, #14
--.*: 04a0cdc0 uqdecw z0\.s, #14
--.*: 04a0cde0 uqdecw z0\.s, #15
--.*: 04a0cde0 uqdecw z0\.s, #15
--.*: 04a0cde0 uqdecw z0\.s, #15
--.*: 04a0ce00 uqdecw z0\.s, #16
--.*: 04a0ce00 uqdecw z0\.s, #16
--.*: 04a0ce00 uqdecw z0\.s, #16
--.*: 04a0ce20 uqdecw z0\.s, #17
--.*: 04a0ce20 uqdecw z0\.s, #17
--.*: 04a0ce20 uqdecw z0\.s, #17
--.*: 04a0ce40 uqdecw z0\.s, #18
--.*: 04a0ce40 uqdecw z0\.s, #18
--.*: 04a0ce40 uqdecw z0\.s, #18
--.*: 04a0ce60 uqdecw z0\.s, #19
--.*: 04a0ce60 uqdecw z0\.s, #19
--.*: 04a0ce60 uqdecw z0\.s, #19
--.*: 04a0ce80 uqdecw z0\.s, #20
--.*: 04a0ce80 uqdecw z0\.s, #20
--.*: 04a0ce80 uqdecw z0\.s, #20
--.*: 04a0cea0 uqdecw z0\.s, #21
--.*: 04a0cea0 uqdecw z0\.s, #21
--.*: 04a0cea0 uqdecw z0\.s, #21
--.*: 04a0cec0 uqdecw z0\.s, #22
--.*: 04a0cec0 uqdecw z0\.s, #22
--.*: 04a0cec0 uqdecw z0\.s, #22
--.*: 04a0cee0 uqdecw z0\.s, #23
--.*: 04a0cee0 uqdecw z0\.s, #23
--.*: 04a0cee0 uqdecw z0\.s, #23
--.*: 04a0cf00 uqdecw z0\.s, #24
--.*: 04a0cf00 uqdecw z0\.s, #24
--.*: 04a0cf00 uqdecw z0\.s, #24
--.*: 04a0cf20 uqdecw z0\.s, #25
--.*: 04a0cf20 uqdecw z0\.s, #25
--.*: 04a0cf20 uqdecw z0\.s, #25
--.*: 04a0cf40 uqdecw z0\.s, #26
--.*: 04a0cf40 uqdecw z0\.s, #26
--.*: 04a0cf40 uqdecw z0\.s, #26
--.*: 04a0cf60 uqdecw z0\.s, #27
--.*: 04a0cf60 uqdecw z0\.s, #27
--.*: 04a0cf60 uqdecw z0\.s, #27
--.*: 04a0cf80 uqdecw z0\.s, #28
--.*: 04a0cf80 uqdecw z0\.s, #28
--.*: 04a0cf80 uqdecw z0\.s, #28
--.*: 04a0cfa0 uqdecw z0\.s, mul4
--.*: 04a0cfa0 uqdecw z0\.s, mul4
--.*: 04a0cfa0 uqdecw z0\.s, mul4
--.*: 04a0cfc0 uqdecw z0\.s, mul3
--.*: 04a0cfc0 uqdecw z0\.s, mul3
--.*: 04a0cfc0 uqdecw z0\.s, mul3
--.*: 04a0cfe0 uqdecw z0\.s
--.*: 04a0cfe0 uqdecw z0\.s
--.*: 04a0cfe0 uqdecw z0\.s
--.*: 04a0cfe0 uqdecw z0\.s
--.*: 04a7cc00 uqdecw z0\.s, pow2, mul #8
--.*: 04a7cc00 uqdecw z0\.s, pow2, mul #8
--.*: 04a8cc00 uqdecw z0\.s, pow2, mul #9
--.*: 04a8cc00 uqdecw z0\.s, pow2, mul #9
--.*: 04a9cc00 uqdecw z0\.s, pow2, mul #10
--.*: 04a9cc00 uqdecw z0\.s, pow2, mul #10
--.*: 04afcc00 uqdecw z0\.s, pow2, mul #16
--.*: 04afcc00 uqdecw z0\.s, pow2, mul #16
--.*: 04a0fc00 uqdecw w0, pow2
--.*: 04a0fc00 uqdecw w0, pow2
--.*: 04a0fc00 uqdecw w0, pow2
--.*: 04a0fc01 uqdecw w1, pow2
--.*: 04a0fc01 uqdecw w1, pow2
--.*: 04a0fc01 uqdecw w1, pow2
--.*: 04a0fc1f uqdecw wzr, pow2
--.*: 04a0fc1f uqdecw wzr, pow2
--.*: 04a0fc1f uqdecw wzr, pow2
--.*: 04a0fc20 uqdecw w0, vl1
--.*: 04a0fc20 uqdecw w0, vl1
--.*: 04a0fc20 uqdecw w0, vl1
--.*: 04a0fc40 uqdecw w0, vl2
--.*: 04a0fc40 uqdecw w0, vl2
--.*: 04a0fc40 uqdecw w0, vl2
--.*: 04a0fc60 uqdecw w0, vl3
--.*: 04a0fc60 uqdecw w0, vl3
--.*: 04a0fc60 uqdecw w0, vl3
--.*: 04a0fc80 uqdecw w0, vl4
--.*: 04a0fc80 uqdecw w0, vl4
--.*: 04a0fc80 uqdecw w0, vl4
--.*: 04a0fca0 uqdecw w0, vl5
--.*: 04a0fca0 uqdecw w0, vl5
--.*: 04a0fca0 uqdecw w0, vl5
--.*: 04a0fcc0 uqdecw w0, vl6
--.*: 04a0fcc0 uqdecw w0, vl6
--.*: 04a0fcc0 uqdecw w0, vl6
--.*: 04a0fce0 uqdecw w0, vl7
--.*: 04a0fce0 uqdecw w0, vl7
--.*: 04a0fce0 uqdecw w0, vl7
--.*: 04a0fd00 uqdecw w0, vl8
--.*: 04a0fd00 uqdecw w0, vl8
--.*: 04a0fd00 uqdecw w0, vl8
--.*: 04a0fd20 uqdecw w0, vl16
--.*: 04a0fd20 uqdecw w0, vl16
--.*: 04a0fd20 uqdecw w0, vl16
--.*: 04a0fd40 uqdecw w0, vl32
--.*: 04a0fd40 uqdecw w0, vl32
--.*: 04a0fd40 uqdecw w0, vl32
--.*: 04a0fd60 uqdecw w0, vl64
--.*: 04a0fd60 uqdecw w0, vl64
--.*: 04a0fd60 uqdecw w0, vl64
--.*: 04a0fd80 uqdecw w0, vl128
--.*: 04a0fd80 uqdecw w0, vl128
--.*: 04a0fd80 uqdecw w0, vl128
--.*: 04a0fda0 uqdecw w0, vl256
--.*: 04a0fda0 uqdecw w0, vl256
--.*: 04a0fda0 uqdecw w0, vl256
--.*: 04a0fdc0 uqdecw w0, #14
--.*: 04a0fdc0 uqdecw w0, #14
--.*: 04a0fdc0 uqdecw w0, #14
--.*: 04a0fde0 uqdecw w0, #15
--.*: 04a0fde0 uqdecw w0, #15
--.*: 04a0fde0 uqdecw w0, #15
--.*: 04a0fe00 uqdecw w0, #16
--.*: 04a0fe00 uqdecw w0, #16
--.*: 04a0fe00 uqdecw w0, #16
--.*: 04a0fe20 uqdecw w0, #17
--.*: 04a0fe20 uqdecw w0, #17
--.*: 04a0fe20 uqdecw w0, #17
--.*: 04a0fe40 uqdecw w0, #18
--.*: 04a0fe40 uqdecw w0, #18
--.*: 04a0fe40 uqdecw w0, #18
--.*: 04a0fe60 uqdecw w0, #19
--.*: 04a0fe60 uqdecw w0, #19
--.*: 04a0fe60 uqdecw w0, #19
--.*: 04a0fe80 uqdecw w0, #20
--.*: 04a0fe80 uqdecw w0, #20
--.*: 04a0fe80 uqdecw w0, #20
--.*: 04a0fea0 uqdecw w0, #21
--.*: 04a0fea0 uqdecw w0, #21
--.*: 04a0fea0 uqdecw w0, #21
--.*: 04a0fec0 uqdecw w0, #22
--.*: 04a0fec0 uqdecw w0, #22
--.*: 04a0fec0 uqdecw w0, #22
--.*: 04a0fee0 uqdecw w0, #23
--.*: 04a0fee0 uqdecw w0, #23
--.*: 04a0fee0 uqdecw w0, #23
--.*: 04a0ff00 uqdecw w0, #24
--.*: 04a0ff00 uqdecw w0, #24
--.*: 04a0ff00 uqdecw w0, #24
--.*: 04a0ff20 uqdecw w0, #25
--.*: 04a0ff20 uqdecw w0, #25
--.*: 04a0ff20 uqdecw w0, #25
--.*: 04a0ff40 uqdecw w0, #26
--.*: 04a0ff40 uqdecw w0, #26
--.*: 04a0ff40 uqdecw w0, #26
--.*: 04a0ff60 uqdecw w0, #27
--.*: 04a0ff60 uqdecw w0, #27
--.*: 04a0ff60 uqdecw w0, #27
--.*: 04a0ff80 uqdecw w0, #28
--.*: 04a0ff80 uqdecw w0, #28
--.*: 04a0ff80 uqdecw w0, #28
--.*: 04a0ffa0 uqdecw w0, mul4
--.*: 04a0ffa0 uqdecw w0, mul4
--.*: 04a0ffa0 uqdecw w0, mul4
--.*: 04a0ffc0 uqdecw w0, mul3
--.*: 04a0ffc0 uqdecw w0, mul3
--.*: 04a0ffc0 uqdecw w0, mul3
--.*: 04a0ffe0 uqdecw w0
--.*: 04a0ffe0 uqdecw w0
--.*: 04a0ffe0 uqdecw w0
--.*: 04a0ffe0 uqdecw w0
--.*: 04a7fc00 uqdecw w0, pow2, mul #8
--.*: 04a7fc00 uqdecw w0, pow2, mul #8
--.*: 04a8fc00 uqdecw w0, pow2, mul #9
--.*: 04a8fc00 uqdecw w0, pow2, mul #9
--.*: 04a9fc00 uqdecw w0, pow2, mul #10
--.*: 04a9fc00 uqdecw w0, pow2, mul #10
--.*: 04affc00 uqdecw w0, pow2, mul #16
--.*: 04affc00 uqdecw w0, pow2, mul #16
--.*: 04b0fc00 uqdecw x0, pow2
--.*: 04b0fc00 uqdecw x0, pow2
--.*: 04b0fc00 uqdecw x0, pow2
--.*: 04b0fc01 uqdecw x1, pow2
--.*: 04b0fc01 uqdecw x1, pow2
--.*: 04b0fc01 uqdecw x1, pow2
--.*: 04b0fc1f uqdecw xzr, pow2
--.*: 04b0fc1f uqdecw xzr, pow2
--.*: 04b0fc1f uqdecw xzr, pow2
--.*: 04b0fc20 uqdecw x0, vl1
--.*: 04b0fc20 uqdecw x0, vl1
--.*: 04b0fc20 uqdecw x0, vl1
--.*: 04b0fc40 uqdecw x0, vl2
--.*: 04b0fc40 uqdecw x0, vl2
--.*: 04b0fc40 uqdecw x0, vl2
--.*: 04b0fc60 uqdecw x0, vl3
--.*: 04b0fc60 uqdecw x0, vl3
--.*: 04b0fc60 uqdecw x0, vl3
--.*: 04b0fc80 uqdecw x0, vl4
--.*: 04b0fc80 uqdecw x0, vl4
--.*: 04b0fc80 uqdecw x0, vl4
--.*: 04b0fca0 uqdecw x0, vl5
--.*: 04b0fca0 uqdecw x0, vl5
--.*: 04b0fca0 uqdecw x0, vl5
--.*: 04b0fcc0 uqdecw x0, vl6
--.*: 04b0fcc0 uqdecw x0, vl6
--.*: 04b0fcc0 uqdecw x0, vl6
--.*: 04b0fce0 uqdecw x0, vl7
--.*: 04b0fce0 uqdecw x0, vl7
--.*: 04b0fce0 uqdecw x0, vl7
--.*: 04b0fd00 uqdecw x0, vl8
--.*: 04b0fd00 uqdecw x0, vl8
--.*: 04b0fd00 uqdecw x0, vl8
--.*: 04b0fd20 uqdecw x0, vl16
--.*: 04b0fd20 uqdecw x0, vl16
--.*: 04b0fd20 uqdecw x0, vl16
--.*: 04b0fd40 uqdecw x0, vl32
--.*: 04b0fd40 uqdecw x0, vl32
--.*: 04b0fd40 uqdecw x0, vl32
--.*: 04b0fd60 uqdecw x0, vl64
--.*: 04b0fd60 uqdecw x0, vl64
--.*: 04b0fd60 uqdecw x0, vl64
--.*: 04b0fd80 uqdecw x0, vl128
--.*: 04b0fd80 uqdecw x0, vl128
--.*: 04b0fd80 uqdecw x0, vl128
--.*: 04b0fda0 uqdecw x0, vl256
--.*: 04b0fda0 uqdecw x0, vl256
--.*: 04b0fda0 uqdecw x0, vl256
--.*: 04b0fdc0 uqdecw x0, #14
--.*: 04b0fdc0 uqdecw x0, #14
--.*: 04b0fdc0 uqdecw x0, #14
--.*: 04b0fde0 uqdecw x0, #15
--.*: 04b0fde0 uqdecw x0, #15
--.*: 04b0fde0 uqdecw x0, #15
--.*: 04b0fe00 uqdecw x0, #16
--.*: 04b0fe00 uqdecw x0, #16
--.*: 04b0fe00 uqdecw x0, #16
--.*: 04b0fe20 uqdecw x0, #17
--.*: 04b0fe20 uqdecw x0, #17
--.*: 04b0fe20 uqdecw x0, #17
--.*: 04b0fe40 uqdecw x0, #18
--.*: 04b0fe40 uqdecw x0, #18
--.*: 04b0fe40 uqdecw x0, #18
--.*: 04b0fe60 uqdecw x0, #19
--.*: 04b0fe60 uqdecw x0, #19
--.*: 04b0fe60 uqdecw x0, #19
--.*: 04b0fe80 uqdecw x0, #20
--.*: 04b0fe80 uqdecw x0, #20
--.*: 04b0fe80 uqdecw x0, #20
--.*: 04b0fea0 uqdecw x0, #21
--.*: 04b0fea0 uqdecw x0, #21
--.*: 04b0fea0 uqdecw x0, #21
--.*: 04b0fec0 uqdecw x0, #22
--.*: 04b0fec0 uqdecw x0, #22
--.*: 04b0fec0 uqdecw x0, #22
--.*: 04b0fee0 uqdecw x0, #23
--.*: 04b0fee0 uqdecw x0, #23
--.*: 04b0fee0 uqdecw x0, #23
--.*: 04b0ff00 uqdecw x0, #24
--.*: 04b0ff00 uqdecw x0, #24
--.*: 04b0ff00 uqdecw x0, #24
--.*: 04b0ff20 uqdecw x0, #25
--.*: 04b0ff20 uqdecw x0, #25
--.*: 04b0ff20 uqdecw x0, #25
--.*: 04b0ff40 uqdecw x0, #26
--.*: 04b0ff40 uqdecw x0, #26
--.*: 04b0ff40 uqdecw x0, #26
--.*: 04b0ff60 uqdecw x0, #27
--.*: 04b0ff60 uqdecw x0, #27
--.*: 04b0ff60 uqdecw x0, #27
--.*: 04b0ff80 uqdecw x0, #28
--.*: 04b0ff80 uqdecw x0, #28
--.*: 04b0ff80 uqdecw x0, #28
--.*: 04b0ffa0 uqdecw x0, mul4
--.*: 04b0ffa0 uqdecw x0, mul4
--.*: 04b0ffa0 uqdecw x0, mul4
--.*: 04b0ffc0 uqdecw x0, mul3
--.*: 04b0ffc0 uqdecw x0, mul3
--.*: 04b0ffc0 uqdecw x0, mul3
--.*: 04b0ffe0 uqdecw x0
--.*: 04b0ffe0 uqdecw x0
--.*: 04b0ffe0 uqdecw x0
--.*: 04b0ffe0 uqdecw x0
--.*: 04b7fc00 uqdecw x0, pow2, mul #8
--.*: 04b7fc00 uqdecw x0, pow2, mul #8
--.*: 04b8fc00 uqdecw x0, pow2, mul #9
--.*: 04b8fc00 uqdecw x0, pow2, mul #9
--.*: 04b9fc00 uqdecw x0, pow2, mul #10
--.*: 04b9fc00 uqdecw x0, pow2, mul #10
--.*: 04bffc00 uqdecw x0, pow2, mul #16
--.*: 04bffc00 uqdecw x0, pow2, mul #16
--.*: 0420f400 uqincb w0, pow2
--.*: 0420f400 uqincb w0, pow2
--.*: 0420f400 uqincb w0, pow2
--.*: 0420f401 uqincb w1, pow2
--.*: 0420f401 uqincb w1, pow2
--.*: 0420f401 uqincb w1, pow2
--.*: 0420f41f uqincb wzr, pow2
--.*: 0420f41f uqincb wzr, pow2
--.*: 0420f41f uqincb wzr, pow2
--.*: 0420f420 uqincb w0, vl1
--.*: 0420f420 uqincb w0, vl1
--.*: 0420f420 uqincb w0, vl1
--.*: 0420f440 uqincb w0, vl2
--.*: 0420f440 uqincb w0, vl2
--.*: 0420f440 uqincb w0, vl2
--.*: 0420f460 uqincb w0, vl3
--.*: 0420f460 uqincb w0, vl3
--.*: 0420f460 uqincb w0, vl3
--.*: 0420f480 uqincb w0, vl4
--.*: 0420f480 uqincb w0, vl4
--.*: 0420f480 uqincb w0, vl4
--.*: 0420f4a0 uqincb w0, vl5
--.*: 0420f4a0 uqincb w0, vl5
--.*: 0420f4a0 uqincb w0, vl5
--.*: 0420f4c0 uqincb w0, vl6
--.*: 0420f4c0 uqincb w0, vl6
--.*: 0420f4c0 uqincb w0, vl6
--.*: 0420f4e0 uqincb w0, vl7
--.*: 0420f4e0 uqincb w0, vl7
--.*: 0420f4e0 uqincb w0, vl7
--.*: 0420f500 uqincb w0, vl8
--.*: 0420f500 uqincb w0, vl8
--.*: 0420f500 uqincb w0, vl8
--.*: 0420f520 uqincb w0, vl16
--.*: 0420f520 uqincb w0, vl16
--.*: 0420f520 uqincb w0, vl16
--.*: 0420f540 uqincb w0, vl32
--.*: 0420f540 uqincb w0, vl32
--.*: 0420f540 uqincb w0, vl32
--.*: 0420f560 uqincb w0, vl64
--.*: 0420f560 uqincb w0, vl64
--.*: 0420f560 uqincb w0, vl64
--.*: 0420f580 uqincb w0, vl128
--.*: 0420f580 uqincb w0, vl128
--.*: 0420f580 uqincb w0, vl128
--.*: 0420f5a0 uqincb w0, vl256
--.*: 0420f5a0 uqincb w0, vl256
--.*: 0420f5a0 uqincb w0, vl256
--.*: 0420f5c0 uqincb w0, #14
--.*: 0420f5c0 uqincb w0, #14
--.*: 0420f5c0 uqincb w0, #14
--.*: 0420f5e0 uqincb w0, #15
--.*: 0420f5e0 uqincb w0, #15
--.*: 0420f5e0 uqincb w0, #15
--.*: 0420f600 uqincb w0, #16
--.*: 0420f600 uqincb w0, #16
--.*: 0420f600 uqincb w0, #16
--.*: 0420f620 uqincb w0, #17
--.*: 0420f620 uqincb w0, #17
--.*: 0420f620 uqincb w0, #17
--.*: 0420f640 uqincb w0, #18
--.*: 0420f640 uqincb w0, #18
--.*: 0420f640 uqincb w0, #18
--.*: 0420f660 uqincb w0, #19
--.*: 0420f660 uqincb w0, #19
--.*: 0420f660 uqincb w0, #19
--.*: 0420f680 uqincb w0, #20
--.*: 0420f680 uqincb w0, #20
--.*: 0420f680 uqincb w0, #20
--.*: 0420f6a0 uqincb w0, #21
--.*: 0420f6a0 uqincb w0, #21
--.*: 0420f6a0 uqincb w0, #21
--.*: 0420f6c0 uqincb w0, #22
--.*: 0420f6c0 uqincb w0, #22
--.*: 0420f6c0 uqincb w0, #22
--.*: 0420f6e0 uqincb w0, #23
--.*: 0420f6e0 uqincb w0, #23
--.*: 0420f6e0 uqincb w0, #23
--.*: 0420f700 uqincb w0, #24
--.*: 0420f700 uqincb w0, #24
--.*: 0420f700 uqincb w0, #24
--.*: 0420f720 uqincb w0, #25
--.*: 0420f720 uqincb w0, #25
--.*: 0420f720 uqincb w0, #25
--.*: 0420f740 uqincb w0, #26
--.*: 0420f740 uqincb w0, #26
--.*: 0420f740 uqincb w0, #26
--.*: 0420f760 uqincb w0, #27
--.*: 0420f760 uqincb w0, #27
--.*: 0420f760 uqincb w0, #27
--.*: 0420f780 uqincb w0, #28
--.*: 0420f780 uqincb w0, #28
--.*: 0420f780 uqincb w0, #28
--.*: 0420f7a0 uqincb w0, mul4
--.*: 0420f7a0 uqincb w0, mul4
--.*: 0420f7a0 uqincb w0, mul4
--.*: 0420f7c0 uqincb w0, mul3
--.*: 0420f7c0 uqincb w0, mul3
--.*: 0420f7c0 uqincb w0, mul3
--.*: 0420f7e0 uqincb w0
--.*: 0420f7e0 uqincb w0
--.*: 0420f7e0 uqincb w0
--.*: 0420f7e0 uqincb w0
--.*: 0427f400 uqincb w0, pow2, mul #8
--.*: 0427f400 uqincb w0, pow2, mul #8
--.*: 0428f400 uqincb w0, pow2, mul #9
--.*: 0428f400 uqincb w0, pow2, mul #9
--.*: 0429f400 uqincb w0, pow2, mul #10
--.*: 0429f400 uqincb w0, pow2, mul #10
--.*: 042ff400 uqincb w0, pow2, mul #16
--.*: 042ff400 uqincb w0, pow2, mul #16
--.*: 0430f400 uqincb x0, pow2
--.*: 0430f400 uqincb x0, pow2
--.*: 0430f400 uqincb x0, pow2
--.*: 0430f401 uqincb x1, pow2
--.*: 0430f401 uqincb x1, pow2
--.*: 0430f401 uqincb x1, pow2
--.*: 0430f41f uqincb xzr, pow2
--.*: 0430f41f uqincb xzr, pow2
--.*: 0430f41f uqincb xzr, pow2
--.*: 0430f420 uqincb x0, vl1
--.*: 0430f420 uqincb x0, vl1
--.*: 0430f420 uqincb x0, vl1
--.*: 0430f440 uqincb x0, vl2
--.*: 0430f440 uqincb x0, vl2
--.*: 0430f440 uqincb x0, vl2
--.*: 0430f460 uqincb x0, vl3
--.*: 0430f460 uqincb x0, vl3
--.*: 0430f460 uqincb x0, vl3
--.*: 0430f480 uqincb x0, vl4
--.*: 0430f480 uqincb x0, vl4
--.*: 0430f480 uqincb x0, vl4
--.*: 0430f4a0 uqincb x0, vl5
--.*: 0430f4a0 uqincb x0, vl5
--.*: 0430f4a0 uqincb x0, vl5
--.*: 0430f4c0 uqincb x0, vl6
--.*: 0430f4c0 uqincb x0, vl6
--.*: 0430f4c0 uqincb x0, vl6
--.*: 0430f4e0 uqincb x0, vl7
--.*: 0430f4e0 uqincb x0, vl7
--.*: 0430f4e0 uqincb x0, vl7
--.*: 0430f500 uqincb x0, vl8
--.*: 0430f500 uqincb x0, vl8
--.*: 0430f500 uqincb x0, vl8
--.*: 0430f520 uqincb x0, vl16
--.*: 0430f520 uqincb x0, vl16
--.*: 0430f520 uqincb x0, vl16
--.*: 0430f540 uqincb x0, vl32
--.*: 0430f540 uqincb x0, vl32
--.*: 0430f540 uqincb x0, vl32
--.*: 0430f560 uqincb x0, vl64
--.*: 0430f560 uqincb x0, vl64
--.*: 0430f560 uqincb x0, vl64
--.*: 0430f580 uqincb x0, vl128
--.*: 0430f580 uqincb x0, vl128
--.*: 0430f580 uqincb x0, vl128
--.*: 0430f5a0 uqincb x0, vl256
--.*: 0430f5a0 uqincb x0, vl256
--.*: 0430f5a0 uqincb x0, vl256
--.*: 0430f5c0 uqincb x0, #14
--.*: 0430f5c0 uqincb x0, #14
--.*: 0430f5c0 uqincb x0, #14
--.*: 0430f5e0 uqincb x0, #15
--.*: 0430f5e0 uqincb x0, #15
--.*: 0430f5e0 uqincb x0, #15
--.*: 0430f600 uqincb x0, #16
--.*: 0430f600 uqincb x0, #16
--.*: 0430f600 uqincb x0, #16
--.*: 0430f620 uqincb x0, #17
--.*: 0430f620 uqincb x0, #17
--.*: 0430f620 uqincb x0, #17
--.*: 0430f640 uqincb x0, #18
--.*: 0430f640 uqincb x0, #18
--.*: 0430f640 uqincb x0, #18
--.*: 0430f660 uqincb x0, #19
--.*: 0430f660 uqincb x0, #19
--.*: 0430f660 uqincb x0, #19
--.*: 0430f680 uqincb x0, #20
--.*: 0430f680 uqincb x0, #20
--.*: 0430f680 uqincb x0, #20
--.*: 0430f6a0 uqincb x0, #21
--.*: 0430f6a0 uqincb x0, #21
--.*: 0430f6a0 uqincb x0, #21
--.*: 0430f6c0 uqincb x0, #22
--.*: 0430f6c0 uqincb x0, #22
--.*: 0430f6c0 uqincb x0, #22
--.*: 0430f6e0 uqincb x0, #23
--.*: 0430f6e0 uqincb x0, #23
--.*: 0430f6e0 uqincb x0, #23
--.*: 0430f700 uqincb x0, #24
--.*: 0430f700 uqincb x0, #24
--.*: 0430f700 uqincb x0, #24
--.*: 0430f720 uqincb x0, #25
--.*: 0430f720 uqincb x0, #25
--.*: 0430f720 uqincb x0, #25
--.*: 0430f740 uqincb x0, #26
--.*: 0430f740 uqincb x0, #26
--.*: 0430f740 uqincb x0, #26
--.*: 0430f760 uqincb x0, #27
--.*: 0430f760 uqincb x0, #27
--.*: 0430f760 uqincb x0, #27
--.*: 0430f780 uqincb x0, #28
--.*: 0430f780 uqincb x0, #28
--.*: 0430f780 uqincb x0, #28
--.*: 0430f7a0 uqincb x0, mul4
--.*: 0430f7a0 uqincb x0, mul4
--.*: 0430f7a0 uqincb x0, mul4
--.*: 0430f7c0 uqincb x0, mul3
--.*: 0430f7c0 uqincb x0, mul3
--.*: 0430f7c0 uqincb x0, mul3
--.*: 0430f7e0 uqincb x0
--.*: 0430f7e0 uqincb x0
--.*: 0430f7e0 uqincb x0
--.*: 0430f7e0 uqincb x0
--.*: 0437f400 uqincb x0, pow2, mul #8
--.*: 0437f400 uqincb x0, pow2, mul #8
--.*: 0438f400 uqincb x0, pow2, mul #9
--.*: 0438f400 uqincb x0, pow2, mul #9
--.*: 0439f400 uqincb x0, pow2, mul #10
--.*: 0439f400 uqincb x0, pow2, mul #10
--.*: 043ff400 uqincb x0, pow2, mul #16
--.*: 043ff400 uqincb x0, pow2, mul #16
--.*: 04e0c400 uqincd z0\.d, pow2
--.*: 04e0c400 uqincd z0\.d, pow2
--.*: 04e0c400 uqincd z0\.d, pow2
--.*: 04e0c401 uqincd z1\.d, pow2
--.*: 04e0c401 uqincd z1\.d, pow2
--.*: 04e0c401 uqincd z1\.d, pow2
--.*: 04e0c41f uqincd z31\.d, pow2
--.*: 04e0c41f uqincd z31\.d, pow2
--.*: 04e0c41f uqincd z31\.d, pow2
--.*: 04e0c420 uqincd z0\.d, vl1
--.*: 04e0c420 uqincd z0\.d, vl1
--.*: 04e0c420 uqincd z0\.d, vl1
--.*: 04e0c440 uqincd z0\.d, vl2
--.*: 04e0c440 uqincd z0\.d, vl2
--.*: 04e0c440 uqincd z0\.d, vl2
--.*: 04e0c460 uqincd z0\.d, vl3
--.*: 04e0c460 uqincd z0\.d, vl3
--.*: 04e0c460 uqincd z0\.d, vl3
--.*: 04e0c480 uqincd z0\.d, vl4
--.*: 04e0c480 uqincd z0\.d, vl4
--.*: 04e0c480 uqincd z0\.d, vl4
--.*: 04e0c4a0 uqincd z0\.d, vl5
--.*: 04e0c4a0 uqincd z0\.d, vl5
--.*: 04e0c4a0 uqincd z0\.d, vl5
--.*: 04e0c4c0 uqincd z0\.d, vl6
--.*: 04e0c4c0 uqincd z0\.d, vl6
--.*: 04e0c4c0 uqincd z0\.d, vl6
--.*: 04e0c4e0 uqincd z0\.d, vl7
--.*: 04e0c4e0 uqincd z0\.d, vl7
--.*: 04e0c4e0 uqincd z0\.d, vl7
--.*: 04e0c500 uqincd z0\.d, vl8
--.*: 04e0c500 uqincd z0\.d, vl8
--.*: 04e0c500 uqincd z0\.d, vl8
--.*: 04e0c520 uqincd z0\.d, vl16
--.*: 04e0c520 uqincd z0\.d, vl16
--.*: 04e0c520 uqincd z0\.d, vl16
--.*: 04e0c540 uqincd z0\.d, vl32
--.*: 04e0c540 uqincd z0\.d, vl32
--.*: 04e0c540 uqincd z0\.d, vl32
--.*: 04e0c560 uqincd z0\.d, vl64
--.*: 04e0c560 uqincd z0\.d, vl64
--.*: 04e0c560 uqincd z0\.d, vl64
--.*: 04e0c580 uqincd z0\.d, vl128
--.*: 04e0c580 uqincd z0\.d, vl128
--.*: 04e0c580 uqincd z0\.d, vl128
--.*: 04e0c5a0 uqincd z0\.d, vl256
--.*: 04e0c5a0 uqincd z0\.d, vl256
--.*: 04e0c5a0 uqincd z0\.d, vl256
--.*: 04e0c5c0 uqincd z0\.d, #14
--.*: 04e0c5c0 uqincd z0\.d, #14
--.*: 04e0c5c0 uqincd z0\.d, #14
--.*: 04e0c5e0 uqincd z0\.d, #15
--.*: 04e0c5e0 uqincd z0\.d, #15
--.*: 04e0c5e0 uqincd z0\.d, #15
--.*: 04e0c600 uqincd z0\.d, #16
--.*: 04e0c600 uqincd z0\.d, #16
--.*: 04e0c600 uqincd z0\.d, #16
--.*: 04e0c620 uqincd z0\.d, #17
--.*: 04e0c620 uqincd z0\.d, #17
--.*: 04e0c620 uqincd z0\.d, #17
--.*: 04e0c640 uqincd z0\.d, #18
--.*: 04e0c640 uqincd z0\.d, #18
--.*: 04e0c640 uqincd z0\.d, #18
--.*: 04e0c660 uqincd z0\.d, #19
--.*: 04e0c660 uqincd z0\.d, #19
--.*: 04e0c660 uqincd z0\.d, #19
--.*: 04e0c680 uqincd z0\.d, #20
--.*: 04e0c680 uqincd z0\.d, #20
--.*: 04e0c680 uqincd z0\.d, #20
--.*: 04e0c6a0 uqincd z0\.d, #21
--.*: 04e0c6a0 uqincd z0\.d, #21
--.*: 04e0c6a0 uqincd z0\.d, #21
--.*: 04e0c6c0 uqincd z0\.d, #22
--.*: 04e0c6c0 uqincd z0\.d, #22
--.*: 04e0c6c0 uqincd z0\.d, #22
--.*: 04e0c6e0 uqincd z0\.d, #23
--.*: 04e0c6e0 uqincd z0\.d, #23
--.*: 04e0c6e0 uqincd z0\.d, #23
--.*: 04e0c700 uqincd z0\.d, #24
--.*: 04e0c700 uqincd z0\.d, #24
--.*: 04e0c700 uqincd z0\.d, #24
--.*: 04e0c720 uqincd z0\.d, #25
--.*: 04e0c720 uqincd z0\.d, #25
--.*: 04e0c720 uqincd z0\.d, #25
--.*: 04e0c740 uqincd z0\.d, #26
--.*: 04e0c740 uqincd z0\.d, #26
--.*: 04e0c740 uqincd z0\.d, #26
--.*: 04e0c760 uqincd z0\.d, #27
--.*: 04e0c760 uqincd z0\.d, #27
--.*: 04e0c760 uqincd z0\.d, #27
--.*: 04e0c780 uqincd z0\.d, #28
--.*: 04e0c780 uqincd z0\.d, #28
--.*: 04e0c780 uqincd z0\.d, #28
--.*: 04e0c7a0 uqincd z0\.d, mul4
--.*: 04e0c7a0 uqincd z0\.d, mul4
--.*: 04e0c7a0 uqincd z0\.d, mul4
--.*: 04e0c7c0 uqincd z0\.d, mul3
--.*: 04e0c7c0 uqincd z0\.d, mul3
--.*: 04e0c7c0 uqincd z0\.d, mul3
--.*: 04e0c7e0 uqincd z0\.d
--.*: 04e0c7e0 uqincd z0\.d
--.*: 04e0c7e0 uqincd z0\.d
--.*: 04e0c7e0 uqincd z0\.d
--.*: 04e7c400 uqincd z0\.d, pow2, mul #8
--.*: 04e7c400 uqincd z0\.d, pow2, mul #8
--.*: 04e8c400 uqincd z0\.d, pow2, mul #9
--.*: 04e8c400 uqincd z0\.d, pow2, mul #9
--.*: 04e9c400 uqincd z0\.d, pow2, mul #10
--.*: 04e9c400 uqincd z0\.d, pow2, mul #10
--.*: 04efc400 uqincd z0\.d, pow2, mul #16
--.*: 04efc400 uqincd z0\.d, pow2, mul #16
--.*: 04e0f400 uqincd w0, pow2
--.*: 04e0f400 uqincd w0, pow2
--.*: 04e0f400 uqincd w0, pow2
--.*: 04e0f401 uqincd w1, pow2
--.*: 04e0f401 uqincd w1, pow2
--.*: 04e0f401 uqincd w1, pow2
--.*: 04e0f41f uqincd wzr, pow2
--.*: 04e0f41f uqincd wzr, pow2
--.*: 04e0f41f uqincd wzr, pow2
--.*: 04e0f420 uqincd w0, vl1
--.*: 04e0f420 uqincd w0, vl1
--.*: 04e0f420 uqincd w0, vl1
--.*: 04e0f440 uqincd w0, vl2
--.*: 04e0f440 uqincd w0, vl2
--.*: 04e0f440 uqincd w0, vl2
--.*: 04e0f460 uqincd w0, vl3
--.*: 04e0f460 uqincd w0, vl3
--.*: 04e0f460 uqincd w0, vl3
--.*: 04e0f480 uqincd w0, vl4
--.*: 04e0f480 uqincd w0, vl4
--.*: 04e0f480 uqincd w0, vl4
--.*: 04e0f4a0 uqincd w0, vl5
--.*: 04e0f4a0 uqincd w0, vl5
--.*: 04e0f4a0 uqincd w0, vl5
--.*: 04e0f4c0 uqincd w0, vl6
--.*: 04e0f4c0 uqincd w0, vl6
--.*: 04e0f4c0 uqincd w0, vl6
--.*: 04e0f4e0 uqincd w0, vl7
--.*: 04e0f4e0 uqincd w0, vl7
--.*: 04e0f4e0 uqincd w0, vl7
--.*: 04e0f500 uqincd w0, vl8
--.*: 04e0f500 uqincd w0, vl8
--.*: 04e0f500 uqincd w0, vl8
--.*: 04e0f520 uqincd w0, vl16
--.*: 04e0f520 uqincd w0, vl16
--.*: 04e0f520 uqincd w0, vl16
--.*: 04e0f540 uqincd w0, vl32
--.*: 04e0f540 uqincd w0, vl32
--.*: 04e0f540 uqincd w0, vl32
--.*: 04e0f560 uqincd w0, vl64
--.*: 04e0f560 uqincd w0, vl64
--.*: 04e0f560 uqincd w0, vl64
--.*: 04e0f580 uqincd w0, vl128
--.*: 04e0f580 uqincd w0, vl128
--.*: 04e0f580 uqincd w0, vl128
--.*: 04e0f5a0 uqincd w0, vl256
--.*: 04e0f5a0 uqincd w0, vl256
--.*: 04e0f5a0 uqincd w0, vl256
--.*: 04e0f5c0 uqincd w0, #14
--.*: 04e0f5c0 uqincd w0, #14
--.*: 04e0f5c0 uqincd w0, #14
--.*: 04e0f5e0 uqincd w0, #15
--.*: 04e0f5e0 uqincd w0, #15
--.*: 04e0f5e0 uqincd w0, #15
--.*: 04e0f600 uqincd w0, #16
--.*: 04e0f600 uqincd w0, #16
--.*: 04e0f600 uqincd w0, #16
--.*: 04e0f620 uqincd w0, #17
--.*: 04e0f620 uqincd w0, #17
--.*: 04e0f620 uqincd w0, #17
--.*: 04e0f640 uqincd w0, #18
--.*: 04e0f640 uqincd w0, #18
--.*: 04e0f640 uqincd w0, #18
--.*: 04e0f660 uqincd w0, #19
--.*: 04e0f660 uqincd w0, #19
--.*: 04e0f660 uqincd w0, #19
--.*: 04e0f680 uqincd w0, #20
--.*: 04e0f680 uqincd w0, #20
--.*: 04e0f680 uqincd w0, #20
--.*: 04e0f6a0 uqincd w0, #21
--.*: 04e0f6a0 uqincd w0, #21
--.*: 04e0f6a0 uqincd w0, #21
--.*: 04e0f6c0 uqincd w0, #22
--.*: 04e0f6c0 uqincd w0, #22
--.*: 04e0f6c0 uqincd w0, #22
--.*: 04e0f6e0 uqincd w0, #23
--.*: 04e0f6e0 uqincd w0, #23
--.*: 04e0f6e0 uqincd w0, #23
--.*: 04e0f700 uqincd w0, #24
--.*: 04e0f700 uqincd w0, #24
--.*: 04e0f700 uqincd w0, #24
--.*: 04e0f720 uqincd w0, #25
--.*: 04e0f720 uqincd w0, #25
--.*: 04e0f720 uqincd w0, #25
--.*: 04e0f740 uqincd w0, #26
--.*: 04e0f740 uqincd w0, #26
--.*: 04e0f740 uqincd w0, #26
--.*: 04e0f760 uqincd w0, #27
--.*: 04e0f760 uqincd w0, #27
--.*: 04e0f760 uqincd w0, #27
--.*: 04e0f780 uqincd w0, #28
--.*: 04e0f780 uqincd w0, #28
--.*: 04e0f780 uqincd w0, #28
--.*: 04e0f7a0 uqincd w0, mul4
--.*: 04e0f7a0 uqincd w0, mul4
--.*: 04e0f7a0 uqincd w0, mul4
--.*: 04e0f7c0 uqincd w0, mul3
--.*: 04e0f7c0 uqincd w0, mul3
--.*: 04e0f7c0 uqincd w0, mul3
--.*: 04e0f7e0 uqincd w0
--.*: 04e0f7e0 uqincd w0
--.*: 04e0f7e0 uqincd w0
--.*: 04e0f7e0 uqincd w0
--.*: 04e7f400 uqincd w0, pow2, mul #8
--.*: 04e7f400 uqincd w0, pow2, mul #8
--.*: 04e8f400 uqincd w0, pow2, mul #9
--.*: 04e8f400 uqincd w0, pow2, mul #9
--.*: 04e9f400 uqincd w0, pow2, mul #10
--.*: 04e9f400 uqincd w0, pow2, mul #10
--.*: 04eff400 uqincd w0, pow2, mul #16
--.*: 04eff400 uqincd w0, pow2, mul #16
--.*: 04f0f400 uqincd x0, pow2
--.*: 04f0f400 uqincd x0, pow2
--.*: 04f0f400 uqincd x0, pow2
--.*: 04f0f401 uqincd x1, pow2
--.*: 04f0f401 uqincd x1, pow2
--.*: 04f0f401 uqincd x1, pow2
--.*: 04f0f41f uqincd xzr, pow2
--.*: 04f0f41f uqincd xzr, pow2
--.*: 04f0f41f uqincd xzr, pow2
--.*: 04f0f420 uqincd x0, vl1
--.*: 04f0f420 uqincd x0, vl1
--.*: 04f0f420 uqincd x0, vl1
--.*: 04f0f440 uqincd x0, vl2
--.*: 04f0f440 uqincd x0, vl2
--.*: 04f0f440 uqincd x0, vl2
--.*: 04f0f460 uqincd x0, vl3
--.*: 04f0f460 uqincd x0, vl3
--.*: 04f0f460 uqincd x0, vl3
--.*: 04f0f480 uqincd x0, vl4
--.*: 04f0f480 uqincd x0, vl4
--.*: 04f0f480 uqincd x0, vl4
--.*: 04f0f4a0 uqincd x0, vl5
--.*: 04f0f4a0 uqincd x0, vl5
--.*: 04f0f4a0 uqincd x0, vl5
--.*: 04f0f4c0 uqincd x0, vl6
--.*: 04f0f4c0 uqincd x0, vl6
--.*: 04f0f4c0 uqincd x0, vl6
--.*: 04f0f4e0 uqincd x0, vl7
--.*: 04f0f4e0 uqincd x0, vl7
--.*: 04f0f4e0 uqincd x0, vl7
--.*: 04f0f500 uqincd x0, vl8
--.*: 04f0f500 uqincd x0, vl8
--.*: 04f0f500 uqincd x0, vl8
--.*: 04f0f520 uqincd x0, vl16
--.*: 04f0f520 uqincd x0, vl16
--.*: 04f0f520 uqincd x0, vl16
--.*: 04f0f540 uqincd x0, vl32
--.*: 04f0f540 uqincd x0, vl32
--.*: 04f0f540 uqincd x0, vl32
--.*: 04f0f560 uqincd x0, vl64
--.*: 04f0f560 uqincd x0, vl64
--.*: 04f0f560 uqincd x0, vl64
--.*: 04f0f580 uqincd x0, vl128
--.*: 04f0f580 uqincd x0, vl128
--.*: 04f0f580 uqincd x0, vl128
--.*: 04f0f5a0 uqincd x0, vl256
--.*: 04f0f5a0 uqincd x0, vl256
--.*: 04f0f5a0 uqincd x0, vl256
--.*: 04f0f5c0 uqincd x0, #14
--.*: 04f0f5c0 uqincd x0, #14
--.*: 04f0f5c0 uqincd x0, #14
--.*: 04f0f5e0 uqincd x0, #15
--.*: 04f0f5e0 uqincd x0, #15
--.*: 04f0f5e0 uqincd x0, #15
--.*: 04f0f600 uqincd x0, #16
--.*: 04f0f600 uqincd x0, #16
--.*: 04f0f600 uqincd x0, #16
--.*: 04f0f620 uqincd x0, #17
--.*: 04f0f620 uqincd x0, #17
--.*: 04f0f620 uqincd x0, #17
--.*: 04f0f640 uqincd x0, #18
--.*: 04f0f640 uqincd x0, #18
--.*: 04f0f640 uqincd x0, #18
--.*: 04f0f660 uqincd x0, #19
--.*: 04f0f660 uqincd x0, #19
--.*: 04f0f660 uqincd x0, #19
--.*: 04f0f680 uqincd x0, #20
--.*: 04f0f680 uqincd x0, #20
--.*: 04f0f680 uqincd x0, #20
--.*: 04f0f6a0 uqincd x0, #21
--.*: 04f0f6a0 uqincd x0, #21
--.*: 04f0f6a0 uqincd x0, #21
--.*: 04f0f6c0 uqincd x0, #22
--.*: 04f0f6c0 uqincd x0, #22
--.*: 04f0f6c0 uqincd x0, #22
--.*: 04f0f6e0 uqincd x0, #23
--.*: 04f0f6e0 uqincd x0, #23
--.*: 04f0f6e0 uqincd x0, #23
--.*: 04f0f700 uqincd x0, #24
--.*: 04f0f700 uqincd x0, #24
--.*: 04f0f700 uqincd x0, #24
--.*: 04f0f720 uqincd x0, #25
--.*: 04f0f720 uqincd x0, #25
--.*: 04f0f720 uqincd x0, #25
--.*: 04f0f740 uqincd x0, #26
--.*: 04f0f740 uqincd x0, #26
--.*: 04f0f740 uqincd x0, #26
--.*: 04f0f760 uqincd x0, #27
--.*: 04f0f760 uqincd x0, #27
--.*: 04f0f760 uqincd x0, #27
--.*: 04f0f780 uqincd x0, #28
--.*: 04f0f780 uqincd x0, #28
--.*: 04f0f780 uqincd x0, #28
--.*: 04f0f7a0 uqincd x0, mul4
--.*: 04f0f7a0 uqincd x0, mul4
--.*: 04f0f7a0 uqincd x0, mul4
--.*: 04f0f7c0 uqincd x0, mul3
--.*: 04f0f7c0 uqincd x0, mul3
--.*: 04f0f7c0 uqincd x0, mul3
--.*: 04f0f7e0 uqincd x0
--.*: 04f0f7e0 uqincd x0
--.*: 04f0f7e0 uqincd x0
--.*: 04f0f7e0 uqincd x0
--.*: 04f7f400 uqincd x0, pow2, mul #8
--.*: 04f7f400 uqincd x0, pow2, mul #8
--.*: 04f8f400 uqincd x0, pow2, mul #9
--.*: 04f8f400 uqincd x0, pow2, mul #9
--.*: 04f9f400 uqincd x0, pow2, mul #10
--.*: 04f9f400 uqincd x0, pow2, mul #10
--.*: 04fff400 uqincd x0, pow2, mul #16
--.*: 04fff400 uqincd x0, pow2, mul #16
--.*: 0460c400 uqinch z0\.h, pow2
--.*: 0460c400 uqinch z0\.h, pow2
--.*: 0460c400 uqinch z0\.h, pow2
--.*: 0460c401 uqinch z1\.h, pow2
--.*: 0460c401 uqinch z1\.h, pow2
--.*: 0460c401 uqinch z1\.h, pow2
--.*: 0460c41f uqinch z31\.h, pow2
--.*: 0460c41f uqinch z31\.h, pow2
--.*: 0460c41f uqinch z31\.h, pow2
--.*: 0460c420 uqinch z0\.h, vl1
--.*: 0460c420 uqinch z0\.h, vl1
--.*: 0460c420 uqinch z0\.h, vl1
--.*: 0460c440 uqinch z0\.h, vl2
--.*: 0460c440 uqinch z0\.h, vl2
--.*: 0460c440 uqinch z0\.h, vl2
--.*: 0460c460 uqinch z0\.h, vl3
--.*: 0460c460 uqinch z0\.h, vl3
--.*: 0460c460 uqinch z0\.h, vl3
--.*: 0460c480 uqinch z0\.h, vl4
--.*: 0460c480 uqinch z0\.h, vl4
--.*: 0460c480 uqinch z0\.h, vl4
--.*: 0460c4a0 uqinch z0\.h, vl5
--.*: 0460c4a0 uqinch z0\.h, vl5
--.*: 0460c4a0 uqinch z0\.h, vl5
--.*: 0460c4c0 uqinch z0\.h, vl6
--.*: 0460c4c0 uqinch z0\.h, vl6
--.*: 0460c4c0 uqinch z0\.h, vl6
--.*: 0460c4e0 uqinch z0\.h, vl7
--.*: 0460c4e0 uqinch z0\.h, vl7
--.*: 0460c4e0 uqinch z0\.h, vl7
--.*: 0460c500 uqinch z0\.h, vl8
--.*: 0460c500 uqinch z0\.h, vl8
--.*: 0460c500 uqinch z0\.h, vl8
--.*: 0460c520 uqinch z0\.h, vl16
--.*: 0460c520 uqinch z0\.h, vl16
--.*: 0460c520 uqinch z0\.h, vl16
--.*: 0460c540 uqinch z0\.h, vl32
--.*: 0460c540 uqinch z0\.h, vl32
--.*: 0460c540 uqinch z0\.h, vl32
--.*: 0460c560 uqinch z0\.h, vl64
--.*: 0460c560 uqinch z0\.h, vl64
--.*: 0460c560 uqinch z0\.h, vl64
--.*: 0460c580 uqinch z0\.h, vl128
--.*: 0460c580 uqinch z0\.h, vl128
--.*: 0460c580 uqinch z0\.h, vl128
--.*: 0460c5a0 uqinch z0\.h, vl256
--.*: 0460c5a0 uqinch z0\.h, vl256
--.*: 0460c5a0 uqinch z0\.h, vl256
--.*: 0460c5c0 uqinch z0\.h, #14
--.*: 0460c5c0 uqinch z0\.h, #14
--.*: 0460c5c0 uqinch z0\.h, #14
--.*: 0460c5e0 uqinch z0\.h, #15
--.*: 0460c5e0 uqinch z0\.h, #15
--.*: 0460c5e0 uqinch z0\.h, #15
--.*: 0460c600 uqinch z0\.h, #16
--.*: 0460c600 uqinch z0\.h, #16
--.*: 0460c600 uqinch z0\.h, #16
--.*: 0460c620 uqinch z0\.h, #17
--.*: 0460c620 uqinch z0\.h, #17
--.*: 0460c620 uqinch z0\.h, #17
--.*: 0460c640 uqinch z0\.h, #18
--.*: 0460c640 uqinch z0\.h, #18
--.*: 0460c640 uqinch z0\.h, #18
--.*: 0460c660 uqinch z0\.h, #19
--.*: 0460c660 uqinch z0\.h, #19
--.*: 0460c660 uqinch z0\.h, #19
--.*: 0460c680 uqinch z0\.h, #20
--.*: 0460c680 uqinch z0\.h, #20
--.*: 0460c680 uqinch z0\.h, #20
--.*: 0460c6a0 uqinch z0\.h, #21
--.*: 0460c6a0 uqinch z0\.h, #21
--.*: 0460c6a0 uqinch z0\.h, #21
--.*: 0460c6c0 uqinch z0\.h, #22
--.*: 0460c6c0 uqinch z0\.h, #22
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--.*: 0460c6e0 uqinch z0\.h, #23
--.*: 0460c6e0 uqinch z0\.h, #23
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--.*: 0460c700 uqinch z0\.h, #24
--.*: 0460c700 uqinch z0\.h, #24
--.*: 0460c700 uqinch z0\.h, #24
--.*: 0460c720 uqinch z0\.h, #25
--.*: 0460c720 uqinch z0\.h, #25
--.*: 0460c720 uqinch z0\.h, #25
--.*: 0460c740 uqinch z0\.h, #26
--.*: 0460c740 uqinch z0\.h, #26
--.*: 0460c740 uqinch z0\.h, #26
--.*: 0460c760 uqinch z0\.h, #27
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--.*: 0460c760 uqinch z0\.h, #27
--.*: 0460c780 uqinch z0\.h, #28
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--.*: 04a0c4a0 uqincw z0\.s, vl5
--.*: 04a0c4c0 uqincw z0\.s, vl6
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--.*: 04a0c4e0 uqincw z0\.s, vl7
--.*: 04a0c500 uqincw z0\.s, vl8
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--.*: 04a0c520 uqincw z0\.s, vl16
--.*: 04a0c520 uqincw z0\.s, vl16
--.*: 04a0c520 uqincw z0\.s, vl16
--.*: 04a0c540 uqincw z0\.s, vl32
--.*: 04a0c540 uqincw z0\.s, vl32
--.*: 04a0c540 uqincw z0\.s, vl32
--.*: 04a0c560 uqincw z0\.s, vl64
--.*: 04a0c560 uqincw z0\.s, vl64
--.*: 04a0c560 uqincw z0\.s, vl64
--.*: 04a0c580 uqincw z0\.s, vl128
--.*: 04a0c580 uqincw z0\.s, vl128
--.*: 04a0c580 uqincw z0\.s, vl128
--.*: 04a0c5a0 uqincw z0\.s, vl256
--.*: 04a0c5a0 uqincw z0\.s, vl256
--.*: 04a0c5a0 uqincw z0\.s, vl256
--.*: 04a0c5c0 uqincw z0\.s, #14
--.*: 04a0c5c0 uqincw z0\.s, #14
--.*: 04a0c5c0 uqincw z0\.s, #14
--.*: 04a0c5e0 uqincw z0\.s, #15
--.*: 04a0c5e0 uqincw z0\.s, #15
--.*: 04a0c5e0 uqincw z0\.s, #15
--.*: 04a0c600 uqincw z0\.s, #16
--.*: 04a0c600 uqincw z0\.s, #16
--.*: 04a0c600 uqincw z0\.s, #16
--.*: 04a0c620 uqincw z0\.s, #17
--.*: 04a0c620 uqincw z0\.s, #17
--.*: 04a0c620 uqincw z0\.s, #17
--.*: 04a0c640 uqincw z0\.s, #18
--.*: 04a0c640 uqincw z0\.s, #18
--.*: 04a0c640 uqincw z0\.s, #18
--.*: 04a0c660 uqincw z0\.s, #19
--.*: 04a0c660 uqincw z0\.s, #19
--.*: 04a0c660 uqincw z0\.s, #19
--.*: 04a0c680 uqincw z0\.s, #20
--.*: 04a0c680 uqincw z0\.s, #20
--.*: 04a0c680 uqincw z0\.s, #20
--.*: 04a0c6a0 uqincw z0\.s, #21
--.*: 04a0c6a0 uqincw z0\.s, #21
--.*: 04a0c6a0 uqincw z0\.s, #21
--.*: 04a0c6c0 uqincw z0\.s, #22
--.*: 04a0c6c0 uqincw z0\.s, #22
--.*: 04a0c6c0 uqincw z0\.s, #22
--.*: 04a0c6e0 uqincw z0\.s, #23
--.*: 04a0c6e0 uqincw z0\.s, #23
--.*: 04a0c6e0 uqincw z0\.s, #23
--.*: 04a0c700 uqincw z0\.s, #24
--.*: 04a0c700 uqincw z0\.s, #24
--.*: 04a0c700 uqincw z0\.s, #24
--.*: 04a0c720 uqincw z0\.s, #25
--.*: 04a0c720 uqincw z0\.s, #25
--.*: 04a0c720 uqincw z0\.s, #25
--.*: 04a0c740 uqincw z0\.s, #26
--.*: 04a0c740 uqincw z0\.s, #26
--.*: 04a0c740 uqincw z0\.s, #26
--.*: 04a0c760 uqincw z0\.s, #27
--.*: 04a0c760 uqincw z0\.s, #27
--.*: 04a0c760 uqincw z0\.s, #27
--.*: 04a0c780 uqincw z0\.s, #28
--.*: 04a0c780 uqincw z0\.s, #28
--.*: 04a0c780 uqincw z0\.s, #28
--.*: 04a0c7a0 uqincw z0\.s, mul4
--.*: 04a0c7a0 uqincw z0\.s, mul4
--.*: 04a0c7a0 uqincw z0\.s, mul4
--.*: 04a0c7c0 uqincw z0\.s, mul3
--.*: 04a0c7c0 uqincw z0\.s, mul3
--.*: 04a0c7c0 uqincw z0\.s, mul3
--.*: 04a0c7e0 uqincw z0\.s
--.*: 04a0c7e0 uqincw z0\.s
--.*: 04a0c7e0 uqincw z0\.s
--.*: 04a0c7e0 uqincw z0\.s
--.*: 04a7c400 uqincw z0\.s, pow2, mul #8
--.*: 04a7c400 uqincw z0\.s, pow2, mul #8
--.*: 04a8c400 uqincw z0\.s, pow2, mul #9
--.*: 04a8c400 uqincw z0\.s, pow2, mul #9
--.*: 04a9c400 uqincw z0\.s, pow2, mul #10
--.*: 04a9c400 uqincw z0\.s, pow2, mul #10
--.*: 04afc400 uqincw z0\.s, pow2, mul #16
--.*: 04afc400 uqincw z0\.s, pow2, mul #16
--.*: 04a0f400 uqincw w0, pow2
--.*: 04a0f400 uqincw w0, pow2
--.*: 04a0f400 uqincw w0, pow2
--.*: 04a0f401 uqincw w1, pow2
--.*: 04a0f401 uqincw w1, pow2
--.*: 04a0f401 uqincw w1, pow2
--.*: 04a0f41f uqincw wzr, pow2
--.*: 04a0f41f uqincw wzr, pow2
--.*: 04a0f41f uqincw wzr, pow2
--.*: 04a0f420 uqincw w0, vl1
--.*: 04a0f420 uqincw w0, vl1
--.*: 04a0f420 uqincw w0, vl1
--.*: 04a0f440 uqincw w0, vl2
--.*: 04a0f440 uqincw w0, vl2
--.*: 04a0f440 uqincw w0, vl2
--.*: 04a0f460 uqincw w0, vl3
--.*: 04a0f460 uqincw w0, vl3
--.*: 04a0f460 uqincw w0, vl3
--.*: 04a0f480 uqincw w0, vl4
--.*: 04a0f480 uqincw w0, vl4
--.*: 04a0f480 uqincw w0, vl4
--.*: 04a0f4a0 uqincw w0, vl5
--.*: 04a0f4a0 uqincw w0, vl5
--.*: 04a0f4a0 uqincw w0, vl5
--.*: 04a0f4c0 uqincw w0, vl6
--.*: 04a0f4c0 uqincw w0, vl6
--.*: 04a0f4c0 uqincw w0, vl6
--.*: 04a0f4e0 uqincw w0, vl7
--.*: 04a0f4e0 uqincw w0, vl7
--.*: 04a0f4e0 uqincw w0, vl7
--.*: 04a0f500 uqincw w0, vl8
--.*: 04a0f500 uqincw w0, vl8
--.*: 04a0f500 uqincw w0, vl8
--.*: 04a0f520 uqincw w0, vl16
--.*: 04a0f520 uqincw w0, vl16
--.*: 04a0f520 uqincw w0, vl16
--.*: 04a0f540 uqincw w0, vl32
--.*: 04a0f540 uqincw w0, vl32
--.*: 04a0f540 uqincw w0, vl32
--.*: 04a0f560 uqincw w0, vl64
--.*: 04a0f560 uqincw w0, vl64
--.*: 04a0f560 uqincw w0, vl64
--.*: 04a0f580 uqincw w0, vl128
--.*: 04a0f580 uqincw w0, vl128
--.*: 04a0f580 uqincw w0, vl128
--.*: 04a0f5a0 uqincw w0, vl256
--.*: 04a0f5a0 uqincw w0, vl256
--.*: 04a0f5a0 uqincw w0, vl256
--.*: 04a0f5c0 uqincw w0, #14
--.*: 04a0f5c0 uqincw w0, #14
--.*: 04a0f5c0 uqincw w0, #14
--.*: 04a0f5e0 uqincw w0, #15
--.*: 04a0f5e0 uqincw w0, #15
--.*: 04a0f5e0 uqincw w0, #15
--.*: 04a0f600 uqincw w0, #16
--.*: 04a0f600 uqincw w0, #16
--.*: 04a0f600 uqincw w0, #16
--.*: 04a0f620 uqincw w0, #17
--.*: 04a0f620 uqincw w0, #17
--.*: 04a0f620 uqincw w0, #17
--.*: 04a0f640 uqincw w0, #18
--.*: 04a0f640 uqincw w0, #18
--.*: 04a0f640 uqincw w0, #18
--.*: 04a0f660 uqincw w0, #19
--.*: 04a0f660 uqincw w0, #19
--.*: 04a0f660 uqincw w0, #19
--.*: 04a0f680 uqincw w0, #20
--.*: 04a0f680 uqincw w0, #20
--.*: 04a0f680 uqincw w0, #20
--.*: 04a0f6a0 uqincw w0, #21
--.*: 04a0f6a0 uqincw w0, #21
--.*: 04a0f6a0 uqincw w0, #21
--.*: 04a0f6c0 uqincw w0, #22
--.*: 04a0f6c0 uqincw w0, #22
--.*: 04a0f6c0 uqincw w0, #22
--.*: 04a0f6e0 uqincw w0, #23
--.*: 04a0f6e0 uqincw w0, #23
--.*: 04a0f6e0 uqincw w0, #23
--.*: 04a0f700 uqincw w0, #24
--.*: 04a0f700 uqincw w0, #24
--.*: 04a0f700 uqincw w0, #24
--.*: 04a0f720 uqincw w0, #25
--.*: 04a0f720 uqincw w0, #25
--.*: 04a0f720 uqincw w0, #25
--.*: 04a0f740 uqincw w0, #26
--.*: 04a0f740 uqincw w0, #26
--.*: 04a0f740 uqincw w0, #26
--.*: 04a0f760 uqincw w0, #27
--.*: 04a0f760 uqincw w0, #27
--.*: 04a0f760 uqincw w0, #27
--.*: 04a0f780 uqincw w0, #28
--.*: 04a0f780 uqincw w0, #28
--.*: 04a0f780 uqincw w0, #28
--.*: 04a0f7a0 uqincw w0, mul4
--.*: 04a0f7a0 uqincw w0, mul4
--.*: 04a0f7a0 uqincw w0, mul4
--.*: 04a0f7c0 uqincw w0, mul3
--.*: 04a0f7c0 uqincw w0, mul3
--.*: 04a0f7c0 uqincw w0, mul3
--.*: 04a0f7e0 uqincw w0
--.*: 04a0f7e0 uqincw w0
--.*: 04a0f7e0 uqincw w0
--.*: 04a0f7e0 uqincw w0
--.*: 04a7f400 uqincw w0, pow2, mul #8
--.*: 04a7f400 uqincw w0, pow2, mul #8
--.*: 04a8f400 uqincw w0, pow2, mul #9
--.*: 04a8f400 uqincw w0, pow2, mul #9
--.*: 04a9f400 uqincw w0, pow2, mul #10
--.*: 04a9f400 uqincw w0, pow2, mul #10
--.*: 04aff400 uqincw w0, pow2, mul #16
--.*: 04aff400 uqincw w0, pow2, mul #16
--.*: 04b0f400 uqincw x0, pow2
--.*: 04b0f400 uqincw x0, pow2
--.*: 04b0f400 uqincw x0, pow2
--.*: 04b0f401 uqincw x1, pow2
--.*: 04b0f401 uqincw x1, pow2
--.*: 04b0f401 uqincw x1, pow2
--.*: 04b0f41f uqincw xzr, pow2
--.*: 04b0f41f uqincw xzr, pow2
--.*: 04b0f41f uqincw xzr, pow2
--.*: 04b0f420 uqincw x0, vl1
--.*: 04b0f420 uqincw x0, vl1
--.*: 04b0f420 uqincw x0, vl1
--.*: 04b0f440 uqincw x0, vl2
--.*: 04b0f440 uqincw x0, vl2
--.*: 04b0f440 uqincw x0, vl2
--.*: 04b0f460 uqincw x0, vl3
--.*: 04b0f460 uqincw x0, vl3
--.*: 04b0f460 uqincw x0, vl3
--.*: 04b0f480 uqincw x0, vl4
--.*: 04b0f480 uqincw x0, vl4
--.*: 04b0f480 uqincw x0, vl4
--.*: 04b0f4a0 uqincw x0, vl5
--.*: 04b0f4a0 uqincw x0, vl5
--.*: 04b0f4a0 uqincw x0, vl5
--.*: 04b0f4c0 uqincw x0, vl6
--.*: 04b0f4c0 uqincw x0, vl6
--.*: 04b0f4c0 uqincw x0, vl6
--.*: 04b0f4e0 uqincw x0, vl7
--.*: 04b0f4e0 uqincw x0, vl7
--.*: 04b0f4e0 uqincw x0, vl7
--.*: 04b0f500 uqincw x0, vl8
--.*: 04b0f500 uqincw x0, vl8
--.*: 04b0f500 uqincw x0, vl8
--.*: 04b0f520 uqincw x0, vl16
--.*: 04b0f520 uqincw x0, vl16
--.*: 04b0f520 uqincw x0, vl16
--.*: 04b0f540 uqincw x0, vl32
--.*: 04b0f540 uqincw x0, vl32
--.*: 04b0f540 uqincw x0, vl32
--.*: 04b0f560 uqincw x0, vl64
--.*: 04b0f560 uqincw x0, vl64
--.*: 04b0f560 uqincw x0, vl64
--.*: 04b0f580 uqincw x0, vl128
--.*: 04b0f580 uqincw x0, vl128
--.*: 04b0f580 uqincw x0, vl128
--.*: 04b0f5a0 uqincw x0, vl256
--.*: 04b0f5a0 uqincw x0, vl256
--.*: 04b0f5a0 uqincw x0, vl256
--.*: 04b0f5c0 uqincw x0, #14
--.*: 04b0f5c0 uqincw x0, #14
--.*: 04b0f5c0 uqincw x0, #14
--.*: 04b0f5e0 uqincw x0, #15
--.*: 04b0f5e0 uqincw x0, #15
--.*: 04b0f5e0 uqincw x0, #15
--.*: 04b0f600 uqincw x0, #16
--.*: 04b0f600 uqincw x0, #16
--.*: 04b0f600 uqincw x0, #16
--.*: 04b0f620 uqincw x0, #17
--.*: 04b0f620 uqincw x0, #17
--.*: 04b0f620 uqincw x0, #17
--.*: 04b0f640 uqincw x0, #18
--.*: 04b0f640 uqincw x0, #18
--.*: 04b0f640 uqincw x0, #18
--.*: 04b0f660 uqincw x0, #19
--.*: 04b0f660 uqincw x0, #19
--.*: 04b0f660 uqincw x0, #19
--.*: 04b0f680 uqincw x0, #20
--.*: 04b0f680 uqincw x0, #20
--.*: 04b0f680 uqincw x0, #20
--.*: 04b0f6a0 uqincw x0, #21
--.*: 04b0f6a0 uqincw x0, #21
--.*: 04b0f6a0 uqincw x0, #21
--.*: 04b0f6c0 uqincw x0, #22
--.*: 04b0f6c0 uqincw x0, #22
--.*: 04b0f6c0 uqincw x0, #22
--.*: 04b0f6e0 uqincw x0, #23
--.*: 04b0f6e0 uqincw x0, #23
--.*: 04b0f6e0 uqincw x0, #23
--.*: 04b0f700 uqincw x0, #24
--.*: 04b0f700 uqincw x0, #24
--.*: 04b0f700 uqincw x0, #24
--.*: 04b0f720 uqincw x0, #25
--.*: 04b0f720 uqincw x0, #25
--.*: 04b0f720 uqincw x0, #25
--.*: 04b0f740 uqincw x0, #26
--.*: 04b0f740 uqincw x0, #26
--.*: 04b0f740 uqincw x0, #26
--.*: 04b0f760 uqincw x0, #27
--.*: 04b0f760 uqincw x0, #27
--.*: 04b0f760 uqincw x0, #27
--.*: 04b0f780 uqincw x0, #28
--.*: 04b0f780 uqincw x0, #28
--.*: 04b0f780 uqincw x0, #28
--.*: 04b0f7a0 uqincw x0, mul4
--.*: 04b0f7a0 uqincw x0, mul4
--.*: 04b0f7a0 uqincw x0, mul4
--.*: 04b0f7c0 uqincw x0, mul3
--.*: 04b0f7c0 uqincw x0, mul3
--.*: 04b0f7c0 uqincw x0, mul3
--.*: 04b0f7e0 uqincw x0
--.*: 04b0f7e0 uqincw x0
--.*: 04b0f7e0 uqincw x0
--.*: 04b0f7e0 uqincw x0
--.*: 04b7f400 uqincw x0, pow2, mul #8
--.*: 04b7f400 uqincw x0, pow2, mul #8
--.*: 04b8f400 uqincw x0, pow2, mul #9
--.*: 04b8f400 uqincw x0, pow2, mul #9
--.*: 04b9f400 uqincw x0, pow2, mul #10
--.*: 04b9f400 uqincw x0, pow2, mul #10
--.*: 04bff400 uqincw x0, pow2, mul #16
--.*: 04bff400 uqincw x0, pow2, mul #16
--.*: 04201c00 uqsub z0\.b, z0\.b, z0\.b
--.*: 04201c00 uqsub z0\.b, z0\.b, z0\.b
--.*: 04201c01 uqsub z1\.b, z0\.b, z0\.b
--.*: 04201c01 uqsub z1\.b, z0\.b, z0\.b
--.*: 04201c1f uqsub z31\.b, z0\.b, z0\.b
--.*: 04201c1f uqsub z31\.b, z0\.b, z0\.b
--.*: 04201c40 uqsub z0\.b, z2\.b, z0\.b
--.*: 04201c40 uqsub z0\.b, z2\.b, z0\.b
--.*: 04201fe0 uqsub z0\.b, z31\.b, z0\.b
--.*: 04201fe0 uqsub z0\.b, z31\.b, z0\.b
--.*: 04231c00 uqsub z0\.b, z0\.b, z3\.b
--.*: 04231c00 uqsub z0\.b, z0\.b, z3\.b
--.*: 043f1c00 uqsub z0\.b, z0\.b, z31\.b
--.*: 043f1c00 uqsub z0\.b, z0\.b, z31\.b
--.*: 04601c00 uqsub z0\.h, z0\.h, z0\.h
--.*: 04601c00 uqsub z0\.h, z0\.h, z0\.h
--.*: 04601c01 uqsub z1\.h, z0\.h, z0\.h
--.*: 04601c01 uqsub z1\.h, z0\.h, z0\.h
--.*: 04601c1f uqsub z31\.h, z0\.h, z0\.h
--.*: 04601c1f uqsub z31\.h, z0\.h, z0\.h
--.*: 04601c40 uqsub z0\.h, z2\.h, z0\.h
--.*: 04601c40 uqsub z0\.h, z2\.h, z0\.h
--.*: 04601fe0 uqsub z0\.h, z31\.h, z0\.h
--.*: 04601fe0 uqsub z0\.h, z31\.h, z0\.h
--.*: 04631c00 uqsub z0\.h, z0\.h, z3\.h
--.*: 04631c00 uqsub z0\.h, z0\.h, z3\.h
--.*: 047f1c00 uqsub z0\.h, z0\.h, z31\.h
--.*: 047f1c00 uqsub z0\.h, z0\.h, z31\.h
--.*: 04a01c00 uqsub z0\.s, z0\.s, z0\.s
--.*: 04a01c00 uqsub z0\.s, z0\.s, z0\.s
--.*: 04a01c01 uqsub z1\.s, z0\.s, z0\.s
--.*: 04a01c01 uqsub z1\.s, z0\.s, z0\.s
--.*: 04a01c1f uqsub z31\.s, z0\.s, z0\.s
--.*: 04a01c1f uqsub z31\.s, z0\.s, z0\.s
--.*: 04a01c40 uqsub z0\.s, z2\.s, z0\.s
--.*: 04a01c40 uqsub z0\.s, z2\.s, z0\.s
--.*: 04a01fe0 uqsub z0\.s, z31\.s, z0\.s
--.*: 04a01fe0 uqsub z0\.s, z31\.s, z0\.s
--.*: 04a31c00 uqsub z0\.s, z0\.s, z3\.s
--.*: 04a31c00 uqsub z0\.s, z0\.s, z3\.s
--.*: 04bf1c00 uqsub z0\.s, z0\.s, z31\.s
--.*: 04bf1c00 uqsub z0\.s, z0\.s, z31\.s
--.*: 04e01c00 uqsub z0\.d, z0\.d, z0\.d
--.*: 04e01c00 uqsub z0\.d, z0\.d, z0\.d
--.*: 04e01c01 uqsub z1\.d, z0\.d, z0\.d
--.*: 04e01c01 uqsub z1\.d, z0\.d, z0\.d
--.*: 04e01c1f uqsub z31\.d, z0\.d, z0\.d
--.*: 04e01c1f uqsub z31\.d, z0\.d, z0\.d
--.*: 04e01c40 uqsub z0\.d, z2\.d, z0\.d
--.*: 04e01c40 uqsub z0\.d, z2\.d, z0\.d
--.*: 04e01fe0 uqsub z0\.d, z31\.d, z0\.d
--.*: 04e01fe0 uqsub z0\.d, z31\.d, z0\.d
--.*: 04e31c00 uqsub z0\.d, z0\.d, z3\.d
--.*: 04e31c00 uqsub z0\.d, z0\.d, z3\.d
--.*: 04ff1c00 uqsub z0\.d, z0\.d, z31\.d
--.*: 04ff1c00 uqsub z0\.d, z0\.d, z31\.d
--.*: 2527c000 uqsub z0\.b, z0\.b, #0
--.*: 2527c000 uqsub z0\.b, z0\.b, #0
--.*: 2527c000 uqsub z0\.b, z0\.b, #0
--.*: 2527c001 uqsub z1\.b, z1\.b, #0
--.*: 2527c001 uqsub z1\.b, z1\.b, #0
--.*: 2527c001 uqsub z1\.b, z1\.b, #0
--.*: 2527c01f uqsub z31\.b, z31\.b, #0
--.*: 2527c01f uqsub z31\.b, z31\.b, #0
--.*: 2527c01f uqsub z31\.b, z31\.b, #0
--.*: 2527c002 uqsub z2\.b, z2\.b, #0
--.*: 2527c002 uqsub z2\.b, z2\.b, #0
--.*: 2527c002 uqsub z2\.b, z2\.b, #0
--.*: 2527cfe0 uqsub z0\.b, z0\.b, #127
--.*: 2527cfe0 uqsub z0\.b, z0\.b, #127
--.*: 2527cfe0 uqsub z0\.b, z0\.b, #127
--.*: 2527d000 uqsub z0\.b, z0\.b, #128
--.*: 2527d000 uqsub z0\.b, z0\.b, #128
--.*: 2527d000 uqsub z0\.b, z0\.b, #128
--.*: 2527d020 uqsub z0\.b, z0\.b, #129
--.*: 2527d020 uqsub z0\.b, z0\.b, #129
--.*: 2527d020 uqsub z0\.b, z0\.b, #129
--.*: 2527dfe0 uqsub z0\.b, z0\.b, #255
--.*: 2527dfe0 uqsub z0\.b, z0\.b, #255
--.*: 2527dfe0 uqsub z0\.b, z0\.b, #255
--.*: 2567c000 uqsub z0\.h, z0\.h, #0
--.*: 2567c000 uqsub z0\.h, z0\.h, #0
--.*: 2567c000 uqsub z0\.h, z0\.h, #0
--.*: 2567c001 uqsub z1\.h, z1\.h, #0
--.*: 2567c001 uqsub z1\.h, z1\.h, #0
--.*: 2567c001 uqsub z1\.h, z1\.h, #0
--.*: 2567c01f uqsub z31\.h, z31\.h, #0
--.*: 2567c01f uqsub z31\.h, z31\.h, #0
--.*: 2567c01f uqsub z31\.h, z31\.h, #0
--.*: 2567c002 uqsub z2\.h, z2\.h, #0
--.*: 2567c002 uqsub z2\.h, z2\.h, #0
--.*: 2567c002 uqsub z2\.h, z2\.h, #0
--.*: 2567cfe0 uqsub z0\.h, z0\.h, #127
--.*: 2567cfe0 uqsub z0\.h, z0\.h, #127
--.*: 2567cfe0 uqsub z0\.h, z0\.h, #127
--.*: 2567d000 uqsub z0\.h, z0\.h, #128
--.*: 2567d000 uqsub z0\.h, z0\.h, #128
--.*: 2567d000 uqsub z0\.h, z0\.h, #128
--.*: 2567d020 uqsub z0\.h, z0\.h, #129
--.*: 2567d020 uqsub z0\.h, z0\.h, #129
--.*: 2567d020 uqsub z0\.h, z0\.h, #129
--.*: 2567dfe0 uqsub z0\.h, z0\.h, #255
--.*: 2567dfe0 uqsub z0\.h, z0\.h, #255
--.*: 2567dfe0 uqsub z0\.h, z0\.h, #255
--.*: 2567e000 uqsub z0\.h, z0\.h, #0, lsl #8
--.*: 2567e000 uqsub z0\.h, z0\.h, #0, lsl #8
--.*: 2567efe0 uqsub z0\.h, z0\.h, #32512
--.*: 2567efe0 uqsub z0\.h, z0\.h, #32512
--.*: 2567efe0 uqsub z0\.h, z0\.h, #32512
--.*: 2567efe0 uqsub z0\.h, z0\.h, #32512
--.*: 2567f000 uqsub z0\.h, z0\.h, #32768
--.*: 2567f000 uqsub z0\.h, z0\.h, #32768
--.*: 2567f000 uqsub z0\.h, z0\.h, #32768
--.*: 2567f000 uqsub z0\.h, z0\.h, #32768
--.*: 2567f020 uqsub z0\.h, z0\.h, #33024
--.*: 2567f020 uqsub z0\.h, z0\.h, #33024
--.*: 2567f020 uqsub z0\.h, z0\.h, #33024
--.*: 2567f020 uqsub z0\.h, z0\.h, #33024
--.*: 2567ffe0 uqsub z0\.h, z0\.h, #65280
--.*: 2567ffe0 uqsub z0\.h, z0\.h, #65280
--.*: 2567ffe0 uqsub z0\.h, z0\.h, #65280
--.*: 2567ffe0 uqsub z0\.h, z0\.h, #65280
--.*: 25a7c000 uqsub z0\.s, z0\.s, #0
--.*: 25a7c000 uqsub z0\.s, z0\.s, #0
--.*: 25a7c000 uqsub z0\.s, z0\.s, #0
--.*: 25a7c001 uqsub z1\.s, z1\.s, #0
--.*: 25a7c001 uqsub z1\.s, z1\.s, #0
--.*: 25a7c001 uqsub z1\.s, z1\.s, #0
--.*: 25a7c01f uqsub z31\.s, z31\.s, #0
--.*: 25a7c01f uqsub z31\.s, z31\.s, #0
--.*: 25a7c01f uqsub z31\.s, z31\.s, #0
--.*: 25a7c002 uqsub z2\.s, z2\.s, #0
--.*: 25a7c002 uqsub z2\.s, z2\.s, #0
--.*: 25a7c002 uqsub z2\.s, z2\.s, #0
--.*: 25a7cfe0 uqsub z0\.s, z0\.s, #127
--.*: 25a7cfe0 uqsub z0\.s, z0\.s, #127
--.*: 25a7cfe0 uqsub z0\.s, z0\.s, #127
--.*: 25a7d000 uqsub z0\.s, z0\.s, #128
--.*: 25a7d000 uqsub z0\.s, z0\.s, #128
--.*: 25a7d000 uqsub z0\.s, z0\.s, #128
--.*: 25a7d020 uqsub z0\.s, z0\.s, #129
--.*: 25a7d020 uqsub z0\.s, z0\.s, #129
--.*: 25a7d020 uqsub z0\.s, z0\.s, #129
--.*: 25a7dfe0 uqsub z0\.s, z0\.s, #255
--.*: 25a7dfe0 uqsub z0\.s, z0\.s, #255
--.*: 25a7dfe0 uqsub z0\.s, z0\.s, #255
--.*: 25a7e000 uqsub z0\.s, z0\.s, #0, lsl #8
--.*: 25a7e000 uqsub z0\.s, z0\.s, #0, lsl #8
--.*: 25a7efe0 uqsub z0\.s, z0\.s, #32512
--.*: 25a7efe0 uqsub z0\.s, z0\.s, #32512
--.*: 25a7efe0 uqsub z0\.s, z0\.s, #32512
--.*: 25a7efe0 uqsub z0\.s, z0\.s, #32512
--.*: 25a7f000 uqsub z0\.s, z0\.s, #32768
--.*: 25a7f000 uqsub z0\.s, z0\.s, #32768
--.*: 25a7f000 uqsub z0\.s, z0\.s, #32768
--.*: 25a7f000 uqsub z0\.s, z0\.s, #32768
--.*: 25a7f020 uqsub z0\.s, z0\.s, #33024
--.*: 25a7f020 uqsub z0\.s, z0\.s, #33024
--.*: 25a7f020 uqsub z0\.s, z0\.s, #33024
--.*: 25a7f020 uqsub z0\.s, z0\.s, #33024
--.*: 25a7ffe0 uqsub z0\.s, z0\.s, #65280
--.*: 25a7ffe0 uqsub z0\.s, z0\.s, #65280
--.*: 25a7ffe0 uqsub z0\.s, z0\.s, #65280
--.*: 25a7ffe0 uqsub z0\.s, z0\.s, #65280
--.*: 25e7c000 uqsub z0\.d, z0\.d, #0
--.*: 25e7c000 uqsub z0\.d, z0\.d, #0
--.*: 25e7c000 uqsub z0\.d, z0\.d, #0
--.*: 25e7c001 uqsub z1\.d, z1\.d, #0
--.*: 25e7c001 uqsub z1\.d, z1\.d, #0
--.*: 25e7c001 uqsub z1\.d, z1\.d, #0
--.*: 25e7c01f uqsub z31\.d, z31\.d, #0
--.*: 25e7c01f uqsub z31\.d, z31\.d, #0
--.*: 25e7c01f uqsub z31\.d, z31\.d, #0
--.*: 25e7c002 uqsub z2\.d, z2\.d, #0
--.*: 25e7c002 uqsub z2\.d, z2\.d, #0
--.*: 25e7c002 uqsub z2\.d, z2\.d, #0
--.*: 25e7cfe0 uqsub z0\.d, z0\.d, #127
--.*: 25e7cfe0 uqsub z0\.d, z0\.d, #127
--.*: 25e7cfe0 uqsub z0\.d, z0\.d, #127
--.*: 25e7d000 uqsub z0\.d, z0\.d, #128
--.*: 25e7d000 uqsub z0\.d, z0\.d, #128
--.*: 25e7d000 uqsub z0\.d, z0\.d, #128
--.*: 25e7d020 uqsub z0\.d, z0\.d, #129
--.*: 25e7d020 uqsub z0\.d, z0\.d, #129
--.*: 25e7d020 uqsub z0\.d, z0\.d, #129
--.*: 25e7dfe0 uqsub z0\.d, z0\.d, #255
--.*: 25e7dfe0 uqsub z0\.d, z0\.d, #255
--.*: 25e7dfe0 uqsub z0\.d, z0\.d, #255
--.*: 25e7e000 uqsub z0\.d, z0\.d, #0, lsl #8
--.*: 25e7e000 uqsub z0\.d, z0\.d, #0, lsl #8
--.*: 25e7efe0 uqsub z0\.d, z0\.d, #32512
--.*: 25e7efe0 uqsub z0\.d, z0\.d, #32512
--.*: 25e7efe0 uqsub z0\.d, z0\.d, #32512
--.*: 25e7efe0 uqsub z0\.d, z0\.d, #32512
--.*: 25e7f000 uqsub z0\.d, z0\.d, #32768
--.*: 25e7f000 uqsub z0\.d, z0\.d, #32768
--.*: 25e7f000 uqsub z0\.d, z0\.d, #32768
--.*: 25e7f000 uqsub z0\.d, z0\.d, #32768
--.*: 25e7f020 uqsub z0\.d, z0\.d, #33024
--.*: 25e7f020 uqsub z0\.d, z0\.d, #33024
--.*: 25e7f020 uqsub z0\.d, z0\.d, #33024
--.*: 25e7f020 uqsub z0\.d, z0\.d, #33024
--.*: 25e7ffe0 uqsub z0\.d, z0\.d, #65280
--.*: 25e7ffe0 uqsub z0\.d, z0\.d, #65280
--.*: 25e7ffe0 uqsub z0\.d, z0\.d, #65280
--.*: 25e7ffe0 uqsub z0\.d, z0\.d, #65280
--.*: 05733800 uunpkhi z0\.h, z0\.b
--.*: 05733800 uunpkhi z0\.h, z0\.b
--.*: 05733801 uunpkhi z1\.h, z0\.b
--.*: 05733801 uunpkhi z1\.h, z0\.b
--.*: 0573381f uunpkhi z31\.h, z0\.b
--.*: 0573381f uunpkhi z31\.h, z0\.b
--.*: 05733840 uunpkhi z0\.h, z2\.b
--.*: 05733840 uunpkhi z0\.h, z2\.b
--.*: 05733be0 uunpkhi z0\.h, z31\.b
--.*: 05733be0 uunpkhi z0\.h, z31\.b
--.*: 05b33800 uunpkhi z0\.s, z0\.h
--.*: 05b33800 uunpkhi z0\.s, z0\.h
--.*: 05b33801 uunpkhi z1\.s, z0\.h
--.*: 05b33801 uunpkhi z1\.s, z0\.h
--.*: 05b3381f uunpkhi z31\.s, z0\.h
--.*: 05b3381f uunpkhi z31\.s, z0\.h
--.*: 05b33840 uunpkhi z0\.s, z2\.h
--.*: 05b33840 uunpkhi z0\.s, z2\.h
--.*: 05b33be0 uunpkhi z0\.s, z31\.h
--.*: 05b33be0 uunpkhi z0\.s, z31\.h
--.*: 05f33800 uunpkhi z0\.d, z0\.s
--.*: 05f33800 uunpkhi z0\.d, z0\.s
--.*: 05f33801 uunpkhi z1\.d, z0\.s
--.*: 05f33801 uunpkhi z1\.d, z0\.s
--.*: 05f3381f uunpkhi z31\.d, z0\.s
--.*: 05f3381f uunpkhi z31\.d, z0\.s
--.*: 05f33840 uunpkhi z0\.d, z2\.s
--.*: 05f33840 uunpkhi z0\.d, z2\.s
--.*: 05f33be0 uunpkhi z0\.d, z31\.s
--.*: 05f33be0 uunpkhi z0\.d, z31\.s
--.*: 05723800 uunpklo z0\.h, z0\.b
--.*: 05723800 uunpklo z0\.h, z0\.b
--.*: 05723801 uunpklo z1\.h, z0\.b
--.*: 05723801 uunpklo z1\.h, z0\.b
--.*: 0572381f uunpklo z31\.h, z0\.b
--.*: 0572381f uunpklo z31\.h, z0\.b
--.*: 05723840 uunpklo z0\.h, z2\.b
--.*: 05723840 uunpklo z0\.h, z2\.b
--.*: 05723be0 uunpklo z0\.h, z31\.b
--.*: 05723be0 uunpklo z0\.h, z31\.b
--.*: 05b23800 uunpklo z0\.s, z0\.h
--.*: 05b23800 uunpklo z0\.s, z0\.h
--.*: 05b23801 uunpklo z1\.s, z0\.h
--.*: 05b23801 uunpklo z1\.s, z0\.h
--.*: 05b2381f uunpklo z31\.s, z0\.h
--.*: 05b2381f uunpklo z31\.s, z0\.h
--.*: 05b23840 uunpklo z0\.s, z2\.h
--.*: 05b23840 uunpklo z0\.s, z2\.h
--.*: 05b23be0 uunpklo z0\.s, z31\.h
--.*: 05b23be0 uunpklo z0\.s, z31\.h
--.*: 05f23800 uunpklo z0\.d, z0\.s
--.*: 05f23800 uunpklo z0\.d, z0\.s
--.*: 05f23801 uunpklo z1\.d, z0\.s
--.*: 05f23801 uunpklo z1\.d, z0\.s
--.*: 05f2381f uunpklo z31\.d, z0\.s
--.*: 05f2381f uunpklo z31\.d, z0\.s
--.*: 05f23840 uunpklo z0\.d, z2\.s
--.*: 05f23840 uunpklo z0\.d, z2\.s
--.*: 05f23be0 uunpklo z0\.d, z31\.s
--.*: 05f23be0 uunpklo z0\.d, z31\.s
--.*: 0451a000 uxtb z0\.h, p0/m, z0\.h
--.*: 0451a000 uxtb z0\.h, p0/m, z0\.h
--.*: 0451a001 uxtb z1\.h, p0/m, z0\.h
--.*: 0451a001 uxtb z1\.h, p0/m, z0\.h
--.*: 0451a01f uxtb z31\.h, p0/m, z0\.h
--.*: 0451a01f uxtb z31\.h, p0/m, z0\.h
--.*: 0451a800 uxtb z0\.h, p2/m, z0\.h
--.*: 0451a800 uxtb z0\.h, p2/m, z0\.h
--.*: 0451bc00 uxtb z0\.h, p7/m, z0\.h
--.*: 0451bc00 uxtb z0\.h, p7/m, z0\.h
--.*: 0451a060 uxtb z0\.h, p0/m, z3\.h
--.*: 0451a060 uxtb z0\.h, p0/m, z3\.h
--.*: 0451a3e0 uxtb z0\.h, p0/m, z31\.h
--.*: 0451a3e0 uxtb z0\.h, p0/m, z31\.h
--.*: 0491a000 uxtb z0\.s, p0/m, z0\.s
--.*: 0491a000 uxtb z0\.s, p0/m, z0\.s
--.*: 0491a001 uxtb z1\.s, p0/m, z0\.s
--.*: 0491a001 uxtb z1\.s, p0/m, z0\.s
--.*: 0491a01f uxtb z31\.s, p0/m, z0\.s
--.*: 0491a01f uxtb z31\.s, p0/m, z0\.s
--.*: 0491a800 uxtb z0\.s, p2/m, z0\.s
--.*: 0491a800 uxtb z0\.s, p2/m, z0\.s
--.*: 0491bc00 uxtb z0\.s, p7/m, z0\.s
--.*: 0491bc00 uxtb z0\.s, p7/m, z0\.s
--.*: 0491a060 uxtb z0\.s, p0/m, z3\.s
--.*: 0491a060 uxtb z0\.s, p0/m, z3\.s
--.*: 0491a3e0 uxtb z0\.s, p0/m, z31\.s
--.*: 0491a3e0 uxtb z0\.s, p0/m, z31\.s
--.*: 04d1a000 uxtb z0\.d, p0/m, z0\.d
--.*: 04d1a000 uxtb z0\.d, p0/m, z0\.d
--.*: 04d1a001 uxtb z1\.d, p0/m, z0\.d
--.*: 04d1a001 uxtb z1\.d, p0/m, z0\.d
--.*: 04d1a01f uxtb z31\.d, p0/m, z0\.d
--.*: 04d1a01f uxtb z31\.d, p0/m, z0\.d
--.*: 04d1a800 uxtb z0\.d, p2/m, z0\.d
--.*: 04d1a800 uxtb z0\.d, p2/m, z0\.d
--.*: 04d1bc00 uxtb z0\.d, p7/m, z0\.d
--.*: 04d1bc00 uxtb z0\.d, p7/m, z0\.d
--.*: 04d1a060 uxtb z0\.d, p0/m, z3\.d
--.*: 04d1a060 uxtb z0\.d, p0/m, z3\.d
--.*: 04d1a3e0 uxtb z0\.d, p0/m, z31\.d
--.*: 04d1a3e0 uxtb z0\.d, p0/m, z31\.d
--.*: 0493a000 uxth z0\.s, p0/m, z0\.s
--.*: 0493a000 uxth z0\.s, p0/m, z0\.s
--.*: 0493a001 uxth z1\.s, p0/m, z0\.s
--.*: 0493a001 uxth z1\.s, p0/m, z0\.s
--.*: 0493a01f uxth z31\.s, p0/m, z0\.s
--.*: 0493a01f uxth z31\.s, p0/m, z0\.s
--.*: 0493a800 uxth z0\.s, p2/m, z0\.s
--.*: 0493a800 uxth z0\.s, p2/m, z0\.s
--.*: 0493bc00 uxth z0\.s, p7/m, z0\.s
--.*: 0493bc00 uxth z0\.s, p7/m, z0\.s
--.*: 0493a060 uxth z0\.s, p0/m, z3\.s
--.*: 0493a060 uxth z0\.s, p0/m, z3\.s
--.*: 0493a3e0 uxth z0\.s, p0/m, z31\.s
--.*: 0493a3e0 uxth z0\.s, p0/m, z31\.s
--.*: 04d3a000 uxth z0\.d, p0/m, z0\.d
--.*: 04d3a000 uxth z0\.d, p0/m, z0\.d
--.*: 04d3a001 uxth z1\.d, p0/m, z0\.d
--.*: 04d3a001 uxth z1\.d, p0/m, z0\.d
--.*: 04d3a01f uxth z31\.d, p0/m, z0\.d
--.*: 04d3a01f uxth z31\.d, p0/m, z0\.d
--.*: 04d3a800 uxth z0\.d, p2/m, z0\.d
--.*: 04d3a800 uxth z0\.d, p2/m, z0\.d
--.*: 04d3bc00 uxth z0\.d, p7/m, z0\.d
--.*: 04d3bc00 uxth z0\.d, p7/m, z0\.d
--.*: 04d3a060 uxth z0\.d, p0/m, z3\.d
--.*: 04d3a060 uxth z0\.d, p0/m, z3\.d
--.*: 04d3a3e0 uxth z0\.d, p0/m, z31\.d
--.*: 04d3a3e0 uxth z0\.d, p0/m, z31\.d
--.*: 04d5a000 uxtw z0\.d, p0/m, z0\.d
--.*: 04d5a000 uxtw z0\.d, p0/m, z0\.d
--.*: 04d5a001 uxtw z1\.d, p0/m, z0\.d
--.*: 04d5a001 uxtw z1\.d, p0/m, z0\.d
--.*: 04d5a01f uxtw z31\.d, p0/m, z0\.d
--.*: 04d5a01f uxtw z31\.d, p0/m, z0\.d
--.*: 04d5a800 uxtw z0\.d, p2/m, z0\.d
--.*: 04d5a800 uxtw z0\.d, p2/m, z0\.d
--.*: 04d5bc00 uxtw z0\.d, p7/m, z0\.d
--.*: 04d5bc00 uxtw z0\.d, p7/m, z0\.d
--.*: 04d5a060 uxtw z0\.d, p0/m, z3\.d
--.*: 04d5a060 uxtw z0\.d, p0/m, z3\.d
--.*: 04d5a3e0 uxtw z0\.d, p0/m, z31\.d
--.*: 04d5a3e0 uxtw z0\.d, p0/m, z31\.d
--.*: 05204800 uzp1 p0\.b, p0\.b, p0\.b
--.*: 05204800 uzp1 p0\.b, p0\.b, p0\.b
--.*: 05204801 uzp1 p1\.b, p0\.b, p0\.b
--.*: 05204801 uzp1 p1\.b, p0\.b, p0\.b
--.*: 0520480f uzp1 p15\.b, p0\.b, p0\.b
--.*: 0520480f uzp1 p15\.b, p0\.b, p0\.b
--.*: 05204840 uzp1 p0\.b, p2\.b, p0\.b
--.*: 05204840 uzp1 p0\.b, p2\.b, p0\.b
--.*: 052049e0 uzp1 p0\.b, p15\.b, p0\.b
--.*: 052049e0 uzp1 p0\.b, p15\.b, p0\.b
--.*: 05234800 uzp1 p0\.b, p0\.b, p3\.b
--.*: 05234800 uzp1 p0\.b, p0\.b, p3\.b
--.*: 052f4800 uzp1 p0\.b, p0\.b, p15\.b
--.*: 052f4800 uzp1 p0\.b, p0\.b, p15\.b
--.*: 05604800 uzp1 p0\.h, p0\.h, p0\.h
--.*: 05604800 uzp1 p0\.h, p0\.h, p0\.h
--.*: 05604801 uzp1 p1\.h, p0\.h, p0\.h
--.*: 05604801 uzp1 p1\.h, p0\.h, p0\.h
--.*: 0560480f uzp1 p15\.h, p0\.h, p0\.h
--.*: 0560480f uzp1 p15\.h, p0\.h, p0\.h
--.*: 05604840 uzp1 p0\.h, p2\.h, p0\.h
--.*: 05604840 uzp1 p0\.h, p2\.h, p0\.h
--.*: 056049e0 uzp1 p0\.h, p15\.h, p0\.h
--.*: 056049e0 uzp1 p0\.h, p15\.h, p0\.h
--.*: 05634800 uzp1 p0\.h, p0\.h, p3\.h
--.*: 05634800 uzp1 p0\.h, p0\.h, p3\.h
--.*: 056f4800 uzp1 p0\.h, p0\.h, p15\.h
--.*: 056f4800 uzp1 p0\.h, p0\.h, p15\.h
--.*: 05a04800 uzp1 p0\.s, p0\.s, p0\.s
--.*: 05a04800 uzp1 p0\.s, p0\.s, p0\.s
--.*: 05a04801 uzp1 p1\.s, p0\.s, p0\.s
--.*: 05a04801 uzp1 p1\.s, p0\.s, p0\.s
--.*: 05a0480f uzp1 p15\.s, p0\.s, p0\.s
--.*: 05a0480f uzp1 p15\.s, p0\.s, p0\.s
--.*: 05a04840 uzp1 p0\.s, p2\.s, p0\.s
--.*: 05a04840 uzp1 p0\.s, p2\.s, p0\.s
--.*: 05a049e0 uzp1 p0\.s, p15\.s, p0\.s
--.*: 05a049e0 uzp1 p0\.s, p15\.s, p0\.s
--.*: 05a34800 uzp1 p0\.s, p0\.s, p3\.s
--.*: 05a34800 uzp1 p0\.s, p0\.s, p3\.s
--.*: 05af4800 uzp1 p0\.s, p0\.s, p15\.s
--.*: 05af4800 uzp1 p0\.s, p0\.s, p15\.s
--.*: 05e04800 uzp1 p0\.d, p0\.d, p0\.d
--.*: 05e04800 uzp1 p0\.d, p0\.d, p0\.d
--.*: 05e04801 uzp1 p1\.d, p0\.d, p0\.d
--.*: 05e04801 uzp1 p1\.d, p0\.d, p0\.d
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--.*: 05a34c00 uzp2 p0\.s, p0\.s, p3\.s
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--.*: 25a00c40 whilelo p0\.s, w2, w0
--.*: 25a00fe0 whilelo p0\.s, wzr, w0
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--.*: 25a30c00 whilelo p0\.s, w0, w3
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--.*: 25bf0c00 whilelo p0\.s, w0, wzr
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--.*: 257f1c10 whilels p0\.h, x0, xzr
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--.*: 25a01c10 whilels p0\.s, x0, x0
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--.*: 25a01c50 whilels p0\.s, x2, x0
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--.*: 25a31c10 whilels p0\.s, x0, x3
--.*: 25a31c10 whilels p0\.s, x0, x3
--.*: 25bf1c10 whilels p0\.s, x0, xzr
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--.*: 0560601f zip1 z31\.h, z0\.h, z0\.h
--.*: 0560601f zip1 z31\.h, z0\.h, z0\.h
--.*: 05606040 zip1 z0\.h, z2\.h, z0\.h
--.*: 05606040 zip1 z0\.h, z2\.h, z0\.h
--.*: 056063e0 zip1 z0\.h, z31\.h, z0\.h
--.*: 056063e0 zip1 z0\.h, z31\.h, z0\.h
--.*: 05636000 zip1 z0\.h, z0\.h, z3\.h
--.*: 05636000 zip1 z0\.h, z0\.h, z3\.h
--.*: 057f6000 zip1 z0\.h, z0\.h, z31\.h
--.*: 057f6000 zip1 z0\.h, z0\.h, z31\.h
--.*: 05a06000 zip1 z0\.s, z0\.s, z0\.s
--.*: 05a06000 zip1 z0\.s, z0\.s, z0\.s
--.*: 05a06001 zip1 z1\.s, z0\.s, z0\.s
--.*: 05a06001 zip1 z1\.s, z0\.s, z0\.s
--.*: 05a0601f zip1 z31\.s, z0\.s, z0\.s
--.*: 05a0601f zip1 z31\.s, z0\.s, z0\.s
--.*: 05a06040 zip1 z0\.s, z2\.s, z0\.s
--.*: 05a06040 zip1 z0\.s, z2\.s, z0\.s
--.*: 05a063e0 zip1 z0\.s, z31\.s, z0\.s
--.*: 05a063e0 zip1 z0\.s, z31\.s, z0\.s
--.*: 05a36000 zip1 z0\.s, z0\.s, z3\.s
--.*: 05a36000 zip1 z0\.s, z0\.s, z3\.s
--.*: 05bf6000 zip1 z0\.s, z0\.s, z31\.s
--.*: 05bf6000 zip1 z0\.s, z0\.s, z31\.s
--.*: 05e06000 zip1 z0\.d, z0\.d, z0\.d
--.*: 05e06000 zip1 z0\.d, z0\.d, z0\.d
--.*: 05e06001 zip1 z1\.d, z0\.d, z0\.d
--.*: 05e06001 zip1 z1\.d, z0\.d, z0\.d
--.*: 05e0601f zip1 z31\.d, z0\.d, z0\.d
--.*: 05e0601f zip1 z31\.d, z0\.d, z0\.d
--.*: 05e06040 zip1 z0\.d, z2\.d, z0\.d
--.*: 05e06040 zip1 z0\.d, z2\.d, z0\.d
--.*: 05e063e0 zip1 z0\.d, z31\.d, z0\.d
--.*: 05e063e0 zip1 z0\.d, z31\.d, z0\.d
--.*: 05e36000 zip1 z0\.d, z0\.d, z3\.d
--.*: 05e36000 zip1 z0\.d, z0\.d, z3\.d
--.*: 05ff6000 zip1 z0\.d, z0\.d, z31\.d
--.*: 05ff6000 zip1 z0\.d, z0\.d, z31\.d
--.*: 05204400 zip2 p0\.b, p0\.b, p0\.b
--.*: 05204400 zip2 p0\.b, p0\.b, p0\.b
--.*: 05204401 zip2 p1\.b, p0\.b, p0\.b
--.*: 05204401 zip2 p1\.b, p0\.b, p0\.b
--.*: 0520440f zip2 p15\.b, p0\.b, p0\.b
--.*: 0520440f zip2 p15\.b, p0\.b, p0\.b
--.*: 05204440 zip2 p0\.b, p2\.b, p0\.b
--.*: 05204440 zip2 p0\.b, p2\.b, p0\.b
--.*: 052045e0 zip2 p0\.b, p15\.b, p0\.b
--.*: 052045e0 zip2 p0\.b, p15\.b, p0\.b
--.*: 05234400 zip2 p0\.b, p0\.b, p3\.b
--.*: 05234400 zip2 p0\.b, p0\.b, p3\.b
--.*: 052f4400 zip2 p0\.b, p0\.b, p15\.b
--.*: 052f4400 zip2 p0\.b, p0\.b, p15\.b
--.*: 05604400 zip2 p0\.h, p0\.h, p0\.h
--.*: 05604400 zip2 p0\.h, p0\.h, p0\.h
--.*: 05604401 zip2 p1\.h, p0\.h, p0\.h
--.*: 05604401 zip2 p1\.h, p0\.h, p0\.h
--.*: 0560440f zip2 p15\.h, p0\.h, p0\.h
--.*: 0560440f zip2 p15\.h, p0\.h, p0\.h
--.*: 05604440 zip2 p0\.h, p2\.h, p0\.h
--.*: 05604440 zip2 p0\.h, p2\.h, p0\.h
--.*: 056045e0 zip2 p0\.h, p15\.h, p0\.h
--.*: 056045e0 zip2 p0\.h, p15\.h, p0\.h
--.*: 05634400 zip2 p0\.h, p0\.h, p3\.h
--.*: 05634400 zip2 p0\.h, p0\.h, p3\.h
--.*: 056f4400 zip2 p0\.h, p0\.h, p15\.h
--.*: 056f4400 zip2 p0\.h, p0\.h, p15\.h
--.*: 05a04400 zip2 p0\.s, p0\.s, p0\.s
--.*: 05a04400 zip2 p0\.s, p0\.s, p0\.s
--.*: 05a04401 zip2 p1\.s, p0\.s, p0\.s
--.*: 05a04401 zip2 p1\.s, p0\.s, p0\.s
--.*: 05a0440f zip2 p15\.s, p0\.s, p0\.s
--.*: 05a0440f zip2 p15\.s, p0\.s, p0\.s
--.*: 05a04440 zip2 p0\.s, p2\.s, p0\.s
--.*: 05a04440 zip2 p0\.s, p2\.s, p0\.s
--.*: 05a045e0 zip2 p0\.s, p15\.s, p0\.s
--.*: 05a045e0 zip2 p0\.s, p15\.s, p0\.s
--.*: 05a34400 zip2 p0\.s, p0\.s, p3\.s
--.*: 05a34400 zip2 p0\.s, p0\.s, p3\.s
--.*: 05af4400 zip2 p0\.s, p0\.s, p15\.s
--.*: 05af4400 zip2 p0\.s, p0\.s, p15\.s
--.*: 05e04400 zip2 p0\.d, p0\.d, p0\.d
--.*: 05e04400 zip2 p0\.d, p0\.d, p0\.d
--.*: 05e04401 zip2 p1\.d, p0\.d, p0\.d
--.*: 05e04401 zip2 p1\.d, p0\.d, p0\.d
--.*: 05e0440f zip2 p15\.d, p0\.d, p0\.d
--.*: 05e0440f zip2 p15\.d, p0\.d, p0\.d
--.*: 05e04440 zip2 p0\.d, p2\.d, p0\.d
--.*: 05e04440 zip2 p0\.d, p2\.d, p0\.d
--.*: 05e045e0 zip2 p0\.d, p15\.d, p0\.d
--.*: 05e045e0 zip2 p0\.d, p15\.d, p0\.d
--.*: 05e34400 zip2 p0\.d, p0\.d, p3\.d
--.*: 05e34400 zip2 p0\.d, p0\.d, p3\.d
--.*: 05ef4400 zip2 p0\.d, p0\.d, p15\.d
--.*: 05ef4400 zip2 p0\.d, p0\.d, p15\.d
--.*: 05206400 zip2 z0\.b, z0\.b, z0\.b
--.*: 05206400 zip2 z0\.b, z0\.b, z0\.b
--.*: 05206401 zip2 z1\.b, z0\.b, z0\.b
--.*: 05206401 zip2 z1\.b, z0\.b, z0\.b
--.*: 0520641f zip2 z31\.b, z0\.b, z0\.b
--.*: 0520641f zip2 z31\.b, z0\.b, z0\.b
--.*: 05206440 zip2 z0\.b, z2\.b, z0\.b
--.*: 05206440 zip2 z0\.b, z2\.b, z0\.b
--.*: 052067e0 zip2 z0\.b, z31\.b, z0\.b
--.*: 052067e0 zip2 z0\.b, z31\.b, z0\.b
--.*: 05236400 zip2 z0\.b, z0\.b, z3\.b
--.*: 05236400 zip2 z0\.b, z0\.b, z3\.b
--.*: 053f6400 zip2 z0\.b, z0\.b, z31\.b
--.*: 053f6400 zip2 z0\.b, z0\.b, z31\.b
--.*: 05606400 zip2 z0\.h, z0\.h, z0\.h
--.*: 05606400 zip2 z0\.h, z0\.h, z0\.h
--.*: 05606401 zip2 z1\.h, z0\.h, z0\.h
--.*: 05606401 zip2 z1\.h, z0\.h, z0\.h
--.*: 0560641f zip2 z31\.h, z0\.h, z0\.h
--.*: 0560641f zip2 z31\.h, z0\.h, z0\.h
--.*: 05606440 zip2 z0\.h, z2\.h, z0\.h
--.*: 05606440 zip2 z0\.h, z2\.h, z0\.h
--.*: 056067e0 zip2 z0\.h, z31\.h, z0\.h
--.*: 056067e0 zip2 z0\.h, z31\.h, z0\.h
--.*: 05636400 zip2 z0\.h, z0\.h, z3\.h
--.*: 05636400 zip2 z0\.h, z0\.h, z3\.h
--.*: 057f6400 zip2 z0\.h, z0\.h, z31\.h
--.*: 057f6400 zip2 z0\.h, z0\.h, z31\.h
--.*: 05a06400 zip2 z0\.s, z0\.s, z0\.s
--.*: 05a06400 zip2 z0\.s, z0\.s, z0\.s
--.*: 05a06401 zip2 z1\.s, z0\.s, z0\.s
--.*: 05a06401 zip2 z1\.s, z0\.s, z0\.s
--.*: 05a0641f zip2 z31\.s, z0\.s, z0\.s
--.*: 05a0641f zip2 z31\.s, z0\.s, z0\.s
--.*: 05a06440 zip2 z0\.s, z2\.s, z0\.s
--.*: 05a06440 zip2 z0\.s, z2\.s, z0\.s
--.*: 05a067e0 zip2 z0\.s, z31\.s, z0\.s
--.*: 05a067e0 zip2 z0\.s, z31\.s, z0\.s
--.*: 05a36400 zip2 z0\.s, z0\.s, z3\.s
--.*: 05a36400 zip2 z0\.s, z0\.s, z3\.s
--.*: 05bf6400 zip2 z0\.s, z0\.s, z31\.s
--.*: 05bf6400 zip2 z0\.s, z0\.s, z31\.s
--.*: 05e06400 zip2 z0\.d, z0\.d, z0\.d
--.*: 05e06400 zip2 z0\.d, z0\.d, z0\.d
--.*: 05e06401 zip2 z1\.d, z0\.d, z0\.d
--.*: 05e06401 zip2 z1\.d, z0\.d, z0\.d
--.*: 05e0641f zip2 z31\.d, z0\.d, z0\.d
--.*: 05e0641f zip2 z31\.d, z0\.d, z0\.d
--.*: 05e06440 zip2 z0\.d, z2\.d, z0\.d
--.*: 05e06440 zip2 z0\.d, z2\.d, z0\.d
--.*: 05e067e0 zip2 z0\.d, z31\.d, z0\.d
--.*: 05e067e0 zip2 z0\.d, z31\.d, z0\.d
--.*: 05e36400 zip2 z0\.d, z0\.d, z3\.d
--.*: 05e36400 zip2 z0\.d, z0\.d, z3\.d
--.*: 05ff6400 zip2 z0\.d, z0\.d, z31\.d
--.*: 05ff6400 zip2 z0\.d, z0\.d, z31\.d
--.*: 05800000 and z0\.s, z0\.s, #0x1
--.*: 05800000 and z0\.s, z0\.s, #0x1
--.*: 05800000 and z0\.s, z0\.s, #0x1
--.*: 05800001 and z1\.s, z1\.s, #0x1
--.*: 05800001 and z1\.s, z1\.s, #0x1
--.*: 05800001 and z1\.s, z1\.s, #0x1
--.*: 0580001f and z31\.s, z31\.s, #0x1
--.*: 0580001f and z31\.s, z31\.s, #0x1
--.*: 0580001f and z31\.s, z31\.s, #0x1
--.*: 05800002 and z2\.s, z2\.s, #0x1
--.*: 05800002 and z2\.s, z2\.s, #0x1
--.*: 05800002 and z2\.s, z2\.s, #0x1
--.*: 058000c0 and z0\.s, z0\.s, #0x7f
--.*: 058000c0 and z0\.s, z0\.s, #0x7f
--.*: 058000c0 and z0\.s, z0\.s, #0x7f
--.*: 058003c0 and z0\.s, z0\.s, #0x7fffffff
--.*: 058003c0 and z0\.s, z0\.s, #0x7fffffff
--.*: 058003c0 and z0\.s, z0\.s, #0x7fffffff
--.*: 05800400 and z0\.h, z0\.h, #0x1
--.*: 05800400 and z0\.h, z0\.h, #0x1
--.*: 05800400 and z0\.h, z0\.h, #0x1
--.*: 05800400 and z0\.h, z0\.h, #0x1
--.*: 058005c0 and z0\.h, z0\.h, #0x7fff
--.*: 058005c0 and z0\.h, z0\.h, #0x7fff
--.*: 058005c0 and z0\.h, z0\.h, #0x7fff
--.*: 058005c0 and z0\.h, z0\.h, #0x7fff
--.*: 05800600 and z0\.b, z0\.b, #0x1
--.*: 05800600 and z0\.b, z0\.b, #0x1
--.*: 05800600 and z0\.b, z0\.b, #0x1
--.*: 05800600 and z0\.b, z0\.b, #0x1
--.*: 05800600 and z0\.b, z0\.b, #0x1
--.*: 05800780 and z0\.b, z0\.b, #0x55
--.*: 05800780 and z0\.b, z0\.b, #0x55
--.*: 05800780 and z0\.b, z0\.b, #0x55
--.*: 05800780 and z0\.b, z0\.b, #0x55
--.*: 05800780 and z0\.b, z0\.b, #0x55
--.*: 05800800 and z0\.s, z0\.s, #0x80000000
--.*: 05800800 and z0\.s, z0\.s, #0x80000000
--.*: 05800800 and z0\.s, z0\.s, #0x80000000
--.*: 05800bc0 and z0\.s, z0\.s, #0xbfffffff
--.*: 05800bc0 and z0\.s, z0\.s, #0xbfffffff
--.*: 05800bc0 and z0\.s, z0\.s, #0xbfffffff
--.*: 05800c00 and z0\.h, z0\.h, #0x8000
--.*: 05800c00 and z0\.h, z0\.h, #0x8000
--.*: 05800c00 and z0\.h, z0\.h, #0x8000
--.*: 05800c00 and z0\.h, z0\.h, #0x8000
--.*: 05800ec0 and z0\.b, z0\.b, #0xbf
--.*: 05800ec0 and z0\.b, z0\.b, #0xbf
--.*: 05800ec0 and z0\.b, z0\.b, #0xbf
--.*: 05800ec0 and z0\.b, z0\.b, #0xbf
--.*: 05800ec0 and z0\.b, z0\.b, #0xbf
--.*: 05801e80 and z0\.b, z0\.b, #0xe3
--.*: 05801e80 and z0\.b, z0\.b, #0xe3
--.*: 05801e80 and z0\.b, z0\.b, #0xe3
--.*: 05801e80 and z0\.b, z0\.b, #0xe3
--.*: 05801e80 and z0\.b, z0\.b, #0xe3
--.*: 0580bbc0 and z0\.s, z0\.s, #0xfffffeff
--.*: 0580bbc0 and z0\.s, z0\.s, #0xfffffeff
--.*: 0580bbc0 and z0\.s, z0\.s, #0xfffffeff
--.*: 0583ffc0 and z0\.d, z0\.d, #0xfffffffffffffffe
--.*: 0583ffc0 and z0\.d, z0\.d, #0xfffffffffffffffe
--.*: 24008000 cmpge p0\.b, p0/z, z0\.b, z0\.b
--.*: 24008000 cmpge p0\.b, p0/z, z0\.b, z0\.b
--.*: 24008001 cmpge p1\.b, p0/z, z0\.b, z0\.b
--.*: 24008001 cmpge p1\.b, p0/z, z0\.b, z0\.b
--.*: 2400800f cmpge p15\.b, p0/z, z0\.b, z0\.b
--.*: 2400800f cmpge p15\.b, p0/z, z0\.b, z0\.b
--.*: 24008800 cmpge p0\.b, p2/z, z0\.b, z0\.b
--.*: 24008800 cmpge p0\.b, p2/z, z0\.b, z0\.b
--.*: 24009c00 cmpge p0\.b, p7/z, z0\.b, z0\.b
--.*: 24009c00 cmpge p0\.b, p7/z, z0\.b, z0\.b
--.*: 24038000 cmpge p0\.b, p0/z, z0\.b, z3\.b
--.*: 24038000 cmpge p0\.b, p0/z, z0\.b, z3\.b
--.*: 241f8000 cmpge p0\.b, p0/z, z0\.b, z31\.b
--.*: 241f8000 cmpge p0\.b, p0/z, z0\.b, z31\.b
--.*: 24008080 cmpge p0\.b, p0/z, z4\.b, z0\.b
--.*: 24008080 cmpge p0\.b, p0/z, z4\.b, z0\.b
--.*: 240083e0 cmpge p0\.b, p0/z, z31\.b, z0\.b
--.*: 240083e0 cmpge p0\.b, p0/z, z31\.b, z0\.b
--.*: 24408000 cmpge p0\.h, p0/z, z0\.h, z0\.h
--.*: 24408000 cmpge p0\.h, p0/z, z0\.h, z0\.h
--.*: 24408001 cmpge p1\.h, p0/z, z0\.h, z0\.h
--.*: 24408001 cmpge p1\.h, p0/z, z0\.h, z0\.h
--.*: 2440800f cmpge p15\.h, p0/z, z0\.h, z0\.h
--.*: 2440800f cmpge p15\.h, p0/z, z0\.h, z0\.h
--.*: 24408800 cmpge p0\.h, p2/z, z0\.h, z0\.h
--.*: 24408800 cmpge p0\.h, p2/z, z0\.h, z0\.h
--.*: 24409c00 cmpge p0\.h, p7/z, z0\.h, z0\.h
--.*: 24409c00 cmpge p0\.h, p7/z, z0\.h, z0\.h
--.*: 24438000 cmpge p0\.h, p0/z, z0\.h, z3\.h
--.*: 24438000 cmpge p0\.h, p0/z, z0\.h, z3\.h
--.*: 245f8000 cmpge p0\.h, p0/z, z0\.h, z31\.h
--.*: 245f8000 cmpge p0\.h, p0/z, z0\.h, z31\.h
--.*: 24408080 cmpge p0\.h, p0/z, z4\.h, z0\.h
--.*: 24408080 cmpge p0\.h, p0/z, z4\.h, z0\.h
--.*: 244083e0 cmpge p0\.h, p0/z, z31\.h, z0\.h
--.*: 244083e0 cmpge p0\.h, p0/z, z31\.h, z0\.h
--.*: 24808000 cmpge p0\.s, p0/z, z0\.s, z0\.s
--.*: 24808000 cmpge p0\.s, p0/z, z0\.s, z0\.s
--.*: 24808001 cmpge p1\.s, p0/z, z0\.s, z0\.s
--.*: 24808001 cmpge p1\.s, p0/z, z0\.s, z0\.s
--.*: 2480800f cmpge p15\.s, p0/z, z0\.s, z0\.s
--.*: 2480800f cmpge p15\.s, p0/z, z0\.s, z0\.s
--.*: 24808800 cmpge p0\.s, p2/z, z0\.s, z0\.s
--.*: 24808800 cmpge p0\.s, p2/z, z0\.s, z0\.s
--.*: 24809c00 cmpge p0\.s, p7/z, z0\.s, z0\.s
--.*: 24809c00 cmpge p0\.s, p7/z, z0\.s, z0\.s
--.*: 24838000 cmpge p0\.s, p0/z, z0\.s, z3\.s
--.*: 24838000 cmpge p0\.s, p0/z, z0\.s, z3\.s
--.*: 249f8000 cmpge p0\.s, p0/z, z0\.s, z31\.s
--.*: 249f8000 cmpge p0\.s, p0/z, z0\.s, z31\.s
--.*: 24808080 cmpge p0\.s, p0/z, z4\.s, z0\.s
--.*: 24808080 cmpge p0\.s, p0/z, z4\.s, z0\.s
--.*: 248083e0 cmpge p0\.s, p0/z, z31\.s, z0\.s
--.*: 248083e0 cmpge p0\.s, p0/z, z31\.s, z0\.s
--.*: 24c08000 cmpge p0\.d, p0/z, z0\.d, z0\.d
--.*: 24c08000 cmpge p0\.d, p0/z, z0\.d, z0\.d
--.*: 24c08001 cmpge p1\.d, p0/z, z0\.d, z0\.d
--.*: 24c08001 cmpge p1\.d, p0/z, z0\.d, z0\.d
--.*: 24c0800f cmpge p15\.d, p0/z, z0\.d, z0\.d
--.*: 24c0800f cmpge p15\.d, p0/z, z0\.d, z0\.d
--.*: 24c08800 cmpge p0\.d, p2/z, z0\.d, z0\.d
--.*: 24c08800 cmpge p0\.d, p2/z, z0\.d, z0\.d
--.*: 24c09c00 cmpge p0\.d, p7/z, z0\.d, z0\.d
--.*: 24c09c00 cmpge p0\.d, p7/z, z0\.d, z0\.d
--.*: 24c38000 cmpge p0\.d, p0/z, z0\.d, z3\.d
--.*: 24c38000 cmpge p0\.d, p0/z, z0\.d, z3\.d
--.*: 24df8000 cmpge p0\.d, p0/z, z0\.d, z31\.d
--.*: 24df8000 cmpge p0\.d, p0/z, z0\.d, z31\.d
--.*: 24c08080 cmpge p0\.d, p0/z, z4\.d, z0\.d
--.*: 24c08080 cmpge p0\.d, p0/z, z4\.d, z0\.d
--.*: 24c083e0 cmpge p0\.d, p0/z, z31\.d, z0\.d
--.*: 24c083e0 cmpge p0\.d, p0/z, z31\.d, z0\.d
--.*: 24000010 cmphi p0\.b, p0/z, z0\.b, z0\.b
--.*: 24000010 cmphi p0\.b, p0/z, z0\.b, z0\.b
--.*: 24000011 cmphi p1\.b, p0/z, z0\.b, z0\.b
--.*: 24000011 cmphi p1\.b, p0/z, z0\.b, z0\.b
--.*: 2400001f cmphi p15\.b, p0/z, z0\.b, z0\.b
--.*: 2400001f cmphi p15\.b, p0/z, z0\.b, z0\.b
--.*: 24000810 cmphi p0\.b, p2/z, z0\.b, z0\.b
--.*: 24000810 cmphi p0\.b, p2/z, z0\.b, z0\.b
--.*: 24001c10 cmphi p0\.b, p7/z, z0\.b, z0\.b
--.*: 24001c10 cmphi p0\.b, p7/z, z0\.b, z0\.b
--.*: 24030010 cmphi p0\.b, p0/z, z0\.b, z3\.b
--.*: 24030010 cmphi p0\.b, p0/z, z0\.b, z3\.b
--.*: 241f0010 cmphi p0\.b, p0/z, z0\.b, z31\.b
--.*: 241f0010 cmphi p0\.b, p0/z, z0\.b, z31\.b
--.*: 24000090 cmphi p0\.b, p0/z, z4\.b, z0\.b
--.*: 24000090 cmphi p0\.b, p0/z, z4\.b, z0\.b
--.*: 240003f0 cmphi p0\.b, p0/z, z31\.b, z0\.b
--.*: 240003f0 cmphi p0\.b, p0/z, z31\.b, z0\.b
--.*: 24400010 cmphi p0\.h, p0/z, z0\.h, z0\.h
--.*: 24400010 cmphi p0\.h, p0/z, z0\.h, z0\.h
--.*: 24400011 cmphi p1\.h, p0/z, z0\.h, z0\.h
--.*: 24400011 cmphi p1\.h, p0/z, z0\.h, z0\.h
--.*: 2440001f cmphi p15\.h, p0/z, z0\.h, z0\.h
--.*: 2440001f cmphi p15\.h, p0/z, z0\.h, z0\.h
--.*: 24400810 cmphi p0\.h, p2/z, z0\.h, z0\.h
--.*: 24400810 cmphi p0\.h, p2/z, z0\.h, z0\.h
--.*: 24401c10 cmphi p0\.h, p7/z, z0\.h, z0\.h
--.*: 24401c10 cmphi p0\.h, p7/z, z0\.h, z0\.h
--.*: 24430010 cmphi p0\.h, p0/z, z0\.h, z3\.h
--.*: 24430010 cmphi p0\.h, p0/z, z0\.h, z3\.h
--.*: 245f0010 cmphi p0\.h, p0/z, z0\.h, z31\.h
--.*: 245f0010 cmphi p0\.h, p0/z, z0\.h, z31\.h
--.*: 24400090 cmphi p0\.h, p0/z, z4\.h, z0\.h
--.*: 24400090 cmphi p0\.h, p0/z, z4\.h, z0\.h
--.*: 244003f0 cmphi p0\.h, p0/z, z31\.h, z0\.h
--.*: 244003f0 cmphi p0\.h, p0/z, z31\.h, z0\.h
--.*: 24800010 cmphi p0\.s, p0/z, z0\.s, z0\.s
--.*: 24800010 cmphi p0\.s, p0/z, z0\.s, z0\.s
--.*: 24800011 cmphi p1\.s, p0/z, z0\.s, z0\.s
--.*: 24800011 cmphi p1\.s, p0/z, z0\.s, z0\.s
--.*: 2480001f cmphi p15\.s, p0/z, z0\.s, z0\.s
--.*: 2480001f cmphi p15\.s, p0/z, z0\.s, z0\.s
--.*: 24800810 cmphi p0\.s, p2/z, z0\.s, z0\.s
--.*: 24800810 cmphi p0\.s, p2/z, z0\.s, z0\.s
--.*: 24801c10 cmphi p0\.s, p7/z, z0\.s, z0\.s
--.*: 24801c10 cmphi p0\.s, p7/z, z0\.s, z0\.s
--.*: 24830010 cmphi p0\.s, p0/z, z0\.s, z3\.s
--.*: 24830010 cmphi p0\.s, p0/z, z0\.s, z3\.s
--.*: 249f0010 cmphi p0\.s, p0/z, z0\.s, z31\.s
--.*: 249f0010 cmphi p0\.s, p0/z, z0\.s, z31\.s
--.*: 24800090 cmphi p0\.s, p0/z, z4\.s, z0\.s
--.*: 24800090 cmphi p0\.s, p0/z, z4\.s, z0\.s
--.*: 248003f0 cmphi p0\.s, p0/z, z31\.s, z0\.s
--.*: 248003f0 cmphi p0\.s, p0/z, z31\.s, z0\.s
--.*: 24c00010 cmphi p0\.d, p0/z, z0\.d, z0\.d
--.*: 24c00010 cmphi p0\.d, p0/z, z0\.d, z0\.d
--.*: 24c00011 cmphi p1\.d, p0/z, z0\.d, z0\.d
--.*: 24c00011 cmphi p1\.d, p0/z, z0\.d, z0\.d
--.*: 24c0001f cmphi p15\.d, p0/z, z0\.d, z0\.d
--.*: 24c0001f cmphi p15\.d, p0/z, z0\.d, z0\.d
--.*: 24c00810 cmphi p0\.d, p2/z, z0\.d, z0\.d
--.*: 24c00810 cmphi p0\.d, p2/z, z0\.d, z0\.d
--.*: 24c01c10 cmphi p0\.d, p7/z, z0\.d, z0\.d
--.*: 24c01c10 cmphi p0\.d, p7/z, z0\.d, z0\.d
--.*: 24c30010 cmphi p0\.d, p0/z, z0\.d, z3\.d
--.*: 24c30010 cmphi p0\.d, p0/z, z0\.d, z3\.d
--.*: 24df0010 cmphi p0\.d, p0/z, z0\.d, z31\.d
--.*: 24df0010 cmphi p0\.d, p0/z, z0\.d, z31\.d
--.*: 24c00090 cmphi p0\.d, p0/z, z4\.d, z0\.d
--.*: 24c00090 cmphi p0\.d, p0/z, z4\.d, z0\.d
--.*: 24c003f0 cmphi p0\.d, p0/z, z31\.d, z0\.d
--.*: 24c003f0 cmphi p0\.d, p0/z, z31\.d, z0\.d
--.*: 24000000 cmphs p0\.b, p0/z, z0\.b, z0\.b
--.*: 24000000 cmphs p0\.b, p0/z, z0\.b, z0\.b
--.*: 24000001 cmphs p1\.b, p0/z, z0\.b, z0\.b
--.*: 24000001 cmphs p1\.b, p0/z, z0\.b, z0\.b
--.*: 2400000f cmphs p15\.b, p0/z, z0\.b, z0\.b
--.*: 2400000f cmphs p15\.b, p0/z, z0\.b, z0\.b
--.*: 24000800 cmphs p0\.b, p2/z, z0\.b, z0\.b
--.*: 24000800 cmphs p0\.b, p2/z, z0\.b, z0\.b
--.*: 24001c00 cmphs p0\.b, p7/z, z0\.b, z0\.b
--.*: 24001c00 cmphs p0\.b, p7/z, z0\.b, z0\.b
--.*: 24030000 cmphs p0\.b, p0/z, z0\.b, z3\.b
--.*: 24030000 cmphs p0\.b, p0/z, z0\.b, z3\.b
--.*: 241f0000 cmphs p0\.b, p0/z, z0\.b, z31\.b
--.*: 241f0000 cmphs p0\.b, p0/z, z0\.b, z31\.b
--.*: 24000080 cmphs p0\.b, p0/z, z4\.b, z0\.b
--.*: 24000080 cmphs p0\.b, p0/z, z4\.b, z0\.b
--.*: 240003e0 cmphs p0\.b, p0/z, z31\.b, z0\.b
--.*: 240003e0 cmphs p0\.b, p0/z, z31\.b, z0\.b
--.*: 24400000 cmphs p0\.h, p0/z, z0\.h, z0\.h
--.*: 24400000 cmphs p0\.h, p0/z, z0\.h, z0\.h
--.*: 24400001 cmphs p1\.h, p0/z, z0\.h, z0\.h
--.*: 24400001 cmphs p1\.h, p0/z, z0\.h, z0\.h
--.*: 2440000f cmphs p15\.h, p0/z, z0\.h, z0\.h
--.*: 2440000f cmphs p15\.h, p0/z, z0\.h, z0\.h
--.*: 24400800 cmphs p0\.h, p2/z, z0\.h, z0\.h
--.*: 24400800 cmphs p0\.h, p2/z, z0\.h, z0\.h
--.*: 24401c00 cmphs p0\.h, p7/z, z0\.h, z0\.h
--.*: 24401c00 cmphs p0\.h, p7/z, z0\.h, z0\.h
--.*: 24430000 cmphs p0\.h, p0/z, z0\.h, z3\.h
--.*: 24430000 cmphs p0\.h, p0/z, z0\.h, z3\.h
--.*: 245f0000 cmphs p0\.h, p0/z, z0\.h, z31\.h
--.*: 245f0000 cmphs p0\.h, p0/z, z0\.h, z31\.h
--.*: 24400080 cmphs p0\.h, p0/z, z4\.h, z0\.h
--.*: 24400080 cmphs p0\.h, p0/z, z4\.h, z0\.h
--.*: 244003e0 cmphs p0\.h, p0/z, z31\.h, z0\.h
--.*: 244003e0 cmphs p0\.h, p0/z, z31\.h, z0\.h
--.*: 24800000 cmphs p0\.s, p0/z, z0\.s, z0\.s
--.*: 24800000 cmphs p0\.s, p0/z, z0\.s, z0\.s
--.*: 24800001 cmphs p1\.s, p0/z, z0\.s, z0\.s
--.*: 24800001 cmphs p1\.s, p0/z, z0\.s, z0\.s
--.*: 2480000f cmphs p15\.s, p0/z, z0\.s, z0\.s
--.*: 2480000f cmphs p15\.s, p0/z, z0\.s, z0\.s
--.*: 24800800 cmphs p0\.s, p2/z, z0\.s, z0\.s
--.*: 24800800 cmphs p0\.s, p2/z, z0\.s, z0\.s
--.*: 24801c00 cmphs p0\.s, p7/z, z0\.s, z0\.s
--.*: 24801c00 cmphs p0\.s, p7/z, z0\.s, z0\.s
--.*: 24830000 cmphs p0\.s, p0/z, z0\.s, z3\.s
--.*: 24830000 cmphs p0\.s, p0/z, z0\.s, z3\.s
--.*: 249f0000 cmphs p0\.s, p0/z, z0\.s, z31\.s
--.*: 249f0000 cmphs p0\.s, p0/z, z0\.s, z31\.s
--.*: 24800080 cmphs p0\.s, p0/z, z4\.s, z0\.s
--.*: 24800080 cmphs p0\.s, p0/z, z4\.s, z0\.s
--.*: 248003e0 cmphs p0\.s, p0/z, z31\.s, z0\.s
--.*: 248003e0 cmphs p0\.s, p0/z, z31\.s, z0\.s
--.*: 24c00000 cmphs p0\.d, p0/z, z0\.d, z0\.d
--.*: 24c00000 cmphs p0\.d, p0/z, z0\.d, z0\.d
--.*: 24c00001 cmphs p1\.d, p0/z, z0\.d, z0\.d
--.*: 24c00001 cmphs p1\.d, p0/z, z0\.d, z0\.d
--.*: 24c0000f cmphs p15\.d, p0/z, z0\.d, z0\.d
--.*: 24c0000f cmphs p15\.d, p0/z, z0\.d, z0\.d
--.*: 24c00800 cmphs p0\.d, p2/z, z0\.d, z0\.d
--.*: 24c00800 cmphs p0\.d, p2/z, z0\.d, z0\.d
--.*: 24c01c00 cmphs p0\.d, p7/z, z0\.d, z0\.d
--.*: 24c01c00 cmphs p0\.d, p7/z, z0\.d, z0\.d
--.*: 24c30000 cmphs p0\.d, p0/z, z0\.d, z3\.d
--.*: 24c30000 cmphs p0\.d, p0/z, z0\.d, z3\.d
--.*: 24df0000 cmphs p0\.d, p0/z, z0\.d, z31\.d
--.*: 24df0000 cmphs p0\.d, p0/z, z0\.d, z31\.d
--.*: 24c00080 cmphs p0\.d, p0/z, z4\.d, z0\.d
--.*: 24c00080 cmphs p0\.d, p0/z, z4\.d, z0\.d
--.*: 24c003e0 cmphs p0\.d, p0/z, z31\.d, z0\.d
--.*: 24c003e0 cmphs p0\.d, p0/z, z31\.d, z0\.d
--.*: 24008010 cmpgt p0\.b, p0/z, z0\.b, z0\.b
--.*: 24008010 cmpgt p0\.b, p0/z, z0\.b, z0\.b
--.*: 24008011 cmpgt p1\.b, p0/z, z0\.b, z0\.b
--.*: 24008011 cmpgt p1\.b, p0/z, z0\.b, z0\.b
--.*: 2400801f cmpgt p15\.b, p0/z, z0\.b, z0\.b
--.*: 2400801f cmpgt p15\.b, p0/z, z0\.b, z0\.b
--.*: 24008810 cmpgt p0\.b, p2/z, z0\.b, z0\.b
--.*: 24008810 cmpgt p0\.b, p2/z, z0\.b, z0\.b
--.*: 24009c10 cmpgt p0\.b, p7/z, z0\.b, z0\.b
--.*: 24009c10 cmpgt p0\.b, p7/z, z0\.b, z0\.b
--.*: 24038010 cmpgt p0\.b, p0/z, z0\.b, z3\.b
--.*: 24038010 cmpgt p0\.b, p0/z, z0\.b, z3\.b
--.*: 241f8010 cmpgt p0\.b, p0/z, z0\.b, z31\.b
--.*: 241f8010 cmpgt p0\.b, p0/z, z0\.b, z31\.b
--.*: 24008090 cmpgt p0\.b, p0/z, z4\.b, z0\.b
--.*: 24008090 cmpgt p0\.b, p0/z, z4\.b, z0\.b
--.*: 240083f0 cmpgt p0\.b, p0/z, z31\.b, z0\.b
--.*: 240083f0 cmpgt p0\.b, p0/z, z31\.b, z0\.b
--.*: 24408010 cmpgt p0\.h, p0/z, z0\.h, z0\.h
--.*: 24408010 cmpgt p0\.h, p0/z, z0\.h, z0\.h
--.*: 24408011 cmpgt p1\.h, p0/z, z0\.h, z0\.h
--.*: 24408011 cmpgt p1\.h, p0/z, z0\.h, z0\.h
--.*: 2440801f cmpgt p15\.h, p0/z, z0\.h, z0\.h
--.*: 2440801f cmpgt p15\.h, p0/z, z0\.h, z0\.h
--.*: 24408810 cmpgt p0\.h, p2/z, z0\.h, z0\.h
--.*: 24408810 cmpgt p0\.h, p2/z, z0\.h, z0\.h
--.*: 24409c10 cmpgt p0\.h, p7/z, z0\.h, z0\.h
--.*: 24409c10 cmpgt p0\.h, p7/z, z0\.h, z0\.h
--.*: 24438010 cmpgt p0\.h, p0/z, z0\.h, z3\.h
--.*: 24438010 cmpgt p0\.h, p0/z, z0\.h, z3\.h
--.*: 245f8010 cmpgt p0\.h, p0/z, z0\.h, z31\.h
--.*: 245f8010 cmpgt p0\.h, p0/z, z0\.h, z31\.h
--.*: 24408090 cmpgt p0\.h, p0/z, z4\.h, z0\.h
--.*: 24408090 cmpgt p0\.h, p0/z, z4\.h, z0\.h
--.*: 244083f0 cmpgt p0\.h, p0/z, z31\.h, z0\.h
--.*: 244083f0 cmpgt p0\.h, p0/z, z31\.h, z0\.h
--.*: 24808010 cmpgt p0\.s, p0/z, z0\.s, z0\.s
--.*: 24808010 cmpgt p0\.s, p0/z, z0\.s, z0\.s
--.*: 24808011 cmpgt p1\.s, p0/z, z0\.s, z0\.s
--.*: 24808011 cmpgt p1\.s, p0/z, z0\.s, z0\.s
--.*: 2480801f cmpgt p15\.s, p0/z, z0\.s, z0\.s
--.*: 2480801f cmpgt p15\.s, p0/z, z0\.s, z0\.s
--.*: 24808810 cmpgt p0\.s, p2/z, z0\.s, z0\.s
--.*: 24808810 cmpgt p0\.s, p2/z, z0\.s, z0\.s
--.*: 24809c10 cmpgt p0\.s, p7/z, z0\.s, z0\.s
--.*: 24809c10 cmpgt p0\.s, p7/z, z0\.s, z0\.s
--.*: 24838010 cmpgt p0\.s, p0/z, z0\.s, z3\.s
--.*: 24838010 cmpgt p0\.s, p0/z, z0\.s, z3\.s
--.*: 249f8010 cmpgt p0\.s, p0/z, z0\.s, z31\.s
--.*: 249f8010 cmpgt p0\.s, p0/z, z0\.s, z31\.s
--.*: 24808090 cmpgt p0\.s, p0/z, z4\.s, z0\.s
--.*: 24808090 cmpgt p0\.s, p0/z, z4\.s, z0\.s
--.*: 248083f0 cmpgt p0\.s, p0/z, z31\.s, z0\.s
--.*: 248083f0 cmpgt p0\.s, p0/z, z31\.s, z0\.s
--.*: 24c08010 cmpgt p0\.d, p0/z, z0\.d, z0\.d
--.*: 24c08010 cmpgt p0\.d, p0/z, z0\.d, z0\.d
--.*: 24c08011 cmpgt p1\.d, p0/z, z0\.d, z0\.d
--.*: 24c08011 cmpgt p1\.d, p0/z, z0\.d, z0\.d
--.*: 24c0801f cmpgt p15\.d, p0/z, z0\.d, z0\.d
--.*: 24c0801f cmpgt p15\.d, p0/z, z0\.d, z0\.d
--.*: 24c08810 cmpgt p0\.d, p2/z, z0\.d, z0\.d
--.*: 24c08810 cmpgt p0\.d, p2/z, z0\.d, z0\.d
--.*: 24c09c10 cmpgt p0\.d, p7/z, z0\.d, z0\.d
--.*: 24c09c10 cmpgt p0\.d, p7/z, z0\.d, z0\.d
--.*: 24c38010 cmpgt p0\.d, p0/z, z0\.d, z3\.d
--.*: 24c38010 cmpgt p0\.d, p0/z, z0\.d, z3\.d
--.*: 24df8010 cmpgt p0\.d, p0/z, z0\.d, z31\.d
--.*: 24df8010 cmpgt p0\.d, p0/z, z0\.d, z31\.d
--.*: 24c08090 cmpgt p0\.d, p0/z, z4\.d, z0\.d
--.*: 24c08090 cmpgt p0\.d, p0/z, z4\.d, z0\.d
--.*: 24c083f0 cmpgt p0\.d, p0/z, z31\.d, z0\.d
--.*: 24c083f0 cmpgt p0\.d, p0/z, z31\.d, z0\.d
--.*: 05400000 eor z0\.s, z0\.s, #0x1
--.*: 05400000 eor z0\.s, z0\.s, #0x1
--.*: 05400000 eor z0\.s, z0\.s, #0x1
--.*: 05400001 eor z1\.s, z1\.s, #0x1
--.*: 05400001 eor z1\.s, z1\.s, #0x1
--.*: 05400001 eor z1\.s, z1\.s, #0x1
--.*: 0540001f eor z31\.s, z31\.s, #0x1
--.*: 0540001f eor z31\.s, z31\.s, #0x1
--.*: 0540001f eor z31\.s, z31\.s, #0x1
--.*: 05400002 eor z2\.s, z2\.s, #0x1
--.*: 05400002 eor z2\.s, z2\.s, #0x1
--.*: 05400002 eor z2\.s, z2\.s, #0x1
--.*: 054000c0 eor z0\.s, z0\.s, #0x7f
--.*: 054000c0 eor z0\.s, z0\.s, #0x7f
--.*: 054000c0 eor z0\.s, z0\.s, #0x7f
--.*: 054003c0 eor z0\.s, z0\.s, #0x7fffffff
--.*: 054003c0 eor z0\.s, z0\.s, #0x7fffffff
--.*: 054003c0 eor z0\.s, z0\.s, #0x7fffffff
--.*: 05400400 eor z0\.h, z0\.h, #0x1
--.*: 05400400 eor z0\.h, z0\.h, #0x1
--.*: 05400400 eor z0\.h, z0\.h, #0x1
--.*: 05400400 eor z0\.h, z0\.h, #0x1
--.*: 054005c0 eor z0\.h, z0\.h, #0x7fff
--.*: 054005c0 eor z0\.h, z0\.h, #0x7fff
--.*: 054005c0 eor z0\.h, z0\.h, #0x7fff
--.*: 054005c0 eor z0\.h, z0\.h, #0x7fff
--.*: 05400600 eor z0\.b, z0\.b, #0x1
--.*: 05400600 eor z0\.b, z0\.b, #0x1
--.*: 05400600 eor z0\.b, z0\.b, #0x1
--.*: 05400600 eor z0\.b, z0\.b, #0x1
--.*: 05400600 eor z0\.b, z0\.b, #0x1
--.*: 05400780 eor z0\.b, z0\.b, #0x55
--.*: 05400780 eor z0\.b, z0\.b, #0x55
--.*: 05400780 eor z0\.b, z0\.b, #0x55
--.*: 05400780 eor z0\.b, z0\.b, #0x55
--.*: 05400780 eor z0\.b, z0\.b, #0x55
--.*: 05400800 eor z0\.s, z0\.s, #0x80000000
--.*: 05400800 eor z0\.s, z0\.s, #0x80000000
--.*: 05400800 eor z0\.s, z0\.s, #0x80000000
--.*: 05400bc0 eor z0\.s, z0\.s, #0xbfffffff
--.*: 05400bc0 eor z0\.s, z0\.s, #0xbfffffff
--.*: 05400bc0 eor z0\.s, z0\.s, #0xbfffffff
--.*: 05400c00 eor z0\.h, z0\.h, #0x8000
--.*: 05400c00 eor z0\.h, z0\.h, #0x8000
--.*: 05400c00 eor z0\.h, z0\.h, #0x8000
--.*: 05400c00 eor z0\.h, z0\.h, #0x8000
--.*: 05400ec0 eor z0\.b, z0\.b, #0xbf
--.*: 05400ec0 eor z0\.b, z0\.b, #0xbf
--.*: 05400ec0 eor z0\.b, z0\.b, #0xbf
--.*: 05400ec0 eor z0\.b, z0\.b, #0xbf
--.*: 05400ec0 eor z0\.b, z0\.b, #0xbf
--.*: 05401e80 eor z0\.b, z0\.b, #0xe3
--.*: 05401e80 eor z0\.b, z0\.b, #0xe3
--.*: 05401e80 eor z0\.b, z0\.b, #0xe3
--.*: 05401e80 eor z0\.b, z0\.b, #0xe3
--.*: 05401e80 eor z0\.b, z0\.b, #0xe3
--.*: 0540bbc0 eor z0\.s, z0\.s, #0xfffffeff
--.*: 0540bbc0 eor z0\.s, z0\.s, #0xfffffeff
--.*: 0540bbc0 eor z0\.s, z0\.s, #0xfffffeff
--.*: 0543ffc0 eor z0\.d, z0\.d, #0xfffffffffffffffe
--.*: 0543ffc0 eor z0\.d, z0\.d, #0xfffffffffffffffe
--.*: 6540c010 facge p0\.h, p0/z, z0\.h, z0\.h
--.*: 6540c010 facge p0\.h, p0/z, z0\.h, z0\.h
--.*: 6540c011 facge p1\.h, p0/z, z0\.h, z0\.h
--.*: 6540c011 facge p1\.h, p0/z, z0\.h, z0\.h
--.*: 6540c01f facge p15\.h, p0/z, z0\.h, z0\.h
--.*: 6540c01f facge p15\.h, p0/z, z0\.h, z0\.h
--.*: 6540c810 facge p0\.h, p2/z, z0\.h, z0\.h
--.*: 6540c810 facge p0\.h, p2/z, z0\.h, z0\.h
--.*: 6540dc10 facge p0\.h, p7/z, z0\.h, z0\.h
--.*: 6540dc10 facge p0\.h, p7/z, z0\.h, z0\.h
--.*: 6543c010 facge p0\.h, p0/z, z0\.h, z3\.h
--.*: 6543c010 facge p0\.h, p0/z, z0\.h, z3\.h
--.*: 655fc010 facge p0\.h, p0/z, z0\.h, z31\.h
--.*: 655fc010 facge p0\.h, p0/z, z0\.h, z31\.h
--.*: 6540c090 facge p0\.h, p0/z, z4\.h, z0\.h
--.*: 6540c090 facge p0\.h, p0/z, z4\.h, z0\.h
--.*: 6540c3f0 facge p0\.h, p0/z, z31\.h, z0\.h
--.*: 6540c3f0 facge p0\.h, p0/z, z31\.h, z0\.h
--.*: 6580c010 facge p0\.s, p0/z, z0\.s, z0\.s
--.*: 6580c010 facge p0\.s, p0/z, z0\.s, z0\.s
--.*: 6580c011 facge p1\.s, p0/z, z0\.s, z0\.s
--.*: 6580c011 facge p1\.s, p0/z, z0\.s, z0\.s
--.*: 6580c01f facge p15\.s, p0/z, z0\.s, z0\.s
--.*: 6580c01f facge p15\.s, p0/z, z0\.s, z0\.s
--.*: 6580c810 facge p0\.s, p2/z, z0\.s, z0\.s
--.*: 6580c810 facge p0\.s, p2/z, z0\.s, z0\.s
--.*: 6580dc10 facge p0\.s, p7/z, z0\.s, z0\.s
--.*: 6580dc10 facge p0\.s, p7/z, z0\.s, z0\.s
--.*: 6583c010 facge p0\.s, p0/z, z0\.s, z3\.s
--.*: 6583c010 facge p0\.s, p0/z, z0\.s, z3\.s
--.*: 659fc010 facge p0\.s, p0/z, z0\.s, z31\.s
--.*: 659fc010 facge p0\.s, p0/z, z0\.s, z31\.s
--.*: 6580c090 facge p0\.s, p0/z, z4\.s, z0\.s
--.*: 6580c090 facge p0\.s, p0/z, z4\.s, z0\.s
--.*: 6580c3f0 facge p0\.s, p0/z, z31\.s, z0\.s
--.*: 6580c3f0 facge p0\.s, p0/z, z31\.s, z0\.s
--.*: 65c0c010 facge p0\.d, p0/z, z0\.d, z0\.d
--.*: 65c0c010 facge p0\.d, p0/z, z0\.d, z0\.d
--.*: 65c0c011 facge p1\.d, p0/z, z0\.d, z0\.d
--.*: 65c0c011 facge p1\.d, p0/z, z0\.d, z0\.d
--.*: 65c0c01f facge p15\.d, p0/z, z0\.d, z0\.d
--.*: 65c0c01f facge p15\.d, p0/z, z0\.d, z0\.d
--.*: 65c0c810 facge p0\.d, p2/z, z0\.d, z0\.d
--.*: 65c0c810 facge p0\.d, p2/z, z0\.d, z0\.d
--.*: 65c0dc10 facge p0\.d, p7/z, z0\.d, z0\.d
--.*: 65c0dc10 facge p0\.d, p7/z, z0\.d, z0\.d
--.*: 65c3c010 facge p0\.d, p0/z, z0\.d, z3\.d
--.*: 65c3c010 facge p0\.d, p0/z, z0\.d, z3\.d
--.*: 65dfc010 facge p0\.d, p0/z, z0\.d, z31\.d
--.*: 65dfc010 facge p0\.d, p0/z, z0\.d, z31\.d
--.*: 65c0c090 facge p0\.d, p0/z, z4\.d, z0\.d
--.*: 65c0c090 facge p0\.d, p0/z, z4\.d, z0\.d
--.*: 65c0c3f0 facge p0\.d, p0/z, z31\.d, z0\.d
--.*: 65c0c3f0 facge p0\.d, p0/z, z31\.d, z0\.d
--.*: 6540e010 facgt p0\.h, p0/z, z0\.h, z0\.h
--.*: 6540e010 facgt p0\.h, p0/z, z0\.h, z0\.h
--.*: 6540e011 facgt p1\.h, p0/z, z0\.h, z0\.h
--.*: 6540e011 facgt p1\.h, p0/z, z0\.h, z0\.h
--.*: 6540e01f facgt p15\.h, p0/z, z0\.h, z0\.h
--.*: 6540e01f facgt p15\.h, p0/z, z0\.h, z0\.h
--.*: 6540e810 facgt p0\.h, p2/z, z0\.h, z0\.h
--.*: 6540e810 facgt p0\.h, p2/z, z0\.h, z0\.h
--.*: 6540fc10 facgt p0\.h, p7/z, z0\.h, z0\.h
--.*: 6540fc10 facgt p0\.h, p7/z, z0\.h, z0\.h
--.*: 6543e010 facgt p0\.h, p0/z, z0\.h, z3\.h
--.*: 6543e010 facgt p0\.h, p0/z, z0\.h, z3\.h
--.*: 655fe010 facgt p0\.h, p0/z, z0\.h, z31\.h
--.*: 655fe010 facgt p0\.h, p0/z, z0\.h, z31\.h
--.*: 6540e090 facgt p0\.h, p0/z, z4\.h, z0\.h
--.*: 6540e090 facgt p0\.h, p0/z, z4\.h, z0\.h
--.*: 6540e3f0 facgt p0\.h, p0/z, z31\.h, z0\.h
--.*: 6540e3f0 facgt p0\.h, p0/z, z31\.h, z0\.h
--.*: 6580e010 facgt p0\.s, p0/z, z0\.s, z0\.s
--.*: 6580e010 facgt p0\.s, p0/z, z0\.s, z0\.s
--.*: 6580e011 facgt p1\.s, p0/z, z0\.s, z0\.s
--.*: 6580e011 facgt p1\.s, p0/z, z0\.s, z0\.s
--.*: 6580e01f facgt p15\.s, p0/z, z0\.s, z0\.s
--.*: 6580e01f facgt p15\.s, p0/z, z0\.s, z0\.s
--.*: 6580e810 facgt p0\.s, p2/z, z0\.s, z0\.s
--.*: 6580e810 facgt p0\.s, p2/z, z0\.s, z0\.s
--.*: 6580fc10 facgt p0\.s, p7/z, z0\.s, z0\.s
--.*: 6580fc10 facgt p0\.s, p7/z, z0\.s, z0\.s
--.*: 6583e010 facgt p0\.s, p0/z, z0\.s, z3\.s
--.*: 6583e010 facgt p0\.s, p0/z, z0\.s, z3\.s
--.*: 659fe010 facgt p0\.s, p0/z, z0\.s, z31\.s
--.*: 659fe010 facgt p0\.s, p0/z, z0\.s, z31\.s
--.*: 6580e090 facgt p0\.s, p0/z, z4\.s, z0\.s
--.*: 6580e090 facgt p0\.s, p0/z, z4\.s, z0\.s
--.*: 6580e3f0 facgt p0\.s, p0/z, z31\.s, z0\.s
--.*: 6580e3f0 facgt p0\.s, p0/z, z31\.s, z0\.s
--.*: 65c0e010 facgt p0\.d, p0/z, z0\.d, z0\.d
--.*: 65c0e010 facgt p0\.d, p0/z, z0\.d, z0\.d
--.*: 65c0e011 facgt p1\.d, p0/z, z0\.d, z0\.d
--.*: 65c0e011 facgt p1\.d, p0/z, z0\.d, z0\.d
--.*: 65c0e01f facgt p15\.d, p0/z, z0\.d, z0\.d
--.*: 65c0e01f facgt p15\.d, p0/z, z0\.d, z0\.d
--.*: 65c0e810 facgt p0\.d, p2/z, z0\.d, z0\.d
--.*: 65c0e810 facgt p0\.d, p2/z, z0\.d, z0\.d
--.*: 65c0fc10 facgt p0\.d, p7/z, z0\.d, z0\.d
--.*: 65c0fc10 facgt p0\.d, p7/z, z0\.d, z0\.d
--.*: 65c3e010 facgt p0\.d, p0/z, z0\.d, z3\.d
--.*: 65c3e010 facgt p0\.d, p0/z, z0\.d, z3\.d
--.*: 65dfe010 facgt p0\.d, p0/z, z0\.d, z31\.d
--.*: 65dfe010 facgt p0\.d, p0/z, z0\.d, z31\.d
--.*: 65c0e090 facgt p0\.d, p0/z, z4\.d, z0\.d
--.*: 65c0e090 facgt p0\.d, p0/z, z4\.d, z0\.d
--.*: 65c0e3f0 facgt p0\.d, p0/z, z31\.d, z0\.d
--.*: 65c0e3f0 facgt p0\.d, p0/z, z31\.d, z0\.d
--.*: 65404000 fcmge p0\.h, p0/z, z0\.h, z0\.h
--.*: 65404000 fcmge p0\.h, p0/z, z0\.h, z0\.h
--.*: 65404001 fcmge p1\.h, p0/z, z0\.h, z0\.h
--.*: 65404001 fcmge p1\.h, p0/z, z0\.h, z0\.h
--.*: 6540400f fcmge p15\.h, p0/z, z0\.h, z0\.h
--.*: 6540400f fcmge p15\.h, p0/z, z0\.h, z0\.h
--.*: 65404800 fcmge p0\.h, p2/z, z0\.h, z0\.h
--.*: 65404800 fcmge p0\.h, p2/z, z0\.h, z0\.h
--.*: 65405c00 fcmge p0\.h, p7/z, z0\.h, z0\.h
--.*: 65405c00 fcmge p0\.h, p7/z, z0\.h, z0\.h
--.*: 65434000 fcmge p0\.h, p0/z, z0\.h, z3\.h
--.*: 65434000 fcmge p0\.h, p0/z, z0\.h, z3\.h
--.*: 655f4000 fcmge p0\.h, p0/z, z0\.h, z31\.h
--.*: 655f4000 fcmge p0\.h, p0/z, z0\.h, z31\.h
--.*: 65404080 fcmge p0\.h, p0/z, z4\.h, z0\.h
--.*: 65404080 fcmge p0\.h, p0/z, z4\.h, z0\.h
--.*: 654043e0 fcmge p0\.h, p0/z, z31\.h, z0\.h
--.*: 654043e0 fcmge p0\.h, p0/z, z31\.h, z0\.h
--.*: 65804000 fcmge p0\.s, p0/z, z0\.s, z0\.s
--.*: 65804000 fcmge p0\.s, p0/z, z0\.s, z0\.s
--.*: 65804001 fcmge p1\.s, p0/z, z0\.s, z0\.s
--.*: 65804001 fcmge p1\.s, p0/z, z0\.s, z0\.s
--.*: 6580400f fcmge p15\.s, p0/z, z0\.s, z0\.s
--.*: 6580400f fcmge p15\.s, p0/z, z0\.s, z0\.s
--.*: 65804800 fcmge p0\.s, p2/z, z0\.s, z0\.s
--.*: 65804800 fcmge p0\.s, p2/z, z0\.s, z0\.s
--.*: 65805c00 fcmge p0\.s, p7/z, z0\.s, z0\.s
--.*: 65805c00 fcmge p0\.s, p7/z, z0\.s, z0\.s
--.*: 65834000 fcmge p0\.s, p0/z, z0\.s, z3\.s
--.*: 65834000 fcmge p0\.s, p0/z, z0\.s, z3\.s
--.*: 659f4000 fcmge p0\.s, p0/z, z0\.s, z31\.s
--.*: 659f4000 fcmge p0\.s, p0/z, z0\.s, z31\.s
--.*: 65804080 fcmge p0\.s, p0/z, z4\.s, z0\.s
--.*: 65804080 fcmge p0\.s, p0/z, z4\.s, z0\.s
--.*: 658043e0 fcmge p0\.s, p0/z, z31\.s, z0\.s
--.*: 658043e0 fcmge p0\.s, p0/z, z31\.s, z0\.s
--.*: 65c04000 fcmge p0\.d, p0/z, z0\.d, z0\.d
--.*: 65c04000 fcmge p0\.d, p0/z, z0\.d, z0\.d
--.*: 65c04001 fcmge p1\.d, p0/z, z0\.d, z0\.d
--.*: 65c04001 fcmge p1\.d, p0/z, z0\.d, z0\.d
--.*: 65c0400f fcmge p15\.d, p0/z, z0\.d, z0\.d
--.*: 65c0400f fcmge p15\.d, p0/z, z0\.d, z0\.d
--.*: 65c04800 fcmge p0\.d, p2/z, z0\.d, z0\.d
--.*: 65c04800 fcmge p0\.d, p2/z, z0\.d, z0\.d
--.*: 65c05c00 fcmge p0\.d, p7/z, z0\.d, z0\.d
--.*: 65c05c00 fcmge p0\.d, p7/z, z0\.d, z0\.d
--.*: 65c34000 fcmge p0\.d, p0/z, z0\.d, z3\.d
--.*: 65c34000 fcmge p0\.d, p0/z, z0\.d, z3\.d
--.*: 65df4000 fcmge p0\.d, p0/z, z0\.d, z31\.d
--.*: 65df4000 fcmge p0\.d, p0/z, z0\.d, z31\.d
--.*: 65c04080 fcmge p0\.d, p0/z, z4\.d, z0\.d
--.*: 65c04080 fcmge p0\.d, p0/z, z4\.d, z0\.d
--.*: 65c043e0 fcmge p0\.d, p0/z, z31\.d, z0\.d
--.*: 65c043e0 fcmge p0\.d, p0/z, z31\.d, z0\.d
--.*: 65404010 fcmgt p0\.h, p0/z, z0\.h, z0\.h
--.*: 65404010 fcmgt p0\.h, p0/z, z0\.h, z0\.h
--.*: 65404011 fcmgt p1\.h, p0/z, z0\.h, z0\.h
--.*: 65404011 fcmgt p1\.h, p0/z, z0\.h, z0\.h
--.*: 6540401f fcmgt p15\.h, p0/z, z0\.h, z0\.h
--.*: 6540401f fcmgt p15\.h, p0/z, z0\.h, z0\.h
--.*: 65404810 fcmgt p0\.h, p2/z, z0\.h, z0\.h
--.*: 65404810 fcmgt p0\.h, p2/z, z0\.h, z0\.h
--.*: 65405c10 fcmgt p0\.h, p7/z, z0\.h, z0\.h
--.*: 65405c10 fcmgt p0\.h, p7/z, z0\.h, z0\.h
--.*: 65434010 fcmgt p0\.h, p0/z, z0\.h, z3\.h
--.*: 65434010 fcmgt p0\.h, p0/z, z0\.h, z3\.h
--.*: 655f4010 fcmgt p0\.h, p0/z, z0\.h, z31\.h
--.*: 655f4010 fcmgt p0\.h, p0/z, z0\.h, z31\.h
--.*: 65404090 fcmgt p0\.h, p0/z, z4\.h, z0\.h
--.*: 65404090 fcmgt p0\.h, p0/z, z4\.h, z0\.h
--.*: 654043f0 fcmgt p0\.h, p0/z, z31\.h, z0\.h
--.*: 654043f0 fcmgt p0\.h, p0/z, z31\.h, z0\.h
--.*: 65804010 fcmgt p0\.s, p0/z, z0\.s, z0\.s
--.*: 65804010 fcmgt p0\.s, p0/z, z0\.s, z0\.s
--.*: 65804011 fcmgt p1\.s, p0/z, z0\.s, z0\.s
--.*: 65804011 fcmgt p1\.s, p0/z, z0\.s, z0\.s
--.*: 6580401f fcmgt p15\.s, p0/z, z0\.s, z0\.s
--.*: 6580401f fcmgt p15\.s, p0/z, z0\.s, z0\.s
--.*: 65804810 fcmgt p0\.s, p2/z, z0\.s, z0\.s
--.*: 65804810 fcmgt p0\.s, p2/z, z0\.s, z0\.s
--.*: 65805c10 fcmgt p0\.s, p7/z, z0\.s, z0\.s
--.*: 65805c10 fcmgt p0\.s, p7/z, z0\.s, z0\.s
--.*: 65834010 fcmgt p0\.s, p0/z, z0\.s, z3\.s
--.*: 65834010 fcmgt p0\.s, p0/z, z0\.s, z3\.s
--.*: 659f4010 fcmgt p0\.s, p0/z, z0\.s, z31\.s
--.*: 659f4010 fcmgt p0\.s, p0/z, z0\.s, z31\.s
--.*: 65804090 fcmgt p0\.s, p0/z, z4\.s, z0\.s
--.*: 65804090 fcmgt p0\.s, p0/z, z4\.s, z0\.s
--.*: 658043f0 fcmgt p0\.s, p0/z, z31\.s, z0\.s
--.*: 658043f0 fcmgt p0\.s, p0/z, z31\.s, z0\.s
--.*: 65c04010 fcmgt p0\.d, p0/z, z0\.d, z0\.d
--.*: 65c04010 fcmgt p0\.d, p0/z, z0\.d, z0\.d
--.*: 65c04011 fcmgt p1\.d, p0/z, z0\.d, z0\.d
--.*: 65c04011 fcmgt p1\.d, p0/z, z0\.d, z0\.d
--.*: 65c0401f fcmgt p15\.d, p0/z, z0\.d, z0\.d
--.*: 65c0401f fcmgt p15\.d, p0/z, z0\.d, z0\.d
--.*: 65c04810 fcmgt p0\.d, p2/z, z0\.d, z0\.d
--.*: 65c04810 fcmgt p0\.d, p2/z, z0\.d, z0\.d
--.*: 65c05c10 fcmgt p0\.d, p7/z, z0\.d, z0\.d
--.*: 65c05c10 fcmgt p0\.d, p7/z, z0\.d, z0\.d
--.*: 65c34010 fcmgt p0\.d, p0/z, z0\.d, z3\.d
--.*: 65c34010 fcmgt p0\.d, p0/z, z0\.d, z3\.d
--.*: 65df4010 fcmgt p0\.d, p0/z, z0\.d, z31\.d
--.*: 65df4010 fcmgt p0\.d, p0/z, z0\.d, z31\.d
--.*: 65c04090 fcmgt p0\.d, p0/z, z4\.d, z0\.d
--.*: 65c04090 fcmgt p0\.d, p0/z, z4\.d, z0\.d
--.*: 65c043f0 fcmgt p0\.d, p0/z, z31\.d, z0\.d
--.*: 65c043f0 fcmgt p0\.d, p0/z, z31\.d, z0\.d
--.*: 2578c000 mov z0\.h, #0
--.*: 2578c000 mov z0\.h, #0
--.*: 2578c001 mov z1\.h, #0
--.*: 2578c001 mov z1\.h, #0
--.*: 2578c01f mov z31\.h, #0
--.*: 2578c01f mov z31\.h, #0
--.*: 25b8c000 mov z0\.s, #0
--.*: 25b8c000 mov z0\.s, #0
--.*: 25b8c001 mov z1\.s, #0
--.*: 25b8c001 mov z1\.s, #0
--.*: 25b8c01f mov z31\.s, #0
--.*: 25b8c01f mov z31\.s, #0
--.*: 25f8c000 mov z0\.d, #0
--.*: 25f8c000 mov z0\.d, #0
--.*: 25f8c001 mov z1\.d, #0
--.*: 25f8c001 mov z1\.d, #0
--.*: 25f8c01f mov z31\.d, #0
--.*: 25f8c01f mov z31\.d, #0
--.*: 05504000 mov z0\.h, p0/m, #0
--.*: 05504000 mov z0\.h, p0/m, #0
--.*: 05504001 mov z1\.h, p0/m, #0
--.*: 05504001 mov z1\.h, p0/m, #0
--.*: 0550401f mov z31\.h, p0/m, #0
--.*: 0550401f mov z31\.h, p0/m, #0
--.*: 05524000 mov z0\.h, p2/m, #0
--.*: 05524000 mov z0\.h, p2/m, #0
--.*: 055f4000 mov z0\.h, p15/m, #0
--.*: 055f4000 mov z0\.h, p15/m, #0
--.*: 05904000 mov z0\.s, p0/m, #0
--.*: 05904000 mov z0\.s, p0/m, #0
--.*: 05904001 mov z1\.s, p0/m, #0
--.*: 05904001 mov z1\.s, p0/m, #0
--.*: 0590401f mov z31\.s, p0/m, #0
--.*: 0590401f mov z31\.s, p0/m, #0
--.*: 05924000 mov z0\.s, p2/m, #0
--.*: 05924000 mov z0\.s, p2/m, #0
--.*: 059f4000 mov z0\.s, p15/m, #0
--.*: 059f4000 mov z0\.s, p15/m, #0
--.*: 05d04000 mov z0\.d, p0/m, #0
--.*: 05d04000 mov z0\.d, p0/m, #0
--.*: 05d04001 mov z1\.d, p0/m, #0
--.*: 05d04001 mov z1\.d, p0/m, #0
--.*: 05d0401f mov z31\.d, p0/m, #0
--.*: 05d0401f mov z31\.d, p0/m, #0
--.*: 05d24000 mov z0\.d, p2/m, #0
--.*: 05d24000 mov z0\.d, p2/m, #0
--.*: 05df4000 mov z0\.d, p15/m, #0
--.*: 05df4000 mov z0\.d, p15/m, #0
--.*: 05000000 orr z0\.s, z0\.s, #0x1
--.*: 05000000 orr z0\.s, z0\.s, #0x1
--.*: 05000000 orr z0\.s, z0\.s, #0x1
--.*: 05000001 orr z1\.s, z1\.s, #0x1
--.*: 05000001 orr z1\.s, z1\.s, #0x1
--.*: 05000001 orr z1\.s, z1\.s, #0x1
--.*: 0500001f orr z31\.s, z31\.s, #0x1
--.*: 0500001f orr z31\.s, z31\.s, #0x1
--.*: 0500001f orr z31\.s, z31\.s, #0x1
--.*: 05000002 orr z2\.s, z2\.s, #0x1
--.*: 05000002 orr z2\.s, z2\.s, #0x1
--.*: 05000002 orr z2\.s, z2\.s, #0x1
--.*: 050000c0 orr z0\.s, z0\.s, #0x7f
--.*: 050000c0 orr z0\.s, z0\.s, #0x7f
--.*: 050000c0 orr z0\.s, z0\.s, #0x7f
--.*: 050003c0 orr z0\.s, z0\.s, #0x7fffffff
--.*: 050003c0 orr z0\.s, z0\.s, #0x7fffffff
--.*: 050003c0 orr z0\.s, z0\.s, #0x7fffffff
--.*: 05000400 orr z0\.h, z0\.h, #0x1
--.*: 05000400 orr z0\.h, z0\.h, #0x1
--.*: 05000400 orr z0\.h, z0\.h, #0x1
--.*: 05000400 orr z0\.h, z0\.h, #0x1
--.*: 050005c0 orr z0\.h, z0\.h, #0x7fff
--.*: 050005c0 orr z0\.h, z0\.h, #0x7fff
--.*: 050005c0 orr z0\.h, z0\.h, #0x7fff
--.*: 050005c0 orr z0\.h, z0\.h, #0x7fff
--.*: 05000600 orr z0\.b, z0\.b, #0x1
--.*: 05000600 orr z0\.b, z0\.b, #0x1
--.*: 05000600 orr z0\.b, z0\.b, #0x1
--.*: 05000600 orr z0\.b, z0\.b, #0x1
--.*: 05000600 orr z0\.b, z0\.b, #0x1
--.*: 05000780 orr z0\.b, z0\.b, #0x55
--.*: 05000780 orr z0\.b, z0\.b, #0x55
--.*: 05000780 orr z0\.b, z0\.b, #0x55
--.*: 05000780 orr z0\.b, z0\.b, #0x55
--.*: 05000780 orr z0\.b, z0\.b, #0x55
--.*: 05000800 orr z0\.s, z0\.s, #0x80000000
--.*: 05000800 orr z0\.s, z0\.s, #0x80000000
--.*: 05000800 orr z0\.s, z0\.s, #0x80000000
--.*: 05000bc0 orr z0\.s, z0\.s, #0xbfffffff
--.*: 05000bc0 orr z0\.s, z0\.s, #0xbfffffff
--.*: 05000bc0 orr z0\.s, z0\.s, #0xbfffffff
--.*: 05000c00 orr z0\.h, z0\.h, #0x8000
--.*: 05000c00 orr z0\.h, z0\.h, #0x8000
--.*: 05000c00 orr z0\.h, z0\.h, #0x8000
--.*: 05000c00 orr z0\.h, z0\.h, #0x8000
--.*: 05000ec0 orr z0\.b, z0\.b, #0xbf
--.*: 05000ec0 orr z0\.b, z0\.b, #0xbf
--.*: 05000ec0 orr z0\.b, z0\.b, #0xbf
--.*: 05000ec0 orr z0\.b, z0\.b, #0xbf
--.*: 05000ec0 orr z0\.b, z0\.b, #0xbf
--.*: 05001e80 orr z0\.b, z0\.b, #0xe3
--.*: 05001e80 orr z0\.b, z0\.b, #0xe3
--.*: 05001e80 orr z0\.b, z0\.b, #0xe3
--.*: 05001e80 orr z0\.b, z0\.b, #0xe3
--.*: 05001e80 orr z0\.b, z0\.b, #0xe3
--.*: 0500bbc0 orr z0\.s, z0\.s, #0xfffffeff
--.*: 0500bbc0 orr z0\.s, z0\.s, #0xfffffeff
--.*: 0500bbc0 orr z0\.s, z0\.s, #0xfffffeff
--.*: 0503ffc0 orr z0\.d, z0\.d, #0xfffffffffffffffe
--.*: 0503ffc0 orr z0\.d, z0\.d, #0xfffffffffffffffe
--
--.*: 6ec3c441 fcmla v1\.2d, v2\.2d, v3\.2d, #0
--.*: 6ec3cc41 fcmla v1\.2d, v2\.2d, v3\.2d, #90
--.*: 6ec3d441 fcmla v1\.2d, v2\.2d, v3\.2d, #180
--.*: 6ec3dc41 fcmla v1\.2d, v2\.2d, v3\.2d, #270
--.*: 2e83cc41 fcmla v1\.2s, v2\.2s, v3\.2s, #90
--.*: 6e83cc41 fcmla v1\.4s, v2\.4s, v3\.4s, #90
--.*: 2e43cc41 fcmla v1\.4h, v2\.4h, v3\.4h, #90
--.*: 6e43cc41 fcmla v1\.8h, v2\.8h, v3\.8h, #90
--.*: 6f831041 fcmla v1\.4s, v2\.4s, v3\.s\[0\], #0
--.*: 6f833041 fcmla v1\.4s, v2\.4s, v3\.s\[0\], #90
--.*: 6f835041 fcmla v1\.4s, v2\.4s, v3\.s\[0\], #180
--.*: 6f837041 fcmla v1\.4s, v2\.4s, v3\.s\[0\], #270
--.*: 6f833841 fcmla v1\.4s, v2\.4s, v3\.s\[1\], #90
--.*: 2f433041 fcmla v1\.4h, v2\.4h, v3\.h\[0\], #90
--.*: 2f633041 fcmla v1\.4h, v2\.4h, v3\.h\[1\], #90
--.*: 6f433041 fcmla v1\.8h, v2\.8h, v3\.h\[0\], #90
--.*: 6f633041 fcmla v1\.8h, v2\.8h, v3\.h\[1\], #90
--.*: 6f433841 fcmla v1\.8h, v2\.8h, v3\.h\[2\], #90
--.*: 6f633841 fcmla v1\.8h, v2\.8h, v3\.h\[3\], #90
--.*: 6ec3e441 fcadd v1\.2d, v2\.2d, v3\.2d, #90
--.*: 6ec3f441 fcadd v1\.2d, v2\.2d, v3\.2d, #270
--.*: 2e83e441 fcadd v1\.2s, v2\.2s, v3\.2s, #90
--.*: 6e83e441 fcadd v1\.4s, v2\.4s, v3\.4s, #90
--.*: 2e43e441 fcadd v1\.4h, v2\.4h, v3\.4h, #90
--.*: 6e43e441 fcadd v1\.8h, v2\.8h, v3\.8h, #90
--.*: 4e63d441 fadd v1\.2d, v2\.2d, v3\.2d
--.*: 0e23d441 fadd v1\.2s, v2\.2s, v3\.2s
--.*: 4e23d441 fadd v1\.4s, v2\.4s, v3\.4s
--.*: 0e401400 fadd v0\.4h, v0\.4h, v0\.4h
--.*: 0e431441 fadd v1\.4h, v2\.4h, v3\.4h
--.*: 4e401400 fadd v0\.8h, v0\.8h, v0\.8h
--.*: 4e431441 fadd v1\.8h, v2\.8h, v3\.8h
-+[^:]+: 2579c000 fmov z0.h, #2.0+e\+00
-+[^:]+: 2579c000 fmov z0.h, #2.0+e\+00
-+[^:]+: 2579c001 fmov z1.h, #2.0+e\+00
-+[^:]+: 2579c001 fmov z1.h, #2.0+e\+00
-+[^:]+: 2579c01f fmov z31.h, #2.0+e\+00
-+[^:]+: 2579c01f fmov z31.h, #2.0+e\+00
-+[^:]+: 2579c600 fmov z0.h, #1.60+e\+01
-+[^:]+: 2579c600 fmov z0.h, #1.60+e\+01
-+[^:]+: 2579c900 fmov z0.h, #1.8750+e-01
-+[^:]+: 2579c900 fmov z0.h, #1.8750+e-01
-+[^:]+: 2579cfe0 fmov z0.h, #1.93750+e\+00
-+[^:]+: 2579cfe0 fmov z0.h, #1.93750+e\+00
-+[^:]+: 2579d100 fmov z0.h, #-3.0+e\+00
-+[^:]+: 2579d100 fmov z0.h, #-3.0+e\+00
-+[^:]+: 2579d800 fmov z0.h, #-1.250+e-01
-+[^:]+: 2579d800 fmov z0.h, #-1.250+e-01
-+[^:]+: 2579dfe0 fmov z0.h, #-1.93750+e\+00
-+[^:]+: 2579dfe0 fmov z0.h, #-1.93750+e\+00
-+[^:]+: 25b9c000 fmov z0.s, #2.0+e\+00
-+[^:]+: 25b9c000 fmov z0.s, #2.0+e\+00
-+[^:]+: 25b9c001 fmov z1.s, #2.0+e\+00
-+[^:]+: 25b9c001 fmov z1.s, #2.0+e\+00
-+[^:]+: 25b9c01f fmov z31.s, #2.0+e\+00
-+[^:]+: 25b9c01f fmov z31.s, #2.0+e\+00
-+[^:]+: 25b9c600 fmov z0.s, #1.60+e\+01
-+[^:]+: 25b9c600 fmov z0.s, #1.60+e\+01
-+[^:]+: 25b9c900 fmov z0.s, #1.8750+e-01
-+[^:]+: 25b9c900 fmov z0.s, #1.8750+e-01
-+[^:]+: 25b9cfe0 fmov z0.s, #1.93750+e\+00
-+[^:]+: 25b9cfe0 fmov z0.s, #1.93750+e\+00
-+[^:]+: 25b9d100 fmov z0.s, #-3.0+e\+00
-+[^:]+: 25b9d100 fmov z0.s, #-3.0+e\+00
-+[^:]+: 25b9d800 fmov z0.s, #-1.250+e-01
-+[^:]+: 25b9d800 fmov z0.s, #-1.250+e-01
-+[^:]+: 25b9dfe0 fmov z0.s, #-1.93750+e\+00
-+[^:]+: 25b9dfe0 fmov z0.s, #-1.93750+e\+00
-+[^:]+: 25f9c000 fmov z0.d, #2.0+e\+00
-+[^:]+: 25f9c000 fmov z0.d, #2.0+e\+00
-+[^:]+: 25f9c001 fmov z1.d, #2.0+e\+00
-+[^:]+: 25f9c001 fmov z1.d, #2.0+e\+00
-+[^:]+: 25f9c01f fmov z31.d, #2.0+e\+00
-+[^:]+: 25f9c01f fmov z31.d, #2.0+e\+00
-+[^:]+: 25f9c600 fmov z0.d, #1.60+e\+01
-+[^:]+: 25f9c600 fmov z0.d, #1.60+e\+01
-+[^:]+: 25f9c900 fmov z0.d, #1.8750+e-01
-+[^:]+: 25f9c900 fmov z0.d, #1.8750+e-01
-+[^:]+: 25f9cfe0 fmov z0.d, #1.93750+e\+00
-+[^:]+: 25f9cfe0 fmov z0.d, #1.93750+e\+00
-+[^:]+: 25f9d100 fmov z0.d, #-3.0+e\+00
-+[^:]+: 25f9d100 fmov z0.d, #-3.0+e\+00
-+[^:]+: 25f9d800 fmov z0.d, #-1.250+e-01
-+[^:]+: 25f9d800 fmov z0.d, #-1.250+e-01
-+[^:]+: 25f9dfe0 fmov z0.d, #-1.93750+e\+00
-+[^:]+: 25f9dfe0 fmov z0.d, #-1.93750+e\+00
-+[^:]+: 0550c000 fmov z0.h, p0/m, #2.0+e\+00
-+[^:]+: 0550c000 fmov z0.h, p0/m, #2.0+e\+00
-+[^:]+: 0550c001 fmov z1.h, p0/m, #2.0+e\+00
-+[^:]+: 0550c001 fmov z1.h, p0/m, #2.0+e\+00
-+[^:]+: 0550c01f fmov z31.h, p0/m, #2.0+e\+00
-+[^:]+: 0550c01f fmov z31.h, p0/m, #2.0+e\+00
-+[^:]+: 0552c000 fmov z0.h, p2/m, #2.0+e\+00
-+[^:]+: 0552c000 fmov z0.h, p2/m, #2.0+e\+00
-+[^:]+: 055fc000 fmov z0.h, p15/m, #2.0+e\+00
-+[^:]+: 055fc000 fmov z0.h, p15/m, #2.0+e\+00
-+[^:]+: 0550c600 fmov z0.h, p0/m, #1.60+e\+01
-+[^:]+: 0550c600 fmov z0.h, p0/m, #1.60+e\+01
-+[^:]+: 0550c900 fmov z0.h, p0/m, #1.8750+e-01
-+[^:]+: 0550c900 fmov z0.h, p0/m, #1.8750+e-01
-+[^:]+: 0550cfe0 fmov z0.h, p0/m, #1.93750+e\+00
-+[^:]+: 0550cfe0 fmov z0.h, p0/m, #1.93750+e\+00
-+[^:]+: 0550d100 fmov z0.h, p0/m, #-3.0+e\+00
-+[^:]+: 0550d100 fmov z0.h, p0/m, #-3.0+e\+00
-+[^:]+: 0550d800 fmov z0.h, p0/m, #-1.250+e-01
-+[^:]+: 0550d800 fmov z0.h, p0/m, #-1.250+e-01
-+[^:]+: 0550dfe0 fmov z0.h, p0/m, #-1.93750+e\+00
-+[^:]+: 0550dfe0 fmov z0.h, p0/m, #-1.93750+e\+00
-+[^:]+: 0590c000 fmov z0.s, p0/m, #2.0+e\+00
-+[^:]+: 0590c000 fmov z0.s, p0/m, #2.0+e\+00
-+[^:]+: 0590c001 fmov z1.s, p0/m, #2.0+e\+00
-+[^:]+: 0590c001 fmov z1.s, p0/m, #2.0+e\+00
-+[^:]+: 0590c01f fmov z31.s, p0/m, #2.0+e\+00
-+[^:]+: 0590c01f fmov z31.s, p0/m, #2.0+e\+00
-+[^:]+: 0592c000 fmov z0.s, p2/m, #2.0+e\+00
-+[^:]+: 0592c000 fmov z0.s, p2/m, #2.0+e\+00
-+[^:]+: 059fc000 fmov z0.s, p15/m, #2.0+e\+00
-+[^:]+: 059fc000 fmov z0.s, p15/m, #2.0+e\+00
-+[^:]+: 0590c600 fmov z0.s, p0/m, #1.60+e\+01
-+[^:]+: 0590c600 fmov z0.s, p0/m, #1.60+e\+01
-+[^:]+: 0590c900 fmov z0.s, p0/m, #1.8750+e-01
-+[^:]+: 0590c900 fmov z0.s, p0/m, #1.8750+e-01
-+[^:]+: 0590cfe0 fmov z0.s, p0/m, #1.93750+e\+00
-+[^:]+: 0590cfe0 fmov z0.s, p0/m, #1.93750+e\+00
-+[^:]+: 0590d100 fmov z0.s, p0/m, #-3.0+e\+00
-+[^:]+: 0590d100 fmov z0.s, p0/m, #-3.0+e\+00
-+[^:]+: 0590d800 fmov z0.s, p0/m, #-1.250+e-01
-+[^:]+: 0590d800 fmov z0.s, p0/m, #-1.250+e-01
-+[^:]+: 0590dfe0 fmov z0.s, p0/m, #-1.93750+e\+00
-+[^:]+: 0590dfe0 fmov z0.s, p0/m, #-1.93750+e\+00
-+[^:]+: 05d0c000 fmov z0.d, p0/m, #2.0+e\+00
-+[^:]+: 05d0c000 fmov z0.d, p0/m, #2.0+e\+00
-+[^:]+: 05d0c001 fmov z1.d, p0/m, #2.0+e\+00
-+[^:]+: 05d0c001 fmov z1.d, p0/m, #2.0+e\+00
-+[^:]+: 05d0c01f fmov z31.d, p0/m, #2.0+e\+00
-+[^:]+: 05d0c01f fmov z31.d, p0/m, #2.0+e\+00
-+[^:]+: 05d2c000 fmov z0.d, p2/m, #2.0+e\+00
-+[^:]+: 05d2c000 fmov z0.d, p2/m, #2.0+e\+00
-+[^:]+: 05dfc000 fmov z0.d, p15/m, #2.0+e\+00
-+[^:]+: 05dfc000 fmov z0.d, p15/m, #2.0+e\+00
-+[^:]+: 05d0c600 fmov z0.d, p0/m, #1.60+e\+01
-+[^:]+: 05d0c600 fmov z0.d, p0/m, #1.60+e\+01
-+[^:]+: 05d0c900 fmov z0.d, p0/m, #1.8750+e-01
-+[^:]+: 05d0c900 fmov z0.d, p0/m, #1.8750+e-01
-+[^:]+: 05d0cfe0 fmov z0.d, p0/m, #1.93750+e\+00
-+[^:]+: 05d0cfe0 fmov z0.d, p0/m, #1.93750+e\+00
-+[^:]+: 05d0d100 fmov z0.d, p0/m, #-3.0+e\+00
-+[^:]+: 05d0d100 fmov z0.d, p0/m, #-3.0+e\+00
-+[^:]+: 05d0d800 fmov z0.d, p0/m, #-1.250+e-01
-+[^:]+: 05d0d800 fmov z0.d, p0/m, #-1.250+e-01
-+[^:]+: 05d0dfe0 fmov z0.d, p0/m, #-1.93750+e\+00
-+[^:]+: 05d0dfe0 fmov z0.d, p0/m, #-1.93750+e\+00
-+[^:]+: 04603000 mov z0.d, z0.d
-+[^:]+: 04603000 mov z0.d, z0.d
-+[^:]+: 04603001 mov z1.d, z0.d
-+[^:]+: 04603001 mov z1.d, z0.d
-+[^:]+: 0460301f mov z31.d, z0.d
-+[^:]+: 0460301f mov z31.d, z0.d
-+[^:]+: 04623040 mov z0.d, z2.d
-+[^:]+: 04623040 mov z0.d, z2.d
-+[^:]+: 047f33e0 mov z0.d, z31.d
-+[^:]+: 047f33e0 mov z0.d, z31.d
-+[^:]+: 05212000 mov z0.b, b0
-+[^:]+: 05212000 mov z0.b, b0
-+[^:]+: 05212001 mov z1.b, b0
-+[^:]+: 05212001 mov z1.b, b0
-+[^:]+: 0521201f mov z31.b, b0
-+[^:]+: 0521201f mov z31.b, b0
-+[^:]+: 05212040 mov z0.b, b2
-+[^:]+: 05212040 mov z0.b, b2
-+[^:]+: 052123e0 mov z0.b, b31
-+[^:]+: 052123e0 mov z0.b, b31
-+[^:]+: 05222000 mov z0.h, h0
-+[^:]+: 05222000 mov z0.h, h0
-+[^:]+: 05222001 mov z1.h, h0
-+[^:]+: 05222001 mov z1.h, h0
-+[^:]+: 0522201f mov z31.h, h0
-+[^:]+: 0522201f mov z31.h, h0
-+[^:]+: 05222040 mov z0.h, h2
-+[^:]+: 05222040 mov z0.h, h2
-+[^:]+: 052223e0 mov z0.h, h31
-+[^:]+: 052223e0 mov z0.h, h31
-+[^:]+: 05242000 mov z0.s, s0
-+[^:]+: 05242000 mov z0.s, s0
-+[^:]+: 05242001 mov z1.s, s0
-+[^:]+: 05242001 mov z1.s, s0
-+[^:]+: 0524201f mov z31.s, s0
-+[^:]+: 0524201f mov z31.s, s0
-+[^:]+: 05242040 mov z0.s, s2
-+[^:]+: 05242040 mov z0.s, s2
-+[^:]+: 052423e0 mov z0.s, s31
-+[^:]+: 052423e0 mov z0.s, s31
-+[^:]+: 05282000 mov z0.d, d0
-+[^:]+: 05282000 mov z0.d, d0
-+[^:]+: 05282001 mov z1.d, d0
-+[^:]+: 05282001 mov z1.d, d0
-+[^:]+: 0528201f mov z31.d, d0
-+[^:]+: 0528201f mov z31.d, d0
-+[^:]+: 05282040 mov z0.d, d2
-+[^:]+: 05282040 mov z0.d, d2
-+[^:]+: 052823e0 mov z0.d, d31
-+[^:]+: 052823e0 mov z0.d, d31
-+[^:]+: 05302000 mov z0.q, q0
-+[^:]+: 05302000 mov z0.q, q0
-+[^:]+: 05302001 mov z1.q, q0
-+[^:]+: 05302001 mov z1.q, q0
-+[^:]+: 0530201f mov z31.q, q0
-+[^:]+: 0530201f mov z31.q, q0
-+[^:]+: 05302040 mov z0.q, q2
-+[^:]+: 05302040 mov z0.q, q2
-+[^:]+: 053023e0 mov z0.q, q31
-+[^:]+: 053023e0 mov z0.q, q31
-+[^:]+: 05203800 mov z0.b, w0
-+[^:]+: 05203800 mov z0.b, w0
-+[^:]+: 05203801 mov z1.b, w0
-+[^:]+: 05203801 mov z1.b, w0
-+[^:]+: 0520381f mov z31.b, w0
-+[^:]+: 0520381f mov z31.b, w0
-+[^:]+: 05203840 mov z0.b, w2
-+[^:]+: 05203840 mov z0.b, w2
-+[^:]+: 05203be0 mov z0.b, wsp
-+[^:]+: 05203be0 mov z0.b, wsp
-+[^:]+: 05603800 mov z0.h, w0
-+[^:]+: 05603800 mov z0.h, w0
-+[^:]+: 05603801 mov z1.h, w0
-+[^:]+: 05603801 mov z1.h, w0
-+[^:]+: 0560381f mov z31.h, w0
-+[^:]+: 0560381f mov z31.h, w0
-+[^:]+: 05603840 mov z0.h, w2
-+[^:]+: 05603840 mov z0.h, w2
-+[^:]+: 05603be0 mov z0.h, wsp
-+[^:]+: 05603be0 mov z0.h, wsp
-+[^:]+: 05a03800 mov z0.s, w0
-+[^:]+: 05a03800 mov z0.s, w0
-+[^:]+: 05a03801 mov z1.s, w0
-+[^:]+: 05a03801 mov z1.s, w0
-+[^:]+: 05a0381f mov z31.s, w0
-+[^:]+: 05a0381f mov z31.s, w0
-+[^:]+: 05a03840 mov z0.s, w2
-+[^:]+: 05a03840 mov z0.s, w2
-+[^:]+: 05a03be0 mov z0.s, wsp
-+[^:]+: 05a03be0 mov z0.s, wsp
-+[^:]+: 05e03800 mov z0.d, x0
-+[^:]+: 05e03800 mov z0.d, x0
-+[^:]+: 05e03801 mov z1.d, x0
-+[^:]+: 05e03801 mov z1.d, x0
-+[^:]+: 05e0381f mov z31.d, x0
-+[^:]+: 05e0381f mov z31.d, x0
-+[^:]+: 05e03840 mov z0.d, x2
-+[^:]+: 05e03840 mov z0.d, x2
-+[^:]+: 05e03be0 mov z0.d, sp
-+[^:]+: 05e03be0 mov z0.d, sp
-+[^:]+: 25804000 mov p0.b, p0.b
-+[^:]+: 25804000 mov p0.b, p0.b
-+[^:]+: 25804001 mov p1.b, p0.b
-+[^:]+: 25804001 mov p1.b, p0.b
-+[^:]+: 2580400f mov p15.b, p0.b
-+[^:]+: 2580400f mov p15.b, p0.b
-+[^:]+: 25824840 mov p0.b, p2.b
-+[^:]+: 25824840 mov p0.b, p2.b
-+[^:]+: 258f7de0 mov p0.b, p15.b
-+[^:]+: 258f7de0 mov p0.b, p15.b
-+[^:]+: 05232000 mov z0.b, z0.b\[1\]
-+[^:]+: 05232000 mov z0.b, z0.b\[1\]
-+[^:]+: 05232001 mov z1.b, z0.b\[1\]
-+[^:]+: 05232001 mov z1.b, z0.b\[1\]
-+[^:]+: 0523201f mov z31.b, z0.b\[1\]
-+[^:]+: 0523201f mov z31.b, z0.b\[1\]
-+[^:]+: 05232040 mov z0.b, z2.b\[1\]
-+[^:]+: 05232040 mov z0.b, z2.b\[1\]
-+[^:]+: 052323e0 mov z0.b, z31.b\[1\]
-+[^:]+: 052323e0 mov z0.b, z31.b\[1\]
-+[^:]+: 05252000 mov z0.b, z0.b\[2\]
-+[^:]+: 05252000 mov z0.b, z0.b\[2\]
-+[^:]+: 05fd2000 mov z0.b, z0.b\[62\]
-+[^:]+: 05fd2000 mov z0.b, z0.b\[62\]
-+[^:]+: 05ff2000 mov z0.b, z0.b\[63\]
-+[^:]+: 05ff2000 mov z0.b, z0.b\[63\]
-+[^:]+: 05252001 mov z1.b, z0.b\[2\]
-+[^:]+: 05252001 mov z1.b, z0.b\[2\]
-+[^:]+: 0525201f mov z31.b, z0.b\[2\]
-+[^:]+: 0525201f mov z31.b, z0.b\[2\]
-+[^:]+: 05252040 mov z0.b, z2.b\[2\]
-+[^:]+: 05252040 mov z0.b, z2.b\[2\]
-+[^:]+: 052523e0 mov z0.b, z31.b\[2\]
-+[^:]+: 052523e0 mov z0.b, z31.b\[2\]
-+[^:]+: 05272000 mov z0.b, z0.b\[3\]
-+[^:]+: 05272000 mov z0.b, z0.b\[3\]
-+[^:]+: 05262000 mov z0.h, z0.h\[1\]
-+[^:]+: 05262000 mov z0.h, z0.h\[1\]
-+[^:]+: 05262001 mov z1.h, z0.h\[1\]
-+[^:]+: 05262001 mov z1.h, z0.h\[1\]
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-+[^:]+: 0420a7e0 adr z0.d, \[z31.d, z0.d, sxtw #1\]
-+[^:]+: 0423a400 adr z0.d, \[z0.d, z3.d, sxtw #1\]
-+[^:]+: 0423a400 adr z0.d, \[z0.d, z3.d, sxtw #1\]
-+[^:]+: 043fa400 adr z0.d, \[z0.d, z31.d, sxtw #1\]
-+[^:]+: 043fa400 adr z0.d, \[z0.d, z31.d, sxtw #1\]
-+[^:]+: 0420a800 adr z0.d, \[z0.d, z0.d, sxtw #2\]
-+[^:]+: 0420a800 adr z0.d, \[z0.d, z0.d, sxtw #2\]
-+[^:]+: 0420a801 adr z1.d, \[z0.d, z0.d, sxtw #2\]
-+[^:]+: 0420a801 adr z1.d, \[z0.d, z0.d, sxtw #2\]
-+[^:]+: 0420a81f adr z31.d, \[z0.d, z0.d, sxtw #2\]
-+[^:]+: 0420a81f adr z31.d, \[z0.d, z0.d, sxtw #2\]
-+[^:]+: 0420a840 adr z0.d, \[z2.d, z0.d, sxtw #2\]
-+[^:]+: 0420a840 adr z0.d, \[z2.d, z0.d, sxtw #2\]
-+[^:]+: 0420abe0 adr z0.d, \[z31.d, z0.d, sxtw #2\]
-+[^:]+: 0420abe0 adr z0.d, \[z31.d, z0.d, sxtw #2\]
-+[^:]+: 0423a800 adr z0.d, \[z0.d, z3.d, sxtw #2\]
-+[^:]+: 0423a800 adr z0.d, \[z0.d, z3.d, sxtw #2\]
-+[^:]+: 043fa800 adr z0.d, \[z0.d, z31.d, sxtw #2\]
-+[^:]+: 043fa800 adr z0.d, \[z0.d, z31.d, sxtw #2\]
-+[^:]+: 0420ac00 adr z0.d, \[z0.d, z0.d, sxtw #3\]
-+[^:]+: 0420ac00 adr z0.d, \[z0.d, z0.d, sxtw #3\]
-+[^:]+: 0420ac01 adr z1.d, \[z0.d, z0.d, sxtw #3\]
-+[^:]+: 0420ac01 adr z1.d, \[z0.d, z0.d, sxtw #3\]
-+[^:]+: 0420ac1f adr z31.d, \[z0.d, z0.d, sxtw #3\]
-+[^:]+: 0420ac1f adr z31.d, \[z0.d, z0.d, sxtw #3\]
-+[^:]+: 0420ac40 adr z0.d, \[z2.d, z0.d, sxtw #3\]
-+[^:]+: 0420ac40 adr z0.d, \[z2.d, z0.d, sxtw #3\]
-+[^:]+: 0420afe0 adr z0.d, \[z31.d, z0.d, sxtw #3\]
-+[^:]+: 0420afe0 adr z0.d, \[z31.d, z0.d, sxtw #3\]
-+[^:]+: 0423ac00 adr z0.d, \[z0.d, z3.d, sxtw #3\]
-+[^:]+: 0423ac00 adr z0.d, \[z0.d, z3.d, sxtw #3\]
-+[^:]+: 043fac00 adr z0.d, \[z0.d, z31.d, sxtw #3\]
-+[^:]+: 043fac00 adr z0.d, \[z0.d, z31.d, sxtw #3\]
-+[^:]+: 0460a000 adr z0.d, \[z0.d, z0.d, uxtw\]
-+[^:]+: 0460a000 adr z0.d, \[z0.d, z0.d, uxtw\]
-+[^:]+: 0460a000 adr z0.d, \[z0.d, z0.d, uxtw\]
-+[^:]+: 0460a001 adr z1.d, \[z0.d, z0.d, uxtw\]
-+[^:]+: 0460a001 adr z1.d, \[z0.d, z0.d, uxtw\]
-+[^:]+: 0460a001 adr z1.d, \[z0.d, z0.d, uxtw\]
-+[^:]+: 0460a01f adr z31.d, \[z0.d, z0.d, uxtw\]
-+[^:]+: 0460a01f adr z31.d, \[z0.d, z0.d, uxtw\]
-+[^:]+: 0460a01f adr z31.d, \[z0.d, z0.d, uxtw\]
-+[^:]+: 0460a040 adr z0.d, \[z2.d, z0.d, uxtw\]
-+[^:]+: 0460a040 adr z0.d, \[z2.d, z0.d, uxtw\]
-+[^:]+: 0460a040 adr z0.d, \[z2.d, z0.d, uxtw\]
-+[^:]+: 0460a3e0 adr z0.d, \[z31.d, z0.d, uxtw\]
-+[^:]+: 0460a3e0 adr z0.d, \[z31.d, z0.d, uxtw\]
-+[^:]+: 0460a3e0 adr z0.d, \[z31.d, z0.d, uxtw\]
-+[^:]+: 0463a000 adr z0.d, \[z0.d, z3.d, uxtw\]
-+[^:]+: 0463a000 adr z0.d, \[z0.d, z3.d, uxtw\]
-+[^:]+: 0463a000 adr z0.d, \[z0.d, z3.d, uxtw\]
-+[^:]+: 047fa000 adr z0.d, \[z0.d, z31.d, uxtw\]
-+[^:]+: 047fa000 adr z0.d, \[z0.d, z31.d, uxtw\]
-+[^:]+: 047fa000 adr z0.d, \[z0.d, z31.d, uxtw\]
-+[^:]+: 0460a400 adr z0.d, \[z0.d, z0.d, uxtw #1\]
-+[^:]+: 0460a400 adr z0.d, \[z0.d, z0.d, uxtw #1\]
-+[^:]+: 0460a401 adr z1.d, \[z0.d, z0.d, uxtw #1\]
-+[^:]+: 0460a401 adr z1.d, \[z0.d, z0.d, uxtw #1\]
-+[^:]+: 0460a41f adr z31.d, \[z0.d, z0.d, uxtw #1\]
-+[^:]+: 0460a41f adr z31.d, \[z0.d, z0.d, uxtw #1\]
-+[^:]+: 0460a440 adr z0.d, \[z2.d, z0.d, uxtw #1\]
-+[^:]+: 0460a440 adr z0.d, \[z2.d, z0.d, uxtw #1\]
-+[^:]+: 0460a7e0 adr z0.d, \[z31.d, z0.d, uxtw #1\]
-+[^:]+: 0460a7e0 adr z0.d, \[z31.d, z0.d, uxtw #1\]
-+[^:]+: 0463a400 adr z0.d, \[z0.d, z3.d, uxtw #1\]
-+[^:]+: 0463a400 adr z0.d, \[z0.d, z3.d, uxtw #1\]
-+[^:]+: 047fa400 adr z0.d, \[z0.d, z31.d, uxtw #1\]
-+[^:]+: 047fa400 adr z0.d, \[z0.d, z31.d, uxtw #1\]
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-+[^:]+: 0460a800 adr z0.d, \[z0.d, z0.d, uxtw #2\]
-+[^:]+: 0460a801 adr z1.d, \[z0.d, z0.d, uxtw #2\]
-+[^:]+: 0460a801 adr z1.d, \[z0.d, z0.d, uxtw #2\]
-+[^:]+: 0460a81f adr z31.d, \[z0.d, z0.d, uxtw #2\]
-+[^:]+: 0460a81f adr z31.d, \[z0.d, z0.d, uxtw #2\]
-+[^:]+: 0460a840 adr z0.d, \[z2.d, z0.d, uxtw #2\]
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-+[^:]+: 0460abe0 adr z0.d, \[z31.d, z0.d, uxtw #2\]
-+[^:]+: 0460abe0 adr z0.d, \[z31.d, z0.d, uxtw #2\]
-+[^:]+: 0463a800 adr z0.d, \[z0.d, z3.d, uxtw #2\]
-+[^:]+: 0463a800 adr z0.d, \[z0.d, z3.d, uxtw #2\]
-+[^:]+: 047fa800 adr z0.d, \[z0.d, z31.d, uxtw #2\]
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-+[^:]+: 0463ac00 adr z0.d, \[z0.d, z3.d, uxtw #3\]
-+[^:]+: 047fac00 adr z0.d, \[z0.d, z31.d, uxtw #3\]
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-+[^:]+: 04a0a000 adr z0.s, \[z0.s, z0.s\]
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-+[^:]+: 04a0a01f adr z31.s, \[z0.s, z0.s\]
-+[^:]+: 04a0a01f adr z31.s, \[z0.s, z0.s\]
-+[^:]+: 04a0a040 adr z0.s, \[z2.s, z0.s\]
-+[^:]+: 04a0a040 adr z0.s, \[z2.s, z0.s\]
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-+[^:]+: 04a0a3e0 adr z0.s, \[z31.s, z0.s\]
-+[^:]+: 04a0a3e0 adr z0.s, \[z31.s, z0.s\]
-+[^:]+: 04a3a000 adr z0.s, \[z0.s, z3.s\]
-+[^:]+: 04a3a000 adr z0.s, \[z0.s, z3.s\]
-+[^:]+: 04a3a000 adr z0.s, \[z0.s, z3.s\]
-+[^:]+: 04bfa000 adr z0.s, \[z0.s, z31.s\]
-+[^:]+: 04bfa000 adr z0.s, \[z0.s, z31.s\]
-+[^:]+: 04bfa000 adr z0.s, \[z0.s, z31.s\]
-+[^:]+: 04a0a400 adr z0.s, \[z0.s, z0.s, lsl #1\]
-+[^:]+: 04a0a400 adr z0.s, \[z0.s, z0.s, lsl #1\]
-+[^:]+: 04a0a401 adr z1.s, \[z0.s, z0.s, lsl #1\]
-+[^:]+: 04a0a401 adr z1.s, \[z0.s, z0.s, lsl #1\]
-+[^:]+: 04a0a41f adr z31.s, \[z0.s, z0.s, lsl #1\]
-+[^:]+: 04a0a41f adr z31.s, \[z0.s, z0.s, lsl #1\]
-+[^:]+: 04a0a440 adr z0.s, \[z2.s, z0.s, lsl #1\]
-+[^:]+: 04a0a440 adr z0.s, \[z2.s, z0.s, lsl #1\]
-+[^:]+: 04a0a7e0 adr z0.s, \[z31.s, z0.s, lsl #1\]
-+[^:]+: 04a0a7e0 adr z0.s, \[z31.s, z0.s, lsl #1\]
-+[^:]+: 04a3a400 adr z0.s, \[z0.s, z3.s, lsl #1\]
-+[^:]+: 04a3a400 adr z0.s, \[z0.s, z3.s, lsl #1\]
-+[^:]+: 04bfa400 adr z0.s, \[z0.s, z31.s, lsl #1\]
-+[^:]+: 04bfa400 adr z0.s, \[z0.s, z31.s, lsl #1\]
-+[^:]+: 04a0a800 adr z0.s, \[z0.s, z0.s, lsl #2\]
-+[^:]+: 04a0a800 adr z0.s, \[z0.s, z0.s, lsl #2\]
-+[^:]+: 04a0a801 adr z1.s, \[z0.s, z0.s, lsl #2\]
-+[^:]+: 04a0a801 adr z1.s, \[z0.s, z0.s, lsl #2\]
-+[^:]+: 04a0a81f adr z31.s, \[z0.s, z0.s, lsl #2\]
-+[^:]+: 04a0a81f adr z31.s, \[z0.s, z0.s, lsl #2\]
-+[^:]+: 04a0a840 adr z0.s, \[z2.s, z0.s, lsl #2\]
-+[^:]+: 04a0a840 adr z0.s, \[z2.s, z0.s, lsl #2\]
-+[^:]+: 04a0abe0 adr z0.s, \[z31.s, z0.s, lsl #2\]
-+[^:]+: 04a0abe0 adr z0.s, \[z31.s, z0.s, lsl #2\]
-+[^:]+: 04a3a800 adr z0.s, \[z0.s, z3.s, lsl #2\]
-+[^:]+: 04a3a800 adr z0.s, \[z0.s, z3.s, lsl #2\]
-+[^:]+: 04bfa800 adr z0.s, \[z0.s, z31.s, lsl #2\]
-+[^:]+: 04bfa800 adr z0.s, \[z0.s, z31.s, lsl #2\]
-+[^:]+: 04a0ac00 adr z0.s, \[z0.s, z0.s, lsl #3\]
-+[^:]+: 04a0ac00 adr z0.s, \[z0.s, z0.s, lsl #3\]
-+[^:]+: 04a0ac01 adr z1.s, \[z0.s, z0.s, lsl #3\]
-+[^:]+: 04a0ac01 adr z1.s, \[z0.s, z0.s, lsl #3\]
-+[^:]+: 04a0ac1f adr z31.s, \[z0.s, z0.s, lsl #3\]
-+[^:]+: 04a0ac1f adr z31.s, \[z0.s, z0.s, lsl #3\]
-+[^:]+: 04a0ac40 adr z0.s, \[z2.s, z0.s, lsl #3\]
-+[^:]+: 04a0ac40 adr z0.s, \[z2.s, z0.s, lsl #3\]
-+[^:]+: 04a0afe0 adr z0.s, \[z31.s, z0.s, lsl #3\]
-+[^:]+: 04a0afe0 adr z0.s, \[z31.s, z0.s, lsl #3\]
-+[^:]+: 04a3ac00 adr z0.s, \[z0.s, z3.s, lsl #3\]
-+[^:]+: 04a3ac00 adr z0.s, \[z0.s, z3.s, lsl #3\]
-+[^:]+: 04bfac00 adr z0.s, \[z0.s, z31.s, lsl #3\]
-+[^:]+: 04bfac00 adr z0.s, \[z0.s, z31.s, lsl #3\]
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-+[^:]+: 04e0a000 adr z0.d, \[z0.d, z0.d\]
-+[^:]+: 04e0a000 adr z0.d, \[z0.d, z0.d\]
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-+[^:]+: 04e0a001 adr z1.d, \[z0.d, z0.d\]
-+[^:]+: 04e0a001 adr z1.d, \[z0.d, z0.d\]
-+[^:]+: 04e0a01f adr z31.d, \[z0.d, z0.d\]
-+[^:]+: 04e0a01f adr z31.d, \[z0.d, z0.d\]
-+[^:]+: 04e0a01f adr z31.d, \[z0.d, z0.d\]
-+[^:]+: 04e0a040 adr z0.d, \[z2.d, z0.d\]
-+[^:]+: 04e0a040 adr z0.d, \[z2.d, z0.d\]
-+[^:]+: 04e0a040 adr z0.d, \[z2.d, z0.d\]
-+[^:]+: 04e0a3e0 adr z0.d, \[z31.d, z0.d\]
-+[^:]+: 04e0a3e0 adr z0.d, \[z31.d, z0.d\]
-+[^:]+: 04e0a3e0 adr z0.d, \[z31.d, z0.d\]
-+[^:]+: 04e3a000 adr z0.d, \[z0.d, z3.d\]
-+[^:]+: 04e3a000 adr z0.d, \[z0.d, z3.d\]
-+[^:]+: 04e3a000 adr z0.d, \[z0.d, z3.d\]
-+[^:]+: 04ffa000 adr z0.d, \[z0.d, z31.d\]
-+[^:]+: 04ffa000 adr z0.d, \[z0.d, z31.d\]
-+[^:]+: 04ffa000 adr z0.d, \[z0.d, z31.d\]
-+[^:]+: 04e0a400 adr z0.d, \[z0.d, z0.d, lsl #1\]
-+[^:]+: 04e0a400 adr z0.d, \[z0.d, z0.d, lsl #1\]
-+[^:]+: 04e0a401 adr z1.d, \[z0.d, z0.d, lsl #1\]
-+[^:]+: 04e0a401 adr z1.d, \[z0.d, z0.d, lsl #1\]
-+[^:]+: 04e0a41f adr z31.d, \[z0.d, z0.d, lsl #1\]
-+[^:]+: 04e0a41f adr z31.d, \[z0.d, z0.d, lsl #1\]
-+[^:]+: 04e0a440 adr z0.d, \[z2.d, z0.d, lsl #1\]
-+[^:]+: 04e0a440 adr z0.d, \[z2.d, z0.d, lsl #1\]
-+[^:]+: 04e0a7e0 adr z0.d, \[z31.d, z0.d, lsl #1\]
-+[^:]+: 04e0a7e0 adr z0.d, \[z31.d, z0.d, lsl #1\]
-+[^:]+: 04e3a400 adr z0.d, \[z0.d, z3.d, lsl #1\]
-+[^:]+: 04e3a400 adr z0.d, \[z0.d, z3.d, lsl #1\]
-+[^:]+: 04ffa400 adr z0.d, \[z0.d, z31.d, lsl #1\]
-+[^:]+: 04ffa400 adr z0.d, \[z0.d, z31.d, lsl #1\]
-+[^:]+: 04e0a800 adr z0.d, \[z0.d, z0.d, lsl #2\]
-+[^:]+: 04e0a800 adr z0.d, \[z0.d, z0.d, lsl #2\]
-+[^:]+: 04e0a801 adr z1.d, \[z0.d, z0.d, lsl #2\]
-+[^:]+: 04e0a801 adr z1.d, \[z0.d, z0.d, lsl #2\]
-+[^:]+: 04e0a81f adr z31.d, \[z0.d, z0.d, lsl #2\]
-+[^:]+: 04e0a81f adr z31.d, \[z0.d, z0.d, lsl #2\]
-+[^:]+: 04e0a840 adr z0.d, \[z2.d, z0.d, lsl #2\]
-+[^:]+: 04e0a840 adr z0.d, \[z2.d, z0.d, lsl #2\]
-+[^:]+: 04e0abe0 adr z0.d, \[z31.d, z0.d, lsl #2\]
-+[^:]+: 04e0abe0 adr z0.d, \[z31.d, z0.d, lsl #2\]
-+[^:]+: 04e3a800 adr z0.d, \[z0.d, z3.d, lsl #2\]
-+[^:]+: 04e3a800 adr z0.d, \[z0.d, z3.d, lsl #2\]
-+[^:]+: 04ffa800 adr z0.d, \[z0.d, z31.d, lsl #2\]
-+[^:]+: 04ffa800 adr z0.d, \[z0.d, z31.d, lsl #2\]
-+[^:]+: 04e0ac00 adr z0.d, \[z0.d, z0.d, lsl #3\]
-+[^:]+: 04e0ac00 adr z0.d, \[z0.d, z0.d, lsl #3\]
-+[^:]+: 04e0ac01 adr z1.d, \[z0.d, z0.d, lsl #3\]
-+[^:]+: 04e0ac01 adr z1.d, \[z0.d, z0.d, lsl #3\]
-+[^:]+: 04e0ac1f adr z31.d, \[z0.d, z0.d, lsl #3\]
-+[^:]+: 04e0ac1f adr z31.d, \[z0.d, z0.d, lsl #3\]
-+[^:]+: 04e0ac40 adr z0.d, \[z2.d, z0.d, lsl #3\]
-+[^:]+: 04e0ac40 adr z0.d, \[z2.d, z0.d, lsl #3\]
-+[^:]+: 04e0afe0 adr z0.d, \[z31.d, z0.d, lsl #3\]
-+[^:]+: 04e0afe0 adr z0.d, \[z31.d, z0.d, lsl #3\]
-+[^:]+: 04e3ac00 adr z0.d, \[z0.d, z3.d, lsl #3\]
-+[^:]+: 04e3ac00 adr z0.d, \[z0.d, z3.d, lsl #3\]
-+[^:]+: 04ffac00 adr z0.d, \[z0.d, z31.d, lsl #3\]
-+[^:]+: 04ffac00 adr z0.d, \[z0.d, z31.d, lsl #3\]
-+[^:]+: 04203000 and z0.d, z0.d, z0.d
-+[^:]+: 04203000 and z0.d, z0.d, z0.d
-+[^:]+: 04203001 and z1.d, z0.d, z0.d
-+[^:]+: 04203001 and z1.d, z0.d, z0.d
-+[^:]+: 0420301f and z31.d, z0.d, z0.d
-+[^:]+: 0420301f and z31.d, z0.d, z0.d
-+[^:]+: 04203040 and z0.d, z2.d, z0.d
-+[^:]+: 04203040 and z0.d, z2.d, z0.d
-+[^:]+: 042033e0 and z0.d, z31.d, z0.d
-+[^:]+: 042033e0 and z0.d, z31.d, z0.d
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-+[^:]+: 2558400f brkns p15.b, p0/z, p0.b, p15.b
-+[^:]+: 2558400f brkns p15.b, p0/z, p0.b, p15.b
-+[^:]+: 25584800 brkns p0.b, p2/z, p0.b, p0.b
-+[^:]+: 25584800 brkns p0.b, p2/z, p0.b, p0.b
-+[^:]+: 25587c00 brkns p0.b, p15/z, p0.b, p0.b
-+[^:]+: 25587c00 brkns p0.b, p15/z, p0.b, p0.b
-+[^:]+: 25584060 brkns p0.b, p0/z, p3.b, p0.b
-+[^:]+: 25584060 brkns p0.b, p0/z, p3.b, p0.b
-+[^:]+: 255841e0 brkns p0.b, p0/z, p15.b, p0.b
-+[^:]+: 255841e0 brkns p0.b, p0/z, p15.b, p0.b
-+[^:]+: 25584004 brkns p4.b, p0/z, p0.b, p4.b
-+[^:]+: 25584004 brkns p4.b, p0/z, p0.b, p4.b
-+[^:]+: 2500c000 brkpa p0.b, p0/z, p0.b, p0.b
-+[^:]+: 2500c000 brkpa p0.b, p0/z, p0.b, p0.b
-+[^:]+: 2500c001 brkpa p1.b, p0/z, p0.b, p0.b
-+[^:]+: 2500c001 brkpa p1.b, p0/z, p0.b, p0.b
-+[^:]+: 2500c00f brkpa p15.b, p0/z, p0.b, p0.b
-+[^:]+: 2500c00f brkpa p15.b, p0/z, p0.b, p0.b
-+[^:]+: 2500c800 brkpa p0.b, p2/z, p0.b, p0.b
-+[^:]+: 2500c800 brkpa p0.b, p2/z, p0.b, p0.b
-+[^:]+: 2500fc00 brkpa p0.b, p15/z, p0.b, p0.b
-+[^:]+: 2500fc00 brkpa p0.b, p15/z, p0.b, p0.b
-+[^:]+: 2500c060 brkpa p0.b, p0/z, p3.b, p0.b
-+[^:]+: 2500c060 brkpa p0.b, p0/z, p3.b, p0.b
-+[^:]+: 2500c1e0 brkpa p0.b, p0/z, p15.b, p0.b
-+[^:]+: 2500c1e0 brkpa p0.b, p0/z, p15.b, p0.b
-+[^:]+: 2504c000 brkpa p0.b, p0/z, p0.b, p4.b
-+[^:]+: 2504c000 brkpa p0.b, p0/z, p0.b, p4.b
-+[^:]+: 250fc000 brkpa p0.b, p0/z, p0.b, p15.b
-+[^:]+: 250fc000 brkpa p0.b, p0/z, p0.b, p15.b
-+[^:]+: 2540c000 brkpas p0.b, p0/z, p0.b, p0.b
-+[^:]+: 2540c000 brkpas p0.b, p0/z, p0.b, p0.b
-+[^:]+: 2540c001 brkpas p1.b, p0/z, p0.b, p0.b
-+[^:]+: 2540c001 brkpas p1.b, p0/z, p0.b, p0.b
-+[^:]+: 2540c00f brkpas p15.b, p0/z, p0.b, p0.b
-+[^:]+: 2540c00f brkpas p15.b, p0/z, p0.b, p0.b
-+[^:]+: 2540c800 brkpas p0.b, p2/z, p0.b, p0.b
-+[^:]+: 2540c800 brkpas p0.b, p2/z, p0.b, p0.b
-+[^:]+: 2540fc00 brkpas p0.b, p15/z, p0.b, p0.b
-+[^:]+: 2540fc00 brkpas p0.b, p15/z, p0.b, p0.b
-+[^:]+: 2540c060 brkpas p0.b, p0/z, p3.b, p0.b
-+[^:]+: 2540c060 brkpas p0.b, p0/z, p3.b, p0.b
-+[^:]+: 2540c1e0 brkpas p0.b, p0/z, p15.b, p0.b
-+[^:]+: 2540c1e0 brkpas p0.b, p0/z, p15.b, p0.b
-+[^:]+: 2544c000 brkpas p0.b, p0/z, p0.b, p4.b
-+[^:]+: 2544c000 brkpas p0.b, p0/z, p0.b, p4.b
-+[^:]+: 254fc000 brkpas p0.b, p0/z, p0.b, p15.b
-+[^:]+: 254fc000 brkpas p0.b, p0/z, p0.b, p15.b
-+[^:]+: 2500c010 brkpb p0.b, p0/z, p0.b, p0.b
-+[^:]+: 2500c010 brkpb p0.b, p0/z, p0.b, p0.b
-+[^:]+: 2500c011 brkpb p1.b, p0/z, p0.b, p0.b
-+[^:]+: 2500c011 brkpb p1.b, p0/z, p0.b, p0.b
-+[^:]+: 2500c01f brkpb p15.b, p0/z, p0.b, p0.b
-+[^:]+: 2500c01f brkpb p15.b, p0/z, p0.b, p0.b
-+[^:]+: 2500c810 brkpb p0.b, p2/z, p0.b, p0.b
-+[^:]+: 2500c810 brkpb p0.b, p2/z, p0.b, p0.b
-+[^:]+: 2500fc10 brkpb p0.b, p15/z, p0.b, p0.b
-+[^:]+: 2500fc10 brkpb p0.b, p15/z, p0.b, p0.b
-+[^:]+: 2500c070 brkpb p0.b, p0/z, p3.b, p0.b
-+[^:]+: 2500c070 brkpb p0.b, p0/z, p3.b, p0.b
-+[^:]+: 2500c1f0 brkpb p0.b, p0/z, p15.b, p0.b
-+[^:]+: 2500c1f0 brkpb p0.b, p0/z, p15.b, p0.b
-+[^:]+: 2504c010 brkpb p0.b, p0/z, p0.b, p4.b
-+[^:]+: 2504c010 brkpb p0.b, p0/z, p0.b, p4.b
-+[^:]+: 250fc010 brkpb p0.b, p0/z, p0.b, p15.b
-+[^:]+: 250fc010 brkpb p0.b, p0/z, p0.b, p15.b
-+[^:]+: 2540c010 brkpbs p0.b, p0/z, p0.b, p0.b
-+[^:]+: 2540c010 brkpbs p0.b, p0/z, p0.b, p0.b
-+[^:]+: 2540c011 brkpbs p1.b, p0/z, p0.b, p0.b
-+[^:]+: 2540c011 brkpbs p1.b, p0/z, p0.b, p0.b
-+[^:]+: 2540c01f brkpbs p15.b, p0/z, p0.b, p0.b
-+[^:]+: 2540c01f brkpbs p15.b, p0/z, p0.b, p0.b
-+[^:]+: 2540c810 brkpbs p0.b, p2/z, p0.b, p0.b
-+[^:]+: 2540c810 brkpbs p0.b, p2/z, p0.b, p0.b
-+[^:]+: 2540fc10 brkpbs p0.b, p15/z, p0.b, p0.b
-+[^:]+: 2540fc10 brkpbs p0.b, p15/z, p0.b, p0.b
-+[^:]+: 2540c070 brkpbs p0.b, p0/z, p3.b, p0.b
-+[^:]+: 2540c070 brkpbs p0.b, p0/z, p3.b, p0.b
-+[^:]+: 2540c1f0 brkpbs p0.b, p0/z, p15.b, p0.b
-+[^:]+: 2540c1f0 brkpbs p0.b, p0/z, p15.b, p0.b
-+[^:]+: 2544c010 brkpbs p0.b, p0/z, p0.b, p4.b
-+[^:]+: 2544c010 brkpbs p0.b, p0/z, p0.b, p4.b
-+[^:]+: 254fc010 brkpbs p0.b, p0/z, p0.b, p15.b
-+[^:]+: 254fc010 brkpbs p0.b, p0/z, p0.b, p15.b
-+[^:]+: 05288000 clasta z0.b, p0, z0.b, z0.b
-+[^:]+: 05288000 clasta z0.b, p0, z0.b, z0.b
-+[^:]+: 05288001 clasta z1.b, p0, z1.b, z0.b
-+[^:]+: 05288001 clasta z1.b, p0, z1.b, z0.b
-+[^:]+: 0528801f clasta z31.b, p0, z31.b, z0.b
-+[^:]+: 0528801f clasta z31.b, p0, z31.b, z0.b
-+[^:]+: 05288800 clasta z0.b, p2, z0.b, z0.b
-+[^:]+: 05288800 clasta z0.b, p2, z0.b, z0.b
-+[^:]+: 05289c00 clasta z0.b, p7, z0.b, z0.b
-+[^:]+: 05289c00 clasta z0.b, p7, z0.b, z0.b
-+[^:]+: 05288003 clasta z3.b, p0, z3.b, z0.b
-+[^:]+: 05288003 clasta z3.b, p0, z3.b, z0.b
-+[^:]+: 05288080 clasta z0.b, p0, z0.b, z4.b
-+[^:]+: 05288080 clasta z0.b, p0, z0.b, z4.b
-+[^:]+: 052883e0 clasta z0.b, p0, z0.b, z31.b
-+[^:]+: 052883e0 clasta z0.b, p0, z0.b, z31.b
-+[^:]+: 05688000 clasta z0.h, p0, z0.h, z0.h
-+[^:]+: 05688000 clasta z0.h, p0, z0.h, z0.h
-+[^:]+: 05688001 clasta z1.h, p0, z1.h, z0.h
-+[^:]+: 05688001 clasta z1.h, p0, z1.h, z0.h
-+[^:]+: 0568801f clasta z31.h, p0, z31.h, z0.h
-+[^:]+: 0568801f clasta z31.h, p0, z31.h, z0.h
-+[^:]+: 05688800 clasta z0.h, p2, z0.h, z0.h
-+[^:]+: 05688800 clasta z0.h, p2, z0.h, z0.h
-+[^:]+: 05689c00 clasta z0.h, p7, z0.h, z0.h
-+[^:]+: 05689c00 clasta z0.h, p7, z0.h, z0.h
-+[^:]+: 05688003 clasta z3.h, p0, z3.h, z0.h
-+[^:]+: 05688003 clasta z3.h, p0, z3.h, z0.h
-+[^:]+: 05688080 clasta z0.h, p0, z0.h, z4.h
-+[^:]+: 05688080 clasta z0.h, p0, z0.h, z4.h
-+[^:]+: 056883e0 clasta z0.h, p0, z0.h, z31.h
-+[^:]+: 056883e0 clasta z0.h, p0, z0.h, z31.h
-+[^:]+: 05a88000 clasta z0.s, p0, z0.s, z0.s
-+[^:]+: 05a88000 clasta z0.s, p0, z0.s, z0.s
-+[^:]+: 05a88001 clasta z1.s, p0, z1.s, z0.s
-+[^:]+: 05a88001 clasta z1.s, p0, z1.s, z0.s
-+[^:]+: 05a8801f clasta z31.s, p0, z31.s, z0.s
-+[^:]+: 05a8801f clasta z31.s, p0, z31.s, z0.s
-+[^:]+: 05a88800 clasta z0.s, p2, z0.s, z0.s
-+[^:]+: 05a88800 clasta z0.s, p2, z0.s, z0.s
-+[^:]+: 05a89c00 clasta z0.s, p7, z0.s, z0.s
-+[^:]+: 05a89c00 clasta z0.s, p7, z0.s, z0.s
-+[^:]+: 05a88003 clasta z3.s, p0, z3.s, z0.s
-+[^:]+: 05a88003 clasta z3.s, p0, z3.s, z0.s
-+[^:]+: 05a88080 clasta z0.s, p0, z0.s, z4.s
-+[^:]+: 05a88080 clasta z0.s, p0, z0.s, z4.s
-+[^:]+: 05a883e0 clasta z0.s, p0, z0.s, z31.s
-+[^:]+: 05a883e0 clasta z0.s, p0, z0.s, z31.s
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-+[^:]+: 05e88000 clasta z0.d, p0, z0.d, z0.d
-+[^:]+: 05e88001 clasta z1.d, p0, z1.d, z0.d
-+[^:]+: 05e88001 clasta z1.d, p0, z1.d, z0.d
-+[^:]+: 05e8801f clasta z31.d, p0, z31.d, z0.d
-+[^:]+: 05e8801f clasta z31.d, p0, z31.d, z0.d
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-+[^:]+: 05e88800 clasta z0.d, p2, z0.d, z0.d
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-+[^:]+: 05e89c00 clasta z0.d, p7, z0.d, z0.d
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-+[^:]+: 05e88003 clasta z3.d, p0, z3.d, z0.d
-+[^:]+: 05e88080 clasta z0.d, p0, z0.d, z4.d
-+[^:]+: 05e88080 clasta z0.d, p0, z0.d, z4.d
-+[^:]+: 05e883e0 clasta z0.d, p0, z0.d, z31.d
-+[^:]+: 05e883e0 clasta z0.d, p0, z0.d, z31.d
-+[^:]+: 052a8000 clasta b0, p0, b0, z0.b
-+[^:]+: 052a8000 clasta b0, p0, b0, z0.b
-+[^:]+: 052a8001 clasta b1, p0, b1, z0.b
-+[^:]+: 052a8001 clasta b1, p0, b1, z0.b
-+[^:]+: 052a801f clasta b31, p0, b31, z0.b
-+[^:]+: 052a801f clasta b31, p0, b31, z0.b
-+[^:]+: 052a8800 clasta b0, p2, b0, z0.b
-+[^:]+: 052a8800 clasta b0, p2, b0, z0.b
-+[^:]+: 052a9c00 clasta b0, p7, b0, z0.b
-+[^:]+: 052a9c00 clasta b0, p7, b0, z0.b
-+[^:]+: 052a8003 clasta b3, p0, b3, z0.b
-+[^:]+: 052a8003 clasta b3, p0, b3, z0.b
-+[^:]+: 052a8080 clasta b0, p0, b0, z4.b
-+[^:]+: 052a8080 clasta b0, p0, b0, z4.b
-+[^:]+: 052a83e0 clasta b0, p0, b0, z31.b
-+[^:]+: 052a83e0 clasta b0, p0, b0, z31.b
-+[^:]+: 056a8000 clasta h0, p0, h0, z0.h
-+[^:]+: 056a8000 clasta h0, p0, h0, z0.h
-+[^:]+: 056a8001 clasta h1, p0, h1, z0.h
-+[^:]+: 056a8001 clasta h1, p0, h1, z0.h
-+[^:]+: 056a801f clasta h31, p0, h31, z0.h
-+[^:]+: 056a801f clasta h31, p0, h31, z0.h
-+[^:]+: 056a8800 clasta h0, p2, h0, z0.h
-+[^:]+: 056a8800 clasta h0, p2, h0, z0.h
-+[^:]+: 056a9c00 clasta h0, p7, h0, z0.h
-+[^:]+: 056a9c00 clasta h0, p7, h0, z0.h
-+[^:]+: 056a8003 clasta h3, p0, h3, z0.h
-+[^:]+: 056a8003 clasta h3, p0, h3, z0.h
-+[^:]+: 056a8080 clasta h0, p0, h0, z4.h
-+[^:]+: 056a8080 clasta h0, p0, h0, z4.h
-+[^:]+: 056a83e0 clasta h0, p0, h0, z31.h
-+[^:]+: 056a83e0 clasta h0, p0, h0, z31.h
-+[^:]+: 05aa8000 clasta s0, p0, s0, z0.s
-+[^:]+: 05aa8000 clasta s0, p0, s0, z0.s
-+[^:]+: 05aa8001 clasta s1, p0, s1, z0.s
-+[^:]+: 05aa8001 clasta s1, p0, s1, z0.s
-+[^:]+: 05aa801f clasta s31, p0, s31, z0.s
-+[^:]+: 05aa801f clasta s31, p0, s31, z0.s
-+[^:]+: 05aa8800 clasta s0, p2, s0, z0.s
-+[^:]+: 05aa8800 clasta s0, p2, s0, z0.s
-+[^:]+: 05aa9c00 clasta s0, p7, s0, z0.s
-+[^:]+: 05aa9c00 clasta s0, p7, s0, z0.s
-+[^:]+: 05aa8003 clasta s3, p0, s3, z0.s
-+[^:]+: 05aa8003 clasta s3, p0, s3, z0.s
-+[^:]+: 05aa8080 clasta s0, p0, s0, z4.s
-+[^:]+: 05aa8080 clasta s0, p0, s0, z4.s
-+[^:]+: 05aa83e0 clasta s0, p0, s0, z31.s
-+[^:]+: 05aa83e0 clasta s0, p0, s0, z31.s
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-+[^:]+: 05ea8000 clasta d0, p0, d0, z0.d
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-+[^:]+: 05ea8001 clasta d1, p0, d1, z0.d
-+[^:]+: 05ea801f clasta d31, p0, d31, z0.d
-+[^:]+: 05ea801f clasta d31, p0, d31, z0.d
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-+[^:]+: 05ea8080 clasta d0, p0, d0, z4.d
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-+[^:]+: 05ea83e0 clasta d0, p0, d0, z31.d
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-+[^:]+: 0530a3e0 clasta w0, p0, w0, z31.b
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-+[^:]+: 24444010 cmpgt p0.h, p0/z, z0.h, z4.d
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-+[^:]+: 245f4010 cmpgt p0.h, p0/z, z0.h, z31.d
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-+[^:]+: 24805c10 cmpgt p0.s, p7/z, z0.s, z0.d
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-+[^:]+: 24804070 cmpgt p0.s, p0/z, z3.s, z0.d
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-+[^:]+: 248043f0 cmpgt p0.s, p0/z, z31.s, z0.d
-+[^:]+: 24844010 cmpgt p0.s, p0/z, z0.s, z4.d
-+[^:]+: 24844010 cmpgt p0.s, p0/z, z0.s, z4.d
-+[^:]+: 249f4010 cmpgt p0.s, p0/z, z0.s, z31.d
-+[^:]+: 249f4010 cmpgt p0.s, p0/z, z0.s, z31.d
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-+[^:]+: 24008810 cmpgt p0.b, p2/z, z0.b, z0.b
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-+[^:]+: 24008070 cmpgt p0.b, p0/z, z3.b, z0.b
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-+[^:]+: 240083f0 cmpgt p0.b, p0/z, z31.b, z0.b
-+[^:]+: 24048010 cmpgt p0.b, p0/z, z0.b, z4.b
-+[^:]+: 24048010 cmpgt p0.b, p0/z, z0.b, z4.b
-+[^:]+: 241f8010 cmpgt p0.b, p0/z, z0.b, z31.b
-+[^:]+: 241f8010 cmpgt p0.b, p0/z, z0.b, z31.b
-+[^:]+: 24408010 cmpgt p0.h, p0/z, z0.h, z0.h
-+[^:]+: 24408010 cmpgt p0.h, p0/z, z0.h, z0.h
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-+[^:]+: 24408011 cmpgt p1.h, p0/z, z0.h, z0.h
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-+[^:]+: 24408810 cmpgt p0.h, p2/z, z0.h, z0.h
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-+[^:]+: 24409c10 cmpgt p0.h, p7/z, z0.h, z0.h
-+[^:]+: 24408070 cmpgt p0.h, p0/z, z3.h, z0.h
-+[^:]+: 24408070 cmpgt p0.h, p0/z, z3.h, z0.h
-+[^:]+: 244083f0 cmpgt p0.h, p0/z, z31.h, z0.h
-+[^:]+: 244083f0 cmpgt p0.h, p0/z, z31.h, z0.h
-+[^:]+: 24448010 cmpgt p0.h, p0/z, z0.h, z4.h
-+[^:]+: 24448010 cmpgt p0.h, p0/z, z0.h, z4.h
-+[^:]+: 245f8010 cmpgt p0.h, p0/z, z0.h, z31.h
-+[^:]+: 245f8010 cmpgt p0.h, p0/z, z0.h, z31.h
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-+[^:]+: 24808010 cmpgt p0.s, p0/z, z0.s, z0.s
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-+[^:]+: 24808011 cmpgt p1.s, p0/z, z0.s, z0.s
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-+[^:]+: 2480801f cmpgt p15.s, p0/z, z0.s, z0.s
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-+[^:]+: 24808810 cmpgt p0.s, p2/z, z0.s, z0.s
-+[^:]+: 24809c10 cmpgt p0.s, p7/z, z0.s, z0.s
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-+[^:]+: 24808070 cmpgt p0.s, p0/z, z3.s, z0.s
-+[^:]+: 24808070 cmpgt p0.s, p0/z, z3.s, z0.s
-+[^:]+: 248083f0 cmpgt p0.s, p0/z, z31.s, z0.s
-+[^:]+: 248083f0 cmpgt p0.s, p0/z, z31.s, z0.s
-+[^:]+: 24848010 cmpgt p0.s, p0/z, z0.s, z4.s
-+[^:]+: 24848010 cmpgt p0.s, p0/z, z0.s, z4.s
-+[^:]+: 249f8010 cmpgt p0.s, p0/z, z0.s, z31.s
-+[^:]+: 249f8010 cmpgt p0.s, p0/z, z0.s, z31.s
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-+[^:]+: 24c08010 cmpgt p0.d, p0/z, z0.d, z0.d
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-+[^:]+: 24c08011 cmpgt p1.d, p0/z, z0.d, z0.d
-+[^:]+: 24c0801f cmpgt p15.d, p0/z, z0.d, z0.d
-+[^:]+: 24c0801f cmpgt p15.d, p0/z, z0.d, z0.d
-+[^:]+: 24c08810 cmpgt p0.d, p2/z, z0.d, z0.d
-+[^:]+: 24c08810 cmpgt p0.d, p2/z, z0.d, z0.d
-+[^:]+: 24c09c10 cmpgt p0.d, p7/z, z0.d, z0.d
-+[^:]+: 24c09c10 cmpgt p0.d, p7/z, z0.d, z0.d
-+[^:]+: 24c08070 cmpgt p0.d, p0/z, z3.d, z0.d
-+[^:]+: 24c08070 cmpgt p0.d, p0/z, z3.d, z0.d
-+[^:]+: 24c083f0 cmpgt p0.d, p0/z, z31.d, z0.d
-+[^:]+: 24c083f0 cmpgt p0.d, p0/z, z31.d, z0.d
-+[^:]+: 24c48010 cmpgt p0.d, p0/z, z0.d, z4.d
-+[^:]+: 24c48010 cmpgt p0.d, p0/z, z0.d, z4.d
-+[^:]+: 24df8010 cmpgt p0.d, p0/z, z0.d, z31.d
-+[^:]+: 24df8010 cmpgt p0.d, p0/z, z0.d, z31.d
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-+[^:]+: 25000810 cmpgt p0.b, p2/z, z0.b, #0
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-+[^:]+: 25000070 cmpgt p0.b, p0/z, z3.b, #0
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-+[^:]+: 250003f0 cmpgt p0.b, p0/z, z31.b, #0
-+[^:]+: 250f0010 cmpgt p0.b, p0/z, z0.b, #15
-+[^:]+: 250f0010 cmpgt p0.b, p0/z, z0.b, #15
-+[^:]+: 25100010 cmpgt p0.b, p0/z, z0.b, #-16
-+[^:]+: 25100010 cmpgt p0.b, p0/z, z0.b, #-16
-+[^:]+: 25110010 cmpgt p0.b, p0/z, z0.b, #-15
-+[^:]+: 25110010 cmpgt p0.b, p0/z, z0.b, #-15
-+[^:]+: 251f0010 cmpgt p0.b, p0/z, z0.b, #-1
-+[^:]+: 251f0010 cmpgt p0.b, p0/z, z0.b, #-1
-+[^:]+: 25400010 cmpgt p0.h, p0/z, z0.h, #0
-+[^:]+: 25400010 cmpgt p0.h, p0/z, z0.h, #0
-+[^:]+: 25400011 cmpgt p1.h, p0/z, z0.h, #0
-+[^:]+: 25400011 cmpgt p1.h, p0/z, z0.h, #0
-+[^:]+: 2540001f cmpgt p15.h, p0/z, z0.h, #0
-+[^:]+: 2540001f cmpgt p15.h, p0/z, z0.h, #0
-+[^:]+: 25400810 cmpgt p0.h, p2/z, z0.h, #0
-+[^:]+: 25400810 cmpgt p0.h, p2/z, z0.h, #0
-+[^:]+: 25401c10 cmpgt p0.h, p7/z, z0.h, #0
-+[^:]+: 25401c10 cmpgt p0.h, p7/z, z0.h, #0
-+[^:]+: 25400070 cmpgt p0.h, p0/z, z3.h, #0
-+[^:]+: 25400070 cmpgt p0.h, p0/z, z3.h, #0
-+[^:]+: 254003f0 cmpgt p0.h, p0/z, z31.h, #0
-+[^:]+: 254003f0 cmpgt p0.h, p0/z, z31.h, #0
-+[^:]+: 254f0010 cmpgt p0.h, p0/z, z0.h, #15
-+[^:]+: 254f0010 cmpgt p0.h, p0/z, z0.h, #15
-+[^:]+: 25500010 cmpgt p0.h, p0/z, z0.h, #-16
-+[^:]+: 25500010 cmpgt p0.h, p0/z, z0.h, #-16
-+[^:]+: 25510010 cmpgt p0.h, p0/z, z0.h, #-15
-+[^:]+: 25510010 cmpgt p0.h, p0/z, z0.h, #-15
-+[^:]+: 255f0010 cmpgt p0.h, p0/z, z0.h, #-1
-+[^:]+: 255f0010 cmpgt p0.h, p0/z, z0.h, #-1
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-+[^:]+: 25800010 cmpgt p0.s, p0/z, z0.s, #0
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-+[^:]+: 25800011 cmpgt p1.s, p0/z, z0.s, #0
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-+[^:]+: 2580001f cmpgt p15.s, p0/z, z0.s, #0
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-+[^:]+: 25800810 cmpgt p0.s, p2/z, z0.s, #0
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-+[^:]+: 25800070 cmpgt p0.s, p0/z, z3.s, #0
-+[^:]+: 25800070 cmpgt p0.s, p0/z, z3.s, #0
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-+[^:]+: 258003f0 cmpgt p0.s, p0/z, z31.s, #0
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-+[^:]+: 258f0010 cmpgt p0.s, p0/z, z0.s, #15
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-+[^:]+: 25900010 cmpgt p0.s, p0/z, z0.s, #-16
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-+[^:]+: 25910010 cmpgt p0.s, p0/z, z0.s, #-15
-+[^:]+: 259f0010 cmpgt p0.s, p0/z, z0.s, #-1
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-+[^:]+: 25c00011 cmpgt p1.d, p0/z, z0.d, #0
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-+[^:]+: 25c0001f cmpgt p15.d, p0/z, z0.d, #0
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-+[^:]+: 25c00810 cmpgt p0.d, p2/z, z0.d, #0
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-+[^:]+: 25c00070 cmpgt p0.d, p0/z, z3.d, #0
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-+[^:]+: 25c003f0 cmpgt p0.d, p0/z, z31.d, #0
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-+[^:]+: 25cf0010 cmpgt p0.d, p0/z, z0.d, #15
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-+[^:]+: 25d00010 cmpgt p0.d, p0/z, z0.d, #-16
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-+[^:]+: 25d10010 cmpgt p0.d, p0/z, z0.d, #-15
-+[^:]+: 25df0010 cmpgt p0.d, p0/z, z0.d, #-1
-+[^:]+: 25df0010 cmpgt p0.d, p0/z, z0.d, #-1
-+[^:]+: 24000010 cmphi p0.b, p0/z, z0.b, z0.b
-+[^:]+: 24000010 cmphi p0.b, p0/z, z0.b, z0.b
-+[^:]+: 24000011 cmphi p1.b, p0/z, z0.b, z0.b
-+[^:]+: 24000011 cmphi p1.b, p0/z, z0.b, z0.b
-+[^:]+: 2400001f cmphi p15.b, p0/z, z0.b, z0.b
-+[^:]+: 2400001f cmphi p15.b, p0/z, z0.b, z0.b
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-+[^:]+: 24000810 cmphi p0.b, p2/z, z0.b, z0.b
-+[^:]+: 24001c10 cmphi p0.b, p7/z, z0.b, z0.b
-+[^:]+: 24001c10 cmphi p0.b, p7/z, z0.b, z0.b
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-+[^:]+: 24000070 cmphi p0.b, p0/z, z3.b, z0.b
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-+[^:]+: 240003f0 cmphi p0.b, p0/z, z31.b, z0.b
-+[^:]+: 24040010 cmphi p0.b, p0/z, z0.b, z4.b
-+[^:]+: 24040010 cmphi p0.b, p0/z, z0.b, z4.b
-+[^:]+: 241f0010 cmphi p0.b, p0/z, z0.b, z31.b
-+[^:]+: 241f0010 cmphi p0.b, p0/z, z0.b, z31.b
-+[^:]+: 24400010 cmphi p0.h, p0/z, z0.h, z0.h
-+[^:]+: 24400010 cmphi p0.h, p0/z, z0.h, z0.h
-+[^:]+: 24400011 cmphi p1.h, p0/z, z0.h, z0.h
-+[^:]+: 24400011 cmphi p1.h, p0/z, z0.h, z0.h
-+[^:]+: 2440001f cmphi p15.h, p0/z, z0.h, z0.h
-+[^:]+: 2440001f cmphi p15.h, p0/z, z0.h, z0.h
-+[^:]+: 24400810 cmphi p0.h, p2/z, z0.h, z0.h
-+[^:]+: 24400810 cmphi p0.h, p2/z, z0.h, z0.h
-+[^:]+: 24401c10 cmphi p0.h, p7/z, z0.h, z0.h
-+[^:]+: 24401c10 cmphi p0.h, p7/z, z0.h, z0.h
-+[^:]+: 24400070 cmphi p0.h, p0/z, z3.h, z0.h
-+[^:]+: 24400070 cmphi p0.h, p0/z, z3.h, z0.h
-+[^:]+: 244003f0 cmphi p0.h, p0/z, z31.h, z0.h
-+[^:]+: 244003f0 cmphi p0.h, p0/z, z31.h, z0.h
-+[^:]+: 24440010 cmphi p0.h, p0/z, z0.h, z4.h
-+[^:]+: 24440010 cmphi p0.h, p0/z, z0.h, z4.h
-+[^:]+: 245f0010 cmphi p0.h, p0/z, z0.h, z31.h
-+[^:]+: 245f0010 cmphi p0.h, p0/z, z0.h, z31.h
-+[^:]+: 24800010 cmphi p0.s, p0/z, z0.s, z0.s
-+[^:]+: 24800010 cmphi p0.s, p0/z, z0.s, z0.s
-+[^:]+: 24800011 cmphi p1.s, p0/z, z0.s, z0.s
-+[^:]+: 24800011 cmphi p1.s, p0/z, z0.s, z0.s
-+[^:]+: 2480001f cmphi p15.s, p0/z, z0.s, z0.s
-+[^:]+: 2480001f cmphi p15.s, p0/z, z0.s, z0.s
-+[^:]+: 24800810 cmphi p0.s, p2/z, z0.s, z0.s
-+[^:]+: 24800810 cmphi p0.s, p2/z, z0.s, z0.s
-+[^:]+: 24801c10 cmphi p0.s, p7/z, z0.s, z0.s
-+[^:]+: 24801c10 cmphi p0.s, p7/z, z0.s, z0.s
-+[^:]+: 24800070 cmphi p0.s, p0/z, z3.s, z0.s
-+[^:]+: 24800070 cmphi p0.s, p0/z, z3.s, z0.s
-+[^:]+: 248003f0 cmphi p0.s, p0/z, z31.s, z0.s
-+[^:]+: 248003f0 cmphi p0.s, p0/z, z31.s, z0.s
-+[^:]+: 24840010 cmphi p0.s, p0/z, z0.s, z4.s
-+[^:]+: 24840010 cmphi p0.s, p0/z, z0.s, z4.s
-+[^:]+: 249f0010 cmphi p0.s, p0/z, z0.s, z31.s
-+[^:]+: 249f0010 cmphi p0.s, p0/z, z0.s, z31.s
-+[^:]+: 24c00010 cmphi p0.d, p0/z, z0.d, z0.d
-+[^:]+: 24c00010 cmphi p0.d, p0/z, z0.d, z0.d
-+[^:]+: 24c00011 cmphi p1.d, p0/z, z0.d, z0.d
-+[^:]+: 24c00011 cmphi p1.d, p0/z, z0.d, z0.d
-+[^:]+: 24c0001f cmphi p15.d, p0/z, z0.d, z0.d
-+[^:]+: 24c0001f cmphi p15.d, p0/z, z0.d, z0.d
-+[^:]+: 24c00810 cmphi p0.d, p2/z, z0.d, z0.d
-+[^:]+: 24c00810 cmphi p0.d, p2/z, z0.d, z0.d
-+[^:]+: 24c01c10 cmphi p0.d, p7/z, z0.d, z0.d
-+[^:]+: 24c01c10 cmphi p0.d, p7/z, z0.d, z0.d
-+[^:]+: 24c00070 cmphi p0.d, p0/z, z3.d, z0.d
-+[^:]+: 24c00070 cmphi p0.d, p0/z, z3.d, z0.d
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-+[^:]+: 24c003f0 cmphi p0.d, p0/z, z31.d, z0.d
-+[^:]+: 24c40010 cmphi p0.d, p0/z, z0.d, z4.d
-+[^:]+: 24c40010 cmphi p0.d, p0/z, z0.d, z4.d
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-+[^:]+: 2400c010 cmphi p0.b, p0/z, z0.b, z0.d
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-+[^:]+: 2400c011 cmphi p1.b, p0/z, z0.b, z0.d
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-+[^:]+: 2400c070 cmphi p0.b, p0/z, z3.b, z0.d
-+[^:]+: 2400c3f0 cmphi p0.b, p0/z, z31.b, z0.d
-+[^:]+: 2400c3f0 cmphi p0.b, p0/z, z31.b, z0.d
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-+[^:]+: 2404c010 cmphi p0.b, p0/z, z0.b, z4.d
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-+[^:]+: 241fc010 cmphi p0.b, p0/z, z0.b, z31.d
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-+[^:]+: 2440c010 cmphi p0.h, p0/z, z0.h, z0.d
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-+[^:]+: 2444c010 cmphi p0.h, p0/z, z0.h, z4.d
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-+[^:]+: 245fc010 cmphi p0.h, p0/z, z0.h, z31.d
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-+[^:]+: 2480c010 cmphi p0.s, p0/z, z0.s, z0.d
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-+[^:]+: 2480c011 cmphi p1.s, p0/z, z0.s, z0.d
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-+[^:]+: 2480c01f cmphi p15.s, p0/z, z0.s, z0.d
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-+[^:]+: 2480c810 cmphi p0.s, p2/z, z0.s, z0.d
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-+[^:]+: 2480dc10 cmphi p0.s, p7/z, z0.s, z0.d
-+[^:]+: 2480c070 cmphi p0.s, p0/z, z3.s, z0.d
-+[^:]+: 2480c070 cmphi p0.s, p0/z, z3.s, z0.d
-+[^:]+: 2480c3f0 cmphi p0.s, p0/z, z31.s, z0.d
-+[^:]+: 2480c3f0 cmphi p0.s, p0/z, z31.s, z0.d
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-+[^:]+: 2484c010 cmphi p0.s, p0/z, z0.s, z4.d
-+[^:]+: 249fc010 cmphi p0.s, p0/z, z0.s, z31.d
-+[^:]+: 249fc010 cmphi p0.s, p0/z, z0.s, z31.d
-+[^:]+: 24200010 cmphi p0.b, p0/z, z0.b, #0
-+[^:]+: 24200010 cmphi p0.b, p0/z, z0.b, #0
-+[^:]+: 24200011 cmphi p1.b, p0/z, z0.b, #0
-+[^:]+: 24200011 cmphi p1.b, p0/z, z0.b, #0
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-+[^:]+: 2420001f cmphi p15.b, p0/z, z0.b, #0
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-+[^:]+: 24201c10 cmphi p0.b, p7/z, z0.b, #0
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-+[^:]+: 24200070 cmphi p0.b, p0/z, z3.b, #0
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-+[^:]+: 242003f0 cmphi p0.b, p0/z, z31.b, #0
-+[^:]+: 242fc010 cmphi p0.b, p0/z, z0.b, #63
-+[^:]+: 242fc010 cmphi p0.b, p0/z, z0.b, #63
-+[^:]+: 24300010 cmphi p0.b, p0/z, z0.b, #64
-+[^:]+: 24300010 cmphi p0.b, p0/z, z0.b, #64
-+[^:]+: 24304010 cmphi p0.b, p0/z, z0.b, #65
-+[^:]+: 24304010 cmphi p0.b, p0/z, z0.b, #65
-+[^:]+: 243fc010 cmphi p0.b, p0/z, z0.b, #127
-+[^:]+: 243fc010 cmphi p0.b, p0/z, z0.b, #127
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-+[^:]+: 24600010 cmphi p0.h, p0/z, z0.h, #0
-+[^:]+: 24600011 cmphi p1.h, p0/z, z0.h, #0
-+[^:]+: 24600011 cmphi p1.h, p0/z, z0.h, #0
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-+[^:]+: 2460001f cmphi p15.h, p0/z, z0.h, #0
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-+[^:]+: 24600810 cmphi p0.h, p2/z, z0.h, #0
-+[^:]+: 24601c10 cmphi p0.h, p7/z, z0.h, #0
-+[^:]+: 24601c10 cmphi p0.h, p7/z, z0.h, #0
-+[^:]+: 24600070 cmphi p0.h, p0/z, z3.h, #0
-+[^:]+: 24600070 cmphi p0.h, p0/z, z3.h, #0
-+[^:]+: 246003f0 cmphi p0.h, p0/z, z31.h, #0
-+[^:]+: 246003f0 cmphi p0.h, p0/z, z31.h, #0
-+[^:]+: 246fc010 cmphi p0.h, p0/z, z0.h, #63
-+[^:]+: 246fc010 cmphi p0.h, p0/z, z0.h, #63
-+[^:]+: 24700010 cmphi p0.h, p0/z, z0.h, #64
-+[^:]+: 24700010 cmphi p0.h, p0/z, z0.h, #64
-+[^:]+: 24704010 cmphi p0.h, p0/z, z0.h, #65
-+[^:]+: 24704010 cmphi p0.h, p0/z, z0.h, #65
-+[^:]+: 247fc010 cmphi p0.h, p0/z, z0.h, #127
-+[^:]+: 247fc010 cmphi p0.h, p0/z, z0.h, #127
-+[^:]+: 24a00010 cmphi p0.s, p0/z, z0.s, #0
-+[^:]+: 24a00010 cmphi p0.s, p0/z, z0.s, #0
-+[^:]+: 24a00011 cmphi p1.s, p0/z, z0.s, #0
-+[^:]+: 24a00011 cmphi p1.s, p0/z, z0.s, #0
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-+[^:]+: 24a0001f cmphi p15.s, p0/z, z0.s, #0
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-+[^:]+: 24a00810 cmphi p0.s, p2/z, z0.s, #0
-+[^:]+: 24a01c10 cmphi p0.s, p7/z, z0.s, #0
-+[^:]+: 24a01c10 cmphi p0.s, p7/z, z0.s, #0
-+[^:]+: 24a00070 cmphi p0.s, p0/z, z3.s, #0
-+[^:]+: 24a00070 cmphi p0.s, p0/z, z3.s, #0
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-+[^:]+: 24a003f0 cmphi p0.s, p0/z, z31.s, #0
-+[^:]+: 24afc010 cmphi p0.s, p0/z, z0.s, #63
-+[^:]+: 24afc010 cmphi p0.s, p0/z, z0.s, #63
-+[^:]+: 24b00010 cmphi p0.s, p0/z, z0.s, #64
-+[^:]+: 24b00010 cmphi p0.s, p0/z, z0.s, #64
-+[^:]+: 24b04010 cmphi p0.s, p0/z, z0.s, #65
-+[^:]+: 24b04010 cmphi p0.s, p0/z, z0.s, #65
-+[^:]+: 24bfc010 cmphi p0.s, p0/z, z0.s, #127
-+[^:]+: 24bfc010 cmphi p0.s, p0/z, z0.s, #127
-+[^:]+: 24e00010 cmphi p0.d, p0/z, z0.d, #0
-+[^:]+: 24e00010 cmphi p0.d, p0/z, z0.d, #0
-+[^:]+: 24e00011 cmphi p1.d, p0/z, z0.d, #0
-+[^:]+: 24e00011 cmphi p1.d, p0/z, z0.d, #0
-+[^:]+: 24e0001f cmphi p15.d, p0/z, z0.d, #0
-+[^:]+: 24e0001f cmphi p15.d, p0/z, z0.d, #0
-+[^:]+: 24e00810 cmphi p0.d, p2/z, z0.d, #0
-+[^:]+: 24e00810 cmphi p0.d, p2/z, z0.d, #0
-+[^:]+: 24e01c10 cmphi p0.d, p7/z, z0.d, #0
-+[^:]+: 24e01c10 cmphi p0.d, p7/z, z0.d, #0
-+[^:]+: 24e00070 cmphi p0.d, p0/z, z3.d, #0
-+[^:]+: 24e00070 cmphi p0.d, p0/z, z3.d, #0
-+[^:]+: 24e003f0 cmphi p0.d, p0/z, z31.d, #0
-+[^:]+: 24e003f0 cmphi p0.d, p0/z, z31.d, #0
-+[^:]+: 24efc010 cmphi p0.d, p0/z, z0.d, #63
-+[^:]+: 24efc010 cmphi p0.d, p0/z, z0.d, #63
-+[^:]+: 24f00010 cmphi p0.d, p0/z, z0.d, #64
-+[^:]+: 24f00010 cmphi p0.d, p0/z, z0.d, #64
-+[^:]+: 24f04010 cmphi p0.d, p0/z, z0.d, #65
-+[^:]+: 24f04010 cmphi p0.d, p0/z, z0.d, #65
-+[^:]+: 24ffc010 cmphi p0.d, p0/z, z0.d, #127
-+[^:]+: 24ffc010 cmphi p0.d, p0/z, z0.d, #127
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-+[^:]+: 24000000 cmphs p0.b, p0/z, z0.b, z0.b
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-+[^:]+: 24000001 cmphs p1.b, p0/z, z0.b, z0.b
-+[^:]+: 2400000f cmphs p15.b, p0/z, z0.b, z0.b
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-+[^:]+: 241f0000 cmphs p0.b, p0/z, z0.b, z31.b
-+[^:]+: 24400000 cmphs p0.h, p0/z, z0.h, z0.h
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-+[^:]+: 24400001 cmphs p1.h, p0/z, z0.h, z0.h
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-+[^:]+: 2440a010 cmpne p0.h, p0/z, z0.h, z0.h
-+[^:]+: 2440a010 cmpne p0.h, p0/z, z0.h, z0.h
-+[^:]+: 2440a011 cmpne p1.h, p0/z, z0.h, z0.h
-+[^:]+: 2440a011 cmpne p1.h, p0/z, z0.h, z0.h
-+[^:]+: 2440a01f cmpne p15.h, p0/z, z0.h, z0.h
-+[^:]+: 2440a01f cmpne p15.h, p0/z, z0.h, z0.h
-+[^:]+: 2440a810 cmpne p0.h, p2/z, z0.h, z0.h
-+[^:]+: 2440a810 cmpne p0.h, p2/z, z0.h, z0.h
-+[^:]+: 2440bc10 cmpne p0.h, p7/z, z0.h, z0.h
-+[^:]+: 2440bc10 cmpne p0.h, p7/z, z0.h, z0.h
-+[^:]+: 2440a070 cmpne p0.h, p0/z, z3.h, z0.h
-+[^:]+: 2440a070 cmpne p0.h, p0/z, z3.h, z0.h
-+[^:]+: 2440a3f0 cmpne p0.h, p0/z, z31.h, z0.h
-+[^:]+: 2440a3f0 cmpne p0.h, p0/z, z31.h, z0.h
-+[^:]+: 2444a010 cmpne p0.h, p0/z, z0.h, z4.h
-+[^:]+: 2444a010 cmpne p0.h, p0/z, z0.h, z4.h
-+[^:]+: 245fa010 cmpne p0.h, p0/z, z0.h, z31.h
-+[^:]+: 245fa010 cmpne p0.h, p0/z, z0.h, z31.h
-+[^:]+: 2480a010 cmpne p0.s, p0/z, z0.s, z0.s
-+[^:]+: 2480a010 cmpne p0.s, p0/z, z0.s, z0.s
-+[^:]+: 2480a011 cmpne p1.s, p0/z, z0.s, z0.s
-+[^:]+: 2480a011 cmpne p1.s, p0/z, z0.s, z0.s
-+[^:]+: 2480a01f cmpne p15.s, p0/z, z0.s, z0.s
-+[^:]+: 2480a01f cmpne p15.s, p0/z, z0.s, z0.s
-+[^:]+: 2480a810 cmpne p0.s, p2/z, z0.s, z0.s
-+[^:]+: 2480a810 cmpne p0.s, p2/z, z0.s, z0.s
-+[^:]+: 2480bc10 cmpne p0.s, p7/z, z0.s, z0.s
-+[^:]+: 2480bc10 cmpne p0.s, p7/z, z0.s, z0.s
-+[^:]+: 2480a070 cmpne p0.s, p0/z, z3.s, z0.s
-+[^:]+: 2480a070 cmpne p0.s, p0/z, z3.s, z0.s
-+[^:]+: 2480a3f0 cmpne p0.s, p0/z, z31.s, z0.s
-+[^:]+: 2480a3f0 cmpne p0.s, p0/z, z31.s, z0.s
-+[^:]+: 2484a010 cmpne p0.s, p0/z, z0.s, z4.s
-+[^:]+: 2484a010 cmpne p0.s, p0/z, z0.s, z4.s
-+[^:]+: 249fa010 cmpne p0.s, p0/z, z0.s, z31.s
-+[^:]+: 249fa010 cmpne p0.s, p0/z, z0.s, z31.s
-+[^:]+: 24c0a010 cmpne p0.d, p0/z, z0.d, z0.d
-+[^:]+: 24c0a010 cmpne p0.d, p0/z, z0.d, z0.d
-+[^:]+: 24c0a011 cmpne p1.d, p0/z, z0.d, z0.d
-+[^:]+: 24c0a011 cmpne p1.d, p0/z, z0.d, z0.d
-+[^:]+: 24c0a01f cmpne p15.d, p0/z, z0.d, z0.d
-+[^:]+: 24c0a01f cmpne p15.d, p0/z, z0.d, z0.d
-+[^:]+: 24c0a810 cmpne p0.d, p2/z, z0.d, z0.d
-+[^:]+: 24c0a810 cmpne p0.d, p2/z, z0.d, z0.d
-+[^:]+: 24c0bc10 cmpne p0.d, p7/z, z0.d, z0.d
-+[^:]+: 24c0bc10 cmpne p0.d, p7/z, z0.d, z0.d
-+[^:]+: 24c0a070 cmpne p0.d, p0/z, z3.d, z0.d
-+[^:]+: 24c0a070 cmpne p0.d, p0/z, z3.d, z0.d
-+[^:]+: 24c0a3f0 cmpne p0.d, p0/z, z31.d, z0.d
-+[^:]+: 24c0a3f0 cmpne p0.d, p0/z, z31.d, z0.d
-+[^:]+: 24c4a010 cmpne p0.d, p0/z, z0.d, z4.d
-+[^:]+: 24c4a010 cmpne p0.d, p0/z, z0.d, z4.d
-+[^:]+: 24dfa010 cmpne p0.d, p0/z, z0.d, z31.d
-+[^:]+: 24dfa010 cmpne p0.d, p0/z, z0.d, z31.d
-+[^:]+: 25008010 cmpne p0.b, p0/z, z0.b, #0
-+[^:]+: 25008010 cmpne p0.b, p0/z, z0.b, #0
-+[^:]+: 25008011 cmpne p1.b, p0/z, z0.b, #0
-+[^:]+: 25008011 cmpne p1.b, p0/z, z0.b, #0
-+[^:]+: 2500801f cmpne p15.b, p0/z, z0.b, #0
-+[^:]+: 2500801f cmpne p15.b, p0/z, z0.b, #0
-+[^:]+: 25008810 cmpne p0.b, p2/z, z0.b, #0
-+[^:]+: 25008810 cmpne p0.b, p2/z, z0.b, #0
-+[^:]+: 25009c10 cmpne p0.b, p7/z, z0.b, #0
-+[^:]+: 25009c10 cmpne p0.b, p7/z, z0.b, #0
-+[^:]+: 25008070 cmpne p0.b, p0/z, z3.b, #0
-+[^:]+: 25008070 cmpne p0.b, p0/z, z3.b, #0
-+[^:]+: 250083f0 cmpne p0.b, p0/z, z31.b, #0
-+[^:]+: 250083f0 cmpne p0.b, p0/z, z31.b, #0
-+[^:]+: 250f8010 cmpne p0.b, p0/z, z0.b, #15
-+[^:]+: 250f8010 cmpne p0.b, p0/z, z0.b, #15
-+[^:]+: 25108010 cmpne p0.b, p0/z, z0.b, #-16
-+[^:]+: 25108010 cmpne p0.b, p0/z, z0.b, #-16
-+[^:]+: 25118010 cmpne p0.b, p0/z, z0.b, #-15
-+[^:]+: 25118010 cmpne p0.b, p0/z, z0.b, #-15
-+[^:]+: 251f8010 cmpne p0.b, p0/z, z0.b, #-1
-+[^:]+: 251f8010 cmpne p0.b, p0/z, z0.b, #-1
-+[^:]+: 25408010 cmpne p0.h, p0/z, z0.h, #0
-+[^:]+: 25408010 cmpne p0.h, p0/z, z0.h, #0
-+[^:]+: 25408011 cmpne p1.h, p0/z, z0.h, #0
-+[^:]+: 25408011 cmpne p1.h, p0/z, z0.h, #0
-+[^:]+: 2540801f cmpne p15.h, p0/z, z0.h, #0
-+[^:]+: 2540801f cmpne p15.h, p0/z, z0.h, #0
-+[^:]+: 25408810 cmpne p0.h, p2/z, z0.h, #0
-+[^:]+: 25408810 cmpne p0.h, p2/z, z0.h, #0
-+[^:]+: 25409c10 cmpne p0.h, p7/z, z0.h, #0
-+[^:]+: 25409c10 cmpne p0.h, p7/z, z0.h, #0
-+[^:]+: 25408070 cmpne p0.h, p0/z, z3.h, #0
-+[^:]+: 25408070 cmpne p0.h, p0/z, z3.h, #0
-+[^:]+: 254083f0 cmpne p0.h, p0/z, z31.h, #0
-+[^:]+: 254083f0 cmpne p0.h, p0/z, z31.h, #0
-+[^:]+: 254f8010 cmpne p0.h, p0/z, z0.h, #15
-+[^:]+: 254f8010 cmpne p0.h, p0/z, z0.h, #15
-+[^:]+: 25508010 cmpne p0.h, p0/z, z0.h, #-16
-+[^:]+: 25508010 cmpne p0.h, p0/z, z0.h, #-16
-+[^:]+: 25518010 cmpne p0.h, p0/z, z0.h, #-15
-+[^:]+: 25518010 cmpne p0.h, p0/z, z0.h, #-15
-+[^:]+: 255f8010 cmpne p0.h, p0/z, z0.h, #-1
-+[^:]+: 255f8010 cmpne p0.h, p0/z, z0.h, #-1
-+[^:]+: 25808010 cmpne p0.s, p0/z, z0.s, #0
-+[^:]+: 25808010 cmpne p0.s, p0/z, z0.s, #0
-+[^:]+: 25808011 cmpne p1.s, p0/z, z0.s, #0
-+[^:]+: 25808011 cmpne p1.s, p0/z, z0.s, #0
-+[^:]+: 2580801f cmpne p15.s, p0/z, z0.s, #0
-+[^:]+: 2580801f cmpne p15.s, p0/z, z0.s, #0
-+[^:]+: 25808810 cmpne p0.s, p2/z, z0.s, #0
-+[^:]+: 25808810 cmpne p0.s, p2/z, z0.s, #0
-+[^:]+: 25809c10 cmpne p0.s, p7/z, z0.s, #0
-+[^:]+: 25809c10 cmpne p0.s, p7/z, z0.s, #0
-+[^:]+: 25808070 cmpne p0.s, p0/z, z3.s, #0
-+[^:]+: 25808070 cmpne p0.s, p0/z, z3.s, #0
-+[^:]+: 258083f0 cmpne p0.s, p0/z, z31.s, #0
-+[^:]+: 258083f0 cmpne p0.s, p0/z, z31.s, #0
-+[^:]+: 258f8010 cmpne p0.s, p0/z, z0.s, #15
-+[^:]+: 258f8010 cmpne p0.s, p0/z, z0.s, #15
-+[^:]+: 25908010 cmpne p0.s, p0/z, z0.s, #-16
-+[^:]+: 25908010 cmpne p0.s, p0/z, z0.s, #-16
-+[^:]+: 25918010 cmpne p0.s, p0/z, z0.s, #-15
-+[^:]+: 25918010 cmpne p0.s, p0/z, z0.s, #-15
-+[^:]+: 259f8010 cmpne p0.s, p0/z, z0.s, #-1
-+[^:]+: 259f8010 cmpne p0.s, p0/z, z0.s, #-1
-+[^:]+: 25c08010 cmpne p0.d, p0/z, z0.d, #0
-+[^:]+: 25c08010 cmpne p0.d, p0/z, z0.d, #0
-+[^:]+: 25c08011 cmpne p1.d, p0/z, z0.d, #0
-+[^:]+: 25c08011 cmpne p1.d, p0/z, z0.d, #0
-+[^:]+: 25c0801f cmpne p15.d, p0/z, z0.d, #0
-+[^:]+: 25c0801f cmpne p15.d, p0/z, z0.d, #0
-+[^:]+: 25c08810 cmpne p0.d, p2/z, z0.d, #0
-+[^:]+: 25c08810 cmpne p0.d, p2/z, z0.d, #0
-+[^:]+: 25c09c10 cmpne p0.d, p7/z, z0.d, #0
-+[^:]+: 25c09c10 cmpne p0.d, p7/z, z0.d, #0
-+[^:]+: 25c08070 cmpne p0.d, p0/z, z3.d, #0
-+[^:]+: 25c08070 cmpne p0.d, p0/z, z3.d, #0
-+[^:]+: 25c083f0 cmpne p0.d, p0/z, z31.d, #0
-+[^:]+: 25c083f0 cmpne p0.d, p0/z, z31.d, #0
-+[^:]+: 25cf8010 cmpne p0.d, p0/z, z0.d, #15
-+[^:]+: 25cf8010 cmpne p0.d, p0/z, z0.d, #15
-+[^:]+: 25d08010 cmpne p0.d, p0/z, z0.d, #-16
-+[^:]+: 25d08010 cmpne p0.d, p0/z, z0.d, #-16
-+[^:]+: 25d18010 cmpne p0.d, p0/z, z0.d, #-15
-+[^:]+: 25d18010 cmpne p0.d, p0/z, z0.d, #-15
-+[^:]+: 25df8010 cmpne p0.d, p0/z, z0.d, #-1
-+[^:]+: 25df8010 cmpne p0.d, p0/z, z0.d, #-1
-+[^:]+: 041ba000 cnot z0.b, p0/m, z0.b
-+[^:]+: 041ba000 cnot z0.b, p0/m, z0.b
-+[^:]+: 041ba001 cnot z1.b, p0/m, z0.b
-+[^:]+: 041ba001 cnot z1.b, p0/m, z0.b
-+[^:]+: 041ba01f cnot z31.b, p0/m, z0.b
-+[^:]+: 041ba01f cnot z31.b, p0/m, z0.b
-+[^:]+: 041ba800 cnot z0.b, p2/m, z0.b
-+[^:]+: 041ba800 cnot z0.b, p2/m, z0.b
-+[^:]+: 041bbc00 cnot z0.b, p7/m, z0.b
-+[^:]+: 041bbc00 cnot z0.b, p7/m, z0.b
-+[^:]+: 041ba060 cnot z0.b, p0/m, z3.b
-+[^:]+: 041ba060 cnot z0.b, p0/m, z3.b
-+[^:]+: 041ba3e0 cnot z0.b, p0/m, z31.b
-+[^:]+: 041ba3e0 cnot z0.b, p0/m, z31.b
-+[^:]+: 045ba000 cnot z0.h, p0/m, z0.h
-+[^:]+: 045ba000 cnot z0.h, p0/m, z0.h
-+[^:]+: 045ba001 cnot z1.h, p0/m, z0.h
-+[^:]+: 045ba001 cnot z1.h, p0/m, z0.h
-+[^:]+: 045ba01f cnot z31.h, p0/m, z0.h
-+[^:]+: 045ba01f cnot z31.h, p0/m, z0.h
-+[^:]+: 045ba800 cnot z0.h, p2/m, z0.h
-+[^:]+: 045ba800 cnot z0.h, p2/m, z0.h
-+[^:]+: 045bbc00 cnot z0.h, p7/m, z0.h
-+[^:]+: 045bbc00 cnot z0.h, p7/m, z0.h
-+[^:]+: 045ba060 cnot z0.h, p0/m, z3.h
-+[^:]+: 045ba060 cnot z0.h, p0/m, z3.h
-+[^:]+: 045ba3e0 cnot z0.h, p0/m, z31.h
-+[^:]+: 045ba3e0 cnot z0.h, p0/m, z31.h
-+[^:]+: 049ba000 cnot z0.s, p0/m, z0.s
-+[^:]+: 049ba000 cnot z0.s, p0/m, z0.s
-+[^:]+: 049ba001 cnot z1.s, p0/m, z0.s
-+[^:]+: 049ba001 cnot z1.s, p0/m, z0.s
-+[^:]+: 049ba01f cnot z31.s, p0/m, z0.s
-+[^:]+: 049ba01f cnot z31.s, p0/m, z0.s
-+[^:]+: 049ba800 cnot z0.s, p2/m, z0.s
-+[^:]+: 049ba800 cnot z0.s, p2/m, z0.s
-+[^:]+: 049bbc00 cnot z0.s, p7/m, z0.s
-+[^:]+: 049bbc00 cnot z0.s, p7/m, z0.s
-+[^:]+: 049ba060 cnot z0.s, p0/m, z3.s
-+[^:]+: 049ba060 cnot z0.s, p0/m, z3.s
-+[^:]+: 049ba3e0 cnot z0.s, p0/m, z31.s
-+[^:]+: 049ba3e0 cnot z0.s, p0/m, z31.s
-+[^:]+: 04dba000 cnot z0.d, p0/m, z0.d
-+[^:]+: 04dba000 cnot z0.d, p0/m, z0.d
-+[^:]+: 04dba001 cnot z1.d, p0/m, z0.d
-+[^:]+: 04dba001 cnot z1.d, p0/m, z0.d
-+[^:]+: 04dba01f cnot z31.d, p0/m, z0.d
-+[^:]+: 04dba01f cnot z31.d, p0/m, z0.d
-+[^:]+: 04dba800 cnot z0.d, p2/m, z0.d
-+[^:]+: 04dba800 cnot z0.d, p2/m, z0.d
-+[^:]+: 04dbbc00 cnot z0.d, p7/m, z0.d
-+[^:]+: 04dbbc00 cnot z0.d, p7/m, z0.d
-+[^:]+: 04dba060 cnot z0.d, p0/m, z3.d
-+[^:]+: 04dba060 cnot z0.d, p0/m, z3.d
-+[^:]+: 04dba3e0 cnot z0.d, p0/m, z31.d
-+[^:]+: 04dba3e0 cnot z0.d, p0/m, z31.d
-+[^:]+: 041aa000 cnt z0.b, p0/m, z0.b
-+[^:]+: 041aa000 cnt z0.b, p0/m, z0.b
-+[^:]+: 041aa001 cnt z1.b, p0/m, z0.b
-+[^:]+: 041aa001 cnt z1.b, p0/m, z0.b
-+[^:]+: 041aa01f cnt z31.b, p0/m, z0.b
-+[^:]+: 041aa01f cnt z31.b, p0/m, z0.b
-+[^:]+: 041aa800 cnt z0.b, p2/m, z0.b
-+[^:]+: 041aa800 cnt z0.b, p2/m, z0.b
-+[^:]+: 041abc00 cnt z0.b, p7/m, z0.b
-+[^:]+: 041abc00 cnt z0.b, p7/m, z0.b
-+[^:]+: 041aa060 cnt z0.b, p0/m, z3.b
-+[^:]+: 041aa060 cnt z0.b, p0/m, z3.b
-+[^:]+: 041aa3e0 cnt z0.b, p0/m, z31.b
-+[^:]+: 041aa3e0 cnt z0.b, p0/m, z31.b
-+[^:]+: 045aa000 cnt z0.h, p0/m, z0.h
-+[^:]+: 045aa000 cnt z0.h, p0/m, z0.h
-+[^:]+: 045aa001 cnt z1.h, p0/m, z0.h
-+[^:]+: 045aa001 cnt z1.h, p0/m, z0.h
-+[^:]+: 045aa01f cnt z31.h, p0/m, z0.h
-+[^:]+: 045aa01f cnt z31.h, p0/m, z0.h
-+[^:]+: 045aa800 cnt z0.h, p2/m, z0.h
-+[^:]+: 045aa800 cnt z0.h, p2/m, z0.h
-+[^:]+: 045abc00 cnt z0.h, p7/m, z0.h
-+[^:]+: 045abc00 cnt z0.h, p7/m, z0.h
-+[^:]+: 045aa060 cnt z0.h, p0/m, z3.h
-+[^:]+: 045aa060 cnt z0.h, p0/m, z3.h
-+[^:]+: 045aa3e0 cnt z0.h, p0/m, z31.h
-+[^:]+: 045aa3e0 cnt z0.h, p0/m, z31.h
-+[^:]+: 049aa000 cnt z0.s, p0/m, z0.s
-+[^:]+: 049aa000 cnt z0.s, p0/m, z0.s
-+[^:]+: 049aa001 cnt z1.s, p0/m, z0.s
-+[^:]+: 049aa001 cnt z1.s, p0/m, z0.s
-+[^:]+: 049aa01f cnt z31.s, p0/m, z0.s
-+[^:]+: 049aa01f cnt z31.s, p0/m, z0.s
-+[^:]+: 049aa800 cnt z0.s, p2/m, z0.s
-+[^:]+: 049aa800 cnt z0.s, p2/m, z0.s
-+[^:]+: 049abc00 cnt z0.s, p7/m, z0.s
-+[^:]+: 049abc00 cnt z0.s, p7/m, z0.s
-+[^:]+: 049aa060 cnt z0.s, p0/m, z3.s
-+[^:]+: 049aa060 cnt z0.s, p0/m, z3.s
-+[^:]+: 049aa3e0 cnt z0.s, p0/m, z31.s
-+[^:]+: 049aa3e0 cnt z0.s, p0/m, z31.s
-+[^:]+: 04daa000 cnt z0.d, p0/m, z0.d
-+[^:]+: 04daa000 cnt z0.d, p0/m, z0.d
-+[^:]+: 04daa001 cnt z1.d, p0/m, z0.d
-+[^:]+: 04daa001 cnt z1.d, p0/m, z0.d
-+[^:]+: 04daa01f cnt z31.d, p0/m, z0.d
-+[^:]+: 04daa01f cnt z31.d, p0/m, z0.d
-+[^:]+: 04daa800 cnt z0.d, p2/m, z0.d
-+[^:]+: 04daa800 cnt z0.d, p2/m, z0.d
-+[^:]+: 04dabc00 cnt z0.d, p7/m, z0.d
-+[^:]+: 04dabc00 cnt z0.d, p7/m, z0.d
-+[^:]+: 04daa060 cnt z0.d, p0/m, z3.d
-+[^:]+: 04daa060 cnt z0.d, p0/m, z3.d
-+[^:]+: 04daa3e0 cnt z0.d, p0/m, z31.d
-+[^:]+: 04daa3e0 cnt z0.d, p0/m, z31.d
-+[^:]+: 0420e000 cntb x0, pow2
-+[^:]+: 0420e000 cntb x0, pow2
-+[^:]+: 0420e000 cntb x0, pow2
-+[^:]+: 0420e001 cntb x1, pow2
-+[^:]+: 0420e001 cntb x1, pow2
-+[^:]+: 0420e001 cntb x1, pow2
-+[^:]+: 0420e01f cntb xzr, pow2
-+[^:]+: 0420e01f cntb xzr, pow2
-+[^:]+: 0420e01f cntb xzr, pow2
-+[^:]+: 0420e020 cntb x0, vl1
-+[^:]+: 0420e020 cntb x0, vl1
-+[^:]+: 0420e020 cntb x0, vl1
-+[^:]+: 0420e040 cntb x0, vl2
-+[^:]+: 0420e040 cntb x0, vl2
-+[^:]+: 0420e040 cntb x0, vl2
-+[^:]+: 0420e060 cntb x0, vl3
-+[^:]+: 0420e060 cntb x0, vl3
-+[^:]+: 0420e060 cntb x0, vl3
-+[^:]+: 0420e080 cntb x0, vl4
-+[^:]+: 0420e080 cntb x0, vl4
-+[^:]+: 0420e080 cntb x0, vl4
-+[^:]+: 0420e0a0 cntb x0, vl5
-+[^:]+: 0420e0a0 cntb x0, vl5
-+[^:]+: 0420e0a0 cntb x0, vl5
-+[^:]+: 0420e0c0 cntb x0, vl6
-+[^:]+: 0420e0c0 cntb x0, vl6
-+[^:]+: 0420e0c0 cntb x0, vl6
-+[^:]+: 0420e0e0 cntb x0, vl7
-+[^:]+: 0420e0e0 cntb x0, vl7
-+[^:]+: 0420e0e0 cntb x0, vl7
-+[^:]+: 0420e100 cntb x0, vl8
-+[^:]+: 0420e100 cntb x0, vl8
-+[^:]+: 0420e100 cntb x0, vl8
-+[^:]+: 0420e120 cntb x0, vl16
-+[^:]+: 0420e120 cntb x0, vl16
-+[^:]+: 0420e120 cntb x0, vl16
-+[^:]+: 0420e140 cntb x0, vl32
-+[^:]+: 0420e140 cntb x0, vl32
-+[^:]+: 0420e140 cntb x0, vl32
-+[^:]+: 0420e160 cntb x0, vl64
-+[^:]+: 0420e160 cntb x0, vl64
-+[^:]+: 0420e160 cntb x0, vl64
-+[^:]+: 0420e180 cntb x0, vl128
-+[^:]+: 0420e180 cntb x0, vl128
-+[^:]+: 0420e180 cntb x0, vl128
-+[^:]+: 0420e1a0 cntb x0, vl256
-+[^:]+: 0420e1a0 cntb x0, vl256
-+[^:]+: 0420e1a0 cntb x0, vl256
-+[^:]+: 0420e1c0 cntb x0, #14
-+[^:]+: 0420e1c0 cntb x0, #14
-+[^:]+: 0420e1c0 cntb x0, #14
-+[^:]+: 0420e1e0 cntb x0, #15
-+[^:]+: 0420e1e0 cntb x0, #15
-+[^:]+: 0420e1e0 cntb x0, #15
-+[^:]+: 0420e200 cntb x0, #16
-+[^:]+: 0420e200 cntb x0, #16
-+[^:]+: 0420e200 cntb x0, #16
-+[^:]+: 0420e220 cntb x0, #17
-+[^:]+: 0420e220 cntb x0, #17
-+[^:]+: 0420e220 cntb x0, #17
-+[^:]+: 0420e240 cntb x0, #18
-+[^:]+: 0420e240 cntb x0, #18
-+[^:]+: 0420e240 cntb x0, #18
-+[^:]+: 0420e260 cntb x0, #19
-+[^:]+: 0420e260 cntb x0, #19
-+[^:]+: 0420e260 cntb x0, #19
-+[^:]+: 0420e280 cntb x0, #20
-+[^:]+: 0420e280 cntb x0, #20
-+[^:]+: 0420e280 cntb x0, #20
-+[^:]+: 0420e2a0 cntb x0, #21
-+[^:]+: 0420e2a0 cntb x0, #21
-+[^:]+: 0420e2a0 cntb x0, #21
-+[^:]+: 0420e2c0 cntb x0, #22
-+[^:]+: 0420e2c0 cntb x0, #22
-+[^:]+: 0420e2c0 cntb x0, #22
-+[^:]+: 0420e2e0 cntb x0, #23
-+[^:]+: 0420e2e0 cntb x0, #23
-+[^:]+: 0420e2e0 cntb x0, #23
-+[^:]+: 0420e300 cntb x0, #24
-+[^:]+: 0420e300 cntb x0, #24
-+[^:]+: 0420e300 cntb x0, #24
-+[^:]+: 0420e320 cntb x0, #25
-+[^:]+: 0420e320 cntb x0, #25
-+[^:]+: 0420e320 cntb x0, #25
-+[^:]+: 0420e340 cntb x0, #26
-+[^:]+: 0420e340 cntb x0, #26
-+[^:]+: 0420e340 cntb x0, #26
-+[^:]+: 0420e360 cntb x0, #27
-+[^:]+: 0420e360 cntb x0, #27
-+[^:]+: 0420e360 cntb x0, #27
-+[^:]+: 0420e380 cntb x0, #28
-+[^:]+: 0420e380 cntb x0, #28
-+[^:]+: 0420e380 cntb x0, #28
-+[^:]+: 0420e3a0 cntb x0, mul4
-+[^:]+: 0420e3a0 cntb x0, mul4
-+[^:]+: 0420e3a0 cntb x0, mul4
-+[^:]+: 0420e3c0 cntb x0, mul3
-+[^:]+: 0420e3c0 cntb x0, mul3
-+[^:]+: 0420e3c0 cntb x0, mul3
-+[^:]+: 0420e3e0 cntb x0
-+[^:]+: 0420e3e0 cntb x0
-+[^:]+: 0420e3e0 cntb x0
-+[^:]+: 0420e3e0 cntb x0
-+[^:]+: 0427e000 cntb x0, pow2, mul #8
-+[^:]+: 0427e000 cntb x0, pow2, mul #8
-+[^:]+: 0428e000 cntb x0, pow2, mul #9
-+[^:]+: 0428e000 cntb x0, pow2, mul #9
-+[^:]+: 0429e000 cntb x0, pow2, mul #10
-+[^:]+: 0429e000 cntb x0, pow2, mul #10
-+[^:]+: 042fe000 cntb x0, pow2, mul #16
-+[^:]+: 042fe000 cntb x0, pow2, mul #16
-+[^:]+: 04e0e000 cntd x0, pow2
-+[^:]+: 04e0e000 cntd x0, pow2
-+[^:]+: 04e0e000 cntd x0, pow2
-+[^:]+: 04e0e001 cntd x1, pow2
-+[^:]+: 04e0e001 cntd x1, pow2
-+[^:]+: 04e0e001 cntd x1, pow2
-+[^:]+: 04e0e01f cntd xzr, pow2
-+[^:]+: 04e0e01f cntd xzr, pow2
-+[^:]+: 04e0e01f cntd xzr, pow2
-+[^:]+: 04e0e020 cntd x0, vl1
-+[^:]+: 04e0e020 cntd x0, vl1
-+[^:]+: 04e0e020 cntd x0, vl1
-+[^:]+: 04e0e040 cntd x0, vl2
-+[^:]+: 04e0e040 cntd x0, vl2
-+[^:]+: 04e0e040 cntd x0, vl2
-+[^:]+: 04e0e060 cntd x0, vl3
-+[^:]+: 04e0e060 cntd x0, vl3
-+[^:]+: 04e0e060 cntd x0, vl3
-+[^:]+: 04e0e080 cntd x0, vl4
-+[^:]+: 04e0e080 cntd x0, vl4
-+[^:]+: 04e0e080 cntd x0, vl4
-+[^:]+: 04e0e0a0 cntd x0, vl5
-+[^:]+: 04e0e0a0 cntd x0, vl5
-+[^:]+: 04e0e0a0 cntd x0, vl5
-+[^:]+: 04e0e0c0 cntd x0, vl6
-+[^:]+: 04e0e0c0 cntd x0, vl6
-+[^:]+: 04e0e0c0 cntd x0, vl6
-+[^:]+: 04e0e0e0 cntd x0, vl7
-+[^:]+: 04e0e0e0 cntd x0, vl7
-+[^:]+: 04e0e0e0 cntd x0, vl7
-+[^:]+: 04e0e100 cntd x0, vl8
-+[^:]+: 04e0e100 cntd x0, vl8
-+[^:]+: 04e0e100 cntd x0, vl8
-+[^:]+: 04e0e120 cntd x0, vl16
-+[^:]+: 04e0e120 cntd x0, vl16
-+[^:]+: 04e0e120 cntd x0, vl16
-+[^:]+: 04e0e140 cntd x0, vl32
-+[^:]+: 04e0e140 cntd x0, vl32
-+[^:]+: 04e0e140 cntd x0, vl32
-+[^:]+: 04e0e160 cntd x0, vl64
-+[^:]+: 04e0e160 cntd x0, vl64
-+[^:]+: 04e0e160 cntd x0, vl64
-+[^:]+: 04e0e180 cntd x0, vl128
-+[^:]+: 04e0e180 cntd x0, vl128
-+[^:]+: 04e0e180 cntd x0, vl128
-+[^:]+: 04e0e1a0 cntd x0, vl256
-+[^:]+: 04e0e1a0 cntd x0, vl256
-+[^:]+: 04e0e1a0 cntd x0, vl256
-+[^:]+: 04e0e1c0 cntd x0, #14
-+[^:]+: 04e0e1c0 cntd x0, #14
-+[^:]+: 04e0e1c0 cntd x0, #14
-+[^:]+: 04e0e1e0 cntd x0, #15
-+[^:]+: 04e0e1e0 cntd x0, #15
-+[^:]+: 04e0e1e0 cntd x0, #15
-+[^:]+: 04e0e200 cntd x0, #16
-+[^:]+: 04e0e200 cntd x0, #16
-+[^:]+: 04e0e200 cntd x0, #16
-+[^:]+: 04e0e220 cntd x0, #17
-+[^:]+: 04e0e220 cntd x0, #17
-+[^:]+: 04e0e220 cntd x0, #17
-+[^:]+: 04e0e240 cntd x0, #18
-+[^:]+: 04e0e240 cntd x0, #18
-+[^:]+: 04e0e240 cntd x0, #18
-+[^:]+: 04e0e260 cntd x0, #19
-+[^:]+: 04e0e260 cntd x0, #19
-+[^:]+: 04e0e260 cntd x0, #19
-+[^:]+: 04e0e280 cntd x0, #20
-+[^:]+: 04e0e280 cntd x0, #20
-+[^:]+: 04e0e280 cntd x0, #20
-+[^:]+: 04e0e2a0 cntd x0, #21
-+[^:]+: 04e0e2a0 cntd x0, #21
-+[^:]+: 04e0e2a0 cntd x0, #21
-+[^:]+: 04e0e2c0 cntd x0, #22
-+[^:]+: 04e0e2c0 cntd x0, #22
-+[^:]+: 04e0e2c0 cntd x0, #22
-+[^:]+: 04e0e2e0 cntd x0, #23
-+[^:]+: 04e0e2e0 cntd x0, #23
-+[^:]+: 04e0e2e0 cntd x0, #23
-+[^:]+: 04e0e300 cntd x0, #24
-+[^:]+: 04e0e300 cntd x0, #24
-+[^:]+: 04e0e300 cntd x0, #24
-+[^:]+: 04e0e320 cntd x0, #25
-+[^:]+: 04e0e320 cntd x0, #25
-+[^:]+: 04e0e320 cntd x0, #25
-+[^:]+: 04e0e340 cntd x0, #26
-+[^:]+: 04e0e340 cntd x0, #26
-+[^:]+: 04e0e340 cntd x0, #26
-+[^:]+: 04e0e360 cntd x0, #27
-+[^:]+: 04e0e360 cntd x0, #27
-+[^:]+: 04e0e360 cntd x0, #27
-+[^:]+: 04e0e380 cntd x0, #28
-+[^:]+: 04e0e380 cntd x0, #28
-+[^:]+: 04e0e380 cntd x0, #28
-+[^:]+: 04e0e3a0 cntd x0, mul4
-+[^:]+: 04e0e3a0 cntd x0, mul4
-+[^:]+: 04e0e3a0 cntd x0, mul4
-+[^:]+: 04e0e3c0 cntd x0, mul3
-+[^:]+: 04e0e3c0 cntd x0, mul3
-+[^:]+: 04e0e3c0 cntd x0, mul3
-+[^:]+: 04e0e3e0 cntd x0
-+[^:]+: 04e0e3e0 cntd x0
-+[^:]+: 04e0e3e0 cntd x0
-+[^:]+: 04e0e3e0 cntd x0
-+[^:]+: 04e7e000 cntd x0, pow2, mul #8
-+[^:]+: 04e7e000 cntd x0, pow2, mul #8
-+[^:]+: 04e8e000 cntd x0, pow2, mul #9
-+[^:]+: 04e8e000 cntd x0, pow2, mul #9
-+[^:]+: 04e9e000 cntd x0, pow2, mul #10
-+[^:]+: 04e9e000 cntd x0, pow2, mul #10
-+[^:]+: 04efe000 cntd x0, pow2, mul #16
-+[^:]+: 04efe000 cntd x0, pow2, mul #16
-+[^:]+: 0460e000 cnth x0, pow2
-+[^:]+: 0460e000 cnth x0, pow2
-+[^:]+: 0460e000 cnth x0, pow2
-+[^:]+: 0460e001 cnth x1, pow2
-+[^:]+: 0460e001 cnth x1, pow2
-+[^:]+: 0460e001 cnth x1, pow2
-+[^:]+: 0460e01f cnth xzr, pow2
-+[^:]+: 0460e01f cnth xzr, pow2
-+[^:]+: 0460e01f cnth xzr, pow2
-+[^:]+: 0460e020 cnth x0, vl1
-+[^:]+: 0460e020 cnth x0, vl1
-+[^:]+: 0460e020 cnth x0, vl1
-+[^:]+: 0460e040 cnth x0, vl2
-+[^:]+: 0460e040 cnth x0, vl2
-+[^:]+: 0460e040 cnth x0, vl2
-+[^:]+: 0460e060 cnth x0, vl3
-+[^:]+: 0460e060 cnth x0, vl3
-+[^:]+: 0460e060 cnth x0, vl3
-+[^:]+: 0460e080 cnth x0, vl4
-+[^:]+: 0460e080 cnth x0, vl4
-+[^:]+: 0460e080 cnth x0, vl4
-+[^:]+: 0460e0a0 cnth x0, vl5
-+[^:]+: 0460e0a0 cnth x0, vl5
-+[^:]+: 0460e0a0 cnth x0, vl5
-+[^:]+: 0460e0c0 cnth x0, vl6
-+[^:]+: 0460e0c0 cnth x0, vl6
-+[^:]+: 0460e0c0 cnth x0, vl6
-+[^:]+: 0460e0e0 cnth x0, vl7
-+[^:]+: 0460e0e0 cnth x0, vl7
-+[^:]+: 0460e0e0 cnth x0, vl7
-+[^:]+: 0460e100 cnth x0, vl8
-+[^:]+: 0460e100 cnth x0, vl8
-+[^:]+: 0460e100 cnth x0, vl8
-+[^:]+: 0460e120 cnth x0, vl16
-+[^:]+: 0460e120 cnth x0, vl16
-+[^:]+: 0460e120 cnth x0, vl16
-+[^:]+: 0460e140 cnth x0, vl32
-+[^:]+: 0460e140 cnth x0, vl32
-+[^:]+: 0460e140 cnth x0, vl32
-+[^:]+: 0460e160 cnth x0, vl64
-+[^:]+: 0460e160 cnth x0, vl64
-+[^:]+: 0460e160 cnth x0, vl64
-+[^:]+: 0460e180 cnth x0, vl128
-+[^:]+: 0460e180 cnth x0, vl128
-+[^:]+: 0460e180 cnth x0, vl128
-+[^:]+: 0460e1a0 cnth x0, vl256
-+[^:]+: 0460e1a0 cnth x0, vl256
-+[^:]+: 0460e1a0 cnth x0, vl256
-+[^:]+: 0460e1c0 cnth x0, #14
-+[^:]+: 0460e1c0 cnth x0, #14
-+[^:]+: 0460e1c0 cnth x0, #14
-+[^:]+: 0460e1e0 cnth x0, #15
-+[^:]+: 0460e1e0 cnth x0, #15
-+[^:]+: 0460e1e0 cnth x0, #15
-+[^:]+: 0460e200 cnth x0, #16
-+[^:]+: 0460e200 cnth x0, #16
-+[^:]+: 0460e200 cnth x0, #16
-+[^:]+: 0460e220 cnth x0, #17
-+[^:]+: 0460e220 cnth x0, #17
-+[^:]+: 0460e220 cnth x0, #17
-+[^:]+: 0460e240 cnth x0, #18
-+[^:]+: 0460e240 cnth x0, #18
-+[^:]+: 0460e240 cnth x0, #18
-+[^:]+: 0460e260 cnth x0, #19
-+[^:]+: 0460e260 cnth x0, #19
-+[^:]+: 0460e260 cnth x0, #19
-+[^:]+: 0460e280 cnth x0, #20
-+[^:]+: 0460e280 cnth x0, #20
-+[^:]+: 0460e280 cnth x0, #20
-+[^:]+: 0460e2a0 cnth x0, #21
-+[^:]+: 0460e2a0 cnth x0, #21
-+[^:]+: 0460e2a0 cnth x0, #21
-+[^:]+: 0460e2c0 cnth x0, #22
-+[^:]+: 0460e2c0 cnth x0, #22
-+[^:]+: 0460e2c0 cnth x0, #22
-+[^:]+: 0460e2e0 cnth x0, #23
-+[^:]+: 0460e2e0 cnth x0, #23
-+[^:]+: 0460e2e0 cnth x0, #23
-+[^:]+: 0460e300 cnth x0, #24
-+[^:]+: 0460e300 cnth x0, #24
-+[^:]+: 0460e300 cnth x0, #24
-+[^:]+: 0460e320 cnth x0, #25
-+[^:]+: 0460e320 cnth x0, #25
-+[^:]+: 0460e320 cnth x0, #25
-+[^:]+: 0460e340 cnth x0, #26
-+[^:]+: 0460e340 cnth x0, #26
-+[^:]+: 0460e340 cnth x0, #26
-+[^:]+: 0460e360 cnth x0, #27
-+[^:]+: 0460e360 cnth x0, #27
-+[^:]+: 0460e360 cnth x0, #27
-+[^:]+: 0460e380 cnth x0, #28
-+[^:]+: 0460e380 cnth x0, #28
-+[^:]+: 0460e380 cnth x0, #28
-+[^:]+: 0460e3a0 cnth x0, mul4
-+[^:]+: 0460e3a0 cnth x0, mul4
-+[^:]+: 0460e3a0 cnth x0, mul4
-+[^:]+: 0460e3c0 cnth x0, mul3
-+[^:]+: 0460e3c0 cnth x0, mul3
-+[^:]+: 0460e3c0 cnth x0, mul3
-+[^:]+: 0460e3e0 cnth x0
-+[^:]+: 0460e3e0 cnth x0
-+[^:]+: 0460e3e0 cnth x0
-+[^:]+: 0460e3e0 cnth x0
-+[^:]+: 0467e000 cnth x0, pow2, mul #8
-+[^:]+: 0467e000 cnth x0, pow2, mul #8
-+[^:]+: 0468e000 cnth x0, pow2, mul #9
-+[^:]+: 0468e000 cnth x0, pow2, mul #9
-+[^:]+: 0469e000 cnth x0, pow2, mul #10
-+[^:]+: 0469e000 cnth x0, pow2, mul #10
-+[^:]+: 046fe000 cnth x0, pow2, mul #16
-+[^:]+: 046fe000 cnth x0, pow2, mul #16
-+[^:]+: 25208000 cntp x0, p0, p0.b
-+[^:]+: 25208000 cntp x0, p0, p0.b
-+[^:]+: 25208001 cntp x1, p0, p0.b
-+[^:]+: 25208001 cntp x1, p0, p0.b
-+[^:]+: 2520801f cntp xzr, p0, p0.b
-+[^:]+: 2520801f cntp xzr, p0, p0.b
-+[^:]+: 25208800 cntp x0, p2, p0.b
-+[^:]+: 25208800 cntp x0, p2, p0.b
-+[^:]+: 2520bc00 cntp x0, p15, p0.b
-+[^:]+: 2520bc00 cntp x0, p15, p0.b
-+[^:]+: 25208060 cntp x0, p0, p3.b
-+[^:]+: 25208060 cntp x0, p0, p3.b
-+[^:]+: 252081e0 cntp x0, p0, p15.b
-+[^:]+: 252081e0 cntp x0, p0, p15.b
-+[^:]+: 25608000 cntp x0, p0, p0.h
-+[^:]+: 25608000 cntp x0, p0, p0.h
-+[^:]+: 25608001 cntp x1, p0, p0.h
-+[^:]+: 25608001 cntp x1, p0, p0.h
-+[^:]+: 2560801f cntp xzr, p0, p0.h
-+[^:]+: 2560801f cntp xzr, p0, p0.h
-+[^:]+: 25608800 cntp x0, p2, p0.h
-+[^:]+: 25608800 cntp x0, p2, p0.h
-+[^:]+: 2560bc00 cntp x0, p15, p0.h
-+[^:]+: 2560bc00 cntp x0, p15, p0.h
-+[^:]+: 25608060 cntp x0, p0, p3.h
-+[^:]+: 25608060 cntp x0, p0, p3.h
-+[^:]+: 256081e0 cntp x0, p0, p15.h
-+[^:]+: 256081e0 cntp x0, p0, p15.h
-+[^:]+: 25a08000 cntp x0, p0, p0.s
-+[^:]+: 25a08000 cntp x0, p0, p0.s
-+[^:]+: 25a08001 cntp x1, p0, p0.s
-+[^:]+: 25a08001 cntp x1, p0, p0.s
-+[^:]+: 25a0801f cntp xzr, p0, p0.s
-+[^:]+: 25a0801f cntp xzr, p0, p0.s
-+[^:]+: 25a08800 cntp x0, p2, p0.s
-+[^:]+: 25a08800 cntp x0, p2, p0.s
-+[^:]+: 25a0bc00 cntp x0, p15, p0.s
-+[^:]+: 25a0bc00 cntp x0, p15, p0.s
-+[^:]+: 25a08060 cntp x0, p0, p3.s
-+[^:]+: 25a08060 cntp x0, p0, p3.s
-+[^:]+: 25a081e0 cntp x0, p0, p15.s
-+[^:]+: 25a081e0 cntp x0, p0, p15.s
-+[^:]+: 25e08000 cntp x0, p0, p0.d
-+[^:]+: 25e08000 cntp x0, p0, p0.d
-+[^:]+: 25e08001 cntp x1, p0, p0.d
-+[^:]+: 25e08001 cntp x1, p0, p0.d
-+[^:]+: 25e0801f cntp xzr, p0, p0.d
-+[^:]+: 25e0801f cntp xzr, p0, p0.d
-+[^:]+: 25e08800 cntp x0, p2, p0.d
-+[^:]+: 25e08800 cntp x0, p2, p0.d
-+[^:]+: 25e0bc00 cntp x0, p15, p0.d
-+[^:]+: 25e0bc00 cntp x0, p15, p0.d
-+[^:]+: 25e08060 cntp x0, p0, p3.d
-+[^:]+: 25e08060 cntp x0, p0, p3.d
-+[^:]+: 25e081e0 cntp x0, p0, p15.d
-+[^:]+: 25e081e0 cntp x0, p0, p15.d
-+[^:]+: 04a0e000 cntw x0, pow2
-+[^:]+: 04a0e000 cntw x0, pow2
-+[^:]+: 04a0e000 cntw x0, pow2
-+[^:]+: 04a0e001 cntw x1, pow2
-+[^:]+: 04a0e001 cntw x1, pow2
-+[^:]+: 04a0e001 cntw x1, pow2
-+[^:]+: 04a0e01f cntw xzr, pow2
-+[^:]+: 04a0e01f cntw xzr, pow2
-+[^:]+: 04a0e01f cntw xzr, pow2
-+[^:]+: 04a0e020 cntw x0, vl1
-+[^:]+: 04a0e020 cntw x0, vl1
-+[^:]+: 04a0e020 cntw x0, vl1
-+[^:]+: 04a0e040 cntw x0, vl2
-+[^:]+: 04a0e040 cntw x0, vl2
-+[^:]+: 04a0e040 cntw x0, vl2
-+[^:]+: 04a0e060 cntw x0, vl3
-+[^:]+: 04a0e060 cntw x0, vl3
-+[^:]+: 04a0e060 cntw x0, vl3
-+[^:]+: 04a0e080 cntw x0, vl4
-+[^:]+: 04a0e080 cntw x0, vl4
-+[^:]+: 04a0e080 cntw x0, vl4
-+[^:]+: 04a0e0a0 cntw x0, vl5
-+[^:]+: 04a0e0a0 cntw x0, vl5
-+[^:]+: 04a0e0a0 cntw x0, vl5
-+[^:]+: 04a0e0c0 cntw x0, vl6
-+[^:]+: 04a0e0c0 cntw x0, vl6
-+[^:]+: 04a0e0c0 cntw x0, vl6
-+[^:]+: 04a0e0e0 cntw x0, vl7
-+[^:]+: 04a0e0e0 cntw x0, vl7
-+[^:]+: 04a0e0e0 cntw x0, vl7
-+[^:]+: 04a0e100 cntw x0, vl8
-+[^:]+: 04a0e100 cntw x0, vl8
-+[^:]+: 04a0e100 cntw x0, vl8
-+[^:]+: 04a0e120 cntw x0, vl16
-+[^:]+: 04a0e120 cntw x0, vl16
-+[^:]+: 04a0e120 cntw x0, vl16
-+[^:]+: 04a0e140 cntw x0, vl32
-+[^:]+: 04a0e140 cntw x0, vl32
-+[^:]+: 04a0e140 cntw x0, vl32
-+[^:]+: 04a0e160 cntw x0, vl64
-+[^:]+: 04a0e160 cntw x0, vl64
-+[^:]+: 04a0e160 cntw x0, vl64
-+[^:]+: 04a0e180 cntw x0, vl128
-+[^:]+: 04a0e180 cntw x0, vl128
-+[^:]+: 04a0e180 cntw x0, vl128
-+[^:]+: 04a0e1a0 cntw x0, vl256
-+[^:]+: 04a0e1a0 cntw x0, vl256
-+[^:]+: 04a0e1a0 cntw x0, vl256
-+[^:]+: 04a0e1c0 cntw x0, #14
-+[^:]+: 04a0e1c0 cntw x0, #14
-+[^:]+: 04a0e1c0 cntw x0, #14
-+[^:]+: 04a0e1e0 cntw x0, #15
-+[^:]+: 04a0e1e0 cntw x0, #15
-+[^:]+: 04a0e1e0 cntw x0, #15
-+[^:]+: 04a0e200 cntw x0, #16
-+[^:]+: 04a0e200 cntw x0, #16
-+[^:]+: 04a0e200 cntw x0, #16
-+[^:]+: 04a0e220 cntw x0, #17
-+[^:]+: 04a0e220 cntw x0, #17
-+[^:]+: 04a0e220 cntw x0, #17
-+[^:]+: 04a0e240 cntw x0, #18
-+[^:]+: 04a0e240 cntw x0, #18
-+[^:]+: 04a0e240 cntw x0, #18
-+[^:]+: 04a0e260 cntw x0, #19
-+[^:]+: 04a0e260 cntw x0, #19
-+[^:]+: 04a0e260 cntw x0, #19
-+[^:]+: 04a0e280 cntw x0, #20
-+[^:]+: 04a0e280 cntw x0, #20
-+[^:]+: 04a0e280 cntw x0, #20
-+[^:]+: 04a0e2a0 cntw x0, #21
-+[^:]+: 04a0e2a0 cntw x0, #21
-+[^:]+: 04a0e2a0 cntw x0, #21
-+[^:]+: 04a0e2c0 cntw x0, #22
-+[^:]+: 04a0e2c0 cntw x0, #22
-+[^:]+: 04a0e2c0 cntw x0, #22
-+[^:]+: 04a0e2e0 cntw x0, #23
-+[^:]+: 04a0e2e0 cntw x0, #23
-+[^:]+: 04a0e2e0 cntw x0, #23
-+[^:]+: 04a0e300 cntw x0, #24
-+[^:]+: 04a0e300 cntw x0, #24
-+[^:]+: 04a0e300 cntw x0, #24
-+[^:]+: 04a0e320 cntw x0, #25
-+[^:]+: 04a0e320 cntw x0, #25
-+[^:]+: 04a0e320 cntw x0, #25
-+[^:]+: 04a0e340 cntw x0, #26
-+[^:]+: 04a0e340 cntw x0, #26
-+[^:]+: 04a0e340 cntw x0, #26
-+[^:]+: 04a0e360 cntw x0, #27
-+[^:]+: 04a0e360 cntw x0, #27
-+[^:]+: 04a0e360 cntw x0, #27
-+[^:]+: 04a0e380 cntw x0, #28
-+[^:]+: 04a0e380 cntw x0, #28
-+[^:]+: 04a0e380 cntw x0, #28
-+[^:]+: 04a0e3a0 cntw x0, mul4
-+[^:]+: 04a0e3a0 cntw x0, mul4
-+[^:]+: 04a0e3a0 cntw x0, mul4
-+[^:]+: 04a0e3c0 cntw x0, mul3
-+[^:]+: 04a0e3c0 cntw x0, mul3
-+[^:]+: 04a0e3c0 cntw x0, mul3
-+[^:]+: 04a0e3e0 cntw x0
-+[^:]+: 04a0e3e0 cntw x0
-+[^:]+: 04a0e3e0 cntw x0
-+[^:]+: 04a0e3e0 cntw x0
-+[^:]+: 04a7e000 cntw x0, pow2, mul #8
-+[^:]+: 04a7e000 cntw x0, pow2, mul #8
-+[^:]+: 04a8e000 cntw x0, pow2, mul #9
-+[^:]+: 04a8e000 cntw x0, pow2, mul #9
-+[^:]+: 04a9e000 cntw x0, pow2, mul #10
-+[^:]+: 04a9e000 cntw x0, pow2, mul #10
-+[^:]+: 04afe000 cntw x0, pow2, mul #16
-+[^:]+: 04afe000 cntw x0, pow2, mul #16
-+[^:]+: 05a18000 compact z0.s, p0, z0.s
-+[^:]+: 05a18000 compact z0.s, p0, z0.s
-+[^:]+: 05a18001 compact z1.s, p0, z0.s
-+[^:]+: 05a18001 compact z1.s, p0, z0.s
-+[^:]+: 05a1801f compact z31.s, p0, z0.s
-+[^:]+: 05a1801f compact z31.s, p0, z0.s
-+[^:]+: 05a18800 compact z0.s, p2, z0.s
-+[^:]+: 05a18800 compact z0.s, p2, z0.s
-+[^:]+: 05a19c00 compact z0.s, p7, z0.s
-+[^:]+: 05a19c00 compact z0.s, p7, z0.s
-+[^:]+: 05a18060 compact z0.s, p0, z3.s
-+[^:]+: 05a18060 compact z0.s, p0, z3.s
-+[^:]+: 05a183e0 compact z0.s, p0, z31.s
-+[^:]+: 05a183e0 compact z0.s, p0, z31.s
-+[^:]+: 05e18000 compact z0.d, p0, z0.d
-+[^:]+: 05e18000 compact z0.d, p0, z0.d
-+[^:]+: 05e18001 compact z1.d, p0, z0.d
-+[^:]+: 05e18001 compact z1.d, p0, z0.d
-+[^:]+: 05e1801f compact z31.d, p0, z0.d
-+[^:]+: 05e1801f compact z31.d, p0, z0.d
-+[^:]+: 05e18800 compact z0.d, p2, z0.d
-+[^:]+: 05e18800 compact z0.d, p2, z0.d
-+[^:]+: 05e19c00 compact z0.d, p7, z0.d
-+[^:]+: 05e19c00 compact z0.d, p7, z0.d
-+[^:]+: 05e18060 compact z0.d, p0, z3.d
-+[^:]+: 05e18060 compact z0.d, p0, z3.d
-+[^:]+: 05e183e0 compact z0.d, p0, z31.d
-+[^:]+: 05e183e0 compact z0.d, p0, z31.d
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-+[^:]+: 05208000 mov z0.b, p0/m, b0
-+[^:]+: 05208001 mov z1.b, p0/m, b0
-+[^:]+: 05208001 mov z1.b, p0/m, b0
-+[^:]+: 0520801f mov z31.b, p0/m, b0
-+[^:]+: 0520801f mov z31.b, p0/m, b0
-+[^:]+: 05208800 mov z0.b, p2/m, b0
-+[^:]+: 05208800 mov z0.b, p2/m, b0
-+[^:]+: 05209c00 mov z0.b, p7/m, b0
-+[^:]+: 05209c00 mov z0.b, p7/m, b0
-+[^:]+: 05208060 mov z0.b, p0/m, b3
-+[^:]+: 05208060 mov z0.b, p0/m, b3
-+[^:]+: 052083e0 mov z0.b, p0/m, b31
-+[^:]+: 052083e0 mov z0.b, p0/m, b31
-+[^:]+: 05608000 mov z0.h, p0/m, h0
-+[^:]+: 05608000 mov z0.h, p0/m, h0
-+[^:]+: 05608001 mov z1.h, p0/m, h0
-+[^:]+: 05608001 mov z1.h, p0/m, h0
-+[^:]+: 0560801f mov z31.h, p0/m, h0
-+[^:]+: 0560801f mov z31.h, p0/m, h0
-+[^:]+: 05608800 mov z0.h, p2/m, h0
-+[^:]+: 05608800 mov z0.h, p2/m, h0
-+[^:]+: 05609c00 mov z0.h, p7/m, h0
-+[^:]+: 05609c00 mov z0.h, p7/m, h0
-+[^:]+: 05608060 mov z0.h, p0/m, h3
-+[^:]+: 05608060 mov z0.h, p0/m, h3
-+[^:]+: 056083e0 mov z0.h, p0/m, h31
-+[^:]+: 056083e0 mov z0.h, p0/m, h31
-+[^:]+: 05a08000 mov z0.s, p0/m, s0
-+[^:]+: 05a08000 mov z0.s, p0/m, s0
-+[^:]+: 05a08001 mov z1.s, p0/m, s0
-+[^:]+: 05a08001 mov z1.s, p0/m, s0
-+[^:]+: 05a0801f mov z31.s, p0/m, s0
-+[^:]+: 05a0801f mov z31.s, p0/m, s0
-+[^:]+: 05a08800 mov z0.s, p2/m, s0
-+[^:]+: 05a08800 mov z0.s, p2/m, s0
-+[^:]+: 05a09c00 mov z0.s, p7/m, s0
-+[^:]+: 05a09c00 mov z0.s, p7/m, s0
-+[^:]+: 05a08060 mov z0.s, p0/m, s3
-+[^:]+: 05a08060 mov z0.s, p0/m, s3
-+[^:]+: 05a083e0 mov z0.s, p0/m, s31
-+[^:]+: 05a083e0 mov z0.s, p0/m, s31
-+[^:]+: 05e08000 mov z0.d, p0/m, d0
-+[^:]+: 05e08000 mov z0.d, p0/m, d0
-+[^:]+: 05e08001 mov z1.d, p0/m, d0
-+[^:]+: 05e08001 mov z1.d, p0/m, d0
-+[^:]+: 05e0801f mov z31.d, p0/m, d0
-+[^:]+: 05e0801f mov z31.d, p0/m, d0
-+[^:]+: 05e08800 mov z0.d, p2/m, d0
-+[^:]+: 05e08800 mov z0.d, p2/m, d0
-+[^:]+: 05e09c00 mov z0.d, p7/m, d0
-+[^:]+: 05e09c00 mov z0.d, p7/m, d0
-+[^:]+: 05e08060 mov z0.d, p0/m, d3
-+[^:]+: 05e08060 mov z0.d, p0/m, d3
-+[^:]+: 05e083e0 mov z0.d, p0/m, d31
-+[^:]+: 05e083e0 mov z0.d, p0/m, d31
-+[^:]+: 0528a000 mov z0.b, p0/m, w0
-+[^:]+: 0528a000 mov z0.b, p0/m, w0
-+[^:]+: 0528a001 mov z1.b, p0/m, w0
-+[^:]+: 0528a001 mov z1.b, p0/m, w0
-+[^:]+: 0528a01f mov z31.b, p0/m, w0
-+[^:]+: 0528a01f mov z31.b, p0/m, w0
-+[^:]+: 0528a800 mov z0.b, p2/m, w0
-+[^:]+: 0528a800 mov z0.b, p2/m, w0
-+[^:]+: 0528bc00 mov z0.b, p7/m, w0
-+[^:]+: 0528bc00 mov z0.b, p7/m, w0
-+[^:]+: 0528a060 mov z0.b, p0/m, w3
-+[^:]+: 0528a060 mov z0.b, p0/m, w3
-+[^:]+: 0528a3e0 mov z0.b, p0/m, wsp
-+[^:]+: 0528a3e0 mov z0.b, p0/m, wsp
-+[^:]+: 0568a000 mov z0.h, p0/m, w0
-+[^:]+: 0568a000 mov z0.h, p0/m, w0
-+[^:]+: 0568a001 mov z1.h, p0/m, w0
-+[^:]+: 0568a001 mov z1.h, p0/m, w0
-+[^:]+: 0568a01f mov z31.h, p0/m, w0
-+[^:]+: 0568a01f mov z31.h, p0/m, w0
-+[^:]+: 0568a800 mov z0.h, p2/m, w0
-+[^:]+: 0568a800 mov z0.h, p2/m, w0
-+[^:]+: 0568bc00 mov z0.h, p7/m, w0
-+[^:]+: 0568bc00 mov z0.h, p7/m, w0
-+[^:]+: 0568a060 mov z0.h, p0/m, w3
-+[^:]+: 0568a060 mov z0.h, p0/m, w3
-+[^:]+: 0568a3e0 mov z0.h, p0/m, wsp
-+[^:]+: 0568a3e0 mov z0.h, p0/m, wsp
-+[^:]+: 05a8a000 mov z0.s, p0/m, w0
-+[^:]+: 05a8a000 mov z0.s, p0/m, w0
-+[^:]+: 05a8a001 mov z1.s, p0/m, w0
-+[^:]+: 05a8a001 mov z1.s, p0/m, w0
-+[^:]+: 05a8a01f mov z31.s, p0/m, w0
-+[^:]+: 05a8a01f mov z31.s, p0/m, w0
-+[^:]+: 05a8a800 mov z0.s, p2/m, w0
-+[^:]+: 05a8a800 mov z0.s, p2/m, w0
-+[^:]+: 05a8bc00 mov z0.s, p7/m, w0
-+[^:]+: 05a8bc00 mov z0.s, p7/m, w0
-+[^:]+: 05a8a060 mov z0.s, p0/m, w3
-+[^:]+: 05a8a060 mov z0.s, p0/m, w3
-+[^:]+: 05a8a3e0 mov z0.s, p0/m, wsp
-+[^:]+: 05a8a3e0 mov z0.s, p0/m, wsp
-+[^:]+: 05e8a000 mov z0.d, p0/m, x0
-+[^:]+: 05e8a000 mov z0.d, p0/m, x0
-+[^:]+: 05e8a001 mov z1.d, p0/m, x0
-+[^:]+: 05e8a001 mov z1.d, p0/m, x0
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-+[^:]+: 05e8a01f mov z31.d, p0/m, x0
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-+[^:]+: 05e8a800 mov z0.d, p2/m, x0
-+[^:]+: 05e8bc00 mov z0.d, p7/m, x0
-+[^:]+: 05e8bc00 mov z0.d, p7/m, x0
-+[^:]+: 05e8a060 mov z0.d, p0/m, x3
-+[^:]+: 05e8a060 mov z0.d, p0/m, x3
-+[^:]+: 05e8a3e0 mov z0.d, p0/m, sp
-+[^:]+: 05e8a3e0 mov z0.d, p0/m, sp
-+[^:]+: 05100000 mov z0.b, p0/z, #0
-+[^:]+: 05100000 mov z0.b, p0/z, #0
-+[^:]+: 05100000 mov z0.b, p0/z, #0
-+[^:]+: 05100001 mov z1.b, p0/z, #0
-+[^:]+: 05100001 mov z1.b, p0/z, #0
-+[^:]+: 05100001 mov z1.b, p0/z, #0
-+[^:]+: 0510001f mov z31.b, p0/z, #0
-+[^:]+: 0510001f mov z31.b, p0/z, #0
-+[^:]+: 0510001f mov z31.b, p0/z, #0
-+[^:]+: 05120000 mov z0.b, p2/z, #0
-+[^:]+: 05120000 mov z0.b, p2/z, #0
-+[^:]+: 05120000 mov z0.b, p2/z, #0
-+[^:]+: 051f0000 mov z0.b, p15/z, #0
-+[^:]+: 051f0000 mov z0.b, p15/z, #0
-+[^:]+: 051f0000 mov z0.b, p15/z, #0
-+[^:]+: 05100fe0 mov z0.b, p0/z, #127
-+[^:]+: 05100fe0 mov z0.b, p0/z, #127
-+[^:]+: 05100fe0 mov z0.b, p0/z, #127
-+[^:]+: 05101000 mov z0.b, p0/z, #-128
-+[^:]+: 05101000 mov z0.b, p0/z, #-128
-+[^:]+: 05101000 mov z0.b, p0/z, #-128
-+[^:]+: 05101020 mov z0.b, p0/z, #-127
-+[^:]+: 05101020 mov z0.b, p0/z, #-127
-+[^:]+: 05101020 mov z0.b, p0/z, #-127
-+[^:]+: 05101fe0 mov z0.b, p0/z, #-1
-+[^:]+: 05101fe0 mov z0.b, p0/z, #-1
-+[^:]+: 05101fe0 mov z0.b, p0/z, #-1
-+[^:]+: 05104000 mov z0.b, p0/m, #0
-+[^:]+: 05104000 mov z0.b, p0/m, #0
-+[^:]+: 05104000 mov z0.b, p0/m, #0
-+[^:]+: 05104001 mov z1.b, p0/m, #0
-+[^:]+: 05104001 mov z1.b, p0/m, #0
-+[^:]+: 05104001 mov z1.b, p0/m, #0
-+[^:]+: 0510401f mov z31.b, p0/m, #0
-+[^:]+: 0510401f mov z31.b, p0/m, #0
-+[^:]+: 0510401f mov z31.b, p0/m, #0
-+[^:]+: 05124000 mov z0.b, p2/m, #0
-+[^:]+: 05124000 mov z0.b, p2/m, #0
-+[^:]+: 05124000 mov z0.b, p2/m, #0
-+[^:]+: 051f4000 mov z0.b, p15/m, #0
-+[^:]+: 051f4000 mov z0.b, p15/m, #0
-+[^:]+: 051f4000 mov z0.b, p15/m, #0
-+[^:]+: 05104fe0 mov z0.b, p0/m, #127
-+[^:]+: 05104fe0 mov z0.b, p0/m, #127
-+[^:]+: 05104fe0 mov z0.b, p0/m, #127
-+[^:]+: 05105000 mov z0.b, p0/m, #-128
-+[^:]+: 05105000 mov z0.b, p0/m, #-128
-+[^:]+: 05105000 mov z0.b, p0/m, #-128
-+[^:]+: 05105020 mov z0.b, p0/m, #-127
-+[^:]+: 05105020 mov z0.b, p0/m, #-127
-+[^:]+: 05105020 mov z0.b, p0/m, #-127
-+[^:]+: 05105fe0 mov z0.b, p0/m, #-1
-+[^:]+: 05105fe0 mov z0.b, p0/m, #-1
-+[^:]+: 05105fe0 mov z0.b, p0/m, #-1
-+[^:]+: 05500000 mov z0.h, p0/z, #0
-+[^:]+: 05500000 mov z0.h, p0/z, #0
-+[^:]+: 05500000 mov z0.h, p0/z, #0
-+[^:]+: 05500001 mov z1.h, p0/z, #0
-+[^:]+: 05500001 mov z1.h, p0/z, #0
-+[^:]+: 05500001 mov z1.h, p0/z, #0
-+[^:]+: 0550001f mov z31.h, p0/z, #0
-+[^:]+: 0550001f mov z31.h, p0/z, #0
-+[^:]+: 0550001f mov z31.h, p0/z, #0
-+[^:]+: 05520000 mov z0.h, p2/z, #0
-+[^:]+: 05520000 mov z0.h, p2/z, #0
-+[^:]+: 05520000 mov z0.h, p2/z, #0
-+[^:]+: 055f0000 mov z0.h, p15/z, #0
-+[^:]+: 055f0000 mov z0.h, p15/z, #0
-+[^:]+: 055f0000 mov z0.h, p15/z, #0
-+[^:]+: 05500fe0 mov z0.h, p0/z, #127
-+[^:]+: 05500fe0 mov z0.h, p0/z, #127
-+[^:]+: 05500fe0 mov z0.h, p0/z, #127
-+[^:]+: 05501000 mov z0.h, p0/z, #-128
-+[^:]+: 05501000 mov z0.h, p0/z, #-128
-+[^:]+: 05501000 mov z0.h, p0/z, #-128
-+[^:]+: 05501020 mov z0.h, p0/z, #-127
-+[^:]+: 05501020 mov z0.h, p0/z, #-127
-+[^:]+: 05501020 mov z0.h, p0/z, #-127
-+[^:]+: 05501fe0 mov z0.h, p0/z, #-1
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-+[^:]+: 05d07fe0 mov z0.d, p0/m, #-256
-+[^:]+: 25a02000 ctermeq w0, w0
-+[^:]+: 25a02000 ctermeq w0, w0
-+[^:]+: 25a02020 ctermeq w1, w0
-+[^:]+: 25a02020 ctermeq w1, w0
-+[^:]+: 25a023e0 ctermeq wzr, w0
-+[^:]+: 25a023e0 ctermeq wzr, w0
-+[^:]+: 25a22000 ctermeq w0, w2
-+[^:]+: 25a22000 ctermeq w0, w2
-+[^:]+: 25bf2000 ctermeq w0, wzr
-+[^:]+: 25bf2000 ctermeq w0, wzr
-+[^:]+: 25e02000 ctermeq x0, x0
-+[^:]+: 25e02000 ctermeq x0, x0
-+[^:]+: 25e02020 ctermeq x1, x0
-+[^:]+: 25e02020 ctermeq x1, x0
-+[^:]+: 25e023e0 ctermeq xzr, x0
-+[^:]+: 25e023e0 ctermeq xzr, x0
-+[^:]+: 25e22000 ctermeq x0, x2
-+[^:]+: 25e22000 ctermeq x0, x2
-+[^:]+: 25ff2000 ctermeq x0, xzr
-+[^:]+: 25ff2000 ctermeq x0, xzr
-+[^:]+: 25a02010 ctermne w0, w0
-+[^:]+: 25a02010 ctermne w0, w0
-+[^:]+: 25a02030 ctermne w1, w0
-+[^:]+: 25a02030 ctermne w1, w0
-+[^:]+: 25a023f0 ctermne wzr, w0
-+[^:]+: 25a023f0 ctermne wzr, w0
-+[^:]+: 25a22010 ctermne w0, w2
-+[^:]+: 25a22010 ctermne w0, w2
-+[^:]+: 25bf2010 ctermne w0, wzr
-+[^:]+: 25bf2010 ctermne w0, wzr
-+[^:]+: 25e02010 ctermne x0, x0
-+[^:]+: 25e02010 ctermne x0, x0
-+[^:]+: 25e02030 ctermne x1, x0
-+[^:]+: 25e02030 ctermne x1, x0
-+[^:]+: 25e023f0 ctermne xzr, x0
-+[^:]+: 25e023f0 ctermne xzr, x0
-+[^:]+: 25e22010 ctermne x0, x2
-+[^:]+: 25e22010 ctermne x0, x2
-+[^:]+: 25ff2010 ctermne x0, xzr
-+[^:]+: 25ff2010 ctermne x0, xzr
-+[^:]+: 0430e400 decb x0, pow2
-+[^:]+: 0430e400 decb x0, pow2
-+[^:]+: 0430e400 decb x0, pow2
-+[^:]+: 0430e401 decb x1, pow2
-+[^:]+: 0430e401 decb x1, pow2
-+[^:]+: 0430e401 decb x1, pow2
-+[^:]+: 0430e41f decb xzr, pow2
-+[^:]+: 0430e41f decb xzr, pow2
-+[^:]+: 0430e41f decb xzr, pow2
-+[^:]+: 0430e420 decb x0, vl1
-+[^:]+: 0430e420 decb x0, vl1
-+[^:]+: 0430e420 decb x0, vl1
-+[^:]+: 0430e440 decb x0, vl2
-+[^:]+: 0430e440 decb x0, vl2
-+[^:]+: 0430e440 decb x0, vl2
-+[^:]+: 0430e460 decb x0, vl3
-+[^:]+: 0430e460 decb x0, vl3
-+[^:]+: 0430e460 decb x0, vl3
-+[^:]+: 0430e480 decb x0, vl4
-+[^:]+: 0430e480 decb x0, vl4
-+[^:]+: 0430e480 decb x0, vl4
-+[^:]+: 0430e4a0 decb x0, vl5
-+[^:]+: 0430e4a0 decb x0, vl5
-+[^:]+: 0430e4a0 decb x0, vl5
-+[^:]+: 0430e4c0 decb x0, vl6
-+[^:]+: 0430e4c0 decb x0, vl6
-+[^:]+: 0430e4c0 decb x0, vl6
-+[^:]+: 0430e4e0 decb x0, vl7
-+[^:]+: 0430e4e0 decb x0, vl7
-+[^:]+: 0430e4e0 decb x0, vl7
-+[^:]+: 0430e500 decb x0, vl8
-+[^:]+: 0430e500 decb x0, vl8
-+[^:]+: 0430e500 decb x0, vl8
-+[^:]+: 0430e520 decb x0, vl16
-+[^:]+: 0430e520 decb x0, vl16
-+[^:]+: 0430e520 decb x0, vl16
-+[^:]+: 0430e540 decb x0, vl32
-+[^:]+: 0430e540 decb x0, vl32
-+[^:]+: 0430e540 decb x0, vl32
-+[^:]+: 0430e560 decb x0, vl64
-+[^:]+: 0430e560 decb x0, vl64
-+[^:]+: 0430e560 decb x0, vl64
-+[^:]+: 0430e580 decb x0, vl128
-+[^:]+: 0430e580 decb x0, vl128
-+[^:]+: 0430e580 decb x0, vl128
-+[^:]+: 0430e5a0 decb x0, vl256
-+[^:]+: 0430e5a0 decb x0, vl256
-+[^:]+: 0430e5a0 decb x0, vl256
-+[^:]+: 0430e5c0 decb x0, #14
-+[^:]+: 0430e5c0 decb x0, #14
-+[^:]+: 0430e5c0 decb x0, #14
-+[^:]+: 0430e5e0 decb x0, #15
-+[^:]+: 0430e5e0 decb x0, #15
-+[^:]+: 0430e5e0 decb x0, #15
-+[^:]+: 0430e600 decb x0, #16
-+[^:]+: 0430e600 decb x0, #16
-+[^:]+: 0430e600 decb x0, #16
-+[^:]+: 0430e620 decb x0, #17
-+[^:]+: 0430e620 decb x0, #17
-+[^:]+: 0430e620 decb x0, #17
-+[^:]+: 0430e640 decb x0, #18
-+[^:]+: 0430e640 decb x0, #18
-+[^:]+: 0430e640 decb x0, #18
-+[^:]+: 0430e660 decb x0, #19
-+[^:]+: 0430e660 decb x0, #19
-+[^:]+: 0430e660 decb x0, #19
-+[^:]+: 0430e680 decb x0, #20
-+[^:]+: 0430e680 decb x0, #20
-+[^:]+: 0430e680 decb x0, #20
-+[^:]+: 0430e6a0 decb x0, #21
-+[^:]+: 0430e6a0 decb x0, #21
-+[^:]+: 0430e6a0 decb x0, #21
-+[^:]+: 0430e6c0 decb x0, #22
-+[^:]+: 0430e6c0 decb x0, #22
-+[^:]+: 0430e6c0 decb x0, #22
-+[^:]+: 0430e6e0 decb x0, #23
-+[^:]+: 0430e6e0 decb x0, #23
-+[^:]+: 0430e6e0 decb x0, #23
-+[^:]+: 0430e700 decb x0, #24
-+[^:]+: 0430e700 decb x0, #24
-+[^:]+: 0430e700 decb x0, #24
-+[^:]+: 0430e720 decb x0, #25
-+[^:]+: 0430e720 decb x0, #25
-+[^:]+: 0430e720 decb x0, #25
-+[^:]+: 0430e740 decb x0, #26
-+[^:]+: 0430e740 decb x0, #26
-+[^:]+: 0430e740 decb x0, #26
-+[^:]+: 0430e760 decb x0, #27
-+[^:]+: 0430e760 decb x0, #27
-+[^:]+: 0430e760 decb x0, #27
-+[^:]+: 0430e780 decb x0, #28
-+[^:]+: 0430e780 decb x0, #28
-+[^:]+: 0430e780 decb x0, #28
-+[^:]+: 0430e7a0 decb x0, mul4
-+[^:]+: 0430e7a0 decb x0, mul4
-+[^:]+: 0430e7a0 decb x0, mul4
-+[^:]+: 0430e7c0 decb x0, mul3
-+[^:]+: 0430e7c0 decb x0, mul3
-+[^:]+: 0430e7c0 decb x0, mul3
-+[^:]+: 0430e7e0 decb x0
-+[^:]+: 0430e7e0 decb x0
-+[^:]+: 0430e7e0 decb x0
-+[^:]+: 0430e7e0 decb x0
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-+[^:]+: 0437e400 decb x0, pow2, mul #8
-+[^:]+: 0438e400 decb x0, pow2, mul #9
-+[^:]+: 0438e400 decb x0, pow2, mul #9
-+[^:]+: 0439e400 decb x0, pow2, mul #10
-+[^:]+: 0439e400 decb x0, pow2, mul #10
-+[^:]+: 043fe400 decb x0, pow2, mul #16
-+[^:]+: 043fe400 decb x0, pow2, mul #16
-+[^:]+: 04f0c400 decd z0.d, pow2
-+[^:]+: 04f0c400 decd z0.d, pow2
-+[^:]+: 04f0c400 decd z0.d, pow2
-+[^:]+: 04f0c401 decd z1.d, pow2
-+[^:]+: 04f0c401 decd z1.d, pow2
-+[^:]+: 04f0c401 decd z1.d, pow2
-+[^:]+: 04f0c41f decd z31.d, pow2
-+[^:]+: 04f0c41f decd z31.d, pow2
-+[^:]+: 04f0c41f decd z31.d, pow2
-+[^:]+: 04f0c420 decd z0.d, vl1
-+[^:]+: 04f0c420 decd z0.d, vl1
-+[^:]+: 04f0c420 decd z0.d, vl1
-+[^:]+: 04f0c440 decd z0.d, vl2
-+[^:]+: 04f0c440 decd z0.d, vl2
-+[^:]+: 04f0c440 decd z0.d, vl2
-+[^:]+: 04f0c460 decd z0.d, vl3
-+[^:]+: 04f0c460 decd z0.d, vl3
-+[^:]+: 04f0c460 decd z0.d, vl3
-+[^:]+: 04f0c480 decd z0.d, vl4
-+[^:]+: 04f0c480 decd z0.d, vl4
-+[^:]+: 04f0c480 decd z0.d, vl4
-+[^:]+: 04f0c4a0 decd z0.d, vl5
-+[^:]+: 04f0c4a0 decd z0.d, vl5
-+[^:]+: 04f0c4a0 decd z0.d, vl5
-+[^:]+: 04f0c4c0 decd z0.d, vl6
-+[^:]+: 04f0c4c0 decd z0.d, vl6
-+[^:]+: 04f0c4c0 decd z0.d, vl6
-+[^:]+: 04f0c4e0 decd z0.d, vl7
-+[^:]+: 04f0c4e0 decd z0.d, vl7
-+[^:]+: 04f0c4e0 decd z0.d, vl7
-+[^:]+: 04f0c500 decd z0.d, vl8
-+[^:]+: 04f0c500 decd z0.d, vl8
-+[^:]+: 04f0c500 decd z0.d, vl8
-+[^:]+: 04f0c520 decd z0.d, vl16
-+[^:]+: 04f0c520 decd z0.d, vl16
-+[^:]+: 04f0c520 decd z0.d, vl16
-+[^:]+: 04f0c540 decd z0.d, vl32
-+[^:]+: 04f0c540 decd z0.d, vl32
-+[^:]+: 04f0c540 decd z0.d, vl32
-+[^:]+: 04f0c560 decd z0.d, vl64
-+[^:]+: 04f0c560 decd z0.d, vl64
-+[^:]+: 04f0c560 decd z0.d, vl64
-+[^:]+: 04f0c580 decd z0.d, vl128
-+[^:]+: 04f0c580 decd z0.d, vl128
-+[^:]+: 04f0c580 decd z0.d, vl128
-+[^:]+: 04f0c5a0 decd z0.d, vl256
-+[^:]+: 04f0c5a0 decd z0.d, vl256
-+[^:]+: 04f0c5a0 decd z0.d, vl256
-+[^:]+: 04f0c5c0 decd z0.d, #14
-+[^:]+: 04f0c5c0 decd z0.d, #14
-+[^:]+: 04f0c5c0 decd z0.d, #14
-+[^:]+: 04f0c5e0 decd z0.d, #15
-+[^:]+: 04f0c5e0 decd z0.d, #15
-+[^:]+: 04f0c5e0 decd z0.d, #15
-+[^:]+: 04f0c600 decd z0.d, #16
-+[^:]+: 04f0c600 decd z0.d, #16
-+[^:]+: 04f0c600 decd z0.d, #16
-+[^:]+: 04f0c620 decd z0.d, #17
-+[^:]+: 04f0c620 decd z0.d, #17
-+[^:]+: 04f0c620 decd z0.d, #17
-+[^:]+: 04f0c640 decd z0.d, #18
-+[^:]+: 04f0c640 decd z0.d, #18
-+[^:]+: 04f0c640 decd z0.d, #18
-+[^:]+: 04f0c660 decd z0.d, #19
-+[^:]+: 04f0c660 decd z0.d, #19
-+[^:]+: 04f0c660 decd z0.d, #19
-+[^:]+: 04f0c680 decd z0.d, #20
-+[^:]+: 04f0c680 decd z0.d, #20
-+[^:]+: 04f0c680 decd z0.d, #20
-+[^:]+: 04f0c6a0 decd z0.d, #21
-+[^:]+: 04f0c6a0 decd z0.d, #21
-+[^:]+: 04f0c6a0 decd z0.d, #21
-+[^:]+: 04f0c6c0 decd z0.d, #22
-+[^:]+: 04f0c6c0 decd z0.d, #22
-+[^:]+: 04f0c6c0 decd z0.d, #22
-+[^:]+: 04f0c6e0 decd z0.d, #23
-+[^:]+: 04f0c6e0 decd z0.d, #23
-+[^:]+: 04f0c6e0 decd z0.d, #23
-+[^:]+: 04f0c700 decd z0.d, #24
-+[^:]+: 04f0c700 decd z0.d, #24
-+[^:]+: 04f0c700 decd z0.d, #24
-+[^:]+: 04f0c720 decd z0.d, #25
-+[^:]+: 04f0c720 decd z0.d, #25
-+[^:]+: 04f0c720 decd z0.d, #25
-+[^:]+: 04f0c740 decd z0.d, #26
-+[^:]+: 04f0c740 decd z0.d, #26
-+[^:]+: 04f0c740 decd z0.d, #26
-+[^:]+: 04f0c760 decd z0.d, #27
-+[^:]+: 04f0c760 decd z0.d, #27
-+[^:]+: 04f0c760 decd z0.d, #27
-+[^:]+: 04f0c780 decd z0.d, #28
-+[^:]+: 04f0c780 decd z0.d, #28
-+[^:]+: 04f0c780 decd z0.d, #28
-+[^:]+: 04f0c7a0 decd z0.d, mul4
-+[^:]+: 04f0c7a0 decd z0.d, mul4
-+[^:]+: 04f0c7a0 decd z0.d, mul4
-+[^:]+: 04f0c7c0 decd z0.d, mul3
-+[^:]+: 04f0c7c0 decd z0.d, mul3
-+[^:]+: 04f0c7c0 decd z0.d, mul3
-+[^:]+: 04f0c7e0 decd z0.d
-+[^:]+: 04f0c7e0 decd z0.d
-+[^:]+: 04f0c7e0 decd z0.d
-+[^:]+: 04f0c7e0 decd z0.d
-+[^:]+: 04f7c400 decd z0.d, pow2, mul #8
-+[^:]+: 04f7c400 decd z0.d, pow2, mul #8
-+[^:]+: 04f8c400 decd z0.d, pow2, mul #9
-+[^:]+: 04f8c400 decd z0.d, pow2, mul #9
-+[^:]+: 04f9c400 decd z0.d, pow2, mul #10
-+[^:]+: 04f9c400 decd z0.d, pow2, mul #10
-+[^:]+: 04ffc400 decd z0.d, pow2, mul #16
-+[^:]+: 04ffc400 decd z0.d, pow2, mul #16
-+[^:]+: 04f0e400 decd x0, pow2
-+[^:]+: 04f0e400 decd x0, pow2
-+[^:]+: 04f0e400 decd x0, pow2
-+[^:]+: 04f0e401 decd x1, pow2
-+[^:]+: 04f0e401 decd x1, pow2
-+[^:]+: 04f0e401 decd x1, pow2
-+[^:]+: 04f0e41f decd xzr, pow2
-+[^:]+: 04f0e41f decd xzr, pow2
-+[^:]+: 04f0e41f decd xzr, pow2
-+[^:]+: 04f0e420 decd x0, vl1
-+[^:]+: 04f0e420 decd x0, vl1
-+[^:]+: 04f0e420 decd x0, vl1
-+[^:]+: 04f0e440 decd x0, vl2
-+[^:]+: 04f0e440 decd x0, vl2
-+[^:]+: 04f0e440 decd x0, vl2
-+[^:]+: 04f0e460 decd x0, vl3
-+[^:]+: 04f0e460 decd x0, vl3
-+[^:]+: 04f0e460 decd x0, vl3
-+[^:]+: 04f0e480 decd x0, vl4
-+[^:]+: 04f0e480 decd x0, vl4
-+[^:]+: 04f0e480 decd x0, vl4
-+[^:]+: 04f0e4a0 decd x0, vl5
-+[^:]+: 04f0e4a0 decd x0, vl5
-+[^:]+: 04f0e4a0 decd x0, vl5
-+[^:]+: 04f0e4c0 decd x0, vl6
-+[^:]+: 04f0e4c0 decd x0, vl6
-+[^:]+: 04f0e4c0 decd x0, vl6
-+[^:]+: 04f0e4e0 decd x0, vl7
-+[^:]+: 04f0e4e0 decd x0, vl7
-+[^:]+: 04f0e4e0 decd x0, vl7
-+[^:]+: 04f0e500 decd x0, vl8
-+[^:]+: 04f0e500 decd x0, vl8
-+[^:]+: 04f0e500 decd x0, vl8
-+[^:]+: 04f0e520 decd x0, vl16
-+[^:]+: 04f0e520 decd x0, vl16
-+[^:]+: 04f0e520 decd x0, vl16
-+[^:]+: 04f0e540 decd x0, vl32
-+[^:]+: 04f0e540 decd x0, vl32
-+[^:]+: 04f0e540 decd x0, vl32
-+[^:]+: 04f0e560 decd x0, vl64
-+[^:]+: 04f0e560 decd x0, vl64
-+[^:]+: 04f0e560 decd x0, vl64
-+[^:]+: 04f0e580 decd x0, vl128
-+[^:]+: 04f0e580 decd x0, vl128
-+[^:]+: 04f0e580 decd x0, vl128
-+[^:]+: 04f0e5a0 decd x0, vl256
-+[^:]+: 04f0e5a0 decd x0, vl256
-+[^:]+: 04f0e5a0 decd x0, vl256
-+[^:]+: 04f0e5c0 decd x0, #14
-+[^:]+: 04f0e5c0 decd x0, #14
-+[^:]+: 04f0e5c0 decd x0, #14
-+[^:]+: 04f0e5e0 decd x0, #15
-+[^:]+: 04f0e5e0 decd x0, #15
-+[^:]+: 04f0e5e0 decd x0, #15
-+[^:]+: 04f0e600 decd x0, #16
-+[^:]+: 04f0e600 decd x0, #16
-+[^:]+: 04f0e600 decd x0, #16
-+[^:]+: 04f0e620 decd x0, #17
-+[^:]+: 04f0e620 decd x0, #17
-+[^:]+: 04f0e620 decd x0, #17
-+[^:]+: 04f0e640 decd x0, #18
-+[^:]+: 04f0e640 decd x0, #18
-+[^:]+: 04f0e640 decd x0, #18
-+[^:]+: 04f0e660 decd x0, #19
-+[^:]+: 04f0e660 decd x0, #19
-+[^:]+: 04f0e660 decd x0, #19
-+[^:]+: 04f0e680 decd x0, #20
-+[^:]+: 04f0e680 decd x0, #20
-+[^:]+: 04f0e680 decd x0, #20
-+[^:]+: 04f0e6a0 decd x0, #21
-+[^:]+: 04f0e6a0 decd x0, #21
-+[^:]+: 04f0e6a0 decd x0, #21
-+[^:]+: 04f0e6c0 decd x0, #22
-+[^:]+: 04f0e6c0 decd x0, #22
-+[^:]+: 04f0e6c0 decd x0, #22
-+[^:]+: 04f0e6e0 decd x0, #23
-+[^:]+: 04f0e6e0 decd x0, #23
-+[^:]+: 04f0e6e0 decd x0, #23
-+[^:]+: 04f0e700 decd x0, #24
-+[^:]+: 04f0e700 decd x0, #24
-+[^:]+: 04f0e700 decd x0, #24
-+[^:]+: 04f0e720 decd x0, #25
-+[^:]+: 04f0e720 decd x0, #25
-+[^:]+: 04f0e720 decd x0, #25
-+[^:]+: 04f0e740 decd x0, #26
-+[^:]+: 04f0e740 decd x0, #26
-+[^:]+: 04f0e740 decd x0, #26
-+[^:]+: 04f0e760 decd x0, #27
-+[^:]+: 04f0e760 decd x0, #27
-+[^:]+: 04f0e760 decd x0, #27
-+[^:]+: 04f0e780 decd x0, #28
-+[^:]+: 04f0e780 decd x0, #28
-+[^:]+: 04f0e780 decd x0, #28
-+[^:]+: 04f0e7a0 decd x0, mul4
-+[^:]+: 04f0e7a0 decd x0, mul4
-+[^:]+: 04f0e7a0 decd x0, mul4
-+[^:]+: 04f0e7c0 decd x0, mul3
-+[^:]+: 04f0e7c0 decd x0, mul3
-+[^:]+: 04f0e7c0 decd x0, mul3
-+[^:]+: 04f0e7e0 decd x0
-+[^:]+: 04f0e7e0 decd x0
-+[^:]+: 04f0e7e0 decd x0
-+[^:]+: 04f0e7e0 decd x0
-+[^:]+: 04f7e400 decd x0, pow2, mul #8
-+[^:]+: 04f7e400 decd x0, pow2, mul #8
-+[^:]+: 04f8e400 decd x0, pow2, mul #9
-+[^:]+: 04f8e400 decd x0, pow2, mul #9
-+[^:]+: 04f9e400 decd x0, pow2, mul #10
-+[^:]+: 04f9e400 decd x0, pow2, mul #10
-+[^:]+: 04ffe400 decd x0, pow2, mul #16
-+[^:]+: 04ffe400 decd x0, pow2, mul #16
-+[^:]+: 0470c400 dech z0.h, pow2
-+[^:]+: 0470c400 dech z0.h, pow2
-+[^:]+: 0470c400 dech z0.h, pow2
-+[^:]+: 0470c401 dech z1.h, pow2
-+[^:]+: 0470c401 dech z1.h, pow2
-+[^:]+: 0470c401 dech z1.h, pow2
-+[^:]+: 0470c41f dech z31.h, pow2
-+[^:]+: 0470c41f dech z31.h, pow2
-+[^:]+: 0470c41f dech z31.h, pow2
-+[^:]+: 0470c420 dech z0.h, vl1
-+[^:]+: 0470c420 dech z0.h, vl1
-+[^:]+: 0470c420 dech z0.h, vl1
-+[^:]+: 0470c440 dech z0.h, vl2
-+[^:]+: 0470c440 dech z0.h, vl2
-+[^:]+: 0470c440 dech z0.h, vl2
-+[^:]+: 0470c460 dech z0.h, vl3
-+[^:]+: 0470c460 dech z0.h, vl3
-+[^:]+: 0470c460 dech z0.h, vl3
-+[^:]+: 0470c480 dech z0.h, vl4
-+[^:]+: 0470c480 dech z0.h, vl4
-+[^:]+: 0470c480 dech z0.h, vl4
-+[^:]+: 0470c4a0 dech z0.h, vl5
-+[^:]+: 0470c4a0 dech z0.h, vl5
-+[^:]+: 0470c4a0 dech z0.h, vl5
-+[^:]+: 0470c4c0 dech z0.h, vl6
-+[^:]+: 0470c4c0 dech z0.h, vl6
-+[^:]+: 0470c4c0 dech z0.h, vl6
-+[^:]+: 0470c4e0 dech z0.h, vl7
-+[^:]+: 0470c4e0 dech z0.h, vl7
-+[^:]+: 0470c4e0 dech z0.h, vl7
-+[^:]+: 0470c500 dech z0.h, vl8
-+[^:]+: 0470c500 dech z0.h, vl8
-+[^:]+: 0470c500 dech z0.h, vl8
-+[^:]+: 0470c520 dech z0.h, vl16
-+[^:]+: 0470c520 dech z0.h, vl16
-+[^:]+: 0470c520 dech z0.h, vl16
-+[^:]+: 0470c540 dech z0.h, vl32
-+[^:]+: 0470c540 dech z0.h, vl32
-+[^:]+: 0470c540 dech z0.h, vl32
-+[^:]+: 0470c560 dech z0.h, vl64
-+[^:]+: 0470c560 dech z0.h, vl64
-+[^:]+: 0470c560 dech z0.h, vl64
-+[^:]+: 0470c580 dech z0.h, vl128
-+[^:]+: 0470c580 dech z0.h, vl128
-+[^:]+: 0470c580 dech z0.h, vl128
-+[^:]+: 0470c5a0 dech z0.h, vl256
-+[^:]+: 0470c5a0 dech z0.h, vl256
-+[^:]+: 0470c5a0 dech z0.h, vl256
-+[^:]+: 0470c5c0 dech z0.h, #14
-+[^:]+: 0470c5c0 dech z0.h, #14
-+[^:]+: 0470c5c0 dech z0.h, #14
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-+[^:]+: 0470c5e0 dech z0.h, #15
-+[^:]+: 0470c600 dech z0.h, #16
-+[^:]+: 0470c600 dech z0.h, #16
-+[^:]+: 0470c600 dech z0.h, #16
-+[^:]+: 0470c620 dech z0.h, #17
-+[^:]+: 0470c620 dech z0.h, #17
-+[^:]+: 0470c620 dech z0.h, #17
-+[^:]+: 0470c640 dech z0.h, #18
-+[^:]+: 0470c640 dech z0.h, #18
-+[^:]+: 0470c640 dech z0.h, #18
-+[^:]+: 0470c660 dech z0.h, #19
-+[^:]+: 0470c660 dech z0.h, #19
-+[^:]+: 0470c660 dech z0.h, #19
-+[^:]+: 0470c680 dech z0.h, #20
-+[^:]+: 0470c680 dech z0.h, #20
-+[^:]+: 0470c680 dech z0.h, #20
-+[^:]+: 0470c6a0 dech z0.h, #21
-+[^:]+: 0470c6a0 dech z0.h, #21
-+[^:]+: 0470c6a0 dech z0.h, #21
-+[^:]+: 0470c6c0 dech z0.h, #22
-+[^:]+: 0470c6c0 dech z0.h, #22
-+[^:]+: 0470c6c0 dech z0.h, #22
-+[^:]+: 0470c6e0 dech z0.h, #23
-+[^:]+: 0470c6e0 dech z0.h, #23
-+[^:]+: 0470c6e0 dech z0.h, #23
-+[^:]+: 0470c700 dech z0.h, #24
-+[^:]+: 0470c700 dech z0.h, #24
-+[^:]+: 0470c700 dech z0.h, #24
-+[^:]+: 0470c720 dech z0.h, #25
-+[^:]+: 0470c720 dech z0.h, #25
-+[^:]+: 0470c720 dech z0.h, #25
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-+[^:]+: 04b0e620 decw x0, #17
-+[^:]+: 04b0e640 decw x0, #18
-+[^:]+: 04b0e640 decw x0, #18
-+[^:]+: 04b0e640 decw x0, #18
-+[^:]+: 04b0e660 decw x0, #19
-+[^:]+: 04b0e660 decw x0, #19
-+[^:]+: 04b0e660 decw x0, #19
-+[^:]+: 04b0e680 decw x0, #20
-+[^:]+: 04b0e680 decw x0, #20
-+[^:]+: 04b0e680 decw x0, #20
-+[^:]+: 04b0e6a0 decw x0, #21
-+[^:]+: 04b0e6a0 decw x0, #21
-+[^:]+: 04b0e6a0 decw x0, #21
-+[^:]+: 04b0e6c0 decw x0, #22
-+[^:]+: 04b0e6c0 decw x0, #22
-+[^:]+: 04b0e6c0 decw x0, #22
-+[^:]+: 04b0e6e0 decw x0, #23
-+[^:]+: 04b0e6e0 decw x0, #23
-+[^:]+: 04b0e6e0 decw x0, #23
-+[^:]+: 04b0e700 decw x0, #24
-+[^:]+: 04b0e700 decw x0, #24
-+[^:]+: 04b0e700 decw x0, #24
-+[^:]+: 04b0e720 decw x0, #25
-+[^:]+: 04b0e720 decw x0, #25
-+[^:]+: 04b0e720 decw x0, #25
-+[^:]+: 04b0e740 decw x0, #26
-+[^:]+: 04b0e740 decw x0, #26
-+[^:]+: 04b0e740 decw x0, #26
-+[^:]+: 04b0e760 decw x0, #27
-+[^:]+: 04b0e760 decw x0, #27
-+[^:]+: 04b0e760 decw x0, #27
-+[^:]+: 04b0e780 decw x0, #28
-+[^:]+: 04b0e780 decw x0, #28
-+[^:]+: 04b0e780 decw x0, #28
-+[^:]+: 04b0e7a0 decw x0, mul4
-+[^:]+: 04b0e7a0 decw x0, mul4
-+[^:]+: 04b0e7a0 decw x0, mul4
-+[^:]+: 04b0e7c0 decw x0, mul3
-+[^:]+: 04b0e7c0 decw x0, mul3
-+[^:]+: 04b0e7c0 decw x0, mul3
-+[^:]+: 04b0e7e0 decw x0
-+[^:]+: 04b0e7e0 decw x0
-+[^:]+: 04b0e7e0 decw x0
-+[^:]+: 04b0e7e0 decw x0
-+[^:]+: 04b7e400 decw x0, pow2, mul #8
-+[^:]+: 04b7e400 decw x0, pow2, mul #8
-+[^:]+: 04b8e400 decw x0, pow2, mul #9
-+[^:]+: 04b8e400 decw x0, pow2, mul #9
-+[^:]+: 04b9e400 decw x0, pow2, mul #10
-+[^:]+: 04b9e400 decw x0, pow2, mul #10
-+[^:]+: 04bfe400 decw x0, pow2, mul #16
-+[^:]+: 04bfe400 decw x0, pow2, mul #16
-+[^:]+: 05203800 mov z0.b, w0
-+[^:]+: 05203800 mov z0.b, w0
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-+[^:]+: 05203801 mov z1.b, w0
-+[^:]+: 0520381f mov z31.b, w0
-+[^:]+: 0520381f mov z31.b, w0
-+[^:]+: 05203840 mov z0.b, w2
-+[^:]+: 05203840 mov z0.b, w2
-+[^:]+: 05203be0 mov z0.b, wsp
-+[^:]+: 05203be0 mov z0.b, wsp
-+[^:]+: 05603800 mov z0.h, w0
-+[^:]+: 05603800 mov z0.h, w0
-+[^:]+: 05603801 mov z1.h, w0
-+[^:]+: 05603801 mov z1.h, w0
-+[^:]+: 0560381f mov z31.h, w0
-+[^:]+: 0560381f mov z31.h, w0
-+[^:]+: 05603840 mov z0.h, w2
-+[^:]+: 05603840 mov z0.h, w2
-+[^:]+: 05603be0 mov z0.h, wsp
-+[^:]+: 05603be0 mov z0.h, wsp
-+[^:]+: 05a03800 mov z0.s, w0
-+[^:]+: 05a03800 mov z0.s, w0
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-+[^:]+: 05a03801 mov z1.s, w0
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-+[^:]+: 05a03840 mov z0.s, w2
-+[^:]+: 05a03be0 mov z0.s, wsp
-+[^:]+: 05a03be0 mov z0.s, wsp
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-+[^:]+: 05e03800 mov z0.d, x0
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-+[^:]+: 05e03801 mov z1.d, x0
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-+[^:]+: 05e0381f mov z31.d, x0
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-+[^:]+: 05e03840 mov z0.d, x2
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-+[^:]+: 05212000 mov z0.b, b0
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-+[^:]+: 05212001 mov z1.b, b0
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-+[^:]+: 05232000 mov z0.b, z0.b\[1\]
-+[^:]+: 05fd2000 mov z0.b, z0.b\[62\]
-+[^:]+: 05fd2000 mov z0.b, z0.b\[62\]
-+[^:]+: 05ff2000 mov z0.b, z0.b\[63\]
-+[^:]+: 05ff2000 mov z0.b, z0.b\[63\]
-+[^:]+: 05222000 mov z0.h, h0
-+[^:]+: 05222000 mov z0.h, h0
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-+[^:]+: 05222001 mov z1.h, h0
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-+[^:]+: 0522201f mov z31.h, h0
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-+[^:]+: 05222040 mov z0.h, h2
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-+[^:]+: 052223e0 mov z0.h, h31
-+[^:]+: 05262000 mov z0.h, z0.h\[1\]
-+[^:]+: 05262000 mov z0.h, z0.h\[1\]
-+[^:]+: 05fa2000 mov z0.h, z0.h\[30\]
-+[^:]+: 05fa2000 mov z0.h, z0.h\[30\]
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-+[^:]+: 05fe2000 mov z0.h, z0.h\[31\]
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-+[^:]+: 05232001 mov z1.b, z0.b\[1\]
-+[^:]+: 0523201f mov z31.b, z0.b\[1\]
-+[^:]+: 0523201f mov z31.b, z0.b\[1\]
-+[^:]+: 05232040 mov z0.b, z2.b\[1\]
-+[^:]+: 05232040 mov z0.b, z2.b\[1\]
-+[^:]+: 052323e0 mov z0.b, z31.b\[1\]
-+[^:]+: 052323e0 mov z0.b, z31.b\[1\]
-+[^:]+: 05252000 mov z0.b, z0.b\[2\]
-+[^:]+: 05252000 mov z0.b, z0.b\[2\]
-+[^:]+: 05242000 mov z0.s, s0
-+[^:]+: 05242000 mov z0.s, s0
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-+[^:]+: 05242001 mov z1.s, s0
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-+[^:]+: 0524201f mov z31.s, s0
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-+[^:]+: 05242040 mov z0.s, s2
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-+[^:]+: 052423e0 mov z0.s, s31
-+[^:]+: 052c2000 mov z0.s, z0.s\[1\]
-+[^:]+: 052c2000 mov z0.s, z0.s\[1\]
-+[^:]+: 05f42000 mov z0.s, z0.s\[14\]
-+[^:]+: 05f42000 mov z0.s, z0.s\[14\]
-+[^:]+: 05fc2000 mov z0.s, z0.s\[15\]
-+[^:]+: 05fc2000 mov z0.s, z0.s\[15\]
-+[^:]+: 05252001 mov z1.b, z0.b\[2\]
-+[^:]+: 05252001 mov z1.b, z0.b\[2\]
-+[^:]+: 0525201f mov z31.b, z0.b\[2\]
-+[^:]+: 0525201f mov z31.b, z0.b\[2\]
-+[^:]+: 05252040 mov z0.b, z2.b\[2\]
-+[^:]+: 05252040 mov z0.b, z2.b\[2\]
-+[^:]+: 052523e0 mov z0.b, z31.b\[2\]
-+[^:]+: 052523e0 mov z0.b, z31.b\[2\]
-+[^:]+: 05272000 mov z0.b, z0.b\[3\]
-+[^:]+: 05272000 mov z0.b, z0.b\[3\]
-+[^:]+: 05262001 mov z1.h, z0.h\[1\]
-+[^:]+: 05262001 mov z1.h, z0.h\[1\]
-+[^:]+: 0526201f mov z31.h, z0.h\[1\]
-+[^:]+: 0526201f mov z31.h, z0.h\[1\]
-+[^:]+: 05262040 mov z0.h, z2.h\[1\]
-+[^:]+: 05262040 mov z0.h, z2.h\[1\]
-+[^:]+: 052623e0 mov z0.h, z31.h\[1\]
-+[^:]+: 052623e0 mov z0.h, z31.h\[1\]
-+[^:]+: 052a2000 mov z0.h, z0.h\[2\]
-+[^:]+: 052a2000 mov z0.h, z0.h\[2\]
-+[^:]+: 05272001 mov z1.b, z0.b\[3\]
-+[^:]+: 05272001 mov z1.b, z0.b\[3\]
-+[^:]+: 0527201f mov z31.b, z0.b\[3\]
-+[^:]+: 0527201f mov z31.b, z0.b\[3\]
-+[^:]+: 05272040 mov z0.b, z2.b\[3\]
-+[^:]+: 05272040 mov z0.b, z2.b\[3\]
-+[^:]+: 052723e0 mov z0.b, z31.b\[3\]
-+[^:]+: 052723e0 mov z0.b, z31.b\[3\]
-+[^:]+: 05292000 mov z0.b, z0.b\[4\]
-+[^:]+: 05292000 mov z0.b, z0.b\[4\]
-+[^:]+: 05282000 mov z0.d, d0
-+[^:]+: 05282000 mov z0.d, d0
-+[^:]+: 05282001 mov z1.d, d0
-+[^:]+: 05282001 mov z1.d, d0
-+[^:]+: 0528201f mov z31.d, d0
-+[^:]+: 0528201f mov z31.d, d0
-+[^:]+: 05282040 mov z0.d, d2
-+[^:]+: 05282040 mov z0.d, d2
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-+[^:]+: 052823e0 mov z0.d, d31
-+[^:]+: 05382000 mov z0.d, z0.d\[1\]
-+[^:]+: 05382000 mov z0.d, z0.d\[1\]
-+[^:]+: 05e82000 mov z0.d, z0.d\[6\]
-+[^:]+: 05e82000 mov z0.d, z0.d\[6\]
-+[^:]+: 05f82000 mov z0.d, z0.d\[7\]
-+[^:]+: 05f82000 mov z0.d, z0.d\[7\]
-+[^:]+: 05292001 mov z1.b, z0.b\[4\]
-+[^:]+: 05292001 mov z1.b, z0.b\[4\]
-+[^:]+: 0529201f mov z31.b, z0.b\[4\]
-+[^:]+: 0529201f mov z31.b, z0.b\[4\]
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-+[^:]+: 05292040 mov z0.b, z2.b\[4\]
-+[^:]+: 052923e0 mov z0.b, z31.b\[4\]
-+[^:]+: 052923e0 mov z0.b, z31.b\[4\]
-+[^:]+: 052b2000 mov z0.b, z0.b\[5\]
-+[^:]+: 052b2000 mov z0.b, z0.b\[5\]
-+[^:]+: 052a2001 mov z1.h, z0.h\[2\]
-+[^:]+: 052a2001 mov z1.h, z0.h\[2\]
-+[^:]+: 052a201f mov z31.h, z0.h\[2\]
-+[^:]+: 052a201f mov z31.h, z0.h\[2\]
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-+[^:]+: 052a2040 mov z0.h, z2.h\[2\]
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-+[^:]+: 052e2000 mov z0.h, z0.h\[3\]
-+[^:]+: 052e2000 mov z0.h, z0.h\[3\]
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-+[^:]+: 052b201f mov z31.b, z0.b\[5\]
-+[^:]+: 052b201f mov z31.b, z0.b\[5\]
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-+[^:]+: 052b2040 mov z0.b, z2.b\[5\]
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-+[^:]+: 052b23e0 mov z0.b, z31.b\[5\]
-+[^:]+: 052d2000 mov z0.b, z0.b\[6\]
-+[^:]+: 052d2000 mov z0.b, z0.b\[6\]
-+[^:]+: 052c2001 mov z1.s, z0.s\[1\]
-+[^:]+: 052c2001 mov z1.s, z0.s\[1\]
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-+[^:]+: 052c2040 mov z0.s, z2.s\[1\]
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-+[^:]+: 052c23e0 mov z0.s, z31.s\[1\]
-+[^:]+: 05342000 mov z0.s, z0.s\[2\]
-+[^:]+: 05342000 mov z0.s, z0.s\[2\]
-+[^:]+: 052d2001 mov z1.b, z0.b\[6\]
-+[^:]+: 052d2001 mov z1.b, z0.b\[6\]
-+[^:]+: 052d201f mov z31.b, z0.b\[6\]
-+[^:]+: 052d201f mov z31.b, z0.b\[6\]
-+[^:]+: 052d2040 mov z0.b, z2.b\[6\]
-+[^:]+: 052d2040 mov z0.b, z2.b\[6\]
-+[^:]+: 052d23e0 mov z0.b, z31.b\[6\]
-+[^:]+: 052d23e0 mov z0.b, z31.b\[6\]
-+[^:]+: 052f2000 mov z0.b, z0.b\[7\]
-+[^:]+: 052f2000 mov z0.b, z0.b\[7\]
-+[^:]+: 052e2001 mov z1.h, z0.h\[3\]
-+[^:]+: 052e2001 mov z1.h, z0.h\[3\]
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-+[^:]+: 05322000 mov z0.h, z0.h\[4\]
-+[^:]+: 05322000 mov z0.h, z0.h\[4\]
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-+[^:]+: 052f2001 mov z1.b, z0.b\[7\]
-+[^:]+: 052f201f mov z31.b, z0.b\[7\]
-+[^:]+: 052f201f mov z31.b, z0.b\[7\]
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-+[^:]+: 052f2040 mov z0.b, z2.b\[7\]
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-+[^:]+: 05312000 mov z0.b, z0.b\[8\]
-+[^:]+: 05312000 mov z0.b, z0.b\[8\]
-+[^:]+: 05702000 mov z0.q, z0.q\[1\]
-+[^:]+: 05702000 mov z0.q, z0.q\[1\]
-+[^:]+: 05702001 mov z1.q, z0.q\[1\]
-+[^:]+: 05702001 mov z1.q, z0.q\[1\]
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-+[^:]+: 0570201f mov z31.q, z0.q\[1\]
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-+[^:]+: 05702040 mov z0.q, z2.q\[1\]
-+[^:]+: 057023e0 mov z0.q, z31.q\[1\]
-+[^:]+: 057023e0 mov z0.q, z31.q\[1\]
-+[^:]+: 05302000 mov z0.q, q0
-+[^:]+: 05302000 mov z0.q, q0
-+[^:]+: 05b02000 mov z0.q, z0.q\[2\]
-+[^:]+: 05b02000 mov z0.q, z0.q\[2\]
-+[^:]+: 05f02000 mov z0.q, z0.q\[3\]
-+[^:]+: 05f02000 mov z0.q, z0.q\[3\]
-+[^:]+: 2538c000 mov z0.b, #0
-+[^:]+: 2538c000 mov z0.b, #0
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-+[^:]+: 2538cfe0 mov z0.b, #127
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-+[^:]+: 2538d000 mov z0.b, #-128
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-+[^:]+: 2538d020 mov z0.b, #-127
-+[^:]+: 2538d020 mov z0.b, #-127
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-+[^:]+: 2578c000 mov z0.h, #0
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-+[^:]+: 2578f000 mov z0.h, #-32768
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-+[^:]+: 2578f000 mov z0.h, #-32768
-+[^:]+: 2578f020 mov z0.h, #-32512
-+[^:]+: 2578f020 mov z0.h, #-32512
-+[^:]+: 2578f020 mov z0.h, #-32512
-+[^:]+: 2578f020 mov z0.h, #-32512
-+[^:]+: 2578ffe0 mov z0.h, #-256
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-+[^:]+: 2578ffe0 mov z0.h, #-256
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-+[^:]+: 25b8cfe0 mov z0.s, #127
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-+[^:]+: 25b8cfe0 mov z0.s, #127
-+[^:]+: 25b8d000 mov z0.s, #-128
-+[^:]+: 25b8d000 mov z0.s, #-128
-+[^:]+: 25b8d000 mov z0.s, #-128
-+[^:]+: 25b8d020 mov z0.s, #-127
-+[^:]+: 25b8d020 mov z0.s, #-127
-+[^:]+: 25b8d020 mov z0.s, #-127
-+[^:]+: 25b8dfe0 mov z0.s, #-1
-+[^:]+: 25b8dfe0 mov z0.s, #-1
-+[^:]+: 25b8dfe0 mov z0.s, #-1
-+[^:]+: 25b8e000 mov z0.s, #0, lsl #8
-+[^:]+: 25b8e000 mov z0.s, #0, lsl #8
-+[^:]+: 25b8efe0 mov z0.s, #32512
-+[^:]+: 25b8efe0 mov z0.s, #32512
-+[^:]+: 25b8efe0 mov z0.s, #32512
-+[^:]+: 25b8efe0 mov z0.s, #32512
-+[^:]+: 25b8f000 mov z0.s, #-32768
-+[^:]+: 25b8f000 mov z0.s, #-32768
-+[^:]+: 25b8f000 mov z0.s, #-32768
-+[^:]+: 25b8f000 mov z0.s, #-32768
-+[^:]+: 25b8f020 mov z0.s, #-32512
-+[^:]+: 25b8f020 mov z0.s, #-32512
-+[^:]+: 25b8f020 mov z0.s, #-32512
-+[^:]+: 25b8f020 mov z0.s, #-32512
-+[^:]+: 25b8ffe0 mov z0.s, #-256
-+[^:]+: 25b8ffe0 mov z0.s, #-256
-+[^:]+: 25b8ffe0 mov z0.s, #-256
-+[^:]+: 25b8ffe0 mov z0.s, #-256
-+[^:]+: 25f8c000 mov z0.d, #0
-+[^:]+: 25f8c000 mov z0.d, #0
-+[^:]+: 25f8c000 mov z0.d, #0
-+[^:]+: 25f8c001 mov z1.d, #0
-+[^:]+: 25f8c001 mov z1.d, #0
-+[^:]+: 25f8c001 mov z1.d, #0
-+[^:]+: 25f8c01f mov z31.d, #0
-+[^:]+: 25f8c01f mov z31.d, #0
-+[^:]+: 25f8c01f mov z31.d, #0
-+[^:]+: 25f8cfe0 mov z0.d, #127
-+[^:]+: 25f8cfe0 mov z0.d, #127
-+[^:]+: 25f8cfe0 mov z0.d, #127
-+[^:]+: 25f8d000 mov z0.d, #-128
-+[^:]+: 25f8d000 mov z0.d, #-128
-+[^:]+: 25f8d000 mov z0.d, #-128
-+[^:]+: 25f8d020 mov z0.d, #-127
-+[^:]+: 25f8d020 mov z0.d, #-127
-+[^:]+: 25f8d020 mov z0.d, #-127
-+[^:]+: 25f8dfe0 mov z0.d, #-1
-+[^:]+: 25f8dfe0 mov z0.d, #-1
-+[^:]+: 25f8dfe0 mov z0.d, #-1
-+[^:]+: 25f8e000 mov z0.d, #0, lsl #8
-+[^:]+: 25f8e000 mov z0.d, #0, lsl #8
-+[^:]+: 25f8efe0 mov z0.d, #32512
-+[^:]+: 25f8efe0 mov z0.d, #32512
-+[^:]+: 25f8efe0 mov z0.d, #32512
-+[^:]+: 25f8efe0 mov z0.d, #32512
-+[^:]+: 25f8f000 mov z0.d, #-32768
-+[^:]+: 25f8f000 mov z0.d, #-32768
-+[^:]+: 25f8f000 mov z0.d, #-32768
-+[^:]+: 25f8f000 mov z0.d, #-32768
-+[^:]+: 25f8f020 mov z0.d, #-32512
-+[^:]+: 25f8f020 mov z0.d, #-32512
-+[^:]+: 25f8f020 mov z0.d, #-32512
-+[^:]+: 25f8f020 mov z0.d, #-32512
-+[^:]+: 25f8ffe0 mov z0.d, #-256
-+[^:]+: 25f8ffe0 mov z0.d, #-256
-+[^:]+: 25f8ffe0 mov z0.d, #-256
-+[^:]+: 25f8ffe0 mov z0.d, #-256
-+[^:]+: 05c00000 dupm z0.s, #0x1
-+[^:]+: 05c00000 dupm z0.s, #0x1
-+[^:]+: 05c00000 dupm z0.s, #0x1
-+[^:]+: 05c00001 dupm z1.s, #0x1
-+[^:]+: 05c00001 dupm z1.s, #0x1
-+[^:]+: 05c00001 dupm z1.s, #0x1
-+[^:]+: 05c0001f dupm z31.s, #0x1
-+[^:]+: 05c0001f dupm z31.s, #0x1
-+[^:]+: 05c0001f dupm z31.s, #0x1
-+[^:]+: 05c000c0 dupm z0.s, #0x7f
-+[^:]+: 05c000c0 dupm z0.s, #0x7f
-+[^:]+: 05c000c0 dupm z0.s, #0x7f
-+[^:]+: 05c003c0 mov z0.s, #0x7fffffff
-+[^:]+: 05c003c0 mov z0.s, #0x7fffffff
-+[^:]+: 05c003c0 mov z0.s, #0x7fffffff
-+[^:]+: 05c00400 dupm z0.h, #0x1
-+[^:]+: 05c00400 dupm z0.h, #0x1
-+[^:]+: 05c00400 dupm z0.h, #0x1
-+[^:]+: 05c00400 dupm z0.h, #0x1
-+[^:]+: 05c005c0 mov z0.h, #0x7fff
-+[^:]+: 05c005c0 mov z0.h, #0x7fff
-+[^:]+: 05c005c0 mov z0.h, #0x7fff
-+[^:]+: 05c005c0 mov z0.h, #0x7fff
-+[^:]+: 05c00600 dupm z0.b, #0x1
-+[^:]+: 05c00600 dupm z0.b, #0x1
-+[^:]+: 05c00600 dupm z0.b, #0x1
-+[^:]+: 05c00600 dupm z0.b, #0x1
-+[^:]+: 05c00600 dupm z0.b, #0x1
-+[^:]+: 05c00780 dupm z0.b, #0x55
-+[^:]+: 05c00780 dupm z0.b, #0x55
-+[^:]+: 05c00780 dupm z0.b, #0x55
-+[^:]+: 05c00780 dupm z0.b, #0x55
-+[^:]+: 05c00780 dupm z0.b, #0x55
-+[^:]+: 05c00800 mov z0.s, #0x80000000
-+[^:]+: 05c00800 mov z0.s, #0x80000000
-+[^:]+: 05c00800 mov z0.s, #0x80000000
-+[^:]+: 05c00bc0 mov z0.s, #0xbfffffff
-+[^:]+: 05c00bc0 mov z0.s, #0xbfffffff
-+[^:]+: 05c00bc0 mov z0.s, #0xbfffffff
-+[^:]+: 05c00c00 dupm z0.h, #0x8000
-+[^:]+: 05c00c00 dupm z0.h, #0x8000
-+[^:]+: 05c00c00 dupm z0.h, #0x8000
-+[^:]+: 05c00c00 dupm z0.h, #0x8000
-+[^:]+: 05c0+ec0 dupm z0.b, #0xbf
-+[^:]+: 05c0+ec0 dupm z0.b, #0xbf
-+[^:]+: 05c0+ec0 dupm z0.b, #0xbf
-+[^:]+: 05c0+ec0 dupm z0.b, #0xbf
-+[^:]+: 05c0+ec0 dupm z0.b, #0xbf
-+[^:]+: 05c01e80 dupm z0.b, #0xe3
-+[^:]+: 05c01e80 dupm z0.b, #0xe3
-+[^:]+: 05c01e80 dupm z0.b, #0xe3
-+[^:]+: 05c01e80 dupm z0.b, #0xe3
-+[^:]+: 05c01e80 dupm z0.b, #0xe3
-+[^:]+: 05c0bbc0 mov z0.s, #0xfffffeff
-+[^:]+: 05c0bbc0 mov z0.s, #0xfffffeff
-+[^:]+: 05c0bbc0 mov z0.s, #0xfffffeff
-+[^:]+: 05c3ffc0 dupm z0.d, #0xfffffffffffffffe
-+[^:]+: 05c3ffc0 dupm z0.d, #0xfffffffffffffffe
-+[^:]+: 04a03000 eor z0.d, z0.d, z0.d
-+[^:]+: 04a03000 eor z0.d, z0.d, z0.d
-+[^:]+: 04a03001 eor z1.d, z0.d, z0.d
-+[^:]+: 04a03001 eor z1.d, z0.d, z0.d
-+[^:]+: 04a0301f eor z31.d, z0.d, z0.d
-+[^:]+: 04a0301f eor z31.d, z0.d, z0.d
-+[^:]+: 04a03040 eor z0.d, z2.d, z0.d
-+[^:]+: 04a03040 eor z0.d, z2.d, z0.d
-+[^:]+: 04a033e0 eor z0.d, z31.d, z0.d
-+[^:]+: 04a033e0 eor z0.d, z31.d, z0.d
-+[^:]+: 04a33000 eor z0.d, z0.d, z3.d
-+[^:]+: 04a33000 eor z0.d, z0.d, z3.d
-+[^:]+: 04bf3000 eor z0.d, z0.d, z31.d
-+[^:]+: 04bf3000 eor z0.d, z0.d, z31.d
-+[^:]+: 05400000 eor z0.s, z0.s, #0x1
-+[^:]+: 05400000 eor z0.s, z0.s, #0x1
-+[^:]+: 05400000 eor z0.s, z0.s, #0x1
-+[^:]+: 05400001 eor z1.s, z1.s, #0x1
-+[^:]+: 05400001 eor z1.s, z1.s, #0x1
-+[^:]+: 05400001 eor z1.s, z1.s, #0x1
-+[^:]+: 0540001f eor z31.s, z31.s, #0x1
-+[^:]+: 0540001f eor z31.s, z31.s, #0x1
-+[^:]+: 0540001f eor z31.s, z31.s, #0x1
-+[^:]+: 05400002 eor z2.s, z2.s, #0x1
-+[^:]+: 05400002 eor z2.s, z2.s, #0x1
-+[^:]+: 05400002 eor z2.s, z2.s, #0x1
-+[^:]+: 054000c0 eor z0.s, z0.s, #0x7f
-+[^:]+: 054000c0 eor z0.s, z0.s, #0x7f
-+[^:]+: 054000c0 eor z0.s, z0.s, #0x7f
-+[^:]+: 054003c0 eor z0.s, z0.s, #0x7fffffff
-+[^:]+: 054003c0 eor z0.s, z0.s, #0x7fffffff
-+[^:]+: 054003c0 eor z0.s, z0.s, #0x7fffffff
-+[^:]+: 05400400 eor z0.h, z0.h, #0x1
-+[^:]+: 05400400 eor z0.h, z0.h, #0x1
-+[^:]+: 05400400 eor z0.h, z0.h, #0x1
-+[^:]+: 05400400 eor z0.h, z0.h, #0x1
-+[^:]+: 054005c0 eor z0.h, z0.h, #0x7fff
-+[^:]+: 054005c0 eor z0.h, z0.h, #0x7fff
-+[^:]+: 054005c0 eor z0.h, z0.h, #0x7fff
-+[^:]+: 054005c0 eor z0.h, z0.h, #0x7fff
-+[^:]+: 05400600 eor z0.b, z0.b, #0x1
-+[^:]+: 05400600 eor z0.b, z0.b, #0x1
-+[^:]+: 05400600 eor z0.b, z0.b, #0x1
-+[^:]+: 05400600 eor z0.b, z0.b, #0x1
-+[^:]+: 05400600 eor z0.b, z0.b, #0x1
-+[^:]+: 05400780 eor z0.b, z0.b, #0x55
-+[^:]+: 05400780 eor z0.b, z0.b, #0x55
-+[^:]+: 05400780 eor z0.b, z0.b, #0x55
-+[^:]+: 05400780 eor z0.b, z0.b, #0x55
-+[^:]+: 05400780 eor z0.b, z0.b, #0x55
-+[^:]+: 05400800 eor z0.s, z0.s, #0x80000000
-+[^:]+: 05400800 eor z0.s, z0.s, #0x80000000
-+[^:]+: 05400800 eor z0.s, z0.s, #0x80000000
-+[^:]+: 05400bc0 eor z0.s, z0.s, #0xbfffffff
-+[^:]+: 05400bc0 eor z0.s, z0.s, #0xbfffffff
-+[^:]+: 05400bc0 eor z0.s, z0.s, #0xbfffffff
-+[^:]+: 05400c00 eor z0.h, z0.h, #0x8000
-+[^:]+: 05400c00 eor z0.h, z0.h, #0x8000
-+[^:]+: 05400c00 eor z0.h, z0.h, #0x8000
-+[^:]+: 05400c00 eor z0.h, z0.h, #0x8000
-+[^:]+: 0540+ec0 eor z0.b, z0.b, #0xbf
-+[^:]+: 0540+ec0 eor z0.b, z0.b, #0xbf
-+[^:]+: 0540+ec0 eor z0.b, z0.b, #0xbf
-+[^:]+: 0540+ec0 eor z0.b, z0.b, #0xbf
-+[^:]+: 0540+ec0 eor z0.b, z0.b, #0xbf
-+[^:]+: 05401e80 eor z0.b, z0.b, #0xe3
-+[^:]+: 05401e80 eor z0.b, z0.b, #0xe3
-+[^:]+: 05401e80 eor z0.b, z0.b, #0xe3
-+[^:]+: 05401e80 eor z0.b, z0.b, #0xe3
-+[^:]+: 05401e80 eor z0.b, z0.b, #0xe3
-+[^:]+: 0540bbc0 eor z0.s, z0.s, #0xfffffeff
-+[^:]+: 0540bbc0 eor z0.s, z0.s, #0xfffffeff
-+[^:]+: 0540bbc0 eor z0.s, z0.s, #0xfffffeff
-+[^:]+: 0543ffc0 eor z0.d, z0.d, #0xfffffffffffffffe
-+[^:]+: 0543ffc0 eor z0.d, z0.d, #0xfffffffffffffffe
-+[^:]+: 04190000 eor z0.b, p0/m, z0.b, z0.b
-+[^:]+: 04190000 eor z0.b, p0/m, z0.b, z0.b
-+[^:]+: 04190001 eor z1.b, p0/m, z1.b, z0.b
-+[^:]+: 04190001 eor z1.b, p0/m, z1.b, z0.b
-+[^:]+: 0419001f eor z31.b, p0/m, z31.b, z0.b
-+[^:]+: 0419001f eor z31.b, p0/m, z31.b, z0.b
-+[^:]+: 04190800 eor z0.b, p2/m, z0.b, z0.b
-+[^:]+: 04190800 eor z0.b, p2/m, z0.b, z0.b
-+[^:]+: 04191c00 eor z0.b, p7/m, z0.b, z0.b
-+[^:]+: 04191c00 eor z0.b, p7/m, z0.b, z0.b
-+[^:]+: 04190003 eor z3.b, p0/m, z3.b, z0.b
-+[^:]+: 04190003 eor z3.b, p0/m, z3.b, z0.b
-+[^:]+: 04190080 eor z0.b, p0/m, z0.b, z4.b
-+[^:]+: 04190080 eor z0.b, p0/m, z0.b, z4.b
-+[^:]+: 041903e0 eor z0.b, p0/m, z0.b, z31.b
-+[^:]+: 041903e0 eor z0.b, p0/m, z0.b, z31.b
-+[^:]+: 04590000 eor z0.h, p0/m, z0.h, z0.h
-+[^:]+: 04590000 eor z0.h, p0/m, z0.h, z0.h
-+[^:]+: 04590001 eor z1.h, p0/m, z1.h, z0.h
-+[^:]+: 04590001 eor z1.h, p0/m, z1.h, z0.h
-+[^:]+: 0459001f eor z31.h, p0/m, z31.h, z0.h
-+[^:]+: 0459001f eor z31.h, p0/m, z31.h, z0.h
-+[^:]+: 04590800 eor z0.h, p2/m, z0.h, z0.h
-+[^:]+: 04590800 eor z0.h, p2/m, z0.h, z0.h
-+[^:]+: 04591c00 eor z0.h, p7/m, z0.h, z0.h
-+[^:]+: 04591c00 eor z0.h, p7/m, z0.h, z0.h
-+[^:]+: 04590003 eor z3.h, p0/m, z3.h, z0.h
-+[^:]+: 04590003 eor z3.h, p0/m, z3.h, z0.h
-+[^:]+: 04590080 eor z0.h, p0/m, z0.h, z4.h
-+[^:]+: 04590080 eor z0.h, p0/m, z0.h, z4.h
-+[^:]+: 045903e0 eor z0.h, p0/m, z0.h, z31.h
-+[^:]+: 045903e0 eor z0.h, p0/m, z0.h, z31.h
-+[^:]+: 04990000 eor z0.s, p0/m, z0.s, z0.s
-+[^:]+: 04990000 eor z0.s, p0/m, z0.s, z0.s
-+[^:]+: 04990001 eor z1.s, p0/m, z1.s, z0.s
-+[^:]+: 04990001 eor z1.s, p0/m, z1.s, z0.s
-+[^:]+: 0499001f eor z31.s, p0/m, z31.s, z0.s
-+[^:]+: 0499001f eor z31.s, p0/m, z31.s, z0.s
-+[^:]+: 04990800 eor z0.s, p2/m, z0.s, z0.s
-+[^:]+: 04990800 eor z0.s, p2/m, z0.s, z0.s
-+[^:]+: 04991c00 eor z0.s, p7/m, z0.s, z0.s
-+[^:]+: 04991c00 eor z0.s, p7/m, z0.s, z0.s
-+[^:]+: 04990003 eor z3.s, p0/m, z3.s, z0.s
-+[^:]+: 04990003 eor z3.s, p0/m, z3.s, z0.s
-+[^:]+: 04990080 eor z0.s, p0/m, z0.s, z4.s
-+[^:]+: 04990080 eor z0.s, p0/m, z0.s, z4.s
-+[^:]+: 049903e0 eor z0.s, p0/m, z0.s, z31.s
-+[^:]+: 049903e0 eor z0.s, p0/m, z0.s, z31.s
-+[^:]+: 04d90000 eor z0.d, p0/m, z0.d, z0.d
-+[^:]+: 04d90000 eor z0.d, p0/m, z0.d, z0.d
-+[^:]+: 04d90001 eor z1.d, p0/m, z1.d, z0.d
-+[^:]+: 04d90001 eor z1.d, p0/m, z1.d, z0.d
-+[^:]+: 04d9001f eor z31.d, p0/m, z31.d, z0.d
-+[^:]+: 04d9001f eor z31.d, p0/m, z31.d, z0.d
-+[^:]+: 04d90800 eor z0.d, p2/m, z0.d, z0.d
-+[^:]+: 04d90800 eor z0.d, p2/m, z0.d, z0.d
-+[^:]+: 04d91c00 eor z0.d, p7/m, z0.d, z0.d
-+[^:]+: 04d91c00 eor z0.d, p7/m, z0.d, z0.d
-+[^:]+: 04d90003 eor z3.d, p0/m, z3.d, z0.d
-+[^:]+: 04d90003 eor z3.d, p0/m, z3.d, z0.d
-+[^:]+: 04d90080 eor z0.d, p0/m, z0.d, z4.d
-+[^:]+: 04d90080 eor z0.d, p0/m, z0.d, z4.d
-+[^:]+: 04d903e0 eor z0.d, p0/m, z0.d, z31.d
-+[^:]+: 04d903e0 eor z0.d, p0/m, z0.d, z31.d
-+[^:]+: 25004200 not p0.b, p0/z, p0.b
-+[^:]+: 25004200 not p0.b, p0/z, p0.b
-+[^:]+: 25004201 not p1.b, p0/z, p0.b
-+[^:]+: 25004201 not p1.b, p0/z, p0.b
-+[^:]+: 2500420f not p15.b, p0/z, p0.b
-+[^:]+: 2500420f not p15.b, p0/z, p0.b
-+[^:]+: 25004a00 eor p0.b, p2/z, p0.b, p0.b
-+[^:]+: 25004a00 eor p0.b, p2/z, p0.b, p0.b
-+[^:]+: 25007e00 eor p0.b, p15/z, p0.b, p0.b
-+[^:]+: 25007e00 eor p0.b, p15/z, p0.b, p0.b
-+[^:]+: 25004260 not p0.b, p0/z, p3.b
-+[^:]+: 25004260 not p0.b, p0/z, p3.b
-+[^:]+: 250043e0 not p0.b, p0/z, p15.b
-+[^:]+: 250043e0 not p0.b, p0/z, p15.b
-+[^:]+: 25044200 eor p0.b, p0/z, p0.b, p4.b
-+[^:]+: 25044200 eor p0.b, p0/z, p0.b, p4.b
-+[^:]+: 250f4200 eor p0.b, p0/z, p0.b, p15.b
-+[^:]+: 250f4200 eor p0.b, p0/z, p0.b, p15.b
-+[^:]+: 25404200 nots p0.b, p0/z, p0.b
-+[^:]+: 25404200 nots p0.b, p0/z, p0.b
-+[^:]+: 25404201 nots p1.b, p0/z, p0.b
-+[^:]+: 25404201 nots p1.b, p0/z, p0.b
-+[^:]+: 2540420f nots p15.b, p0/z, p0.b
-+[^:]+: 2540420f nots p15.b, p0/z, p0.b
-+[^:]+: 25404a00 eors p0.b, p2/z, p0.b, p0.b
-+[^:]+: 25404a00 eors p0.b, p2/z, p0.b, p0.b
-+[^:]+: 25407e00 eors p0.b, p15/z, p0.b, p0.b
-+[^:]+: 25407e00 eors p0.b, p15/z, p0.b, p0.b
-+[^:]+: 25404260 nots p0.b, p0/z, p3.b
-+[^:]+: 25404260 nots p0.b, p0/z, p3.b
-+[^:]+: 254043e0 nots p0.b, p0/z, p15.b
-+[^:]+: 254043e0 nots p0.b, p0/z, p15.b
-+[^:]+: 25444200 eors p0.b, p0/z, p0.b, p4.b
-+[^:]+: 25444200 eors p0.b, p0/z, p0.b, p4.b
-+[^:]+: 254f4200 eors p0.b, p0/z, p0.b, p15.b
-+[^:]+: 254f4200 eors p0.b, p0/z, p0.b, p15.b
-+[^:]+: 04192000 eorv b0, p0, z0.b
-+[^:]+: 04192000 eorv b0, p0, z0.b
-+[^:]+: 04192001 eorv b1, p0, z0.b
-+[^:]+: 04192001 eorv b1, p0, z0.b
-+[^:]+: 0419201f eorv b31, p0, z0.b
-+[^:]+: 0419201f eorv b31, p0, z0.b
-+[^:]+: 04192800 eorv b0, p2, z0.b
-+[^:]+: 04192800 eorv b0, p2, z0.b
-+[^:]+: 04193c00 eorv b0, p7, z0.b
-+[^:]+: 04193c00 eorv b0, p7, z0.b
-+[^:]+: 04192060 eorv b0, p0, z3.b
-+[^:]+: 04192060 eorv b0, p0, z3.b
-+[^:]+: 041923e0 eorv b0, p0, z31.b
-+[^:]+: 041923e0 eorv b0, p0, z31.b
-+[^:]+: 04592000 eorv h0, p0, z0.h
-+[^:]+: 04592000 eorv h0, p0, z0.h
-+[^:]+: 04592001 eorv h1, p0, z0.h
-+[^:]+: 04592001 eorv h1, p0, z0.h
-+[^:]+: 0459201f eorv h31, p0, z0.h
-+[^:]+: 0459201f eorv h31, p0, z0.h
-+[^:]+: 04592800 eorv h0, p2, z0.h
-+[^:]+: 04592800 eorv h0, p2, z0.h
-+[^:]+: 04593c00 eorv h0, p7, z0.h
-+[^:]+: 04593c00 eorv h0, p7, z0.h
-+[^:]+: 04592060 eorv h0, p0, z3.h
-+[^:]+: 04592060 eorv h0, p0, z3.h
-+[^:]+: 045923e0 eorv h0, p0, z31.h
-+[^:]+: 045923e0 eorv h0, p0, z31.h
-+[^:]+: 04992000 eorv s0, p0, z0.s
-+[^:]+: 04992000 eorv s0, p0, z0.s
-+[^:]+: 04992001 eorv s1, p0, z0.s
-+[^:]+: 04992001 eorv s1, p0, z0.s
-+[^:]+: 0499201f eorv s31, p0, z0.s
-+[^:]+: 0499201f eorv s31, p0, z0.s
-+[^:]+: 04992800 eorv s0, p2, z0.s
-+[^:]+: 04992800 eorv s0, p2, z0.s
-+[^:]+: 04993c00 eorv s0, p7, z0.s
-+[^:]+: 04993c00 eorv s0, p7, z0.s
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-+[^:]+: 04992060 eorv s0, p0, z3.s
-+[^:]+: 049923e0 eorv s0, p0, z31.s
-+[^:]+: 049923e0 eorv s0, p0, z31.s
-+[^:]+: 04d92000 eorv d0, p0, z0.d
-+[^:]+: 04d92000 eorv d0, p0, z0.d
-+[^:]+: 04d92001 eorv d1, p0, z0.d
-+[^:]+: 04d92001 eorv d1, p0, z0.d
-+[^:]+: 04d9201f eorv d31, p0, z0.d
-+[^:]+: 04d9201f eorv d31, p0, z0.d
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-+[^:]+: 04d92800 eorv d0, p2, z0.d
-+[^:]+: 04d93c00 eorv d0, p7, z0.d
-+[^:]+: 04d93c00 eorv d0, p7, z0.d
-+[^:]+: 04d92060 eorv d0, p0, z3.d
-+[^:]+: 04d92060 eorv d0, p0, z3.d
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-+[^:]+: 04d923e0 eorv d0, p0, z31.d
-+[^:]+: 05200000 ext z0.b, z0.b, z0.b, #0
-+[^:]+: 05200000 ext z0.b, z0.b, z0.b, #0
-+[^:]+: 05200001 ext z1.b, z1.b, z0.b, #0
-+[^:]+: 05200001 ext z1.b, z1.b, z0.b, #0
-+[^:]+: 0520001f ext z31.b, z31.b, z0.b, #0
-+[^:]+: 0520001f ext z31.b, z31.b, z0.b, #0
-+[^:]+: 05200002 ext z2.b, z2.b, z0.b, #0
-+[^:]+: 05200002 ext z2.b, z2.b, z0.b, #0
-+[^:]+: 05200060 ext z0.b, z0.b, z3.b, #0
-+[^:]+: 05200060 ext z0.b, z0.b, z3.b, #0
-+[^:]+: 052003e0 ext z0.b, z0.b, z31.b, #0
-+[^:]+: 052003e0 ext z0.b, z0.b, z31.b, #0
-+[^:]+: 052f1c00 ext z0.b, z0.b, z0.b, #127
-+[^:]+: 052f1c00 ext z0.b, z0.b, z0.b, #127
-+[^:]+: 05300000 ext z0.b, z0.b, z0.b, #128
-+[^:]+: 05300000 ext z0.b, z0.b, z0.b, #128
-+[^:]+: 05300400 ext z0.b, z0.b, z0.b, #129
-+[^:]+: 05300400 ext z0.b, z0.b, z0.b, #129
-+[^:]+: 053f1c00 ext z0.b, z0.b, z0.b, #255
-+[^:]+: 053f1c00 ext z0.b, z0.b, z0.b, #255
-+[^:]+: 65488000 fabd z0.h, p0/m, z0.h, z0.h
-+[^:]+: 65488000 fabd z0.h, p0/m, z0.h, z0.h
-+[^:]+: 65488001 fabd z1.h, p0/m, z1.h, z0.h
-+[^:]+: 65488001 fabd z1.h, p0/m, z1.h, z0.h
-+[^:]+: 6548801f fabd z31.h, p0/m, z31.h, z0.h
-+[^:]+: 6548801f fabd z31.h, p0/m, z31.h, z0.h
-+[^:]+: 65488800 fabd z0.h, p2/m, z0.h, z0.h
-+[^:]+: 65488800 fabd z0.h, p2/m, z0.h, z0.h
-+[^:]+: 65489c00 fabd z0.h, p7/m, z0.h, z0.h
-+[^:]+: 65489c00 fabd z0.h, p7/m, z0.h, z0.h
-+[^:]+: 65488003 fabd z3.h, p0/m, z3.h, z0.h
-+[^:]+: 65488003 fabd z3.h, p0/m, z3.h, z0.h
-+[^:]+: 65488080 fabd z0.h, p0/m, z0.h, z4.h
-+[^:]+: 65488080 fabd z0.h, p0/m, z0.h, z4.h
-+[^:]+: 654883e0 fabd z0.h, p0/m, z0.h, z31.h
-+[^:]+: 654883e0 fabd z0.h, p0/m, z0.h, z31.h
-+[^:]+: 65888000 fabd z0.s, p0/m, z0.s, z0.s
-+[^:]+: 65888000 fabd z0.s, p0/m, z0.s, z0.s
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-+[^:]+: 65888001 fabd z1.s, p0/m, z1.s, z0.s
-+[^:]+: 6588801f fabd z31.s, p0/m, z31.s, z0.s
-+[^:]+: 6588801f fabd z31.s, p0/m, z31.s, z0.s
-+[^:]+: 65888800 fabd z0.s, p2/m, z0.s, z0.s
-+[^:]+: 65888800 fabd z0.s, p2/m, z0.s, z0.s
-+[^:]+: 65889c00 fabd z0.s, p7/m, z0.s, z0.s
-+[^:]+: 65889c00 fabd z0.s, p7/m, z0.s, z0.s
-+[^:]+: 65888003 fabd z3.s, p0/m, z3.s, z0.s
-+[^:]+: 65888003 fabd z3.s, p0/m, z3.s, z0.s
-+[^:]+: 65888080 fabd z0.s, p0/m, z0.s, z4.s
-+[^:]+: 65888080 fabd z0.s, p0/m, z0.s, z4.s
-+[^:]+: 658883e0 fabd z0.s, p0/m, z0.s, z31.s
-+[^:]+: 658883e0 fabd z0.s, p0/m, z0.s, z31.s
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-+[^:]+: 65c88000 fabd z0.d, p0/m, z0.d, z0.d
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-+[^:]+: 65c88001 fabd z1.d, p0/m, z1.d, z0.d
-+[^:]+: 65c8801f fabd z31.d, p0/m, z31.d, z0.d
-+[^:]+: 65c8801f fabd z31.d, p0/m, z31.d, z0.d
-+[^:]+: 65c88800 fabd z0.d, p2/m, z0.d, z0.d
-+[^:]+: 65c88800 fabd z0.d, p2/m, z0.d, z0.d
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-+[^:]+: 65c89c00 fabd z0.d, p7/m, z0.d, z0.d
-+[^:]+: 65c88003 fabd z3.d, p0/m, z3.d, z0.d
-+[^:]+: 65c88003 fabd z3.d, p0/m, z3.d, z0.d
-+[^:]+: 65c88080 fabd z0.d, p0/m, z0.d, z4.d
-+[^:]+: 65c88080 fabd z0.d, p0/m, z0.d, z4.d
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-+[^:]+: 65c883e0 fabd z0.d, p0/m, z0.d, z31.d
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-+[^:]+: 045ca000 fabs z0.h, p0/m, z0.h
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-+[^:]+: 045ca001 fabs z1.h, p0/m, z0.h
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-+[^:]+: 045ca800 fabs z0.h, p2/m, z0.h
-+[^:]+: 045cbc00 fabs z0.h, p7/m, z0.h
-+[^:]+: 045cbc00 fabs z0.h, p7/m, z0.h
-+[^:]+: 045ca060 fabs z0.h, p0/m, z3.h
-+[^:]+: 045ca060 fabs z0.h, p0/m, z3.h
-+[^:]+: 045ca3e0 fabs z0.h, p0/m, z31.h
-+[^:]+: 045ca3e0 fabs z0.h, p0/m, z31.h
-+[^:]+: 049ca000 fabs z0.s, p0/m, z0.s
-+[^:]+: 049ca000 fabs z0.s, p0/m, z0.s
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-+[^:]+: 049ca01f fabs z31.s, p0/m, z0.s
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-+[^:]+: 049ca800 fabs z0.s, p2/m, z0.s
-+[^:]+: 049cbc00 fabs z0.s, p7/m, z0.s
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-+[^:]+: 049ca060 fabs z0.s, p0/m, z3.s
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-+[^:]+: 049ca3e0 fabs z0.s, p0/m, z31.s
-+[^:]+: 04dca000 fabs z0.d, p0/m, z0.d
-+[^:]+: 04dca000 fabs z0.d, p0/m, z0.d
-+[^:]+: 04dca001 fabs z1.d, p0/m, z0.d
-+[^:]+: 04dca001 fabs z1.d, p0/m, z0.d
-+[^:]+: 04dca01f fabs z31.d, p0/m, z0.d
-+[^:]+: 04dca01f fabs z31.d, p0/m, z0.d
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-+[^:]+: 04dca3e0 fabs z0.d, p0/m, z31.d
-+[^:]+: 6540c010 facge p0.h, p0/z, z0.h, z0.h
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-+[^:]+: 655fc000 fcmuo p0.h, p0/z, z0.h, z31.h
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-+[^:]+: 65c0c00f fcmuo p15.d, p0/z, z0.d, z0.d
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-+[^:]+: 65c0dc00 fcmuo p0.d, p7/z, z0.d, z0.d
-+[^:]+: 65c0dc00 fcmuo p0.d, p7/z, z0.d, z0.d
-+[^:]+: 65c0c060 fcmuo p0.d, p0/z, z3.d, z0.d
-+[^:]+: 65c0c060 fcmuo p0.d, p0/z, z3.d, z0.d
-+[^:]+: 65c0c3e0 fcmuo p0.d, p0/z, z31.d, z0.d
-+[^:]+: 65c0c3e0 fcmuo p0.d, p0/z, z31.d, z0.d
-+[^:]+: 65c4c000 fcmuo p0.d, p0/z, z0.d, z4.d
-+[^:]+: 65c4c000 fcmuo p0.d, p0/z, z0.d, z4.d
-+[^:]+: 65dfc000 fcmuo p0.d, p0/z, z0.d, z31.d
-+[^:]+: 65dfc000 fcmuo p0.d, p0/z, z0.d, z31.d
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-+[^:]+: 055fc000 fmov z0.h, p15/m, #2.0+e\+00
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-+[^:]+: 6588a000 fcvt z0.h, p0/m, z0.s
-+[^:]+: 6588a000 fcvt z0.h, p0/m, z0.s
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-+[^:]+: 6588bc00 fcvt z0.h, p7/m, z0.s
-+[^:]+: 6588a060 fcvt z0.h, p0/m, z3.s
-+[^:]+: 6588a060 fcvt z0.h, p0/m, z3.s
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-+[^:]+: 6588a3e0 fcvt z0.h, p0/m, z31.s
-+[^:]+: 6589a000 fcvt z0.s, p0/m, z0.h
-+[^:]+: 6589a000 fcvt z0.s, p0/m, z0.h
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-+[^:]+: 6589a01f fcvt z31.s, p0/m, z0.h
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-+[^:]+: 6589bc00 fcvt z0.s, p7/m, z0.h
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-+[^:]+: 6589a3e0 fcvt z0.s, p0/m, z31.h
-+[^:]+: 65c8a000 fcvt z0.h, p0/m, z0.d
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-+[^:]+: 655aa000 fcvtzs z0.h, p0/m, z0.h
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-+[^:]+: 655ba000 fcvtzu z0.h, p0/m, z0.h
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-+[^:]+: 655ba001 fcvtzu z1.h, p0/m, z0.h
-+[^:]+: 655ba01f fcvtzu z31.h, p0/m, z0.h
-+[^:]+: 655ba01f fcvtzu z31.h, p0/m, z0.h
-+[^:]+: 655ba800 fcvtzu z0.h, p2/m, z0.h
-+[^:]+: 655ba800 fcvtzu z0.h, p2/m, z0.h
-+[^:]+: 655bbc00 fcvtzu z0.h, p7/m, z0.h
-+[^:]+: 655bbc00 fcvtzu z0.h, p7/m, z0.h
-+[^:]+: 655ba060 fcvtzu z0.h, p0/m, z3.h
-+[^:]+: 655ba060 fcvtzu z0.h, p0/m, z3.h
-+[^:]+: 655ba3e0 fcvtzu z0.h, p0/m, z31.h
-+[^:]+: 655ba3e0 fcvtzu z0.h, p0/m, z31.h
-+[^:]+: 655da000 fcvtzu z0.s, p0/m, z0.h
-+[^:]+: 655da000 fcvtzu z0.s, p0/m, z0.h
-+[^:]+: 655da001 fcvtzu z1.s, p0/m, z0.h
-+[^:]+: 655da001 fcvtzu z1.s, p0/m, z0.h
-+[^:]+: 655da01f fcvtzu z31.s, p0/m, z0.h
-+[^:]+: 655da01f fcvtzu z31.s, p0/m, z0.h
-+[^:]+: 655da800 fcvtzu z0.s, p2/m, z0.h
-+[^:]+: 655da800 fcvtzu z0.s, p2/m, z0.h
-+[^:]+: 655dbc00 fcvtzu z0.s, p7/m, z0.h
-+[^:]+: 655dbc00 fcvtzu z0.s, p7/m, z0.h
-+[^:]+: 655da060 fcvtzu z0.s, p0/m, z3.h
-+[^:]+: 655da060 fcvtzu z0.s, p0/m, z3.h
-+[^:]+: 655da3e0 fcvtzu z0.s, p0/m, z31.h
-+[^:]+: 655da3e0 fcvtzu z0.s, p0/m, z31.h
-+[^:]+: 655fa000 fcvtzu z0.d, p0/m, z0.h
-+[^:]+: 655fa000 fcvtzu z0.d, p0/m, z0.h
-+[^:]+: 655fa001 fcvtzu z1.d, p0/m, z0.h
-+[^:]+: 655fa001 fcvtzu z1.d, p0/m, z0.h
-+[^:]+: 655fa01f fcvtzu z31.d, p0/m, z0.h
-+[^:]+: 655fa01f fcvtzu z31.d, p0/m, z0.h
-+[^:]+: 655fa800 fcvtzu z0.d, p2/m, z0.h
-+[^:]+: 655fa800 fcvtzu z0.d, p2/m, z0.h
-+[^:]+: 655fbc00 fcvtzu z0.d, p7/m, z0.h
-+[^:]+: 655fbc00 fcvtzu z0.d, p7/m, z0.h
-+[^:]+: 655fa060 fcvtzu z0.d, p0/m, z3.h
-+[^:]+: 655fa060 fcvtzu z0.d, p0/m, z3.h
-+[^:]+: 655fa3e0 fcvtzu z0.d, p0/m, z31.h
-+[^:]+: 655fa3e0 fcvtzu z0.d, p0/m, z31.h
-+[^:]+: 659da000 fcvtzu z0.s, p0/m, z0.s
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-+[^:]+: 659da001 fcvtzu z1.s, p0/m, z0.s
-+[^:]+: 659da01f fcvtzu z31.s, p0/m, z0.s
-+[^:]+: 659da01f fcvtzu z31.s, p0/m, z0.s
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-+[^:]+: 659da800 fcvtzu z0.s, p2/m, z0.s
-+[^:]+: 659dbc00 fcvtzu z0.s, p7/m, z0.s
-+[^:]+: 659dbc00 fcvtzu z0.s, p7/m, z0.s
-+[^:]+: 659da060 fcvtzu z0.s, p0/m, z3.s
-+[^:]+: 659da060 fcvtzu z0.s, p0/m, z3.s
-+[^:]+: 659da3e0 fcvtzu z0.s, p0/m, z31.s
-+[^:]+: 659da3e0 fcvtzu z0.s, p0/m, z31.s
-+[^:]+: 65d9a000 fcvtzu z0.s, p0/m, z0.d
-+[^:]+: 65d9a000 fcvtzu z0.s, p0/m, z0.d
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-+[^:]+: 65d9a001 fcvtzu z1.s, p0/m, z0.d
-+[^:]+: 65d9a01f fcvtzu z31.s, p0/m, z0.d
-+[^:]+: 65d9a01f fcvtzu z31.s, p0/m, z0.d
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-+[^:]+: 65d9a800 fcvtzu z0.s, p2/m, z0.d
-+[^:]+: 65d9bc00 fcvtzu z0.s, p7/m, z0.d
-+[^:]+: 65d9bc00 fcvtzu z0.s, p7/m, z0.d
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-+[^:]+: 65d9a060 fcvtzu z0.s, p0/m, z3.d
-+[^:]+: 65d9a3e0 fcvtzu z0.s, p0/m, z31.d
-+[^:]+: 65d9a3e0 fcvtzu z0.s, p0/m, z31.d
-+[^:]+: 65dda000 fcvtzu z0.d, p0/m, z0.s
-+[^:]+: 65dda000 fcvtzu z0.d, p0/m, z0.s
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-+[^:]+: 65dda001 fcvtzu z1.d, p0/m, z0.s
-+[^:]+: 65dda01f fcvtzu z31.d, p0/m, z0.s
-+[^:]+: 65dda01f fcvtzu z31.d, p0/m, z0.s
-+[^:]+: 65dda800 fcvtzu z0.d, p2/m, z0.s
-+[^:]+: 65dda800 fcvtzu z0.d, p2/m, z0.s
-+[^:]+: 65ddbc00 fcvtzu z0.d, p7/m, z0.s
-+[^:]+: 65ddbc00 fcvtzu z0.d, p7/m, z0.s
-+[^:]+: 65dda060 fcvtzu z0.d, p0/m, z3.s
-+[^:]+: 65dda060 fcvtzu z0.d, p0/m, z3.s
-+[^:]+: 65dda3e0 fcvtzu z0.d, p0/m, z31.s
-+[^:]+: 65dda3e0 fcvtzu z0.d, p0/m, z31.s
-+[^:]+: 65dfa000 fcvtzu z0.d, p0/m, z0.d
-+[^:]+: 65dfa000 fcvtzu z0.d, p0/m, z0.d
-+[^:]+: 65dfa001 fcvtzu z1.d, p0/m, z0.d
-+[^:]+: 65dfa001 fcvtzu z1.d, p0/m, z0.d
-+[^:]+: 65dfa01f fcvtzu z31.d, p0/m, z0.d
-+[^:]+: 65dfa01f fcvtzu z31.d, p0/m, z0.d
-+[^:]+: 65dfa800 fcvtzu z0.d, p2/m, z0.d
-+[^:]+: 65dfa800 fcvtzu z0.d, p2/m, z0.d
-+[^:]+: 65dfbc00 fcvtzu z0.d, p7/m, z0.d
-+[^:]+: 65dfbc00 fcvtzu z0.d, p7/m, z0.d
-+[^:]+: 65dfa060 fcvtzu z0.d, p0/m, z3.d
-+[^:]+: 65dfa060 fcvtzu z0.d, p0/m, z3.d
-+[^:]+: 65dfa3e0 fcvtzu z0.d, p0/m, z31.d
-+[^:]+: 65dfa3e0 fcvtzu z0.d, p0/m, z31.d
-+[^:]+: 654d8000 fdiv z0.h, p0/m, z0.h, z0.h
-+[^:]+: 654d8000 fdiv z0.h, p0/m, z0.h, z0.h
-+[^:]+: 654d8001 fdiv z1.h, p0/m, z1.h, z0.h
-+[^:]+: 654d8001 fdiv z1.h, p0/m, z1.h, z0.h
-+[^:]+: 654d801f fdiv z31.h, p0/m, z31.h, z0.h
-+[^:]+: 654d801f fdiv z31.h, p0/m, z31.h, z0.h
-+[^:]+: 654d8800 fdiv z0.h, p2/m, z0.h, z0.h
-+[^:]+: 654d8800 fdiv z0.h, p2/m, z0.h, z0.h
-+[^:]+: 654d9c00 fdiv z0.h, p7/m, z0.h, z0.h
-+[^:]+: 654d9c00 fdiv z0.h, p7/m, z0.h, z0.h
-+[^:]+: 654d8003 fdiv z3.h, p0/m, z3.h, z0.h
-+[^:]+: 654d8003 fdiv z3.h, p0/m, z3.h, z0.h
-+[^:]+: 654d8080 fdiv z0.h, p0/m, z0.h, z4.h
-+[^:]+: 654d8080 fdiv z0.h, p0/m, z0.h, z4.h
-+[^:]+: 654d83e0 fdiv z0.h, p0/m, z0.h, z31.h
-+[^:]+: 654d83e0 fdiv z0.h, p0/m, z0.h, z31.h
-+[^:]+: 658d8000 fdiv z0.s, p0/m, z0.s, z0.s
-+[^:]+: 658d8000 fdiv z0.s, p0/m, z0.s, z0.s
-+[^:]+: 658d8001 fdiv z1.s, p0/m, z1.s, z0.s
-+[^:]+: 658d8001 fdiv z1.s, p0/m, z1.s, z0.s
-+[^:]+: 658d801f fdiv z31.s, p0/m, z31.s, z0.s
-+[^:]+: 658d801f fdiv z31.s, p0/m, z31.s, z0.s
-+[^:]+: 658d8800 fdiv z0.s, p2/m, z0.s, z0.s
-+[^:]+: 658d8800 fdiv z0.s, p2/m, z0.s, z0.s
-+[^:]+: 658d9c00 fdiv z0.s, p7/m, z0.s, z0.s
-+[^:]+: 658d9c00 fdiv z0.s, p7/m, z0.s, z0.s
-+[^:]+: 658d8003 fdiv z3.s, p0/m, z3.s, z0.s
-+[^:]+: 658d8003 fdiv z3.s, p0/m, z3.s, z0.s
-+[^:]+: 658d8080 fdiv z0.s, p0/m, z0.s, z4.s
-+[^:]+: 658d8080 fdiv z0.s, p0/m, z0.s, z4.s
-+[^:]+: 658d83e0 fdiv z0.s, p0/m, z0.s, z31.s
-+[^:]+: 658d83e0 fdiv z0.s, p0/m, z0.s, z31.s
-+[^:]+: 65cd8000 fdiv z0.d, p0/m, z0.d, z0.d
-+[^:]+: 65cd8000 fdiv z0.d, p0/m, z0.d, z0.d
-+[^:]+: 65cd8001 fdiv z1.d, p0/m, z1.d, z0.d
-+[^:]+: 65cd8001 fdiv z1.d, p0/m, z1.d, z0.d
-+[^:]+: 65cd801f fdiv z31.d, p0/m, z31.d, z0.d
-+[^:]+: 65cd801f fdiv z31.d, p0/m, z31.d, z0.d
-+[^:]+: 65cd8800 fdiv z0.d, p2/m, z0.d, z0.d
-+[^:]+: 65cd8800 fdiv z0.d, p2/m, z0.d, z0.d
-+[^:]+: 65cd9c00 fdiv z0.d, p7/m, z0.d, z0.d
-+[^:]+: 65cd9c00 fdiv z0.d, p7/m, z0.d, z0.d
-+[^:]+: 65cd8003 fdiv z3.d, p0/m, z3.d, z0.d
-+[^:]+: 65cd8003 fdiv z3.d, p0/m, z3.d, z0.d
-+[^:]+: 65cd8080 fdiv z0.d, p0/m, z0.d, z4.d
-+[^:]+: 65cd8080 fdiv z0.d, p0/m, z0.d, z4.d
-+[^:]+: 65cd83e0 fdiv z0.d, p0/m, z0.d, z31.d
-+[^:]+: 65cd83e0 fdiv z0.d, p0/m, z0.d, z31.d
-+[^:]+: 654c8000 fdivr z0.h, p0/m, z0.h, z0.h
-+[^:]+: 654c8000 fdivr z0.h, p0/m, z0.h, z0.h
-+[^:]+: 654c8001 fdivr z1.h, p0/m, z1.h, z0.h
-+[^:]+: 654c8001 fdivr z1.h, p0/m, z1.h, z0.h
-+[^:]+: 654c801f fdivr z31.h, p0/m, z31.h, z0.h
-+[^:]+: 654c801f fdivr z31.h, p0/m, z31.h, z0.h
-+[^:]+: 654c8800 fdivr z0.h, p2/m, z0.h, z0.h
-+[^:]+: 654c8800 fdivr z0.h, p2/m, z0.h, z0.h
-+[^:]+: 654c9c00 fdivr z0.h, p7/m, z0.h, z0.h
-+[^:]+: 654c9c00 fdivr z0.h, p7/m, z0.h, z0.h
-+[^:]+: 654c8003 fdivr z3.h, p0/m, z3.h, z0.h
-+[^:]+: 654c8003 fdivr z3.h, p0/m, z3.h, z0.h
-+[^:]+: 654c8080 fdivr z0.h, p0/m, z0.h, z4.h
-+[^:]+: 654c8080 fdivr z0.h, p0/m, z0.h, z4.h
-+[^:]+: 654c83e0 fdivr z0.h, p0/m, z0.h, z31.h
-+[^:]+: 654c83e0 fdivr z0.h, p0/m, z0.h, z31.h
-+[^:]+: 658c8000 fdivr z0.s, p0/m, z0.s, z0.s
-+[^:]+: 658c8000 fdivr z0.s, p0/m, z0.s, z0.s
-+[^:]+: 658c8001 fdivr z1.s, p0/m, z1.s, z0.s
-+[^:]+: 658c8001 fdivr z1.s, p0/m, z1.s, z0.s
-+[^:]+: 658c801f fdivr z31.s, p0/m, z31.s, z0.s
-+[^:]+: 658c801f fdivr z31.s, p0/m, z31.s, z0.s
-+[^:]+: 658c8800 fdivr z0.s, p2/m, z0.s, z0.s
-+[^:]+: 658c8800 fdivr z0.s, p2/m, z0.s, z0.s
-+[^:]+: 658c9c00 fdivr z0.s, p7/m, z0.s, z0.s
-+[^:]+: 658c9c00 fdivr z0.s, p7/m, z0.s, z0.s
-+[^:]+: 658c8003 fdivr z3.s, p0/m, z3.s, z0.s
-+[^:]+: 658c8003 fdivr z3.s, p0/m, z3.s, z0.s
-+[^:]+: 658c8080 fdivr z0.s, p0/m, z0.s, z4.s
-+[^:]+: 658c8080 fdivr z0.s, p0/m, z0.s, z4.s
-+[^:]+: 658c83e0 fdivr z0.s, p0/m, z0.s, z31.s
-+[^:]+: 658c83e0 fdivr z0.s, p0/m, z0.s, z31.s
-+[^:]+: 65cc8000 fdivr z0.d, p0/m, z0.d, z0.d
-+[^:]+: 65cc8000 fdivr z0.d, p0/m, z0.d, z0.d
-+[^:]+: 65cc8001 fdivr z1.d, p0/m, z1.d, z0.d
-+[^:]+: 65cc8001 fdivr z1.d, p0/m, z1.d, z0.d
-+[^:]+: 65cc801f fdivr z31.d, p0/m, z31.d, z0.d
-+[^:]+: 65cc801f fdivr z31.d, p0/m, z31.d, z0.d
-+[^:]+: 65cc8800 fdivr z0.d, p2/m, z0.d, z0.d
-+[^:]+: 65cc8800 fdivr z0.d, p2/m, z0.d, z0.d
-+[^:]+: 65cc9c00 fdivr z0.d, p7/m, z0.d, z0.d
-+[^:]+: 65cc9c00 fdivr z0.d, p7/m, z0.d, z0.d
-+[^:]+: 65cc8003 fdivr z3.d, p0/m, z3.d, z0.d
-+[^:]+: 65cc8003 fdivr z3.d, p0/m, z3.d, z0.d
-+[^:]+: 65cc8080 fdivr z0.d, p0/m, z0.d, z4.d
-+[^:]+: 65cc8080 fdivr z0.d, p0/m, z0.d, z4.d
-+[^:]+: 65cc83e0 fdivr z0.d, p0/m, z0.d, z31.d
-+[^:]+: 65cc83e0 fdivr z0.d, p0/m, z0.d, z31.d
-+[^:]+: 2579c000 fmov z0.h, #2.0+e\+00
-+[^:]+: 2579c000 fmov z0.h, #2.0+e\+00
-+[^:]+: 2579c001 fmov z1.h, #2.0+e\+00
-+[^:]+: 2579c001 fmov z1.h, #2.0+e\+00
-+[^:]+: 2579c01f fmov z31.h, #2.0+e\+00
-+[^:]+: 2579c01f fmov z31.h, #2.0+e\+00
-+[^:]+: 2579c600 fmov z0.h, #1.60+e\+01
-+[^:]+: 2579c600 fmov z0.h, #1.60+e\+01
-+[^:]+: 2579c900 fmov z0.h, #1.8750+e-01
-+[^:]+: 2579c900 fmov z0.h, #1.8750+e-01
-+[^:]+: 2579cfe0 fmov z0.h, #1.93750+e\+00
-+[^:]+: 2579cfe0 fmov z0.h, #1.93750+e\+00
-+[^:]+: 2579d100 fmov z0.h, #-3.0+e\+00
-+[^:]+: 2579d100 fmov z0.h, #-3.0+e\+00
-+[^:]+: 2579d800 fmov z0.h, #-1.250+e-01
-+[^:]+: 2579d800 fmov z0.h, #-1.250+e-01
-+[^:]+: 2579dfe0 fmov z0.h, #-1.93750+e\+00
-+[^:]+: 2579dfe0 fmov z0.h, #-1.93750+e\+00
-+[^:]+: 25b9c000 fmov z0.s, #2.0+e\+00
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-+[^:]+: 25b9c01f fmov z31.s, #2.0+e\+00
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-+[^:]+: 25b9c600 fmov z0.s, #1.60+e\+01
-+[^:]+: 25b9c600 fmov z0.s, #1.60+e\+01
-+[^:]+: 25b9c900 fmov z0.s, #1.8750+e-01
-+[^:]+: 25b9c900 fmov z0.s, #1.8750+e-01
-+[^:]+: 25b9cfe0 fmov z0.s, #1.93750+e\+00
-+[^:]+: 25b9cfe0 fmov z0.s, #1.93750+e\+00
-+[^:]+: 25b9d100 fmov z0.s, #-3.0+e\+00
-+[^:]+: 25b9d100 fmov z0.s, #-3.0+e\+00
-+[^:]+: 25b9d800 fmov z0.s, #-1.250+e-01
-+[^:]+: 25b9d800 fmov z0.s, #-1.250+e-01
-+[^:]+: 25b9dfe0 fmov z0.s, #-1.93750+e\+00
-+[^:]+: 25b9dfe0 fmov z0.s, #-1.93750+e\+00
-+[^:]+: 25f9c000 fmov z0.d, #2.0+e\+00
-+[^:]+: 25f9c000 fmov z0.d, #2.0+e\+00
-+[^:]+: 25f9c001 fmov z1.d, #2.0+e\+00
-+[^:]+: 25f9c001 fmov z1.d, #2.0+e\+00
-+[^:]+: 25f9c01f fmov z31.d, #2.0+e\+00
-+[^:]+: 25f9c01f fmov z31.d, #2.0+e\+00
-+[^:]+: 25f9c600 fmov z0.d, #1.60+e\+01
-+[^:]+: 25f9c600 fmov z0.d, #1.60+e\+01
-+[^:]+: 25f9c900 fmov z0.d, #1.8750+e-01
-+[^:]+: 25f9c900 fmov z0.d, #1.8750+e-01
-+[^:]+: 25f9cfe0 fmov z0.d, #1.93750+e\+00
-+[^:]+: 25f9cfe0 fmov z0.d, #1.93750+e\+00
-+[^:]+: 25f9d100 fmov z0.d, #-3.0+e\+00
-+[^:]+: 25f9d100 fmov z0.d, #-3.0+e\+00
-+[^:]+: 25f9d800 fmov z0.d, #-1.250+e-01
-+[^:]+: 25f9d800 fmov z0.d, #-1.250+e-01
-+[^:]+: 25f9dfe0 fmov z0.d, #-1.93750+e\+00
-+[^:]+: 25f9dfe0 fmov z0.d, #-1.93750+e\+00
-+[^:]+: 0460b800 fexpa z0.h, z0.h
-+[^:]+: 0460b800 fexpa z0.h, z0.h
-+[^:]+: 0460b801 fexpa z1.h, z0.h
-+[^:]+: 0460b801 fexpa z1.h, z0.h
-+[^:]+: 0460b81f fexpa z31.h, z0.h
-+[^:]+: 0460b81f fexpa z31.h, z0.h
-+[^:]+: 0460b840 fexpa z0.h, z2.h
-+[^:]+: 0460b840 fexpa z0.h, z2.h
-+[^:]+: 0460bbe0 fexpa z0.h, z31.h
-+[^:]+: 0460bbe0 fexpa z0.h, z31.h
-+[^:]+: 04a0b800 fexpa z0.s, z0.s
-+[^:]+: 04a0b800 fexpa z0.s, z0.s
-+[^:]+: 04a0b801 fexpa z1.s, z0.s
-+[^:]+: 04a0b801 fexpa z1.s, z0.s
-+[^:]+: 04a0b81f fexpa z31.s, z0.s
-+[^:]+: 04a0b81f fexpa z31.s, z0.s
-+[^:]+: 04a0b840 fexpa z0.s, z2.s
-+[^:]+: 04a0b840 fexpa z0.s, z2.s
-+[^:]+: 04a0bbe0 fexpa z0.s, z31.s
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-+[^:]+: 64a82000 fmul z0.s, z0.s, z0.s\[1\]
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-+[^:]+: 045da000 fneg z0.h, p0/m, z0.h
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-+[^:]+: 6560dc00 fnmad z0.h, p7/m, z0.h, z0.h
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-+[^:]+: 6564c000 fnmad z0.h, p0/m, z0.h, z4.h
-+[^:]+: 6564c000 fnmad z0.h, p0/m, z0.h, z4.h
-+[^:]+: 657fc000 fnmad z0.h, p0/m, z0.h, z31.h
-+[^:]+: 657fc000 fnmad z0.h, p0/m, z0.h, z31.h
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-+[^:]+: 65ff4000 fnmla z0.d, p0/m, z0.d, z31.d
-+[^:]+: 65ff4000 fnmla z0.d, p0/m, z0.d, z31.d
-+[^:]+: 65606000 fnmls z0.h, p0/m, z0.h, z0.h
-+[^:]+: 65606000 fnmls z0.h, p0/m, z0.h, z0.h
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-+[^:]+: 65606001 fnmls z1.h, p0/m, z0.h, z0.h
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-+[^:]+: 6560601f fnmls z31.h, p0/m, z0.h, z0.h
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-+[^:]+: 65607c00 fnmls z0.h, p7/m, z0.h, z0.h
-+[^:]+: 65606060 fnmls z0.h, p0/m, z3.h, z0.h
-+[^:]+: 65606060 fnmls z0.h, p0/m, z3.h, z0.h
-+[^:]+: 656063e0 fnmls z0.h, p0/m, z31.h, z0.h
-+[^:]+: 656063e0 fnmls z0.h, p0/m, z31.h, z0.h
-+[^:]+: 65646000 fnmls z0.h, p0/m, z0.h, z4.h
-+[^:]+: 65646000 fnmls z0.h, p0/m, z0.h, z4.h
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-+[^:]+: 65800c1f ftsmul z31.s, z0.s, z0.s
-+[^:]+: 65800c1f ftsmul z31.s, z0.s, z0.s
-+[^:]+: 65800c40 ftsmul z0.s, z2.s, z0.s
-+[^:]+: 65800c40 ftsmul z0.s, z2.s, z0.s
-+[^:]+: 65800fe0 ftsmul z0.s, z31.s, z0.s
-+[^:]+: 65800fe0 ftsmul z0.s, z31.s, z0.s
-+[^:]+: 65830c00 ftsmul z0.s, z0.s, z3.s
-+[^:]+: 65830c00 ftsmul z0.s, z0.s, z3.s
-+[^:]+: 659f0c00 ftsmul z0.s, z0.s, z31.s
-+[^:]+: 659f0c00 ftsmul z0.s, z0.s, z31.s
-+[^:]+: 65c00c00 ftsmul z0.d, z0.d, z0.d
-+[^:]+: 65c00c00 ftsmul z0.d, z0.d, z0.d
-+[^:]+: 65c00c01 ftsmul z1.d, z0.d, z0.d
-+[^:]+: 65c00c01 ftsmul z1.d, z0.d, z0.d
-+[^:]+: 65c00c1f ftsmul z31.d, z0.d, z0.d
-+[^:]+: 65c00c1f ftsmul z31.d, z0.d, z0.d
-+[^:]+: 65c00c40 ftsmul z0.d, z2.d, z0.d
-+[^:]+: 65c00c40 ftsmul z0.d, z2.d, z0.d
-+[^:]+: 65c00fe0 ftsmul z0.d, z31.d, z0.d
-+[^:]+: 65c00fe0 ftsmul z0.d, z31.d, z0.d
-+[^:]+: 65c30c00 ftsmul z0.d, z0.d, z3.d
-+[^:]+: 65c30c00 ftsmul z0.d, z0.d, z3.d
-+[^:]+: 65df0c00 ftsmul z0.d, z0.d, z31.d
-+[^:]+: 65df0c00 ftsmul z0.d, z0.d, z31.d
-+[^:]+: 0460b000 ftssel z0.h, z0.h, z0.h
-+[^:]+: 0460b000 ftssel z0.h, z0.h, z0.h
-+[^:]+: 0460b001 ftssel z1.h, z0.h, z0.h
-+[^:]+: 0460b001 ftssel z1.h, z0.h, z0.h
-+[^:]+: 0460b01f ftssel z31.h, z0.h, z0.h
-+[^:]+: 0460b01f ftssel z31.h, z0.h, z0.h
-+[^:]+: 0460b040 ftssel z0.h, z2.h, z0.h
-+[^:]+: 0460b040 ftssel z0.h, z2.h, z0.h
-+[^:]+: 0460b3e0 ftssel z0.h, z31.h, z0.h
-+[^:]+: 0460b3e0 ftssel z0.h, z31.h, z0.h
-+[^:]+: 0463b000 ftssel z0.h, z0.h, z3.h
-+[^:]+: 0463b000 ftssel z0.h, z0.h, z3.h
-+[^:]+: 047fb000 ftssel z0.h, z0.h, z31.h
-+[^:]+: 047fb000 ftssel z0.h, z0.h, z31.h
-+[^:]+: 04a0b000 ftssel z0.s, z0.s, z0.s
-+[^:]+: 04a0b000 ftssel z0.s, z0.s, z0.s
-+[^:]+: 04a0b001 ftssel z1.s, z0.s, z0.s
-+[^:]+: 04a0b001 ftssel z1.s, z0.s, z0.s
-+[^:]+: 04a0b01f ftssel z31.s, z0.s, z0.s
-+[^:]+: 04a0b01f ftssel z31.s, z0.s, z0.s
-+[^:]+: 04a0b040 ftssel z0.s, z2.s, z0.s
-+[^:]+: 04a0b040 ftssel z0.s, z2.s, z0.s
-+[^:]+: 04a0b3e0 ftssel z0.s, z31.s, z0.s
-+[^:]+: 04a0b3e0 ftssel z0.s, z31.s, z0.s
-+[^:]+: 04a3b000 ftssel z0.s, z0.s, z3.s
-+[^:]+: 04a3b000 ftssel z0.s, z0.s, z3.s
-+[^:]+: 04bfb000 ftssel z0.s, z0.s, z31.s
-+[^:]+: 04bfb000 ftssel z0.s, z0.s, z31.s
-+[^:]+: 04e0b000 ftssel z0.d, z0.d, z0.d
-+[^:]+: 04e0b000 ftssel z0.d, z0.d, z0.d
-+[^:]+: 04e0b001 ftssel z1.d, z0.d, z0.d
-+[^:]+: 04e0b001 ftssel z1.d, z0.d, z0.d
-+[^:]+: 04e0b01f ftssel z31.d, z0.d, z0.d
-+[^:]+: 04e0b01f ftssel z31.d, z0.d, z0.d
-+[^:]+: 04e0b040 ftssel z0.d, z2.d, z0.d
-+[^:]+: 04e0b040 ftssel z0.d, z2.d, z0.d
-+[^:]+: 04e0b3e0 ftssel z0.d, z31.d, z0.d
-+[^:]+: 04e0b3e0 ftssel z0.d, z31.d, z0.d
-+[^:]+: 04e3b000 ftssel z0.d, z0.d, z3.d
-+[^:]+: 04e3b000 ftssel z0.d, z0.d, z3.d
-+[^:]+: 04ffb000 ftssel z0.d, z0.d, z31.d
-+[^:]+: 04ffb000 ftssel z0.d, z0.d, z31.d
-+[^:]+: 0430e000 incb x0, pow2
-+[^:]+: 0430e000 incb x0, pow2
-+[^:]+: 0430e000 incb x0, pow2
-+[^:]+: 0430e001 incb x1, pow2
-+[^:]+: 0430e001 incb x1, pow2
-+[^:]+: 0430e001 incb x1, pow2
-+[^:]+: 0430e01f incb xzr, pow2
-+[^:]+: 0430e01f incb xzr, pow2
-+[^:]+: 0430e01f incb xzr, pow2
-+[^:]+: 0430e020 incb x0, vl1
-+[^:]+: 0430e020 incb x0, vl1
-+[^:]+: 0430e020 incb x0, vl1
-+[^:]+: 0430e040 incb x0, vl2
-+[^:]+: 0430e040 incb x0, vl2
-+[^:]+: 0430e040 incb x0, vl2
-+[^:]+: 0430e060 incb x0, vl3
-+[^:]+: 0430e060 incb x0, vl3
-+[^:]+: 0430e060 incb x0, vl3
-+[^:]+: 0430e080 incb x0, vl4
-+[^:]+: 0430e080 incb x0, vl4
-+[^:]+: 0430e080 incb x0, vl4
-+[^:]+: 0430e0a0 incb x0, vl5
-+[^:]+: 0430e0a0 incb x0, vl5
-+[^:]+: 0430e0a0 incb x0, vl5
-+[^:]+: 0430e0c0 incb x0, vl6
-+[^:]+: 0430e0c0 incb x0, vl6
-+[^:]+: 0430e0c0 incb x0, vl6
-+[^:]+: 0430e0e0 incb x0, vl7
-+[^:]+: 0430e0e0 incb x0, vl7
-+[^:]+: 0430e0e0 incb x0, vl7
-+[^:]+: 0430e100 incb x0, vl8
-+[^:]+: 0430e100 incb x0, vl8
-+[^:]+: 0430e100 incb x0, vl8
-+[^:]+: 0430e120 incb x0, vl16
-+[^:]+: 0430e120 incb x0, vl16
-+[^:]+: 0430e120 incb x0, vl16
-+[^:]+: 0430e140 incb x0, vl32
-+[^:]+: 0430e140 incb x0, vl32
-+[^:]+: 0430e140 incb x0, vl32
-+[^:]+: 0430e160 incb x0, vl64
-+[^:]+: 0430e160 incb x0, vl64
-+[^:]+: 0430e160 incb x0, vl64
-+[^:]+: 0430e180 incb x0, vl128
-+[^:]+: 0430e180 incb x0, vl128
-+[^:]+: 0430e180 incb x0, vl128
-+[^:]+: 0430e1a0 incb x0, vl256
-+[^:]+: 0430e1a0 incb x0, vl256
-+[^:]+: 0430e1a0 incb x0, vl256
-+[^:]+: 0430e1c0 incb x0, #14
-+[^:]+: 0430e1c0 incb x0, #14
-+[^:]+: 0430e1c0 incb x0, #14
-+[^:]+: 0430e1e0 incb x0, #15
-+[^:]+: 0430e1e0 incb x0, #15
-+[^:]+: 0430e1e0 incb x0, #15
-+[^:]+: 0430e200 incb x0, #16
-+[^:]+: 0430e200 incb x0, #16
-+[^:]+: 0430e200 incb x0, #16
-+[^:]+: 0430e220 incb x0, #17
-+[^:]+: 0430e220 incb x0, #17
-+[^:]+: 0430e220 incb x0, #17
-+[^:]+: 0430e240 incb x0, #18
-+[^:]+: 0430e240 incb x0, #18
-+[^:]+: 0430e240 incb x0, #18
-+[^:]+: 0430e260 incb x0, #19
-+[^:]+: 0430e260 incb x0, #19
-+[^:]+: 0430e260 incb x0, #19
-+[^:]+: 0430e280 incb x0, #20
-+[^:]+: 0430e280 incb x0, #20
-+[^:]+: 0430e280 incb x0, #20
-+[^:]+: 0430e2a0 incb x0, #21
-+[^:]+: 0430e2a0 incb x0, #21
-+[^:]+: 0430e2a0 incb x0, #21
-+[^:]+: 0430e2c0 incb x0, #22
-+[^:]+: 0430e2c0 incb x0, #22
-+[^:]+: 0430e2c0 incb x0, #22
-+[^:]+: 0430e2e0 incb x0, #23
-+[^:]+: 0430e2e0 incb x0, #23
-+[^:]+: 0430e2e0 incb x0, #23
-+[^:]+: 0430e300 incb x0, #24
-+[^:]+: 0430e300 incb x0, #24
-+[^:]+: 0430e300 incb x0, #24
-+[^:]+: 0430e320 incb x0, #25
-+[^:]+: 0430e320 incb x0, #25
-+[^:]+: 0430e320 incb x0, #25
-+[^:]+: 0430e340 incb x0, #26
-+[^:]+: 0430e340 incb x0, #26
-+[^:]+: 0430e340 incb x0, #26
-+[^:]+: 0430e360 incb x0, #27
-+[^:]+: 0430e360 incb x0, #27
-+[^:]+: 0430e360 incb x0, #27
-+[^:]+: 0430e380 incb x0, #28
-+[^:]+: 0430e380 incb x0, #28
-+[^:]+: 0430e380 incb x0, #28
-+[^:]+: 0430e3a0 incb x0, mul4
-+[^:]+: 0430e3a0 incb x0, mul4
-+[^:]+: 0430e3a0 incb x0, mul4
-+[^:]+: 0430e3c0 incb x0, mul3
-+[^:]+: 0430e3c0 incb x0, mul3
-+[^:]+: 0430e3c0 incb x0, mul3
-+[^:]+: 0430e3e0 incb x0
-+[^:]+: 0430e3e0 incb x0
-+[^:]+: 0430e3e0 incb x0
-+[^:]+: 0430e3e0 incb x0
-+[^:]+: 0437e000 incb x0, pow2, mul #8
-+[^:]+: 0437e000 incb x0, pow2, mul #8
-+[^:]+: 0438e000 incb x0, pow2, mul #9
-+[^:]+: 0438e000 incb x0, pow2, mul #9
-+[^:]+: 0439e000 incb x0, pow2, mul #10
-+[^:]+: 0439e000 incb x0, pow2, mul #10
-+[^:]+: 043fe000 incb x0, pow2, mul #16
-+[^:]+: 043fe000 incb x0, pow2, mul #16
-+[^:]+: 04f0c000 incd z0.d, pow2
-+[^:]+: 04f0c000 incd z0.d, pow2
-+[^:]+: 04f0c000 incd z0.d, pow2
-+[^:]+: 04f0c001 incd z1.d, pow2
-+[^:]+: 04f0c001 incd z1.d, pow2
-+[^:]+: 04f0c001 incd z1.d, pow2
-+[^:]+: 04f0c01f incd z31.d, pow2
-+[^:]+: 04f0c01f incd z31.d, pow2
-+[^:]+: 04f0c01f incd z31.d, pow2
-+[^:]+: 04f0c020 incd z0.d, vl1
-+[^:]+: 04f0c020 incd z0.d, vl1
-+[^:]+: 04f0c020 incd z0.d, vl1
-+[^:]+: 04f0c040 incd z0.d, vl2
-+[^:]+: 04f0c040 incd z0.d, vl2
-+[^:]+: 04f0c040 incd z0.d, vl2
-+[^:]+: 04f0c060 incd z0.d, vl3
-+[^:]+: 04f0c060 incd z0.d, vl3
-+[^:]+: 04f0c060 incd z0.d, vl3
-+[^:]+: 04f0c080 incd z0.d, vl4
-+[^:]+: 04f0c080 incd z0.d, vl4
-+[^:]+: 04f0c080 incd z0.d, vl4
-+[^:]+: 04f0c0a0 incd z0.d, vl5
-+[^:]+: 04f0c0a0 incd z0.d, vl5
-+[^:]+: 04f0c0a0 incd z0.d, vl5
-+[^:]+: 04f0c0c0 incd z0.d, vl6
-+[^:]+: 04f0c0c0 incd z0.d, vl6
-+[^:]+: 04f0c0c0 incd z0.d, vl6
-+[^:]+: 04f0c0e0 incd z0.d, vl7
-+[^:]+: 04f0c0e0 incd z0.d, vl7
-+[^:]+: 04f0c0e0 incd z0.d, vl7
-+[^:]+: 04f0c100 incd z0.d, vl8
-+[^:]+: 04f0c100 incd z0.d, vl8
-+[^:]+: 04f0c100 incd z0.d, vl8
-+[^:]+: 04f0c120 incd z0.d, vl16
-+[^:]+: 04f0c120 incd z0.d, vl16
-+[^:]+: 04f0c120 incd z0.d, vl16
-+[^:]+: 04f0c140 incd z0.d, vl32
-+[^:]+: 04f0c140 incd z0.d, vl32
-+[^:]+: 04f0c140 incd z0.d, vl32
-+[^:]+: 04f0c160 incd z0.d, vl64
-+[^:]+: 04f0c160 incd z0.d, vl64
-+[^:]+: 04f0c160 incd z0.d, vl64
-+[^:]+: 04f0c180 incd z0.d, vl128
-+[^:]+: 04f0c180 incd z0.d, vl128
-+[^:]+: 04f0c180 incd z0.d, vl128
-+[^:]+: 04f0c1a0 incd z0.d, vl256
-+[^:]+: 04f0c1a0 incd z0.d, vl256
-+[^:]+: 04f0c1a0 incd z0.d, vl256
-+[^:]+: 04f0c1c0 incd z0.d, #14
-+[^:]+: 04f0c1c0 incd z0.d, #14
-+[^:]+: 04f0c1c0 incd z0.d, #14
-+[^:]+: 04f0c1e0 incd z0.d, #15
-+[^:]+: 04f0c1e0 incd z0.d, #15
-+[^:]+: 04f0c1e0 incd z0.d, #15
-+[^:]+: 04f0c200 incd z0.d, #16
-+[^:]+: 04f0c200 incd z0.d, #16
-+[^:]+: 04f0c200 incd z0.d, #16
-+[^:]+: 04f0c220 incd z0.d, #17
-+[^:]+: 04f0c220 incd z0.d, #17
-+[^:]+: 04f0c220 incd z0.d, #17
-+[^:]+: 04f0c240 incd z0.d, #18
-+[^:]+: 04f0c240 incd z0.d, #18
-+[^:]+: 04f0c240 incd z0.d, #18
-+[^:]+: 04f0c260 incd z0.d, #19
-+[^:]+: 04f0c260 incd z0.d, #19
-+[^:]+: 04f0c260 incd z0.d, #19
-+[^:]+: 04f0c280 incd z0.d, #20
-+[^:]+: 04f0c280 incd z0.d, #20
-+[^:]+: 04f0c280 incd z0.d, #20
-+[^:]+: 04f0c2a0 incd z0.d, #21
-+[^:]+: 04f0c2a0 incd z0.d, #21
-+[^:]+: 04f0c2a0 incd z0.d, #21
-+[^:]+: 04f0c2c0 incd z0.d, #22
-+[^:]+: 04f0c2c0 incd z0.d, #22
-+[^:]+: 04f0c2c0 incd z0.d, #22
-+[^:]+: 04f0c2e0 incd z0.d, #23
-+[^:]+: 04f0c2e0 incd z0.d, #23
-+[^:]+: 04f0c2e0 incd z0.d, #23
-+[^:]+: 04f0c300 incd z0.d, #24
-+[^:]+: 04f0c300 incd z0.d, #24
-+[^:]+: 04f0c300 incd z0.d, #24
-+[^:]+: 04f0c320 incd z0.d, #25
-+[^:]+: 04f0c320 incd z0.d, #25
-+[^:]+: 04f0c320 incd z0.d, #25
-+[^:]+: 04f0c340 incd z0.d, #26
-+[^:]+: 04f0c340 incd z0.d, #26
-+[^:]+: 04f0c340 incd z0.d, #26
-+[^:]+: 04f0c360 incd z0.d, #27
-+[^:]+: 04f0c360 incd z0.d, #27
-+[^:]+: 04f0c360 incd z0.d, #27
-+[^:]+: 04f0c380 incd z0.d, #28
-+[^:]+: 04f0c380 incd z0.d, #28
-+[^:]+: 04f0c380 incd z0.d, #28
-+[^:]+: 04f0c3a0 incd z0.d, mul4
-+[^:]+: 04f0c3a0 incd z0.d, mul4
-+[^:]+: 04f0c3a0 incd z0.d, mul4
-+[^:]+: 04f0c3c0 incd z0.d, mul3
-+[^:]+: 04f0c3c0 incd z0.d, mul3
-+[^:]+: 04f0c3c0 incd z0.d, mul3
-+[^:]+: 04f0c3e0 incd z0.d
-+[^:]+: 04f0c3e0 incd z0.d
-+[^:]+: 04f0c3e0 incd z0.d
-+[^:]+: 04f0c3e0 incd z0.d
-+[^:]+: 04f7c000 incd z0.d, pow2, mul #8
-+[^:]+: 04f7c000 incd z0.d, pow2, mul #8
-+[^:]+: 04f8c000 incd z0.d, pow2, mul #9
-+[^:]+: 04f8c000 incd z0.d, pow2, mul #9
-+[^:]+: 04f9c000 incd z0.d, pow2, mul #10
-+[^:]+: 04f9c000 incd z0.d, pow2, mul #10
-+[^:]+: 04ffc000 incd z0.d, pow2, mul #16
-+[^:]+: 04ffc000 incd z0.d, pow2, mul #16
-+[^:]+: 04f0e000 incd x0, pow2
-+[^:]+: 04f0e000 incd x0, pow2
-+[^:]+: 04f0e000 incd x0, pow2
-+[^:]+: 04f0e001 incd x1, pow2
-+[^:]+: 04f0e001 incd x1, pow2
-+[^:]+: 04f0e001 incd x1, pow2
-+[^:]+: 04f0e01f incd xzr, pow2
-+[^:]+: 04f0e01f incd xzr, pow2
-+[^:]+: 04f0e01f incd xzr, pow2
-+[^:]+: 04f0e020 incd x0, vl1
-+[^:]+: 04f0e020 incd x0, vl1
-+[^:]+: 04f0e020 incd x0, vl1
-+[^:]+: 04f0e040 incd x0, vl2
-+[^:]+: 04f0e040 incd x0, vl2
-+[^:]+: 04f0e040 incd x0, vl2
-+[^:]+: 04f0e060 incd x0, vl3
-+[^:]+: 04f0e060 incd x0, vl3
-+[^:]+: 04f0e060 incd x0, vl3
-+[^:]+: 04f0e080 incd x0, vl4
-+[^:]+: 04f0e080 incd x0, vl4
-+[^:]+: 04f0e080 incd x0, vl4
-+[^:]+: 04f0e0a0 incd x0, vl5
-+[^:]+: 04f0e0a0 incd x0, vl5
-+[^:]+: 04f0e0a0 incd x0, vl5
-+[^:]+: 04f0e0c0 incd x0, vl6
-+[^:]+: 04f0e0c0 incd x0, vl6
-+[^:]+: 04f0e0c0 incd x0, vl6
-+[^:]+: 04f0e0e0 incd x0, vl7
-+[^:]+: 04f0e0e0 incd x0, vl7
-+[^:]+: 04f0e0e0 incd x0, vl7
-+[^:]+: 04f0e100 incd x0, vl8
-+[^:]+: 04f0e100 incd x0, vl8
-+[^:]+: 04f0e100 incd x0, vl8
-+[^:]+: 04f0e120 incd x0, vl16
-+[^:]+: 04f0e120 incd x0, vl16
-+[^:]+: 04f0e120 incd x0, vl16
-+[^:]+: 04f0e140 incd x0, vl32
-+[^:]+: 04f0e140 incd x0, vl32
-+[^:]+: 04f0e140 incd x0, vl32
-+[^:]+: 04f0e160 incd x0, vl64
-+[^:]+: 04f0e160 incd x0, vl64
-+[^:]+: 04f0e160 incd x0, vl64
-+[^:]+: 04f0e180 incd x0, vl128
-+[^:]+: 04f0e180 incd x0, vl128
-+[^:]+: 04f0e180 incd x0, vl128
-+[^:]+: 04f0e1a0 incd x0, vl256
-+[^:]+: 04f0e1a0 incd x0, vl256
-+[^:]+: 04f0e1a0 incd x0, vl256
-+[^:]+: 04f0e1c0 incd x0, #14
-+[^:]+: 04f0e1c0 incd x0, #14
-+[^:]+: 04f0e1c0 incd x0, #14
-+[^:]+: 04f0e1e0 incd x0, #15
-+[^:]+: 04f0e1e0 incd x0, #15
-+[^:]+: 04f0e1e0 incd x0, #15
-+[^:]+: 04f0e200 incd x0, #16
-+[^:]+: 04f0e200 incd x0, #16
-+[^:]+: 04f0e200 incd x0, #16
-+[^:]+: 04f0e220 incd x0, #17
-+[^:]+: 04f0e220 incd x0, #17
-+[^:]+: 04f0e220 incd x0, #17
-+[^:]+: 04f0e240 incd x0, #18
-+[^:]+: 04f0e240 incd x0, #18
-+[^:]+: 04f0e240 incd x0, #18
-+[^:]+: 04f0e260 incd x0, #19
-+[^:]+: 04f0e260 incd x0, #19
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-+[^:]+: 0523801f lastb b31, p0, z0.b
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-+[^:]+: 0563801f lastb h31, p0, z0.h
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-+[^:]+: 05638800 lastb h0, p2, z0.h
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-+[^:]+: 05638060 lastb h0, p0, z3.h
-+[^:]+: 05638060 lastb h0, p0, z3.h
-+[^:]+: 056383e0 lastb h0, p0, z31.h
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-+[^:]+: 05a3801f lastb s31, p0, z0.s
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-+[^:]+: 05a38060 lastb s0, p0, z3.s
-+[^:]+: 05a383e0 lastb s0, p0, z31.s
-+[^:]+: 05a383e0 lastb s0, p0, z31.s
-+[^:]+: 05e38000 lastb d0, p0, z0.d
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-+[^:]+: 05e3801f lastb d31, p0, z0.d
-+[^:]+: 05e3801f lastb d31, p0, z0.d
-+[^:]+: 05e38800 lastb d0, p2, z0.d
-+[^:]+: 05e38800 lastb d0, p2, z0.d
-+[^:]+: 05e39c00 lastb d0, p7, z0.d
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-+[^:]+: 05e38060 lastb d0, p0, z3.d
-+[^:]+: 05e38060 lastb d0, p0, z3.d
-+[^:]+: 05e383e0 lastb d0, p0, z31.d
-+[^:]+: 05e383e0 lastb d0, p0, z31.d
-+[^:]+: 84004000 ld1b {z0.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84004000 ld1b {z0.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84004000 ld1b {z0.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84004000 ld1b {z0.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84004001 ld1b {z1.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84004001 ld1b {z1.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84004001 ld1b {z1.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84004001 ld1b {z1.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 8400401f ld1b {z31.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 8400401f ld1b {z31.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 8400401f ld1b {z31.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 8400401f ld1b {z31.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84004800 ld1b {z0.s}, p2/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84004800 ld1b {z0.s}, p2/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84004800 ld1b {z0.s}, p2/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84005c00 ld1b {z0.s}, p7/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84005c00 ld1b {z0.s}, p7/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84005c00 ld1b {z0.s}, p7/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84004060 ld1b {z0.s}, p0/z, \[x3, z0.s, uxtw\]
-+[^:]+: 84004060 ld1b {z0.s}, p0/z, \[x3, z0.s, uxtw\]
-+[^:]+: 84004060 ld1b {z0.s}, p0/z, \[x3, z0.s, uxtw\]
-+[^:]+: 840043e0 ld1b {z0.s}, p0/z, \[sp, z0.s, uxtw\]
-+[^:]+: 840043e0 ld1b {z0.s}, p0/z, \[sp, z0.s, uxtw\]
-+[^:]+: 840043e0 ld1b {z0.s}, p0/z, \[sp, z0.s, uxtw\]
-+[^:]+: 84044000 ld1b {z0.s}, p0/z, \[x0, z4.s, uxtw\]
-+[^:]+: 84044000 ld1b {z0.s}, p0/z, \[x0, z4.s, uxtw\]
-+[^:]+: 84044000 ld1b {z0.s}, p0/z, \[x0, z4.s, uxtw\]
-+[^:]+: 841f4000 ld1b {z0.s}, p0/z, \[x0, z31.s, uxtw\]
-+[^:]+: 841f4000 ld1b {z0.s}, p0/z, \[x0, z31.s, uxtw\]
-+[^:]+: 841f4000 ld1b {z0.s}, p0/z, \[x0, z31.s, uxtw\]
-+[^:]+: 84404000 ld1b {z0.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84404000 ld1b {z0.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84404000 ld1b {z0.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84404000 ld1b {z0.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84404001 ld1b {z1.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84404001 ld1b {z1.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84404001 ld1b {z1.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84404001 ld1b {z1.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 8440401f ld1b {z31.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 8440401f ld1b {z31.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 8440401f ld1b {z31.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 8440401f ld1b {z31.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84404800 ld1b {z0.s}, p2/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84404800 ld1b {z0.s}, p2/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84404800 ld1b {z0.s}, p2/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84405c00 ld1b {z0.s}, p7/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84405c00 ld1b {z0.s}, p7/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84405c00 ld1b {z0.s}, p7/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84404060 ld1b {z0.s}, p0/z, \[x3, z0.s, sxtw\]
-+[^:]+: 84404060 ld1b {z0.s}, p0/z, \[x3, z0.s, sxtw\]
-+[^:]+: 84404060 ld1b {z0.s}, p0/z, \[x3, z0.s, sxtw\]
-+[^:]+: 844043e0 ld1b {z0.s}, p0/z, \[sp, z0.s, sxtw\]
-+[^:]+: 844043e0 ld1b {z0.s}, p0/z, \[sp, z0.s, sxtw\]
-+[^:]+: 844043e0 ld1b {z0.s}, p0/z, \[sp, z0.s, sxtw\]
-+[^:]+: 84444000 ld1b {z0.s}, p0/z, \[x0, z4.s, sxtw\]
-+[^:]+: 84444000 ld1b {z0.s}, p0/z, \[x0, z4.s, sxtw\]
-+[^:]+: 84444000 ld1b {z0.s}, p0/z, \[x0, z4.s, sxtw\]
-+[^:]+: 845f4000 ld1b {z0.s}, p0/z, \[x0, z31.s, sxtw\]
-+[^:]+: 845f4000 ld1b {z0.s}, p0/z, \[x0, z31.s, sxtw\]
-+[^:]+: 845f4000 ld1b {z0.s}, p0/z, \[x0, z31.s, sxtw\]
-+[^:]+: a4004000 ld1b {z0.b}, p0/z, \[x0, x0\]
-+[^:]+: a4004000 ld1b {z0.b}, p0/z, \[x0, x0\]
-+[^:]+: a4004000 ld1b {z0.b}, p0/z, \[x0, x0\]
-+[^:]+: a4004000 ld1b {z0.b}, p0/z, \[x0, x0\]
-+[^:]+: a4004001 ld1b {z1.b}, p0/z, \[x0, x0\]
-+[^:]+: a4004001 ld1b {z1.b}, p0/z, \[x0, x0\]
-+[^:]+: a4004001 ld1b {z1.b}, p0/z, \[x0, x0\]
-+[^:]+: a4004001 ld1b {z1.b}, p0/z, \[x0, x0\]
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-+[^:]+: a400401f ld1b {z31.b}, p0/z, \[x0, x0\]
-+[^:]+: a400401f ld1b {z31.b}, p0/z, \[x0, x0\]
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-+[^:]+: a4004800 ld1b {z0.b}, p2/z, \[x0, x0\]
-+[^:]+: a4004800 ld1b {z0.b}, p2/z, \[x0, x0\]
-+[^:]+: a4005c00 ld1b {z0.b}, p7/z, \[x0, x0\]
-+[^:]+: a4005c00 ld1b {z0.b}, p7/z, \[x0, x0\]
-+[^:]+: a4005c00 ld1b {z0.b}, p7/z, \[x0, x0\]
-+[^:]+: a4004060 ld1b {z0.b}, p0/z, \[x3, x0\]
-+[^:]+: a4004060 ld1b {z0.b}, p0/z, \[x3, x0\]
-+[^:]+: a4004060 ld1b {z0.b}, p0/z, \[x3, x0\]
-+[^:]+: a40043e0 ld1b {z0.b}, p0/z, \[sp, x0\]
-+[^:]+: a40043e0 ld1b {z0.b}, p0/z, \[sp, x0\]
-+[^:]+: a40043e0 ld1b {z0.b}, p0/z, \[sp, x0\]
-+[^:]+: a4044000 ld1b {z0.b}, p0/z, \[x0, x4\]
-+[^:]+: a4044000 ld1b {z0.b}, p0/z, \[x0, x4\]
-+[^:]+: a4044000 ld1b {z0.b}, p0/z, \[x0, x4\]
-+[^:]+: a41e4000 ld1b {z0.b}, p0/z, \[x0, x30\]
-+[^:]+: a41e4000 ld1b {z0.b}, p0/z, \[x0, x30\]
-+[^:]+: a41e4000 ld1b {z0.b}, p0/z, \[x0, x30\]
-+[^:]+: a4204000 ld1b {z0.h}, p0/z, \[x0, x0\]
-+[^:]+: a4204000 ld1b {z0.h}, p0/z, \[x0, x0\]
-+[^:]+: a4204000 ld1b {z0.h}, p0/z, \[x0, x0\]
-+[^:]+: a4204000 ld1b {z0.h}, p0/z, \[x0, x0\]
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-+[^:]+: a4204001 ld1b {z1.h}, p0/z, \[x0, x0\]
-+[^:]+: a4204001 ld1b {z1.h}, p0/z, \[x0, x0\]
-+[^:]+: a4204001 ld1b {z1.h}, p0/z, \[x0, x0\]
-+[^:]+: a420401f ld1b {z31.h}, p0/z, \[x0, x0\]
-+[^:]+: a420401f ld1b {z31.h}, p0/z, \[x0, x0\]
-+[^:]+: a420401f ld1b {z31.h}, p0/z, \[x0, x0\]
-+[^:]+: a420401f ld1b {z31.h}, p0/z, \[x0, x0\]
-+[^:]+: a4204800 ld1b {z0.h}, p2/z, \[x0, x0\]
-+[^:]+: a4204800 ld1b {z0.h}, p2/z, \[x0, x0\]
-+[^:]+: a4204800 ld1b {z0.h}, p2/z, \[x0, x0\]
-+[^:]+: a4205c00 ld1b {z0.h}, p7/z, \[x0, x0\]
-+[^:]+: a4205c00 ld1b {z0.h}, p7/z, \[x0, x0\]
-+[^:]+: a4205c00 ld1b {z0.h}, p7/z, \[x0, x0\]
-+[^:]+: a4204060 ld1b {z0.h}, p0/z, \[x3, x0\]
-+[^:]+: a4204060 ld1b {z0.h}, p0/z, \[x3, x0\]
-+[^:]+: a4204060 ld1b {z0.h}, p0/z, \[x3, x0\]
-+[^:]+: a42043e0 ld1b {z0.h}, p0/z, \[sp, x0\]
-+[^:]+: a42043e0 ld1b {z0.h}, p0/z, \[sp, x0\]
-+[^:]+: a42043e0 ld1b {z0.h}, p0/z, \[sp, x0\]
-+[^:]+: a4244000 ld1b {z0.h}, p0/z, \[x0, x4\]
-+[^:]+: a4244000 ld1b {z0.h}, p0/z, \[x0, x4\]
-+[^:]+: a4244000 ld1b {z0.h}, p0/z, \[x0, x4\]
-+[^:]+: a43e4000 ld1b {z0.h}, p0/z, \[x0, x30\]
-+[^:]+: a43e4000 ld1b {z0.h}, p0/z, \[x0, x30\]
-+[^:]+: a43e4000 ld1b {z0.h}, p0/z, \[x0, x30\]
-+[^:]+: a4404000 ld1b {z0.s}, p0/z, \[x0, x0\]
-+[^:]+: a4404000 ld1b {z0.s}, p0/z, \[x0, x0\]
-+[^:]+: a4404000 ld1b {z0.s}, p0/z, \[x0, x0\]
-+[^:]+: a4404000 ld1b {z0.s}, p0/z, \[x0, x0\]
-+[^:]+: a4404001 ld1b {z1.s}, p0/z, \[x0, x0\]
-+[^:]+: a4404001 ld1b {z1.s}, p0/z, \[x0, x0\]
-+[^:]+: a4404001 ld1b {z1.s}, p0/z, \[x0, x0\]
-+[^:]+: a4404001 ld1b {z1.s}, p0/z, \[x0, x0\]
-+[^:]+: a440401f ld1b {z31.s}, p0/z, \[x0, x0\]
-+[^:]+: a440401f ld1b {z31.s}, p0/z, \[x0, x0\]
-+[^:]+: a440401f ld1b {z31.s}, p0/z, \[x0, x0\]
-+[^:]+: a440401f ld1b {z31.s}, p0/z, \[x0, x0\]
-+[^:]+: a4404800 ld1b {z0.s}, p2/z, \[x0, x0\]
-+[^:]+: a4404800 ld1b {z0.s}, p2/z, \[x0, x0\]
-+[^:]+: a4404800 ld1b {z0.s}, p2/z, \[x0, x0\]
-+[^:]+: a4405c00 ld1b {z0.s}, p7/z, \[x0, x0\]
-+[^:]+: a4405c00 ld1b {z0.s}, p7/z, \[x0, x0\]
-+[^:]+: a4405c00 ld1b {z0.s}, p7/z, \[x0, x0\]
-+[^:]+: a4404060 ld1b {z0.s}, p0/z, \[x3, x0\]
-+[^:]+: a4404060 ld1b {z0.s}, p0/z, \[x3, x0\]
-+[^:]+: a4404060 ld1b {z0.s}, p0/z, \[x3, x0\]
-+[^:]+: a44043e0 ld1b {z0.s}, p0/z, \[sp, x0\]
-+[^:]+: a44043e0 ld1b {z0.s}, p0/z, \[sp, x0\]
-+[^:]+: a44043e0 ld1b {z0.s}, p0/z, \[sp, x0\]
-+[^:]+: a4444000 ld1b {z0.s}, p0/z, \[x0, x4\]
-+[^:]+: a4444000 ld1b {z0.s}, p0/z, \[x0, x4\]
-+[^:]+: a4444000 ld1b {z0.s}, p0/z, \[x0, x4\]
-+[^:]+: a45e4000 ld1b {z0.s}, p0/z, \[x0, x30\]
-+[^:]+: a45e4000 ld1b {z0.s}, p0/z, \[x0, x30\]
-+[^:]+: a45e4000 ld1b {z0.s}, p0/z, \[x0, x30\]
-+[^:]+: a4604000 ld1b {z0.d}, p0/z, \[x0, x0\]
-+[^:]+: a4604000 ld1b {z0.d}, p0/z, \[x0, x0\]
-+[^:]+: a4604000 ld1b {z0.d}, p0/z, \[x0, x0\]
-+[^:]+: a4604000 ld1b {z0.d}, p0/z, \[x0, x0\]
-+[^:]+: a4604001 ld1b {z1.d}, p0/z, \[x0, x0\]
-+[^:]+: a4604001 ld1b {z1.d}, p0/z, \[x0, x0\]
-+[^:]+: a4604001 ld1b {z1.d}, p0/z, \[x0, x0\]
-+[^:]+: a4604001 ld1b {z1.d}, p0/z, \[x0, x0\]
-+[^:]+: a460401f ld1b {z31.d}, p0/z, \[x0, x0\]
-+[^:]+: a460401f ld1b {z31.d}, p0/z, \[x0, x0\]
-+[^:]+: a460401f ld1b {z31.d}, p0/z, \[x0, x0\]
-+[^:]+: a460401f ld1b {z31.d}, p0/z, \[x0, x0\]
-+[^:]+: a4604800 ld1b {z0.d}, p2/z, \[x0, x0\]
-+[^:]+: a4604800 ld1b {z0.d}, p2/z, \[x0, x0\]
-+[^:]+: a4604800 ld1b {z0.d}, p2/z, \[x0, x0\]
-+[^:]+: a4605c00 ld1b {z0.d}, p7/z, \[x0, x0\]
-+[^:]+: a4605c00 ld1b {z0.d}, p7/z, \[x0, x0\]
-+[^:]+: a4605c00 ld1b {z0.d}, p7/z, \[x0, x0\]
-+[^:]+: a4604060 ld1b {z0.d}, p0/z, \[x3, x0\]
-+[^:]+: a4604060 ld1b {z0.d}, p0/z, \[x3, x0\]
-+[^:]+: a4604060 ld1b {z0.d}, p0/z, \[x3, x0\]
-+[^:]+: a46043e0 ld1b {z0.d}, p0/z, \[sp, x0\]
-+[^:]+: a46043e0 ld1b {z0.d}, p0/z, \[sp, x0\]
-+[^:]+: a46043e0 ld1b {z0.d}, p0/z, \[sp, x0\]
-+[^:]+: a4644000 ld1b {z0.d}, p0/z, \[x0, x4\]
-+[^:]+: a4644000 ld1b {z0.d}, p0/z, \[x0, x4\]
-+[^:]+: a4644000 ld1b {z0.d}, p0/z, \[x0, x4\]
-+[^:]+: a47e4000 ld1b {z0.d}, p0/z, \[x0, x30\]
-+[^:]+: a47e4000 ld1b {z0.d}, p0/z, \[x0, x30\]
-+[^:]+: a47e4000 ld1b {z0.d}, p0/z, \[x0, x30\]
-+[^:]+: c4004000 ld1b {z0.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4004000 ld1b {z0.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4004000 ld1b {z0.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4004000 ld1b {z0.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4004001 ld1b {z1.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4004001 ld1b {z1.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4004001 ld1b {z1.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4004001 ld1b {z1.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c400401f ld1b {z31.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c400401f ld1b {z31.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c400401f ld1b {z31.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c400401f ld1b {z31.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4004800 ld1b {z0.d}, p2/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4004800 ld1b {z0.d}, p2/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4004800 ld1b {z0.d}, p2/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4005c00 ld1b {z0.d}, p7/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4005c00 ld1b {z0.d}, p7/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4005c00 ld1b {z0.d}, p7/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4004060 ld1b {z0.d}, p0/z, \[x3, z0.d, uxtw\]
-+[^:]+: c4004060 ld1b {z0.d}, p0/z, \[x3, z0.d, uxtw\]
-+[^:]+: c4004060 ld1b {z0.d}, p0/z, \[x3, z0.d, uxtw\]
-+[^:]+: c40043e0 ld1b {z0.d}, p0/z, \[sp, z0.d, uxtw\]
-+[^:]+: c40043e0 ld1b {z0.d}, p0/z, \[sp, z0.d, uxtw\]
-+[^:]+: c40043e0 ld1b {z0.d}, p0/z, \[sp, z0.d, uxtw\]
-+[^:]+: c4044000 ld1b {z0.d}, p0/z, \[x0, z4.d, uxtw\]
-+[^:]+: c4044000 ld1b {z0.d}, p0/z, \[x0, z4.d, uxtw\]
-+[^:]+: c4044000 ld1b {z0.d}, p0/z, \[x0, z4.d, uxtw\]
-+[^:]+: c41f4000 ld1b {z0.d}, p0/z, \[x0, z31.d, uxtw\]
-+[^:]+: c41f4000 ld1b {z0.d}, p0/z, \[x0, z31.d, uxtw\]
-+[^:]+: c41f4000 ld1b {z0.d}, p0/z, \[x0, z31.d, uxtw\]
-+[^:]+: c4404000 ld1b {z0.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4404000 ld1b {z0.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4404000 ld1b {z0.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4404000 ld1b {z0.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4404001 ld1b {z1.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4404001 ld1b {z1.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4404001 ld1b {z1.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4404001 ld1b {z1.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c440401f ld1b {z31.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c440401f ld1b {z31.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c440401f ld1b {z31.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c440401f ld1b {z31.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4404800 ld1b {z0.d}, p2/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4404800 ld1b {z0.d}, p2/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4404800 ld1b {z0.d}, p2/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4405c00 ld1b {z0.d}, p7/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4405c00 ld1b {z0.d}, p7/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4405c00 ld1b {z0.d}, p7/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4404060 ld1b {z0.d}, p0/z, \[x3, z0.d, sxtw\]
-+[^:]+: c4404060 ld1b {z0.d}, p0/z, \[x3, z0.d, sxtw\]
-+[^:]+: c4404060 ld1b {z0.d}, p0/z, \[x3, z0.d, sxtw\]
-+[^:]+: c44043e0 ld1b {z0.d}, p0/z, \[sp, z0.d, sxtw\]
-+[^:]+: c44043e0 ld1b {z0.d}, p0/z, \[sp, z0.d, sxtw\]
-+[^:]+: c44043e0 ld1b {z0.d}, p0/z, \[sp, z0.d, sxtw\]
-+[^:]+: c4444000 ld1b {z0.d}, p0/z, \[x0, z4.d, sxtw\]
-+[^:]+: c4444000 ld1b {z0.d}, p0/z, \[x0, z4.d, sxtw\]
-+[^:]+: c4444000 ld1b {z0.d}, p0/z, \[x0, z4.d, sxtw\]
-+[^:]+: c45f4000 ld1b {z0.d}, p0/z, \[x0, z31.d, sxtw\]
-+[^:]+: c45f4000 ld1b {z0.d}, p0/z, \[x0, z31.d, sxtw\]
-+[^:]+: c45f4000 ld1b {z0.d}, p0/z, \[x0, z31.d, sxtw\]
-+[^:]+: c440c000 ld1b {z0.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c440c000 ld1b {z0.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c440c000 ld1b {z0.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c440c000 ld1b {z0.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c440c001 ld1b {z1.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c440c001 ld1b {z1.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c440c001 ld1b {z1.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c440c001 ld1b {z1.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c440c01f ld1b {z31.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c440c01f ld1b {z31.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c440c01f ld1b {z31.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c440c01f ld1b {z31.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c440c800 ld1b {z0.d}, p2/z, \[x0, z0.d\]
-+[^:]+: c440c800 ld1b {z0.d}, p2/z, \[x0, z0.d\]
-+[^:]+: c440c800 ld1b {z0.d}, p2/z, \[x0, z0.d\]
-+[^:]+: c440dc00 ld1b {z0.d}, p7/z, \[x0, z0.d\]
-+[^:]+: c440dc00 ld1b {z0.d}, p7/z, \[x0, z0.d\]
-+[^:]+: c440dc00 ld1b {z0.d}, p7/z, \[x0, z0.d\]
-+[^:]+: c440c060 ld1b {z0.d}, p0/z, \[x3, z0.d\]
-+[^:]+: c440c060 ld1b {z0.d}, p0/z, \[x3, z0.d\]
-+[^:]+: c440c060 ld1b {z0.d}, p0/z, \[x3, z0.d\]
-+[^:]+: c440c3e0 ld1b {z0.d}, p0/z, \[sp, z0.d\]
-+[^:]+: c440c3e0 ld1b {z0.d}, p0/z, \[sp, z0.d\]
-+[^:]+: c440c3e0 ld1b {z0.d}, p0/z, \[sp, z0.d\]
-+[^:]+: c444c000 ld1b {z0.d}, p0/z, \[x0, z4.d\]
-+[^:]+: c444c000 ld1b {z0.d}, p0/z, \[x0, z4.d\]
-+[^:]+: c444c000 ld1b {z0.d}, p0/z, \[x0, z4.d\]
-+[^:]+: c45fc000 ld1b {z0.d}, p0/z, \[x0, z31.d\]
-+[^:]+: c45fc000 ld1b {z0.d}, p0/z, \[x0, z31.d\]
-+[^:]+: c45fc000 ld1b {z0.d}, p0/z, \[x0, z31.d\]
-+[^:]+: 8420c000 ld1b {z0.s}, p0/z, \[z0.s\]
-+[^:]+: 8420c000 ld1b {z0.s}, p0/z, \[z0.s\]
-+[^:]+: 8420c000 ld1b {z0.s}, p0/z, \[z0.s\]
-+[^:]+: 8420c000 ld1b {z0.s}, p0/z, \[z0.s\]
-+[^:]+: 8420c001 ld1b {z1.s}, p0/z, \[z0.s\]
-+[^:]+: 8420c001 ld1b {z1.s}, p0/z, \[z0.s\]
-+[^:]+: 8420c001 ld1b {z1.s}, p0/z, \[z0.s\]
-+[^:]+: 8420c001 ld1b {z1.s}, p0/z, \[z0.s\]
-+[^:]+: 8420c01f ld1b {z31.s}, p0/z, \[z0.s\]
-+[^:]+: 8420c01f ld1b {z31.s}, p0/z, \[z0.s\]
-+[^:]+: 8420c01f ld1b {z31.s}, p0/z, \[z0.s\]
-+[^:]+: 8420c01f ld1b {z31.s}, p0/z, \[z0.s\]
-+[^:]+: 8420c800 ld1b {z0.s}, p2/z, \[z0.s\]
-+[^:]+: 8420c800 ld1b {z0.s}, p2/z, \[z0.s\]
-+[^:]+: 8420c800 ld1b {z0.s}, p2/z, \[z0.s\]
-+[^:]+: 8420dc00 ld1b {z0.s}, p7/z, \[z0.s\]
-+[^:]+: 8420dc00 ld1b {z0.s}, p7/z, \[z0.s\]
-+[^:]+: 8420dc00 ld1b {z0.s}, p7/z, \[z0.s\]
-+[^:]+: 8420c060 ld1b {z0.s}, p0/z, \[z3.s\]
-+[^:]+: 8420c060 ld1b {z0.s}, p0/z, \[z3.s\]
-+[^:]+: 8420c060 ld1b {z0.s}, p0/z, \[z3.s\]
-+[^:]+: 8420c3e0 ld1b {z0.s}, p0/z, \[z31.s\]
-+[^:]+: 8420c3e0 ld1b {z0.s}, p0/z, \[z31.s\]
-+[^:]+: 8420c3e0 ld1b {z0.s}, p0/z, \[z31.s\]
-+[^:]+: 842fc000 ld1b {z0.s}, p0/z, \[z0.s, #15\]
-+[^:]+: 842fc000 ld1b {z0.s}, p0/z, \[z0.s, #15\]
-+[^:]+: 8430c000 ld1b {z0.s}, p0/z, \[z0.s, #16\]
-+[^:]+: 8430c000 ld1b {z0.s}, p0/z, \[z0.s, #16\]
-+[^:]+: 8431c000 ld1b {z0.s}, p0/z, \[z0.s, #17\]
-+[^:]+: 8431c000 ld1b {z0.s}, p0/z, \[z0.s, #17\]
-+[^:]+: 843fc000 ld1b {z0.s}, p0/z, \[z0.s, #31\]
-+[^:]+: 843fc000 ld1b {z0.s}, p0/z, \[z0.s, #31\]
-+[^:]+: a400a000 ld1b {z0.b}, p0/z, \[x0\]
-+[^:]+: a400a000 ld1b {z0.b}, p0/z, \[x0\]
-+[^:]+: a400a000 ld1b {z0.b}, p0/z, \[x0\]
-+[^:]+: a400a000 ld1b {z0.b}, p0/z, \[x0\]
-+[^:]+: a400a000 ld1b {z0.b}, p0/z, \[x0\]
-+[^:]+: a400a001 ld1b {z1.b}, p0/z, \[x0\]
-+[^:]+: a400a001 ld1b {z1.b}, p0/z, \[x0\]
-+[^:]+: a400a001 ld1b {z1.b}, p0/z, \[x0\]
-+[^:]+: a400a001 ld1b {z1.b}, p0/z, \[x0\]
-+[^:]+: a400a001 ld1b {z1.b}, p0/z, \[x0\]
-+[^:]+: a400a01f ld1b {z31.b}, p0/z, \[x0\]
-+[^:]+: a400a01f ld1b {z31.b}, p0/z, \[x0\]
-+[^:]+: a400a01f ld1b {z31.b}, p0/z, \[x0\]
-+[^:]+: a400a01f ld1b {z31.b}, p0/z, \[x0\]
-+[^:]+: a400a01f ld1b {z31.b}, p0/z, \[x0\]
-+[^:]+: a400a800 ld1b {z0.b}, p2/z, \[x0\]
-+[^:]+: a400a800 ld1b {z0.b}, p2/z, \[x0\]
-+[^:]+: a400a800 ld1b {z0.b}, p2/z, \[x0\]
-+[^:]+: a400a800 ld1b {z0.b}, p2/z, \[x0\]
-+[^:]+: a400bc00 ld1b {z0.b}, p7/z, \[x0\]
-+[^:]+: a400bc00 ld1b {z0.b}, p7/z, \[x0\]
-+[^:]+: a400bc00 ld1b {z0.b}, p7/z, \[x0\]
-+[^:]+: a400bc00 ld1b {z0.b}, p7/z, \[x0\]
-+[^:]+: a400a060 ld1b {z0.b}, p0/z, \[x3\]
-+[^:]+: a400a060 ld1b {z0.b}, p0/z, \[x3\]
-+[^:]+: a400a060 ld1b {z0.b}, p0/z, \[x3\]
-+[^:]+: a400a060 ld1b {z0.b}, p0/z, \[x3\]
-+[^:]+: a400a3e0 ld1b {z0.b}, p0/z, \[sp\]
-+[^:]+: a400a3e0 ld1b {z0.b}, p0/z, \[sp\]
-+[^:]+: a400a3e0 ld1b {z0.b}, p0/z, \[sp\]
-+[^:]+: a400a3e0 ld1b {z0.b}, p0/z, \[sp\]
-+[^:]+: a407a000 ld1b {z0.b}, p0/z, \[x0, #7, mul vl\]
-+[^:]+: a407a000 ld1b {z0.b}, p0/z, \[x0, #7, mul vl\]
-+[^:]+: a408a000 ld1b {z0.b}, p0/z, \[x0, #-8, mul vl\]
-+[^:]+: a408a000 ld1b {z0.b}, p0/z, \[x0, #-8, mul vl\]
-+[^:]+: a409a000 ld1b {z0.b}, p0/z, \[x0, #-7, mul vl\]
-+[^:]+: a409a000 ld1b {z0.b}, p0/z, \[x0, #-7, mul vl\]
-+[^:]+: a40fa000 ld1b {z0.b}, p0/z, \[x0, #-1, mul vl\]
-+[^:]+: a40fa000 ld1b {z0.b}, p0/z, \[x0, #-1, mul vl\]
-+[^:]+: a420a000 ld1b {z0.h}, p0/z, \[x0\]
-+[^:]+: a420a000 ld1b {z0.h}, p0/z, \[x0\]
-+[^:]+: a420a000 ld1b {z0.h}, p0/z, \[x0\]
-+[^:]+: a420a000 ld1b {z0.h}, p0/z, \[x0\]
-+[^:]+: a420a000 ld1b {z0.h}, p0/z, \[x0\]
-+[^:]+: a420a001 ld1b {z1.h}, p0/z, \[x0\]
-+[^:]+: a420a001 ld1b {z1.h}, p0/z, \[x0\]
-+[^:]+: a420a001 ld1b {z1.h}, p0/z, \[x0\]
-+[^:]+: a420a001 ld1b {z1.h}, p0/z, \[x0\]
-+[^:]+: a420a001 ld1b {z1.h}, p0/z, \[x0\]
-+[^:]+: a420a01f ld1b {z31.h}, p0/z, \[x0\]
-+[^:]+: a420a01f ld1b {z31.h}, p0/z, \[x0\]
-+[^:]+: a420a01f ld1b {z31.h}, p0/z, \[x0\]
-+[^:]+: a420a01f ld1b {z31.h}, p0/z, \[x0\]
-+[^:]+: a420a01f ld1b {z31.h}, p0/z, \[x0\]
-+[^:]+: a420a800 ld1b {z0.h}, p2/z, \[x0\]
-+[^:]+: a420a800 ld1b {z0.h}, p2/z, \[x0\]
-+[^:]+: a420a800 ld1b {z0.h}, p2/z, \[x0\]
-+[^:]+: a420a800 ld1b {z0.h}, p2/z, \[x0\]
-+[^:]+: a420bc00 ld1b {z0.h}, p7/z, \[x0\]
-+[^:]+: a420bc00 ld1b {z0.h}, p7/z, \[x0\]
-+[^:]+: a420bc00 ld1b {z0.h}, p7/z, \[x0\]
-+[^:]+: a420bc00 ld1b {z0.h}, p7/z, \[x0\]
-+[^:]+: a420a060 ld1b {z0.h}, p0/z, \[x3\]
-+[^:]+: a420a060 ld1b {z0.h}, p0/z, \[x3\]
-+[^:]+: a420a060 ld1b {z0.h}, p0/z, \[x3\]
-+[^:]+: a420a060 ld1b {z0.h}, p0/z, \[x3\]
-+[^:]+: a420a3e0 ld1b {z0.h}, p0/z, \[sp\]
-+[^:]+: a420a3e0 ld1b {z0.h}, p0/z, \[sp\]
-+[^:]+: a420a3e0 ld1b {z0.h}, p0/z, \[sp\]
-+[^:]+: a420a3e0 ld1b {z0.h}, p0/z, \[sp\]
-+[^:]+: a427a000 ld1b {z0.h}, p0/z, \[x0, #7, mul vl\]
-+[^:]+: a427a000 ld1b {z0.h}, p0/z, \[x0, #7, mul vl\]
-+[^:]+: a428a000 ld1b {z0.h}, p0/z, \[x0, #-8, mul vl\]
-+[^:]+: a428a000 ld1b {z0.h}, p0/z, \[x0, #-8, mul vl\]
-+[^:]+: a429a000 ld1b {z0.h}, p0/z, \[x0, #-7, mul vl\]
-+[^:]+: a429a000 ld1b {z0.h}, p0/z, \[x0, #-7, mul vl\]
-+[^:]+: a42fa000 ld1b {z0.h}, p0/z, \[x0, #-1, mul vl\]
-+[^:]+: a42fa000 ld1b {z0.h}, p0/z, \[x0, #-1, mul vl\]
-+[^:]+: a440a000 ld1b {z0.s}, p0/z, \[x0\]
-+[^:]+: a440a000 ld1b {z0.s}, p0/z, \[x0\]
-+[^:]+: a440a000 ld1b {z0.s}, p0/z, \[x0\]
-+[^:]+: a440a000 ld1b {z0.s}, p0/z, \[x0\]
-+[^:]+: a440a000 ld1b {z0.s}, p0/z, \[x0\]
-+[^:]+: a440a001 ld1b {z1.s}, p0/z, \[x0\]
-+[^:]+: a440a001 ld1b {z1.s}, p0/z, \[x0\]
-+[^:]+: a440a001 ld1b {z1.s}, p0/z, \[x0\]
-+[^:]+: a440a001 ld1b {z1.s}, p0/z, \[x0\]
-+[^:]+: a440a001 ld1b {z1.s}, p0/z, \[x0\]
-+[^:]+: a440a01f ld1b {z31.s}, p0/z, \[x0\]
-+[^:]+: a440a01f ld1b {z31.s}, p0/z, \[x0\]
-+[^:]+: a440a01f ld1b {z31.s}, p0/z, \[x0\]
-+[^:]+: a440a01f ld1b {z31.s}, p0/z, \[x0\]
-+[^:]+: a440a01f ld1b {z31.s}, p0/z, \[x0\]
-+[^:]+: a440a800 ld1b {z0.s}, p2/z, \[x0\]
-+[^:]+: a440a800 ld1b {z0.s}, p2/z, \[x0\]
-+[^:]+: a440a800 ld1b {z0.s}, p2/z, \[x0\]
-+[^:]+: a440a800 ld1b {z0.s}, p2/z, \[x0\]
-+[^:]+: a440bc00 ld1b {z0.s}, p7/z, \[x0\]
-+[^:]+: a440bc00 ld1b {z0.s}, p7/z, \[x0\]
-+[^:]+: a440bc00 ld1b {z0.s}, p7/z, \[x0\]
-+[^:]+: a440bc00 ld1b {z0.s}, p7/z, \[x0\]
-+[^:]+: a440a060 ld1b {z0.s}, p0/z, \[x3\]
-+[^:]+: a440a060 ld1b {z0.s}, p0/z, \[x3\]
-+[^:]+: a440a060 ld1b {z0.s}, p0/z, \[x3\]
-+[^:]+: a440a060 ld1b {z0.s}, p0/z, \[x3\]
-+[^:]+: a440a3e0 ld1b {z0.s}, p0/z, \[sp\]
-+[^:]+: a440a3e0 ld1b {z0.s}, p0/z, \[sp\]
-+[^:]+: a440a3e0 ld1b {z0.s}, p0/z, \[sp\]
-+[^:]+: a440a3e0 ld1b {z0.s}, p0/z, \[sp\]
-+[^:]+: a447a000 ld1b {z0.s}, p0/z, \[x0, #7, mul vl\]
-+[^:]+: a447a000 ld1b {z0.s}, p0/z, \[x0, #7, mul vl\]
-+[^:]+: a448a000 ld1b {z0.s}, p0/z, \[x0, #-8, mul vl\]
-+[^:]+: a448a000 ld1b {z0.s}, p0/z, \[x0, #-8, mul vl\]
-+[^:]+: a449a000 ld1b {z0.s}, p0/z, \[x0, #-7, mul vl\]
-+[^:]+: a449a000 ld1b {z0.s}, p0/z, \[x0, #-7, mul vl\]
-+[^:]+: a44fa000 ld1b {z0.s}, p0/z, \[x0, #-1, mul vl\]
-+[^:]+: a44fa000 ld1b {z0.s}, p0/z, \[x0, #-1, mul vl\]
-+[^:]+: a460a000 ld1b {z0.d}, p0/z, \[x0\]
-+[^:]+: a460a000 ld1b {z0.d}, p0/z, \[x0\]
-+[^:]+: a460a000 ld1b {z0.d}, p0/z, \[x0\]
-+[^:]+: a460a000 ld1b {z0.d}, p0/z, \[x0\]
-+[^:]+: a460a000 ld1b {z0.d}, p0/z, \[x0\]
-+[^:]+: a460a001 ld1b {z1.d}, p0/z, \[x0\]
-+[^:]+: a460a001 ld1b {z1.d}, p0/z, \[x0\]
-+[^:]+: a460a001 ld1b {z1.d}, p0/z, \[x0\]
-+[^:]+: a460a001 ld1b {z1.d}, p0/z, \[x0\]
-+[^:]+: a460a001 ld1b {z1.d}, p0/z, \[x0\]
-+[^:]+: a460a01f ld1b {z31.d}, p0/z, \[x0\]
-+[^:]+: a460a01f ld1b {z31.d}, p0/z, \[x0\]
-+[^:]+: a460a01f ld1b {z31.d}, p0/z, \[x0\]
-+[^:]+: a460a01f ld1b {z31.d}, p0/z, \[x0\]
-+[^:]+: a460a01f ld1b {z31.d}, p0/z, \[x0\]
-+[^:]+: a460a800 ld1b {z0.d}, p2/z, \[x0\]
-+[^:]+: a460a800 ld1b {z0.d}, p2/z, \[x0\]
-+[^:]+: a460a800 ld1b {z0.d}, p2/z, \[x0\]
-+[^:]+: a460a800 ld1b {z0.d}, p2/z, \[x0\]
-+[^:]+: a460bc00 ld1b {z0.d}, p7/z, \[x0\]
-+[^:]+: a460bc00 ld1b {z0.d}, p7/z, \[x0\]
-+[^:]+: a460bc00 ld1b {z0.d}, p7/z, \[x0\]
-+[^:]+: a460bc00 ld1b {z0.d}, p7/z, \[x0\]
-+[^:]+: a460a060 ld1b {z0.d}, p0/z, \[x3\]
-+[^:]+: a460a060 ld1b {z0.d}, p0/z, \[x3\]
-+[^:]+: a460a060 ld1b {z0.d}, p0/z, \[x3\]
-+[^:]+: a460a060 ld1b {z0.d}, p0/z, \[x3\]
-+[^:]+: a460a3e0 ld1b {z0.d}, p0/z, \[sp\]
-+[^:]+: a460a3e0 ld1b {z0.d}, p0/z, \[sp\]
-+[^:]+: a460a3e0 ld1b {z0.d}, p0/z, \[sp\]
-+[^:]+: a460a3e0 ld1b {z0.d}, p0/z, \[sp\]
-+[^:]+: a467a000 ld1b {z0.d}, p0/z, \[x0, #7, mul vl\]
-+[^:]+: a467a000 ld1b {z0.d}, p0/z, \[x0, #7, mul vl\]
-+[^:]+: a468a000 ld1b {z0.d}, p0/z, \[x0, #-8, mul vl\]
-+[^:]+: a468a000 ld1b {z0.d}, p0/z, \[x0, #-8, mul vl\]
-+[^:]+: a469a000 ld1b {z0.d}, p0/z, \[x0, #-7, mul vl\]
-+[^:]+: a469a000 ld1b {z0.d}, p0/z, \[x0, #-7, mul vl\]
-+[^:]+: a46fa000 ld1b {z0.d}, p0/z, \[x0, #-1, mul vl\]
-+[^:]+: a46fa000 ld1b {z0.d}, p0/z, \[x0, #-1, mul vl\]
-+[^:]+: c420c000 ld1b {z0.d}, p0/z, \[z0.d\]
-+[^:]+: c420c000 ld1b {z0.d}, p0/z, \[z0.d\]
-+[^:]+: c420c000 ld1b {z0.d}, p0/z, \[z0.d\]
-+[^:]+: c420c000 ld1b {z0.d}, p0/z, \[z0.d\]
-+[^:]+: c420c001 ld1b {z1.d}, p0/z, \[z0.d\]
-+[^:]+: c420c001 ld1b {z1.d}, p0/z, \[z0.d\]
-+[^:]+: c420c001 ld1b {z1.d}, p0/z, \[z0.d\]
-+[^:]+: c420c001 ld1b {z1.d}, p0/z, \[z0.d\]
-+[^:]+: c420c01f ld1b {z31.d}, p0/z, \[z0.d\]
-+[^:]+: c420c01f ld1b {z31.d}, p0/z, \[z0.d\]
-+[^:]+: c420c01f ld1b {z31.d}, p0/z, \[z0.d\]
-+[^:]+: c420c01f ld1b {z31.d}, p0/z, \[z0.d\]
-+[^:]+: c420c800 ld1b {z0.d}, p2/z, \[z0.d\]
-+[^:]+: c420c800 ld1b {z0.d}, p2/z, \[z0.d\]
-+[^:]+: c420c800 ld1b {z0.d}, p2/z, \[z0.d\]
-+[^:]+: c420dc00 ld1b {z0.d}, p7/z, \[z0.d\]
-+[^:]+: c420dc00 ld1b {z0.d}, p7/z, \[z0.d\]
-+[^:]+: c420dc00 ld1b {z0.d}, p7/z, \[z0.d\]
-+[^:]+: c420c060 ld1b {z0.d}, p0/z, \[z3.d\]
-+[^:]+: c420c060 ld1b {z0.d}, p0/z, \[z3.d\]
-+[^:]+: c420c060 ld1b {z0.d}, p0/z, \[z3.d\]
-+[^:]+: c420c3e0 ld1b {z0.d}, p0/z, \[z31.d\]
-+[^:]+: c420c3e0 ld1b {z0.d}, p0/z, \[z31.d\]
-+[^:]+: c420c3e0 ld1b {z0.d}, p0/z, \[z31.d\]
-+[^:]+: c42fc000 ld1b {z0.d}, p0/z, \[z0.d, #15\]
-+[^:]+: c42fc000 ld1b {z0.d}, p0/z, \[z0.d, #15\]
-+[^:]+: c430c000 ld1b {z0.d}, p0/z, \[z0.d, #16\]
-+[^:]+: c430c000 ld1b {z0.d}, p0/z, \[z0.d, #16\]
-+[^:]+: c431c000 ld1b {z0.d}, p0/z, \[z0.d, #17\]
-+[^:]+: c431c000 ld1b {z0.d}, p0/z, \[z0.d, #17\]
-+[^:]+: c43fc000 ld1b {z0.d}, p0/z, \[z0.d, #31\]
-+[^:]+: c43fc000 ld1b {z0.d}, p0/z, \[z0.d, #31\]
-+[^:]+: a5e04000 ld1d {z0.d}, p0/z, \[x0, x0, lsl #3\]
-+[^:]+: a5e04000 ld1d {z0.d}, p0/z, \[x0, x0, lsl #3\]
-+[^:]+: a5e04000 ld1d {z0.d}, p0/z, \[x0, x0, lsl #3\]
-+[^:]+: a5e04001 ld1d {z1.d}, p0/z, \[x0, x0, lsl #3\]
-+[^:]+: a5e04001 ld1d {z1.d}, p0/z, \[x0, x0, lsl #3\]
-+[^:]+: a5e04001 ld1d {z1.d}, p0/z, \[x0, x0, lsl #3\]
-+[^:]+: a5e0401f ld1d {z31.d}, p0/z, \[x0, x0, lsl #3\]
-+[^:]+: a5e0401f ld1d {z31.d}, p0/z, \[x0, x0, lsl #3\]
-+[^:]+: a5e0401f ld1d {z31.d}, p0/z, \[x0, x0, lsl #3\]
-+[^:]+: a5e04800 ld1d {z0.d}, p2/z, \[x0, x0, lsl #3\]
-+[^:]+: a5e04800 ld1d {z0.d}, p2/z, \[x0, x0, lsl #3\]
-+[^:]+: a5e05c00 ld1d {z0.d}, p7/z, \[x0, x0, lsl #3\]
-+[^:]+: a5e05c00 ld1d {z0.d}, p7/z, \[x0, x0, lsl #3\]
-+[^:]+: a5e04060 ld1d {z0.d}, p0/z, \[x3, x0, lsl #3\]
-+[^:]+: a5e04060 ld1d {z0.d}, p0/z, \[x3, x0, lsl #3\]
-+[^:]+: a5e043e0 ld1d {z0.d}, p0/z, \[sp, x0, lsl #3\]
-+[^:]+: a5e043e0 ld1d {z0.d}, p0/z, \[sp, x0, lsl #3\]
-+[^:]+: a5e44000 ld1d {z0.d}, p0/z, \[x0, x4, lsl #3\]
-+[^:]+: a5e44000 ld1d {z0.d}, p0/z, \[x0, x4, lsl #3\]
-+[^:]+: a5fe4000 ld1d {z0.d}, p0/z, \[x0, x30, lsl #3\]
-+[^:]+: a5fe4000 ld1d {z0.d}, p0/z, \[x0, x30, lsl #3\]
-+[^:]+: c5804000 ld1d {z0.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c5804000 ld1d {z0.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c5804000 ld1d {z0.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c5804000 ld1d {z0.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c5804001 ld1d {z1.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c5804001 ld1d {z1.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c5804001 ld1d {z1.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c5804001 ld1d {z1.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c580401f ld1d {z31.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c580401f ld1d {z31.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c580401f ld1d {z31.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c580401f ld1d {z31.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c5804800 ld1d {z0.d}, p2/z, \[x0, z0.d, uxtw\]
-+[^:]+: c5804800 ld1d {z0.d}, p2/z, \[x0, z0.d, uxtw\]
-+[^:]+: c5804800 ld1d {z0.d}, p2/z, \[x0, z0.d, uxtw\]
-+[^:]+: c5805c00 ld1d {z0.d}, p7/z, \[x0, z0.d, uxtw\]
-+[^:]+: c5805c00 ld1d {z0.d}, p7/z, \[x0, z0.d, uxtw\]
-+[^:]+: c5805c00 ld1d {z0.d}, p7/z, \[x0, z0.d, uxtw\]
-+[^:]+: c5804060 ld1d {z0.d}, p0/z, \[x3, z0.d, uxtw\]
-+[^:]+: c5804060 ld1d {z0.d}, p0/z, \[x3, z0.d, uxtw\]
-+[^:]+: c5804060 ld1d {z0.d}, p0/z, \[x3, z0.d, uxtw\]
-+[^:]+: c58043e0 ld1d {z0.d}, p0/z, \[sp, z0.d, uxtw\]
-+[^:]+: c58043e0 ld1d {z0.d}, p0/z, \[sp, z0.d, uxtw\]
-+[^:]+: c58043e0 ld1d {z0.d}, p0/z, \[sp, z0.d, uxtw\]
-+[^:]+: c5844000 ld1d {z0.d}, p0/z, \[x0, z4.d, uxtw\]
-+[^:]+: c5844000 ld1d {z0.d}, p0/z, \[x0, z4.d, uxtw\]
-+[^:]+: c5844000 ld1d {z0.d}, p0/z, \[x0, z4.d, uxtw\]
-+[^:]+: c59f4000 ld1d {z0.d}, p0/z, \[x0, z31.d, uxtw\]
-+[^:]+: c59f4000 ld1d {z0.d}, p0/z, \[x0, z31.d, uxtw\]
-+[^:]+: c59f4000 ld1d {z0.d}, p0/z, \[x0, z31.d, uxtw\]
-+[^:]+: c5c04000 ld1d {z0.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5c04000 ld1d {z0.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5c04000 ld1d {z0.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5c04000 ld1d {z0.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5c04001 ld1d {z1.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5c04001 ld1d {z1.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5c04001 ld1d {z1.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5c04001 ld1d {z1.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5c0401f ld1d {z31.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5c0401f ld1d {z31.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5c0401f ld1d {z31.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5c0401f ld1d {z31.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5c04800 ld1d {z0.d}, p2/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5c04800 ld1d {z0.d}, p2/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5c04800 ld1d {z0.d}, p2/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5c05c00 ld1d {z0.d}, p7/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5c05c00 ld1d {z0.d}, p7/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5c05c00 ld1d {z0.d}, p7/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5c04060 ld1d {z0.d}, p0/z, \[x3, z0.d, sxtw\]
-+[^:]+: c5c04060 ld1d {z0.d}, p0/z, \[x3, z0.d, sxtw\]
-+[^:]+: c5c04060 ld1d {z0.d}, p0/z, \[x3, z0.d, sxtw\]
-+[^:]+: c5c043e0 ld1d {z0.d}, p0/z, \[sp, z0.d, sxtw\]
-+[^:]+: c5c043e0 ld1d {z0.d}, p0/z, \[sp, z0.d, sxtw\]
-+[^:]+: c5c043e0 ld1d {z0.d}, p0/z, \[sp, z0.d, sxtw\]
-+[^:]+: c5c44000 ld1d {z0.d}, p0/z, \[x0, z4.d, sxtw\]
-+[^:]+: c5c44000 ld1d {z0.d}, p0/z, \[x0, z4.d, sxtw\]
-+[^:]+: c5c44000 ld1d {z0.d}, p0/z, \[x0, z4.d, sxtw\]
-+[^:]+: c5df4000 ld1d {z0.d}, p0/z, \[x0, z31.d, sxtw\]
-+[^:]+: c5df4000 ld1d {z0.d}, p0/z, \[x0, z31.d, sxtw\]
-+[^:]+: c5df4000 ld1d {z0.d}, p0/z, \[x0, z31.d, sxtw\]
-+[^:]+: c5a04000 ld1d {z0.d}, p0/z, \[x0, z0.d, uxtw #3\]
-+[^:]+: c5a04000 ld1d {z0.d}, p0/z, \[x0, z0.d, uxtw #3\]
-+[^:]+: c5a04000 ld1d {z0.d}, p0/z, \[x0, z0.d, uxtw #3\]
-+[^:]+: c5a04001 ld1d {z1.d}, p0/z, \[x0, z0.d, uxtw #3\]
-+[^:]+: c5a04001 ld1d {z1.d}, p0/z, \[x0, z0.d, uxtw #3\]
-+[^:]+: c5a04001 ld1d {z1.d}, p0/z, \[x0, z0.d, uxtw #3\]
-+[^:]+: c5a0401f ld1d {z31.d}, p0/z, \[x0, z0.d, uxtw #3\]
-+[^:]+: c5a0401f ld1d {z31.d}, p0/z, \[x0, z0.d, uxtw #3\]
-+[^:]+: c5a0401f ld1d {z31.d}, p0/z, \[x0, z0.d, uxtw #3\]
-+[^:]+: c5a04800 ld1d {z0.d}, p2/z, \[x0, z0.d, uxtw #3\]
-+[^:]+: c5a04800 ld1d {z0.d}, p2/z, \[x0, z0.d, uxtw #3\]
-+[^:]+: c5a05c00 ld1d {z0.d}, p7/z, \[x0, z0.d, uxtw #3\]
-+[^:]+: c5a05c00 ld1d {z0.d}, p7/z, \[x0, z0.d, uxtw #3\]
-+[^:]+: c5a04060 ld1d {z0.d}, p0/z, \[x3, z0.d, uxtw #3\]
-+[^:]+: c5a04060 ld1d {z0.d}, p0/z, \[x3, z0.d, uxtw #3\]
-+[^:]+: c5a043e0 ld1d {z0.d}, p0/z, \[sp, z0.d, uxtw #3\]
-+[^:]+: c5a043e0 ld1d {z0.d}, p0/z, \[sp, z0.d, uxtw #3\]
-+[^:]+: c5a44000 ld1d {z0.d}, p0/z, \[x0, z4.d, uxtw #3\]
-+[^:]+: c5a44000 ld1d {z0.d}, p0/z, \[x0, z4.d, uxtw #3\]
-+[^:]+: c5bf4000 ld1d {z0.d}, p0/z, \[x0, z31.d, uxtw #3\]
-+[^:]+: c5bf4000 ld1d {z0.d}, p0/z, \[x0, z31.d, uxtw #3\]
-+[^:]+: c5e04000 ld1d {z0.d}, p0/z, \[x0, z0.d, sxtw #3\]
-+[^:]+: c5e04000 ld1d {z0.d}, p0/z, \[x0, z0.d, sxtw #3\]
-+[^:]+: c5e04000 ld1d {z0.d}, p0/z, \[x0, z0.d, sxtw #3\]
-+[^:]+: c5e04001 ld1d {z1.d}, p0/z, \[x0, z0.d, sxtw #3\]
-+[^:]+: c5e04001 ld1d {z1.d}, p0/z, \[x0, z0.d, sxtw #3\]
-+[^:]+: c5e04001 ld1d {z1.d}, p0/z, \[x0, z0.d, sxtw #3\]
-+[^:]+: c5e0401f ld1d {z31.d}, p0/z, \[x0, z0.d, sxtw #3\]
-+[^:]+: c5e0401f ld1d {z31.d}, p0/z, \[x0, z0.d, sxtw #3\]
-+[^:]+: c5e0401f ld1d {z31.d}, p0/z, \[x0, z0.d, sxtw #3\]
-+[^:]+: c5e04800 ld1d {z0.d}, p2/z, \[x0, z0.d, sxtw #3\]
-+[^:]+: c5e04800 ld1d {z0.d}, p2/z, \[x0, z0.d, sxtw #3\]
-+[^:]+: c5e05c00 ld1d {z0.d}, p7/z, \[x0, z0.d, sxtw #3\]
-+[^:]+: c5e05c00 ld1d {z0.d}, p7/z, \[x0, z0.d, sxtw #3\]
-+[^:]+: c5e04060 ld1d {z0.d}, p0/z, \[x3, z0.d, sxtw #3\]
-+[^:]+: c5e04060 ld1d {z0.d}, p0/z, \[x3, z0.d, sxtw #3\]
-+[^:]+: c5e043e0 ld1d {z0.d}, p0/z, \[sp, z0.d, sxtw #3\]
-+[^:]+: c5e043e0 ld1d {z0.d}, p0/z, \[sp, z0.d, sxtw #3\]
-+[^:]+: c5e44000 ld1d {z0.d}, p0/z, \[x0, z4.d, sxtw #3\]
-+[^:]+: c5e44000 ld1d {z0.d}, p0/z, \[x0, z4.d, sxtw #3\]
-+[^:]+: c5ff4000 ld1d {z0.d}, p0/z, \[x0, z31.d, sxtw #3\]
-+[^:]+: c5ff4000 ld1d {z0.d}, p0/z, \[x0, z31.d, sxtw #3\]
-+[^:]+: c5c0c000 ld1d {z0.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c5c0c000 ld1d {z0.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c5c0c000 ld1d {z0.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c5c0c000 ld1d {z0.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c5c0c001 ld1d {z1.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c5c0c001 ld1d {z1.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c5c0c001 ld1d {z1.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c5c0c001 ld1d {z1.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c5c0c01f ld1d {z31.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c5c0c01f ld1d {z31.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c5c0c01f ld1d {z31.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c5c0c01f ld1d {z31.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c5c0c800 ld1d {z0.d}, p2/z, \[x0, z0.d\]
-+[^:]+: c5c0c800 ld1d {z0.d}, p2/z, \[x0, z0.d\]
-+[^:]+: c5c0c800 ld1d {z0.d}, p2/z, \[x0, z0.d\]
-+[^:]+: c5c0dc00 ld1d {z0.d}, p7/z, \[x0, z0.d\]
-+[^:]+: c5c0dc00 ld1d {z0.d}, p7/z, \[x0, z0.d\]
-+[^:]+: c5c0dc00 ld1d {z0.d}, p7/z, \[x0, z0.d\]
-+[^:]+: c5c0c060 ld1d {z0.d}, p0/z, \[x3, z0.d\]
-+[^:]+: c5c0c060 ld1d {z0.d}, p0/z, \[x3, z0.d\]
-+[^:]+: c5c0c060 ld1d {z0.d}, p0/z, \[x3, z0.d\]
-+[^:]+: c5c0c3e0 ld1d {z0.d}, p0/z, \[sp, z0.d\]
-+[^:]+: c5c0c3e0 ld1d {z0.d}, p0/z, \[sp, z0.d\]
-+[^:]+: c5c0c3e0 ld1d {z0.d}, p0/z, \[sp, z0.d\]
-+[^:]+: c5c4c000 ld1d {z0.d}, p0/z, \[x0, z4.d\]
-+[^:]+: c5c4c000 ld1d {z0.d}, p0/z, \[x0, z4.d\]
-+[^:]+: c5c4c000 ld1d {z0.d}, p0/z, \[x0, z4.d\]
-+[^:]+: c5dfc000 ld1d {z0.d}, p0/z, \[x0, z31.d\]
-+[^:]+: c5dfc000 ld1d {z0.d}, p0/z, \[x0, z31.d\]
-+[^:]+: c5dfc000 ld1d {z0.d}, p0/z, \[x0, z31.d\]
-+[^:]+: c5e0c000 ld1d {z0.d}, p0/z, \[x0, z0.d, lsl #3\]
-+[^:]+: c5e0c000 ld1d {z0.d}, p0/z, \[x0, z0.d, lsl #3\]
-+[^:]+: c5e0c000 ld1d {z0.d}, p0/z, \[x0, z0.d, lsl #3\]
-+[^:]+: c5e0c001 ld1d {z1.d}, p0/z, \[x0, z0.d, lsl #3\]
-+[^:]+: c5e0c001 ld1d {z1.d}, p0/z, \[x0, z0.d, lsl #3\]
-+[^:]+: c5e0c001 ld1d {z1.d}, p0/z, \[x0, z0.d, lsl #3\]
-+[^:]+: c5e0c01f ld1d {z31.d}, p0/z, \[x0, z0.d, lsl #3\]
-+[^:]+: c5e0c01f ld1d {z31.d}, p0/z, \[x0, z0.d, lsl #3\]
-+[^:]+: c5e0c01f ld1d {z31.d}, p0/z, \[x0, z0.d, lsl #3\]
-+[^:]+: c5e0c800 ld1d {z0.d}, p2/z, \[x0, z0.d, lsl #3\]
-+[^:]+: c5e0c800 ld1d {z0.d}, p2/z, \[x0, z0.d, lsl #3\]
-+[^:]+: c5e0dc00 ld1d {z0.d}, p7/z, \[x0, z0.d, lsl #3\]
-+[^:]+: c5e0dc00 ld1d {z0.d}, p7/z, \[x0, z0.d, lsl #3\]
-+[^:]+: c5e0c060 ld1d {z0.d}, p0/z, \[x3, z0.d, lsl #3\]
-+[^:]+: c5e0c060 ld1d {z0.d}, p0/z, \[x3, z0.d, lsl #3\]
-+[^:]+: c5e0c3e0 ld1d {z0.d}, p0/z, \[sp, z0.d, lsl #3\]
-+[^:]+: c5e0c3e0 ld1d {z0.d}, p0/z, \[sp, z0.d, lsl #3\]
-+[^:]+: c5e4c000 ld1d {z0.d}, p0/z, \[x0, z4.d, lsl #3\]
-+[^:]+: c5e4c000 ld1d {z0.d}, p0/z, \[x0, z4.d, lsl #3\]
-+[^:]+: c5ffc000 ld1d {z0.d}, p0/z, \[x0, z31.d, lsl #3\]
-+[^:]+: c5ffc000 ld1d {z0.d}, p0/z, \[x0, z31.d, lsl #3\]
-+[^:]+: a5e0a000 ld1d {z0.d}, p0/z, \[x0\]
-+[^:]+: a5e0a000 ld1d {z0.d}, p0/z, \[x0\]
-+[^:]+: a5e0a000 ld1d {z0.d}, p0/z, \[x0\]
-+[^:]+: a5e0a000 ld1d {z0.d}, p0/z, \[x0\]
-+[^:]+: a5e0a000 ld1d {z0.d}, p0/z, \[x0\]
-+[^:]+: a5e0a001 ld1d {z1.d}, p0/z, \[x0\]
-+[^:]+: a5e0a001 ld1d {z1.d}, p0/z, \[x0\]
-+[^:]+: a5e0a001 ld1d {z1.d}, p0/z, \[x0\]
-+[^:]+: a5e0a001 ld1d {z1.d}, p0/z, \[x0\]
-+[^:]+: a5e0a001 ld1d {z1.d}, p0/z, \[x0\]
-+[^:]+: a5e0a01f ld1d {z31.d}, p0/z, \[x0\]
-+[^:]+: a5e0a01f ld1d {z31.d}, p0/z, \[x0\]
-+[^:]+: a5e0a01f ld1d {z31.d}, p0/z, \[x0\]
-+[^:]+: a5e0a01f ld1d {z31.d}, p0/z, \[x0\]
-+[^:]+: a5e0a01f ld1d {z31.d}, p0/z, \[x0\]
-+[^:]+: a5e0a800 ld1d {z0.d}, p2/z, \[x0\]
-+[^:]+: a5e0a800 ld1d {z0.d}, p2/z, \[x0\]
-+[^:]+: a5e0a800 ld1d {z0.d}, p2/z, \[x0\]
-+[^:]+: a5e0a800 ld1d {z0.d}, p2/z, \[x0\]
-+[^:]+: a5e0bc00 ld1d {z0.d}, p7/z, \[x0\]
-+[^:]+: a5e0bc00 ld1d {z0.d}, p7/z, \[x0\]
-+[^:]+: a5e0bc00 ld1d {z0.d}, p7/z, \[x0\]
-+[^:]+: a5e0bc00 ld1d {z0.d}, p7/z, \[x0\]
-+[^:]+: a5e0a060 ld1d {z0.d}, p0/z, \[x3\]
-+[^:]+: a5e0a060 ld1d {z0.d}, p0/z, \[x3\]
-+[^:]+: a5e0a060 ld1d {z0.d}, p0/z, \[x3\]
-+[^:]+: a5e0a060 ld1d {z0.d}, p0/z, \[x3\]
-+[^:]+: a5e0a3e0 ld1d {z0.d}, p0/z, \[sp\]
-+[^:]+: a5e0a3e0 ld1d {z0.d}, p0/z, \[sp\]
-+[^:]+: a5e0a3e0 ld1d {z0.d}, p0/z, \[sp\]
-+[^:]+: a5e0a3e0 ld1d {z0.d}, p0/z, \[sp\]
-+[^:]+: a5e7a000 ld1d {z0.d}, p0/z, \[x0, #7, mul vl\]
-+[^:]+: a5e7a000 ld1d {z0.d}, p0/z, \[x0, #7, mul vl\]
-+[^:]+: a5e8a000 ld1d {z0.d}, p0/z, \[x0, #-8, mul vl\]
-+[^:]+: a5e8a000 ld1d {z0.d}, p0/z, \[x0, #-8, mul vl\]
-+[^:]+: a5e9a000 ld1d {z0.d}, p0/z, \[x0, #-7, mul vl\]
-+[^:]+: a5e9a000 ld1d {z0.d}, p0/z, \[x0, #-7, mul vl\]
-+[^:]+: a5efa000 ld1d {z0.d}, p0/z, \[x0, #-1, mul vl\]
-+[^:]+: a5efa000 ld1d {z0.d}, p0/z, \[x0, #-1, mul vl\]
-+[^:]+: c5a0c000 ld1d {z0.d}, p0/z, \[z0.d\]
-+[^:]+: c5a0c000 ld1d {z0.d}, p0/z, \[z0.d\]
-+[^:]+: c5a0c000 ld1d {z0.d}, p0/z, \[z0.d\]
-+[^:]+: c5a0c000 ld1d {z0.d}, p0/z, \[z0.d\]
-+[^:]+: c5a0c001 ld1d {z1.d}, p0/z, \[z0.d\]
-+[^:]+: c5a0c001 ld1d {z1.d}, p0/z, \[z0.d\]
-+[^:]+: c5a0c001 ld1d {z1.d}, p0/z, \[z0.d\]
-+[^:]+: c5a0c001 ld1d {z1.d}, p0/z, \[z0.d\]
-+[^:]+: c5a0c01f ld1d {z31.d}, p0/z, \[z0.d\]
-+[^:]+: c5a0c01f ld1d {z31.d}, p0/z, \[z0.d\]
-+[^:]+: c5a0c01f ld1d {z31.d}, p0/z, \[z0.d\]
-+[^:]+: c5a0c01f ld1d {z31.d}, p0/z, \[z0.d\]
-+[^:]+: c5a0c800 ld1d {z0.d}, p2/z, \[z0.d\]
-+[^:]+: c5a0c800 ld1d {z0.d}, p2/z, \[z0.d\]
-+[^:]+: c5a0c800 ld1d {z0.d}, p2/z, \[z0.d\]
-+[^:]+: c5a0dc00 ld1d {z0.d}, p7/z, \[z0.d\]
-+[^:]+: c5a0dc00 ld1d {z0.d}, p7/z, \[z0.d\]
-+[^:]+: c5a0dc00 ld1d {z0.d}, p7/z, \[z0.d\]
-+[^:]+: c5a0c060 ld1d {z0.d}, p0/z, \[z3.d\]
-+[^:]+: c5a0c060 ld1d {z0.d}, p0/z, \[z3.d\]
-+[^:]+: c5a0c060 ld1d {z0.d}, p0/z, \[z3.d\]
-+[^:]+: c5a0c3e0 ld1d {z0.d}, p0/z, \[z31.d\]
-+[^:]+: c5a0c3e0 ld1d {z0.d}, p0/z, \[z31.d\]
-+[^:]+: c5a0c3e0 ld1d {z0.d}, p0/z, \[z31.d\]
-+[^:]+: c5afc000 ld1d {z0.d}, p0/z, \[z0.d, #120\]
-+[^:]+: c5afc000 ld1d {z0.d}, p0/z, \[z0.d, #120\]
-+[^:]+: c5b0c000 ld1d {z0.d}, p0/z, \[z0.d, #128\]
-+[^:]+: c5b0c000 ld1d {z0.d}, p0/z, \[z0.d, #128\]
-+[^:]+: c5b1c000 ld1d {z0.d}, p0/z, \[z0.d, #136\]
-+[^:]+: c5b1c000 ld1d {z0.d}, p0/z, \[z0.d, #136\]
-+[^:]+: c5bfc000 ld1d {z0.d}, p0/z, \[z0.d, #248\]
-+[^:]+: c5bfc000 ld1d {z0.d}, p0/z, \[z0.d, #248\]
-+[^:]+: 84804000 ld1h {z0.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84804000 ld1h {z0.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84804000 ld1h {z0.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84804000 ld1h {z0.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84804001 ld1h {z1.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84804001 ld1h {z1.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84804001 ld1h {z1.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84804001 ld1h {z1.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 8480401f ld1h {z31.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 8480401f ld1h {z31.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 8480401f ld1h {z31.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 8480401f ld1h {z31.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84804800 ld1h {z0.s}, p2/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84804800 ld1h {z0.s}, p2/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84804800 ld1h {z0.s}, p2/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84805c00 ld1h {z0.s}, p7/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84805c00 ld1h {z0.s}, p7/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84805c00 ld1h {z0.s}, p7/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84804060 ld1h {z0.s}, p0/z, \[x3, z0.s, uxtw\]
-+[^:]+: 84804060 ld1h {z0.s}, p0/z, \[x3, z0.s, uxtw\]
-+[^:]+: 84804060 ld1h {z0.s}, p0/z, \[x3, z0.s, uxtw\]
-+[^:]+: 848043e0 ld1h {z0.s}, p0/z, \[sp, z0.s, uxtw\]
-+[^:]+: 848043e0 ld1h {z0.s}, p0/z, \[sp, z0.s, uxtw\]
-+[^:]+: 848043e0 ld1h {z0.s}, p0/z, \[sp, z0.s, uxtw\]
-+[^:]+: 84844000 ld1h {z0.s}, p0/z, \[x0, z4.s, uxtw\]
-+[^:]+: 84844000 ld1h {z0.s}, p0/z, \[x0, z4.s, uxtw\]
-+[^:]+: 84844000 ld1h {z0.s}, p0/z, \[x0, z4.s, uxtw\]
-+[^:]+: 849f4000 ld1h {z0.s}, p0/z, \[x0, z31.s, uxtw\]
-+[^:]+: 849f4000 ld1h {z0.s}, p0/z, \[x0, z31.s, uxtw\]
-+[^:]+: 849f4000 ld1h {z0.s}, p0/z, \[x0, z31.s, uxtw\]
-+[^:]+: 84c04000 ld1h {z0.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84c04000 ld1h {z0.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84c04000 ld1h {z0.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84c04000 ld1h {z0.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84c04001 ld1h {z1.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84c04001 ld1h {z1.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84c04001 ld1h {z1.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84c04001 ld1h {z1.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84c0401f ld1h {z31.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84c0401f ld1h {z31.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84c0401f ld1h {z31.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84c0401f ld1h {z31.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84c04800 ld1h {z0.s}, p2/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84c04800 ld1h {z0.s}, p2/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84c04800 ld1h {z0.s}, p2/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84c05c00 ld1h {z0.s}, p7/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84c05c00 ld1h {z0.s}, p7/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84c05c00 ld1h {z0.s}, p7/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84c04060 ld1h {z0.s}, p0/z, \[x3, z0.s, sxtw\]
-+[^:]+: 84c04060 ld1h {z0.s}, p0/z, \[x3, z0.s, sxtw\]
-+[^:]+: 84c04060 ld1h {z0.s}, p0/z, \[x3, z0.s, sxtw\]
-+[^:]+: 84c043e0 ld1h {z0.s}, p0/z, \[sp, z0.s, sxtw\]
-+[^:]+: 84c043e0 ld1h {z0.s}, p0/z, \[sp, z0.s, sxtw\]
-+[^:]+: 84c043e0 ld1h {z0.s}, p0/z, \[sp, z0.s, sxtw\]
-+[^:]+: 84c44000 ld1h {z0.s}, p0/z, \[x0, z4.s, sxtw\]
-+[^:]+: 84c44000 ld1h {z0.s}, p0/z, \[x0, z4.s, sxtw\]
-+[^:]+: 84c44000 ld1h {z0.s}, p0/z, \[x0, z4.s, sxtw\]
-+[^:]+: 84df4000 ld1h {z0.s}, p0/z, \[x0, z31.s, sxtw\]
-+[^:]+: 84df4000 ld1h {z0.s}, p0/z, \[x0, z31.s, sxtw\]
-+[^:]+: 84df4000 ld1h {z0.s}, p0/z, \[x0, z31.s, sxtw\]
-+[^:]+: 84a04000 ld1h {z0.s}, p0/z, \[x0, z0.s, uxtw #1\]
-+[^:]+: 84a04000 ld1h {z0.s}, p0/z, \[x0, z0.s, uxtw #1\]
-+[^:]+: 84a04000 ld1h {z0.s}, p0/z, \[x0, z0.s, uxtw #1\]
-+[^:]+: 84a04001 ld1h {z1.s}, p0/z, \[x0, z0.s, uxtw #1\]
-+[^:]+: 84a04001 ld1h {z1.s}, p0/z, \[x0, z0.s, uxtw #1\]
-+[^:]+: 84a04001 ld1h {z1.s}, p0/z, \[x0, z0.s, uxtw #1\]
-+[^:]+: 84a0401f ld1h {z31.s}, p0/z, \[x0, z0.s, uxtw #1\]
-+[^:]+: 84a0401f ld1h {z31.s}, p0/z, \[x0, z0.s, uxtw #1\]
-+[^:]+: 84a0401f ld1h {z31.s}, p0/z, \[x0, z0.s, uxtw #1\]
-+[^:]+: 84a04800 ld1h {z0.s}, p2/z, \[x0, z0.s, uxtw #1\]
-+[^:]+: 84a04800 ld1h {z0.s}, p2/z, \[x0, z0.s, uxtw #1\]
-+[^:]+: 84a05c00 ld1h {z0.s}, p7/z, \[x0, z0.s, uxtw #1\]
-+[^:]+: 84a05c00 ld1h {z0.s}, p7/z, \[x0, z0.s, uxtw #1\]
-+[^:]+: 84a04060 ld1h {z0.s}, p0/z, \[x3, z0.s, uxtw #1\]
-+[^:]+: 84a04060 ld1h {z0.s}, p0/z, \[x3, z0.s, uxtw #1\]
-+[^:]+: 84a043e0 ld1h {z0.s}, p0/z, \[sp, z0.s, uxtw #1\]
-+[^:]+: 84a043e0 ld1h {z0.s}, p0/z, \[sp, z0.s, uxtw #1\]
-+[^:]+: 84a44000 ld1h {z0.s}, p0/z, \[x0, z4.s, uxtw #1\]
-+[^:]+: 84a44000 ld1h {z0.s}, p0/z, \[x0, z4.s, uxtw #1\]
-+[^:]+: 84bf4000 ld1h {z0.s}, p0/z, \[x0, z31.s, uxtw #1\]
-+[^:]+: 84bf4000 ld1h {z0.s}, p0/z, \[x0, z31.s, uxtw #1\]
-+[^:]+: 84e04000 ld1h {z0.s}, p0/z, \[x0, z0.s, sxtw #1\]
-+[^:]+: 84e04000 ld1h {z0.s}, p0/z, \[x0, z0.s, sxtw #1\]
-+[^:]+: 84e04000 ld1h {z0.s}, p0/z, \[x0, z0.s, sxtw #1\]
-+[^:]+: 84e04001 ld1h {z1.s}, p0/z, \[x0, z0.s, sxtw #1\]
-+[^:]+: 84e04001 ld1h {z1.s}, p0/z, \[x0, z0.s, sxtw #1\]
-+[^:]+: 84e04001 ld1h {z1.s}, p0/z, \[x0, z0.s, sxtw #1\]
-+[^:]+: 84e0401f ld1h {z31.s}, p0/z, \[x0, z0.s, sxtw #1\]
-+[^:]+: 84e0401f ld1h {z31.s}, p0/z, \[x0, z0.s, sxtw #1\]
-+[^:]+: 84e0401f ld1h {z31.s}, p0/z, \[x0, z0.s, sxtw #1\]
-+[^:]+: 84e04800 ld1h {z0.s}, p2/z, \[x0, z0.s, sxtw #1\]
-+[^:]+: 84e04800 ld1h {z0.s}, p2/z, \[x0, z0.s, sxtw #1\]
-+[^:]+: 84e05c00 ld1h {z0.s}, p7/z, \[x0, z0.s, sxtw #1\]
-+[^:]+: 84e05c00 ld1h {z0.s}, p7/z, \[x0, z0.s, sxtw #1\]
-+[^:]+: 84e04060 ld1h {z0.s}, p0/z, \[x3, z0.s, sxtw #1\]
-+[^:]+: 84e04060 ld1h {z0.s}, p0/z, \[x3, z0.s, sxtw #1\]
-+[^:]+: 84e043e0 ld1h {z0.s}, p0/z, \[sp, z0.s, sxtw #1\]
-+[^:]+: 84e043e0 ld1h {z0.s}, p0/z, \[sp, z0.s, sxtw #1\]
-+[^:]+: 84e44000 ld1h {z0.s}, p0/z, \[x0, z4.s, sxtw #1\]
-+[^:]+: 84e44000 ld1h {z0.s}, p0/z, \[x0, z4.s, sxtw #1\]
-+[^:]+: 84ff4000 ld1h {z0.s}, p0/z, \[x0, z31.s, sxtw #1\]
-+[^:]+: 84ff4000 ld1h {z0.s}, p0/z, \[x0, z31.s, sxtw #1\]
-+[^:]+: a4a04000 ld1h {z0.h}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a4a04000 ld1h {z0.h}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a4a04000 ld1h {z0.h}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a4a04001 ld1h {z1.h}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a4a04001 ld1h {z1.h}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a4a04001 ld1h {z1.h}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a4a0401f ld1h {z31.h}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a4a0401f ld1h {z31.h}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a4a0401f ld1h {z31.h}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a4a04800 ld1h {z0.h}, p2/z, \[x0, x0, lsl #1\]
-+[^:]+: a4a04800 ld1h {z0.h}, p2/z, \[x0, x0, lsl #1\]
-+[^:]+: a4a05c00 ld1h {z0.h}, p7/z, \[x0, x0, lsl #1\]
-+[^:]+: a4a05c00 ld1h {z0.h}, p7/z, \[x0, x0, lsl #1\]
-+[^:]+: a4a04060 ld1h {z0.h}, p0/z, \[x3, x0, lsl #1\]
-+[^:]+: a4a04060 ld1h {z0.h}, p0/z, \[x3, x0, lsl #1\]
-+[^:]+: a4a043e0 ld1h {z0.h}, p0/z, \[sp, x0, lsl #1\]
-+[^:]+: a4a043e0 ld1h {z0.h}, p0/z, \[sp, x0, lsl #1\]
-+[^:]+: a4a44000 ld1h {z0.h}, p0/z, \[x0, x4, lsl #1\]
-+[^:]+: a4a44000 ld1h {z0.h}, p0/z, \[x0, x4, lsl #1\]
-+[^:]+: a4be4000 ld1h {z0.h}, p0/z, \[x0, x30, lsl #1\]
-+[^:]+: a4be4000 ld1h {z0.h}, p0/z, \[x0, x30, lsl #1\]
-+[^:]+: a4c04000 ld1h {z0.s}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a4c04000 ld1h {z0.s}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a4c04000 ld1h {z0.s}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a4c04001 ld1h {z1.s}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a4c04001 ld1h {z1.s}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a4c04001 ld1h {z1.s}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a4c0401f ld1h {z31.s}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a4c0401f ld1h {z31.s}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a4c0401f ld1h {z31.s}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a4c04800 ld1h {z0.s}, p2/z, \[x0, x0, lsl #1\]
-+[^:]+: a4c04800 ld1h {z0.s}, p2/z, \[x0, x0, lsl #1\]
-+[^:]+: a4c05c00 ld1h {z0.s}, p7/z, \[x0, x0, lsl #1\]
-+[^:]+: a4c05c00 ld1h {z0.s}, p7/z, \[x0, x0, lsl #1\]
-+[^:]+: a4c04060 ld1h {z0.s}, p0/z, \[x3, x0, lsl #1\]
-+[^:]+: a4c04060 ld1h {z0.s}, p0/z, \[x3, x0, lsl #1\]
-+[^:]+: a4c043e0 ld1h {z0.s}, p0/z, \[sp, x0, lsl #1\]
-+[^:]+: a4c043e0 ld1h {z0.s}, p0/z, \[sp, x0, lsl #1\]
-+[^:]+: a4c44000 ld1h {z0.s}, p0/z, \[x0, x4, lsl #1\]
-+[^:]+: a4c44000 ld1h {z0.s}, p0/z, \[x0, x4, lsl #1\]
-+[^:]+: a4de4000 ld1h {z0.s}, p0/z, \[x0, x30, lsl #1\]
-+[^:]+: a4de4000 ld1h {z0.s}, p0/z, \[x0, x30, lsl #1\]
-+[^:]+: a4e04000 ld1h {z0.d}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a4e04000 ld1h {z0.d}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a4e04000 ld1h {z0.d}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a4e04001 ld1h {z1.d}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a4e04001 ld1h {z1.d}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a4e04001 ld1h {z1.d}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a4e0401f ld1h {z31.d}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a4e0401f ld1h {z31.d}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a4e0401f ld1h {z31.d}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a4e04800 ld1h {z0.d}, p2/z, \[x0, x0, lsl #1\]
-+[^:]+: a4e04800 ld1h {z0.d}, p2/z, \[x0, x0, lsl #1\]
-+[^:]+: a4e05c00 ld1h {z0.d}, p7/z, \[x0, x0, lsl #1\]
-+[^:]+: a4e05c00 ld1h {z0.d}, p7/z, \[x0, x0, lsl #1\]
-+[^:]+: a4e04060 ld1h {z0.d}, p0/z, \[x3, x0, lsl #1\]
-+[^:]+: a4e04060 ld1h {z0.d}, p0/z, \[x3, x0, lsl #1\]
-+[^:]+: a4e043e0 ld1h {z0.d}, p0/z, \[sp, x0, lsl #1\]
-+[^:]+: a4e043e0 ld1h {z0.d}, p0/z, \[sp, x0, lsl #1\]
-+[^:]+: a4e44000 ld1h {z0.d}, p0/z, \[x0, x4, lsl #1\]
-+[^:]+: a4e44000 ld1h {z0.d}, p0/z, \[x0, x4, lsl #1\]
-+[^:]+: a4fe4000 ld1h {z0.d}, p0/z, \[x0, x30, lsl #1\]
-+[^:]+: a4fe4000 ld1h {z0.d}, p0/z, \[x0, x30, lsl #1\]
-+[^:]+: c4804000 ld1h {z0.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4804000 ld1h {z0.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4804000 ld1h {z0.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4804000 ld1h {z0.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4804001 ld1h {z1.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4804001 ld1h {z1.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4804001 ld1h {z1.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4804001 ld1h {z1.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c480401f ld1h {z31.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c480401f ld1h {z31.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c480401f ld1h {z31.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c480401f ld1h {z31.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4804800 ld1h {z0.d}, p2/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4804800 ld1h {z0.d}, p2/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4804800 ld1h {z0.d}, p2/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4805c00 ld1h {z0.d}, p7/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4805c00 ld1h {z0.d}, p7/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4805c00 ld1h {z0.d}, p7/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4804060 ld1h {z0.d}, p0/z, \[x3, z0.d, uxtw\]
-+[^:]+: c4804060 ld1h {z0.d}, p0/z, \[x3, z0.d, uxtw\]
-+[^:]+: c4804060 ld1h {z0.d}, p0/z, \[x3, z0.d, uxtw\]
-+[^:]+: c48043e0 ld1h {z0.d}, p0/z, \[sp, z0.d, uxtw\]
-+[^:]+: c48043e0 ld1h {z0.d}, p0/z, \[sp, z0.d, uxtw\]
-+[^:]+: c48043e0 ld1h {z0.d}, p0/z, \[sp, z0.d, uxtw\]
-+[^:]+: c4844000 ld1h {z0.d}, p0/z, \[x0, z4.d, uxtw\]
-+[^:]+: c4844000 ld1h {z0.d}, p0/z, \[x0, z4.d, uxtw\]
-+[^:]+: c4844000 ld1h {z0.d}, p0/z, \[x0, z4.d, uxtw\]
-+[^:]+: c49f4000 ld1h {z0.d}, p0/z, \[x0, z31.d, uxtw\]
-+[^:]+: c49f4000 ld1h {z0.d}, p0/z, \[x0, z31.d, uxtw\]
-+[^:]+: c49f4000 ld1h {z0.d}, p0/z, \[x0, z31.d, uxtw\]
-+[^:]+: c4c04000 ld1h {z0.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4c04000 ld1h {z0.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4c04000 ld1h {z0.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4c04000 ld1h {z0.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4c04001 ld1h {z1.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4c04001 ld1h {z1.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4c04001 ld1h {z1.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4c04001 ld1h {z1.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4c0401f ld1h {z31.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4c0401f ld1h {z31.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4c0401f ld1h {z31.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4c0401f ld1h {z31.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4c04800 ld1h {z0.d}, p2/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4c04800 ld1h {z0.d}, p2/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4c04800 ld1h {z0.d}, p2/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4c05c00 ld1h {z0.d}, p7/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4c05c00 ld1h {z0.d}, p7/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4c05c00 ld1h {z0.d}, p7/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4c04060 ld1h {z0.d}, p0/z, \[x3, z0.d, sxtw\]
-+[^:]+: c4c04060 ld1h {z0.d}, p0/z, \[x3, z0.d, sxtw\]
-+[^:]+: c4c04060 ld1h {z0.d}, p0/z, \[x3, z0.d, sxtw\]
-+[^:]+: c4c043e0 ld1h {z0.d}, p0/z, \[sp, z0.d, sxtw\]
-+[^:]+: c4c043e0 ld1h {z0.d}, p0/z, \[sp, z0.d, sxtw\]
-+[^:]+: c4c043e0 ld1h {z0.d}, p0/z, \[sp, z0.d, sxtw\]
-+[^:]+: c4c44000 ld1h {z0.d}, p0/z, \[x0, z4.d, sxtw\]
-+[^:]+: c4c44000 ld1h {z0.d}, p0/z, \[x0, z4.d, sxtw\]
-+[^:]+: c4c44000 ld1h {z0.d}, p0/z, \[x0, z4.d, sxtw\]
-+[^:]+: c4df4000 ld1h {z0.d}, p0/z, \[x0, z31.d, sxtw\]
-+[^:]+: c4df4000 ld1h {z0.d}, p0/z, \[x0, z31.d, sxtw\]
-+[^:]+: c4df4000 ld1h {z0.d}, p0/z, \[x0, z31.d, sxtw\]
-+[^:]+: c4a04000 ld1h {z0.d}, p0/z, \[x0, z0.d, uxtw #1\]
-+[^:]+: c4a04000 ld1h {z0.d}, p0/z, \[x0, z0.d, uxtw #1\]
-+[^:]+: c4a04000 ld1h {z0.d}, p0/z, \[x0, z0.d, uxtw #1\]
-+[^:]+: c4a04001 ld1h {z1.d}, p0/z, \[x0, z0.d, uxtw #1\]
-+[^:]+: c4a04001 ld1h {z1.d}, p0/z, \[x0, z0.d, uxtw #1\]
-+[^:]+: c4a04001 ld1h {z1.d}, p0/z, \[x0, z0.d, uxtw #1\]
-+[^:]+: c4a0401f ld1h {z31.d}, p0/z, \[x0, z0.d, uxtw #1\]
-+[^:]+: c4a0401f ld1h {z31.d}, p0/z, \[x0, z0.d, uxtw #1\]
-+[^:]+: c4a0401f ld1h {z31.d}, p0/z, \[x0, z0.d, uxtw #1\]
-+[^:]+: c4a04800 ld1h {z0.d}, p2/z, \[x0, z0.d, uxtw #1\]
-+[^:]+: c4a04800 ld1h {z0.d}, p2/z, \[x0, z0.d, uxtw #1\]
-+[^:]+: c4a05c00 ld1h {z0.d}, p7/z, \[x0, z0.d, uxtw #1\]
-+[^:]+: c4a05c00 ld1h {z0.d}, p7/z, \[x0, z0.d, uxtw #1\]
-+[^:]+: c4a04060 ld1h {z0.d}, p0/z, \[x3, z0.d, uxtw #1\]
-+[^:]+: c4a04060 ld1h {z0.d}, p0/z, \[x3, z0.d, uxtw #1\]
-+[^:]+: c4a043e0 ld1h {z0.d}, p0/z, \[sp, z0.d, uxtw #1\]
-+[^:]+: c4a043e0 ld1h {z0.d}, p0/z, \[sp, z0.d, uxtw #1\]
-+[^:]+: c4a44000 ld1h {z0.d}, p0/z, \[x0, z4.d, uxtw #1\]
-+[^:]+: c4a44000 ld1h {z0.d}, p0/z, \[x0, z4.d, uxtw #1\]
-+[^:]+: c4bf4000 ld1h {z0.d}, p0/z, \[x0, z31.d, uxtw #1\]
-+[^:]+: c4bf4000 ld1h {z0.d}, p0/z, \[x0, z31.d, uxtw #1\]
-+[^:]+: c4e04000 ld1h {z0.d}, p0/z, \[x0, z0.d, sxtw #1\]
-+[^:]+: c4e04000 ld1h {z0.d}, p0/z, \[x0, z0.d, sxtw #1\]
-+[^:]+: c4e04000 ld1h {z0.d}, p0/z, \[x0, z0.d, sxtw #1\]
-+[^:]+: c4e04001 ld1h {z1.d}, p0/z, \[x0, z0.d, sxtw #1\]
-+[^:]+: c4e04001 ld1h {z1.d}, p0/z, \[x0, z0.d, sxtw #1\]
-+[^:]+: c4e04001 ld1h {z1.d}, p0/z, \[x0, z0.d, sxtw #1\]
-+[^:]+: c4e0401f ld1h {z31.d}, p0/z, \[x0, z0.d, sxtw #1\]
-+[^:]+: c4e0401f ld1h {z31.d}, p0/z, \[x0, z0.d, sxtw #1\]
-+[^:]+: c4e0401f ld1h {z31.d}, p0/z, \[x0, z0.d, sxtw #1\]
-+[^:]+: c4e04800 ld1h {z0.d}, p2/z, \[x0, z0.d, sxtw #1\]
-+[^:]+: c4e04800 ld1h {z0.d}, p2/z, \[x0, z0.d, sxtw #1\]
-+[^:]+: c4e05c00 ld1h {z0.d}, p7/z, \[x0, z0.d, sxtw #1\]
-+[^:]+: c4e05c00 ld1h {z0.d}, p7/z, \[x0, z0.d, sxtw #1\]
-+[^:]+: c4e04060 ld1h {z0.d}, p0/z, \[x3, z0.d, sxtw #1\]
-+[^:]+: c4e04060 ld1h {z0.d}, p0/z, \[x3, z0.d, sxtw #1\]
-+[^:]+: c4e043e0 ld1h {z0.d}, p0/z, \[sp, z0.d, sxtw #1\]
-+[^:]+: c4e043e0 ld1h {z0.d}, p0/z, \[sp, z0.d, sxtw #1\]
-+[^:]+: c4e44000 ld1h {z0.d}, p0/z, \[x0, z4.d, sxtw #1\]
-+[^:]+: c4e44000 ld1h {z0.d}, p0/z, \[x0, z4.d, sxtw #1\]
-+[^:]+: c4ff4000 ld1h {z0.d}, p0/z, \[x0, z31.d, sxtw #1\]
-+[^:]+: c4ff4000 ld1h {z0.d}, p0/z, \[x0, z31.d, sxtw #1\]
-+[^:]+: c4c0c000 ld1h {z0.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c4c0c000 ld1h {z0.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c4c0c000 ld1h {z0.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c4c0c000 ld1h {z0.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c4c0c001 ld1h {z1.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c4c0c001 ld1h {z1.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c4c0c001 ld1h {z1.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c4c0c001 ld1h {z1.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c4c0c01f ld1h {z31.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c4c0c01f ld1h {z31.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c4c0c01f ld1h {z31.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c4c0c01f ld1h {z31.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c4c0c800 ld1h {z0.d}, p2/z, \[x0, z0.d\]
-+[^:]+: c4c0c800 ld1h {z0.d}, p2/z, \[x0, z0.d\]
-+[^:]+: c4c0c800 ld1h {z0.d}, p2/z, \[x0, z0.d\]
-+[^:]+: c4c0dc00 ld1h {z0.d}, p7/z, \[x0, z0.d\]
-+[^:]+: c4c0dc00 ld1h {z0.d}, p7/z, \[x0, z0.d\]
-+[^:]+: c4c0dc00 ld1h {z0.d}, p7/z, \[x0, z0.d\]
-+[^:]+: c4c0c060 ld1h {z0.d}, p0/z, \[x3, z0.d\]
-+[^:]+: c4c0c060 ld1h {z0.d}, p0/z, \[x3, z0.d\]
-+[^:]+: c4c0c060 ld1h {z0.d}, p0/z, \[x3, z0.d\]
-+[^:]+: c4c0c3e0 ld1h {z0.d}, p0/z, \[sp, z0.d\]
-+[^:]+: c4c0c3e0 ld1h {z0.d}, p0/z, \[sp, z0.d\]
-+[^:]+: c4c0c3e0 ld1h {z0.d}, p0/z, \[sp, z0.d\]
-+[^:]+: c4c4c000 ld1h {z0.d}, p0/z, \[x0, z4.d\]
-+[^:]+: c4c4c000 ld1h {z0.d}, p0/z, \[x0, z4.d\]
-+[^:]+: c4c4c000 ld1h {z0.d}, p0/z, \[x0, z4.d\]
-+[^:]+: c4dfc000 ld1h {z0.d}, p0/z, \[x0, z31.d\]
-+[^:]+: c4dfc000 ld1h {z0.d}, p0/z, \[x0, z31.d\]
-+[^:]+: c4dfc000 ld1h {z0.d}, p0/z, \[x0, z31.d\]
-+[^:]+: c4e0c000 ld1h {z0.d}, p0/z, \[x0, z0.d, lsl #1\]
-+[^:]+: c4e0c000 ld1h {z0.d}, p0/z, \[x0, z0.d, lsl #1\]
-+[^:]+: c4e0c000 ld1h {z0.d}, p0/z, \[x0, z0.d, lsl #1\]
-+[^:]+: c4e0c001 ld1h {z1.d}, p0/z, \[x0, z0.d, lsl #1\]
-+[^:]+: c4e0c001 ld1h {z1.d}, p0/z, \[x0, z0.d, lsl #1\]
-+[^:]+: c4e0c001 ld1h {z1.d}, p0/z, \[x0, z0.d, lsl #1\]
-+[^:]+: c4e0c01f ld1h {z31.d}, p0/z, \[x0, z0.d, lsl #1\]
-+[^:]+: c4e0c01f ld1h {z31.d}, p0/z, \[x0, z0.d, lsl #1\]
-+[^:]+: c4e0c01f ld1h {z31.d}, p0/z, \[x0, z0.d, lsl #1\]
-+[^:]+: c4e0c800 ld1h {z0.d}, p2/z, \[x0, z0.d, lsl #1\]
-+[^:]+: c4e0c800 ld1h {z0.d}, p2/z, \[x0, z0.d, lsl #1\]
-+[^:]+: c4e0dc00 ld1h {z0.d}, p7/z, \[x0, z0.d, lsl #1\]
-+[^:]+: c4e0dc00 ld1h {z0.d}, p7/z, \[x0, z0.d, lsl #1\]
-+[^:]+: c4e0c060 ld1h {z0.d}, p0/z, \[x3, z0.d, lsl #1\]
-+[^:]+: c4e0c060 ld1h {z0.d}, p0/z, \[x3, z0.d, lsl #1\]
-+[^:]+: c4e0c3e0 ld1h {z0.d}, p0/z, \[sp, z0.d, lsl #1\]
-+[^:]+: c4e0c3e0 ld1h {z0.d}, p0/z, \[sp, z0.d, lsl #1\]
-+[^:]+: c4e4c000 ld1h {z0.d}, p0/z, \[x0, z4.d, lsl #1\]
-+[^:]+: c4e4c000 ld1h {z0.d}, p0/z, \[x0, z4.d, lsl #1\]
-+[^:]+: c4ffc000 ld1h {z0.d}, p0/z, \[x0, z31.d, lsl #1\]
-+[^:]+: c4ffc000 ld1h {z0.d}, p0/z, \[x0, z31.d, lsl #1\]
-+[^:]+: 84a0c000 ld1h {z0.s}, p0/z, \[z0.s\]
-+[^:]+: 84a0c000 ld1h {z0.s}, p0/z, \[z0.s\]
-+[^:]+: 84a0c000 ld1h {z0.s}, p0/z, \[z0.s\]
-+[^:]+: 84a0c000 ld1h {z0.s}, p0/z, \[z0.s\]
-+[^:]+: 84a0c001 ld1h {z1.s}, p0/z, \[z0.s\]
-+[^:]+: 84a0c001 ld1h {z1.s}, p0/z, \[z0.s\]
-+[^:]+: 84a0c001 ld1h {z1.s}, p0/z, \[z0.s\]
-+[^:]+: 84a0c001 ld1h {z1.s}, p0/z, \[z0.s\]
-+[^:]+: 84a0c01f ld1h {z31.s}, p0/z, \[z0.s\]
-+[^:]+: 84a0c01f ld1h {z31.s}, p0/z, \[z0.s\]
-+[^:]+: 84a0c01f ld1h {z31.s}, p0/z, \[z0.s\]
-+[^:]+: 84a0c01f ld1h {z31.s}, p0/z, \[z0.s\]
-+[^:]+: 84a0c800 ld1h {z0.s}, p2/z, \[z0.s\]
-+[^:]+: 84a0c800 ld1h {z0.s}, p2/z, \[z0.s\]
-+[^:]+: 84a0c800 ld1h {z0.s}, p2/z, \[z0.s\]
-+[^:]+: 84a0dc00 ld1h {z0.s}, p7/z, \[z0.s\]
-+[^:]+: 84a0dc00 ld1h {z0.s}, p7/z, \[z0.s\]
-+[^:]+: 84a0dc00 ld1h {z0.s}, p7/z, \[z0.s\]
-+[^:]+: 84a0c060 ld1h {z0.s}, p0/z, \[z3.s\]
-+[^:]+: 84a0c060 ld1h {z0.s}, p0/z, \[z3.s\]
-+[^:]+: 84a0c060 ld1h {z0.s}, p0/z, \[z3.s\]
-+[^:]+: 84a0c3e0 ld1h {z0.s}, p0/z, \[z31.s\]
-+[^:]+: 84a0c3e0 ld1h {z0.s}, p0/z, \[z31.s\]
-+[^:]+: 84a0c3e0 ld1h {z0.s}, p0/z, \[z31.s\]
-+[^:]+: 84afc000 ld1h {z0.s}, p0/z, \[z0.s, #30\]
-+[^:]+: 84afc000 ld1h {z0.s}, p0/z, \[z0.s, #30\]
-+[^:]+: 84b0c000 ld1h {z0.s}, p0/z, \[z0.s, #32\]
-+[^:]+: 84b0c000 ld1h {z0.s}, p0/z, \[z0.s, #32\]
-+[^:]+: 84b1c000 ld1h {z0.s}, p0/z, \[z0.s, #34\]
-+[^:]+: 84b1c000 ld1h {z0.s}, p0/z, \[z0.s, #34\]
-+[^:]+: 84bfc000 ld1h {z0.s}, p0/z, \[z0.s, #62\]
-+[^:]+: 84bfc000 ld1h {z0.s}, p0/z, \[z0.s, #62\]
-+[^:]+: a4a0a000 ld1h {z0.h}, p0/z, \[x0\]
-+[^:]+: a4a0a000 ld1h {z0.h}, p0/z, \[x0\]
-+[^:]+: a4a0a000 ld1h {z0.h}, p0/z, \[x0\]
-+[^:]+: a4a0a000 ld1h {z0.h}, p0/z, \[x0\]
-+[^:]+: a4a0a000 ld1h {z0.h}, p0/z, \[x0\]
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-+[^:]+: a4a0a001 ld1h {z1.h}, p0/z, \[x0\]
-+[^:]+: a4a0a001 ld1h {z1.h}, p0/z, \[x0\]
-+[^:]+: a4a0a001 ld1h {z1.h}, p0/z, \[x0\]
-+[^:]+: a4a0a001 ld1h {z1.h}, p0/z, \[x0\]
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-+[^:]+: a4a0a01f ld1h {z31.h}, p0/z, \[x0\]
-+[^:]+: a4a0a01f ld1h {z31.h}, p0/z, \[x0\]
-+[^:]+: a4a0a01f ld1h {z31.h}, p0/z, \[x0\]
-+[^:]+: a4a0a01f ld1h {z31.h}, p0/z, \[x0\]
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-+[^:]+: a4a0a800 ld1h {z0.h}, p2/z, \[x0\]
-+[^:]+: a4a0a800 ld1h {z0.h}, p2/z, \[x0\]
-+[^:]+: a4a0a800 ld1h {z0.h}, p2/z, \[x0\]
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-+[^:]+: a4a0bc00 ld1h {z0.h}, p7/z, \[x0\]
-+[^:]+: a4a0bc00 ld1h {z0.h}, p7/z, \[x0\]
-+[^:]+: a4a0bc00 ld1h {z0.h}, p7/z, \[x0\]
-+[^:]+: a4a0a060 ld1h {z0.h}, p0/z, \[x3\]
-+[^:]+: a4a0a060 ld1h {z0.h}, p0/z, \[x3\]
-+[^:]+: a4a0a060 ld1h {z0.h}, p0/z, \[x3\]
-+[^:]+: a4a0a060 ld1h {z0.h}, p0/z, \[x3\]
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-+[^:]+: a4a0a3e0 ld1h {z0.h}, p0/z, \[sp\]
-+[^:]+: a4a0a3e0 ld1h {z0.h}, p0/z, \[sp\]
-+[^:]+: a4a0a3e0 ld1h {z0.h}, p0/z, \[sp\]
-+[^:]+: a4a7a000 ld1h {z0.h}, p0/z, \[x0, #7, mul vl\]
-+[^:]+: a4a7a000 ld1h {z0.h}, p0/z, \[x0, #7, mul vl\]
-+[^:]+: a4a8a000 ld1h {z0.h}, p0/z, \[x0, #-8, mul vl\]
-+[^:]+: a4a8a000 ld1h {z0.h}, p0/z, \[x0, #-8, mul vl\]
-+[^:]+: a4a9a000 ld1h {z0.h}, p0/z, \[x0, #-7, mul vl\]
-+[^:]+: a4a9a000 ld1h {z0.h}, p0/z, \[x0, #-7, mul vl\]
-+[^:]+: a4afa000 ld1h {z0.h}, p0/z, \[x0, #-1, mul vl\]
-+[^:]+: a4afa000 ld1h {z0.h}, p0/z, \[x0, #-1, mul vl\]
-+[^:]+: a4c0a000 ld1h {z0.s}, p0/z, \[x0\]
-+[^:]+: a4c0a000 ld1h {z0.s}, p0/z, \[x0\]
-+[^:]+: a4c0a000 ld1h {z0.s}, p0/z, \[x0\]
-+[^:]+: a4c0a000 ld1h {z0.s}, p0/z, \[x0\]
-+[^:]+: a4c0a000 ld1h {z0.s}, p0/z, \[x0\]
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-+[^:]+: a4c0a001 ld1h {z1.s}, p0/z, \[x0\]
-+[^:]+: a4c0a001 ld1h {z1.s}, p0/z, \[x0\]
-+[^:]+: a4c0a001 ld1h {z1.s}, p0/z, \[x0\]
-+[^:]+: a4c0a001 ld1h {z1.s}, p0/z, \[x0\]
-+[^:]+: a4c0a01f ld1h {z31.s}, p0/z, \[x0\]
-+[^:]+: a4c0a01f ld1h {z31.s}, p0/z, \[x0\]
-+[^:]+: a4c0a01f ld1h {z31.s}, p0/z, \[x0\]
-+[^:]+: a4c0a01f ld1h {z31.s}, p0/z, \[x0\]
-+[^:]+: a4c0a01f ld1h {z31.s}, p0/z, \[x0\]
-+[^:]+: a4c0a800 ld1h {z0.s}, p2/z, \[x0\]
-+[^:]+: a4c0a800 ld1h {z0.s}, p2/z, \[x0\]
-+[^:]+: a4c0a800 ld1h {z0.s}, p2/z, \[x0\]
-+[^:]+: a4c0a800 ld1h {z0.s}, p2/z, \[x0\]
-+[^:]+: a4c0bc00 ld1h {z0.s}, p7/z, \[x0\]
-+[^:]+: a4c0bc00 ld1h {z0.s}, p7/z, \[x0\]
-+[^:]+: a4c0bc00 ld1h {z0.s}, p7/z, \[x0\]
-+[^:]+: a4c0bc00 ld1h {z0.s}, p7/z, \[x0\]
-+[^:]+: a4c0a060 ld1h {z0.s}, p0/z, \[x3\]
-+[^:]+: a4c0a060 ld1h {z0.s}, p0/z, \[x3\]
-+[^:]+: a4c0a060 ld1h {z0.s}, p0/z, \[x3\]
-+[^:]+: a4c0a060 ld1h {z0.s}, p0/z, \[x3\]
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-+[^:]+: a4c0a3e0 ld1h {z0.s}, p0/z, \[sp\]
-+[^:]+: a4c0a3e0 ld1h {z0.s}, p0/z, \[sp\]
-+[^:]+: a4c7a000 ld1h {z0.s}, p0/z, \[x0, #7, mul vl\]
-+[^:]+: a4c7a000 ld1h {z0.s}, p0/z, \[x0, #7, mul vl\]
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-+[^:]+: a4c8a000 ld1h {z0.s}, p0/z, \[x0, #-8, mul vl\]
-+[^:]+: a4c9a000 ld1h {z0.s}, p0/z, \[x0, #-7, mul vl\]
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-+[^:]+: a4cfa000 ld1h {z0.s}, p0/z, \[x0, #-1, mul vl\]
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-+[^:]+: a4e0a000 ld1h {z0.d}, p0/z, \[x0\]
-+[^:]+: a4e0a000 ld1h {z0.d}, p0/z, \[x0\]
-+[^:]+: a4e0a000 ld1h {z0.d}, p0/z, \[x0\]
-+[^:]+: a4e0a000 ld1h {z0.d}, p0/z, \[x0\]
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-+[^:]+: a4e0a001 ld1h {z1.d}, p0/z, \[x0\]
-+[^:]+: a4e0a001 ld1h {z1.d}, p0/z, \[x0\]
-+[^:]+: a4e0a001 ld1h {z1.d}, p0/z, \[x0\]
-+[^:]+: a4e0a001 ld1h {z1.d}, p0/z, \[x0\]
-+[^:]+: a4e0a01f ld1h {z31.d}, p0/z, \[x0\]
-+[^:]+: a4e0a01f ld1h {z31.d}, p0/z, \[x0\]
-+[^:]+: a4e0a01f ld1h {z31.d}, p0/z, \[x0\]
-+[^:]+: a4e0a01f ld1h {z31.d}, p0/z, \[x0\]
-+[^:]+: a4e0a01f ld1h {z31.d}, p0/z, \[x0\]
-+[^:]+: a4e0a800 ld1h {z0.d}, p2/z, \[x0\]
-+[^:]+: a4e0a800 ld1h {z0.d}, p2/z, \[x0\]
-+[^:]+: a4e0a800 ld1h {z0.d}, p2/z, \[x0\]
-+[^:]+: a4e0a800 ld1h {z0.d}, p2/z, \[x0\]
-+[^:]+: a4e0bc00 ld1h {z0.d}, p7/z, \[x0\]
-+[^:]+: a4e0bc00 ld1h {z0.d}, p7/z, \[x0\]
-+[^:]+: a4e0bc00 ld1h {z0.d}, p7/z, \[x0\]
-+[^:]+: a4e0bc00 ld1h {z0.d}, p7/z, \[x0\]
-+[^:]+: a4e0a060 ld1h {z0.d}, p0/z, \[x3\]
-+[^:]+: a4e0a060 ld1h {z0.d}, p0/z, \[x3\]
-+[^:]+: a4e0a060 ld1h {z0.d}, p0/z, \[x3\]
-+[^:]+: a4e0a060 ld1h {z0.d}, p0/z, \[x3\]
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-+[^:]+: a4e7a000 ld1h {z0.d}, p0/z, \[x0, #7, mul vl\]
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-+[^:]+: a4e9a000 ld1h {z0.d}, p0/z, \[x0, #-7, mul vl\]
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-+[^:]+: a4efa000 ld1h {z0.d}, p0/z, \[x0, #-1, mul vl\]
-+[^:]+: c4a0c000 ld1h {z0.d}, p0/z, \[z0.d\]
-+[^:]+: c4a0c000 ld1h {z0.d}, p0/z, \[z0.d\]
-+[^:]+: c4a0c000 ld1h {z0.d}, p0/z, \[z0.d\]
-+[^:]+: c4a0c000 ld1h {z0.d}, p0/z, \[z0.d\]
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-+[^:]+: c4a0c001 ld1h {z1.d}, p0/z, \[z0.d\]
-+[^:]+: c4a0c001 ld1h {z1.d}, p0/z, \[z0.d\]
-+[^:]+: c4a0c001 ld1h {z1.d}, p0/z, \[z0.d\]
-+[^:]+: c4a0c01f ld1h {z31.d}, p0/z, \[z0.d\]
-+[^:]+: c4a0c01f ld1h {z31.d}, p0/z, \[z0.d\]
-+[^:]+: c4a0c01f ld1h {z31.d}, p0/z, \[z0.d\]
-+[^:]+: c4a0c01f ld1h {z31.d}, p0/z, \[z0.d\]
-+[^:]+: c4a0c800 ld1h {z0.d}, p2/z, \[z0.d\]
-+[^:]+: c4a0c800 ld1h {z0.d}, p2/z, \[z0.d\]
-+[^:]+: c4a0c800 ld1h {z0.d}, p2/z, \[z0.d\]
-+[^:]+: c4a0dc00 ld1h {z0.d}, p7/z, \[z0.d\]
-+[^:]+: c4a0dc00 ld1h {z0.d}, p7/z, \[z0.d\]
-+[^:]+: c4a0dc00 ld1h {z0.d}, p7/z, \[z0.d\]
-+[^:]+: c4a0c060 ld1h {z0.d}, p0/z, \[z3.d\]
-+[^:]+: c4a0c060 ld1h {z0.d}, p0/z, \[z3.d\]
-+[^:]+: c4a0c060 ld1h {z0.d}, p0/z, \[z3.d\]
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-+[^:]+: c4a0c3e0 ld1h {z0.d}, p0/z, \[z31.d\]
-+[^:]+: c4a0c3e0 ld1h {z0.d}, p0/z, \[z31.d\]
-+[^:]+: c4afc000 ld1h {z0.d}, p0/z, \[z0.d, #30\]
-+[^:]+: c4afc000 ld1h {z0.d}, p0/z, \[z0.d, #30\]
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-+[^:]+: c4b0c000 ld1h {z0.d}, p0/z, \[z0.d, #32\]
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-+[^:]+: c4b1c000 ld1h {z0.d}, p0/z, \[z0.d, #34\]
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-+[^:]+: c4bfc000 ld1h {z0.d}, p0/z, \[z0.d, #62\]
-+[^:]+: 84408000 ld1rb {z0.b}, p0/z, \[x0\]
-+[^:]+: 84408000 ld1rb {z0.b}, p0/z, \[x0\]
-+[^:]+: 84408000 ld1rb {z0.b}, p0/z, \[x0\]
-+[^:]+: 84408000 ld1rb {z0.b}, p0/z, \[x0\]
-+[^:]+: 84408001 ld1rb {z1.b}, p0/z, \[x0\]
-+[^:]+: 84408001 ld1rb {z1.b}, p0/z, \[x0\]
-+[^:]+: 84408001 ld1rb {z1.b}, p0/z, \[x0\]
-+[^:]+: 84408001 ld1rb {z1.b}, p0/z, \[x0\]
-+[^:]+: 8440801f ld1rb {z31.b}, p0/z, \[x0\]
-+[^:]+: 8440801f ld1rb {z31.b}, p0/z, \[x0\]
-+[^:]+: 8440801f ld1rb {z31.b}, p0/z, \[x0\]
-+[^:]+: 8440801f ld1rb {z31.b}, p0/z, \[x0\]
-+[^:]+: 84408800 ld1rb {z0.b}, p2/z, \[x0\]
-+[^:]+: 84408800 ld1rb {z0.b}, p2/z, \[x0\]
-+[^:]+: 84408800 ld1rb {z0.b}, p2/z, \[x0\]
-+[^:]+: 84409c00 ld1rb {z0.b}, p7/z, \[x0\]
-+[^:]+: 84409c00 ld1rb {z0.b}, p7/z, \[x0\]
-+[^:]+: 84409c00 ld1rb {z0.b}, p7/z, \[x0\]
-+[^:]+: 84408060 ld1rb {z0.b}, p0/z, \[x3\]
-+[^:]+: 84408060 ld1rb {z0.b}, p0/z, \[x3\]
-+[^:]+: 84408060 ld1rb {z0.b}, p0/z, \[x3\]
-+[^:]+: 844083e0 ld1rb {z0.b}, p0/z, \[sp\]
-+[^:]+: 844083e0 ld1rb {z0.b}, p0/z, \[sp\]
-+[^:]+: 844083e0 ld1rb {z0.b}, p0/z, \[sp\]
-+[^:]+: 845f8000 ld1rb {z0.b}, p0/z, \[x0, #31\]
-+[^:]+: 845f8000 ld1rb {z0.b}, p0/z, \[x0, #31\]
-+[^:]+: 84608000 ld1rb {z0.b}, p0/z, \[x0, #32\]
-+[^:]+: 84608000 ld1rb {z0.b}, p0/z, \[x0, #32\]
-+[^:]+: 84618000 ld1rb {z0.b}, p0/z, \[x0, #33\]
-+[^:]+: 84618000 ld1rb {z0.b}, p0/z, \[x0, #33\]
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-+[^:]+: 847f8000 ld1rb {z0.b}, p0/z, \[x0, #63\]
-+[^:]+: 8440a000 ld1rb {z0.h}, p0/z, \[x0\]
-+[^:]+: 8440a000 ld1rb {z0.h}, p0/z, \[x0\]
-+[^:]+: 8440a000 ld1rb {z0.h}, p0/z, \[x0\]
-+[^:]+: 8440a000 ld1rb {z0.h}, p0/z, \[x0\]
-+[^:]+: 8440a001 ld1rb {z1.h}, p0/z, \[x0\]
-+[^:]+: 8440a001 ld1rb {z1.h}, p0/z, \[x0\]
-+[^:]+: 8440a001 ld1rb {z1.h}, p0/z, \[x0\]
-+[^:]+: 8440a001 ld1rb {z1.h}, p0/z, \[x0\]
-+[^:]+: 8440a01f ld1rb {z31.h}, p0/z, \[x0\]
-+[^:]+: 8440a01f ld1rb {z31.h}, p0/z, \[x0\]
-+[^:]+: 8440a01f ld1rb {z31.h}, p0/z, \[x0\]
-+[^:]+: 8440a01f ld1rb {z31.h}, p0/z, \[x0\]
-+[^:]+: 8440a800 ld1rb {z0.h}, p2/z, \[x0\]
-+[^:]+: 8440a800 ld1rb {z0.h}, p2/z, \[x0\]
-+[^:]+: 8440a800 ld1rb {z0.h}, p2/z, \[x0\]
-+[^:]+: 8440bc00 ld1rb {z0.h}, p7/z, \[x0\]
-+[^:]+: 8440bc00 ld1rb {z0.h}, p7/z, \[x0\]
-+[^:]+: 8440bc00 ld1rb {z0.h}, p7/z, \[x0\]
-+[^:]+: 8440a060 ld1rb {z0.h}, p0/z, \[x3\]
-+[^:]+: 8440a060 ld1rb {z0.h}, p0/z, \[x3\]
-+[^:]+: 8440a060 ld1rb {z0.h}, p0/z, \[x3\]
-+[^:]+: 8440a3e0 ld1rb {z0.h}, p0/z, \[sp\]
-+[^:]+: 8440a3e0 ld1rb {z0.h}, p0/z, \[sp\]
-+[^:]+: 8440a3e0 ld1rb {z0.h}, p0/z, \[sp\]
-+[^:]+: 845fa000 ld1rb {z0.h}, p0/z, \[x0, #31\]
-+[^:]+: 845fa000 ld1rb {z0.h}, p0/z, \[x0, #31\]
-+[^:]+: 8460a000 ld1rb {z0.h}, p0/z, \[x0, #32\]
-+[^:]+: 8460a000 ld1rb {z0.h}, p0/z, \[x0, #32\]
-+[^:]+: 8461a000 ld1rb {z0.h}, p0/z, \[x0, #33\]
-+[^:]+: 8461a000 ld1rb {z0.h}, p0/z, \[x0, #33\]
-+[^:]+: 847fa000 ld1rb {z0.h}, p0/z, \[x0, #63\]
-+[^:]+: 847fa000 ld1rb {z0.h}, p0/z, \[x0, #63\]
-+[^:]+: 8440c000 ld1rb {z0.s}, p0/z, \[x0\]
-+[^:]+: 8440c000 ld1rb {z0.s}, p0/z, \[x0\]
-+[^:]+: 8440c000 ld1rb {z0.s}, p0/z, \[x0\]
-+[^:]+: 8440c000 ld1rb {z0.s}, p0/z, \[x0\]
-+[^:]+: 8440c001 ld1rb {z1.s}, p0/z, \[x0\]
-+[^:]+: 8440c001 ld1rb {z1.s}, p0/z, \[x0\]
-+[^:]+: 8440c001 ld1rb {z1.s}, p0/z, \[x0\]
-+[^:]+: 8440c001 ld1rb {z1.s}, p0/z, \[x0\]
-+[^:]+: 8440c01f ld1rb {z31.s}, p0/z, \[x0\]
-+[^:]+: 8440c01f ld1rb {z31.s}, p0/z, \[x0\]
-+[^:]+: 8440c01f ld1rb {z31.s}, p0/z, \[x0\]
-+[^:]+: 8440c01f ld1rb {z31.s}, p0/z, \[x0\]
-+[^:]+: 8440c800 ld1rb {z0.s}, p2/z, \[x0\]
-+[^:]+: 8440c800 ld1rb {z0.s}, p2/z, \[x0\]
-+[^:]+: 8440c800 ld1rb {z0.s}, p2/z, \[x0\]
-+[^:]+: 8440dc00 ld1rb {z0.s}, p7/z, \[x0\]
-+[^:]+: 8440dc00 ld1rb {z0.s}, p7/z, \[x0\]
-+[^:]+: 8440dc00 ld1rb {z0.s}, p7/z, \[x0\]
-+[^:]+: 8440c060 ld1rb {z0.s}, p0/z, \[x3\]
-+[^:]+: 8440c060 ld1rb {z0.s}, p0/z, \[x3\]
-+[^:]+: 8440c060 ld1rb {z0.s}, p0/z, \[x3\]
-+[^:]+: 8440c3e0 ld1rb {z0.s}, p0/z, \[sp\]
-+[^:]+: 8440c3e0 ld1rb {z0.s}, p0/z, \[sp\]
-+[^:]+: 8440c3e0 ld1rb {z0.s}, p0/z, \[sp\]
-+[^:]+: 845fc000 ld1rb {z0.s}, p0/z, \[x0, #31\]
-+[^:]+: 845fc000 ld1rb {z0.s}, p0/z, \[x0, #31\]
-+[^:]+: 8460c000 ld1rb {z0.s}, p0/z, \[x0, #32\]
-+[^:]+: 8460c000 ld1rb {z0.s}, p0/z, \[x0, #32\]
-+[^:]+: 8461c000 ld1rb {z0.s}, p0/z, \[x0, #33\]
-+[^:]+: 8461c000 ld1rb {z0.s}, p0/z, \[x0, #33\]
-+[^:]+: 847fc000 ld1rb {z0.s}, p0/z, \[x0, #63\]
-+[^:]+: 847fc000 ld1rb {z0.s}, p0/z, \[x0, #63\]
-+[^:]+: 8440e000 ld1rb {z0.d}, p0/z, \[x0\]
-+[^:]+: 8440e000 ld1rb {z0.d}, p0/z, \[x0\]
-+[^:]+: 8440e000 ld1rb {z0.d}, p0/z, \[x0\]
-+[^:]+: 8440e000 ld1rb {z0.d}, p0/z, \[x0\]
-+[^:]+: 8440e001 ld1rb {z1.d}, p0/z, \[x0\]
-+[^:]+: 8440e001 ld1rb {z1.d}, p0/z, \[x0\]
-+[^:]+: 8440e001 ld1rb {z1.d}, p0/z, \[x0\]
-+[^:]+: 8440e001 ld1rb {z1.d}, p0/z, \[x0\]
-+[^:]+: 8440e01f ld1rb {z31.d}, p0/z, \[x0\]
-+[^:]+: 8440e01f ld1rb {z31.d}, p0/z, \[x0\]
-+[^:]+: 8440e01f ld1rb {z31.d}, p0/z, \[x0\]
-+[^:]+: 8440e01f ld1rb {z31.d}, p0/z, \[x0\]
-+[^:]+: 8440e800 ld1rb {z0.d}, p2/z, \[x0\]
-+[^:]+: 8440e800 ld1rb {z0.d}, p2/z, \[x0\]
-+[^:]+: 8440e800 ld1rb {z0.d}, p2/z, \[x0\]
-+[^:]+: 8440fc00 ld1rb {z0.d}, p7/z, \[x0\]
-+[^:]+: 8440fc00 ld1rb {z0.d}, p7/z, \[x0\]
-+[^:]+: 8440fc00 ld1rb {z0.d}, p7/z, \[x0\]
-+[^:]+: 8440e060 ld1rb {z0.d}, p0/z, \[x3\]
-+[^:]+: 8440e060 ld1rb {z0.d}, p0/z, \[x3\]
-+[^:]+: 8440e060 ld1rb {z0.d}, p0/z, \[x3\]
-+[^:]+: 8440e3e0 ld1rb {z0.d}, p0/z, \[sp\]
-+[^:]+: 8440e3e0 ld1rb {z0.d}, p0/z, \[sp\]
-+[^:]+: 8440e3e0 ld1rb {z0.d}, p0/z, \[sp\]
-+[^:]+: 845fe000 ld1rb {z0.d}, p0/z, \[x0, #31\]
-+[^:]+: 845fe000 ld1rb {z0.d}, p0/z, \[x0, #31\]
-+[^:]+: 8460e000 ld1rb {z0.d}, p0/z, \[x0, #32\]
-+[^:]+: 8460e000 ld1rb {z0.d}, p0/z, \[x0, #32\]
-+[^:]+: 8461e000 ld1rb {z0.d}, p0/z, \[x0, #33\]
-+[^:]+: 8461e000 ld1rb {z0.d}, p0/z, \[x0, #33\]
-+[^:]+: 847fe000 ld1rb {z0.d}, p0/z, \[x0, #63\]
-+[^:]+: 847fe000 ld1rb {z0.d}, p0/z, \[x0, #63\]
-+[^:]+: 85c0e000 ld1rd {z0.d}, p0/z, \[x0\]
-+[^:]+: 85c0e000 ld1rd {z0.d}, p0/z, \[x0\]
-+[^:]+: 85c0e000 ld1rd {z0.d}, p0/z, \[x0\]
-+[^:]+: 85c0e000 ld1rd {z0.d}, p0/z, \[x0\]
-+[^:]+: 85c0e001 ld1rd {z1.d}, p0/z, \[x0\]
-+[^:]+: 85c0e001 ld1rd {z1.d}, p0/z, \[x0\]
-+[^:]+: 85c0e001 ld1rd {z1.d}, p0/z, \[x0\]
-+[^:]+: 85c0e001 ld1rd {z1.d}, p0/z, \[x0\]
-+[^:]+: 85c0e01f ld1rd {z31.d}, p0/z, \[x0\]
-+[^:]+: 85c0e01f ld1rd {z31.d}, p0/z, \[x0\]
-+[^:]+: 85c0e01f ld1rd {z31.d}, p0/z, \[x0\]
-+[^:]+: 85c0e01f ld1rd {z31.d}, p0/z, \[x0\]
-+[^:]+: 85c0e800 ld1rd {z0.d}, p2/z, \[x0\]
-+[^:]+: 85c0e800 ld1rd {z0.d}, p2/z, \[x0\]
-+[^:]+: 85c0e800 ld1rd {z0.d}, p2/z, \[x0\]
-+[^:]+: 85c0fc00 ld1rd {z0.d}, p7/z, \[x0\]
-+[^:]+: 85c0fc00 ld1rd {z0.d}, p7/z, \[x0\]
-+[^:]+: 85c0fc00 ld1rd {z0.d}, p7/z, \[x0\]
-+[^:]+: 85c0e060 ld1rd {z0.d}, p0/z, \[x3\]
-+[^:]+: 85c0e060 ld1rd {z0.d}, p0/z, \[x3\]
-+[^:]+: 85c0e060 ld1rd {z0.d}, p0/z, \[x3\]
-+[^:]+: 85c0e3e0 ld1rd {z0.d}, p0/z, \[sp\]
-+[^:]+: 85c0e3e0 ld1rd {z0.d}, p0/z, \[sp\]
-+[^:]+: 85c0e3e0 ld1rd {z0.d}, p0/z, \[sp\]
-+[^:]+: 85dfe000 ld1rd {z0.d}, p0/z, \[x0, #248\]
-+[^:]+: 85dfe000 ld1rd {z0.d}, p0/z, \[x0, #248\]
-+[^:]+: 85e0e000 ld1rd {z0.d}, p0/z, \[x0, #256\]
-+[^:]+: 85e0e000 ld1rd {z0.d}, p0/z, \[x0, #256\]
-+[^:]+: 85e1e000 ld1rd {z0.d}, p0/z, \[x0, #264\]
-+[^:]+: 85e1e000 ld1rd {z0.d}, p0/z, \[x0, #264\]
-+[^:]+: 85ffe000 ld1rd {z0.d}, p0/z, \[x0, #504\]
-+[^:]+: 85ffe000 ld1rd {z0.d}, p0/z, \[x0, #504\]
-+[^:]+: 84c0a000 ld1rh {z0.h}, p0/z, \[x0\]
-+[^:]+: 84c0a000 ld1rh {z0.h}, p0/z, \[x0\]
-+[^:]+: 84c0a000 ld1rh {z0.h}, p0/z, \[x0\]
-+[^:]+: 84c0a000 ld1rh {z0.h}, p0/z, \[x0\]
-+[^:]+: 84c0a001 ld1rh {z1.h}, p0/z, \[x0\]
-+[^:]+: 84c0a001 ld1rh {z1.h}, p0/z, \[x0\]
-+[^:]+: 84c0a001 ld1rh {z1.h}, p0/z, \[x0\]
-+[^:]+: 84c0a001 ld1rh {z1.h}, p0/z, \[x0\]
-+[^:]+: 84c0a01f ld1rh {z31.h}, p0/z, \[x0\]
-+[^:]+: 84c0a01f ld1rh {z31.h}, p0/z, \[x0\]
-+[^:]+: 84c0a01f ld1rh {z31.h}, p0/z, \[x0\]
-+[^:]+: 84c0a01f ld1rh {z31.h}, p0/z, \[x0\]
-+[^:]+: 84c0a800 ld1rh {z0.h}, p2/z, \[x0\]
-+[^:]+: 84c0a800 ld1rh {z0.h}, p2/z, \[x0\]
-+[^:]+: 84c0a800 ld1rh {z0.h}, p2/z, \[x0\]
-+[^:]+: 84c0bc00 ld1rh {z0.h}, p7/z, \[x0\]
-+[^:]+: 84c0bc00 ld1rh {z0.h}, p7/z, \[x0\]
-+[^:]+: 84c0bc00 ld1rh {z0.h}, p7/z, \[x0\]
-+[^:]+: 84c0a060 ld1rh {z0.h}, p0/z, \[x3\]
-+[^:]+: 84c0a060 ld1rh {z0.h}, p0/z, \[x3\]
-+[^:]+: 84c0a060 ld1rh {z0.h}, p0/z, \[x3\]
-+[^:]+: 84c0a3e0 ld1rh {z0.h}, p0/z, \[sp\]
-+[^:]+: 84c0a3e0 ld1rh {z0.h}, p0/z, \[sp\]
-+[^:]+: 84c0a3e0 ld1rh {z0.h}, p0/z, \[sp\]
-+[^:]+: 84dfa000 ld1rh {z0.h}, p0/z, \[x0, #62\]
-+[^:]+: 84dfa000 ld1rh {z0.h}, p0/z, \[x0, #62\]
-+[^:]+: 84e0a000 ld1rh {z0.h}, p0/z, \[x0, #64\]
-+[^:]+: 84e0a000 ld1rh {z0.h}, p0/z, \[x0, #64\]
-+[^:]+: 84e1a000 ld1rh {z0.h}, p0/z, \[x0, #66\]
-+[^:]+: 84e1a000 ld1rh {z0.h}, p0/z, \[x0, #66\]
-+[^:]+: 84ffa000 ld1rh {z0.h}, p0/z, \[x0, #126\]
-+[^:]+: 84ffa000 ld1rh {z0.h}, p0/z, \[x0, #126\]
-+[^:]+: 84c0c000 ld1rh {z0.s}, p0/z, \[x0\]
-+[^:]+: 84c0c000 ld1rh {z0.s}, p0/z, \[x0\]
-+[^:]+: 84c0c000 ld1rh {z0.s}, p0/z, \[x0\]
-+[^:]+: 84c0c000 ld1rh {z0.s}, p0/z, \[x0\]
-+[^:]+: 84c0c001 ld1rh {z1.s}, p0/z, \[x0\]
-+[^:]+: 84c0c001 ld1rh {z1.s}, p0/z, \[x0\]
-+[^:]+: 84c0c001 ld1rh {z1.s}, p0/z, \[x0\]
-+[^:]+: 84c0c001 ld1rh {z1.s}, p0/z, \[x0\]
-+[^:]+: 84c0c01f ld1rh {z31.s}, p0/z, \[x0\]
-+[^:]+: 84c0c01f ld1rh {z31.s}, p0/z, \[x0\]
-+[^:]+: 84c0c01f ld1rh {z31.s}, p0/z, \[x0\]
-+[^:]+: 84c0c01f ld1rh {z31.s}, p0/z, \[x0\]
-+[^:]+: 84c0c800 ld1rh {z0.s}, p2/z, \[x0\]
-+[^:]+: 84c0c800 ld1rh {z0.s}, p2/z, \[x0\]
-+[^:]+: 84c0c800 ld1rh {z0.s}, p2/z, \[x0\]
-+[^:]+: 84c0dc00 ld1rh {z0.s}, p7/z, \[x0\]
-+[^:]+: 84c0dc00 ld1rh {z0.s}, p7/z, \[x0\]
-+[^:]+: 84c0dc00 ld1rh {z0.s}, p7/z, \[x0\]
-+[^:]+: 84c0c060 ld1rh {z0.s}, p0/z, \[x3\]
-+[^:]+: 84c0c060 ld1rh {z0.s}, p0/z, \[x3\]
-+[^:]+: 84c0c060 ld1rh {z0.s}, p0/z, \[x3\]
-+[^:]+: 84c0c3e0 ld1rh {z0.s}, p0/z, \[sp\]
-+[^:]+: 84c0c3e0 ld1rh {z0.s}, p0/z, \[sp\]
-+[^:]+: 84c0c3e0 ld1rh {z0.s}, p0/z, \[sp\]
-+[^:]+: 84dfc000 ld1rh {z0.s}, p0/z, \[x0, #62\]
-+[^:]+: 84dfc000 ld1rh {z0.s}, p0/z, \[x0, #62\]
-+[^:]+: 84e0c000 ld1rh {z0.s}, p0/z, \[x0, #64\]
-+[^:]+: 84e0c000 ld1rh {z0.s}, p0/z, \[x0, #64\]
-+[^:]+: 84e1c000 ld1rh {z0.s}, p0/z, \[x0, #66\]
-+[^:]+: 84e1c000 ld1rh {z0.s}, p0/z, \[x0, #66\]
-+[^:]+: 84ffc000 ld1rh {z0.s}, p0/z, \[x0, #126\]
-+[^:]+: 84ffc000 ld1rh {z0.s}, p0/z, \[x0, #126\]
-+[^:]+: 84c0e000 ld1rh {z0.d}, p0/z, \[x0\]
-+[^:]+: 84c0e000 ld1rh {z0.d}, p0/z, \[x0\]
-+[^:]+: 84c0e000 ld1rh {z0.d}, p0/z, \[x0\]
-+[^:]+: 84c0e000 ld1rh {z0.d}, p0/z, \[x0\]
-+[^:]+: 84c0e001 ld1rh {z1.d}, p0/z, \[x0\]
-+[^:]+: 84c0e001 ld1rh {z1.d}, p0/z, \[x0\]
-+[^:]+: 84c0e001 ld1rh {z1.d}, p0/z, \[x0\]
-+[^:]+: 84c0e001 ld1rh {z1.d}, p0/z, \[x0\]
-+[^:]+: 84c0e01f ld1rh {z31.d}, p0/z, \[x0\]
-+[^:]+: 84c0e01f ld1rh {z31.d}, p0/z, \[x0\]
-+[^:]+: 84c0e01f ld1rh {z31.d}, p0/z, \[x0\]
-+[^:]+: 84c0e01f ld1rh {z31.d}, p0/z, \[x0\]
-+[^:]+: 84c0e800 ld1rh {z0.d}, p2/z, \[x0\]
-+[^:]+: 84c0e800 ld1rh {z0.d}, p2/z, \[x0\]
-+[^:]+: 84c0e800 ld1rh {z0.d}, p2/z, \[x0\]
-+[^:]+: 84c0fc00 ld1rh {z0.d}, p7/z, \[x0\]
-+[^:]+: 84c0fc00 ld1rh {z0.d}, p7/z, \[x0\]
-+[^:]+: 84c0fc00 ld1rh {z0.d}, p7/z, \[x0\]
-+[^:]+: 84c0e060 ld1rh {z0.d}, p0/z, \[x3\]
-+[^:]+: 84c0e060 ld1rh {z0.d}, p0/z, \[x3\]
-+[^:]+: 84c0e060 ld1rh {z0.d}, p0/z, \[x3\]
-+[^:]+: 84c0e3e0 ld1rh {z0.d}, p0/z, \[sp\]
-+[^:]+: 84c0e3e0 ld1rh {z0.d}, p0/z, \[sp\]
-+[^:]+: 84c0e3e0 ld1rh {z0.d}, p0/z, \[sp\]
-+[^:]+: 84dfe000 ld1rh {z0.d}, p0/z, \[x0, #62\]
-+[^:]+: 84dfe000 ld1rh {z0.d}, p0/z, \[x0, #62\]
-+[^:]+: 84e0e000 ld1rh {z0.d}, p0/z, \[x0, #64\]
-+[^:]+: 84e0e000 ld1rh {z0.d}, p0/z, \[x0, #64\]
-+[^:]+: 84e1e000 ld1rh {z0.d}, p0/z, \[x0, #66\]
-+[^:]+: 84e1e000 ld1rh {z0.d}, p0/z, \[x0, #66\]
-+[^:]+: 84ffe000 ld1rh {z0.d}, p0/z, \[x0, #126\]
-+[^:]+: 84ffe000 ld1rh {z0.d}, p0/z, \[x0, #126\]
-+[^:]+: 85c08000 ld1rsb {z0.d}, p0/z, \[x0\]
-+[^:]+: 85c08000 ld1rsb {z0.d}, p0/z, \[x0\]
-+[^:]+: 85c08000 ld1rsb {z0.d}, p0/z, \[x0\]
-+[^:]+: 85c08000 ld1rsb {z0.d}, p0/z, \[x0\]
-+[^:]+: 85c08001 ld1rsb {z1.d}, p0/z, \[x0\]
-+[^:]+: 85c08001 ld1rsb {z1.d}, p0/z, \[x0\]
-+[^:]+: 85c08001 ld1rsb {z1.d}, p0/z, \[x0\]
-+[^:]+: 85c08001 ld1rsb {z1.d}, p0/z, \[x0\]
-+[^:]+: 85c0801f ld1rsb {z31.d}, p0/z, \[x0\]
-+[^:]+: 85c0801f ld1rsb {z31.d}, p0/z, \[x0\]
-+[^:]+: 85c0801f ld1rsb {z31.d}, p0/z, \[x0\]
-+[^:]+: 85c0801f ld1rsb {z31.d}, p0/z, \[x0\]
-+[^:]+: 85c08800 ld1rsb {z0.d}, p2/z, \[x0\]
-+[^:]+: 85c08800 ld1rsb {z0.d}, p2/z, \[x0\]
-+[^:]+: 85c08800 ld1rsb {z0.d}, p2/z, \[x0\]
-+[^:]+: 85c09c00 ld1rsb {z0.d}, p7/z, \[x0\]
-+[^:]+: 85c09c00 ld1rsb {z0.d}, p7/z, \[x0\]
-+[^:]+: 85c09c00 ld1rsb {z0.d}, p7/z, \[x0\]
-+[^:]+: 85c08060 ld1rsb {z0.d}, p0/z, \[x3\]
-+[^:]+: 85c08060 ld1rsb {z0.d}, p0/z, \[x3\]
-+[^:]+: 85c08060 ld1rsb {z0.d}, p0/z, \[x3\]
-+[^:]+: 85c083e0 ld1rsb {z0.d}, p0/z, \[sp\]
-+[^:]+: 85c083e0 ld1rsb {z0.d}, p0/z, \[sp\]
-+[^:]+: 85c083e0 ld1rsb {z0.d}, p0/z, \[sp\]
-+[^:]+: 85df8000 ld1rsb {z0.d}, p0/z, \[x0, #31\]
-+[^:]+: 85df8000 ld1rsb {z0.d}, p0/z, \[x0, #31\]
-+[^:]+: 85e08000 ld1rsb {z0.d}, p0/z, \[x0, #32\]
-+[^:]+: 85e08000 ld1rsb {z0.d}, p0/z, \[x0, #32\]
-+[^:]+: 85e18000 ld1rsb {z0.d}, p0/z, \[x0, #33\]
-+[^:]+: 85e18000 ld1rsb {z0.d}, p0/z, \[x0, #33\]
-+[^:]+: 85ff8000 ld1rsb {z0.d}, p0/z, \[x0, #63\]
-+[^:]+: 85ff8000 ld1rsb {z0.d}, p0/z, \[x0, #63\]
-+[^:]+: 85c0a000 ld1rsb {z0.s}, p0/z, \[x0\]
-+[^:]+: 85c0a000 ld1rsb {z0.s}, p0/z, \[x0\]
-+[^:]+: 85c0a000 ld1rsb {z0.s}, p0/z, \[x0\]
-+[^:]+: 85c0a000 ld1rsb {z0.s}, p0/z, \[x0\]
-+[^:]+: 85c0a001 ld1rsb {z1.s}, p0/z, \[x0\]
-+[^:]+: 85c0a001 ld1rsb {z1.s}, p0/z, \[x0\]
-+[^:]+: 85c0a001 ld1rsb {z1.s}, p0/z, \[x0\]
-+[^:]+: 85c0a001 ld1rsb {z1.s}, p0/z, \[x0\]
-+[^:]+: 85c0a01f ld1rsb {z31.s}, p0/z, \[x0\]
-+[^:]+: 85c0a01f ld1rsb {z31.s}, p0/z, \[x0\]
-+[^:]+: 85c0a01f ld1rsb {z31.s}, p0/z, \[x0\]
-+[^:]+: 85c0a01f ld1rsb {z31.s}, p0/z, \[x0\]
-+[^:]+: 85c0a800 ld1rsb {z0.s}, p2/z, \[x0\]
-+[^:]+: 85c0a800 ld1rsb {z0.s}, p2/z, \[x0\]
-+[^:]+: 85c0a800 ld1rsb {z0.s}, p2/z, \[x0\]
-+[^:]+: 85c0bc00 ld1rsb {z0.s}, p7/z, \[x0\]
-+[^:]+: 85c0bc00 ld1rsb {z0.s}, p7/z, \[x0\]
-+[^:]+: 85c0bc00 ld1rsb {z0.s}, p7/z, \[x0\]
-+[^:]+: 85c0a060 ld1rsb {z0.s}, p0/z, \[x3\]
-+[^:]+: 85c0a060 ld1rsb {z0.s}, p0/z, \[x3\]
-+[^:]+: 85c0a060 ld1rsb {z0.s}, p0/z, \[x3\]
-+[^:]+: 85c0a3e0 ld1rsb {z0.s}, p0/z, \[sp\]
-+[^:]+: 85c0a3e0 ld1rsb {z0.s}, p0/z, \[sp\]
-+[^:]+: 85c0a3e0 ld1rsb {z0.s}, p0/z, \[sp\]
-+[^:]+: 85dfa000 ld1rsb {z0.s}, p0/z, \[x0, #31\]
-+[^:]+: 85dfa000 ld1rsb {z0.s}, p0/z, \[x0, #31\]
-+[^:]+: 85e0a000 ld1rsb {z0.s}, p0/z, \[x0, #32\]
-+[^:]+: 85e0a000 ld1rsb {z0.s}, p0/z, \[x0, #32\]
-+[^:]+: 85e1a000 ld1rsb {z0.s}, p0/z, \[x0, #33\]
-+[^:]+: 85e1a000 ld1rsb {z0.s}, p0/z, \[x0, #33\]
-+[^:]+: 85ffa000 ld1rsb {z0.s}, p0/z, \[x0, #63\]
-+[^:]+: 85ffa000 ld1rsb {z0.s}, p0/z, \[x0, #63\]
-+[^:]+: 85c0c000 ld1rsb {z0.h}, p0/z, \[x0\]
-+[^:]+: 85c0c000 ld1rsb {z0.h}, p0/z, \[x0\]
-+[^:]+: 85c0c000 ld1rsb {z0.h}, p0/z, \[x0\]
-+[^:]+: 85c0c000 ld1rsb {z0.h}, p0/z, \[x0\]
-+[^:]+: 85c0c001 ld1rsb {z1.h}, p0/z, \[x0\]
-+[^:]+: 85c0c001 ld1rsb {z1.h}, p0/z, \[x0\]
-+[^:]+: 85c0c001 ld1rsb {z1.h}, p0/z, \[x0\]
-+[^:]+: 85c0c001 ld1rsb {z1.h}, p0/z, \[x0\]
-+[^:]+: 85c0c01f ld1rsb {z31.h}, p0/z, \[x0\]
-+[^:]+: 85c0c01f ld1rsb {z31.h}, p0/z, \[x0\]
-+[^:]+: 85c0c01f ld1rsb {z31.h}, p0/z, \[x0\]
-+[^:]+: 85c0c01f ld1rsb {z31.h}, p0/z, \[x0\]
-+[^:]+: 85c0c800 ld1rsb {z0.h}, p2/z, \[x0\]
-+[^:]+: 85c0c800 ld1rsb {z0.h}, p2/z, \[x0\]
-+[^:]+: 85c0c800 ld1rsb {z0.h}, p2/z, \[x0\]
-+[^:]+: 85c0dc00 ld1rsb {z0.h}, p7/z, \[x0\]
-+[^:]+: 85c0dc00 ld1rsb {z0.h}, p7/z, \[x0\]
-+[^:]+: 85c0dc00 ld1rsb {z0.h}, p7/z, \[x0\]
-+[^:]+: 85c0c060 ld1rsb {z0.h}, p0/z, \[x3\]
-+[^:]+: 85c0c060 ld1rsb {z0.h}, p0/z, \[x3\]
-+[^:]+: 85c0c060 ld1rsb {z0.h}, p0/z, \[x3\]
-+[^:]+: 85c0c3e0 ld1rsb {z0.h}, p0/z, \[sp\]
-+[^:]+: 85c0c3e0 ld1rsb {z0.h}, p0/z, \[sp\]
-+[^:]+: 85c0c3e0 ld1rsb {z0.h}, p0/z, \[sp\]
-+[^:]+: 85dfc000 ld1rsb {z0.h}, p0/z, \[x0, #31\]
-+[^:]+: 85dfc000 ld1rsb {z0.h}, p0/z, \[x0, #31\]
-+[^:]+: 85e0c000 ld1rsb {z0.h}, p0/z, \[x0, #32\]
-+[^:]+: 85e0c000 ld1rsb {z0.h}, p0/z, \[x0, #32\]
-+[^:]+: 85e1c000 ld1rsb {z0.h}, p0/z, \[x0, #33\]
-+[^:]+: 85e1c000 ld1rsb {z0.h}, p0/z, \[x0, #33\]
-+[^:]+: 85ffc000 ld1rsb {z0.h}, p0/z, \[x0, #63\]
-+[^:]+: 85ffc000 ld1rsb {z0.h}, p0/z, \[x0, #63\]
-+[^:]+: 85408000 ld1rsh {z0.d}, p0/z, \[x0\]
-+[^:]+: 85408000 ld1rsh {z0.d}, p0/z, \[x0\]
-+[^:]+: 85408000 ld1rsh {z0.d}, p0/z, \[x0\]
-+[^:]+: 85408000 ld1rsh {z0.d}, p0/z, \[x0\]
-+[^:]+: 85408001 ld1rsh {z1.d}, p0/z, \[x0\]
-+[^:]+: 85408001 ld1rsh {z1.d}, p0/z, \[x0\]
-+[^:]+: 85408001 ld1rsh {z1.d}, p0/z, \[x0\]
-+[^:]+: 85408001 ld1rsh {z1.d}, p0/z, \[x0\]
-+[^:]+: 8540801f ld1rsh {z31.d}, p0/z, \[x0\]
-+[^:]+: 8540801f ld1rsh {z31.d}, p0/z, \[x0\]
-+[^:]+: 8540801f ld1rsh {z31.d}, p0/z, \[x0\]
-+[^:]+: 8540801f ld1rsh {z31.d}, p0/z, \[x0\]
-+[^:]+: 85408800 ld1rsh {z0.d}, p2/z, \[x0\]
-+[^:]+: 85408800 ld1rsh {z0.d}, p2/z, \[x0\]
-+[^:]+: 85408800 ld1rsh {z0.d}, p2/z, \[x0\]
-+[^:]+: 85409c00 ld1rsh {z0.d}, p7/z, \[x0\]
-+[^:]+: 85409c00 ld1rsh {z0.d}, p7/z, \[x0\]
-+[^:]+: 85409c00 ld1rsh {z0.d}, p7/z, \[x0\]
-+[^:]+: 85408060 ld1rsh {z0.d}, p0/z, \[x3\]
-+[^:]+: 85408060 ld1rsh {z0.d}, p0/z, \[x3\]
-+[^:]+: 85408060 ld1rsh {z0.d}, p0/z, \[x3\]
-+[^:]+: 854083e0 ld1rsh {z0.d}, p0/z, \[sp\]
-+[^:]+: 854083e0 ld1rsh {z0.d}, p0/z, \[sp\]
-+[^:]+: 854083e0 ld1rsh {z0.d}, p0/z, \[sp\]
-+[^:]+: 855f8000 ld1rsh {z0.d}, p0/z, \[x0, #62\]
-+[^:]+: 855f8000 ld1rsh {z0.d}, p0/z, \[x0, #62\]
-+[^:]+: 85608000 ld1rsh {z0.d}, p0/z, \[x0, #64\]
-+[^:]+: 85608000 ld1rsh {z0.d}, p0/z, \[x0, #64\]
-+[^:]+: 85618000 ld1rsh {z0.d}, p0/z, \[x0, #66\]
-+[^:]+: 85618000 ld1rsh {z0.d}, p0/z, \[x0, #66\]
-+[^:]+: 857f8000 ld1rsh {z0.d}, p0/z, \[x0, #126\]
-+[^:]+: 857f8000 ld1rsh {z0.d}, p0/z, \[x0, #126\]
-+[^:]+: 8540a000 ld1rsh {z0.s}, p0/z, \[x0\]
-+[^:]+: 8540a000 ld1rsh {z0.s}, p0/z, \[x0\]
-+[^:]+: 8540a000 ld1rsh {z0.s}, p0/z, \[x0\]
-+[^:]+: 8540a000 ld1rsh {z0.s}, p0/z, \[x0\]
-+[^:]+: 8540a001 ld1rsh {z1.s}, p0/z, \[x0\]
-+[^:]+: 8540a001 ld1rsh {z1.s}, p0/z, \[x0\]
-+[^:]+: 8540a001 ld1rsh {z1.s}, p0/z, \[x0\]
-+[^:]+: 8540a001 ld1rsh {z1.s}, p0/z, \[x0\]
-+[^:]+: 8540a01f ld1rsh {z31.s}, p0/z, \[x0\]
-+[^:]+: 8540a01f ld1rsh {z31.s}, p0/z, \[x0\]
-+[^:]+: 8540a01f ld1rsh {z31.s}, p0/z, \[x0\]
-+[^:]+: 8540a01f ld1rsh {z31.s}, p0/z, \[x0\]
-+[^:]+: 8540a800 ld1rsh {z0.s}, p2/z, \[x0\]
-+[^:]+: 8540a800 ld1rsh {z0.s}, p2/z, \[x0\]
-+[^:]+: 8540a800 ld1rsh {z0.s}, p2/z, \[x0\]
-+[^:]+: 8540bc00 ld1rsh {z0.s}, p7/z, \[x0\]
-+[^:]+: 8540bc00 ld1rsh {z0.s}, p7/z, \[x0\]
-+[^:]+: 8540bc00 ld1rsh {z0.s}, p7/z, \[x0\]
-+[^:]+: 8540a060 ld1rsh {z0.s}, p0/z, \[x3\]
-+[^:]+: 8540a060 ld1rsh {z0.s}, p0/z, \[x3\]
-+[^:]+: 8540a060 ld1rsh {z0.s}, p0/z, \[x3\]
-+[^:]+: 8540a3e0 ld1rsh {z0.s}, p0/z, \[sp\]
-+[^:]+: 8540a3e0 ld1rsh {z0.s}, p0/z, \[sp\]
-+[^:]+: 8540a3e0 ld1rsh {z0.s}, p0/z, \[sp\]
-+[^:]+: 855fa000 ld1rsh {z0.s}, p0/z, \[x0, #62\]
-+[^:]+: 855fa000 ld1rsh {z0.s}, p0/z, \[x0, #62\]
-+[^:]+: 8560a000 ld1rsh {z0.s}, p0/z, \[x0, #64\]
-+[^:]+: 8560a000 ld1rsh {z0.s}, p0/z, \[x0, #64\]
-+[^:]+: 8561a000 ld1rsh {z0.s}, p0/z, \[x0, #66\]
-+[^:]+: 8561a000 ld1rsh {z0.s}, p0/z, \[x0, #66\]
-+[^:]+: 857fa000 ld1rsh {z0.s}, p0/z, \[x0, #126\]
-+[^:]+: 857fa000 ld1rsh {z0.s}, p0/z, \[x0, #126\]
-+[^:]+: 84c08000 ld1rsw {z0.d}, p0/z, \[x0\]
-+[^:]+: 84c08000 ld1rsw {z0.d}, p0/z, \[x0\]
-+[^:]+: 84c08000 ld1rsw {z0.d}, p0/z, \[x0\]
-+[^:]+: 84c08000 ld1rsw {z0.d}, p0/z, \[x0\]
-+[^:]+: 84c08001 ld1rsw {z1.d}, p0/z, \[x0\]
-+[^:]+: 84c08001 ld1rsw {z1.d}, p0/z, \[x0\]
-+[^:]+: 84c08001 ld1rsw {z1.d}, p0/z, \[x0\]
-+[^:]+: 84c08001 ld1rsw {z1.d}, p0/z, \[x0\]
-+[^:]+: 84c0801f ld1rsw {z31.d}, p0/z, \[x0\]
-+[^:]+: 84c0801f ld1rsw {z31.d}, p0/z, \[x0\]
-+[^:]+: 84c0801f ld1rsw {z31.d}, p0/z, \[x0\]
-+[^:]+: 84c0801f ld1rsw {z31.d}, p0/z, \[x0\]
-+[^:]+: 84c08800 ld1rsw {z0.d}, p2/z, \[x0\]
-+[^:]+: 84c08800 ld1rsw {z0.d}, p2/z, \[x0\]
-+[^:]+: 84c08800 ld1rsw {z0.d}, p2/z, \[x0\]
-+[^:]+: 84c09c00 ld1rsw {z0.d}, p7/z, \[x0\]
-+[^:]+: 84c09c00 ld1rsw {z0.d}, p7/z, \[x0\]
-+[^:]+: 84c09c00 ld1rsw {z0.d}, p7/z, \[x0\]
-+[^:]+: 84c08060 ld1rsw {z0.d}, p0/z, \[x3\]
-+[^:]+: 84c08060 ld1rsw {z0.d}, p0/z, \[x3\]
-+[^:]+: 84c08060 ld1rsw {z0.d}, p0/z, \[x3\]
-+[^:]+: 84c083e0 ld1rsw {z0.d}, p0/z, \[sp\]
-+[^:]+: 84c083e0 ld1rsw {z0.d}, p0/z, \[sp\]
-+[^:]+: 84c083e0 ld1rsw {z0.d}, p0/z, \[sp\]
-+[^:]+: 84df8000 ld1rsw {z0.d}, p0/z, \[x0, #124\]
-+[^:]+: 84df8000 ld1rsw {z0.d}, p0/z, \[x0, #124\]
-+[^:]+: 84e08000 ld1rsw {z0.d}, p0/z, \[x0, #128\]
-+[^:]+: 84e08000 ld1rsw {z0.d}, p0/z, \[x0, #128\]
-+[^:]+: 84e18000 ld1rsw {z0.d}, p0/z, \[x0, #132\]
-+[^:]+: 84e18000 ld1rsw {z0.d}, p0/z, \[x0, #132\]
-+[^:]+: 84ff8000 ld1rsw {z0.d}, p0/z, \[x0, #252\]
-+[^:]+: 84ff8000 ld1rsw {z0.d}, p0/z, \[x0, #252\]
-+[^:]+: a4002000 ld1rqb {z0.b}, p0/z, \[x0\]
-+[^:]+: a4002000 ld1rqb {z0.b}, p0/z, \[x0\]
-+[^:]+: a4002000 ld1rqb {z0.b}, p0/z, \[x0\]
-+[^:]+: a4002000 ld1rqb {z0.b}, p0/z, \[x0\]
-+[^:]+: a4002001 ld1rqb {z1.b}, p0/z, \[x0\]
-+[^:]+: a4002001 ld1rqb {z1.b}, p0/z, \[x0\]
-+[^:]+: a4002001 ld1rqb {z1.b}, p0/z, \[x0\]
-+[^:]+: a4002001 ld1rqb {z1.b}, p0/z, \[x0\]
-+[^:]+: a400201f ld1rqb {z31.b}, p0/z, \[x0\]
-+[^:]+: a400201f ld1rqb {z31.b}, p0/z, \[x0\]
-+[^:]+: a400201f ld1rqb {z31.b}, p0/z, \[x0\]
-+[^:]+: a400201f ld1rqb {z31.b}, p0/z, \[x0\]
-+[^:]+: a4002800 ld1rqb {z0.b}, p2/z, \[x0\]
-+[^:]+: a4002800 ld1rqb {z0.b}, p2/z, \[x0\]
-+[^:]+: a4002800 ld1rqb {z0.b}, p2/z, \[x0\]
-+[^:]+: a4003c00 ld1rqb {z0.b}, p7/z, \[x0\]
-+[^:]+: a4003c00 ld1rqb {z0.b}, p7/z, \[x0\]
-+[^:]+: a4003c00 ld1rqb {z0.b}, p7/z, \[x0\]
-+[^:]+: a4002060 ld1rqb {z0.b}, p0/z, \[x3\]
-+[^:]+: a4002060 ld1rqb {z0.b}, p0/z, \[x3\]
-+[^:]+: a4002060 ld1rqb {z0.b}, p0/z, \[x3\]
-+[^:]+: a40023e0 ld1rqb {z0.b}, p0/z, \[sp\]
-+[^:]+: a40023e0 ld1rqb {z0.b}, p0/z, \[sp\]
-+[^:]+: a40023e0 ld1rqb {z0.b}, p0/z, \[sp\]
-+[^:]+: a4082000 ld1rqb {z0.b}, p0/z, \[x0, #-128\]
-+[^:]+: a4082000 ld1rqb {z0.b}, p0/z, \[x0, #-128\]
-+[^:]+: a40f2000 ld1rqb {z0.b}, p0/z, \[x0, #-16\]
-+[^:]+: a40f2000 ld1rqb {z0.b}, p0/z, \[x0, #-16\]
-+[^:]+: a4012000 ld1rqb {z0.b}, p0/z, \[x0, #16\]
-+[^:]+: a4012000 ld1rqb {z0.b}, p0/z, \[x0, #16\]
-+[^:]+: a4072000 ld1rqb {z0.b}, p0/z, \[x0, #112\]
-+[^:]+: a4072000 ld1rqb {z0.b}, p0/z, \[x0, #112\]
-+[^:]+: a4000000 ld1rqb {z0.b}, p0/z, \[x0, x0\]
-+[^:]+: a4000000 ld1rqb {z0.b}, p0/z, \[x0, x0\]
-+[^:]+: a4000000 ld1rqb {z0.b}, p0/z, \[x0, x0\]
-+[^:]+: a4000000 ld1rqb {z0.b}, p0/z, \[x0, x0\]
-+[^:]+: a4000001 ld1rqb {z1.b}, p0/z, \[x0, x0\]
-+[^:]+: a4000001 ld1rqb {z1.b}, p0/z, \[x0, x0\]
-+[^:]+: a4000001 ld1rqb {z1.b}, p0/z, \[x0, x0\]
-+[^:]+: a4000001 ld1rqb {z1.b}, p0/z, \[x0, x0\]
-+[^:]+: a400001f ld1rqb {z31.b}, p0/z, \[x0, x0\]
-+[^:]+: a400001f ld1rqb {z31.b}, p0/z, \[x0, x0\]
-+[^:]+: a400001f ld1rqb {z31.b}, p0/z, \[x0, x0\]
-+[^:]+: a400001f ld1rqb {z31.b}, p0/z, \[x0, x0\]
-+[^:]+: a4000800 ld1rqb {z0.b}, p2/z, \[x0, x0\]
-+[^:]+: a4000800 ld1rqb {z0.b}, p2/z, \[x0, x0\]
-+[^:]+: a4000800 ld1rqb {z0.b}, p2/z, \[x0, x0\]
-+[^:]+: a4001c00 ld1rqb {z0.b}, p7/z, \[x0, x0\]
-+[^:]+: a4001c00 ld1rqb {z0.b}, p7/z, \[x0, x0\]
-+[^:]+: a4001c00 ld1rqb {z0.b}, p7/z, \[x0, x0\]
-+[^:]+: a4000060 ld1rqb {z0.b}, p0/z, \[x3, x0\]
-+[^:]+: a4000060 ld1rqb {z0.b}, p0/z, \[x3, x0\]
-+[^:]+: a4000060 ld1rqb {z0.b}, p0/z, \[x3, x0\]
-+[^:]+: a40003e0 ld1rqb {z0.b}, p0/z, \[sp, x0\]
-+[^:]+: a40003e0 ld1rqb {z0.b}, p0/z, \[sp, x0\]
-+[^:]+: a40003e0 ld1rqb {z0.b}, p0/z, \[sp, x0\]
-+[^:]+: a4040000 ld1rqb {z0.b}, p0/z, \[x0, x4\]
-+[^:]+: a4040000 ld1rqb {z0.b}, p0/z, \[x0, x4\]
-+[^:]+: a4040000 ld1rqb {z0.b}, p0/z, \[x0, x4\]
-+[^:]+: a41e0000 ld1rqb {z0.b}, p0/z, \[x0, x30\]
-+[^:]+: a41e0000 ld1rqb {z0.b}, p0/z, \[x0, x30\]
-+[^:]+: a41e0000 ld1rqb {z0.b}, p0/z, \[x0, x30\]
-+[^:]+: a5802000 ld1rqd {z0.d}, p0/z, \[x0\]
-+[^:]+: a5802000 ld1rqd {z0.d}, p0/z, \[x0\]
-+[^:]+: a5802000 ld1rqd {z0.d}, p0/z, \[x0\]
-+[^:]+: a5802000 ld1rqd {z0.d}, p0/z, \[x0\]
-+[^:]+: a5802001 ld1rqd {z1.d}, p0/z, \[x0\]
-+[^:]+: a5802001 ld1rqd {z1.d}, p0/z, \[x0\]
-+[^:]+: a5802001 ld1rqd {z1.d}, p0/z, \[x0\]
-+[^:]+: a5802001 ld1rqd {z1.d}, p0/z, \[x0\]
-+[^:]+: a580201f ld1rqd {z31.d}, p0/z, \[x0\]
-+[^:]+: a580201f ld1rqd {z31.d}, p0/z, \[x0\]
-+[^:]+: a580201f ld1rqd {z31.d}, p0/z, \[x0\]
-+[^:]+: a580201f ld1rqd {z31.d}, p0/z, \[x0\]
-+[^:]+: a5802800 ld1rqd {z0.d}, p2/z, \[x0\]
-+[^:]+: a5802800 ld1rqd {z0.d}, p2/z, \[x0\]
-+[^:]+: a5802800 ld1rqd {z0.d}, p2/z, \[x0\]
-+[^:]+: a5803c00 ld1rqd {z0.d}, p7/z, \[x0\]
-+[^:]+: a5803c00 ld1rqd {z0.d}, p7/z, \[x0\]
-+[^:]+: a5803c00 ld1rqd {z0.d}, p7/z, \[x0\]
-+[^:]+: a5802060 ld1rqd {z0.d}, p0/z, \[x3\]
-+[^:]+: a5802060 ld1rqd {z0.d}, p0/z, \[x3\]
-+[^:]+: a5802060 ld1rqd {z0.d}, p0/z, \[x3\]
-+[^:]+: a58023e0 ld1rqd {z0.d}, p0/z, \[sp\]
-+[^:]+: a58023e0 ld1rqd {z0.d}, p0/z, \[sp\]
-+[^:]+: a58023e0 ld1rqd {z0.d}, p0/z, \[sp\]
-+[^:]+: a5882000 ld1rqd {z0.d}, p0/z, \[x0, #-128\]
-+[^:]+: a5882000 ld1rqd {z0.d}, p0/z, \[x0, #-128\]
-+[^:]+: a58f2000 ld1rqd {z0.d}, p0/z, \[x0, #-16\]
-+[^:]+: a58f2000 ld1rqd {z0.d}, p0/z, \[x0, #-16\]
-+[^:]+: a5812000 ld1rqd {z0.d}, p0/z, \[x0, #16\]
-+[^:]+: a5812000 ld1rqd {z0.d}, p0/z, \[x0, #16\]
-+[^:]+: a5872000 ld1rqd {z0.d}, p0/z, \[x0, #112\]
-+[^:]+: a5872000 ld1rqd {z0.d}, p0/z, \[x0, #112\]
-+[^:]+: a5800000 ld1rqd {z0.d}, p0/z, \[x0, x0, lsl #3\]
-+[^:]+: a5800000 ld1rqd {z0.d}, p0/z, \[x0, x0, lsl #3\]
-+[^:]+: a5800000 ld1rqd {z0.d}, p0/z, \[x0, x0, lsl #3\]
-+[^:]+: a5800001 ld1rqd {z1.d}, p0/z, \[x0, x0, lsl #3\]
-+[^:]+: a5800001 ld1rqd {z1.d}, p0/z, \[x0, x0, lsl #3\]
-+[^:]+: a5800001 ld1rqd {z1.d}, p0/z, \[x0, x0, lsl #3\]
-+[^:]+: a580001f ld1rqd {z31.d}, p0/z, \[x0, x0, lsl #3\]
-+[^:]+: a580001f ld1rqd {z31.d}, p0/z, \[x0, x0, lsl #3\]
-+[^:]+: a580001f ld1rqd {z31.d}, p0/z, \[x0, x0, lsl #3\]
-+[^:]+: a5800800 ld1rqd {z0.d}, p2/z, \[x0, x0, lsl #3\]
-+[^:]+: a5800800 ld1rqd {z0.d}, p2/z, \[x0, x0, lsl #3\]
-+[^:]+: a5801c00 ld1rqd {z0.d}, p7/z, \[x0, x0, lsl #3\]
-+[^:]+: a5801c00 ld1rqd {z0.d}, p7/z, \[x0, x0, lsl #3\]
-+[^:]+: a5800060 ld1rqd {z0.d}, p0/z, \[x3, x0, lsl #3\]
-+[^:]+: a5800060 ld1rqd {z0.d}, p0/z, \[x3, x0, lsl #3\]
-+[^:]+: a58003e0 ld1rqd {z0.d}, p0/z, \[sp, x0, lsl #3\]
-+[^:]+: a58003e0 ld1rqd {z0.d}, p0/z, \[sp, x0, lsl #3\]
-+[^:]+: a5840000 ld1rqd {z0.d}, p0/z, \[x0, x4, lsl #3\]
-+[^:]+: a5840000 ld1rqd {z0.d}, p0/z, \[x0, x4, lsl #3\]
-+[^:]+: a59e0000 ld1rqd {z0.d}, p0/z, \[x0, x30, lsl #3\]
-+[^:]+: a59e0000 ld1rqd {z0.d}, p0/z, \[x0, x30, lsl #3\]
-+[^:]+: a4802000 ld1rqh {z0.h}, p0/z, \[x0\]
-+[^:]+: a4802000 ld1rqh {z0.h}, p0/z, \[x0\]
-+[^:]+: a4802000 ld1rqh {z0.h}, p0/z, \[x0\]
-+[^:]+: a4802000 ld1rqh {z0.h}, p0/z, \[x0\]
-+[^:]+: a4802001 ld1rqh {z1.h}, p0/z, \[x0\]
-+[^:]+: a4802001 ld1rqh {z1.h}, p0/z, \[x0\]
-+[^:]+: a4802001 ld1rqh {z1.h}, p0/z, \[x0\]
-+[^:]+: a4802001 ld1rqh {z1.h}, p0/z, \[x0\]
-+[^:]+: a480201f ld1rqh {z31.h}, p0/z, \[x0\]
-+[^:]+: a480201f ld1rqh {z31.h}, p0/z, \[x0\]
-+[^:]+: a480201f ld1rqh {z31.h}, p0/z, \[x0\]
-+[^:]+: a480201f ld1rqh {z31.h}, p0/z, \[x0\]
-+[^:]+: a4802800 ld1rqh {z0.h}, p2/z, \[x0\]
-+[^:]+: a4802800 ld1rqh {z0.h}, p2/z, \[x0\]
-+[^:]+: a4802800 ld1rqh {z0.h}, p2/z, \[x0\]
-+[^:]+: a4803c00 ld1rqh {z0.h}, p7/z, \[x0\]
-+[^:]+: a4803c00 ld1rqh {z0.h}, p7/z, \[x0\]
-+[^:]+: a4803c00 ld1rqh {z0.h}, p7/z, \[x0\]
-+[^:]+: a4802060 ld1rqh {z0.h}, p0/z, \[x3\]
-+[^:]+: a4802060 ld1rqh {z0.h}, p0/z, \[x3\]
-+[^:]+: a4802060 ld1rqh {z0.h}, p0/z, \[x3\]
-+[^:]+: a48023e0 ld1rqh {z0.h}, p0/z, \[sp\]
-+[^:]+: a48023e0 ld1rqh {z0.h}, p0/z, \[sp\]
-+[^:]+: a48023e0 ld1rqh {z0.h}, p0/z, \[sp\]
-+[^:]+: a4882000 ld1rqh {z0.h}, p0/z, \[x0, #-128\]
-+[^:]+: a4882000 ld1rqh {z0.h}, p0/z, \[x0, #-128\]
-+[^:]+: a48f2000 ld1rqh {z0.h}, p0/z, \[x0, #-16\]
-+[^:]+: a48f2000 ld1rqh {z0.h}, p0/z, \[x0, #-16\]
-+[^:]+: a4812000 ld1rqh {z0.h}, p0/z, \[x0, #16\]
-+[^:]+: a4812000 ld1rqh {z0.h}, p0/z, \[x0, #16\]
-+[^:]+: a4872000 ld1rqh {z0.h}, p0/z, \[x0, #112\]
-+[^:]+: a4872000 ld1rqh {z0.h}, p0/z, \[x0, #112\]
-+[^:]+: a4800000 ld1rqh {z0.h}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a4800000 ld1rqh {z0.h}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a4800000 ld1rqh {z0.h}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a4800001 ld1rqh {z1.h}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a4800001 ld1rqh {z1.h}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a4800001 ld1rqh {z1.h}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a480001f ld1rqh {z31.h}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a480001f ld1rqh {z31.h}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a480001f ld1rqh {z31.h}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a4800800 ld1rqh {z0.h}, p2/z, \[x0, x0, lsl #1\]
-+[^:]+: a4800800 ld1rqh {z0.h}, p2/z, \[x0, x0, lsl #1\]
-+[^:]+: a4801c00 ld1rqh {z0.h}, p7/z, \[x0, x0, lsl #1\]
-+[^:]+: a4801c00 ld1rqh {z0.h}, p7/z, \[x0, x0, lsl #1\]
-+[^:]+: a4800060 ld1rqh {z0.h}, p0/z, \[x3, x0, lsl #1\]
-+[^:]+: a4800060 ld1rqh {z0.h}, p0/z, \[x3, x0, lsl #1\]
-+[^:]+: a48003e0 ld1rqh {z0.h}, p0/z, \[sp, x0, lsl #1\]
-+[^:]+: a48003e0 ld1rqh {z0.h}, p0/z, \[sp, x0, lsl #1\]
-+[^:]+: a4840000 ld1rqh {z0.h}, p0/z, \[x0, x4, lsl #1\]
-+[^:]+: a4840000 ld1rqh {z0.h}, p0/z, \[x0, x4, lsl #1\]
-+[^:]+: a49e0000 ld1rqh {z0.h}, p0/z, \[x0, x30, lsl #1\]
-+[^:]+: a49e0000 ld1rqh {z0.h}, p0/z, \[x0, x30, lsl #1\]
-+[^:]+: a5002000 ld1rqw {z0.s}, p0/z, \[x0\]
-+[^:]+: a5002000 ld1rqw {z0.s}, p0/z, \[x0\]
-+[^:]+: a5002000 ld1rqw {z0.s}, p0/z, \[x0\]
-+[^:]+: a5002000 ld1rqw {z0.s}, p0/z, \[x0\]
-+[^:]+: a5002001 ld1rqw {z1.s}, p0/z, \[x0\]
-+[^:]+: a5002001 ld1rqw {z1.s}, p0/z, \[x0\]
-+[^:]+: a5002001 ld1rqw {z1.s}, p0/z, \[x0\]
-+[^:]+: a5002001 ld1rqw {z1.s}, p0/z, \[x0\]
-+[^:]+: a500201f ld1rqw {z31.s}, p0/z, \[x0\]
-+[^:]+: a500201f ld1rqw {z31.s}, p0/z, \[x0\]
-+[^:]+: a500201f ld1rqw {z31.s}, p0/z, \[x0\]
-+[^:]+: a500201f ld1rqw {z31.s}, p0/z, \[x0\]
-+[^:]+: a5002800 ld1rqw {z0.s}, p2/z, \[x0\]
-+[^:]+: a5002800 ld1rqw {z0.s}, p2/z, \[x0\]
-+[^:]+: a5002800 ld1rqw {z0.s}, p2/z, \[x0\]
-+[^:]+: a5003c00 ld1rqw {z0.s}, p7/z, \[x0\]
-+[^:]+: a5003c00 ld1rqw {z0.s}, p7/z, \[x0\]
-+[^:]+: a5003c00 ld1rqw {z0.s}, p7/z, \[x0\]
-+[^:]+: a5002060 ld1rqw {z0.s}, p0/z, \[x3\]
-+[^:]+: a5002060 ld1rqw {z0.s}, p0/z, \[x3\]
-+[^:]+: a5002060 ld1rqw {z0.s}, p0/z, \[x3\]
-+[^:]+: a50023e0 ld1rqw {z0.s}, p0/z, \[sp\]
-+[^:]+: a50023e0 ld1rqw {z0.s}, p0/z, \[sp\]
-+[^:]+: a50023e0 ld1rqw {z0.s}, p0/z, \[sp\]
-+[^:]+: a5082000 ld1rqw {z0.s}, p0/z, \[x0, #-128\]
-+[^:]+: a5082000 ld1rqw {z0.s}, p0/z, \[x0, #-128\]
-+[^:]+: a50f2000 ld1rqw {z0.s}, p0/z, \[x0, #-16\]
-+[^:]+: a50f2000 ld1rqw {z0.s}, p0/z, \[x0, #-16\]
-+[^:]+: a5012000 ld1rqw {z0.s}, p0/z, \[x0, #16\]
-+[^:]+: a5012000 ld1rqw {z0.s}, p0/z, \[x0, #16\]
-+[^:]+: a5072000 ld1rqw {z0.s}, p0/z, \[x0, #112\]
-+[^:]+: a5072000 ld1rqw {z0.s}, p0/z, \[x0, #112\]
-+[^:]+: a5000000 ld1rqw {z0.s}, p0/z, \[x0, x0, lsl #2\]
-+[^:]+: a5000000 ld1rqw {z0.s}, p0/z, \[x0, x0, lsl #2\]
-+[^:]+: a5000000 ld1rqw {z0.s}, p0/z, \[x0, x0, lsl #2\]
-+[^:]+: a5000001 ld1rqw {z1.s}, p0/z, \[x0, x0, lsl #2\]
-+[^:]+: a5000001 ld1rqw {z1.s}, p0/z, \[x0, x0, lsl #2\]
-+[^:]+: a5000001 ld1rqw {z1.s}, p0/z, \[x0, x0, lsl #2\]
-+[^:]+: a500001f ld1rqw {z31.s}, p0/z, \[x0, x0, lsl #2\]
-+[^:]+: a500001f ld1rqw {z31.s}, p0/z, \[x0, x0, lsl #2\]
-+[^:]+: a500001f ld1rqw {z31.s}, p0/z, \[x0, x0, lsl #2\]
-+[^:]+: a5000800 ld1rqw {z0.s}, p2/z, \[x0, x0, lsl #2\]
-+[^:]+: a5000800 ld1rqw {z0.s}, p2/z, \[x0, x0, lsl #2\]
-+[^:]+: a5001c00 ld1rqw {z0.s}, p7/z, \[x0, x0, lsl #2\]
-+[^:]+: a5001c00 ld1rqw {z0.s}, p7/z, \[x0, x0, lsl #2\]
-+[^:]+: a5000060 ld1rqw {z0.s}, p0/z, \[x3, x0, lsl #2\]
-+[^:]+: a5000060 ld1rqw {z0.s}, p0/z, \[x3, x0, lsl #2\]
-+[^:]+: a50003e0 ld1rqw {z0.s}, p0/z, \[sp, x0, lsl #2\]
-+[^:]+: a50003e0 ld1rqw {z0.s}, p0/z, \[sp, x0, lsl #2\]
-+[^:]+: a5040000 ld1rqw {z0.s}, p0/z, \[x0, x4, lsl #2\]
-+[^:]+: a5040000 ld1rqw {z0.s}, p0/z, \[x0, x4, lsl #2\]
-+[^:]+: a51e0000 ld1rqw {z0.s}, p0/z, \[x0, x30, lsl #2\]
-+[^:]+: a51e0000 ld1rqw {z0.s}, p0/z, \[x0, x30, lsl #2\]
-+[^:]+: 8540c000 ld1rw {z0.s}, p0/z, \[x0\]
-+[^:]+: 8540c000 ld1rw {z0.s}, p0/z, \[x0\]
-+[^:]+: 8540c000 ld1rw {z0.s}, p0/z, \[x0\]
-+[^:]+: 8540c000 ld1rw {z0.s}, p0/z, \[x0\]
-+[^:]+: 8540c001 ld1rw {z1.s}, p0/z, \[x0\]
-+[^:]+: 8540c001 ld1rw {z1.s}, p0/z, \[x0\]
-+[^:]+: 8540c001 ld1rw {z1.s}, p0/z, \[x0\]
-+[^:]+: 8540c001 ld1rw {z1.s}, p0/z, \[x0\]
-+[^:]+: 8540c01f ld1rw {z31.s}, p0/z, \[x0\]
-+[^:]+: 8540c01f ld1rw {z31.s}, p0/z, \[x0\]
-+[^:]+: 8540c01f ld1rw {z31.s}, p0/z, \[x0\]
-+[^:]+: 8540c01f ld1rw {z31.s}, p0/z, \[x0\]
-+[^:]+: 8540c800 ld1rw {z0.s}, p2/z, \[x0\]
-+[^:]+: 8540c800 ld1rw {z0.s}, p2/z, \[x0\]
-+[^:]+: 8540c800 ld1rw {z0.s}, p2/z, \[x0\]
-+[^:]+: 8540dc00 ld1rw {z0.s}, p7/z, \[x0\]
-+[^:]+: 8540dc00 ld1rw {z0.s}, p7/z, \[x0\]
-+[^:]+: 8540dc00 ld1rw {z0.s}, p7/z, \[x0\]
-+[^:]+: 8540c060 ld1rw {z0.s}, p0/z, \[x3\]
-+[^:]+: 8540c060 ld1rw {z0.s}, p0/z, \[x3\]
-+[^:]+: 8540c060 ld1rw {z0.s}, p0/z, \[x3\]
-+[^:]+: 8540c3e0 ld1rw {z0.s}, p0/z, \[sp\]
-+[^:]+: 8540c3e0 ld1rw {z0.s}, p0/z, \[sp\]
-+[^:]+: 8540c3e0 ld1rw {z0.s}, p0/z, \[sp\]
-+[^:]+: 855fc000 ld1rw {z0.s}, p0/z, \[x0, #124\]
-+[^:]+: 855fc000 ld1rw {z0.s}, p0/z, \[x0, #124\]
-+[^:]+: 8560c000 ld1rw {z0.s}, p0/z, \[x0, #128\]
-+[^:]+: 8560c000 ld1rw {z0.s}, p0/z, \[x0, #128\]
-+[^:]+: 8561c000 ld1rw {z0.s}, p0/z, \[x0, #132\]
-+[^:]+: 8561c000 ld1rw {z0.s}, p0/z, \[x0, #132\]
-+[^:]+: 857fc000 ld1rw {z0.s}, p0/z, \[x0, #252\]
-+[^:]+: 857fc000 ld1rw {z0.s}, p0/z, \[x0, #252\]
-+[^:]+: 8540e000 ld1rw {z0.d}, p0/z, \[x0\]
-+[^:]+: 8540e000 ld1rw {z0.d}, p0/z, \[x0\]
-+[^:]+: 8540e000 ld1rw {z0.d}, p0/z, \[x0\]
-+[^:]+: 8540e000 ld1rw {z0.d}, p0/z, \[x0\]
-+[^:]+: 8540e001 ld1rw {z1.d}, p0/z, \[x0\]
-+[^:]+: 8540e001 ld1rw {z1.d}, p0/z, \[x0\]
-+[^:]+: 8540e001 ld1rw {z1.d}, p0/z, \[x0\]
-+[^:]+: 8540e001 ld1rw {z1.d}, p0/z, \[x0\]
-+[^:]+: 8540e01f ld1rw {z31.d}, p0/z, \[x0\]
-+[^:]+: 8540e01f ld1rw {z31.d}, p0/z, \[x0\]
-+[^:]+: 8540e01f ld1rw {z31.d}, p0/z, \[x0\]
-+[^:]+: 8540e01f ld1rw {z31.d}, p0/z, \[x0\]
-+[^:]+: 8540e800 ld1rw {z0.d}, p2/z, \[x0\]
-+[^:]+: 8540e800 ld1rw {z0.d}, p2/z, \[x0\]
-+[^:]+: 8540e800 ld1rw {z0.d}, p2/z, \[x0\]
-+[^:]+: 8540fc00 ld1rw {z0.d}, p7/z, \[x0\]
-+[^:]+: 8540fc00 ld1rw {z0.d}, p7/z, \[x0\]
-+[^:]+: 8540fc00 ld1rw {z0.d}, p7/z, \[x0\]
-+[^:]+: 8540e060 ld1rw {z0.d}, p0/z, \[x3\]
-+[^:]+: 8540e060 ld1rw {z0.d}, p0/z, \[x3\]
-+[^:]+: 8540e060 ld1rw {z0.d}, p0/z, \[x3\]
-+[^:]+: 8540e3e0 ld1rw {z0.d}, p0/z, \[sp\]
-+[^:]+: 8540e3e0 ld1rw {z0.d}, p0/z, \[sp\]
-+[^:]+: 8540e3e0 ld1rw {z0.d}, p0/z, \[sp\]
-+[^:]+: 855fe000 ld1rw {z0.d}, p0/z, \[x0, #124\]
-+[^:]+: 855fe000 ld1rw {z0.d}, p0/z, \[x0, #124\]
-+[^:]+: 8560e000 ld1rw {z0.d}, p0/z, \[x0, #128\]
-+[^:]+: 8560e000 ld1rw {z0.d}, p0/z, \[x0, #128\]
-+[^:]+: 8561e000 ld1rw {z0.d}, p0/z, \[x0, #132\]
-+[^:]+: 8561e000 ld1rw {z0.d}, p0/z, \[x0, #132\]
-+[^:]+: 857fe000 ld1rw {z0.d}, p0/z, \[x0, #252\]
-+[^:]+: 857fe000 ld1rw {z0.d}, p0/z, \[x0, #252\]
-+[^:]+: 84000000 ld1sb {z0.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84000000 ld1sb {z0.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84000000 ld1sb {z0.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84000000 ld1sb {z0.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84000001 ld1sb {z1.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84000001 ld1sb {z1.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84000001 ld1sb {z1.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84000001 ld1sb {z1.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 8400001f ld1sb {z31.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 8400001f ld1sb {z31.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 8400001f ld1sb {z31.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 8400001f ld1sb {z31.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84000800 ld1sb {z0.s}, p2/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84000800 ld1sb {z0.s}, p2/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84000800 ld1sb {z0.s}, p2/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84001c00 ld1sb {z0.s}, p7/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84001c00 ld1sb {z0.s}, p7/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84001c00 ld1sb {z0.s}, p7/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84000060 ld1sb {z0.s}, p0/z, \[x3, z0.s, uxtw\]
-+[^:]+: 84000060 ld1sb {z0.s}, p0/z, \[x3, z0.s, uxtw\]
-+[^:]+: 84000060 ld1sb {z0.s}, p0/z, \[x3, z0.s, uxtw\]
-+[^:]+: 840003e0 ld1sb {z0.s}, p0/z, \[sp, z0.s, uxtw\]
-+[^:]+: 840003e0 ld1sb {z0.s}, p0/z, \[sp, z0.s, uxtw\]
-+[^:]+: 840003e0 ld1sb {z0.s}, p0/z, \[sp, z0.s, uxtw\]
-+[^:]+: 84040000 ld1sb {z0.s}, p0/z, \[x0, z4.s, uxtw\]
-+[^:]+: 84040000 ld1sb {z0.s}, p0/z, \[x0, z4.s, uxtw\]
-+[^:]+: 84040000 ld1sb {z0.s}, p0/z, \[x0, z4.s, uxtw\]
-+[^:]+: 841f0000 ld1sb {z0.s}, p0/z, \[x0, z31.s, uxtw\]
-+[^:]+: 841f0000 ld1sb {z0.s}, p0/z, \[x0, z31.s, uxtw\]
-+[^:]+: 841f0000 ld1sb {z0.s}, p0/z, \[x0, z31.s, uxtw\]
-+[^:]+: 84400000 ld1sb {z0.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84400000 ld1sb {z0.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84400000 ld1sb {z0.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84400000 ld1sb {z0.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84400001 ld1sb {z1.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84400001 ld1sb {z1.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84400001 ld1sb {z1.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84400001 ld1sb {z1.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 8440001f ld1sb {z31.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 8440001f ld1sb {z31.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 8440001f ld1sb {z31.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 8440001f ld1sb {z31.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84400800 ld1sb {z0.s}, p2/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84400800 ld1sb {z0.s}, p2/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84400800 ld1sb {z0.s}, p2/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84401c00 ld1sb {z0.s}, p7/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84401c00 ld1sb {z0.s}, p7/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84401c00 ld1sb {z0.s}, p7/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84400060 ld1sb {z0.s}, p0/z, \[x3, z0.s, sxtw\]
-+[^:]+: 84400060 ld1sb {z0.s}, p0/z, \[x3, z0.s, sxtw\]
-+[^:]+: 84400060 ld1sb {z0.s}, p0/z, \[x3, z0.s, sxtw\]
-+[^:]+: 844003e0 ld1sb {z0.s}, p0/z, \[sp, z0.s, sxtw\]
-+[^:]+: 844003e0 ld1sb {z0.s}, p0/z, \[sp, z0.s, sxtw\]
-+[^:]+: 844003e0 ld1sb {z0.s}, p0/z, \[sp, z0.s, sxtw\]
-+[^:]+: 84440000 ld1sb {z0.s}, p0/z, \[x0, z4.s, sxtw\]
-+[^:]+: 84440000 ld1sb {z0.s}, p0/z, \[x0, z4.s, sxtw\]
-+[^:]+: 84440000 ld1sb {z0.s}, p0/z, \[x0, z4.s, sxtw\]
-+[^:]+: 845f0000 ld1sb {z0.s}, p0/z, \[x0, z31.s, sxtw\]
-+[^:]+: 845f0000 ld1sb {z0.s}, p0/z, \[x0, z31.s, sxtw\]
-+[^:]+: 845f0000 ld1sb {z0.s}, p0/z, \[x0, z31.s, sxtw\]
-+[^:]+: a5804000 ld1sb {z0.d}, p0/z, \[x0, x0\]
-+[^:]+: a5804000 ld1sb {z0.d}, p0/z, \[x0, x0\]
-+[^:]+: a5804000 ld1sb {z0.d}, p0/z, \[x0, x0\]
-+[^:]+: a5804000 ld1sb {z0.d}, p0/z, \[x0, x0\]
-+[^:]+: a5804001 ld1sb {z1.d}, p0/z, \[x0, x0\]
-+[^:]+: a5804001 ld1sb {z1.d}, p0/z, \[x0, x0\]
-+[^:]+: a5804001 ld1sb {z1.d}, p0/z, \[x0, x0\]
-+[^:]+: a5804001 ld1sb {z1.d}, p0/z, \[x0, x0\]
-+[^:]+: a580401f ld1sb {z31.d}, p0/z, \[x0, x0\]
-+[^:]+: a580401f ld1sb {z31.d}, p0/z, \[x0, x0\]
-+[^:]+: a580401f ld1sb {z31.d}, p0/z, \[x0, x0\]
-+[^:]+: a580401f ld1sb {z31.d}, p0/z, \[x0, x0\]
-+[^:]+: a5804800 ld1sb {z0.d}, p2/z, \[x0, x0\]
-+[^:]+: a5804800 ld1sb {z0.d}, p2/z, \[x0, x0\]
-+[^:]+: a5804800 ld1sb {z0.d}, p2/z, \[x0, x0\]
-+[^:]+: a5805c00 ld1sb {z0.d}, p7/z, \[x0, x0\]
-+[^:]+: a5805c00 ld1sb {z0.d}, p7/z, \[x0, x0\]
-+[^:]+: a5805c00 ld1sb {z0.d}, p7/z, \[x0, x0\]
-+[^:]+: a5804060 ld1sb {z0.d}, p0/z, \[x3, x0\]
-+[^:]+: a5804060 ld1sb {z0.d}, p0/z, \[x3, x0\]
-+[^:]+: a5804060 ld1sb {z0.d}, p0/z, \[x3, x0\]
-+[^:]+: a58043e0 ld1sb {z0.d}, p0/z, \[sp, x0\]
-+[^:]+: a58043e0 ld1sb {z0.d}, p0/z, \[sp, x0\]
-+[^:]+: a58043e0 ld1sb {z0.d}, p0/z, \[sp, x0\]
-+[^:]+: a5844000 ld1sb {z0.d}, p0/z, \[x0, x4\]
-+[^:]+: a5844000 ld1sb {z0.d}, p0/z, \[x0, x4\]
-+[^:]+: a5844000 ld1sb {z0.d}, p0/z, \[x0, x4\]
-+[^:]+: a59e4000 ld1sb {z0.d}, p0/z, \[x0, x30\]
-+[^:]+: a59e4000 ld1sb {z0.d}, p0/z, \[x0, x30\]
-+[^:]+: a59e4000 ld1sb {z0.d}, p0/z, \[x0, x30\]
-+[^:]+: a5a04000 ld1sb {z0.s}, p0/z, \[x0, x0\]
-+[^:]+: a5a04000 ld1sb {z0.s}, p0/z, \[x0, x0\]
-+[^:]+: a5a04000 ld1sb {z0.s}, p0/z, \[x0, x0\]
-+[^:]+: a5a04000 ld1sb {z0.s}, p0/z, \[x0, x0\]
-+[^:]+: a5a04001 ld1sb {z1.s}, p0/z, \[x0, x0\]
-+[^:]+: a5a04001 ld1sb {z1.s}, p0/z, \[x0, x0\]
-+[^:]+: a5a04001 ld1sb {z1.s}, p0/z, \[x0, x0\]
-+[^:]+: a5a04001 ld1sb {z1.s}, p0/z, \[x0, x0\]
-+[^:]+: a5a0401f ld1sb {z31.s}, p0/z, \[x0, x0\]
-+[^:]+: a5a0401f ld1sb {z31.s}, p0/z, \[x0, x0\]
-+[^:]+: a5a0401f ld1sb {z31.s}, p0/z, \[x0, x0\]
-+[^:]+: a5a0401f ld1sb {z31.s}, p0/z, \[x0, x0\]
-+[^:]+: a5a04800 ld1sb {z0.s}, p2/z, \[x0, x0\]
-+[^:]+: a5a04800 ld1sb {z0.s}, p2/z, \[x0, x0\]
-+[^:]+: a5a04800 ld1sb {z0.s}, p2/z, \[x0, x0\]
-+[^:]+: a5a05c00 ld1sb {z0.s}, p7/z, \[x0, x0\]
-+[^:]+: a5a05c00 ld1sb {z0.s}, p7/z, \[x0, x0\]
-+[^:]+: a5a05c00 ld1sb {z0.s}, p7/z, \[x0, x0\]
-+[^:]+: a5a04060 ld1sb {z0.s}, p0/z, \[x3, x0\]
-+[^:]+: a5a04060 ld1sb {z0.s}, p0/z, \[x3, x0\]
-+[^:]+: a5a04060 ld1sb {z0.s}, p0/z, \[x3, x0\]
-+[^:]+: a5a043e0 ld1sb {z0.s}, p0/z, \[sp, x0\]
-+[^:]+: a5a043e0 ld1sb {z0.s}, p0/z, \[sp, x0\]
-+[^:]+: a5a043e0 ld1sb {z0.s}, p0/z, \[sp, x0\]
-+[^:]+: a5a44000 ld1sb {z0.s}, p0/z, \[x0, x4\]
-+[^:]+: a5a44000 ld1sb {z0.s}, p0/z, \[x0, x4\]
-+[^:]+: a5a44000 ld1sb {z0.s}, p0/z, \[x0, x4\]
-+[^:]+: a5be4000 ld1sb {z0.s}, p0/z, \[x0, x30\]
-+[^:]+: a5be4000 ld1sb {z0.s}, p0/z, \[x0, x30\]
-+[^:]+: a5be4000 ld1sb {z0.s}, p0/z, \[x0, x30\]
-+[^:]+: a5c04000 ld1sb {z0.h}, p0/z, \[x0, x0\]
-+[^:]+: a5c04000 ld1sb {z0.h}, p0/z, \[x0, x0\]
-+[^:]+: a5c04000 ld1sb {z0.h}, p0/z, \[x0, x0\]
-+[^:]+: a5c04000 ld1sb {z0.h}, p0/z, \[x0, x0\]
-+[^:]+: a5c04001 ld1sb {z1.h}, p0/z, \[x0, x0\]
-+[^:]+: a5c04001 ld1sb {z1.h}, p0/z, \[x0, x0\]
-+[^:]+: a5c04001 ld1sb {z1.h}, p0/z, \[x0, x0\]
-+[^:]+: a5c04001 ld1sb {z1.h}, p0/z, \[x0, x0\]
-+[^:]+: a5c0401f ld1sb {z31.h}, p0/z, \[x0, x0\]
-+[^:]+: a5c0401f ld1sb {z31.h}, p0/z, \[x0, x0\]
-+[^:]+: a5c0401f ld1sb {z31.h}, p0/z, \[x0, x0\]
-+[^:]+: a5c0401f ld1sb {z31.h}, p0/z, \[x0, x0\]
-+[^:]+: a5c04800 ld1sb {z0.h}, p2/z, \[x0, x0\]
-+[^:]+: a5c04800 ld1sb {z0.h}, p2/z, \[x0, x0\]
-+[^:]+: a5c04800 ld1sb {z0.h}, p2/z, \[x0, x0\]
-+[^:]+: a5c05c00 ld1sb {z0.h}, p7/z, \[x0, x0\]
-+[^:]+: a5c05c00 ld1sb {z0.h}, p7/z, \[x0, x0\]
-+[^:]+: a5c05c00 ld1sb {z0.h}, p7/z, \[x0, x0\]
-+[^:]+: a5c04060 ld1sb {z0.h}, p0/z, \[x3, x0\]
-+[^:]+: a5c04060 ld1sb {z0.h}, p0/z, \[x3, x0\]
-+[^:]+: a5c04060 ld1sb {z0.h}, p0/z, \[x3, x0\]
-+[^:]+: a5c043e0 ld1sb {z0.h}, p0/z, \[sp, x0\]
-+[^:]+: a5c043e0 ld1sb {z0.h}, p0/z, \[sp, x0\]
-+[^:]+: a5c043e0 ld1sb {z0.h}, p0/z, \[sp, x0\]
-+[^:]+: a5c44000 ld1sb {z0.h}, p0/z, \[x0, x4\]
-+[^:]+: a5c44000 ld1sb {z0.h}, p0/z, \[x0, x4\]
-+[^:]+: a5c44000 ld1sb {z0.h}, p0/z, \[x0, x4\]
-+[^:]+: a5de4000 ld1sb {z0.h}, p0/z, \[x0, x30\]
-+[^:]+: a5de4000 ld1sb {z0.h}, p0/z, \[x0, x30\]
-+[^:]+: a5de4000 ld1sb {z0.h}, p0/z, \[x0, x30\]
-+[^:]+: c4000000 ld1sb {z0.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4000000 ld1sb {z0.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4000000 ld1sb {z0.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4000000 ld1sb {z0.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4000001 ld1sb {z1.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4000001 ld1sb {z1.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4000001 ld1sb {z1.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4000001 ld1sb {z1.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c400001f ld1sb {z31.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c400001f ld1sb {z31.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c400001f ld1sb {z31.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c400001f ld1sb {z31.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4000800 ld1sb {z0.d}, p2/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4000800 ld1sb {z0.d}, p2/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4000800 ld1sb {z0.d}, p2/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4001c00 ld1sb {z0.d}, p7/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4001c00 ld1sb {z0.d}, p7/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4001c00 ld1sb {z0.d}, p7/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4000060 ld1sb {z0.d}, p0/z, \[x3, z0.d, uxtw\]
-+[^:]+: c4000060 ld1sb {z0.d}, p0/z, \[x3, z0.d, uxtw\]
-+[^:]+: c4000060 ld1sb {z0.d}, p0/z, \[x3, z0.d, uxtw\]
-+[^:]+: c40003e0 ld1sb {z0.d}, p0/z, \[sp, z0.d, uxtw\]
-+[^:]+: c40003e0 ld1sb {z0.d}, p0/z, \[sp, z0.d, uxtw\]
-+[^:]+: c40003e0 ld1sb {z0.d}, p0/z, \[sp, z0.d, uxtw\]
-+[^:]+: c4040000 ld1sb {z0.d}, p0/z, \[x0, z4.d, uxtw\]
-+[^:]+: c4040000 ld1sb {z0.d}, p0/z, \[x0, z4.d, uxtw\]
-+[^:]+: c4040000 ld1sb {z0.d}, p0/z, \[x0, z4.d, uxtw\]
-+[^:]+: c41f0000 ld1sb {z0.d}, p0/z, \[x0, z31.d, uxtw\]
-+[^:]+: c41f0000 ld1sb {z0.d}, p0/z, \[x0, z31.d, uxtw\]
-+[^:]+: c41f0000 ld1sb {z0.d}, p0/z, \[x0, z31.d, uxtw\]
-+[^:]+: c4400000 ld1sb {z0.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4400000 ld1sb {z0.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4400000 ld1sb {z0.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4400000 ld1sb {z0.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4400001 ld1sb {z1.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4400001 ld1sb {z1.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4400001 ld1sb {z1.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4400001 ld1sb {z1.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c440001f ld1sb {z31.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c440001f ld1sb {z31.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c440001f ld1sb {z31.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c440001f ld1sb {z31.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4400800 ld1sb {z0.d}, p2/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4400800 ld1sb {z0.d}, p2/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4400800 ld1sb {z0.d}, p2/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4401c00 ld1sb {z0.d}, p7/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4401c00 ld1sb {z0.d}, p7/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4401c00 ld1sb {z0.d}, p7/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4400060 ld1sb {z0.d}, p0/z, \[x3, z0.d, sxtw\]
-+[^:]+: c4400060 ld1sb {z0.d}, p0/z, \[x3, z0.d, sxtw\]
-+[^:]+: c4400060 ld1sb {z0.d}, p0/z, \[x3, z0.d, sxtw\]
-+[^:]+: c44003e0 ld1sb {z0.d}, p0/z, \[sp, z0.d, sxtw\]
-+[^:]+: c44003e0 ld1sb {z0.d}, p0/z, \[sp, z0.d, sxtw\]
-+[^:]+: c44003e0 ld1sb {z0.d}, p0/z, \[sp, z0.d, sxtw\]
-+[^:]+: c4440000 ld1sb {z0.d}, p0/z, \[x0, z4.d, sxtw\]
-+[^:]+: c4440000 ld1sb {z0.d}, p0/z, \[x0, z4.d, sxtw\]
-+[^:]+: c4440000 ld1sb {z0.d}, p0/z, \[x0, z4.d, sxtw\]
-+[^:]+: c45f0000 ld1sb {z0.d}, p0/z, \[x0, z31.d, sxtw\]
-+[^:]+: c45f0000 ld1sb {z0.d}, p0/z, \[x0, z31.d, sxtw\]
-+[^:]+: c45f0000 ld1sb {z0.d}, p0/z, \[x0, z31.d, sxtw\]
-+[^:]+: c4408000 ld1sb {z0.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c4408000 ld1sb {z0.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c4408000 ld1sb {z0.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c4408000 ld1sb {z0.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c4408001 ld1sb {z1.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c4408001 ld1sb {z1.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c4408001 ld1sb {z1.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c4408001 ld1sb {z1.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c440801f ld1sb {z31.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c440801f ld1sb {z31.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c440801f ld1sb {z31.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c440801f ld1sb {z31.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c4408800 ld1sb {z0.d}, p2/z, \[x0, z0.d\]
-+[^:]+: c4408800 ld1sb {z0.d}, p2/z, \[x0, z0.d\]
-+[^:]+: c4408800 ld1sb {z0.d}, p2/z, \[x0, z0.d\]
-+[^:]+: c4409c00 ld1sb {z0.d}, p7/z, \[x0, z0.d\]
-+[^:]+: c4409c00 ld1sb {z0.d}, p7/z, \[x0, z0.d\]
-+[^:]+: c4409c00 ld1sb {z0.d}, p7/z, \[x0, z0.d\]
-+[^:]+: c4408060 ld1sb {z0.d}, p0/z, \[x3, z0.d\]
-+[^:]+: c4408060 ld1sb {z0.d}, p0/z, \[x3, z0.d\]
-+[^:]+: c4408060 ld1sb {z0.d}, p0/z, \[x3, z0.d\]
-+[^:]+: c44083e0 ld1sb {z0.d}, p0/z, \[sp, z0.d\]
-+[^:]+: c44083e0 ld1sb {z0.d}, p0/z, \[sp, z0.d\]
-+[^:]+: c44083e0 ld1sb {z0.d}, p0/z, \[sp, z0.d\]
-+[^:]+: c4448000 ld1sb {z0.d}, p0/z, \[x0, z4.d\]
-+[^:]+: c4448000 ld1sb {z0.d}, p0/z, \[x0, z4.d\]
-+[^:]+: c4448000 ld1sb {z0.d}, p0/z, \[x0, z4.d\]
-+[^:]+: c45f8000 ld1sb {z0.d}, p0/z, \[x0, z31.d\]
-+[^:]+: c45f8000 ld1sb {z0.d}, p0/z, \[x0, z31.d\]
-+[^:]+: c45f8000 ld1sb {z0.d}, p0/z, \[x0, z31.d\]
-+[^:]+: 84208000 ld1sb {z0.s}, p0/z, \[z0.s\]
-+[^:]+: 84208000 ld1sb {z0.s}, p0/z, \[z0.s\]
-+[^:]+: 84208000 ld1sb {z0.s}, p0/z, \[z0.s\]
-+[^:]+: 84208000 ld1sb {z0.s}, p0/z, \[z0.s\]
-+[^:]+: 84208001 ld1sb {z1.s}, p0/z, \[z0.s\]
-+[^:]+: 84208001 ld1sb {z1.s}, p0/z, \[z0.s\]
-+[^:]+: 84208001 ld1sb {z1.s}, p0/z, \[z0.s\]
-+[^:]+: 84208001 ld1sb {z1.s}, p0/z, \[z0.s\]
-+[^:]+: 8420801f ld1sb {z31.s}, p0/z, \[z0.s\]
-+[^:]+: 8420801f ld1sb {z31.s}, p0/z, \[z0.s\]
-+[^:]+: 8420801f ld1sb {z31.s}, p0/z, \[z0.s\]
-+[^:]+: 8420801f ld1sb {z31.s}, p0/z, \[z0.s\]
-+[^:]+: 84208800 ld1sb {z0.s}, p2/z, \[z0.s\]
-+[^:]+: 84208800 ld1sb {z0.s}, p2/z, \[z0.s\]
-+[^:]+: 84208800 ld1sb {z0.s}, p2/z, \[z0.s\]
-+[^:]+: 84209c00 ld1sb {z0.s}, p7/z, \[z0.s\]
-+[^:]+: 84209c00 ld1sb {z0.s}, p7/z, \[z0.s\]
-+[^:]+: 84209c00 ld1sb {z0.s}, p7/z, \[z0.s\]
-+[^:]+: 84208060 ld1sb {z0.s}, p0/z, \[z3.s\]
-+[^:]+: 84208060 ld1sb {z0.s}, p0/z, \[z3.s\]
-+[^:]+: 84208060 ld1sb {z0.s}, p0/z, \[z3.s\]
-+[^:]+: 842083e0 ld1sb {z0.s}, p0/z, \[z31.s\]
-+[^:]+: 842083e0 ld1sb {z0.s}, p0/z, \[z31.s\]
-+[^:]+: 842083e0 ld1sb {z0.s}, p0/z, \[z31.s\]
-+[^:]+: 842f8000 ld1sb {z0.s}, p0/z, \[z0.s, #15\]
-+[^:]+: 842f8000 ld1sb {z0.s}, p0/z, \[z0.s, #15\]
-+[^:]+: 84308000 ld1sb {z0.s}, p0/z, \[z0.s, #16\]
-+[^:]+: 84308000 ld1sb {z0.s}, p0/z, \[z0.s, #16\]
-+[^:]+: 84318000 ld1sb {z0.s}, p0/z, \[z0.s, #17\]
-+[^:]+: 84318000 ld1sb {z0.s}, p0/z, \[z0.s, #17\]
-+[^:]+: 843f8000 ld1sb {z0.s}, p0/z, \[z0.s, #31\]
-+[^:]+: 843f8000 ld1sb {z0.s}, p0/z, \[z0.s, #31\]
-+[^:]+: a580a000 ld1sb {z0.d}, p0/z, \[x0\]
-+[^:]+: a580a000 ld1sb {z0.d}, p0/z, \[x0\]
-+[^:]+: a580a000 ld1sb {z0.d}, p0/z, \[x0\]
-+[^:]+: a580a000 ld1sb {z0.d}, p0/z, \[x0\]
-+[^:]+: a580a000 ld1sb {z0.d}, p0/z, \[x0\]
-+[^:]+: a580a001 ld1sb {z1.d}, p0/z, \[x0\]
-+[^:]+: a580a001 ld1sb {z1.d}, p0/z, \[x0\]
-+[^:]+: a580a001 ld1sb {z1.d}, p0/z, \[x0\]
-+[^:]+: a580a001 ld1sb {z1.d}, p0/z, \[x0\]
-+[^:]+: a580a001 ld1sb {z1.d}, p0/z, \[x0\]
-+[^:]+: a580a01f ld1sb {z31.d}, p0/z, \[x0\]
-+[^:]+: a580a01f ld1sb {z31.d}, p0/z, \[x0\]
-+[^:]+: a580a01f ld1sb {z31.d}, p0/z, \[x0\]
-+[^:]+: a580a01f ld1sb {z31.d}, p0/z, \[x0\]
-+[^:]+: a580a01f ld1sb {z31.d}, p0/z, \[x0\]
-+[^:]+: a580a800 ld1sb {z0.d}, p2/z, \[x0\]
-+[^:]+: a580a800 ld1sb {z0.d}, p2/z, \[x0\]
-+[^:]+: a580a800 ld1sb {z0.d}, p2/z, \[x0\]
-+[^:]+: a580a800 ld1sb {z0.d}, p2/z, \[x0\]
-+[^:]+: a580bc00 ld1sb {z0.d}, p7/z, \[x0\]
-+[^:]+: a580bc00 ld1sb {z0.d}, p7/z, \[x0\]
-+[^:]+: a580bc00 ld1sb {z0.d}, p7/z, \[x0\]
-+[^:]+: a580bc00 ld1sb {z0.d}, p7/z, \[x0\]
-+[^:]+: a580a060 ld1sb {z0.d}, p0/z, \[x3\]
-+[^:]+: a580a060 ld1sb {z0.d}, p0/z, \[x3\]
-+[^:]+: a580a060 ld1sb {z0.d}, p0/z, \[x3\]
-+[^:]+: a580a060 ld1sb {z0.d}, p0/z, \[x3\]
-+[^:]+: a580a3e0 ld1sb {z0.d}, p0/z, \[sp\]
-+[^:]+: a580a3e0 ld1sb {z0.d}, p0/z, \[sp\]
-+[^:]+: a580a3e0 ld1sb {z0.d}, p0/z, \[sp\]
-+[^:]+: a580a3e0 ld1sb {z0.d}, p0/z, \[sp\]
-+[^:]+: a587a000 ld1sb {z0.d}, p0/z, \[x0, #7, mul vl\]
-+[^:]+: a587a000 ld1sb {z0.d}, p0/z, \[x0, #7, mul vl\]
-+[^:]+: a588a000 ld1sb {z0.d}, p0/z, \[x0, #-8, mul vl\]
-+[^:]+: a588a000 ld1sb {z0.d}, p0/z, \[x0, #-8, mul vl\]
-+[^:]+: a589a000 ld1sb {z0.d}, p0/z, \[x0, #-7, mul vl\]
-+[^:]+: a589a000 ld1sb {z0.d}, p0/z, \[x0, #-7, mul vl\]
-+[^:]+: a58fa000 ld1sb {z0.d}, p0/z, \[x0, #-1, mul vl\]
-+[^:]+: a58fa000 ld1sb {z0.d}, p0/z, \[x0, #-1, mul vl\]
-+[^:]+: a5a0a000 ld1sb {z0.s}, p0/z, \[x0\]
-+[^:]+: a5a0a000 ld1sb {z0.s}, p0/z, \[x0\]
-+[^:]+: a5a0a000 ld1sb {z0.s}, p0/z, \[x0\]
-+[^:]+: a5a0a000 ld1sb {z0.s}, p0/z, \[x0\]
-+[^:]+: a5a0a000 ld1sb {z0.s}, p0/z, \[x0\]
-+[^:]+: a5a0a001 ld1sb {z1.s}, p0/z, \[x0\]
-+[^:]+: a5a0a001 ld1sb {z1.s}, p0/z, \[x0\]
-+[^:]+: a5a0a001 ld1sb {z1.s}, p0/z, \[x0\]
-+[^:]+: a5a0a001 ld1sb {z1.s}, p0/z, \[x0\]
-+[^:]+: a5a0a001 ld1sb {z1.s}, p0/z, \[x0\]
-+[^:]+: a5a0a01f ld1sb {z31.s}, p0/z, \[x0\]
-+[^:]+: a5a0a01f ld1sb {z31.s}, p0/z, \[x0\]
-+[^:]+: a5a0a01f ld1sb {z31.s}, p0/z, \[x0\]
-+[^:]+: a5a0a01f ld1sb {z31.s}, p0/z, \[x0\]
-+[^:]+: a5a0a01f ld1sb {z31.s}, p0/z, \[x0\]
-+[^:]+: a5a0a800 ld1sb {z0.s}, p2/z, \[x0\]
-+[^:]+: a5a0a800 ld1sb {z0.s}, p2/z, \[x0\]
-+[^:]+: a5a0a800 ld1sb {z0.s}, p2/z, \[x0\]
-+[^:]+: a5a0a800 ld1sb {z0.s}, p2/z, \[x0\]
-+[^:]+: a5a0bc00 ld1sb {z0.s}, p7/z, \[x0\]
-+[^:]+: a5a0bc00 ld1sb {z0.s}, p7/z, \[x0\]
-+[^:]+: a5a0bc00 ld1sb {z0.s}, p7/z, \[x0\]
-+[^:]+: a5a0bc00 ld1sb {z0.s}, p7/z, \[x0\]
-+[^:]+: a5a0a060 ld1sb {z0.s}, p0/z, \[x3\]
-+[^:]+: a5a0a060 ld1sb {z0.s}, p0/z, \[x3\]
-+[^:]+: a5a0a060 ld1sb {z0.s}, p0/z, \[x3\]
-+[^:]+: a5a0a060 ld1sb {z0.s}, p0/z, \[x3\]
-+[^:]+: a5a0a3e0 ld1sb {z0.s}, p0/z, \[sp\]
-+[^:]+: a5a0a3e0 ld1sb {z0.s}, p0/z, \[sp\]
-+[^:]+: a5a0a3e0 ld1sb {z0.s}, p0/z, \[sp\]
-+[^:]+: a5a0a3e0 ld1sb {z0.s}, p0/z, \[sp\]
-+[^:]+: a5a7a000 ld1sb {z0.s}, p0/z, \[x0, #7, mul vl\]
-+[^:]+: a5a7a000 ld1sb {z0.s}, p0/z, \[x0, #7, mul vl\]
-+[^:]+: a5a8a000 ld1sb {z0.s}, p0/z, \[x0, #-8, mul vl\]
-+[^:]+: a5a8a000 ld1sb {z0.s}, p0/z, \[x0, #-8, mul vl\]
-+[^:]+: a5a9a000 ld1sb {z0.s}, p0/z, \[x0, #-7, mul vl\]
-+[^:]+: a5a9a000 ld1sb {z0.s}, p0/z, \[x0, #-7, mul vl\]
-+[^:]+: a5afa000 ld1sb {z0.s}, p0/z, \[x0, #-1, mul vl\]
-+[^:]+: a5afa000 ld1sb {z0.s}, p0/z, \[x0, #-1, mul vl\]
-+[^:]+: a5c0a000 ld1sb {z0.h}, p0/z, \[x0\]
-+[^:]+: a5c0a000 ld1sb {z0.h}, p0/z, \[x0\]
-+[^:]+: a5c0a000 ld1sb {z0.h}, p0/z, \[x0\]
-+[^:]+: a5c0a000 ld1sb {z0.h}, p0/z, \[x0\]
-+[^:]+: a5c0a000 ld1sb {z0.h}, p0/z, \[x0\]
-+[^:]+: a5c0a001 ld1sb {z1.h}, p0/z, \[x0\]
-+[^:]+: a5c0a001 ld1sb {z1.h}, p0/z, \[x0\]
-+[^:]+: a5c0a001 ld1sb {z1.h}, p0/z, \[x0\]
-+[^:]+: a5c0a001 ld1sb {z1.h}, p0/z, \[x0\]
-+[^:]+: a5c0a001 ld1sb {z1.h}, p0/z, \[x0\]
-+[^:]+: a5c0a01f ld1sb {z31.h}, p0/z, \[x0\]
-+[^:]+: a5c0a01f ld1sb {z31.h}, p0/z, \[x0\]
-+[^:]+: a5c0a01f ld1sb {z31.h}, p0/z, \[x0\]
-+[^:]+: a5c0a01f ld1sb {z31.h}, p0/z, \[x0\]
-+[^:]+: a5c0a01f ld1sb {z31.h}, p0/z, \[x0\]
-+[^:]+: a5c0a800 ld1sb {z0.h}, p2/z, \[x0\]
-+[^:]+: a5c0a800 ld1sb {z0.h}, p2/z, \[x0\]
-+[^:]+: a5c0a800 ld1sb {z0.h}, p2/z, \[x0\]
-+[^:]+: a5c0a800 ld1sb {z0.h}, p2/z, \[x0\]
-+[^:]+: a5c0bc00 ld1sb {z0.h}, p7/z, \[x0\]
-+[^:]+: a5c0bc00 ld1sb {z0.h}, p7/z, \[x0\]
-+[^:]+: a5c0bc00 ld1sb {z0.h}, p7/z, \[x0\]
-+[^:]+: a5c0bc00 ld1sb {z0.h}, p7/z, \[x0\]
-+[^:]+: a5c0a060 ld1sb {z0.h}, p0/z, \[x3\]
-+[^:]+: a5c0a060 ld1sb {z0.h}, p0/z, \[x3\]
-+[^:]+: a5c0a060 ld1sb {z0.h}, p0/z, \[x3\]
-+[^:]+: a5c0a060 ld1sb {z0.h}, p0/z, \[x3\]
-+[^:]+: a5c0a3e0 ld1sb {z0.h}, p0/z, \[sp\]
-+[^:]+: a5c0a3e0 ld1sb {z0.h}, p0/z, \[sp\]
-+[^:]+: a5c0a3e0 ld1sb {z0.h}, p0/z, \[sp\]
-+[^:]+: a5c0a3e0 ld1sb {z0.h}, p0/z, \[sp\]
-+[^:]+: a5c7a000 ld1sb {z0.h}, p0/z, \[x0, #7, mul vl\]
-+[^:]+: a5c7a000 ld1sb {z0.h}, p0/z, \[x0, #7, mul vl\]
-+[^:]+: a5c8a000 ld1sb {z0.h}, p0/z, \[x0, #-8, mul vl\]
-+[^:]+: a5c8a000 ld1sb {z0.h}, p0/z, \[x0, #-8, mul vl\]
-+[^:]+: a5c9a000 ld1sb {z0.h}, p0/z, \[x0, #-7, mul vl\]
-+[^:]+: a5c9a000 ld1sb {z0.h}, p0/z, \[x0, #-7, mul vl\]
-+[^:]+: a5cfa000 ld1sb {z0.h}, p0/z, \[x0, #-1, mul vl\]
-+[^:]+: a5cfa000 ld1sb {z0.h}, p0/z, \[x0, #-1, mul vl\]
-+[^:]+: c4208000 ld1sb {z0.d}, p0/z, \[z0.d\]
-+[^:]+: c4208000 ld1sb {z0.d}, p0/z, \[z0.d\]
-+[^:]+: c4208000 ld1sb {z0.d}, p0/z, \[z0.d\]
-+[^:]+: c4208000 ld1sb {z0.d}, p0/z, \[z0.d\]
-+[^:]+: c4208001 ld1sb {z1.d}, p0/z, \[z0.d\]
-+[^:]+: c4208001 ld1sb {z1.d}, p0/z, \[z0.d\]
-+[^:]+: c4208001 ld1sb {z1.d}, p0/z, \[z0.d\]
-+[^:]+: c4208001 ld1sb {z1.d}, p0/z, \[z0.d\]
-+[^:]+: c420801f ld1sb {z31.d}, p0/z, \[z0.d\]
-+[^:]+: c420801f ld1sb {z31.d}, p0/z, \[z0.d\]
-+[^:]+: c420801f ld1sb {z31.d}, p0/z, \[z0.d\]
-+[^:]+: c420801f ld1sb {z31.d}, p0/z, \[z0.d\]
-+[^:]+: c4208800 ld1sb {z0.d}, p2/z, \[z0.d\]
-+[^:]+: c4208800 ld1sb {z0.d}, p2/z, \[z0.d\]
-+[^:]+: c4208800 ld1sb {z0.d}, p2/z, \[z0.d\]
-+[^:]+: c4209c00 ld1sb {z0.d}, p7/z, \[z0.d\]
-+[^:]+: c4209c00 ld1sb {z0.d}, p7/z, \[z0.d\]
-+[^:]+: c4209c00 ld1sb {z0.d}, p7/z, \[z0.d\]
-+[^:]+: c4208060 ld1sb {z0.d}, p0/z, \[z3.d\]
-+[^:]+: c4208060 ld1sb {z0.d}, p0/z, \[z3.d\]
-+[^:]+: c4208060 ld1sb {z0.d}, p0/z, \[z3.d\]
-+[^:]+: c42083e0 ld1sb {z0.d}, p0/z, \[z31.d\]
-+[^:]+: c42083e0 ld1sb {z0.d}, p0/z, \[z31.d\]
-+[^:]+: c42083e0 ld1sb {z0.d}, p0/z, \[z31.d\]
-+[^:]+: c42f8000 ld1sb {z0.d}, p0/z, \[z0.d, #15\]
-+[^:]+: c42f8000 ld1sb {z0.d}, p0/z, \[z0.d, #15\]
-+[^:]+: c4308000 ld1sb {z0.d}, p0/z, \[z0.d, #16\]
-+[^:]+: c4308000 ld1sb {z0.d}, p0/z, \[z0.d, #16\]
-+[^:]+: c4318000 ld1sb {z0.d}, p0/z, \[z0.d, #17\]
-+[^:]+: c4318000 ld1sb {z0.d}, p0/z, \[z0.d, #17\]
-+[^:]+: c43f8000 ld1sb {z0.d}, p0/z, \[z0.d, #31\]
-+[^:]+: c43f8000 ld1sb {z0.d}, p0/z, \[z0.d, #31\]
-+[^:]+: 84800000 ld1sh {z0.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84800000 ld1sh {z0.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84800000 ld1sh {z0.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84800000 ld1sh {z0.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84800001 ld1sh {z1.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84800001 ld1sh {z1.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84800001 ld1sh {z1.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84800001 ld1sh {z1.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 8480001f ld1sh {z31.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 8480001f ld1sh {z31.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 8480001f ld1sh {z31.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 8480001f ld1sh {z31.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84800800 ld1sh {z0.s}, p2/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84800800 ld1sh {z0.s}, p2/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84800800 ld1sh {z0.s}, p2/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84801c00 ld1sh {z0.s}, p7/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84801c00 ld1sh {z0.s}, p7/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84801c00 ld1sh {z0.s}, p7/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84800060 ld1sh {z0.s}, p0/z, \[x3, z0.s, uxtw\]
-+[^:]+: 84800060 ld1sh {z0.s}, p0/z, \[x3, z0.s, uxtw\]
-+[^:]+: 84800060 ld1sh {z0.s}, p0/z, \[x3, z0.s, uxtw\]
-+[^:]+: 848003e0 ld1sh {z0.s}, p0/z, \[sp, z0.s, uxtw\]
-+[^:]+: 848003e0 ld1sh {z0.s}, p0/z, \[sp, z0.s, uxtw\]
-+[^:]+: 848003e0 ld1sh {z0.s}, p0/z, \[sp, z0.s, uxtw\]
-+[^:]+: 84840000 ld1sh {z0.s}, p0/z, \[x0, z4.s, uxtw\]
-+[^:]+: 84840000 ld1sh {z0.s}, p0/z, \[x0, z4.s, uxtw\]
-+[^:]+: 84840000 ld1sh {z0.s}, p0/z, \[x0, z4.s, uxtw\]
-+[^:]+: 849f0000 ld1sh {z0.s}, p0/z, \[x0, z31.s, uxtw\]
-+[^:]+: 849f0000 ld1sh {z0.s}, p0/z, \[x0, z31.s, uxtw\]
-+[^:]+: 849f0000 ld1sh {z0.s}, p0/z, \[x0, z31.s, uxtw\]
-+[^:]+: 84c00000 ld1sh {z0.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84c00000 ld1sh {z0.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84c00000 ld1sh {z0.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84c00000 ld1sh {z0.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84c00001 ld1sh {z1.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84c00001 ld1sh {z1.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84c00001 ld1sh {z1.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84c00001 ld1sh {z1.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84c0001f ld1sh {z31.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84c0001f ld1sh {z31.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84c0001f ld1sh {z31.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84c0001f ld1sh {z31.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84c00800 ld1sh {z0.s}, p2/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84c00800 ld1sh {z0.s}, p2/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84c00800 ld1sh {z0.s}, p2/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84c01c00 ld1sh {z0.s}, p7/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84c01c00 ld1sh {z0.s}, p7/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84c01c00 ld1sh {z0.s}, p7/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84c00060 ld1sh {z0.s}, p0/z, \[x3, z0.s, sxtw\]
-+[^:]+: 84c00060 ld1sh {z0.s}, p0/z, \[x3, z0.s, sxtw\]
-+[^:]+: 84c00060 ld1sh {z0.s}, p0/z, \[x3, z0.s, sxtw\]
-+[^:]+: 84c003e0 ld1sh {z0.s}, p0/z, \[sp, z0.s, sxtw\]
-+[^:]+: 84c003e0 ld1sh {z0.s}, p0/z, \[sp, z0.s, sxtw\]
-+[^:]+: 84c003e0 ld1sh {z0.s}, p0/z, \[sp, z0.s, sxtw\]
-+[^:]+: 84c40000 ld1sh {z0.s}, p0/z, \[x0, z4.s, sxtw\]
-+[^:]+: 84c40000 ld1sh {z0.s}, p0/z, \[x0, z4.s, sxtw\]
-+[^:]+: 84c40000 ld1sh {z0.s}, p0/z, \[x0, z4.s, sxtw\]
-+[^:]+: 84df0000 ld1sh {z0.s}, p0/z, \[x0, z31.s, sxtw\]
-+[^:]+: 84df0000 ld1sh {z0.s}, p0/z, \[x0, z31.s, sxtw\]
-+[^:]+: 84df0000 ld1sh {z0.s}, p0/z, \[x0, z31.s, sxtw\]
-+[^:]+: 84a00000 ld1sh {z0.s}, p0/z, \[x0, z0.s, uxtw #1\]
-+[^:]+: 84a00000 ld1sh {z0.s}, p0/z, \[x0, z0.s, uxtw #1\]
-+[^:]+: 84a00000 ld1sh {z0.s}, p0/z, \[x0, z0.s, uxtw #1\]
-+[^:]+: 84a00001 ld1sh {z1.s}, p0/z, \[x0, z0.s, uxtw #1\]
-+[^:]+: 84a00001 ld1sh {z1.s}, p0/z, \[x0, z0.s, uxtw #1\]
-+[^:]+: 84a00001 ld1sh {z1.s}, p0/z, \[x0, z0.s, uxtw #1\]
-+[^:]+: 84a0001f ld1sh {z31.s}, p0/z, \[x0, z0.s, uxtw #1\]
-+[^:]+: 84a0001f ld1sh {z31.s}, p0/z, \[x0, z0.s, uxtw #1\]
-+[^:]+: 84a0001f ld1sh {z31.s}, p0/z, \[x0, z0.s, uxtw #1\]
-+[^:]+: 84a00800 ld1sh {z0.s}, p2/z, \[x0, z0.s, uxtw #1\]
-+[^:]+: 84a00800 ld1sh {z0.s}, p2/z, \[x0, z0.s, uxtw #1\]
-+[^:]+: 84a01c00 ld1sh {z0.s}, p7/z, \[x0, z0.s, uxtw #1\]
-+[^:]+: 84a01c00 ld1sh {z0.s}, p7/z, \[x0, z0.s, uxtw #1\]
-+[^:]+: 84a00060 ld1sh {z0.s}, p0/z, \[x3, z0.s, uxtw #1\]
-+[^:]+: 84a00060 ld1sh {z0.s}, p0/z, \[x3, z0.s, uxtw #1\]
-+[^:]+: 84a003e0 ld1sh {z0.s}, p0/z, \[sp, z0.s, uxtw #1\]
-+[^:]+: 84a003e0 ld1sh {z0.s}, p0/z, \[sp, z0.s, uxtw #1\]
-+[^:]+: 84a40000 ld1sh {z0.s}, p0/z, \[x0, z4.s, uxtw #1\]
-+[^:]+: 84a40000 ld1sh {z0.s}, p0/z, \[x0, z4.s, uxtw #1\]
-+[^:]+: 84bf0000 ld1sh {z0.s}, p0/z, \[x0, z31.s, uxtw #1\]
-+[^:]+: 84bf0000 ld1sh {z0.s}, p0/z, \[x0, z31.s, uxtw #1\]
-+[^:]+: 84e00000 ld1sh {z0.s}, p0/z, \[x0, z0.s, sxtw #1\]
-+[^:]+: 84e00000 ld1sh {z0.s}, p0/z, \[x0, z0.s, sxtw #1\]
-+[^:]+: 84e00000 ld1sh {z0.s}, p0/z, \[x0, z0.s, sxtw #1\]
-+[^:]+: 84e00001 ld1sh {z1.s}, p0/z, \[x0, z0.s, sxtw #1\]
-+[^:]+: 84e00001 ld1sh {z1.s}, p0/z, \[x0, z0.s, sxtw #1\]
-+[^:]+: 84e00001 ld1sh {z1.s}, p0/z, \[x0, z0.s, sxtw #1\]
-+[^:]+: 84e0001f ld1sh {z31.s}, p0/z, \[x0, z0.s, sxtw #1\]
-+[^:]+: 84e0001f ld1sh {z31.s}, p0/z, \[x0, z0.s, sxtw #1\]
-+[^:]+: 84e0001f ld1sh {z31.s}, p0/z, \[x0, z0.s, sxtw #1\]
-+[^:]+: 84e00800 ld1sh {z0.s}, p2/z, \[x0, z0.s, sxtw #1\]
-+[^:]+: 84e00800 ld1sh {z0.s}, p2/z, \[x0, z0.s, sxtw #1\]
-+[^:]+: 84e01c00 ld1sh {z0.s}, p7/z, \[x0, z0.s, sxtw #1\]
-+[^:]+: 84e01c00 ld1sh {z0.s}, p7/z, \[x0, z0.s, sxtw #1\]
-+[^:]+: 84e00060 ld1sh {z0.s}, p0/z, \[x3, z0.s, sxtw #1\]
-+[^:]+: 84e00060 ld1sh {z0.s}, p0/z, \[x3, z0.s, sxtw #1\]
-+[^:]+: 84e003e0 ld1sh {z0.s}, p0/z, \[sp, z0.s, sxtw #1\]
-+[^:]+: 84e003e0 ld1sh {z0.s}, p0/z, \[sp, z0.s, sxtw #1\]
-+[^:]+: 84e40000 ld1sh {z0.s}, p0/z, \[x0, z4.s, sxtw #1\]
-+[^:]+: 84e40000 ld1sh {z0.s}, p0/z, \[x0, z4.s, sxtw #1\]
-+[^:]+: 84ff0000 ld1sh {z0.s}, p0/z, \[x0, z31.s, sxtw #1\]
-+[^:]+: 84ff0000 ld1sh {z0.s}, p0/z, \[x0, z31.s, sxtw #1\]
-+[^:]+: a5004000 ld1sh {z0.d}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a5004000 ld1sh {z0.d}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a5004000 ld1sh {z0.d}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a5004001 ld1sh {z1.d}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a5004001 ld1sh {z1.d}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a5004001 ld1sh {z1.d}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a500401f ld1sh {z31.d}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a500401f ld1sh {z31.d}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a500401f ld1sh {z31.d}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a5004800 ld1sh {z0.d}, p2/z, \[x0, x0, lsl #1\]
-+[^:]+: a5004800 ld1sh {z0.d}, p2/z, \[x0, x0, lsl #1\]
-+[^:]+: a5005c00 ld1sh {z0.d}, p7/z, \[x0, x0, lsl #1\]
-+[^:]+: a5005c00 ld1sh {z0.d}, p7/z, \[x0, x0, lsl #1\]
-+[^:]+: a5004060 ld1sh {z0.d}, p0/z, \[x3, x0, lsl #1\]
-+[^:]+: a5004060 ld1sh {z0.d}, p0/z, \[x3, x0, lsl #1\]
-+[^:]+: a50043e0 ld1sh {z0.d}, p0/z, \[sp, x0, lsl #1\]
-+[^:]+: a50043e0 ld1sh {z0.d}, p0/z, \[sp, x0, lsl #1\]
-+[^:]+: a5044000 ld1sh {z0.d}, p0/z, \[x0, x4, lsl #1\]
-+[^:]+: a5044000 ld1sh {z0.d}, p0/z, \[x0, x4, lsl #1\]
-+[^:]+: a51e4000 ld1sh {z0.d}, p0/z, \[x0, x30, lsl #1\]
-+[^:]+: a51e4000 ld1sh {z0.d}, p0/z, \[x0, x30, lsl #1\]
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-+[^:]+: a5204000 ld1sh {z0.s}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a5204000 ld1sh {z0.s}, p0/z, \[x0, x0, lsl #1\]
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-+[^:]+: a5204001 ld1sh {z1.s}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a5204001 ld1sh {z1.s}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a520401f ld1sh {z31.s}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a520401f ld1sh {z31.s}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a520401f ld1sh {z31.s}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a5204800 ld1sh {z0.s}, p2/z, \[x0, x0, lsl #1\]
-+[^:]+: a5204800 ld1sh {z0.s}, p2/z, \[x0, x0, lsl #1\]
-+[^:]+: a5205c00 ld1sh {z0.s}, p7/z, \[x0, x0, lsl #1\]
-+[^:]+: a5205c00 ld1sh {z0.s}, p7/z, \[x0, x0, lsl #1\]
-+[^:]+: a5204060 ld1sh {z0.s}, p0/z, \[x3, x0, lsl #1\]
-+[^:]+: a5204060 ld1sh {z0.s}, p0/z, \[x3, x0, lsl #1\]
-+[^:]+: a52043e0 ld1sh {z0.s}, p0/z, \[sp, x0, lsl #1\]
-+[^:]+: a52043e0 ld1sh {z0.s}, p0/z, \[sp, x0, lsl #1\]
-+[^:]+: a5244000 ld1sh {z0.s}, p0/z, \[x0, x4, lsl #1\]
-+[^:]+: a5244000 ld1sh {z0.s}, p0/z, \[x0, x4, lsl #1\]
-+[^:]+: a53e4000 ld1sh {z0.s}, p0/z, \[x0, x30, lsl #1\]
-+[^:]+: a53e4000 ld1sh {z0.s}, p0/z, \[x0, x30, lsl #1\]
-+[^:]+: c4800000 ld1sh {z0.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4800000 ld1sh {z0.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4800000 ld1sh {z0.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4800000 ld1sh {z0.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4800001 ld1sh {z1.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4800001 ld1sh {z1.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4800001 ld1sh {z1.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4800001 ld1sh {z1.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c480001f ld1sh {z31.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c480001f ld1sh {z31.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c480001f ld1sh {z31.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c480001f ld1sh {z31.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4800800 ld1sh {z0.d}, p2/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4800800 ld1sh {z0.d}, p2/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4800800 ld1sh {z0.d}, p2/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4801c00 ld1sh {z0.d}, p7/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4801c00 ld1sh {z0.d}, p7/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4801c00 ld1sh {z0.d}, p7/z, \[x0, z0.d, uxtw\]
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-+[^:]+: c4800060 ld1sh {z0.d}, p0/z, \[x3, z0.d, uxtw\]
-+[^:]+: c4800060 ld1sh {z0.d}, p0/z, \[x3, z0.d, uxtw\]
-+[^:]+: c48003e0 ld1sh {z0.d}, p0/z, \[sp, z0.d, uxtw\]
-+[^:]+: c48003e0 ld1sh {z0.d}, p0/z, \[sp, z0.d, uxtw\]
-+[^:]+: c48003e0 ld1sh {z0.d}, p0/z, \[sp, z0.d, uxtw\]
-+[^:]+: c4840000 ld1sh {z0.d}, p0/z, \[x0, z4.d, uxtw\]
-+[^:]+: c4840000 ld1sh {z0.d}, p0/z, \[x0, z4.d, uxtw\]
-+[^:]+: c4840000 ld1sh {z0.d}, p0/z, \[x0, z4.d, uxtw\]
-+[^:]+: c49f0000 ld1sh {z0.d}, p0/z, \[x0, z31.d, uxtw\]
-+[^:]+: c49f0000 ld1sh {z0.d}, p0/z, \[x0, z31.d, uxtw\]
-+[^:]+: c49f0000 ld1sh {z0.d}, p0/z, \[x0, z31.d, uxtw\]
-+[^:]+: c4c00000 ld1sh {z0.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4c00000 ld1sh {z0.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4c00000 ld1sh {z0.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4c00000 ld1sh {z0.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4c00001 ld1sh {z1.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4c00001 ld1sh {z1.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4c00001 ld1sh {z1.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4c00001 ld1sh {z1.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4c0001f ld1sh {z31.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4c0001f ld1sh {z31.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4c0001f ld1sh {z31.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4c0001f ld1sh {z31.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4c00800 ld1sh {z0.d}, p2/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4c00800 ld1sh {z0.d}, p2/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4c00800 ld1sh {z0.d}, p2/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4c01c00 ld1sh {z0.d}, p7/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4c01c00 ld1sh {z0.d}, p7/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4c01c00 ld1sh {z0.d}, p7/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4c00060 ld1sh {z0.d}, p0/z, \[x3, z0.d, sxtw\]
-+[^:]+: c4c00060 ld1sh {z0.d}, p0/z, \[x3, z0.d, sxtw\]
-+[^:]+: c4c00060 ld1sh {z0.d}, p0/z, \[x3, z0.d, sxtw\]
-+[^:]+: c4c003e0 ld1sh {z0.d}, p0/z, \[sp, z0.d, sxtw\]
-+[^:]+: c4c003e0 ld1sh {z0.d}, p0/z, \[sp, z0.d, sxtw\]
-+[^:]+: c4c003e0 ld1sh {z0.d}, p0/z, \[sp, z0.d, sxtw\]
-+[^:]+: c4c40000 ld1sh {z0.d}, p0/z, \[x0, z4.d, sxtw\]
-+[^:]+: c4c40000 ld1sh {z0.d}, p0/z, \[x0, z4.d, sxtw\]
-+[^:]+: c4c40000 ld1sh {z0.d}, p0/z, \[x0, z4.d, sxtw\]
-+[^:]+: c4df0000 ld1sh {z0.d}, p0/z, \[x0, z31.d, sxtw\]
-+[^:]+: c4df0000 ld1sh {z0.d}, p0/z, \[x0, z31.d, sxtw\]
-+[^:]+: c4df0000 ld1sh {z0.d}, p0/z, \[x0, z31.d, sxtw\]
-+[^:]+: c4a00000 ld1sh {z0.d}, p0/z, \[x0, z0.d, uxtw #1\]
-+[^:]+: c4a00000 ld1sh {z0.d}, p0/z, \[x0, z0.d, uxtw #1\]
-+[^:]+: c4a00000 ld1sh {z0.d}, p0/z, \[x0, z0.d, uxtw #1\]
-+[^:]+: c4a00001 ld1sh {z1.d}, p0/z, \[x0, z0.d, uxtw #1\]
-+[^:]+: c4a00001 ld1sh {z1.d}, p0/z, \[x0, z0.d, uxtw #1\]
-+[^:]+: c4a00001 ld1sh {z1.d}, p0/z, \[x0, z0.d, uxtw #1\]
-+[^:]+: c4a0001f ld1sh {z31.d}, p0/z, \[x0, z0.d, uxtw #1\]
-+[^:]+: c4a0001f ld1sh {z31.d}, p0/z, \[x0, z0.d, uxtw #1\]
-+[^:]+: c4a0001f ld1sh {z31.d}, p0/z, \[x0, z0.d, uxtw #1\]
-+[^:]+: c4a00800 ld1sh {z0.d}, p2/z, \[x0, z0.d, uxtw #1\]
-+[^:]+: c4a00800 ld1sh {z0.d}, p2/z, \[x0, z0.d, uxtw #1\]
-+[^:]+: c4a01c00 ld1sh {z0.d}, p7/z, \[x0, z0.d, uxtw #1\]
-+[^:]+: c4a01c00 ld1sh {z0.d}, p7/z, \[x0, z0.d, uxtw #1\]
-+[^:]+: c4a00060 ld1sh {z0.d}, p0/z, \[x3, z0.d, uxtw #1\]
-+[^:]+: c4a00060 ld1sh {z0.d}, p0/z, \[x3, z0.d, uxtw #1\]
-+[^:]+: c4a003e0 ld1sh {z0.d}, p0/z, \[sp, z0.d, uxtw #1\]
-+[^:]+: c4a003e0 ld1sh {z0.d}, p0/z, \[sp, z0.d, uxtw #1\]
-+[^:]+: c4a40000 ld1sh {z0.d}, p0/z, \[x0, z4.d, uxtw #1\]
-+[^:]+: c4a40000 ld1sh {z0.d}, p0/z, \[x0, z4.d, uxtw #1\]
-+[^:]+: c4bf0000 ld1sh {z0.d}, p0/z, \[x0, z31.d, uxtw #1\]
-+[^:]+: c4bf0000 ld1sh {z0.d}, p0/z, \[x0, z31.d, uxtw #1\]
-+[^:]+: c4e00000 ld1sh {z0.d}, p0/z, \[x0, z0.d, sxtw #1\]
-+[^:]+: c4e00000 ld1sh {z0.d}, p0/z, \[x0, z0.d, sxtw #1\]
-+[^:]+: c4e00000 ld1sh {z0.d}, p0/z, \[x0, z0.d, sxtw #1\]
-+[^:]+: c4e00001 ld1sh {z1.d}, p0/z, \[x0, z0.d, sxtw #1\]
-+[^:]+: c4e00001 ld1sh {z1.d}, p0/z, \[x0, z0.d, sxtw #1\]
-+[^:]+: c4e00001 ld1sh {z1.d}, p0/z, \[x0, z0.d, sxtw #1\]
-+[^:]+: c4e0001f ld1sh {z31.d}, p0/z, \[x0, z0.d, sxtw #1\]
-+[^:]+: c4e0001f ld1sh {z31.d}, p0/z, \[x0, z0.d, sxtw #1\]
-+[^:]+: c4e0001f ld1sh {z31.d}, p0/z, \[x0, z0.d, sxtw #1\]
-+[^:]+: c4e00800 ld1sh {z0.d}, p2/z, \[x0, z0.d, sxtw #1\]
-+[^:]+: c4e00800 ld1sh {z0.d}, p2/z, \[x0, z0.d, sxtw #1\]
-+[^:]+: c4e01c00 ld1sh {z0.d}, p7/z, \[x0, z0.d, sxtw #1\]
-+[^:]+: c4e01c00 ld1sh {z0.d}, p7/z, \[x0, z0.d, sxtw #1\]
-+[^:]+: c4e00060 ld1sh {z0.d}, p0/z, \[x3, z0.d, sxtw #1\]
-+[^:]+: c4e00060 ld1sh {z0.d}, p0/z, \[x3, z0.d, sxtw #1\]
-+[^:]+: c4e003e0 ld1sh {z0.d}, p0/z, \[sp, z0.d, sxtw #1\]
-+[^:]+: c4e003e0 ld1sh {z0.d}, p0/z, \[sp, z0.d, sxtw #1\]
-+[^:]+: c4e40000 ld1sh {z0.d}, p0/z, \[x0, z4.d, sxtw #1\]
-+[^:]+: c4e40000 ld1sh {z0.d}, p0/z, \[x0, z4.d, sxtw #1\]
-+[^:]+: c4ff0000 ld1sh {z0.d}, p0/z, \[x0, z31.d, sxtw #1\]
-+[^:]+: c4ff0000 ld1sh {z0.d}, p0/z, \[x0, z31.d, sxtw #1\]
-+[^:]+: c4c08000 ld1sh {z0.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c4c08000 ld1sh {z0.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c4c08000 ld1sh {z0.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c4c08000 ld1sh {z0.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c4c08001 ld1sh {z1.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c4c08001 ld1sh {z1.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c4c08001 ld1sh {z1.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c4c08001 ld1sh {z1.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c4c0801f ld1sh {z31.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c4c0801f ld1sh {z31.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c4c0801f ld1sh {z31.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c4c0801f ld1sh {z31.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c4c08800 ld1sh {z0.d}, p2/z, \[x0, z0.d\]
-+[^:]+: c4c08800 ld1sh {z0.d}, p2/z, \[x0, z0.d\]
-+[^:]+: c4c08800 ld1sh {z0.d}, p2/z, \[x0, z0.d\]
-+[^:]+: c4c09c00 ld1sh {z0.d}, p7/z, \[x0, z0.d\]
-+[^:]+: c4c09c00 ld1sh {z0.d}, p7/z, \[x0, z0.d\]
-+[^:]+: c4c09c00 ld1sh {z0.d}, p7/z, \[x0, z0.d\]
-+[^:]+: c4c08060 ld1sh {z0.d}, p0/z, \[x3, z0.d\]
-+[^:]+: c4c08060 ld1sh {z0.d}, p0/z, \[x3, z0.d\]
-+[^:]+: c4c08060 ld1sh {z0.d}, p0/z, \[x3, z0.d\]
-+[^:]+: c4c083e0 ld1sh {z0.d}, p0/z, \[sp, z0.d\]
-+[^:]+: c4c083e0 ld1sh {z0.d}, p0/z, \[sp, z0.d\]
-+[^:]+: c4c083e0 ld1sh {z0.d}, p0/z, \[sp, z0.d\]
-+[^:]+: c4c48000 ld1sh {z0.d}, p0/z, \[x0, z4.d\]
-+[^:]+: c4c48000 ld1sh {z0.d}, p0/z, \[x0, z4.d\]
-+[^:]+: c4c48000 ld1sh {z0.d}, p0/z, \[x0, z4.d\]
-+[^:]+: c4df8000 ld1sh {z0.d}, p0/z, \[x0, z31.d\]
-+[^:]+: c4df8000 ld1sh {z0.d}, p0/z, \[x0, z31.d\]
-+[^:]+: c4df8000 ld1sh {z0.d}, p0/z, \[x0, z31.d\]
-+[^:]+: c4e08000 ld1sh {z0.d}, p0/z, \[x0, z0.d, lsl #1\]
-+[^:]+: c4e08000 ld1sh {z0.d}, p0/z, \[x0, z0.d, lsl #1\]
-+[^:]+: c4e08000 ld1sh {z0.d}, p0/z, \[x0, z0.d, lsl #1\]
-+[^:]+: c4e08001 ld1sh {z1.d}, p0/z, \[x0, z0.d, lsl #1\]
-+[^:]+: c4e08001 ld1sh {z1.d}, p0/z, \[x0, z0.d, lsl #1\]
-+[^:]+: c4e08001 ld1sh {z1.d}, p0/z, \[x0, z0.d, lsl #1\]
-+[^:]+: c4e0801f ld1sh {z31.d}, p0/z, \[x0, z0.d, lsl #1\]
-+[^:]+: c4e0801f ld1sh {z31.d}, p0/z, \[x0, z0.d, lsl #1\]
-+[^:]+: c4e0801f ld1sh {z31.d}, p0/z, \[x0, z0.d, lsl #1\]
-+[^:]+: c4e08800 ld1sh {z0.d}, p2/z, \[x0, z0.d, lsl #1\]
-+[^:]+: c4e08800 ld1sh {z0.d}, p2/z, \[x0, z0.d, lsl #1\]
-+[^:]+: c4e09c00 ld1sh {z0.d}, p7/z, \[x0, z0.d, lsl #1\]
-+[^:]+: c4e09c00 ld1sh {z0.d}, p7/z, \[x0, z0.d, lsl #1\]
-+[^:]+: c4e08060 ld1sh {z0.d}, p0/z, \[x3, z0.d, lsl #1\]
-+[^:]+: c4e08060 ld1sh {z0.d}, p0/z, \[x3, z0.d, lsl #1\]
-+[^:]+: c4e083e0 ld1sh {z0.d}, p0/z, \[sp, z0.d, lsl #1\]
-+[^:]+: c4e083e0 ld1sh {z0.d}, p0/z, \[sp, z0.d, lsl #1\]
-+[^:]+: c4e48000 ld1sh {z0.d}, p0/z, \[x0, z4.d, lsl #1\]
-+[^:]+: c4e48000 ld1sh {z0.d}, p0/z, \[x0, z4.d, lsl #1\]
-+[^:]+: c4ff8000 ld1sh {z0.d}, p0/z, \[x0, z31.d, lsl #1\]
-+[^:]+: c4ff8000 ld1sh {z0.d}, p0/z, \[x0, z31.d, lsl #1\]
-+[^:]+: 84a08000 ld1sh {z0.s}, p0/z, \[z0.s\]
-+[^:]+: 84a08000 ld1sh {z0.s}, p0/z, \[z0.s\]
-+[^:]+: 84a08000 ld1sh {z0.s}, p0/z, \[z0.s\]
-+[^:]+: 84a08000 ld1sh {z0.s}, p0/z, \[z0.s\]
-+[^:]+: 84a08001 ld1sh {z1.s}, p0/z, \[z0.s\]
-+[^:]+: 84a08001 ld1sh {z1.s}, p0/z, \[z0.s\]
-+[^:]+: 84a08001 ld1sh {z1.s}, p0/z, \[z0.s\]
-+[^:]+: 84a08001 ld1sh {z1.s}, p0/z, \[z0.s\]
-+[^:]+: 84a0801f ld1sh {z31.s}, p0/z, \[z0.s\]
-+[^:]+: 84a0801f ld1sh {z31.s}, p0/z, \[z0.s\]
-+[^:]+: 84a0801f ld1sh {z31.s}, p0/z, \[z0.s\]
-+[^:]+: 84a0801f ld1sh {z31.s}, p0/z, \[z0.s\]
-+[^:]+: 84a08800 ld1sh {z0.s}, p2/z, \[z0.s\]
-+[^:]+: 84a08800 ld1sh {z0.s}, p2/z, \[z0.s\]
-+[^:]+: 84a08800 ld1sh {z0.s}, p2/z, \[z0.s\]
-+[^:]+: 84a09c00 ld1sh {z0.s}, p7/z, \[z0.s\]
-+[^:]+: 84a09c00 ld1sh {z0.s}, p7/z, \[z0.s\]
-+[^:]+: 84a09c00 ld1sh {z0.s}, p7/z, \[z0.s\]
-+[^:]+: 84a08060 ld1sh {z0.s}, p0/z, \[z3.s\]
-+[^:]+: 84a08060 ld1sh {z0.s}, p0/z, \[z3.s\]
-+[^:]+: 84a08060 ld1sh {z0.s}, p0/z, \[z3.s\]
-+[^:]+: 84a083e0 ld1sh {z0.s}, p0/z, \[z31.s\]
-+[^:]+: 84a083e0 ld1sh {z0.s}, p0/z, \[z31.s\]
-+[^:]+: 84a083e0 ld1sh {z0.s}, p0/z, \[z31.s\]
-+[^:]+: 84af8000 ld1sh {z0.s}, p0/z, \[z0.s, #30\]
-+[^:]+: 84af8000 ld1sh {z0.s}, p0/z, \[z0.s, #30\]
-+[^:]+: 84b08000 ld1sh {z0.s}, p0/z, \[z0.s, #32\]
-+[^:]+: 84b08000 ld1sh {z0.s}, p0/z, \[z0.s, #32\]
-+[^:]+: 84b18000 ld1sh {z0.s}, p0/z, \[z0.s, #34\]
-+[^:]+: 84b18000 ld1sh {z0.s}, p0/z, \[z0.s, #34\]
-+[^:]+: 84bf8000 ld1sh {z0.s}, p0/z, \[z0.s, #62\]
-+[^:]+: 84bf8000 ld1sh {z0.s}, p0/z, \[z0.s, #62\]
-+[^:]+: a500a000 ld1sh {z0.d}, p0/z, \[x0\]
-+[^:]+: a500a000 ld1sh {z0.d}, p0/z, \[x0\]
-+[^:]+: a500a000 ld1sh {z0.d}, p0/z, \[x0\]
-+[^:]+: a500a000 ld1sh {z0.d}, p0/z, \[x0\]
-+[^:]+: a500a000 ld1sh {z0.d}, p0/z, \[x0\]
-+[^:]+: a500a001 ld1sh {z1.d}, p0/z, \[x0\]
-+[^:]+: a500a001 ld1sh {z1.d}, p0/z, \[x0\]
-+[^:]+: a500a001 ld1sh {z1.d}, p0/z, \[x0\]
-+[^:]+: a500a001 ld1sh {z1.d}, p0/z, \[x0\]
-+[^:]+: a500a001 ld1sh {z1.d}, p0/z, \[x0\]
-+[^:]+: a500a01f ld1sh {z31.d}, p0/z, \[x0\]
-+[^:]+: a500a01f ld1sh {z31.d}, p0/z, \[x0\]
-+[^:]+: a500a01f ld1sh {z31.d}, p0/z, \[x0\]
-+[^:]+: a500a01f ld1sh {z31.d}, p0/z, \[x0\]
-+[^:]+: a500a01f ld1sh {z31.d}, p0/z, \[x0\]
-+[^:]+: a500a800 ld1sh {z0.d}, p2/z, \[x0\]
-+[^:]+: a500a800 ld1sh {z0.d}, p2/z, \[x0\]
-+[^:]+: a500a800 ld1sh {z0.d}, p2/z, \[x0\]
-+[^:]+: a500a800 ld1sh {z0.d}, p2/z, \[x0\]
-+[^:]+: a500bc00 ld1sh {z0.d}, p7/z, \[x0\]
-+[^:]+: a500bc00 ld1sh {z0.d}, p7/z, \[x0\]
-+[^:]+: a500bc00 ld1sh {z0.d}, p7/z, \[x0\]
-+[^:]+: a500bc00 ld1sh {z0.d}, p7/z, \[x0\]
-+[^:]+: a500a060 ld1sh {z0.d}, p0/z, \[x3\]
-+[^:]+: a500a060 ld1sh {z0.d}, p0/z, \[x3\]
-+[^:]+: a500a060 ld1sh {z0.d}, p0/z, \[x3\]
-+[^:]+: a500a060 ld1sh {z0.d}, p0/z, \[x3\]
-+[^:]+: a500a3e0 ld1sh {z0.d}, p0/z, \[sp\]
-+[^:]+: a500a3e0 ld1sh {z0.d}, p0/z, \[sp\]
-+[^:]+: a500a3e0 ld1sh {z0.d}, p0/z, \[sp\]
-+[^:]+: a500a3e0 ld1sh {z0.d}, p0/z, \[sp\]
-+[^:]+: a507a000 ld1sh {z0.d}, p0/z, \[x0, #7, mul vl\]
-+[^:]+: a507a000 ld1sh {z0.d}, p0/z, \[x0, #7, mul vl\]
-+[^:]+: a508a000 ld1sh {z0.d}, p0/z, \[x0, #-8, mul vl\]
-+[^:]+: a508a000 ld1sh {z0.d}, p0/z, \[x0, #-8, mul vl\]
-+[^:]+: a509a000 ld1sh {z0.d}, p0/z, \[x0, #-7, mul vl\]
-+[^:]+: a509a000 ld1sh {z0.d}, p0/z, \[x0, #-7, mul vl\]
-+[^:]+: a50fa000 ld1sh {z0.d}, p0/z, \[x0, #-1, mul vl\]
-+[^:]+: a50fa000 ld1sh {z0.d}, p0/z, \[x0, #-1, mul vl\]
-+[^:]+: a520a000 ld1sh {z0.s}, p0/z, \[x0\]
-+[^:]+: a520a000 ld1sh {z0.s}, p0/z, \[x0\]
-+[^:]+: a520a000 ld1sh {z0.s}, p0/z, \[x0\]
-+[^:]+: a520a000 ld1sh {z0.s}, p0/z, \[x0\]
-+[^:]+: a520a000 ld1sh {z0.s}, p0/z, \[x0\]
-+[^:]+: a520a001 ld1sh {z1.s}, p0/z, \[x0\]
-+[^:]+: a520a001 ld1sh {z1.s}, p0/z, \[x0\]
-+[^:]+: a520a001 ld1sh {z1.s}, p0/z, \[x0\]
-+[^:]+: a520a001 ld1sh {z1.s}, p0/z, \[x0\]
-+[^:]+: a520a001 ld1sh {z1.s}, p0/z, \[x0\]
-+[^:]+: a520a01f ld1sh {z31.s}, p0/z, \[x0\]
-+[^:]+: a520a01f ld1sh {z31.s}, p0/z, \[x0\]
-+[^:]+: a520a01f ld1sh {z31.s}, p0/z, \[x0\]
-+[^:]+: a520a01f ld1sh {z31.s}, p0/z, \[x0\]
-+[^:]+: a520a01f ld1sh {z31.s}, p0/z, \[x0\]
-+[^:]+: a520a800 ld1sh {z0.s}, p2/z, \[x0\]
-+[^:]+: a520a800 ld1sh {z0.s}, p2/z, \[x0\]
-+[^:]+: a520a800 ld1sh {z0.s}, p2/z, \[x0\]
-+[^:]+: a520a800 ld1sh {z0.s}, p2/z, \[x0\]
-+[^:]+: a520bc00 ld1sh {z0.s}, p7/z, \[x0\]
-+[^:]+: a520bc00 ld1sh {z0.s}, p7/z, \[x0\]
-+[^:]+: a520bc00 ld1sh {z0.s}, p7/z, \[x0\]
-+[^:]+: a520bc00 ld1sh {z0.s}, p7/z, \[x0\]
-+[^:]+: a520a060 ld1sh {z0.s}, p0/z, \[x3\]
-+[^:]+: a520a060 ld1sh {z0.s}, p0/z, \[x3\]
-+[^:]+: a520a060 ld1sh {z0.s}, p0/z, \[x3\]
-+[^:]+: a520a060 ld1sh {z0.s}, p0/z, \[x3\]
-+[^:]+: a520a3e0 ld1sh {z0.s}, p0/z, \[sp\]
-+[^:]+: a520a3e0 ld1sh {z0.s}, p0/z, \[sp\]
-+[^:]+: a520a3e0 ld1sh {z0.s}, p0/z, \[sp\]
-+[^:]+: a520a3e0 ld1sh {z0.s}, p0/z, \[sp\]
-+[^:]+: a527a000 ld1sh {z0.s}, p0/z, \[x0, #7, mul vl\]
-+[^:]+: a527a000 ld1sh {z0.s}, p0/z, \[x0, #7, mul vl\]
-+[^:]+: a528a000 ld1sh {z0.s}, p0/z, \[x0, #-8, mul vl\]
-+[^:]+: a528a000 ld1sh {z0.s}, p0/z, \[x0, #-8, mul vl\]
-+[^:]+: a529a000 ld1sh {z0.s}, p0/z, \[x0, #-7, mul vl\]
-+[^:]+: a529a000 ld1sh {z0.s}, p0/z, \[x0, #-7, mul vl\]
-+[^:]+: a52fa000 ld1sh {z0.s}, p0/z, \[x0, #-1, mul vl\]
-+[^:]+: a52fa000 ld1sh {z0.s}, p0/z, \[x0, #-1, mul vl\]
-+[^:]+: c4a08000 ld1sh {z0.d}, p0/z, \[z0.d\]
-+[^:]+: c4a08000 ld1sh {z0.d}, p0/z, \[z0.d\]
-+[^:]+: c4a08000 ld1sh {z0.d}, p0/z, \[z0.d\]
-+[^:]+: c4a08000 ld1sh {z0.d}, p0/z, \[z0.d\]
-+[^:]+: c4a08001 ld1sh {z1.d}, p0/z, \[z0.d\]
-+[^:]+: c4a08001 ld1sh {z1.d}, p0/z, \[z0.d\]
-+[^:]+: c4a08001 ld1sh {z1.d}, p0/z, \[z0.d\]
-+[^:]+: c4a08001 ld1sh {z1.d}, p0/z, \[z0.d\]
-+[^:]+: c4a0801f ld1sh {z31.d}, p0/z, \[z0.d\]
-+[^:]+: c4a0801f ld1sh {z31.d}, p0/z, \[z0.d\]
-+[^:]+: c4a0801f ld1sh {z31.d}, p0/z, \[z0.d\]
-+[^:]+: c4a0801f ld1sh {z31.d}, p0/z, \[z0.d\]
-+[^:]+: c4a08800 ld1sh {z0.d}, p2/z, \[z0.d\]
-+[^:]+: c4a08800 ld1sh {z0.d}, p2/z, \[z0.d\]
-+[^:]+: c4a08800 ld1sh {z0.d}, p2/z, \[z0.d\]
-+[^:]+: c4a09c00 ld1sh {z0.d}, p7/z, \[z0.d\]
-+[^:]+: c4a09c00 ld1sh {z0.d}, p7/z, \[z0.d\]
-+[^:]+: c4a09c00 ld1sh {z0.d}, p7/z, \[z0.d\]
-+[^:]+: c4a08060 ld1sh {z0.d}, p0/z, \[z3.d\]
-+[^:]+: c4a08060 ld1sh {z0.d}, p0/z, \[z3.d\]
-+[^:]+: c4a08060 ld1sh {z0.d}, p0/z, \[z3.d\]
-+[^:]+: c4a083e0 ld1sh {z0.d}, p0/z, \[z31.d\]
-+[^:]+: c4a083e0 ld1sh {z0.d}, p0/z, \[z31.d\]
-+[^:]+: c4a083e0 ld1sh {z0.d}, p0/z, \[z31.d\]
-+[^:]+: c4af8000 ld1sh {z0.d}, p0/z, \[z0.d, #30\]
-+[^:]+: c4af8000 ld1sh {z0.d}, p0/z, \[z0.d, #30\]
-+[^:]+: c4b08000 ld1sh {z0.d}, p0/z, \[z0.d, #32\]
-+[^:]+: c4b08000 ld1sh {z0.d}, p0/z, \[z0.d, #32\]
-+[^:]+: c4b18000 ld1sh {z0.d}, p0/z, \[z0.d, #34\]
-+[^:]+: c4b18000 ld1sh {z0.d}, p0/z, \[z0.d, #34\]
-+[^:]+: c4bf8000 ld1sh {z0.d}, p0/z, \[z0.d, #62\]
-+[^:]+: c4bf8000 ld1sh {z0.d}, p0/z, \[z0.d, #62\]
-+[^:]+: a4804000 ld1sw {z0.d}, p0/z, \[x0, x0, lsl #2\]
-+[^:]+: a4804000 ld1sw {z0.d}, p0/z, \[x0, x0, lsl #2\]
-+[^:]+: a4804000 ld1sw {z0.d}, p0/z, \[x0, x0, lsl #2\]
-+[^:]+: a4804001 ld1sw {z1.d}, p0/z, \[x0, x0, lsl #2\]
-+[^:]+: a4804001 ld1sw {z1.d}, p0/z, \[x0, x0, lsl #2\]
-+[^:]+: a4804001 ld1sw {z1.d}, p0/z, \[x0, x0, lsl #2\]
-+[^:]+: a480401f ld1sw {z31.d}, p0/z, \[x0, x0, lsl #2\]
-+[^:]+: a480401f ld1sw {z31.d}, p0/z, \[x0, x0, lsl #2\]
-+[^:]+: a480401f ld1sw {z31.d}, p0/z, \[x0, x0, lsl #2\]
-+[^:]+: a4804800 ld1sw {z0.d}, p2/z, \[x0, x0, lsl #2\]
-+[^:]+: a4804800 ld1sw {z0.d}, p2/z, \[x0, x0, lsl #2\]
-+[^:]+: a4805c00 ld1sw {z0.d}, p7/z, \[x0, x0, lsl #2\]
-+[^:]+: a4805c00 ld1sw {z0.d}, p7/z, \[x0, x0, lsl #2\]
-+[^:]+: a4804060 ld1sw {z0.d}, p0/z, \[x3, x0, lsl #2\]
-+[^:]+: a4804060 ld1sw {z0.d}, p0/z, \[x3, x0, lsl #2\]
-+[^:]+: a48043e0 ld1sw {z0.d}, p0/z, \[sp, x0, lsl #2\]
-+[^:]+: a48043e0 ld1sw {z0.d}, p0/z, \[sp, x0, lsl #2\]
-+[^:]+: a4844000 ld1sw {z0.d}, p0/z, \[x0, x4, lsl #2\]
-+[^:]+: a4844000 ld1sw {z0.d}, p0/z, \[x0, x4, lsl #2\]
-+[^:]+: a49e4000 ld1sw {z0.d}, p0/z, \[x0, x30, lsl #2\]
-+[^:]+: a49e4000 ld1sw {z0.d}, p0/z, \[x0, x30, lsl #2\]
-+[^:]+: c5000000 ld1sw {z0.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c5000000 ld1sw {z0.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c5000000 ld1sw {z0.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c5000000 ld1sw {z0.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c5000001 ld1sw {z1.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c5000001 ld1sw {z1.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c5000001 ld1sw {z1.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c5000001 ld1sw {z1.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c500001f ld1sw {z31.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c500001f ld1sw {z31.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c500001f ld1sw {z31.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c500001f ld1sw {z31.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c5000800 ld1sw {z0.d}, p2/z, \[x0, z0.d, uxtw\]
-+[^:]+: c5000800 ld1sw {z0.d}, p2/z, \[x0, z0.d, uxtw\]
-+[^:]+: c5000800 ld1sw {z0.d}, p2/z, \[x0, z0.d, uxtw\]
-+[^:]+: c5001c00 ld1sw {z0.d}, p7/z, \[x0, z0.d, uxtw\]
-+[^:]+: c5001c00 ld1sw {z0.d}, p7/z, \[x0, z0.d, uxtw\]
-+[^:]+: c5001c00 ld1sw {z0.d}, p7/z, \[x0, z0.d, uxtw\]
-+[^:]+: c5000060 ld1sw {z0.d}, p0/z, \[x3, z0.d, uxtw\]
-+[^:]+: c5000060 ld1sw {z0.d}, p0/z, \[x3, z0.d, uxtw\]
-+[^:]+: c5000060 ld1sw {z0.d}, p0/z, \[x3, z0.d, uxtw\]
-+[^:]+: c50003e0 ld1sw {z0.d}, p0/z, \[sp, z0.d, uxtw\]
-+[^:]+: c50003e0 ld1sw {z0.d}, p0/z, \[sp, z0.d, uxtw\]
-+[^:]+: c50003e0 ld1sw {z0.d}, p0/z, \[sp, z0.d, uxtw\]
-+[^:]+: c5040000 ld1sw {z0.d}, p0/z, \[x0, z4.d, uxtw\]
-+[^:]+: c5040000 ld1sw {z0.d}, p0/z, \[x0, z4.d, uxtw\]
-+[^:]+: c5040000 ld1sw {z0.d}, p0/z, \[x0, z4.d, uxtw\]
-+[^:]+: c51f0000 ld1sw {z0.d}, p0/z, \[x0, z31.d, uxtw\]
-+[^:]+: c51f0000 ld1sw {z0.d}, p0/z, \[x0, z31.d, uxtw\]
-+[^:]+: c51f0000 ld1sw {z0.d}, p0/z, \[x0, z31.d, uxtw\]
-+[^:]+: c5400000 ld1sw {z0.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5400000 ld1sw {z0.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5400000 ld1sw {z0.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5400000 ld1sw {z0.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5400001 ld1sw {z1.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5400001 ld1sw {z1.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5400001 ld1sw {z1.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5400001 ld1sw {z1.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c540001f ld1sw {z31.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c540001f ld1sw {z31.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c540001f ld1sw {z31.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c540001f ld1sw {z31.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5400800 ld1sw {z0.d}, p2/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5400800 ld1sw {z0.d}, p2/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5400800 ld1sw {z0.d}, p2/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5401c00 ld1sw {z0.d}, p7/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5401c00 ld1sw {z0.d}, p7/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5401c00 ld1sw {z0.d}, p7/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5400060 ld1sw {z0.d}, p0/z, \[x3, z0.d, sxtw\]
-+[^:]+: c5400060 ld1sw {z0.d}, p0/z, \[x3, z0.d, sxtw\]
-+[^:]+: c5400060 ld1sw {z0.d}, p0/z, \[x3, z0.d, sxtw\]
-+[^:]+: c54003e0 ld1sw {z0.d}, p0/z, \[sp, z0.d, sxtw\]
-+[^:]+: c54003e0 ld1sw {z0.d}, p0/z, \[sp, z0.d, sxtw\]
-+[^:]+: c54003e0 ld1sw {z0.d}, p0/z, \[sp, z0.d, sxtw\]
-+[^:]+: c5440000 ld1sw {z0.d}, p0/z, \[x0, z4.d, sxtw\]
-+[^:]+: c5440000 ld1sw {z0.d}, p0/z, \[x0, z4.d, sxtw\]
-+[^:]+: c5440000 ld1sw {z0.d}, p0/z, \[x0, z4.d, sxtw\]
-+[^:]+: c55f0000 ld1sw {z0.d}, p0/z, \[x0, z31.d, sxtw\]
-+[^:]+: c55f0000 ld1sw {z0.d}, p0/z, \[x0, z31.d, sxtw\]
-+[^:]+: c55f0000 ld1sw {z0.d}, p0/z, \[x0, z31.d, sxtw\]
-+[^:]+: c5200000 ld1sw {z0.d}, p0/z, \[x0, z0.d, uxtw #2\]
-+[^:]+: c5200000 ld1sw {z0.d}, p0/z, \[x0, z0.d, uxtw #2\]
-+[^:]+: c5200000 ld1sw {z0.d}, p0/z, \[x0, z0.d, uxtw #2\]
-+[^:]+: c5200001 ld1sw {z1.d}, p0/z, \[x0, z0.d, uxtw #2\]
-+[^:]+: c5200001 ld1sw {z1.d}, p0/z, \[x0, z0.d, uxtw #2\]
-+[^:]+: c5200001 ld1sw {z1.d}, p0/z, \[x0, z0.d, uxtw #2\]
-+[^:]+: c520001f ld1sw {z31.d}, p0/z, \[x0, z0.d, uxtw #2\]
-+[^:]+: c520001f ld1sw {z31.d}, p0/z, \[x0, z0.d, uxtw #2\]
-+[^:]+: c520001f ld1sw {z31.d}, p0/z, \[x0, z0.d, uxtw #2\]
-+[^:]+: c5200800 ld1sw {z0.d}, p2/z, \[x0, z0.d, uxtw #2\]
-+[^:]+: c5200800 ld1sw {z0.d}, p2/z, \[x0, z0.d, uxtw #2\]
-+[^:]+: c5201c00 ld1sw {z0.d}, p7/z, \[x0, z0.d, uxtw #2\]
-+[^:]+: c5201c00 ld1sw {z0.d}, p7/z, \[x0, z0.d, uxtw #2\]
-+[^:]+: c5200060 ld1sw {z0.d}, p0/z, \[x3, z0.d, uxtw #2\]
-+[^:]+: c5200060 ld1sw {z0.d}, p0/z, \[x3, z0.d, uxtw #2\]
-+[^:]+: c52003e0 ld1sw {z0.d}, p0/z, \[sp, z0.d, uxtw #2\]
-+[^:]+: c52003e0 ld1sw {z0.d}, p0/z, \[sp, z0.d, uxtw #2\]
-+[^:]+: c5240000 ld1sw {z0.d}, p0/z, \[x0, z4.d, uxtw #2\]
-+[^:]+: c5240000 ld1sw {z0.d}, p0/z, \[x0, z4.d, uxtw #2\]
-+[^:]+: c53f0000 ld1sw {z0.d}, p0/z, \[x0, z31.d, uxtw #2\]
-+[^:]+: c53f0000 ld1sw {z0.d}, p0/z, \[x0, z31.d, uxtw #2\]
-+[^:]+: c5600000 ld1sw {z0.d}, p0/z, \[x0, z0.d, sxtw #2\]
-+[^:]+: c5600000 ld1sw {z0.d}, p0/z, \[x0, z0.d, sxtw #2\]
-+[^:]+: c5600000 ld1sw {z0.d}, p0/z, \[x0, z0.d, sxtw #2\]
-+[^:]+: c5600001 ld1sw {z1.d}, p0/z, \[x0, z0.d, sxtw #2\]
-+[^:]+: c5600001 ld1sw {z1.d}, p0/z, \[x0, z0.d, sxtw #2\]
-+[^:]+: c5600001 ld1sw {z1.d}, p0/z, \[x0, z0.d, sxtw #2\]
-+[^:]+: c560001f ld1sw {z31.d}, p0/z, \[x0, z0.d, sxtw #2\]
-+[^:]+: c560001f ld1sw {z31.d}, p0/z, \[x0, z0.d, sxtw #2\]
-+[^:]+: c560001f ld1sw {z31.d}, p0/z, \[x0, z0.d, sxtw #2\]
-+[^:]+: c5600800 ld1sw {z0.d}, p2/z, \[x0, z0.d, sxtw #2\]
-+[^:]+: c5600800 ld1sw {z0.d}, p2/z, \[x0, z0.d, sxtw #2\]
-+[^:]+: c5601c00 ld1sw {z0.d}, p7/z, \[x0, z0.d, sxtw #2\]
-+[^:]+: c5601c00 ld1sw {z0.d}, p7/z, \[x0, z0.d, sxtw #2\]
-+[^:]+: c5600060 ld1sw {z0.d}, p0/z, \[x3, z0.d, sxtw #2\]
-+[^:]+: c5600060 ld1sw {z0.d}, p0/z, \[x3, z0.d, sxtw #2\]
-+[^:]+: c56003e0 ld1sw {z0.d}, p0/z, \[sp, z0.d, sxtw #2\]
-+[^:]+: c56003e0 ld1sw {z0.d}, p0/z, \[sp, z0.d, sxtw #2\]
-+[^:]+: c5640000 ld1sw {z0.d}, p0/z, \[x0, z4.d, sxtw #2\]
-+[^:]+: c5640000 ld1sw {z0.d}, p0/z, \[x0, z4.d, sxtw #2\]
-+[^:]+: c57f0000 ld1sw {z0.d}, p0/z, \[x0, z31.d, sxtw #2\]
-+[^:]+: c57f0000 ld1sw {z0.d}, p0/z, \[x0, z31.d, sxtw #2\]
-+[^:]+: c5408000 ld1sw {z0.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c5408000 ld1sw {z0.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c5408000 ld1sw {z0.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c5408000 ld1sw {z0.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c5408001 ld1sw {z1.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c5408001 ld1sw {z1.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c5408001 ld1sw {z1.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c5408001 ld1sw {z1.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c540801f ld1sw {z31.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c540801f ld1sw {z31.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c540801f ld1sw {z31.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c540801f ld1sw {z31.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c5408800 ld1sw {z0.d}, p2/z, \[x0, z0.d\]
-+[^:]+: c5408800 ld1sw {z0.d}, p2/z, \[x0, z0.d\]
-+[^:]+: c5408800 ld1sw {z0.d}, p2/z, \[x0, z0.d\]
-+[^:]+: c5409c00 ld1sw {z0.d}, p7/z, \[x0, z0.d\]
-+[^:]+: c5409c00 ld1sw {z0.d}, p7/z, \[x0, z0.d\]
-+[^:]+: c5409c00 ld1sw {z0.d}, p7/z, \[x0, z0.d\]
-+[^:]+: c5408060 ld1sw {z0.d}, p0/z, \[x3, z0.d\]
-+[^:]+: c5408060 ld1sw {z0.d}, p0/z, \[x3, z0.d\]
-+[^:]+: c5408060 ld1sw {z0.d}, p0/z, \[x3, z0.d\]
-+[^:]+: c54083e0 ld1sw {z0.d}, p0/z, \[sp, z0.d\]
-+[^:]+: c54083e0 ld1sw {z0.d}, p0/z, \[sp, z0.d\]
-+[^:]+: c54083e0 ld1sw {z0.d}, p0/z, \[sp, z0.d\]
-+[^:]+: c5448000 ld1sw {z0.d}, p0/z, \[x0, z4.d\]
-+[^:]+: c5448000 ld1sw {z0.d}, p0/z, \[x0, z4.d\]
-+[^:]+: c5448000 ld1sw {z0.d}, p0/z, \[x0, z4.d\]
-+[^:]+: c55f8000 ld1sw {z0.d}, p0/z, \[x0, z31.d\]
-+[^:]+: c55f8000 ld1sw {z0.d}, p0/z, \[x0, z31.d\]
-+[^:]+: c55f8000 ld1sw {z0.d}, p0/z, \[x0, z31.d\]
-+[^:]+: c5608000 ld1sw {z0.d}, p0/z, \[x0, z0.d, lsl #2\]
-+[^:]+: c5608000 ld1sw {z0.d}, p0/z, \[x0, z0.d, lsl #2\]
-+[^:]+: c5608000 ld1sw {z0.d}, p0/z, \[x0, z0.d, lsl #2\]
-+[^:]+: c5608001 ld1sw {z1.d}, p0/z, \[x0, z0.d, lsl #2\]
-+[^:]+: c5608001 ld1sw {z1.d}, p0/z, \[x0, z0.d, lsl #2\]
-+[^:]+: c5608001 ld1sw {z1.d}, p0/z, \[x0, z0.d, lsl #2\]
-+[^:]+: c560801f ld1sw {z31.d}, p0/z, \[x0, z0.d, lsl #2\]
-+[^:]+: c560801f ld1sw {z31.d}, p0/z, \[x0, z0.d, lsl #2\]
-+[^:]+: c560801f ld1sw {z31.d}, p0/z, \[x0, z0.d, lsl #2\]
-+[^:]+: c5608800 ld1sw {z0.d}, p2/z, \[x0, z0.d, lsl #2\]
-+[^:]+: c5608800 ld1sw {z0.d}, p2/z, \[x0, z0.d, lsl #2\]
-+[^:]+: c5609c00 ld1sw {z0.d}, p7/z, \[x0, z0.d, lsl #2\]
-+[^:]+: c5609c00 ld1sw {z0.d}, p7/z, \[x0, z0.d, lsl #2\]
-+[^:]+: c5608060 ld1sw {z0.d}, p0/z, \[x3, z0.d, lsl #2\]
-+[^:]+: c5608060 ld1sw {z0.d}, p0/z, \[x3, z0.d, lsl #2\]
-+[^:]+: c56083e0 ld1sw {z0.d}, p0/z, \[sp, z0.d, lsl #2\]
-+[^:]+: c56083e0 ld1sw {z0.d}, p0/z, \[sp, z0.d, lsl #2\]
-+[^:]+: c5648000 ld1sw {z0.d}, p0/z, \[x0, z4.d, lsl #2\]
-+[^:]+: c5648000 ld1sw {z0.d}, p0/z, \[x0, z4.d, lsl #2\]
-+[^:]+: c57f8000 ld1sw {z0.d}, p0/z, \[x0, z31.d, lsl #2\]
-+[^:]+: c57f8000 ld1sw {z0.d}, p0/z, \[x0, z31.d, lsl #2\]
-+[^:]+: a480a000 ld1sw {z0.d}, p0/z, \[x0\]
-+[^:]+: a480a000 ld1sw {z0.d}, p0/z, \[x0\]
-+[^:]+: a480a000 ld1sw {z0.d}, p0/z, \[x0\]
-+[^:]+: a480a000 ld1sw {z0.d}, p0/z, \[x0\]
-+[^:]+: a480a000 ld1sw {z0.d}, p0/z, \[x0\]
-+[^:]+: a480a001 ld1sw {z1.d}, p0/z, \[x0\]
-+[^:]+: a480a001 ld1sw {z1.d}, p0/z, \[x0\]
-+[^:]+: a480a001 ld1sw {z1.d}, p0/z, \[x0\]
-+[^:]+: a480a001 ld1sw {z1.d}, p0/z, \[x0\]
-+[^:]+: a480a001 ld1sw {z1.d}, p0/z, \[x0\]
-+[^:]+: a480a01f ld1sw {z31.d}, p0/z, \[x0\]
-+[^:]+: a480a01f ld1sw {z31.d}, p0/z, \[x0\]
-+[^:]+: a480a01f ld1sw {z31.d}, p0/z, \[x0\]
-+[^:]+: a480a01f ld1sw {z31.d}, p0/z, \[x0\]
-+[^:]+: a480a01f ld1sw {z31.d}, p0/z, \[x0\]
-+[^:]+: a480a800 ld1sw {z0.d}, p2/z, \[x0\]
-+[^:]+: a480a800 ld1sw {z0.d}, p2/z, \[x0\]
-+[^:]+: a480a800 ld1sw {z0.d}, p2/z, \[x0\]
-+[^:]+: a480a800 ld1sw {z0.d}, p2/z, \[x0\]
-+[^:]+: a480bc00 ld1sw {z0.d}, p7/z, \[x0\]
-+[^:]+: a480bc00 ld1sw {z0.d}, p7/z, \[x0\]
-+[^:]+: a480bc00 ld1sw {z0.d}, p7/z, \[x0\]
-+[^:]+: a480bc00 ld1sw {z0.d}, p7/z, \[x0\]
-+[^:]+: a480a060 ld1sw {z0.d}, p0/z, \[x3\]
-+[^:]+: a480a060 ld1sw {z0.d}, p0/z, \[x3\]
-+[^:]+: a480a060 ld1sw {z0.d}, p0/z, \[x3\]
-+[^:]+: a480a060 ld1sw {z0.d}, p0/z, \[x3\]
-+[^:]+: a480a3e0 ld1sw {z0.d}, p0/z, \[sp\]
-+[^:]+: a480a3e0 ld1sw {z0.d}, p0/z, \[sp\]
-+[^:]+: a480a3e0 ld1sw {z0.d}, p0/z, \[sp\]
-+[^:]+: a480a3e0 ld1sw {z0.d}, p0/z, \[sp\]
-+[^:]+: a487a000 ld1sw {z0.d}, p0/z, \[x0, #7, mul vl\]
-+[^:]+: a487a000 ld1sw {z0.d}, p0/z, \[x0, #7, mul vl\]
-+[^:]+: a488a000 ld1sw {z0.d}, p0/z, \[x0, #-8, mul vl\]
-+[^:]+: a488a000 ld1sw {z0.d}, p0/z, \[x0, #-8, mul vl\]
-+[^:]+: a489a000 ld1sw {z0.d}, p0/z, \[x0, #-7, mul vl\]
-+[^:]+: a489a000 ld1sw {z0.d}, p0/z, \[x0, #-7, mul vl\]
-+[^:]+: a48fa000 ld1sw {z0.d}, p0/z, \[x0, #-1, mul vl\]
-+[^:]+: a48fa000 ld1sw {z0.d}, p0/z, \[x0, #-1, mul vl\]
-+[^:]+: c5208000 ld1sw {z0.d}, p0/z, \[z0.d\]
-+[^:]+: c5208000 ld1sw {z0.d}, p0/z, \[z0.d\]
-+[^:]+: c5208000 ld1sw {z0.d}, p0/z, \[z0.d\]
-+[^:]+: c5208000 ld1sw {z0.d}, p0/z, \[z0.d\]
-+[^:]+: c5208001 ld1sw {z1.d}, p0/z, \[z0.d\]
-+[^:]+: c5208001 ld1sw {z1.d}, p0/z, \[z0.d\]
-+[^:]+: c5208001 ld1sw {z1.d}, p0/z, \[z0.d\]
-+[^:]+: c5208001 ld1sw {z1.d}, p0/z, \[z0.d\]
-+[^:]+: c520801f ld1sw {z31.d}, p0/z, \[z0.d\]
-+[^:]+: c520801f ld1sw {z31.d}, p0/z, \[z0.d\]
-+[^:]+: c520801f ld1sw {z31.d}, p0/z, \[z0.d\]
-+[^:]+: c520801f ld1sw {z31.d}, p0/z, \[z0.d\]
-+[^:]+: c5208800 ld1sw {z0.d}, p2/z, \[z0.d\]
-+[^:]+: c5208800 ld1sw {z0.d}, p2/z, \[z0.d\]
-+[^:]+: c5208800 ld1sw {z0.d}, p2/z, \[z0.d\]
-+[^:]+: c5209c00 ld1sw {z0.d}, p7/z, \[z0.d\]
-+[^:]+: c5209c00 ld1sw {z0.d}, p7/z, \[z0.d\]
-+[^:]+: c5209c00 ld1sw {z0.d}, p7/z, \[z0.d\]
-+[^:]+: c5208060 ld1sw {z0.d}, p0/z, \[z3.d\]
-+[^:]+: c5208060 ld1sw {z0.d}, p0/z, \[z3.d\]
-+[^:]+: c5208060 ld1sw {z0.d}, p0/z, \[z3.d\]
-+[^:]+: c52083e0 ld1sw {z0.d}, p0/z, \[z31.d\]
-+[^:]+: c52083e0 ld1sw {z0.d}, p0/z, \[z31.d\]
-+[^:]+: c52083e0 ld1sw {z0.d}, p0/z, \[z31.d\]
-+[^:]+: c52f8000 ld1sw {z0.d}, p0/z, \[z0.d, #60\]
-+[^:]+: c52f8000 ld1sw {z0.d}, p0/z, \[z0.d, #60\]
-+[^:]+: c5308000 ld1sw {z0.d}, p0/z, \[z0.d, #64\]
-+[^:]+: c5308000 ld1sw {z0.d}, p0/z, \[z0.d, #64\]
-+[^:]+: c5318000 ld1sw {z0.d}, p0/z, \[z0.d, #68\]
-+[^:]+: c5318000 ld1sw {z0.d}, p0/z, \[z0.d, #68\]
-+[^:]+: c53f8000 ld1sw {z0.d}, p0/z, \[z0.d, #124\]
-+[^:]+: c53f8000 ld1sw {z0.d}, p0/z, \[z0.d, #124\]
-+[^:]+: 85004000 ld1w {z0.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 85004000 ld1w {z0.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 85004000 ld1w {z0.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 85004000 ld1w {z0.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 85004001 ld1w {z1.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 85004001 ld1w {z1.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 85004001 ld1w {z1.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 85004001 ld1w {z1.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 8500401f ld1w {z31.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 8500401f ld1w {z31.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 8500401f ld1w {z31.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 8500401f ld1w {z31.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 85004800 ld1w {z0.s}, p2/z, \[x0, z0.s, uxtw\]
-+[^:]+: 85004800 ld1w {z0.s}, p2/z, \[x0, z0.s, uxtw\]
-+[^:]+: 85004800 ld1w {z0.s}, p2/z, \[x0, z0.s, uxtw\]
-+[^:]+: 85005c00 ld1w {z0.s}, p7/z, \[x0, z0.s, uxtw\]
-+[^:]+: 85005c00 ld1w {z0.s}, p7/z, \[x0, z0.s, uxtw\]
-+[^:]+: 85005c00 ld1w {z0.s}, p7/z, \[x0, z0.s, uxtw\]
-+[^:]+: 85004060 ld1w {z0.s}, p0/z, \[x3, z0.s, uxtw\]
-+[^:]+: 85004060 ld1w {z0.s}, p0/z, \[x3, z0.s, uxtw\]
-+[^:]+: 85004060 ld1w {z0.s}, p0/z, \[x3, z0.s, uxtw\]
-+[^:]+: 850043e0 ld1w {z0.s}, p0/z, \[sp, z0.s, uxtw\]
-+[^:]+: 850043e0 ld1w {z0.s}, p0/z, \[sp, z0.s, uxtw\]
-+[^:]+: 850043e0 ld1w {z0.s}, p0/z, \[sp, z0.s, uxtw\]
-+[^:]+: 85044000 ld1w {z0.s}, p0/z, \[x0, z4.s, uxtw\]
-+[^:]+: 85044000 ld1w {z0.s}, p0/z, \[x0, z4.s, uxtw\]
-+[^:]+: 85044000 ld1w {z0.s}, p0/z, \[x0, z4.s, uxtw\]
-+[^:]+: 851f4000 ld1w {z0.s}, p0/z, \[x0, z31.s, uxtw\]
-+[^:]+: 851f4000 ld1w {z0.s}, p0/z, \[x0, z31.s, uxtw\]
-+[^:]+: 851f4000 ld1w {z0.s}, p0/z, \[x0, z31.s, uxtw\]
-+[^:]+: 85404000 ld1w {z0.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 85404000 ld1w {z0.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 85404000 ld1w {z0.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 85404000 ld1w {z0.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 85404001 ld1w {z1.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 85404001 ld1w {z1.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 85404001 ld1w {z1.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 85404001 ld1w {z1.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 8540401f ld1w {z31.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 8540401f ld1w {z31.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 8540401f ld1w {z31.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 8540401f ld1w {z31.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 85404800 ld1w {z0.s}, p2/z, \[x0, z0.s, sxtw\]
-+[^:]+: 85404800 ld1w {z0.s}, p2/z, \[x0, z0.s, sxtw\]
-+[^:]+: 85404800 ld1w {z0.s}, p2/z, \[x0, z0.s, sxtw\]
-+[^:]+: 85405c00 ld1w {z0.s}, p7/z, \[x0, z0.s, sxtw\]
-+[^:]+: 85405c00 ld1w {z0.s}, p7/z, \[x0, z0.s, sxtw\]
-+[^:]+: 85405c00 ld1w {z0.s}, p7/z, \[x0, z0.s, sxtw\]
-+[^:]+: 85404060 ld1w {z0.s}, p0/z, \[x3, z0.s, sxtw\]
-+[^:]+: 85404060 ld1w {z0.s}, p0/z, \[x3, z0.s, sxtw\]
-+[^:]+: 85404060 ld1w {z0.s}, p0/z, \[x3, z0.s, sxtw\]
-+[^:]+: 854043e0 ld1w {z0.s}, p0/z, \[sp, z0.s, sxtw\]
-+[^:]+: 854043e0 ld1w {z0.s}, p0/z, \[sp, z0.s, sxtw\]
-+[^:]+: 854043e0 ld1w {z0.s}, p0/z, \[sp, z0.s, sxtw\]
-+[^:]+: 85444000 ld1w {z0.s}, p0/z, \[x0, z4.s, sxtw\]
-+[^:]+: 85444000 ld1w {z0.s}, p0/z, \[x0, z4.s, sxtw\]
-+[^:]+: 85444000 ld1w {z0.s}, p0/z, \[x0, z4.s, sxtw\]
-+[^:]+: 855f4000 ld1w {z0.s}, p0/z, \[x0, z31.s, sxtw\]
-+[^:]+: 855f4000 ld1w {z0.s}, p0/z, \[x0, z31.s, sxtw\]
-+[^:]+: 855f4000 ld1w {z0.s}, p0/z, \[x0, z31.s, sxtw\]
-+[^:]+: 85204000 ld1w {z0.s}, p0/z, \[x0, z0.s, uxtw #2\]
-+[^:]+: 85204000 ld1w {z0.s}, p0/z, \[x0, z0.s, uxtw #2\]
-+[^:]+: 85204000 ld1w {z0.s}, p0/z, \[x0, z0.s, uxtw #2\]
-+[^:]+: 85204001 ld1w {z1.s}, p0/z, \[x0, z0.s, uxtw #2\]
-+[^:]+: 85204001 ld1w {z1.s}, p0/z, \[x0, z0.s, uxtw #2\]
-+[^:]+: 85204001 ld1w {z1.s}, p0/z, \[x0, z0.s, uxtw #2\]
-+[^:]+: 8520401f ld1w {z31.s}, p0/z, \[x0, z0.s, uxtw #2\]
-+[^:]+: 8520401f ld1w {z31.s}, p0/z, \[x0, z0.s, uxtw #2\]
-+[^:]+: 8520401f ld1w {z31.s}, p0/z, \[x0, z0.s, uxtw #2\]
-+[^:]+: 85204800 ld1w {z0.s}, p2/z, \[x0, z0.s, uxtw #2\]
-+[^:]+: 85204800 ld1w {z0.s}, p2/z, \[x0, z0.s, uxtw #2\]
-+[^:]+: 85205c00 ld1w {z0.s}, p7/z, \[x0, z0.s, uxtw #2\]
-+[^:]+: 85205c00 ld1w {z0.s}, p7/z, \[x0, z0.s, uxtw #2\]
-+[^:]+: 85204060 ld1w {z0.s}, p0/z, \[x3, z0.s, uxtw #2\]
-+[^:]+: 85204060 ld1w {z0.s}, p0/z, \[x3, z0.s, uxtw #2\]
-+[^:]+: 852043e0 ld1w {z0.s}, p0/z, \[sp, z0.s, uxtw #2\]
-+[^:]+: 852043e0 ld1w {z0.s}, p0/z, \[sp, z0.s, uxtw #2\]
-+[^:]+: 85244000 ld1w {z0.s}, p0/z, \[x0, z4.s, uxtw #2\]
-+[^:]+: 85244000 ld1w {z0.s}, p0/z, \[x0, z4.s, uxtw #2\]
-+[^:]+: 853f4000 ld1w {z0.s}, p0/z, \[x0, z31.s, uxtw #2\]
-+[^:]+: 853f4000 ld1w {z0.s}, p0/z, \[x0, z31.s, uxtw #2\]
-+[^:]+: 85604000 ld1w {z0.s}, p0/z, \[x0, z0.s, sxtw #2\]
-+[^:]+: 85604000 ld1w {z0.s}, p0/z, \[x0, z0.s, sxtw #2\]
-+[^:]+: 85604000 ld1w {z0.s}, p0/z, \[x0, z0.s, sxtw #2\]
-+[^:]+: 85604001 ld1w {z1.s}, p0/z, \[x0, z0.s, sxtw #2\]
-+[^:]+: 85604001 ld1w {z1.s}, p0/z, \[x0, z0.s, sxtw #2\]
-+[^:]+: 85604001 ld1w {z1.s}, p0/z, \[x0, z0.s, sxtw #2\]
-+[^:]+: 8560401f ld1w {z31.s}, p0/z, \[x0, z0.s, sxtw #2\]
-+[^:]+: 8560401f ld1w {z31.s}, p0/z, \[x0, z0.s, sxtw #2\]
-+[^:]+: 8560401f ld1w {z31.s}, p0/z, \[x0, z0.s, sxtw #2\]
-+[^:]+: 85604800 ld1w {z0.s}, p2/z, \[x0, z0.s, sxtw #2\]
-+[^:]+: 85604800 ld1w {z0.s}, p2/z, \[x0, z0.s, sxtw #2\]
-+[^:]+: 85605c00 ld1w {z0.s}, p7/z, \[x0, z0.s, sxtw #2\]
-+[^:]+: 85605c00 ld1w {z0.s}, p7/z, \[x0, z0.s, sxtw #2\]
-+[^:]+: 85604060 ld1w {z0.s}, p0/z, \[x3, z0.s, sxtw #2\]
-+[^:]+: 85604060 ld1w {z0.s}, p0/z, \[x3, z0.s, sxtw #2\]
-+[^:]+: 856043e0 ld1w {z0.s}, p0/z, \[sp, z0.s, sxtw #2\]
-+[^:]+: 856043e0 ld1w {z0.s}, p0/z, \[sp, z0.s, sxtw #2\]
-+[^:]+: 85644000 ld1w {z0.s}, p0/z, \[x0, z4.s, sxtw #2\]
-+[^:]+: 85644000 ld1w {z0.s}, p0/z, \[x0, z4.s, sxtw #2\]
-+[^:]+: 857f4000 ld1w {z0.s}, p0/z, \[x0, z31.s, sxtw #2\]
-+[^:]+: 857f4000 ld1w {z0.s}, p0/z, \[x0, z31.s, sxtw #2\]
-+[^:]+: a5404000 ld1w {z0.s}, p0/z, \[x0, x0, lsl #2\]
-+[^:]+: a5404000 ld1w {z0.s}, p0/z, \[x0, x0, lsl #2\]
-+[^:]+: a5404000 ld1w {z0.s}, p0/z, \[x0, x0, lsl #2\]
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-+[^:]+: a5404001 ld1w {z1.s}, p0/z, \[x0, x0, lsl #2\]
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-+[^:]+: a540401f ld1w {z31.s}, p0/z, \[x0, x0, lsl #2\]
-+[^:]+: a540401f ld1w {z31.s}, p0/z, \[x0, x0, lsl #2\]
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-+[^:]+: a5404800 ld1w {z0.s}, p2/z, \[x0, x0, lsl #2\]
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-+[^:]+: a5405c00 ld1w {z0.s}, p7/z, \[x0, x0, lsl #2\]
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-+[^:]+: a5404060 ld1w {z0.s}, p0/z, \[x3, x0, lsl #2\]
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-+[^:]+: a5444000 ld1w {z0.s}, p0/z, \[x0, x4, lsl #2\]
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-+[^:]+: a55e4000 ld1w {z0.s}, p0/z, \[x0, x30, lsl #2\]
-+[^:]+: a5604000 ld1w {z0.d}, p0/z, \[x0, x0, lsl #2\]
-+[^:]+: a5604000 ld1w {z0.d}, p0/z, \[x0, x0, lsl #2\]
-+[^:]+: a5604000 ld1w {z0.d}, p0/z, \[x0, x0, lsl #2\]
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-+[^:]+: a560401f ld1w {z31.d}, p0/z, \[x0, x0, lsl #2\]
-+[^:]+: a560401f ld1w {z31.d}, p0/z, \[x0, x0, lsl #2\]
-+[^:]+: a560401f ld1w {z31.d}, p0/z, \[x0, x0, lsl #2\]
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-+[^:]+: a5604800 ld1w {z0.d}, p2/z, \[x0, x0, lsl #2\]
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-+[^:]+: a5605c00 ld1w {z0.d}, p7/z, \[x0, x0, lsl #2\]
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-+[^:]+: a5604060 ld1w {z0.d}, p0/z, \[x3, x0, lsl #2\]
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-+[^:]+: a56043e0 ld1w {z0.d}, p0/z, \[sp, x0, lsl #2\]
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-+[^:]+: a5644000 ld1w {z0.d}, p0/z, \[x0, x4, lsl #2\]
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-+[^:]+: a57e4000 ld1w {z0.d}, p0/z, \[x0, x30, lsl #2\]
-+[^:]+: c5004000 ld1w {z0.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c5004000 ld1w {z0.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c5004000 ld1w {z0.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c5004000 ld1w {z0.d}, p0/z, \[x0, z0.d, uxtw\]
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-+[^:]+: c5004001 ld1w {z1.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c5004001 ld1w {z1.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c500401f ld1w {z31.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c500401f ld1w {z31.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c500401f ld1w {z31.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c500401f ld1w {z31.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c5004800 ld1w {z0.d}, p2/z, \[x0, z0.d, uxtw\]
-+[^:]+: c5004800 ld1w {z0.d}, p2/z, \[x0, z0.d, uxtw\]
-+[^:]+: c5004800 ld1w {z0.d}, p2/z, \[x0, z0.d, uxtw\]
-+[^:]+: c5005c00 ld1w {z0.d}, p7/z, \[x0, z0.d, uxtw\]
-+[^:]+: c5005c00 ld1w {z0.d}, p7/z, \[x0, z0.d, uxtw\]
-+[^:]+: c5005c00 ld1w {z0.d}, p7/z, \[x0, z0.d, uxtw\]
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-+[^:]+: c5004060 ld1w {z0.d}, p0/z, \[x3, z0.d, uxtw\]
-+[^:]+: c5004060 ld1w {z0.d}, p0/z, \[x3, z0.d, uxtw\]
-+[^:]+: c50043e0 ld1w {z0.d}, p0/z, \[sp, z0.d, uxtw\]
-+[^:]+: c50043e0 ld1w {z0.d}, p0/z, \[sp, z0.d, uxtw\]
-+[^:]+: c50043e0 ld1w {z0.d}, p0/z, \[sp, z0.d, uxtw\]
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-+[^:]+: c5044000 ld1w {z0.d}, p0/z, \[x0, z4.d, uxtw\]
-+[^:]+: c5044000 ld1w {z0.d}, p0/z, \[x0, z4.d, uxtw\]
-+[^:]+: c51f4000 ld1w {z0.d}, p0/z, \[x0, z31.d, uxtw\]
-+[^:]+: c51f4000 ld1w {z0.d}, p0/z, \[x0, z31.d, uxtw\]
-+[^:]+: c51f4000 ld1w {z0.d}, p0/z, \[x0, z31.d, uxtw\]
-+[^:]+: c5404000 ld1w {z0.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5404000 ld1w {z0.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5404000 ld1w {z0.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5404000 ld1w {z0.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5404001 ld1w {z1.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5404001 ld1w {z1.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5404001 ld1w {z1.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5404001 ld1w {z1.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c540401f ld1w {z31.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c540401f ld1w {z31.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c540401f ld1w {z31.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c540401f ld1w {z31.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5404800 ld1w {z0.d}, p2/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5404800 ld1w {z0.d}, p2/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5404800 ld1w {z0.d}, p2/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5405c00 ld1w {z0.d}, p7/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5405c00 ld1w {z0.d}, p7/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5405c00 ld1w {z0.d}, p7/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5404060 ld1w {z0.d}, p0/z, \[x3, z0.d, sxtw\]
-+[^:]+: c5404060 ld1w {z0.d}, p0/z, \[x3, z0.d, sxtw\]
-+[^:]+: c5404060 ld1w {z0.d}, p0/z, \[x3, z0.d, sxtw\]
-+[^:]+: c54043e0 ld1w {z0.d}, p0/z, \[sp, z0.d, sxtw\]
-+[^:]+: c54043e0 ld1w {z0.d}, p0/z, \[sp, z0.d, sxtw\]
-+[^:]+: c54043e0 ld1w {z0.d}, p0/z, \[sp, z0.d, sxtw\]
-+[^:]+: c5444000 ld1w {z0.d}, p0/z, \[x0, z4.d, sxtw\]
-+[^:]+: c5444000 ld1w {z0.d}, p0/z, \[x0, z4.d, sxtw\]
-+[^:]+: c5444000 ld1w {z0.d}, p0/z, \[x0, z4.d, sxtw\]
-+[^:]+: c55f4000 ld1w {z0.d}, p0/z, \[x0, z31.d, sxtw\]
-+[^:]+: c55f4000 ld1w {z0.d}, p0/z, \[x0, z31.d, sxtw\]
-+[^:]+: c55f4000 ld1w {z0.d}, p0/z, \[x0, z31.d, sxtw\]
-+[^:]+: c5204000 ld1w {z0.d}, p0/z, \[x0, z0.d, uxtw #2\]
-+[^:]+: c5204000 ld1w {z0.d}, p0/z, \[x0, z0.d, uxtw #2\]
-+[^:]+: c5204000 ld1w {z0.d}, p0/z, \[x0, z0.d, uxtw #2\]
-+[^:]+: c5204001 ld1w {z1.d}, p0/z, \[x0, z0.d, uxtw #2\]
-+[^:]+: c5204001 ld1w {z1.d}, p0/z, \[x0, z0.d, uxtw #2\]
-+[^:]+: c5204001 ld1w {z1.d}, p0/z, \[x0, z0.d, uxtw #2\]
-+[^:]+: c520401f ld1w {z31.d}, p0/z, \[x0, z0.d, uxtw #2\]
-+[^:]+: c520401f ld1w {z31.d}, p0/z, \[x0, z0.d, uxtw #2\]
-+[^:]+: c520401f ld1w {z31.d}, p0/z, \[x0, z0.d, uxtw #2\]
-+[^:]+: c5204800 ld1w {z0.d}, p2/z, \[x0, z0.d, uxtw #2\]
-+[^:]+: c5204800 ld1w {z0.d}, p2/z, \[x0, z0.d, uxtw #2\]
-+[^:]+: c5205c00 ld1w {z0.d}, p7/z, \[x0, z0.d, uxtw #2\]
-+[^:]+: c5205c00 ld1w {z0.d}, p7/z, \[x0, z0.d, uxtw #2\]
-+[^:]+: c5204060 ld1w {z0.d}, p0/z, \[x3, z0.d, uxtw #2\]
-+[^:]+: c5204060 ld1w {z0.d}, p0/z, \[x3, z0.d, uxtw #2\]
-+[^:]+: c52043e0 ld1w {z0.d}, p0/z, \[sp, z0.d, uxtw #2\]
-+[^:]+: c52043e0 ld1w {z0.d}, p0/z, \[sp, z0.d, uxtw #2\]
-+[^:]+: c5244000 ld1w {z0.d}, p0/z, \[x0, z4.d, uxtw #2\]
-+[^:]+: c5244000 ld1w {z0.d}, p0/z, \[x0, z4.d, uxtw #2\]
-+[^:]+: c53f4000 ld1w {z0.d}, p0/z, \[x0, z31.d, uxtw #2\]
-+[^:]+: c53f4000 ld1w {z0.d}, p0/z, \[x0, z31.d, uxtw #2\]
-+[^:]+: c5604000 ld1w {z0.d}, p0/z, \[x0, z0.d, sxtw #2\]
-+[^:]+: c5604000 ld1w {z0.d}, p0/z, \[x0, z0.d, sxtw #2\]
-+[^:]+: c5604000 ld1w {z0.d}, p0/z, \[x0, z0.d, sxtw #2\]
-+[^:]+: c5604001 ld1w {z1.d}, p0/z, \[x0, z0.d, sxtw #2\]
-+[^:]+: c5604001 ld1w {z1.d}, p0/z, \[x0, z0.d, sxtw #2\]
-+[^:]+: c5604001 ld1w {z1.d}, p0/z, \[x0, z0.d, sxtw #2\]
-+[^:]+: c560401f ld1w {z31.d}, p0/z, \[x0, z0.d, sxtw #2\]
-+[^:]+: c560401f ld1w {z31.d}, p0/z, \[x0, z0.d, sxtw #2\]
-+[^:]+: c560401f ld1w {z31.d}, p0/z, \[x0, z0.d, sxtw #2\]
-+[^:]+: c5604800 ld1w {z0.d}, p2/z, \[x0, z0.d, sxtw #2\]
-+[^:]+: c5604800 ld1w {z0.d}, p2/z, \[x0, z0.d, sxtw #2\]
-+[^:]+: c5605c00 ld1w {z0.d}, p7/z, \[x0, z0.d, sxtw #2\]
-+[^:]+: c5605c00 ld1w {z0.d}, p7/z, \[x0, z0.d, sxtw #2\]
-+[^:]+: c5604060 ld1w {z0.d}, p0/z, \[x3, z0.d, sxtw #2\]
-+[^:]+: c5604060 ld1w {z0.d}, p0/z, \[x3, z0.d, sxtw #2\]
-+[^:]+: c56043e0 ld1w {z0.d}, p0/z, \[sp, z0.d, sxtw #2\]
-+[^:]+: c56043e0 ld1w {z0.d}, p0/z, \[sp, z0.d, sxtw #2\]
-+[^:]+: c5644000 ld1w {z0.d}, p0/z, \[x0, z4.d, sxtw #2\]
-+[^:]+: c5644000 ld1w {z0.d}, p0/z, \[x0, z4.d, sxtw #2\]
-+[^:]+: c57f4000 ld1w {z0.d}, p0/z, \[x0, z31.d, sxtw #2\]
-+[^:]+: c57f4000 ld1w {z0.d}, p0/z, \[x0, z31.d, sxtw #2\]
-+[^:]+: c540c000 ld1w {z0.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c540c000 ld1w {z0.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c540c000 ld1w {z0.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c540c000 ld1w {z0.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c540c001 ld1w {z1.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c540c001 ld1w {z1.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c540c001 ld1w {z1.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c540c001 ld1w {z1.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c540c01f ld1w {z31.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c540c01f ld1w {z31.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c540c01f ld1w {z31.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c540c01f ld1w {z31.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c540c800 ld1w {z0.d}, p2/z, \[x0, z0.d\]
-+[^:]+: c540c800 ld1w {z0.d}, p2/z, \[x0, z0.d\]
-+[^:]+: c540c800 ld1w {z0.d}, p2/z, \[x0, z0.d\]
-+[^:]+: c540dc00 ld1w {z0.d}, p7/z, \[x0, z0.d\]
-+[^:]+: c540dc00 ld1w {z0.d}, p7/z, \[x0, z0.d\]
-+[^:]+: c540dc00 ld1w {z0.d}, p7/z, \[x0, z0.d\]
-+[^:]+: c540c060 ld1w {z0.d}, p0/z, \[x3, z0.d\]
-+[^:]+: c540c060 ld1w {z0.d}, p0/z, \[x3, z0.d\]
-+[^:]+: c540c060 ld1w {z0.d}, p0/z, \[x3, z0.d\]
-+[^:]+: c540c3e0 ld1w {z0.d}, p0/z, \[sp, z0.d\]
-+[^:]+: c540c3e0 ld1w {z0.d}, p0/z, \[sp, z0.d\]
-+[^:]+: c540c3e0 ld1w {z0.d}, p0/z, \[sp, z0.d\]
-+[^:]+: c544c000 ld1w {z0.d}, p0/z, \[x0, z4.d\]
-+[^:]+: c544c000 ld1w {z0.d}, p0/z, \[x0, z4.d\]
-+[^:]+: c544c000 ld1w {z0.d}, p0/z, \[x0, z4.d\]
-+[^:]+: c55fc000 ld1w {z0.d}, p0/z, \[x0, z31.d\]
-+[^:]+: c55fc000 ld1w {z0.d}, p0/z, \[x0, z31.d\]
-+[^:]+: c55fc000 ld1w {z0.d}, p0/z, \[x0, z31.d\]
-+[^:]+: c560c000 ld1w {z0.d}, p0/z, \[x0, z0.d, lsl #2\]
-+[^:]+: c560c000 ld1w {z0.d}, p0/z, \[x0, z0.d, lsl #2\]
-+[^:]+: c560c000 ld1w {z0.d}, p0/z, \[x0, z0.d, lsl #2\]
-+[^:]+: c560c001 ld1w {z1.d}, p0/z, \[x0, z0.d, lsl #2\]
-+[^:]+: c560c001 ld1w {z1.d}, p0/z, \[x0, z0.d, lsl #2\]
-+[^:]+: c560c001 ld1w {z1.d}, p0/z, \[x0, z0.d, lsl #2\]
-+[^:]+: c560c01f ld1w {z31.d}, p0/z, \[x0, z0.d, lsl #2\]
-+[^:]+: c560c01f ld1w {z31.d}, p0/z, \[x0, z0.d, lsl #2\]
-+[^:]+: c560c01f ld1w {z31.d}, p0/z, \[x0, z0.d, lsl #2\]
-+[^:]+: c560c800 ld1w {z0.d}, p2/z, \[x0, z0.d, lsl #2\]
-+[^:]+: c560c800 ld1w {z0.d}, p2/z, \[x0, z0.d, lsl #2\]
-+[^:]+: c560dc00 ld1w {z0.d}, p7/z, \[x0, z0.d, lsl #2\]
-+[^:]+: c560dc00 ld1w {z0.d}, p7/z, \[x0, z0.d, lsl #2\]
-+[^:]+: c560c060 ld1w {z0.d}, p0/z, \[x3, z0.d, lsl #2\]
-+[^:]+: c560c060 ld1w {z0.d}, p0/z, \[x3, z0.d, lsl #2\]
-+[^:]+: c560c3e0 ld1w {z0.d}, p0/z, \[sp, z0.d, lsl #2\]
-+[^:]+: c560c3e0 ld1w {z0.d}, p0/z, \[sp, z0.d, lsl #2\]
-+[^:]+: c564c000 ld1w {z0.d}, p0/z, \[x0, z4.d, lsl #2\]
-+[^:]+: c564c000 ld1w {z0.d}, p0/z, \[x0, z4.d, lsl #2\]
-+[^:]+: c57fc000 ld1w {z0.d}, p0/z, \[x0, z31.d, lsl #2\]
-+[^:]+: c57fc000 ld1w {z0.d}, p0/z, \[x0, z31.d, lsl #2\]
-+[^:]+: 8520c000 ld1w {z0.s}, p0/z, \[z0.s\]
-+[^:]+: 8520c000 ld1w {z0.s}, p0/z, \[z0.s\]
-+[^:]+: 8520c000 ld1w {z0.s}, p0/z, \[z0.s\]
-+[^:]+: 8520c000 ld1w {z0.s}, p0/z, \[z0.s\]
-+[^:]+: 8520c001 ld1w {z1.s}, p0/z, \[z0.s\]
-+[^:]+: 8520c001 ld1w {z1.s}, p0/z, \[z0.s\]
-+[^:]+: 8520c001 ld1w {z1.s}, p0/z, \[z0.s\]
-+[^:]+: 8520c001 ld1w {z1.s}, p0/z, \[z0.s\]
-+[^:]+: 8520c01f ld1w {z31.s}, p0/z, \[z0.s\]
-+[^:]+: 8520c01f ld1w {z31.s}, p0/z, \[z0.s\]
-+[^:]+: 8520c01f ld1w {z31.s}, p0/z, \[z0.s\]
-+[^:]+: 8520c01f ld1w {z31.s}, p0/z, \[z0.s\]
-+[^:]+: 8520c800 ld1w {z0.s}, p2/z, \[z0.s\]
-+[^:]+: 8520c800 ld1w {z0.s}, p2/z, \[z0.s\]
-+[^:]+: 8520c800 ld1w {z0.s}, p2/z, \[z0.s\]
-+[^:]+: 8520dc00 ld1w {z0.s}, p7/z, \[z0.s\]
-+[^:]+: 8520dc00 ld1w {z0.s}, p7/z, \[z0.s\]
-+[^:]+: 8520dc00 ld1w {z0.s}, p7/z, \[z0.s\]
-+[^:]+: 8520c060 ld1w {z0.s}, p0/z, \[z3.s\]
-+[^:]+: 8520c060 ld1w {z0.s}, p0/z, \[z3.s\]
-+[^:]+: 8520c060 ld1w {z0.s}, p0/z, \[z3.s\]
-+[^:]+: 8520c3e0 ld1w {z0.s}, p0/z, \[z31.s\]
-+[^:]+: 8520c3e0 ld1w {z0.s}, p0/z, \[z31.s\]
-+[^:]+: 8520c3e0 ld1w {z0.s}, p0/z, \[z31.s\]
-+[^:]+: 852fc000 ld1w {z0.s}, p0/z, \[z0.s, #60\]
-+[^:]+: 852fc000 ld1w {z0.s}, p0/z, \[z0.s, #60\]
-+[^:]+: 8530c000 ld1w {z0.s}, p0/z, \[z0.s, #64\]
-+[^:]+: 8530c000 ld1w {z0.s}, p0/z, \[z0.s, #64\]
-+[^:]+: 8531c000 ld1w {z0.s}, p0/z, \[z0.s, #68\]
-+[^:]+: 8531c000 ld1w {z0.s}, p0/z, \[z0.s, #68\]
-+[^:]+: 853fc000 ld1w {z0.s}, p0/z, \[z0.s, #124\]
-+[^:]+: 853fc000 ld1w {z0.s}, p0/z, \[z0.s, #124\]
-+[^:]+: a540a000 ld1w {z0.s}, p0/z, \[x0\]
-+[^:]+: a540a000 ld1w {z0.s}, p0/z, \[x0\]
-+[^:]+: a540a000 ld1w {z0.s}, p0/z, \[x0\]
-+[^:]+: a540a000 ld1w {z0.s}, p0/z, \[x0\]
-+[^:]+: a540a000 ld1w {z0.s}, p0/z, \[x0\]
-+[^:]+: a540a001 ld1w {z1.s}, p0/z, \[x0\]
-+[^:]+: a540a001 ld1w {z1.s}, p0/z, \[x0\]
-+[^:]+: a540a001 ld1w {z1.s}, p0/z, \[x0\]
-+[^:]+: a540a001 ld1w {z1.s}, p0/z, \[x0\]
-+[^:]+: a540a001 ld1w {z1.s}, p0/z, \[x0\]
-+[^:]+: a540a01f ld1w {z31.s}, p0/z, \[x0\]
-+[^:]+: a540a01f ld1w {z31.s}, p0/z, \[x0\]
-+[^:]+: a540a01f ld1w {z31.s}, p0/z, \[x0\]
-+[^:]+: a540a01f ld1w {z31.s}, p0/z, \[x0\]
-+[^:]+: a540a01f ld1w {z31.s}, p0/z, \[x0\]
-+[^:]+: a540a800 ld1w {z0.s}, p2/z, \[x0\]
-+[^:]+: a540a800 ld1w {z0.s}, p2/z, \[x0\]
-+[^:]+: a540a800 ld1w {z0.s}, p2/z, \[x0\]
-+[^:]+: a540a800 ld1w {z0.s}, p2/z, \[x0\]
-+[^:]+: a540bc00 ld1w {z0.s}, p7/z, \[x0\]
-+[^:]+: a540bc00 ld1w {z0.s}, p7/z, \[x0\]
-+[^:]+: a540bc00 ld1w {z0.s}, p7/z, \[x0\]
-+[^:]+: a540bc00 ld1w {z0.s}, p7/z, \[x0\]
-+[^:]+: a540a060 ld1w {z0.s}, p0/z, \[x3\]
-+[^:]+: a540a060 ld1w {z0.s}, p0/z, \[x3\]
-+[^:]+: a540a060 ld1w {z0.s}, p0/z, \[x3\]
-+[^:]+: a540a060 ld1w {z0.s}, p0/z, \[x3\]
-+[^:]+: a540a3e0 ld1w {z0.s}, p0/z, \[sp\]
-+[^:]+: a540a3e0 ld1w {z0.s}, p0/z, \[sp\]
-+[^:]+: a540a3e0 ld1w {z0.s}, p0/z, \[sp\]
-+[^:]+: a540a3e0 ld1w {z0.s}, p0/z, \[sp\]
-+[^:]+: a547a000 ld1w {z0.s}, p0/z, \[x0, #7, mul vl\]
-+[^:]+: a547a000 ld1w {z0.s}, p0/z, \[x0, #7, mul vl\]
-+[^:]+: a548a000 ld1w {z0.s}, p0/z, \[x0, #-8, mul vl\]
-+[^:]+: a548a000 ld1w {z0.s}, p0/z, \[x0, #-8, mul vl\]
-+[^:]+: a549a000 ld1w {z0.s}, p0/z, \[x0, #-7, mul vl\]
-+[^:]+: a549a000 ld1w {z0.s}, p0/z, \[x0, #-7, mul vl\]
-+[^:]+: a54fa000 ld1w {z0.s}, p0/z, \[x0, #-1, mul vl\]
-+[^:]+: a54fa000 ld1w {z0.s}, p0/z, \[x0, #-1, mul vl\]
-+[^:]+: a560a000 ld1w {z0.d}, p0/z, \[x0\]
-+[^:]+: a560a000 ld1w {z0.d}, p0/z, \[x0\]
-+[^:]+: a560a000 ld1w {z0.d}, p0/z, \[x0\]
-+[^:]+: a560a000 ld1w {z0.d}, p0/z, \[x0\]
-+[^:]+: a560a000 ld1w {z0.d}, p0/z, \[x0\]
-+[^:]+: a560a001 ld1w {z1.d}, p0/z, \[x0\]
-+[^:]+: a560a001 ld1w {z1.d}, p0/z, \[x0\]
-+[^:]+: a560a001 ld1w {z1.d}, p0/z, \[x0\]
-+[^:]+: a560a001 ld1w {z1.d}, p0/z, \[x0\]
-+[^:]+: a560a001 ld1w {z1.d}, p0/z, \[x0\]
-+[^:]+: a560a01f ld1w {z31.d}, p0/z, \[x0\]
-+[^:]+: a560a01f ld1w {z31.d}, p0/z, \[x0\]
-+[^:]+: a560a01f ld1w {z31.d}, p0/z, \[x0\]
-+[^:]+: a560a01f ld1w {z31.d}, p0/z, \[x0\]
-+[^:]+: a560a01f ld1w {z31.d}, p0/z, \[x0\]
-+[^:]+: a560a800 ld1w {z0.d}, p2/z, \[x0\]
-+[^:]+: a560a800 ld1w {z0.d}, p2/z, \[x0\]
-+[^:]+: a560a800 ld1w {z0.d}, p2/z, \[x0\]
-+[^:]+: a560a800 ld1w {z0.d}, p2/z, \[x0\]
-+[^:]+: a560bc00 ld1w {z0.d}, p7/z, \[x0\]
-+[^:]+: a560bc00 ld1w {z0.d}, p7/z, \[x0\]
-+[^:]+: a560bc00 ld1w {z0.d}, p7/z, \[x0\]
-+[^:]+: a560bc00 ld1w {z0.d}, p7/z, \[x0\]
-+[^:]+: a560a060 ld1w {z0.d}, p0/z, \[x3\]
-+[^:]+: a560a060 ld1w {z0.d}, p0/z, \[x3\]
-+[^:]+: a560a060 ld1w {z0.d}, p0/z, \[x3\]
-+[^:]+: a560a060 ld1w {z0.d}, p0/z, \[x3\]
-+[^:]+: a560a3e0 ld1w {z0.d}, p0/z, \[sp\]
-+[^:]+: a560a3e0 ld1w {z0.d}, p0/z, \[sp\]
-+[^:]+: a560a3e0 ld1w {z0.d}, p0/z, \[sp\]
-+[^:]+: a560a3e0 ld1w {z0.d}, p0/z, \[sp\]
-+[^:]+: a567a000 ld1w {z0.d}, p0/z, \[x0, #7, mul vl\]
-+[^:]+: a567a000 ld1w {z0.d}, p0/z, \[x0, #7, mul vl\]
-+[^:]+: a568a000 ld1w {z0.d}, p0/z, \[x0, #-8, mul vl\]
-+[^:]+: a568a000 ld1w {z0.d}, p0/z, \[x0, #-8, mul vl\]
-+[^:]+: a569a000 ld1w {z0.d}, p0/z, \[x0, #-7, mul vl\]
-+[^:]+: a569a000 ld1w {z0.d}, p0/z, \[x0, #-7, mul vl\]
-+[^:]+: a56fa000 ld1w {z0.d}, p0/z, \[x0, #-1, mul vl\]
-+[^:]+: a56fa000 ld1w {z0.d}, p0/z, \[x0, #-1, mul vl\]
-+[^:]+: c520c000 ld1w {z0.d}, p0/z, \[z0.d\]
-+[^:]+: c520c000 ld1w {z0.d}, p0/z, \[z0.d\]
-+[^:]+: c520c000 ld1w {z0.d}, p0/z, \[z0.d\]
-+[^:]+: c520c000 ld1w {z0.d}, p0/z, \[z0.d\]
-+[^:]+: c520c001 ld1w {z1.d}, p0/z, \[z0.d\]
-+[^:]+: c520c001 ld1w {z1.d}, p0/z, \[z0.d\]
-+[^:]+: c520c001 ld1w {z1.d}, p0/z, \[z0.d\]
-+[^:]+: c520c001 ld1w {z1.d}, p0/z, \[z0.d\]
-+[^:]+: c520c01f ld1w {z31.d}, p0/z, \[z0.d\]
-+[^:]+: c520c01f ld1w {z31.d}, p0/z, \[z0.d\]
-+[^:]+: c520c01f ld1w {z31.d}, p0/z, \[z0.d\]
-+[^:]+: c520c01f ld1w {z31.d}, p0/z, \[z0.d\]
-+[^:]+: c520c800 ld1w {z0.d}, p2/z, \[z0.d\]
-+[^:]+: c520c800 ld1w {z0.d}, p2/z, \[z0.d\]
-+[^:]+: c520c800 ld1w {z0.d}, p2/z, \[z0.d\]
-+[^:]+: c520dc00 ld1w {z0.d}, p7/z, \[z0.d\]
-+[^:]+: c520dc00 ld1w {z0.d}, p7/z, \[z0.d\]
-+[^:]+: c520dc00 ld1w {z0.d}, p7/z, \[z0.d\]
-+[^:]+: c520c060 ld1w {z0.d}, p0/z, \[z3.d\]
-+[^:]+: c520c060 ld1w {z0.d}, p0/z, \[z3.d\]
-+[^:]+: c520c060 ld1w {z0.d}, p0/z, \[z3.d\]
-+[^:]+: c520c3e0 ld1w {z0.d}, p0/z, \[z31.d\]
-+[^:]+: c520c3e0 ld1w {z0.d}, p0/z, \[z31.d\]
-+[^:]+: c520c3e0 ld1w {z0.d}, p0/z, \[z31.d\]
-+[^:]+: c52fc000 ld1w {z0.d}, p0/z, \[z0.d, #60\]
-+[^:]+: c52fc000 ld1w {z0.d}, p0/z, \[z0.d, #60\]
-+[^:]+: c530c000 ld1w {z0.d}, p0/z, \[z0.d, #64\]
-+[^:]+: c530c000 ld1w {z0.d}, p0/z, \[z0.d, #64\]
-+[^:]+: c531c000 ld1w {z0.d}, p0/z, \[z0.d, #68\]
-+[^:]+: c531c000 ld1w {z0.d}, p0/z, \[z0.d, #68\]
-+[^:]+: c53fc000 ld1w {z0.d}, p0/z, \[z0.d, #124\]
-+[^:]+: c53fc000 ld1w {z0.d}, p0/z, \[z0.d, #124\]
-+[^:]+: a420c000 ld2b {z0.b, z1.b}, p0/z, \[x0, x0\]
-+[^:]+: a420c000 ld2b {z0.b, z1.b}, p0/z, \[x0, x0\]
-+[^:]+: a420c000 ld2b {z0.b, z1.b}, p0/z, \[x0, x0\]
-+[^:]+: a420c000 ld2b {z0.b, z1.b}, p0/z, \[x0, x0\]
-+[^:]+: a420c000 ld2b {z0.b, z1.b}, p0/z, \[x0, x0\]
-+[^:]+: a420c001 ld2b {z1.b, z2.b}, p0/z, \[x0, x0\]
-+[^:]+: a420c001 ld2b {z1.b, z2.b}, p0/z, \[x0, x0\]
-+[^:]+: a420c001 ld2b {z1.b, z2.b}, p0/z, \[x0, x0\]
-+[^:]+: a420c001 ld2b {z1.b, z2.b}, p0/z, \[x0, x0\]
-+[^:]+: a420c001 ld2b {z1.b, z2.b}, p0/z, \[x0, x0\]
-+[^:]+: a420c01f ld2b {z31.b, z0.b}, p0/z, \[x0, x0\]
-+[^:]+: a420c01f ld2b {z31.b, z0.b}, p0/z, \[x0, x0\]
-+[^:]+: a420c01f ld2b {z31.b, z0.b}, p0/z, \[x0, x0\]
-+[^:]+: a420c800 ld2b {z0.b, z1.b}, p2/z, \[x0, x0\]
-+[^:]+: a420c800 ld2b {z0.b, z1.b}, p2/z, \[x0, x0\]
-+[^:]+: a420c800 ld2b {z0.b, z1.b}, p2/z, \[x0, x0\]
-+[^:]+: a420c800 ld2b {z0.b, z1.b}, p2/z, \[x0, x0\]
-+[^:]+: a420c800 ld2b {z0.b, z1.b}, p2/z, \[x0, x0\]
-+[^:]+: a420dc00 ld2b {z0.b, z1.b}, p7/z, \[x0, x0\]
-+[^:]+: a420dc00 ld2b {z0.b, z1.b}, p7/z, \[x0, x0\]
-+[^:]+: a420dc00 ld2b {z0.b, z1.b}, p7/z, \[x0, x0\]
-+[^:]+: a420dc00 ld2b {z0.b, z1.b}, p7/z, \[x0, x0\]
-+[^:]+: a420dc00 ld2b {z0.b, z1.b}, p7/z, \[x0, x0\]
-+[^:]+: a420c060 ld2b {z0.b, z1.b}, p0/z, \[x3, x0\]
-+[^:]+: a420c060 ld2b {z0.b, z1.b}, p0/z, \[x3, x0\]
-+[^:]+: a420c060 ld2b {z0.b, z1.b}, p0/z, \[x3, x0\]
-+[^:]+: a420c060 ld2b {z0.b, z1.b}, p0/z, \[x3, x0\]
-+[^:]+: a420c060 ld2b {z0.b, z1.b}, p0/z, \[x3, x0\]
-+[^:]+: a420c3e0 ld2b {z0.b, z1.b}, p0/z, \[sp, x0\]
-+[^:]+: a420c3e0 ld2b {z0.b, z1.b}, p0/z, \[sp, x0\]
-+[^:]+: a420c3e0 ld2b {z0.b, z1.b}, p0/z, \[sp, x0\]
-+[^:]+: a420c3e0 ld2b {z0.b, z1.b}, p0/z, \[sp, x0\]
-+[^:]+: a420c3e0 ld2b {z0.b, z1.b}, p0/z, \[sp, x0\]
-+[^:]+: a424c000 ld2b {z0.b, z1.b}, p0/z, \[x0, x4\]
-+[^:]+: a424c000 ld2b {z0.b, z1.b}, p0/z, \[x0, x4\]
-+[^:]+: a424c000 ld2b {z0.b, z1.b}, p0/z, \[x0, x4\]
-+[^:]+: a424c000 ld2b {z0.b, z1.b}, p0/z, \[x0, x4\]
-+[^:]+: a424c000 ld2b {z0.b, z1.b}, p0/z, \[x0, x4\]
-+[^:]+: a43ec000 ld2b {z0.b, z1.b}, p0/z, \[x0, x30\]
-+[^:]+: a43ec000 ld2b {z0.b, z1.b}, p0/z, \[x0, x30\]
-+[^:]+: a43ec000 ld2b {z0.b, z1.b}, p0/z, \[x0, x30\]
-+[^:]+: a43ec000 ld2b {z0.b, z1.b}, p0/z, \[x0, x30\]
-+[^:]+: a43ec000 ld2b {z0.b, z1.b}, p0/z, \[x0, x30\]
-+[^:]+: a420e000 ld2b {z0.b, z1.b}, p0/z, \[x0\]
-+[^:]+: a420e000 ld2b {z0.b, z1.b}, p0/z, \[x0\]
-+[^:]+: a420e000 ld2b {z0.b, z1.b}, p0/z, \[x0\]
-+[^:]+: a420e000 ld2b {z0.b, z1.b}, p0/z, \[x0\]
-+[^:]+: a420e000 ld2b {z0.b, z1.b}, p0/z, \[x0\]
-+[^:]+: a420e000 ld2b {z0.b, z1.b}, p0/z, \[x0\]
-+[^:]+: a420e000 ld2b {z0.b, z1.b}, p0/z, \[x0\]
-+[^:]+: a420e001 ld2b {z1.b, z2.b}, p0/z, \[x0\]
-+[^:]+: a420e001 ld2b {z1.b, z2.b}, p0/z, \[x0\]
-+[^:]+: a420e001 ld2b {z1.b, z2.b}, p0/z, \[x0\]
-+[^:]+: a420e001 ld2b {z1.b, z2.b}, p0/z, \[x0\]
-+[^:]+: a420e001 ld2b {z1.b, z2.b}, p0/z, \[x0\]
-+[^:]+: a420e001 ld2b {z1.b, z2.b}, p0/z, \[x0\]
-+[^:]+: a420e001 ld2b {z1.b, z2.b}, p0/z, \[x0\]
-+[^:]+: a420e01f ld2b {z31.b, z0.b}, p0/z, \[x0\]
-+[^:]+: a420e01f ld2b {z31.b, z0.b}, p0/z, \[x0\]
-+[^:]+: a420e01f ld2b {z31.b, z0.b}, p0/z, \[x0\]
-+[^:]+: a420e01f ld2b {z31.b, z0.b}, p0/z, \[x0\]
-+[^:]+: a420e800 ld2b {z0.b, z1.b}, p2/z, \[x0\]
-+[^:]+: a420e800 ld2b {z0.b, z1.b}, p2/z, \[x0\]
-+[^:]+: a420e800 ld2b {z0.b, z1.b}, p2/z, \[x0\]
-+[^:]+: a420e800 ld2b {z0.b, z1.b}, p2/z, \[x0\]
-+[^:]+: a420e800 ld2b {z0.b, z1.b}, p2/z, \[x0\]
-+[^:]+: a420e800 ld2b {z0.b, z1.b}, p2/z, \[x0\]
-+[^:]+: a420e800 ld2b {z0.b, z1.b}, p2/z, \[x0\]
-+[^:]+: a420fc00 ld2b {z0.b, z1.b}, p7/z, \[x0\]
-+[^:]+: a420fc00 ld2b {z0.b, z1.b}, p7/z, \[x0\]
-+[^:]+: a420fc00 ld2b {z0.b, z1.b}, p7/z, \[x0\]
-+[^:]+: a420fc00 ld2b {z0.b, z1.b}, p7/z, \[x0\]
-+[^:]+: a420fc00 ld2b {z0.b, z1.b}, p7/z, \[x0\]
-+[^:]+: a420fc00 ld2b {z0.b, z1.b}, p7/z, \[x0\]
-+[^:]+: a420fc00 ld2b {z0.b, z1.b}, p7/z, \[x0\]
-+[^:]+: a420e060 ld2b {z0.b, z1.b}, p0/z, \[x3\]
-+[^:]+: a420e060 ld2b {z0.b, z1.b}, p0/z, \[x3\]
-+[^:]+: a420e060 ld2b {z0.b, z1.b}, p0/z, \[x3\]
-+[^:]+: a420e060 ld2b {z0.b, z1.b}, p0/z, \[x3\]
-+[^:]+: a420e060 ld2b {z0.b, z1.b}, p0/z, \[x3\]
-+[^:]+: a420e060 ld2b {z0.b, z1.b}, p0/z, \[x3\]
-+[^:]+: a420e060 ld2b {z0.b, z1.b}, p0/z, \[x3\]
-+[^:]+: a420e3e0 ld2b {z0.b, z1.b}, p0/z, \[sp\]
-+[^:]+: a420e3e0 ld2b {z0.b, z1.b}, p0/z, \[sp\]
-+[^:]+: a420e3e0 ld2b {z0.b, z1.b}, p0/z, \[sp\]
-+[^:]+: a420e3e0 ld2b {z0.b, z1.b}, p0/z, \[sp\]
-+[^:]+: a420e3e0 ld2b {z0.b, z1.b}, p0/z, \[sp\]
-+[^:]+: a420e3e0 ld2b {z0.b, z1.b}, p0/z, \[sp\]
-+[^:]+: a420e3e0 ld2b {z0.b, z1.b}, p0/z, \[sp\]
-+[^:]+: a427e000 ld2b {z0.b, z1.b}, p0/z, \[x0, #14, mul vl\]
-+[^:]+: a427e000 ld2b {z0.b, z1.b}, p0/z, \[x0, #14, mul vl\]
-+[^:]+: a427e000 ld2b {z0.b, z1.b}, p0/z, \[x0, #14, mul vl\]
-+[^:]+: a428e000 ld2b {z0.b, z1.b}, p0/z, \[x0, #-16, mul vl\]
-+[^:]+: a428e000 ld2b {z0.b, z1.b}, p0/z, \[x0, #-16, mul vl\]
-+[^:]+: a428e000 ld2b {z0.b, z1.b}, p0/z, \[x0, #-16, mul vl\]
-+[^:]+: a429e000 ld2b {z0.b, z1.b}, p0/z, \[x0, #-14, mul vl\]
-+[^:]+: a429e000 ld2b {z0.b, z1.b}, p0/z, \[x0, #-14, mul vl\]
-+[^:]+: a429e000 ld2b {z0.b, z1.b}, p0/z, \[x0, #-14, mul vl\]
-+[^:]+: a42fe000 ld2b {z0.b, z1.b}, p0/z, \[x0, #-2, mul vl\]
-+[^:]+: a42fe000 ld2b {z0.b, z1.b}, p0/z, \[x0, #-2, mul vl\]
-+[^:]+: a42fe000 ld2b {z0.b, z1.b}, p0/z, \[x0, #-2, mul vl\]
-+[^:]+: a5a0c000 ld2d {z0.d, z1.d}, p0/z, \[x0, x0, lsl #3\]
-+[^:]+: a5a0c000 ld2d {z0.d, z1.d}, p0/z, \[x0, x0, lsl #3\]
-+[^:]+: a5a0c000 ld2d {z0.d, z1.d}, p0/z, \[x0, x0, lsl #3\]
-+[^:]+: a5a0c001 ld2d {z1.d, z2.d}, p0/z, \[x0, x0, lsl #3\]
-+[^:]+: a5a0c001 ld2d {z1.d, z2.d}, p0/z, \[x0, x0, lsl #3\]
-+[^:]+: a5a0c001 ld2d {z1.d, z2.d}, p0/z, \[x0, x0, lsl #3\]
-+[^:]+: a5a0c01f ld2d {z31.d, z0.d}, p0/z, \[x0, x0, lsl #3\]
-+[^:]+: a5a0c01f ld2d {z31.d, z0.d}, p0/z, \[x0, x0, lsl #3\]
-+[^:]+: a5a0c800 ld2d {z0.d, z1.d}, p2/z, \[x0, x0, lsl #3\]
-+[^:]+: a5a0c800 ld2d {z0.d, z1.d}, p2/z, \[x0, x0, lsl #3\]
-+[^:]+: a5a0c800 ld2d {z0.d, z1.d}, p2/z, \[x0, x0, lsl #3\]
-+[^:]+: a5a0dc00 ld2d {z0.d, z1.d}, p7/z, \[x0, x0, lsl #3\]
-+[^:]+: a5a0dc00 ld2d {z0.d, z1.d}, p7/z, \[x0, x0, lsl #3\]
-+[^:]+: a5a0dc00 ld2d {z0.d, z1.d}, p7/z, \[x0, x0, lsl #3\]
-+[^:]+: a5a0c060 ld2d {z0.d, z1.d}, p0/z, \[x3, x0, lsl #3\]
-+[^:]+: a5a0c060 ld2d {z0.d, z1.d}, p0/z, \[x3, x0, lsl #3\]
-+[^:]+: a5a0c060 ld2d {z0.d, z1.d}, p0/z, \[x3, x0, lsl #3\]
-+[^:]+: a5a0c3e0 ld2d {z0.d, z1.d}, p0/z, \[sp, x0, lsl #3\]
-+[^:]+: a5a0c3e0 ld2d {z0.d, z1.d}, p0/z, \[sp, x0, lsl #3\]
-+[^:]+: a5a0c3e0 ld2d {z0.d, z1.d}, p0/z, \[sp, x0, lsl #3\]
-+[^:]+: a5a4c000 ld2d {z0.d, z1.d}, p0/z, \[x0, x4, lsl #3\]
-+[^:]+: a5a4c000 ld2d {z0.d, z1.d}, p0/z, \[x0, x4, lsl #3\]
-+[^:]+: a5a4c000 ld2d {z0.d, z1.d}, p0/z, \[x0, x4, lsl #3\]
-+[^:]+: a5bec000 ld2d {z0.d, z1.d}, p0/z, \[x0, x30, lsl #3\]
-+[^:]+: a5bec000 ld2d {z0.d, z1.d}, p0/z, \[x0, x30, lsl #3\]
-+[^:]+: a5bec000 ld2d {z0.d, z1.d}, p0/z, \[x0, x30, lsl #3\]
-+[^:]+: a5a0e000 ld2d {z0.d, z1.d}, p0/z, \[x0\]
-+[^:]+: a5a0e000 ld2d {z0.d, z1.d}, p0/z, \[x0\]
-+[^:]+: a5a0e000 ld2d {z0.d, z1.d}, p0/z, \[x0\]
-+[^:]+: a5a0e000 ld2d {z0.d, z1.d}, p0/z, \[x0\]
-+[^:]+: a5a0e000 ld2d {z0.d, z1.d}, p0/z, \[x0\]
-+[^:]+: a5a0e000 ld2d {z0.d, z1.d}, p0/z, \[x0\]
-+[^:]+: a5a0e000 ld2d {z0.d, z1.d}, p0/z, \[x0\]
-+[^:]+: a5a0e001 ld2d {z1.d, z2.d}, p0/z, \[x0\]
-+[^:]+: a5a0e001 ld2d {z1.d, z2.d}, p0/z, \[x0\]
-+[^:]+: a5a0e001 ld2d {z1.d, z2.d}, p0/z, \[x0\]
-+[^:]+: a5a0e001 ld2d {z1.d, z2.d}, p0/z, \[x0\]
-+[^:]+: a5a0e001 ld2d {z1.d, z2.d}, p0/z, \[x0\]
-+[^:]+: a5a0e001 ld2d {z1.d, z2.d}, p0/z, \[x0\]
-+[^:]+: a5a0e001 ld2d {z1.d, z2.d}, p0/z, \[x0\]
-+[^:]+: a5a0e01f ld2d {z31.d, z0.d}, p0/z, \[x0\]
-+[^:]+: a5a0e01f ld2d {z31.d, z0.d}, p0/z, \[x0\]
-+[^:]+: a5a0e01f ld2d {z31.d, z0.d}, p0/z, \[x0\]
-+[^:]+: a5a0e01f ld2d {z31.d, z0.d}, p0/z, \[x0\]
-+[^:]+: a5a0e800 ld2d {z0.d, z1.d}, p2/z, \[x0\]
-+[^:]+: a5a0e800 ld2d {z0.d, z1.d}, p2/z, \[x0\]
-+[^:]+: a5a0e800 ld2d {z0.d, z1.d}, p2/z, \[x0\]
-+[^:]+: a5a0e800 ld2d {z0.d, z1.d}, p2/z, \[x0\]
-+[^:]+: a5a0e800 ld2d {z0.d, z1.d}, p2/z, \[x0\]
-+[^:]+: a5a0e800 ld2d {z0.d, z1.d}, p2/z, \[x0\]
-+[^:]+: a5a0e800 ld2d {z0.d, z1.d}, p2/z, \[x0\]
-+[^:]+: a5a0fc00 ld2d {z0.d, z1.d}, p7/z, \[x0\]
-+[^:]+: a5a0fc00 ld2d {z0.d, z1.d}, p7/z, \[x0\]
-+[^:]+: a5a0fc00 ld2d {z0.d, z1.d}, p7/z, \[x0\]
-+[^:]+: a5a0fc00 ld2d {z0.d, z1.d}, p7/z, \[x0\]
-+[^:]+: a5a0fc00 ld2d {z0.d, z1.d}, p7/z, \[x0\]
-+[^:]+: a5a0fc00 ld2d {z0.d, z1.d}, p7/z, \[x0\]
-+[^:]+: a5a0fc00 ld2d {z0.d, z1.d}, p7/z, \[x0\]
-+[^:]+: a5a0e060 ld2d {z0.d, z1.d}, p0/z, \[x3\]
-+[^:]+: a5a0e060 ld2d {z0.d, z1.d}, p0/z, \[x3\]
-+[^:]+: a5a0e060 ld2d {z0.d, z1.d}, p0/z, \[x3\]
-+[^:]+: a5a0e060 ld2d {z0.d, z1.d}, p0/z, \[x3\]
-+[^:]+: a5a0e060 ld2d {z0.d, z1.d}, p0/z, \[x3\]
-+[^:]+: a5a0e060 ld2d {z0.d, z1.d}, p0/z, \[x3\]
-+[^:]+: a5a0e060 ld2d {z0.d, z1.d}, p0/z, \[x3\]
-+[^:]+: a5a0e3e0 ld2d {z0.d, z1.d}, p0/z, \[sp\]
-+[^:]+: a5a0e3e0 ld2d {z0.d, z1.d}, p0/z, \[sp\]
-+[^:]+: a5a0e3e0 ld2d {z0.d, z1.d}, p0/z, \[sp\]
-+[^:]+: a5a0e3e0 ld2d {z0.d, z1.d}, p0/z, \[sp\]
-+[^:]+: a5a0e3e0 ld2d {z0.d, z1.d}, p0/z, \[sp\]
-+[^:]+: a5a0e3e0 ld2d {z0.d, z1.d}, p0/z, \[sp\]
-+[^:]+: a5a0e3e0 ld2d {z0.d, z1.d}, p0/z, \[sp\]
-+[^:]+: a5a7e000 ld2d {z0.d, z1.d}, p0/z, \[x0, #14, mul vl\]
-+[^:]+: a5a7e000 ld2d {z0.d, z1.d}, p0/z, \[x0, #14, mul vl\]
-+[^:]+: a5a7e000 ld2d {z0.d, z1.d}, p0/z, \[x0, #14, mul vl\]
-+[^:]+: a5a8e000 ld2d {z0.d, z1.d}, p0/z, \[x0, #-16, mul vl\]
-+[^:]+: a5a8e000 ld2d {z0.d, z1.d}, p0/z, \[x0, #-16, mul vl\]
-+[^:]+: a5a8e000 ld2d {z0.d, z1.d}, p0/z, \[x0, #-16, mul vl\]
-+[^:]+: a5a9e000 ld2d {z0.d, z1.d}, p0/z, \[x0, #-14, mul vl\]
-+[^:]+: a5a9e000 ld2d {z0.d, z1.d}, p0/z, \[x0, #-14, mul vl\]
-+[^:]+: a5a9e000 ld2d {z0.d, z1.d}, p0/z, \[x0, #-14, mul vl\]
-+[^:]+: a5afe000 ld2d {z0.d, z1.d}, p0/z, \[x0, #-2, mul vl\]
-+[^:]+: a5afe000 ld2d {z0.d, z1.d}, p0/z, \[x0, #-2, mul vl\]
-+[^:]+: a5afe000 ld2d {z0.d, z1.d}, p0/z, \[x0, #-2, mul vl\]
-+[^:]+: a4a0c000 ld2h {z0.h, z1.h}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a4a0c000 ld2h {z0.h, z1.h}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a4a0c000 ld2h {z0.h, z1.h}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a4a0c001 ld2h {z1.h, z2.h}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a4a0c001 ld2h {z1.h, z2.h}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a4a0c001 ld2h {z1.h, z2.h}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a4a0c01f ld2h {z31.h, z0.h}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a4a0c01f ld2h {z31.h, z0.h}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a4a0c800 ld2h {z0.h, z1.h}, p2/z, \[x0, x0, lsl #1\]
-+[^:]+: a4a0c800 ld2h {z0.h, z1.h}, p2/z, \[x0, x0, lsl #1\]
-+[^:]+: a4a0c800 ld2h {z0.h, z1.h}, p2/z, \[x0, x0, lsl #1\]
-+[^:]+: a4a0dc00 ld2h {z0.h, z1.h}, p7/z, \[x0, x0, lsl #1\]
-+[^:]+: a4a0dc00 ld2h {z0.h, z1.h}, p7/z, \[x0, x0, lsl #1\]
-+[^:]+: a4a0dc00 ld2h {z0.h, z1.h}, p7/z, \[x0, x0, lsl #1\]
-+[^:]+: a4a0c060 ld2h {z0.h, z1.h}, p0/z, \[x3, x0, lsl #1\]
-+[^:]+: a4a0c060 ld2h {z0.h, z1.h}, p0/z, \[x3, x0, lsl #1\]
-+[^:]+: a4a0c060 ld2h {z0.h, z1.h}, p0/z, \[x3, x0, lsl #1\]
-+[^:]+: a4a0c3e0 ld2h {z0.h, z1.h}, p0/z, \[sp, x0, lsl #1\]
-+[^:]+: a4a0c3e0 ld2h {z0.h, z1.h}, p0/z, \[sp, x0, lsl #1\]
-+[^:]+: a4a0c3e0 ld2h {z0.h, z1.h}, p0/z, \[sp, x0, lsl #1\]
-+[^:]+: a4a4c000 ld2h {z0.h, z1.h}, p0/z, \[x0, x4, lsl #1\]
-+[^:]+: a4a4c000 ld2h {z0.h, z1.h}, p0/z, \[x0, x4, lsl #1\]
-+[^:]+: a4a4c000 ld2h {z0.h, z1.h}, p0/z, \[x0, x4, lsl #1\]
-+[^:]+: a4bec000 ld2h {z0.h, z1.h}, p0/z, \[x0, x30, lsl #1\]
-+[^:]+: a4bec000 ld2h {z0.h, z1.h}, p0/z, \[x0, x30, lsl #1\]
-+[^:]+: a4bec000 ld2h {z0.h, z1.h}, p0/z, \[x0, x30, lsl #1\]
-+[^:]+: a4a0e000 ld2h {z0.h, z1.h}, p0/z, \[x0\]
-+[^:]+: a4a0e000 ld2h {z0.h, z1.h}, p0/z, \[x0\]
-+[^:]+: a4a0e000 ld2h {z0.h, z1.h}, p0/z, \[x0\]
-+[^:]+: a4a0e000 ld2h {z0.h, z1.h}, p0/z, \[x0\]
-+[^:]+: a4a0e000 ld2h {z0.h, z1.h}, p0/z, \[x0\]
-+[^:]+: a4a0e000 ld2h {z0.h, z1.h}, p0/z, \[x0\]
-+[^:]+: a4a0e000 ld2h {z0.h, z1.h}, p0/z, \[x0\]
-+[^:]+: a4a0e001 ld2h {z1.h, z2.h}, p0/z, \[x0\]
-+[^:]+: a4a0e001 ld2h {z1.h, z2.h}, p0/z, \[x0\]
-+[^:]+: a4a0e001 ld2h {z1.h, z2.h}, p0/z, \[x0\]
-+[^:]+: a4a0e001 ld2h {z1.h, z2.h}, p0/z, \[x0\]
-+[^:]+: a4a0e001 ld2h {z1.h, z2.h}, p0/z, \[x0\]
-+[^:]+: a4a0e001 ld2h {z1.h, z2.h}, p0/z, \[x0\]
-+[^:]+: a4a0e001 ld2h {z1.h, z2.h}, p0/z, \[x0\]
-+[^:]+: a4a0e01f ld2h {z31.h, z0.h}, p0/z, \[x0\]
-+[^:]+: a4a0e01f ld2h {z31.h, z0.h}, p0/z, \[x0\]
-+[^:]+: a4a0e01f ld2h {z31.h, z0.h}, p0/z, \[x0\]
-+[^:]+: a4a0e01f ld2h {z31.h, z0.h}, p0/z, \[x0\]
-+[^:]+: a4a0e800 ld2h {z0.h, z1.h}, p2/z, \[x0\]
-+[^:]+: a4a0e800 ld2h {z0.h, z1.h}, p2/z, \[x0\]
-+[^:]+: a4a0e800 ld2h {z0.h, z1.h}, p2/z, \[x0\]
-+[^:]+: a4a0e800 ld2h {z0.h, z1.h}, p2/z, \[x0\]
-+[^:]+: a4a0e800 ld2h {z0.h, z1.h}, p2/z, \[x0\]
-+[^:]+: a4a0e800 ld2h {z0.h, z1.h}, p2/z, \[x0\]
-+[^:]+: a4a0e800 ld2h {z0.h, z1.h}, p2/z, \[x0\]
-+[^:]+: a4a0fc00 ld2h {z0.h, z1.h}, p7/z, \[x0\]
-+[^:]+: a4a0fc00 ld2h {z0.h, z1.h}, p7/z, \[x0\]
-+[^:]+: a4a0fc00 ld2h {z0.h, z1.h}, p7/z, \[x0\]
-+[^:]+: a4a0fc00 ld2h {z0.h, z1.h}, p7/z, \[x0\]
-+[^:]+: a4a0fc00 ld2h {z0.h, z1.h}, p7/z, \[x0\]
-+[^:]+: a4a0fc00 ld2h {z0.h, z1.h}, p7/z, \[x0\]
-+[^:]+: a4a0fc00 ld2h {z0.h, z1.h}, p7/z, \[x0\]
-+[^:]+: a4a0e060 ld2h {z0.h, z1.h}, p0/z, \[x3\]
-+[^:]+: a4a0e060 ld2h {z0.h, z1.h}, p0/z, \[x3\]
-+[^:]+: a4a0e060 ld2h {z0.h, z1.h}, p0/z, \[x3\]
-+[^:]+: a4a0e060 ld2h {z0.h, z1.h}, p0/z, \[x3\]
-+[^:]+: a4a0e060 ld2h {z0.h, z1.h}, p0/z, \[x3\]
-+[^:]+: a4a0e060 ld2h {z0.h, z1.h}, p0/z, \[x3\]
-+[^:]+: a4a0e060 ld2h {z0.h, z1.h}, p0/z, \[x3\]
-+[^:]+: a4a0e3e0 ld2h {z0.h, z1.h}, p0/z, \[sp\]
-+[^:]+: a4a0e3e0 ld2h {z0.h, z1.h}, p0/z, \[sp\]
-+[^:]+: a4a0e3e0 ld2h {z0.h, z1.h}, p0/z, \[sp\]
-+[^:]+: a4a0e3e0 ld2h {z0.h, z1.h}, p0/z, \[sp\]
-+[^:]+: a4a0e3e0 ld2h {z0.h, z1.h}, p0/z, \[sp\]
-+[^:]+: a4a0e3e0 ld2h {z0.h, z1.h}, p0/z, \[sp\]
-+[^:]+: a4a0e3e0 ld2h {z0.h, z1.h}, p0/z, \[sp\]
-+[^:]+: a4a7e000 ld2h {z0.h, z1.h}, p0/z, \[x0, #14, mul vl\]
-+[^:]+: a4a7e000 ld2h {z0.h, z1.h}, p0/z, \[x0, #14, mul vl\]
-+[^:]+: a4a7e000 ld2h {z0.h, z1.h}, p0/z, \[x0, #14, mul vl\]
-+[^:]+: a4a8e000 ld2h {z0.h, z1.h}, p0/z, \[x0, #-16, mul vl\]
-+[^:]+: a4a8e000 ld2h {z0.h, z1.h}, p0/z, \[x0, #-16, mul vl\]
-+[^:]+: a4a8e000 ld2h {z0.h, z1.h}, p0/z, \[x0, #-16, mul vl\]
-+[^:]+: a4a9e000 ld2h {z0.h, z1.h}, p0/z, \[x0, #-14, mul vl\]
-+[^:]+: a4a9e000 ld2h {z0.h, z1.h}, p0/z, \[x0, #-14, mul vl\]
-+[^:]+: a4a9e000 ld2h {z0.h, z1.h}, p0/z, \[x0, #-14, mul vl\]
-+[^:]+: a4afe000 ld2h {z0.h, z1.h}, p0/z, \[x0, #-2, mul vl\]
-+[^:]+: a4afe000 ld2h {z0.h, z1.h}, p0/z, \[x0, #-2, mul vl\]
-+[^:]+: a4afe000 ld2h {z0.h, z1.h}, p0/z, \[x0, #-2, mul vl\]
-+[^:]+: a520c000 ld2w {z0.s, z1.s}, p0/z, \[x0, x0, lsl #2\]
-+[^:]+: a520c000 ld2w {z0.s, z1.s}, p0/z, \[x0, x0, lsl #2\]
-+[^:]+: a520c000 ld2w {z0.s, z1.s}, p0/z, \[x0, x0, lsl #2\]
-+[^:]+: a520c001 ld2w {z1.s, z2.s}, p0/z, \[x0, x0, lsl #2\]
-+[^:]+: a520c001 ld2w {z1.s, z2.s}, p0/z, \[x0, x0, lsl #2\]
-+[^:]+: a520c001 ld2w {z1.s, z2.s}, p0/z, \[x0, x0, lsl #2\]
-+[^:]+: a520c01f ld2w {z31.s, z0.s}, p0/z, \[x0, x0, lsl #2\]
-+[^:]+: a520c01f ld2w {z31.s, z0.s}, p0/z, \[x0, x0, lsl #2\]
-+[^:]+: a520c800 ld2w {z0.s, z1.s}, p2/z, \[x0, x0, lsl #2\]
-+[^:]+: a520c800 ld2w {z0.s, z1.s}, p2/z, \[x0, x0, lsl #2\]
-+[^:]+: a520c800 ld2w {z0.s, z1.s}, p2/z, \[x0, x0, lsl #2\]
-+[^:]+: a520dc00 ld2w {z0.s, z1.s}, p7/z, \[x0, x0, lsl #2\]
-+[^:]+: a520dc00 ld2w {z0.s, z1.s}, p7/z, \[x0, x0, lsl #2\]
-+[^:]+: a520dc00 ld2w {z0.s, z1.s}, p7/z, \[x0, x0, lsl #2\]
-+[^:]+: a520c060 ld2w {z0.s, z1.s}, p0/z, \[x3, x0, lsl #2\]
-+[^:]+: a520c060 ld2w {z0.s, z1.s}, p0/z, \[x3, x0, lsl #2\]
-+[^:]+: a520c060 ld2w {z0.s, z1.s}, p0/z, \[x3, x0, lsl #2\]
-+[^:]+: a520c3e0 ld2w {z0.s, z1.s}, p0/z, \[sp, x0, lsl #2\]
-+[^:]+: a520c3e0 ld2w {z0.s, z1.s}, p0/z, \[sp, x0, lsl #2\]
-+[^:]+: a520c3e0 ld2w {z0.s, z1.s}, p0/z, \[sp, x0, lsl #2\]
-+[^:]+: a524c000 ld2w {z0.s, z1.s}, p0/z, \[x0, x4, lsl #2\]
-+[^:]+: a524c000 ld2w {z0.s, z1.s}, p0/z, \[x0, x4, lsl #2\]
-+[^:]+: a524c000 ld2w {z0.s, z1.s}, p0/z, \[x0, x4, lsl #2\]
-+[^:]+: a53ec000 ld2w {z0.s, z1.s}, p0/z, \[x0, x30, lsl #2\]
-+[^:]+: a53ec000 ld2w {z0.s, z1.s}, p0/z, \[x0, x30, lsl #2\]
-+[^:]+: a53ec000 ld2w {z0.s, z1.s}, p0/z, \[x0, x30, lsl #2\]
-+[^:]+: a520e000 ld2w {z0.s, z1.s}, p0/z, \[x0\]
-+[^:]+: a520e000 ld2w {z0.s, z1.s}, p0/z, \[x0\]
-+[^:]+: a520e000 ld2w {z0.s, z1.s}, p0/z, \[x0\]
-+[^:]+: a520e000 ld2w {z0.s, z1.s}, p0/z, \[x0\]
-+[^:]+: a520e000 ld2w {z0.s, z1.s}, p0/z, \[x0\]
-+[^:]+: a520e000 ld2w {z0.s, z1.s}, p0/z, \[x0\]
-+[^:]+: a520e000 ld2w {z0.s, z1.s}, p0/z, \[x0\]
-+[^:]+: a520e001 ld2w {z1.s, z2.s}, p0/z, \[x0\]
-+[^:]+: a520e001 ld2w {z1.s, z2.s}, p0/z, \[x0\]
-+[^:]+: a520e001 ld2w {z1.s, z2.s}, p0/z, \[x0\]
-+[^:]+: a520e001 ld2w {z1.s, z2.s}, p0/z, \[x0\]
-+[^:]+: a520e001 ld2w {z1.s, z2.s}, p0/z, \[x0\]
-+[^:]+: a520e001 ld2w {z1.s, z2.s}, p0/z, \[x0\]
-+[^:]+: a520e001 ld2w {z1.s, z2.s}, p0/z, \[x0\]
-+[^:]+: a520e01f ld2w {z31.s, z0.s}, p0/z, \[x0\]
-+[^:]+: a520e01f ld2w {z31.s, z0.s}, p0/z, \[x0\]
-+[^:]+: a520e01f ld2w {z31.s, z0.s}, p0/z, \[x0\]
-+[^:]+: a520e01f ld2w {z31.s, z0.s}, p0/z, \[x0\]
-+[^:]+: a520e800 ld2w {z0.s, z1.s}, p2/z, \[x0\]
-+[^:]+: a520e800 ld2w {z0.s, z1.s}, p2/z, \[x0\]
-+[^:]+: a520e800 ld2w {z0.s, z1.s}, p2/z, \[x0\]
-+[^:]+: a520e800 ld2w {z0.s, z1.s}, p2/z, \[x0\]
-+[^:]+: a520e800 ld2w {z0.s, z1.s}, p2/z, \[x0\]
-+[^:]+: a520e800 ld2w {z0.s, z1.s}, p2/z, \[x0\]
-+[^:]+: a520e800 ld2w {z0.s, z1.s}, p2/z, \[x0\]
-+[^:]+: a520fc00 ld2w {z0.s, z1.s}, p7/z, \[x0\]
-+[^:]+: a520fc00 ld2w {z0.s, z1.s}, p7/z, \[x0\]
-+[^:]+: a520fc00 ld2w {z0.s, z1.s}, p7/z, \[x0\]
-+[^:]+: a520fc00 ld2w {z0.s, z1.s}, p7/z, \[x0\]
-+[^:]+: a520fc00 ld2w {z0.s, z1.s}, p7/z, \[x0\]
-+[^:]+: a520fc00 ld2w {z0.s, z1.s}, p7/z, \[x0\]
-+[^:]+: a520fc00 ld2w {z0.s, z1.s}, p7/z, \[x0\]
-+[^:]+: a520e060 ld2w {z0.s, z1.s}, p0/z, \[x3\]
-+[^:]+: a520e060 ld2w {z0.s, z1.s}, p0/z, \[x3\]
-+[^:]+: a520e060 ld2w {z0.s, z1.s}, p0/z, \[x3\]
-+[^:]+: a520e060 ld2w {z0.s, z1.s}, p0/z, \[x3\]
-+[^:]+: a520e060 ld2w {z0.s, z1.s}, p0/z, \[x3\]
-+[^:]+: a520e060 ld2w {z0.s, z1.s}, p0/z, \[x3\]
-+[^:]+: a520e060 ld2w {z0.s, z1.s}, p0/z, \[x3\]
-+[^:]+: a520e3e0 ld2w {z0.s, z1.s}, p0/z, \[sp\]
-+[^:]+: a520e3e0 ld2w {z0.s, z1.s}, p0/z, \[sp\]
-+[^:]+: a520e3e0 ld2w {z0.s, z1.s}, p0/z, \[sp\]
-+[^:]+: a520e3e0 ld2w {z0.s, z1.s}, p0/z, \[sp\]
-+[^:]+: a520e3e0 ld2w {z0.s, z1.s}, p0/z, \[sp\]
-+[^:]+: a520e3e0 ld2w {z0.s, z1.s}, p0/z, \[sp\]
-+[^:]+: a520e3e0 ld2w {z0.s, z1.s}, p0/z, \[sp\]
-+[^:]+: a527e000 ld2w {z0.s, z1.s}, p0/z, \[x0, #14, mul vl\]
-+[^:]+: a527e000 ld2w {z0.s, z1.s}, p0/z, \[x0, #14, mul vl\]
-+[^:]+: a527e000 ld2w {z0.s, z1.s}, p0/z, \[x0, #14, mul vl\]
-+[^:]+: a528e000 ld2w {z0.s, z1.s}, p0/z, \[x0, #-16, mul vl\]
-+[^:]+: a528e000 ld2w {z0.s, z1.s}, p0/z, \[x0, #-16, mul vl\]
-+[^:]+: a528e000 ld2w {z0.s, z1.s}, p0/z, \[x0, #-16, mul vl\]
-+[^:]+: a529e000 ld2w {z0.s, z1.s}, p0/z, \[x0, #-14, mul vl\]
-+[^:]+: a529e000 ld2w {z0.s, z1.s}, p0/z, \[x0, #-14, mul vl\]
-+[^:]+: a529e000 ld2w {z0.s, z1.s}, p0/z, \[x0, #-14, mul vl\]
-+[^:]+: a52fe000 ld2w {z0.s, z1.s}, p0/z, \[x0, #-2, mul vl\]
-+[^:]+: a52fe000 ld2w {z0.s, z1.s}, p0/z, \[x0, #-2, mul vl\]
-+[^:]+: a52fe000 ld2w {z0.s, z1.s}, p0/z, \[x0, #-2, mul vl\]
-+[^:]+: a440c000 ld3b {z0.b-z2.b}, p0/z, \[x0, x0\]
-+[^:]+: a440c000 ld3b {z0.b-z2.b}, p0/z, \[x0, x0\]
-+[^:]+: a440c000 ld3b {z0.b-z2.b}, p0/z, \[x0, x0\]
-+[^:]+: a440c000 ld3b {z0.b-z2.b}, p0/z, \[x0, x0\]
-+[^:]+: a440c000 ld3b {z0.b-z2.b}, p0/z, \[x0, x0\]
-+[^:]+: a440c001 ld3b {z1.b-z3.b}, p0/z, \[x0, x0\]
-+[^:]+: a440c001 ld3b {z1.b-z3.b}, p0/z, \[x0, x0\]
-+[^:]+: a440c001 ld3b {z1.b-z3.b}, p0/z, \[x0, x0\]
-+[^:]+: a440c001 ld3b {z1.b-z3.b}, p0/z, \[x0, x0\]
-+[^:]+: a440c001 ld3b {z1.b-z3.b}, p0/z, \[x0, x0\]
-+[^:]+: a440c01f ld3b {z31.b, z0.b, z1.b}, p0/z, \[x0, x0\]
-+[^:]+: a440c01f ld3b {z31.b, z0.b, z1.b}, p0/z, \[x0, x0\]
-+[^:]+: a440c01f ld3b {z31.b, z0.b, z1.b}, p0/z, \[x0, x0\]
-+[^:]+: a440c800 ld3b {z0.b-z2.b}, p2/z, \[x0, x0\]
-+[^:]+: a440c800 ld3b {z0.b-z2.b}, p2/z, \[x0, x0\]
-+[^:]+: a440c800 ld3b {z0.b-z2.b}, p2/z, \[x0, x0\]
-+[^:]+: a440c800 ld3b {z0.b-z2.b}, p2/z, \[x0, x0\]
-+[^:]+: a440c800 ld3b {z0.b-z2.b}, p2/z, \[x0, x0\]
-+[^:]+: a440dc00 ld3b {z0.b-z2.b}, p7/z, \[x0, x0\]
-+[^:]+: a440dc00 ld3b {z0.b-z2.b}, p7/z, \[x0, x0\]
-+[^:]+: a440dc00 ld3b {z0.b-z2.b}, p7/z, \[x0, x0\]
-+[^:]+: a440dc00 ld3b {z0.b-z2.b}, p7/z, \[x0, x0\]
-+[^:]+: a440dc00 ld3b {z0.b-z2.b}, p7/z, \[x0, x0\]
-+[^:]+: a440c060 ld3b {z0.b-z2.b}, p0/z, \[x3, x0\]
-+[^:]+: a440c060 ld3b {z0.b-z2.b}, p0/z, \[x3, x0\]
-+[^:]+: a440c060 ld3b {z0.b-z2.b}, p0/z, \[x3, x0\]
-+[^:]+: a440c060 ld3b {z0.b-z2.b}, p0/z, \[x3, x0\]
-+[^:]+: a440c060 ld3b {z0.b-z2.b}, p0/z, \[x3, x0\]
-+[^:]+: a440c3e0 ld3b {z0.b-z2.b}, p0/z, \[sp, x0\]
-+[^:]+: a440c3e0 ld3b {z0.b-z2.b}, p0/z, \[sp, x0\]
-+[^:]+: a440c3e0 ld3b {z0.b-z2.b}, p0/z, \[sp, x0\]
-+[^:]+: a440c3e0 ld3b {z0.b-z2.b}, p0/z, \[sp, x0\]
-+[^:]+: a440c3e0 ld3b {z0.b-z2.b}, p0/z, \[sp, x0\]
-+[^:]+: a444c000 ld3b {z0.b-z2.b}, p0/z, \[x0, x4\]
-+[^:]+: a444c000 ld3b {z0.b-z2.b}, p0/z, \[x0, x4\]
-+[^:]+: a444c000 ld3b {z0.b-z2.b}, p0/z, \[x0, x4\]
-+[^:]+: a444c000 ld3b {z0.b-z2.b}, p0/z, \[x0, x4\]
-+[^:]+: a444c000 ld3b {z0.b-z2.b}, p0/z, \[x0, x4\]
-+[^:]+: a45ec000 ld3b {z0.b-z2.b}, p0/z, \[x0, x30\]
-+[^:]+: a45ec000 ld3b {z0.b-z2.b}, p0/z, \[x0, x30\]
-+[^:]+: a45ec000 ld3b {z0.b-z2.b}, p0/z, \[x0, x30\]
-+[^:]+: a45ec000 ld3b {z0.b-z2.b}, p0/z, \[x0, x30\]
-+[^:]+: a45ec000 ld3b {z0.b-z2.b}, p0/z, \[x0, x30\]
-+[^:]+: a440e000 ld3b {z0.b-z2.b}, p0/z, \[x0\]
-+[^:]+: a440e000 ld3b {z0.b-z2.b}, p0/z, \[x0\]
-+[^:]+: a440e000 ld3b {z0.b-z2.b}, p0/z, \[x0\]
-+[^:]+: a440e000 ld3b {z0.b-z2.b}, p0/z, \[x0\]
-+[^:]+: a440e000 ld3b {z0.b-z2.b}, p0/z, \[x0\]
-+[^:]+: a440e000 ld3b {z0.b-z2.b}, p0/z, \[x0\]
-+[^:]+: a440e000 ld3b {z0.b-z2.b}, p0/z, \[x0\]
-+[^:]+: a440e001 ld3b {z1.b-z3.b}, p0/z, \[x0\]
-+[^:]+: a440e001 ld3b {z1.b-z3.b}, p0/z, \[x0\]
-+[^:]+: a440e001 ld3b {z1.b-z3.b}, p0/z, \[x0\]
-+[^:]+: a440e001 ld3b {z1.b-z3.b}, p0/z, \[x0\]
-+[^:]+: a440e001 ld3b {z1.b-z3.b}, p0/z, \[x0\]
-+[^:]+: a440e001 ld3b {z1.b-z3.b}, p0/z, \[x0\]
-+[^:]+: a440e001 ld3b {z1.b-z3.b}, p0/z, \[x0\]
-+[^:]+: a440e01f ld3b {z31.b, z0.b, z1.b}, p0/z, \[x0\]
-+[^:]+: a440e01f ld3b {z31.b, z0.b, z1.b}, p0/z, \[x0\]
-+[^:]+: a440e01f ld3b {z31.b, z0.b, z1.b}, p0/z, \[x0\]
-+[^:]+: a440e01f ld3b {z31.b, z0.b, z1.b}, p0/z, \[x0\]
-+[^:]+: a440e800 ld3b {z0.b-z2.b}, p2/z, \[x0\]
-+[^:]+: a440e800 ld3b {z0.b-z2.b}, p2/z, \[x0\]
-+[^:]+: a440e800 ld3b {z0.b-z2.b}, p2/z, \[x0\]
-+[^:]+: a440e800 ld3b {z0.b-z2.b}, p2/z, \[x0\]
-+[^:]+: a440e800 ld3b {z0.b-z2.b}, p2/z, \[x0\]
-+[^:]+: a440e800 ld3b {z0.b-z2.b}, p2/z, \[x0\]
-+[^:]+: a440e800 ld3b {z0.b-z2.b}, p2/z, \[x0\]
-+[^:]+: a440fc00 ld3b {z0.b-z2.b}, p7/z, \[x0\]
-+[^:]+: a440fc00 ld3b {z0.b-z2.b}, p7/z, \[x0\]
-+[^:]+: a440fc00 ld3b {z0.b-z2.b}, p7/z, \[x0\]
-+[^:]+: a440fc00 ld3b {z0.b-z2.b}, p7/z, \[x0\]
-+[^:]+: a440fc00 ld3b {z0.b-z2.b}, p7/z, \[x0\]
-+[^:]+: a440fc00 ld3b {z0.b-z2.b}, p7/z, \[x0\]
-+[^:]+: a440fc00 ld3b {z0.b-z2.b}, p7/z, \[x0\]
-+[^:]+: a440e060 ld3b {z0.b-z2.b}, p0/z, \[x3\]
-+[^:]+: a440e060 ld3b {z0.b-z2.b}, p0/z, \[x3\]
-+[^:]+: a440e060 ld3b {z0.b-z2.b}, p0/z, \[x3\]
-+[^:]+: a440e060 ld3b {z0.b-z2.b}, p0/z, \[x3\]
-+[^:]+: a440e060 ld3b {z0.b-z2.b}, p0/z, \[x3\]
-+[^:]+: a440e060 ld3b {z0.b-z2.b}, p0/z, \[x3\]
-+[^:]+: a440e060 ld3b {z0.b-z2.b}, p0/z, \[x3\]
-+[^:]+: a440e3e0 ld3b {z0.b-z2.b}, p0/z, \[sp\]
-+[^:]+: a440e3e0 ld3b {z0.b-z2.b}, p0/z, \[sp\]
-+[^:]+: a440e3e0 ld3b {z0.b-z2.b}, p0/z, \[sp\]
-+[^:]+: a440e3e0 ld3b {z0.b-z2.b}, p0/z, \[sp\]
-+[^:]+: a440e3e0 ld3b {z0.b-z2.b}, p0/z, \[sp\]
-+[^:]+: a440e3e0 ld3b {z0.b-z2.b}, p0/z, \[sp\]
-+[^:]+: a440e3e0 ld3b {z0.b-z2.b}, p0/z, \[sp\]
-+[^:]+: a447e000 ld3b {z0.b-z2.b}, p0/z, \[x0, #21, mul vl\]
-+[^:]+: a447e000 ld3b {z0.b-z2.b}, p0/z, \[x0, #21, mul vl\]
-+[^:]+: a447e000 ld3b {z0.b-z2.b}, p0/z, \[x0, #21, mul vl\]
-+[^:]+: a448e000 ld3b {z0.b-z2.b}, p0/z, \[x0, #-24, mul vl\]
-+[^:]+: a448e000 ld3b {z0.b-z2.b}, p0/z, \[x0, #-24, mul vl\]
-+[^:]+: a448e000 ld3b {z0.b-z2.b}, p0/z, \[x0, #-24, mul vl\]
-+[^:]+: a449e000 ld3b {z0.b-z2.b}, p0/z, \[x0, #-21, mul vl\]
-+[^:]+: a449e000 ld3b {z0.b-z2.b}, p0/z, \[x0, #-21, mul vl\]
-+[^:]+: a449e000 ld3b {z0.b-z2.b}, p0/z, \[x0, #-21, mul vl\]
-+[^:]+: a44fe000 ld3b {z0.b-z2.b}, p0/z, \[x0, #-3, mul vl\]
-+[^:]+: a44fe000 ld3b {z0.b-z2.b}, p0/z, \[x0, #-3, mul vl\]
-+[^:]+: a44fe000 ld3b {z0.b-z2.b}, p0/z, \[x0, #-3, mul vl\]
-+[^:]+: a5c0c000 ld3d {z0.d-z2.d}, p0/z, \[x0, x0, lsl #3\]
-+[^:]+: a5c0c000 ld3d {z0.d-z2.d}, p0/z, \[x0, x0, lsl #3\]
-+[^:]+: a5c0c000 ld3d {z0.d-z2.d}, p0/z, \[x0, x0, lsl #3\]
-+[^:]+: a5c0c001 ld3d {z1.d-z3.d}, p0/z, \[x0, x0, lsl #3\]
-+[^:]+: a5c0c001 ld3d {z1.d-z3.d}, p0/z, \[x0, x0, lsl #3\]
-+[^:]+: a5c0c001 ld3d {z1.d-z3.d}, p0/z, \[x0, x0, lsl #3\]
-+[^:]+: a5c0c01f ld3d {z31.d, z0.d, z1.d}, p0/z, \[x0, x0, lsl #3\]
-+[^:]+: a5c0c01f ld3d {z31.d, z0.d, z1.d}, p0/z, \[x0, x0, lsl #3\]
-+[^:]+: a5c0c800 ld3d {z0.d-z2.d}, p2/z, \[x0, x0, lsl #3\]
-+[^:]+: a5c0c800 ld3d {z0.d-z2.d}, p2/z, \[x0, x0, lsl #3\]
-+[^:]+: a5c0c800 ld3d {z0.d-z2.d}, p2/z, \[x0, x0, lsl #3\]
-+[^:]+: a5c0dc00 ld3d {z0.d-z2.d}, p7/z, \[x0, x0, lsl #3\]
-+[^:]+: a5c0dc00 ld3d {z0.d-z2.d}, p7/z, \[x0, x0, lsl #3\]
-+[^:]+: a5c0dc00 ld3d {z0.d-z2.d}, p7/z, \[x0, x0, lsl #3\]
-+[^:]+: a5c0c060 ld3d {z0.d-z2.d}, p0/z, \[x3, x0, lsl #3\]
-+[^:]+: a5c0c060 ld3d {z0.d-z2.d}, p0/z, \[x3, x0, lsl #3\]
-+[^:]+: a5c0c060 ld3d {z0.d-z2.d}, p0/z, \[x3, x0, lsl #3\]
-+[^:]+: a5c0c3e0 ld3d {z0.d-z2.d}, p0/z, \[sp, x0, lsl #3\]
-+[^:]+: a5c0c3e0 ld3d {z0.d-z2.d}, p0/z, \[sp, x0, lsl #3\]
-+[^:]+: a5c0c3e0 ld3d {z0.d-z2.d}, p0/z, \[sp, x0, lsl #3\]
-+[^:]+: a5c4c000 ld3d {z0.d-z2.d}, p0/z, \[x0, x4, lsl #3\]
-+[^:]+: a5c4c000 ld3d {z0.d-z2.d}, p0/z, \[x0, x4, lsl #3\]
-+[^:]+: a5c4c000 ld3d {z0.d-z2.d}, p0/z, \[x0, x4, lsl #3\]
-+[^:]+: a5dec000 ld3d {z0.d-z2.d}, p0/z, \[x0, x30, lsl #3\]
-+[^:]+: a5dec000 ld3d {z0.d-z2.d}, p0/z, \[x0, x30, lsl #3\]
-+[^:]+: a5dec000 ld3d {z0.d-z2.d}, p0/z, \[x0, x30, lsl #3\]
-+[^:]+: a5c0e000 ld3d {z0.d-z2.d}, p0/z, \[x0\]
-+[^:]+: a5c0e000 ld3d {z0.d-z2.d}, p0/z, \[x0\]
-+[^:]+: a5c0e000 ld3d {z0.d-z2.d}, p0/z, \[x0\]
-+[^:]+: a5c0e000 ld3d {z0.d-z2.d}, p0/z, \[x0\]
-+[^:]+: a5c0e000 ld3d {z0.d-z2.d}, p0/z, \[x0\]
-+[^:]+: a5c0e000 ld3d {z0.d-z2.d}, p0/z, \[x0\]
-+[^:]+: a5c0e000 ld3d {z0.d-z2.d}, p0/z, \[x0\]
-+[^:]+: a5c0e001 ld3d {z1.d-z3.d}, p0/z, \[x0\]
-+[^:]+: a5c0e001 ld3d {z1.d-z3.d}, p0/z, \[x0\]
-+[^:]+: a5c0e001 ld3d {z1.d-z3.d}, p0/z, \[x0\]
-+[^:]+: a5c0e001 ld3d {z1.d-z3.d}, p0/z, \[x0\]
-+[^:]+: a5c0e001 ld3d {z1.d-z3.d}, p0/z, \[x0\]
-+[^:]+: a5c0e001 ld3d {z1.d-z3.d}, p0/z, \[x0\]
-+[^:]+: a5c0e001 ld3d {z1.d-z3.d}, p0/z, \[x0\]
-+[^:]+: a5c0e01f ld3d {z31.d, z0.d, z1.d}, p0/z, \[x0\]
-+[^:]+: a5c0e01f ld3d {z31.d, z0.d, z1.d}, p0/z, \[x0\]
-+[^:]+: a5c0e01f ld3d {z31.d, z0.d, z1.d}, p0/z, \[x0\]
-+[^:]+: a5c0e01f ld3d {z31.d, z0.d, z1.d}, p0/z, \[x0\]
-+[^:]+: a5c0e800 ld3d {z0.d-z2.d}, p2/z, \[x0\]
-+[^:]+: a5c0e800 ld3d {z0.d-z2.d}, p2/z, \[x0\]
-+[^:]+: a5c0e800 ld3d {z0.d-z2.d}, p2/z, \[x0\]
-+[^:]+: a5c0e800 ld3d {z0.d-z2.d}, p2/z, \[x0\]
-+[^:]+: a5c0e800 ld3d {z0.d-z2.d}, p2/z, \[x0\]
-+[^:]+: a5c0e800 ld3d {z0.d-z2.d}, p2/z, \[x0\]
-+[^:]+: a5c0e800 ld3d {z0.d-z2.d}, p2/z, \[x0\]
-+[^:]+: a5c0fc00 ld3d {z0.d-z2.d}, p7/z, \[x0\]
-+[^:]+: a5c0fc00 ld3d {z0.d-z2.d}, p7/z, \[x0\]
-+[^:]+: a5c0fc00 ld3d {z0.d-z2.d}, p7/z, \[x0\]
-+[^:]+: a5c0fc00 ld3d {z0.d-z2.d}, p7/z, \[x0\]
-+[^:]+: a5c0fc00 ld3d {z0.d-z2.d}, p7/z, \[x0\]
-+[^:]+: a5c0fc00 ld3d {z0.d-z2.d}, p7/z, \[x0\]
-+[^:]+: a5c0fc00 ld3d {z0.d-z2.d}, p7/z, \[x0\]
-+[^:]+: a5c0e060 ld3d {z0.d-z2.d}, p0/z, \[x3\]
-+[^:]+: a5c0e060 ld3d {z0.d-z2.d}, p0/z, \[x3\]
-+[^:]+: a5c0e060 ld3d {z0.d-z2.d}, p0/z, \[x3\]
-+[^:]+: a5c0e060 ld3d {z0.d-z2.d}, p0/z, \[x3\]
-+[^:]+: a5c0e060 ld3d {z0.d-z2.d}, p0/z, \[x3\]
-+[^:]+: a5c0e060 ld3d {z0.d-z2.d}, p0/z, \[x3\]
-+[^:]+: a5c0e060 ld3d {z0.d-z2.d}, p0/z, \[x3\]
-+[^:]+: a5c0e3e0 ld3d {z0.d-z2.d}, p0/z, \[sp\]
-+[^:]+: a5c0e3e0 ld3d {z0.d-z2.d}, p0/z, \[sp\]
-+[^:]+: a5c0e3e0 ld3d {z0.d-z2.d}, p0/z, \[sp\]
-+[^:]+: a5c0e3e0 ld3d {z0.d-z2.d}, p0/z, \[sp\]
-+[^:]+: a5c0e3e0 ld3d {z0.d-z2.d}, p0/z, \[sp\]
-+[^:]+: a5c0e3e0 ld3d {z0.d-z2.d}, p0/z, \[sp\]
-+[^:]+: a5c0e3e0 ld3d {z0.d-z2.d}, p0/z, \[sp\]
-+[^:]+: a5c7e000 ld3d {z0.d-z2.d}, p0/z, \[x0, #21, mul vl\]
-+[^:]+: a5c7e000 ld3d {z0.d-z2.d}, p0/z, \[x0, #21, mul vl\]
-+[^:]+: a5c7e000 ld3d {z0.d-z2.d}, p0/z, \[x0, #21, mul vl\]
-+[^:]+: a5c8e000 ld3d {z0.d-z2.d}, p0/z, \[x0, #-24, mul vl\]
-+[^:]+: a5c8e000 ld3d {z0.d-z2.d}, p0/z, \[x0, #-24, mul vl\]
-+[^:]+: a5c8e000 ld3d {z0.d-z2.d}, p0/z, \[x0, #-24, mul vl\]
-+[^:]+: a5c9e000 ld3d {z0.d-z2.d}, p0/z, \[x0, #-21, mul vl\]
-+[^:]+: a5c9e000 ld3d {z0.d-z2.d}, p0/z, \[x0, #-21, mul vl\]
-+[^:]+: a5c9e000 ld3d {z0.d-z2.d}, p0/z, \[x0, #-21, mul vl\]
-+[^:]+: a5cfe000 ld3d {z0.d-z2.d}, p0/z, \[x0, #-3, mul vl\]
-+[^:]+: a5cfe000 ld3d {z0.d-z2.d}, p0/z, \[x0, #-3, mul vl\]
-+[^:]+: a5cfe000 ld3d {z0.d-z2.d}, p0/z, \[x0, #-3, mul vl\]
-+[^:]+: a4c0c000 ld3h {z0.h-z2.h}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a4c0c000 ld3h {z0.h-z2.h}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a4c0c000 ld3h {z0.h-z2.h}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a4c0c001 ld3h {z1.h-z3.h}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a4c0c001 ld3h {z1.h-z3.h}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a4c0c001 ld3h {z1.h-z3.h}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a4c0c01f ld3h {z31.h, z0.h, z1.h}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a4c0c01f ld3h {z31.h, z0.h, z1.h}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a4c0c800 ld3h {z0.h-z2.h}, p2/z, \[x0, x0, lsl #1\]
-+[^:]+: a4c0c800 ld3h {z0.h-z2.h}, p2/z, \[x0, x0, lsl #1\]
-+[^:]+: a4c0c800 ld3h {z0.h-z2.h}, p2/z, \[x0, x0, lsl #1\]
-+[^:]+: a4c0dc00 ld3h {z0.h-z2.h}, p7/z, \[x0, x0, lsl #1\]
-+[^:]+: a4c0dc00 ld3h {z0.h-z2.h}, p7/z, \[x0, x0, lsl #1\]
-+[^:]+: a4c0dc00 ld3h {z0.h-z2.h}, p7/z, \[x0, x0, lsl #1\]
-+[^:]+: a4c0c060 ld3h {z0.h-z2.h}, p0/z, \[x3, x0, lsl #1\]
-+[^:]+: a4c0c060 ld3h {z0.h-z2.h}, p0/z, \[x3, x0, lsl #1\]
-+[^:]+: a4c0c060 ld3h {z0.h-z2.h}, p0/z, \[x3, x0, lsl #1\]
-+[^:]+: a4c0c3e0 ld3h {z0.h-z2.h}, p0/z, \[sp, x0, lsl #1\]
-+[^:]+: a4c0c3e0 ld3h {z0.h-z2.h}, p0/z, \[sp, x0, lsl #1\]
-+[^:]+: a4c0c3e0 ld3h {z0.h-z2.h}, p0/z, \[sp, x0, lsl #1\]
-+[^:]+: a4c4c000 ld3h {z0.h-z2.h}, p0/z, \[x0, x4, lsl #1\]
-+[^:]+: a4c4c000 ld3h {z0.h-z2.h}, p0/z, \[x0, x4, lsl #1\]
-+[^:]+: a4c4c000 ld3h {z0.h-z2.h}, p0/z, \[x0, x4, lsl #1\]
-+[^:]+: a4dec000 ld3h {z0.h-z2.h}, p0/z, \[x0, x30, lsl #1\]
-+[^:]+: a4dec000 ld3h {z0.h-z2.h}, p0/z, \[x0, x30, lsl #1\]
-+[^:]+: a4dec000 ld3h {z0.h-z2.h}, p0/z, \[x0, x30, lsl #1\]
-+[^:]+: a4c0e000 ld3h {z0.h-z2.h}, p0/z, \[x0\]
-+[^:]+: a4c0e000 ld3h {z0.h-z2.h}, p0/z, \[x0\]
-+[^:]+: a4c0e000 ld3h {z0.h-z2.h}, p0/z, \[x0\]
-+[^:]+: a4c0e000 ld3h {z0.h-z2.h}, p0/z, \[x0\]
-+[^:]+: a4c0e000 ld3h {z0.h-z2.h}, p0/z, \[x0\]
-+[^:]+: a4c0e000 ld3h {z0.h-z2.h}, p0/z, \[x0\]
-+[^:]+: a4c0e000 ld3h {z0.h-z2.h}, p0/z, \[x0\]
-+[^:]+: a4c0e001 ld3h {z1.h-z3.h}, p0/z, \[x0\]
-+[^:]+: a4c0e001 ld3h {z1.h-z3.h}, p0/z, \[x0\]
-+[^:]+: a4c0e001 ld3h {z1.h-z3.h}, p0/z, \[x0\]
-+[^:]+: a4c0e001 ld3h {z1.h-z3.h}, p0/z, \[x0\]
-+[^:]+: a4c0e001 ld3h {z1.h-z3.h}, p0/z, \[x0\]
-+[^:]+: a4c0e001 ld3h {z1.h-z3.h}, p0/z, \[x0\]
-+[^:]+: a4c0e001 ld3h {z1.h-z3.h}, p0/z, \[x0\]
-+[^:]+: a4c0e01f ld3h {z31.h, z0.h, z1.h}, p0/z, \[x0\]
-+[^:]+: a4c0e01f ld3h {z31.h, z0.h, z1.h}, p0/z, \[x0\]
-+[^:]+: a4c0e01f ld3h {z31.h, z0.h, z1.h}, p0/z, \[x0\]
-+[^:]+: a4c0e01f ld3h {z31.h, z0.h, z1.h}, p0/z, \[x0\]
-+[^:]+: a4c0e800 ld3h {z0.h-z2.h}, p2/z, \[x0\]
-+[^:]+: a4c0e800 ld3h {z0.h-z2.h}, p2/z, \[x0\]
-+[^:]+: a4c0e800 ld3h {z0.h-z2.h}, p2/z, \[x0\]
-+[^:]+: a4c0e800 ld3h {z0.h-z2.h}, p2/z, \[x0\]
-+[^:]+: a4c0e800 ld3h {z0.h-z2.h}, p2/z, \[x0\]
-+[^:]+: a4c0e800 ld3h {z0.h-z2.h}, p2/z, \[x0\]
-+[^:]+: a4c0e800 ld3h {z0.h-z2.h}, p2/z, \[x0\]
-+[^:]+: a4c0fc00 ld3h {z0.h-z2.h}, p7/z, \[x0\]
-+[^:]+: a4c0fc00 ld3h {z0.h-z2.h}, p7/z, \[x0\]
-+[^:]+: a4c0fc00 ld3h {z0.h-z2.h}, p7/z, \[x0\]
-+[^:]+: a4c0fc00 ld3h {z0.h-z2.h}, p7/z, \[x0\]
-+[^:]+: a4c0fc00 ld3h {z0.h-z2.h}, p7/z, \[x0\]
-+[^:]+: a4c0fc00 ld3h {z0.h-z2.h}, p7/z, \[x0\]
-+[^:]+: a4c0fc00 ld3h {z0.h-z2.h}, p7/z, \[x0\]
-+[^:]+: a4c0e060 ld3h {z0.h-z2.h}, p0/z, \[x3\]
-+[^:]+: a4c0e060 ld3h {z0.h-z2.h}, p0/z, \[x3\]
-+[^:]+: a4c0e060 ld3h {z0.h-z2.h}, p0/z, \[x3\]
-+[^:]+: a4c0e060 ld3h {z0.h-z2.h}, p0/z, \[x3\]
-+[^:]+: a4c0e060 ld3h {z0.h-z2.h}, p0/z, \[x3\]
-+[^:]+: a4c0e060 ld3h {z0.h-z2.h}, p0/z, \[x3\]
-+[^:]+: a4c0e060 ld3h {z0.h-z2.h}, p0/z, \[x3\]
-+[^:]+: a4c0e3e0 ld3h {z0.h-z2.h}, p0/z, \[sp\]
-+[^:]+: a4c0e3e0 ld3h {z0.h-z2.h}, p0/z, \[sp\]
-+[^:]+: a4c0e3e0 ld3h {z0.h-z2.h}, p0/z, \[sp\]
-+[^:]+: a4c0e3e0 ld3h {z0.h-z2.h}, p0/z, \[sp\]
-+[^:]+: a4c0e3e0 ld3h {z0.h-z2.h}, p0/z, \[sp\]
-+[^:]+: a4c0e3e0 ld3h {z0.h-z2.h}, p0/z, \[sp\]
-+[^:]+: a4c0e3e0 ld3h {z0.h-z2.h}, p0/z, \[sp\]
-+[^:]+: a4c7e000 ld3h {z0.h-z2.h}, p0/z, \[x0, #21, mul vl\]
-+[^:]+: a4c7e000 ld3h {z0.h-z2.h}, p0/z, \[x0, #21, mul vl\]
-+[^:]+: a4c7e000 ld3h {z0.h-z2.h}, p0/z, \[x0, #21, mul vl\]
-+[^:]+: a4c8e000 ld3h {z0.h-z2.h}, p0/z, \[x0, #-24, mul vl\]
-+[^:]+: a4c8e000 ld3h {z0.h-z2.h}, p0/z, \[x0, #-24, mul vl\]
-+[^:]+: a4c8e000 ld3h {z0.h-z2.h}, p0/z, \[x0, #-24, mul vl\]
-+[^:]+: a4c9e000 ld3h {z0.h-z2.h}, p0/z, \[x0, #-21, mul vl\]
-+[^:]+: a4c9e000 ld3h {z0.h-z2.h}, p0/z, \[x0, #-21, mul vl\]
-+[^:]+: a4c9e000 ld3h {z0.h-z2.h}, p0/z, \[x0, #-21, mul vl\]
-+[^:]+: a4cfe000 ld3h {z0.h-z2.h}, p0/z, \[x0, #-3, mul vl\]
-+[^:]+: a4cfe000 ld3h {z0.h-z2.h}, p0/z, \[x0, #-3, mul vl\]
-+[^:]+: a4cfe000 ld3h {z0.h-z2.h}, p0/z, \[x0, #-3, mul vl\]
-+[^:]+: a540c000 ld3w {z0.s-z2.s}, p0/z, \[x0, x0, lsl #2\]
-+[^:]+: a540c000 ld3w {z0.s-z2.s}, p0/z, \[x0, x0, lsl #2\]
-+[^:]+: a540c000 ld3w {z0.s-z2.s}, p0/z, \[x0, x0, lsl #2\]
-+[^:]+: a540c001 ld3w {z1.s-z3.s}, p0/z, \[x0, x0, lsl #2\]
-+[^:]+: a540c001 ld3w {z1.s-z3.s}, p0/z, \[x0, x0, lsl #2\]
-+[^:]+: a540c001 ld3w {z1.s-z3.s}, p0/z, \[x0, x0, lsl #2\]
-+[^:]+: a540c01f ld3w {z31.s, z0.s, z1.s}, p0/z, \[x0, x0, lsl #2\]
-+[^:]+: a540c01f ld3w {z31.s, z0.s, z1.s}, p0/z, \[x0, x0, lsl #2\]
-+[^:]+: a540c800 ld3w {z0.s-z2.s}, p2/z, \[x0, x0, lsl #2\]
-+[^:]+: a540c800 ld3w {z0.s-z2.s}, p2/z, \[x0, x0, lsl #2\]
-+[^:]+: a540c800 ld3w {z0.s-z2.s}, p2/z, \[x0, x0, lsl #2\]
-+[^:]+: a540dc00 ld3w {z0.s-z2.s}, p7/z, \[x0, x0, lsl #2\]
-+[^:]+: a540dc00 ld3w {z0.s-z2.s}, p7/z, \[x0, x0, lsl #2\]
-+[^:]+: a540dc00 ld3w {z0.s-z2.s}, p7/z, \[x0, x0, lsl #2\]
-+[^:]+: a540c060 ld3w {z0.s-z2.s}, p0/z, \[x3, x0, lsl #2\]
-+[^:]+: a540c060 ld3w {z0.s-z2.s}, p0/z, \[x3, x0, lsl #2\]
-+[^:]+: a540c060 ld3w {z0.s-z2.s}, p0/z, \[x3, x0, lsl #2\]
-+[^:]+: a540c3e0 ld3w {z0.s-z2.s}, p0/z, \[sp, x0, lsl #2\]
-+[^:]+: a540c3e0 ld3w {z0.s-z2.s}, p0/z, \[sp, x0, lsl #2\]
-+[^:]+: a540c3e0 ld3w {z0.s-z2.s}, p0/z, \[sp, x0, lsl #2\]
-+[^:]+: a544c000 ld3w {z0.s-z2.s}, p0/z, \[x0, x4, lsl #2\]
-+[^:]+: a544c000 ld3w {z0.s-z2.s}, p0/z, \[x0, x4, lsl #2\]
-+[^:]+: a544c000 ld3w {z0.s-z2.s}, p0/z, \[x0, x4, lsl #2\]
-+[^:]+: a55ec000 ld3w {z0.s-z2.s}, p0/z, \[x0, x30, lsl #2\]
-+[^:]+: a55ec000 ld3w {z0.s-z2.s}, p0/z, \[x0, x30, lsl #2\]
-+[^:]+: a55ec000 ld3w {z0.s-z2.s}, p0/z, \[x0, x30, lsl #2\]
-+[^:]+: a540e000 ld3w {z0.s-z2.s}, p0/z, \[x0\]
-+[^:]+: a540e000 ld3w {z0.s-z2.s}, p0/z, \[x0\]
-+[^:]+: a540e000 ld3w {z0.s-z2.s}, p0/z, \[x0\]
-+[^:]+: a540e000 ld3w {z0.s-z2.s}, p0/z, \[x0\]
-+[^:]+: a540e000 ld3w {z0.s-z2.s}, p0/z, \[x0\]
-+[^:]+: a540e000 ld3w {z0.s-z2.s}, p0/z, \[x0\]
-+[^:]+: a540e000 ld3w {z0.s-z2.s}, p0/z, \[x0\]
-+[^:]+: a540e001 ld3w {z1.s-z3.s}, p0/z, \[x0\]
-+[^:]+: a540e001 ld3w {z1.s-z3.s}, p0/z, \[x0\]
-+[^:]+: a540e001 ld3w {z1.s-z3.s}, p0/z, \[x0\]
-+[^:]+: a540e001 ld3w {z1.s-z3.s}, p0/z, \[x0\]
-+[^:]+: a540e001 ld3w {z1.s-z3.s}, p0/z, \[x0\]
-+[^:]+: a540e001 ld3w {z1.s-z3.s}, p0/z, \[x0\]
-+[^:]+: a540e001 ld3w {z1.s-z3.s}, p0/z, \[x0\]
-+[^:]+: a540e01f ld3w {z31.s, z0.s, z1.s}, p0/z, \[x0\]
-+[^:]+: a540e01f ld3w {z31.s, z0.s, z1.s}, p0/z, \[x0\]
-+[^:]+: a540e01f ld3w {z31.s, z0.s, z1.s}, p0/z, \[x0\]
-+[^:]+: a540e01f ld3w {z31.s, z0.s, z1.s}, p0/z, \[x0\]
-+[^:]+: a540e800 ld3w {z0.s-z2.s}, p2/z, \[x0\]
-+[^:]+: a540e800 ld3w {z0.s-z2.s}, p2/z, \[x0\]
-+[^:]+: a540e800 ld3w {z0.s-z2.s}, p2/z, \[x0\]
-+[^:]+: a540e800 ld3w {z0.s-z2.s}, p2/z, \[x0\]
-+[^:]+: a540e800 ld3w {z0.s-z2.s}, p2/z, \[x0\]
-+[^:]+: a540e800 ld3w {z0.s-z2.s}, p2/z, \[x0\]
-+[^:]+: a540e800 ld3w {z0.s-z2.s}, p2/z, \[x0\]
-+[^:]+: a540fc00 ld3w {z0.s-z2.s}, p7/z, \[x0\]
-+[^:]+: a540fc00 ld3w {z0.s-z2.s}, p7/z, \[x0\]
-+[^:]+: a540fc00 ld3w {z0.s-z2.s}, p7/z, \[x0\]
-+[^:]+: a540fc00 ld3w {z0.s-z2.s}, p7/z, \[x0\]
-+[^:]+: a540fc00 ld3w {z0.s-z2.s}, p7/z, \[x0\]
-+[^:]+: a540fc00 ld3w {z0.s-z2.s}, p7/z, \[x0\]
-+[^:]+: a540fc00 ld3w {z0.s-z2.s}, p7/z, \[x0\]
-+[^:]+: a540e060 ld3w {z0.s-z2.s}, p0/z, \[x3\]
-+[^:]+: a540e060 ld3w {z0.s-z2.s}, p0/z, \[x3\]
-+[^:]+: a540e060 ld3w {z0.s-z2.s}, p0/z, \[x3\]
-+[^:]+: a540e060 ld3w {z0.s-z2.s}, p0/z, \[x3\]
-+[^:]+: a540e060 ld3w {z0.s-z2.s}, p0/z, \[x3\]
-+[^:]+: a540e060 ld3w {z0.s-z2.s}, p0/z, \[x3\]
-+[^:]+: a540e060 ld3w {z0.s-z2.s}, p0/z, \[x3\]
-+[^:]+: a540e3e0 ld3w {z0.s-z2.s}, p0/z, \[sp\]
-+[^:]+: a540e3e0 ld3w {z0.s-z2.s}, p0/z, \[sp\]
-+[^:]+: a540e3e0 ld3w {z0.s-z2.s}, p0/z, \[sp\]
-+[^:]+: a540e3e0 ld3w {z0.s-z2.s}, p0/z, \[sp\]
-+[^:]+: a540e3e0 ld3w {z0.s-z2.s}, p0/z, \[sp\]
-+[^:]+: a540e3e0 ld3w {z0.s-z2.s}, p0/z, \[sp\]
-+[^:]+: a540e3e0 ld3w {z0.s-z2.s}, p0/z, \[sp\]
-+[^:]+: a547e000 ld3w {z0.s-z2.s}, p0/z, \[x0, #21, mul vl\]
-+[^:]+: a547e000 ld3w {z0.s-z2.s}, p0/z, \[x0, #21, mul vl\]
-+[^:]+: a547e000 ld3w {z0.s-z2.s}, p0/z, \[x0, #21, mul vl\]
-+[^:]+: a548e000 ld3w {z0.s-z2.s}, p0/z, \[x0, #-24, mul vl\]
-+[^:]+: a548e000 ld3w {z0.s-z2.s}, p0/z, \[x0, #-24, mul vl\]
-+[^:]+: a548e000 ld3w {z0.s-z2.s}, p0/z, \[x0, #-24, mul vl\]
-+[^:]+: a549e000 ld3w {z0.s-z2.s}, p0/z, \[x0, #-21, mul vl\]
-+[^:]+: a549e000 ld3w {z0.s-z2.s}, p0/z, \[x0, #-21, mul vl\]
-+[^:]+: a549e000 ld3w {z0.s-z2.s}, p0/z, \[x0, #-21, mul vl\]
-+[^:]+: a54fe000 ld3w {z0.s-z2.s}, p0/z, \[x0, #-3, mul vl\]
-+[^:]+: a54fe000 ld3w {z0.s-z2.s}, p0/z, \[x0, #-3, mul vl\]
-+[^:]+: a54fe000 ld3w {z0.s-z2.s}, p0/z, \[x0, #-3, mul vl\]
-+[^:]+: a460c000 ld4b {z0.b-z3.b}, p0/z, \[x0, x0\]
-+[^:]+: a460c000 ld4b {z0.b-z3.b}, p0/z, \[x0, x0\]
-+[^:]+: a460c000 ld4b {z0.b-z3.b}, p0/z, \[x0, x0\]
-+[^:]+: a460c000 ld4b {z0.b-z3.b}, p0/z, \[x0, x0\]
-+[^:]+: a460c000 ld4b {z0.b-z3.b}, p0/z, \[x0, x0\]
-+[^:]+: a460c001 ld4b {z1.b-z4.b}, p0/z, \[x0, x0\]
-+[^:]+: a460c001 ld4b {z1.b-z4.b}, p0/z, \[x0, x0\]
-+[^:]+: a460c001 ld4b {z1.b-z4.b}, p0/z, \[x0, x0\]
-+[^:]+: a460c001 ld4b {z1.b-z4.b}, p0/z, \[x0, x0\]
-+[^:]+: a460c001 ld4b {z1.b-z4.b}, p0/z, \[x0, x0\]
-+[^:]+: a460c01f ld4b {z31.b, z0.b, z1.b, z2.b}, p0/z, \[x0, x0\]
-+[^:]+: a460c01f ld4b {z31.b, z0.b, z1.b, z2.b}, p0/z, \[x0, x0\]
-+[^:]+: a460c01f ld4b {z31.b, z0.b, z1.b, z2.b}, p0/z, \[x0, x0\]
-+[^:]+: a460c800 ld4b {z0.b-z3.b}, p2/z, \[x0, x0\]
-+[^:]+: a460c800 ld4b {z0.b-z3.b}, p2/z, \[x0, x0\]
-+[^:]+: a460c800 ld4b {z0.b-z3.b}, p2/z, \[x0, x0\]
-+[^:]+: a460c800 ld4b {z0.b-z3.b}, p2/z, \[x0, x0\]
-+[^:]+: a460c800 ld4b {z0.b-z3.b}, p2/z, \[x0, x0\]
-+[^:]+: a460dc00 ld4b {z0.b-z3.b}, p7/z, \[x0, x0\]
-+[^:]+: a460dc00 ld4b {z0.b-z3.b}, p7/z, \[x0, x0\]
-+[^:]+: a460dc00 ld4b {z0.b-z3.b}, p7/z, \[x0, x0\]
-+[^:]+: a460dc00 ld4b {z0.b-z3.b}, p7/z, \[x0, x0\]
-+[^:]+: a460dc00 ld4b {z0.b-z3.b}, p7/z, \[x0, x0\]
-+[^:]+: a460c060 ld4b {z0.b-z3.b}, p0/z, \[x3, x0\]
-+[^:]+: a460c060 ld4b {z0.b-z3.b}, p0/z, \[x3, x0\]
-+[^:]+: a460c060 ld4b {z0.b-z3.b}, p0/z, \[x3, x0\]
-+[^:]+: a460c060 ld4b {z0.b-z3.b}, p0/z, \[x3, x0\]
-+[^:]+: a460c060 ld4b {z0.b-z3.b}, p0/z, \[x3, x0\]
-+[^:]+: a460c3e0 ld4b {z0.b-z3.b}, p0/z, \[sp, x0\]
-+[^:]+: a460c3e0 ld4b {z0.b-z3.b}, p0/z, \[sp, x0\]
-+[^:]+: a460c3e0 ld4b {z0.b-z3.b}, p0/z, \[sp, x0\]
-+[^:]+: a460c3e0 ld4b {z0.b-z3.b}, p0/z, \[sp, x0\]
-+[^:]+: a460c3e0 ld4b {z0.b-z3.b}, p0/z, \[sp, x0\]
-+[^:]+: a464c000 ld4b {z0.b-z3.b}, p0/z, \[x0, x4\]
-+[^:]+: a464c000 ld4b {z0.b-z3.b}, p0/z, \[x0, x4\]
-+[^:]+: a464c000 ld4b {z0.b-z3.b}, p0/z, \[x0, x4\]
-+[^:]+: a464c000 ld4b {z0.b-z3.b}, p0/z, \[x0, x4\]
-+[^:]+: a464c000 ld4b {z0.b-z3.b}, p0/z, \[x0, x4\]
-+[^:]+: a47ec000 ld4b {z0.b-z3.b}, p0/z, \[x0, x30\]
-+[^:]+: a47ec000 ld4b {z0.b-z3.b}, p0/z, \[x0, x30\]
-+[^:]+: a47ec000 ld4b {z0.b-z3.b}, p0/z, \[x0, x30\]
-+[^:]+: a47ec000 ld4b {z0.b-z3.b}, p0/z, \[x0, x30\]
-+[^:]+: a47ec000 ld4b {z0.b-z3.b}, p0/z, \[x0, x30\]
-+[^:]+: a460e000 ld4b {z0.b-z3.b}, p0/z, \[x0\]
-+[^:]+: a460e000 ld4b {z0.b-z3.b}, p0/z, \[x0\]
-+[^:]+: a460e000 ld4b {z0.b-z3.b}, p0/z, \[x0\]
-+[^:]+: a460e000 ld4b {z0.b-z3.b}, p0/z, \[x0\]
-+[^:]+: a460e000 ld4b {z0.b-z3.b}, p0/z, \[x0\]
-+[^:]+: a460e000 ld4b {z0.b-z3.b}, p0/z, \[x0\]
-+[^:]+: a460e000 ld4b {z0.b-z3.b}, p0/z, \[x0\]
-+[^:]+: a460e001 ld4b {z1.b-z4.b}, p0/z, \[x0\]
-+[^:]+: a460e001 ld4b {z1.b-z4.b}, p0/z, \[x0\]
-+[^:]+: a460e001 ld4b {z1.b-z4.b}, p0/z, \[x0\]
-+[^:]+: a460e001 ld4b {z1.b-z4.b}, p0/z, \[x0\]
-+[^:]+: a460e001 ld4b {z1.b-z4.b}, p0/z, \[x0\]
-+[^:]+: a460e001 ld4b {z1.b-z4.b}, p0/z, \[x0\]
-+[^:]+: a460e001 ld4b {z1.b-z4.b}, p0/z, \[x0\]
-+[^:]+: a460e01f ld4b {z31.b, z0.b, z1.b, z2.b}, p0/z, \[x0\]
-+[^:]+: a460e01f ld4b {z31.b, z0.b, z1.b, z2.b}, p0/z, \[x0\]
-+[^:]+: a460e01f ld4b {z31.b, z0.b, z1.b, z2.b}, p0/z, \[x0\]
-+[^:]+: a460e01f ld4b {z31.b, z0.b, z1.b, z2.b}, p0/z, \[x0\]
-+[^:]+: a460e800 ld4b {z0.b-z3.b}, p2/z, \[x0\]
-+[^:]+: a460e800 ld4b {z0.b-z3.b}, p2/z, \[x0\]
-+[^:]+: a460e800 ld4b {z0.b-z3.b}, p2/z, \[x0\]
-+[^:]+: a460e800 ld4b {z0.b-z3.b}, p2/z, \[x0\]
-+[^:]+: a460e800 ld4b {z0.b-z3.b}, p2/z, \[x0\]
-+[^:]+: a460e800 ld4b {z0.b-z3.b}, p2/z, \[x0\]
-+[^:]+: a460e800 ld4b {z0.b-z3.b}, p2/z, \[x0\]
-+[^:]+: a460fc00 ld4b {z0.b-z3.b}, p7/z, \[x0\]
-+[^:]+: a460fc00 ld4b {z0.b-z3.b}, p7/z, \[x0\]
-+[^:]+: a460fc00 ld4b {z0.b-z3.b}, p7/z, \[x0\]
-+[^:]+: a460fc00 ld4b {z0.b-z3.b}, p7/z, \[x0\]
-+[^:]+: a460fc00 ld4b {z0.b-z3.b}, p7/z, \[x0\]
-+[^:]+: a460fc00 ld4b {z0.b-z3.b}, p7/z, \[x0\]
-+[^:]+: a460fc00 ld4b {z0.b-z3.b}, p7/z, \[x0\]
-+[^:]+: a460e060 ld4b {z0.b-z3.b}, p0/z, \[x3\]
-+[^:]+: a460e060 ld4b {z0.b-z3.b}, p0/z, \[x3\]
-+[^:]+: a460e060 ld4b {z0.b-z3.b}, p0/z, \[x3\]
-+[^:]+: a460e060 ld4b {z0.b-z3.b}, p0/z, \[x3\]
-+[^:]+: a460e060 ld4b {z0.b-z3.b}, p0/z, \[x3\]
-+[^:]+: a460e060 ld4b {z0.b-z3.b}, p0/z, \[x3\]
-+[^:]+: a460e060 ld4b {z0.b-z3.b}, p0/z, \[x3\]
-+[^:]+: a460e3e0 ld4b {z0.b-z3.b}, p0/z, \[sp\]
-+[^:]+: a460e3e0 ld4b {z0.b-z3.b}, p0/z, \[sp\]
-+[^:]+: a460e3e0 ld4b {z0.b-z3.b}, p0/z, \[sp\]
-+[^:]+: a460e3e0 ld4b {z0.b-z3.b}, p0/z, \[sp\]
-+[^:]+: a460e3e0 ld4b {z0.b-z3.b}, p0/z, \[sp\]
-+[^:]+: a460e3e0 ld4b {z0.b-z3.b}, p0/z, \[sp\]
-+[^:]+: a460e3e0 ld4b {z0.b-z3.b}, p0/z, \[sp\]
-+[^:]+: a467e000 ld4b {z0.b-z3.b}, p0/z, \[x0, #28, mul vl\]
-+[^:]+: a467e000 ld4b {z0.b-z3.b}, p0/z, \[x0, #28, mul vl\]
-+[^:]+: a467e000 ld4b {z0.b-z3.b}, p0/z, \[x0, #28, mul vl\]
-+[^:]+: a468e000 ld4b {z0.b-z3.b}, p0/z, \[x0, #-32, mul vl\]
-+[^:]+: a468e000 ld4b {z0.b-z3.b}, p0/z, \[x0, #-32, mul vl\]
-+[^:]+: a468e000 ld4b {z0.b-z3.b}, p0/z, \[x0, #-32, mul vl\]
-+[^:]+: a469e000 ld4b {z0.b-z3.b}, p0/z, \[x0, #-28, mul vl\]
-+[^:]+: a469e000 ld4b {z0.b-z3.b}, p0/z, \[x0, #-28, mul vl\]
-+[^:]+: a469e000 ld4b {z0.b-z3.b}, p0/z, \[x0, #-28, mul vl\]
-+[^:]+: a46fe000 ld4b {z0.b-z3.b}, p0/z, \[x0, #-4, mul vl\]
-+[^:]+: a46fe000 ld4b {z0.b-z3.b}, p0/z, \[x0, #-4, mul vl\]
-+[^:]+: a46fe000 ld4b {z0.b-z3.b}, p0/z, \[x0, #-4, mul vl\]
-+[^:]+: a5e0c000 ld4d {z0.d-z3.d}, p0/z, \[x0, x0, lsl #3\]
-+[^:]+: a5e0c000 ld4d {z0.d-z3.d}, p0/z, \[x0, x0, lsl #3\]
-+[^:]+: a5e0c000 ld4d {z0.d-z3.d}, p0/z, \[x0, x0, lsl #3\]
-+[^:]+: a5e0c001 ld4d {z1.d-z4.d}, p0/z, \[x0, x0, lsl #3\]
-+[^:]+: a5e0c001 ld4d {z1.d-z4.d}, p0/z, \[x0, x0, lsl #3\]
-+[^:]+: a5e0c001 ld4d {z1.d-z4.d}, p0/z, \[x0, x0, lsl #3\]
-+[^:]+: a5e0c01f ld4d {z31.d, z0.d, z1.d, z2.d}, p0/z, \[x0, x0, lsl #3\]
-+[^:]+: a5e0c01f ld4d {z31.d, z0.d, z1.d, z2.d}, p0/z, \[x0, x0, lsl #3\]
-+[^:]+: a5e0c800 ld4d {z0.d-z3.d}, p2/z, \[x0, x0, lsl #3\]
-+[^:]+: a5e0c800 ld4d {z0.d-z3.d}, p2/z, \[x0, x0, lsl #3\]
-+[^:]+: a5e0c800 ld4d {z0.d-z3.d}, p2/z, \[x0, x0, lsl #3\]
-+[^:]+: a5e0dc00 ld4d {z0.d-z3.d}, p7/z, \[x0, x0, lsl #3\]
-+[^:]+: a5e0dc00 ld4d {z0.d-z3.d}, p7/z, \[x0, x0, lsl #3\]
-+[^:]+: a5e0dc00 ld4d {z0.d-z3.d}, p7/z, \[x0, x0, lsl #3\]
-+[^:]+: a5e0c060 ld4d {z0.d-z3.d}, p0/z, \[x3, x0, lsl #3\]
-+[^:]+: a5e0c060 ld4d {z0.d-z3.d}, p0/z, \[x3, x0, lsl #3\]
-+[^:]+: a5e0c060 ld4d {z0.d-z3.d}, p0/z, \[x3, x0, lsl #3\]
-+[^:]+: a5e0c3e0 ld4d {z0.d-z3.d}, p0/z, \[sp, x0, lsl #3\]
-+[^:]+: a5e0c3e0 ld4d {z0.d-z3.d}, p0/z, \[sp, x0, lsl #3\]
-+[^:]+: a5e0c3e0 ld4d {z0.d-z3.d}, p0/z, \[sp, x0, lsl #3\]
-+[^:]+: a5e4c000 ld4d {z0.d-z3.d}, p0/z, \[x0, x4, lsl #3\]
-+[^:]+: a5e4c000 ld4d {z0.d-z3.d}, p0/z, \[x0, x4, lsl #3\]
-+[^:]+: a5e4c000 ld4d {z0.d-z3.d}, p0/z, \[x0, x4, lsl #3\]
-+[^:]+: a5fec000 ld4d {z0.d-z3.d}, p0/z, \[x0, x30, lsl #3\]
-+[^:]+: a5fec000 ld4d {z0.d-z3.d}, p0/z, \[x0, x30, lsl #3\]
-+[^:]+: a5fec000 ld4d {z0.d-z3.d}, p0/z, \[x0, x30, lsl #3\]
-+[^:]+: a5e0e000 ld4d {z0.d-z3.d}, p0/z, \[x0\]
-+[^:]+: a5e0e000 ld4d {z0.d-z3.d}, p0/z, \[x0\]
-+[^:]+: a5e0e000 ld4d {z0.d-z3.d}, p0/z, \[x0\]
-+[^:]+: a5e0e000 ld4d {z0.d-z3.d}, p0/z, \[x0\]
-+[^:]+: a5e0e000 ld4d {z0.d-z3.d}, p0/z, \[x0\]
-+[^:]+: a5e0e000 ld4d {z0.d-z3.d}, p0/z, \[x0\]
-+[^:]+: a5e0e000 ld4d {z0.d-z3.d}, p0/z, \[x0\]
-+[^:]+: a5e0e001 ld4d {z1.d-z4.d}, p0/z, \[x0\]
-+[^:]+: a5e0e001 ld4d {z1.d-z4.d}, p0/z, \[x0\]
-+[^:]+: a5e0e001 ld4d {z1.d-z4.d}, p0/z, \[x0\]
-+[^:]+: a5e0e001 ld4d {z1.d-z4.d}, p0/z, \[x0\]
-+[^:]+: a5e0e001 ld4d {z1.d-z4.d}, p0/z, \[x0\]
-+[^:]+: a5e0e001 ld4d {z1.d-z4.d}, p0/z, \[x0\]
-+[^:]+: a5e0e001 ld4d {z1.d-z4.d}, p0/z, \[x0\]
-+[^:]+: a5e0e01f ld4d {z31.d, z0.d, z1.d, z2.d}, p0/z, \[x0\]
-+[^:]+: a5e0e01f ld4d {z31.d, z0.d, z1.d, z2.d}, p0/z, \[x0\]
-+[^:]+: a5e0e01f ld4d {z31.d, z0.d, z1.d, z2.d}, p0/z, \[x0\]
-+[^:]+: a5e0e01f ld4d {z31.d, z0.d, z1.d, z2.d}, p0/z, \[x0\]
-+[^:]+: a5e0e800 ld4d {z0.d-z3.d}, p2/z, \[x0\]
-+[^:]+: a5e0e800 ld4d {z0.d-z3.d}, p2/z, \[x0\]
-+[^:]+: a5e0e800 ld4d {z0.d-z3.d}, p2/z, \[x0\]
-+[^:]+: a5e0e800 ld4d {z0.d-z3.d}, p2/z, \[x0\]
-+[^:]+: a5e0e800 ld4d {z0.d-z3.d}, p2/z, \[x0\]
-+[^:]+: a5e0e800 ld4d {z0.d-z3.d}, p2/z, \[x0\]
-+[^:]+: a5e0e800 ld4d {z0.d-z3.d}, p2/z, \[x0\]
-+[^:]+: a5e0fc00 ld4d {z0.d-z3.d}, p7/z, \[x0\]
-+[^:]+: a5e0fc00 ld4d {z0.d-z3.d}, p7/z, \[x0\]
-+[^:]+: a5e0fc00 ld4d {z0.d-z3.d}, p7/z, \[x0\]
-+[^:]+: a5e0fc00 ld4d {z0.d-z3.d}, p7/z, \[x0\]
-+[^:]+: a5e0fc00 ld4d {z0.d-z3.d}, p7/z, \[x0\]
-+[^:]+: a5e0fc00 ld4d {z0.d-z3.d}, p7/z, \[x0\]
-+[^:]+: a5e0fc00 ld4d {z0.d-z3.d}, p7/z, \[x0\]
-+[^:]+: a5e0e060 ld4d {z0.d-z3.d}, p0/z, \[x3\]
-+[^:]+: a5e0e060 ld4d {z0.d-z3.d}, p0/z, \[x3\]
-+[^:]+: a5e0e060 ld4d {z0.d-z3.d}, p0/z, \[x3\]
-+[^:]+: a5e0e060 ld4d {z0.d-z3.d}, p0/z, \[x3\]
-+[^:]+: a5e0e060 ld4d {z0.d-z3.d}, p0/z, \[x3\]
-+[^:]+: a5e0e060 ld4d {z0.d-z3.d}, p0/z, \[x3\]
-+[^:]+: a5e0e060 ld4d {z0.d-z3.d}, p0/z, \[x3\]
-+[^:]+: a5e0e3e0 ld4d {z0.d-z3.d}, p0/z, \[sp\]
-+[^:]+: a5e0e3e0 ld4d {z0.d-z3.d}, p0/z, \[sp\]
-+[^:]+: a5e0e3e0 ld4d {z0.d-z3.d}, p0/z, \[sp\]
-+[^:]+: a5e0e3e0 ld4d {z0.d-z3.d}, p0/z, \[sp\]
-+[^:]+: a5e0e3e0 ld4d {z0.d-z3.d}, p0/z, \[sp\]
-+[^:]+: a5e0e3e0 ld4d {z0.d-z3.d}, p0/z, \[sp\]
-+[^:]+: a5e0e3e0 ld4d {z0.d-z3.d}, p0/z, \[sp\]
-+[^:]+: a5e7e000 ld4d {z0.d-z3.d}, p0/z, \[x0, #28, mul vl\]
-+[^:]+: a5e7e000 ld4d {z0.d-z3.d}, p0/z, \[x0, #28, mul vl\]
-+[^:]+: a5e7e000 ld4d {z0.d-z3.d}, p0/z, \[x0, #28, mul vl\]
-+[^:]+: a5e8e000 ld4d {z0.d-z3.d}, p0/z, \[x0, #-32, mul vl\]
-+[^:]+: a5e8e000 ld4d {z0.d-z3.d}, p0/z, \[x0, #-32, mul vl\]
-+[^:]+: a5e8e000 ld4d {z0.d-z3.d}, p0/z, \[x0, #-32, mul vl\]
-+[^:]+: a5e9e000 ld4d {z0.d-z3.d}, p0/z, \[x0, #-28, mul vl\]
-+[^:]+: a5e9e000 ld4d {z0.d-z3.d}, p0/z, \[x0, #-28, mul vl\]
-+[^:]+: a5e9e000 ld4d {z0.d-z3.d}, p0/z, \[x0, #-28, mul vl\]
-+[^:]+: a5efe000 ld4d {z0.d-z3.d}, p0/z, \[x0, #-4, mul vl\]
-+[^:]+: a5efe000 ld4d {z0.d-z3.d}, p0/z, \[x0, #-4, mul vl\]
-+[^:]+: a5efe000 ld4d {z0.d-z3.d}, p0/z, \[x0, #-4, mul vl\]
-+[^:]+: a4e0c000 ld4h {z0.h-z3.h}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a4e0c000 ld4h {z0.h-z3.h}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a4e0c000 ld4h {z0.h-z3.h}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a4e0c001 ld4h {z1.h-z4.h}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a4e0c001 ld4h {z1.h-z4.h}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a4e0c001 ld4h {z1.h-z4.h}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a4e0c01f ld4h {z31.h, z0.h, z1.h, z2.h}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a4e0c01f ld4h {z31.h, z0.h, z1.h, z2.h}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a4e0c800 ld4h {z0.h-z3.h}, p2/z, \[x0, x0, lsl #1\]
-+[^:]+: a4e0c800 ld4h {z0.h-z3.h}, p2/z, \[x0, x0, lsl #1\]
-+[^:]+: a4e0c800 ld4h {z0.h-z3.h}, p2/z, \[x0, x0, lsl #1\]
-+[^:]+: a4e0dc00 ld4h {z0.h-z3.h}, p7/z, \[x0, x0, lsl #1\]
-+[^:]+: a4e0dc00 ld4h {z0.h-z3.h}, p7/z, \[x0, x0, lsl #1\]
-+[^:]+: a4e0dc00 ld4h {z0.h-z3.h}, p7/z, \[x0, x0, lsl #1\]
-+[^:]+: a4e0c060 ld4h {z0.h-z3.h}, p0/z, \[x3, x0, lsl #1\]
-+[^:]+: a4e0c060 ld4h {z0.h-z3.h}, p0/z, \[x3, x0, lsl #1\]
-+[^:]+: a4e0c060 ld4h {z0.h-z3.h}, p0/z, \[x3, x0, lsl #1\]
-+[^:]+: a4e0c3e0 ld4h {z0.h-z3.h}, p0/z, \[sp, x0, lsl #1\]
-+[^:]+: a4e0c3e0 ld4h {z0.h-z3.h}, p0/z, \[sp, x0, lsl #1\]
-+[^:]+: a4e0c3e0 ld4h {z0.h-z3.h}, p0/z, \[sp, x0, lsl #1\]
-+[^:]+: a4e4c000 ld4h {z0.h-z3.h}, p0/z, \[x0, x4, lsl #1\]
-+[^:]+: a4e4c000 ld4h {z0.h-z3.h}, p0/z, \[x0, x4, lsl #1\]
-+[^:]+: a4e4c000 ld4h {z0.h-z3.h}, p0/z, \[x0, x4, lsl #1\]
-+[^:]+: a4fec000 ld4h {z0.h-z3.h}, p0/z, \[x0, x30, lsl #1\]
-+[^:]+: a4fec000 ld4h {z0.h-z3.h}, p0/z, \[x0, x30, lsl #1\]
-+[^:]+: a4fec000 ld4h {z0.h-z3.h}, p0/z, \[x0, x30, lsl #1\]
-+[^:]+: a4e0e000 ld4h {z0.h-z3.h}, p0/z, \[x0\]
-+[^:]+: a4e0e000 ld4h {z0.h-z3.h}, p0/z, \[x0\]
-+[^:]+: a4e0e000 ld4h {z0.h-z3.h}, p0/z, \[x0\]
-+[^:]+: a4e0e000 ld4h {z0.h-z3.h}, p0/z, \[x0\]
-+[^:]+: a4e0e000 ld4h {z0.h-z3.h}, p0/z, \[x0\]
-+[^:]+: a4e0e000 ld4h {z0.h-z3.h}, p0/z, \[x0\]
-+[^:]+: a4e0e000 ld4h {z0.h-z3.h}, p0/z, \[x0\]
-+[^:]+: a4e0e001 ld4h {z1.h-z4.h}, p0/z, \[x0\]
-+[^:]+: a4e0e001 ld4h {z1.h-z4.h}, p0/z, \[x0\]
-+[^:]+: a4e0e001 ld4h {z1.h-z4.h}, p0/z, \[x0\]
-+[^:]+: a4e0e001 ld4h {z1.h-z4.h}, p0/z, \[x0\]
-+[^:]+: a4e0e001 ld4h {z1.h-z4.h}, p0/z, \[x0\]
-+[^:]+: a4e0e001 ld4h {z1.h-z4.h}, p0/z, \[x0\]
-+[^:]+: a4e0e001 ld4h {z1.h-z4.h}, p0/z, \[x0\]
-+[^:]+: a4e0e01f ld4h {z31.h, z0.h, z1.h, z2.h}, p0/z, \[x0\]
-+[^:]+: a4e0e01f ld4h {z31.h, z0.h, z1.h, z2.h}, p0/z, \[x0\]
-+[^:]+: a4e0e01f ld4h {z31.h, z0.h, z1.h, z2.h}, p0/z, \[x0\]
-+[^:]+: a4e0e01f ld4h {z31.h, z0.h, z1.h, z2.h}, p0/z, \[x0\]
-+[^:]+: a4e0e800 ld4h {z0.h-z3.h}, p2/z, \[x0\]
-+[^:]+: a4e0e800 ld4h {z0.h-z3.h}, p2/z, \[x0\]
-+[^:]+: a4e0e800 ld4h {z0.h-z3.h}, p2/z, \[x0\]
-+[^:]+: a4e0e800 ld4h {z0.h-z3.h}, p2/z, \[x0\]
-+[^:]+: a4e0e800 ld4h {z0.h-z3.h}, p2/z, \[x0\]
-+[^:]+: a4e0e800 ld4h {z0.h-z3.h}, p2/z, \[x0\]
-+[^:]+: a4e0e800 ld4h {z0.h-z3.h}, p2/z, \[x0\]
-+[^:]+: a4e0fc00 ld4h {z0.h-z3.h}, p7/z, \[x0\]
-+[^:]+: a4e0fc00 ld4h {z0.h-z3.h}, p7/z, \[x0\]
-+[^:]+: a4e0fc00 ld4h {z0.h-z3.h}, p7/z, \[x0\]
-+[^:]+: a4e0fc00 ld4h {z0.h-z3.h}, p7/z, \[x0\]
-+[^:]+: a4e0fc00 ld4h {z0.h-z3.h}, p7/z, \[x0\]
-+[^:]+: a4e0fc00 ld4h {z0.h-z3.h}, p7/z, \[x0\]
-+[^:]+: a4e0fc00 ld4h {z0.h-z3.h}, p7/z, \[x0\]
-+[^:]+: a4e0e060 ld4h {z0.h-z3.h}, p0/z, \[x3\]
-+[^:]+: a4e0e060 ld4h {z0.h-z3.h}, p0/z, \[x3\]
-+[^:]+: a4e0e060 ld4h {z0.h-z3.h}, p0/z, \[x3\]
-+[^:]+: a4e0e060 ld4h {z0.h-z3.h}, p0/z, \[x3\]
-+[^:]+: a4e0e060 ld4h {z0.h-z3.h}, p0/z, \[x3\]
-+[^:]+: a4e0e060 ld4h {z0.h-z3.h}, p0/z, \[x3\]
-+[^:]+: a4e0e060 ld4h {z0.h-z3.h}, p0/z, \[x3\]
-+[^:]+: a4e0e3e0 ld4h {z0.h-z3.h}, p0/z, \[sp\]
-+[^:]+: a4e0e3e0 ld4h {z0.h-z3.h}, p0/z, \[sp\]
-+[^:]+: a4e0e3e0 ld4h {z0.h-z3.h}, p0/z, \[sp\]
-+[^:]+: a4e0e3e0 ld4h {z0.h-z3.h}, p0/z, \[sp\]
-+[^:]+: a4e0e3e0 ld4h {z0.h-z3.h}, p0/z, \[sp\]
-+[^:]+: a4e0e3e0 ld4h {z0.h-z3.h}, p0/z, \[sp\]
-+[^:]+: a4e0e3e0 ld4h {z0.h-z3.h}, p0/z, \[sp\]
-+[^:]+: a4e7e000 ld4h {z0.h-z3.h}, p0/z, \[x0, #28, mul vl\]
-+[^:]+: a4e7e000 ld4h {z0.h-z3.h}, p0/z, \[x0, #28, mul vl\]
-+[^:]+: a4e7e000 ld4h {z0.h-z3.h}, p0/z, \[x0, #28, mul vl\]
-+[^:]+: a4e8e000 ld4h {z0.h-z3.h}, p0/z, \[x0, #-32, mul vl\]
-+[^:]+: a4e8e000 ld4h {z0.h-z3.h}, p0/z, \[x0, #-32, mul vl\]
-+[^:]+: a4e8e000 ld4h {z0.h-z3.h}, p0/z, \[x0, #-32, mul vl\]
-+[^:]+: a4e9e000 ld4h {z0.h-z3.h}, p0/z, \[x0, #-28, mul vl\]
-+[^:]+: a4e9e000 ld4h {z0.h-z3.h}, p0/z, \[x0, #-28, mul vl\]
-+[^:]+: a4e9e000 ld4h {z0.h-z3.h}, p0/z, \[x0, #-28, mul vl\]
-+[^:]+: a4efe000 ld4h {z0.h-z3.h}, p0/z, \[x0, #-4, mul vl\]
-+[^:]+: a4efe000 ld4h {z0.h-z3.h}, p0/z, \[x0, #-4, mul vl\]
-+[^:]+: a4efe000 ld4h {z0.h-z3.h}, p0/z, \[x0, #-4, mul vl\]
-+[^:]+: a560c000 ld4w {z0.s-z3.s}, p0/z, \[x0, x0, lsl #2\]
-+[^:]+: a560c000 ld4w {z0.s-z3.s}, p0/z, \[x0, x0, lsl #2\]
-+[^:]+: a560c000 ld4w {z0.s-z3.s}, p0/z, \[x0, x0, lsl #2\]
-+[^:]+: a560c001 ld4w {z1.s-z4.s}, p0/z, \[x0, x0, lsl #2\]
-+[^:]+: a560c001 ld4w {z1.s-z4.s}, p0/z, \[x0, x0, lsl #2\]
-+[^:]+: a560c001 ld4w {z1.s-z4.s}, p0/z, \[x0, x0, lsl #2\]
-+[^:]+: a560c01f ld4w {z31.s, z0.s, z1.s, z2.s}, p0/z, \[x0, x0, lsl #2\]
-+[^:]+: a560c01f ld4w {z31.s, z0.s, z1.s, z2.s}, p0/z, \[x0, x0, lsl #2\]
-+[^:]+: a560c800 ld4w {z0.s-z3.s}, p2/z, \[x0, x0, lsl #2\]
-+[^:]+: a560c800 ld4w {z0.s-z3.s}, p2/z, \[x0, x0, lsl #2\]
-+[^:]+: a560c800 ld4w {z0.s-z3.s}, p2/z, \[x0, x0, lsl #2\]
-+[^:]+: a560dc00 ld4w {z0.s-z3.s}, p7/z, \[x0, x0, lsl #2\]
-+[^:]+: a560dc00 ld4w {z0.s-z3.s}, p7/z, \[x0, x0, lsl #2\]
-+[^:]+: a560dc00 ld4w {z0.s-z3.s}, p7/z, \[x0, x0, lsl #2\]
-+[^:]+: a560c060 ld4w {z0.s-z3.s}, p0/z, \[x3, x0, lsl #2\]
-+[^:]+: a560c060 ld4w {z0.s-z3.s}, p0/z, \[x3, x0, lsl #2\]
-+[^:]+: a560c060 ld4w {z0.s-z3.s}, p0/z, \[x3, x0, lsl #2\]
-+[^:]+: a560c3e0 ld4w {z0.s-z3.s}, p0/z, \[sp, x0, lsl #2\]
-+[^:]+: a560c3e0 ld4w {z0.s-z3.s}, p0/z, \[sp, x0, lsl #2\]
-+[^:]+: a560c3e0 ld4w {z0.s-z3.s}, p0/z, \[sp, x0, lsl #2\]
-+[^:]+: a564c000 ld4w {z0.s-z3.s}, p0/z, \[x0, x4, lsl #2\]
-+[^:]+: a564c000 ld4w {z0.s-z3.s}, p0/z, \[x0, x4, lsl #2\]
-+[^:]+: a564c000 ld4w {z0.s-z3.s}, p0/z, \[x0, x4, lsl #2\]
-+[^:]+: a57ec000 ld4w {z0.s-z3.s}, p0/z, \[x0, x30, lsl #2\]
-+[^:]+: a57ec000 ld4w {z0.s-z3.s}, p0/z, \[x0, x30, lsl #2\]
-+[^:]+: a57ec000 ld4w {z0.s-z3.s}, p0/z, \[x0, x30, lsl #2\]
-+[^:]+: a560e000 ld4w {z0.s-z3.s}, p0/z, \[x0\]
-+[^:]+: a560e000 ld4w {z0.s-z3.s}, p0/z, \[x0\]
-+[^:]+: a560e000 ld4w {z0.s-z3.s}, p0/z, \[x0\]
-+[^:]+: a560e000 ld4w {z0.s-z3.s}, p0/z, \[x0\]
-+[^:]+: a560e000 ld4w {z0.s-z3.s}, p0/z, \[x0\]
-+[^:]+: a560e000 ld4w {z0.s-z3.s}, p0/z, \[x0\]
-+[^:]+: a560e000 ld4w {z0.s-z3.s}, p0/z, \[x0\]
-+[^:]+: a560e001 ld4w {z1.s-z4.s}, p0/z, \[x0\]
-+[^:]+: a560e001 ld4w {z1.s-z4.s}, p0/z, \[x0\]
-+[^:]+: a560e001 ld4w {z1.s-z4.s}, p0/z, \[x0\]
-+[^:]+: a560e001 ld4w {z1.s-z4.s}, p0/z, \[x0\]
-+[^:]+: a560e001 ld4w {z1.s-z4.s}, p0/z, \[x0\]
-+[^:]+: a560e001 ld4w {z1.s-z4.s}, p0/z, \[x0\]
-+[^:]+: a560e001 ld4w {z1.s-z4.s}, p0/z, \[x0\]
-+[^:]+: a560e01f ld4w {z31.s, z0.s, z1.s, z2.s}, p0/z, \[x0\]
-+[^:]+: a560e01f ld4w {z31.s, z0.s, z1.s, z2.s}, p0/z, \[x0\]
-+[^:]+: a560e01f ld4w {z31.s, z0.s, z1.s, z2.s}, p0/z, \[x0\]
-+[^:]+: a560e01f ld4w {z31.s, z0.s, z1.s, z2.s}, p0/z, \[x0\]
-+[^:]+: a560e800 ld4w {z0.s-z3.s}, p2/z, \[x0\]
-+[^:]+: a560e800 ld4w {z0.s-z3.s}, p2/z, \[x0\]
-+[^:]+: a560e800 ld4w {z0.s-z3.s}, p2/z, \[x0\]
-+[^:]+: a560e800 ld4w {z0.s-z3.s}, p2/z, \[x0\]
-+[^:]+: a560e800 ld4w {z0.s-z3.s}, p2/z, \[x0\]
-+[^:]+: a560e800 ld4w {z0.s-z3.s}, p2/z, \[x0\]
-+[^:]+: a560e800 ld4w {z0.s-z3.s}, p2/z, \[x0\]
-+[^:]+: a560fc00 ld4w {z0.s-z3.s}, p7/z, \[x0\]
-+[^:]+: a560fc00 ld4w {z0.s-z3.s}, p7/z, \[x0\]
-+[^:]+: a560fc00 ld4w {z0.s-z3.s}, p7/z, \[x0\]
-+[^:]+: a560fc00 ld4w {z0.s-z3.s}, p7/z, \[x0\]
-+[^:]+: a560fc00 ld4w {z0.s-z3.s}, p7/z, \[x0\]
-+[^:]+: a560fc00 ld4w {z0.s-z3.s}, p7/z, \[x0\]
-+[^:]+: a560fc00 ld4w {z0.s-z3.s}, p7/z, \[x0\]
-+[^:]+: a560e060 ld4w {z0.s-z3.s}, p0/z, \[x3\]
-+[^:]+: a560e060 ld4w {z0.s-z3.s}, p0/z, \[x3\]
-+[^:]+: a560e060 ld4w {z0.s-z3.s}, p0/z, \[x3\]
-+[^:]+: a560e060 ld4w {z0.s-z3.s}, p0/z, \[x3\]
-+[^:]+: a560e060 ld4w {z0.s-z3.s}, p0/z, \[x3\]
-+[^:]+: a560e060 ld4w {z0.s-z3.s}, p0/z, \[x3\]
-+[^:]+: a560e060 ld4w {z0.s-z3.s}, p0/z, \[x3\]
-+[^:]+: a560e3e0 ld4w {z0.s-z3.s}, p0/z, \[sp\]
-+[^:]+: a560e3e0 ld4w {z0.s-z3.s}, p0/z, \[sp\]
-+[^:]+: a560e3e0 ld4w {z0.s-z3.s}, p0/z, \[sp\]
-+[^:]+: a560e3e0 ld4w {z0.s-z3.s}, p0/z, \[sp\]
-+[^:]+: a560e3e0 ld4w {z0.s-z3.s}, p0/z, \[sp\]
-+[^:]+: a560e3e0 ld4w {z0.s-z3.s}, p0/z, \[sp\]
-+[^:]+: a560e3e0 ld4w {z0.s-z3.s}, p0/z, \[sp\]
-+[^:]+: a567e000 ld4w {z0.s-z3.s}, p0/z, \[x0, #28, mul vl\]
-+[^:]+: a567e000 ld4w {z0.s-z3.s}, p0/z, \[x0, #28, mul vl\]
-+[^:]+: a567e000 ld4w {z0.s-z3.s}, p0/z, \[x0, #28, mul vl\]
-+[^:]+: a568e000 ld4w {z0.s-z3.s}, p0/z, \[x0, #-32, mul vl\]
-+[^:]+: a568e000 ld4w {z0.s-z3.s}, p0/z, \[x0, #-32, mul vl\]
-+[^:]+: a568e000 ld4w {z0.s-z3.s}, p0/z, \[x0, #-32, mul vl\]
-+[^:]+: a569e000 ld4w {z0.s-z3.s}, p0/z, \[x0, #-28, mul vl\]
-+[^:]+: a569e000 ld4w {z0.s-z3.s}, p0/z, \[x0, #-28, mul vl\]
-+[^:]+: a569e000 ld4w {z0.s-z3.s}, p0/z, \[x0, #-28, mul vl\]
-+[^:]+: a56fe000 ld4w {z0.s-z3.s}, p0/z, \[x0, #-4, mul vl\]
-+[^:]+: a56fe000 ld4w {z0.s-z3.s}, p0/z, \[x0, #-4, mul vl\]
-+[^:]+: a56fe000 ld4w {z0.s-z3.s}, p0/z, \[x0, #-4, mul vl\]
-+[^:]+: 84006000 ldff1b {z0.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84006000 ldff1b {z0.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84006000 ldff1b {z0.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84006000 ldff1b {z0.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84006001 ldff1b {z1.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84006001 ldff1b {z1.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84006001 ldff1b {z1.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84006001 ldff1b {z1.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 8400601f ldff1b {z31.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 8400601f ldff1b {z31.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 8400601f ldff1b {z31.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 8400601f ldff1b {z31.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84006800 ldff1b {z0.s}, p2/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84006800 ldff1b {z0.s}, p2/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84006800 ldff1b {z0.s}, p2/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84007c00 ldff1b {z0.s}, p7/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84007c00 ldff1b {z0.s}, p7/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84007c00 ldff1b {z0.s}, p7/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84006060 ldff1b {z0.s}, p0/z, \[x3, z0.s, uxtw\]
-+[^:]+: 84006060 ldff1b {z0.s}, p0/z, \[x3, z0.s, uxtw\]
-+[^:]+: 84006060 ldff1b {z0.s}, p0/z, \[x3, z0.s, uxtw\]
-+[^:]+: 840063e0 ldff1b {z0.s}, p0/z, \[sp, z0.s, uxtw\]
-+[^:]+: 840063e0 ldff1b {z0.s}, p0/z, \[sp, z0.s, uxtw\]
-+[^:]+: 840063e0 ldff1b {z0.s}, p0/z, \[sp, z0.s, uxtw\]
-+[^:]+: 84046000 ldff1b {z0.s}, p0/z, \[x0, z4.s, uxtw\]
-+[^:]+: 84046000 ldff1b {z0.s}, p0/z, \[x0, z4.s, uxtw\]
-+[^:]+: 84046000 ldff1b {z0.s}, p0/z, \[x0, z4.s, uxtw\]
-+[^:]+: 841f6000 ldff1b {z0.s}, p0/z, \[x0, z31.s, uxtw\]
-+[^:]+: 841f6000 ldff1b {z0.s}, p0/z, \[x0, z31.s, uxtw\]
-+[^:]+: 841f6000 ldff1b {z0.s}, p0/z, \[x0, z31.s, uxtw\]
-+[^:]+: 84406000 ldff1b {z0.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84406000 ldff1b {z0.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84406000 ldff1b {z0.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84406000 ldff1b {z0.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84406001 ldff1b {z1.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84406001 ldff1b {z1.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84406001 ldff1b {z1.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84406001 ldff1b {z1.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 8440601f ldff1b {z31.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 8440601f ldff1b {z31.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 8440601f ldff1b {z31.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 8440601f ldff1b {z31.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84406800 ldff1b {z0.s}, p2/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84406800 ldff1b {z0.s}, p2/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84406800 ldff1b {z0.s}, p2/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84407c00 ldff1b {z0.s}, p7/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84407c00 ldff1b {z0.s}, p7/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84407c00 ldff1b {z0.s}, p7/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84406060 ldff1b {z0.s}, p0/z, \[x3, z0.s, sxtw\]
-+[^:]+: 84406060 ldff1b {z0.s}, p0/z, \[x3, z0.s, sxtw\]
-+[^:]+: 84406060 ldff1b {z0.s}, p0/z, \[x3, z0.s, sxtw\]
-+[^:]+: 844063e0 ldff1b {z0.s}, p0/z, \[sp, z0.s, sxtw\]
-+[^:]+: 844063e0 ldff1b {z0.s}, p0/z, \[sp, z0.s, sxtw\]
-+[^:]+: 844063e0 ldff1b {z0.s}, p0/z, \[sp, z0.s, sxtw\]
-+[^:]+: 84446000 ldff1b {z0.s}, p0/z, \[x0, z4.s, sxtw\]
-+[^:]+: 84446000 ldff1b {z0.s}, p0/z, \[x0, z4.s, sxtw\]
-+[^:]+: 84446000 ldff1b {z0.s}, p0/z, \[x0, z4.s, sxtw\]
-+[^:]+: 845f6000 ldff1b {z0.s}, p0/z, \[x0, z31.s, sxtw\]
-+[^:]+: 845f6000 ldff1b {z0.s}, p0/z, \[x0, z31.s, sxtw\]
-+[^:]+: 845f6000 ldff1b {z0.s}, p0/z, \[x0, z31.s, sxtw\]
-+[^:]+: a4006000 ldff1b {z0.b}, p0/z, \[x0, x0\]
-+[^:]+: a4006000 ldff1b {z0.b}, p0/z, \[x0, x0\]
-+[^:]+: a4006000 ldff1b {z0.b}, p0/z, \[x0, x0\]
-+[^:]+: a4006000 ldff1b {z0.b}, p0/z, \[x0, x0\]
-+[^:]+: a4006001 ldff1b {z1.b}, p0/z, \[x0, x0\]
-+[^:]+: a4006001 ldff1b {z1.b}, p0/z, \[x0, x0\]
-+[^:]+: a4006001 ldff1b {z1.b}, p0/z, \[x0, x0\]
-+[^:]+: a4006001 ldff1b {z1.b}, p0/z, \[x0, x0\]
-+[^:]+: a400601f ldff1b {z31.b}, p0/z, \[x0, x0\]
-+[^:]+: a400601f ldff1b {z31.b}, p0/z, \[x0, x0\]
-+[^:]+: a400601f ldff1b {z31.b}, p0/z, \[x0, x0\]
-+[^:]+: a400601f ldff1b {z31.b}, p0/z, \[x0, x0\]
-+[^:]+: a4006800 ldff1b {z0.b}, p2/z, \[x0, x0\]
-+[^:]+: a4006800 ldff1b {z0.b}, p2/z, \[x0, x0\]
-+[^:]+: a4006800 ldff1b {z0.b}, p2/z, \[x0, x0\]
-+[^:]+: a4007c00 ldff1b {z0.b}, p7/z, \[x0, x0\]
-+[^:]+: a4007c00 ldff1b {z0.b}, p7/z, \[x0, x0\]
-+[^:]+: a4007c00 ldff1b {z0.b}, p7/z, \[x0, x0\]
-+[^:]+: a4006060 ldff1b {z0.b}, p0/z, \[x3, x0\]
-+[^:]+: a4006060 ldff1b {z0.b}, p0/z, \[x3, x0\]
-+[^:]+: a4006060 ldff1b {z0.b}, p0/z, \[x3, x0\]
-+[^:]+: a40063e0 ldff1b {z0.b}, p0/z, \[sp, x0\]
-+[^:]+: a40063e0 ldff1b {z0.b}, p0/z, \[sp, x0\]
-+[^:]+: a40063e0 ldff1b {z0.b}, p0/z, \[sp, x0\]
-+[^:]+: a4046000 ldff1b {z0.b}, p0/z, \[x0, x4\]
-+[^:]+: a4046000 ldff1b {z0.b}, p0/z, \[x0, x4\]
-+[^:]+: a4046000 ldff1b {z0.b}, p0/z, \[x0, x4\]
-+[^:]+: a41f6000 ldff1b {z0.b}, p0/z, \[x0, xzr\]
-+[^:]+: a41f6000 ldff1b {z0.b}, p0/z, \[x0, xzr\]
-+[^:]+: a41f6000 ldff1b {z0.b}, p0/z, \[x0, xzr\]
-+[^:]+: a4206000 ldff1b {z0.h}, p0/z, \[x0, x0\]
-+[^:]+: a4206000 ldff1b {z0.h}, p0/z, \[x0, x0\]
-+[^:]+: a4206000 ldff1b {z0.h}, p0/z, \[x0, x0\]
-+[^:]+: a4206000 ldff1b {z0.h}, p0/z, \[x0, x0\]
-+[^:]+: a4206001 ldff1b {z1.h}, p0/z, \[x0, x0\]
-+[^:]+: a4206001 ldff1b {z1.h}, p0/z, \[x0, x0\]
-+[^:]+: a4206001 ldff1b {z1.h}, p0/z, \[x0, x0\]
-+[^:]+: a4206001 ldff1b {z1.h}, p0/z, \[x0, x0\]
-+[^:]+: a420601f ldff1b {z31.h}, p0/z, \[x0, x0\]
-+[^:]+: a420601f ldff1b {z31.h}, p0/z, \[x0, x0\]
-+[^:]+: a420601f ldff1b {z31.h}, p0/z, \[x0, x0\]
-+[^:]+: a420601f ldff1b {z31.h}, p0/z, \[x0, x0\]
-+[^:]+: a4206800 ldff1b {z0.h}, p2/z, \[x0, x0\]
-+[^:]+: a4206800 ldff1b {z0.h}, p2/z, \[x0, x0\]
-+[^:]+: a4206800 ldff1b {z0.h}, p2/z, \[x0, x0\]
-+[^:]+: a4207c00 ldff1b {z0.h}, p7/z, \[x0, x0\]
-+[^:]+: a4207c00 ldff1b {z0.h}, p7/z, \[x0, x0\]
-+[^:]+: a4207c00 ldff1b {z0.h}, p7/z, \[x0, x0\]
-+[^:]+: a4206060 ldff1b {z0.h}, p0/z, \[x3, x0\]
-+[^:]+: a4206060 ldff1b {z0.h}, p0/z, \[x3, x0\]
-+[^:]+: a4206060 ldff1b {z0.h}, p0/z, \[x3, x0\]
-+[^:]+: a42063e0 ldff1b {z0.h}, p0/z, \[sp, x0\]
-+[^:]+: a42063e0 ldff1b {z0.h}, p0/z, \[sp, x0\]
-+[^:]+: a42063e0 ldff1b {z0.h}, p0/z, \[sp, x0\]
-+[^:]+: a4246000 ldff1b {z0.h}, p0/z, \[x0, x4\]
-+[^:]+: a4246000 ldff1b {z0.h}, p0/z, \[x0, x4\]
-+[^:]+: a4246000 ldff1b {z0.h}, p0/z, \[x0, x4\]
-+[^:]+: a43f6000 ldff1b {z0.h}, p0/z, \[x0, xzr\]
-+[^:]+: a43f6000 ldff1b {z0.h}, p0/z, \[x0, xzr\]
-+[^:]+: a43f6000 ldff1b {z0.h}, p0/z, \[x0, xzr\]
-+[^:]+: a4406000 ldff1b {z0.s}, p0/z, \[x0, x0\]
-+[^:]+: a4406000 ldff1b {z0.s}, p0/z, \[x0, x0\]
-+[^:]+: a4406000 ldff1b {z0.s}, p0/z, \[x0, x0\]
-+[^:]+: a4406000 ldff1b {z0.s}, p0/z, \[x0, x0\]
-+[^:]+: a4406001 ldff1b {z1.s}, p0/z, \[x0, x0\]
-+[^:]+: a4406001 ldff1b {z1.s}, p0/z, \[x0, x0\]
-+[^:]+: a4406001 ldff1b {z1.s}, p0/z, \[x0, x0\]
-+[^:]+: a4406001 ldff1b {z1.s}, p0/z, \[x0, x0\]
-+[^:]+: a440601f ldff1b {z31.s}, p0/z, \[x0, x0\]
-+[^:]+: a440601f ldff1b {z31.s}, p0/z, \[x0, x0\]
-+[^:]+: a440601f ldff1b {z31.s}, p0/z, \[x0, x0\]
-+[^:]+: a440601f ldff1b {z31.s}, p0/z, \[x0, x0\]
-+[^:]+: a4406800 ldff1b {z0.s}, p2/z, \[x0, x0\]
-+[^:]+: a4406800 ldff1b {z0.s}, p2/z, \[x0, x0\]
-+[^:]+: a4406800 ldff1b {z0.s}, p2/z, \[x0, x0\]
-+[^:]+: a4407c00 ldff1b {z0.s}, p7/z, \[x0, x0\]
-+[^:]+: a4407c00 ldff1b {z0.s}, p7/z, \[x0, x0\]
-+[^:]+: a4407c00 ldff1b {z0.s}, p7/z, \[x0, x0\]
-+[^:]+: a4406060 ldff1b {z0.s}, p0/z, \[x3, x0\]
-+[^:]+: a4406060 ldff1b {z0.s}, p0/z, \[x3, x0\]
-+[^:]+: a4406060 ldff1b {z0.s}, p0/z, \[x3, x0\]
-+[^:]+: a44063e0 ldff1b {z0.s}, p0/z, \[sp, x0\]
-+[^:]+: a44063e0 ldff1b {z0.s}, p0/z, \[sp, x0\]
-+[^:]+: a44063e0 ldff1b {z0.s}, p0/z, \[sp, x0\]
-+[^:]+: a4446000 ldff1b {z0.s}, p0/z, \[x0, x4\]
-+[^:]+: a4446000 ldff1b {z0.s}, p0/z, \[x0, x4\]
-+[^:]+: a4446000 ldff1b {z0.s}, p0/z, \[x0, x4\]
-+[^:]+: a45f6000 ldff1b {z0.s}, p0/z, \[x0, xzr\]
-+[^:]+: a45f6000 ldff1b {z0.s}, p0/z, \[x0, xzr\]
-+[^:]+: a45f6000 ldff1b {z0.s}, p0/z, \[x0, xzr\]
-+[^:]+: a4606000 ldff1b {z0.d}, p0/z, \[x0, x0\]
-+[^:]+: a4606000 ldff1b {z0.d}, p0/z, \[x0, x0\]
-+[^:]+: a4606000 ldff1b {z0.d}, p0/z, \[x0, x0\]
-+[^:]+: a4606000 ldff1b {z0.d}, p0/z, \[x0, x0\]
-+[^:]+: a4606001 ldff1b {z1.d}, p0/z, \[x0, x0\]
-+[^:]+: a4606001 ldff1b {z1.d}, p0/z, \[x0, x0\]
-+[^:]+: a4606001 ldff1b {z1.d}, p0/z, \[x0, x0\]
-+[^:]+: a4606001 ldff1b {z1.d}, p0/z, \[x0, x0\]
-+[^:]+: a460601f ldff1b {z31.d}, p0/z, \[x0, x0\]
-+[^:]+: a460601f ldff1b {z31.d}, p0/z, \[x0, x0\]
-+[^:]+: a460601f ldff1b {z31.d}, p0/z, \[x0, x0\]
-+[^:]+: a460601f ldff1b {z31.d}, p0/z, \[x0, x0\]
-+[^:]+: a4606800 ldff1b {z0.d}, p2/z, \[x0, x0\]
-+[^:]+: a4606800 ldff1b {z0.d}, p2/z, \[x0, x0\]
-+[^:]+: a4606800 ldff1b {z0.d}, p2/z, \[x0, x0\]
-+[^:]+: a4607c00 ldff1b {z0.d}, p7/z, \[x0, x0\]
-+[^:]+: a4607c00 ldff1b {z0.d}, p7/z, \[x0, x0\]
-+[^:]+: a4607c00 ldff1b {z0.d}, p7/z, \[x0, x0\]
-+[^:]+: a4606060 ldff1b {z0.d}, p0/z, \[x3, x0\]
-+[^:]+: a4606060 ldff1b {z0.d}, p0/z, \[x3, x0\]
-+[^:]+: a4606060 ldff1b {z0.d}, p0/z, \[x3, x0\]
-+[^:]+: a46063e0 ldff1b {z0.d}, p0/z, \[sp, x0\]
-+[^:]+: a46063e0 ldff1b {z0.d}, p0/z, \[sp, x0\]
-+[^:]+: a46063e0 ldff1b {z0.d}, p0/z, \[sp, x0\]
-+[^:]+: a4646000 ldff1b {z0.d}, p0/z, \[x0, x4\]
-+[^:]+: a4646000 ldff1b {z0.d}, p0/z, \[x0, x4\]
-+[^:]+: a4646000 ldff1b {z0.d}, p0/z, \[x0, x4\]
-+[^:]+: a47f6000 ldff1b {z0.d}, p0/z, \[x0, xzr\]
-+[^:]+: a47f6000 ldff1b {z0.d}, p0/z, \[x0, xzr\]
-+[^:]+: a47f6000 ldff1b {z0.d}, p0/z, \[x0, xzr\]
-+[^:]+: c4006000 ldff1b {z0.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4006000 ldff1b {z0.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4006000 ldff1b {z0.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4006000 ldff1b {z0.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4006001 ldff1b {z1.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4006001 ldff1b {z1.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4006001 ldff1b {z1.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4006001 ldff1b {z1.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c400601f ldff1b {z31.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c400601f ldff1b {z31.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c400601f ldff1b {z31.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c400601f ldff1b {z31.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4006800 ldff1b {z0.d}, p2/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4006800 ldff1b {z0.d}, p2/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4006800 ldff1b {z0.d}, p2/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4007c00 ldff1b {z0.d}, p7/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4007c00 ldff1b {z0.d}, p7/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4007c00 ldff1b {z0.d}, p7/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4006060 ldff1b {z0.d}, p0/z, \[x3, z0.d, uxtw\]
-+[^:]+: c4006060 ldff1b {z0.d}, p0/z, \[x3, z0.d, uxtw\]
-+[^:]+: c4006060 ldff1b {z0.d}, p0/z, \[x3, z0.d, uxtw\]
-+[^:]+: c40063e0 ldff1b {z0.d}, p0/z, \[sp, z0.d, uxtw\]
-+[^:]+: c40063e0 ldff1b {z0.d}, p0/z, \[sp, z0.d, uxtw\]
-+[^:]+: c40063e0 ldff1b {z0.d}, p0/z, \[sp, z0.d, uxtw\]
-+[^:]+: c4046000 ldff1b {z0.d}, p0/z, \[x0, z4.d, uxtw\]
-+[^:]+: c4046000 ldff1b {z0.d}, p0/z, \[x0, z4.d, uxtw\]
-+[^:]+: c4046000 ldff1b {z0.d}, p0/z, \[x0, z4.d, uxtw\]
-+[^:]+: c41f6000 ldff1b {z0.d}, p0/z, \[x0, z31.d, uxtw\]
-+[^:]+: c41f6000 ldff1b {z0.d}, p0/z, \[x0, z31.d, uxtw\]
-+[^:]+: c41f6000 ldff1b {z0.d}, p0/z, \[x0, z31.d, uxtw\]
-+[^:]+: c4406000 ldff1b {z0.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4406000 ldff1b {z0.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4406000 ldff1b {z0.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4406000 ldff1b {z0.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4406001 ldff1b {z1.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4406001 ldff1b {z1.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4406001 ldff1b {z1.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4406001 ldff1b {z1.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c440601f ldff1b {z31.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c440601f ldff1b {z31.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c440601f ldff1b {z31.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c440601f ldff1b {z31.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4406800 ldff1b {z0.d}, p2/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4406800 ldff1b {z0.d}, p2/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4406800 ldff1b {z0.d}, p2/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4407c00 ldff1b {z0.d}, p7/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4407c00 ldff1b {z0.d}, p7/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4407c00 ldff1b {z0.d}, p7/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4406060 ldff1b {z0.d}, p0/z, \[x3, z0.d, sxtw\]
-+[^:]+: c4406060 ldff1b {z0.d}, p0/z, \[x3, z0.d, sxtw\]
-+[^:]+: c4406060 ldff1b {z0.d}, p0/z, \[x3, z0.d, sxtw\]
-+[^:]+: c44063e0 ldff1b {z0.d}, p0/z, \[sp, z0.d, sxtw\]
-+[^:]+: c44063e0 ldff1b {z0.d}, p0/z, \[sp, z0.d, sxtw\]
-+[^:]+: c44063e0 ldff1b {z0.d}, p0/z, \[sp, z0.d, sxtw\]
-+[^:]+: c4446000 ldff1b {z0.d}, p0/z, \[x0, z4.d, sxtw\]
-+[^:]+: c4446000 ldff1b {z0.d}, p0/z, \[x0, z4.d, sxtw\]
-+[^:]+: c4446000 ldff1b {z0.d}, p0/z, \[x0, z4.d, sxtw\]
-+[^:]+: c45f6000 ldff1b {z0.d}, p0/z, \[x0, z31.d, sxtw\]
-+[^:]+: c45f6000 ldff1b {z0.d}, p0/z, \[x0, z31.d, sxtw\]
-+[^:]+: c45f6000 ldff1b {z0.d}, p0/z, \[x0, z31.d, sxtw\]
-+[^:]+: c440e000 ldff1b {z0.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c440e000 ldff1b {z0.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c440e000 ldff1b {z0.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c440e000 ldff1b {z0.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c440e001 ldff1b {z1.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c440e001 ldff1b {z1.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c440e001 ldff1b {z1.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c440e001 ldff1b {z1.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c440e01f ldff1b {z31.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c440e01f ldff1b {z31.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c440e01f ldff1b {z31.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c440e01f ldff1b {z31.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c440e800 ldff1b {z0.d}, p2/z, \[x0, z0.d\]
-+[^:]+: c440e800 ldff1b {z0.d}, p2/z, \[x0, z0.d\]
-+[^:]+: c440e800 ldff1b {z0.d}, p2/z, \[x0, z0.d\]
-+[^:]+: c440fc00 ldff1b {z0.d}, p7/z, \[x0, z0.d\]
-+[^:]+: c440fc00 ldff1b {z0.d}, p7/z, \[x0, z0.d\]
-+[^:]+: c440fc00 ldff1b {z0.d}, p7/z, \[x0, z0.d\]
-+[^:]+: c440e060 ldff1b {z0.d}, p0/z, \[x3, z0.d\]
-+[^:]+: c440e060 ldff1b {z0.d}, p0/z, \[x3, z0.d\]
-+[^:]+: c440e060 ldff1b {z0.d}, p0/z, \[x3, z0.d\]
-+[^:]+: c440e3e0 ldff1b {z0.d}, p0/z, \[sp, z0.d\]
-+[^:]+: c440e3e0 ldff1b {z0.d}, p0/z, \[sp, z0.d\]
-+[^:]+: c440e3e0 ldff1b {z0.d}, p0/z, \[sp, z0.d\]
-+[^:]+: c444e000 ldff1b {z0.d}, p0/z, \[x0, z4.d\]
-+[^:]+: c444e000 ldff1b {z0.d}, p0/z, \[x0, z4.d\]
-+[^:]+: c444e000 ldff1b {z0.d}, p0/z, \[x0, z4.d\]
-+[^:]+: c45fe000 ldff1b {z0.d}, p0/z, \[x0, z31.d\]
-+[^:]+: c45fe000 ldff1b {z0.d}, p0/z, \[x0, z31.d\]
-+[^:]+: c45fe000 ldff1b {z0.d}, p0/z, \[x0, z31.d\]
-+[^:]+: 8420e000 ldff1b {z0.s}, p0/z, \[z0.s\]
-+[^:]+: 8420e000 ldff1b {z0.s}, p0/z, \[z0.s\]
-+[^:]+: 8420e000 ldff1b {z0.s}, p0/z, \[z0.s\]
-+[^:]+: 8420e000 ldff1b {z0.s}, p0/z, \[z0.s\]
-+[^:]+: 8420e001 ldff1b {z1.s}, p0/z, \[z0.s\]
-+[^:]+: 8420e001 ldff1b {z1.s}, p0/z, \[z0.s\]
-+[^:]+: 8420e001 ldff1b {z1.s}, p0/z, \[z0.s\]
-+[^:]+: 8420e001 ldff1b {z1.s}, p0/z, \[z0.s\]
-+[^:]+: 8420e01f ldff1b {z31.s}, p0/z, \[z0.s\]
-+[^:]+: 8420e01f ldff1b {z31.s}, p0/z, \[z0.s\]
-+[^:]+: 8420e01f ldff1b {z31.s}, p0/z, \[z0.s\]
-+[^:]+: 8420e01f ldff1b {z31.s}, p0/z, \[z0.s\]
-+[^:]+: 8420e800 ldff1b {z0.s}, p2/z, \[z0.s\]
-+[^:]+: 8420e800 ldff1b {z0.s}, p2/z, \[z0.s\]
-+[^:]+: 8420e800 ldff1b {z0.s}, p2/z, \[z0.s\]
-+[^:]+: 8420fc00 ldff1b {z0.s}, p7/z, \[z0.s\]
-+[^:]+: 8420fc00 ldff1b {z0.s}, p7/z, \[z0.s\]
-+[^:]+: 8420fc00 ldff1b {z0.s}, p7/z, \[z0.s\]
-+[^:]+: 8420e060 ldff1b {z0.s}, p0/z, \[z3.s\]
-+[^:]+: 8420e060 ldff1b {z0.s}, p0/z, \[z3.s\]
-+[^:]+: 8420e060 ldff1b {z0.s}, p0/z, \[z3.s\]
-+[^:]+: 8420e3e0 ldff1b {z0.s}, p0/z, \[z31.s\]
-+[^:]+: 8420e3e0 ldff1b {z0.s}, p0/z, \[z31.s\]
-+[^:]+: 8420e3e0 ldff1b {z0.s}, p0/z, \[z31.s\]
-+[^:]+: 842fe000 ldff1b {z0.s}, p0/z, \[z0.s, #15\]
-+[^:]+: 842fe000 ldff1b {z0.s}, p0/z, \[z0.s, #15\]
-+[^:]+: 8430e000 ldff1b {z0.s}, p0/z, \[z0.s, #16\]
-+[^:]+: 8430e000 ldff1b {z0.s}, p0/z, \[z0.s, #16\]
-+[^:]+: 8431e000 ldff1b {z0.s}, p0/z, \[z0.s, #17\]
-+[^:]+: 8431e000 ldff1b {z0.s}, p0/z, \[z0.s, #17\]
-+[^:]+: 843fe000 ldff1b {z0.s}, p0/z, \[z0.s, #31\]
-+[^:]+: 843fe000 ldff1b {z0.s}, p0/z, \[z0.s, #31\]
-+[^:]+: c420e000 ldff1b {z0.d}, p0/z, \[z0.d\]
-+[^:]+: c420e000 ldff1b {z0.d}, p0/z, \[z0.d\]
-+[^:]+: c420e000 ldff1b {z0.d}, p0/z, \[z0.d\]
-+[^:]+: c420e000 ldff1b {z0.d}, p0/z, \[z0.d\]
-+[^:]+: c420e001 ldff1b {z1.d}, p0/z, \[z0.d\]
-+[^:]+: c420e001 ldff1b {z1.d}, p0/z, \[z0.d\]
-+[^:]+: c420e001 ldff1b {z1.d}, p0/z, \[z0.d\]
-+[^:]+: c420e001 ldff1b {z1.d}, p0/z, \[z0.d\]
-+[^:]+: c420e01f ldff1b {z31.d}, p0/z, \[z0.d\]
-+[^:]+: c420e01f ldff1b {z31.d}, p0/z, \[z0.d\]
-+[^:]+: c420e01f ldff1b {z31.d}, p0/z, \[z0.d\]
-+[^:]+: c420e01f ldff1b {z31.d}, p0/z, \[z0.d\]
-+[^:]+: c420e800 ldff1b {z0.d}, p2/z, \[z0.d\]
-+[^:]+: c420e800 ldff1b {z0.d}, p2/z, \[z0.d\]
-+[^:]+: c420e800 ldff1b {z0.d}, p2/z, \[z0.d\]
-+[^:]+: c420fc00 ldff1b {z0.d}, p7/z, \[z0.d\]
-+[^:]+: c420fc00 ldff1b {z0.d}, p7/z, \[z0.d\]
-+[^:]+: c420fc00 ldff1b {z0.d}, p7/z, \[z0.d\]
-+[^:]+: c420e060 ldff1b {z0.d}, p0/z, \[z3.d\]
-+[^:]+: c420e060 ldff1b {z0.d}, p0/z, \[z3.d\]
-+[^:]+: c420e060 ldff1b {z0.d}, p0/z, \[z3.d\]
-+[^:]+: c420e3e0 ldff1b {z0.d}, p0/z, \[z31.d\]
-+[^:]+: c420e3e0 ldff1b {z0.d}, p0/z, \[z31.d\]
-+[^:]+: c420e3e0 ldff1b {z0.d}, p0/z, \[z31.d\]
-+[^:]+: c42fe000 ldff1b {z0.d}, p0/z, \[z0.d, #15\]
-+[^:]+: c42fe000 ldff1b {z0.d}, p0/z, \[z0.d, #15\]
-+[^:]+: c430e000 ldff1b {z0.d}, p0/z, \[z0.d, #16\]
-+[^:]+: c430e000 ldff1b {z0.d}, p0/z, \[z0.d, #16\]
-+[^:]+: c431e000 ldff1b {z0.d}, p0/z, \[z0.d, #17\]
-+[^:]+: c431e000 ldff1b {z0.d}, p0/z, \[z0.d, #17\]
-+[^:]+: c43fe000 ldff1b {z0.d}, p0/z, \[z0.d, #31\]
-+[^:]+: c43fe000 ldff1b {z0.d}, p0/z, \[z0.d, #31\]
-+[^:]+: a5e06000 ldff1d {z0.d}, p0/z, \[x0, x0, lsl #3\]
-+[^:]+: a5e06000 ldff1d {z0.d}, p0/z, \[x0, x0, lsl #3\]
-+[^:]+: a5e06000 ldff1d {z0.d}, p0/z, \[x0, x0, lsl #3\]
-+[^:]+: a5e06001 ldff1d {z1.d}, p0/z, \[x0, x0, lsl #3\]
-+[^:]+: a5e06001 ldff1d {z1.d}, p0/z, \[x0, x0, lsl #3\]
-+[^:]+: a5e06001 ldff1d {z1.d}, p0/z, \[x0, x0, lsl #3\]
-+[^:]+: a5e0601f ldff1d {z31.d}, p0/z, \[x0, x0, lsl #3\]
-+[^:]+: a5e0601f ldff1d {z31.d}, p0/z, \[x0, x0, lsl #3\]
-+[^:]+: a5e0601f ldff1d {z31.d}, p0/z, \[x0, x0, lsl #3\]
-+[^:]+: a5e06800 ldff1d {z0.d}, p2/z, \[x0, x0, lsl #3\]
-+[^:]+: a5e06800 ldff1d {z0.d}, p2/z, \[x0, x0, lsl #3\]
-+[^:]+: a5e07c00 ldff1d {z0.d}, p7/z, \[x0, x0, lsl #3\]
-+[^:]+: a5e07c00 ldff1d {z0.d}, p7/z, \[x0, x0, lsl #3\]
-+[^:]+: a5e06060 ldff1d {z0.d}, p0/z, \[x3, x0, lsl #3\]
-+[^:]+: a5e06060 ldff1d {z0.d}, p0/z, \[x3, x0, lsl #3\]
-+[^:]+: a5e063e0 ldff1d {z0.d}, p0/z, \[sp, x0, lsl #3\]
-+[^:]+: a5e063e0 ldff1d {z0.d}, p0/z, \[sp, x0, lsl #3\]
-+[^:]+: a5e46000 ldff1d {z0.d}, p0/z, \[x0, x4, lsl #3\]
-+[^:]+: a5e46000 ldff1d {z0.d}, p0/z, \[x0, x4, lsl #3\]
-+[^:]+: a5ff6000 ldff1d {z0.d}, p0/z, \[x0, xzr, lsl #3\]
-+[^:]+: a5ff6000 ldff1d {z0.d}, p0/z, \[x0, xzr, lsl #3\]
-+[^:]+: c5806000 ldff1d {z0.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c5806000 ldff1d {z0.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c5806000 ldff1d {z0.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c5806000 ldff1d {z0.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c5806001 ldff1d {z1.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c5806001 ldff1d {z1.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c5806001 ldff1d {z1.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c5806001 ldff1d {z1.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c580601f ldff1d {z31.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c580601f ldff1d {z31.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c580601f ldff1d {z31.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c580601f ldff1d {z31.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c5806800 ldff1d {z0.d}, p2/z, \[x0, z0.d, uxtw\]
-+[^:]+: c5806800 ldff1d {z0.d}, p2/z, \[x0, z0.d, uxtw\]
-+[^:]+: c5806800 ldff1d {z0.d}, p2/z, \[x0, z0.d, uxtw\]
-+[^:]+: c5807c00 ldff1d {z0.d}, p7/z, \[x0, z0.d, uxtw\]
-+[^:]+: c5807c00 ldff1d {z0.d}, p7/z, \[x0, z0.d, uxtw\]
-+[^:]+: c5807c00 ldff1d {z0.d}, p7/z, \[x0, z0.d, uxtw\]
-+[^:]+: c5806060 ldff1d {z0.d}, p0/z, \[x3, z0.d, uxtw\]
-+[^:]+: c5806060 ldff1d {z0.d}, p0/z, \[x3, z0.d, uxtw\]
-+[^:]+: c5806060 ldff1d {z0.d}, p0/z, \[x3, z0.d, uxtw\]
-+[^:]+: c58063e0 ldff1d {z0.d}, p0/z, \[sp, z0.d, uxtw\]
-+[^:]+: c58063e0 ldff1d {z0.d}, p0/z, \[sp, z0.d, uxtw\]
-+[^:]+: c58063e0 ldff1d {z0.d}, p0/z, \[sp, z0.d, uxtw\]
-+[^:]+: c5846000 ldff1d {z0.d}, p0/z, \[x0, z4.d, uxtw\]
-+[^:]+: c5846000 ldff1d {z0.d}, p0/z, \[x0, z4.d, uxtw\]
-+[^:]+: c5846000 ldff1d {z0.d}, p0/z, \[x0, z4.d, uxtw\]
-+[^:]+: c59f6000 ldff1d {z0.d}, p0/z, \[x0, z31.d, uxtw\]
-+[^:]+: c59f6000 ldff1d {z0.d}, p0/z, \[x0, z31.d, uxtw\]
-+[^:]+: c59f6000 ldff1d {z0.d}, p0/z, \[x0, z31.d, uxtw\]
-+[^:]+: c5c06000 ldff1d {z0.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5c06000 ldff1d {z0.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5c06000 ldff1d {z0.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5c06000 ldff1d {z0.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5c06001 ldff1d {z1.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5c06001 ldff1d {z1.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5c06001 ldff1d {z1.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5c06001 ldff1d {z1.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5c0601f ldff1d {z31.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5c0601f ldff1d {z31.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5c0601f ldff1d {z31.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5c0601f ldff1d {z31.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5c06800 ldff1d {z0.d}, p2/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5c06800 ldff1d {z0.d}, p2/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5c06800 ldff1d {z0.d}, p2/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5c07c00 ldff1d {z0.d}, p7/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5c07c00 ldff1d {z0.d}, p7/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5c07c00 ldff1d {z0.d}, p7/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5c06060 ldff1d {z0.d}, p0/z, \[x3, z0.d, sxtw\]
-+[^:]+: c5c06060 ldff1d {z0.d}, p0/z, \[x3, z0.d, sxtw\]
-+[^:]+: c5c06060 ldff1d {z0.d}, p0/z, \[x3, z0.d, sxtw\]
-+[^:]+: c5c063e0 ldff1d {z0.d}, p0/z, \[sp, z0.d, sxtw\]
-+[^:]+: c5c063e0 ldff1d {z0.d}, p0/z, \[sp, z0.d, sxtw\]
-+[^:]+: c5c063e0 ldff1d {z0.d}, p0/z, \[sp, z0.d, sxtw\]
-+[^:]+: c5c46000 ldff1d {z0.d}, p0/z, \[x0, z4.d, sxtw\]
-+[^:]+: c5c46000 ldff1d {z0.d}, p0/z, \[x0, z4.d, sxtw\]
-+[^:]+: c5c46000 ldff1d {z0.d}, p0/z, \[x0, z4.d, sxtw\]
-+[^:]+: c5df6000 ldff1d {z0.d}, p0/z, \[x0, z31.d, sxtw\]
-+[^:]+: c5df6000 ldff1d {z0.d}, p0/z, \[x0, z31.d, sxtw\]
-+[^:]+: c5df6000 ldff1d {z0.d}, p0/z, \[x0, z31.d, sxtw\]
-+[^:]+: c5a06000 ldff1d {z0.d}, p0/z, \[x0, z0.d, uxtw #3\]
-+[^:]+: c5a06000 ldff1d {z0.d}, p0/z, \[x0, z0.d, uxtw #3\]
-+[^:]+: c5a06000 ldff1d {z0.d}, p0/z, \[x0, z0.d, uxtw #3\]
-+[^:]+: c5a06001 ldff1d {z1.d}, p0/z, \[x0, z0.d, uxtw #3\]
-+[^:]+: c5a06001 ldff1d {z1.d}, p0/z, \[x0, z0.d, uxtw #3\]
-+[^:]+: c5a06001 ldff1d {z1.d}, p0/z, \[x0, z0.d, uxtw #3\]
-+[^:]+: c5a0601f ldff1d {z31.d}, p0/z, \[x0, z0.d, uxtw #3\]
-+[^:]+: c5a0601f ldff1d {z31.d}, p0/z, \[x0, z0.d, uxtw #3\]
-+[^:]+: c5a0601f ldff1d {z31.d}, p0/z, \[x0, z0.d, uxtw #3\]
-+[^:]+: c5a06800 ldff1d {z0.d}, p2/z, \[x0, z0.d, uxtw #3\]
-+[^:]+: c5a06800 ldff1d {z0.d}, p2/z, \[x0, z0.d, uxtw #3\]
-+[^:]+: c5a07c00 ldff1d {z0.d}, p7/z, \[x0, z0.d, uxtw #3\]
-+[^:]+: c5a07c00 ldff1d {z0.d}, p7/z, \[x0, z0.d, uxtw #3\]
-+[^:]+: c5a06060 ldff1d {z0.d}, p0/z, \[x3, z0.d, uxtw #3\]
-+[^:]+: c5a06060 ldff1d {z0.d}, p0/z, \[x3, z0.d, uxtw #3\]
-+[^:]+: c5a063e0 ldff1d {z0.d}, p0/z, \[sp, z0.d, uxtw #3\]
-+[^:]+: c5a063e0 ldff1d {z0.d}, p0/z, \[sp, z0.d, uxtw #3\]
-+[^:]+: c5a46000 ldff1d {z0.d}, p0/z, \[x0, z4.d, uxtw #3\]
-+[^:]+: c5a46000 ldff1d {z0.d}, p0/z, \[x0, z4.d, uxtw #3\]
-+[^:]+: c5bf6000 ldff1d {z0.d}, p0/z, \[x0, z31.d, uxtw #3\]
-+[^:]+: c5bf6000 ldff1d {z0.d}, p0/z, \[x0, z31.d, uxtw #3\]
-+[^:]+: c5e06000 ldff1d {z0.d}, p0/z, \[x0, z0.d, sxtw #3\]
-+[^:]+: c5e06000 ldff1d {z0.d}, p0/z, \[x0, z0.d, sxtw #3\]
-+[^:]+: c5e06000 ldff1d {z0.d}, p0/z, \[x0, z0.d, sxtw #3\]
-+[^:]+: c5e06001 ldff1d {z1.d}, p0/z, \[x0, z0.d, sxtw #3\]
-+[^:]+: c5e06001 ldff1d {z1.d}, p0/z, \[x0, z0.d, sxtw #3\]
-+[^:]+: c5e06001 ldff1d {z1.d}, p0/z, \[x0, z0.d, sxtw #3\]
-+[^:]+: c5e0601f ldff1d {z31.d}, p0/z, \[x0, z0.d, sxtw #3\]
-+[^:]+: c5e0601f ldff1d {z31.d}, p0/z, \[x0, z0.d, sxtw #3\]
-+[^:]+: c5e0601f ldff1d {z31.d}, p0/z, \[x0, z0.d, sxtw #3\]
-+[^:]+: c5e06800 ldff1d {z0.d}, p2/z, \[x0, z0.d, sxtw #3\]
-+[^:]+: c5e06800 ldff1d {z0.d}, p2/z, \[x0, z0.d, sxtw #3\]
-+[^:]+: c5e07c00 ldff1d {z0.d}, p7/z, \[x0, z0.d, sxtw #3\]
-+[^:]+: c5e07c00 ldff1d {z0.d}, p7/z, \[x0, z0.d, sxtw #3\]
-+[^:]+: c5e06060 ldff1d {z0.d}, p0/z, \[x3, z0.d, sxtw #3\]
-+[^:]+: c5e06060 ldff1d {z0.d}, p0/z, \[x3, z0.d, sxtw #3\]
-+[^:]+: c5e063e0 ldff1d {z0.d}, p0/z, \[sp, z0.d, sxtw #3\]
-+[^:]+: c5e063e0 ldff1d {z0.d}, p0/z, \[sp, z0.d, sxtw #3\]
-+[^:]+: c5e46000 ldff1d {z0.d}, p0/z, \[x0, z4.d, sxtw #3\]
-+[^:]+: c5e46000 ldff1d {z0.d}, p0/z, \[x0, z4.d, sxtw #3\]
-+[^:]+: c5ff6000 ldff1d {z0.d}, p0/z, \[x0, z31.d, sxtw #3\]
-+[^:]+: c5ff6000 ldff1d {z0.d}, p0/z, \[x0, z31.d, sxtw #3\]
-+[^:]+: c5c0e000 ldff1d {z0.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c5c0e000 ldff1d {z0.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c5c0e000 ldff1d {z0.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c5c0e000 ldff1d {z0.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c5c0e001 ldff1d {z1.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c5c0e001 ldff1d {z1.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c5c0e001 ldff1d {z1.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c5c0e001 ldff1d {z1.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c5c0e01f ldff1d {z31.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c5c0e01f ldff1d {z31.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c5c0e01f ldff1d {z31.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c5c0e01f ldff1d {z31.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c5c0e800 ldff1d {z0.d}, p2/z, \[x0, z0.d\]
-+[^:]+: c5c0e800 ldff1d {z0.d}, p2/z, \[x0, z0.d\]
-+[^:]+: c5c0e800 ldff1d {z0.d}, p2/z, \[x0, z0.d\]
-+[^:]+: c5c0fc00 ldff1d {z0.d}, p7/z, \[x0, z0.d\]
-+[^:]+: c5c0fc00 ldff1d {z0.d}, p7/z, \[x0, z0.d\]
-+[^:]+: c5c0fc00 ldff1d {z0.d}, p7/z, \[x0, z0.d\]
-+[^:]+: c5c0e060 ldff1d {z0.d}, p0/z, \[x3, z0.d\]
-+[^:]+: c5c0e060 ldff1d {z0.d}, p0/z, \[x3, z0.d\]
-+[^:]+: c5c0e060 ldff1d {z0.d}, p0/z, \[x3, z0.d\]
-+[^:]+: c5c0e3e0 ldff1d {z0.d}, p0/z, \[sp, z0.d\]
-+[^:]+: c5c0e3e0 ldff1d {z0.d}, p0/z, \[sp, z0.d\]
-+[^:]+: c5c0e3e0 ldff1d {z0.d}, p0/z, \[sp, z0.d\]
-+[^:]+: c5c4e000 ldff1d {z0.d}, p0/z, \[x0, z4.d\]
-+[^:]+: c5c4e000 ldff1d {z0.d}, p0/z, \[x0, z4.d\]
-+[^:]+: c5c4e000 ldff1d {z0.d}, p0/z, \[x0, z4.d\]
-+[^:]+: c5dfe000 ldff1d {z0.d}, p0/z, \[x0, z31.d\]
-+[^:]+: c5dfe000 ldff1d {z0.d}, p0/z, \[x0, z31.d\]
-+[^:]+: c5dfe000 ldff1d {z0.d}, p0/z, \[x0, z31.d\]
-+[^:]+: c5e0e000 ldff1d {z0.d}, p0/z, \[x0, z0.d, lsl #3\]
-+[^:]+: c5e0e000 ldff1d {z0.d}, p0/z, \[x0, z0.d, lsl #3\]
-+[^:]+: c5e0e000 ldff1d {z0.d}, p0/z, \[x0, z0.d, lsl #3\]
-+[^:]+: c5e0e001 ldff1d {z1.d}, p0/z, \[x0, z0.d, lsl #3\]
-+[^:]+: c5e0e001 ldff1d {z1.d}, p0/z, \[x0, z0.d, lsl #3\]
-+[^:]+: c5e0e001 ldff1d {z1.d}, p0/z, \[x0, z0.d, lsl #3\]
-+[^:]+: c5e0e01f ldff1d {z31.d}, p0/z, \[x0, z0.d, lsl #3\]
-+[^:]+: c5e0e01f ldff1d {z31.d}, p0/z, \[x0, z0.d, lsl #3\]
-+[^:]+: c5e0e01f ldff1d {z31.d}, p0/z, \[x0, z0.d, lsl #3\]
-+[^:]+: c5e0e800 ldff1d {z0.d}, p2/z, \[x0, z0.d, lsl #3\]
-+[^:]+: c5e0e800 ldff1d {z0.d}, p2/z, \[x0, z0.d, lsl #3\]
-+[^:]+: c5e0fc00 ldff1d {z0.d}, p7/z, \[x0, z0.d, lsl #3\]
-+[^:]+: c5e0fc00 ldff1d {z0.d}, p7/z, \[x0, z0.d, lsl #3\]
-+[^:]+: c5e0e060 ldff1d {z0.d}, p0/z, \[x3, z0.d, lsl #3\]
-+[^:]+: c5e0e060 ldff1d {z0.d}, p0/z, \[x3, z0.d, lsl #3\]
-+[^:]+: c5e0e3e0 ldff1d {z0.d}, p0/z, \[sp, z0.d, lsl #3\]
-+[^:]+: c5e0e3e0 ldff1d {z0.d}, p0/z, \[sp, z0.d, lsl #3\]
-+[^:]+: c5e4e000 ldff1d {z0.d}, p0/z, \[x0, z4.d, lsl #3\]
-+[^:]+: c5e4e000 ldff1d {z0.d}, p0/z, \[x0, z4.d, lsl #3\]
-+[^:]+: c5ffe000 ldff1d {z0.d}, p0/z, \[x0, z31.d, lsl #3\]
-+[^:]+: c5ffe000 ldff1d {z0.d}, p0/z, \[x0, z31.d, lsl #3\]
-+[^:]+: c5a0e000 ldff1d {z0.d}, p0/z, \[z0.d\]
-+[^:]+: c5a0e000 ldff1d {z0.d}, p0/z, \[z0.d\]
-+[^:]+: c5a0e000 ldff1d {z0.d}, p0/z, \[z0.d\]
-+[^:]+: c5a0e000 ldff1d {z0.d}, p0/z, \[z0.d\]
-+[^:]+: c5a0e001 ldff1d {z1.d}, p0/z, \[z0.d\]
-+[^:]+: c5a0e001 ldff1d {z1.d}, p0/z, \[z0.d\]
-+[^:]+: c5a0e001 ldff1d {z1.d}, p0/z, \[z0.d\]
-+[^:]+: c5a0e001 ldff1d {z1.d}, p0/z, \[z0.d\]
-+[^:]+: c5a0e01f ldff1d {z31.d}, p0/z, \[z0.d\]
-+[^:]+: c5a0e01f ldff1d {z31.d}, p0/z, \[z0.d\]
-+[^:]+: c5a0e01f ldff1d {z31.d}, p0/z, \[z0.d\]
-+[^:]+: c5a0e01f ldff1d {z31.d}, p0/z, \[z0.d\]
-+[^:]+: c5a0e800 ldff1d {z0.d}, p2/z, \[z0.d\]
-+[^:]+: c5a0e800 ldff1d {z0.d}, p2/z, \[z0.d\]
-+[^:]+: c5a0e800 ldff1d {z0.d}, p2/z, \[z0.d\]
-+[^:]+: c5a0fc00 ldff1d {z0.d}, p7/z, \[z0.d\]
-+[^:]+: c5a0fc00 ldff1d {z0.d}, p7/z, \[z0.d\]
-+[^:]+: c5a0fc00 ldff1d {z0.d}, p7/z, \[z0.d\]
-+[^:]+: c5a0e060 ldff1d {z0.d}, p0/z, \[z3.d\]
-+[^:]+: c5a0e060 ldff1d {z0.d}, p0/z, \[z3.d\]
-+[^:]+: c5a0e060 ldff1d {z0.d}, p0/z, \[z3.d\]
-+[^:]+: c5a0e3e0 ldff1d {z0.d}, p0/z, \[z31.d\]
-+[^:]+: c5a0e3e0 ldff1d {z0.d}, p0/z, \[z31.d\]
-+[^:]+: c5a0e3e0 ldff1d {z0.d}, p0/z, \[z31.d\]
-+[^:]+: c5afe000 ldff1d {z0.d}, p0/z, \[z0.d, #120\]
-+[^:]+: c5afe000 ldff1d {z0.d}, p0/z, \[z0.d, #120\]
-+[^:]+: c5b0e000 ldff1d {z0.d}, p0/z, \[z0.d, #128\]
-+[^:]+: c5b0e000 ldff1d {z0.d}, p0/z, \[z0.d, #128\]
-+[^:]+: c5b1e000 ldff1d {z0.d}, p0/z, \[z0.d, #136\]
-+[^:]+: c5b1e000 ldff1d {z0.d}, p0/z, \[z0.d, #136\]
-+[^:]+: c5bfe000 ldff1d {z0.d}, p0/z, \[z0.d, #248\]
-+[^:]+: c5bfe000 ldff1d {z0.d}, p0/z, \[z0.d, #248\]
-+[^:]+: 84806000 ldff1h {z0.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84806000 ldff1h {z0.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84806000 ldff1h {z0.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84806000 ldff1h {z0.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84806001 ldff1h {z1.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84806001 ldff1h {z1.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84806001 ldff1h {z1.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84806001 ldff1h {z1.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 8480601f ldff1h {z31.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 8480601f ldff1h {z31.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 8480601f ldff1h {z31.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 8480601f ldff1h {z31.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84806800 ldff1h {z0.s}, p2/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84806800 ldff1h {z0.s}, p2/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84806800 ldff1h {z0.s}, p2/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84807c00 ldff1h {z0.s}, p7/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84807c00 ldff1h {z0.s}, p7/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84807c00 ldff1h {z0.s}, p7/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84806060 ldff1h {z0.s}, p0/z, \[x3, z0.s, uxtw\]
-+[^:]+: 84806060 ldff1h {z0.s}, p0/z, \[x3, z0.s, uxtw\]
-+[^:]+: 84806060 ldff1h {z0.s}, p0/z, \[x3, z0.s, uxtw\]
-+[^:]+: 848063e0 ldff1h {z0.s}, p0/z, \[sp, z0.s, uxtw\]
-+[^:]+: 848063e0 ldff1h {z0.s}, p0/z, \[sp, z0.s, uxtw\]
-+[^:]+: 848063e0 ldff1h {z0.s}, p0/z, \[sp, z0.s, uxtw\]
-+[^:]+: 84846000 ldff1h {z0.s}, p0/z, \[x0, z4.s, uxtw\]
-+[^:]+: 84846000 ldff1h {z0.s}, p0/z, \[x0, z4.s, uxtw\]
-+[^:]+: 84846000 ldff1h {z0.s}, p0/z, \[x0, z4.s, uxtw\]
-+[^:]+: 849f6000 ldff1h {z0.s}, p0/z, \[x0, z31.s, uxtw\]
-+[^:]+: 849f6000 ldff1h {z0.s}, p0/z, \[x0, z31.s, uxtw\]
-+[^:]+: 849f6000 ldff1h {z0.s}, p0/z, \[x0, z31.s, uxtw\]
-+[^:]+: 84c06000 ldff1h {z0.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84c06000 ldff1h {z0.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84c06000 ldff1h {z0.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84c06000 ldff1h {z0.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84c06001 ldff1h {z1.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84c06001 ldff1h {z1.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84c06001 ldff1h {z1.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84c06001 ldff1h {z1.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84c0601f ldff1h {z31.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84c0601f ldff1h {z31.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84c0601f ldff1h {z31.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84c0601f ldff1h {z31.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84c06800 ldff1h {z0.s}, p2/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84c06800 ldff1h {z0.s}, p2/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84c06800 ldff1h {z0.s}, p2/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84c07c00 ldff1h {z0.s}, p7/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84c07c00 ldff1h {z0.s}, p7/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84c07c00 ldff1h {z0.s}, p7/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84c06060 ldff1h {z0.s}, p0/z, \[x3, z0.s, sxtw\]
-+[^:]+: 84c06060 ldff1h {z0.s}, p0/z, \[x3, z0.s, sxtw\]
-+[^:]+: 84c06060 ldff1h {z0.s}, p0/z, \[x3, z0.s, sxtw\]
-+[^:]+: 84c063e0 ldff1h {z0.s}, p0/z, \[sp, z0.s, sxtw\]
-+[^:]+: 84c063e0 ldff1h {z0.s}, p0/z, \[sp, z0.s, sxtw\]
-+[^:]+: 84c063e0 ldff1h {z0.s}, p0/z, \[sp, z0.s, sxtw\]
-+[^:]+: 84c46000 ldff1h {z0.s}, p0/z, \[x0, z4.s, sxtw\]
-+[^:]+: 84c46000 ldff1h {z0.s}, p0/z, \[x0, z4.s, sxtw\]
-+[^:]+: 84c46000 ldff1h {z0.s}, p0/z, \[x0, z4.s, sxtw\]
-+[^:]+: 84df6000 ldff1h {z0.s}, p0/z, \[x0, z31.s, sxtw\]
-+[^:]+: 84df6000 ldff1h {z0.s}, p0/z, \[x0, z31.s, sxtw\]
-+[^:]+: 84df6000 ldff1h {z0.s}, p0/z, \[x0, z31.s, sxtw\]
-+[^:]+: 84a06000 ldff1h {z0.s}, p0/z, \[x0, z0.s, uxtw #1\]
-+[^:]+: 84a06000 ldff1h {z0.s}, p0/z, \[x0, z0.s, uxtw #1\]
-+[^:]+: 84a06000 ldff1h {z0.s}, p0/z, \[x0, z0.s, uxtw #1\]
-+[^:]+: 84a06001 ldff1h {z1.s}, p0/z, \[x0, z0.s, uxtw #1\]
-+[^:]+: 84a06001 ldff1h {z1.s}, p0/z, \[x0, z0.s, uxtw #1\]
-+[^:]+: 84a06001 ldff1h {z1.s}, p0/z, \[x0, z0.s, uxtw #1\]
-+[^:]+: 84a0601f ldff1h {z31.s}, p0/z, \[x0, z0.s, uxtw #1\]
-+[^:]+: 84a0601f ldff1h {z31.s}, p0/z, \[x0, z0.s, uxtw #1\]
-+[^:]+: 84a0601f ldff1h {z31.s}, p0/z, \[x0, z0.s, uxtw #1\]
-+[^:]+: 84a06800 ldff1h {z0.s}, p2/z, \[x0, z0.s, uxtw #1\]
-+[^:]+: 84a06800 ldff1h {z0.s}, p2/z, \[x0, z0.s, uxtw #1\]
-+[^:]+: 84a07c00 ldff1h {z0.s}, p7/z, \[x0, z0.s, uxtw #1\]
-+[^:]+: 84a07c00 ldff1h {z0.s}, p7/z, \[x0, z0.s, uxtw #1\]
-+[^:]+: 84a06060 ldff1h {z0.s}, p0/z, \[x3, z0.s, uxtw #1\]
-+[^:]+: 84a06060 ldff1h {z0.s}, p0/z, \[x3, z0.s, uxtw #1\]
-+[^:]+: 84a063e0 ldff1h {z0.s}, p0/z, \[sp, z0.s, uxtw #1\]
-+[^:]+: 84a063e0 ldff1h {z0.s}, p0/z, \[sp, z0.s, uxtw #1\]
-+[^:]+: 84a46000 ldff1h {z0.s}, p0/z, \[x0, z4.s, uxtw #1\]
-+[^:]+: 84a46000 ldff1h {z0.s}, p0/z, \[x0, z4.s, uxtw #1\]
-+[^:]+: 84bf6000 ldff1h {z0.s}, p0/z, \[x0, z31.s, uxtw #1\]
-+[^:]+: 84bf6000 ldff1h {z0.s}, p0/z, \[x0, z31.s, uxtw #1\]
-+[^:]+: 84e06000 ldff1h {z0.s}, p0/z, \[x0, z0.s, sxtw #1\]
-+[^:]+: 84e06000 ldff1h {z0.s}, p0/z, \[x0, z0.s, sxtw #1\]
-+[^:]+: 84e06000 ldff1h {z0.s}, p0/z, \[x0, z0.s, sxtw #1\]
-+[^:]+: 84e06001 ldff1h {z1.s}, p0/z, \[x0, z0.s, sxtw #1\]
-+[^:]+: 84e06001 ldff1h {z1.s}, p0/z, \[x0, z0.s, sxtw #1\]
-+[^:]+: 84e06001 ldff1h {z1.s}, p0/z, \[x0, z0.s, sxtw #1\]
-+[^:]+: 84e0601f ldff1h {z31.s}, p0/z, \[x0, z0.s, sxtw #1\]
-+[^:]+: 84e0601f ldff1h {z31.s}, p0/z, \[x0, z0.s, sxtw #1\]
-+[^:]+: 84e0601f ldff1h {z31.s}, p0/z, \[x0, z0.s, sxtw #1\]
-+[^:]+: 84e06800 ldff1h {z0.s}, p2/z, \[x0, z0.s, sxtw #1\]
-+[^:]+: 84e06800 ldff1h {z0.s}, p2/z, \[x0, z0.s, sxtw #1\]
-+[^:]+: 84e07c00 ldff1h {z0.s}, p7/z, \[x0, z0.s, sxtw #1\]
-+[^:]+: 84e07c00 ldff1h {z0.s}, p7/z, \[x0, z0.s, sxtw #1\]
-+[^:]+: 84e06060 ldff1h {z0.s}, p0/z, \[x3, z0.s, sxtw #1\]
-+[^:]+: 84e06060 ldff1h {z0.s}, p0/z, \[x3, z0.s, sxtw #1\]
-+[^:]+: 84e063e0 ldff1h {z0.s}, p0/z, \[sp, z0.s, sxtw #1\]
-+[^:]+: 84e063e0 ldff1h {z0.s}, p0/z, \[sp, z0.s, sxtw #1\]
-+[^:]+: 84e46000 ldff1h {z0.s}, p0/z, \[x0, z4.s, sxtw #1\]
-+[^:]+: 84e46000 ldff1h {z0.s}, p0/z, \[x0, z4.s, sxtw #1\]
-+[^:]+: 84ff6000 ldff1h {z0.s}, p0/z, \[x0, z31.s, sxtw #1\]
-+[^:]+: 84ff6000 ldff1h {z0.s}, p0/z, \[x0, z31.s, sxtw #1\]
-+[^:]+: a4a06000 ldff1h {z0.h}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a4a06000 ldff1h {z0.h}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a4a06000 ldff1h {z0.h}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a4a06001 ldff1h {z1.h}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a4a06001 ldff1h {z1.h}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a4a06001 ldff1h {z1.h}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a4a0601f ldff1h {z31.h}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a4a0601f ldff1h {z31.h}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a4a0601f ldff1h {z31.h}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a4a06800 ldff1h {z0.h}, p2/z, \[x0, x0, lsl #1\]
-+[^:]+: a4a06800 ldff1h {z0.h}, p2/z, \[x0, x0, lsl #1\]
-+[^:]+: a4a07c00 ldff1h {z0.h}, p7/z, \[x0, x0, lsl #1\]
-+[^:]+: a4a07c00 ldff1h {z0.h}, p7/z, \[x0, x0, lsl #1\]
-+[^:]+: a4a06060 ldff1h {z0.h}, p0/z, \[x3, x0, lsl #1\]
-+[^:]+: a4a06060 ldff1h {z0.h}, p0/z, \[x3, x0, lsl #1\]
-+[^:]+: a4a063e0 ldff1h {z0.h}, p0/z, \[sp, x0, lsl #1\]
-+[^:]+: a4a063e0 ldff1h {z0.h}, p0/z, \[sp, x0, lsl #1\]
-+[^:]+: a4a46000 ldff1h {z0.h}, p0/z, \[x0, x4, lsl #1\]
-+[^:]+: a4a46000 ldff1h {z0.h}, p0/z, \[x0, x4, lsl #1\]
-+[^:]+: a4bf6000 ldff1h {z0.h}, p0/z, \[x0, xzr, lsl #1\]
-+[^:]+: a4bf6000 ldff1h {z0.h}, p0/z, \[x0, xzr, lsl #1\]
-+[^:]+: a4c06000 ldff1h {z0.s}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a4c06000 ldff1h {z0.s}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a4c06000 ldff1h {z0.s}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a4c06001 ldff1h {z1.s}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a4c06001 ldff1h {z1.s}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a4c06001 ldff1h {z1.s}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a4c0601f ldff1h {z31.s}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a4c0601f ldff1h {z31.s}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a4c0601f ldff1h {z31.s}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a4c06800 ldff1h {z0.s}, p2/z, \[x0, x0, lsl #1\]
-+[^:]+: a4c06800 ldff1h {z0.s}, p2/z, \[x0, x0, lsl #1\]
-+[^:]+: a4c07c00 ldff1h {z0.s}, p7/z, \[x0, x0, lsl #1\]
-+[^:]+: a4c07c00 ldff1h {z0.s}, p7/z, \[x0, x0, lsl #1\]
-+[^:]+: a4c06060 ldff1h {z0.s}, p0/z, \[x3, x0, lsl #1\]
-+[^:]+: a4c06060 ldff1h {z0.s}, p0/z, \[x3, x0, lsl #1\]
-+[^:]+: a4c063e0 ldff1h {z0.s}, p0/z, \[sp, x0, lsl #1\]
-+[^:]+: a4c063e0 ldff1h {z0.s}, p0/z, \[sp, x0, lsl #1\]
-+[^:]+: a4c46000 ldff1h {z0.s}, p0/z, \[x0, x4, lsl #1\]
-+[^:]+: a4c46000 ldff1h {z0.s}, p0/z, \[x0, x4, lsl #1\]
-+[^:]+: a4df6000 ldff1h {z0.s}, p0/z, \[x0, xzr, lsl #1\]
-+[^:]+: a4df6000 ldff1h {z0.s}, p0/z, \[x0, xzr, lsl #1\]
-+[^:]+: a4e06000 ldff1h {z0.d}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a4e06000 ldff1h {z0.d}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a4e06000 ldff1h {z0.d}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a4e06001 ldff1h {z1.d}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a4e06001 ldff1h {z1.d}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a4e06001 ldff1h {z1.d}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a4e0601f ldff1h {z31.d}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a4e0601f ldff1h {z31.d}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a4e0601f ldff1h {z31.d}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a4e06800 ldff1h {z0.d}, p2/z, \[x0, x0, lsl #1\]
-+[^:]+: a4e06800 ldff1h {z0.d}, p2/z, \[x0, x0, lsl #1\]
-+[^:]+: a4e07c00 ldff1h {z0.d}, p7/z, \[x0, x0, lsl #1\]
-+[^:]+: a4e07c00 ldff1h {z0.d}, p7/z, \[x0, x0, lsl #1\]
-+[^:]+: a4e06060 ldff1h {z0.d}, p0/z, \[x3, x0, lsl #1\]
-+[^:]+: a4e06060 ldff1h {z0.d}, p0/z, \[x3, x0, lsl #1\]
-+[^:]+: a4e063e0 ldff1h {z0.d}, p0/z, \[sp, x0, lsl #1\]
-+[^:]+: a4e063e0 ldff1h {z0.d}, p0/z, \[sp, x0, lsl #1\]
-+[^:]+: a4e46000 ldff1h {z0.d}, p0/z, \[x0, x4, lsl #1\]
-+[^:]+: a4e46000 ldff1h {z0.d}, p0/z, \[x0, x4, lsl #1\]
-+[^:]+: a4ff6000 ldff1h {z0.d}, p0/z, \[x0, xzr, lsl #1\]
-+[^:]+: a4ff6000 ldff1h {z0.d}, p0/z, \[x0, xzr, lsl #1\]
-+[^:]+: c4806000 ldff1h {z0.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4806000 ldff1h {z0.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4806000 ldff1h {z0.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4806000 ldff1h {z0.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4806001 ldff1h {z1.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4806001 ldff1h {z1.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4806001 ldff1h {z1.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4806001 ldff1h {z1.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c480601f ldff1h {z31.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c480601f ldff1h {z31.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c480601f ldff1h {z31.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c480601f ldff1h {z31.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4806800 ldff1h {z0.d}, p2/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4806800 ldff1h {z0.d}, p2/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4806800 ldff1h {z0.d}, p2/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4807c00 ldff1h {z0.d}, p7/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4807c00 ldff1h {z0.d}, p7/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4807c00 ldff1h {z0.d}, p7/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4806060 ldff1h {z0.d}, p0/z, \[x3, z0.d, uxtw\]
-+[^:]+: c4806060 ldff1h {z0.d}, p0/z, \[x3, z0.d, uxtw\]
-+[^:]+: c4806060 ldff1h {z0.d}, p0/z, \[x3, z0.d, uxtw\]
-+[^:]+: c48063e0 ldff1h {z0.d}, p0/z, \[sp, z0.d, uxtw\]
-+[^:]+: c48063e0 ldff1h {z0.d}, p0/z, \[sp, z0.d, uxtw\]
-+[^:]+: c48063e0 ldff1h {z0.d}, p0/z, \[sp, z0.d, uxtw\]
-+[^:]+: c4846000 ldff1h {z0.d}, p0/z, \[x0, z4.d, uxtw\]
-+[^:]+: c4846000 ldff1h {z0.d}, p0/z, \[x0, z4.d, uxtw\]
-+[^:]+: c4846000 ldff1h {z0.d}, p0/z, \[x0, z4.d, uxtw\]
-+[^:]+: c49f6000 ldff1h {z0.d}, p0/z, \[x0, z31.d, uxtw\]
-+[^:]+: c49f6000 ldff1h {z0.d}, p0/z, \[x0, z31.d, uxtw\]
-+[^:]+: c49f6000 ldff1h {z0.d}, p0/z, \[x0, z31.d, uxtw\]
-+[^:]+: c4c06000 ldff1h {z0.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4c06000 ldff1h {z0.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4c06000 ldff1h {z0.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4c06000 ldff1h {z0.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4c06001 ldff1h {z1.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4c06001 ldff1h {z1.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4c06001 ldff1h {z1.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4c06001 ldff1h {z1.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4c0601f ldff1h {z31.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4c0601f ldff1h {z31.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4c0601f ldff1h {z31.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4c0601f ldff1h {z31.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4c06800 ldff1h {z0.d}, p2/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4c06800 ldff1h {z0.d}, p2/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4c06800 ldff1h {z0.d}, p2/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4c07c00 ldff1h {z0.d}, p7/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4c07c00 ldff1h {z0.d}, p7/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4c07c00 ldff1h {z0.d}, p7/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4c06060 ldff1h {z0.d}, p0/z, \[x3, z0.d, sxtw\]
-+[^:]+: c4c06060 ldff1h {z0.d}, p0/z, \[x3, z0.d, sxtw\]
-+[^:]+: c4c06060 ldff1h {z0.d}, p0/z, \[x3, z0.d, sxtw\]
-+[^:]+: c4c063e0 ldff1h {z0.d}, p0/z, \[sp, z0.d, sxtw\]
-+[^:]+: c4c063e0 ldff1h {z0.d}, p0/z, \[sp, z0.d, sxtw\]
-+[^:]+: c4c063e0 ldff1h {z0.d}, p0/z, \[sp, z0.d, sxtw\]
-+[^:]+: c4c46000 ldff1h {z0.d}, p0/z, \[x0, z4.d, sxtw\]
-+[^:]+: c4c46000 ldff1h {z0.d}, p0/z, \[x0, z4.d, sxtw\]
-+[^:]+: c4c46000 ldff1h {z0.d}, p0/z, \[x0, z4.d, sxtw\]
-+[^:]+: c4df6000 ldff1h {z0.d}, p0/z, \[x0, z31.d, sxtw\]
-+[^:]+: c4df6000 ldff1h {z0.d}, p0/z, \[x0, z31.d, sxtw\]
-+[^:]+: c4df6000 ldff1h {z0.d}, p0/z, \[x0, z31.d, sxtw\]
-+[^:]+: c4a06000 ldff1h {z0.d}, p0/z, \[x0, z0.d, uxtw #1\]
-+[^:]+: c4a06000 ldff1h {z0.d}, p0/z, \[x0, z0.d, uxtw #1\]
-+[^:]+: c4a06000 ldff1h {z0.d}, p0/z, \[x0, z0.d, uxtw #1\]
-+[^:]+: c4a06001 ldff1h {z1.d}, p0/z, \[x0, z0.d, uxtw #1\]
-+[^:]+: c4a06001 ldff1h {z1.d}, p0/z, \[x0, z0.d, uxtw #1\]
-+[^:]+: c4a06001 ldff1h {z1.d}, p0/z, \[x0, z0.d, uxtw #1\]
-+[^:]+: c4a0601f ldff1h {z31.d}, p0/z, \[x0, z0.d, uxtw #1\]
-+[^:]+: c4a0601f ldff1h {z31.d}, p0/z, \[x0, z0.d, uxtw #1\]
-+[^:]+: c4a0601f ldff1h {z31.d}, p0/z, \[x0, z0.d, uxtw #1\]
-+[^:]+: c4a06800 ldff1h {z0.d}, p2/z, \[x0, z0.d, uxtw #1\]
-+[^:]+: c4a06800 ldff1h {z0.d}, p2/z, \[x0, z0.d, uxtw #1\]
-+[^:]+: c4a07c00 ldff1h {z0.d}, p7/z, \[x0, z0.d, uxtw #1\]
-+[^:]+: c4a07c00 ldff1h {z0.d}, p7/z, \[x0, z0.d, uxtw #1\]
-+[^:]+: c4a06060 ldff1h {z0.d}, p0/z, \[x3, z0.d, uxtw #1\]
-+[^:]+: c4a06060 ldff1h {z0.d}, p0/z, \[x3, z0.d, uxtw #1\]
-+[^:]+: c4a063e0 ldff1h {z0.d}, p0/z, \[sp, z0.d, uxtw #1\]
-+[^:]+: c4a063e0 ldff1h {z0.d}, p0/z, \[sp, z0.d, uxtw #1\]
-+[^:]+: c4a46000 ldff1h {z0.d}, p0/z, \[x0, z4.d, uxtw #1\]
-+[^:]+: c4a46000 ldff1h {z0.d}, p0/z, \[x0, z4.d, uxtw #1\]
-+[^:]+: c4bf6000 ldff1h {z0.d}, p0/z, \[x0, z31.d, uxtw #1\]
-+[^:]+: c4bf6000 ldff1h {z0.d}, p0/z, \[x0, z31.d, uxtw #1\]
-+[^:]+: c4e06000 ldff1h {z0.d}, p0/z, \[x0, z0.d, sxtw #1\]
-+[^:]+: c4e06000 ldff1h {z0.d}, p0/z, \[x0, z0.d, sxtw #1\]
-+[^:]+: c4e06000 ldff1h {z0.d}, p0/z, \[x0, z0.d, sxtw #1\]
-+[^:]+: c4e06001 ldff1h {z1.d}, p0/z, \[x0, z0.d, sxtw #1\]
-+[^:]+: c4e06001 ldff1h {z1.d}, p0/z, \[x0, z0.d, sxtw #1\]
-+[^:]+: c4e06001 ldff1h {z1.d}, p0/z, \[x0, z0.d, sxtw #1\]
-+[^:]+: c4e0601f ldff1h {z31.d}, p0/z, \[x0, z0.d, sxtw #1\]
-+[^:]+: c4e0601f ldff1h {z31.d}, p0/z, \[x0, z0.d, sxtw #1\]
-+[^:]+: c4e0601f ldff1h {z31.d}, p0/z, \[x0, z0.d, sxtw #1\]
-+[^:]+: c4e06800 ldff1h {z0.d}, p2/z, \[x0, z0.d, sxtw #1\]
-+[^:]+: c4e06800 ldff1h {z0.d}, p2/z, \[x0, z0.d, sxtw #1\]
-+[^:]+: c4e07c00 ldff1h {z0.d}, p7/z, \[x0, z0.d, sxtw #1\]
-+[^:]+: c4e07c00 ldff1h {z0.d}, p7/z, \[x0, z0.d, sxtw #1\]
-+[^:]+: c4e06060 ldff1h {z0.d}, p0/z, \[x3, z0.d, sxtw #1\]
-+[^:]+: c4e06060 ldff1h {z0.d}, p0/z, \[x3, z0.d, sxtw #1\]
-+[^:]+: c4e063e0 ldff1h {z0.d}, p0/z, \[sp, z0.d, sxtw #1\]
-+[^:]+: c4e063e0 ldff1h {z0.d}, p0/z, \[sp, z0.d, sxtw #1\]
-+[^:]+: c4e46000 ldff1h {z0.d}, p0/z, \[x0, z4.d, sxtw #1\]
-+[^:]+: c4e46000 ldff1h {z0.d}, p0/z, \[x0, z4.d, sxtw #1\]
-+[^:]+: c4ff6000 ldff1h {z0.d}, p0/z, \[x0, z31.d, sxtw #1\]
-+[^:]+: c4ff6000 ldff1h {z0.d}, p0/z, \[x0, z31.d, sxtw #1\]
-+[^:]+: c4c0e000 ldff1h {z0.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c4c0e000 ldff1h {z0.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c4c0e000 ldff1h {z0.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c4c0e000 ldff1h {z0.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c4c0e001 ldff1h {z1.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c4c0e001 ldff1h {z1.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c4c0e001 ldff1h {z1.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c4c0e001 ldff1h {z1.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c4c0e01f ldff1h {z31.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c4c0e01f ldff1h {z31.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c4c0e01f ldff1h {z31.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c4c0e01f ldff1h {z31.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c4c0e800 ldff1h {z0.d}, p2/z, \[x0, z0.d\]
-+[^:]+: c4c0e800 ldff1h {z0.d}, p2/z, \[x0, z0.d\]
-+[^:]+: c4c0e800 ldff1h {z0.d}, p2/z, \[x0, z0.d\]
-+[^:]+: c4c0fc00 ldff1h {z0.d}, p7/z, \[x0, z0.d\]
-+[^:]+: c4c0fc00 ldff1h {z0.d}, p7/z, \[x0, z0.d\]
-+[^:]+: c4c0fc00 ldff1h {z0.d}, p7/z, \[x0, z0.d\]
-+[^:]+: c4c0e060 ldff1h {z0.d}, p0/z, \[x3, z0.d\]
-+[^:]+: c4c0e060 ldff1h {z0.d}, p0/z, \[x3, z0.d\]
-+[^:]+: c4c0e060 ldff1h {z0.d}, p0/z, \[x3, z0.d\]
-+[^:]+: c4c0e3e0 ldff1h {z0.d}, p0/z, \[sp, z0.d\]
-+[^:]+: c4c0e3e0 ldff1h {z0.d}, p0/z, \[sp, z0.d\]
-+[^:]+: c4c0e3e0 ldff1h {z0.d}, p0/z, \[sp, z0.d\]
-+[^:]+: c4c4e000 ldff1h {z0.d}, p0/z, \[x0, z4.d\]
-+[^:]+: c4c4e000 ldff1h {z0.d}, p0/z, \[x0, z4.d\]
-+[^:]+: c4c4e000 ldff1h {z0.d}, p0/z, \[x0, z4.d\]
-+[^:]+: c4dfe000 ldff1h {z0.d}, p0/z, \[x0, z31.d\]
-+[^:]+: c4dfe000 ldff1h {z0.d}, p0/z, \[x0, z31.d\]
-+[^:]+: c4dfe000 ldff1h {z0.d}, p0/z, \[x0, z31.d\]
-+[^:]+: c4e0e000 ldff1h {z0.d}, p0/z, \[x0, z0.d, lsl #1\]
-+[^:]+: c4e0e000 ldff1h {z0.d}, p0/z, \[x0, z0.d, lsl #1\]
-+[^:]+: c4e0e000 ldff1h {z0.d}, p0/z, \[x0, z0.d, lsl #1\]
-+[^:]+: c4e0e001 ldff1h {z1.d}, p0/z, \[x0, z0.d, lsl #1\]
-+[^:]+: c4e0e001 ldff1h {z1.d}, p0/z, \[x0, z0.d, lsl #1\]
-+[^:]+: c4e0e001 ldff1h {z1.d}, p0/z, \[x0, z0.d, lsl #1\]
-+[^:]+: c4e0e01f ldff1h {z31.d}, p0/z, \[x0, z0.d, lsl #1\]
-+[^:]+: c4e0e01f ldff1h {z31.d}, p0/z, \[x0, z0.d, lsl #1\]
-+[^:]+: c4e0e01f ldff1h {z31.d}, p0/z, \[x0, z0.d, lsl #1\]
-+[^:]+: c4e0e800 ldff1h {z0.d}, p2/z, \[x0, z0.d, lsl #1\]
-+[^:]+: c4e0e800 ldff1h {z0.d}, p2/z, \[x0, z0.d, lsl #1\]
-+[^:]+: c4e0fc00 ldff1h {z0.d}, p7/z, \[x0, z0.d, lsl #1\]
-+[^:]+: c4e0fc00 ldff1h {z0.d}, p7/z, \[x0, z0.d, lsl #1\]
-+[^:]+: c4e0e060 ldff1h {z0.d}, p0/z, \[x3, z0.d, lsl #1\]
-+[^:]+: c4e0e060 ldff1h {z0.d}, p0/z, \[x3, z0.d, lsl #1\]
-+[^:]+: c4e0e3e0 ldff1h {z0.d}, p0/z, \[sp, z0.d, lsl #1\]
-+[^:]+: c4e0e3e0 ldff1h {z0.d}, p0/z, \[sp, z0.d, lsl #1\]
-+[^:]+: c4e4e000 ldff1h {z0.d}, p0/z, \[x0, z4.d, lsl #1\]
-+[^:]+: c4e4e000 ldff1h {z0.d}, p0/z, \[x0, z4.d, lsl #1\]
-+[^:]+: c4ffe000 ldff1h {z0.d}, p0/z, \[x0, z31.d, lsl #1\]
-+[^:]+: c4ffe000 ldff1h {z0.d}, p0/z, \[x0, z31.d, lsl #1\]
-+[^:]+: 84a0e000 ldff1h {z0.s}, p0/z, \[z0.s\]
-+[^:]+: 84a0e000 ldff1h {z0.s}, p0/z, \[z0.s\]
-+[^:]+: 84a0e000 ldff1h {z0.s}, p0/z, \[z0.s\]
-+[^:]+: 84a0e000 ldff1h {z0.s}, p0/z, \[z0.s\]
-+[^:]+: 84a0e001 ldff1h {z1.s}, p0/z, \[z0.s\]
-+[^:]+: 84a0e001 ldff1h {z1.s}, p0/z, \[z0.s\]
-+[^:]+: 84a0e001 ldff1h {z1.s}, p0/z, \[z0.s\]
-+[^:]+: 84a0e001 ldff1h {z1.s}, p0/z, \[z0.s\]
-+[^:]+: 84a0e01f ldff1h {z31.s}, p0/z, \[z0.s\]
-+[^:]+: 84a0e01f ldff1h {z31.s}, p0/z, \[z0.s\]
-+[^:]+: 84a0e01f ldff1h {z31.s}, p0/z, \[z0.s\]
-+[^:]+: 84a0e01f ldff1h {z31.s}, p0/z, \[z0.s\]
-+[^:]+: 84a0e800 ldff1h {z0.s}, p2/z, \[z0.s\]
-+[^:]+: 84a0e800 ldff1h {z0.s}, p2/z, \[z0.s\]
-+[^:]+: 84a0e800 ldff1h {z0.s}, p2/z, \[z0.s\]
-+[^:]+: 84a0fc00 ldff1h {z0.s}, p7/z, \[z0.s\]
-+[^:]+: 84a0fc00 ldff1h {z0.s}, p7/z, \[z0.s\]
-+[^:]+: 84a0fc00 ldff1h {z0.s}, p7/z, \[z0.s\]
-+[^:]+: 84a0e060 ldff1h {z0.s}, p0/z, \[z3.s\]
-+[^:]+: 84a0e060 ldff1h {z0.s}, p0/z, \[z3.s\]
-+[^:]+: 84a0e060 ldff1h {z0.s}, p0/z, \[z3.s\]
-+[^:]+: 84a0e3e0 ldff1h {z0.s}, p0/z, \[z31.s\]
-+[^:]+: 84a0e3e0 ldff1h {z0.s}, p0/z, \[z31.s\]
-+[^:]+: 84a0e3e0 ldff1h {z0.s}, p0/z, \[z31.s\]
-+[^:]+: 84afe000 ldff1h {z0.s}, p0/z, \[z0.s, #30\]
-+[^:]+: 84afe000 ldff1h {z0.s}, p0/z, \[z0.s, #30\]
-+[^:]+: 84b0e000 ldff1h {z0.s}, p0/z, \[z0.s, #32\]
-+[^:]+: 84b0e000 ldff1h {z0.s}, p0/z, \[z0.s, #32\]
-+[^:]+: 84b1e000 ldff1h {z0.s}, p0/z, \[z0.s, #34\]
-+[^:]+: 84b1e000 ldff1h {z0.s}, p0/z, \[z0.s, #34\]
-+[^:]+: 84bfe000 ldff1h {z0.s}, p0/z, \[z0.s, #62\]
-+[^:]+: 84bfe000 ldff1h {z0.s}, p0/z, \[z0.s, #62\]
-+[^:]+: c4a0e000 ldff1h {z0.d}, p0/z, \[z0.d\]
-+[^:]+: c4a0e000 ldff1h {z0.d}, p0/z, \[z0.d\]
-+[^:]+: c4a0e000 ldff1h {z0.d}, p0/z, \[z0.d\]
-+[^:]+: c4a0e000 ldff1h {z0.d}, p0/z, \[z0.d\]
-+[^:]+: c4a0e001 ldff1h {z1.d}, p0/z, \[z0.d\]
-+[^:]+: c4a0e001 ldff1h {z1.d}, p0/z, \[z0.d\]
-+[^:]+: c4a0e001 ldff1h {z1.d}, p0/z, \[z0.d\]
-+[^:]+: c4a0e001 ldff1h {z1.d}, p0/z, \[z0.d\]
-+[^:]+: c4a0e01f ldff1h {z31.d}, p0/z, \[z0.d\]
-+[^:]+: c4a0e01f ldff1h {z31.d}, p0/z, \[z0.d\]
-+[^:]+: c4a0e01f ldff1h {z31.d}, p0/z, \[z0.d\]
-+[^:]+: c4a0e01f ldff1h {z31.d}, p0/z, \[z0.d\]
-+[^:]+: c4a0e800 ldff1h {z0.d}, p2/z, \[z0.d\]
-+[^:]+: c4a0e800 ldff1h {z0.d}, p2/z, \[z0.d\]
-+[^:]+: c4a0e800 ldff1h {z0.d}, p2/z, \[z0.d\]
-+[^:]+: c4a0fc00 ldff1h {z0.d}, p7/z, \[z0.d\]
-+[^:]+: c4a0fc00 ldff1h {z0.d}, p7/z, \[z0.d\]
-+[^:]+: c4a0fc00 ldff1h {z0.d}, p7/z, \[z0.d\]
-+[^:]+: c4a0e060 ldff1h {z0.d}, p0/z, \[z3.d\]
-+[^:]+: c4a0e060 ldff1h {z0.d}, p0/z, \[z3.d\]
-+[^:]+: c4a0e060 ldff1h {z0.d}, p0/z, \[z3.d\]
-+[^:]+: c4a0e3e0 ldff1h {z0.d}, p0/z, \[z31.d\]
-+[^:]+: c4a0e3e0 ldff1h {z0.d}, p0/z, \[z31.d\]
-+[^:]+: c4a0e3e0 ldff1h {z0.d}, p0/z, \[z31.d\]
-+[^:]+: c4afe000 ldff1h {z0.d}, p0/z, \[z0.d, #30\]
-+[^:]+: c4afe000 ldff1h {z0.d}, p0/z, \[z0.d, #30\]
-+[^:]+: c4b0e000 ldff1h {z0.d}, p0/z, \[z0.d, #32\]
-+[^:]+: c4b0e000 ldff1h {z0.d}, p0/z, \[z0.d, #32\]
-+[^:]+: c4b1e000 ldff1h {z0.d}, p0/z, \[z0.d, #34\]
-+[^:]+: c4b1e000 ldff1h {z0.d}, p0/z, \[z0.d, #34\]
-+[^:]+: c4bfe000 ldff1h {z0.d}, p0/z, \[z0.d, #62\]
-+[^:]+: c4bfe000 ldff1h {z0.d}, p0/z, \[z0.d, #62\]
-+[^:]+: 84002000 ldff1sb {z0.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84002000 ldff1sb {z0.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84002000 ldff1sb {z0.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84002000 ldff1sb {z0.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84002001 ldff1sb {z1.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84002001 ldff1sb {z1.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84002001 ldff1sb {z1.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84002001 ldff1sb {z1.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 8400201f ldff1sb {z31.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 8400201f ldff1sb {z31.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 8400201f ldff1sb {z31.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 8400201f ldff1sb {z31.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84002800 ldff1sb {z0.s}, p2/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84002800 ldff1sb {z0.s}, p2/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84002800 ldff1sb {z0.s}, p2/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84003c00 ldff1sb {z0.s}, p7/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84003c00 ldff1sb {z0.s}, p7/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84003c00 ldff1sb {z0.s}, p7/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84002060 ldff1sb {z0.s}, p0/z, \[x3, z0.s, uxtw\]
-+[^:]+: 84002060 ldff1sb {z0.s}, p0/z, \[x3, z0.s, uxtw\]
-+[^:]+: 84002060 ldff1sb {z0.s}, p0/z, \[x3, z0.s, uxtw\]
-+[^:]+: 840023e0 ldff1sb {z0.s}, p0/z, \[sp, z0.s, uxtw\]
-+[^:]+: 840023e0 ldff1sb {z0.s}, p0/z, \[sp, z0.s, uxtw\]
-+[^:]+: 840023e0 ldff1sb {z0.s}, p0/z, \[sp, z0.s, uxtw\]
-+[^:]+: 84042000 ldff1sb {z0.s}, p0/z, \[x0, z4.s, uxtw\]
-+[^:]+: 84042000 ldff1sb {z0.s}, p0/z, \[x0, z4.s, uxtw\]
-+[^:]+: 84042000 ldff1sb {z0.s}, p0/z, \[x0, z4.s, uxtw\]
-+[^:]+: 841f2000 ldff1sb {z0.s}, p0/z, \[x0, z31.s, uxtw\]
-+[^:]+: 841f2000 ldff1sb {z0.s}, p0/z, \[x0, z31.s, uxtw\]
-+[^:]+: 841f2000 ldff1sb {z0.s}, p0/z, \[x0, z31.s, uxtw\]
-+[^:]+: 84402000 ldff1sb {z0.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84402000 ldff1sb {z0.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84402000 ldff1sb {z0.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84402000 ldff1sb {z0.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84402001 ldff1sb {z1.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84402001 ldff1sb {z1.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84402001 ldff1sb {z1.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84402001 ldff1sb {z1.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 8440201f ldff1sb {z31.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 8440201f ldff1sb {z31.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 8440201f ldff1sb {z31.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 8440201f ldff1sb {z31.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84402800 ldff1sb {z0.s}, p2/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84402800 ldff1sb {z0.s}, p2/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84402800 ldff1sb {z0.s}, p2/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84403c00 ldff1sb {z0.s}, p7/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84403c00 ldff1sb {z0.s}, p7/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84403c00 ldff1sb {z0.s}, p7/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84402060 ldff1sb {z0.s}, p0/z, \[x3, z0.s, sxtw\]
-+[^:]+: 84402060 ldff1sb {z0.s}, p0/z, \[x3, z0.s, sxtw\]
-+[^:]+: 84402060 ldff1sb {z0.s}, p0/z, \[x3, z0.s, sxtw\]
-+[^:]+: 844023e0 ldff1sb {z0.s}, p0/z, \[sp, z0.s, sxtw\]
-+[^:]+: 844023e0 ldff1sb {z0.s}, p0/z, \[sp, z0.s, sxtw\]
-+[^:]+: 844023e0 ldff1sb {z0.s}, p0/z, \[sp, z0.s, sxtw\]
-+[^:]+: 84442000 ldff1sb {z0.s}, p0/z, \[x0, z4.s, sxtw\]
-+[^:]+: 84442000 ldff1sb {z0.s}, p0/z, \[x0, z4.s, sxtw\]
-+[^:]+: 84442000 ldff1sb {z0.s}, p0/z, \[x0, z4.s, sxtw\]
-+[^:]+: 845f2000 ldff1sb {z0.s}, p0/z, \[x0, z31.s, sxtw\]
-+[^:]+: 845f2000 ldff1sb {z0.s}, p0/z, \[x0, z31.s, sxtw\]
-+[^:]+: 845f2000 ldff1sb {z0.s}, p0/z, \[x0, z31.s, sxtw\]
-+[^:]+: a5806000 ldff1sb {z0.d}, p0/z, \[x0, x0\]
-+[^:]+: a5806000 ldff1sb {z0.d}, p0/z, \[x0, x0\]
-+[^:]+: a5806000 ldff1sb {z0.d}, p0/z, \[x0, x0\]
-+[^:]+: a5806000 ldff1sb {z0.d}, p0/z, \[x0, x0\]
-+[^:]+: a5806001 ldff1sb {z1.d}, p0/z, \[x0, x0\]
-+[^:]+: a5806001 ldff1sb {z1.d}, p0/z, \[x0, x0\]
-+[^:]+: a5806001 ldff1sb {z1.d}, p0/z, \[x0, x0\]
-+[^:]+: a5806001 ldff1sb {z1.d}, p0/z, \[x0, x0\]
-+[^:]+: a580601f ldff1sb {z31.d}, p0/z, \[x0, x0\]
-+[^:]+: a580601f ldff1sb {z31.d}, p0/z, \[x0, x0\]
-+[^:]+: a580601f ldff1sb {z31.d}, p0/z, \[x0, x0\]
-+[^:]+: a580601f ldff1sb {z31.d}, p0/z, \[x0, x0\]
-+[^:]+: a5806800 ldff1sb {z0.d}, p2/z, \[x0, x0\]
-+[^:]+: a5806800 ldff1sb {z0.d}, p2/z, \[x0, x0\]
-+[^:]+: a5806800 ldff1sb {z0.d}, p2/z, \[x0, x0\]
-+[^:]+: a5807c00 ldff1sb {z0.d}, p7/z, \[x0, x0\]
-+[^:]+: a5807c00 ldff1sb {z0.d}, p7/z, \[x0, x0\]
-+[^:]+: a5807c00 ldff1sb {z0.d}, p7/z, \[x0, x0\]
-+[^:]+: a5806060 ldff1sb {z0.d}, p0/z, \[x3, x0\]
-+[^:]+: a5806060 ldff1sb {z0.d}, p0/z, \[x3, x0\]
-+[^:]+: a5806060 ldff1sb {z0.d}, p0/z, \[x3, x0\]
-+[^:]+: a58063e0 ldff1sb {z0.d}, p0/z, \[sp, x0\]
-+[^:]+: a58063e0 ldff1sb {z0.d}, p0/z, \[sp, x0\]
-+[^:]+: a58063e0 ldff1sb {z0.d}, p0/z, \[sp, x0\]
-+[^:]+: a5846000 ldff1sb {z0.d}, p0/z, \[x0, x4\]
-+[^:]+: a5846000 ldff1sb {z0.d}, p0/z, \[x0, x4\]
-+[^:]+: a5846000 ldff1sb {z0.d}, p0/z, \[x0, x4\]
-+[^:]+: a59f6000 ldff1sb {z0.d}, p0/z, \[x0, xzr\]
-+[^:]+: a59f6000 ldff1sb {z0.d}, p0/z, \[x0, xzr\]
-+[^:]+: a59f6000 ldff1sb {z0.d}, p0/z, \[x0, xzr\]
-+[^:]+: a5a06000 ldff1sb {z0.s}, p0/z, \[x0, x0\]
-+[^:]+: a5a06000 ldff1sb {z0.s}, p0/z, \[x0, x0\]
-+[^:]+: a5a06000 ldff1sb {z0.s}, p0/z, \[x0, x0\]
-+[^:]+: a5a06000 ldff1sb {z0.s}, p0/z, \[x0, x0\]
-+[^:]+: a5a06001 ldff1sb {z1.s}, p0/z, \[x0, x0\]
-+[^:]+: a5a06001 ldff1sb {z1.s}, p0/z, \[x0, x0\]
-+[^:]+: a5a06001 ldff1sb {z1.s}, p0/z, \[x0, x0\]
-+[^:]+: a5a06001 ldff1sb {z1.s}, p0/z, \[x0, x0\]
-+[^:]+: a5a0601f ldff1sb {z31.s}, p0/z, \[x0, x0\]
-+[^:]+: a5a0601f ldff1sb {z31.s}, p0/z, \[x0, x0\]
-+[^:]+: a5a0601f ldff1sb {z31.s}, p0/z, \[x0, x0\]
-+[^:]+: a5a0601f ldff1sb {z31.s}, p0/z, \[x0, x0\]
-+[^:]+: a5a06800 ldff1sb {z0.s}, p2/z, \[x0, x0\]
-+[^:]+: a5a06800 ldff1sb {z0.s}, p2/z, \[x0, x0\]
-+[^:]+: a5a06800 ldff1sb {z0.s}, p2/z, \[x0, x0\]
-+[^:]+: a5a07c00 ldff1sb {z0.s}, p7/z, \[x0, x0\]
-+[^:]+: a5a07c00 ldff1sb {z0.s}, p7/z, \[x0, x0\]
-+[^:]+: a5a07c00 ldff1sb {z0.s}, p7/z, \[x0, x0\]
-+[^:]+: a5a06060 ldff1sb {z0.s}, p0/z, \[x3, x0\]
-+[^:]+: a5a06060 ldff1sb {z0.s}, p0/z, \[x3, x0\]
-+[^:]+: a5a06060 ldff1sb {z0.s}, p0/z, \[x3, x0\]
-+[^:]+: a5a063e0 ldff1sb {z0.s}, p0/z, \[sp, x0\]
-+[^:]+: a5a063e0 ldff1sb {z0.s}, p0/z, \[sp, x0\]
-+[^:]+: a5a063e0 ldff1sb {z0.s}, p0/z, \[sp, x0\]
-+[^:]+: a5a46000 ldff1sb {z0.s}, p0/z, \[x0, x4\]
-+[^:]+: a5a46000 ldff1sb {z0.s}, p0/z, \[x0, x4\]
-+[^:]+: a5a46000 ldff1sb {z0.s}, p0/z, \[x0, x4\]
-+[^:]+: a5bf6000 ldff1sb {z0.s}, p0/z, \[x0, xzr\]
-+[^:]+: a5bf6000 ldff1sb {z0.s}, p0/z, \[x0, xzr\]
-+[^:]+: a5bf6000 ldff1sb {z0.s}, p0/z, \[x0, xzr\]
-+[^:]+: a5c06000 ldff1sb {z0.h}, p0/z, \[x0, x0\]
-+[^:]+: a5c06000 ldff1sb {z0.h}, p0/z, \[x0, x0\]
-+[^:]+: a5c06000 ldff1sb {z0.h}, p0/z, \[x0, x0\]
-+[^:]+: a5c06000 ldff1sb {z0.h}, p0/z, \[x0, x0\]
-+[^:]+: a5c06001 ldff1sb {z1.h}, p0/z, \[x0, x0\]
-+[^:]+: a5c06001 ldff1sb {z1.h}, p0/z, \[x0, x0\]
-+[^:]+: a5c06001 ldff1sb {z1.h}, p0/z, \[x0, x0\]
-+[^:]+: a5c06001 ldff1sb {z1.h}, p0/z, \[x0, x0\]
-+[^:]+: a5c0601f ldff1sb {z31.h}, p0/z, \[x0, x0\]
-+[^:]+: a5c0601f ldff1sb {z31.h}, p0/z, \[x0, x0\]
-+[^:]+: a5c0601f ldff1sb {z31.h}, p0/z, \[x0, x0\]
-+[^:]+: a5c0601f ldff1sb {z31.h}, p0/z, \[x0, x0\]
-+[^:]+: a5c06800 ldff1sb {z0.h}, p2/z, \[x0, x0\]
-+[^:]+: a5c06800 ldff1sb {z0.h}, p2/z, \[x0, x0\]
-+[^:]+: a5c06800 ldff1sb {z0.h}, p2/z, \[x0, x0\]
-+[^:]+: a5c07c00 ldff1sb {z0.h}, p7/z, \[x0, x0\]
-+[^:]+: a5c07c00 ldff1sb {z0.h}, p7/z, \[x0, x0\]
-+[^:]+: a5c07c00 ldff1sb {z0.h}, p7/z, \[x0, x0\]
-+[^:]+: a5c06060 ldff1sb {z0.h}, p0/z, \[x3, x0\]
-+[^:]+: a5c06060 ldff1sb {z0.h}, p0/z, \[x3, x0\]
-+[^:]+: a5c06060 ldff1sb {z0.h}, p0/z, \[x3, x0\]
-+[^:]+: a5c063e0 ldff1sb {z0.h}, p0/z, \[sp, x0\]
-+[^:]+: a5c063e0 ldff1sb {z0.h}, p0/z, \[sp, x0\]
-+[^:]+: a5c063e0 ldff1sb {z0.h}, p0/z, \[sp, x0\]
-+[^:]+: a5c46000 ldff1sb {z0.h}, p0/z, \[x0, x4\]
-+[^:]+: a5c46000 ldff1sb {z0.h}, p0/z, \[x0, x4\]
-+[^:]+: a5c46000 ldff1sb {z0.h}, p0/z, \[x0, x4\]
-+[^:]+: a5df6000 ldff1sb {z0.h}, p0/z, \[x0, xzr\]
-+[^:]+: a5df6000 ldff1sb {z0.h}, p0/z, \[x0, xzr\]
-+[^:]+: a5df6000 ldff1sb {z0.h}, p0/z, \[x0, xzr\]
-+[^:]+: c4002000 ldff1sb {z0.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4002000 ldff1sb {z0.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4002000 ldff1sb {z0.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4002000 ldff1sb {z0.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4002001 ldff1sb {z1.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4002001 ldff1sb {z1.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4002001 ldff1sb {z1.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4002001 ldff1sb {z1.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c400201f ldff1sb {z31.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c400201f ldff1sb {z31.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c400201f ldff1sb {z31.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c400201f ldff1sb {z31.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4002800 ldff1sb {z0.d}, p2/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4002800 ldff1sb {z0.d}, p2/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4002800 ldff1sb {z0.d}, p2/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4003c00 ldff1sb {z0.d}, p7/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4003c00 ldff1sb {z0.d}, p7/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4003c00 ldff1sb {z0.d}, p7/z, \[x0, z0.d, uxtw\]
-+[^:]+: c4002060 ldff1sb {z0.d}, p0/z, \[x3, z0.d, uxtw\]
-+[^:]+: c4002060 ldff1sb {z0.d}, p0/z, \[x3, z0.d, uxtw\]
-+[^:]+: c4002060 ldff1sb {z0.d}, p0/z, \[x3, z0.d, uxtw\]
-+[^:]+: c40023e0 ldff1sb {z0.d}, p0/z, \[sp, z0.d, uxtw\]
-+[^:]+: c40023e0 ldff1sb {z0.d}, p0/z, \[sp, z0.d, uxtw\]
-+[^:]+: c40023e0 ldff1sb {z0.d}, p0/z, \[sp, z0.d, uxtw\]
-+[^:]+: c4042000 ldff1sb {z0.d}, p0/z, \[x0, z4.d, uxtw\]
-+[^:]+: c4042000 ldff1sb {z0.d}, p0/z, \[x0, z4.d, uxtw\]
-+[^:]+: c4042000 ldff1sb {z0.d}, p0/z, \[x0, z4.d, uxtw\]
-+[^:]+: c41f2000 ldff1sb {z0.d}, p0/z, \[x0, z31.d, uxtw\]
-+[^:]+: c41f2000 ldff1sb {z0.d}, p0/z, \[x0, z31.d, uxtw\]
-+[^:]+: c41f2000 ldff1sb {z0.d}, p0/z, \[x0, z31.d, uxtw\]
-+[^:]+: c4402000 ldff1sb {z0.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4402000 ldff1sb {z0.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4402000 ldff1sb {z0.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4402000 ldff1sb {z0.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4402001 ldff1sb {z1.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4402001 ldff1sb {z1.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4402001 ldff1sb {z1.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4402001 ldff1sb {z1.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c440201f ldff1sb {z31.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c440201f ldff1sb {z31.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c440201f ldff1sb {z31.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c440201f ldff1sb {z31.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4402800 ldff1sb {z0.d}, p2/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4402800 ldff1sb {z0.d}, p2/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4402800 ldff1sb {z0.d}, p2/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4403c00 ldff1sb {z0.d}, p7/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4403c00 ldff1sb {z0.d}, p7/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4403c00 ldff1sb {z0.d}, p7/z, \[x0, z0.d, sxtw\]
-+[^:]+: c4402060 ldff1sb {z0.d}, p0/z, \[x3, z0.d, sxtw\]
-+[^:]+: c4402060 ldff1sb {z0.d}, p0/z, \[x3, z0.d, sxtw\]
-+[^:]+: c4402060 ldff1sb {z0.d}, p0/z, \[x3, z0.d, sxtw\]
-+[^:]+: c44023e0 ldff1sb {z0.d}, p0/z, \[sp, z0.d, sxtw\]
-+[^:]+: c44023e0 ldff1sb {z0.d}, p0/z, \[sp, z0.d, sxtw\]
-+[^:]+: c44023e0 ldff1sb {z0.d}, p0/z, \[sp, z0.d, sxtw\]
-+[^:]+: c4442000 ldff1sb {z0.d}, p0/z, \[x0, z4.d, sxtw\]
-+[^:]+: c4442000 ldff1sb {z0.d}, p0/z, \[x0, z4.d, sxtw\]
-+[^:]+: c4442000 ldff1sb {z0.d}, p0/z, \[x0, z4.d, sxtw\]
-+[^:]+: c45f2000 ldff1sb {z0.d}, p0/z, \[x0, z31.d, sxtw\]
-+[^:]+: c45f2000 ldff1sb {z0.d}, p0/z, \[x0, z31.d, sxtw\]
-+[^:]+: c45f2000 ldff1sb {z0.d}, p0/z, \[x0, z31.d, sxtw\]
-+[^:]+: c440a000 ldff1sb {z0.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c440a000 ldff1sb {z0.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c440a000 ldff1sb {z0.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c440a000 ldff1sb {z0.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c440a001 ldff1sb {z1.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c440a001 ldff1sb {z1.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c440a001 ldff1sb {z1.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c440a001 ldff1sb {z1.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c440a01f ldff1sb {z31.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c440a01f ldff1sb {z31.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c440a01f ldff1sb {z31.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c440a01f ldff1sb {z31.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c440a800 ldff1sb {z0.d}, p2/z, \[x0, z0.d\]
-+[^:]+: c440a800 ldff1sb {z0.d}, p2/z, \[x0, z0.d\]
-+[^:]+: c440a800 ldff1sb {z0.d}, p2/z, \[x0, z0.d\]
-+[^:]+: c440bc00 ldff1sb {z0.d}, p7/z, \[x0, z0.d\]
-+[^:]+: c440bc00 ldff1sb {z0.d}, p7/z, \[x0, z0.d\]
-+[^:]+: c440bc00 ldff1sb {z0.d}, p7/z, \[x0, z0.d\]
-+[^:]+: c440a060 ldff1sb {z0.d}, p0/z, \[x3, z0.d\]
-+[^:]+: c440a060 ldff1sb {z0.d}, p0/z, \[x3, z0.d\]
-+[^:]+: c440a060 ldff1sb {z0.d}, p0/z, \[x3, z0.d\]
-+[^:]+: c440a3e0 ldff1sb {z0.d}, p0/z, \[sp, z0.d\]
-+[^:]+: c440a3e0 ldff1sb {z0.d}, p0/z, \[sp, z0.d\]
-+[^:]+: c440a3e0 ldff1sb {z0.d}, p0/z, \[sp, z0.d\]
-+[^:]+: c444a000 ldff1sb {z0.d}, p0/z, \[x0, z4.d\]
-+[^:]+: c444a000 ldff1sb {z0.d}, p0/z, \[x0, z4.d\]
-+[^:]+: c444a000 ldff1sb {z0.d}, p0/z, \[x0, z4.d\]
-+[^:]+: c45fa000 ldff1sb {z0.d}, p0/z, \[x0, z31.d\]
-+[^:]+: c45fa000 ldff1sb {z0.d}, p0/z, \[x0, z31.d\]
-+[^:]+: c45fa000 ldff1sb {z0.d}, p0/z, \[x0, z31.d\]
-+[^:]+: 8420a000 ldff1sb {z0.s}, p0/z, \[z0.s\]
-+[^:]+: 8420a000 ldff1sb {z0.s}, p0/z, \[z0.s\]
-+[^:]+: 8420a000 ldff1sb {z0.s}, p0/z, \[z0.s\]
-+[^:]+: 8420a000 ldff1sb {z0.s}, p0/z, \[z0.s\]
-+[^:]+: 8420a001 ldff1sb {z1.s}, p0/z, \[z0.s\]
-+[^:]+: 8420a001 ldff1sb {z1.s}, p0/z, \[z0.s\]
-+[^:]+: 8420a001 ldff1sb {z1.s}, p0/z, \[z0.s\]
-+[^:]+: 8420a001 ldff1sb {z1.s}, p0/z, \[z0.s\]
-+[^:]+: 8420a01f ldff1sb {z31.s}, p0/z, \[z0.s\]
-+[^:]+: 8420a01f ldff1sb {z31.s}, p0/z, \[z0.s\]
-+[^:]+: 8420a01f ldff1sb {z31.s}, p0/z, \[z0.s\]
-+[^:]+: 8420a01f ldff1sb {z31.s}, p0/z, \[z0.s\]
-+[^:]+: 8420a800 ldff1sb {z0.s}, p2/z, \[z0.s\]
-+[^:]+: 8420a800 ldff1sb {z0.s}, p2/z, \[z0.s\]
-+[^:]+: 8420a800 ldff1sb {z0.s}, p2/z, \[z0.s\]
-+[^:]+: 8420bc00 ldff1sb {z0.s}, p7/z, \[z0.s\]
-+[^:]+: 8420bc00 ldff1sb {z0.s}, p7/z, \[z0.s\]
-+[^:]+: 8420bc00 ldff1sb {z0.s}, p7/z, \[z0.s\]
-+[^:]+: 8420a060 ldff1sb {z0.s}, p0/z, \[z3.s\]
-+[^:]+: 8420a060 ldff1sb {z0.s}, p0/z, \[z3.s\]
-+[^:]+: 8420a060 ldff1sb {z0.s}, p0/z, \[z3.s\]
-+[^:]+: 8420a3e0 ldff1sb {z0.s}, p0/z, \[z31.s\]
-+[^:]+: 8420a3e0 ldff1sb {z0.s}, p0/z, \[z31.s\]
-+[^:]+: 8420a3e0 ldff1sb {z0.s}, p0/z, \[z31.s\]
-+[^:]+: 842fa000 ldff1sb {z0.s}, p0/z, \[z0.s, #15\]
-+[^:]+: 842fa000 ldff1sb {z0.s}, p0/z, \[z0.s, #15\]
-+[^:]+: 8430a000 ldff1sb {z0.s}, p0/z, \[z0.s, #16\]
-+[^:]+: 8430a000 ldff1sb {z0.s}, p0/z, \[z0.s, #16\]
-+[^:]+: 8431a000 ldff1sb {z0.s}, p0/z, \[z0.s, #17\]
-+[^:]+: 8431a000 ldff1sb {z0.s}, p0/z, \[z0.s, #17\]
-+[^:]+: 843fa000 ldff1sb {z0.s}, p0/z, \[z0.s, #31\]
-+[^:]+: 843fa000 ldff1sb {z0.s}, p0/z, \[z0.s, #31\]
-+[^:]+: c420a000 ldff1sb {z0.d}, p0/z, \[z0.d\]
-+[^:]+: c420a000 ldff1sb {z0.d}, p0/z, \[z0.d\]
-+[^:]+: c420a000 ldff1sb {z0.d}, p0/z, \[z0.d\]
-+[^:]+: c420a000 ldff1sb {z0.d}, p0/z, \[z0.d\]
-+[^:]+: c420a001 ldff1sb {z1.d}, p0/z, \[z0.d\]
-+[^:]+: c420a001 ldff1sb {z1.d}, p0/z, \[z0.d\]
-+[^:]+: c420a001 ldff1sb {z1.d}, p0/z, \[z0.d\]
-+[^:]+: c420a001 ldff1sb {z1.d}, p0/z, \[z0.d\]
-+[^:]+: c420a01f ldff1sb {z31.d}, p0/z, \[z0.d\]
-+[^:]+: c420a01f ldff1sb {z31.d}, p0/z, \[z0.d\]
-+[^:]+: c420a01f ldff1sb {z31.d}, p0/z, \[z0.d\]
-+[^:]+: c420a01f ldff1sb {z31.d}, p0/z, \[z0.d\]
-+[^:]+: c420a800 ldff1sb {z0.d}, p2/z, \[z0.d\]
-+[^:]+: c420a800 ldff1sb {z0.d}, p2/z, \[z0.d\]
-+[^:]+: c420a800 ldff1sb {z0.d}, p2/z, \[z0.d\]
-+[^:]+: c420bc00 ldff1sb {z0.d}, p7/z, \[z0.d\]
-+[^:]+: c420bc00 ldff1sb {z0.d}, p7/z, \[z0.d\]
-+[^:]+: c420bc00 ldff1sb {z0.d}, p7/z, \[z0.d\]
-+[^:]+: c420a060 ldff1sb {z0.d}, p0/z, \[z3.d\]
-+[^:]+: c420a060 ldff1sb {z0.d}, p0/z, \[z3.d\]
-+[^:]+: c420a060 ldff1sb {z0.d}, p0/z, \[z3.d\]
-+[^:]+: c420a3e0 ldff1sb {z0.d}, p0/z, \[z31.d\]
-+[^:]+: c420a3e0 ldff1sb {z0.d}, p0/z, \[z31.d\]
-+[^:]+: c420a3e0 ldff1sb {z0.d}, p0/z, \[z31.d\]
-+[^:]+: c42fa000 ldff1sb {z0.d}, p0/z, \[z0.d, #15\]
-+[^:]+: c42fa000 ldff1sb {z0.d}, p0/z, \[z0.d, #15\]
-+[^:]+: c430a000 ldff1sb {z0.d}, p0/z, \[z0.d, #16\]
-+[^:]+: c430a000 ldff1sb {z0.d}, p0/z, \[z0.d, #16\]
-+[^:]+: c431a000 ldff1sb {z0.d}, p0/z, \[z0.d, #17\]
-+[^:]+: c431a000 ldff1sb {z0.d}, p0/z, \[z0.d, #17\]
-+[^:]+: c43fa000 ldff1sb {z0.d}, p0/z, \[z0.d, #31\]
-+[^:]+: c43fa000 ldff1sb {z0.d}, p0/z, \[z0.d, #31\]
-+[^:]+: 84802000 ldff1sh {z0.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84802000 ldff1sh {z0.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84802000 ldff1sh {z0.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84802000 ldff1sh {z0.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84802001 ldff1sh {z1.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84802001 ldff1sh {z1.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84802001 ldff1sh {z1.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84802001 ldff1sh {z1.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 8480201f ldff1sh {z31.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 8480201f ldff1sh {z31.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 8480201f ldff1sh {z31.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 8480201f ldff1sh {z31.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84802800 ldff1sh {z0.s}, p2/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84802800 ldff1sh {z0.s}, p2/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84802800 ldff1sh {z0.s}, p2/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84803c00 ldff1sh {z0.s}, p7/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84803c00 ldff1sh {z0.s}, p7/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84803c00 ldff1sh {z0.s}, p7/z, \[x0, z0.s, uxtw\]
-+[^:]+: 84802060 ldff1sh {z0.s}, p0/z, \[x3, z0.s, uxtw\]
-+[^:]+: 84802060 ldff1sh {z0.s}, p0/z, \[x3, z0.s, uxtw\]
-+[^:]+: 84802060 ldff1sh {z0.s}, p0/z, \[x3, z0.s, uxtw\]
-+[^:]+: 848023e0 ldff1sh {z0.s}, p0/z, \[sp, z0.s, uxtw\]
-+[^:]+: 848023e0 ldff1sh {z0.s}, p0/z, \[sp, z0.s, uxtw\]
-+[^:]+: 848023e0 ldff1sh {z0.s}, p0/z, \[sp, z0.s, uxtw\]
-+[^:]+: 84842000 ldff1sh {z0.s}, p0/z, \[x0, z4.s, uxtw\]
-+[^:]+: 84842000 ldff1sh {z0.s}, p0/z, \[x0, z4.s, uxtw\]
-+[^:]+: 84842000 ldff1sh {z0.s}, p0/z, \[x0, z4.s, uxtw\]
-+[^:]+: 849f2000 ldff1sh {z0.s}, p0/z, \[x0, z31.s, uxtw\]
-+[^:]+: 849f2000 ldff1sh {z0.s}, p0/z, \[x0, z31.s, uxtw\]
-+[^:]+: 849f2000 ldff1sh {z0.s}, p0/z, \[x0, z31.s, uxtw\]
-+[^:]+: 84c02000 ldff1sh {z0.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84c02000 ldff1sh {z0.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84c02000 ldff1sh {z0.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84c02000 ldff1sh {z0.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84c02001 ldff1sh {z1.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84c02001 ldff1sh {z1.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84c02001 ldff1sh {z1.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84c02001 ldff1sh {z1.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84c0201f ldff1sh {z31.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84c0201f ldff1sh {z31.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84c0201f ldff1sh {z31.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84c0201f ldff1sh {z31.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84c02800 ldff1sh {z0.s}, p2/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84c02800 ldff1sh {z0.s}, p2/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84c02800 ldff1sh {z0.s}, p2/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84c03c00 ldff1sh {z0.s}, p7/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84c03c00 ldff1sh {z0.s}, p7/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84c03c00 ldff1sh {z0.s}, p7/z, \[x0, z0.s, sxtw\]
-+[^:]+: 84c02060 ldff1sh {z0.s}, p0/z, \[x3, z0.s, sxtw\]
-+[^:]+: 84c02060 ldff1sh {z0.s}, p0/z, \[x3, z0.s, sxtw\]
-+[^:]+: 84c02060 ldff1sh {z0.s}, p0/z, \[x3, z0.s, sxtw\]
-+[^:]+: 84c023e0 ldff1sh {z0.s}, p0/z, \[sp, z0.s, sxtw\]
-+[^:]+: 84c023e0 ldff1sh {z0.s}, p0/z, \[sp, z0.s, sxtw\]
-+[^:]+: 84c023e0 ldff1sh {z0.s}, p0/z, \[sp, z0.s, sxtw\]
-+[^:]+: 84c42000 ldff1sh {z0.s}, p0/z, \[x0, z4.s, sxtw\]
-+[^:]+: 84c42000 ldff1sh {z0.s}, p0/z, \[x0, z4.s, sxtw\]
-+[^:]+: 84c42000 ldff1sh {z0.s}, p0/z, \[x0, z4.s, sxtw\]
-+[^:]+: 84df2000 ldff1sh {z0.s}, p0/z, \[x0, z31.s, sxtw\]
-+[^:]+: 84df2000 ldff1sh {z0.s}, p0/z, \[x0, z31.s, sxtw\]
-+[^:]+: 84df2000 ldff1sh {z0.s}, p0/z, \[x0, z31.s, sxtw\]
-+[^:]+: 84a02000 ldff1sh {z0.s}, p0/z, \[x0, z0.s, uxtw #1\]
-+[^:]+: 84a02000 ldff1sh {z0.s}, p0/z, \[x0, z0.s, uxtw #1\]
-+[^:]+: 84a02000 ldff1sh {z0.s}, p0/z, \[x0, z0.s, uxtw #1\]
-+[^:]+: 84a02001 ldff1sh {z1.s}, p0/z, \[x0, z0.s, uxtw #1\]
-+[^:]+: 84a02001 ldff1sh {z1.s}, p0/z, \[x0, z0.s, uxtw #1\]
-+[^:]+: 84a02001 ldff1sh {z1.s}, p0/z, \[x0, z0.s, uxtw #1\]
-+[^:]+: 84a0201f ldff1sh {z31.s}, p0/z, \[x0, z0.s, uxtw #1\]
-+[^:]+: 84a0201f ldff1sh {z31.s}, p0/z, \[x0, z0.s, uxtw #1\]
-+[^:]+: 84a0201f ldff1sh {z31.s}, p0/z, \[x0, z0.s, uxtw #1\]
-+[^:]+: 84a02800 ldff1sh {z0.s}, p2/z, \[x0, z0.s, uxtw #1\]
-+[^:]+: 84a02800 ldff1sh {z0.s}, p2/z, \[x0, z0.s, uxtw #1\]
-+[^:]+: 84a03c00 ldff1sh {z0.s}, p7/z, \[x0, z0.s, uxtw #1\]
-+[^:]+: 84a03c00 ldff1sh {z0.s}, p7/z, \[x0, z0.s, uxtw #1\]
-+[^:]+: 84a02060 ldff1sh {z0.s}, p0/z, \[x3, z0.s, uxtw #1\]
-+[^:]+: 84a02060 ldff1sh {z0.s}, p0/z, \[x3, z0.s, uxtw #1\]
-+[^:]+: 84a023e0 ldff1sh {z0.s}, p0/z, \[sp, z0.s, uxtw #1\]
-+[^:]+: 84a023e0 ldff1sh {z0.s}, p0/z, \[sp, z0.s, uxtw #1\]
-+[^:]+: 84a42000 ldff1sh {z0.s}, p0/z, \[x0, z4.s, uxtw #1\]
-+[^:]+: 84a42000 ldff1sh {z0.s}, p0/z, \[x0, z4.s, uxtw #1\]
-+[^:]+: 84bf2000 ldff1sh {z0.s}, p0/z, \[x0, z31.s, uxtw #1\]
-+[^:]+: 84bf2000 ldff1sh {z0.s}, p0/z, \[x0, z31.s, uxtw #1\]
-+[^:]+: 84e02000 ldff1sh {z0.s}, p0/z, \[x0, z0.s, sxtw #1\]
-+[^:]+: 84e02000 ldff1sh {z0.s}, p0/z, \[x0, z0.s, sxtw #1\]
-+[^:]+: 84e02000 ldff1sh {z0.s}, p0/z, \[x0, z0.s, sxtw #1\]
-+[^:]+: 84e02001 ldff1sh {z1.s}, p0/z, \[x0, z0.s, sxtw #1\]
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-+[^:]+: c4bf2000 ldff1sh {z0.d}, p0/z, \[x0, z31.d, uxtw #1\]
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-+[^:]+: c4e02000 ldff1sh {z0.d}, p0/z, \[x0, z0.d, sxtw #1\]
-+[^:]+: c4e02000 ldff1sh {z0.d}, p0/z, \[x0, z0.d, sxtw #1\]
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-+[^:]+: c4e02001 ldff1sh {z1.d}, p0/z, \[x0, z0.d, sxtw #1\]
-+[^:]+: c4e02001 ldff1sh {z1.d}, p0/z, \[x0, z0.d, sxtw #1\]
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-+[^:]+: c4e0201f ldff1sh {z31.d}, p0/z, \[x0, z0.d, sxtw #1\]
-+[^:]+: c4e0201f ldff1sh {z31.d}, p0/z, \[x0, z0.d, sxtw #1\]
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-+[^:]+: c4e02060 ldff1sh {z0.d}, p0/z, \[x3, z0.d, sxtw #1\]
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-+[^:]+: c4e42000 ldff1sh {z0.d}, p0/z, \[x0, z4.d, sxtw #1\]
-+[^:]+: c4ff2000 ldff1sh {z0.d}, p0/z, \[x0, z31.d, sxtw #1\]
-+[^:]+: c4ff2000 ldff1sh {z0.d}, p0/z, \[x0, z31.d, sxtw #1\]
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-+[^:]+: c4c0a000 ldff1sh {z0.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c4c0a000 ldff1sh {z0.d}, p0/z, \[x0, z0.d\]
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-+[^:]+: c4c0a001 ldff1sh {z1.d}, p0/z, \[x0, z0.d\]
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-+[^:]+: c4c0a01f ldff1sh {z31.d}, p0/z, \[x0, z0.d\]
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-+[^:]+: c4c0a800 ldff1sh {z0.d}, p2/z, \[x0, z0.d\]
-+[^:]+: c4c0a800 ldff1sh {z0.d}, p2/z, \[x0, z0.d\]
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-+[^:]+: c4c0bc00 ldff1sh {z0.d}, p7/z, \[x0, z0.d\]
-+[^:]+: c4c0bc00 ldff1sh {z0.d}, p7/z, \[x0, z0.d\]
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-+[^:]+: c4c4a000 ldff1sh {z0.d}, p0/z, \[x0, z4.d\]
-+[^:]+: c4c4a000 ldff1sh {z0.d}, p0/z, \[x0, z4.d\]
-+[^:]+: c4dfa000 ldff1sh {z0.d}, p0/z, \[x0, z31.d\]
-+[^:]+: c4dfa000 ldff1sh {z0.d}, p0/z, \[x0, z31.d\]
-+[^:]+: c4dfa000 ldff1sh {z0.d}, p0/z, \[x0, z31.d\]
-+[^:]+: c4e0a000 ldff1sh {z0.d}, p0/z, \[x0, z0.d, lsl #1\]
-+[^:]+: c4e0a000 ldff1sh {z0.d}, p0/z, \[x0, z0.d, lsl #1\]
-+[^:]+: c4e0a000 ldff1sh {z0.d}, p0/z, \[x0, z0.d, lsl #1\]
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-+[^:]+: c4e0a001 ldff1sh {z1.d}, p0/z, \[x0, z0.d, lsl #1\]
-+[^:]+: c4e0a001 ldff1sh {z1.d}, p0/z, \[x0, z0.d, lsl #1\]
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-+[^:]+: c4e0a01f ldff1sh {z31.d}, p0/z, \[x0, z0.d, lsl #1\]
-+[^:]+: c4e0a01f ldff1sh {z31.d}, p0/z, \[x0, z0.d, lsl #1\]
-+[^:]+: c4e0a800 ldff1sh {z0.d}, p2/z, \[x0, z0.d, lsl #1\]
-+[^:]+: c4e0a800 ldff1sh {z0.d}, p2/z, \[x0, z0.d, lsl #1\]
-+[^:]+: c4e0bc00 ldff1sh {z0.d}, p7/z, \[x0, z0.d, lsl #1\]
-+[^:]+: c4e0bc00 ldff1sh {z0.d}, p7/z, \[x0, z0.d, lsl #1\]
-+[^:]+: c4e0a060 ldff1sh {z0.d}, p0/z, \[x3, z0.d, lsl #1\]
-+[^:]+: c4e0a060 ldff1sh {z0.d}, p0/z, \[x3, z0.d, lsl #1\]
-+[^:]+: c4e0a3e0 ldff1sh {z0.d}, p0/z, \[sp, z0.d, lsl #1\]
-+[^:]+: c4e0a3e0 ldff1sh {z0.d}, p0/z, \[sp, z0.d, lsl #1\]
-+[^:]+: c4e4a000 ldff1sh {z0.d}, p0/z, \[x0, z4.d, lsl #1\]
-+[^:]+: c4e4a000 ldff1sh {z0.d}, p0/z, \[x0, z4.d, lsl #1\]
-+[^:]+: c4ffa000 ldff1sh {z0.d}, p0/z, \[x0, z31.d, lsl #1\]
-+[^:]+: c4ffa000 ldff1sh {z0.d}, p0/z, \[x0, z31.d, lsl #1\]
-+[^:]+: 84a0a000 ldff1sh {z0.s}, p0/z, \[z0.s\]
-+[^:]+: 84a0a000 ldff1sh {z0.s}, p0/z, \[z0.s\]
-+[^:]+: 84a0a000 ldff1sh {z0.s}, p0/z, \[z0.s\]
-+[^:]+: 84a0a000 ldff1sh {z0.s}, p0/z, \[z0.s\]
-+[^:]+: 84a0a001 ldff1sh {z1.s}, p0/z, \[z0.s\]
-+[^:]+: 84a0a001 ldff1sh {z1.s}, p0/z, \[z0.s\]
-+[^:]+: 84a0a001 ldff1sh {z1.s}, p0/z, \[z0.s\]
-+[^:]+: 84a0a001 ldff1sh {z1.s}, p0/z, \[z0.s\]
-+[^:]+: 84a0a01f ldff1sh {z31.s}, p0/z, \[z0.s\]
-+[^:]+: 84a0a01f ldff1sh {z31.s}, p0/z, \[z0.s\]
-+[^:]+: 84a0a01f ldff1sh {z31.s}, p0/z, \[z0.s\]
-+[^:]+: 84a0a01f ldff1sh {z31.s}, p0/z, \[z0.s\]
-+[^:]+: 84a0a800 ldff1sh {z0.s}, p2/z, \[z0.s\]
-+[^:]+: 84a0a800 ldff1sh {z0.s}, p2/z, \[z0.s\]
-+[^:]+: 84a0a800 ldff1sh {z0.s}, p2/z, \[z0.s\]
-+[^:]+: 84a0bc00 ldff1sh {z0.s}, p7/z, \[z0.s\]
-+[^:]+: 84a0bc00 ldff1sh {z0.s}, p7/z, \[z0.s\]
-+[^:]+: 84a0bc00 ldff1sh {z0.s}, p7/z, \[z0.s\]
-+[^:]+: 84a0a060 ldff1sh {z0.s}, p0/z, \[z3.s\]
-+[^:]+: 84a0a060 ldff1sh {z0.s}, p0/z, \[z3.s\]
-+[^:]+: 84a0a060 ldff1sh {z0.s}, p0/z, \[z3.s\]
-+[^:]+: 84a0a3e0 ldff1sh {z0.s}, p0/z, \[z31.s\]
-+[^:]+: 84a0a3e0 ldff1sh {z0.s}, p0/z, \[z31.s\]
-+[^:]+: 84a0a3e0 ldff1sh {z0.s}, p0/z, \[z31.s\]
-+[^:]+: 84afa000 ldff1sh {z0.s}, p0/z, \[z0.s, #30\]
-+[^:]+: 84afa000 ldff1sh {z0.s}, p0/z, \[z0.s, #30\]
-+[^:]+: 84b0a000 ldff1sh {z0.s}, p0/z, \[z0.s, #32\]
-+[^:]+: 84b0a000 ldff1sh {z0.s}, p0/z, \[z0.s, #32\]
-+[^:]+: 84b1a000 ldff1sh {z0.s}, p0/z, \[z0.s, #34\]
-+[^:]+: 84b1a000 ldff1sh {z0.s}, p0/z, \[z0.s, #34\]
-+[^:]+: 84bfa000 ldff1sh {z0.s}, p0/z, \[z0.s, #62\]
-+[^:]+: 84bfa000 ldff1sh {z0.s}, p0/z, \[z0.s, #62\]
-+[^:]+: c4a0a000 ldff1sh {z0.d}, p0/z, \[z0.d\]
-+[^:]+: c4a0a000 ldff1sh {z0.d}, p0/z, \[z0.d\]
-+[^:]+: c4a0a000 ldff1sh {z0.d}, p0/z, \[z0.d\]
-+[^:]+: c4a0a000 ldff1sh {z0.d}, p0/z, \[z0.d\]
-+[^:]+: c4a0a001 ldff1sh {z1.d}, p0/z, \[z0.d\]
-+[^:]+: c4a0a001 ldff1sh {z1.d}, p0/z, \[z0.d\]
-+[^:]+: c4a0a001 ldff1sh {z1.d}, p0/z, \[z0.d\]
-+[^:]+: c4a0a001 ldff1sh {z1.d}, p0/z, \[z0.d\]
-+[^:]+: c4a0a01f ldff1sh {z31.d}, p0/z, \[z0.d\]
-+[^:]+: c4a0a01f ldff1sh {z31.d}, p0/z, \[z0.d\]
-+[^:]+: c4a0a01f ldff1sh {z31.d}, p0/z, \[z0.d\]
-+[^:]+: c4a0a01f ldff1sh {z31.d}, p0/z, \[z0.d\]
-+[^:]+: c4a0a800 ldff1sh {z0.d}, p2/z, \[z0.d\]
-+[^:]+: c4a0a800 ldff1sh {z0.d}, p2/z, \[z0.d\]
-+[^:]+: c4a0a800 ldff1sh {z0.d}, p2/z, \[z0.d\]
-+[^:]+: c4a0bc00 ldff1sh {z0.d}, p7/z, \[z0.d\]
-+[^:]+: c4a0bc00 ldff1sh {z0.d}, p7/z, \[z0.d\]
-+[^:]+: c4a0bc00 ldff1sh {z0.d}, p7/z, \[z0.d\]
-+[^:]+: c4a0a060 ldff1sh {z0.d}, p0/z, \[z3.d\]
-+[^:]+: c4a0a060 ldff1sh {z0.d}, p0/z, \[z3.d\]
-+[^:]+: c4a0a060 ldff1sh {z0.d}, p0/z, \[z3.d\]
-+[^:]+: c4a0a3e0 ldff1sh {z0.d}, p0/z, \[z31.d\]
-+[^:]+: c4a0a3e0 ldff1sh {z0.d}, p0/z, \[z31.d\]
-+[^:]+: c4a0a3e0 ldff1sh {z0.d}, p0/z, \[z31.d\]
-+[^:]+: c4afa000 ldff1sh {z0.d}, p0/z, \[z0.d, #30\]
-+[^:]+: c4afa000 ldff1sh {z0.d}, p0/z, \[z0.d, #30\]
-+[^:]+: c4b0a000 ldff1sh {z0.d}, p0/z, \[z0.d, #32\]
-+[^:]+: c4b0a000 ldff1sh {z0.d}, p0/z, \[z0.d, #32\]
-+[^:]+: c4b1a000 ldff1sh {z0.d}, p0/z, \[z0.d, #34\]
-+[^:]+: c4b1a000 ldff1sh {z0.d}, p0/z, \[z0.d, #34\]
-+[^:]+: c4bfa000 ldff1sh {z0.d}, p0/z, \[z0.d, #62\]
-+[^:]+: c4bfa000 ldff1sh {z0.d}, p0/z, \[z0.d, #62\]
-+[^:]+: a4806000 ldff1sw {z0.d}, p0/z, \[x0, x0, lsl #2\]
-+[^:]+: a4806000 ldff1sw {z0.d}, p0/z, \[x0, x0, lsl #2\]
-+[^:]+: a4806000 ldff1sw {z0.d}, p0/z, \[x0, x0, lsl #2\]
-+[^:]+: a4806001 ldff1sw {z1.d}, p0/z, \[x0, x0, lsl #2\]
-+[^:]+: a4806001 ldff1sw {z1.d}, p0/z, \[x0, x0, lsl #2\]
-+[^:]+: a4806001 ldff1sw {z1.d}, p0/z, \[x0, x0, lsl #2\]
-+[^:]+: a480601f ldff1sw {z31.d}, p0/z, \[x0, x0, lsl #2\]
-+[^:]+: a480601f ldff1sw {z31.d}, p0/z, \[x0, x0, lsl #2\]
-+[^:]+: a480601f ldff1sw {z31.d}, p0/z, \[x0, x0, lsl #2\]
-+[^:]+: a4806800 ldff1sw {z0.d}, p2/z, \[x0, x0, lsl #2\]
-+[^:]+: a4806800 ldff1sw {z0.d}, p2/z, \[x0, x0, lsl #2\]
-+[^:]+: a4807c00 ldff1sw {z0.d}, p7/z, \[x0, x0, lsl #2\]
-+[^:]+: a4807c00 ldff1sw {z0.d}, p7/z, \[x0, x0, lsl #2\]
-+[^:]+: a4806060 ldff1sw {z0.d}, p0/z, \[x3, x0, lsl #2\]
-+[^:]+: a4806060 ldff1sw {z0.d}, p0/z, \[x3, x0, lsl #2\]
-+[^:]+: a48063e0 ldff1sw {z0.d}, p0/z, \[sp, x0, lsl #2\]
-+[^:]+: a48063e0 ldff1sw {z0.d}, p0/z, \[sp, x0, lsl #2\]
-+[^:]+: a4846000 ldff1sw {z0.d}, p0/z, \[x0, x4, lsl #2\]
-+[^:]+: a4846000 ldff1sw {z0.d}, p0/z, \[x0, x4, lsl #2\]
-+[^:]+: a49f6000 ldff1sw {z0.d}, p0/z, \[x0, xzr, lsl #2\]
-+[^:]+: a49f6000 ldff1sw {z0.d}, p0/z, \[x0, xzr, lsl #2\]
-+[^:]+: c5002000 ldff1sw {z0.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c5002000 ldff1sw {z0.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c5002000 ldff1sw {z0.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c5002000 ldff1sw {z0.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c5002001 ldff1sw {z1.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c5002001 ldff1sw {z1.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c5002001 ldff1sw {z1.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c5002001 ldff1sw {z1.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c500201f ldff1sw {z31.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c500201f ldff1sw {z31.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c500201f ldff1sw {z31.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c500201f ldff1sw {z31.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c5002800 ldff1sw {z0.d}, p2/z, \[x0, z0.d, uxtw\]
-+[^:]+: c5002800 ldff1sw {z0.d}, p2/z, \[x0, z0.d, uxtw\]
-+[^:]+: c5002800 ldff1sw {z0.d}, p2/z, \[x0, z0.d, uxtw\]
-+[^:]+: c5003c00 ldff1sw {z0.d}, p7/z, \[x0, z0.d, uxtw\]
-+[^:]+: c5003c00 ldff1sw {z0.d}, p7/z, \[x0, z0.d, uxtw\]
-+[^:]+: c5003c00 ldff1sw {z0.d}, p7/z, \[x0, z0.d, uxtw\]
-+[^:]+: c5002060 ldff1sw {z0.d}, p0/z, \[x3, z0.d, uxtw\]
-+[^:]+: c5002060 ldff1sw {z0.d}, p0/z, \[x3, z0.d, uxtw\]
-+[^:]+: c5002060 ldff1sw {z0.d}, p0/z, \[x3, z0.d, uxtw\]
-+[^:]+: c50023e0 ldff1sw {z0.d}, p0/z, \[sp, z0.d, uxtw\]
-+[^:]+: c50023e0 ldff1sw {z0.d}, p0/z, \[sp, z0.d, uxtw\]
-+[^:]+: c50023e0 ldff1sw {z0.d}, p0/z, \[sp, z0.d, uxtw\]
-+[^:]+: c5042000 ldff1sw {z0.d}, p0/z, \[x0, z4.d, uxtw\]
-+[^:]+: c5042000 ldff1sw {z0.d}, p0/z, \[x0, z4.d, uxtw\]
-+[^:]+: c5042000 ldff1sw {z0.d}, p0/z, \[x0, z4.d, uxtw\]
-+[^:]+: c51f2000 ldff1sw {z0.d}, p0/z, \[x0, z31.d, uxtw\]
-+[^:]+: c51f2000 ldff1sw {z0.d}, p0/z, \[x0, z31.d, uxtw\]
-+[^:]+: c51f2000 ldff1sw {z0.d}, p0/z, \[x0, z31.d, uxtw\]
-+[^:]+: c5402000 ldff1sw {z0.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5402000 ldff1sw {z0.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5402000 ldff1sw {z0.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5402000 ldff1sw {z0.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5402001 ldff1sw {z1.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5402001 ldff1sw {z1.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5402001 ldff1sw {z1.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5402001 ldff1sw {z1.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c540201f ldff1sw {z31.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c540201f ldff1sw {z31.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c540201f ldff1sw {z31.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c540201f ldff1sw {z31.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5402800 ldff1sw {z0.d}, p2/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5402800 ldff1sw {z0.d}, p2/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5402800 ldff1sw {z0.d}, p2/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5403c00 ldff1sw {z0.d}, p7/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5403c00 ldff1sw {z0.d}, p7/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5403c00 ldff1sw {z0.d}, p7/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5402060 ldff1sw {z0.d}, p0/z, \[x3, z0.d, sxtw\]
-+[^:]+: c5402060 ldff1sw {z0.d}, p0/z, \[x3, z0.d, sxtw\]
-+[^:]+: c5402060 ldff1sw {z0.d}, p0/z, \[x3, z0.d, sxtw\]
-+[^:]+: c54023e0 ldff1sw {z0.d}, p0/z, \[sp, z0.d, sxtw\]
-+[^:]+: c54023e0 ldff1sw {z0.d}, p0/z, \[sp, z0.d, sxtw\]
-+[^:]+: c54023e0 ldff1sw {z0.d}, p0/z, \[sp, z0.d, sxtw\]
-+[^:]+: c5442000 ldff1sw {z0.d}, p0/z, \[x0, z4.d, sxtw\]
-+[^:]+: c5442000 ldff1sw {z0.d}, p0/z, \[x0, z4.d, sxtw\]
-+[^:]+: c5442000 ldff1sw {z0.d}, p0/z, \[x0, z4.d, sxtw\]
-+[^:]+: c55f2000 ldff1sw {z0.d}, p0/z, \[x0, z31.d, sxtw\]
-+[^:]+: c55f2000 ldff1sw {z0.d}, p0/z, \[x0, z31.d, sxtw\]
-+[^:]+: c55f2000 ldff1sw {z0.d}, p0/z, \[x0, z31.d, sxtw\]
-+[^:]+: c5202000 ldff1sw {z0.d}, p0/z, \[x0, z0.d, uxtw #2\]
-+[^:]+: c5202000 ldff1sw {z0.d}, p0/z, \[x0, z0.d, uxtw #2\]
-+[^:]+: c5202000 ldff1sw {z0.d}, p0/z, \[x0, z0.d, uxtw #2\]
-+[^:]+: c5202001 ldff1sw {z1.d}, p0/z, \[x0, z0.d, uxtw #2\]
-+[^:]+: c5202001 ldff1sw {z1.d}, p0/z, \[x0, z0.d, uxtw #2\]
-+[^:]+: c5202001 ldff1sw {z1.d}, p0/z, \[x0, z0.d, uxtw #2\]
-+[^:]+: c520201f ldff1sw {z31.d}, p0/z, \[x0, z0.d, uxtw #2\]
-+[^:]+: c520201f ldff1sw {z31.d}, p0/z, \[x0, z0.d, uxtw #2\]
-+[^:]+: c520201f ldff1sw {z31.d}, p0/z, \[x0, z0.d, uxtw #2\]
-+[^:]+: c5202800 ldff1sw {z0.d}, p2/z, \[x0, z0.d, uxtw #2\]
-+[^:]+: c5202800 ldff1sw {z0.d}, p2/z, \[x0, z0.d, uxtw #2\]
-+[^:]+: c5203c00 ldff1sw {z0.d}, p7/z, \[x0, z0.d, uxtw #2\]
-+[^:]+: c5203c00 ldff1sw {z0.d}, p7/z, \[x0, z0.d, uxtw #2\]
-+[^:]+: c5202060 ldff1sw {z0.d}, p0/z, \[x3, z0.d, uxtw #2\]
-+[^:]+: c5202060 ldff1sw {z0.d}, p0/z, \[x3, z0.d, uxtw #2\]
-+[^:]+: c52023e0 ldff1sw {z0.d}, p0/z, \[sp, z0.d, uxtw #2\]
-+[^:]+: c52023e0 ldff1sw {z0.d}, p0/z, \[sp, z0.d, uxtw #2\]
-+[^:]+: c5242000 ldff1sw {z0.d}, p0/z, \[x0, z4.d, uxtw #2\]
-+[^:]+: c5242000 ldff1sw {z0.d}, p0/z, \[x0, z4.d, uxtw #2\]
-+[^:]+: c53f2000 ldff1sw {z0.d}, p0/z, \[x0, z31.d, uxtw #2\]
-+[^:]+: c53f2000 ldff1sw {z0.d}, p0/z, \[x0, z31.d, uxtw #2\]
-+[^:]+: c5602000 ldff1sw {z0.d}, p0/z, \[x0, z0.d, sxtw #2\]
-+[^:]+: c5602000 ldff1sw {z0.d}, p0/z, \[x0, z0.d, sxtw #2\]
-+[^:]+: c5602000 ldff1sw {z0.d}, p0/z, \[x0, z0.d, sxtw #2\]
-+[^:]+: c5602001 ldff1sw {z1.d}, p0/z, \[x0, z0.d, sxtw #2\]
-+[^:]+: c5602001 ldff1sw {z1.d}, p0/z, \[x0, z0.d, sxtw #2\]
-+[^:]+: c5602001 ldff1sw {z1.d}, p0/z, \[x0, z0.d, sxtw #2\]
-+[^:]+: c560201f ldff1sw {z31.d}, p0/z, \[x0, z0.d, sxtw #2\]
-+[^:]+: c560201f ldff1sw {z31.d}, p0/z, \[x0, z0.d, sxtw #2\]
-+[^:]+: c560201f ldff1sw {z31.d}, p0/z, \[x0, z0.d, sxtw #2\]
-+[^:]+: c5602800 ldff1sw {z0.d}, p2/z, \[x0, z0.d, sxtw #2\]
-+[^:]+: c5602800 ldff1sw {z0.d}, p2/z, \[x0, z0.d, sxtw #2\]
-+[^:]+: c5603c00 ldff1sw {z0.d}, p7/z, \[x0, z0.d, sxtw #2\]
-+[^:]+: c5603c00 ldff1sw {z0.d}, p7/z, \[x0, z0.d, sxtw #2\]
-+[^:]+: c5602060 ldff1sw {z0.d}, p0/z, \[x3, z0.d, sxtw #2\]
-+[^:]+: c5602060 ldff1sw {z0.d}, p0/z, \[x3, z0.d, sxtw #2\]
-+[^:]+: c56023e0 ldff1sw {z0.d}, p0/z, \[sp, z0.d, sxtw #2\]
-+[^:]+: c56023e0 ldff1sw {z0.d}, p0/z, \[sp, z0.d, sxtw #2\]
-+[^:]+: c5642000 ldff1sw {z0.d}, p0/z, \[x0, z4.d, sxtw #2\]
-+[^:]+: c5642000 ldff1sw {z0.d}, p0/z, \[x0, z4.d, sxtw #2\]
-+[^:]+: c57f2000 ldff1sw {z0.d}, p0/z, \[x0, z31.d, sxtw #2\]
-+[^:]+: c57f2000 ldff1sw {z0.d}, p0/z, \[x0, z31.d, sxtw #2\]
-+[^:]+: c540a000 ldff1sw {z0.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c540a000 ldff1sw {z0.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c540a000 ldff1sw {z0.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c540a000 ldff1sw {z0.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c540a001 ldff1sw {z1.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c540a001 ldff1sw {z1.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c540a001 ldff1sw {z1.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c540a001 ldff1sw {z1.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c540a01f ldff1sw {z31.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c540a01f ldff1sw {z31.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c540a01f ldff1sw {z31.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c540a01f ldff1sw {z31.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c540a800 ldff1sw {z0.d}, p2/z, \[x0, z0.d\]
-+[^:]+: c540a800 ldff1sw {z0.d}, p2/z, \[x0, z0.d\]
-+[^:]+: c540a800 ldff1sw {z0.d}, p2/z, \[x0, z0.d\]
-+[^:]+: c540bc00 ldff1sw {z0.d}, p7/z, \[x0, z0.d\]
-+[^:]+: c540bc00 ldff1sw {z0.d}, p7/z, \[x0, z0.d\]
-+[^:]+: c540bc00 ldff1sw {z0.d}, p7/z, \[x0, z0.d\]
-+[^:]+: c540a060 ldff1sw {z0.d}, p0/z, \[x3, z0.d\]
-+[^:]+: c540a060 ldff1sw {z0.d}, p0/z, \[x3, z0.d\]
-+[^:]+: c540a060 ldff1sw {z0.d}, p0/z, \[x3, z0.d\]
-+[^:]+: c540a3e0 ldff1sw {z0.d}, p0/z, \[sp, z0.d\]
-+[^:]+: c540a3e0 ldff1sw {z0.d}, p0/z, \[sp, z0.d\]
-+[^:]+: c540a3e0 ldff1sw {z0.d}, p0/z, \[sp, z0.d\]
-+[^:]+: c544a000 ldff1sw {z0.d}, p0/z, \[x0, z4.d\]
-+[^:]+: c544a000 ldff1sw {z0.d}, p0/z, \[x0, z4.d\]
-+[^:]+: c544a000 ldff1sw {z0.d}, p0/z, \[x0, z4.d\]
-+[^:]+: c55fa000 ldff1sw {z0.d}, p0/z, \[x0, z31.d\]
-+[^:]+: c55fa000 ldff1sw {z0.d}, p0/z, \[x0, z31.d\]
-+[^:]+: c55fa000 ldff1sw {z0.d}, p0/z, \[x0, z31.d\]
-+[^:]+: c560a000 ldff1sw {z0.d}, p0/z, \[x0, z0.d, lsl #2\]
-+[^:]+: c560a000 ldff1sw {z0.d}, p0/z, \[x0, z0.d, lsl #2\]
-+[^:]+: c560a000 ldff1sw {z0.d}, p0/z, \[x0, z0.d, lsl #2\]
-+[^:]+: c560a001 ldff1sw {z1.d}, p0/z, \[x0, z0.d, lsl #2\]
-+[^:]+: c560a001 ldff1sw {z1.d}, p0/z, \[x0, z0.d, lsl #2\]
-+[^:]+: c560a001 ldff1sw {z1.d}, p0/z, \[x0, z0.d, lsl #2\]
-+[^:]+: c560a01f ldff1sw {z31.d}, p0/z, \[x0, z0.d, lsl #2\]
-+[^:]+: c560a01f ldff1sw {z31.d}, p0/z, \[x0, z0.d, lsl #2\]
-+[^:]+: c560a01f ldff1sw {z31.d}, p0/z, \[x0, z0.d, lsl #2\]
-+[^:]+: c560a800 ldff1sw {z0.d}, p2/z, \[x0, z0.d, lsl #2\]
-+[^:]+: c560a800 ldff1sw {z0.d}, p2/z, \[x0, z0.d, lsl #2\]
-+[^:]+: c560bc00 ldff1sw {z0.d}, p7/z, \[x0, z0.d, lsl #2\]
-+[^:]+: c560bc00 ldff1sw {z0.d}, p7/z, \[x0, z0.d, lsl #2\]
-+[^:]+: c560a060 ldff1sw {z0.d}, p0/z, \[x3, z0.d, lsl #2\]
-+[^:]+: c560a060 ldff1sw {z0.d}, p0/z, \[x3, z0.d, lsl #2\]
-+[^:]+: c560a3e0 ldff1sw {z0.d}, p0/z, \[sp, z0.d, lsl #2\]
-+[^:]+: c560a3e0 ldff1sw {z0.d}, p0/z, \[sp, z0.d, lsl #2\]
-+[^:]+: c564a000 ldff1sw {z0.d}, p0/z, \[x0, z4.d, lsl #2\]
-+[^:]+: c564a000 ldff1sw {z0.d}, p0/z, \[x0, z4.d, lsl #2\]
-+[^:]+: c57fa000 ldff1sw {z0.d}, p0/z, \[x0, z31.d, lsl #2\]
-+[^:]+: c57fa000 ldff1sw {z0.d}, p0/z, \[x0, z31.d, lsl #2\]
-+[^:]+: c520a000 ldff1sw {z0.d}, p0/z, \[z0.d\]
-+[^:]+: c520a000 ldff1sw {z0.d}, p0/z, \[z0.d\]
-+[^:]+: c520a000 ldff1sw {z0.d}, p0/z, \[z0.d\]
-+[^:]+: c520a000 ldff1sw {z0.d}, p0/z, \[z0.d\]
-+[^:]+: c520a001 ldff1sw {z1.d}, p0/z, \[z0.d\]
-+[^:]+: c520a001 ldff1sw {z1.d}, p0/z, \[z0.d\]
-+[^:]+: c520a001 ldff1sw {z1.d}, p0/z, \[z0.d\]
-+[^:]+: c520a001 ldff1sw {z1.d}, p0/z, \[z0.d\]
-+[^:]+: c520a01f ldff1sw {z31.d}, p0/z, \[z0.d\]
-+[^:]+: c520a01f ldff1sw {z31.d}, p0/z, \[z0.d\]
-+[^:]+: c520a01f ldff1sw {z31.d}, p0/z, \[z0.d\]
-+[^:]+: c520a01f ldff1sw {z31.d}, p0/z, \[z0.d\]
-+[^:]+: c520a800 ldff1sw {z0.d}, p2/z, \[z0.d\]
-+[^:]+: c520a800 ldff1sw {z0.d}, p2/z, \[z0.d\]
-+[^:]+: c520a800 ldff1sw {z0.d}, p2/z, \[z0.d\]
-+[^:]+: c520bc00 ldff1sw {z0.d}, p7/z, \[z0.d\]
-+[^:]+: c520bc00 ldff1sw {z0.d}, p7/z, \[z0.d\]
-+[^:]+: c520bc00 ldff1sw {z0.d}, p7/z, \[z0.d\]
-+[^:]+: c520a060 ldff1sw {z0.d}, p0/z, \[z3.d\]
-+[^:]+: c520a060 ldff1sw {z0.d}, p0/z, \[z3.d\]
-+[^:]+: c520a060 ldff1sw {z0.d}, p0/z, \[z3.d\]
-+[^:]+: c520a3e0 ldff1sw {z0.d}, p0/z, \[z31.d\]
-+[^:]+: c520a3e0 ldff1sw {z0.d}, p0/z, \[z31.d\]
-+[^:]+: c520a3e0 ldff1sw {z0.d}, p0/z, \[z31.d\]
-+[^:]+: c52fa000 ldff1sw {z0.d}, p0/z, \[z0.d, #60\]
-+[^:]+: c52fa000 ldff1sw {z0.d}, p0/z, \[z0.d, #60\]
-+[^:]+: c530a000 ldff1sw {z0.d}, p0/z, \[z0.d, #64\]
-+[^:]+: c530a000 ldff1sw {z0.d}, p0/z, \[z0.d, #64\]
-+[^:]+: c531a000 ldff1sw {z0.d}, p0/z, \[z0.d, #68\]
-+[^:]+: c531a000 ldff1sw {z0.d}, p0/z, \[z0.d, #68\]
-+[^:]+: c53fa000 ldff1sw {z0.d}, p0/z, \[z0.d, #124\]
-+[^:]+: c53fa000 ldff1sw {z0.d}, p0/z, \[z0.d, #124\]
-+[^:]+: 85006000 ldff1w {z0.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 85006000 ldff1w {z0.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 85006000 ldff1w {z0.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 85006000 ldff1w {z0.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 85006001 ldff1w {z1.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 85006001 ldff1w {z1.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 85006001 ldff1w {z1.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 85006001 ldff1w {z1.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 8500601f ldff1w {z31.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 8500601f ldff1w {z31.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 8500601f ldff1w {z31.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 8500601f ldff1w {z31.s}, p0/z, \[x0, z0.s, uxtw\]
-+[^:]+: 85006800 ldff1w {z0.s}, p2/z, \[x0, z0.s, uxtw\]
-+[^:]+: 85006800 ldff1w {z0.s}, p2/z, \[x0, z0.s, uxtw\]
-+[^:]+: 85006800 ldff1w {z0.s}, p2/z, \[x0, z0.s, uxtw\]
-+[^:]+: 85007c00 ldff1w {z0.s}, p7/z, \[x0, z0.s, uxtw\]
-+[^:]+: 85007c00 ldff1w {z0.s}, p7/z, \[x0, z0.s, uxtw\]
-+[^:]+: 85007c00 ldff1w {z0.s}, p7/z, \[x0, z0.s, uxtw\]
-+[^:]+: 85006060 ldff1w {z0.s}, p0/z, \[x3, z0.s, uxtw\]
-+[^:]+: 85006060 ldff1w {z0.s}, p0/z, \[x3, z0.s, uxtw\]
-+[^:]+: 85006060 ldff1w {z0.s}, p0/z, \[x3, z0.s, uxtw\]
-+[^:]+: 850063e0 ldff1w {z0.s}, p0/z, \[sp, z0.s, uxtw\]
-+[^:]+: 850063e0 ldff1w {z0.s}, p0/z, \[sp, z0.s, uxtw\]
-+[^:]+: 850063e0 ldff1w {z0.s}, p0/z, \[sp, z0.s, uxtw\]
-+[^:]+: 85046000 ldff1w {z0.s}, p0/z, \[x0, z4.s, uxtw\]
-+[^:]+: 85046000 ldff1w {z0.s}, p0/z, \[x0, z4.s, uxtw\]
-+[^:]+: 85046000 ldff1w {z0.s}, p0/z, \[x0, z4.s, uxtw\]
-+[^:]+: 851f6000 ldff1w {z0.s}, p0/z, \[x0, z31.s, uxtw\]
-+[^:]+: 851f6000 ldff1w {z0.s}, p0/z, \[x0, z31.s, uxtw\]
-+[^:]+: 851f6000 ldff1w {z0.s}, p0/z, \[x0, z31.s, uxtw\]
-+[^:]+: 85406000 ldff1w {z0.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 85406000 ldff1w {z0.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 85406000 ldff1w {z0.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 85406000 ldff1w {z0.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 85406001 ldff1w {z1.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 85406001 ldff1w {z1.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 85406001 ldff1w {z1.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 85406001 ldff1w {z1.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 8540601f ldff1w {z31.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 8540601f ldff1w {z31.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 8540601f ldff1w {z31.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 8540601f ldff1w {z31.s}, p0/z, \[x0, z0.s, sxtw\]
-+[^:]+: 85406800 ldff1w {z0.s}, p2/z, \[x0, z0.s, sxtw\]
-+[^:]+: 85406800 ldff1w {z0.s}, p2/z, \[x0, z0.s, sxtw\]
-+[^:]+: 85406800 ldff1w {z0.s}, p2/z, \[x0, z0.s, sxtw\]
-+[^:]+: 85407c00 ldff1w {z0.s}, p7/z, \[x0, z0.s, sxtw\]
-+[^:]+: 85407c00 ldff1w {z0.s}, p7/z, \[x0, z0.s, sxtw\]
-+[^:]+: 85407c00 ldff1w {z0.s}, p7/z, \[x0, z0.s, sxtw\]
-+[^:]+: 85406060 ldff1w {z0.s}, p0/z, \[x3, z0.s, sxtw\]
-+[^:]+: 85406060 ldff1w {z0.s}, p0/z, \[x3, z0.s, sxtw\]
-+[^:]+: 85406060 ldff1w {z0.s}, p0/z, \[x3, z0.s, sxtw\]
-+[^:]+: 854063e0 ldff1w {z0.s}, p0/z, \[sp, z0.s, sxtw\]
-+[^:]+: 854063e0 ldff1w {z0.s}, p0/z, \[sp, z0.s, sxtw\]
-+[^:]+: 854063e0 ldff1w {z0.s}, p0/z, \[sp, z0.s, sxtw\]
-+[^:]+: 85446000 ldff1w {z0.s}, p0/z, \[x0, z4.s, sxtw\]
-+[^:]+: 85446000 ldff1w {z0.s}, p0/z, \[x0, z4.s, sxtw\]
-+[^:]+: 85446000 ldff1w {z0.s}, p0/z, \[x0, z4.s, sxtw\]
-+[^:]+: 855f6000 ldff1w {z0.s}, p0/z, \[x0, z31.s, sxtw\]
-+[^:]+: 855f6000 ldff1w {z0.s}, p0/z, \[x0, z31.s, sxtw\]
-+[^:]+: 855f6000 ldff1w {z0.s}, p0/z, \[x0, z31.s, sxtw\]
-+[^:]+: 85206000 ldff1w {z0.s}, p0/z, \[x0, z0.s, uxtw #2\]
-+[^:]+: 85206000 ldff1w {z0.s}, p0/z, \[x0, z0.s, uxtw #2\]
-+[^:]+: 85206000 ldff1w {z0.s}, p0/z, \[x0, z0.s, uxtw #2\]
-+[^:]+: 85206001 ldff1w {z1.s}, p0/z, \[x0, z0.s, uxtw #2\]
-+[^:]+: 85206001 ldff1w {z1.s}, p0/z, \[x0, z0.s, uxtw #2\]
-+[^:]+: 85206001 ldff1w {z1.s}, p0/z, \[x0, z0.s, uxtw #2\]
-+[^:]+: 8520601f ldff1w {z31.s}, p0/z, \[x0, z0.s, uxtw #2\]
-+[^:]+: 8520601f ldff1w {z31.s}, p0/z, \[x0, z0.s, uxtw #2\]
-+[^:]+: 8520601f ldff1w {z31.s}, p0/z, \[x0, z0.s, uxtw #2\]
-+[^:]+: 85206800 ldff1w {z0.s}, p2/z, \[x0, z0.s, uxtw #2\]
-+[^:]+: 85206800 ldff1w {z0.s}, p2/z, \[x0, z0.s, uxtw #2\]
-+[^:]+: 85207c00 ldff1w {z0.s}, p7/z, \[x0, z0.s, uxtw #2\]
-+[^:]+: 85207c00 ldff1w {z0.s}, p7/z, \[x0, z0.s, uxtw #2\]
-+[^:]+: 85206060 ldff1w {z0.s}, p0/z, \[x3, z0.s, uxtw #2\]
-+[^:]+: 85206060 ldff1w {z0.s}, p0/z, \[x3, z0.s, uxtw #2\]
-+[^:]+: 852063e0 ldff1w {z0.s}, p0/z, \[sp, z0.s, uxtw #2\]
-+[^:]+: 852063e0 ldff1w {z0.s}, p0/z, \[sp, z0.s, uxtw #2\]
-+[^:]+: 85246000 ldff1w {z0.s}, p0/z, \[x0, z4.s, uxtw #2\]
-+[^:]+: 85246000 ldff1w {z0.s}, p0/z, \[x0, z4.s, uxtw #2\]
-+[^:]+: 853f6000 ldff1w {z0.s}, p0/z, \[x0, z31.s, uxtw #2\]
-+[^:]+: 853f6000 ldff1w {z0.s}, p0/z, \[x0, z31.s, uxtw #2\]
-+[^:]+: 85606000 ldff1w {z0.s}, p0/z, \[x0, z0.s, sxtw #2\]
-+[^:]+: 85606000 ldff1w {z0.s}, p0/z, \[x0, z0.s, sxtw #2\]
-+[^:]+: 85606000 ldff1w {z0.s}, p0/z, \[x0, z0.s, sxtw #2\]
-+[^:]+: 85606001 ldff1w {z1.s}, p0/z, \[x0, z0.s, sxtw #2\]
-+[^:]+: 85606001 ldff1w {z1.s}, p0/z, \[x0, z0.s, sxtw #2\]
-+[^:]+: 85606001 ldff1w {z1.s}, p0/z, \[x0, z0.s, sxtw #2\]
-+[^:]+: 8560601f ldff1w {z31.s}, p0/z, \[x0, z0.s, sxtw #2\]
-+[^:]+: 8560601f ldff1w {z31.s}, p0/z, \[x0, z0.s, sxtw #2\]
-+[^:]+: 8560601f ldff1w {z31.s}, p0/z, \[x0, z0.s, sxtw #2\]
-+[^:]+: 85606800 ldff1w {z0.s}, p2/z, \[x0, z0.s, sxtw #2\]
-+[^:]+: 85606800 ldff1w {z0.s}, p2/z, \[x0, z0.s, sxtw #2\]
-+[^:]+: 85607c00 ldff1w {z0.s}, p7/z, \[x0, z0.s, sxtw #2\]
-+[^:]+: 85607c00 ldff1w {z0.s}, p7/z, \[x0, z0.s, sxtw #2\]
-+[^:]+: 85606060 ldff1w {z0.s}, p0/z, \[x3, z0.s, sxtw #2\]
-+[^:]+: 85606060 ldff1w {z0.s}, p0/z, \[x3, z0.s, sxtw #2\]
-+[^:]+: 856063e0 ldff1w {z0.s}, p0/z, \[sp, z0.s, sxtw #2\]
-+[^:]+: 856063e0 ldff1w {z0.s}, p0/z, \[sp, z0.s, sxtw #2\]
-+[^:]+: 85646000 ldff1w {z0.s}, p0/z, \[x0, z4.s, sxtw #2\]
-+[^:]+: 85646000 ldff1w {z0.s}, p0/z, \[x0, z4.s, sxtw #2\]
-+[^:]+: 857f6000 ldff1w {z0.s}, p0/z, \[x0, z31.s, sxtw #2\]
-+[^:]+: 857f6000 ldff1w {z0.s}, p0/z, \[x0, z31.s, sxtw #2\]
-+[^:]+: a5406000 ldff1w {z0.s}, p0/z, \[x0, x0, lsl #2\]
-+[^:]+: a5406000 ldff1w {z0.s}, p0/z, \[x0, x0, lsl #2\]
-+[^:]+: a5406000 ldff1w {z0.s}, p0/z, \[x0, x0, lsl #2\]
-+[^:]+: a5406001 ldff1w {z1.s}, p0/z, \[x0, x0, lsl #2\]
-+[^:]+: a5406001 ldff1w {z1.s}, p0/z, \[x0, x0, lsl #2\]
-+[^:]+: a5406001 ldff1w {z1.s}, p0/z, \[x0, x0, lsl #2\]
-+[^:]+: a540601f ldff1w {z31.s}, p0/z, \[x0, x0, lsl #2\]
-+[^:]+: a540601f ldff1w {z31.s}, p0/z, \[x0, x0, lsl #2\]
-+[^:]+: a540601f ldff1w {z31.s}, p0/z, \[x0, x0, lsl #2\]
-+[^:]+: a5406800 ldff1w {z0.s}, p2/z, \[x0, x0, lsl #2\]
-+[^:]+: a5406800 ldff1w {z0.s}, p2/z, \[x0, x0, lsl #2\]
-+[^:]+: a5407c00 ldff1w {z0.s}, p7/z, \[x0, x0, lsl #2\]
-+[^:]+: a5407c00 ldff1w {z0.s}, p7/z, \[x0, x0, lsl #2\]
-+[^:]+: a5406060 ldff1w {z0.s}, p0/z, \[x3, x0, lsl #2\]
-+[^:]+: a5406060 ldff1w {z0.s}, p0/z, \[x3, x0, lsl #2\]
-+[^:]+: a54063e0 ldff1w {z0.s}, p0/z, \[sp, x0, lsl #2\]
-+[^:]+: a54063e0 ldff1w {z0.s}, p0/z, \[sp, x0, lsl #2\]
-+[^:]+: a5446000 ldff1w {z0.s}, p0/z, \[x0, x4, lsl #2\]
-+[^:]+: a5446000 ldff1w {z0.s}, p0/z, \[x0, x4, lsl #2\]
-+[^:]+: a55f6000 ldff1w {z0.s}, p0/z, \[x0, xzr, lsl #2\]
-+[^:]+: a55f6000 ldff1w {z0.s}, p0/z, \[x0, xzr, lsl #2\]
-+[^:]+: a5606000 ldff1w {z0.d}, p0/z, \[x0, x0, lsl #2\]
-+[^:]+: a5606000 ldff1w {z0.d}, p0/z, \[x0, x0, lsl #2\]
-+[^:]+: a5606000 ldff1w {z0.d}, p0/z, \[x0, x0, lsl #2\]
-+[^:]+: a5606001 ldff1w {z1.d}, p0/z, \[x0, x0, lsl #2\]
-+[^:]+: a5606001 ldff1w {z1.d}, p0/z, \[x0, x0, lsl #2\]
-+[^:]+: a5606001 ldff1w {z1.d}, p0/z, \[x0, x0, lsl #2\]
-+[^:]+: a560601f ldff1w {z31.d}, p0/z, \[x0, x0, lsl #2\]
-+[^:]+: a560601f ldff1w {z31.d}, p0/z, \[x0, x0, lsl #2\]
-+[^:]+: a560601f ldff1w {z31.d}, p0/z, \[x0, x0, lsl #2\]
-+[^:]+: a5606800 ldff1w {z0.d}, p2/z, \[x0, x0, lsl #2\]
-+[^:]+: a5606800 ldff1w {z0.d}, p2/z, \[x0, x0, lsl #2\]
-+[^:]+: a5607c00 ldff1w {z0.d}, p7/z, \[x0, x0, lsl #2\]
-+[^:]+: a5607c00 ldff1w {z0.d}, p7/z, \[x0, x0, lsl #2\]
-+[^:]+: a5606060 ldff1w {z0.d}, p0/z, \[x3, x0, lsl #2\]
-+[^:]+: a5606060 ldff1w {z0.d}, p0/z, \[x3, x0, lsl #2\]
-+[^:]+: a56063e0 ldff1w {z0.d}, p0/z, \[sp, x0, lsl #2\]
-+[^:]+: a56063e0 ldff1w {z0.d}, p0/z, \[sp, x0, lsl #2\]
-+[^:]+: a5646000 ldff1w {z0.d}, p0/z, \[x0, x4, lsl #2\]
-+[^:]+: a5646000 ldff1w {z0.d}, p0/z, \[x0, x4, lsl #2\]
-+[^:]+: a57f6000 ldff1w {z0.d}, p0/z, \[x0, xzr, lsl #2\]
-+[^:]+: a57f6000 ldff1w {z0.d}, p0/z, \[x0, xzr, lsl #2\]
-+[^:]+: c5006000 ldff1w {z0.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c5006000 ldff1w {z0.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c5006000 ldff1w {z0.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c5006000 ldff1w {z0.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c5006001 ldff1w {z1.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c5006001 ldff1w {z1.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c5006001 ldff1w {z1.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c5006001 ldff1w {z1.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c500601f ldff1w {z31.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c500601f ldff1w {z31.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c500601f ldff1w {z31.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c500601f ldff1w {z31.d}, p0/z, \[x0, z0.d, uxtw\]
-+[^:]+: c5006800 ldff1w {z0.d}, p2/z, \[x0, z0.d, uxtw\]
-+[^:]+: c5006800 ldff1w {z0.d}, p2/z, \[x0, z0.d, uxtw\]
-+[^:]+: c5006800 ldff1w {z0.d}, p2/z, \[x0, z0.d, uxtw\]
-+[^:]+: c5007c00 ldff1w {z0.d}, p7/z, \[x0, z0.d, uxtw\]
-+[^:]+: c5007c00 ldff1w {z0.d}, p7/z, \[x0, z0.d, uxtw\]
-+[^:]+: c5007c00 ldff1w {z0.d}, p7/z, \[x0, z0.d, uxtw\]
-+[^:]+: c5006060 ldff1w {z0.d}, p0/z, \[x3, z0.d, uxtw\]
-+[^:]+: c5006060 ldff1w {z0.d}, p0/z, \[x3, z0.d, uxtw\]
-+[^:]+: c5006060 ldff1w {z0.d}, p0/z, \[x3, z0.d, uxtw\]
-+[^:]+: c50063e0 ldff1w {z0.d}, p0/z, \[sp, z0.d, uxtw\]
-+[^:]+: c50063e0 ldff1w {z0.d}, p0/z, \[sp, z0.d, uxtw\]
-+[^:]+: c50063e0 ldff1w {z0.d}, p0/z, \[sp, z0.d, uxtw\]
-+[^:]+: c5046000 ldff1w {z0.d}, p0/z, \[x0, z4.d, uxtw\]
-+[^:]+: c5046000 ldff1w {z0.d}, p0/z, \[x0, z4.d, uxtw\]
-+[^:]+: c5046000 ldff1w {z0.d}, p0/z, \[x0, z4.d, uxtw\]
-+[^:]+: c51f6000 ldff1w {z0.d}, p0/z, \[x0, z31.d, uxtw\]
-+[^:]+: c51f6000 ldff1w {z0.d}, p0/z, \[x0, z31.d, uxtw\]
-+[^:]+: c51f6000 ldff1w {z0.d}, p0/z, \[x0, z31.d, uxtw\]
-+[^:]+: c5406000 ldff1w {z0.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5406000 ldff1w {z0.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5406000 ldff1w {z0.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5406000 ldff1w {z0.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5406001 ldff1w {z1.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5406001 ldff1w {z1.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5406001 ldff1w {z1.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5406001 ldff1w {z1.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c540601f ldff1w {z31.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c540601f ldff1w {z31.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c540601f ldff1w {z31.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c540601f ldff1w {z31.d}, p0/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5406800 ldff1w {z0.d}, p2/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5406800 ldff1w {z0.d}, p2/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5406800 ldff1w {z0.d}, p2/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5407c00 ldff1w {z0.d}, p7/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5407c00 ldff1w {z0.d}, p7/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5407c00 ldff1w {z0.d}, p7/z, \[x0, z0.d, sxtw\]
-+[^:]+: c5406060 ldff1w {z0.d}, p0/z, \[x3, z0.d, sxtw\]
-+[^:]+: c5406060 ldff1w {z0.d}, p0/z, \[x3, z0.d, sxtw\]
-+[^:]+: c5406060 ldff1w {z0.d}, p0/z, \[x3, z0.d, sxtw\]
-+[^:]+: c54063e0 ldff1w {z0.d}, p0/z, \[sp, z0.d, sxtw\]
-+[^:]+: c54063e0 ldff1w {z0.d}, p0/z, \[sp, z0.d, sxtw\]
-+[^:]+: c54063e0 ldff1w {z0.d}, p0/z, \[sp, z0.d, sxtw\]
-+[^:]+: c5446000 ldff1w {z0.d}, p0/z, \[x0, z4.d, sxtw\]
-+[^:]+: c5446000 ldff1w {z0.d}, p0/z, \[x0, z4.d, sxtw\]
-+[^:]+: c5446000 ldff1w {z0.d}, p0/z, \[x0, z4.d, sxtw\]
-+[^:]+: c55f6000 ldff1w {z0.d}, p0/z, \[x0, z31.d, sxtw\]
-+[^:]+: c55f6000 ldff1w {z0.d}, p0/z, \[x0, z31.d, sxtw\]
-+[^:]+: c55f6000 ldff1w {z0.d}, p0/z, \[x0, z31.d, sxtw\]
-+[^:]+: c5206000 ldff1w {z0.d}, p0/z, \[x0, z0.d, uxtw #2\]
-+[^:]+: c5206000 ldff1w {z0.d}, p0/z, \[x0, z0.d, uxtw #2\]
-+[^:]+: c5206000 ldff1w {z0.d}, p0/z, \[x0, z0.d, uxtw #2\]
-+[^:]+: c5206001 ldff1w {z1.d}, p0/z, \[x0, z0.d, uxtw #2\]
-+[^:]+: c5206001 ldff1w {z1.d}, p0/z, \[x0, z0.d, uxtw #2\]
-+[^:]+: c5206001 ldff1w {z1.d}, p0/z, \[x0, z0.d, uxtw #2\]
-+[^:]+: c520601f ldff1w {z31.d}, p0/z, \[x0, z0.d, uxtw #2\]
-+[^:]+: c520601f ldff1w {z31.d}, p0/z, \[x0, z0.d, uxtw #2\]
-+[^:]+: c520601f ldff1w {z31.d}, p0/z, \[x0, z0.d, uxtw #2\]
-+[^:]+: c5206800 ldff1w {z0.d}, p2/z, \[x0, z0.d, uxtw #2\]
-+[^:]+: c5206800 ldff1w {z0.d}, p2/z, \[x0, z0.d, uxtw #2\]
-+[^:]+: c5207c00 ldff1w {z0.d}, p7/z, \[x0, z0.d, uxtw #2\]
-+[^:]+: c5207c00 ldff1w {z0.d}, p7/z, \[x0, z0.d, uxtw #2\]
-+[^:]+: c5206060 ldff1w {z0.d}, p0/z, \[x3, z0.d, uxtw #2\]
-+[^:]+: c5206060 ldff1w {z0.d}, p0/z, \[x3, z0.d, uxtw #2\]
-+[^:]+: c52063e0 ldff1w {z0.d}, p0/z, \[sp, z0.d, uxtw #2\]
-+[^:]+: c52063e0 ldff1w {z0.d}, p0/z, \[sp, z0.d, uxtw #2\]
-+[^:]+: c5246000 ldff1w {z0.d}, p0/z, \[x0, z4.d, uxtw #2\]
-+[^:]+: c5246000 ldff1w {z0.d}, p0/z, \[x0, z4.d, uxtw #2\]
-+[^:]+: c53f6000 ldff1w {z0.d}, p0/z, \[x0, z31.d, uxtw #2\]
-+[^:]+: c53f6000 ldff1w {z0.d}, p0/z, \[x0, z31.d, uxtw #2\]
-+[^:]+: c5606000 ldff1w {z0.d}, p0/z, \[x0, z0.d, sxtw #2\]
-+[^:]+: c5606000 ldff1w {z0.d}, p0/z, \[x0, z0.d, sxtw #2\]
-+[^:]+: c5606000 ldff1w {z0.d}, p0/z, \[x0, z0.d, sxtw #2\]
-+[^:]+: c5606001 ldff1w {z1.d}, p0/z, \[x0, z0.d, sxtw #2\]
-+[^:]+: c5606001 ldff1w {z1.d}, p0/z, \[x0, z0.d, sxtw #2\]
-+[^:]+: c5606001 ldff1w {z1.d}, p0/z, \[x0, z0.d, sxtw #2\]
-+[^:]+: c560601f ldff1w {z31.d}, p0/z, \[x0, z0.d, sxtw #2\]
-+[^:]+: c560601f ldff1w {z31.d}, p0/z, \[x0, z0.d, sxtw #2\]
-+[^:]+: c560601f ldff1w {z31.d}, p0/z, \[x0, z0.d, sxtw #2\]
-+[^:]+: c5606800 ldff1w {z0.d}, p2/z, \[x0, z0.d, sxtw #2\]
-+[^:]+: c5606800 ldff1w {z0.d}, p2/z, \[x0, z0.d, sxtw #2\]
-+[^:]+: c5607c00 ldff1w {z0.d}, p7/z, \[x0, z0.d, sxtw #2\]
-+[^:]+: c5607c00 ldff1w {z0.d}, p7/z, \[x0, z0.d, sxtw #2\]
-+[^:]+: c5606060 ldff1w {z0.d}, p0/z, \[x3, z0.d, sxtw #2\]
-+[^:]+: c5606060 ldff1w {z0.d}, p0/z, \[x3, z0.d, sxtw #2\]
-+[^:]+: c56063e0 ldff1w {z0.d}, p0/z, \[sp, z0.d, sxtw #2\]
-+[^:]+: c56063e0 ldff1w {z0.d}, p0/z, \[sp, z0.d, sxtw #2\]
-+[^:]+: c5646000 ldff1w {z0.d}, p0/z, \[x0, z4.d, sxtw #2\]
-+[^:]+: c5646000 ldff1w {z0.d}, p0/z, \[x0, z4.d, sxtw #2\]
-+[^:]+: c57f6000 ldff1w {z0.d}, p0/z, \[x0, z31.d, sxtw #2\]
-+[^:]+: c57f6000 ldff1w {z0.d}, p0/z, \[x0, z31.d, sxtw #2\]
-+[^:]+: c540e000 ldff1w {z0.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c540e000 ldff1w {z0.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c540e000 ldff1w {z0.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c540e000 ldff1w {z0.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c540e001 ldff1w {z1.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c540e001 ldff1w {z1.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c540e001 ldff1w {z1.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c540e001 ldff1w {z1.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c540e01f ldff1w {z31.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c540e01f ldff1w {z31.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c540e01f ldff1w {z31.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c540e01f ldff1w {z31.d}, p0/z, \[x0, z0.d\]
-+[^:]+: c540e800 ldff1w {z0.d}, p2/z, \[x0, z0.d\]
-+[^:]+: c540e800 ldff1w {z0.d}, p2/z, \[x0, z0.d\]
-+[^:]+: c540e800 ldff1w {z0.d}, p2/z, \[x0, z0.d\]
-+[^:]+: c540fc00 ldff1w {z0.d}, p7/z, \[x0, z0.d\]
-+[^:]+: c540fc00 ldff1w {z0.d}, p7/z, \[x0, z0.d\]
-+[^:]+: c540fc00 ldff1w {z0.d}, p7/z, \[x0, z0.d\]
-+[^:]+: c540e060 ldff1w {z0.d}, p0/z, \[x3, z0.d\]
-+[^:]+: c540e060 ldff1w {z0.d}, p0/z, \[x3, z0.d\]
-+[^:]+: c540e060 ldff1w {z0.d}, p0/z, \[x3, z0.d\]
-+[^:]+: c540e3e0 ldff1w {z0.d}, p0/z, \[sp, z0.d\]
-+[^:]+: c540e3e0 ldff1w {z0.d}, p0/z, \[sp, z0.d\]
-+[^:]+: c540e3e0 ldff1w {z0.d}, p0/z, \[sp, z0.d\]
-+[^:]+: c544e000 ldff1w {z0.d}, p0/z, \[x0, z4.d\]
-+[^:]+: c544e000 ldff1w {z0.d}, p0/z, \[x0, z4.d\]
-+[^:]+: c544e000 ldff1w {z0.d}, p0/z, \[x0, z4.d\]
-+[^:]+: c55fe000 ldff1w {z0.d}, p0/z, \[x0, z31.d\]
-+[^:]+: c55fe000 ldff1w {z0.d}, p0/z, \[x0, z31.d\]
-+[^:]+: c55fe000 ldff1w {z0.d}, p0/z, \[x0, z31.d\]
-+[^:]+: c560e000 ldff1w {z0.d}, p0/z, \[x0, z0.d, lsl #2\]
-+[^:]+: c560e000 ldff1w {z0.d}, p0/z, \[x0, z0.d, lsl #2\]
-+[^:]+: c560e000 ldff1w {z0.d}, p0/z, \[x0, z0.d, lsl #2\]
-+[^:]+: c560e001 ldff1w {z1.d}, p0/z, \[x0, z0.d, lsl #2\]
-+[^:]+: c560e001 ldff1w {z1.d}, p0/z, \[x0, z0.d, lsl #2\]
-+[^:]+: c560e001 ldff1w {z1.d}, p0/z, \[x0, z0.d, lsl #2\]
-+[^:]+: c560e01f ldff1w {z31.d}, p0/z, \[x0, z0.d, lsl #2\]
-+[^:]+: c560e01f ldff1w {z31.d}, p0/z, \[x0, z0.d, lsl #2\]
-+[^:]+: c560e01f ldff1w {z31.d}, p0/z, \[x0, z0.d, lsl #2\]
-+[^:]+: c560e800 ldff1w {z0.d}, p2/z, \[x0, z0.d, lsl #2\]
-+[^:]+: c560e800 ldff1w {z0.d}, p2/z, \[x0, z0.d, lsl #2\]
-+[^:]+: c560fc00 ldff1w {z0.d}, p7/z, \[x0, z0.d, lsl #2\]
-+[^:]+: c560fc00 ldff1w {z0.d}, p7/z, \[x0, z0.d, lsl #2\]
-+[^:]+: c560e060 ldff1w {z0.d}, p0/z, \[x3, z0.d, lsl #2\]
-+[^:]+: c560e060 ldff1w {z0.d}, p0/z, \[x3, z0.d, lsl #2\]
-+[^:]+: c560e3e0 ldff1w {z0.d}, p0/z, \[sp, z0.d, lsl #2\]
-+[^:]+: c560e3e0 ldff1w {z0.d}, p0/z, \[sp, z0.d, lsl #2\]
-+[^:]+: c564e000 ldff1w {z0.d}, p0/z, \[x0, z4.d, lsl #2\]
-+[^:]+: c564e000 ldff1w {z0.d}, p0/z, \[x0, z4.d, lsl #2\]
-+[^:]+: c57fe000 ldff1w {z0.d}, p0/z, \[x0, z31.d, lsl #2\]
-+[^:]+: c57fe000 ldff1w {z0.d}, p0/z, \[x0, z31.d, lsl #2\]
-+[^:]+: 8520e000 ldff1w {z0.s}, p0/z, \[z0.s\]
-+[^:]+: 8520e000 ldff1w {z0.s}, p0/z, \[z0.s\]
-+[^:]+: 8520e000 ldff1w {z0.s}, p0/z, \[z0.s\]
-+[^:]+: 8520e000 ldff1w {z0.s}, p0/z, \[z0.s\]
-+[^:]+: 8520e001 ldff1w {z1.s}, p0/z, \[z0.s\]
-+[^:]+: 8520e001 ldff1w {z1.s}, p0/z, \[z0.s\]
-+[^:]+: 8520e001 ldff1w {z1.s}, p0/z, \[z0.s\]
-+[^:]+: 8520e001 ldff1w {z1.s}, p0/z, \[z0.s\]
-+[^:]+: 8520e01f ldff1w {z31.s}, p0/z, \[z0.s\]
-+[^:]+: 8520e01f ldff1w {z31.s}, p0/z, \[z0.s\]
-+[^:]+: 8520e01f ldff1w {z31.s}, p0/z, \[z0.s\]
-+[^:]+: 8520e01f ldff1w {z31.s}, p0/z, \[z0.s\]
-+[^:]+: 8520e800 ldff1w {z0.s}, p2/z, \[z0.s\]
-+[^:]+: 8520e800 ldff1w {z0.s}, p2/z, \[z0.s\]
-+[^:]+: 8520e800 ldff1w {z0.s}, p2/z, \[z0.s\]
-+[^:]+: 8520fc00 ldff1w {z0.s}, p7/z, \[z0.s\]
-+[^:]+: 8520fc00 ldff1w {z0.s}, p7/z, \[z0.s\]
-+[^:]+: 8520fc00 ldff1w {z0.s}, p7/z, \[z0.s\]
-+[^:]+: 8520e060 ldff1w {z0.s}, p0/z, \[z3.s\]
-+[^:]+: 8520e060 ldff1w {z0.s}, p0/z, \[z3.s\]
-+[^:]+: 8520e060 ldff1w {z0.s}, p0/z, \[z3.s\]
-+[^:]+: 8520e3e0 ldff1w {z0.s}, p0/z, \[z31.s\]
-+[^:]+: 8520e3e0 ldff1w {z0.s}, p0/z, \[z31.s\]
-+[^:]+: 8520e3e0 ldff1w {z0.s}, p0/z, \[z31.s\]
-+[^:]+: 852fe000 ldff1w {z0.s}, p0/z, \[z0.s, #60\]
-+[^:]+: 852fe000 ldff1w {z0.s}, p0/z, \[z0.s, #60\]
-+[^:]+: 8530e000 ldff1w {z0.s}, p0/z, \[z0.s, #64\]
-+[^:]+: 8530e000 ldff1w {z0.s}, p0/z, \[z0.s, #64\]
-+[^:]+: 8531e000 ldff1w {z0.s}, p0/z, \[z0.s, #68\]
-+[^:]+: 8531e000 ldff1w {z0.s}, p0/z, \[z0.s, #68\]
-+[^:]+: 853fe000 ldff1w {z0.s}, p0/z, \[z0.s, #124\]
-+[^:]+: 853fe000 ldff1w {z0.s}, p0/z, \[z0.s, #124\]
-+[^:]+: c520e000 ldff1w {z0.d}, p0/z, \[z0.d\]
-+[^:]+: c520e000 ldff1w {z0.d}, p0/z, \[z0.d\]
-+[^:]+: c520e000 ldff1w {z0.d}, p0/z, \[z0.d\]
-+[^:]+: c520e000 ldff1w {z0.d}, p0/z, \[z0.d\]
-+[^:]+: c520e001 ldff1w {z1.d}, p0/z, \[z0.d\]
-+[^:]+: c520e001 ldff1w {z1.d}, p0/z, \[z0.d\]
-+[^:]+: c520e001 ldff1w {z1.d}, p0/z, \[z0.d\]
-+[^:]+: c520e001 ldff1w {z1.d}, p0/z, \[z0.d\]
-+[^:]+: c520e01f ldff1w {z31.d}, p0/z, \[z0.d\]
-+[^:]+: c520e01f ldff1w {z31.d}, p0/z, \[z0.d\]
-+[^:]+: c520e01f ldff1w {z31.d}, p0/z, \[z0.d\]
-+[^:]+: c520e01f ldff1w {z31.d}, p0/z, \[z0.d\]
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-+[^:]+: c520e800 ldff1w {z0.d}, p2/z, \[z0.d\]
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-+[^:]+: a407e000 ldnt1b {z0.b}, p0/z, \[x0, #7, mul vl\]
-+[^:]+: a408e000 ldnt1b {z0.b}, p0/z, \[x0, #-8, mul vl\]
-+[^:]+: a408e000 ldnt1b {z0.b}, p0/z, \[x0, #-8, mul vl\]
-+[^:]+: a409e000 ldnt1b {z0.b}, p0/z, \[x0, #-7, mul vl\]
-+[^:]+: a409e000 ldnt1b {z0.b}, p0/z, \[x0, #-7, mul vl\]
-+[^:]+: a40fe000 ldnt1b {z0.b}, p0/z, \[x0, #-1, mul vl\]
-+[^:]+: a40fe000 ldnt1b {z0.b}, p0/z, \[x0, #-1, mul vl\]
-+[^:]+: a580c000 ldnt1d {z0.d}, p0/z, \[x0, x0, lsl #3\]
-+[^:]+: a580c000 ldnt1d {z0.d}, p0/z, \[x0, x0, lsl #3\]
-+[^:]+: a580c000 ldnt1d {z0.d}, p0/z, \[x0, x0, lsl #3\]
-+[^:]+: a580c001 ldnt1d {z1.d}, p0/z, \[x0, x0, lsl #3\]
-+[^:]+: a580c001 ldnt1d {z1.d}, p0/z, \[x0, x0, lsl #3\]
-+[^:]+: a580c001 ldnt1d {z1.d}, p0/z, \[x0, x0, lsl #3\]
-+[^:]+: a580c01f ldnt1d {z31.d}, p0/z, \[x0, x0, lsl #3\]
-+[^:]+: a580c01f ldnt1d {z31.d}, p0/z, \[x0, x0, lsl #3\]
-+[^:]+: a580c01f ldnt1d {z31.d}, p0/z, \[x0, x0, lsl #3\]
-+[^:]+: a580c800 ldnt1d {z0.d}, p2/z, \[x0, x0, lsl #3\]
-+[^:]+: a580c800 ldnt1d {z0.d}, p2/z, \[x0, x0, lsl #3\]
-+[^:]+: a580dc00 ldnt1d {z0.d}, p7/z, \[x0, x0, lsl #3\]
-+[^:]+: a580dc00 ldnt1d {z0.d}, p7/z, \[x0, x0, lsl #3\]
-+[^:]+: a580c060 ldnt1d {z0.d}, p0/z, \[x3, x0, lsl #3\]
-+[^:]+: a580c060 ldnt1d {z0.d}, p0/z, \[x3, x0, lsl #3\]
-+[^:]+: a580c3e0 ldnt1d {z0.d}, p0/z, \[sp, x0, lsl #3\]
-+[^:]+: a580c3e0 ldnt1d {z0.d}, p0/z, \[sp, x0, lsl #3\]
-+[^:]+: a584c000 ldnt1d {z0.d}, p0/z, \[x0, x4, lsl #3\]
-+[^:]+: a584c000 ldnt1d {z0.d}, p0/z, \[x0, x4, lsl #3\]
-+[^:]+: a59ec000 ldnt1d {z0.d}, p0/z, \[x0, x30, lsl #3\]
-+[^:]+: a59ec000 ldnt1d {z0.d}, p0/z, \[x0, x30, lsl #3\]
-+[^:]+: a580e000 ldnt1d {z0.d}, p0/z, \[x0\]
-+[^:]+: a580e000 ldnt1d {z0.d}, p0/z, \[x0\]
-+[^:]+: a580e000 ldnt1d {z0.d}, p0/z, \[x0\]
-+[^:]+: a580e000 ldnt1d {z0.d}, p0/z, \[x0\]
-+[^:]+: a580e000 ldnt1d {z0.d}, p0/z, \[x0\]
-+[^:]+: a580e001 ldnt1d {z1.d}, p0/z, \[x0\]
-+[^:]+: a580e001 ldnt1d {z1.d}, p0/z, \[x0\]
-+[^:]+: a580e001 ldnt1d {z1.d}, p0/z, \[x0\]
-+[^:]+: a580e001 ldnt1d {z1.d}, p0/z, \[x0\]
-+[^:]+: a580e001 ldnt1d {z1.d}, p0/z, \[x0\]
-+[^:]+: a580e01f ldnt1d {z31.d}, p0/z, \[x0\]
-+[^:]+: a580e01f ldnt1d {z31.d}, p0/z, \[x0\]
-+[^:]+: a580e01f ldnt1d {z31.d}, p0/z, \[x0\]
-+[^:]+: a580e01f ldnt1d {z31.d}, p0/z, \[x0\]
-+[^:]+: a580e01f ldnt1d {z31.d}, p0/z, \[x0\]
-+[^:]+: a580e800 ldnt1d {z0.d}, p2/z, \[x0\]
-+[^:]+: a580e800 ldnt1d {z0.d}, p2/z, \[x0\]
-+[^:]+: a580e800 ldnt1d {z0.d}, p2/z, \[x0\]
-+[^:]+: a580e800 ldnt1d {z0.d}, p2/z, \[x0\]
-+[^:]+: a580fc00 ldnt1d {z0.d}, p7/z, \[x0\]
-+[^:]+: a580fc00 ldnt1d {z0.d}, p7/z, \[x0\]
-+[^:]+: a580fc00 ldnt1d {z0.d}, p7/z, \[x0\]
-+[^:]+: a580fc00 ldnt1d {z0.d}, p7/z, \[x0\]
-+[^:]+: a580e060 ldnt1d {z0.d}, p0/z, \[x3\]
-+[^:]+: a580e060 ldnt1d {z0.d}, p0/z, \[x3\]
-+[^:]+: a580e060 ldnt1d {z0.d}, p0/z, \[x3\]
-+[^:]+: a580e060 ldnt1d {z0.d}, p0/z, \[x3\]
-+[^:]+: a580e3e0 ldnt1d {z0.d}, p0/z, \[sp\]
-+[^:]+: a580e3e0 ldnt1d {z0.d}, p0/z, \[sp\]
-+[^:]+: a580e3e0 ldnt1d {z0.d}, p0/z, \[sp\]
-+[^:]+: a580e3e0 ldnt1d {z0.d}, p0/z, \[sp\]
-+[^:]+: a587e000 ldnt1d {z0.d}, p0/z, \[x0, #7, mul vl\]
-+[^:]+: a587e000 ldnt1d {z0.d}, p0/z, \[x0, #7, mul vl\]
-+[^:]+: a588e000 ldnt1d {z0.d}, p0/z, \[x0, #-8, mul vl\]
-+[^:]+: a588e000 ldnt1d {z0.d}, p0/z, \[x0, #-8, mul vl\]
-+[^:]+: a589e000 ldnt1d {z0.d}, p0/z, \[x0, #-7, mul vl\]
-+[^:]+: a589e000 ldnt1d {z0.d}, p0/z, \[x0, #-7, mul vl\]
-+[^:]+: a58fe000 ldnt1d {z0.d}, p0/z, \[x0, #-1, mul vl\]
-+[^:]+: a58fe000 ldnt1d {z0.d}, p0/z, \[x0, #-1, mul vl\]
-+[^:]+: a480c000 ldnt1h {z0.h}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a480c000 ldnt1h {z0.h}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a480c000 ldnt1h {z0.h}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a480c001 ldnt1h {z1.h}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a480c001 ldnt1h {z1.h}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a480c001 ldnt1h {z1.h}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a480c01f ldnt1h {z31.h}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a480c01f ldnt1h {z31.h}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a480c01f ldnt1h {z31.h}, p0/z, \[x0, x0, lsl #1\]
-+[^:]+: a480c800 ldnt1h {z0.h}, p2/z, \[x0, x0, lsl #1\]
-+[^:]+: a480c800 ldnt1h {z0.h}, p2/z, \[x0, x0, lsl #1\]
-+[^:]+: a480dc00 ldnt1h {z0.h}, p7/z, \[x0, x0, lsl #1\]
-+[^:]+: a480dc00 ldnt1h {z0.h}, p7/z, \[x0, x0, lsl #1\]
-+[^:]+: a480c060 ldnt1h {z0.h}, p0/z, \[x3, x0, lsl #1\]
-+[^:]+: a480c060 ldnt1h {z0.h}, p0/z, \[x3, x0, lsl #1\]
-+[^:]+: a480c3e0 ldnt1h {z0.h}, p0/z, \[sp, x0, lsl #1\]
-+[^:]+: a480c3e0 ldnt1h {z0.h}, p0/z, \[sp, x0, lsl #1\]
-+[^:]+: a484c000 ldnt1h {z0.h}, p0/z, \[x0, x4, lsl #1\]
-+[^:]+: a484c000 ldnt1h {z0.h}, p0/z, \[x0, x4, lsl #1\]
-+[^:]+: a49ec000 ldnt1h {z0.h}, p0/z, \[x0, x30, lsl #1\]
-+[^:]+: a49ec000 ldnt1h {z0.h}, p0/z, \[x0, x30, lsl #1\]
-+[^:]+: a480e000 ldnt1h {z0.h}, p0/z, \[x0\]
-+[^:]+: a480e000 ldnt1h {z0.h}, p0/z, \[x0\]
-+[^:]+: a480e000 ldnt1h {z0.h}, p0/z, \[x0\]
-+[^:]+: a480e000 ldnt1h {z0.h}, p0/z, \[x0\]
-+[^:]+: a480e000 ldnt1h {z0.h}, p0/z, \[x0\]
-+[^:]+: a480e001 ldnt1h {z1.h}, p0/z, \[x0\]
-+[^:]+: a480e001 ldnt1h {z1.h}, p0/z, \[x0\]
-+[^:]+: a480e001 ldnt1h {z1.h}, p0/z, \[x0\]
-+[^:]+: a480e001 ldnt1h {z1.h}, p0/z, \[x0\]
-+[^:]+: a480e001 ldnt1h {z1.h}, p0/z, \[x0\]
-+[^:]+: a480e01f ldnt1h {z31.h}, p0/z, \[x0\]
-+[^:]+: a480e01f ldnt1h {z31.h}, p0/z, \[x0\]
-+[^:]+: a480e01f ldnt1h {z31.h}, p0/z, \[x0\]
-+[^:]+: a480e01f ldnt1h {z31.h}, p0/z, \[x0\]
-+[^:]+: a480e01f ldnt1h {z31.h}, p0/z, \[x0\]
-+[^:]+: a480e800 ldnt1h {z0.h}, p2/z, \[x0\]
-+[^:]+: a480e800 ldnt1h {z0.h}, p2/z, \[x0\]
-+[^:]+: a480e800 ldnt1h {z0.h}, p2/z, \[x0\]
-+[^:]+: a480e800 ldnt1h {z0.h}, p2/z, \[x0\]
-+[^:]+: a480fc00 ldnt1h {z0.h}, p7/z, \[x0\]
-+[^:]+: a480fc00 ldnt1h {z0.h}, p7/z, \[x0\]
-+[^:]+: a480fc00 ldnt1h {z0.h}, p7/z, \[x0\]
-+[^:]+: a480fc00 ldnt1h {z0.h}, p7/z, \[x0\]
-+[^:]+: a480e060 ldnt1h {z0.h}, p0/z, \[x3\]
-+[^:]+: a480e060 ldnt1h {z0.h}, p0/z, \[x3\]
-+[^:]+: a480e060 ldnt1h {z0.h}, p0/z, \[x3\]
-+[^:]+: a480e060 ldnt1h {z0.h}, p0/z, \[x3\]
-+[^:]+: a480e3e0 ldnt1h {z0.h}, p0/z, \[sp\]
-+[^:]+: a480e3e0 ldnt1h {z0.h}, p0/z, \[sp\]
-+[^:]+: a480e3e0 ldnt1h {z0.h}, p0/z, \[sp\]
-+[^:]+: a480e3e0 ldnt1h {z0.h}, p0/z, \[sp\]
-+[^:]+: a487e000 ldnt1h {z0.h}, p0/z, \[x0, #7, mul vl\]
-+[^:]+: a487e000 ldnt1h {z0.h}, p0/z, \[x0, #7, mul vl\]
-+[^:]+: a488e000 ldnt1h {z0.h}, p0/z, \[x0, #-8, mul vl\]
-+[^:]+: a488e000 ldnt1h {z0.h}, p0/z, \[x0, #-8, mul vl\]
-+[^:]+: a489e000 ldnt1h {z0.h}, p0/z, \[x0, #-7, mul vl\]
-+[^:]+: a489e000 ldnt1h {z0.h}, p0/z, \[x0, #-7, mul vl\]
-+[^:]+: a48fe000 ldnt1h {z0.h}, p0/z, \[x0, #-1, mul vl\]
-+[^:]+: a48fe000 ldnt1h {z0.h}, p0/z, \[x0, #-1, mul vl\]
-+[^:]+: a500c000 ldnt1w {z0.s}, p0/z, \[x0, x0, lsl #2\]
-+[^:]+: a500c000 ldnt1w {z0.s}, p0/z, \[x0, x0, lsl #2\]
-+[^:]+: a500c000 ldnt1w {z0.s}, p0/z, \[x0, x0, lsl #2\]
-+[^:]+: a500c001 ldnt1w {z1.s}, p0/z, \[x0, x0, lsl #2\]
-+[^:]+: a500c001 ldnt1w {z1.s}, p0/z, \[x0, x0, lsl #2\]
-+[^:]+: a500c001 ldnt1w {z1.s}, p0/z, \[x0, x0, lsl #2\]
-+[^:]+: a500c01f ldnt1w {z31.s}, p0/z, \[x0, x0, lsl #2\]
-+[^:]+: a500c01f ldnt1w {z31.s}, p0/z, \[x0, x0, lsl #2\]
-+[^:]+: a500c01f ldnt1w {z31.s}, p0/z, \[x0, x0, lsl #2\]
-+[^:]+: a500c800 ldnt1w {z0.s}, p2/z, \[x0, x0, lsl #2\]
-+[^:]+: a500c800 ldnt1w {z0.s}, p2/z, \[x0, x0, lsl #2\]
-+[^:]+: a500dc00 ldnt1w {z0.s}, p7/z, \[x0, x0, lsl #2\]
-+[^:]+: a500dc00 ldnt1w {z0.s}, p7/z, \[x0, x0, lsl #2\]
-+[^:]+: a500c060 ldnt1w {z0.s}, p0/z, \[x3, x0, lsl #2\]
-+[^:]+: a500c060 ldnt1w {z0.s}, p0/z, \[x3, x0, lsl #2\]
-+[^:]+: a500c3e0 ldnt1w {z0.s}, p0/z, \[sp, x0, lsl #2\]
-+[^:]+: a500c3e0 ldnt1w {z0.s}, p0/z, \[sp, x0, lsl #2\]
-+[^:]+: a504c000 ldnt1w {z0.s}, p0/z, \[x0, x4, lsl #2\]
-+[^:]+: a504c000 ldnt1w {z0.s}, p0/z, \[x0, x4, lsl #2\]
-+[^:]+: a51ec000 ldnt1w {z0.s}, p0/z, \[x0, x30, lsl #2\]
-+[^:]+: a51ec000 ldnt1w {z0.s}, p0/z, \[x0, x30, lsl #2\]
-+[^:]+: a50+e000 ldnt1w {z0.s}, p0/z, \[x0\]
-+[^:]+: a50+e000 ldnt1w {z0.s}, p0/z, \[x0\]
-+[^:]+: a50+e000 ldnt1w {z0.s}, p0/z, \[x0\]
-+[^:]+: a50+e000 ldnt1w {z0.s}, p0/z, \[x0\]
-+[^:]+: a50+e000 ldnt1w {z0.s}, p0/z, \[x0\]
-+[^:]+: a50+e001 ldnt1w {z1.s}, p0/z, \[x0\]
-+[^:]+: a50+e001 ldnt1w {z1.s}, p0/z, \[x0\]
-+[^:]+: a50+e001 ldnt1w {z1.s}, p0/z, \[x0\]
-+[^:]+: a50+e001 ldnt1w {z1.s}, p0/z, \[x0\]
-+[^:]+: a50+e001 ldnt1w {z1.s}, p0/z, \[x0\]
-+[^:]+: a50+e01f ldnt1w {z31.s}, p0/z, \[x0\]
-+[^:]+: a50+e01f ldnt1w {z31.s}, p0/z, \[x0\]
-+[^:]+: a50+e01f ldnt1w {z31.s}, p0/z, \[x0\]
-+[^:]+: a50+e01f ldnt1w {z31.s}, p0/z, \[x0\]
-+[^:]+: a50+e01f ldnt1w {z31.s}, p0/z, \[x0\]
-+[^:]+: a50+e800 ldnt1w {z0.s}, p2/z, \[x0\]
-+[^:]+: a50+e800 ldnt1w {z0.s}, p2/z, \[x0\]
-+[^:]+: a50+e800 ldnt1w {z0.s}, p2/z, \[x0\]
-+[^:]+: a50+e800 ldnt1w {z0.s}, p2/z, \[x0\]
-+[^:]+: a500fc00 ldnt1w {z0.s}, p7/z, \[x0\]
-+[^:]+: a500fc00 ldnt1w {z0.s}, p7/z, \[x0\]
-+[^:]+: a500fc00 ldnt1w {z0.s}, p7/z, \[x0\]
-+[^:]+: a500fc00 ldnt1w {z0.s}, p7/z, \[x0\]
-+[^:]+: a50+e060 ldnt1w {z0.s}, p0/z, \[x3\]
-+[^:]+: a50+e060 ldnt1w {z0.s}, p0/z, \[x3\]
-+[^:]+: a50+e060 ldnt1w {z0.s}, p0/z, \[x3\]
-+[^:]+: a50+e060 ldnt1w {z0.s}, p0/z, \[x3\]
-+[^:]+: a50+e3e0 ldnt1w {z0.s}, p0/z, \[sp\]
-+[^:]+: a50+e3e0 ldnt1w {z0.s}, p0/z, \[sp\]
-+[^:]+: a50+e3e0 ldnt1w {z0.s}, p0/z, \[sp\]
-+[^:]+: a50+e3e0 ldnt1w {z0.s}, p0/z, \[sp\]
-+[^:]+: a507e000 ldnt1w {z0.s}, p0/z, \[x0, #7, mul vl\]
-+[^:]+: a507e000 ldnt1w {z0.s}, p0/z, \[x0, #7, mul vl\]
-+[^:]+: a508e000 ldnt1w {z0.s}, p0/z, \[x0, #-8, mul vl\]
-+[^:]+: a508e000 ldnt1w {z0.s}, p0/z, \[x0, #-8, mul vl\]
-+[^:]+: a509e000 ldnt1w {z0.s}, p0/z, \[x0, #-7, mul vl\]
-+[^:]+: a509e000 ldnt1w {z0.s}, p0/z, \[x0, #-7, mul vl\]
-+[^:]+: a50fe000 ldnt1w {z0.s}, p0/z, \[x0, #-1, mul vl\]
-+[^:]+: a50fe000 ldnt1w {z0.s}, p0/z, \[x0, #-1, mul vl\]
-+[^:]+: 85800000 ldr p0, \[x0\]
-+[^:]+: 85800000 ldr p0, \[x0\]
-+[^:]+: 85800000 ldr p0, \[x0\]
-+[^:]+: 85800000 ldr p0, \[x0\]
-+[^:]+: 85800001 ldr p1, \[x0\]
-+[^:]+: 85800001 ldr p1, \[x0\]
-+[^:]+: 85800001 ldr p1, \[x0\]
-+[^:]+: 85800001 ldr p1, \[x0\]
-+[^:]+: 8580000f ldr p15, \[x0\]
-+[^:]+: 8580000f ldr p15, \[x0\]
-+[^:]+: 8580000f ldr p15, \[x0\]
-+[^:]+: 8580000f ldr p15, \[x0\]
-+[^:]+: 85800040 ldr p0, \[x2\]
-+[^:]+: 85800040 ldr p0, \[x2\]
-+[^:]+: 85800040 ldr p0, \[x2\]
-+[^:]+: 85800040 ldr p0, \[x2\]
-+[^:]+: 858003e0 ldr p0, \[sp\]
-+[^:]+: 858003e0 ldr p0, \[sp\]
-+[^:]+: 858003e0 ldr p0, \[sp\]
-+[^:]+: 858003e0 ldr p0, \[sp\]
-+[^:]+: 859f1c00 ldr p0, \[x0, #255, mul vl\]
-+[^:]+: 859f1c00 ldr p0, \[x0, #255, mul vl\]
-+[^:]+: 85a00000 ldr p0, \[x0, #-256, mul vl\]
-+[^:]+: 85a00000 ldr p0, \[x0, #-256, mul vl\]
-+[^:]+: 85a00400 ldr p0, \[x0, #-255, mul vl\]
-+[^:]+: 85a00400 ldr p0, \[x0, #-255, mul vl\]
-+[^:]+: 85bf1c00 ldr p0, \[x0, #-1, mul vl\]
-+[^:]+: 85bf1c00 ldr p0, \[x0, #-1, mul vl\]
-+[^:]+: 85804000 ldr z0, \[x0\]
-+[^:]+: 85804000 ldr z0, \[x0\]
-+[^:]+: 85804000 ldr z0, \[x0\]
-+[^:]+: 85804000 ldr z0, \[x0\]
-+[^:]+: 85804001 ldr z1, \[x0\]
-+[^:]+: 85804001 ldr z1, \[x0\]
-+[^:]+: 85804001 ldr z1, \[x0\]
-+[^:]+: 85804001 ldr z1, \[x0\]
-+[^:]+: 8580401f ldr z31, \[x0\]
-+[^:]+: 8580401f ldr z31, \[x0\]
-+[^:]+: 8580401f ldr z31, \[x0\]
-+[^:]+: 8580401f ldr z31, \[x0\]
-+[^:]+: 85804040 ldr z0, \[x2\]
-+[^:]+: 85804040 ldr z0, \[x2\]
-+[^:]+: 85804040 ldr z0, \[x2\]
-+[^:]+: 85804040 ldr z0, \[x2\]
-+[^:]+: 858043e0 ldr z0, \[sp\]
-+[^:]+: 858043e0 ldr z0, \[sp\]
-+[^:]+: 858043e0 ldr z0, \[sp\]
-+[^:]+: 858043e0 ldr z0, \[sp\]
-+[^:]+: 859f5c00 ldr z0, \[x0, #255, mul vl\]
-+[^:]+: 859f5c00 ldr z0, \[x0, #255, mul vl\]
-+[^:]+: 85a04000 ldr z0, \[x0, #-256, mul vl\]
-+[^:]+: 85a04000 ldr z0, \[x0, #-256, mul vl\]
-+[^:]+: 85a04400 ldr z0, \[x0, #-255, mul vl\]
-+[^:]+: 85a04400 ldr z0, \[x0, #-255, mul vl\]
-+[^:]+: 85bf5c00 ldr z0, \[x0, #-1, mul vl\]
-+[^:]+: 85bf5c00 ldr z0, \[x0, #-1, mul vl\]
-+[^:]+: 04208c00 lsl z0.b, z0.b, z0.d
-+[^:]+: 04208c00 lsl z0.b, z0.b, z0.d
-+[^:]+: 04208c01 lsl z1.b, z0.b, z0.d
-+[^:]+: 04208c01 lsl z1.b, z0.b, z0.d
-+[^:]+: 04208c1f lsl z31.b, z0.b, z0.d
-+[^:]+: 04208c1f lsl z31.b, z0.b, z0.d
-+[^:]+: 04208c40 lsl z0.b, z2.b, z0.d
-+[^:]+: 04208c40 lsl z0.b, z2.b, z0.d
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-+[^:]+: 0441801f lsr z31.s, p0/m, z31.s, #32
-+[^:]+: 04418800 lsr z0.s, p2/m, z0.s, #32
-+[^:]+: 04418800 lsr z0.s, p2/m, z0.s, #32
-+[^:]+: 04419c00 lsr z0.s, p7/m, z0.s, #32
-+[^:]+: 04419c00 lsr z0.s, p7/m, z0.s, #32
-+[^:]+: 04418003 lsr z3.s, p0/m, z3.s, #32
-+[^:]+: 04418003 lsr z3.s, p0/m, z3.s, #32
-+[^:]+: 04418020 lsr z0.s, p0/m, z0.s, #31
-+[^:]+: 04418020 lsr z0.s, p0/m, z0.s, #31
-+[^:]+: 044183c0 lsr z0.s, p0/m, z0.s, #2
-+[^:]+: 044183c0 lsr z0.s, p0/m, z0.s, #2
-+[^:]+: 044183e0 lsr z0.s, p0/m, z0.s, #1
-+[^:]+: 044183e0 lsr z0.s, p0/m, z0.s, #1
-+[^:]+: 04418100 lsr z0.s, p0/m, z0.s, #24
-+[^:]+: 04418100 lsr z0.s, p0/m, z0.s, #24
-+[^:]+: 04418101 lsr z1.s, p0/m, z1.s, #24
-+[^:]+: 04418101 lsr z1.s, p0/m, z1.s, #24
-+[^:]+: 0441811f lsr z31.s, p0/m, z31.s, #24
-+[^:]+: 0441811f lsr z31.s, p0/m, z31.s, #24
-+[^:]+: 04418900 lsr z0.s, p2/m, z0.s, #24
-+[^:]+: 04418900 lsr z0.s, p2/m, z0.s, #24
-+[^:]+: 04419d00 lsr z0.s, p7/m, z0.s, #24
-+[^:]+: 04419d00 lsr z0.s, p7/m, z0.s, #24
-+[^:]+: 04418103 lsr z3.s, p0/m, z3.s, #24
-+[^:]+: 04418103 lsr z3.s, p0/m, z3.s, #24
-+[^:]+: 04418120 lsr z0.s, p0/m, z0.s, #23
-+[^:]+: 04418120 lsr z0.s, p0/m, z0.s, #23
-+[^:]+: 048181c0 lsr z0.d, p0/m, z0.d, #50
-+[^:]+: 048181c0 lsr z0.d, p0/m, z0.d, #50
-+[^:]+: 048181e0 lsr z0.d, p0/m, z0.d, #49
-+[^:]+: 048181e0 lsr z0.d, p0/m, z0.d, #49
-+[^:]+: 04418200 lsr z0.s, p0/m, z0.s, #16
-+[^:]+: 04418200 lsr z0.s, p0/m, z0.s, #16
-+[^:]+: 04418201 lsr z1.s, p0/m, z1.s, #16
-+[^:]+: 04418201 lsr z1.s, p0/m, z1.s, #16
-+[^:]+: 0441821f lsr z31.s, p0/m, z31.s, #16
-+[^:]+: 0441821f lsr z31.s, p0/m, z31.s, #16
-+[^:]+: 04418a00 lsr z0.s, p2/m, z0.s, #16
-+[^:]+: 04418a00 lsr z0.s, p2/m, z0.s, #16
-+[^:]+: 04419e00 lsr z0.s, p7/m, z0.s, #16
-+[^:]+: 04419e00 lsr z0.s, p7/m, z0.s, #16
-+[^:]+: 04418203 lsr z3.s, p0/m, z3.s, #16
-+[^:]+: 04418203 lsr z3.s, p0/m, z3.s, #16
-+[^:]+: 04418220 lsr z0.s, p0/m, z0.s, #15
-+[^:]+: 04418220 lsr z0.s, p0/m, z0.s, #15
-+[^:]+: 048183c0 lsr z0.d, p0/m, z0.d, #34
-+[^:]+: 048183c0 lsr z0.d, p0/m, z0.d, #34
-+[^:]+: 048183e0 lsr z0.d, p0/m, z0.d, #33
-+[^:]+: 048183e0 lsr z0.d, p0/m, z0.d, #33
-+[^:]+: 04418300 lsr z0.s, p0/m, z0.s, #8
-+[^:]+: 04418300 lsr z0.s, p0/m, z0.s, #8
-+[^:]+: 04418301 lsr z1.s, p0/m, z1.s, #8
-+[^:]+: 04418301 lsr z1.s, p0/m, z1.s, #8
-+[^:]+: 0441831f lsr z31.s, p0/m, z31.s, #8
-+[^:]+: 0441831f lsr z31.s, p0/m, z31.s, #8
-+[^:]+: 04418b00 lsr z0.s, p2/m, z0.s, #8
-+[^:]+: 04418b00 lsr z0.s, p2/m, z0.s, #8
-+[^:]+: 04419f00 lsr z0.s, p7/m, z0.s, #8
-+[^:]+: 04419f00 lsr z0.s, p7/m, z0.s, #8
-+[^:]+: 04418303 lsr z3.s, p0/m, z3.s, #8
-+[^:]+: 04418303 lsr z3.s, p0/m, z3.s, #8
-+[^:]+: 04418320 lsr z0.s, p0/m, z0.s, #7
-+[^:]+: 04418320 lsr z0.s, p0/m, z0.s, #7
-+[^:]+: 04c181c0 lsr z0.d, p0/m, z0.d, #18
-+[^:]+: 04c181c0 lsr z0.d, p0/m, z0.d, #18
-+[^:]+: 04c181e0 lsr z0.d, p0/m, z0.d, #17
-+[^:]+: 04c181e0 lsr z0.d, p0/m, z0.d, #17
-+[^:]+: 04818000 lsr z0.d, p0/m, z0.d, #64
-+[^:]+: 04818000 lsr z0.d, p0/m, z0.d, #64
-+[^:]+: 04818001 lsr z1.d, p0/m, z1.d, #64
-+[^:]+: 04818001 lsr z1.d, p0/m, z1.d, #64
-+[^:]+: 0481801f lsr z31.d, p0/m, z31.d, #64
-+[^:]+: 0481801f lsr z31.d, p0/m, z31.d, #64
-+[^:]+: 04818800 lsr z0.d, p2/m, z0.d, #64
-+[^:]+: 04818800 lsr z0.d, p2/m, z0.d, #64
-+[^:]+: 04819c00 lsr z0.d, p7/m, z0.d, #64
-+[^:]+: 04819c00 lsr z0.d, p7/m, z0.d, #64
-+[^:]+: 04818003 lsr z3.d, p0/m, z3.d, #64
-+[^:]+: 04818003 lsr z3.d, p0/m, z3.d, #64
-+[^:]+: 04818020 lsr z0.d, p0/m, z0.d, #63
-+[^:]+: 04818020 lsr z0.d, p0/m, z0.d, #63
-+[^:]+: 04c183c0 lsr z0.d, p0/m, z0.d, #2
-+[^:]+: 04c183c0 lsr z0.d, p0/m, z0.d, #2
-+[^:]+: 04c183e0 lsr z0.d, p0/m, z0.d, #1
-+[^:]+: 04c183e0 lsr z0.d, p0/m, z0.d, #1
-+[^:]+: 04818100 lsr z0.d, p0/m, z0.d, #56
-+[^:]+: 04818100 lsr z0.d, p0/m, z0.d, #56
-+[^:]+: 04818101 lsr z1.d, p0/m, z1.d, #56
-+[^:]+: 04818101 lsr z1.d, p0/m, z1.d, #56
-+[^:]+: 0481811f lsr z31.d, p0/m, z31.d, #56
-+[^:]+: 0481811f lsr z31.d, p0/m, z31.d, #56
-+[^:]+: 04818900 lsr z0.d, p2/m, z0.d, #56
-+[^:]+: 04818900 lsr z0.d, p2/m, z0.d, #56
-+[^:]+: 04819d00 lsr z0.d, p7/m, z0.d, #56
-+[^:]+: 04819d00 lsr z0.d, p7/m, z0.d, #56
-+[^:]+: 04818103 lsr z3.d, p0/m, z3.d, #56
-+[^:]+: 04818103 lsr z3.d, p0/m, z3.d, #56
-+[^:]+: 04818120 lsr z0.d, p0/m, z0.d, #55
-+[^:]+: 04818120 lsr z0.d, p0/m, z0.d, #55
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-+[^:]+: 04818200 lsr z0.d, p0/m, z0.d, #48
-+[^:]+: 04818201 lsr z1.d, p0/m, z1.d, #48
-+[^:]+: 04818201 lsr z1.d, p0/m, z1.d, #48
-+[^:]+: 0481821f lsr z31.d, p0/m, z31.d, #48
-+[^:]+: 0481821f lsr z31.d, p0/m, z31.d, #48
-+[^:]+: 04818a00 lsr z0.d, p2/m, z0.d, #48
-+[^:]+: 04818a00 lsr z0.d, p2/m, z0.d, #48
-+[^:]+: 04819e00 lsr z0.d, p7/m, z0.d, #48
-+[^:]+: 04819e00 lsr z0.d, p7/m, z0.d, #48
-+[^:]+: 04818203 lsr z3.d, p0/m, z3.d, #48
-+[^:]+: 04818203 lsr z3.d, p0/m, z3.d, #48
-+[^:]+: 04818220 lsr z0.d, p0/m, z0.d, #47
-+[^:]+: 04818220 lsr z0.d, p0/m, z0.d, #47
-+[^:]+: 04818300 lsr z0.d, p0/m, z0.d, #40
-+[^:]+: 04818300 lsr z0.d, p0/m, z0.d, #40
-+[^:]+: 04818301 lsr z1.d, p0/m, z1.d, #40
-+[^:]+: 04818301 lsr z1.d, p0/m, z1.d, #40
-+[^:]+: 0481831f lsr z31.d, p0/m, z31.d, #40
-+[^:]+: 0481831f lsr z31.d, p0/m, z31.d, #40
-+[^:]+: 04818b00 lsr z0.d, p2/m, z0.d, #40
-+[^:]+: 04818b00 lsr z0.d, p2/m, z0.d, #40
-+[^:]+: 04819f00 lsr z0.d, p7/m, z0.d, #40
-+[^:]+: 04819f00 lsr z0.d, p7/m, z0.d, #40
-+[^:]+: 04818303 lsr z3.d, p0/m, z3.d, #40
-+[^:]+: 04818303 lsr z3.d, p0/m, z3.d, #40
-+[^:]+: 04818320 lsr z0.d, p0/m, z0.d, #39
-+[^:]+: 04818320 lsr z0.d, p0/m, z0.d, #39
-+[^:]+: 04c18000 lsr z0.d, p0/m, z0.d, #32
-+[^:]+: 04c18000 lsr z0.d, p0/m, z0.d, #32
-+[^:]+: 04c18001 lsr z1.d, p0/m, z1.d, #32
-+[^:]+: 04c18001 lsr z1.d, p0/m, z1.d, #32
-+[^:]+: 04c1801f lsr z31.d, p0/m, z31.d, #32
-+[^:]+: 04c1801f lsr z31.d, p0/m, z31.d, #32
-+[^:]+: 04c18800 lsr z0.d, p2/m, z0.d, #32
-+[^:]+: 04c18800 lsr z0.d, p2/m, z0.d, #32
-+[^:]+: 04c19c00 lsr z0.d, p7/m, z0.d, #32
-+[^:]+: 04c19c00 lsr z0.d, p7/m, z0.d, #32
-+[^:]+: 04c18003 lsr z3.d, p0/m, z3.d, #32
-+[^:]+: 04c18003 lsr z3.d, p0/m, z3.d, #32
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-+[^:]+: 04c18020 lsr z0.d, p0/m, z0.d, #31
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-+[^:]+: 04c18100 lsr z0.d, p0/m, z0.d, #24
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-+[^:]+: 04c18101 lsr z1.d, p0/m, z1.d, #24
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-+[^:]+: 04c1811f lsr z31.d, p0/m, z31.d, #24
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-+[^:]+: 04c18900 lsr z0.d, p2/m, z0.d, #24
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-+[^:]+: 04c19d00 lsr z0.d, p7/m, z0.d, #24
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-+[^:]+: 04c18103 lsr z3.d, p0/m, z3.d, #24
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-+[^:]+: 04c18120 lsr z0.d, p0/m, z0.d, #23
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-+[^:]+: 04c1821f lsr z31.d, p0/m, z31.d, #16
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-+[^:]+: 04c18a00 lsr z0.d, p2/m, z0.d, #16
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-+[^:]+: 04c18320 lsr z0.d, p0/m, z0.d, #7
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-+[^:]+: 04158000 lsrr z0.b, p0/m, z0.b, z0.b
-+[^:]+: 04158001 lsrr z1.b, p0/m, z1.b, z0.b
-+[^:]+: 04158001 lsrr z1.b, p0/m, z1.b, z0.b
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-+[^:]+: 0480e001 msb z1.s, p0/m, z0.s, z0.s
-+[^:]+: 0480e01f msb z31.s, p0/m, z0.s, z0.s
-+[^:]+: 0480e01f msb z31.s, p0/m, z0.s, z0.s
-+[^:]+: 0480e800 msb z0.s, p2/m, z0.s, z0.s
-+[^:]+: 0480e800 msb z0.s, p2/m, z0.s, z0.s
-+[^:]+: 0480fc00 msb z0.s, p7/m, z0.s, z0.s
-+[^:]+: 0480fc00 msb z0.s, p7/m, z0.s, z0.s
-+[^:]+: 0483e000 msb z0.s, p0/m, z3.s, z0.s
-+[^:]+: 0483e000 msb z0.s, p0/m, z3.s, z0.s
-+[^:]+: 049fe000 msb z0.s, p0/m, z31.s, z0.s
-+[^:]+: 049fe000 msb z0.s, p0/m, z31.s, z0.s
-+[^:]+: 0480e080 msb z0.s, p0/m, z0.s, z4.s
-+[^:]+: 0480e080 msb z0.s, p0/m, z0.s, z4.s
-+[^:]+: 0480e3e0 msb z0.s, p0/m, z0.s, z31.s
-+[^:]+: 0480e3e0 msb z0.s, p0/m, z0.s, z31.s
-+[^:]+: 04c0e000 msb z0.d, p0/m, z0.d, z0.d
-+[^:]+: 04c0e000 msb z0.d, p0/m, z0.d, z0.d
-+[^:]+: 04c0e001 msb z1.d, p0/m, z0.d, z0.d
-+[^:]+: 04c0e001 msb z1.d, p0/m, z0.d, z0.d
-+[^:]+: 04c0e01f msb z31.d, p0/m, z0.d, z0.d
-+[^:]+: 04c0e01f msb z31.d, p0/m, z0.d, z0.d
-+[^:]+: 04c0e800 msb z0.d, p2/m, z0.d, z0.d
-+[^:]+: 04c0e800 msb z0.d, p2/m, z0.d, z0.d
-+[^:]+: 04c0fc00 msb z0.d, p7/m, z0.d, z0.d
-+[^:]+: 04c0fc00 msb z0.d, p7/m, z0.d, z0.d
-+[^:]+: 04c3e000 msb z0.d, p0/m, z3.d, z0.d
-+[^:]+: 04c3e000 msb z0.d, p0/m, z3.d, z0.d
-+[^:]+: 04dfe000 msb z0.d, p0/m, z31.d, z0.d
-+[^:]+: 04dfe000 msb z0.d, p0/m, z31.d, z0.d
-+[^:]+: 04c0e080 msb z0.d, p0/m, z0.d, z4.d
-+[^:]+: 04c0e080 msb z0.d, p0/m, z0.d, z4.d
-+[^:]+: 04c0e3e0 msb z0.d, p0/m, z0.d, z31.d
-+[^:]+: 04c0e3e0 msb z0.d, p0/m, z0.d, z31.d
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-+[^:]+: 2530c000 mul z0.b, z0.b, #0
-+[^:]+: 2530c001 mul z1.b, z1.b, #0
-+[^:]+: 2530c001 mul z1.b, z1.b, #0
-+[^:]+: 2530c01f mul z31.b, z31.b, #0
-+[^:]+: 2530c01f mul z31.b, z31.b, #0
-+[^:]+: 2530c002 mul z2.b, z2.b, #0
-+[^:]+: 2530c002 mul z2.b, z2.b, #0
-+[^:]+: 2530cfe0 mul z0.b, z0.b, #127
-+[^:]+: 2530cfe0 mul z0.b, z0.b, #127
-+[^:]+: 2530d000 mul z0.b, z0.b, #-128
-+[^:]+: 2530d000 mul z0.b, z0.b, #-128
-+[^:]+: 2530d020 mul z0.b, z0.b, #-127
-+[^:]+: 2530d020 mul z0.b, z0.b, #-127
-+[^:]+: 2530dfe0 mul z0.b, z0.b, #-1
-+[^:]+: 2530dfe0 mul z0.b, z0.b, #-1
-+[^:]+: 2570c000 mul z0.h, z0.h, #0
-+[^:]+: 2570c000 mul z0.h, z0.h, #0
-+[^:]+: 2570c001 mul z1.h, z1.h, #0
-+[^:]+: 2570c001 mul z1.h, z1.h, #0
-+[^:]+: 2570c01f mul z31.h, z31.h, #0
-+[^:]+: 2570c01f mul z31.h, z31.h, #0
-+[^:]+: 2570c002 mul z2.h, z2.h, #0
-+[^:]+: 2570c002 mul z2.h, z2.h, #0
-+[^:]+: 2570cfe0 mul z0.h, z0.h, #127
-+[^:]+: 2570cfe0 mul z0.h, z0.h, #127
-+[^:]+: 2570d000 mul z0.h, z0.h, #-128
-+[^:]+: 2570d000 mul z0.h, z0.h, #-128
-+[^:]+: 2570d020 mul z0.h, z0.h, #-127
-+[^:]+: 2570d020 mul z0.h, z0.h, #-127
-+[^:]+: 2570dfe0 mul z0.h, z0.h, #-1
-+[^:]+: 2570dfe0 mul z0.h, z0.h, #-1
-+[^:]+: 25b0c000 mul z0.s, z0.s, #0
-+[^:]+: 25b0c000 mul z0.s, z0.s, #0
-+[^:]+: 25b0c001 mul z1.s, z1.s, #0
-+[^:]+: 25b0c001 mul z1.s, z1.s, #0
-+[^:]+: 25b0c01f mul z31.s, z31.s, #0
-+[^:]+: 25b0c01f mul z31.s, z31.s, #0
-+[^:]+: 25b0c002 mul z2.s, z2.s, #0
-+[^:]+: 25b0c002 mul z2.s, z2.s, #0
-+[^:]+: 25b0cfe0 mul z0.s, z0.s, #127
-+[^:]+: 25b0cfe0 mul z0.s, z0.s, #127
-+[^:]+: 25b0d000 mul z0.s, z0.s, #-128
-+[^:]+: 25b0d000 mul z0.s, z0.s, #-128
-+[^:]+: 25b0d020 mul z0.s, z0.s, #-127
-+[^:]+: 25b0d020 mul z0.s, z0.s, #-127
-+[^:]+: 25b0dfe0 mul z0.s, z0.s, #-1
-+[^:]+: 25b0dfe0 mul z0.s, z0.s, #-1
-+[^:]+: 25f0c000 mul z0.d, z0.d, #0
-+[^:]+: 25f0c000 mul z0.d, z0.d, #0
-+[^:]+: 25f0c001 mul z1.d, z1.d, #0
-+[^:]+: 25f0c001 mul z1.d, z1.d, #0
-+[^:]+: 25f0c01f mul z31.d, z31.d, #0
-+[^:]+: 25f0c01f mul z31.d, z31.d, #0
-+[^:]+: 25f0c002 mul z2.d, z2.d, #0
-+[^:]+: 25f0c002 mul z2.d, z2.d, #0
-+[^:]+: 25f0cfe0 mul z0.d, z0.d, #127
-+[^:]+: 25f0cfe0 mul z0.d, z0.d, #127
-+[^:]+: 25f0d000 mul z0.d, z0.d, #-128
-+[^:]+: 25f0d000 mul z0.d, z0.d, #-128
-+[^:]+: 25f0d020 mul z0.d, z0.d, #-127
-+[^:]+: 25f0d020 mul z0.d, z0.d, #-127
-+[^:]+: 25f0dfe0 mul z0.d, z0.d, #-1
-+[^:]+: 25f0dfe0 mul z0.d, z0.d, #-1
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-+[^:]+: 04100000 mul z0.b, p0/m, z0.b, z0.b
-+[^:]+: 04100001 mul z1.b, p0/m, z1.b, z0.b
-+[^:]+: 04100001 mul z1.b, p0/m, z1.b, z0.b
-+[^:]+: 0410001f mul z31.b, p0/m, z31.b, z0.b
-+[^:]+: 0410001f mul z31.b, p0/m, z31.b, z0.b
-+[^:]+: 04100800 mul z0.b, p2/m, z0.b, z0.b
-+[^:]+: 04100800 mul z0.b, p2/m, z0.b, z0.b
-+[^:]+: 04101c00 mul z0.b, p7/m, z0.b, z0.b
-+[^:]+: 04101c00 mul z0.b, p7/m, z0.b, z0.b
-+[^:]+: 04100003 mul z3.b, p0/m, z3.b, z0.b
-+[^:]+: 04100003 mul z3.b, p0/m, z3.b, z0.b
-+[^:]+: 04100080 mul z0.b, p0/m, z0.b, z4.b
-+[^:]+: 04100080 mul z0.b, p0/m, z0.b, z4.b
-+[^:]+: 041003e0 mul z0.b, p0/m, z0.b, z31.b
-+[^:]+: 041003e0 mul z0.b, p0/m, z0.b, z31.b
-+[^:]+: 04500000 mul z0.h, p0/m, z0.h, z0.h
-+[^:]+: 04500000 mul z0.h, p0/m, z0.h, z0.h
-+[^:]+: 04500001 mul z1.h, p0/m, z1.h, z0.h
-+[^:]+: 04500001 mul z1.h, p0/m, z1.h, z0.h
-+[^:]+: 0450001f mul z31.h, p0/m, z31.h, z0.h
-+[^:]+: 0450001f mul z31.h, p0/m, z31.h, z0.h
-+[^:]+: 04500800 mul z0.h, p2/m, z0.h, z0.h
-+[^:]+: 04500800 mul z0.h, p2/m, z0.h, z0.h
-+[^:]+: 04501c00 mul z0.h, p7/m, z0.h, z0.h
-+[^:]+: 04501c00 mul z0.h, p7/m, z0.h, z0.h
-+[^:]+: 04500003 mul z3.h, p0/m, z3.h, z0.h
-+[^:]+: 04500003 mul z3.h, p0/m, z3.h, z0.h
-+[^:]+: 04500080 mul z0.h, p0/m, z0.h, z4.h
-+[^:]+: 04500080 mul z0.h, p0/m, z0.h, z4.h
-+[^:]+: 045003e0 mul z0.h, p0/m, z0.h, z31.h
-+[^:]+: 045003e0 mul z0.h, p0/m, z0.h, z31.h
-+[^:]+: 04900000 mul z0.s, p0/m, z0.s, z0.s
-+[^:]+: 04900000 mul z0.s, p0/m, z0.s, z0.s
-+[^:]+: 04900001 mul z1.s, p0/m, z1.s, z0.s
-+[^:]+: 04900001 mul z1.s, p0/m, z1.s, z0.s
-+[^:]+: 0490001f mul z31.s, p0/m, z31.s, z0.s
-+[^:]+: 0490001f mul z31.s, p0/m, z31.s, z0.s
-+[^:]+: 04900800 mul z0.s, p2/m, z0.s, z0.s
-+[^:]+: 04900800 mul z0.s, p2/m, z0.s, z0.s
-+[^:]+: 04901c00 mul z0.s, p7/m, z0.s, z0.s
-+[^:]+: 04901c00 mul z0.s, p7/m, z0.s, z0.s
-+[^:]+: 04900003 mul z3.s, p0/m, z3.s, z0.s
-+[^:]+: 04900003 mul z3.s, p0/m, z3.s, z0.s
-+[^:]+: 04900080 mul z0.s, p0/m, z0.s, z4.s
-+[^:]+: 04900080 mul z0.s, p0/m, z0.s, z4.s
-+[^:]+: 049003e0 mul z0.s, p0/m, z0.s, z31.s
-+[^:]+: 049003e0 mul z0.s, p0/m, z0.s, z31.s
-+[^:]+: 04d00000 mul z0.d, p0/m, z0.d, z0.d
-+[^:]+: 04d00000 mul z0.d, p0/m, z0.d, z0.d
-+[^:]+: 04d00001 mul z1.d, p0/m, z1.d, z0.d
-+[^:]+: 04d00001 mul z1.d, p0/m, z1.d, z0.d
-+[^:]+: 04d0001f mul z31.d, p0/m, z31.d, z0.d
-+[^:]+: 04d0001f mul z31.d, p0/m, z31.d, z0.d
-+[^:]+: 04d00800 mul z0.d, p2/m, z0.d, z0.d
-+[^:]+: 04d00800 mul z0.d, p2/m, z0.d, z0.d
-+[^:]+: 04d01c00 mul z0.d, p7/m, z0.d, z0.d
-+[^:]+: 04d01c00 mul z0.d, p7/m, z0.d, z0.d
-+[^:]+: 04d00003 mul z3.d, p0/m, z3.d, z0.d
-+[^:]+: 04d00003 mul z3.d, p0/m, z3.d, z0.d
-+[^:]+: 04d00080 mul z0.d, p0/m, z0.d, z4.d
-+[^:]+: 04d00080 mul z0.d, p0/m, z0.d, z4.d
-+[^:]+: 04d003e0 mul z0.d, p0/m, z0.d, z31.d
-+[^:]+: 04d003e0 mul z0.d, p0/m, z0.d, z31.d
-+[^:]+: 25804210 nand p0.b, p0/z, p0.b, p0.b
-+[^:]+: 25804210 nand p0.b, p0/z, p0.b, p0.b
-+[^:]+: 25804211 nand p1.b, p0/z, p0.b, p0.b
-+[^:]+: 25804211 nand p1.b, p0/z, p0.b, p0.b
-+[^:]+: 2580421f nand p15.b, p0/z, p0.b, p0.b
-+[^:]+: 2580421f nand p15.b, p0/z, p0.b, p0.b
-+[^:]+: 25804a10 nand p0.b, p2/z, p0.b, p0.b
-+[^:]+: 25804a10 nand p0.b, p2/z, p0.b, p0.b
-+[^:]+: 25807e10 nand p0.b, p15/z, p0.b, p0.b
-+[^:]+: 25807e10 nand p0.b, p15/z, p0.b, p0.b
-+[^:]+: 25804270 nand p0.b, p0/z, p3.b, p0.b
-+[^:]+: 25804270 nand p0.b, p0/z, p3.b, p0.b
-+[^:]+: 258043f0 nand p0.b, p0/z, p15.b, p0.b
-+[^:]+: 258043f0 nand p0.b, p0/z, p15.b, p0.b
-+[^:]+: 25844210 nand p0.b, p0/z, p0.b, p4.b
-+[^:]+: 25844210 nand p0.b, p0/z, p0.b, p4.b
-+[^:]+: 258f4210 nand p0.b, p0/z, p0.b, p15.b
-+[^:]+: 258f4210 nand p0.b, p0/z, p0.b, p15.b
-+[^:]+: 25c04210 nands p0.b, p0/z, p0.b, p0.b
-+[^:]+: 25c04210 nands p0.b, p0/z, p0.b, p0.b
-+[^:]+: 25c04211 nands p1.b, p0/z, p0.b, p0.b
-+[^:]+: 25c04211 nands p1.b, p0/z, p0.b, p0.b
-+[^:]+: 25c0421f nands p15.b, p0/z, p0.b, p0.b
-+[^:]+: 25c0421f nands p15.b, p0/z, p0.b, p0.b
-+[^:]+: 25c04a10 nands p0.b, p2/z, p0.b, p0.b
-+[^:]+: 25c04a10 nands p0.b, p2/z, p0.b, p0.b
-+[^:]+: 25c07e10 nands p0.b, p15/z, p0.b, p0.b
-+[^:]+: 25c07e10 nands p0.b, p15/z, p0.b, p0.b
-+[^:]+: 25c04270 nands p0.b, p0/z, p3.b, p0.b
-+[^:]+: 25c04270 nands p0.b, p0/z, p3.b, p0.b
-+[^:]+: 25c043f0 nands p0.b, p0/z, p15.b, p0.b
-+[^:]+: 25c043f0 nands p0.b, p0/z, p15.b, p0.b
-+[^:]+: 25c44210 nands p0.b, p0/z, p0.b, p4.b
-+[^:]+: 25c44210 nands p0.b, p0/z, p0.b, p4.b
-+[^:]+: 25cf4210 nands p0.b, p0/z, p0.b, p15.b
-+[^:]+: 25cf4210 nands p0.b, p0/z, p0.b, p15.b
-+[^:]+: 0417a000 neg z0.b, p0/m, z0.b
-+[^:]+: 0417a000 neg z0.b, p0/m, z0.b
-+[^:]+: 0417a001 neg z1.b, p0/m, z0.b
-+[^:]+: 0417a001 neg z1.b, p0/m, z0.b
-+[^:]+: 0417a01f neg z31.b, p0/m, z0.b
-+[^:]+: 0417a01f neg z31.b, p0/m, z0.b
-+[^:]+: 0417a800 neg z0.b, p2/m, z0.b
-+[^:]+: 0417a800 neg z0.b, p2/m, z0.b
-+[^:]+: 0417bc00 neg z0.b, p7/m, z0.b
-+[^:]+: 0417bc00 neg z0.b, p7/m, z0.b
-+[^:]+: 0417a060 neg z0.b, p0/m, z3.b
-+[^:]+: 0417a060 neg z0.b, p0/m, z3.b
-+[^:]+: 0417a3e0 neg z0.b, p0/m, z31.b
-+[^:]+: 0417a3e0 neg z0.b, p0/m, z31.b
-+[^:]+: 0457a000 neg z0.h, p0/m, z0.h
-+[^:]+: 0457a000 neg z0.h, p0/m, z0.h
-+[^:]+: 0457a001 neg z1.h, p0/m, z0.h
-+[^:]+: 0457a001 neg z1.h, p0/m, z0.h
-+[^:]+: 0457a01f neg z31.h, p0/m, z0.h
-+[^:]+: 0457a01f neg z31.h, p0/m, z0.h
-+[^:]+: 0457a800 neg z0.h, p2/m, z0.h
-+[^:]+: 0457a800 neg z0.h, p2/m, z0.h
-+[^:]+: 0457bc00 neg z0.h, p7/m, z0.h
-+[^:]+: 0457bc00 neg z0.h, p7/m, z0.h
-+[^:]+: 0457a060 neg z0.h, p0/m, z3.h
-+[^:]+: 0457a060 neg z0.h, p0/m, z3.h
-+[^:]+: 0457a3e0 neg z0.h, p0/m, z31.h
-+[^:]+: 0457a3e0 neg z0.h, p0/m, z31.h
-+[^:]+: 0497a000 neg z0.s, p0/m, z0.s
-+[^:]+: 0497a000 neg z0.s, p0/m, z0.s
-+[^:]+: 0497a001 neg z1.s, p0/m, z0.s
-+[^:]+: 0497a001 neg z1.s, p0/m, z0.s
-+[^:]+: 0497a01f neg z31.s, p0/m, z0.s
-+[^:]+: 0497a01f neg z31.s, p0/m, z0.s
-+[^:]+: 0497a800 neg z0.s, p2/m, z0.s
-+[^:]+: 0497a800 neg z0.s, p2/m, z0.s
-+[^:]+: 0497bc00 neg z0.s, p7/m, z0.s
-+[^:]+: 0497bc00 neg z0.s, p7/m, z0.s
-+[^:]+: 0497a060 neg z0.s, p0/m, z3.s
-+[^:]+: 0497a060 neg z0.s, p0/m, z3.s
-+[^:]+: 0497a3e0 neg z0.s, p0/m, z31.s
-+[^:]+: 0497a3e0 neg z0.s, p0/m, z31.s
-+[^:]+: 04d7a000 neg z0.d, p0/m, z0.d
-+[^:]+: 04d7a000 neg z0.d, p0/m, z0.d
-+[^:]+: 04d7a001 neg z1.d, p0/m, z0.d
-+[^:]+: 04d7a001 neg z1.d, p0/m, z0.d
-+[^:]+: 04d7a01f neg z31.d, p0/m, z0.d
-+[^:]+: 04d7a01f neg z31.d, p0/m, z0.d
-+[^:]+: 04d7a800 neg z0.d, p2/m, z0.d
-+[^:]+: 04d7a800 neg z0.d, p2/m, z0.d
-+[^:]+: 04d7bc00 neg z0.d, p7/m, z0.d
-+[^:]+: 04d7bc00 neg z0.d, p7/m, z0.d
-+[^:]+: 04d7a060 neg z0.d, p0/m, z3.d
-+[^:]+: 04d7a060 neg z0.d, p0/m, z3.d
-+[^:]+: 04d7a3e0 neg z0.d, p0/m, z31.d
-+[^:]+: 04d7a3e0 neg z0.d, p0/m, z31.d
-+[^:]+: 25804200 nor p0.b, p0/z, p0.b, p0.b
-+[^:]+: 25804200 nor p0.b, p0/z, p0.b, p0.b
-+[^:]+: 25804201 nor p1.b, p0/z, p0.b, p0.b
-+[^:]+: 25804201 nor p1.b, p0/z, p0.b, p0.b
-+[^:]+: 2580420f nor p15.b, p0/z, p0.b, p0.b
-+[^:]+: 2580420f nor p15.b, p0/z, p0.b, p0.b
-+[^:]+: 25804a00 nor p0.b, p2/z, p0.b, p0.b
-+[^:]+: 25804a00 nor p0.b, p2/z, p0.b, p0.b
-+[^:]+: 25807e00 nor p0.b, p15/z, p0.b, p0.b
-+[^:]+: 25807e00 nor p0.b, p15/z, p0.b, p0.b
-+[^:]+: 25804260 nor p0.b, p0/z, p3.b, p0.b
-+[^:]+: 25804260 nor p0.b, p0/z, p3.b, p0.b
-+[^:]+: 258043e0 nor p0.b, p0/z, p15.b, p0.b
-+[^:]+: 258043e0 nor p0.b, p0/z, p15.b, p0.b
-+[^:]+: 25844200 nor p0.b, p0/z, p0.b, p4.b
-+[^:]+: 25844200 nor p0.b, p0/z, p0.b, p4.b
-+[^:]+: 258f4200 nor p0.b, p0/z, p0.b, p15.b
-+[^:]+: 258f4200 nor p0.b, p0/z, p0.b, p15.b
-+[^:]+: 25c04200 nors p0.b, p0/z, p0.b, p0.b
-+[^:]+: 25c04200 nors p0.b, p0/z, p0.b, p0.b
-+[^:]+: 25c04201 nors p1.b, p0/z, p0.b, p0.b
-+[^:]+: 25c04201 nors p1.b, p0/z, p0.b, p0.b
-+[^:]+: 25c0420f nors p15.b, p0/z, p0.b, p0.b
-+[^:]+: 25c0420f nors p15.b, p0/z, p0.b, p0.b
-+[^:]+: 25c04a00 nors p0.b, p2/z, p0.b, p0.b
-+[^:]+: 25c04a00 nors p0.b, p2/z, p0.b, p0.b
-+[^:]+: 25c07e00 nors p0.b, p15/z, p0.b, p0.b
-+[^:]+: 25c07e00 nors p0.b, p15/z, p0.b, p0.b
-+[^:]+: 25c04260 nors p0.b, p0/z, p3.b, p0.b
-+[^:]+: 25c04260 nors p0.b, p0/z, p3.b, p0.b
-+[^:]+: 25c043e0 nors p0.b, p0/z, p15.b, p0.b
-+[^:]+: 25c043e0 nors p0.b, p0/z, p15.b, p0.b
-+[^:]+: 25c44200 nors p0.b, p0/z, p0.b, p4.b
-+[^:]+: 25c44200 nors p0.b, p0/z, p0.b, p4.b
-+[^:]+: 25cf4200 nors p0.b, p0/z, p0.b, p15.b
-+[^:]+: 25cf4200 nors p0.b, p0/z, p0.b, p15.b
-+[^:]+: 041ea000 not z0.b, p0/m, z0.b
-+[^:]+: 041ea000 not z0.b, p0/m, z0.b
-+[^:]+: 041ea001 not z1.b, p0/m, z0.b
-+[^:]+: 041ea001 not z1.b, p0/m, z0.b
-+[^:]+: 041ea01f not z31.b, p0/m, z0.b
-+[^:]+: 041ea01f not z31.b, p0/m, z0.b
-+[^:]+: 041ea800 not z0.b, p2/m, z0.b
-+[^:]+: 041ea800 not z0.b, p2/m, z0.b
-+[^:]+: 041ebc00 not z0.b, p7/m, z0.b
-+[^:]+: 041ebc00 not z0.b, p7/m, z0.b
-+[^:]+: 041ea060 not z0.b, p0/m, z3.b
-+[^:]+: 041ea060 not z0.b, p0/m, z3.b
-+[^:]+: 041ea3e0 not z0.b, p0/m, z31.b
-+[^:]+: 041ea3e0 not z0.b, p0/m, z31.b
-+[^:]+: 045ea000 not z0.h, p0/m, z0.h
-+[^:]+: 045ea000 not z0.h, p0/m, z0.h
-+[^:]+: 045ea001 not z1.h, p0/m, z0.h
-+[^:]+: 045ea001 not z1.h, p0/m, z0.h
-+[^:]+: 045ea01f not z31.h, p0/m, z0.h
-+[^:]+: 045ea01f not z31.h, p0/m, z0.h
-+[^:]+: 045ea800 not z0.h, p2/m, z0.h
-+[^:]+: 045ea800 not z0.h, p2/m, z0.h
-+[^:]+: 045ebc00 not z0.h, p7/m, z0.h
-+[^:]+: 045ebc00 not z0.h, p7/m, z0.h
-+[^:]+: 045ea060 not z0.h, p0/m, z3.h
-+[^:]+: 045ea060 not z0.h, p0/m, z3.h
-+[^:]+: 045ea3e0 not z0.h, p0/m, z31.h
-+[^:]+: 045ea3e0 not z0.h, p0/m, z31.h
-+[^:]+: 049ea000 not z0.s, p0/m, z0.s
-+[^:]+: 049ea000 not z0.s, p0/m, z0.s
-+[^:]+: 049ea001 not z1.s, p0/m, z0.s
-+[^:]+: 049ea001 not z1.s, p0/m, z0.s
-+[^:]+: 049ea01f not z31.s, p0/m, z0.s
-+[^:]+: 049ea01f not z31.s, p0/m, z0.s
-+[^:]+: 049ea800 not z0.s, p2/m, z0.s
-+[^:]+: 049ea800 not z0.s, p2/m, z0.s
-+[^:]+: 049ebc00 not z0.s, p7/m, z0.s
-+[^:]+: 049ebc00 not z0.s, p7/m, z0.s
-+[^:]+: 049ea060 not z0.s, p0/m, z3.s
-+[^:]+: 049ea060 not z0.s, p0/m, z3.s
-+[^:]+: 049ea3e0 not z0.s, p0/m, z31.s
-+[^:]+: 049ea3e0 not z0.s, p0/m, z31.s
-+[^:]+: 04dea000 not z0.d, p0/m, z0.d
-+[^:]+: 04dea000 not z0.d, p0/m, z0.d
-+[^:]+: 04dea001 not z1.d, p0/m, z0.d
-+[^:]+: 04dea001 not z1.d, p0/m, z0.d
-+[^:]+: 04dea01f not z31.d, p0/m, z0.d
-+[^:]+: 04dea01f not z31.d, p0/m, z0.d
-+[^:]+: 04dea800 not z0.d, p2/m, z0.d
-+[^:]+: 04dea800 not z0.d, p2/m, z0.d
-+[^:]+: 04debc00 not z0.d, p7/m, z0.d
-+[^:]+: 04debc00 not z0.d, p7/m, z0.d
-+[^:]+: 04dea060 not z0.d, p0/m, z3.d
-+[^:]+: 04dea060 not z0.d, p0/m, z3.d
-+[^:]+: 04dea3e0 not z0.d, p0/m, z31.d
-+[^:]+: 04dea3e0 not z0.d, p0/m, z31.d
-+[^:]+: 25804010 orn p0.b, p0/z, p0.b, p0.b
-+[^:]+: 25804010 orn p0.b, p0/z, p0.b, p0.b
-+[^:]+: 25804011 orn p1.b, p0/z, p0.b, p0.b
-+[^:]+: 25804011 orn p1.b, p0/z, p0.b, p0.b
-+[^:]+: 2580401f orn p15.b, p0/z, p0.b, p0.b
-+[^:]+: 2580401f orn p15.b, p0/z, p0.b, p0.b
-+[^:]+: 25804810 orn p0.b, p2/z, p0.b, p0.b
-+[^:]+: 25804810 orn p0.b, p2/z, p0.b, p0.b
-+[^:]+: 25807c10 orn p0.b, p15/z, p0.b, p0.b
-+[^:]+: 25807c10 orn p0.b, p15/z, p0.b, p0.b
-+[^:]+: 25804070 orn p0.b, p0/z, p3.b, p0.b
-+[^:]+: 25804070 orn p0.b, p0/z, p3.b, p0.b
-+[^:]+: 258041f0 orn p0.b, p0/z, p15.b, p0.b
-+[^:]+: 258041f0 orn p0.b, p0/z, p15.b, p0.b
-+[^:]+: 25844010 orn p0.b, p0/z, p0.b, p4.b
-+[^:]+: 25844010 orn p0.b, p0/z, p0.b, p4.b
-+[^:]+: 258f4010 orn p0.b, p0/z, p0.b, p15.b
-+[^:]+: 258f4010 orn p0.b, p0/z, p0.b, p15.b
-+[^:]+: 25c04010 orns p0.b, p0/z, p0.b, p0.b
-+[^:]+: 25c04010 orns p0.b, p0/z, p0.b, p0.b
-+[^:]+: 25c04011 orns p1.b, p0/z, p0.b, p0.b
-+[^:]+: 25c04011 orns p1.b, p0/z, p0.b, p0.b
-+[^:]+: 25c0401f orns p15.b, p0/z, p0.b, p0.b
-+[^:]+: 25c0401f orns p15.b, p0/z, p0.b, p0.b
-+[^:]+: 25c04810 orns p0.b, p2/z, p0.b, p0.b
-+[^:]+: 25c04810 orns p0.b, p2/z, p0.b, p0.b
-+[^:]+: 25c07c10 orns p0.b, p15/z, p0.b, p0.b
-+[^:]+: 25c07c10 orns p0.b, p15/z, p0.b, p0.b
-+[^:]+: 25c04070 orns p0.b, p0/z, p3.b, p0.b
-+[^:]+: 25c04070 orns p0.b, p0/z, p3.b, p0.b
-+[^:]+: 25c041f0 orns p0.b, p0/z, p15.b, p0.b
-+[^:]+: 25c041f0 orns p0.b, p0/z, p15.b, p0.b
-+[^:]+: 25c44010 orns p0.b, p0/z, p0.b, p4.b
-+[^:]+: 25c44010 orns p0.b, p0/z, p0.b, p4.b
-+[^:]+: 25cf4010 orns p0.b, p0/z, p0.b, p15.b
-+[^:]+: 25cf4010 orns p0.b, p0/z, p0.b, p15.b
-+[^:]+: 04603000 mov z0.d, z0.d
-+[^:]+: 04603000 mov z0.d, z0.d
-+[^:]+: 04603001 mov z1.d, z0.d
-+[^:]+: 04603001 mov z1.d, z0.d
-+[^:]+: 0460301f mov z31.d, z0.d
-+[^:]+: 0460301f mov z31.d, z0.d
-+[^:]+: 04603040 orr z0.d, z2.d, z0.d
-+[^:]+: 04603040 orr z0.d, z2.d, z0.d
-+[^:]+: 046033e0 orr z0.d, z31.d, z0.d
-+[^:]+: 046033e0 orr z0.d, z31.d, z0.d
-+[^:]+: 04633000 orr z0.d, z0.d, z3.d
-+[^:]+: 04633000 orr z0.d, z0.d, z3.d
-+[^:]+: 047f3000 orr z0.d, z0.d, z31.d
-+[^:]+: 047f3000 orr z0.d, z0.d, z31.d
-+[^:]+: 05000000 orr z0.s, z0.s, #0x1
-+[^:]+: 05000000 orr z0.s, z0.s, #0x1
-+[^:]+: 05000000 orr z0.s, z0.s, #0x1
-+[^:]+: 05000001 orr z1.s, z1.s, #0x1
-+[^:]+: 05000001 orr z1.s, z1.s, #0x1
-+[^:]+: 05000001 orr z1.s, z1.s, #0x1
-+[^:]+: 0500001f orr z31.s, z31.s, #0x1
-+[^:]+: 0500001f orr z31.s, z31.s, #0x1
-+[^:]+: 0500001f orr z31.s, z31.s, #0x1
-+[^:]+: 05000002 orr z2.s, z2.s, #0x1
-+[^:]+: 05000002 orr z2.s, z2.s, #0x1
-+[^:]+: 05000002 orr z2.s, z2.s, #0x1
-+[^:]+: 050000c0 orr z0.s, z0.s, #0x7f
-+[^:]+: 050000c0 orr z0.s, z0.s, #0x7f
-+[^:]+: 050000c0 orr z0.s, z0.s, #0x7f
-+[^:]+: 050003c0 orr z0.s, z0.s, #0x7fffffff
-+[^:]+: 050003c0 orr z0.s, z0.s, #0x7fffffff
-+[^:]+: 050003c0 orr z0.s, z0.s, #0x7fffffff
-+[^:]+: 05000400 orr z0.h, z0.h, #0x1
-+[^:]+: 05000400 orr z0.h, z0.h, #0x1
-+[^:]+: 05000400 orr z0.h, z0.h, #0x1
-+[^:]+: 05000400 orr z0.h, z0.h, #0x1
-+[^:]+: 050005c0 orr z0.h, z0.h, #0x7fff
-+[^:]+: 050005c0 orr z0.h, z0.h, #0x7fff
-+[^:]+: 050005c0 orr z0.h, z0.h, #0x7fff
-+[^:]+: 050005c0 orr z0.h, z0.h, #0x7fff
-+[^:]+: 05000600 orr z0.b, z0.b, #0x1
-+[^:]+: 05000600 orr z0.b, z0.b, #0x1
-+[^:]+: 05000600 orr z0.b, z0.b, #0x1
-+[^:]+: 05000600 orr z0.b, z0.b, #0x1
-+[^:]+: 05000600 orr z0.b, z0.b, #0x1
-+[^:]+: 05000780 orr z0.b, z0.b, #0x55
-+[^:]+: 05000780 orr z0.b, z0.b, #0x55
-+[^:]+: 05000780 orr z0.b, z0.b, #0x55
-+[^:]+: 05000780 orr z0.b, z0.b, #0x55
-+[^:]+: 05000780 orr z0.b, z0.b, #0x55
-+[^:]+: 05000800 orr z0.s, z0.s, #0x80000000
-+[^:]+: 05000800 orr z0.s, z0.s, #0x80000000
-+[^:]+: 05000800 orr z0.s, z0.s, #0x80000000
-+[^:]+: 05000bc0 orr z0.s, z0.s, #0xbfffffff
-+[^:]+: 05000bc0 orr z0.s, z0.s, #0xbfffffff
-+[^:]+: 05000bc0 orr z0.s, z0.s, #0xbfffffff
-+[^:]+: 05000c00 orr z0.h, z0.h, #0x8000
-+[^:]+: 05000c00 orr z0.h, z0.h, #0x8000
-+[^:]+: 05000c00 orr z0.h, z0.h, #0x8000
-+[^:]+: 05000c00 orr z0.h, z0.h, #0x8000
-+[^:]+: 050+ec0 orr z0.b, z0.b, #0xbf
-+[^:]+: 050+ec0 orr z0.b, z0.b, #0xbf
-+[^:]+: 050+ec0 orr z0.b, z0.b, #0xbf
-+[^:]+: 050+ec0 orr z0.b, z0.b, #0xbf
-+[^:]+: 050+ec0 orr z0.b, z0.b, #0xbf
-+[^:]+: 05001e80 orr z0.b, z0.b, #0xe3
-+[^:]+: 05001e80 orr z0.b, z0.b, #0xe3
-+[^:]+: 05001e80 orr z0.b, z0.b, #0xe3
-+[^:]+: 05001e80 orr z0.b, z0.b, #0xe3
-+[^:]+: 05001e80 orr z0.b, z0.b, #0xe3
-+[^:]+: 0500bbc0 orr z0.s, z0.s, #0xfffffeff
-+[^:]+: 0500bbc0 orr z0.s, z0.s, #0xfffffeff
-+[^:]+: 0500bbc0 orr z0.s, z0.s, #0xfffffeff
-+[^:]+: 0503ffc0 orr z0.d, z0.d, #0xfffffffffffffffe
-+[^:]+: 0503ffc0 orr z0.d, z0.d, #0xfffffffffffffffe
-+[^:]+: 04180000 orr z0.b, p0/m, z0.b, z0.b
-+[^:]+: 04180000 orr z0.b, p0/m, z0.b, z0.b
-+[^:]+: 04180001 orr z1.b, p0/m, z1.b, z0.b
-+[^:]+: 04180001 orr z1.b, p0/m, z1.b, z0.b
-+[^:]+: 0418001f orr z31.b, p0/m, z31.b, z0.b
-+[^:]+: 0418001f orr z31.b, p0/m, z31.b, z0.b
-+[^:]+: 04180800 orr z0.b, p2/m, z0.b, z0.b
-+[^:]+: 04180800 orr z0.b, p2/m, z0.b, z0.b
-+[^:]+: 04181c00 orr z0.b, p7/m, z0.b, z0.b
-+[^:]+: 04181c00 orr z0.b, p7/m, z0.b, z0.b
-+[^:]+: 04180003 orr z3.b, p0/m, z3.b, z0.b
-+[^:]+: 04180003 orr z3.b, p0/m, z3.b, z0.b
-+[^:]+: 04180080 orr z0.b, p0/m, z0.b, z4.b
-+[^:]+: 04180080 orr z0.b, p0/m, z0.b, z4.b
-+[^:]+: 041803e0 orr z0.b, p0/m, z0.b, z31.b
-+[^:]+: 041803e0 orr z0.b, p0/m, z0.b, z31.b
-+[^:]+: 04580000 orr z0.h, p0/m, z0.h, z0.h
-+[^:]+: 04580000 orr z0.h, p0/m, z0.h, z0.h
-+[^:]+: 04580001 orr z1.h, p0/m, z1.h, z0.h
-+[^:]+: 04580001 orr z1.h, p0/m, z1.h, z0.h
-+[^:]+: 0458001f orr z31.h, p0/m, z31.h, z0.h
-+[^:]+: 0458001f orr z31.h, p0/m, z31.h, z0.h
-+[^:]+: 04580800 orr z0.h, p2/m, z0.h, z0.h
-+[^:]+: 04580800 orr z0.h, p2/m, z0.h, z0.h
-+[^:]+: 04581c00 orr z0.h, p7/m, z0.h, z0.h
-+[^:]+: 04581c00 orr z0.h, p7/m, z0.h, z0.h
-+[^:]+: 04580003 orr z3.h, p0/m, z3.h, z0.h
-+[^:]+: 04580003 orr z3.h, p0/m, z3.h, z0.h
-+[^:]+: 04580080 orr z0.h, p0/m, z0.h, z4.h
-+[^:]+: 04580080 orr z0.h, p0/m, z0.h, z4.h
-+[^:]+: 045803e0 orr z0.h, p0/m, z0.h, z31.h
-+[^:]+: 045803e0 orr z0.h, p0/m, z0.h, z31.h
-+[^:]+: 04980000 orr z0.s, p0/m, z0.s, z0.s
-+[^:]+: 04980000 orr z0.s, p0/m, z0.s, z0.s
-+[^:]+: 04980001 orr z1.s, p0/m, z1.s, z0.s
-+[^:]+: 04980001 orr z1.s, p0/m, z1.s, z0.s
-+[^:]+: 0498001f orr z31.s, p0/m, z31.s, z0.s
-+[^:]+: 0498001f orr z31.s, p0/m, z31.s, z0.s
-+[^:]+: 04980800 orr z0.s, p2/m, z0.s, z0.s
-+[^:]+: 04980800 orr z0.s, p2/m, z0.s, z0.s
-+[^:]+: 04981c00 orr z0.s, p7/m, z0.s, z0.s
-+[^:]+: 04981c00 orr z0.s, p7/m, z0.s, z0.s
-+[^:]+: 04980003 orr z3.s, p0/m, z3.s, z0.s
-+[^:]+: 04980003 orr z3.s, p0/m, z3.s, z0.s
-+[^:]+: 04980080 orr z0.s, p0/m, z0.s, z4.s
-+[^:]+: 04980080 orr z0.s, p0/m, z0.s, z4.s
-+[^:]+: 049803e0 orr z0.s, p0/m, z0.s, z31.s
-+[^:]+: 049803e0 orr z0.s, p0/m, z0.s, z31.s
-+[^:]+: 04d80000 orr z0.d, p0/m, z0.d, z0.d
-+[^:]+: 04d80000 orr z0.d, p0/m, z0.d, z0.d
-+[^:]+: 04d80001 orr z1.d, p0/m, z1.d, z0.d
-+[^:]+: 04d80001 orr z1.d, p0/m, z1.d, z0.d
-+[^:]+: 04d8001f orr z31.d, p0/m, z31.d, z0.d
-+[^:]+: 04d8001f orr z31.d, p0/m, z31.d, z0.d
-+[^:]+: 04d80800 orr z0.d, p2/m, z0.d, z0.d
-+[^:]+: 04d80800 orr z0.d, p2/m, z0.d, z0.d
-+[^:]+: 04d81c00 orr z0.d, p7/m, z0.d, z0.d
-+[^:]+: 04d81c00 orr z0.d, p7/m, z0.d, z0.d
-+[^:]+: 04d80003 orr z3.d, p0/m, z3.d, z0.d
-+[^:]+: 04d80003 orr z3.d, p0/m, z3.d, z0.d
-+[^:]+: 04d80080 orr z0.d, p0/m, z0.d, z4.d
-+[^:]+: 04d80080 orr z0.d, p0/m, z0.d, z4.d
-+[^:]+: 04d803e0 orr z0.d, p0/m, z0.d, z31.d
-+[^:]+: 04d803e0 orr z0.d, p0/m, z0.d, z31.d
-+[^:]+: 25804000 mov p0.b, p0.b
-+[^:]+: 25804000 mov p0.b, p0.b
-+[^:]+: 25804001 mov p1.b, p0.b
-+[^:]+: 25804001 mov p1.b, p0.b
-+[^:]+: 2580400f mov p15.b, p0.b
-+[^:]+: 2580400f mov p15.b, p0.b
-+[^:]+: 25804800 orr p0.b, p2/z, p0.b, p0.b
-+[^:]+: 25804800 orr p0.b, p2/z, p0.b, p0.b
-+[^:]+: 25807c00 orr p0.b, p15/z, p0.b, p0.b
-+[^:]+: 25807c00 orr p0.b, p15/z, p0.b, p0.b
-+[^:]+: 25804060 orr p0.b, p0/z, p3.b, p0.b
-+[^:]+: 25804060 orr p0.b, p0/z, p3.b, p0.b
-+[^:]+: 258041e0 orr p0.b, p0/z, p15.b, p0.b
-+[^:]+: 258041e0 orr p0.b, p0/z, p15.b, p0.b
-+[^:]+: 25844000 orr p0.b, p0/z, p0.b, p4.b
-+[^:]+: 25844000 orr p0.b, p0/z, p0.b, p4.b
-+[^:]+: 258f4000 orr p0.b, p0/z, p0.b, p15.b
-+[^:]+: 258f4000 orr p0.b, p0/z, p0.b, p15.b
-+[^:]+: 25c04000 movs p0.b, p0.b
-+[^:]+: 25c04000 movs p0.b, p0.b
-+[^:]+: 25c04001 movs p1.b, p0.b
-+[^:]+: 25c04001 movs p1.b, p0.b
-+[^:]+: 25c0400f movs p15.b, p0.b
-+[^:]+: 25c0400f movs p15.b, p0.b
-+[^:]+: 25c04800 orrs p0.b, p2/z, p0.b, p0.b
-+[^:]+: 25c04800 orrs p0.b, p2/z, p0.b, p0.b
-+[^:]+: 25c07c00 orrs p0.b, p15/z, p0.b, p0.b
-+[^:]+: 25c07c00 orrs p0.b, p15/z, p0.b, p0.b
-+[^:]+: 25c04060 orrs p0.b, p0/z, p3.b, p0.b
-+[^:]+: 25c04060 orrs p0.b, p0/z, p3.b, p0.b
-+[^:]+: 25c041e0 orrs p0.b, p0/z, p15.b, p0.b
-+[^:]+: 25c041e0 orrs p0.b, p0/z, p15.b, p0.b
-+[^:]+: 25c44000 orrs p0.b, p0/z, p0.b, p4.b
-+[^:]+: 25c44000 orrs p0.b, p0/z, p0.b, p4.b
-+[^:]+: 25cf4000 orrs p0.b, p0/z, p0.b, p15.b
-+[^:]+: 25cf4000 orrs p0.b, p0/z, p0.b, p15.b
-+[^:]+: 04182000 orv b0, p0, z0.b
-+[^:]+: 04182000 orv b0, p0, z0.b
-+[^:]+: 04182001 orv b1, p0, z0.b
-+[^:]+: 04182001 orv b1, p0, z0.b
-+[^:]+: 0418201f orv b31, p0, z0.b
-+[^:]+: 0418201f orv b31, p0, z0.b
-+[^:]+: 04182800 orv b0, p2, z0.b
-+[^:]+: 04182800 orv b0, p2, z0.b
-+[^:]+: 04183c00 orv b0, p7, z0.b
-+[^:]+: 04183c00 orv b0, p7, z0.b
-+[^:]+: 04182060 orv b0, p0, z3.b
-+[^:]+: 04182060 orv b0, p0, z3.b
-+[^:]+: 041823e0 orv b0, p0, z31.b
-+[^:]+: 041823e0 orv b0, p0, z31.b
-+[^:]+: 04582000 orv h0, p0, z0.h
-+[^:]+: 04582000 orv h0, p0, z0.h
-+[^:]+: 04582001 orv h1, p0, z0.h
-+[^:]+: 04582001 orv h1, p0, z0.h
-+[^:]+: 0458201f orv h31, p0, z0.h
-+[^:]+: 0458201f orv h31, p0, z0.h
-+[^:]+: 04582800 orv h0, p2, z0.h
-+[^:]+: 04582800 orv h0, p2, z0.h
-+[^:]+: 04583c00 orv h0, p7, z0.h
-+[^:]+: 04583c00 orv h0, p7, z0.h
-+[^:]+: 04582060 orv h0, p0, z3.h
-+[^:]+: 04582060 orv h0, p0, z3.h
-+[^:]+: 045823e0 orv h0, p0, z31.h
-+[^:]+: 045823e0 orv h0, p0, z31.h
-+[^:]+: 04982000 orv s0, p0, z0.s
-+[^:]+: 04982000 orv s0, p0, z0.s
-+[^:]+: 04982001 orv s1, p0, z0.s
-+[^:]+: 04982001 orv s1, p0, z0.s
-+[^:]+: 0498201f orv s31, p0, z0.s
-+[^:]+: 0498201f orv s31, p0, z0.s
-+[^:]+: 04982800 orv s0, p2, z0.s
-+[^:]+: 04982800 orv s0, p2, z0.s
-+[^:]+: 04983c00 orv s0, p7, z0.s
-+[^:]+: 04983c00 orv s0, p7, z0.s
-+[^:]+: 04982060 orv s0, p0, z3.s
-+[^:]+: 04982060 orv s0, p0, z3.s
-+[^:]+: 049823e0 orv s0, p0, z31.s
-+[^:]+: 049823e0 orv s0, p0, z31.s
-+[^:]+: 04d82000 orv d0, p0, z0.d
-+[^:]+: 04d82000 orv d0, p0, z0.d
-+[^:]+: 04d82001 orv d1, p0, z0.d
-+[^:]+: 04d82001 orv d1, p0, z0.d
-+[^:]+: 04d8201f orv d31, p0, z0.d
-+[^:]+: 04d8201f orv d31, p0, z0.d
-+[^:]+: 04d82800 orv d0, p2, z0.d
-+[^:]+: 04d82800 orv d0, p2, z0.d
-+[^:]+: 04d83c00 orv d0, p7, z0.d
-+[^:]+: 04d83c00 orv d0, p7, z0.d
-+[^:]+: 04d82060 orv d0, p0, z3.d
-+[^:]+: 04d82060 orv d0, p0, z3.d
-+[^:]+: 04d823e0 orv d0, p0, z31.d
-+[^:]+: 04d823e0 orv d0, p0, z31.d
-+[^:]+: 2518e400 pfalse p0.b
-+[^:]+: 2518e400 pfalse p0.b
-+[^:]+: 2518e401 pfalse p1.b
-+[^:]+: 2518e401 pfalse p1.b
-+[^:]+: 2518e40f pfalse p15.b
-+[^:]+: 2518e40f pfalse p15.b
-+[^:]+: 2558c000 pfirst p0.b, p0, p0.b
-+[^:]+: 2558c000 pfirst p0.b, p0, p0.b
-+[^:]+: 2558c001 pfirst p1.b, p0, p1.b
-+[^:]+: 2558c001 pfirst p1.b, p0, p1.b
-+[^:]+: 2558c00f pfirst p15.b, p0, p15.b
-+[^:]+: 2558c00f pfirst p15.b, p0, p15.b
-+[^:]+: 2558c040 pfirst p0.b, p2, p0.b
-+[^:]+: 2558c040 pfirst p0.b, p2, p0.b
-+[^:]+: 2558c1e0 pfirst p0.b, p15, p0.b
-+[^:]+: 2558c1e0 pfirst p0.b, p15, p0.b
-+[^:]+: 2558c003 pfirst p3.b, p0, p3.b
-+[^:]+: 2558c003 pfirst p3.b, p0, p3.b
-+[^:]+: 2519c400 pnext p0.b, p0, p0.b
-+[^:]+: 2519c400 pnext p0.b, p0, p0.b
-+[^:]+: 2519c401 pnext p1.b, p0, p1.b
-+[^:]+: 2519c401 pnext p1.b, p0, p1.b
-+[^:]+: 2519c40f pnext p15.b, p0, p15.b
-+[^:]+: 2519c40f pnext p15.b, p0, p15.b
-+[^:]+: 2519c440 pnext p0.b, p2, p0.b
-+[^:]+: 2519c440 pnext p0.b, p2, p0.b
-+[^:]+: 2519c5e0 pnext p0.b, p15, p0.b
-+[^:]+: 2519c5e0 pnext p0.b, p15, p0.b
-+[^:]+: 2519c403 pnext p3.b, p0, p3.b
-+[^:]+: 2519c403 pnext p3.b, p0, p3.b
-+[^:]+: 2559c400 pnext p0.h, p0, p0.h
-+[^:]+: 2559c400 pnext p0.h, p0, p0.h
-+[^:]+: 2559c401 pnext p1.h, p0, p1.h
-+[^:]+: 2559c401 pnext p1.h, p0, p1.h
-+[^:]+: 2559c40f pnext p15.h, p0, p15.h
-+[^:]+: 2559c40f pnext p15.h, p0, p15.h
-+[^:]+: 2559c440 pnext p0.h, p2, p0.h
-+[^:]+: 2559c440 pnext p0.h, p2, p0.h
-+[^:]+: 2559c5e0 pnext p0.h, p15, p0.h
-+[^:]+: 2559c5e0 pnext p0.h, p15, p0.h
-+[^:]+: 2559c403 pnext p3.h, p0, p3.h
-+[^:]+: 2559c403 pnext p3.h, p0, p3.h
-+[^:]+: 2599c400 pnext p0.s, p0, p0.s
-+[^:]+: 2599c400 pnext p0.s, p0, p0.s
-+[^:]+: 2599c401 pnext p1.s, p0, p1.s
-+[^:]+: 2599c401 pnext p1.s, p0, p1.s
-+[^:]+: 2599c40f pnext p15.s, p0, p15.s
-+[^:]+: 2599c40f pnext p15.s, p0, p15.s
-+[^:]+: 2599c440 pnext p0.s, p2, p0.s
-+[^:]+: 2599c440 pnext p0.s, p2, p0.s
-+[^:]+: 2599c5e0 pnext p0.s, p15, p0.s
-+[^:]+: 2599c5e0 pnext p0.s, p15, p0.s
-+[^:]+: 2599c403 pnext p3.s, p0, p3.s
-+[^:]+: 2599c403 pnext p3.s, p0, p3.s
-+[^:]+: 25d9c400 pnext p0.d, p0, p0.d
-+[^:]+: 25d9c400 pnext p0.d, p0, p0.d
-+[^:]+: 25d9c401 pnext p1.d, p0, p1.d
-+[^:]+: 25d9c401 pnext p1.d, p0, p1.d
-+[^:]+: 25d9c40f pnext p15.d, p0, p15.d
-+[^:]+: 25d9c40f pnext p15.d, p0, p15.d
-+[^:]+: 25d9c440 pnext p0.d, p2, p0.d
-+[^:]+: 25d9c440 pnext p0.d, p2, p0.d
-+[^:]+: 25d9c5e0 pnext p0.d, p15, p0.d
-+[^:]+: 25d9c5e0 pnext p0.d, p15, p0.d
-+[^:]+: 25d9c403 pnext p3.d, p0, p3.d
-+[^:]+: 25d9c403 pnext p3.d, p0, p3.d
-+[^:]+: 8400c000 prfb pldl1keep, p0, \[x0, x0\]
-+[^:]+: 8400c000 prfb pldl1keep, p0, \[x0, x0\]
-+[^:]+: 8400c000 prfb pldl1keep, p0, \[x0, x0\]
-+[^:]+: 8400c001 prfb pldl1strm, p0, \[x0, x0\]
-+[^:]+: 8400c001 prfb pldl1strm, p0, \[x0, x0\]
-+[^:]+: 8400c001 prfb pldl1strm, p0, \[x0, x0\]
-+[^:]+: 8400c002 prfb pldl2keep, p0, \[x0, x0\]
-+[^:]+: 8400c002 prfb pldl2keep, p0, \[x0, x0\]
-+[^:]+: 8400c002 prfb pldl2keep, p0, \[x0, x0\]
-+[^:]+: 8400c003 prfb pldl2strm, p0, \[x0, x0\]
-+[^:]+: 8400c003 prfb pldl2strm, p0, \[x0, x0\]
-+[^:]+: 8400c003 prfb pldl2strm, p0, \[x0, x0\]
-+[^:]+: 8400c004 prfb pldl3keep, p0, \[x0, x0\]
-+[^:]+: 8400c004 prfb pldl3keep, p0, \[x0, x0\]
-+[^:]+: 8400c004 prfb pldl3keep, p0, \[x0, x0\]
-+[^:]+: 8400c005 prfb pldl3strm, p0, \[x0, x0\]
-+[^:]+: 8400c005 prfb pldl3strm, p0, \[x0, x0\]
-+[^:]+: 8400c005 prfb pldl3strm, p0, \[x0, x0\]
-+[^:]+: 8400c006 prfb #6, p0, \[x0, x0\]
-+[^:]+: 8400c006 prfb #6, p0, \[x0, x0\]
-+[^:]+: 8400c006 prfb #6, p0, \[x0, x0\]
-+[^:]+: 8400c007 prfb #7, p0, \[x0, x0\]
-+[^:]+: 8400c007 prfb #7, p0, \[x0, x0\]
-+[^:]+: 8400c007 prfb #7, p0, \[x0, x0\]
-+[^:]+: 8400c008 prfb pstl1keep, p0, \[x0, x0\]
-+[^:]+: 8400c008 prfb pstl1keep, p0, \[x0, x0\]
-+[^:]+: 8400c008 prfb pstl1keep, p0, \[x0, x0\]
-+[^:]+: 8400c009 prfb pstl1strm, p0, \[x0, x0\]
-+[^:]+: 8400c009 prfb pstl1strm, p0, \[x0, x0\]
-+[^:]+: 8400c009 prfb pstl1strm, p0, \[x0, x0\]
-+[^:]+: 8400c00a prfb pstl2keep, p0, \[x0, x0\]
-+[^:]+: 8400c00a prfb pstl2keep, p0, \[x0, x0\]
-+[^:]+: 8400c00a prfb pstl2keep, p0, \[x0, x0\]
-+[^:]+: 8400c00b prfb pstl2strm, p0, \[x0, x0\]
-+[^:]+: 8400c00b prfb pstl2strm, p0, \[x0, x0\]
-+[^:]+: 8400c00b prfb pstl2strm, p0, \[x0, x0\]
-+[^:]+: 8400c00c prfb pstl3keep, p0, \[x0, x0\]
-+[^:]+: 8400c00c prfb pstl3keep, p0, \[x0, x0\]
-+[^:]+: 8400c00c prfb pstl3keep, p0, \[x0, x0\]
-+[^:]+: 8400c00d prfb pstl3strm, p0, \[x0, x0\]
-+[^:]+: 8400c00d prfb pstl3strm, p0, \[x0, x0\]
-+[^:]+: 8400c00d prfb pstl3strm, p0, \[x0, x0\]
-+[^:]+: 8400c0+e prfb #14, p0, \[x0, x0\]
-+[^:]+: 8400c0+e prfb #14, p0, \[x0, x0\]
-+[^:]+: 8400c0+e prfb #14, p0, \[x0, x0\]
-+[^:]+: 8400c00f prfb #15, p0, \[x0, x0\]
-+[^:]+: 8400c00f prfb #15, p0, \[x0, x0\]
-+[^:]+: 8400c00f prfb #15, p0, \[x0, x0\]
-+[^:]+: 8400c800 prfb pldl1keep, p2, \[x0, x0\]
-+[^:]+: 8400c800 prfb pldl1keep, p2, \[x0, x0\]
-+[^:]+: 8400c800 prfb pldl1keep, p2, \[x0, x0\]
-+[^:]+: 8400dc00 prfb pldl1keep, p7, \[x0, x0\]
-+[^:]+: 8400dc00 prfb pldl1keep, p7, \[x0, x0\]
-+[^:]+: 8400dc00 prfb pldl1keep, p7, \[x0, x0\]
-+[^:]+: 8400c060 prfb pldl1keep, p0, \[x3, x0\]
-+[^:]+: 8400c060 prfb pldl1keep, p0, \[x3, x0\]
-+[^:]+: 8400c060 prfb pldl1keep, p0, \[x3, x0\]
-+[^:]+: 8400c3e0 prfb pldl1keep, p0, \[sp, x0\]
-+[^:]+: 8400c3e0 prfb pldl1keep, p0, \[sp, x0\]
-+[^:]+: 8400c3e0 prfb pldl1keep, p0, \[sp, x0\]
-+[^:]+: 8404c000 prfb pldl1keep, p0, \[x0, x4\]
-+[^:]+: 8404c000 prfb pldl1keep, p0, \[x0, x4\]
-+[^:]+: 8404c000 prfb pldl1keep, p0, \[x0, x4\]
-+[^:]+: 841ec000 prfb pldl1keep, p0, \[x0, x30\]
-+[^:]+: 841ec000 prfb pldl1keep, p0, \[x0, x30\]
-+[^:]+: 841ec000 prfb pldl1keep, p0, \[x0, x30\]
-+[^:]+: 84200000 prfb pldl1keep, p0, \[x0, z0.s, uxtw\]
-+[^:]+: 84200000 prfb pldl1keep, p0, \[x0, z0.s, uxtw\]
-+[^:]+: 84200000 prfb pldl1keep, p0, \[x0, z0.s, uxtw\]
-+[^:]+: 84200001 prfb pldl1strm, p0, \[x0, z0.s, uxtw\]
-+[^:]+: 84200001 prfb pldl1strm, p0, \[x0, z0.s, uxtw\]
-+[^:]+: 84200001 prfb pldl1strm, p0, \[x0, z0.s, uxtw\]
-+[^:]+: 84200002 prfb pldl2keep, p0, \[x0, z0.s, uxtw\]
-+[^:]+: 84200002 prfb pldl2keep, p0, \[x0, z0.s, uxtw\]
-+[^:]+: 84200002 prfb pldl2keep, p0, \[x0, z0.s, uxtw\]
-+[^:]+: 84200003 prfb pldl2strm, p0, \[x0, z0.s, uxtw\]
-+[^:]+: 84200003 prfb pldl2strm, p0, \[x0, z0.s, uxtw\]
-+[^:]+: 84200003 prfb pldl2strm, p0, \[x0, z0.s, uxtw\]
-+[^:]+: 84200004 prfb pldl3keep, p0, \[x0, z0.s, uxtw\]
-+[^:]+: 84200004 prfb pldl3keep, p0, \[x0, z0.s, uxtw\]
-+[^:]+: 84200004 prfb pldl3keep, p0, \[x0, z0.s, uxtw\]
-+[^:]+: 84200005 prfb pldl3strm, p0, \[x0, z0.s, uxtw\]
-+[^:]+: 84200005 prfb pldl3strm, p0, \[x0, z0.s, uxtw\]
-+[^:]+: 84200005 prfb pldl3strm, p0, \[x0, z0.s, uxtw\]
-+[^:]+: 84200006 prfb #6, p0, \[x0, z0.s, uxtw\]
-+[^:]+: 84200006 prfb #6, p0, \[x0, z0.s, uxtw\]
-+[^:]+: 84200006 prfb #6, p0, \[x0, z0.s, uxtw\]
-+[^:]+: 84200007 prfb #7, p0, \[x0, z0.s, uxtw\]
-+[^:]+: 84200007 prfb #7, p0, \[x0, z0.s, uxtw\]
-+[^:]+: 84200007 prfb #7, p0, \[x0, z0.s, uxtw\]
-+[^:]+: 84200008 prfb pstl1keep, p0, \[x0, z0.s, uxtw\]
-+[^:]+: 84200008 prfb pstl1keep, p0, \[x0, z0.s, uxtw\]
-+[^:]+: 84200008 prfb pstl1keep, p0, \[x0, z0.s, uxtw\]
-+[^:]+: 84200009 prfb pstl1strm, p0, \[x0, z0.s, uxtw\]
-+[^:]+: 84200009 prfb pstl1strm, p0, \[x0, z0.s, uxtw\]
-+[^:]+: 84200009 prfb pstl1strm, p0, \[x0, z0.s, uxtw\]
-+[^:]+: 8420000a prfb pstl2keep, p0, \[x0, z0.s, uxtw\]
-+[^:]+: 8420000a prfb pstl2keep, p0, \[x0, z0.s, uxtw\]
-+[^:]+: 8420000a prfb pstl2keep, p0, \[x0, z0.s, uxtw\]
-+[^:]+: 8420000b prfb pstl2strm, p0, \[x0, z0.s, uxtw\]
-+[^:]+: 8420000b prfb pstl2strm, p0, \[x0, z0.s, uxtw\]
-+[^:]+: 8420000b prfb pstl2strm, p0, \[x0, z0.s, uxtw\]
-+[^:]+: 8420000c prfb pstl3keep, p0, \[x0, z0.s, uxtw\]
-+[^:]+: 8420000c prfb pstl3keep, p0, \[x0, z0.s, uxtw\]
-+[^:]+: 8420000c prfb pstl3keep, p0, \[x0, z0.s, uxtw\]
-+[^:]+: 8420000d prfb pstl3strm, p0, \[x0, z0.s, uxtw\]
-+[^:]+: 8420000d prfb pstl3strm, p0, \[x0, z0.s, uxtw\]
-+[^:]+: 8420000d prfb pstl3strm, p0, \[x0, z0.s, uxtw\]
-+[^:]+: 8420+e prfb #14, p0, \[x0, z0.s, uxtw\]
-+[^:]+: 8420+e prfb #14, p0, \[x0, z0.s, uxtw\]
-+[^:]+: 8420+e prfb #14, p0, \[x0, z0.s, uxtw\]
-+[^:]+: 8420000f prfb #15, p0, \[x0, z0.s, uxtw\]
-+[^:]+: 8420000f prfb #15, p0, \[x0, z0.s, uxtw\]
-+[^:]+: 8420000f prfb #15, p0, \[x0, z0.s, uxtw\]
-+[^:]+: 84200800 prfb pldl1keep, p2, \[x0, z0.s, uxtw\]
-+[^:]+: 84200800 prfb pldl1keep, p2, \[x0, z0.s, uxtw\]
-+[^:]+: 84200800 prfb pldl1keep, p2, \[x0, z0.s, uxtw\]
-+[^:]+: 84201c00 prfb pldl1keep, p7, \[x0, z0.s, uxtw\]
-+[^:]+: 84201c00 prfb pldl1keep, p7, \[x0, z0.s, uxtw\]
-+[^:]+: 84201c00 prfb pldl1keep, p7, \[x0, z0.s, uxtw\]
-+[^:]+: 84200060 prfb pldl1keep, p0, \[x3, z0.s, uxtw\]
-+[^:]+: 84200060 prfb pldl1keep, p0, \[x3, z0.s, uxtw\]
-+[^:]+: 84200060 prfb pldl1keep, p0, \[x3, z0.s, uxtw\]
-+[^:]+: 842003e0 prfb pldl1keep, p0, \[sp, z0.s, uxtw\]
-+[^:]+: 842003e0 prfb pldl1keep, p0, \[sp, z0.s, uxtw\]
-+[^:]+: 842003e0 prfb pldl1keep, p0, \[sp, z0.s, uxtw\]
-+[^:]+: 84240000 prfb pldl1keep, p0, \[x0, z4.s, uxtw\]
-+[^:]+: 84240000 prfb pldl1keep, p0, \[x0, z4.s, uxtw\]
-+[^:]+: 84240000 prfb pldl1keep, p0, \[x0, z4.s, uxtw\]
-+[^:]+: 843f0000 prfb pldl1keep, p0, \[x0, z31.s, uxtw\]
-+[^:]+: 843f0000 prfb pldl1keep, p0, \[x0, z31.s, uxtw\]
-+[^:]+: 843f0000 prfb pldl1keep, p0, \[x0, z31.s, uxtw\]
-+[^:]+: 84600000 prfb pldl1keep, p0, \[x0, z0.s, sxtw\]
-+[^:]+: 84600000 prfb pldl1keep, p0, \[x0, z0.s, sxtw\]
-+[^:]+: 84600000 prfb pldl1keep, p0, \[x0, z0.s, sxtw\]
-+[^:]+: 84600001 prfb pldl1strm, p0, \[x0, z0.s, sxtw\]
-+[^:]+: 84600001 prfb pldl1strm, p0, \[x0, z0.s, sxtw\]
-+[^:]+: 84600001 prfb pldl1strm, p0, \[x0, z0.s, sxtw\]
-+[^:]+: 84600002 prfb pldl2keep, p0, \[x0, z0.s, sxtw\]
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-+[^:]+: 84600008 prfb pstl1keep, p0, \[x0, z0.s, sxtw\]
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-+[^:]+: 8420600a prfd pstl2keep, p0, \[x0, z0.s, uxtw #3\]
-+[^:]+: 8420600b prfd pstl2strm, p0, \[x0, z0.s, uxtw #3\]
-+[^:]+: 8420600b prfd pstl2strm, p0, \[x0, z0.s, uxtw #3\]
-+[^:]+: 8420600c prfd pstl3keep, p0, \[x0, z0.s, uxtw #3\]
-+[^:]+: 8420600c prfd pstl3keep, p0, \[x0, z0.s, uxtw #3\]
-+[^:]+: 8420600d prfd pstl3strm, p0, \[x0, z0.s, uxtw #3\]
-+[^:]+: 8420600d prfd pstl3strm, p0, \[x0, z0.s, uxtw #3\]
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-+[^:]+: 842060+e prfd #14, p0, \[x0, z0.s, uxtw #3\]
-+[^:]+: 8420600f prfd #15, p0, \[x0, z0.s, uxtw #3\]
-+[^:]+: 8420600f prfd #15, p0, \[x0, z0.s, uxtw #3\]
-+[^:]+: 84206800 prfd pldl1keep, p2, \[x0, z0.s, uxtw #3\]
-+[^:]+: 84206800 prfd pldl1keep, p2, \[x0, z0.s, uxtw #3\]
-+[^:]+: 84207c00 prfd pldl1keep, p7, \[x0, z0.s, uxtw #3\]
-+[^:]+: 84207c00 prfd pldl1keep, p7, \[x0, z0.s, uxtw #3\]
-+[^:]+: 84206060 prfd pldl1keep, p0, \[x3, z0.s, uxtw #3\]
-+[^:]+: 84206060 prfd pldl1keep, p0, \[x3, z0.s, uxtw #3\]
-+[^:]+: 842063e0 prfd pldl1keep, p0, \[sp, z0.s, uxtw #3\]
-+[^:]+: 842063e0 prfd pldl1keep, p0, \[sp, z0.s, uxtw #3\]
-+[^:]+: 84246000 prfd pldl1keep, p0, \[x0, z4.s, uxtw #3\]
-+[^:]+: 84246000 prfd pldl1keep, p0, \[x0, z4.s, uxtw #3\]
-+[^:]+: 843f6000 prfd pldl1keep, p0, \[x0, z31.s, uxtw #3\]
-+[^:]+: 843f6000 prfd pldl1keep, p0, \[x0, z31.s, uxtw #3\]
-+[^:]+: 84606000 prfd pldl1keep, p0, \[x0, z0.s, sxtw #3\]
-+[^:]+: 84606000 prfd pldl1keep, p0, \[x0, z0.s, sxtw #3\]
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-+[^:]+: 84606002 prfd pldl2keep, p0, \[x0, z0.s, sxtw #3\]
-+[^:]+: 84606003 prfd pldl2strm, p0, \[x0, z0.s, sxtw #3\]
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-+[^:]+: 84606004 prfd pldl3keep, p0, \[x0, z0.s, sxtw #3\]
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-+[^:]+: 84606005 prfd pldl3strm, p0, \[x0, z0.s, sxtw #3\]
-+[^:]+: 84606006 prfd #6, p0, \[x0, z0.s, sxtw #3\]
-+[^:]+: 84606006 prfd #6, p0, \[x0, z0.s, sxtw #3\]
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-+[^:]+: 84606007 prfd #7, p0, \[x0, z0.s, sxtw #3\]
-+[^:]+: 84606008 prfd pstl1keep, p0, \[x0, z0.s, sxtw #3\]
-+[^:]+: 84606008 prfd pstl1keep, p0, \[x0, z0.s, sxtw #3\]
-+[^:]+: 84606009 prfd pstl1strm, p0, \[x0, z0.s, sxtw #3\]
-+[^:]+: 84606009 prfd pstl1strm, p0, \[x0, z0.s, sxtw #3\]
-+[^:]+: 8460600a prfd pstl2keep, p0, \[x0, z0.s, sxtw #3\]
-+[^:]+: 8460600a prfd pstl2keep, p0, \[x0, z0.s, sxtw #3\]
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-+[^:]+: 8460600b prfd pstl2strm, p0, \[x0, z0.s, sxtw #3\]
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-+[^:]+: 8460600c prfd pstl3keep, p0, \[x0, z0.s, sxtw #3\]
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-+[^:]+: 847f6000 prfd pldl1keep, p0, \[x0, z31.s, sxtw #3\]
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-+[^:]+: c4607c00 prfd pldl1keep, p7, \[x0, z0.d, sxtw #3\]
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-+[^:]+: c4606060 prfd pldl1keep, p0, \[x3, z0.d, sxtw #3\]
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-+[^:]+: c46063e0 prfd pldl1keep, p0, \[sp, z0.d, sxtw #3\]
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-+[^:]+: c4646000 prfd pldl1keep, p0, \[x0, z4.d, sxtw #3\]
-+[^:]+: c47f6000 prfd pldl1keep, p0, \[x0, z31.d, sxtw #3\]
-+[^:]+: c47f6000 prfd pldl1keep, p0, \[x0, z31.d, sxtw #3\]
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-+[^:]+: c460e001 prfd pldl1strm, p0, \[x0, z0.d, lsl #3\]
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-+[^:]+: c460e002 prfd pldl2keep, p0, \[x0, z0.d, lsl #3\]
-+[^:]+: c460e003 prfd pldl2strm, p0, \[x0, z0.d, lsl #3\]
-+[^:]+: c460e003 prfd pldl2strm, p0, \[x0, z0.d, lsl #3\]
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-+[^:]+: c460e005 prfd pldl3strm, p0, \[x0, z0.d, lsl #3\]
-+[^:]+: c460e005 prfd pldl3strm, p0, \[x0, z0.d, lsl #3\]
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-+[^:]+: c460e008 prfd pstl1keep, p0, \[x0, z0.d, lsl #3\]
-+[^:]+: c460e009 prfd pstl1strm, p0, \[x0, z0.d, lsl #3\]
-+[^:]+: c460e009 prfd pstl1strm, p0, \[x0, z0.d, lsl #3\]
-+[^:]+: c460e00a prfd pstl2keep, p0, \[x0, z0.d, lsl #3\]
-+[^:]+: c460e00a prfd pstl2keep, p0, \[x0, z0.d, lsl #3\]
-+[^:]+: c460e00b prfd pstl2strm, p0, \[x0, z0.d, lsl #3\]
-+[^:]+: c460e00b prfd pstl2strm, p0, \[x0, z0.d, lsl #3\]
-+[^:]+: c460e00c prfd pstl3keep, p0, \[x0, z0.d, lsl #3\]
-+[^:]+: c460e00c prfd pstl3keep, p0, \[x0, z0.d, lsl #3\]
-+[^:]+: c460e00d prfd pstl3strm, p0, \[x0, z0.d, lsl #3\]
-+[^:]+: c460e00d prfd pstl3strm, p0, \[x0, z0.d, lsl #3\]
-+[^:]+: c460e0+e prfd #14, p0, \[x0, z0.d, lsl #3\]
-+[^:]+: c460e0+e prfd #14, p0, \[x0, z0.d, lsl #3\]
-+[^:]+: c460e00f prfd #15, p0, \[x0, z0.d, lsl #3\]
-+[^:]+: c460e00f prfd #15, p0, \[x0, z0.d, lsl #3\]
-+[^:]+: c460e800 prfd pldl1keep, p2, \[x0, z0.d, lsl #3\]
-+[^:]+: c460e800 prfd pldl1keep, p2, \[x0, z0.d, lsl #3\]
-+[^:]+: c460fc00 prfd pldl1keep, p7, \[x0, z0.d, lsl #3\]
-+[^:]+: c460fc00 prfd pldl1keep, p7, \[x0, z0.d, lsl #3\]
-+[^:]+: c460e060 prfd pldl1keep, p0, \[x3, z0.d, lsl #3\]
-+[^:]+: c460e060 prfd pldl1keep, p0, \[x3, z0.d, lsl #3\]
-+[^:]+: c460e3e0 prfd pldl1keep, p0, \[sp, z0.d, lsl #3\]
-+[^:]+: c460e3e0 prfd pldl1keep, p0, \[sp, z0.d, lsl #3\]
-+[^:]+: c464e000 prfd pldl1keep, p0, \[x0, z4.d, lsl #3\]
-+[^:]+: c464e000 prfd pldl1keep, p0, \[x0, z4.d, lsl #3\]
-+[^:]+: c47fe000 prfd pldl1keep, p0, \[x0, z31.d, lsl #3\]
-+[^:]+: c47fe000 prfd pldl1keep, p0, \[x0, z31.d, lsl #3\]
-+[^:]+: 8580e000 prfd pldl1keep, p0, \[z0.s\]
-+[^:]+: 8580e000 prfd pldl1keep, p0, \[z0.s\]
-+[^:]+: 8580e000 prfd pldl1keep, p0, \[z0.s\]
-+[^:]+: 8580e001 prfd pldl1strm, p0, \[z0.s\]
-+[^:]+: 8580e001 prfd pldl1strm, p0, \[z0.s\]
-+[^:]+: 8580e001 prfd pldl1strm, p0, \[z0.s\]
-+[^:]+: 8580e002 prfd pldl2keep, p0, \[z0.s\]
-+[^:]+: 8580e002 prfd pldl2keep, p0, \[z0.s\]
-+[^:]+: 8580e002 prfd pldl2keep, p0, \[z0.s\]
-+[^:]+: 8580e003 prfd pldl2strm, p0, \[z0.s\]
-+[^:]+: 8580e003 prfd pldl2strm, p0, \[z0.s\]
-+[^:]+: 8580e003 prfd pldl2strm, p0, \[z0.s\]
-+[^:]+: 8580e004 prfd pldl3keep, p0, \[z0.s\]
-+[^:]+: 8580e004 prfd pldl3keep, p0, \[z0.s\]
-+[^:]+: 8580e004 prfd pldl3keep, p0, \[z0.s\]
-+[^:]+: 8580e005 prfd pldl3strm, p0, \[z0.s\]
-+[^:]+: 8580e005 prfd pldl3strm, p0, \[z0.s\]
-+[^:]+: 8580e005 prfd pldl3strm, p0, \[z0.s\]
-+[^:]+: 8580e006 prfd #6, p0, \[z0.s\]
-+[^:]+: 8580e006 prfd #6, p0, \[z0.s\]
-+[^:]+: 8580e006 prfd #6, p0, \[z0.s\]
-+[^:]+: 8580e007 prfd #7, p0, \[z0.s\]
-+[^:]+: 8580e007 prfd #7, p0, \[z0.s\]
-+[^:]+: 8580e007 prfd #7, p0, \[z0.s\]
-+[^:]+: 8580e008 prfd pstl1keep, p0, \[z0.s\]
-+[^:]+: 8580e008 prfd pstl1keep, p0, \[z0.s\]
-+[^:]+: 8580e008 prfd pstl1keep, p0, \[z0.s\]
-+[^:]+: 8580e009 prfd pstl1strm, p0, \[z0.s\]
-+[^:]+: 8580e009 prfd pstl1strm, p0, \[z0.s\]
-+[^:]+: 8580e009 prfd pstl1strm, p0, \[z0.s\]
-+[^:]+: 8580e00a prfd pstl2keep, p0, \[z0.s\]
-+[^:]+: 8580e00a prfd pstl2keep, p0, \[z0.s\]
-+[^:]+: 8580e00a prfd pstl2keep, p0, \[z0.s\]
-+[^:]+: 8580e00b prfd pstl2strm, p0, \[z0.s\]
-+[^:]+: 8580e00b prfd pstl2strm, p0, \[z0.s\]
-+[^:]+: 8580e00b prfd pstl2strm, p0, \[z0.s\]
-+[^:]+: 8580e00c prfd pstl3keep, p0, \[z0.s\]
-+[^:]+: 8580e00c prfd pstl3keep, p0, \[z0.s\]
-+[^:]+: 8580e00c prfd pstl3keep, p0, \[z0.s\]
-+[^:]+: 8580e00d prfd pstl3strm, p0, \[z0.s\]
-+[^:]+: 8580e00d prfd pstl3strm, p0, \[z0.s\]
-+[^:]+: 8580e00d prfd pstl3strm, p0, \[z0.s\]
-+[^:]+: 8580e0+e prfd #14, p0, \[z0.s\]
-+[^:]+: 8580e0+e prfd #14, p0, \[z0.s\]
-+[^:]+: 8580e0+e prfd #14, p0, \[z0.s\]
-+[^:]+: 8580e00f prfd #15, p0, \[z0.s\]
-+[^:]+: 8580e00f prfd #15, p0, \[z0.s\]
-+[^:]+: 8580e00f prfd #15, p0, \[z0.s\]
-+[^:]+: 8580e800 prfd pldl1keep, p2, \[z0.s\]
-+[^:]+: 8580e800 prfd pldl1keep, p2, \[z0.s\]
-+[^:]+: 8580e800 prfd pldl1keep, p2, \[z0.s\]
-+[^:]+: 8580fc00 prfd pldl1keep, p7, \[z0.s\]
-+[^:]+: 8580fc00 prfd pldl1keep, p7, \[z0.s\]
-+[^:]+: 8580fc00 prfd pldl1keep, p7, \[z0.s\]
-+[^:]+: 8580e060 prfd pldl1keep, p0, \[z3.s\]
-+[^:]+: 8580e060 prfd pldl1keep, p0, \[z3.s\]
-+[^:]+: 8580e060 prfd pldl1keep, p0, \[z3.s\]
-+[^:]+: 8580e3e0 prfd pldl1keep, p0, \[z31.s\]
-+[^:]+: 8580e3e0 prfd pldl1keep, p0, \[z31.s\]
-+[^:]+: 8580e3e0 prfd pldl1keep, p0, \[z31.s\]
-+[^:]+: 858fe000 prfd pldl1keep, p0, \[z0.s, #120\]
-+[^:]+: 858fe000 prfd pldl1keep, p0, \[z0.s, #120\]
-+[^:]+: 8590e000 prfd pldl1keep, p0, \[z0.s, #128\]
-+[^:]+: 8590e000 prfd pldl1keep, p0, \[z0.s, #128\]
-+[^:]+: 8591e000 prfd pldl1keep, p0, \[z0.s, #136\]
-+[^:]+: 8591e000 prfd pldl1keep, p0, \[z0.s, #136\]
-+[^:]+: 859fe000 prfd pldl1keep, p0, \[z0.s, #248\]
-+[^:]+: 859fe000 prfd pldl1keep, p0, \[z0.s, #248\]
-+[^:]+: 85c06000 prfd pldl1keep, p0, \[x0\]
-+[^:]+: 85c06000 prfd pldl1keep, p0, \[x0\]
-+[^:]+: 85c06000 prfd pldl1keep, p0, \[x0\]
-+[^:]+: 85c06000 prfd pldl1keep, p0, \[x0\]
-+[^:]+: 85c06001 prfd pldl1strm, p0, \[x0\]
-+[^:]+: 85c06001 prfd pldl1strm, p0, \[x0\]
-+[^:]+: 85c06001 prfd pldl1strm, p0, \[x0\]
-+[^:]+: 85c06001 prfd pldl1strm, p0, \[x0\]
-+[^:]+: 85c06002 prfd pldl2keep, p0, \[x0\]
-+[^:]+: 85c06002 prfd pldl2keep, p0, \[x0\]
-+[^:]+: 85c06002 prfd pldl2keep, p0, \[x0\]
-+[^:]+: 85c06002 prfd pldl2keep, p0, \[x0\]
-+[^:]+: 85c06003 prfd pldl2strm, p0, \[x0\]
-+[^:]+: 85c06003 prfd pldl2strm, p0, \[x0\]
-+[^:]+: 85c06003 prfd pldl2strm, p0, \[x0\]
-+[^:]+: 85c06003 prfd pldl2strm, p0, \[x0\]
-+[^:]+: 85c06004 prfd pldl3keep, p0, \[x0\]
-+[^:]+: 85c06004 prfd pldl3keep, p0, \[x0\]
-+[^:]+: 85c06004 prfd pldl3keep, p0, \[x0\]
-+[^:]+: 85c06004 prfd pldl3keep, p0, \[x0\]
-+[^:]+: 85c06005 prfd pldl3strm, p0, \[x0\]
-+[^:]+: 85c06005 prfd pldl3strm, p0, \[x0\]
-+[^:]+: 85c06005 prfd pldl3strm, p0, \[x0\]
-+[^:]+: 85c06005 prfd pldl3strm, p0, \[x0\]
-+[^:]+: 85c06006 prfd #6, p0, \[x0\]
-+[^:]+: 85c06006 prfd #6, p0, \[x0\]
-+[^:]+: 85c06006 prfd #6, p0, \[x0\]
-+[^:]+: 85c06006 prfd #6, p0, \[x0\]
-+[^:]+: 85c06007 prfd #7, p0, \[x0\]
-+[^:]+: 85c06007 prfd #7, p0, \[x0\]
-+[^:]+: 85c06007 prfd #7, p0, \[x0\]
-+[^:]+: 85c06007 prfd #7, p0, \[x0\]
-+[^:]+: 85c06008 prfd pstl1keep, p0, \[x0\]
-+[^:]+: 85c06008 prfd pstl1keep, p0, \[x0\]
-+[^:]+: 85c06008 prfd pstl1keep, p0, \[x0\]
-+[^:]+: 85c06008 prfd pstl1keep, p0, \[x0\]
-+[^:]+: 85c06009 prfd pstl1strm, p0, \[x0\]
-+[^:]+: 85c06009 prfd pstl1strm, p0, \[x0\]
-+[^:]+: 85c06009 prfd pstl1strm, p0, \[x0\]
-+[^:]+: 85c06009 prfd pstl1strm, p0, \[x0\]
-+[^:]+: 85c0600a prfd pstl2keep, p0, \[x0\]
-+[^:]+: 85c0600a prfd pstl2keep, p0, \[x0\]
-+[^:]+: 85c0600a prfd pstl2keep, p0, \[x0\]
-+[^:]+: 85c0600a prfd pstl2keep, p0, \[x0\]
-+[^:]+: 85c0600b prfd pstl2strm, p0, \[x0\]
-+[^:]+: 85c0600b prfd pstl2strm, p0, \[x0\]
-+[^:]+: 85c0600b prfd pstl2strm, p0, \[x0\]
-+[^:]+: 85c0600b prfd pstl2strm, p0, \[x0\]
-+[^:]+: 85c0600c prfd pstl3keep, p0, \[x0\]
-+[^:]+: 85c0600c prfd pstl3keep, p0, \[x0\]
-+[^:]+: 85c0600c prfd pstl3keep, p0, \[x0\]
-+[^:]+: 85c0600c prfd pstl3keep, p0, \[x0\]
-+[^:]+: 85c0600d prfd pstl3strm, p0, \[x0\]
-+[^:]+: 85c0600d prfd pstl3strm, p0, \[x0\]
-+[^:]+: 85c0600d prfd pstl3strm, p0, \[x0\]
-+[^:]+: 85c0600d prfd pstl3strm, p0, \[x0\]
-+[^:]+: 85c060+e prfd #14, p0, \[x0\]
-+[^:]+: 85c060+e prfd #14, p0, \[x0\]
-+[^:]+: 85c060+e prfd #14, p0, \[x0\]
-+[^:]+: 85c060+e prfd #14, p0, \[x0\]
-+[^:]+: 85c0600f prfd #15, p0, \[x0\]
-+[^:]+: 85c0600f prfd #15, p0, \[x0\]
-+[^:]+: 85c0600f prfd #15, p0, \[x0\]
-+[^:]+: 85c0600f prfd #15, p0, \[x0\]
-+[^:]+: 85c06800 prfd pldl1keep, p2, \[x0\]
-+[^:]+: 85c06800 prfd pldl1keep, p2, \[x0\]
-+[^:]+: 85c06800 prfd pldl1keep, p2, \[x0\]
-+[^:]+: 85c06800 prfd pldl1keep, p2, \[x0\]
-+[^:]+: 85c07c00 prfd pldl1keep, p7, \[x0\]
-+[^:]+: 85c07c00 prfd pldl1keep, p7, \[x0\]
-+[^:]+: 85c07c00 prfd pldl1keep, p7, \[x0\]
-+[^:]+: 85c07c00 prfd pldl1keep, p7, \[x0\]
-+[^:]+: 85c06060 prfd pldl1keep, p0, \[x3\]
-+[^:]+: 85c06060 prfd pldl1keep, p0, \[x3\]
-+[^:]+: 85c06060 prfd pldl1keep, p0, \[x3\]
-+[^:]+: 85c06060 prfd pldl1keep, p0, \[x3\]
-+[^:]+: 85c063e0 prfd pldl1keep, p0, \[sp\]
-+[^:]+: 85c063e0 prfd pldl1keep, p0, \[sp\]
-+[^:]+: 85c063e0 prfd pldl1keep, p0, \[sp\]
-+[^:]+: 85c063e0 prfd pldl1keep, p0, \[sp\]
-+[^:]+: 85df6000 prfd pldl1keep, p0, \[x0, #31, mul vl\]
-+[^:]+: 85df6000 prfd pldl1keep, p0, \[x0, #31, mul vl\]
-+[^:]+: 85e06000 prfd pldl1keep, p0, \[x0, #-32, mul vl\]
-+[^:]+: 85e06000 prfd pldl1keep, p0, \[x0, #-32, mul vl\]
-+[^:]+: 85e16000 prfd pldl1keep, p0, \[x0, #-31, mul vl\]
-+[^:]+: 85e16000 prfd pldl1keep, p0, \[x0, #-31, mul vl\]
-+[^:]+: 85ff6000 prfd pldl1keep, p0, \[x0, #-1, mul vl\]
-+[^:]+: 85ff6000 prfd pldl1keep, p0, \[x0, #-1, mul vl\]
-+[^:]+: c580e000 prfd pldl1keep, p0, \[z0.d\]
-+[^:]+: c580e000 prfd pldl1keep, p0, \[z0.d\]
-+[^:]+: c580e000 prfd pldl1keep, p0, \[z0.d\]
-+[^:]+: c580e001 prfd pldl1strm, p0, \[z0.d\]
-+[^:]+: c580e001 prfd pldl1strm, p0, \[z0.d\]
-+[^:]+: c580e001 prfd pldl1strm, p0, \[z0.d\]
-+[^:]+: c580e002 prfd pldl2keep, p0, \[z0.d\]
-+[^:]+: c580e002 prfd pldl2keep, p0, \[z0.d\]
-+[^:]+: c580e002 prfd pldl2keep, p0, \[z0.d\]
-+[^:]+: c580e003 prfd pldl2strm, p0, \[z0.d\]
-+[^:]+: c580e003 prfd pldl2strm, p0, \[z0.d\]
-+[^:]+: c580e003 prfd pldl2strm, p0, \[z0.d\]
-+[^:]+: c580e004 prfd pldl3keep, p0, \[z0.d\]
-+[^:]+: c580e004 prfd pldl3keep, p0, \[z0.d\]
-+[^:]+: c580e004 prfd pldl3keep, p0, \[z0.d\]
-+[^:]+: c580e005 prfd pldl3strm, p0, \[z0.d\]
-+[^:]+: c580e005 prfd pldl3strm, p0, \[z0.d\]
-+[^:]+: c580e005 prfd pldl3strm, p0, \[z0.d\]
-+[^:]+: c580e006 prfd #6, p0, \[z0.d\]
-+[^:]+: c580e006 prfd #6, p0, \[z0.d\]
-+[^:]+: c580e006 prfd #6, p0, \[z0.d\]
-+[^:]+: c580e007 prfd #7, p0, \[z0.d\]
-+[^:]+: c580e007 prfd #7, p0, \[z0.d\]
-+[^:]+: c580e007 prfd #7, p0, \[z0.d\]
-+[^:]+: c580e008 prfd pstl1keep, p0, \[z0.d\]
-+[^:]+: c580e008 prfd pstl1keep, p0, \[z0.d\]
-+[^:]+: c580e008 prfd pstl1keep, p0, \[z0.d\]
-+[^:]+: c580e009 prfd pstl1strm, p0, \[z0.d\]
-+[^:]+: c580e009 prfd pstl1strm, p0, \[z0.d\]
-+[^:]+: c580e009 prfd pstl1strm, p0, \[z0.d\]
-+[^:]+: c580e00a prfd pstl2keep, p0, \[z0.d\]
-+[^:]+: c580e00a prfd pstl2keep, p0, \[z0.d\]
-+[^:]+: c580e00a prfd pstl2keep, p0, \[z0.d\]
-+[^:]+: c580e00b prfd pstl2strm, p0, \[z0.d\]
-+[^:]+: c580e00b prfd pstl2strm, p0, \[z0.d\]
-+[^:]+: c580e00b prfd pstl2strm, p0, \[z0.d\]
-+[^:]+: c580e00c prfd pstl3keep, p0, \[z0.d\]
-+[^:]+: c580e00c prfd pstl3keep, p0, \[z0.d\]
-+[^:]+: c580e00c prfd pstl3keep, p0, \[z0.d\]
-+[^:]+: c580e00d prfd pstl3strm, p0, \[z0.d\]
-+[^:]+: c580e00d prfd pstl3strm, p0, \[z0.d\]
-+[^:]+: c580e00d prfd pstl3strm, p0, \[z0.d\]
-+[^:]+: c580e0+e prfd #14, p0, \[z0.d\]
-+[^:]+: c580e0+e prfd #14, p0, \[z0.d\]
-+[^:]+: c580e0+e prfd #14, p0, \[z0.d\]
-+[^:]+: c580e00f prfd #15, p0, \[z0.d\]
-+[^:]+: c580e00f prfd #15, p0, \[z0.d\]
-+[^:]+: c580e00f prfd #15, p0, \[z0.d\]
-+[^:]+: c580e800 prfd pldl1keep, p2, \[z0.d\]
-+[^:]+: c580e800 prfd pldl1keep, p2, \[z0.d\]
-+[^:]+: c580e800 prfd pldl1keep, p2, \[z0.d\]
-+[^:]+: c580fc00 prfd pldl1keep, p7, \[z0.d\]
-+[^:]+: c580fc00 prfd pldl1keep, p7, \[z0.d\]
-+[^:]+: c580fc00 prfd pldl1keep, p7, \[z0.d\]
-+[^:]+: c580e060 prfd pldl1keep, p0, \[z3.d\]
-+[^:]+: c580e060 prfd pldl1keep, p0, \[z3.d\]
-+[^:]+: c580e060 prfd pldl1keep, p0, \[z3.d\]
-+[^:]+: c580e3e0 prfd pldl1keep, p0, \[z31.d\]
-+[^:]+: c580e3e0 prfd pldl1keep, p0, \[z31.d\]
-+[^:]+: c580e3e0 prfd pldl1keep, p0, \[z31.d\]
-+[^:]+: c58fe000 prfd pldl1keep, p0, \[z0.d, #120\]
-+[^:]+: c58fe000 prfd pldl1keep, p0, \[z0.d, #120\]
-+[^:]+: c590e000 prfd pldl1keep, p0, \[z0.d, #128\]
-+[^:]+: c590e000 prfd pldl1keep, p0, \[z0.d, #128\]
-+[^:]+: c591e000 prfd pldl1keep, p0, \[z0.d, #136\]
-+[^:]+: c591e000 prfd pldl1keep, p0, \[z0.d, #136\]
-+[^:]+: c59fe000 prfd pldl1keep, p0, \[z0.d, #248\]
-+[^:]+: c59fe000 prfd pldl1keep, p0, \[z0.d, #248\]
-+[^:]+: 84202000 prfh pldl1keep, p0, \[x0, z0.s, uxtw #1\]
-+[^:]+: 84202000 prfh pldl1keep, p0, \[x0, z0.s, uxtw #1\]
-+[^:]+: 84202001 prfh pldl1strm, p0, \[x0, z0.s, uxtw #1\]
-+[^:]+: 84202001 prfh pldl1strm, p0, \[x0, z0.s, uxtw #1\]
-+[^:]+: 84202002 prfh pldl2keep, p0, \[x0, z0.s, uxtw #1\]
-+[^:]+: 84202002 prfh pldl2keep, p0, \[x0, z0.s, uxtw #1\]
-+[^:]+: 84202003 prfh pldl2strm, p0, \[x0, z0.s, uxtw #1\]
-+[^:]+: 84202003 prfh pldl2strm, p0, \[x0, z0.s, uxtw #1\]
-+[^:]+: 84202004 prfh pldl3keep, p0, \[x0, z0.s, uxtw #1\]
-+[^:]+: 84202004 prfh pldl3keep, p0, \[x0, z0.s, uxtw #1\]
-+[^:]+: 84202005 prfh pldl3strm, p0, \[x0, z0.s, uxtw #1\]
-+[^:]+: 84202005 prfh pldl3strm, p0, \[x0, z0.s, uxtw #1\]
-+[^:]+: 84202006 prfh #6, p0, \[x0, z0.s, uxtw #1\]
-+[^:]+: 84202006 prfh #6, p0, \[x0, z0.s, uxtw #1\]
-+[^:]+: 84202007 prfh #7, p0, \[x0, z0.s, uxtw #1\]
-+[^:]+: 84202007 prfh #7, p0, \[x0, z0.s, uxtw #1\]
-+[^:]+: 84202008 prfh pstl1keep, p0, \[x0, z0.s, uxtw #1\]
-+[^:]+: 84202008 prfh pstl1keep, p0, \[x0, z0.s, uxtw #1\]
-+[^:]+: 84202009 prfh pstl1strm, p0, \[x0, z0.s, uxtw #1\]
-+[^:]+: 84202009 prfh pstl1strm, p0, \[x0, z0.s, uxtw #1\]
-+[^:]+: 8420200a prfh pstl2keep, p0, \[x0, z0.s, uxtw #1\]
-+[^:]+: 8420200a prfh pstl2keep, p0, \[x0, z0.s, uxtw #1\]
-+[^:]+: 8420200b prfh pstl2strm, p0, \[x0, z0.s, uxtw #1\]
-+[^:]+: 8420200b prfh pstl2strm, p0, \[x0, z0.s, uxtw #1\]
-+[^:]+: 8420200c prfh pstl3keep, p0, \[x0, z0.s, uxtw #1\]
-+[^:]+: 8420200c prfh pstl3keep, p0, \[x0, z0.s, uxtw #1\]
-+[^:]+: 8420200d prfh pstl3strm, p0, \[x0, z0.s, uxtw #1\]
-+[^:]+: 8420200d prfh pstl3strm, p0, \[x0, z0.s, uxtw #1\]
-+[^:]+: 842020+e prfh #14, p0, \[x0, z0.s, uxtw #1\]
-+[^:]+: 842020+e prfh #14, p0, \[x0, z0.s, uxtw #1\]
-+[^:]+: 8420200f prfh #15, p0, \[x0, z0.s, uxtw #1\]
-+[^:]+: 8420200f prfh #15, p0, \[x0, z0.s, uxtw #1\]
-+[^:]+: 84202800 prfh pldl1keep, p2, \[x0, z0.s, uxtw #1\]
-+[^:]+: 84202800 prfh pldl1keep, p2, \[x0, z0.s, uxtw #1\]
-+[^:]+: 84203c00 prfh pldl1keep, p7, \[x0, z0.s, uxtw #1\]
-+[^:]+: 84203c00 prfh pldl1keep, p7, \[x0, z0.s, uxtw #1\]
-+[^:]+: 84202060 prfh pldl1keep, p0, \[x3, z0.s, uxtw #1\]
-+[^:]+: 84202060 prfh pldl1keep, p0, \[x3, z0.s, uxtw #1\]
-+[^:]+: 842023e0 prfh pldl1keep, p0, \[sp, z0.s, uxtw #1\]
-+[^:]+: 842023e0 prfh pldl1keep, p0, \[sp, z0.s, uxtw #1\]
-+[^:]+: 84242000 prfh pldl1keep, p0, \[x0, z4.s, uxtw #1\]
-+[^:]+: 84242000 prfh pldl1keep, p0, \[x0, z4.s, uxtw #1\]
-+[^:]+: 843f2000 prfh pldl1keep, p0, \[x0, z31.s, uxtw #1\]
-+[^:]+: 843f2000 prfh pldl1keep, p0, \[x0, z31.s, uxtw #1\]
-+[^:]+: 84602000 prfh pldl1keep, p0, \[x0, z0.s, sxtw #1\]
-+[^:]+: 84602000 prfh pldl1keep, p0, \[x0, z0.s, sxtw #1\]
-+[^:]+: 84602001 prfh pldl1strm, p0, \[x0, z0.s, sxtw #1\]
-+[^:]+: 84602001 prfh pldl1strm, p0, \[x0, z0.s, sxtw #1\]
-+[^:]+: 84602002 prfh pldl2keep, p0, \[x0, z0.s, sxtw #1\]
-+[^:]+: 84602002 prfh pldl2keep, p0, \[x0, z0.s, sxtw #1\]
-+[^:]+: 84602003 prfh pldl2strm, p0, \[x0, z0.s, sxtw #1\]
-+[^:]+: 84602003 prfh pldl2strm, p0, \[x0, z0.s, sxtw #1\]
-+[^:]+: 84602004 prfh pldl3keep, p0, \[x0, z0.s, sxtw #1\]
-+[^:]+: 84602004 prfh pldl3keep, p0, \[x0, z0.s, sxtw #1\]
-+[^:]+: 84602005 prfh pldl3strm, p0, \[x0, z0.s, sxtw #1\]
-+[^:]+: 84602005 prfh pldl3strm, p0, \[x0, z0.s, sxtw #1\]
-+[^:]+: 84602006 prfh #6, p0, \[x0, z0.s, sxtw #1\]
-+[^:]+: 84602006 prfh #6, p0, \[x0, z0.s, sxtw #1\]
-+[^:]+: 84602007 prfh #7, p0, \[x0, z0.s, sxtw #1\]
-+[^:]+: 84602007 prfh #7, p0, \[x0, z0.s, sxtw #1\]
-+[^:]+: 84602008 prfh pstl1keep, p0, \[x0, z0.s, sxtw #1\]
-+[^:]+: 84602008 prfh pstl1keep, p0, \[x0, z0.s, sxtw #1\]
-+[^:]+: 84602009 prfh pstl1strm, p0, \[x0, z0.s, sxtw #1\]
-+[^:]+: 84602009 prfh pstl1strm, p0, \[x0, z0.s, sxtw #1\]
-+[^:]+: 8460200a prfh pstl2keep, p0, \[x0, z0.s, sxtw #1\]
-+[^:]+: 8460200a prfh pstl2keep, p0, \[x0, z0.s, sxtw #1\]
-+[^:]+: 8460200b prfh pstl2strm, p0, \[x0, z0.s, sxtw #1\]
-+[^:]+: 8460200b prfh pstl2strm, p0, \[x0, z0.s, sxtw #1\]
-+[^:]+: 8460200c prfh pstl3keep, p0, \[x0, z0.s, sxtw #1\]
-+[^:]+: 8460200c prfh pstl3keep, p0, \[x0, z0.s, sxtw #1\]
-+[^:]+: 8460200d prfh pstl3strm, p0, \[x0, z0.s, sxtw #1\]
-+[^:]+: 8460200d prfh pstl3strm, p0, \[x0, z0.s, sxtw #1\]
-+[^:]+: 846020+e prfh #14, p0, \[x0, z0.s, sxtw #1\]
-+[^:]+: 846020+e prfh #14, p0, \[x0, z0.s, sxtw #1\]
-+[^:]+: 8460200f prfh #15, p0, \[x0, z0.s, sxtw #1\]
-+[^:]+: 8460200f prfh #15, p0, \[x0, z0.s, sxtw #1\]
-+[^:]+: 84602800 prfh pldl1keep, p2, \[x0, z0.s, sxtw #1\]
-+[^:]+: 84602800 prfh pldl1keep, p2, \[x0, z0.s, sxtw #1\]
-+[^:]+: 84603c00 prfh pldl1keep, p7, \[x0, z0.s, sxtw #1\]
-+[^:]+: 84603c00 prfh pldl1keep, p7, \[x0, z0.s, sxtw #1\]
-+[^:]+: 84602060 prfh pldl1keep, p0, \[x3, z0.s, sxtw #1\]
-+[^:]+: 84602060 prfh pldl1keep, p0, \[x3, z0.s, sxtw #1\]
-+[^:]+: 846023e0 prfh pldl1keep, p0, \[sp, z0.s, sxtw #1\]
-+[^:]+: 846023e0 prfh pldl1keep, p0, \[sp, z0.s, sxtw #1\]
-+[^:]+: 84642000 prfh pldl1keep, p0, \[x0, z4.s, sxtw #1\]
-+[^:]+: 84642000 prfh pldl1keep, p0, \[x0, z4.s, sxtw #1\]
-+[^:]+: 847f2000 prfh pldl1keep, p0, \[x0, z31.s, sxtw #1\]
-+[^:]+: 847f2000 prfh pldl1keep, p0, \[x0, z31.s, sxtw #1\]
-+[^:]+: 8480c000 prfh pldl1keep, p0, \[x0, x0, lsl #1\]
-+[^:]+: 8480c000 prfh pldl1keep, p0, \[x0, x0, lsl #1\]
-+[^:]+: 8480c001 prfh pldl1strm, p0, \[x0, x0, lsl #1\]
-+[^:]+: 8480c001 prfh pldl1strm, p0, \[x0, x0, lsl #1\]
-+[^:]+: 8480c002 prfh pldl2keep, p0, \[x0, x0, lsl #1\]
-+[^:]+: 8480c002 prfh pldl2keep, p0, \[x0, x0, lsl #1\]
-+[^:]+: 8480c003 prfh pldl2strm, p0, \[x0, x0, lsl #1\]
-+[^:]+: 8480c003 prfh pldl2strm, p0, \[x0, x0, lsl #1\]
-+[^:]+: 8480c004 prfh pldl3keep, p0, \[x0, x0, lsl #1\]
-+[^:]+: 8480c004 prfh pldl3keep, p0, \[x0, x0, lsl #1\]
-+[^:]+: 8480c005 prfh pldl3strm, p0, \[x0, x0, lsl #1\]
-+[^:]+: 8480c005 prfh pldl3strm, p0, \[x0, x0, lsl #1\]
-+[^:]+: 8480c006 prfh #6, p0, \[x0, x0, lsl #1\]
-+[^:]+: 8480c006 prfh #6, p0, \[x0, x0, lsl #1\]
-+[^:]+: 8480c007 prfh #7, p0, \[x0, x0, lsl #1\]
-+[^:]+: 8480c007 prfh #7, p0, \[x0, x0, lsl #1\]
-+[^:]+: 8480c008 prfh pstl1keep, p0, \[x0, x0, lsl #1\]
-+[^:]+: 8480c008 prfh pstl1keep, p0, \[x0, x0, lsl #1\]
-+[^:]+: 8480c009 prfh pstl1strm, p0, \[x0, x0, lsl #1\]
-+[^:]+: 8480c009 prfh pstl1strm, p0, \[x0, x0, lsl #1\]
-+[^:]+: 8480c00a prfh pstl2keep, p0, \[x0, x0, lsl #1\]
-+[^:]+: 8480c00a prfh pstl2keep, p0, \[x0, x0, lsl #1\]
-+[^:]+: 8480c00b prfh pstl2strm, p0, \[x0, x0, lsl #1\]
-+[^:]+: 8480c00b prfh pstl2strm, p0, \[x0, x0, lsl #1\]
-+[^:]+: 8480c00c prfh pstl3keep, p0, \[x0, x0, lsl #1\]
-+[^:]+: 8480c00c prfh pstl3keep, p0, \[x0, x0, lsl #1\]
-+[^:]+: 8480c00d prfh pstl3strm, p0, \[x0, x0, lsl #1\]
-+[^:]+: 8480c00d prfh pstl3strm, p0, \[x0, x0, lsl #1\]
-+[^:]+: 8480c0+e prfh #14, p0, \[x0, x0, lsl #1\]
-+[^:]+: 8480c0+e prfh #14, p0, \[x0, x0, lsl #1\]
-+[^:]+: 8480c00f prfh #15, p0, \[x0, x0, lsl #1\]
-+[^:]+: 8480c00f prfh #15, p0, \[x0, x0, lsl #1\]
-+[^:]+: 8480c800 prfh pldl1keep, p2, \[x0, x0, lsl #1\]
-+[^:]+: 8480c800 prfh pldl1keep, p2, \[x0, x0, lsl #1\]
-+[^:]+: 8480dc00 prfh pldl1keep, p7, \[x0, x0, lsl #1\]
-+[^:]+: 8480dc00 prfh pldl1keep, p7, \[x0, x0, lsl #1\]
-+[^:]+: 8480c060 prfh pldl1keep, p0, \[x3, x0, lsl #1\]
-+[^:]+: 8480c060 prfh pldl1keep, p0, \[x3, x0, lsl #1\]
-+[^:]+: 8480c3e0 prfh pldl1keep, p0, \[sp, x0, lsl #1\]
-+[^:]+: 8480c3e0 prfh pldl1keep, p0, \[sp, x0, lsl #1\]
-+[^:]+: 8484c000 prfh pldl1keep, p0, \[x0, x4, lsl #1\]
-+[^:]+: 8484c000 prfh pldl1keep, p0, \[x0, x4, lsl #1\]
-+[^:]+: 849ec000 prfh pldl1keep, p0, \[x0, x30, lsl #1\]
-+[^:]+: 849ec000 prfh pldl1keep, p0, \[x0, x30, lsl #1\]
-+[^:]+: c4202000 prfh pldl1keep, p0, \[x0, z0.d, uxtw #1\]
-+[^:]+: c4202000 prfh pldl1keep, p0, \[x0, z0.d, uxtw #1\]
-+[^:]+: c4202001 prfh pldl1strm, p0, \[x0, z0.d, uxtw #1\]
-+[^:]+: c4202001 prfh pldl1strm, p0, \[x0, z0.d, uxtw #1\]
-+[^:]+: c4202002 prfh pldl2keep, p0, \[x0, z0.d, uxtw #1\]
-+[^:]+: c4202002 prfh pldl2keep, p0, \[x0, z0.d, uxtw #1\]
-+[^:]+: c4202003 prfh pldl2strm, p0, \[x0, z0.d, uxtw #1\]
-+[^:]+: c4202003 prfh pldl2strm, p0, \[x0, z0.d, uxtw #1\]
-+[^:]+: c4202004 prfh pldl3keep, p0, \[x0, z0.d, uxtw #1\]
-+[^:]+: c4202004 prfh pldl3keep, p0, \[x0, z0.d, uxtw #1\]
-+[^:]+: c4202005 prfh pldl3strm, p0, \[x0, z0.d, uxtw #1\]
-+[^:]+: c4202005 prfh pldl3strm, p0, \[x0, z0.d, uxtw #1\]
-+[^:]+: c4202006 prfh #6, p0, \[x0, z0.d, uxtw #1\]
-+[^:]+: c4202006 prfh #6, p0, \[x0, z0.d, uxtw #1\]
-+[^:]+: c4202007 prfh #7, p0, \[x0, z0.d, uxtw #1\]
-+[^:]+: c4202007 prfh #7, p0, \[x0, z0.d, uxtw #1\]
-+[^:]+: c4202008 prfh pstl1keep, p0, \[x0, z0.d, uxtw #1\]
-+[^:]+: c4202008 prfh pstl1keep, p0, \[x0, z0.d, uxtw #1\]
-+[^:]+: c4202009 prfh pstl1strm, p0, \[x0, z0.d, uxtw #1\]
-+[^:]+: c4202009 prfh pstl1strm, p0, \[x0, z0.d, uxtw #1\]
-+[^:]+: c420200a prfh pstl2keep, p0, \[x0, z0.d, uxtw #1\]
-+[^:]+: c420200a prfh pstl2keep, p0, \[x0, z0.d, uxtw #1\]
-+[^:]+: c420200b prfh pstl2strm, p0, \[x0, z0.d, uxtw #1\]
-+[^:]+: c420200b prfh pstl2strm, p0, \[x0, z0.d, uxtw #1\]
-+[^:]+: c420200c prfh pstl3keep, p0, \[x0, z0.d, uxtw #1\]
-+[^:]+: c420200c prfh pstl3keep, p0, \[x0, z0.d, uxtw #1\]
-+[^:]+: c420200d prfh pstl3strm, p0, \[x0, z0.d, uxtw #1\]
-+[^:]+: c420200d prfh pstl3strm, p0, \[x0, z0.d, uxtw #1\]
-+[^:]+: c42020+e prfh #14, p0, \[x0, z0.d, uxtw #1\]
-+[^:]+: c42020+e prfh #14, p0, \[x0, z0.d, uxtw #1\]
-+[^:]+: c420200f prfh #15, p0, \[x0, z0.d, uxtw #1\]
-+[^:]+: c420200f prfh #15, p0, \[x0, z0.d, uxtw #1\]
-+[^:]+: c4202800 prfh pldl1keep, p2, \[x0, z0.d, uxtw #1\]
-+[^:]+: c4202800 prfh pldl1keep, p2, \[x0, z0.d, uxtw #1\]
-+[^:]+: c4203c00 prfh pldl1keep, p7, \[x0, z0.d, uxtw #1\]
-+[^:]+: c4203c00 prfh pldl1keep, p7, \[x0, z0.d, uxtw #1\]
-+[^:]+: c4202060 prfh pldl1keep, p0, \[x3, z0.d, uxtw #1\]
-+[^:]+: c4202060 prfh pldl1keep, p0, \[x3, z0.d, uxtw #1\]
-+[^:]+: c42023e0 prfh pldl1keep, p0, \[sp, z0.d, uxtw #1\]
-+[^:]+: c42023e0 prfh pldl1keep, p0, \[sp, z0.d, uxtw #1\]
-+[^:]+: c4242000 prfh pldl1keep, p0, \[x0, z4.d, uxtw #1\]
-+[^:]+: c4242000 prfh pldl1keep, p0, \[x0, z4.d, uxtw #1\]
-+[^:]+: c43f2000 prfh pldl1keep, p0, \[x0, z31.d, uxtw #1\]
-+[^:]+: c43f2000 prfh pldl1keep, p0, \[x0, z31.d, uxtw #1\]
-+[^:]+: c4602000 prfh pldl1keep, p0, \[x0, z0.d, sxtw #1\]
-+[^:]+: c4602000 prfh pldl1keep, p0, \[x0, z0.d, sxtw #1\]
-+[^:]+: c4602001 prfh pldl1strm, p0, \[x0, z0.d, sxtw #1\]
-+[^:]+: c4602001 prfh pldl1strm, p0, \[x0, z0.d, sxtw #1\]
-+[^:]+: c4602002 prfh pldl2keep, p0, \[x0, z0.d, sxtw #1\]
-+[^:]+: c4602002 prfh pldl2keep, p0, \[x0, z0.d, sxtw #1\]
-+[^:]+: c4602003 prfh pldl2strm, p0, \[x0, z0.d, sxtw #1\]
-+[^:]+: c4602003 prfh pldl2strm, p0, \[x0, z0.d, sxtw #1\]
-+[^:]+: c4602004 prfh pldl3keep, p0, \[x0, z0.d, sxtw #1\]
-+[^:]+: c4602004 prfh pldl3keep, p0, \[x0, z0.d, sxtw #1\]
-+[^:]+: c4602005 prfh pldl3strm, p0, \[x0, z0.d, sxtw #1\]
-+[^:]+: c4602005 prfh pldl3strm, p0, \[x0, z0.d, sxtw #1\]
-+[^:]+: c4602006 prfh #6, p0, \[x0, z0.d, sxtw #1\]
-+[^:]+: c4602006 prfh #6, p0, \[x0, z0.d, sxtw #1\]
-+[^:]+: c4602007 prfh #7, p0, \[x0, z0.d, sxtw #1\]
-+[^:]+: c4602007 prfh #7, p0, \[x0, z0.d, sxtw #1\]
-+[^:]+: c4602008 prfh pstl1keep, p0, \[x0, z0.d, sxtw #1\]
-+[^:]+: c4602008 prfh pstl1keep, p0, \[x0, z0.d, sxtw #1\]
-+[^:]+: c4602009 prfh pstl1strm, p0, \[x0, z0.d, sxtw #1\]
-+[^:]+: c4602009 prfh pstl1strm, p0, \[x0, z0.d, sxtw #1\]
-+[^:]+: c460200a prfh pstl2keep, p0, \[x0, z0.d, sxtw #1\]
-+[^:]+: c460200a prfh pstl2keep, p0, \[x0, z0.d, sxtw #1\]
-+[^:]+: c460200b prfh pstl2strm, p0, \[x0, z0.d, sxtw #1\]
-+[^:]+: c460200b prfh pstl2strm, p0, \[x0, z0.d, sxtw #1\]
-+[^:]+: c460200c prfh pstl3keep, p0, \[x0, z0.d, sxtw #1\]
-+[^:]+: c460200c prfh pstl3keep, p0, \[x0, z0.d, sxtw #1\]
-+[^:]+: c460200d prfh pstl3strm, p0, \[x0, z0.d, sxtw #1\]
-+[^:]+: c460200d prfh pstl3strm, p0, \[x0, z0.d, sxtw #1\]
-+[^:]+: c46020+e prfh #14, p0, \[x0, z0.d, sxtw #1\]
-+[^:]+: c46020+e prfh #14, p0, \[x0, z0.d, sxtw #1\]
-+[^:]+: c460200f prfh #15, p0, \[x0, z0.d, sxtw #1\]
-+[^:]+: c460200f prfh #15, p0, \[x0, z0.d, sxtw #1\]
-+[^:]+: c4602800 prfh pldl1keep, p2, \[x0, z0.d, sxtw #1\]
-+[^:]+: c4602800 prfh pldl1keep, p2, \[x0, z0.d, sxtw #1\]
-+[^:]+: c4603c00 prfh pldl1keep, p7, \[x0, z0.d, sxtw #1\]
-+[^:]+: c4603c00 prfh pldl1keep, p7, \[x0, z0.d, sxtw #1\]
-+[^:]+: c4602060 prfh pldl1keep, p0, \[x3, z0.d, sxtw #1\]
-+[^:]+: c4602060 prfh pldl1keep, p0, \[x3, z0.d, sxtw #1\]
-+[^:]+: c46023e0 prfh pldl1keep, p0, \[sp, z0.d, sxtw #1\]
-+[^:]+: c46023e0 prfh pldl1keep, p0, \[sp, z0.d, sxtw #1\]
-+[^:]+: c4642000 prfh pldl1keep, p0, \[x0, z4.d, sxtw #1\]
-+[^:]+: c4642000 prfh pldl1keep, p0, \[x0, z4.d, sxtw #1\]
-+[^:]+: c47f2000 prfh pldl1keep, p0, \[x0, z31.d, sxtw #1\]
-+[^:]+: c47f2000 prfh pldl1keep, p0, \[x0, z31.d, sxtw #1\]
-+[^:]+: c460a000 prfh pldl1keep, p0, \[x0, z0.d, lsl #1\]
-+[^:]+: c460a000 prfh pldl1keep, p0, \[x0, z0.d, lsl #1\]
-+[^:]+: c460a001 prfh pldl1strm, p0, \[x0, z0.d, lsl #1\]
-+[^:]+: c460a001 prfh pldl1strm, p0, \[x0, z0.d, lsl #1\]
-+[^:]+: c460a002 prfh pldl2keep, p0, \[x0, z0.d, lsl #1\]
-+[^:]+: c460a002 prfh pldl2keep, p0, \[x0, z0.d, lsl #1\]
-+[^:]+: c460a003 prfh pldl2strm, p0, \[x0, z0.d, lsl #1\]
-+[^:]+: c460a003 prfh pldl2strm, p0, \[x0, z0.d, lsl #1\]
-+[^:]+: c460a004 prfh pldl3keep, p0, \[x0, z0.d, lsl #1\]
-+[^:]+: c460a004 prfh pldl3keep, p0, \[x0, z0.d, lsl #1\]
-+[^:]+: c460a005 prfh pldl3strm, p0, \[x0, z0.d, lsl #1\]
-+[^:]+: c460a005 prfh pldl3strm, p0, \[x0, z0.d, lsl #1\]
-+[^:]+: c460a006 prfh #6, p0, \[x0, z0.d, lsl #1\]
-+[^:]+: c460a006 prfh #6, p0, \[x0, z0.d, lsl #1\]
-+[^:]+: c460a007 prfh #7, p0, \[x0, z0.d, lsl #1\]
-+[^:]+: c460a007 prfh #7, p0, \[x0, z0.d, lsl #1\]
-+[^:]+: c460a008 prfh pstl1keep, p0, \[x0, z0.d, lsl #1\]
-+[^:]+: c460a008 prfh pstl1keep, p0, \[x0, z0.d, lsl #1\]
-+[^:]+: c460a009 prfh pstl1strm, p0, \[x0, z0.d, lsl #1\]
-+[^:]+: c460a009 prfh pstl1strm, p0, \[x0, z0.d, lsl #1\]
-+[^:]+: c460a00a prfh pstl2keep, p0, \[x0, z0.d, lsl #1\]
-+[^:]+: c460a00a prfh pstl2keep, p0, \[x0, z0.d, lsl #1\]
-+[^:]+: c460a00b prfh pstl2strm, p0, \[x0, z0.d, lsl #1\]
-+[^:]+: c460a00b prfh pstl2strm, p0, \[x0, z0.d, lsl #1\]
-+[^:]+: c460a00c prfh pstl3keep, p0, \[x0, z0.d, lsl #1\]
-+[^:]+: c460a00c prfh pstl3keep, p0, \[x0, z0.d, lsl #1\]
-+[^:]+: c460a00d prfh pstl3strm, p0, \[x0, z0.d, lsl #1\]
-+[^:]+: c460a00d prfh pstl3strm, p0, \[x0, z0.d, lsl #1\]
-+[^:]+: c460a0+e prfh #14, p0, \[x0, z0.d, lsl #1\]
-+[^:]+: c460a0+e prfh #14, p0, \[x0, z0.d, lsl #1\]
-+[^:]+: c460a00f prfh #15, p0, \[x0, z0.d, lsl #1\]
-+[^:]+: c460a00f prfh #15, p0, \[x0, z0.d, lsl #1\]
-+[^:]+: c460a800 prfh pldl1keep, p2, \[x0, z0.d, lsl #1\]
-+[^:]+: c460a800 prfh pldl1keep, p2, \[x0, z0.d, lsl #1\]
-+[^:]+: c460bc00 prfh pldl1keep, p7, \[x0, z0.d, lsl #1\]
-+[^:]+: c460bc00 prfh pldl1keep, p7, \[x0, z0.d, lsl #1\]
-+[^:]+: c460a060 prfh pldl1keep, p0, \[x3, z0.d, lsl #1\]
-+[^:]+: c460a060 prfh pldl1keep, p0, \[x3, z0.d, lsl #1\]
-+[^:]+: c460a3e0 prfh pldl1keep, p0, \[sp, z0.d, lsl #1\]
-+[^:]+: c460a3e0 prfh pldl1keep, p0, \[sp, z0.d, lsl #1\]
-+[^:]+: c464a000 prfh pldl1keep, p0, \[x0, z4.d, lsl #1\]
-+[^:]+: c464a000 prfh pldl1keep, p0, \[x0, z4.d, lsl #1\]
-+[^:]+: c47fa000 prfh pldl1keep, p0, \[x0, z31.d, lsl #1\]
-+[^:]+: c47fa000 prfh pldl1keep, p0, \[x0, z31.d, lsl #1\]
-+[^:]+: 8480e000 prfh pldl1keep, p0, \[z0.s\]
-+[^:]+: 8480e000 prfh pldl1keep, p0, \[z0.s\]
-+[^:]+: 8480e000 prfh pldl1keep, p0, \[z0.s\]
-+[^:]+: 8480e001 prfh pldl1strm, p0, \[z0.s\]
-+[^:]+: 8480e001 prfh pldl1strm, p0, \[z0.s\]
-+[^:]+: 8480e001 prfh pldl1strm, p0, \[z0.s\]
-+[^:]+: 8480e002 prfh pldl2keep, p0, \[z0.s\]
-+[^:]+: 8480e002 prfh pldl2keep, p0, \[z0.s\]
-+[^:]+: 8480e002 prfh pldl2keep, p0, \[z0.s\]
-+[^:]+: 8480e003 prfh pldl2strm, p0, \[z0.s\]
-+[^:]+: 8480e003 prfh pldl2strm, p0, \[z0.s\]
-+[^:]+: 8480e003 prfh pldl2strm, p0, \[z0.s\]
-+[^:]+: 8480e004 prfh pldl3keep, p0, \[z0.s\]
-+[^:]+: 8480e004 prfh pldl3keep, p0, \[z0.s\]
-+[^:]+: 8480e004 prfh pldl3keep, p0, \[z0.s\]
-+[^:]+: 8480e005 prfh pldl3strm, p0, \[z0.s\]
-+[^:]+: 8480e005 prfh pldl3strm, p0, \[z0.s\]
-+[^:]+: 8480e005 prfh pldl3strm, p0, \[z0.s\]
-+[^:]+: 8480e006 prfh #6, p0, \[z0.s\]
-+[^:]+: 8480e006 prfh #6, p0, \[z0.s\]
-+[^:]+: 8480e006 prfh #6, p0, \[z0.s\]
-+[^:]+: 8480e007 prfh #7, p0, \[z0.s\]
-+[^:]+: 8480e007 prfh #7, p0, \[z0.s\]
-+[^:]+: 8480e007 prfh #7, p0, \[z0.s\]
-+[^:]+: 8480e008 prfh pstl1keep, p0, \[z0.s\]
-+[^:]+: 8480e008 prfh pstl1keep, p0, \[z0.s\]
-+[^:]+: 8480e008 prfh pstl1keep, p0, \[z0.s\]
-+[^:]+: 8480e009 prfh pstl1strm, p0, \[z0.s\]
-+[^:]+: 8480e009 prfh pstl1strm, p0, \[z0.s\]
-+[^:]+: 8480e009 prfh pstl1strm, p0, \[z0.s\]
-+[^:]+: 8480e00a prfh pstl2keep, p0, \[z0.s\]
-+[^:]+: 8480e00a prfh pstl2keep, p0, \[z0.s\]
-+[^:]+: 8480e00a prfh pstl2keep, p0, \[z0.s\]
-+[^:]+: 8480e00b prfh pstl2strm, p0, \[z0.s\]
-+[^:]+: 8480e00b prfh pstl2strm, p0, \[z0.s\]
-+[^:]+: 8480e00b prfh pstl2strm, p0, \[z0.s\]
-+[^:]+: 8480e00c prfh pstl3keep, p0, \[z0.s\]
-+[^:]+: 8480e00c prfh pstl3keep, p0, \[z0.s\]
-+[^:]+: 8480e00c prfh pstl3keep, p0, \[z0.s\]
-+[^:]+: 8480e00d prfh pstl3strm, p0, \[z0.s\]
-+[^:]+: 8480e00d prfh pstl3strm, p0, \[z0.s\]
-+[^:]+: 8480e00d prfh pstl3strm, p0, \[z0.s\]
-+[^:]+: 8480e0+e prfh #14, p0, \[z0.s\]
-+[^:]+: 8480e0+e prfh #14, p0, \[z0.s\]
-+[^:]+: 8480e0+e prfh #14, p0, \[z0.s\]
-+[^:]+: 8480e00f prfh #15, p0, \[z0.s\]
-+[^:]+: 8480e00f prfh #15, p0, \[z0.s\]
-+[^:]+: 8480e00f prfh #15, p0, \[z0.s\]
-+[^:]+: 8480e800 prfh pldl1keep, p2, \[z0.s\]
-+[^:]+: 8480e800 prfh pldl1keep, p2, \[z0.s\]
-+[^:]+: 8480e800 prfh pldl1keep, p2, \[z0.s\]
-+[^:]+: 8480fc00 prfh pldl1keep, p7, \[z0.s\]
-+[^:]+: 8480fc00 prfh pldl1keep, p7, \[z0.s\]
-+[^:]+: 8480fc00 prfh pldl1keep, p7, \[z0.s\]
-+[^:]+: 8480e060 prfh pldl1keep, p0, \[z3.s\]
-+[^:]+: 8480e060 prfh pldl1keep, p0, \[z3.s\]
-+[^:]+: 8480e060 prfh pldl1keep, p0, \[z3.s\]
-+[^:]+: 8480e3e0 prfh pldl1keep, p0, \[z31.s\]
-+[^:]+: 8480e3e0 prfh pldl1keep, p0, \[z31.s\]
-+[^:]+: 8480e3e0 prfh pldl1keep, p0, \[z31.s\]
-+[^:]+: 848fe000 prfh pldl1keep, p0, \[z0.s, #30\]
-+[^:]+: 848fe000 prfh pldl1keep, p0, \[z0.s, #30\]
-+[^:]+: 8490e000 prfh pldl1keep, p0, \[z0.s, #32\]
-+[^:]+: 8490e000 prfh pldl1keep, p0, \[z0.s, #32\]
-+[^:]+: 8491e000 prfh pldl1keep, p0, \[z0.s, #34\]
-+[^:]+: 8491e000 prfh pldl1keep, p0, \[z0.s, #34\]
-+[^:]+: 849fe000 prfh pldl1keep, p0, \[z0.s, #62\]
-+[^:]+: 849fe000 prfh pldl1keep, p0, \[z0.s, #62\]
-+[^:]+: 85c02000 prfh pldl1keep, p0, \[x0\]
-+[^:]+: 85c02000 prfh pldl1keep, p0, \[x0\]
-+[^:]+: 85c02000 prfh pldl1keep, p0, \[x0\]
-+[^:]+: 85c02000 prfh pldl1keep, p0, \[x0\]
-+[^:]+: 85c02001 prfh pldl1strm, p0, \[x0\]
-+[^:]+: 85c02001 prfh pldl1strm, p0, \[x0\]
-+[^:]+: 85c02001 prfh pldl1strm, p0, \[x0\]
-+[^:]+: 85c02001 prfh pldl1strm, p0, \[x0\]
-+[^:]+: 85c02002 prfh pldl2keep, p0, \[x0\]
-+[^:]+: 85c02002 prfh pldl2keep, p0, \[x0\]
-+[^:]+: 85c02002 prfh pldl2keep, p0, \[x0\]
-+[^:]+: 85c02002 prfh pldl2keep, p0, \[x0\]
-+[^:]+: 85c02003 prfh pldl2strm, p0, \[x0\]
-+[^:]+: 85c02003 prfh pldl2strm, p0, \[x0\]
-+[^:]+: 85c02003 prfh pldl2strm, p0, \[x0\]
-+[^:]+: 85c02003 prfh pldl2strm, p0, \[x0\]
-+[^:]+: 85c02004 prfh pldl3keep, p0, \[x0\]
-+[^:]+: 85c02004 prfh pldl3keep, p0, \[x0\]
-+[^:]+: 85c02004 prfh pldl3keep, p0, \[x0\]
-+[^:]+: 85c02004 prfh pldl3keep, p0, \[x0\]
-+[^:]+: 85c02005 prfh pldl3strm, p0, \[x0\]
-+[^:]+: 85c02005 prfh pldl3strm, p0, \[x0\]
-+[^:]+: 85c02005 prfh pldl3strm, p0, \[x0\]
-+[^:]+: 85c02005 prfh pldl3strm, p0, \[x0\]
-+[^:]+: 85c02006 prfh #6, p0, \[x0\]
-+[^:]+: 85c02006 prfh #6, p0, \[x0\]
-+[^:]+: 85c02006 prfh #6, p0, \[x0\]
-+[^:]+: 85c02006 prfh #6, p0, \[x0\]
-+[^:]+: 85c02007 prfh #7, p0, \[x0\]
-+[^:]+: 85c02007 prfh #7, p0, \[x0\]
-+[^:]+: 85c02007 prfh #7, p0, \[x0\]
-+[^:]+: 85c02007 prfh #7, p0, \[x0\]
-+[^:]+: 85c02008 prfh pstl1keep, p0, \[x0\]
-+[^:]+: 85c02008 prfh pstl1keep, p0, \[x0\]
-+[^:]+: 85c02008 prfh pstl1keep, p0, \[x0\]
-+[^:]+: 85c02008 prfh pstl1keep, p0, \[x0\]
-+[^:]+: 85c02009 prfh pstl1strm, p0, \[x0\]
-+[^:]+: 85c02009 prfh pstl1strm, p0, \[x0\]
-+[^:]+: 85c02009 prfh pstl1strm, p0, \[x0\]
-+[^:]+: 85c02009 prfh pstl1strm, p0, \[x0\]
-+[^:]+: 85c0200a prfh pstl2keep, p0, \[x0\]
-+[^:]+: 85c0200a prfh pstl2keep, p0, \[x0\]
-+[^:]+: 85c0200a prfh pstl2keep, p0, \[x0\]
-+[^:]+: 85c0200a prfh pstl2keep, p0, \[x0\]
-+[^:]+: 85c0200b prfh pstl2strm, p0, \[x0\]
-+[^:]+: 85c0200b prfh pstl2strm, p0, \[x0\]
-+[^:]+: 85c0200b prfh pstl2strm, p0, \[x0\]
-+[^:]+: 85c0200b prfh pstl2strm, p0, \[x0\]
-+[^:]+: 85c0200c prfh pstl3keep, p0, \[x0\]
-+[^:]+: 85c0200c prfh pstl3keep, p0, \[x0\]
-+[^:]+: 85c0200c prfh pstl3keep, p0, \[x0\]
-+[^:]+: 85c0200c prfh pstl3keep, p0, \[x0\]
-+[^:]+: 85c0200d prfh pstl3strm, p0, \[x0\]
-+[^:]+: 85c0200d prfh pstl3strm, p0, \[x0\]
-+[^:]+: 85c0200d prfh pstl3strm, p0, \[x0\]
-+[^:]+: 85c0200d prfh pstl3strm, p0, \[x0\]
-+[^:]+: 85c020+e prfh #14, p0, \[x0\]
-+[^:]+: 85c020+e prfh #14, p0, \[x0\]
-+[^:]+: 85c020+e prfh #14, p0, \[x0\]
-+[^:]+: 85c020+e prfh #14, p0, \[x0\]
-+[^:]+: 85c0200f prfh #15, p0, \[x0\]
-+[^:]+: 85c0200f prfh #15, p0, \[x0\]
-+[^:]+: 85c0200f prfh #15, p0, \[x0\]
-+[^:]+: 85c0200f prfh #15, p0, \[x0\]
-+[^:]+: 85c02800 prfh pldl1keep, p2, \[x0\]
-+[^:]+: 85c02800 prfh pldl1keep, p2, \[x0\]
-+[^:]+: 85c02800 prfh pldl1keep, p2, \[x0\]
-+[^:]+: 85c02800 prfh pldl1keep, p2, \[x0\]
-+[^:]+: 85c03c00 prfh pldl1keep, p7, \[x0\]
-+[^:]+: 85c03c00 prfh pldl1keep, p7, \[x0\]
-+[^:]+: 85c03c00 prfh pldl1keep, p7, \[x0\]
-+[^:]+: 85c03c00 prfh pldl1keep, p7, \[x0\]
-+[^:]+: 85c02060 prfh pldl1keep, p0, \[x3\]
-+[^:]+: 85c02060 prfh pldl1keep, p0, \[x3\]
-+[^:]+: 85c02060 prfh pldl1keep, p0, \[x3\]
-+[^:]+: 85c02060 prfh pldl1keep, p0, \[x3\]
-+[^:]+: 85c023e0 prfh pldl1keep, p0, \[sp\]
-+[^:]+: 85c023e0 prfh pldl1keep, p0, \[sp\]
-+[^:]+: 85c023e0 prfh pldl1keep, p0, \[sp\]
-+[^:]+: 85c023e0 prfh pldl1keep, p0, \[sp\]
-+[^:]+: 85df2000 prfh pldl1keep, p0, \[x0, #31, mul vl\]
-+[^:]+: 85df2000 prfh pldl1keep, p0, \[x0, #31, mul vl\]
-+[^:]+: 85e02000 prfh pldl1keep, p0, \[x0, #-32, mul vl\]
-+[^:]+: 85e02000 prfh pldl1keep, p0, \[x0, #-32, mul vl\]
-+[^:]+: 85e12000 prfh pldl1keep, p0, \[x0, #-31, mul vl\]
-+[^:]+: 85e12000 prfh pldl1keep, p0, \[x0, #-31, mul vl\]
-+[^:]+: 85ff2000 prfh pldl1keep, p0, \[x0, #-1, mul vl\]
-+[^:]+: 85ff2000 prfh pldl1keep, p0, \[x0, #-1, mul vl\]
-+[^:]+: c480e000 prfh pldl1keep, p0, \[z0.d\]
-+[^:]+: c480e000 prfh pldl1keep, p0, \[z0.d\]
-+[^:]+: c480e000 prfh pldl1keep, p0, \[z0.d\]
-+[^:]+: c480e001 prfh pldl1strm, p0, \[z0.d\]
-+[^:]+: c480e001 prfh pldl1strm, p0, \[z0.d\]
-+[^:]+: c480e001 prfh pldl1strm, p0, \[z0.d\]
-+[^:]+: c480e002 prfh pldl2keep, p0, \[z0.d\]
-+[^:]+: c480e002 prfh pldl2keep, p0, \[z0.d\]
-+[^:]+: c480e002 prfh pldl2keep, p0, \[z0.d\]
-+[^:]+: c480e003 prfh pldl2strm, p0, \[z0.d\]
-+[^:]+: c480e003 prfh pldl2strm, p0, \[z0.d\]
-+[^:]+: c480e003 prfh pldl2strm, p0, \[z0.d\]
-+[^:]+: c480e004 prfh pldl3keep, p0, \[z0.d\]
-+[^:]+: c480e004 prfh pldl3keep, p0, \[z0.d\]
-+[^:]+: c480e004 prfh pldl3keep, p0, \[z0.d\]
-+[^:]+: c480e005 prfh pldl3strm, p0, \[z0.d\]
-+[^:]+: c480e005 prfh pldl3strm, p0, \[z0.d\]
-+[^:]+: c480e005 prfh pldl3strm, p0, \[z0.d\]
-+[^:]+: c480e006 prfh #6, p0, \[z0.d\]
-+[^:]+: c480e006 prfh #6, p0, \[z0.d\]
-+[^:]+: c480e006 prfh #6, p0, \[z0.d\]
-+[^:]+: c480e007 prfh #7, p0, \[z0.d\]
-+[^:]+: c480e007 prfh #7, p0, \[z0.d\]
-+[^:]+: c480e007 prfh #7, p0, \[z0.d\]
-+[^:]+: c480e008 prfh pstl1keep, p0, \[z0.d\]
-+[^:]+: c480e008 prfh pstl1keep, p0, \[z0.d\]
-+[^:]+: c480e008 prfh pstl1keep, p0, \[z0.d\]
-+[^:]+: c480e009 prfh pstl1strm, p0, \[z0.d\]
-+[^:]+: c480e009 prfh pstl1strm, p0, \[z0.d\]
-+[^:]+: c480e009 prfh pstl1strm, p0, \[z0.d\]
-+[^:]+: c480e00a prfh pstl2keep, p0, \[z0.d\]
-+[^:]+: c480e00a prfh pstl2keep, p0, \[z0.d\]
-+[^:]+: c480e00a prfh pstl2keep, p0, \[z0.d\]
-+[^:]+: c480e00b prfh pstl2strm, p0, \[z0.d\]
-+[^:]+: c480e00b prfh pstl2strm, p0, \[z0.d\]
-+[^:]+: c480e00b prfh pstl2strm, p0, \[z0.d\]
-+[^:]+: c480e00c prfh pstl3keep, p0, \[z0.d\]
-+[^:]+: c480e00c prfh pstl3keep, p0, \[z0.d\]
-+[^:]+: c480e00c prfh pstl3keep, p0, \[z0.d\]
-+[^:]+: c480e00d prfh pstl3strm, p0, \[z0.d\]
-+[^:]+: c480e00d prfh pstl3strm, p0, \[z0.d\]
-+[^:]+: c480e00d prfh pstl3strm, p0, \[z0.d\]
-+[^:]+: c480e0+e prfh #14, p0, \[z0.d\]
-+[^:]+: c480e0+e prfh #14, p0, \[z0.d\]
-+[^:]+: c480e0+e prfh #14, p0, \[z0.d\]
-+[^:]+: c480e00f prfh #15, p0, \[z0.d\]
-+[^:]+: c480e00f prfh #15, p0, \[z0.d\]
-+[^:]+: c480e00f prfh #15, p0, \[z0.d\]
-+[^:]+: c480e800 prfh pldl1keep, p2, \[z0.d\]
-+[^:]+: c480e800 prfh pldl1keep, p2, \[z0.d\]
-+[^:]+: c480e800 prfh pldl1keep, p2, \[z0.d\]
-+[^:]+: c480fc00 prfh pldl1keep, p7, \[z0.d\]
-+[^:]+: c480fc00 prfh pldl1keep, p7, \[z0.d\]
-+[^:]+: c480fc00 prfh pldl1keep, p7, \[z0.d\]
-+[^:]+: c480e060 prfh pldl1keep, p0, \[z3.d\]
-+[^:]+: c480e060 prfh pldl1keep, p0, \[z3.d\]
-+[^:]+: c480e060 prfh pldl1keep, p0, \[z3.d\]
-+[^:]+: c480e3e0 prfh pldl1keep, p0, \[z31.d\]
-+[^:]+: c480e3e0 prfh pldl1keep, p0, \[z31.d\]
-+[^:]+: c480e3e0 prfh pldl1keep, p0, \[z31.d\]
-+[^:]+: c48fe000 prfh pldl1keep, p0, \[z0.d, #30\]
-+[^:]+: c48fe000 prfh pldl1keep, p0, \[z0.d, #30\]
-+[^:]+: c490e000 prfh pldl1keep, p0, \[z0.d, #32\]
-+[^:]+: c490e000 prfh pldl1keep, p0, \[z0.d, #32\]
-+[^:]+: c491e000 prfh pldl1keep, p0, \[z0.d, #34\]
-+[^:]+: c491e000 prfh pldl1keep, p0, \[z0.d, #34\]
-+[^:]+: c49fe000 prfh pldl1keep, p0, \[z0.d, #62\]
-+[^:]+: c49fe000 prfh pldl1keep, p0, \[z0.d, #62\]
-+[^:]+: 84204000 prfw pldl1keep, p0, \[x0, z0.s, uxtw #2\]
-+[^:]+: 84204000 prfw pldl1keep, p0, \[x0, z0.s, uxtw #2\]
-+[^:]+: 84204001 prfw pldl1strm, p0, \[x0, z0.s, uxtw #2\]
-+[^:]+: 84204001 prfw pldl1strm, p0, \[x0, z0.s, uxtw #2\]
-+[^:]+: 84204002 prfw pldl2keep, p0, \[x0, z0.s, uxtw #2\]
-+[^:]+: 84204002 prfw pldl2keep, p0, \[x0, z0.s, uxtw #2\]
-+[^:]+: 84204003 prfw pldl2strm, p0, \[x0, z0.s, uxtw #2\]
-+[^:]+: 84204003 prfw pldl2strm, p0, \[x0, z0.s, uxtw #2\]
-+[^:]+: 84204004 prfw pldl3keep, p0, \[x0, z0.s, uxtw #2\]
-+[^:]+: 84204004 prfw pldl3keep, p0, \[x0, z0.s, uxtw #2\]
-+[^:]+: 84204005 prfw pldl3strm, p0, \[x0, z0.s, uxtw #2\]
-+[^:]+: 84204005 prfw pldl3strm, p0, \[x0, z0.s, uxtw #2\]
-+[^:]+: 84204006 prfw #6, p0, \[x0, z0.s, uxtw #2\]
-+[^:]+: 84204006 prfw #6, p0, \[x0, z0.s, uxtw #2\]
-+[^:]+: 84204007 prfw #7, p0, \[x0, z0.s, uxtw #2\]
-+[^:]+: 84204007 prfw #7, p0, \[x0, z0.s, uxtw #2\]
-+[^:]+: 84204008 prfw pstl1keep, p0, \[x0, z0.s, uxtw #2\]
-+[^:]+: 84204008 prfw pstl1keep, p0, \[x0, z0.s, uxtw #2\]
-+[^:]+: 84204009 prfw pstl1strm, p0, \[x0, z0.s, uxtw #2\]
-+[^:]+: 84204009 prfw pstl1strm, p0, \[x0, z0.s, uxtw #2\]
-+[^:]+: 8420400a prfw pstl2keep, p0, \[x0, z0.s, uxtw #2\]
-+[^:]+: 8420400a prfw pstl2keep, p0, \[x0, z0.s, uxtw #2\]
-+[^:]+: 8420400b prfw pstl2strm, p0, \[x0, z0.s, uxtw #2\]
-+[^:]+: 8420400b prfw pstl2strm, p0, \[x0, z0.s, uxtw #2\]
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-+[^:]+: 8420400c prfw pstl3keep, p0, \[x0, z0.s, uxtw #2\]
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-+[^:]+: 8420400d prfw pstl3strm, p0, \[x0, z0.s, uxtw #2\]
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-+[^:]+: 84204800 prfw pldl1keep, p2, \[x0, z0.s, uxtw #2\]
-+[^:]+: 84204800 prfw pldl1keep, p2, \[x0, z0.s, uxtw #2\]
-+[^:]+: 84205c00 prfw pldl1keep, p7, \[x0, z0.s, uxtw #2\]
-+[^:]+: 84205c00 prfw pldl1keep, p7, \[x0, z0.s, uxtw #2\]
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-+[^:]+: 84204060 prfw pldl1keep, p0, \[x3, z0.s, uxtw #2\]
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-+[^:]+: 842043e0 prfw pldl1keep, p0, \[sp, z0.s, uxtw #2\]
-+[^:]+: 84244000 prfw pldl1keep, p0, \[x0, z4.s, uxtw #2\]
-+[^:]+: 84244000 prfw pldl1keep, p0, \[x0, z4.s, uxtw #2\]
-+[^:]+: 843f4000 prfw pldl1keep, p0, \[x0, z31.s, uxtw #2\]
-+[^:]+: 843f4000 prfw pldl1keep, p0, \[x0, z31.s, uxtw #2\]
-+[^:]+: 84604000 prfw pldl1keep, p0, \[x0, z0.s, sxtw #2\]
-+[^:]+: 84604000 prfw pldl1keep, p0, \[x0, z0.s, sxtw #2\]
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-+[^:]+: c460c008 prfw pstl1keep, p0, \[x0, z0.d, lsl #2\]
-+[^:]+: c460c009 prfw pstl1strm, p0, \[x0, z0.d, lsl #2\]
-+[^:]+: c460c009 prfw pstl1strm, p0, \[x0, z0.d, lsl #2\]
-+[^:]+: c460c00a prfw pstl2keep, p0, \[x0, z0.d, lsl #2\]
-+[^:]+: c460c00a prfw pstl2keep, p0, \[x0, z0.d, lsl #2\]
-+[^:]+: c460c00b prfw pstl2strm, p0, \[x0, z0.d, lsl #2\]
-+[^:]+: c460c00b prfw pstl2strm, p0, \[x0, z0.d, lsl #2\]
-+[^:]+: c460c00c prfw pstl3keep, p0, \[x0, z0.d, lsl #2\]
-+[^:]+: c460c00c prfw pstl3keep, p0, \[x0, z0.d, lsl #2\]
-+[^:]+: c460c00d prfw pstl3strm, p0, \[x0, z0.d, lsl #2\]
-+[^:]+: c460c00d prfw pstl3strm, p0, \[x0, z0.d, lsl #2\]
-+[^:]+: c460c0+e prfw #14, p0, \[x0, z0.d, lsl #2\]
-+[^:]+: c460c0+e prfw #14, p0, \[x0, z0.d, lsl #2\]
-+[^:]+: c460c00f prfw #15, p0, \[x0, z0.d, lsl #2\]
-+[^:]+: c460c00f prfw #15, p0, \[x0, z0.d, lsl #2\]
-+[^:]+: c460c800 prfw pldl1keep, p2, \[x0, z0.d, lsl #2\]
-+[^:]+: c460c800 prfw pldl1keep, p2, \[x0, z0.d, lsl #2\]
-+[^:]+: c460dc00 prfw pldl1keep, p7, \[x0, z0.d, lsl #2\]
-+[^:]+: c460dc00 prfw pldl1keep, p7, \[x0, z0.d, lsl #2\]
-+[^:]+: c460c060 prfw pldl1keep, p0, \[x3, z0.d, lsl #2\]
-+[^:]+: c460c060 prfw pldl1keep, p0, \[x3, z0.d, lsl #2\]
-+[^:]+: c460c3e0 prfw pldl1keep, p0, \[sp, z0.d, lsl #2\]
-+[^:]+: c460c3e0 prfw pldl1keep, p0, \[sp, z0.d, lsl #2\]
-+[^:]+: c464c000 prfw pldl1keep, p0, \[x0, z4.d, lsl #2\]
-+[^:]+: c464c000 prfw pldl1keep, p0, \[x0, z4.d, lsl #2\]
-+[^:]+: c47fc000 prfw pldl1keep, p0, \[x0, z31.d, lsl #2\]
-+[^:]+: c47fc000 prfw pldl1keep, p0, \[x0, z31.d, lsl #2\]
-+[^:]+: 850+e000 prfw pldl1keep, p0, \[z0.s\]
-+[^:]+: 850+e000 prfw pldl1keep, p0, \[z0.s\]
-+[^:]+: 850+e000 prfw pldl1keep, p0, \[z0.s\]
-+[^:]+: 850+e001 prfw pldl1strm, p0, \[z0.s\]
-+[^:]+: 850+e001 prfw pldl1strm, p0, \[z0.s\]
-+[^:]+: 850+e001 prfw pldl1strm, p0, \[z0.s\]
-+[^:]+: 850+e002 prfw pldl2keep, p0, \[z0.s\]
-+[^:]+: 850+e002 prfw pldl2keep, p0, \[z0.s\]
-+[^:]+: 850+e002 prfw pldl2keep, p0, \[z0.s\]
-+[^:]+: 850+e003 prfw pldl2strm, p0, \[z0.s\]
-+[^:]+: 850+e003 prfw pldl2strm, p0, \[z0.s\]
-+[^:]+: 850+e003 prfw pldl2strm, p0, \[z0.s\]
-+[^:]+: 850+e004 prfw pldl3keep, p0, \[z0.s\]
-+[^:]+: 850+e004 prfw pldl3keep, p0, \[z0.s\]
-+[^:]+: 850+e004 prfw pldl3keep, p0, \[z0.s\]
-+[^:]+: 850+e005 prfw pldl3strm, p0, \[z0.s\]
-+[^:]+: 850+e005 prfw pldl3strm, p0, \[z0.s\]
-+[^:]+: 850+e005 prfw pldl3strm, p0, \[z0.s\]
-+[^:]+: 850+e006 prfw #6, p0, \[z0.s\]
-+[^:]+: 850+e006 prfw #6, p0, \[z0.s\]
-+[^:]+: 850+e006 prfw #6, p0, \[z0.s\]
-+[^:]+: 850+e007 prfw #7, p0, \[z0.s\]
-+[^:]+: 850+e007 prfw #7, p0, \[z0.s\]
-+[^:]+: 850+e007 prfw #7, p0, \[z0.s\]
-+[^:]+: 850+e008 prfw pstl1keep, p0, \[z0.s\]
-+[^:]+: 850+e008 prfw pstl1keep, p0, \[z0.s\]
-+[^:]+: 850+e008 prfw pstl1keep, p0, \[z0.s\]
-+[^:]+: 850+e009 prfw pstl1strm, p0, \[z0.s\]
-+[^:]+: 850+e009 prfw pstl1strm, p0, \[z0.s\]
-+[^:]+: 850+e009 prfw pstl1strm, p0, \[z0.s\]
-+[^:]+: 850+e00a prfw pstl2keep, p0, \[z0.s\]
-+[^:]+: 850+e00a prfw pstl2keep, p0, \[z0.s\]
-+[^:]+: 850+e00a prfw pstl2keep, p0, \[z0.s\]
-+[^:]+: 850+e00b prfw pstl2strm, p0, \[z0.s\]
-+[^:]+: 850+e00b prfw pstl2strm, p0, \[z0.s\]
-+[^:]+: 850+e00b prfw pstl2strm, p0, \[z0.s\]
-+[^:]+: 850+e00c prfw pstl3keep, p0, \[z0.s\]
-+[^:]+: 850+e00c prfw pstl3keep, p0, \[z0.s\]
-+[^:]+: 850+e00c prfw pstl3keep, p0, \[z0.s\]
-+[^:]+: 850+e00d prfw pstl3strm, p0, \[z0.s\]
-+[^:]+: 850+e00d prfw pstl3strm, p0, \[z0.s\]
-+[^:]+: 850+e00d prfw pstl3strm, p0, \[z0.s\]
-+[^:]+: 850+e0+e prfw #14, p0, \[z0.s\]
-+[^:]+: 850+e0+e prfw #14, p0, \[z0.s\]
-+[^:]+: 850+e0+e prfw #14, p0, \[z0.s\]
-+[^:]+: 850+e00f prfw #15, p0, \[z0.s\]
-+[^:]+: 850+e00f prfw #15, p0, \[z0.s\]
-+[^:]+: 850+e00f prfw #15, p0, \[z0.s\]
-+[^:]+: 850+e800 prfw pldl1keep, p2, \[z0.s\]
-+[^:]+: 850+e800 prfw pldl1keep, p2, \[z0.s\]
-+[^:]+: 850+e800 prfw pldl1keep, p2, \[z0.s\]
-+[^:]+: 8500fc00 prfw pldl1keep, p7, \[z0.s\]
-+[^:]+: 8500fc00 prfw pldl1keep, p7, \[z0.s\]
-+[^:]+: 8500fc00 prfw pldl1keep, p7, \[z0.s\]
-+[^:]+: 850+e060 prfw pldl1keep, p0, \[z3.s\]
-+[^:]+: 850+e060 prfw pldl1keep, p0, \[z3.s\]
-+[^:]+: 850+e060 prfw pldl1keep, p0, \[z3.s\]
-+[^:]+: 850+e3e0 prfw pldl1keep, p0, \[z31.s\]
-+[^:]+: 850+e3e0 prfw pldl1keep, p0, \[z31.s\]
-+[^:]+: 850+e3e0 prfw pldl1keep, p0, \[z31.s\]
-+[^:]+: 850fe000 prfw pldl1keep, p0, \[z0.s, #60\]
-+[^:]+: 850fe000 prfw pldl1keep, p0, \[z0.s, #60\]
-+[^:]+: 8510e000 prfw pldl1keep, p0, \[z0.s, #64\]
-+[^:]+: 8510e000 prfw pldl1keep, p0, \[z0.s, #64\]
-+[^:]+: 8511e000 prfw pldl1keep, p0, \[z0.s, #68\]
-+[^:]+: 8511e000 prfw pldl1keep, p0, \[z0.s, #68\]
-+[^:]+: 851fe000 prfw pldl1keep, p0, \[z0.s, #124\]
-+[^:]+: 851fe000 prfw pldl1keep, p0, \[z0.s, #124\]
-+[^:]+: 85c04000 prfw pldl1keep, p0, \[x0\]
-+[^:]+: 85c04000 prfw pldl1keep, p0, \[x0\]
-+[^:]+: 85c04000 prfw pldl1keep, p0, \[x0\]
-+[^:]+: 85c04000 prfw pldl1keep, p0, \[x0\]
-+[^:]+: 85c04001 prfw pldl1strm, p0, \[x0\]
-+[^:]+: 85c04001 prfw pldl1strm, p0, \[x0\]
-+[^:]+: 85c04001 prfw pldl1strm, p0, \[x0\]
-+[^:]+: 85c04001 prfw pldl1strm, p0, \[x0\]
-+[^:]+: 85c04002 prfw pldl2keep, p0, \[x0\]
-+[^:]+: 85c04002 prfw pldl2keep, p0, \[x0\]
-+[^:]+: 85c04002 prfw pldl2keep, p0, \[x0\]
-+[^:]+: 85c04002 prfw pldl2keep, p0, \[x0\]
-+[^:]+: 85c04003 prfw pldl2strm, p0, \[x0\]
-+[^:]+: 85c04003 prfw pldl2strm, p0, \[x0\]
-+[^:]+: 85c04003 prfw pldl2strm, p0, \[x0\]
-+[^:]+: 85c04003 prfw pldl2strm, p0, \[x0\]
-+[^:]+: 85c04004 prfw pldl3keep, p0, \[x0\]
-+[^:]+: 85c04004 prfw pldl3keep, p0, \[x0\]
-+[^:]+: 85c04004 prfw pldl3keep, p0, \[x0\]
-+[^:]+: 85c04004 prfw pldl3keep, p0, \[x0\]
-+[^:]+: 85c04005 prfw pldl3strm, p0, \[x0\]
-+[^:]+: 85c04005 prfw pldl3strm, p0, \[x0\]
-+[^:]+: 85c04005 prfw pldl3strm, p0, \[x0\]
-+[^:]+: 85c04005 prfw pldl3strm, p0, \[x0\]
-+[^:]+: 85c04006 prfw #6, p0, \[x0\]
-+[^:]+: 85c04006 prfw #6, p0, \[x0\]
-+[^:]+: 85c04006 prfw #6, p0, \[x0\]
-+[^:]+: 85c04006 prfw #6, p0, \[x0\]
-+[^:]+: 85c04007 prfw #7, p0, \[x0\]
-+[^:]+: 85c04007 prfw #7, p0, \[x0\]
-+[^:]+: 85c04007 prfw #7, p0, \[x0\]
-+[^:]+: 85c04007 prfw #7, p0, \[x0\]
-+[^:]+: 85c04008 prfw pstl1keep, p0, \[x0\]
-+[^:]+: 85c04008 prfw pstl1keep, p0, \[x0\]
-+[^:]+: 85c04008 prfw pstl1keep, p0, \[x0\]
-+[^:]+: 85c04008 prfw pstl1keep, p0, \[x0\]
-+[^:]+: 85c04009 prfw pstl1strm, p0, \[x0\]
-+[^:]+: 85c04009 prfw pstl1strm, p0, \[x0\]
-+[^:]+: 85c04009 prfw pstl1strm, p0, \[x0\]
-+[^:]+: 85c04009 prfw pstl1strm, p0, \[x0\]
-+[^:]+: 85c0400a prfw pstl2keep, p0, \[x0\]
-+[^:]+: 85c0400a prfw pstl2keep, p0, \[x0\]
-+[^:]+: 85c0400a prfw pstl2keep, p0, \[x0\]
-+[^:]+: 85c0400a prfw pstl2keep, p0, \[x0\]
-+[^:]+: 85c0400b prfw pstl2strm, p0, \[x0\]
-+[^:]+: 85c0400b prfw pstl2strm, p0, \[x0\]
-+[^:]+: 85c0400b prfw pstl2strm, p0, \[x0\]
-+[^:]+: 85c0400b prfw pstl2strm, p0, \[x0\]
-+[^:]+: 85c0400c prfw pstl3keep, p0, \[x0\]
-+[^:]+: 85c0400c prfw pstl3keep, p0, \[x0\]
-+[^:]+: 85c0400c prfw pstl3keep, p0, \[x0\]
-+[^:]+: 85c0400c prfw pstl3keep, p0, \[x0\]
-+[^:]+: 85c0400d prfw pstl3strm, p0, \[x0\]
-+[^:]+: 85c0400d prfw pstl3strm, p0, \[x0\]
-+[^:]+: 85c0400d prfw pstl3strm, p0, \[x0\]
-+[^:]+: 85c0400d prfw pstl3strm, p0, \[x0\]
-+[^:]+: 85c040+e prfw #14, p0, \[x0\]
-+[^:]+: 85c040+e prfw #14, p0, \[x0\]
-+[^:]+: 85c040+e prfw #14, p0, \[x0\]
-+[^:]+: 85c040+e prfw #14, p0, \[x0\]
-+[^:]+: 85c0400f prfw #15, p0, \[x0\]
-+[^:]+: 85c0400f prfw #15, p0, \[x0\]
-+[^:]+: 85c0400f prfw #15, p0, \[x0\]
-+[^:]+: 85c0400f prfw #15, p0, \[x0\]
-+[^:]+: 85c04800 prfw pldl1keep, p2, \[x0\]
-+[^:]+: 85c04800 prfw pldl1keep, p2, \[x0\]
-+[^:]+: 85c04800 prfw pldl1keep, p2, \[x0\]
-+[^:]+: 85c04800 prfw pldl1keep, p2, \[x0\]
-+[^:]+: 85c05c00 prfw pldl1keep, p7, \[x0\]
-+[^:]+: 85c05c00 prfw pldl1keep, p7, \[x0\]
-+[^:]+: 85c05c00 prfw pldl1keep, p7, \[x0\]
-+[^:]+: 85c05c00 prfw pldl1keep, p7, \[x0\]
-+[^:]+: 85c04060 prfw pldl1keep, p0, \[x3\]
-+[^:]+: 85c04060 prfw pldl1keep, p0, \[x3\]
-+[^:]+: 85c04060 prfw pldl1keep, p0, \[x3\]
-+[^:]+: 85c04060 prfw pldl1keep, p0, \[x3\]
-+[^:]+: 85c043e0 prfw pldl1keep, p0, \[sp\]
-+[^:]+: 85c043e0 prfw pldl1keep, p0, \[sp\]
-+[^:]+: 85c043e0 prfw pldl1keep, p0, \[sp\]
-+[^:]+: 85c043e0 prfw pldl1keep, p0, \[sp\]
-+[^:]+: 85df4000 prfw pldl1keep, p0, \[x0, #31, mul vl\]
-+[^:]+: 85df4000 prfw pldl1keep, p0, \[x0, #31, mul vl\]
-+[^:]+: 85e04000 prfw pldl1keep, p0, \[x0, #-32, mul vl\]
-+[^:]+: 85e04000 prfw pldl1keep, p0, \[x0, #-32, mul vl\]
-+[^:]+: 85e14000 prfw pldl1keep, p0, \[x0, #-31, mul vl\]
-+[^:]+: 85e14000 prfw pldl1keep, p0, \[x0, #-31, mul vl\]
-+[^:]+: 85ff4000 prfw pldl1keep, p0, \[x0, #-1, mul vl\]
-+[^:]+: 85ff4000 prfw pldl1keep, p0, \[x0, #-1, mul vl\]
-+[^:]+: c50+e000 prfw pldl1keep, p0, \[z0.d\]
-+[^:]+: c50+e000 prfw pldl1keep, p0, \[z0.d\]
-+[^:]+: c50+e000 prfw pldl1keep, p0, \[z0.d\]
-+[^:]+: c50+e001 prfw pldl1strm, p0, \[z0.d\]
-+[^:]+: c50+e001 prfw pldl1strm, p0, \[z0.d\]
-+[^:]+: c50+e001 prfw pldl1strm, p0, \[z0.d\]
-+[^:]+: c50+e002 prfw pldl2keep, p0, \[z0.d\]
-+[^:]+: c50+e002 prfw pldl2keep, p0, \[z0.d\]
-+[^:]+: c50+e002 prfw pldl2keep, p0, \[z0.d\]
-+[^:]+: c50+e003 prfw pldl2strm, p0, \[z0.d\]
-+[^:]+: c50+e003 prfw pldl2strm, p0, \[z0.d\]
-+[^:]+: c50+e003 prfw pldl2strm, p0, \[z0.d\]
-+[^:]+: c50+e004 prfw pldl3keep, p0, \[z0.d\]
-+[^:]+: c50+e004 prfw pldl3keep, p0, \[z0.d\]
-+[^:]+: c50+e004 prfw pldl3keep, p0, \[z0.d\]
-+[^:]+: c50+e005 prfw pldl3strm, p0, \[z0.d\]
-+[^:]+: c50+e005 prfw pldl3strm, p0, \[z0.d\]
-+[^:]+: c50+e005 prfw pldl3strm, p0, \[z0.d\]
-+[^:]+: c50+e006 prfw #6, p0, \[z0.d\]
-+[^:]+: c50+e006 prfw #6, p0, \[z0.d\]
-+[^:]+: c50+e006 prfw #6, p0, \[z0.d\]
-+[^:]+: c50+e007 prfw #7, p0, \[z0.d\]
-+[^:]+: c50+e007 prfw #7, p0, \[z0.d\]
-+[^:]+: c50+e007 prfw #7, p0, \[z0.d\]
-+[^:]+: c50+e008 prfw pstl1keep, p0, \[z0.d\]
-+[^:]+: c50+e008 prfw pstl1keep, p0, \[z0.d\]
-+[^:]+: c50+e008 prfw pstl1keep, p0, \[z0.d\]
-+[^:]+: c50+e009 prfw pstl1strm, p0, \[z0.d\]
-+[^:]+: c50+e009 prfw pstl1strm, p0, \[z0.d\]
-+[^:]+: c50+e009 prfw pstl1strm, p0, \[z0.d\]
-+[^:]+: c50+e00a prfw pstl2keep, p0, \[z0.d\]
-+[^:]+: c50+e00a prfw pstl2keep, p0, \[z0.d\]
-+[^:]+: c50+e00a prfw pstl2keep, p0, \[z0.d\]
-+[^:]+: c50+e00b prfw pstl2strm, p0, \[z0.d\]
-+[^:]+: c50+e00b prfw pstl2strm, p0, \[z0.d\]
-+[^:]+: c50+e00b prfw pstl2strm, p0, \[z0.d\]
-+[^:]+: c50+e00c prfw pstl3keep, p0, \[z0.d\]
-+[^:]+: c50+e00c prfw pstl3keep, p0, \[z0.d\]
-+[^:]+: c50+e00c prfw pstl3keep, p0, \[z0.d\]
-+[^:]+: c50+e00d prfw pstl3strm, p0, \[z0.d\]
-+[^:]+: c50+e00d prfw pstl3strm, p0, \[z0.d\]
-+[^:]+: c50+e00d prfw pstl3strm, p0, \[z0.d\]
-+[^:]+: c50+e0+e prfw #14, p0, \[z0.d\]
-+[^:]+: c50+e0+e prfw #14, p0, \[z0.d\]
-+[^:]+: c50+e0+e prfw #14, p0, \[z0.d\]
-+[^:]+: c50+e00f prfw #15, p0, \[z0.d\]
-+[^:]+: c50+e00f prfw #15, p0, \[z0.d\]
-+[^:]+: c50+e00f prfw #15, p0, \[z0.d\]
-+[^:]+: c50+e800 prfw pldl1keep, p2, \[z0.d\]
-+[^:]+: c50+e800 prfw pldl1keep, p2, \[z0.d\]
-+[^:]+: c50+e800 prfw pldl1keep, p2, \[z0.d\]
-+[^:]+: c500fc00 prfw pldl1keep, p7, \[z0.d\]
-+[^:]+: c500fc00 prfw pldl1keep, p7, \[z0.d\]
-+[^:]+: c500fc00 prfw pldl1keep, p7, \[z0.d\]
-+[^:]+: c50+e060 prfw pldl1keep, p0, \[z3.d\]
-+[^:]+: c50+e060 prfw pldl1keep, p0, \[z3.d\]
-+[^:]+: c50+e060 prfw pldl1keep, p0, \[z3.d\]
-+[^:]+: c50+e3e0 prfw pldl1keep, p0, \[z31.d\]
-+[^:]+: c50+e3e0 prfw pldl1keep, p0, \[z31.d\]
-+[^:]+: c50+e3e0 prfw pldl1keep, p0, \[z31.d\]
-+[^:]+: c50fe000 prfw pldl1keep, p0, \[z0.d, #60\]
-+[^:]+: c50fe000 prfw pldl1keep, p0, \[z0.d, #60\]
-+[^:]+: c510e000 prfw pldl1keep, p0, \[z0.d, #64\]
-+[^:]+: c510e000 prfw pldl1keep, p0, \[z0.d, #64\]
-+[^:]+: c511e000 prfw pldl1keep, p0, \[z0.d, #68\]
-+[^:]+: c511e000 prfw pldl1keep, p0, \[z0.d, #68\]
-+[^:]+: c51fe000 prfw pldl1keep, p0, \[z0.d, #124\]
-+[^:]+: c51fe000 prfw pldl1keep, p0, \[z0.d, #124\]
-+[^:]+: 2550c000 ptest p0, p0.b
-+[^:]+: 2550c000 ptest p0, p0.b
-+[^:]+: 2550c400 ptest p1, p0.b
-+[^:]+: 2550c400 ptest p1, p0.b
-+[^:]+: 2550fc00 ptest p15, p0.b
-+[^:]+: 2550fc00 ptest p15, p0.b
-+[^:]+: 2550c040 ptest p0, p2.b
-+[^:]+: 2550c040 ptest p0, p2.b
-+[^:]+: 2550c1e0 ptest p0, p15.b
-+[^:]+: 2550c1e0 ptest p0, p15.b
-+[^:]+: 2518e000 ptrue p0.b, pow2
-+[^:]+: 2518e000 ptrue p0.b, pow2
-+[^:]+: 2518e001 ptrue p1.b, pow2
-+[^:]+: 2518e001 ptrue p1.b, pow2
-+[^:]+: 2518e00f ptrue p15.b, pow2
-+[^:]+: 2518e00f ptrue p15.b, pow2
-+[^:]+: 2518e020 ptrue p0.b, vl1
-+[^:]+: 2518e020 ptrue p0.b, vl1
-+[^:]+: 2518e040 ptrue p0.b, vl2
-+[^:]+: 2518e040 ptrue p0.b, vl2
-+[^:]+: 2518e060 ptrue p0.b, vl3
-+[^:]+: 2518e060 ptrue p0.b, vl3
-+[^:]+: 2518e080 ptrue p0.b, vl4
-+[^:]+: 2518e080 ptrue p0.b, vl4
-+[^:]+: 2518e0a0 ptrue p0.b, vl5
-+[^:]+: 2518e0a0 ptrue p0.b, vl5
-+[^:]+: 2518e0c0 ptrue p0.b, vl6
-+[^:]+: 2518e0c0 ptrue p0.b, vl6
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-+[^:]+: 6556a060 scvtf z0.h, p0/m, z3.d
-+[^:]+: 6556a3e0 scvtf z0.h, p0/m, z31.d
-+[^:]+: 6556a3e0 scvtf z0.h, p0/m, z31.d
-+[^:]+: 65d4a000 scvtf z0.s, p0/m, z0.d
-+[^:]+: 65d4a000 scvtf z0.s, p0/m, z0.d
-+[^:]+: 65d4a001 scvtf z1.s, p0/m, z0.d
-+[^:]+: 65d4a001 scvtf z1.s, p0/m, z0.d
-+[^:]+: 65d4a01f scvtf z31.s, p0/m, z0.d
-+[^:]+: 65d4a01f scvtf z31.s, p0/m, z0.d
-+[^:]+: 65d4a800 scvtf z0.s, p2/m, z0.d
-+[^:]+: 65d4a800 scvtf z0.s, p2/m, z0.d
-+[^:]+: 65d4bc00 scvtf z0.s, p7/m, z0.d
-+[^:]+: 65d4bc00 scvtf z0.s, p7/m, z0.d
-+[^:]+: 65d4a060 scvtf z0.s, p0/m, z3.d
-+[^:]+: 65d4a060 scvtf z0.s, p0/m, z3.d
-+[^:]+: 65d4a3e0 scvtf z0.s, p0/m, z31.d
-+[^:]+: 65d4a3e0 scvtf z0.s, p0/m, z31.d
-+[^:]+: 65d6a000 scvtf z0.d, p0/m, z0.d
-+[^:]+: 65d6a000 scvtf z0.d, p0/m, z0.d
-+[^:]+: 65d6a001 scvtf z1.d, p0/m, z0.d
-+[^:]+: 65d6a001 scvtf z1.d, p0/m, z0.d
-+[^:]+: 65d6a01f scvtf z31.d, p0/m, z0.d
-+[^:]+: 65d6a01f scvtf z31.d, p0/m, z0.d
-+[^:]+: 65d6a800 scvtf z0.d, p2/m, z0.d
-+[^:]+: 65d6a800 scvtf z0.d, p2/m, z0.d
-+[^:]+: 65d6bc00 scvtf z0.d, p7/m, z0.d
-+[^:]+: 65d6bc00 scvtf z0.d, p7/m, z0.d
-+[^:]+: 65d6a060 scvtf z0.d, p0/m, z3.d
-+[^:]+: 65d6a060 scvtf z0.d, p0/m, z3.d
-+[^:]+: 65d6a3e0 scvtf z0.d, p0/m, z31.d
-+[^:]+: 65d6a3e0 scvtf z0.d, p0/m, z31.d
-+[^:]+: 04940000 sdiv z0.s, p0/m, z0.s, z0.s
-+[^:]+: 04940000 sdiv z0.s, p0/m, z0.s, z0.s
-+[^:]+: 04940001 sdiv z1.s, p0/m, z1.s, z0.s
-+[^:]+: 04940001 sdiv z1.s, p0/m, z1.s, z0.s
-+[^:]+: 0494001f sdiv z31.s, p0/m, z31.s, z0.s
-+[^:]+: 0494001f sdiv z31.s, p0/m, z31.s, z0.s
-+[^:]+: 04940800 sdiv z0.s, p2/m, z0.s, z0.s
-+[^:]+: 04940800 sdiv z0.s, p2/m, z0.s, z0.s
-+[^:]+: 04941c00 sdiv z0.s, p7/m, z0.s, z0.s
-+[^:]+: 04941c00 sdiv z0.s, p7/m, z0.s, z0.s
-+[^:]+: 04940003 sdiv z3.s, p0/m, z3.s, z0.s
-+[^:]+: 04940003 sdiv z3.s, p0/m, z3.s, z0.s
-+[^:]+: 04940080 sdiv z0.s, p0/m, z0.s, z4.s
-+[^:]+: 04940080 sdiv z0.s, p0/m, z0.s, z4.s
-+[^:]+: 049403e0 sdiv z0.s, p0/m, z0.s, z31.s
-+[^:]+: 049403e0 sdiv z0.s, p0/m, z0.s, z31.s
-+[^:]+: 04d40000 sdiv z0.d, p0/m, z0.d, z0.d
-+[^:]+: 04d40000 sdiv z0.d, p0/m, z0.d, z0.d
-+[^:]+: 04d40001 sdiv z1.d, p0/m, z1.d, z0.d
-+[^:]+: 04d40001 sdiv z1.d, p0/m, z1.d, z0.d
-+[^:]+: 04d4001f sdiv z31.d, p0/m, z31.d, z0.d
-+[^:]+: 04d4001f sdiv z31.d, p0/m, z31.d, z0.d
-+[^:]+: 04d40800 sdiv z0.d, p2/m, z0.d, z0.d
-+[^:]+: 04d40800 sdiv z0.d, p2/m, z0.d, z0.d
-+[^:]+: 04d41c00 sdiv z0.d, p7/m, z0.d, z0.d
-+[^:]+: 04d41c00 sdiv z0.d, p7/m, z0.d, z0.d
-+[^:]+: 04d40003 sdiv z3.d, p0/m, z3.d, z0.d
-+[^:]+: 04d40003 sdiv z3.d, p0/m, z3.d, z0.d
-+[^:]+: 04d40080 sdiv z0.d, p0/m, z0.d, z4.d
-+[^:]+: 04d40080 sdiv z0.d, p0/m, z0.d, z4.d
-+[^:]+: 04d403e0 sdiv z0.d, p0/m, z0.d, z31.d
-+[^:]+: 04d403e0 sdiv z0.d, p0/m, z0.d, z31.d
-+[^:]+: 04960000 sdivr z0.s, p0/m, z0.s, z0.s
-+[^:]+: 04960000 sdivr z0.s, p0/m, z0.s, z0.s
-+[^:]+: 04960001 sdivr z1.s, p0/m, z1.s, z0.s
-+[^:]+: 04960001 sdivr z1.s, p0/m, z1.s, z0.s
-+[^:]+: 0496001f sdivr z31.s, p0/m, z31.s, z0.s
-+[^:]+: 0496001f sdivr z31.s, p0/m, z31.s, z0.s
-+[^:]+: 04960800 sdivr z0.s, p2/m, z0.s, z0.s
-+[^:]+: 04960800 sdivr z0.s, p2/m, z0.s, z0.s
-+[^:]+: 04961c00 sdivr z0.s, p7/m, z0.s, z0.s
-+[^:]+: 04961c00 sdivr z0.s, p7/m, z0.s, z0.s
-+[^:]+: 04960003 sdivr z3.s, p0/m, z3.s, z0.s
-+[^:]+: 04960003 sdivr z3.s, p0/m, z3.s, z0.s
-+[^:]+: 04960080 sdivr z0.s, p0/m, z0.s, z4.s
-+[^:]+: 04960080 sdivr z0.s, p0/m, z0.s, z4.s
-+[^:]+: 049603e0 sdivr z0.s, p0/m, z0.s, z31.s
-+[^:]+: 049603e0 sdivr z0.s, p0/m, z0.s, z31.s
-+[^:]+: 04d60000 sdivr z0.d, p0/m, z0.d, z0.d
-+[^:]+: 04d60000 sdivr z0.d, p0/m, z0.d, z0.d
-+[^:]+: 04d60001 sdivr z1.d, p0/m, z1.d, z0.d
-+[^:]+: 04d60001 sdivr z1.d, p0/m, z1.d, z0.d
-+[^:]+: 04d6001f sdivr z31.d, p0/m, z31.d, z0.d
-+[^:]+: 04d6001f sdivr z31.d, p0/m, z31.d, z0.d
-+[^:]+: 04d60800 sdivr z0.d, p2/m, z0.d, z0.d
-+[^:]+: 04d60800 sdivr z0.d, p2/m, z0.d, z0.d
-+[^:]+: 04d61c00 sdivr z0.d, p7/m, z0.d, z0.d
-+[^:]+: 04d61c00 sdivr z0.d, p7/m, z0.d, z0.d
-+[^:]+: 04d60003 sdivr z3.d, p0/m, z3.d, z0.d
-+[^:]+: 04d60003 sdivr z3.d, p0/m, z3.d, z0.d
-+[^:]+: 04d60080 sdivr z0.d, p0/m, z0.d, z4.d
-+[^:]+: 04d60080 sdivr z0.d, p0/m, z0.d, z4.d
-+[^:]+: 04d603e0 sdivr z0.d, p0/m, z0.d, z31.d
-+[^:]+: 04d603e0 sdivr z0.d, p0/m, z0.d, z31.d
-+[^:]+: 44800000 sdot z0.s, z0.b, z0.b
-+[^:]+: 44800000 sdot z0.s, z0.b, z0.b
-+[^:]+: 44800001 sdot z1.s, z0.b, z0.b
-+[^:]+: 44800001 sdot z1.s, z0.b, z0.b
-+[^:]+: 4480001f sdot z31.s, z0.b, z0.b
-+[^:]+: 4480001f sdot z31.s, z0.b, z0.b
-+[^:]+: 44800040 sdot z0.s, z2.b, z0.b
-+[^:]+: 44800040 sdot z0.s, z2.b, z0.b
-+[^:]+: 448003e0 sdot z0.s, z31.b, z0.b
-+[^:]+: 448003e0 sdot z0.s, z31.b, z0.b
-+[^:]+: 44830000 sdot z0.s, z0.b, z3.b
-+[^:]+: 44830000 sdot z0.s, z0.b, z3.b
-+[^:]+: 449f0000 sdot z0.s, z0.b, z31.b
-+[^:]+: 449f0000 sdot z0.s, z0.b, z31.b
-+[^:]+: 44c00000 sdot z0.d, z0.h, z0.h
-+[^:]+: 44c00000 sdot z0.d, z0.h, z0.h
-+[^:]+: 44c00001 sdot z1.d, z0.h, z0.h
-+[^:]+: 44c00001 sdot z1.d, z0.h, z0.h
-+[^:]+: 44c0001f sdot z31.d, z0.h, z0.h
-+[^:]+: 44c0001f sdot z31.d, z0.h, z0.h
-+[^:]+: 44c00040 sdot z0.d, z2.h, z0.h
-+[^:]+: 44c00040 sdot z0.d, z2.h, z0.h
-+[^:]+: 44c003e0 sdot z0.d, z31.h, z0.h
-+[^:]+: 44c003e0 sdot z0.d, z31.h, z0.h
-+[^:]+: 44c30000 sdot z0.d, z0.h, z3.h
-+[^:]+: 44c30000 sdot z0.d, z0.h, z3.h
-+[^:]+: 44df0000 sdot z0.d, z0.h, z31.h
-+[^:]+: 44df0000 sdot z0.d, z0.h, z31.h
-+[^:]+: 44a00000 sdot z0.s, z0.b, z0.b\[0\]
-+[^:]+: 44a00000 sdot z0.s, z0.b, z0.b\[0\]
-+[^:]+: 44a00001 sdot z1.s, z0.b, z0.b\[0\]
-+[^:]+: 44a00001 sdot z1.s, z0.b, z0.b\[0\]
-+[^:]+: 44a0001f sdot z31.s, z0.b, z0.b\[0\]
-+[^:]+: 44a0001f sdot z31.s, z0.b, z0.b\[0\]
-+[^:]+: 44a00040 sdot z0.s, z2.b, z0.b\[0\]
-+[^:]+: 44a00040 sdot z0.s, z2.b, z0.b\[0\]
-+[^:]+: 44a003e0 sdot z0.s, z31.b, z0.b\[0\]
-+[^:]+: 44a003e0 sdot z0.s, z31.b, z0.b\[0\]
-+[^:]+: 44a30000 sdot z0.s, z0.b, z3.b\[0\]
-+[^:]+: 44a30000 sdot z0.s, z0.b, z3.b\[0\]
-+[^:]+: 44a70000 sdot z0.s, z0.b, z7.b\[0\]
-+[^:]+: 44a70000 sdot z0.s, z0.b, z7.b\[0\]
-+[^:]+: 44a80000 sdot z0.s, z0.b, z0.b\[1\]
-+[^:]+: 44a80000 sdot z0.s, z0.b, z0.b\[1\]
-+[^:]+: 44ac0000 sdot z0.s, z0.b, z4.b\[1\]
-+[^:]+: 44ac0000 sdot z0.s, z0.b, z4.b\[1\]
-+[^:]+: 44b30000 sdot z0.s, z0.b, z3.b\[2\]
-+[^:]+: 44b30000 sdot z0.s, z0.b, z3.b\[2\]
-+[^:]+: 44b80000 sdot z0.s, z0.b, z0.b\[3\]
-+[^:]+: 44b80000 sdot z0.s, z0.b, z0.b\[3\]
-+[^:]+: 44bd0000 sdot z0.s, z0.b, z5.b\[3\]
-+[^:]+: 44bd0000 sdot z0.s, z0.b, z5.b\[3\]
-+[^:]+: 44e00000 sdot z0.d, z0.h, z0.h\[0\]
-+[^:]+: 44e00000 sdot z0.d, z0.h, z0.h\[0\]
-+[^:]+: 44e00001 sdot z1.d, z0.h, z0.h\[0\]
-+[^:]+: 44e00001 sdot z1.d, z0.h, z0.h\[0\]
-+[^:]+: 44e0001f sdot z31.d, z0.h, z0.h\[0\]
-+[^:]+: 44e0001f sdot z31.d, z0.h, z0.h\[0\]
-+[^:]+: 44e00040 sdot z0.d, z2.h, z0.h\[0\]
-+[^:]+: 44e00040 sdot z0.d, z2.h, z0.h\[0\]
-+[^:]+: 44e003e0 sdot z0.d, z31.h, z0.h\[0\]
-+[^:]+: 44e003e0 sdot z0.d, z31.h, z0.h\[0\]
-+[^:]+: 44e30000 sdot z0.d, z0.h, z3.h\[0\]
-+[^:]+: 44e30000 sdot z0.d, z0.h, z3.h\[0\]
-+[^:]+: 44ef0000 sdot z0.d, z0.h, z15.h\[0\]
-+[^:]+: 44ef0000 sdot z0.d, z0.h, z15.h\[0\]
-+[^:]+: 44f00000 sdot z0.d, z0.h, z0.h\[1\]
-+[^:]+: 44f00000 sdot z0.d, z0.h, z0.h\[1\]
-+[^:]+: 44fb0000 sdot z0.d, z0.h, z11.h\[1\]
-+[^:]+: 44fb0000 sdot z0.d, z0.h, z11.h\[1\]
-+[^:]+: 0520c000 mov z0.b, p0/m, z0.b
-+[^:]+: 0520c000 mov z0.b, p0/m, z0.b
-+[^:]+: 0520c001 sel z1.b, p0, z0.b, z0.b
-+[^:]+: 0520c001 sel z1.b, p0, z0.b, z0.b
-+[^:]+: 0520c01f sel z31.b, p0, z0.b, z0.b
-+[^:]+: 0520c01f sel z31.b, p0, z0.b, z0.b
-+[^:]+: 0520c800 mov z0.b, p2/m, z0.b
-+[^:]+: 0520c800 mov z0.b, p2/m, z0.b
-+[^:]+: 0520fc00 mov z0.b, p15/m, z0.b
-+[^:]+: 0520fc00 mov z0.b, p15/m, z0.b
-+[^:]+: 0520c060 mov z0.b, p0/m, z3.b
-+[^:]+: 0520c060 mov z0.b, p0/m, z3.b
-+[^:]+: 0520c3e0 mov z0.b, p0/m, z31.b
-+[^:]+: 0520c3e0 mov z0.b, p0/m, z31.b
-+[^:]+: 0524c000 sel z0.b, p0, z0.b, z4.b
-+[^:]+: 0524c000 sel z0.b, p0, z0.b, z4.b
-+[^:]+: 053fc000 sel z0.b, p0, z0.b, z31.b
-+[^:]+: 053fc000 sel z0.b, p0, z0.b, z31.b
-+[^:]+: 0560c000 mov z0.h, p0/m, z0.h
-+[^:]+: 0560c000 mov z0.h, p0/m, z0.h
-+[^:]+: 0560c001 sel z1.h, p0, z0.h, z0.h
-+[^:]+: 0560c001 sel z1.h, p0, z0.h, z0.h
-+[^:]+: 0560c01f sel z31.h, p0, z0.h, z0.h
-+[^:]+: 0560c01f sel z31.h, p0, z0.h, z0.h
-+[^:]+: 0560c800 mov z0.h, p2/m, z0.h
-+[^:]+: 0560c800 mov z0.h, p2/m, z0.h
-+[^:]+: 0560fc00 mov z0.h, p15/m, z0.h
-+[^:]+: 0560fc00 mov z0.h, p15/m, z0.h
-+[^:]+: 0560c060 mov z0.h, p0/m, z3.h
-+[^:]+: 0560c060 mov z0.h, p0/m, z3.h
-+[^:]+: 0560c3e0 mov z0.h, p0/m, z31.h
-+[^:]+: 0560c3e0 mov z0.h, p0/m, z31.h
-+[^:]+: 0564c000 sel z0.h, p0, z0.h, z4.h
-+[^:]+: 0564c000 sel z0.h, p0, z0.h, z4.h
-+[^:]+: 057fc000 sel z0.h, p0, z0.h, z31.h
-+[^:]+: 057fc000 sel z0.h, p0, z0.h, z31.h
-+[^:]+: 05a0c000 mov z0.s, p0/m, z0.s
-+[^:]+: 05a0c000 mov z0.s, p0/m, z0.s
-+[^:]+: 05a0c001 sel z1.s, p0, z0.s, z0.s
-+[^:]+: 05a0c001 sel z1.s, p0, z0.s, z0.s
-+[^:]+: 05a0c01f sel z31.s, p0, z0.s, z0.s
-+[^:]+: 05a0c01f sel z31.s, p0, z0.s, z0.s
-+[^:]+: 05a0c800 mov z0.s, p2/m, z0.s
-+[^:]+: 05a0c800 mov z0.s, p2/m, z0.s
-+[^:]+: 05a0fc00 mov z0.s, p15/m, z0.s
-+[^:]+: 05a0fc00 mov z0.s, p15/m, z0.s
-+[^:]+: 05a0c060 mov z0.s, p0/m, z3.s
-+[^:]+: 05a0c060 mov z0.s, p0/m, z3.s
-+[^:]+: 05a0c3e0 mov z0.s, p0/m, z31.s
-+[^:]+: 05a0c3e0 mov z0.s, p0/m, z31.s
-+[^:]+: 05a4c000 sel z0.s, p0, z0.s, z4.s
-+[^:]+: 05a4c000 sel z0.s, p0, z0.s, z4.s
-+[^:]+: 05bfc000 sel z0.s, p0, z0.s, z31.s
-+[^:]+: 05bfc000 sel z0.s, p0, z0.s, z31.s
-+[^:]+: 05e0c000 mov z0.d, p0/m, z0.d
-+[^:]+: 05e0c000 mov z0.d, p0/m, z0.d
-+[^:]+: 05e0c001 sel z1.d, p0, z0.d, z0.d
-+[^:]+: 05e0c001 sel z1.d, p0, z0.d, z0.d
-+[^:]+: 05e0c01f sel z31.d, p0, z0.d, z0.d
-+[^:]+: 05e0c01f sel z31.d, p0, z0.d, z0.d
-+[^:]+: 05e0c800 mov z0.d, p2/m, z0.d
-+[^:]+: 05e0c800 mov z0.d, p2/m, z0.d
-+[^:]+: 05e0fc00 mov z0.d, p15/m, z0.d
-+[^:]+: 05e0fc00 mov z0.d, p15/m, z0.d
-+[^:]+: 05e0c060 mov z0.d, p0/m, z3.d
-+[^:]+: 05e0c060 mov z0.d, p0/m, z3.d
-+[^:]+: 05e0c3e0 mov z0.d, p0/m, z31.d
-+[^:]+: 05e0c3e0 mov z0.d, p0/m, z31.d
-+[^:]+: 05e4c000 sel z0.d, p0, z0.d, z4.d
-+[^:]+: 05e4c000 sel z0.d, p0, z0.d, z4.d
-+[^:]+: 05ffc000 sel z0.d, p0, z0.d, z31.d
-+[^:]+: 05ffc000 sel z0.d, p0, z0.d, z31.d
-+[^:]+: 25004210 mov p0.b, p0/m, p0.b
-+[^:]+: 25004210 mov p0.b, p0/m, p0.b
-+[^:]+: 25004211 sel p1.b, p0, p0.b, p0.b
-+[^:]+: 25004211 sel p1.b, p0, p0.b, p0.b
-+[^:]+: 2500421f sel p15.b, p0, p0.b, p0.b
-+[^:]+: 2500421f sel p15.b, p0, p0.b, p0.b
-+[^:]+: 25004a10 mov p0.b, p2/m, p0.b
-+[^:]+: 25004a10 mov p0.b, p2/m, p0.b
-+[^:]+: 25007e10 mov p0.b, p15/m, p0.b
-+[^:]+: 25007e10 mov p0.b, p15/m, p0.b
-+[^:]+: 25004270 mov p0.b, p0/m, p3.b
-+[^:]+: 25004270 mov p0.b, p0/m, p3.b
-+[^:]+: 250043f0 mov p0.b, p0/m, p15.b
-+[^:]+: 250043f0 mov p0.b, p0/m, p15.b
-+[^:]+: 25044210 sel p0.b, p0, p0.b, p4.b
-+[^:]+: 25044210 sel p0.b, p0, p0.b, p4.b
-+[^:]+: 250f4210 sel p0.b, p0, p0.b, p15.b
-+[^:]+: 250f4210 sel p0.b, p0, p0.b, p15.b
-+[^:]+: 252c9000 setffr
-+[^:]+: 252c9000 setffr
-+[^:]+: 2528c000 smax z0.b, z0.b, #0
-+[^:]+: 2528c000 smax z0.b, z0.b, #0
-+[^:]+: 2528c001 smax z1.b, z1.b, #0
-+[^:]+: 2528c001 smax z1.b, z1.b, #0
-+[^:]+: 2528c01f smax z31.b, z31.b, #0
-+[^:]+: 2528c01f smax z31.b, z31.b, #0
-+[^:]+: 2528c002 smax z2.b, z2.b, #0
-+[^:]+: 2528c002 smax z2.b, z2.b, #0
-+[^:]+: 2528cfe0 smax z0.b, z0.b, #127
-+[^:]+: 2528cfe0 smax z0.b, z0.b, #127
-+[^:]+: 2528d000 smax z0.b, z0.b, #-128
-+[^:]+: 2528d000 smax z0.b, z0.b, #-128
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-+[^:]+: 2524d000 sqadd z0.b, z0.b, #128
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-+[^:]+: 2524d020 sqadd z0.b, z0.b, #129
-+[^:]+: 2524d020 sqadd z0.b, z0.b, #129
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-+[^:]+: 2524dfe0 sqadd z0.b, z0.b, #255
-+[^:]+: 2524dfe0 sqadd z0.b, z0.b, #255
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-+[^:]+: 2564c002 sqadd z2.h, z2.h, #0
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-+[^:]+: 2564cfe0 sqadd z0.h, z0.h, #127
-+[^:]+: 2564cfe0 sqadd z0.h, z0.h, #127
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-+[^:]+: 2564d000 sqadd z0.h, z0.h, #128
-+[^:]+: 2564d000 sqadd z0.h, z0.h, #128
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-+[^:]+: 2564d020 sqadd z0.h, z0.h, #129
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-+[^:]+: 2564dfe0 sqadd z0.h, z0.h, #255
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-+[^:]+: 2564e000 sqadd z0.h, z0.h, #0, lsl #8
-+[^:]+: 2564efe0 sqadd z0.h, z0.h, #32512
-+[^:]+: 2564efe0 sqadd z0.h, z0.h, #32512
-+[^:]+: 2564efe0 sqadd z0.h, z0.h, #32512
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-+[^:]+: 2564f000 sqadd z0.h, z0.h, #32768
-+[^:]+: 2564f000 sqadd z0.h, z0.h, #32768
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-+[^:]+: 2564f020 sqadd z0.h, z0.h, #33024
-+[^:]+: 2564f020 sqadd z0.h, z0.h, #33024
-+[^:]+: 2564f020 sqadd z0.h, z0.h, #33024
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-+[^:]+: 2564ffe0 sqadd z0.h, z0.h, #65280
-+[^:]+: 2564ffe0 sqadd z0.h, z0.h, #65280
-+[^:]+: 2564ffe0 sqadd z0.h, z0.h, #65280
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-+[^:]+: 25a4c000 sqadd z0.s, z0.s, #0
-+[^:]+: 25a4c000 sqadd z0.s, z0.s, #0
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-+[^:]+: 25a4cfe0 sqadd z0.s, z0.s, #127
-+[^:]+: 25a4cfe0 sqadd z0.s, z0.s, #127
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-+[^:]+: 25a4d000 sqadd z0.s, z0.s, #128
-+[^:]+: 25a4d000 sqadd z0.s, z0.s, #128
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-+[^:]+: 25a4d020 sqadd z0.s, z0.s, #129
-+[^:]+: 25a4d020 sqadd z0.s, z0.s, #129
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-+[^:]+: 25a4dfe0 sqadd z0.s, z0.s, #255
-+[^:]+: 25a4dfe0 sqadd z0.s, z0.s, #255
-+[^:]+: 25a4e000 sqadd z0.s, z0.s, #0, lsl #8
-+[^:]+: 25a4e000 sqadd z0.s, z0.s, #0, lsl #8
-+[^:]+: 25a4efe0 sqadd z0.s, z0.s, #32512
-+[^:]+: 25a4efe0 sqadd z0.s, z0.s, #32512
-+[^:]+: 25a4efe0 sqadd z0.s, z0.s, #32512
-+[^:]+: 25a4efe0 sqadd z0.s, z0.s, #32512
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-+[^:]+: 25a4f000 sqadd z0.s, z0.s, #32768
-+[^:]+: 25a4f000 sqadd z0.s, z0.s, #32768
-+[^:]+: 25a4f000 sqadd z0.s, z0.s, #32768
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-+[^:]+: 25a4f020 sqadd z0.s, z0.s, #33024
-+[^:]+: 25a4f020 sqadd z0.s, z0.s, #33024
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-+[^:]+: 25a4ffe0 sqadd z0.s, z0.s, #65280
-+[^:]+: 25a4ffe0 sqadd z0.s, z0.s, #65280
-+[^:]+: 25a4ffe0 sqadd z0.s, z0.s, #65280
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-+[^:]+: 25e4c000 sqadd z0.d, z0.d, #0
-+[^:]+: 25e4c000 sqadd z0.d, z0.d, #0
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-+[^:]+: 25e4c001 sqadd z1.d, z1.d, #0
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-+[^:]+: 25e4c01f sqadd z31.d, z31.d, #0
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-+[^:]+: 25e4c002 sqadd z2.d, z2.d, #0
-+[^:]+: 25e4c002 sqadd z2.d, z2.d, #0
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-+[^:]+: 25e4cfe0 sqadd z0.d, z0.d, #127
-+[^:]+: 25e4cfe0 sqadd z0.d, z0.d, #127
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-+[^:]+: 25e4d000 sqadd z0.d, z0.d, #128
-+[^:]+: 25e4d000 sqadd z0.d, z0.d, #128
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-+[^:]+: 25e4d020 sqadd z0.d, z0.d, #129
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-+[^:]+: 25e4dfe0 sqadd z0.d, z0.d, #255
-+[^:]+: 25e4dfe0 sqadd z0.d, z0.d, #255
-+[^:]+: 25e4e000 sqadd z0.d, z0.d, #0, lsl #8
-+[^:]+: 25e4e000 sqadd z0.d, z0.d, #0, lsl #8
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-+[^:]+: 25e4efe0 sqadd z0.d, z0.d, #32512
-+[^:]+: 25e4efe0 sqadd z0.d, z0.d, #32512
-+[^:]+: 25e4efe0 sqadd z0.d, z0.d, #32512
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-+[^:]+: 25e4f000 sqadd z0.d, z0.d, #32768
-+[^:]+: 25e4f000 sqadd z0.d, z0.d, #32768
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-+[^:]+: 25e4f020 sqadd z0.d, z0.d, #33024
-+[^:]+: 25e4f020 sqadd z0.d, z0.d, #33024
-+[^:]+: 25e4f020 sqadd z0.d, z0.d, #33024
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-+[^:]+: 25e4ffe0 sqadd z0.d, z0.d, #65280
-+[^:]+: 25e4ffe0 sqadd z0.d, z0.d, #65280
-+[^:]+: 0430f800 sqdecb x0, pow2
-+[^:]+: 0430f800 sqdecb x0, pow2
-+[^:]+: 0430f800 sqdecb x0, pow2
-+[^:]+: 0430f801 sqdecb x1, pow2
-+[^:]+: 0430f801 sqdecb x1, pow2
-+[^:]+: 0430f801 sqdecb x1, pow2
-+[^:]+: 0430f81f sqdecb xzr, pow2
-+[^:]+: 0430f81f sqdecb xzr, pow2
-+[^:]+: 0430f81f sqdecb xzr, pow2
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-+[^:]+: 0430f820 sqdecb x0, vl1
-+[^:]+: 0430f820 sqdecb x0, vl1
-+[^:]+: 0430f840 sqdecb x0, vl2
-+[^:]+: 0430f840 sqdecb x0, vl2
-+[^:]+: 0430f840 sqdecb x0, vl2
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-+[^:]+: 0430f860 sqdecb x0, vl3
-+[^:]+: 0430f860 sqdecb x0, vl3
-+[^:]+: 0430f880 sqdecb x0, vl4
-+[^:]+: 0430f880 sqdecb x0, vl4
-+[^:]+: 0430f880 sqdecb x0, vl4
-+[^:]+: 0430f8a0 sqdecb x0, vl5
-+[^:]+: 0430f8a0 sqdecb x0, vl5
-+[^:]+: 0430f8a0 sqdecb x0, vl5
-+[^:]+: 0430f8c0 sqdecb x0, vl6
-+[^:]+: 0430f8c0 sqdecb x0, vl6
-+[^:]+: 0430f8c0 sqdecb x0, vl6
-+[^:]+: 0430f8e0 sqdecb x0, vl7
-+[^:]+: 0430f8e0 sqdecb x0, vl7
-+[^:]+: 0430f8e0 sqdecb x0, vl7
-+[^:]+: 0430f900 sqdecb x0, vl8
-+[^:]+: 0430f900 sqdecb x0, vl8
-+[^:]+: 0430f900 sqdecb x0, vl8
-+[^:]+: 0430f920 sqdecb x0, vl16
-+[^:]+: 0430f920 sqdecb x0, vl16
-+[^:]+: 0430f920 sqdecb x0, vl16
-+[^:]+: 0430f940 sqdecb x0, vl32
-+[^:]+: 0430f940 sqdecb x0, vl32
-+[^:]+: 0430f940 sqdecb x0, vl32
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-+[^:]+: 0430f960 sqdecb x0, vl64
-+[^:]+: 0430f960 sqdecb x0, vl64
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-+[^:]+: 0430f980 sqdecb x0, vl128
-+[^:]+: 0430f980 sqdecb x0, vl128
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-+[^:]+: 0430f9a0 sqdecb x0, vl256
-+[^:]+: 0430f9a0 sqdecb x0, vl256
-+[^:]+: 0430f9c0 sqdecb x0, #14
-+[^:]+: 0430f9c0 sqdecb x0, #14
-+[^:]+: 0430f9c0 sqdecb x0, #14
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-+[^:]+: 0430f9e0 sqdecb x0, #15
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-+[^:]+: 0430fa40 sqdecb x0, #18
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-+[^:]+: 0430fa60 sqdecb x0, #19
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-+[^:]+: 0430fa80 sqdecb x0, #20
-+[^:]+: 0430fa80 sqdecb x0, #20
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-+[^:]+: 0430faa0 sqdecb x0, #21
-+[^:]+: 0430faa0 sqdecb x0, #21
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-+[^:]+: 0430fac0 sqdecb x0, #22
-+[^:]+: 0430fac0 sqdecb x0, #22
-+[^:]+: 0430fae0 sqdecb x0, #23
-+[^:]+: 0430fae0 sqdecb x0, #23
-+[^:]+: 0430fae0 sqdecb x0, #23
-+[^:]+: 0430fb00 sqdecb x0, #24
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-+[^:]+: 0430fb00 sqdecb x0, #24
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-+[^:]+: 0430fb20 sqdecb x0, #25
-+[^:]+: 0430fb20 sqdecb x0, #25
-+[^:]+: 0430fb40 sqdecb x0, #26
-+[^:]+: 0430fb40 sqdecb x0, #26
-+[^:]+: 0430fb40 sqdecb x0, #26
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-+[^:]+: 0430fb60 sqdecb x0, #27
-+[^:]+: 0430fb60 sqdecb x0, #27
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-+[^:]+: 0430fb80 sqdecb x0, #28
-+[^:]+: 0430fb80 sqdecb x0, #28
-+[^:]+: 0430fba0 sqdecb x0, mul4
-+[^:]+: 0430fba0 sqdecb x0, mul4
-+[^:]+: 0430fba0 sqdecb x0, mul4
-+[^:]+: 0430fbc0 sqdecb x0, mul3
-+[^:]+: 0430fbc0 sqdecb x0, mul3
-+[^:]+: 0430fbc0 sqdecb x0, mul3
-+[^:]+: 0430fbe0 sqdecb x0
-+[^:]+: 0430fbe0 sqdecb x0
-+[^:]+: 0430fbe0 sqdecb x0
-+[^:]+: 0430fbe0 sqdecb x0
-+[^:]+: 0437f800 sqdecb x0, pow2, mul #8
-+[^:]+: 0437f800 sqdecb x0, pow2, mul #8
-+[^:]+: 0438f800 sqdecb x0, pow2, mul #9
-+[^:]+: 0438f800 sqdecb x0, pow2, mul #9
-+[^:]+: 0439f800 sqdecb x0, pow2, mul #10
-+[^:]+: 0439f800 sqdecb x0, pow2, mul #10
-+[^:]+: 043ff800 sqdecb x0, pow2, mul #16
-+[^:]+: 043ff800 sqdecb x0, pow2, mul #16
-+[^:]+: 0420f800 sqdecb x0, w0, pow2
-+[^:]+: 0420f800 sqdecb x0, w0, pow2
-+[^:]+: 0420f800 sqdecb x0, w0, pow2
-+[^:]+: 0420f801 sqdecb x1, w1, pow2
-+[^:]+: 0420f801 sqdecb x1, w1, pow2
-+[^:]+: 0420f801 sqdecb x1, w1, pow2
-+[^:]+: 0420f81f sqdecb xzr, wzr, pow2
-+[^:]+: 0420f81f sqdecb xzr, wzr, pow2
-+[^:]+: 0420f81f sqdecb xzr, wzr, pow2
-+[^:]+: 0420f802 sqdecb x2, w2, pow2
-+[^:]+: 0420f802 sqdecb x2, w2, pow2
-+[^:]+: 0420f802 sqdecb x2, w2, pow2
-+[^:]+: 0420f820 sqdecb x0, w0, vl1
-+[^:]+: 0420f820 sqdecb x0, w0, vl1
-+[^:]+: 0420f820 sqdecb x0, w0, vl1
-+[^:]+: 0420f840 sqdecb x0, w0, vl2
-+[^:]+: 0420f840 sqdecb x0, w0, vl2
-+[^:]+: 0420f840 sqdecb x0, w0, vl2
-+[^:]+: 0420f860 sqdecb x0, w0, vl3
-+[^:]+: 0420f860 sqdecb x0, w0, vl3
-+[^:]+: 0420f860 sqdecb x0, w0, vl3
-+[^:]+: 0420f880 sqdecb x0, w0, vl4
-+[^:]+: 0420f880 sqdecb x0, w0, vl4
-+[^:]+: 0420f880 sqdecb x0, w0, vl4
-+[^:]+: 0420f8a0 sqdecb x0, w0, vl5
-+[^:]+: 0420f8a0 sqdecb x0, w0, vl5
-+[^:]+: 0420f8a0 sqdecb x0, w0, vl5
-+[^:]+: 0420f8c0 sqdecb x0, w0, vl6
-+[^:]+: 0420f8c0 sqdecb x0, w0, vl6
-+[^:]+: 0420f8c0 sqdecb x0, w0, vl6
-+[^:]+: 0420f8e0 sqdecb x0, w0, vl7
-+[^:]+: 0420f8e0 sqdecb x0, w0, vl7
-+[^:]+: 0420f8e0 sqdecb x0, w0, vl7
-+[^:]+: 0420f900 sqdecb x0, w0, vl8
-+[^:]+: 0420f900 sqdecb x0, w0, vl8
-+[^:]+: 0420f900 sqdecb x0, w0, vl8
-+[^:]+: 0420f920 sqdecb x0, w0, vl16
-+[^:]+: 0420f920 sqdecb x0, w0, vl16
-+[^:]+: 0420f920 sqdecb x0, w0, vl16
-+[^:]+: 0420f940 sqdecb x0, w0, vl32
-+[^:]+: 0420f940 sqdecb x0, w0, vl32
-+[^:]+: 0420f940 sqdecb x0, w0, vl32
-+[^:]+: 0420f960 sqdecb x0, w0, vl64
-+[^:]+: 0420f960 sqdecb x0, w0, vl64
-+[^:]+: 0420f960 sqdecb x0, w0, vl64
-+[^:]+: 0420f980 sqdecb x0, w0, vl128
-+[^:]+: 0420f980 sqdecb x0, w0, vl128
-+[^:]+: 0420f980 sqdecb x0, w0, vl128
-+[^:]+: 0420f9a0 sqdecb x0, w0, vl256
-+[^:]+: 0420f9a0 sqdecb x0, w0, vl256
-+[^:]+: 0420f9a0 sqdecb x0, w0, vl256
-+[^:]+: 0420f9c0 sqdecb x0, w0, #14
-+[^:]+: 0420f9c0 sqdecb x0, w0, #14
-+[^:]+: 0420f9c0 sqdecb x0, w0, #14
-+[^:]+: 0420f9e0 sqdecb x0, w0, #15
-+[^:]+: 0420f9e0 sqdecb x0, w0, #15
-+[^:]+: 0420f9e0 sqdecb x0, w0, #15
-+[^:]+: 0420fa00 sqdecb x0, w0, #16
-+[^:]+: 0420fa00 sqdecb x0, w0, #16
-+[^:]+: 0420fa00 sqdecb x0, w0, #16
-+[^:]+: 0420fa20 sqdecb x0, w0, #17
-+[^:]+: 0420fa20 sqdecb x0, w0, #17
-+[^:]+: 0420fa20 sqdecb x0, w0, #17
-+[^:]+: 0420fa40 sqdecb x0, w0, #18
-+[^:]+: 0420fa40 sqdecb x0, w0, #18
-+[^:]+: 0420fa40 sqdecb x0, w0, #18
-+[^:]+: 0420fa60 sqdecb x0, w0, #19
-+[^:]+: 0420fa60 sqdecb x0, w0, #19
-+[^:]+: 0420fa60 sqdecb x0, w0, #19
-+[^:]+: 0420fa80 sqdecb x0, w0, #20
-+[^:]+: 0420fa80 sqdecb x0, w0, #20
-+[^:]+: 0420fa80 sqdecb x0, w0, #20
-+[^:]+: 0420faa0 sqdecb x0, w0, #21
-+[^:]+: 0420faa0 sqdecb x0, w0, #21
-+[^:]+: 0420faa0 sqdecb x0, w0, #21
-+[^:]+: 0420fac0 sqdecb x0, w0, #22
-+[^:]+: 0420fac0 sqdecb x0, w0, #22
-+[^:]+: 0420fac0 sqdecb x0, w0, #22
-+[^:]+: 0420fae0 sqdecb x0, w0, #23
-+[^:]+: 0420fae0 sqdecb x0, w0, #23
-+[^:]+: 0420fae0 sqdecb x0, w0, #23
-+[^:]+: 0420fb00 sqdecb x0, w0, #24
-+[^:]+: 0420fb00 sqdecb x0, w0, #24
-+[^:]+: 0420fb00 sqdecb x0, w0, #24
-+[^:]+: 0420fb20 sqdecb x0, w0, #25
-+[^:]+: 0420fb20 sqdecb x0, w0, #25
-+[^:]+: 0420fb20 sqdecb x0, w0, #25
-+[^:]+: 0420fb40 sqdecb x0, w0, #26
-+[^:]+: 0420fb40 sqdecb x0, w0, #26
-+[^:]+: 0420fb40 sqdecb x0, w0, #26
-+[^:]+: 0420fb60 sqdecb x0, w0, #27
-+[^:]+: 0420fb60 sqdecb x0, w0, #27
-+[^:]+: 0420fb60 sqdecb x0, w0, #27
-+[^:]+: 0420fb80 sqdecb x0, w0, #28
-+[^:]+: 0420fb80 sqdecb x0, w0, #28
-+[^:]+: 0420fb80 sqdecb x0, w0, #28
-+[^:]+: 0420fba0 sqdecb x0, w0, mul4
-+[^:]+: 0420fba0 sqdecb x0, w0, mul4
-+[^:]+: 0420fba0 sqdecb x0, w0, mul4
-+[^:]+: 0420fbc0 sqdecb x0, w0, mul3
-+[^:]+: 0420fbc0 sqdecb x0, w0, mul3
-+[^:]+: 0420fbc0 sqdecb x0, w0, mul3
-+[^:]+: 0420fbe0 sqdecb x0, w0
-+[^:]+: 0420fbe0 sqdecb x0, w0
-+[^:]+: 0420fbe0 sqdecb x0, w0
-+[^:]+: 0420fbe0 sqdecb x0, w0
-+[^:]+: 0427f800 sqdecb x0, w0, pow2, mul #8
-+[^:]+: 0427f800 sqdecb x0, w0, pow2, mul #8
-+[^:]+: 0428f800 sqdecb x0, w0, pow2, mul #9
-+[^:]+: 0428f800 sqdecb x0, w0, pow2, mul #9
-+[^:]+: 0429f800 sqdecb x0, w0, pow2, mul #10
-+[^:]+: 0429f800 sqdecb x0, w0, pow2, mul #10
-+[^:]+: 042ff800 sqdecb x0, w0, pow2, mul #16
-+[^:]+: 042ff800 sqdecb x0, w0, pow2, mul #16
-+[^:]+: 04e0c800 sqdecd z0.d, pow2
-+[^:]+: 04e0c800 sqdecd z0.d, pow2
-+[^:]+: 04e0c800 sqdecd z0.d, pow2
-+[^:]+: 04e0c801 sqdecd z1.d, pow2
-+[^:]+: 04e0c801 sqdecd z1.d, pow2
-+[^:]+: 04e0c801 sqdecd z1.d, pow2
-+[^:]+: 04e0c81f sqdecd z31.d, pow2
-+[^:]+: 04e0c81f sqdecd z31.d, pow2
-+[^:]+: 04e0c81f sqdecd z31.d, pow2
-+[^:]+: 04e0c820 sqdecd z0.d, vl1
-+[^:]+: 04e0c820 sqdecd z0.d, vl1
-+[^:]+: 04e0c820 sqdecd z0.d, vl1
-+[^:]+: 04e0c840 sqdecd z0.d, vl2
-+[^:]+: 04e0c840 sqdecd z0.d, vl2
-+[^:]+: 04e0c840 sqdecd z0.d, vl2
-+[^:]+: 04e0c860 sqdecd z0.d, vl3
-+[^:]+: 04e0c860 sqdecd z0.d, vl3
-+[^:]+: 04e0c860 sqdecd z0.d, vl3
-+[^:]+: 04e0c880 sqdecd z0.d, vl4
-+[^:]+: 04e0c880 sqdecd z0.d, vl4
-+[^:]+: 04e0c880 sqdecd z0.d, vl4
-+[^:]+: 04e0c8a0 sqdecd z0.d, vl5
-+[^:]+: 04e0c8a0 sqdecd z0.d, vl5
-+[^:]+: 04e0c8a0 sqdecd z0.d, vl5
-+[^:]+: 04e0c8c0 sqdecd z0.d, vl6
-+[^:]+: 04e0c8c0 sqdecd z0.d, vl6
-+[^:]+: 04e0c8c0 sqdecd z0.d, vl6
-+[^:]+: 04e0c8e0 sqdecd z0.d, vl7
-+[^:]+: 04e0c8e0 sqdecd z0.d, vl7
-+[^:]+: 04e0c8e0 sqdecd z0.d, vl7
-+[^:]+: 04e0c900 sqdecd z0.d, vl8
-+[^:]+: 04e0c900 sqdecd z0.d, vl8
-+[^:]+: 04e0c900 sqdecd z0.d, vl8
-+[^:]+: 04e0c920 sqdecd z0.d, vl16
-+[^:]+: 04e0c920 sqdecd z0.d, vl16
-+[^:]+: 04e0c920 sqdecd z0.d, vl16
-+[^:]+: 04e0c940 sqdecd z0.d, vl32
-+[^:]+: 04e0c940 sqdecd z0.d, vl32
-+[^:]+: 04e0c940 sqdecd z0.d, vl32
-+[^:]+: 04e0c960 sqdecd z0.d, vl64
-+[^:]+: 04e0c960 sqdecd z0.d, vl64
-+[^:]+: 04e0c960 sqdecd z0.d, vl64
-+[^:]+: 04e0c980 sqdecd z0.d, vl128
-+[^:]+: 04e0c980 sqdecd z0.d, vl128
-+[^:]+: 04e0c980 sqdecd z0.d, vl128
-+[^:]+: 04e0c9a0 sqdecd z0.d, vl256
-+[^:]+: 04e0c9a0 sqdecd z0.d, vl256
-+[^:]+: 04e0c9a0 sqdecd z0.d, vl256
-+[^:]+: 04e0c9c0 sqdecd z0.d, #14
-+[^:]+: 04e0c9c0 sqdecd z0.d, #14
-+[^:]+: 04e0c9c0 sqdecd z0.d, #14
-+[^:]+: 04e0c9e0 sqdecd z0.d, #15
-+[^:]+: 04e0c9e0 sqdecd z0.d, #15
-+[^:]+: 04e0c9e0 sqdecd z0.d, #15
-+[^:]+: 04e0ca00 sqdecd z0.d, #16
-+[^:]+: 04e0ca00 sqdecd z0.d, #16
-+[^:]+: 04e0ca00 sqdecd z0.d, #16
-+[^:]+: 04e0ca20 sqdecd z0.d, #17
-+[^:]+: 04e0ca20 sqdecd z0.d, #17
-+[^:]+: 04e0ca20 sqdecd z0.d, #17
-+[^:]+: 04e0ca40 sqdecd z0.d, #18
-+[^:]+: 04e0ca40 sqdecd z0.d, #18
-+[^:]+: 04e0ca40 sqdecd z0.d, #18
-+[^:]+: 04e0ca60 sqdecd z0.d, #19
-+[^:]+: 04e0ca60 sqdecd z0.d, #19
-+[^:]+: 04e0ca60 sqdecd z0.d, #19
-+[^:]+: 04e0ca80 sqdecd z0.d, #20
-+[^:]+: 04e0ca80 sqdecd z0.d, #20
-+[^:]+: 04e0ca80 sqdecd z0.d, #20
-+[^:]+: 04e0caa0 sqdecd z0.d, #21
-+[^:]+: 04e0caa0 sqdecd z0.d, #21
-+[^:]+: 04e0caa0 sqdecd z0.d, #21
-+[^:]+: 04e0cac0 sqdecd z0.d, #22
-+[^:]+: 04e0cac0 sqdecd z0.d, #22
-+[^:]+: 04e0cac0 sqdecd z0.d, #22
-+[^:]+: 04e0cae0 sqdecd z0.d, #23
-+[^:]+: 04e0cae0 sqdecd z0.d, #23
-+[^:]+: 04e0cae0 sqdecd z0.d, #23
-+[^:]+: 04e0cb00 sqdecd z0.d, #24
-+[^:]+: 04e0cb00 sqdecd z0.d, #24
-+[^:]+: 04e0cb00 sqdecd z0.d, #24
-+[^:]+: 04e0cb20 sqdecd z0.d, #25
-+[^:]+: 04e0cb20 sqdecd z0.d, #25
-+[^:]+: 04e0cb20 sqdecd z0.d, #25
-+[^:]+: 04e0cb40 sqdecd z0.d, #26
-+[^:]+: 04e0cb40 sqdecd z0.d, #26
-+[^:]+: 04e0cb40 sqdecd z0.d, #26
-+[^:]+: 04e0cb60 sqdecd z0.d, #27
-+[^:]+: 04e0cb60 sqdecd z0.d, #27
-+[^:]+: 04e0cb60 sqdecd z0.d, #27
-+[^:]+: 04e0cb80 sqdecd z0.d, #28
-+[^:]+: 04e0cb80 sqdecd z0.d, #28
-+[^:]+: 04e0cb80 sqdecd z0.d, #28
-+[^:]+: 04e0cba0 sqdecd z0.d, mul4
-+[^:]+: 04e0cba0 sqdecd z0.d, mul4
-+[^:]+: 04e0cba0 sqdecd z0.d, mul4
-+[^:]+: 04e0cbc0 sqdecd z0.d, mul3
-+[^:]+: 04e0cbc0 sqdecd z0.d, mul3
-+[^:]+: 04e0cbc0 sqdecd z0.d, mul3
-+[^:]+: 04e0cbe0 sqdecd z0.d
-+[^:]+: 04e0cbe0 sqdecd z0.d
-+[^:]+: 04e0cbe0 sqdecd z0.d
-+[^:]+: 04e0cbe0 sqdecd z0.d
-+[^:]+: 04e7c800 sqdecd z0.d, pow2, mul #8
-+[^:]+: 04e7c800 sqdecd z0.d, pow2, mul #8
-+[^:]+: 04e8c800 sqdecd z0.d, pow2, mul #9
-+[^:]+: 04e8c800 sqdecd z0.d, pow2, mul #9
-+[^:]+: 04e9c800 sqdecd z0.d, pow2, mul #10
-+[^:]+: 04e9c800 sqdecd z0.d, pow2, mul #10
-+[^:]+: 04efc800 sqdecd z0.d, pow2, mul #16
-+[^:]+: 04efc800 sqdecd z0.d, pow2, mul #16
-+[^:]+: 04f0f800 sqdecd x0, pow2
-+[^:]+: 04f0f800 sqdecd x0, pow2
-+[^:]+: 04f0f800 sqdecd x0, pow2
-+[^:]+: 04f0f801 sqdecd x1, pow2
-+[^:]+: 04f0f801 sqdecd x1, pow2
-+[^:]+: 04f0f801 sqdecd x1, pow2
-+[^:]+: 04f0f81f sqdecd xzr, pow2
-+[^:]+: 04f0f81f sqdecd xzr, pow2
-+[^:]+: 04f0f81f sqdecd xzr, pow2
-+[^:]+: 04f0f820 sqdecd x0, vl1
-+[^:]+: 04f0f820 sqdecd x0, vl1
-+[^:]+: 04f0f820 sqdecd x0, vl1
-+[^:]+: 04f0f840 sqdecd x0, vl2
-+[^:]+: 04f0f840 sqdecd x0, vl2
-+[^:]+: 04f0f840 sqdecd x0, vl2
-+[^:]+: 04f0f860 sqdecd x0, vl3
-+[^:]+: 04f0f860 sqdecd x0, vl3
-+[^:]+: 04f0f860 sqdecd x0, vl3
-+[^:]+: 04f0f880 sqdecd x0, vl4
-+[^:]+: 04f0f880 sqdecd x0, vl4
-+[^:]+: 04f0f880 sqdecd x0, vl4
-+[^:]+: 04f0f8a0 sqdecd x0, vl5
-+[^:]+: 04f0f8a0 sqdecd x0, vl5
-+[^:]+: 04f0f8a0 sqdecd x0, vl5
-+[^:]+: 04f0f8c0 sqdecd x0, vl6
-+[^:]+: 04f0f8c0 sqdecd x0, vl6
-+[^:]+: 04f0f8c0 sqdecd x0, vl6
-+[^:]+: 04f0f8e0 sqdecd x0, vl7
-+[^:]+: 04f0f8e0 sqdecd x0, vl7
-+[^:]+: 04f0f8e0 sqdecd x0, vl7
-+[^:]+: 04f0f900 sqdecd x0, vl8
-+[^:]+: 04f0f900 sqdecd x0, vl8
-+[^:]+: 04f0f900 sqdecd x0, vl8
-+[^:]+: 04f0f920 sqdecd x0, vl16
-+[^:]+: 04f0f920 sqdecd x0, vl16
-+[^:]+: 04f0f920 sqdecd x0, vl16
-+[^:]+: 04f0f940 sqdecd x0, vl32
-+[^:]+: 04f0f940 sqdecd x0, vl32
-+[^:]+: 04f0f940 sqdecd x0, vl32
-+[^:]+: 04f0f960 sqdecd x0, vl64
-+[^:]+: 04f0f960 sqdecd x0, vl64
-+[^:]+: 04f0f960 sqdecd x0, vl64
-+[^:]+: 04f0f980 sqdecd x0, vl128
-+[^:]+: 04f0f980 sqdecd x0, vl128
-+[^:]+: 04f0f980 sqdecd x0, vl128
-+[^:]+: 04f0f9a0 sqdecd x0, vl256
-+[^:]+: 04f0f9a0 sqdecd x0, vl256
-+[^:]+: 04f0f9a0 sqdecd x0, vl256
-+[^:]+: 04f0f9c0 sqdecd x0, #14
-+[^:]+: 04f0f9c0 sqdecd x0, #14
-+[^:]+: 04f0f9c0 sqdecd x0, #14
-+[^:]+: 04f0f9e0 sqdecd x0, #15
-+[^:]+: 04f0f9e0 sqdecd x0, #15
-+[^:]+: 04f0f9e0 sqdecd x0, #15
-+[^:]+: 04f0fa00 sqdecd x0, #16
-+[^:]+: 04f0fa00 sqdecd x0, #16
-+[^:]+: 04f0fa00 sqdecd x0, #16
-+[^:]+: 04f0fa20 sqdecd x0, #17
-+[^:]+: 04f0fa20 sqdecd x0, #17
-+[^:]+: 04f0fa20 sqdecd x0, #17
-+[^:]+: 04f0fa40 sqdecd x0, #18
-+[^:]+: 04f0fa40 sqdecd x0, #18
-+[^:]+: 04f0fa40 sqdecd x0, #18
-+[^:]+: 04f0fa60 sqdecd x0, #19
-+[^:]+: 04f0fa60 sqdecd x0, #19
-+[^:]+: 04f0fa60 sqdecd x0, #19
-+[^:]+: 04f0fa80 sqdecd x0, #20
-+[^:]+: 04f0fa80 sqdecd x0, #20
-+[^:]+: 04f0fa80 sqdecd x0, #20
-+[^:]+: 04f0faa0 sqdecd x0, #21
-+[^:]+: 04f0faa0 sqdecd x0, #21
-+[^:]+: 04f0faa0 sqdecd x0, #21
-+[^:]+: 04f0fac0 sqdecd x0, #22
-+[^:]+: 04f0fac0 sqdecd x0, #22
-+[^:]+: 04f0fac0 sqdecd x0, #22
-+[^:]+: 04f0fae0 sqdecd x0, #23
-+[^:]+: 04f0fae0 sqdecd x0, #23
-+[^:]+: 04f0fae0 sqdecd x0, #23
-+[^:]+: 04f0fb00 sqdecd x0, #24
-+[^:]+: 04f0fb00 sqdecd x0, #24
-+[^:]+: 04f0fb00 sqdecd x0, #24
-+[^:]+: 04f0fb20 sqdecd x0, #25
-+[^:]+: 04f0fb20 sqdecd x0, #25
-+[^:]+: 04f0fb20 sqdecd x0, #25
-+[^:]+: 04f0fb40 sqdecd x0, #26
-+[^:]+: 04f0fb40 sqdecd x0, #26
-+[^:]+: 04f0fb40 sqdecd x0, #26
-+[^:]+: 04f0fb60 sqdecd x0, #27
-+[^:]+: 04f0fb60 sqdecd x0, #27
-+[^:]+: 04f0fb60 sqdecd x0, #27
-+[^:]+: 04f0fb80 sqdecd x0, #28
-+[^:]+: 04f0fb80 sqdecd x0, #28
-+[^:]+: 04f0fb80 sqdecd x0, #28
-+[^:]+: 04f0fba0 sqdecd x0, mul4
-+[^:]+: 04f0fba0 sqdecd x0, mul4
-+[^:]+: 04f0fba0 sqdecd x0, mul4
-+[^:]+: 04f0fbc0 sqdecd x0, mul3
-+[^:]+: 04f0fbc0 sqdecd x0, mul3
-+[^:]+: 04f0fbc0 sqdecd x0, mul3
-+[^:]+: 04f0fbe0 sqdecd x0
-+[^:]+: 04f0fbe0 sqdecd x0
-+[^:]+: 04f0fbe0 sqdecd x0
-+[^:]+: 04f0fbe0 sqdecd x0
-+[^:]+: 04f7f800 sqdecd x0, pow2, mul #8
-+[^:]+: 04f7f800 sqdecd x0, pow2, mul #8
-+[^:]+: 04f8f800 sqdecd x0, pow2, mul #9
-+[^:]+: 04f8f800 sqdecd x0, pow2, mul #9
-+[^:]+: 04f9f800 sqdecd x0, pow2, mul #10
-+[^:]+: 04f9f800 sqdecd x0, pow2, mul #10
-+[^:]+: 04fff800 sqdecd x0, pow2, mul #16
-+[^:]+: 04fff800 sqdecd x0, pow2, mul #16
-+[^:]+: 04e0f800 sqdecd x0, w0, pow2
-+[^:]+: 04e0f800 sqdecd x0, w0, pow2
-+[^:]+: 04e0f800 sqdecd x0, w0, pow2
-+[^:]+: 04e0f801 sqdecd x1, w1, pow2
-+[^:]+: 04e0f801 sqdecd x1, w1, pow2
-+[^:]+: 04e0f801 sqdecd x1, w1, pow2
-+[^:]+: 04e0f81f sqdecd xzr, wzr, pow2
-+[^:]+: 04e0f81f sqdecd xzr, wzr, pow2
-+[^:]+: 04e0f81f sqdecd xzr, wzr, pow2
-+[^:]+: 04e0f802 sqdecd x2, w2, pow2
-+[^:]+: 04e0f802 sqdecd x2, w2, pow2
-+[^:]+: 04e0f802 sqdecd x2, w2, pow2
-+[^:]+: 04e0f820 sqdecd x0, w0, vl1
-+[^:]+: 04e0f820 sqdecd x0, w0, vl1
-+[^:]+: 04e0f820 sqdecd x0, w0, vl1
-+[^:]+: 04e0f840 sqdecd x0, w0, vl2
-+[^:]+: 04e0f840 sqdecd x0, w0, vl2
-+[^:]+: 04e0f840 sqdecd x0, w0, vl2
-+[^:]+: 04e0f860 sqdecd x0, w0, vl3
-+[^:]+: 04e0f860 sqdecd x0, w0, vl3
-+[^:]+: 04e0f860 sqdecd x0, w0, vl3
-+[^:]+: 04e0f880 sqdecd x0, w0, vl4
-+[^:]+: 04e0f880 sqdecd x0, w0, vl4
-+[^:]+: 04e0f880 sqdecd x0, w0, vl4
-+[^:]+: 04e0f8a0 sqdecd x0, w0, vl5
-+[^:]+: 04e0f8a0 sqdecd x0, w0, vl5
-+[^:]+: 04e0f8a0 sqdecd x0, w0, vl5
-+[^:]+: 04e0f8c0 sqdecd x0, w0, vl6
-+[^:]+: 04e0f8c0 sqdecd x0, w0, vl6
-+[^:]+: 04e0f8c0 sqdecd x0, w0, vl6
-+[^:]+: 04e0f8e0 sqdecd x0, w0, vl7
-+[^:]+: 04e0f8e0 sqdecd x0, w0, vl7
-+[^:]+: 04e0f8e0 sqdecd x0, w0, vl7
-+[^:]+: 04e0f900 sqdecd x0, w0, vl8
-+[^:]+: 04e0f900 sqdecd x0, w0, vl8
-+[^:]+: 04e0f900 sqdecd x0, w0, vl8
-+[^:]+: 04e0f920 sqdecd x0, w0, vl16
-+[^:]+: 04e0f920 sqdecd x0, w0, vl16
-+[^:]+: 04e0f920 sqdecd x0, w0, vl16
-+[^:]+: 04e0f940 sqdecd x0, w0, vl32
-+[^:]+: 04e0f940 sqdecd x0, w0, vl32
-+[^:]+: 04e0f940 sqdecd x0, w0, vl32
-+[^:]+: 04e0f960 sqdecd x0, w0, vl64
-+[^:]+: 04e0f960 sqdecd x0, w0, vl64
-+[^:]+: 04e0f960 sqdecd x0, w0, vl64
-+[^:]+: 04e0f980 sqdecd x0, w0, vl128
-+[^:]+: 04e0f980 sqdecd x0, w0, vl128
-+[^:]+: 04e0f980 sqdecd x0, w0, vl128
-+[^:]+: 04e0f9a0 sqdecd x0, w0, vl256
-+[^:]+: 04e0f9a0 sqdecd x0, w0, vl256
-+[^:]+: 04e0f9a0 sqdecd x0, w0, vl256
-+[^:]+: 04e0f9c0 sqdecd x0, w0, #14
-+[^:]+: 04e0f9c0 sqdecd x0, w0, #14
-+[^:]+: 04e0f9c0 sqdecd x0, w0, #14
-+[^:]+: 04e0f9e0 sqdecd x0, w0, #15
-+[^:]+: 04e0f9e0 sqdecd x0, w0, #15
-+[^:]+: 04e0f9e0 sqdecd x0, w0, #15
-+[^:]+: 04e0fa00 sqdecd x0, w0, #16
-+[^:]+: 04e0fa00 sqdecd x0, w0, #16
-+[^:]+: 04e0fa00 sqdecd x0, w0, #16
-+[^:]+: 04e0fa20 sqdecd x0, w0, #17
-+[^:]+: 04e0fa20 sqdecd x0, w0, #17
-+[^:]+: 04e0fa20 sqdecd x0, w0, #17
-+[^:]+: 04e0fa40 sqdecd x0, w0, #18
-+[^:]+: 04e0fa40 sqdecd x0, w0, #18
-+[^:]+: 04e0fa40 sqdecd x0, w0, #18
-+[^:]+: 04e0fa60 sqdecd x0, w0, #19
-+[^:]+: 04e0fa60 sqdecd x0, w0, #19
-+[^:]+: 04e0fa60 sqdecd x0, w0, #19
-+[^:]+: 04e0fa80 sqdecd x0, w0, #20
-+[^:]+: 04e0fa80 sqdecd x0, w0, #20
-+[^:]+: 04e0fa80 sqdecd x0, w0, #20
-+[^:]+: 04e0faa0 sqdecd x0, w0, #21
-+[^:]+: 04e0faa0 sqdecd x0, w0, #21
-+[^:]+: 04e0faa0 sqdecd x0, w0, #21
-+[^:]+: 04e0fac0 sqdecd x0, w0, #22
-+[^:]+: 04e0fac0 sqdecd x0, w0, #22
-+[^:]+: 04e0fac0 sqdecd x0, w0, #22
-+[^:]+: 04e0fae0 sqdecd x0, w0, #23
-+[^:]+: 04e0fae0 sqdecd x0, w0, #23
-+[^:]+: 04e0fae0 sqdecd x0, w0, #23
-+[^:]+: 04e0fb00 sqdecd x0, w0, #24
-+[^:]+: 04e0fb00 sqdecd x0, w0, #24
-+[^:]+: 04e0fb00 sqdecd x0, w0, #24
-+[^:]+: 04e0fb20 sqdecd x0, w0, #25
-+[^:]+: 04e0fb20 sqdecd x0, w0, #25
-+[^:]+: 04e0fb20 sqdecd x0, w0, #25
-+[^:]+: 04e0fb40 sqdecd x0, w0, #26
-+[^:]+: 04e0fb40 sqdecd x0, w0, #26
-+[^:]+: 04e0fb40 sqdecd x0, w0, #26
-+[^:]+: 04e0fb60 sqdecd x0, w0, #27
-+[^:]+: 04e0fb60 sqdecd x0, w0, #27
-+[^:]+: 04e0fb60 sqdecd x0, w0, #27
-+[^:]+: 04e0fb80 sqdecd x0, w0, #28
-+[^:]+: 04e0fb80 sqdecd x0, w0, #28
-+[^:]+: 04e0fb80 sqdecd x0, w0, #28
-+[^:]+: 04e0fba0 sqdecd x0, w0, mul4
-+[^:]+: 04e0fba0 sqdecd x0, w0, mul4
-+[^:]+: 04e0fba0 sqdecd x0, w0, mul4
-+[^:]+: 04e0fbc0 sqdecd x0, w0, mul3
-+[^:]+: 04e0fbc0 sqdecd x0, w0, mul3
-+[^:]+: 04e0fbc0 sqdecd x0, w0, mul3
-+[^:]+: 04e0fbe0 sqdecd x0, w0
-+[^:]+: 04e0fbe0 sqdecd x0, w0
-+[^:]+: 04e0fbe0 sqdecd x0, w0
-+[^:]+: 04e0fbe0 sqdecd x0, w0
-+[^:]+: 04e7f800 sqdecd x0, w0, pow2, mul #8
-+[^:]+: 04e7f800 sqdecd x0, w0, pow2, mul #8
-+[^:]+: 04e8f800 sqdecd x0, w0, pow2, mul #9
-+[^:]+: 04e8f800 sqdecd x0, w0, pow2, mul #9
-+[^:]+: 04e9f800 sqdecd x0, w0, pow2, mul #10
-+[^:]+: 04e9f800 sqdecd x0, w0, pow2, mul #10
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-+[^:]+: 04eff800 sqdecd x0, w0, pow2, mul #16
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-+[^:]+: 0460c8c0 sqdech z0.h, vl6
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-+[^:]+: 0460c900 sqdech z0.h, vl8
-+[^:]+: 0460c900 sqdech z0.h, vl8
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-+[^:]+: 0460c920 sqdech z0.h, vl16
-+[^:]+: 0460c920 sqdech z0.h, vl16
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-+[^:]+: 0460c940 sqdech z0.h, vl32
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-+[^:]+: 0460c960 sqdech z0.h, vl64
-+[^:]+: 0460c960 sqdech z0.h, vl64
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-+[^:]+: 0460c980 sqdech z0.h, vl128
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-+[^:]+: 0460c9a0 sqdech z0.h, vl256
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-+[^:]+: 0460cb00 sqdech z0.h, #24
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-+[^:]+: 0460cb20 sqdech z0.h, #25
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-+[^:]+: 0460cb40 sqdech z0.h, #26
-+[^:]+: 0460cb40 sqdech z0.h, #26
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-+[^:]+: 0460cb60 sqdech z0.h, #27
-+[^:]+: 0460cb60 sqdech z0.h, #27
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-+[^:]+: 0460cb80 sqdech z0.h, #28
-+[^:]+: 0460cb80 sqdech z0.h, #28
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-+[^:]+: 0470f8c0 sqdech x0, vl6
-+[^:]+: 0470f8c0 sqdech x0, vl6
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-+[^:]+: 0470f9a0 sqdech x0, vl256
-+[^:]+: 0470f9c0 sqdech x0, #14
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-+[^:]+: 0460f800 sqdech x0, w0, pow2
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-+[^:]+: 0460f801 sqdech x1, w1, pow2
-+[^:]+: 0460f801 sqdech x1, w1, pow2
-+[^:]+: 0460f81f sqdech xzr, wzr, pow2
-+[^:]+: 0460f81f sqdech xzr, wzr, pow2
-+[^:]+: 0460f81f sqdech xzr, wzr, pow2
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-+[^:]+: 0460f920 sqdech x0, w0, vl16
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-+[^:]+: 0460f960 sqdech x0, w0, vl64
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-+[^:]+: 256a8000 sqdecp z0.h, p0
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-+[^:]+: 04a0f802 sqdecw x2, w2, pow2
-+[^:]+: 04a0f802 sqdecw x2, w2, pow2
-+[^:]+: 04a0f820 sqdecw x0, w0, vl1
-+[^:]+: 04a0f820 sqdecw x0, w0, vl1
-+[^:]+: 04a0f820 sqdecw x0, w0, vl1
-+[^:]+: 04a0f840 sqdecw x0, w0, vl2
-+[^:]+: 04a0f840 sqdecw x0, w0, vl2
-+[^:]+: 04a0f840 sqdecw x0, w0, vl2
-+[^:]+: 04a0f860 sqdecw x0, w0, vl3
-+[^:]+: 04a0f860 sqdecw x0, w0, vl3
-+[^:]+: 04a0f860 sqdecw x0, w0, vl3
-+[^:]+: 04a0f880 sqdecw x0, w0, vl4
-+[^:]+: 04a0f880 sqdecw x0, w0, vl4
-+[^:]+: 04a0f880 sqdecw x0, w0, vl4
-+[^:]+: 04a0f8a0 sqdecw x0, w0, vl5
-+[^:]+: 04a0f8a0 sqdecw x0, w0, vl5
-+[^:]+: 04a0f8a0 sqdecw x0, w0, vl5
-+[^:]+: 04a0f8c0 sqdecw x0, w0, vl6
-+[^:]+: 04a0f8c0 sqdecw x0, w0, vl6
-+[^:]+: 04a0f8c0 sqdecw x0, w0, vl6
-+[^:]+: 04a0f8e0 sqdecw x0, w0, vl7
-+[^:]+: 04a0f8e0 sqdecw x0, w0, vl7
-+[^:]+: 04a0f8e0 sqdecw x0, w0, vl7
-+[^:]+: 04a0f900 sqdecw x0, w0, vl8
-+[^:]+: 04a0f900 sqdecw x0, w0, vl8
-+[^:]+: 04a0f900 sqdecw x0, w0, vl8
-+[^:]+: 04a0f920 sqdecw x0, w0, vl16
-+[^:]+: 04a0f920 sqdecw x0, w0, vl16
-+[^:]+: 04a0f920 sqdecw x0, w0, vl16
-+[^:]+: 04a0f940 sqdecw x0, w0, vl32
-+[^:]+: 04a0f940 sqdecw x0, w0, vl32
-+[^:]+: 04a0f940 sqdecw x0, w0, vl32
-+[^:]+: 04a0f960 sqdecw x0, w0, vl64
-+[^:]+: 04a0f960 sqdecw x0, w0, vl64
-+[^:]+: 04a0f960 sqdecw x0, w0, vl64
-+[^:]+: 04a0f980 sqdecw x0, w0, vl128
-+[^:]+: 04a0f980 sqdecw x0, w0, vl128
-+[^:]+: 04a0f980 sqdecw x0, w0, vl128
-+[^:]+: 04a0f9a0 sqdecw x0, w0, vl256
-+[^:]+: 04a0f9a0 sqdecw x0, w0, vl256
-+[^:]+: 04a0f9a0 sqdecw x0, w0, vl256
-+[^:]+: 04a0f9c0 sqdecw x0, w0, #14
-+[^:]+: 04a0f9c0 sqdecw x0, w0, #14
-+[^:]+: 04a0f9c0 sqdecw x0, w0, #14
-+[^:]+: 04a0f9e0 sqdecw x0, w0, #15
-+[^:]+: 04a0f9e0 sqdecw x0, w0, #15
-+[^:]+: 04a0f9e0 sqdecw x0, w0, #15
-+[^:]+: 04a0fa00 sqdecw x0, w0, #16
-+[^:]+: 04a0fa00 sqdecw x0, w0, #16
-+[^:]+: 04a0fa00 sqdecw x0, w0, #16
-+[^:]+: 04a0fa20 sqdecw x0, w0, #17
-+[^:]+: 04a0fa20 sqdecw x0, w0, #17
-+[^:]+: 04a0fa20 sqdecw x0, w0, #17
-+[^:]+: 04a0fa40 sqdecw x0, w0, #18
-+[^:]+: 04a0fa40 sqdecw x0, w0, #18
-+[^:]+: 04a0fa40 sqdecw x0, w0, #18
-+[^:]+: 04a0fa60 sqdecw x0, w0, #19
-+[^:]+: 04a0fa60 sqdecw x0, w0, #19
-+[^:]+: 04a0fa60 sqdecw x0, w0, #19
-+[^:]+: 04a0fa80 sqdecw x0, w0, #20
-+[^:]+: 04a0fa80 sqdecw x0, w0, #20
-+[^:]+: 04a0fa80 sqdecw x0, w0, #20
-+[^:]+: 04a0faa0 sqdecw x0, w0, #21
-+[^:]+: 04a0faa0 sqdecw x0, w0, #21
-+[^:]+: 04a0faa0 sqdecw x0, w0, #21
-+[^:]+: 04a0fac0 sqdecw x0, w0, #22
-+[^:]+: 04a0fac0 sqdecw x0, w0, #22
-+[^:]+: 04a0fac0 sqdecw x0, w0, #22
-+[^:]+: 04a0fae0 sqdecw x0, w0, #23
-+[^:]+: 04a0fae0 sqdecw x0, w0, #23
-+[^:]+: 04a0fae0 sqdecw x0, w0, #23
-+[^:]+: 04a0fb00 sqdecw x0, w0, #24
-+[^:]+: 04a0fb00 sqdecw x0, w0, #24
-+[^:]+: 04a0fb00 sqdecw x0, w0, #24
-+[^:]+: 04a0fb20 sqdecw x0, w0, #25
-+[^:]+: 04a0fb20 sqdecw x0, w0, #25
-+[^:]+: 04a0fb20 sqdecw x0, w0, #25
-+[^:]+: 04a0fb40 sqdecw x0, w0, #26
-+[^:]+: 04a0fb40 sqdecw x0, w0, #26
-+[^:]+: 04a0fb40 sqdecw x0, w0, #26
-+[^:]+: 04a0fb60 sqdecw x0, w0, #27
-+[^:]+: 04a0fb60 sqdecw x0, w0, #27
-+[^:]+: 04a0fb60 sqdecw x0, w0, #27
-+[^:]+: 04a0fb80 sqdecw x0, w0, #28
-+[^:]+: 04a0fb80 sqdecw x0, w0, #28
-+[^:]+: 04a0fb80 sqdecw x0, w0, #28
-+[^:]+: 04a0fba0 sqdecw x0, w0, mul4
-+[^:]+: 04a0fba0 sqdecw x0, w0, mul4
-+[^:]+: 04a0fba0 sqdecw x0, w0, mul4
-+[^:]+: 04a0fbc0 sqdecw x0, w0, mul3
-+[^:]+: 04a0fbc0 sqdecw x0, w0, mul3
-+[^:]+: 04a0fbc0 sqdecw x0, w0, mul3
-+[^:]+: 04a0fbe0 sqdecw x0, w0
-+[^:]+: 04a0fbe0 sqdecw x0, w0
-+[^:]+: 04a0fbe0 sqdecw x0, w0
-+[^:]+: 04a0fbe0 sqdecw x0, w0
-+[^:]+: 04a7f800 sqdecw x0, w0, pow2, mul #8
-+[^:]+: 04a7f800 sqdecw x0, w0, pow2, mul #8
-+[^:]+: 04a8f800 sqdecw x0, w0, pow2, mul #9
-+[^:]+: 04a8f800 sqdecw x0, w0, pow2, mul #9
-+[^:]+: 04a9f800 sqdecw x0, w0, pow2, mul #10
-+[^:]+: 04a9f800 sqdecw x0, w0, pow2, mul #10
-+[^:]+: 04aff800 sqdecw x0, w0, pow2, mul #16
-+[^:]+: 04aff800 sqdecw x0, w0, pow2, mul #16
-+[^:]+: 0430f000 sqincb x0, pow2
-+[^:]+: 0430f000 sqincb x0, pow2
-+[^:]+: 0430f000 sqincb x0, pow2
-+[^:]+: 0430f001 sqincb x1, pow2
-+[^:]+: 0430f001 sqincb x1, pow2
-+[^:]+: 0430f001 sqincb x1, pow2
-+[^:]+: 0430f01f sqincb xzr, pow2
-+[^:]+: 0430f01f sqincb xzr, pow2
-+[^:]+: 0430f01f sqincb xzr, pow2
-+[^:]+: 0430f020 sqincb x0, vl1
-+[^:]+: 0430f020 sqincb x0, vl1
-+[^:]+: 0430f020 sqincb x0, vl1
-+[^:]+: 0430f040 sqincb x0, vl2
-+[^:]+: 0430f040 sqincb x0, vl2
-+[^:]+: 0430f040 sqincb x0, vl2
-+[^:]+: 0430f060 sqincb x0, vl3
-+[^:]+: 0430f060 sqincb x0, vl3
-+[^:]+: 0430f060 sqincb x0, vl3
-+[^:]+: 0430f080 sqincb x0, vl4
-+[^:]+: 0430f080 sqincb x0, vl4
-+[^:]+: 0430f080 sqincb x0, vl4
-+[^:]+: 0430f0a0 sqincb x0, vl5
-+[^:]+: 0430f0a0 sqincb x0, vl5
-+[^:]+: 0430f0a0 sqincb x0, vl5
-+[^:]+: 0430f0c0 sqincb x0, vl6
-+[^:]+: 0430f0c0 sqincb x0, vl6
-+[^:]+: 0430f0c0 sqincb x0, vl6
-+[^:]+: 0430f0e0 sqincb x0, vl7
-+[^:]+: 0430f0e0 sqincb x0, vl7
-+[^:]+: 0430f0e0 sqincb x0, vl7
-+[^:]+: 0430f100 sqincb x0, vl8
-+[^:]+: 0430f100 sqincb x0, vl8
-+[^:]+: 0430f100 sqincb x0, vl8
-+[^:]+: 0430f120 sqincb x0, vl16
-+[^:]+: 0430f120 sqincb x0, vl16
-+[^:]+: 0430f120 sqincb x0, vl16
-+[^:]+: 0430f140 sqincb x0, vl32
-+[^:]+: 0430f140 sqincb x0, vl32
-+[^:]+: 0430f140 sqincb x0, vl32
-+[^:]+: 0430f160 sqincb x0, vl64
-+[^:]+: 0430f160 sqincb x0, vl64
-+[^:]+: 0430f160 sqincb x0, vl64
-+[^:]+: 0430f180 sqincb x0, vl128
-+[^:]+: 0430f180 sqincb x0, vl128
-+[^:]+: 0430f180 sqincb x0, vl128
-+[^:]+: 0430f1a0 sqincb x0, vl256
-+[^:]+: 0430f1a0 sqincb x0, vl256
-+[^:]+: 0430f1a0 sqincb x0, vl256
-+[^:]+: 0430f1c0 sqincb x0, #14
-+[^:]+: 0430f1c0 sqincb x0, #14
-+[^:]+: 0430f1c0 sqincb x0, #14
-+[^:]+: 0430f1e0 sqincb x0, #15
-+[^:]+: 0430f1e0 sqincb x0, #15
-+[^:]+: 0430f1e0 sqincb x0, #15
-+[^:]+: 0430f200 sqincb x0, #16
-+[^:]+: 0430f200 sqincb x0, #16
-+[^:]+: 0430f200 sqincb x0, #16
-+[^:]+: 0430f220 sqincb x0, #17
-+[^:]+: 0430f220 sqincb x0, #17
-+[^:]+: 0430f220 sqincb x0, #17
-+[^:]+: 0430f240 sqincb x0, #18
-+[^:]+: 0430f240 sqincb x0, #18
-+[^:]+: 0430f240 sqincb x0, #18
-+[^:]+: 0430f260 sqincb x0, #19
-+[^:]+: 0430f260 sqincb x0, #19
-+[^:]+: 0430f260 sqincb x0, #19
-+[^:]+: 0430f280 sqincb x0, #20
-+[^:]+: 0430f280 sqincb x0, #20
-+[^:]+: 0430f280 sqincb x0, #20
-+[^:]+: 0430f2a0 sqincb x0, #21
-+[^:]+: 0430f2a0 sqincb x0, #21
-+[^:]+: 0430f2a0 sqincb x0, #21
-+[^:]+: 0430f2c0 sqincb x0, #22
-+[^:]+: 0430f2c0 sqincb x0, #22
-+[^:]+: 0430f2c0 sqincb x0, #22
-+[^:]+: 0430f2e0 sqincb x0, #23
-+[^:]+: 0430f2e0 sqincb x0, #23
-+[^:]+: 0430f2e0 sqincb x0, #23
-+[^:]+: 0430f300 sqincb x0, #24
-+[^:]+: 0430f300 sqincb x0, #24
-+[^:]+: 0430f300 sqincb x0, #24
-+[^:]+: 0430f320 sqincb x0, #25
-+[^:]+: 0430f320 sqincb x0, #25
-+[^:]+: 0430f320 sqincb x0, #25
-+[^:]+: 0430f340 sqincb x0, #26
-+[^:]+: 0430f340 sqincb x0, #26
-+[^:]+: 0430f340 sqincb x0, #26
-+[^:]+: 0430f360 sqincb x0, #27
-+[^:]+: 0430f360 sqincb x0, #27
-+[^:]+: 0430f360 sqincb x0, #27
-+[^:]+: 0430f380 sqincb x0, #28
-+[^:]+: 0430f380 sqincb x0, #28
-+[^:]+: 0430f380 sqincb x0, #28
-+[^:]+: 0430f3a0 sqincb x0, mul4
-+[^:]+: 0430f3a0 sqincb x0, mul4
-+[^:]+: 0430f3a0 sqincb x0, mul4
-+[^:]+: 0430f3c0 sqincb x0, mul3
-+[^:]+: 0430f3c0 sqincb x0, mul3
-+[^:]+: 0430f3c0 sqincb x0, mul3
-+[^:]+: 0430f3e0 sqincb x0
-+[^:]+: 0430f3e0 sqincb x0
-+[^:]+: 0430f3e0 sqincb x0
-+[^:]+: 0430f3e0 sqincb x0
-+[^:]+: 0437f000 sqincb x0, pow2, mul #8
-+[^:]+: 0437f000 sqincb x0, pow2, mul #8
-+[^:]+: 0438f000 sqincb x0, pow2, mul #9
-+[^:]+: 0438f000 sqincb x0, pow2, mul #9
-+[^:]+: 0439f000 sqincb x0, pow2, mul #10
-+[^:]+: 0439f000 sqincb x0, pow2, mul #10
-+[^:]+: 043ff000 sqincb x0, pow2, mul #16
-+[^:]+: 043ff000 sqincb x0, pow2, mul #16
-+[^:]+: 0420f000 sqincb x0, w0, pow2
-+[^:]+: 0420f000 sqincb x0, w0, pow2
-+[^:]+: 0420f000 sqincb x0, w0, pow2
-+[^:]+: 0420f001 sqincb x1, w1, pow2
-+[^:]+: 0420f001 sqincb x1, w1, pow2
-+[^:]+: 0420f001 sqincb x1, w1, pow2
-+[^:]+: 0420f01f sqincb xzr, wzr, pow2
-+[^:]+: 0420f01f sqincb xzr, wzr, pow2
-+[^:]+: 0420f01f sqincb xzr, wzr, pow2
-+[^:]+: 0420f002 sqincb x2, w2, pow2
-+[^:]+: 0420f002 sqincb x2, w2, pow2
-+[^:]+: 0420f002 sqincb x2, w2, pow2
-+[^:]+: 0420f020 sqincb x0, w0, vl1
-+[^:]+: 0420f020 sqincb x0, w0, vl1
-+[^:]+: 0420f020 sqincb x0, w0, vl1
-+[^:]+: 0420f040 sqincb x0, w0, vl2
-+[^:]+: 0420f040 sqincb x0, w0, vl2
-+[^:]+: 0420f040 sqincb x0, w0, vl2
-+[^:]+: 0420f060 sqincb x0, w0, vl3
-+[^:]+: 0420f060 sqincb x0, w0, vl3
-+[^:]+: 0420f060 sqincb x0, w0, vl3
-+[^:]+: 0420f080 sqincb x0, w0, vl4
-+[^:]+: 0420f080 sqincb x0, w0, vl4
-+[^:]+: 0420f080 sqincb x0, w0, vl4
-+[^:]+: 0420f0a0 sqincb x0, w0, vl5
-+[^:]+: 0420f0a0 sqincb x0, w0, vl5
-+[^:]+: 0420f0a0 sqincb x0, w0, vl5
-+[^:]+: 0420f0c0 sqincb x0, w0, vl6
-+[^:]+: 0420f0c0 sqincb x0, w0, vl6
-+[^:]+: 0420f0c0 sqincb x0, w0, vl6
-+[^:]+: 0420f0e0 sqincb x0, w0, vl7
-+[^:]+: 0420f0e0 sqincb x0, w0, vl7
-+[^:]+: 0420f0e0 sqincb x0, w0, vl7
-+[^:]+: 0420f100 sqincb x0, w0, vl8
-+[^:]+: 0420f100 sqincb x0, w0, vl8
-+[^:]+: 0420f100 sqincb x0, w0, vl8
-+[^:]+: 0420f120 sqincb x0, w0, vl16
-+[^:]+: 0420f120 sqincb x0, w0, vl16
-+[^:]+: 0420f120 sqincb x0, w0, vl16
-+[^:]+: 0420f140 sqincb x0, w0, vl32
-+[^:]+: 0420f140 sqincb x0, w0, vl32
-+[^:]+: 0420f140 sqincb x0, w0, vl32
-+[^:]+: 0420f160 sqincb x0, w0, vl64
-+[^:]+: 0420f160 sqincb x0, w0, vl64
-+[^:]+: 0420f160 sqincb x0, w0, vl64
-+[^:]+: 0420f180 sqincb x0, w0, vl128
-+[^:]+: 0420f180 sqincb x0, w0, vl128
-+[^:]+: 0420f180 sqincb x0, w0, vl128
-+[^:]+: 0420f1a0 sqincb x0, w0, vl256
-+[^:]+: 0420f1a0 sqincb x0, w0, vl256
-+[^:]+: 0420f1a0 sqincb x0, w0, vl256
-+[^:]+: 0420f1c0 sqincb x0, w0, #14
-+[^:]+: 0420f1c0 sqincb x0, w0, #14
-+[^:]+: 0420f1c0 sqincb x0, w0, #14
-+[^:]+: 0420f1e0 sqincb x0, w0, #15
-+[^:]+: 0420f1e0 sqincb x0, w0, #15
-+[^:]+: 0420f1e0 sqincb x0, w0, #15
-+[^:]+: 0420f200 sqincb x0, w0, #16
-+[^:]+: 0420f200 sqincb x0, w0, #16
-+[^:]+: 0420f200 sqincb x0, w0, #16
-+[^:]+: 0420f220 sqincb x0, w0, #17
-+[^:]+: 0420f220 sqincb x0, w0, #17
-+[^:]+: 0420f220 sqincb x0, w0, #17
-+[^:]+: 0420f240 sqincb x0, w0, #18
-+[^:]+: 0420f240 sqincb x0, w0, #18
-+[^:]+: 0420f240 sqincb x0, w0, #18
-+[^:]+: 0420f260 sqincb x0, w0, #19
-+[^:]+: 0420f260 sqincb x0, w0, #19
-+[^:]+: 0420f260 sqincb x0, w0, #19
-+[^:]+: 0420f280 sqincb x0, w0, #20
-+[^:]+: 0420f280 sqincb x0, w0, #20
-+[^:]+: 0420f280 sqincb x0, w0, #20
-+[^:]+: 0420f2a0 sqincb x0, w0, #21
-+[^:]+: 0420f2a0 sqincb x0, w0, #21
-+[^:]+: 0420f2a0 sqincb x0, w0, #21
-+[^:]+: 0420f2c0 sqincb x0, w0, #22
-+[^:]+: 0420f2c0 sqincb x0, w0, #22
-+[^:]+: 0420f2c0 sqincb x0, w0, #22
-+[^:]+: 0420f2e0 sqincb x0, w0, #23
-+[^:]+: 0420f2e0 sqincb x0, w0, #23
-+[^:]+: 0420f2e0 sqincb x0, w0, #23
-+[^:]+: 0420f300 sqincb x0, w0, #24
-+[^:]+: 0420f300 sqincb x0, w0, #24
-+[^:]+: 0420f300 sqincb x0, w0, #24
-+[^:]+: 0420f320 sqincb x0, w0, #25
-+[^:]+: 0420f320 sqincb x0, w0, #25
-+[^:]+: 0420f320 sqincb x0, w0, #25
-+[^:]+: 0420f340 sqincb x0, w0, #26
-+[^:]+: 0420f340 sqincb x0, w0, #26
-+[^:]+: 0420f340 sqincb x0, w0, #26
-+[^:]+: 0420f360 sqincb x0, w0, #27
-+[^:]+: 0420f360 sqincb x0, w0, #27
-+[^:]+: 0420f360 sqincb x0, w0, #27
-+[^:]+: 0420f380 sqincb x0, w0, #28
-+[^:]+: 0420f380 sqincb x0, w0, #28
-+[^:]+: 0420f380 sqincb x0, w0, #28
-+[^:]+: 0420f3a0 sqincb x0, w0, mul4
-+[^:]+: 0420f3a0 sqincb x0, w0, mul4
-+[^:]+: 0420f3a0 sqincb x0, w0, mul4
-+[^:]+: 0420f3c0 sqincb x0, w0, mul3
-+[^:]+: 0420f3c0 sqincb x0, w0, mul3
-+[^:]+: 0420f3c0 sqincb x0, w0, mul3
-+[^:]+: 0420f3e0 sqincb x0, w0
-+[^:]+: 0420f3e0 sqincb x0, w0
-+[^:]+: 0420f3e0 sqincb x0, w0
-+[^:]+: 0420f3e0 sqincb x0, w0
-+[^:]+: 0427f000 sqincb x0, w0, pow2, mul #8
-+[^:]+: 0427f000 sqincb x0, w0, pow2, mul #8
-+[^:]+: 0428f000 sqincb x0, w0, pow2, mul #9
-+[^:]+: 0428f000 sqincb x0, w0, pow2, mul #9
-+[^:]+: 0429f000 sqincb x0, w0, pow2, mul #10
-+[^:]+: 0429f000 sqincb x0, w0, pow2, mul #10
-+[^:]+: 042ff000 sqincb x0, w0, pow2, mul #16
-+[^:]+: 042ff000 sqincb x0, w0, pow2, mul #16
-+[^:]+: 04e0c000 sqincd z0.d, pow2
-+[^:]+: 04e0c000 sqincd z0.d, pow2
-+[^:]+: 04e0c000 sqincd z0.d, pow2
-+[^:]+: 04e0c001 sqincd z1.d, pow2
-+[^:]+: 04e0c001 sqincd z1.d, pow2
-+[^:]+: 04e0c001 sqincd z1.d, pow2
-+[^:]+: 04e0c01f sqincd z31.d, pow2
-+[^:]+: 04e0c01f sqincd z31.d, pow2
-+[^:]+: 04e0c01f sqincd z31.d, pow2
-+[^:]+: 04e0c020 sqincd z0.d, vl1
-+[^:]+: 04e0c020 sqincd z0.d, vl1
-+[^:]+: 04e0c020 sqincd z0.d, vl1
-+[^:]+: 04e0c040 sqincd z0.d, vl2
-+[^:]+: 04e0c040 sqincd z0.d, vl2
-+[^:]+: 04e0c040 sqincd z0.d, vl2
-+[^:]+: 04e0c060 sqincd z0.d, vl3
-+[^:]+: 04e0c060 sqincd z0.d, vl3
-+[^:]+: 04e0c060 sqincd z0.d, vl3
-+[^:]+: 04e0c080 sqincd z0.d, vl4
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-+[^:]+: 04e0c180 sqincd z0.d, vl128
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-+[^:]+: 04e0c1a0 sqincd z0.d, vl256
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-+[^:]+: 04f0f1c0 sqincd x0, #14
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-+[^:]+: 04e0f180 sqincd x0, w0, vl128
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-+[^:]+: 04e0f1a0 sqincd x0, w0, vl256
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-+[^:]+: 04e0f1c0 sqincd x0, w0, #14
-+[^:]+: 04e0f1c0 sqincd x0, w0, #14
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-+[^:]+: e567e000 st1w {z0.d}, p0, \[x0, #7, mul vl\]
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-+[^:]+: e568e000 st1w {z0.d}, p0, \[x0, #-8, mul vl\]
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-+[^:]+: e569e000 st1w {z0.d}, p0, \[x0, #-7, mul vl\]
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-+[^:]+: e56fe000 st1w {z0.d}, p0, \[x0, #-1, mul vl\]
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-+[^:]+: e4206000 st2b {z0.b, z1.b}, p0, \[x0, x0\]
-+[^:]+: e4206000 st2b {z0.b, z1.b}, p0, \[x0, x0\]
-+[^:]+: e4206000 st2b {z0.b, z1.b}, p0, \[x0, x0\]
-+[^:]+: e4206000 st2b {z0.b, z1.b}, p0, \[x0, x0\]
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-+[^:]+: e4206001 st2b {z1.b, z2.b}, p0, \[x0, x0\]
-+[^:]+: e4206001 st2b {z1.b, z2.b}, p0, \[x0, x0\]
-+[^:]+: e4206001 st2b {z1.b, z2.b}, p0, \[x0, x0\]
-+[^:]+: e4206001 st2b {z1.b, z2.b}, p0, \[x0, x0\]
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-+[^:]+: e420601f st2b {z31.b, z0.b}, p0, \[x0, x0\]
-+[^:]+: e420601f st2b {z31.b, z0.b}, p0, \[x0, x0\]
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-+[^:]+: e4206800 st2b {z0.b, z1.b}, p2, \[x0, x0\]
-+[^:]+: e4206800 st2b {z0.b, z1.b}, p2, \[x0, x0\]
-+[^:]+: e4206800 st2b {z0.b, z1.b}, p2, \[x0, x0\]
-+[^:]+: e4206800 st2b {z0.b, z1.b}, p2, \[x0, x0\]
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-+[^:]+: e4207c00 st2b {z0.b, z1.b}, p7, \[x0, x0\]
-+[^:]+: e4207c00 st2b {z0.b, z1.b}, p7, \[x0, x0\]
-+[^:]+: e4207c00 st2b {z0.b, z1.b}, p7, \[x0, x0\]
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-+[^:]+: e4206060 st2b {z0.b, z1.b}, p0, \[x3, x0\]
-+[^:]+: e4206060 st2b {z0.b, z1.b}, p0, \[x3, x0\]
-+[^:]+: e4206060 st2b {z0.b, z1.b}, p0, \[x3, x0\]
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-+[^:]+: e42063e0 st2b {z0.b, z1.b}, p0, \[sp, x0\]
-+[^:]+: e42063e0 st2b {z0.b, z1.b}, p0, \[sp, x0\]
-+[^:]+: e42063e0 st2b {z0.b, z1.b}, p0, \[sp, x0\]
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-+[^:]+: e4246000 st2b {z0.b, z1.b}, p0, \[x0, x4\]
-+[^:]+: e4246000 st2b {z0.b, z1.b}, p0, \[x0, x4\]
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-+[^:]+: e43e6000 st2b {z0.b, z1.b}, p0, \[x0, x30\]
-+[^:]+: e43e6000 st2b {z0.b, z1.b}, p0, \[x0, x30\]
-+[^:]+: e43e6000 st2b {z0.b, z1.b}, p0, \[x0, x30\]
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-+[^:]+: e430e000 st2b {z0.b, z1.b}, p0, \[x0\]
-+[^:]+: e430e000 st2b {z0.b, z1.b}, p0, \[x0\]
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-+[^:]+: e430e001 st2b {z1.b, z2.b}, p0, \[x0\]
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-+[^:]+: e430e001 st2b {z1.b, z2.b}, p0, \[x0\]
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-+[^:]+: e430e01f st2b {z31.b, z0.b}, p0, \[x0\]
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-+[^:]+: e430e800 st2b {z0.b, z1.b}, p2, \[x0\]
-+[^:]+: e430e800 st2b {z0.b, z1.b}, p2, \[x0\]
-+[^:]+: e430e800 st2b {z0.b, z1.b}, p2, \[x0\]
-+[^:]+: e430e800 st2b {z0.b, z1.b}, p2, \[x0\]
-+[^:]+: e430e800 st2b {z0.b, z1.b}, p2, \[x0\]
-+[^:]+: e430e800 st2b {z0.b, z1.b}, p2, \[x0\]
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-+[^:]+: e430fc00 st2b {z0.b, z1.b}, p7, \[x0\]
-+[^:]+: e430fc00 st2b {z0.b, z1.b}, p7, \[x0\]
-+[^:]+: e430fc00 st2b {z0.b, z1.b}, p7, \[x0\]
-+[^:]+: e430fc00 st2b {z0.b, z1.b}, p7, \[x0\]
-+[^:]+: e430fc00 st2b {z0.b, z1.b}, p7, \[x0\]
-+[^:]+: e430fc00 st2b {z0.b, z1.b}, p7, \[x0\]
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-+[^:]+: e430e060 st2b {z0.b, z1.b}, p0, \[x3\]
-+[^:]+: e430e060 st2b {z0.b, z1.b}, p0, \[x3\]
-+[^:]+: e430e060 st2b {z0.b, z1.b}, p0, \[x3\]
-+[^:]+: e430e060 st2b {z0.b, z1.b}, p0, \[x3\]
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-+[^:]+: e430e3e0 st2b {z0.b, z1.b}, p0, \[sp\]
-+[^:]+: e430e3e0 st2b {z0.b, z1.b}, p0, \[sp\]
-+[^:]+: e430e3e0 st2b {z0.b, z1.b}, p0, \[sp\]
-+[^:]+: e430e3e0 st2b {z0.b, z1.b}, p0, \[sp\]
-+[^:]+: e430e3e0 st2b {z0.b, z1.b}, p0, \[sp\]
-+[^:]+: e430e3e0 st2b {z0.b, z1.b}, p0, \[sp\]
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-+[^:]+: e437e000 st2b {z0.b, z1.b}, p0, \[x0, #14, mul vl\]
-+[^:]+: e437e000 st2b {z0.b, z1.b}, p0, \[x0, #14, mul vl\]
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-+[^:]+: e438e000 st2b {z0.b, z1.b}, p0, \[x0, #-16, mul vl\]
-+[^:]+: e438e000 st2b {z0.b, z1.b}, p0, \[x0, #-16, mul vl\]
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-+[^:]+: e439e000 st2b {z0.b, z1.b}, p0, \[x0, #-14, mul vl\]
-+[^:]+: e439e000 st2b {z0.b, z1.b}, p0, \[x0, #-14, mul vl\]
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-+[^:]+: e43fe000 st2b {z0.b, z1.b}, p0, \[x0, #-2, mul vl\]
-+[^:]+: e43fe000 st2b {z0.b, z1.b}, p0, \[x0, #-2, mul vl\]
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-+[^:]+: e5a06000 st2d {z0.d, z1.d}, p0, \[x0, x0, lsl #3\]
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-+[^:]+: e5a0601f st2d {z31.d, z0.d}, p0, \[x0, x0, lsl #3\]
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-+[^:]+: e5a06800 st2d {z0.d, z1.d}, p2, \[x0, x0, lsl #3\]
-+[^:]+: e5a06800 st2d {z0.d, z1.d}, p2, \[x0, x0, lsl #3\]
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-+[^:]+: e5a07c00 st2d {z0.d, z1.d}, p7, \[x0, x0, lsl #3\]
-+[^:]+: e5a07c00 st2d {z0.d, z1.d}, p7, \[x0, x0, lsl #3\]
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-+[^:]+: e5a06060 st2d {z0.d, z1.d}, p0, \[x3, x0, lsl #3\]
-+[^:]+: e5a06060 st2d {z0.d, z1.d}, p0, \[x3, x0, lsl #3\]
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-+[^:]+: e5a063e0 st2d {z0.d, z1.d}, p0, \[sp, x0, lsl #3\]
-+[^:]+: e5a063e0 st2d {z0.d, z1.d}, p0, \[sp, x0, lsl #3\]
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-+[^:]+: e5a46000 st2d {z0.d, z1.d}, p0, \[x0, x4, lsl #3\]
-+[^:]+: e5a46000 st2d {z0.d, z1.d}, p0, \[x0, x4, lsl #3\]
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-+[^:]+: e5be6000 st2d {z0.d, z1.d}, p0, \[x0, x30, lsl #3\]
-+[^:]+: e5be6000 st2d {z0.d, z1.d}, p0, \[x0, x30, lsl #3\]
-+[^:]+: e5b0e000 st2d {z0.d, z1.d}, p0, \[x0\]
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-+[^:]+: e5b0e000 st2d {z0.d, z1.d}, p0, \[x0\]
-+[^:]+: e5b0e000 st2d {z0.d, z1.d}, p0, \[x0\]
-+[^:]+: e5b0e000 st2d {z0.d, z1.d}, p0, \[x0\]
-+[^:]+: e5b0e000 st2d {z0.d, z1.d}, p0, \[x0\]
-+[^:]+: e5b0e000 st2d {z0.d, z1.d}, p0, \[x0\]
-+[^:]+: e5b0e001 st2d {z1.d, z2.d}, p0, \[x0\]
-+[^:]+: e5b0e001 st2d {z1.d, z2.d}, p0, \[x0\]
-+[^:]+: e5b0e001 st2d {z1.d, z2.d}, p0, \[x0\]
-+[^:]+: e5b0e001 st2d {z1.d, z2.d}, p0, \[x0\]
-+[^:]+: e5b0e001 st2d {z1.d, z2.d}, p0, \[x0\]
-+[^:]+: e5b0e001 st2d {z1.d, z2.d}, p0, \[x0\]
-+[^:]+: e5b0e001 st2d {z1.d, z2.d}, p0, \[x0\]
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-+[^:]+: e5b0e800 st2d {z0.d, z1.d}, p2, \[x0\]
-+[^:]+: e5b0e800 st2d {z0.d, z1.d}, p2, \[x0\]
-+[^:]+: e5b0e800 st2d {z0.d, z1.d}, p2, \[x0\]
-+[^:]+: e5b0e800 st2d {z0.d, z1.d}, p2, \[x0\]
-+[^:]+: e5b0e800 st2d {z0.d, z1.d}, p2, \[x0\]
-+[^:]+: e5b0e800 st2d {z0.d, z1.d}, p2, \[x0\]
-+[^:]+: e5b0fc00 st2d {z0.d, z1.d}, p7, \[x0\]
-+[^:]+: e5b0fc00 st2d {z0.d, z1.d}, p7, \[x0\]
-+[^:]+: e5b0fc00 st2d {z0.d, z1.d}, p7, \[x0\]
-+[^:]+: e5b0fc00 st2d {z0.d, z1.d}, p7, \[x0\]
-+[^:]+: e5b0fc00 st2d {z0.d, z1.d}, p7, \[x0\]
-+[^:]+: e5b0fc00 st2d {z0.d, z1.d}, p7, \[x0\]
-+[^:]+: e5b0fc00 st2d {z0.d, z1.d}, p7, \[x0\]
-+[^:]+: e5b0e060 st2d {z0.d, z1.d}, p0, \[x3\]
-+[^:]+: e5b0e060 st2d {z0.d, z1.d}, p0, \[x3\]
-+[^:]+: e5b0e060 st2d {z0.d, z1.d}, p0, \[x3\]
-+[^:]+: e5b0e060 st2d {z0.d, z1.d}, p0, \[x3\]
-+[^:]+: e5b0e060 st2d {z0.d, z1.d}, p0, \[x3\]
-+[^:]+: e5b0e060 st2d {z0.d, z1.d}, p0, \[x3\]
-+[^:]+: e5b0e060 st2d {z0.d, z1.d}, p0, \[x3\]
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-+[^:]+: e5b0e3e0 st2d {z0.d, z1.d}, p0, \[sp\]
-+[^:]+: e5b0e3e0 st2d {z0.d, z1.d}, p0, \[sp\]
-+[^:]+: e5b0e3e0 st2d {z0.d, z1.d}, p0, \[sp\]
-+[^:]+: e5b0e3e0 st2d {z0.d, z1.d}, p0, \[sp\]
-+[^:]+: e5b0e3e0 st2d {z0.d, z1.d}, p0, \[sp\]
-+[^:]+: e5b0e3e0 st2d {z0.d, z1.d}, p0, \[sp\]
-+[^:]+: e5b7e000 st2d {z0.d, z1.d}, p0, \[x0, #14, mul vl\]
-+[^:]+: e5b7e000 st2d {z0.d, z1.d}, p0, \[x0, #14, mul vl\]
-+[^:]+: e5b7e000 st2d {z0.d, z1.d}, p0, \[x0, #14, mul vl\]
-+[^:]+: e5b8e000 st2d {z0.d, z1.d}, p0, \[x0, #-16, mul vl\]
-+[^:]+: e5b8e000 st2d {z0.d, z1.d}, p0, \[x0, #-16, mul vl\]
-+[^:]+: e5b8e000 st2d {z0.d, z1.d}, p0, \[x0, #-16, mul vl\]
-+[^:]+: e5b9e000 st2d {z0.d, z1.d}, p0, \[x0, #-14, mul vl\]
-+[^:]+: e5b9e000 st2d {z0.d, z1.d}, p0, \[x0, #-14, mul vl\]
-+[^:]+: e5b9e000 st2d {z0.d, z1.d}, p0, \[x0, #-14, mul vl\]
-+[^:]+: e5bfe000 st2d {z0.d, z1.d}, p0, \[x0, #-2, mul vl\]
-+[^:]+: e5bfe000 st2d {z0.d, z1.d}, p0, \[x0, #-2, mul vl\]
-+[^:]+: e5bfe000 st2d {z0.d, z1.d}, p0, \[x0, #-2, mul vl\]
-+[^:]+: e4a06000 st2h {z0.h, z1.h}, p0, \[x0, x0, lsl #1\]
-+[^:]+: e4a06000 st2h {z0.h, z1.h}, p0, \[x0, x0, lsl #1\]
-+[^:]+: e4a06000 st2h {z0.h, z1.h}, p0, \[x0, x0, lsl #1\]
-+[^:]+: e4a06001 st2h {z1.h, z2.h}, p0, \[x0, x0, lsl #1\]
-+[^:]+: e4a06001 st2h {z1.h, z2.h}, p0, \[x0, x0, lsl #1\]
-+[^:]+: e4a06001 st2h {z1.h, z2.h}, p0, \[x0, x0, lsl #1\]
-+[^:]+: e4a0601f st2h {z31.h, z0.h}, p0, \[x0, x0, lsl #1\]
-+[^:]+: e4a0601f st2h {z31.h, z0.h}, p0, \[x0, x0, lsl #1\]
-+[^:]+: e4a06800 st2h {z0.h, z1.h}, p2, \[x0, x0, lsl #1\]
-+[^:]+: e4a06800 st2h {z0.h, z1.h}, p2, \[x0, x0, lsl #1\]
-+[^:]+: e4a06800 st2h {z0.h, z1.h}, p2, \[x0, x0, lsl #1\]
-+[^:]+: e4a07c00 st2h {z0.h, z1.h}, p7, \[x0, x0, lsl #1\]
-+[^:]+: e4a07c00 st2h {z0.h, z1.h}, p7, \[x0, x0, lsl #1\]
-+[^:]+: e4a07c00 st2h {z0.h, z1.h}, p7, \[x0, x0, lsl #1\]
-+[^:]+: e4a06060 st2h {z0.h, z1.h}, p0, \[x3, x0, lsl #1\]
-+[^:]+: e4a06060 st2h {z0.h, z1.h}, p0, \[x3, x0, lsl #1\]
-+[^:]+: e4a06060 st2h {z0.h, z1.h}, p0, \[x3, x0, lsl #1\]
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-+[^:]+: e4a063e0 st2h {z0.h, z1.h}, p0, \[sp, x0, lsl #1\]
-+[^:]+: e4a063e0 st2h {z0.h, z1.h}, p0, \[sp, x0, lsl #1\]
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-+[^:]+: e4a46000 st2h {z0.h, z1.h}, p0, \[x0, x4, lsl #1\]
-+[^:]+: e4a46000 st2h {z0.h, z1.h}, p0, \[x0, x4, lsl #1\]
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-+[^:]+: e4be6000 st2h {z0.h, z1.h}, p0, \[x0, x30, lsl #1\]
-+[^:]+: e4be6000 st2h {z0.h, z1.h}, p0, \[x0, x30, lsl #1\]
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-+[^:]+: e4b0fc00 st2h {z0.h, z1.h}, p7, \[x0\]
-+[^:]+: e4b0fc00 st2h {z0.h, z1.h}, p7, \[x0\]
-+[^:]+: e4b0fc00 st2h {z0.h, z1.h}, p7, \[x0\]
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-+[^:]+: e4b7e000 st2h {z0.h, z1.h}, p0, \[x0, #14, mul vl\]
-+[^:]+: e4b7e000 st2h {z0.h, z1.h}, p0, \[x0, #14, mul vl\]
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-+[^:]+: e4b8e000 st2h {z0.h, z1.h}, p0, \[x0, #-16, mul vl\]
-+[^:]+: e4b8e000 st2h {z0.h, z1.h}, p0, \[x0, #-16, mul vl\]
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-+[^:]+: e5206800 st2w {z0.s, z1.s}, p2, \[x0, x0, lsl #2\]
-+[^:]+: e5206800 st2w {z0.s, z1.s}, p2, \[x0, x0, lsl #2\]
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-+[^:]+: e5207c00 st2w {z0.s, z1.s}, p7, \[x0, x0, lsl #2\]
-+[^:]+: e5207c00 st2w {z0.s, z1.s}, p7, \[x0, x0, lsl #2\]
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-+[^:]+: e5206060 st2w {z0.s, z1.s}, p0, \[x3, x0, lsl #2\]
-+[^:]+: e5206060 st2w {z0.s, z1.s}, p0, \[x3, x0, lsl #2\]
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-+[^:]+: e52063e0 st2w {z0.s, z1.s}, p0, \[sp, x0, lsl #2\]
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-+[^:]+: e53e6000 st2w {z0.s, z1.s}, p0, \[x0, x30, lsl #2\]
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-+[^:]+: e53fe000 st2w {z0.s, z1.s}, p0, \[x0, #-2, mul vl\]
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-+[^:]+: e4406000 st3b {z0.b-z2.b}, p0, \[x0, x0\]
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-+[^:]+: e5a00400 str p0, \[x0, #-255, mul vl\]
-+[^:]+: e5a00400 str p0, \[x0, #-255, mul vl\]
-+[^:]+: e5bf1c00 str p0, \[x0, #-1, mul vl\]
-+[^:]+: e5bf1c00 str p0, \[x0, #-1, mul vl\]
-+[^:]+: e5804000 str z0, \[x0\]
-+[^:]+: e5804000 str z0, \[x0\]
-+[^:]+: e5804000 str z0, \[x0\]
-+[^:]+: e5804000 str z0, \[x0\]
-+[^:]+: e5804001 str z1, \[x0\]
-+[^:]+: e5804001 str z1, \[x0\]
-+[^:]+: e5804001 str z1, \[x0\]
-+[^:]+: e5804001 str z1, \[x0\]
-+[^:]+: e580401f str z31, \[x0\]
-+[^:]+: e580401f str z31, \[x0\]
-+[^:]+: e580401f str z31, \[x0\]
-+[^:]+: e580401f str z31, \[x0\]
-+[^:]+: e5804040 str z0, \[x2\]
-+[^:]+: e5804040 str z0, \[x2\]
-+[^:]+: e5804040 str z0, \[x2\]
-+[^:]+: e5804040 str z0, \[x2\]
-+[^:]+: e58043e0 str z0, \[sp\]
-+[^:]+: e58043e0 str z0, \[sp\]
-+[^:]+: e58043e0 str z0, \[sp\]
-+[^:]+: e58043e0 str z0, \[sp\]
-+[^:]+: e59f5c00 str z0, \[x0, #255, mul vl\]
-+[^:]+: e59f5c00 str z0, \[x0, #255, mul vl\]
-+[^:]+: e5a04000 str z0, \[x0, #-256, mul vl\]
-+[^:]+: e5a04000 str z0, \[x0, #-256, mul vl\]
-+[^:]+: e5a04400 str z0, \[x0, #-255, mul vl\]
-+[^:]+: e5a04400 str z0, \[x0, #-255, mul vl\]
-+[^:]+: e5bf5c00 str z0, \[x0, #-1, mul vl\]
-+[^:]+: e5bf5c00 str z0, \[x0, #-1, mul vl\]
-+[^:]+: 04200400 sub z0.b, z0.b, z0.b
-+[^:]+: 04200400 sub z0.b, z0.b, z0.b
-+[^:]+: 04200401 sub z1.b, z0.b, z0.b
-+[^:]+: 04200401 sub z1.b, z0.b, z0.b
-+[^:]+: 0420041f sub z31.b, z0.b, z0.b
-+[^:]+: 0420041f sub z31.b, z0.b, z0.b
-+[^:]+: 04200440 sub z0.b, z2.b, z0.b
-+[^:]+: 04200440 sub z0.b, z2.b, z0.b
-+[^:]+: 042007e0 sub z0.b, z31.b, z0.b
-+[^:]+: 042007e0 sub z0.b, z31.b, z0.b
-+[^:]+: 04230400 sub z0.b, z0.b, z3.b
-+[^:]+: 04230400 sub z0.b, z0.b, z3.b
-+[^:]+: 043f0400 sub z0.b, z0.b, z31.b
-+[^:]+: 043f0400 sub z0.b, z0.b, z31.b
-+[^:]+: 04600400 sub z0.h, z0.h, z0.h
-+[^:]+: 04600400 sub z0.h, z0.h, z0.h
-+[^:]+: 04600401 sub z1.h, z0.h, z0.h
-+[^:]+: 04600401 sub z1.h, z0.h, z0.h
-+[^:]+: 0460041f sub z31.h, z0.h, z0.h
-+[^:]+: 0460041f sub z31.h, z0.h, z0.h
-+[^:]+: 04600440 sub z0.h, z2.h, z0.h
-+[^:]+: 04600440 sub z0.h, z2.h, z0.h
-+[^:]+: 046007e0 sub z0.h, z31.h, z0.h
-+[^:]+: 046007e0 sub z0.h, z31.h, z0.h
-+[^:]+: 04630400 sub z0.h, z0.h, z3.h
-+[^:]+: 04630400 sub z0.h, z0.h, z3.h
-+[^:]+: 047f0400 sub z0.h, z0.h, z31.h
-+[^:]+: 047f0400 sub z0.h, z0.h, z31.h
-+[^:]+: 04a00400 sub z0.s, z0.s, z0.s
-+[^:]+: 04a00400 sub z0.s, z0.s, z0.s
-+[^:]+: 04a00401 sub z1.s, z0.s, z0.s
-+[^:]+: 04a00401 sub z1.s, z0.s, z0.s
-+[^:]+: 04a0041f sub z31.s, z0.s, z0.s
-+[^:]+: 04a0041f sub z31.s, z0.s, z0.s
-+[^:]+: 04a00440 sub z0.s, z2.s, z0.s
-+[^:]+: 04a00440 sub z0.s, z2.s, z0.s
-+[^:]+: 04a007e0 sub z0.s, z31.s, z0.s
-+[^:]+: 04a007e0 sub z0.s, z31.s, z0.s
-+[^:]+: 04a30400 sub z0.s, z0.s, z3.s
-+[^:]+: 04a30400 sub z0.s, z0.s, z3.s
-+[^:]+: 04bf0400 sub z0.s, z0.s, z31.s
-+[^:]+: 04bf0400 sub z0.s, z0.s, z31.s
-+[^:]+: 04e00400 sub z0.d, z0.d, z0.d
-+[^:]+: 04e00400 sub z0.d, z0.d, z0.d
-+[^:]+: 04e00401 sub z1.d, z0.d, z0.d
-+[^:]+: 04e00401 sub z1.d, z0.d, z0.d
-+[^:]+: 04e0041f sub z31.d, z0.d, z0.d
-+[^:]+: 04e0041f sub z31.d, z0.d, z0.d
-+[^:]+: 04e00440 sub z0.d, z2.d, z0.d
-+[^:]+: 04e00440 sub z0.d, z2.d, z0.d
-+[^:]+: 04e007e0 sub z0.d, z31.d, z0.d
-+[^:]+: 04e007e0 sub z0.d, z31.d, z0.d
-+[^:]+: 04e30400 sub z0.d, z0.d, z3.d
-+[^:]+: 04e30400 sub z0.d, z0.d, z3.d
-+[^:]+: 04ff0400 sub z0.d, z0.d, z31.d
-+[^:]+: 04ff0400 sub z0.d, z0.d, z31.d
-+[^:]+: 2521c000 sub z0.b, z0.b, #0
-+[^:]+: 2521c000 sub z0.b, z0.b, #0
-+[^:]+: 2521c000 sub z0.b, z0.b, #0
-+[^:]+: 2521c001 sub z1.b, z1.b, #0
-+[^:]+: 2521c001 sub z1.b, z1.b, #0
-+[^:]+: 2521c001 sub z1.b, z1.b, #0
-+[^:]+: 2521c01f sub z31.b, z31.b, #0
-+[^:]+: 2521c01f sub z31.b, z31.b, #0
-+[^:]+: 2521c01f sub z31.b, z31.b, #0
-+[^:]+: 2521c002 sub z2.b, z2.b, #0
-+[^:]+: 2521c002 sub z2.b, z2.b, #0
-+[^:]+: 2521c002 sub z2.b, z2.b, #0
-+[^:]+: 2521cfe0 sub z0.b, z0.b, #127
-+[^:]+: 2521cfe0 sub z0.b, z0.b, #127
-+[^:]+: 2521cfe0 sub z0.b, z0.b, #127
-+[^:]+: 2521d000 sub z0.b, z0.b, #128
-+[^:]+: 2521d000 sub z0.b, z0.b, #128
-+[^:]+: 2521d000 sub z0.b, z0.b, #128
-+[^:]+: 2521d020 sub z0.b, z0.b, #129
-+[^:]+: 2521d020 sub z0.b, z0.b, #129
-+[^:]+: 2521d020 sub z0.b, z0.b, #129
-+[^:]+: 2521dfe0 sub z0.b, z0.b, #255
-+[^:]+: 2521dfe0 sub z0.b, z0.b, #255
-+[^:]+: 2521dfe0 sub z0.b, z0.b, #255
-+[^:]+: 2561c000 sub z0.h, z0.h, #0
-+[^:]+: 2561c000 sub z0.h, z0.h, #0
-+[^:]+: 2561c000 sub z0.h, z0.h, #0
-+[^:]+: 2561c001 sub z1.h, z1.h, #0
-+[^:]+: 2561c001 sub z1.h, z1.h, #0
-+[^:]+: 2561c001 sub z1.h, z1.h, #0
-+[^:]+: 2561c01f sub z31.h, z31.h, #0
-+[^:]+: 2561c01f sub z31.h, z31.h, #0
-+[^:]+: 2561c01f sub z31.h, z31.h, #0
-+[^:]+: 2561c002 sub z2.h, z2.h, #0
-+[^:]+: 2561c002 sub z2.h, z2.h, #0
-+[^:]+: 2561c002 sub z2.h, z2.h, #0
-+[^:]+: 2561cfe0 sub z0.h, z0.h, #127
-+[^:]+: 2561cfe0 sub z0.h, z0.h, #127
-+[^:]+: 2561cfe0 sub z0.h, z0.h, #127
-+[^:]+: 2561d000 sub z0.h, z0.h, #128
-+[^:]+: 2561d000 sub z0.h, z0.h, #128
-+[^:]+: 2561d000 sub z0.h, z0.h, #128
-+[^:]+: 2561d020 sub z0.h, z0.h, #129
-+[^:]+: 2561d020 sub z0.h, z0.h, #129
-+[^:]+: 2561d020 sub z0.h, z0.h, #129
-+[^:]+: 2561dfe0 sub z0.h, z0.h, #255
-+[^:]+: 2561dfe0 sub z0.h, z0.h, #255
-+[^:]+: 2561dfe0 sub z0.h, z0.h, #255
-+[^:]+: 2561e000 sub z0.h, z0.h, #0, lsl #8
-+[^:]+: 2561e000 sub z0.h, z0.h, #0, lsl #8
-+[^:]+: 2561efe0 sub z0.h, z0.h, #32512
-+[^:]+: 2561efe0 sub z0.h, z0.h, #32512
-+[^:]+: 2561efe0 sub z0.h, z0.h, #32512
-+[^:]+: 2561efe0 sub z0.h, z0.h, #32512
-+[^:]+: 2561f000 sub z0.h, z0.h, #32768
-+[^:]+: 2561f000 sub z0.h, z0.h, #32768
-+[^:]+: 2561f000 sub z0.h, z0.h, #32768
-+[^:]+: 2561f000 sub z0.h, z0.h, #32768
-+[^:]+: 2561f020 sub z0.h, z0.h, #33024
-+[^:]+: 2561f020 sub z0.h, z0.h, #33024
-+[^:]+: 2561f020 sub z0.h, z0.h, #33024
-+[^:]+: 2561f020 sub z0.h, z0.h, #33024
-+[^:]+: 2561ffe0 sub z0.h, z0.h, #65280
-+[^:]+: 2561ffe0 sub z0.h, z0.h, #65280
-+[^:]+: 2561ffe0 sub z0.h, z0.h, #65280
-+[^:]+: 2561ffe0 sub z0.h, z0.h, #65280
-+[^:]+: 25a1c000 sub z0.s, z0.s, #0
-+[^:]+: 25a1c000 sub z0.s, z0.s, #0
-+[^:]+: 25a1c000 sub z0.s, z0.s, #0
-+[^:]+: 25a1c001 sub z1.s, z1.s, #0
-+[^:]+: 25a1c001 sub z1.s, z1.s, #0
-+[^:]+: 25a1c001 sub z1.s, z1.s, #0
-+[^:]+: 25a1c01f sub z31.s, z31.s, #0
-+[^:]+: 25a1c01f sub z31.s, z31.s, #0
-+[^:]+: 25a1c01f sub z31.s, z31.s, #0
-+[^:]+: 25a1c002 sub z2.s, z2.s, #0
-+[^:]+: 25a1c002 sub z2.s, z2.s, #0
-+[^:]+: 25a1c002 sub z2.s, z2.s, #0
-+[^:]+: 25a1cfe0 sub z0.s, z0.s, #127
-+[^:]+: 25a1cfe0 sub z0.s, z0.s, #127
-+[^:]+: 25a1cfe0 sub z0.s, z0.s, #127
-+[^:]+: 25a1d000 sub z0.s, z0.s, #128
-+[^:]+: 25a1d000 sub z0.s, z0.s, #128
-+[^:]+: 25a1d000 sub z0.s, z0.s, #128
-+[^:]+: 25a1d020 sub z0.s, z0.s, #129
-+[^:]+: 25a1d020 sub z0.s, z0.s, #129
-+[^:]+: 25a1d020 sub z0.s, z0.s, #129
-+[^:]+: 25a1dfe0 sub z0.s, z0.s, #255
-+[^:]+: 25a1dfe0 sub z0.s, z0.s, #255
-+[^:]+: 25a1dfe0 sub z0.s, z0.s, #255
-+[^:]+: 25a1e000 sub z0.s, z0.s, #0, lsl #8
-+[^:]+: 25a1e000 sub z0.s, z0.s, #0, lsl #8
-+[^:]+: 25a1efe0 sub z0.s, z0.s, #32512
-+[^:]+: 25a1efe0 sub z0.s, z0.s, #32512
-+[^:]+: 25a1efe0 sub z0.s, z0.s, #32512
-+[^:]+: 25a1efe0 sub z0.s, z0.s, #32512
-+[^:]+: 25a1f000 sub z0.s, z0.s, #32768
-+[^:]+: 25a1f000 sub z0.s, z0.s, #32768
-+[^:]+: 25a1f000 sub z0.s, z0.s, #32768
-+[^:]+: 25a1f000 sub z0.s, z0.s, #32768
-+[^:]+: 25a1f020 sub z0.s, z0.s, #33024
-+[^:]+: 25a1f020 sub z0.s, z0.s, #33024
-+[^:]+: 25a1f020 sub z0.s, z0.s, #33024
-+[^:]+: 25a1f020 sub z0.s, z0.s, #33024
-+[^:]+: 25a1ffe0 sub z0.s, z0.s, #65280
-+[^:]+: 25a1ffe0 sub z0.s, z0.s, #65280
-+[^:]+: 25a1ffe0 sub z0.s, z0.s, #65280
-+[^:]+: 25a1ffe0 sub z0.s, z0.s, #65280
-+[^:]+: 25e1c000 sub z0.d, z0.d, #0
-+[^:]+: 25e1c000 sub z0.d, z0.d, #0
-+[^:]+: 25e1c000 sub z0.d, z0.d, #0
-+[^:]+: 25e1c001 sub z1.d, z1.d, #0
-+[^:]+: 25e1c001 sub z1.d, z1.d, #0
-+[^:]+: 25e1c001 sub z1.d, z1.d, #0
-+[^:]+: 25e1c01f sub z31.d, z31.d, #0
-+[^:]+: 25e1c01f sub z31.d, z31.d, #0
-+[^:]+: 25e1c01f sub z31.d, z31.d, #0
-+[^:]+: 25e1c002 sub z2.d, z2.d, #0
-+[^:]+: 25e1c002 sub z2.d, z2.d, #0
-+[^:]+: 25e1c002 sub z2.d, z2.d, #0
-+[^:]+: 25e1cfe0 sub z0.d, z0.d, #127
-+[^:]+: 25e1cfe0 sub z0.d, z0.d, #127
-+[^:]+: 25e1cfe0 sub z0.d, z0.d, #127
-+[^:]+: 25e1d000 sub z0.d, z0.d, #128
-+[^:]+: 25e1d000 sub z0.d, z0.d, #128
-+[^:]+: 25e1d000 sub z0.d, z0.d, #128
-+[^:]+: 25e1d020 sub z0.d, z0.d, #129
-+[^:]+: 25e1d020 sub z0.d, z0.d, #129
-+[^:]+: 25e1d020 sub z0.d, z0.d, #129
-+[^:]+: 25e1dfe0 sub z0.d, z0.d, #255
-+[^:]+: 25e1dfe0 sub z0.d, z0.d, #255
-+[^:]+: 25e1dfe0 sub z0.d, z0.d, #255
-+[^:]+: 25e1e000 sub z0.d, z0.d, #0, lsl #8
-+[^:]+: 25e1e000 sub z0.d, z0.d, #0, lsl #8
-+[^:]+: 25e1efe0 sub z0.d, z0.d, #32512
-+[^:]+: 25e1efe0 sub z0.d, z0.d, #32512
-+[^:]+: 25e1efe0 sub z0.d, z0.d, #32512
-+[^:]+: 25e1efe0 sub z0.d, z0.d, #32512
-+[^:]+: 25e1f000 sub z0.d, z0.d, #32768
-+[^:]+: 25e1f000 sub z0.d, z0.d, #32768
-+[^:]+: 25e1f000 sub z0.d, z0.d, #32768
-+[^:]+: 25e1f000 sub z0.d, z0.d, #32768
-+[^:]+: 25e1f020 sub z0.d, z0.d, #33024
-+[^:]+: 25e1f020 sub z0.d, z0.d, #33024
-+[^:]+: 25e1f020 sub z0.d, z0.d, #33024
-+[^:]+: 25e1f020 sub z0.d, z0.d, #33024
-+[^:]+: 25e1ffe0 sub z0.d, z0.d, #65280
-+[^:]+: 25e1ffe0 sub z0.d, z0.d, #65280
-+[^:]+: 25e1ffe0 sub z0.d, z0.d, #65280
-+[^:]+: 25e1ffe0 sub z0.d, z0.d, #65280
-+[^:]+: 04010000 sub z0.b, p0/m, z0.b, z0.b
-+[^:]+: 04010000 sub z0.b, p0/m, z0.b, z0.b
-+[^:]+: 04010001 sub z1.b, p0/m, z1.b, z0.b
-+[^:]+: 04010001 sub z1.b, p0/m, z1.b, z0.b
-+[^:]+: 0401001f sub z31.b, p0/m, z31.b, z0.b
-+[^:]+: 0401001f sub z31.b, p0/m, z31.b, z0.b
-+[^:]+: 04010800 sub z0.b, p2/m, z0.b, z0.b
-+[^:]+: 04010800 sub z0.b, p2/m, z0.b, z0.b
-+[^:]+: 04011c00 sub z0.b, p7/m, z0.b, z0.b
-+[^:]+: 04011c00 sub z0.b, p7/m, z0.b, z0.b
-+[^:]+: 04010003 sub z3.b, p0/m, z3.b, z0.b
-+[^:]+: 04010003 sub z3.b, p0/m, z3.b, z0.b
-+[^:]+: 04010080 sub z0.b, p0/m, z0.b, z4.b
-+[^:]+: 04010080 sub z0.b, p0/m, z0.b, z4.b
-+[^:]+: 040103e0 sub z0.b, p0/m, z0.b, z31.b
-+[^:]+: 040103e0 sub z0.b, p0/m, z0.b, z31.b
-+[^:]+: 04410000 sub z0.h, p0/m, z0.h, z0.h
-+[^:]+: 04410000 sub z0.h, p0/m, z0.h, z0.h
-+[^:]+: 04410001 sub z1.h, p0/m, z1.h, z0.h
-+[^:]+: 04410001 sub z1.h, p0/m, z1.h, z0.h
-+[^:]+: 0441001f sub z31.h, p0/m, z31.h, z0.h
-+[^:]+: 0441001f sub z31.h, p0/m, z31.h, z0.h
-+[^:]+: 04410800 sub z0.h, p2/m, z0.h, z0.h
-+[^:]+: 04410800 sub z0.h, p2/m, z0.h, z0.h
-+[^:]+: 04411c00 sub z0.h, p7/m, z0.h, z0.h
-+[^:]+: 04411c00 sub z0.h, p7/m, z0.h, z0.h
-+[^:]+: 04410003 sub z3.h, p0/m, z3.h, z0.h
-+[^:]+: 04410003 sub z3.h, p0/m, z3.h, z0.h
-+[^:]+: 04410080 sub z0.h, p0/m, z0.h, z4.h
-+[^:]+: 04410080 sub z0.h, p0/m, z0.h, z4.h
-+[^:]+: 044103e0 sub z0.h, p0/m, z0.h, z31.h
-+[^:]+: 044103e0 sub z0.h, p0/m, z0.h, z31.h
-+[^:]+: 04810000 sub z0.s, p0/m, z0.s, z0.s
-+[^:]+: 04810000 sub z0.s, p0/m, z0.s, z0.s
-+[^:]+: 04810001 sub z1.s, p0/m, z1.s, z0.s
-+[^:]+: 04810001 sub z1.s, p0/m, z1.s, z0.s
-+[^:]+: 0481001f sub z31.s, p0/m, z31.s, z0.s
-+[^:]+: 0481001f sub z31.s, p0/m, z31.s, z0.s
-+[^:]+: 04810800 sub z0.s, p2/m, z0.s, z0.s
-+[^:]+: 04810800 sub z0.s, p2/m, z0.s, z0.s
-+[^:]+: 04811c00 sub z0.s, p7/m, z0.s, z0.s
-+[^:]+: 04811c00 sub z0.s, p7/m, z0.s, z0.s
-+[^:]+: 04810003 sub z3.s, p0/m, z3.s, z0.s
-+[^:]+: 04810003 sub z3.s, p0/m, z3.s, z0.s
-+[^:]+: 04810080 sub z0.s, p0/m, z0.s, z4.s
-+[^:]+: 04810080 sub z0.s, p0/m, z0.s, z4.s
-+[^:]+: 048103e0 sub z0.s, p0/m, z0.s, z31.s
-+[^:]+: 048103e0 sub z0.s, p0/m, z0.s, z31.s
-+[^:]+: 04c10000 sub z0.d, p0/m, z0.d, z0.d
-+[^:]+: 04c10000 sub z0.d, p0/m, z0.d, z0.d
-+[^:]+: 04c10001 sub z1.d, p0/m, z1.d, z0.d
-+[^:]+: 04c10001 sub z1.d, p0/m, z1.d, z0.d
-+[^:]+: 04c1001f sub z31.d, p0/m, z31.d, z0.d
-+[^:]+: 04c1001f sub z31.d, p0/m, z31.d, z0.d
-+[^:]+: 04c10800 sub z0.d, p2/m, z0.d, z0.d
-+[^:]+: 04c10800 sub z0.d, p2/m, z0.d, z0.d
-+[^:]+: 04c11c00 sub z0.d, p7/m, z0.d, z0.d
-+[^:]+: 04c11c00 sub z0.d, p7/m, z0.d, z0.d
-+[^:]+: 04c10003 sub z3.d, p0/m, z3.d, z0.d
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-+[^:]+: 04c103e0 sub z0.d, p0/m, z0.d, z31.d
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-+[^:]+: 2523c001 subr z1.b, z1.b, #0
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-+[^:]+: 2523c01f subr z31.b, z31.b, #0
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-+[^:]+: 2523c002 subr z2.b, z2.b, #0
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-+[^:]+: 0420fce0 uqdecb w0, vl7
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-+[^:]+: 0420fd00 uqdecb w0, vl8
-+[^:]+: 0420fd00 uqdecb w0, vl8
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-+[^:]+: 0420fd20 uqdecb w0, vl16
-+[^:]+: 0420fd20 uqdecb w0, vl16
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-+[^:]+: 0420fd40 uqdecb w0, vl32
-+[^:]+: 0420fd40 uqdecb w0, vl32
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-+[^:]+: 0420fd60 uqdecb w0, vl64
-+[^:]+: 0420fd60 uqdecb w0, vl64
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-+[^:]+: 0420fd80 uqdecb w0, vl128
-+[^:]+: 0420fd80 uqdecb w0, vl128
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-+[^:]+: 0420fda0 uqdecb w0, vl256
-+[^:]+: 0420fdc0 uqdecb w0, #14
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-+[^:]+: 0420fe00 uqdecb w0, #16
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-+[^:]+: 0420fe20 uqdecb w0, #17
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-+[^:]+: 0420fe40 uqdecb w0, #18
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-+[^:]+: 0420fe60 uqdecb w0, #19
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-+[^:]+: 0420fe80 uqdecb w0, #20
-+[^:]+: 0420fe80 uqdecb w0, #20
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-+[^:]+: 0420ff00 uqdecb w0, #24
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-+[^:]+: 0420ff20 uqdecb w0, #25
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-+[^:]+: 0420ff40 uqdecb w0, #26
-+[^:]+: 0420ff40 uqdecb w0, #26
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-+[^:]+: 0420ff60 uqdecb w0, #27
-+[^:]+: 0420ff60 uqdecb w0, #27
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-+[^:]+: 0420ff80 uqdecb w0, #28
-+[^:]+: 0420ff80 uqdecb w0, #28
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-+[^:]+: 0420ffc0 uqdecb w0, mul3
-+[^:]+: 0420ffc0 uqdecb w0, mul3
-+[^:]+: 0420ffe0 uqdecb w0
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-+[^:]+: 0427fc00 uqdecb w0, pow2, mul #8
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-+[^:]+: 0428fc00 uqdecb w0, pow2, mul #9
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-+[^:]+: 0429fc00 uqdecb w0, pow2, mul #10
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-+[^:]+: 042ffc00 uqdecb w0, pow2, mul #16
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-+[^:]+: 0430fc00 uqdecb x0, pow2
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-+[^:]+: 0430fc01 uqdecb x1, pow2
-+[^:]+: 0430fc01 uqdecb x1, pow2
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-+[^:]+: 0430fc1f uqdecb xzr, pow2
-+[^:]+: 0430fc1f uqdecb xzr, pow2
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-+[^:]+: 0430fc20 uqdecb x0, vl1
-+[^:]+: 0430fc20 uqdecb x0, vl1
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-+[^:]+: 0430fc40 uqdecb x0, vl2
-+[^:]+: 0430fc40 uqdecb x0, vl2
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-+[^:]+: 0430fc60 uqdecb x0, vl3
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-+[^:]+: 0430fc80 uqdecb x0, vl4
-+[^:]+: 0430fc80 uqdecb x0, vl4
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-+[^:]+: 0430fca0 uqdecb x0, vl5
-+[^:]+: 0430fca0 uqdecb x0, vl5
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-+[^:]+: 0430fcc0 uqdecb x0, vl6
-+[^:]+: 0430fcc0 uqdecb x0, vl6
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-+[^:]+: 0430fce0 uqdecb x0, vl7
-+[^:]+: 0430fce0 uqdecb x0, vl7
-+[^:]+: 0430fd00 uqdecb x0, vl8
-+[^:]+: 0430fd00 uqdecb x0, vl8
-+[^:]+: 0430fd00 uqdecb x0, vl8
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-+[^:]+: 0430fd20 uqdecb x0, vl16
-+[^:]+: 0430fd20 uqdecb x0, vl16
-+[^:]+: 0430fd40 uqdecb x0, vl32
-+[^:]+: 0430fd40 uqdecb x0, vl32
-+[^:]+: 0430fd40 uqdecb x0, vl32
-+[^:]+: 0430fd60 uqdecb x0, vl64
-+[^:]+: 0430fd60 uqdecb x0, vl64
-+[^:]+: 0430fd60 uqdecb x0, vl64
-+[^:]+: 0430fd80 uqdecb x0, vl128
-+[^:]+: 0430fd80 uqdecb x0, vl128
-+[^:]+: 0430fd80 uqdecb x0, vl128
-+[^:]+: 0430fda0 uqdecb x0, vl256
-+[^:]+: 0430fda0 uqdecb x0, vl256
-+[^:]+: 0430fda0 uqdecb x0, vl256
-+[^:]+: 0430fdc0 uqdecb x0, #14
-+[^:]+: 0430fdc0 uqdecb x0, #14
-+[^:]+: 0430fdc0 uqdecb x0, #14
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-+[^:]+: 0430fde0 uqdecb x0, #15
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-+[^:]+: 0430fe00 uqdecb x0, #16
-+[^:]+: 0430fe00 uqdecb x0, #16
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-+[^:]+: 0430fe20 uqdecb x0, #17
-+[^:]+: 0430fe20 uqdecb x0, #17
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-+[^:]+: 0430fe40 uqdecb x0, #18
-+[^:]+: 0430fe40 uqdecb x0, #18
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-+[^:]+: 0430fe60 uqdecb x0, #19
-+[^:]+: 0430fe60 uqdecb x0, #19
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-+[^:]+: 0430fe80 uqdecb x0, #20
-+[^:]+: 0430fe80 uqdecb x0, #20
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-+[^:]+: 0430fea0 uqdecb x0, #21
-+[^:]+: 0430fea0 uqdecb x0, #21
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-+[^:]+: 0430fec0 uqdecb x0, #22
-+[^:]+: 0430fec0 uqdecb x0, #22
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-+[^:]+: 0430fee0 uqdecb x0, #23
-+[^:]+: 0430fee0 uqdecb x0, #23
-+[^:]+: 0430ff00 uqdecb x0, #24
-+[^:]+: 0430ff00 uqdecb x0, #24
-+[^:]+: 0430ff00 uqdecb x0, #24
-+[^:]+: 0430ff20 uqdecb x0, #25
-+[^:]+: 0430ff20 uqdecb x0, #25
-+[^:]+: 0430ff20 uqdecb x0, #25
-+[^:]+: 0430ff40 uqdecb x0, #26
-+[^:]+: 0430ff40 uqdecb x0, #26
-+[^:]+: 0430ff40 uqdecb x0, #26
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-+[^:]+: 0430ff60 uqdecb x0, #27
-+[^:]+: 0430ff60 uqdecb x0, #27
-+[^:]+: 0430ff80 uqdecb x0, #28
-+[^:]+: 0430ff80 uqdecb x0, #28
-+[^:]+: 0430ff80 uqdecb x0, #28
-+[^:]+: 0430ffa0 uqdecb x0, mul4
-+[^:]+: 0430ffa0 uqdecb x0, mul4
-+[^:]+: 0430ffa0 uqdecb x0, mul4
-+[^:]+: 0430ffc0 uqdecb x0, mul3
-+[^:]+: 0430ffc0 uqdecb x0, mul3
-+[^:]+: 0430ffc0 uqdecb x0, mul3
-+[^:]+: 0430ffe0 uqdecb x0
-+[^:]+: 0430ffe0 uqdecb x0
-+[^:]+: 0430ffe0 uqdecb x0
-+[^:]+: 0430ffe0 uqdecb x0
-+[^:]+: 0437fc00 uqdecb x0, pow2, mul #8
-+[^:]+: 0437fc00 uqdecb x0, pow2, mul #8
-+[^:]+: 0438fc00 uqdecb x0, pow2, mul #9
-+[^:]+: 0438fc00 uqdecb x0, pow2, mul #9
-+[^:]+: 0439fc00 uqdecb x0, pow2, mul #10
-+[^:]+: 0439fc00 uqdecb x0, pow2, mul #10
-+[^:]+: 043ffc00 uqdecb x0, pow2, mul #16
-+[^:]+: 043ffc00 uqdecb x0, pow2, mul #16
-+[^:]+: 04e0cc00 uqdecd z0.d, pow2
-+[^:]+: 04e0cc00 uqdecd z0.d, pow2
-+[^:]+: 04e0cc00 uqdecd z0.d, pow2
-+[^:]+: 04e0cc01 uqdecd z1.d, pow2
-+[^:]+: 04e0cc01 uqdecd z1.d, pow2
-+[^:]+: 04e0cc01 uqdecd z1.d, pow2
-+[^:]+: 04e0cc1f uqdecd z31.d, pow2
-+[^:]+: 04e0cc1f uqdecd z31.d, pow2
-+[^:]+: 04e0cc1f uqdecd z31.d, pow2
-+[^:]+: 04e0cc20 uqdecd z0.d, vl1
-+[^:]+: 04e0cc20 uqdecd z0.d, vl1
-+[^:]+: 04e0cc20 uqdecd z0.d, vl1
-+[^:]+: 04e0cc40 uqdecd z0.d, vl2
-+[^:]+: 04e0cc40 uqdecd z0.d, vl2
-+[^:]+: 04e0cc40 uqdecd z0.d, vl2
-+[^:]+: 04e0cc60 uqdecd z0.d, vl3
-+[^:]+: 04e0cc60 uqdecd z0.d, vl3
-+[^:]+: 04e0cc60 uqdecd z0.d, vl3
-+[^:]+: 04e0cc80 uqdecd z0.d, vl4
-+[^:]+: 04e0cc80 uqdecd z0.d, vl4
-+[^:]+: 04e0cc80 uqdecd z0.d, vl4
-+[^:]+: 04e0cca0 uqdecd z0.d, vl5
-+[^:]+: 04e0cca0 uqdecd z0.d, vl5
-+[^:]+: 04e0cca0 uqdecd z0.d, vl5
-+[^:]+: 04e0ccc0 uqdecd z0.d, vl6
-+[^:]+: 04e0ccc0 uqdecd z0.d, vl6
-+[^:]+: 04e0ccc0 uqdecd z0.d, vl6
-+[^:]+: 04e0cce0 uqdecd z0.d, vl7
-+[^:]+: 04e0cce0 uqdecd z0.d, vl7
-+[^:]+: 04e0cce0 uqdecd z0.d, vl7
-+[^:]+: 04e0cd00 uqdecd z0.d, vl8
-+[^:]+: 04e0cd00 uqdecd z0.d, vl8
-+[^:]+: 04e0cd00 uqdecd z0.d, vl8
-+[^:]+: 04e0cd20 uqdecd z0.d, vl16
-+[^:]+: 04e0cd20 uqdecd z0.d, vl16
-+[^:]+: 04e0cd20 uqdecd z0.d, vl16
-+[^:]+: 04e0cd40 uqdecd z0.d, vl32
-+[^:]+: 04e0cd40 uqdecd z0.d, vl32
-+[^:]+: 04e0cd40 uqdecd z0.d, vl32
-+[^:]+: 04e0cd60 uqdecd z0.d, vl64
-+[^:]+: 04e0cd60 uqdecd z0.d, vl64
-+[^:]+: 04e0cd60 uqdecd z0.d, vl64
-+[^:]+: 04e0cd80 uqdecd z0.d, vl128
-+[^:]+: 04e0cd80 uqdecd z0.d, vl128
-+[^:]+: 04e0cd80 uqdecd z0.d, vl128
-+[^:]+: 04e0cda0 uqdecd z0.d, vl256
-+[^:]+: 04e0cda0 uqdecd z0.d, vl256
-+[^:]+: 04e0cda0 uqdecd z0.d, vl256
-+[^:]+: 04e0cdc0 uqdecd z0.d, #14
-+[^:]+: 04e0cdc0 uqdecd z0.d, #14
-+[^:]+: 04e0cdc0 uqdecd z0.d, #14
-+[^:]+: 04e0cde0 uqdecd z0.d, #15
-+[^:]+: 04e0cde0 uqdecd z0.d, #15
-+[^:]+: 04e0cde0 uqdecd z0.d, #15
-+[^:]+: 04e0ce00 uqdecd z0.d, #16
-+[^:]+: 04e0ce00 uqdecd z0.d, #16
-+[^:]+: 04e0ce00 uqdecd z0.d, #16
-+[^:]+: 04e0ce20 uqdecd z0.d, #17
-+[^:]+: 04e0ce20 uqdecd z0.d, #17
-+[^:]+: 04e0ce20 uqdecd z0.d, #17
-+[^:]+: 04e0ce40 uqdecd z0.d, #18
-+[^:]+: 04e0ce40 uqdecd z0.d, #18
-+[^:]+: 04e0ce40 uqdecd z0.d, #18
-+[^:]+: 04e0ce60 uqdecd z0.d, #19
-+[^:]+: 04e0ce60 uqdecd z0.d, #19
-+[^:]+: 04e0ce60 uqdecd z0.d, #19
-+[^:]+: 04e0ce80 uqdecd z0.d, #20
-+[^:]+: 04e0ce80 uqdecd z0.d, #20
-+[^:]+: 04e0ce80 uqdecd z0.d, #20
-+[^:]+: 04e0cea0 uqdecd z0.d, #21
-+[^:]+: 04e0cea0 uqdecd z0.d, #21
-+[^:]+: 04e0cea0 uqdecd z0.d, #21
-+[^:]+: 04e0cec0 uqdecd z0.d, #22
-+[^:]+: 04e0cec0 uqdecd z0.d, #22
-+[^:]+: 04e0cec0 uqdecd z0.d, #22
-+[^:]+: 04e0cee0 uqdecd z0.d, #23
-+[^:]+: 04e0cee0 uqdecd z0.d, #23
-+[^:]+: 04e0cee0 uqdecd z0.d, #23
-+[^:]+: 04e0cf00 uqdecd z0.d, #24
-+[^:]+: 04e0cf00 uqdecd z0.d, #24
-+[^:]+: 04e0cf00 uqdecd z0.d, #24
-+[^:]+: 04e0cf20 uqdecd z0.d, #25
-+[^:]+: 04e0cf20 uqdecd z0.d, #25
-+[^:]+: 04e0cf20 uqdecd z0.d, #25
-+[^:]+: 04e0cf40 uqdecd z0.d, #26
-+[^:]+: 04e0cf40 uqdecd z0.d, #26
-+[^:]+: 04e0cf40 uqdecd z0.d, #26
-+[^:]+: 04e0cf60 uqdecd z0.d, #27
-+[^:]+: 04e0cf60 uqdecd z0.d, #27
-+[^:]+: 04e0cf60 uqdecd z0.d, #27
-+[^:]+: 04e0cf80 uqdecd z0.d, #28
-+[^:]+: 04e0cf80 uqdecd z0.d, #28
-+[^:]+: 04e0cf80 uqdecd z0.d, #28
-+[^:]+: 04e0cfa0 uqdecd z0.d, mul4
-+[^:]+: 04e0cfa0 uqdecd z0.d, mul4
-+[^:]+: 04e0cfa0 uqdecd z0.d, mul4
-+[^:]+: 04e0cfc0 uqdecd z0.d, mul3
-+[^:]+: 04e0cfc0 uqdecd z0.d, mul3
-+[^:]+: 04e0cfc0 uqdecd z0.d, mul3
-+[^:]+: 04e0cfe0 uqdecd z0.d
-+[^:]+: 04e0cfe0 uqdecd z0.d
-+[^:]+: 04e0cfe0 uqdecd z0.d
-+[^:]+: 04e0cfe0 uqdecd z0.d
-+[^:]+: 04e7cc00 uqdecd z0.d, pow2, mul #8
-+[^:]+: 04e7cc00 uqdecd z0.d, pow2, mul #8
-+[^:]+: 04e8cc00 uqdecd z0.d, pow2, mul #9
-+[^:]+: 04e8cc00 uqdecd z0.d, pow2, mul #9
-+[^:]+: 04e9cc00 uqdecd z0.d, pow2, mul #10
-+[^:]+: 04e9cc00 uqdecd z0.d, pow2, mul #10
-+[^:]+: 04efcc00 uqdecd z0.d, pow2, mul #16
-+[^:]+: 04efcc00 uqdecd z0.d, pow2, mul #16
-+[^:]+: 04e0fc00 uqdecd w0, pow2
-+[^:]+: 04e0fc00 uqdecd w0, pow2
-+[^:]+: 04e0fc00 uqdecd w0, pow2
-+[^:]+: 04e0fc01 uqdecd w1, pow2
-+[^:]+: 04e0fc01 uqdecd w1, pow2
-+[^:]+: 04e0fc01 uqdecd w1, pow2
-+[^:]+: 04e0fc1f uqdecd wzr, pow2
-+[^:]+: 04e0fc1f uqdecd wzr, pow2
-+[^:]+: 04e0fc1f uqdecd wzr, pow2
-+[^:]+: 04e0fc20 uqdecd w0, vl1
-+[^:]+: 04e0fc20 uqdecd w0, vl1
-+[^:]+: 04e0fc20 uqdecd w0, vl1
-+[^:]+: 04e0fc40 uqdecd w0, vl2
-+[^:]+: 04e0fc40 uqdecd w0, vl2
-+[^:]+: 04e0fc40 uqdecd w0, vl2
-+[^:]+: 04e0fc60 uqdecd w0, vl3
-+[^:]+: 04e0fc60 uqdecd w0, vl3
-+[^:]+: 04e0fc60 uqdecd w0, vl3
-+[^:]+: 04e0fc80 uqdecd w0, vl4
-+[^:]+: 04e0fc80 uqdecd w0, vl4
-+[^:]+: 04e0fc80 uqdecd w0, vl4
-+[^:]+: 04e0fca0 uqdecd w0, vl5
-+[^:]+: 04e0fca0 uqdecd w0, vl5
-+[^:]+: 04e0fca0 uqdecd w0, vl5
-+[^:]+: 04e0fcc0 uqdecd w0, vl6
-+[^:]+: 04e0fcc0 uqdecd w0, vl6
-+[^:]+: 04e0fcc0 uqdecd w0, vl6
-+[^:]+: 04e0fce0 uqdecd w0, vl7
-+[^:]+: 04e0fce0 uqdecd w0, vl7
-+[^:]+: 04e0fce0 uqdecd w0, vl7
-+[^:]+: 04e0fd00 uqdecd w0, vl8
-+[^:]+: 04e0fd00 uqdecd w0, vl8
-+[^:]+: 04e0fd00 uqdecd w0, vl8
-+[^:]+: 04e0fd20 uqdecd w0, vl16
-+[^:]+: 04e0fd20 uqdecd w0, vl16
-+[^:]+: 04e0fd20 uqdecd w0, vl16
-+[^:]+: 04e0fd40 uqdecd w0, vl32
-+[^:]+: 04e0fd40 uqdecd w0, vl32
-+[^:]+: 04e0fd40 uqdecd w0, vl32
-+[^:]+: 04e0fd60 uqdecd w0, vl64
-+[^:]+: 04e0fd60 uqdecd w0, vl64
-+[^:]+: 04e0fd60 uqdecd w0, vl64
-+[^:]+: 04e0fd80 uqdecd w0, vl128
-+[^:]+: 04e0fd80 uqdecd w0, vl128
-+[^:]+: 04e0fd80 uqdecd w0, vl128
-+[^:]+: 04e0fda0 uqdecd w0, vl256
-+[^:]+: 04e0fda0 uqdecd w0, vl256
-+[^:]+: 04e0fda0 uqdecd w0, vl256
-+[^:]+: 04e0fdc0 uqdecd w0, #14
-+[^:]+: 04e0fdc0 uqdecd w0, #14
-+[^:]+: 04e0fdc0 uqdecd w0, #14
-+[^:]+: 04e0fde0 uqdecd w0, #15
-+[^:]+: 04e0fde0 uqdecd w0, #15
-+[^:]+: 04e0fde0 uqdecd w0, #15
-+[^:]+: 04e0fe00 uqdecd w0, #16
-+[^:]+: 04e0fe00 uqdecd w0, #16
-+[^:]+: 04e0fe00 uqdecd w0, #16
-+[^:]+: 04e0fe20 uqdecd w0, #17
-+[^:]+: 04e0fe20 uqdecd w0, #17
-+[^:]+: 04e0fe20 uqdecd w0, #17
-+[^:]+: 04e0fe40 uqdecd w0, #18
-+[^:]+: 04e0fe40 uqdecd w0, #18
-+[^:]+: 04e0fe40 uqdecd w0, #18
-+[^:]+: 04e0fe60 uqdecd w0, #19
-+[^:]+: 04e0fe60 uqdecd w0, #19
-+[^:]+: 04e0fe60 uqdecd w0, #19
-+[^:]+: 04e0fe80 uqdecd w0, #20
-+[^:]+: 04e0fe80 uqdecd w0, #20
-+[^:]+: 04e0fe80 uqdecd w0, #20
-+[^:]+: 04e0fea0 uqdecd w0, #21
-+[^:]+: 04e0fea0 uqdecd w0, #21
-+[^:]+: 04e0fea0 uqdecd w0, #21
-+[^:]+: 04e0fec0 uqdecd w0, #22
-+[^:]+: 04e0fec0 uqdecd w0, #22
-+[^:]+: 04e0fec0 uqdecd w0, #22
-+[^:]+: 04e0fee0 uqdecd w0, #23
-+[^:]+: 04e0fee0 uqdecd w0, #23
-+[^:]+: 04e0fee0 uqdecd w0, #23
-+[^:]+: 04e0ff00 uqdecd w0, #24
-+[^:]+: 04e0ff00 uqdecd w0, #24
-+[^:]+: 04e0ff00 uqdecd w0, #24
-+[^:]+: 04e0ff20 uqdecd w0, #25
-+[^:]+: 04e0ff20 uqdecd w0, #25
-+[^:]+: 04e0ff20 uqdecd w0, #25
-+[^:]+: 04e0ff40 uqdecd w0, #26
-+[^:]+: 04e0ff40 uqdecd w0, #26
-+[^:]+: 04e0ff40 uqdecd w0, #26
-+[^:]+: 04e0ff60 uqdecd w0, #27
-+[^:]+: 04e0ff60 uqdecd w0, #27
-+[^:]+: 04e0ff60 uqdecd w0, #27
-+[^:]+: 04e0ff80 uqdecd w0, #28
-+[^:]+: 04e0ff80 uqdecd w0, #28
-+[^:]+: 04e0ff80 uqdecd w0, #28
-+[^:]+: 04e0ffa0 uqdecd w0, mul4
-+[^:]+: 04e0ffa0 uqdecd w0, mul4
-+[^:]+: 04e0ffa0 uqdecd w0, mul4
-+[^:]+: 04e0ffc0 uqdecd w0, mul3
-+[^:]+: 04e0ffc0 uqdecd w0, mul3
-+[^:]+: 04e0ffc0 uqdecd w0, mul3
-+[^:]+: 04e0ffe0 uqdecd w0
-+[^:]+: 04e0ffe0 uqdecd w0
-+[^:]+: 04e0ffe0 uqdecd w0
-+[^:]+: 04e0ffe0 uqdecd w0
-+[^:]+: 04e7fc00 uqdecd w0, pow2, mul #8
-+[^:]+: 04e7fc00 uqdecd w0, pow2, mul #8
-+[^:]+: 04e8fc00 uqdecd w0, pow2, mul #9
-+[^:]+: 04e8fc00 uqdecd w0, pow2, mul #9
-+[^:]+: 04e9fc00 uqdecd w0, pow2, mul #10
-+[^:]+: 04e9fc00 uqdecd w0, pow2, mul #10
-+[^:]+: 04effc00 uqdecd w0, pow2, mul #16
-+[^:]+: 04effc00 uqdecd w0, pow2, mul #16
-+[^:]+: 04f0fc00 uqdecd x0, pow2
-+[^:]+: 04f0fc00 uqdecd x0, pow2
-+[^:]+: 04f0fc00 uqdecd x0, pow2
-+[^:]+: 04f0fc01 uqdecd x1, pow2
-+[^:]+: 04f0fc01 uqdecd x1, pow2
-+[^:]+: 04f0fc01 uqdecd x1, pow2
-+[^:]+: 04f0fc1f uqdecd xzr, pow2
-+[^:]+: 04f0fc1f uqdecd xzr, pow2
-+[^:]+: 04f0fc1f uqdecd xzr, pow2
-+[^:]+: 04f0fc20 uqdecd x0, vl1
-+[^:]+: 04f0fc20 uqdecd x0, vl1
-+[^:]+: 04f0fc20 uqdecd x0, vl1
-+[^:]+: 04f0fc40 uqdecd x0, vl2
-+[^:]+: 04f0fc40 uqdecd x0, vl2
-+[^:]+: 04f0fc40 uqdecd x0, vl2
-+[^:]+: 04f0fc60 uqdecd x0, vl3
-+[^:]+: 04f0fc60 uqdecd x0, vl3
-+[^:]+: 04f0fc60 uqdecd x0, vl3
-+[^:]+: 04f0fc80 uqdecd x0, vl4
-+[^:]+: 04f0fc80 uqdecd x0, vl4
-+[^:]+: 04f0fc80 uqdecd x0, vl4
-+[^:]+: 04f0fca0 uqdecd x0, vl5
-+[^:]+: 04f0fca0 uqdecd x0, vl5
-+[^:]+: 04f0fca0 uqdecd x0, vl5
-+[^:]+: 04f0fcc0 uqdecd x0, vl6
-+[^:]+: 04f0fcc0 uqdecd x0, vl6
-+[^:]+: 04f0fcc0 uqdecd x0, vl6
-+[^:]+: 04f0fce0 uqdecd x0, vl7
-+[^:]+: 04f0fce0 uqdecd x0, vl7
-+[^:]+: 04f0fce0 uqdecd x0, vl7
-+[^:]+: 04f0fd00 uqdecd x0, vl8
-+[^:]+: 04f0fd00 uqdecd x0, vl8
-+[^:]+: 04f0fd00 uqdecd x0, vl8
-+[^:]+: 04f0fd20 uqdecd x0, vl16
-+[^:]+: 04f0fd20 uqdecd x0, vl16
-+[^:]+: 04f0fd20 uqdecd x0, vl16
-+[^:]+: 04f0fd40 uqdecd x0, vl32
-+[^:]+: 04f0fd40 uqdecd x0, vl32
-+[^:]+: 04f0fd40 uqdecd x0, vl32
-+[^:]+: 04f0fd60 uqdecd x0, vl64
-+[^:]+: 04f0fd60 uqdecd x0, vl64
-+[^:]+: 04f0fd60 uqdecd x0, vl64
-+[^:]+: 04f0fd80 uqdecd x0, vl128
-+[^:]+: 04f0fd80 uqdecd x0, vl128
-+[^:]+: 04f0fd80 uqdecd x0, vl128
-+[^:]+: 04f0fda0 uqdecd x0, vl256
-+[^:]+: 04f0fda0 uqdecd x0, vl256
-+[^:]+: 04f0fda0 uqdecd x0, vl256
-+[^:]+: 04f0fdc0 uqdecd x0, #14
-+[^:]+: 04f0fdc0 uqdecd x0, #14
-+[^:]+: 04f0fdc0 uqdecd x0, #14
-+[^:]+: 04f0fde0 uqdecd x0, #15
-+[^:]+: 04f0fde0 uqdecd x0, #15
-+[^:]+: 04f0fde0 uqdecd x0, #15
-+[^:]+: 04f0fe00 uqdecd x0, #16
-+[^:]+: 04f0fe00 uqdecd x0, #16
-+[^:]+: 04f0fe00 uqdecd x0, #16
-+[^:]+: 04f0fe20 uqdecd x0, #17
-+[^:]+: 04f0fe20 uqdecd x0, #17
-+[^:]+: 04f0fe20 uqdecd x0, #17
-+[^:]+: 04f0fe40 uqdecd x0, #18
-+[^:]+: 04f0fe40 uqdecd x0, #18
-+[^:]+: 04f0fe40 uqdecd x0, #18
-+[^:]+: 04f0fe60 uqdecd x0, #19
-+[^:]+: 04f0fe60 uqdecd x0, #19
-+[^:]+: 04f0fe60 uqdecd x0, #19
-+[^:]+: 04f0fe80 uqdecd x0, #20
-+[^:]+: 04f0fe80 uqdecd x0, #20
-+[^:]+: 04f0fe80 uqdecd x0, #20
-+[^:]+: 04f0fea0 uqdecd x0, #21
-+[^:]+: 04f0fea0 uqdecd x0, #21
-+[^:]+: 04f0fea0 uqdecd x0, #21
-+[^:]+: 04f0fec0 uqdecd x0, #22
-+[^:]+: 04f0fec0 uqdecd x0, #22
-+[^:]+: 04f0fec0 uqdecd x0, #22
-+[^:]+: 04f0fee0 uqdecd x0, #23
-+[^:]+: 04f0fee0 uqdecd x0, #23
-+[^:]+: 04f0fee0 uqdecd x0, #23
-+[^:]+: 04f0ff00 uqdecd x0, #24
-+[^:]+: 04f0ff00 uqdecd x0, #24
-+[^:]+: 04f0ff00 uqdecd x0, #24
-+[^:]+: 04f0ff20 uqdecd x0, #25
-+[^:]+: 04f0ff20 uqdecd x0, #25
-+[^:]+: 04f0ff20 uqdecd x0, #25
-+[^:]+: 04f0ff40 uqdecd x0, #26
-+[^:]+: 04f0ff40 uqdecd x0, #26
-+[^:]+: 04f0ff40 uqdecd x0, #26
-+[^:]+: 04f0ff60 uqdecd x0, #27
-+[^:]+: 04f0ff60 uqdecd x0, #27
-+[^:]+: 04f0ff60 uqdecd x0, #27
-+[^:]+: 04f0ff80 uqdecd x0, #28
-+[^:]+: 04f0ff80 uqdecd x0, #28
-+[^:]+: 04f0ff80 uqdecd x0, #28
-+[^:]+: 04f0ffa0 uqdecd x0, mul4
-+[^:]+: 04f0ffa0 uqdecd x0, mul4
-+[^:]+: 04f0ffa0 uqdecd x0, mul4
-+[^:]+: 04f0ffc0 uqdecd x0, mul3
-+[^:]+: 04f0ffc0 uqdecd x0, mul3
-+[^:]+: 04f0ffc0 uqdecd x0, mul3
-+[^:]+: 04f0ffe0 uqdecd x0
-+[^:]+: 04f0ffe0 uqdecd x0
-+[^:]+: 04f0ffe0 uqdecd x0
-+[^:]+: 04f0ffe0 uqdecd x0
-+[^:]+: 04f7fc00 uqdecd x0, pow2, mul #8
-+[^:]+: 04f7fc00 uqdecd x0, pow2, mul #8
-+[^:]+: 04f8fc00 uqdecd x0, pow2, mul #9
-+[^:]+: 04f8fc00 uqdecd x0, pow2, mul #9
-+[^:]+: 04f9fc00 uqdecd x0, pow2, mul #10
-+[^:]+: 04f9fc00 uqdecd x0, pow2, mul #10
-+[^:]+: 04fffc00 uqdecd x0, pow2, mul #16
-+[^:]+: 04fffc00 uqdecd x0, pow2, mul #16
-+[^:]+: 0460cc00 uqdech z0.h, pow2
-+[^:]+: 0460cc00 uqdech z0.h, pow2
-+[^:]+: 0460cc00 uqdech z0.h, pow2
-+[^:]+: 0460cc01 uqdech z1.h, pow2
-+[^:]+: 0460cc01 uqdech z1.h, pow2
-+[^:]+: 0460cc01 uqdech z1.h, pow2
-+[^:]+: 0460cc1f uqdech z31.h, pow2
-+[^:]+: 0460cc1f uqdech z31.h, pow2
-+[^:]+: 0460cc1f uqdech z31.h, pow2
-+[^:]+: 0460cc20 uqdech z0.h, vl1
-+[^:]+: 0460cc20 uqdech z0.h, vl1
-+[^:]+: 0460cc20 uqdech z0.h, vl1
-+[^:]+: 0460cc40 uqdech z0.h, vl2
-+[^:]+: 0460cc40 uqdech z0.h, vl2
-+[^:]+: 0460cc40 uqdech z0.h, vl2
-+[^:]+: 0460cc60 uqdech z0.h, vl3
-+[^:]+: 0460cc60 uqdech z0.h, vl3
-+[^:]+: 0460cc60 uqdech z0.h, vl3
-+[^:]+: 0460cc80 uqdech z0.h, vl4
-+[^:]+: 0460cc80 uqdech z0.h, vl4
-+[^:]+: 0460cc80 uqdech z0.h, vl4
-+[^:]+: 0460cca0 uqdech z0.h, vl5
-+[^:]+: 0460cca0 uqdech z0.h, vl5
-+[^:]+: 0460cca0 uqdech z0.h, vl5
-+[^:]+: 0460ccc0 uqdech z0.h, vl6
-+[^:]+: 0460ccc0 uqdech z0.h, vl6
-+[^:]+: 0460ccc0 uqdech z0.h, vl6
-+[^:]+: 0460cce0 uqdech z0.h, vl7
-+[^:]+: 0460cce0 uqdech z0.h, vl7
-+[^:]+: 0460cce0 uqdech z0.h, vl7
-+[^:]+: 0460cd00 uqdech z0.h, vl8
-+[^:]+: 0460cd00 uqdech z0.h, vl8
-+[^:]+: 0460cd00 uqdech z0.h, vl8
-+[^:]+: 0460cd20 uqdech z0.h, vl16
-+[^:]+: 0460cd20 uqdech z0.h, vl16
-+[^:]+: 0460cd20 uqdech z0.h, vl16
-+[^:]+: 0460cd40 uqdech z0.h, vl32
-+[^:]+: 0460cd40 uqdech z0.h, vl32
-+[^:]+: 0460cd40 uqdech z0.h, vl32
-+[^:]+: 0460cd60 uqdech z0.h, vl64
-+[^:]+: 0460cd60 uqdech z0.h, vl64
-+[^:]+: 0460cd60 uqdech z0.h, vl64
-+[^:]+: 0460cd80 uqdech z0.h, vl128
-+[^:]+: 0460cd80 uqdech z0.h, vl128
-+[^:]+: 0460cd80 uqdech z0.h, vl128
-+[^:]+: 0460cda0 uqdech z0.h, vl256
-+[^:]+: 0460cda0 uqdech z0.h, vl256
-+[^:]+: 0460cda0 uqdech z0.h, vl256
-+[^:]+: 0460cdc0 uqdech z0.h, #14
-+[^:]+: 0460cdc0 uqdech z0.h, #14
-+[^:]+: 0460cdc0 uqdech z0.h, #14
-+[^:]+: 0460cde0 uqdech z0.h, #15
-+[^:]+: 0460cde0 uqdech z0.h, #15
-+[^:]+: 0460cde0 uqdech z0.h, #15
-+[^:]+: 0460ce00 uqdech z0.h, #16
-+[^:]+: 0460ce00 uqdech z0.h, #16
-+[^:]+: 0460ce00 uqdech z0.h, #16
-+[^:]+: 0460ce20 uqdech z0.h, #17
-+[^:]+: 0460ce20 uqdech z0.h, #17
-+[^:]+: 0460ce20 uqdech z0.h, #17
-+[^:]+: 0460ce40 uqdech z0.h, #18
-+[^:]+: 0460ce40 uqdech z0.h, #18
-+[^:]+: 0460ce40 uqdech z0.h, #18
-+[^:]+: 0460ce60 uqdech z0.h, #19
-+[^:]+: 0460ce60 uqdech z0.h, #19
-+[^:]+: 0460ce60 uqdech z0.h, #19
-+[^:]+: 0460ce80 uqdech z0.h, #20
-+[^:]+: 0460ce80 uqdech z0.h, #20
-+[^:]+: 0460ce80 uqdech z0.h, #20
-+[^:]+: 0460cea0 uqdech z0.h, #21
-+[^:]+: 0460cea0 uqdech z0.h, #21
-+[^:]+: 0460cea0 uqdech z0.h, #21
-+[^:]+: 0460cec0 uqdech z0.h, #22
-+[^:]+: 0460cec0 uqdech z0.h, #22
-+[^:]+: 0460cec0 uqdech z0.h, #22
-+[^:]+: 0460cee0 uqdech z0.h, #23
-+[^:]+: 0460cee0 uqdech z0.h, #23
-+[^:]+: 0460cee0 uqdech z0.h, #23
-+[^:]+: 0460cf00 uqdech z0.h, #24
-+[^:]+: 0460cf00 uqdech z0.h, #24
-+[^:]+: 0460cf00 uqdech z0.h, #24
-+[^:]+: 0460cf20 uqdech z0.h, #25
-+[^:]+: 0460cf20 uqdech z0.h, #25
-+[^:]+: 0460cf20 uqdech z0.h, #25
-+[^:]+: 0460cf40 uqdech z0.h, #26
-+[^:]+: 0460cf40 uqdech z0.h, #26
-+[^:]+: 0460cf40 uqdech z0.h, #26
-+[^:]+: 0460cf60 uqdech z0.h, #27
-+[^:]+: 0460cf60 uqdech z0.h, #27
-+[^:]+: 0460cf60 uqdech z0.h, #27
-+[^:]+: 0460cf80 uqdech z0.h, #28
-+[^:]+: 0460cf80 uqdech z0.h, #28
-+[^:]+: 0460cf80 uqdech z0.h, #28
-+[^:]+: 0460cfa0 uqdech z0.h, mul4
-+[^:]+: 0460cfa0 uqdech z0.h, mul4
-+[^:]+: 0460cfa0 uqdech z0.h, mul4
-+[^:]+: 0460cfc0 uqdech z0.h, mul3
-+[^:]+: 0460cfc0 uqdech z0.h, mul3
-+[^:]+: 0460cfc0 uqdech z0.h, mul3
-+[^:]+: 0460cfe0 uqdech z0.h
-+[^:]+: 0460cfe0 uqdech z0.h
-+[^:]+: 0460cfe0 uqdech z0.h
-+[^:]+: 0460cfe0 uqdech z0.h
-+[^:]+: 0467cc00 uqdech z0.h, pow2, mul #8
-+[^:]+: 0467cc00 uqdech z0.h, pow2, mul #8
-+[^:]+: 0468cc00 uqdech z0.h, pow2, mul #9
-+[^:]+: 0468cc00 uqdech z0.h, pow2, mul #9
-+[^:]+: 0469cc00 uqdech z0.h, pow2, mul #10
-+[^:]+: 0469cc00 uqdech z0.h, pow2, mul #10
-+[^:]+: 046fcc00 uqdech z0.h, pow2, mul #16
-+[^:]+: 046fcc00 uqdech z0.h, pow2, mul #16
-+[^:]+: 0460fc00 uqdech w0, pow2
-+[^:]+: 0460fc00 uqdech w0, pow2
-+[^:]+: 0460fc00 uqdech w0, pow2
-+[^:]+: 0460fc01 uqdech w1, pow2
-+[^:]+: 0460fc01 uqdech w1, pow2
-+[^:]+: 0460fc01 uqdech w1, pow2
-+[^:]+: 0460fc1f uqdech wzr, pow2
-+[^:]+: 0460fc1f uqdech wzr, pow2
-+[^:]+: 0460fc1f uqdech wzr, pow2
-+[^:]+: 0460fc20 uqdech w0, vl1
-+[^:]+: 0460fc20 uqdech w0, vl1
-+[^:]+: 0460fc20 uqdech w0, vl1
-+[^:]+: 0460fc40 uqdech w0, vl2
-+[^:]+: 0460fc40 uqdech w0, vl2
-+[^:]+: 0460fc40 uqdech w0, vl2
-+[^:]+: 0460fc60 uqdech w0, vl3
-+[^:]+: 0460fc60 uqdech w0, vl3
-+[^:]+: 0460fc60 uqdech w0, vl3
-+[^:]+: 0460fc80 uqdech w0, vl4
-+[^:]+: 0460fc80 uqdech w0, vl4
-+[^:]+: 0460fc80 uqdech w0, vl4
-+[^:]+: 0460fca0 uqdech w0, vl5
-+[^:]+: 0460fca0 uqdech w0, vl5
-+[^:]+: 0460fca0 uqdech w0, vl5
-+[^:]+: 0460fcc0 uqdech w0, vl6
-+[^:]+: 0460fcc0 uqdech w0, vl6
-+[^:]+: 0460fcc0 uqdech w0, vl6
-+[^:]+: 0460fce0 uqdech w0, vl7
-+[^:]+: 0460fce0 uqdech w0, vl7
-+[^:]+: 0460fce0 uqdech w0, vl7
-+[^:]+: 0460fd00 uqdech w0, vl8
-+[^:]+: 0460fd00 uqdech w0, vl8
-+[^:]+: 0460fd00 uqdech w0, vl8
-+[^:]+: 0460fd20 uqdech w0, vl16
-+[^:]+: 0460fd20 uqdech w0, vl16
-+[^:]+: 0460fd20 uqdech w0, vl16
-+[^:]+: 0460fd40 uqdech w0, vl32
-+[^:]+: 0460fd40 uqdech w0, vl32
-+[^:]+: 0460fd40 uqdech w0, vl32
-+[^:]+: 0460fd60 uqdech w0, vl64
-+[^:]+: 0460fd60 uqdech w0, vl64
-+[^:]+: 0460fd60 uqdech w0, vl64
-+[^:]+: 0460fd80 uqdech w0, vl128
-+[^:]+: 0460fd80 uqdech w0, vl128
-+[^:]+: 0460fd80 uqdech w0, vl128
-+[^:]+: 0460fda0 uqdech w0, vl256
-+[^:]+: 0460fda0 uqdech w0, vl256
-+[^:]+: 0460fda0 uqdech w0, vl256
-+[^:]+: 0460fdc0 uqdech w0, #14
-+[^:]+: 0460fdc0 uqdech w0, #14
-+[^:]+: 0460fdc0 uqdech w0, #14
-+[^:]+: 0460fde0 uqdech w0, #15
-+[^:]+: 0460fde0 uqdech w0, #15
-+[^:]+: 0460fde0 uqdech w0, #15
-+[^:]+: 0460fe00 uqdech w0, #16
-+[^:]+: 0460fe00 uqdech w0, #16
-+[^:]+: 0460fe00 uqdech w0, #16
-+[^:]+: 0460fe20 uqdech w0, #17
-+[^:]+: 0460fe20 uqdech w0, #17
-+[^:]+: 0460fe20 uqdech w0, #17
-+[^:]+: 0460fe40 uqdech w0, #18
-+[^:]+: 0460fe40 uqdech w0, #18
-+[^:]+: 0460fe40 uqdech w0, #18
-+[^:]+: 0460fe60 uqdech w0, #19
-+[^:]+: 0460fe60 uqdech w0, #19
-+[^:]+: 0460fe60 uqdech w0, #19
-+[^:]+: 0460fe80 uqdech w0, #20
-+[^:]+: 0460fe80 uqdech w0, #20
-+[^:]+: 0460fe80 uqdech w0, #20
-+[^:]+: 0460fea0 uqdech w0, #21
-+[^:]+: 0460fea0 uqdech w0, #21
-+[^:]+: 0460fea0 uqdech w0, #21
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-+[^:]+: 04a0cd60 uqdecw z0.s, vl64
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-+[^:]+: 04a0cd80 uqdecw z0.s, vl128
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-+[^:]+: 04a0cda0 uqdecw z0.s, vl256
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-+[^:]+: 04a7fc00 uqdecw w0, pow2, mul #8
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-+[^:]+: 04b0fdc0 uqdecw x0, #14
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-+[^:]+: 0430f400 uqincb x0, pow2
-+[^:]+: 0430f400 uqincb x0, pow2
-+[^:]+: 0430f401 uqincb x1, pow2
-+[^:]+: 0430f401 uqincb x1, pow2
-+[^:]+: 0430f401 uqincb x1, pow2
-+[^:]+: 0430f41f uqincb xzr, pow2
-+[^:]+: 0430f41f uqincb xzr, pow2
-+[^:]+: 0430f41f uqincb xzr, pow2
-+[^:]+: 0430f420 uqincb x0, vl1
-+[^:]+: 0430f420 uqincb x0, vl1
-+[^:]+: 0430f420 uqincb x0, vl1
-+[^:]+: 0430f440 uqincb x0, vl2
-+[^:]+: 0430f440 uqincb x0, vl2
-+[^:]+: 0430f440 uqincb x0, vl2
-+[^:]+: 0430f460 uqincb x0, vl3
-+[^:]+: 0430f460 uqincb x0, vl3
-+[^:]+: 0430f460 uqincb x0, vl3
-+[^:]+: 0430f480 uqincb x0, vl4
-+[^:]+: 0430f480 uqincb x0, vl4
-+[^:]+: 0430f480 uqincb x0, vl4
-+[^:]+: 0430f4a0 uqincb x0, vl5
-+[^:]+: 0430f4a0 uqincb x0, vl5
-+[^:]+: 0430f4a0 uqincb x0, vl5
-+[^:]+: 0430f4c0 uqincb x0, vl6
-+[^:]+: 0430f4c0 uqincb x0, vl6
-+[^:]+: 0430f4c0 uqincb x0, vl6
-+[^:]+: 0430f4e0 uqincb x0, vl7
-+[^:]+: 0430f4e0 uqincb x0, vl7
-+[^:]+: 0430f4e0 uqincb x0, vl7
-+[^:]+: 0430f500 uqincb x0, vl8
-+[^:]+: 0430f500 uqincb x0, vl8
-+[^:]+: 0430f500 uqincb x0, vl8
-+[^:]+: 0430f520 uqincb x0, vl16
-+[^:]+: 0430f520 uqincb x0, vl16
-+[^:]+: 0430f520 uqincb x0, vl16
-+[^:]+: 0430f540 uqincb x0, vl32
-+[^:]+: 0430f540 uqincb x0, vl32
-+[^:]+: 0430f540 uqincb x0, vl32
-+[^:]+: 0430f560 uqincb x0, vl64
-+[^:]+: 0430f560 uqincb x0, vl64
-+[^:]+: 0430f560 uqincb x0, vl64
-+[^:]+: 0430f580 uqincb x0, vl128
-+[^:]+: 0430f580 uqincb x0, vl128
-+[^:]+: 0430f580 uqincb x0, vl128
-+[^:]+: 0430f5a0 uqincb x0, vl256
-+[^:]+: 0430f5a0 uqincb x0, vl256
-+[^:]+: 0430f5a0 uqincb x0, vl256
-+[^:]+: 0430f5c0 uqincb x0, #14
-+[^:]+: 0430f5c0 uqincb x0, #14
-+[^:]+: 0430f5c0 uqincb x0, #14
-+[^:]+: 0430f5e0 uqincb x0, #15
-+[^:]+: 0430f5e0 uqincb x0, #15
-+[^:]+: 0430f5e0 uqincb x0, #15
-+[^:]+: 0430f600 uqincb x0, #16
-+[^:]+: 0430f600 uqincb x0, #16
-+[^:]+: 0430f600 uqincb x0, #16
-+[^:]+: 0430f620 uqincb x0, #17
-+[^:]+: 0430f620 uqincb x0, #17
-+[^:]+: 0430f620 uqincb x0, #17
-+[^:]+: 0430f640 uqincb x0, #18
-+[^:]+: 0430f640 uqincb x0, #18
-+[^:]+: 0430f640 uqincb x0, #18
-+[^:]+: 0430f660 uqincb x0, #19
-+[^:]+: 0430f660 uqincb x0, #19
-+[^:]+: 0430f660 uqincb x0, #19
-+[^:]+: 0430f680 uqincb x0, #20
-+[^:]+: 0430f680 uqincb x0, #20
-+[^:]+: 0430f680 uqincb x0, #20
-+[^:]+: 0430f6a0 uqincb x0, #21
-+[^:]+: 0430f6a0 uqincb x0, #21
-+[^:]+: 0430f6a0 uqincb x0, #21
-+[^:]+: 0430f6c0 uqincb x0, #22
-+[^:]+: 0430f6c0 uqincb x0, #22
-+[^:]+: 0430f6c0 uqincb x0, #22
-+[^:]+: 0430f6e0 uqincb x0, #23
-+[^:]+: 0430f6e0 uqincb x0, #23
-+[^:]+: 0430f6e0 uqincb x0, #23
-+[^:]+: 0430f700 uqincb x0, #24
-+[^:]+: 0430f700 uqincb x0, #24
-+[^:]+: 0430f700 uqincb x0, #24
-+[^:]+: 0430f720 uqincb x0, #25
-+[^:]+: 0430f720 uqincb x0, #25
-+[^:]+: 0430f720 uqincb x0, #25
-+[^:]+: 0430f740 uqincb x0, #26
-+[^:]+: 0430f740 uqincb x0, #26
-+[^:]+: 0430f740 uqincb x0, #26
-+[^:]+: 0430f760 uqincb x0, #27
-+[^:]+: 0430f760 uqincb x0, #27
-+[^:]+: 0430f760 uqincb x0, #27
-+[^:]+: 0430f780 uqincb x0, #28
-+[^:]+: 0430f780 uqincb x0, #28
-+[^:]+: 0430f780 uqincb x0, #28
-+[^:]+: 0430f7a0 uqincb x0, mul4
-+[^:]+: 0430f7a0 uqincb x0, mul4
-+[^:]+: 0430f7a0 uqincb x0, mul4
-+[^:]+: 0430f7c0 uqincb x0, mul3
-+[^:]+: 0430f7c0 uqincb x0, mul3
-+[^:]+: 0430f7c0 uqincb x0, mul3
-+[^:]+: 0430f7e0 uqincb x0
-+[^:]+: 0430f7e0 uqincb x0
-+[^:]+: 0430f7e0 uqincb x0
-+[^:]+: 0430f7e0 uqincb x0
-+[^:]+: 0437f400 uqincb x0, pow2, mul #8
-+[^:]+: 0437f400 uqincb x0, pow2, mul #8
-+[^:]+: 0438f400 uqincb x0, pow2, mul #9
-+[^:]+: 0438f400 uqincb x0, pow2, mul #9
-+[^:]+: 0439f400 uqincb x0, pow2, mul #10
-+[^:]+: 0439f400 uqincb x0, pow2, mul #10
-+[^:]+: 043ff400 uqincb x0, pow2, mul #16
-+[^:]+: 043ff400 uqincb x0, pow2, mul #16
-+[^:]+: 04e0c400 uqincd z0.d, pow2
-+[^:]+: 04e0c400 uqincd z0.d, pow2
-+[^:]+: 04e0c400 uqincd z0.d, pow2
-+[^:]+: 04e0c401 uqincd z1.d, pow2
-+[^:]+: 04e0c401 uqincd z1.d, pow2
-+[^:]+: 04e0c401 uqincd z1.d, pow2
-+[^:]+: 04e0c41f uqincd z31.d, pow2
-+[^:]+: 04e0c41f uqincd z31.d, pow2
-+[^:]+: 04e0c41f uqincd z31.d, pow2
-+[^:]+: 04e0c420 uqincd z0.d, vl1
-+[^:]+: 04e0c420 uqincd z0.d, vl1
-+[^:]+: 04e0c420 uqincd z0.d, vl1
-+[^:]+: 04e0c440 uqincd z0.d, vl2
-+[^:]+: 04e0c440 uqincd z0.d, vl2
-+[^:]+: 04e0c440 uqincd z0.d, vl2
-+[^:]+: 04e0c460 uqincd z0.d, vl3
-+[^:]+: 04e0c460 uqincd z0.d, vl3
-+[^:]+: 04e0c460 uqincd z0.d, vl3
-+[^:]+: 04e0c480 uqincd z0.d, vl4
-+[^:]+: 04e0c480 uqincd z0.d, vl4
-+[^:]+: 04e0c480 uqincd z0.d, vl4
-+[^:]+: 04e0c4a0 uqincd z0.d, vl5
-+[^:]+: 04e0c4a0 uqincd z0.d, vl5
-+[^:]+: 04e0c4a0 uqincd z0.d, vl5
-+[^:]+: 04e0c4c0 uqincd z0.d, vl6
-+[^:]+: 04e0c4c0 uqincd z0.d, vl6
-+[^:]+: 04e0c4c0 uqincd z0.d, vl6
-+[^:]+: 04e0c4e0 uqincd z0.d, vl7
-+[^:]+: 04e0c4e0 uqincd z0.d, vl7
-+[^:]+: 04e0c4e0 uqincd z0.d, vl7
-+[^:]+: 04e0c500 uqincd z0.d, vl8
-+[^:]+: 04e0c500 uqincd z0.d, vl8
-+[^:]+: 04e0c500 uqincd z0.d, vl8
-+[^:]+: 04e0c520 uqincd z0.d, vl16
-+[^:]+: 04e0c520 uqincd z0.d, vl16
-+[^:]+: 04e0c520 uqincd z0.d, vl16
-+[^:]+: 04e0c540 uqincd z0.d, vl32
-+[^:]+: 04e0c540 uqincd z0.d, vl32
-+[^:]+: 04e0c540 uqincd z0.d, vl32
-+[^:]+: 04e0c560 uqincd z0.d, vl64
-+[^:]+: 04e0c560 uqincd z0.d, vl64
-+[^:]+: 04e0c560 uqincd z0.d, vl64
-+[^:]+: 04e0c580 uqincd z0.d, vl128
-+[^:]+: 04e0c580 uqincd z0.d, vl128
-+[^:]+: 04e0c580 uqincd z0.d, vl128
-+[^:]+: 04e0c5a0 uqincd z0.d, vl256
-+[^:]+: 04e0c5a0 uqincd z0.d, vl256
-+[^:]+: 04e0c5a0 uqincd z0.d, vl256
-+[^:]+: 04e0c5c0 uqincd z0.d, #14
-+[^:]+: 04e0c5c0 uqincd z0.d, #14
-+[^:]+: 04e0c5c0 uqincd z0.d, #14
-+[^:]+: 04e0c5e0 uqincd z0.d, #15
-+[^:]+: 04e0c5e0 uqincd z0.d, #15
-+[^:]+: 04e0c5e0 uqincd z0.d, #15
-+[^:]+: 04e0c600 uqincd z0.d, #16
-+[^:]+: 04e0c600 uqincd z0.d, #16
-+[^:]+: 04e0c600 uqincd z0.d, #16
-+[^:]+: 04e0c620 uqincd z0.d, #17
-+[^:]+: 04e0c620 uqincd z0.d, #17
-+[^:]+: 04e0c620 uqincd z0.d, #17
-+[^:]+: 04e0c640 uqincd z0.d, #18
-+[^:]+: 04e0c640 uqincd z0.d, #18
-+[^:]+: 04e0c640 uqincd z0.d, #18
-+[^:]+: 04e0c660 uqincd z0.d, #19
-+[^:]+: 04e0c660 uqincd z0.d, #19
-+[^:]+: 04e0c660 uqincd z0.d, #19
-+[^:]+: 04e0c680 uqincd z0.d, #20
-+[^:]+: 04e0c680 uqincd z0.d, #20
-+[^:]+: 04e0c680 uqincd z0.d, #20
-+[^:]+: 04e0c6a0 uqincd z0.d, #21
-+[^:]+: 04e0c6a0 uqincd z0.d, #21
-+[^:]+: 04e0c6a0 uqincd z0.d, #21
-+[^:]+: 04e0c6c0 uqincd z0.d, #22
-+[^:]+: 04e0c6c0 uqincd z0.d, #22
-+[^:]+: 04e0c6c0 uqincd z0.d, #22
-+[^:]+: 04e0c6e0 uqincd z0.d, #23
-+[^:]+: 04e0c6e0 uqincd z0.d, #23
-+[^:]+: 04e0c6e0 uqincd z0.d, #23
-+[^:]+: 04e0c700 uqincd z0.d, #24
-+[^:]+: 04e0c700 uqincd z0.d, #24
-+[^:]+: 04e0c700 uqincd z0.d, #24
-+[^:]+: 04e0c720 uqincd z0.d, #25
-+[^:]+: 04e0c720 uqincd z0.d, #25
-+[^:]+: 04e0c720 uqincd z0.d, #25
-+[^:]+: 04e0c740 uqincd z0.d, #26
-+[^:]+: 04e0c740 uqincd z0.d, #26
-+[^:]+: 04e0c740 uqincd z0.d, #26
-+[^:]+: 04e0c760 uqincd z0.d, #27
-+[^:]+: 04e0c760 uqincd z0.d, #27
-+[^:]+: 04e0c760 uqincd z0.d, #27
-+[^:]+: 04e0c780 uqincd z0.d, #28
-+[^:]+: 04e0c780 uqincd z0.d, #28
-+[^:]+: 04e0c780 uqincd z0.d, #28
-+[^:]+: 04e0c7a0 uqincd z0.d, mul4
-+[^:]+: 04e0c7a0 uqincd z0.d, mul4
-+[^:]+: 04e0c7a0 uqincd z0.d, mul4
-+[^:]+: 04e0c7c0 uqincd z0.d, mul3
-+[^:]+: 04e0c7c0 uqincd z0.d, mul3
-+[^:]+: 04e0c7c0 uqincd z0.d, mul3
-+[^:]+: 04e0c7e0 uqincd z0.d
-+[^:]+: 04e0c7e0 uqincd z0.d
-+[^:]+: 04e0c7e0 uqincd z0.d
-+[^:]+: 04e0c7e0 uqincd z0.d
-+[^:]+: 04e7c400 uqincd z0.d, pow2, mul #8
-+[^:]+: 04e7c400 uqincd z0.d, pow2, mul #8
-+[^:]+: 04e8c400 uqincd z0.d, pow2, mul #9
-+[^:]+: 04e8c400 uqincd z0.d, pow2, mul #9
-+[^:]+: 04e9c400 uqincd z0.d, pow2, mul #10
-+[^:]+: 04e9c400 uqincd z0.d, pow2, mul #10
-+[^:]+: 04efc400 uqincd z0.d, pow2, mul #16
-+[^:]+: 04efc400 uqincd z0.d, pow2, mul #16
-+[^:]+: 04e0f400 uqincd w0, pow2
-+[^:]+: 04e0f400 uqincd w0, pow2
-+[^:]+: 04e0f400 uqincd w0, pow2
-+[^:]+: 04e0f401 uqincd w1, pow2
-+[^:]+: 04e0f401 uqincd w1, pow2
-+[^:]+: 04e0f401 uqincd w1, pow2
-+[^:]+: 04e0f41f uqincd wzr, pow2
-+[^:]+: 04e0f41f uqincd wzr, pow2
-+[^:]+: 04e0f41f uqincd wzr, pow2
-+[^:]+: 04e0f420 uqincd w0, vl1
-+[^:]+: 04e0f420 uqincd w0, vl1
-+[^:]+: 04e0f420 uqincd w0, vl1
-+[^:]+: 04e0f440 uqincd w0, vl2
-+[^:]+: 04e0f440 uqincd w0, vl2
-+[^:]+: 04e0f440 uqincd w0, vl2
-+[^:]+: 04e0f460 uqincd w0, vl3
-+[^:]+: 04e0f460 uqincd w0, vl3
-+[^:]+: 04e0f460 uqincd w0, vl3
-+[^:]+: 04e0f480 uqincd w0, vl4
-+[^:]+: 04e0f480 uqincd w0, vl4
-+[^:]+: 04e0f480 uqincd w0, vl4
-+[^:]+: 04e0f4a0 uqincd w0, vl5
-+[^:]+: 04e0f4a0 uqincd w0, vl5
-+[^:]+: 04e0f4a0 uqincd w0, vl5
-+[^:]+: 04e0f4c0 uqincd w0, vl6
-+[^:]+: 04e0f4c0 uqincd w0, vl6
-+[^:]+: 04e0f4c0 uqincd w0, vl6
-+[^:]+: 04e0f4e0 uqincd w0, vl7
-+[^:]+: 04e0f4e0 uqincd w0, vl7
-+[^:]+: 04e0f4e0 uqincd w0, vl7
-+[^:]+: 04e0f500 uqincd w0, vl8
-+[^:]+: 04e0f500 uqincd w0, vl8
-+[^:]+: 04e0f500 uqincd w0, vl8
-+[^:]+: 04e0f520 uqincd w0, vl16
-+[^:]+: 04e0f520 uqincd w0, vl16
-+[^:]+: 04e0f520 uqincd w0, vl16
-+[^:]+: 04e0f540 uqincd w0, vl32
-+[^:]+: 04e0f540 uqincd w0, vl32
-+[^:]+: 04e0f540 uqincd w0, vl32
-+[^:]+: 04e0f560 uqincd w0, vl64
-+[^:]+: 04e0f560 uqincd w0, vl64
-+[^:]+: 04e0f560 uqincd w0, vl64
-+[^:]+: 04e0f580 uqincd w0, vl128
-+[^:]+: 04e0f580 uqincd w0, vl128
-+[^:]+: 04e0f580 uqincd w0, vl128
-+[^:]+: 04e0f5a0 uqincd w0, vl256
-+[^:]+: 04e0f5a0 uqincd w0, vl256
-+[^:]+: 04e0f5a0 uqincd w0, vl256
-+[^:]+: 04e0f5c0 uqincd w0, #14
-+[^:]+: 04e0f5c0 uqincd w0, #14
-+[^:]+: 04e0f5c0 uqincd w0, #14
-+[^:]+: 04e0f5e0 uqincd w0, #15
-+[^:]+: 04e0f5e0 uqincd w0, #15
-+[^:]+: 04e0f5e0 uqincd w0, #15
-+[^:]+: 04e0f600 uqincd w0, #16
-+[^:]+: 04e0f600 uqincd w0, #16
-+[^:]+: 04e0f600 uqincd w0, #16
-+[^:]+: 04e0f620 uqincd w0, #17
-+[^:]+: 04e0f620 uqincd w0, #17
-+[^:]+: 04e0f620 uqincd w0, #17
-+[^:]+: 04e0f640 uqincd w0, #18
-+[^:]+: 04e0f640 uqincd w0, #18
-+[^:]+: 04e0f640 uqincd w0, #18
-+[^:]+: 04e0f660 uqincd w0, #19
-+[^:]+: 04e0f660 uqincd w0, #19
-+[^:]+: 04e0f660 uqincd w0, #19
-+[^:]+: 04e0f680 uqincd w0, #20
-+[^:]+: 04e0f680 uqincd w0, #20
-+[^:]+: 04e0f680 uqincd w0, #20
-+[^:]+: 04e0f6a0 uqincd w0, #21
-+[^:]+: 04e0f6a0 uqincd w0, #21
-+[^:]+: 04e0f6a0 uqincd w0, #21
-+[^:]+: 04e0f6c0 uqincd w0, #22
-+[^:]+: 04e0f6c0 uqincd w0, #22
-+[^:]+: 04e0f6c0 uqincd w0, #22
-+[^:]+: 04e0f6e0 uqincd w0, #23
-+[^:]+: 04e0f6e0 uqincd w0, #23
-+[^:]+: 04e0f6e0 uqincd w0, #23
-+[^:]+: 04e0f700 uqincd w0, #24
-+[^:]+: 04e0f700 uqincd w0, #24
-+[^:]+: 04e0f700 uqincd w0, #24
-+[^:]+: 04e0f720 uqincd w0, #25
-+[^:]+: 04e0f720 uqincd w0, #25
-+[^:]+: 04e0f720 uqincd w0, #25
-+[^:]+: 04e0f740 uqincd w0, #26
-+[^:]+: 04e0f740 uqincd w0, #26
-+[^:]+: 04e0f740 uqincd w0, #26
-+[^:]+: 04e0f760 uqincd w0, #27
-+[^:]+: 04e0f760 uqincd w0, #27
-+[^:]+: 04e0f760 uqincd w0, #27
-+[^:]+: 04e0f780 uqincd w0, #28
-+[^:]+: 04e0f780 uqincd w0, #28
-+[^:]+: 04e0f780 uqincd w0, #28
-+[^:]+: 04e0f7a0 uqincd w0, mul4
-+[^:]+: 04e0f7a0 uqincd w0, mul4
-+[^:]+: 04e0f7a0 uqincd w0, mul4
-+[^:]+: 04e0f7c0 uqincd w0, mul3
-+[^:]+: 04e0f7c0 uqincd w0, mul3
-+[^:]+: 04e0f7c0 uqincd w0, mul3
-+[^:]+: 04e0f7e0 uqincd w0
-+[^:]+: 04e0f7e0 uqincd w0
-+[^:]+: 04e0f7e0 uqincd w0
-+[^:]+: 04e0f7e0 uqincd w0
-+[^:]+: 04e7f400 uqincd w0, pow2, mul #8
-+[^:]+: 04e7f400 uqincd w0, pow2, mul #8
-+[^:]+: 04e8f400 uqincd w0, pow2, mul #9
-+[^:]+: 04e8f400 uqincd w0, pow2, mul #9
-+[^:]+: 04e9f400 uqincd w0, pow2, mul #10
-+[^:]+: 04e9f400 uqincd w0, pow2, mul #10
-+[^:]+: 04eff400 uqincd w0, pow2, mul #16
-+[^:]+: 04eff400 uqincd w0, pow2, mul #16
-+[^:]+: 04f0f400 uqincd x0, pow2
-+[^:]+: 04f0f400 uqincd x0, pow2
-+[^:]+: 04f0f400 uqincd x0, pow2
-+[^:]+: 04f0f401 uqincd x1, pow2
-+[^:]+: 04f0f401 uqincd x1, pow2
-+[^:]+: 04f0f401 uqincd x1, pow2
-+[^:]+: 04f0f41f uqincd xzr, pow2
-+[^:]+: 04f0f41f uqincd xzr, pow2
-+[^:]+: 04f0f41f uqincd xzr, pow2
-+[^:]+: 04f0f420 uqincd x0, vl1
-+[^:]+: 04f0f420 uqincd x0, vl1
-+[^:]+: 04f0f420 uqincd x0, vl1
-+[^:]+: 04f0f440 uqincd x0, vl2
-+[^:]+: 04f0f440 uqincd x0, vl2
-+[^:]+: 04f0f440 uqincd x0, vl2
-+[^:]+: 04f0f460 uqincd x0, vl3
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-+[^:]+: 04b7f400 uqincw x0, pow2, mul #8
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-+[^:]+: 04201fe0 uqsub z0.b, z31.b, z0.b
-+[^:]+: 04201fe0 uqsub z0.b, z31.b, z0.b
-+[^:]+: 04231c00 uqsub z0.b, z0.b, z3.b
-+[^:]+: 04231c00 uqsub z0.b, z0.b, z3.b
-+[^:]+: 043f1c00 uqsub z0.b, z0.b, z31.b
-+[^:]+: 043f1c00 uqsub z0.b, z0.b, z31.b
-+[^:]+: 04601c00 uqsub z0.h, z0.h, z0.h
-+[^:]+: 04601c00 uqsub z0.h, z0.h, z0.h
-+[^:]+: 04601c01 uqsub z1.h, z0.h, z0.h
-+[^:]+: 04601c01 uqsub z1.h, z0.h, z0.h
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-+[^:]+: 04601c1f uqsub z31.h, z0.h, z0.h
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-+[^:]+: 04601fe0 uqsub z0.h, z31.h, z0.h
-+[^:]+: 04601fe0 uqsub z0.h, z31.h, z0.h
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-+[^:]+: 04e31c00 uqsub z0.d, z0.d, z3.d
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-+[^:]+: 04ff1c00 uqsub z0.d, z0.d, z31.d
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-+[^:]+: 2567f000 uqsub z0.h, z0.h, #32768
-+[^:]+: 2567f000 uqsub z0.h, z0.h, #32768
-+[^:]+: 2567f000 uqsub z0.h, z0.h, #32768
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-+[^:]+: 24808001 cmpge p1.s, p0/z, z0.s, z0.s
-+[^:]+: 2480800f cmpge p15.s, p0/z, z0.s, z0.s
-+[^:]+: 2480800f cmpge p15.s, p0/z, z0.s, z0.s
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-+[^:]+: 24808800 cmpge p0.s, p2/z, z0.s, z0.s
-+[^:]+: 24809c00 cmpge p0.s, p7/z, z0.s, z0.s
-+[^:]+: 24809c00 cmpge p0.s, p7/z, z0.s, z0.s
-+[^:]+: 24838000 cmpge p0.s, p0/z, z0.s, z3.s
-+[^:]+: 24838000 cmpge p0.s, p0/z, z0.s, z3.s
-+[^:]+: 249f8000 cmpge p0.s, p0/z, z0.s, z31.s
-+[^:]+: 249f8000 cmpge p0.s, p0/z, z0.s, z31.s
-+[^:]+: 24808080 cmpge p0.s, p0/z, z4.s, z0.s
-+[^:]+: 24808080 cmpge p0.s, p0/z, z4.s, z0.s
-+[^:]+: 248083e0 cmpge p0.s, p0/z, z31.s, z0.s
-+[^:]+: 248083e0 cmpge p0.s, p0/z, z31.s, z0.s
-+[^:]+: 24c08000 cmpge p0.d, p0/z, z0.d, z0.d
-+[^:]+: 24c08000 cmpge p0.d, p0/z, z0.d, z0.d
-+[^:]+: 24c08001 cmpge p1.d, p0/z, z0.d, z0.d
-+[^:]+: 24c08001 cmpge p1.d, p0/z, z0.d, z0.d
-+[^:]+: 24c0800f cmpge p15.d, p0/z, z0.d, z0.d
-+[^:]+: 24c0800f cmpge p15.d, p0/z, z0.d, z0.d
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-+[^:]+: 24c08800 cmpge p0.d, p2/z, z0.d, z0.d
-+[^:]+: 24c09c00 cmpge p0.d, p7/z, z0.d, z0.d
-+[^:]+: 24c09c00 cmpge p0.d, p7/z, z0.d, z0.d
-+[^:]+: 24c38000 cmpge p0.d, p0/z, z0.d, z3.d
-+[^:]+: 24c38000 cmpge p0.d, p0/z, z0.d, z3.d
-+[^:]+: 24df8000 cmpge p0.d, p0/z, z0.d, z31.d
-+[^:]+: 24df8000 cmpge p0.d, p0/z, z0.d, z31.d
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-+[^:]+: 24c08080 cmpge p0.d, p0/z, z4.d, z0.d
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-+[^:]+: 24c083e0 cmpge p0.d, p0/z, z31.d, z0.d
-+[^:]+: 24000010 cmphi p0.b, p0/z, z0.b, z0.b
-+[^:]+: 24000010 cmphi p0.b, p0/z, z0.b, z0.b
-+[^:]+: 24000011 cmphi p1.b, p0/z, z0.b, z0.b
-+[^:]+: 24000011 cmphi p1.b, p0/z, z0.b, z0.b
-+[^:]+: 2400001f cmphi p15.b, p0/z, z0.b, z0.b
-+[^:]+: 2400001f cmphi p15.b, p0/z, z0.b, z0.b
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-+[^:]+: 24000810 cmphi p0.b, p2/z, z0.b, z0.b
-+[^:]+: 24001c10 cmphi p0.b, p7/z, z0.b, z0.b
-+[^:]+: 24001c10 cmphi p0.b, p7/z, z0.b, z0.b
-+[^:]+: 24030010 cmphi p0.b, p0/z, z0.b, z3.b
-+[^:]+: 24030010 cmphi p0.b, p0/z, z0.b, z3.b
-+[^:]+: 241f0010 cmphi p0.b, p0/z, z0.b, z31.b
-+[^:]+: 241f0010 cmphi p0.b, p0/z, z0.b, z31.b
-+[^:]+: 24000090 cmphi p0.b, p0/z, z4.b, z0.b
-+[^:]+: 24000090 cmphi p0.b, p0/z, z4.b, z0.b
-+[^:]+: 240003f0 cmphi p0.b, p0/z, z31.b, z0.b
-+[^:]+: 240003f0 cmphi p0.b, p0/z, z31.b, z0.b
-+[^:]+: 24400010 cmphi p0.h, p0/z, z0.h, z0.h
-+[^:]+: 24400010 cmphi p0.h, p0/z, z0.h, z0.h
-+[^:]+: 24400011 cmphi p1.h, p0/z, z0.h, z0.h
-+[^:]+: 24400011 cmphi p1.h, p0/z, z0.h, z0.h
-+[^:]+: 2440001f cmphi p15.h, p0/z, z0.h, z0.h
-+[^:]+: 2440001f cmphi p15.h, p0/z, z0.h, z0.h
-+[^:]+: 24400810 cmphi p0.h, p2/z, z0.h, z0.h
-+[^:]+: 24400810 cmphi p0.h, p2/z, z0.h, z0.h
-+[^:]+: 24401c10 cmphi p0.h, p7/z, z0.h, z0.h
-+[^:]+: 24401c10 cmphi p0.h, p7/z, z0.h, z0.h
-+[^:]+: 24430010 cmphi p0.h, p0/z, z0.h, z3.h
-+[^:]+: 24430010 cmphi p0.h, p0/z, z0.h, z3.h
-+[^:]+: 245f0010 cmphi p0.h, p0/z, z0.h, z31.h
-+[^:]+: 245f0010 cmphi p0.h, p0/z, z0.h, z31.h
-+[^:]+: 24400090 cmphi p0.h, p0/z, z4.h, z0.h
-+[^:]+: 24400090 cmphi p0.h, p0/z, z4.h, z0.h
-+[^:]+: 244003f0 cmphi p0.h, p0/z, z31.h, z0.h
-+[^:]+: 244003f0 cmphi p0.h, p0/z, z31.h, z0.h
-+[^:]+: 24800010 cmphi p0.s, p0/z, z0.s, z0.s
-+[^:]+: 24800010 cmphi p0.s, p0/z, z0.s, z0.s
-+[^:]+: 24800011 cmphi p1.s, p0/z, z0.s, z0.s
-+[^:]+: 24800011 cmphi p1.s, p0/z, z0.s, z0.s
-+[^:]+: 2480001f cmphi p15.s, p0/z, z0.s, z0.s
-+[^:]+: 2480001f cmphi p15.s, p0/z, z0.s, z0.s
-+[^:]+: 24800810 cmphi p0.s, p2/z, z0.s, z0.s
-+[^:]+: 24800810 cmphi p0.s, p2/z, z0.s, z0.s
-+[^:]+: 24801c10 cmphi p0.s, p7/z, z0.s, z0.s
-+[^:]+: 24801c10 cmphi p0.s, p7/z, z0.s, z0.s
-+[^:]+: 24830010 cmphi p0.s, p0/z, z0.s, z3.s
-+[^:]+: 24830010 cmphi p0.s, p0/z, z0.s, z3.s
-+[^:]+: 249f0010 cmphi p0.s, p0/z, z0.s, z31.s
-+[^:]+: 249f0010 cmphi p0.s, p0/z, z0.s, z31.s
-+[^:]+: 24800090 cmphi p0.s, p0/z, z4.s, z0.s
-+[^:]+: 24800090 cmphi p0.s, p0/z, z4.s, z0.s
-+[^:]+: 248003f0 cmphi p0.s, p0/z, z31.s, z0.s
-+[^:]+: 248003f0 cmphi p0.s, p0/z, z31.s, z0.s
-+[^:]+: 24c00010 cmphi p0.d, p0/z, z0.d, z0.d
-+[^:]+: 24c00010 cmphi p0.d, p0/z, z0.d, z0.d
-+[^:]+: 24c00011 cmphi p1.d, p0/z, z0.d, z0.d
-+[^:]+: 24c00011 cmphi p1.d, p0/z, z0.d, z0.d
-+[^:]+: 24c0001f cmphi p15.d, p0/z, z0.d, z0.d
-+[^:]+: 24c0001f cmphi p15.d, p0/z, z0.d, z0.d
-+[^:]+: 24c00810 cmphi p0.d, p2/z, z0.d, z0.d
-+[^:]+: 24c00810 cmphi p0.d, p2/z, z0.d, z0.d
-+[^:]+: 24c01c10 cmphi p0.d, p7/z, z0.d, z0.d
-+[^:]+: 24c01c10 cmphi p0.d, p7/z, z0.d, z0.d
-+[^:]+: 24c30010 cmphi p0.d, p0/z, z0.d, z3.d
-+[^:]+: 24c30010 cmphi p0.d, p0/z, z0.d, z3.d
-+[^:]+: 24df0010 cmphi p0.d, p0/z, z0.d, z31.d
-+[^:]+: 24df0010 cmphi p0.d, p0/z, z0.d, z31.d
-+[^:]+: 24c00090 cmphi p0.d, p0/z, z4.d, z0.d
-+[^:]+: 24c00090 cmphi p0.d, p0/z, z4.d, z0.d
-+[^:]+: 24c003f0 cmphi p0.d, p0/z, z31.d, z0.d
-+[^:]+: 24c003f0 cmphi p0.d, p0/z, z31.d, z0.d
-+[^:]+: 24000000 cmphs p0.b, p0/z, z0.b, z0.b
-+[^:]+: 24000000 cmphs p0.b, p0/z, z0.b, z0.b
-+[^:]+: 24000001 cmphs p1.b, p0/z, z0.b, z0.b
-+[^:]+: 24000001 cmphs p1.b, p0/z, z0.b, z0.b
-+[^:]+: 2400000f cmphs p15.b, p0/z, z0.b, z0.b
-+[^:]+: 2400000f cmphs p15.b, p0/z, z0.b, z0.b
-+[^:]+: 24000800 cmphs p0.b, p2/z, z0.b, z0.b
-+[^:]+: 24000800 cmphs p0.b, p2/z, z0.b, z0.b
-+[^:]+: 24001c00 cmphs p0.b, p7/z, z0.b, z0.b
-+[^:]+: 24001c00 cmphs p0.b, p7/z, z0.b, z0.b
-+[^:]+: 24030000 cmphs p0.b, p0/z, z0.b, z3.b
-+[^:]+: 24030000 cmphs p0.b, p0/z, z0.b, z3.b
-+[^:]+: 241f0000 cmphs p0.b, p0/z, z0.b, z31.b
-+[^:]+: 241f0000 cmphs p0.b, p0/z, z0.b, z31.b
-+[^:]+: 24000080 cmphs p0.b, p0/z, z4.b, z0.b
-+[^:]+: 24000080 cmphs p0.b, p0/z, z4.b, z0.b
-+[^:]+: 240003e0 cmphs p0.b, p0/z, z31.b, z0.b
-+[^:]+: 240003e0 cmphs p0.b, p0/z, z31.b, z0.b
-+[^:]+: 24400000 cmphs p0.h, p0/z, z0.h, z0.h
-+[^:]+: 24400000 cmphs p0.h, p0/z, z0.h, z0.h
-+[^:]+: 24400001 cmphs p1.h, p0/z, z0.h, z0.h
-+[^:]+: 24400001 cmphs p1.h, p0/z, z0.h, z0.h
-+[^:]+: 2440000f cmphs p15.h, p0/z, z0.h, z0.h
-+[^:]+: 2440000f cmphs p15.h, p0/z, z0.h, z0.h
-+[^:]+: 24400800 cmphs p0.h, p2/z, z0.h, z0.h
-+[^:]+: 24400800 cmphs p0.h, p2/z, z0.h, z0.h
-+[^:]+: 24401c00 cmphs p0.h, p7/z, z0.h, z0.h
-+[^:]+: 24401c00 cmphs p0.h, p7/z, z0.h, z0.h
-+[^:]+: 24430000 cmphs p0.h, p0/z, z0.h, z3.h
-+[^:]+: 24430000 cmphs p0.h, p0/z, z0.h, z3.h
-+[^:]+: 245f0000 cmphs p0.h, p0/z, z0.h, z31.h
-+[^:]+: 245f0000 cmphs p0.h, p0/z, z0.h, z31.h
-+[^:]+: 24400080 cmphs p0.h, p0/z, z4.h, z0.h
-+[^:]+: 24400080 cmphs p0.h, p0/z, z4.h, z0.h
-+[^:]+: 244003e0 cmphs p0.h, p0/z, z31.h, z0.h
-+[^:]+: 244003e0 cmphs p0.h, p0/z, z31.h, z0.h
-+[^:]+: 24800000 cmphs p0.s, p0/z, z0.s, z0.s
-+[^:]+: 24800000 cmphs p0.s, p0/z, z0.s, z0.s
-+[^:]+: 24800001 cmphs p1.s, p0/z, z0.s, z0.s
-+[^:]+: 24800001 cmphs p1.s, p0/z, z0.s, z0.s
-+[^:]+: 2480000f cmphs p15.s, p0/z, z0.s, z0.s
-+[^:]+: 2480000f cmphs p15.s, p0/z, z0.s, z0.s
-+[^:]+: 24800800 cmphs p0.s, p2/z, z0.s, z0.s
-+[^:]+: 24800800 cmphs p0.s, p2/z, z0.s, z0.s
-+[^:]+: 24801c00 cmphs p0.s, p7/z, z0.s, z0.s
-+[^:]+: 24801c00 cmphs p0.s, p7/z, z0.s, z0.s
-+[^:]+: 24830000 cmphs p0.s, p0/z, z0.s, z3.s
-+[^:]+: 24830000 cmphs p0.s, p0/z, z0.s, z3.s
-+[^:]+: 249f0000 cmphs p0.s, p0/z, z0.s, z31.s
-+[^:]+: 249f0000 cmphs p0.s, p0/z, z0.s, z31.s
-+[^:]+: 24800080 cmphs p0.s, p0/z, z4.s, z0.s
-+[^:]+: 24800080 cmphs p0.s, p0/z, z4.s, z0.s
-+[^:]+: 248003e0 cmphs p0.s, p0/z, z31.s, z0.s
-+[^:]+: 248003e0 cmphs p0.s, p0/z, z31.s, z0.s
-+[^:]+: 24c00000 cmphs p0.d, p0/z, z0.d, z0.d
-+[^:]+: 24c00000 cmphs p0.d, p0/z, z0.d, z0.d
-+[^:]+: 24c00001 cmphs p1.d, p0/z, z0.d, z0.d
-+[^:]+: 24c00001 cmphs p1.d, p0/z, z0.d, z0.d
-+[^:]+: 24c0000f cmphs p15.d, p0/z, z0.d, z0.d
-+[^:]+: 24c0000f cmphs p15.d, p0/z, z0.d, z0.d
-+[^:]+: 24c00800 cmphs p0.d, p2/z, z0.d, z0.d
-+[^:]+: 24c00800 cmphs p0.d, p2/z, z0.d, z0.d
-+[^:]+: 24c01c00 cmphs p0.d, p7/z, z0.d, z0.d
-+[^:]+: 24c01c00 cmphs p0.d, p7/z, z0.d, z0.d
-+[^:]+: 24c30000 cmphs p0.d, p0/z, z0.d, z3.d
-+[^:]+: 24c30000 cmphs p0.d, p0/z, z0.d, z3.d
-+[^:]+: 24df0000 cmphs p0.d, p0/z, z0.d, z31.d
-+[^:]+: 24df0000 cmphs p0.d, p0/z, z0.d, z31.d
-+[^:]+: 24c00080 cmphs p0.d, p0/z, z4.d, z0.d
-+[^:]+: 24c00080 cmphs p0.d, p0/z, z4.d, z0.d
-+[^:]+: 24c003e0 cmphs p0.d, p0/z, z31.d, z0.d
-+[^:]+: 24c003e0 cmphs p0.d, p0/z, z31.d, z0.d
-+[^:]+: 24008010 cmpgt p0.b, p0/z, z0.b, z0.b
-+[^:]+: 24008010 cmpgt p0.b, p0/z, z0.b, z0.b
-+[^:]+: 24008011 cmpgt p1.b, p0/z, z0.b, z0.b
-+[^:]+: 24008011 cmpgt p1.b, p0/z, z0.b, z0.b
-+[^:]+: 2400801f cmpgt p15.b, p0/z, z0.b, z0.b
-+[^:]+: 2400801f cmpgt p15.b, p0/z, z0.b, z0.b
-+[^:]+: 24008810 cmpgt p0.b, p2/z, z0.b, z0.b
-+[^:]+: 24008810 cmpgt p0.b, p2/z, z0.b, z0.b
-+[^:]+: 24009c10 cmpgt p0.b, p7/z, z0.b, z0.b
-+[^:]+: 24009c10 cmpgt p0.b, p7/z, z0.b, z0.b
-+[^:]+: 24038010 cmpgt p0.b, p0/z, z0.b, z3.b
-+[^:]+: 24038010 cmpgt p0.b, p0/z, z0.b, z3.b
-+[^:]+: 241f8010 cmpgt p0.b, p0/z, z0.b, z31.b
-+[^:]+: 241f8010 cmpgt p0.b, p0/z, z0.b, z31.b
-+[^:]+: 24008090 cmpgt p0.b, p0/z, z4.b, z0.b
-+[^:]+: 24008090 cmpgt p0.b, p0/z, z4.b, z0.b
-+[^:]+: 240083f0 cmpgt p0.b, p0/z, z31.b, z0.b
-+[^:]+: 240083f0 cmpgt p0.b, p0/z, z31.b, z0.b
-+[^:]+: 24408010 cmpgt p0.h, p0/z, z0.h, z0.h
-+[^:]+: 24408010 cmpgt p0.h, p0/z, z0.h, z0.h
-+[^:]+: 24408011 cmpgt p1.h, p0/z, z0.h, z0.h
-+[^:]+: 24408011 cmpgt p1.h, p0/z, z0.h, z0.h
-+[^:]+: 2440801f cmpgt p15.h, p0/z, z0.h, z0.h
-+[^:]+: 2440801f cmpgt p15.h, p0/z, z0.h, z0.h
-+[^:]+: 24408810 cmpgt p0.h, p2/z, z0.h, z0.h
-+[^:]+: 24408810 cmpgt p0.h, p2/z, z0.h, z0.h
-+[^:]+: 24409c10 cmpgt p0.h, p7/z, z0.h, z0.h
-+[^:]+: 24409c10 cmpgt p0.h, p7/z, z0.h, z0.h
-+[^:]+: 24438010 cmpgt p0.h, p0/z, z0.h, z3.h
-+[^:]+: 24438010 cmpgt p0.h, p0/z, z0.h, z3.h
-+[^:]+: 245f8010 cmpgt p0.h, p0/z, z0.h, z31.h
-+[^:]+: 245f8010 cmpgt p0.h, p0/z, z0.h, z31.h
-+[^:]+: 24408090 cmpgt p0.h, p0/z, z4.h, z0.h
-+[^:]+: 24408090 cmpgt p0.h, p0/z, z4.h, z0.h
-+[^:]+: 244083f0 cmpgt p0.h, p0/z, z31.h, z0.h
-+[^:]+: 244083f0 cmpgt p0.h, p0/z, z31.h, z0.h
-+[^:]+: 24808010 cmpgt p0.s, p0/z, z0.s, z0.s
-+[^:]+: 24808010 cmpgt p0.s, p0/z, z0.s, z0.s
-+[^:]+: 24808011 cmpgt p1.s, p0/z, z0.s, z0.s
-+[^:]+: 24808011 cmpgt p1.s, p0/z, z0.s, z0.s
-+[^:]+: 2480801f cmpgt p15.s, p0/z, z0.s, z0.s
-+[^:]+: 2480801f cmpgt p15.s, p0/z, z0.s, z0.s
-+[^:]+: 24808810 cmpgt p0.s, p2/z, z0.s, z0.s
-+[^:]+: 24808810 cmpgt p0.s, p2/z, z0.s, z0.s
-+[^:]+: 24809c10 cmpgt p0.s, p7/z, z0.s, z0.s
-+[^:]+: 24809c10 cmpgt p0.s, p7/z, z0.s, z0.s
-+[^:]+: 24838010 cmpgt p0.s, p0/z, z0.s, z3.s
-+[^:]+: 24838010 cmpgt p0.s, p0/z, z0.s, z3.s
-+[^:]+: 249f8010 cmpgt p0.s, p0/z, z0.s, z31.s
-+[^:]+: 249f8010 cmpgt p0.s, p0/z, z0.s, z31.s
-+[^:]+: 24808090 cmpgt p0.s, p0/z, z4.s, z0.s
-+[^:]+: 24808090 cmpgt p0.s, p0/z, z4.s, z0.s
-+[^:]+: 248083f0 cmpgt p0.s, p0/z, z31.s, z0.s
-+[^:]+: 248083f0 cmpgt p0.s, p0/z, z31.s, z0.s
-+[^:]+: 24c08010 cmpgt p0.d, p0/z, z0.d, z0.d
-+[^:]+: 24c08010 cmpgt p0.d, p0/z, z0.d, z0.d
-+[^:]+: 24c08011 cmpgt p1.d, p0/z, z0.d, z0.d
-+[^:]+: 24c08011 cmpgt p1.d, p0/z, z0.d, z0.d
-+[^:]+: 24c0801f cmpgt p15.d, p0/z, z0.d, z0.d
-+[^:]+: 24c0801f cmpgt p15.d, p0/z, z0.d, z0.d
-+[^:]+: 24c08810 cmpgt p0.d, p2/z, z0.d, z0.d
-+[^:]+: 24c08810 cmpgt p0.d, p2/z, z0.d, z0.d
-+[^:]+: 24c09c10 cmpgt p0.d, p7/z, z0.d, z0.d
-+[^:]+: 24c09c10 cmpgt p0.d, p7/z, z0.d, z0.d
-+[^:]+: 24c38010 cmpgt p0.d, p0/z, z0.d, z3.d
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-+[^:]+: 0540+ec0 eor z0.b, z0.b, #0xbf
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-+[^:]+: 0540+ec0 eor z0.b, z0.b, #0xbf
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-+[^:]+: 65805c10 fcmgt p0.s, p7/z, z0.s, z0.s
-+[^:]+: 65805c10 fcmgt p0.s, p7/z, z0.s, z0.s
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-+[^:]+: 65834010 fcmgt p0.s, p0/z, z0.s, z3.s
-+[^:]+: 659f4010 fcmgt p0.s, p0/z, z0.s, z31.s
-+[^:]+: 659f4010 fcmgt p0.s, p0/z, z0.s, z31.s
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-+[^:]+: 65804090 fcmgt p0.s, p0/z, z4.s, z0.s
-+[^:]+: 658043f0 fcmgt p0.s, p0/z, z31.s, z0.s
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-+[^:]+: 65c04010 fcmgt p0.d, p0/z, z0.d, z0.d
-+[^:]+: 65c04010 fcmgt p0.d, p0/z, z0.d, z0.d
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-+[^:]+: 05001e80 orr z0.b, z0.b, #0xe3
-+[^:]+: 05001e80 orr z0.b, z0.b, #0xe3
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-+[^:]+: 4e44147b fadd v27.8h, v3.8h, v4.8h
-+[^:]+: 4e46147b fadd v27.8h, v3.8h, v6.8h
-+[^:]+: 4e4f147b fadd v27.8h, v3.8h, v15.8h
-+[^:]+: 4e5e147b fadd v27.8h, v3.8h, v30.8h
-+[^:]+: 4e4314bb fadd v27.8h, v5.8h, v3.8h
-+[^:]+: 4e4414bb fadd v27.8h, v5.8h, v4.8h
-+[^:]+: 4e4614bb fadd v27.8h, v5.8h, v6.8h
-+[^:]+: 4e4f14bb fadd v27.8h, v5.8h, v15.8h
-+[^:]+: 4e5e14bb fadd v27.8h, v5.8h, v30.8h
-+[^:]+: 4e4315db fadd v27.8h, v14.8h, v3.8h
-+[^:]+: 4e4415db fadd v27.8h, v14.8h, v4.8h
-+[^:]+: 4e4615db fadd v27.8h, v14.8h, v6.8h
-+[^:]+: 4e4f15db fadd v27.8h, v14.8h, v15.8h
-+[^:]+: 4e5e15db fadd v27.8h, v14.8h, v30.8h
-+[^:]+: 4e4317fb fadd v27.8h, v31.8h, v3.8h
-+[^:]+: 4e4417fb fadd v27.8h, v31.8h, v4.8h
-+[^:]+: 4e4617fb fadd v27.8h, v31.8h, v6.8h
-+[^:]+: 4e4f17fb fadd v27.8h, v31.8h, v15.8h
-+[^:]+: 4e5e17fb fadd v27.8h, v31.8h, v30.8h
-+[^:]+: a41f6400 ldff1b {z0.b}, p1/z, \[x0, xzr\]
-+[^:]+: a43f6420 ldff1b {z0.h}, p1/z, \[x1, xzr\]
-+[^:]+: a45f6440 ldff1b {z0.s}, p1/z, \[x2, xzr\]
-+[^:]+: a47f6460 ldff1b {z0.d}, p1/z, \[x3, xzr\]
-+[^:]+: a5ff6000 ldff1d {z0.d}, p0/z, \[x0, xzr, lsl #3\]
-+[^:]+: a4bf6520 ldff1h {z0.h}, p1/z, \[x9, xzr, lsl #1\]
-+[^:]+: a4df6540 ldff1h {z0.s}, p1/z, \[x10, xzr, lsl #1\]
-+[^:]+: a4ff6560 ldff1h {z0.d}, p1/z, \[x11, xzr, lsl #1\]
-+[^:]+: a5bf65c0 ldff1sb {z0.s}, p1/z, \[x14, xzr\]
-+[^:]+: a59f65e0 ldff1sb {z0.d}, p1/z, \[x15, xzr\]
-+[^:]+: a53f6640 ldff1sh {z0.s}, p1/z, \[x18, xzr, lsl #1\]
-+[^:]+: a51f6660 ldff1sh {z0.d}, p1/z, \[x19, xzr, lsl #1\]
-+[^:]+: a49f66e0 ldff1sw {z0.d}, p1/z, \[x23, xzr, lsl #2\]
-+[^:]+: a57f6760 ldff1w {z0.d}, p1/z, \[x27, xzr, lsl #2\]
-diff -rup binutils-2.30/gas/testsuite/gas/aarch64/sve.s binutils-2.30.new/gas/testsuite/gas/aarch64/sve.s
---- binutils-2.30/gas/testsuite/gas/aarch64/sve.s 2018-01-13 13:31:15.000000000 +0000
-+++ binutils-2.30.new/gas/testsuite/gas/aarch64/sve.s 2021-03-23 16:19:56.753751928 +0000
-@@ -23137,128 +23137,6 @@
- MLS Z0.D, P0/M, Z0.D, Z4.D
- mls z0.d, p0/m, z0.d, z31.d
- MLS Z0.D, P0/M, Z0.D, Z31.D
-- movprfx z0, z0
-- MOVPRFX Z0, Z0
-- movprfx z1, z0
-- MOVPRFX Z1, Z0
-- movprfx z31, z0
-- MOVPRFX Z31, Z0
-- movprfx z0, z2
-- MOVPRFX Z0, Z2
-- movprfx z0, z31
-- MOVPRFX Z0, Z31
-- movprfx z0.b, p0/z, z0.b
-- MOVPRFX Z0.B, P0/Z, Z0.B
-- movprfx z1.b, p0/z, z0.b
-- MOVPRFX Z1.B, P0/Z, Z0.B
-- movprfx z31.b, p0/z, z0.b
-- MOVPRFX Z31.B, P0/Z, Z0.B
-- movprfx z0.b, p2/z, z0.b
-- MOVPRFX Z0.B, P2/Z, Z0.B
-- movprfx z0.b, p7/z, z0.b
-- MOVPRFX Z0.B, P7/Z, Z0.B
-- movprfx z0.b, p0/z, z3.b
-- MOVPRFX Z0.B, P0/Z, Z3.B
-- movprfx z0.b, p0/z, z31.b
-- MOVPRFX Z0.B, P0/Z, Z31.B
-- movprfx z0.b, p0/m, z0.b
-- MOVPRFX Z0.B, P0/M, Z0.B
-- movprfx z1.b, p0/m, z0.b
-- MOVPRFX Z1.B, P0/M, Z0.B
-- movprfx z31.b, p0/m, z0.b
-- MOVPRFX Z31.B, P0/M, Z0.B
-- movprfx z0.b, p2/m, z0.b
-- MOVPRFX Z0.B, P2/M, Z0.B
-- movprfx z0.b, p7/m, z0.b
-- MOVPRFX Z0.B, P7/M, Z0.B
-- movprfx z0.b, p0/m, z3.b
-- MOVPRFX Z0.B, P0/M, Z3.B
-- movprfx z0.b, p0/m, z31.b
-- MOVPRFX Z0.B, P0/M, Z31.B
-- movprfx z0.h, p0/z, z0.h
-- MOVPRFX Z0.H, P0/Z, Z0.H
-- movprfx z1.h, p0/z, z0.h
-- MOVPRFX Z1.H, P0/Z, Z0.H
-- movprfx z31.h, p0/z, z0.h
-- MOVPRFX Z31.H, P0/Z, Z0.H
-- movprfx z0.h, p2/z, z0.h
-- MOVPRFX Z0.H, P2/Z, Z0.H
-- movprfx z0.h, p7/z, z0.h
-- MOVPRFX Z0.H, P7/Z, Z0.H
-- movprfx z0.h, p0/z, z3.h
-- MOVPRFX Z0.H, P0/Z, Z3.H
-- movprfx z0.h, p0/z, z31.h
-- MOVPRFX Z0.H, P0/Z, Z31.H
-- movprfx z0.h, p0/m, z0.h
-- MOVPRFX Z0.H, P0/M, Z0.H
-- movprfx z1.h, p0/m, z0.h
-- MOVPRFX Z1.H, P0/M, Z0.H
-- movprfx z31.h, p0/m, z0.h
-- MOVPRFX Z31.H, P0/M, Z0.H
-- movprfx z0.h, p2/m, z0.h
-- MOVPRFX Z0.H, P2/M, Z0.H
-- movprfx z0.h, p7/m, z0.h
-- MOVPRFX Z0.H, P7/M, Z0.H
-- movprfx z0.h, p0/m, z3.h
-- MOVPRFX Z0.H, P0/M, Z3.H
-- movprfx z0.h, p0/m, z31.h
-- MOVPRFX Z0.H, P0/M, Z31.H
-- movprfx z0.s, p0/z, z0.s
-- MOVPRFX Z0.S, P0/Z, Z0.S
-- movprfx z1.s, p0/z, z0.s
-- MOVPRFX Z1.S, P0/Z, Z0.S
-- movprfx z31.s, p0/z, z0.s
-- MOVPRFX Z31.S, P0/Z, Z0.S
-- movprfx z0.s, p2/z, z0.s
-- MOVPRFX Z0.S, P2/Z, Z0.S
-- movprfx z0.s, p7/z, z0.s
-- MOVPRFX Z0.S, P7/Z, Z0.S
-- movprfx z0.s, p0/z, z3.s
-- MOVPRFX Z0.S, P0/Z, Z3.S
-- movprfx z0.s, p0/z, z31.s
-- MOVPRFX Z0.S, P0/Z, Z31.S
-- movprfx z0.s, p0/m, z0.s
-- MOVPRFX Z0.S, P0/M, Z0.S
-- movprfx z1.s, p0/m, z0.s
-- MOVPRFX Z1.S, P0/M, Z0.S
-- movprfx z31.s, p0/m, z0.s
-- MOVPRFX Z31.S, P0/M, Z0.S
-- movprfx z0.s, p2/m, z0.s
-- MOVPRFX Z0.S, P2/M, Z0.S
-- movprfx z0.s, p7/m, z0.s
-- MOVPRFX Z0.S, P7/M, Z0.S
-- movprfx z0.s, p0/m, z3.s
-- MOVPRFX Z0.S, P0/M, Z3.S
-- movprfx z0.s, p0/m, z31.s
-- MOVPRFX Z0.S, P0/M, Z31.S
-- movprfx z0.d, p0/z, z0.d
-- MOVPRFX Z0.D, P0/Z, Z0.D
-- movprfx z1.d, p0/z, z0.d
-- MOVPRFX Z1.D, P0/Z, Z0.D
-- movprfx z31.d, p0/z, z0.d
-- MOVPRFX Z31.D, P0/Z, Z0.D
-- movprfx z0.d, p2/z, z0.d
-- MOVPRFX Z0.D, P2/Z, Z0.D
-- movprfx z0.d, p7/z, z0.d
-- MOVPRFX Z0.D, P7/Z, Z0.D
-- movprfx z0.d, p0/z, z3.d
-- MOVPRFX Z0.D, P0/Z, Z3.D
-- movprfx z0.d, p0/z, z31.d
-- MOVPRFX Z0.D, P0/Z, Z31.D
-- movprfx z0.d, p0/m, z0.d
-- MOVPRFX Z0.D, P0/M, Z0.D
-- movprfx z1.d, p0/m, z0.d
-- MOVPRFX Z1.D, P0/M, Z0.D
-- movprfx z31.d, p0/m, z0.d
-- MOVPRFX Z31.D, P0/M, Z0.D
-- movprfx z0.d, p2/m, z0.d
-- MOVPRFX Z0.D, P2/M, Z0.D
-- movprfx z0.d, p7/m, z0.d
-- MOVPRFX Z0.D, P7/M, Z0.D
-- movprfx z0.d, p0/m, z3.d
-- MOVPRFX Z0.D, P0/M, Z3.D
-- movprfx z0.d, p0/m, z31.d
-- MOVPRFX Z0.D, P0/M, Z31.D
- msb z0.b, p0/m, z0.b, z0.b
- MSB Z0.B, P0/M, Z0.B, Z0.B
- msb z1.b, p0/m, z0.b, z0.b
-@@ -40540,3 +40418,25 @@
- ORN Z0.D, Z0.D, #0X1
-
- .include "advsimd-compnum.s"
-+
-+ # PR 22988 - check that [Rn] is equivalent to [Rn,xzr]
-+ ldff1b z0.b, p1/z, [x0]
-+ ldff1b z0.h, p1/z, [x1]
-+ ldff1b z0.s, p1/z, [x2]
-+ ldff1b z0.d, p1/z, [x3]
-+
-+ ldff1d z0.d, p0/z, [x0]
-+
-+ ldff1h z0.h, p1/z, [x9]
-+ ldff1h z0.s, p1/z, [x10]
-+ ldff1h z0.d, p1/z, [x11]
-+
-+ ldff1sb z0.s, p1/z, [x14]
-+ ldff1sb z0.d, p1/z, [x15]
-+
-+ ldff1sh z0.s, p1/z, [x18]
-+ ldff1sh z0.d, p1/z, [x19]
-+
-+ ldff1sw z0.d, p1/z, [x23]
-+
-+ ldff1w z0.d, p1/z, [x27]
-diff -rup binutils-2.30/gas/testsuite/gas/aarch64/sysreg-2.d binutils-2.30.new/gas/testsuite/gas/aarch64/sysreg-2.d
---- binutils-2.30/gas/testsuite/gas/aarch64/sysreg-2.d 2018-01-13 13:31:15.000000000 +0000
-+++ binutils-2.30.new/gas/testsuite/gas/aarch64/sysreg-2.d 2021-03-23 16:19:56.749751955 +0000
-@@ -38,8 +38,6 @@ Disassembly of section .text:
- [0-9a-f]+: d5389a27 mrs x7, pmbptr_el1
- [0-9a-f]+: d5189a67 msr pmbsr_el1, x7
- [0-9a-f]+: d5389a67 mrs x7, pmbsr_el1
-- [0-9a-f]+: d5189ae7 msr pmbidr_el1, x7
-- [0-9a-f]+: d5389ae7 mrs x7, pmbidr_el1
- [0-9a-f]+: d5189907 msr pmscr_el1, x7
- [0-9a-f]+: d5389907 mrs x7, pmscr_el1
- [0-9a-f]+: d5189947 msr pmsicr_el1, x7
-diff -rup binutils-2.30/gas/testsuite/gas/aarch64/sysreg-2.s binutils-2.30.new/gas/testsuite/gas/aarch64/sysreg-2.s
---- binutils-2.30/gas/testsuite/gas/aarch64/sysreg-2.s 2018-01-13 13:31:15.000000000 +0000
-+++ binutils-2.30.new/gas/testsuite/gas/aarch64/sysreg-2.s 2021-03-23 16:19:56.750751949 +0000
-@@ -44,7 +44,7 @@
-
- /* Statistical profiling. */
-
-- .irp reg, pmblimitr_el1, pmbptr_el1, pmbsr_el1 pmbidr_el1
-+ .irp reg, pmblimitr_el1, pmbptr_el1, pmbsr_el1
- rw_sys_reg sys_reg=\reg xreg=x7 r=1 w=1
- .endr
-
-diff -rup binutils-2.30/gas/testsuite/gas/aarch64/sysreg.d binutils-2.30.new/gas/testsuite/gas/aarch64/sysreg.d
---- binutils-2.30/gas/testsuite/gas/aarch64/sysreg.d 2018-01-13 13:31:15.000000000 +0000
-+++ binutils-2.30.new/gas/testsuite/gas/aarch64/sysreg.d 2021-03-23 16:19:56.731752078 +0000
-@@ -27,5 +27,5 @@ Disassembly of section \.text:
- 4c: d538cc00 mrs x0, s3_0_c12_c12_0
- 50: d5384600 mrs x0, s3_0_c4_c6_0
- 54: d5184600 msr s3_0_c4_c6_0, x0
-- 58: d5310300 mrs x0, s2_1_c0_c3_0
-- 5c: d5110300 msr s2_1_c0_c3_0, x0
-+ 58: d5310300 mrs x0, trcstatr
-+ 5c: d5110300 msr trcstatr, x0
-diff -rup binutils-2.30/gas/testsuite/gas/aarch64/system.d binutils-2.30.new/gas/testsuite/gas/aarch64/system.d
---- binutils-2.30/gas/testsuite/gas/aarch64/system.d 2018-01-13 13:31:15.000000000 +0000
-+++ binutils-2.30.new/gas/testsuite/gas/aarch64/system.d 2021-03-23 16:19:56.742752003 +0000
-@@ -30,7 +30,7 @@ Disassembly of section \.text:
- 58: d50321ff hint #0xf
- 5c: d503221f (hint #0x10|esb)
- 60: d503223f (hint #0x11|psb csync)
-- 64: d503225f hint #0x12
-+ 64: d503225f tsb csync
- 68: d503227f hint #0x13
- 6c: d503229f (hint #0x14|csdb)
- 70: d50322bf hint #0x15
-@@ -44,13 +44,13 @@ Disassembly of section \.text:
- 90: d50323bf (hint #0x1d|autiasp)
- 94: d50323df (hint #0x1e|autibz)
- 98: d50323ff (hint #0x1f|autibsp)
-- 9c: d503241f hint #0x20
-+ 9c: d503241f bti
- a0: d503243f hint #0x21
-- a4: d503245f hint #0x22
-+ a4: d503245f bti c
- a8: d503247f hint #0x23
-- ac: d503249f hint #0x24
-+ ac: d503249f bti j
- b0: d50324bf hint #0x25
-- b4: d50324df hint #0x26
-+ b4: d50324df bti jc
- b8: d50324ff hint #0x27
- bc: d503251f hint #0x28
- c0: d503253f hint #0x29
-@@ -141,11 +141,11 @@ Disassembly of section \.text:
- 214: d5032fdf hint #0x7e
- 218: d5032fff hint #0x7f
- 21c: d52bf7e7 sysl x7, #3, C15, C7, #7
-- 220: d503309f dsb #0x00
-+ 220: d503309f ssbb
- 224: d503319f dsb oshld
- 228: d503329f dsb oshst
- 22c: d503339f dsb osh
-- 230: d503349f dsb #0x04
-+ 230: d503349f pssbb
- 234: d503359f dsb nshld
- 238: d503369f dsb nshst
- 23c: d503379f dsb nsh
-diff -rup binutils-2.30/include/elf/aarch64.h binutils-2.30.new/include/elf/aarch64.h
---- binutils-2.30/include/elf/aarch64.h 2021-03-23 16:21:44.128021971 +0000
-+++ binutils-2.30.new/include/elf/aarch64.h 2021-03-23 16:20:02.838710563 +0000
-@@ -35,7 +35,6 @@
- entry point. */
- #define SHF_COMDEF 0x80000000 /* Section may be multiply defined
- in the input to a link step. */
--
- /* Processor specific dynamic array tags. */
- #define DT_AARCH64_BTI_PLT (DT_LOPROC + 1)
- #define DT_AARCH64_PAC_PLT (DT_LOPROC + 3)
-@@ -129,6 +128,10 @@ RELOC_NUMBER (R_AARCH64_P32_JUMP26, 20)
- /* BL: ((S+A-P) >> 2) & 0x3ffffff. */
- RELOC_NUMBER (R_AARCH64_P32_CALL26, 21)
-
-+/* Group relocations to create a 16 or 32 bit PC-relative offset inline. */
-+RELOC_NUMBER (R_AARCH64_P32_MOVW_PREL_G0, 22)
-+RELOC_NUMBER (R_AARCH64_P32_MOVW_PREL_G0_NC, 23)
-+RELOC_NUMBER (R_AARCH64_P32_MOVW_PREL_G1, 24)
-
- RELOC_NUMBER (R_AARCH64_P32_GOT_LD_PREL19, 25)
- RELOC_NUMBER (R_AARCH64_P32_ADR_GOT_PAGE, 26)
-@@ -156,6 +159,14 @@ RELOC_NUMBER (R_AARCH64_P32_TLSLE_MOVW_T
- RELOC_NUMBER (R_AARCH64_P32_TLSLE_ADD_TPREL_HI12, 109)
- RELOC_NUMBER (R_AARCH64_P32_TLSLE_ADD_TPREL_LO12, 110)
- RELOC_NUMBER (R_AARCH64_P32_TLSLE_ADD_TPREL_LO12_NC, 111)
-+RELOC_NUMBER (R_AARCH64_P32_TLSLE_LDST8_TPREL_LO12, 112)
-+RELOC_NUMBER (R_AARCH64_P32_TLSLE_LDST8_TPREL_LO12_NC, 113)
-+RELOC_NUMBER (R_AARCH64_P32_TLSLE_LDST16_TPREL_LO12, 114)
-+RELOC_NUMBER (R_AARCH64_P32_TLSLE_LDST16_TPREL_LO12_NC, 115)
-+RELOC_NUMBER (R_AARCH64_P32_TLSLE_LDST32_TPREL_LO12, 116)
-+RELOC_NUMBER (R_AARCH64_P32_TLSLE_LDST32_TPREL_LO12_NC, 117)
-+RELOC_NUMBER (R_AARCH64_P32_TLSLE_LDST64_TPREL_LO12, 118)
-+RELOC_NUMBER (R_AARCH64_P32_TLSLE_LDST64_TPREL_LO12_NC, 119)
-
- RELOC_NUMBER (R_AARCH64_P32_TLSDESC_LD_PREL19, 122)
- RELOC_NUMBER (R_AARCH64_P32_TLSDESC_ADR_PREL21, 123)
-diff -rup binutils-2.30/include/opcode/aarch64.h binutils-2.30.new/include/opcode/aarch64.h
---- binutils-2.30/include/opcode/aarch64.h 2018-01-13 13:31:16.000000000 +0000
-+++ binutils-2.30.new/include/opcode/aarch64.h 2021-03-23 16:20:02.837710569 +0000
-@@ -1,6 +1,6 @@
- /* AArch64 assembler/disassembler support.
-
-- Copyright (C) 2009-2018 Free Software Foundation, Inc.
-+ Copyright (C) 2009-2021 Free Software Foundation, Inc.
- Contributed by ARM Ltd.
-
- This file is part of GNU Binutils.
-@@ -37,35 +37,68 @@ extern "C" {
- typedef uint32_t aarch64_insn;
-
- /* The following bitmasks control CPU features. */
--#define AARCH64_FEATURE_SHA2 0x200000000ULL /* SHA2 instructions. */
--#define AARCH64_FEATURE_AES 0x800000000ULL /* AES instructions. */
--#define AARCH64_FEATURE_V8_4 0x000000800ULL /* ARMv8.4 processors. */
--#define AARCH64_FEATURE_SM4 0x100000000ULL /* SM3 & SM4 instructions. */
--#define AARCH64_FEATURE_SHA3 0x400000000ULL /* SHA3 instructions. */
--#define AARCH64_FEATURE_V8 0x00000001 /* All processors. */
--#define AARCH64_FEATURE_V8_2 0x00000020 /* ARMv8.2 processors. */
--#define AARCH64_FEATURE_V8_3 0x00000040 /* ARMv8.3 processors. */
--#define AARCH64_FEATURE_CRYPTO 0x00010000 /* Crypto instructions. */
--#define AARCH64_FEATURE_FP 0x00020000 /* FP instructions. */
--#define AARCH64_FEATURE_SIMD 0x00040000 /* SIMD instructions. */
--#define AARCH64_FEATURE_CRC 0x00080000 /* CRC instructions. */
--#define AARCH64_FEATURE_LSE 0x00100000 /* LSE instructions. */
--#define AARCH64_FEATURE_PAN 0x00200000 /* PAN instructions. */
--#define AARCH64_FEATURE_LOR 0x00400000 /* LOR instructions. */
--#define AARCH64_FEATURE_RDMA 0x00800000 /* v8.1 SIMD instructions. */
--#define AARCH64_FEATURE_V8_1 0x01000000 /* v8.1 features. */
--#define AARCH64_FEATURE_F16 0x02000000 /* v8.2 FP16 instructions. */
--#define AARCH64_FEATURE_RAS 0x04000000 /* RAS Extensions. */
--#define AARCH64_FEATURE_PROFILE 0x08000000 /* Statistical Profiling. */
--#define AARCH64_FEATURE_SVE 0x10000000 /* SVE instructions. */
--#define AARCH64_FEATURE_RCPC 0x20000000 /* RCPC instructions. */
--#define AARCH64_FEATURE_COMPNUM 0x40000000 /* Complex # instructions. */
--#define AARCH64_FEATURE_DOTPROD 0x080000000 /* Dot Product instructions. */
--#define AARCH64_FEATURE_F16_FML 0x1000000000ULL /* v8.2 FP16FML ins. */
-+#define AARCH64_FEATURE_V8 (1ULL << 0) /* All processors. */
-+#define AARCH64_FEATURE_V8_6 (1ULL << 1) /* ARMv8.6 processors. */
-+#define AARCH64_FEATURE_BFLOAT16 (1ULL << 2) /* Bfloat16 insns. */
-+#define AARCH64_FEATURE_V8_A (1ULL << 3) /* Armv8-A processors. */
-+#define AARCH64_FEATURE_SVE2 (1ULL << 4) /* SVE2 instructions. */
-+#define AARCH64_FEATURE_V8_2 (1ULL << 5) /* ARMv8.2 processors. */
-+#define AARCH64_FEATURE_V8_3 (1ULL << 6) /* ARMv8.3 processors. */
-+#define AARCH64_FEATURE_SVE2_AES (1ULL << 7)
-+#define AARCH64_FEATURE_SVE2_BITPERM (1ULL << 8)
-+#define AARCH64_FEATURE_SVE2_SM4 (1ULL << 9)
-+#define AARCH64_FEATURE_SVE2_SHA3 (1ULL << 10)
-+#define AARCH64_FEATURE_V8_4 (1ULL << 11) /* ARMv8.4 processors. */
-+#define AARCH64_FEATURE_V8_R (1ULL << 12) /* Armv8-R processors. */
-+#define AARCH64_FEATURE_V8_7 (1ULL << 13) /* Armv8.7 processors. */
-+#define AARCH64_FEATURE_LS64 (1ULL << 15) /* Atomic 64-byte load/store. */
-+#define AARCH64_FEATURE_PAC (1ULL << 16) /* v8.3 Pointer Authentication. */
-+#define AARCH64_FEATURE_FP (1ULL << 17) /* FP instructions. */
-+#define AARCH64_FEATURE_SIMD (1ULL << 18) /* SIMD instructions. */
-+#define AARCH64_FEATURE_CRC (1ULL << 19) /* CRC instructions. */
-+#define AARCH64_FEATURE_LSE (1ULL << 20) /* LSE instructions. */
-+#define AARCH64_FEATURE_PAN (1ULL << 21) /* PAN instructions. */
-+#define AARCH64_FEATURE_LOR (1ULL << 22) /* LOR instructions. */
-+#define AARCH64_FEATURE_RDMA (1ULL << 23) /* v8.1 SIMD instructions. */
-+#define AARCH64_FEATURE_V8_1 (1ULL << 24) /* v8.1 features. */
-+#define AARCH64_FEATURE_F16 (1ULL << 25) /* v8.2 FP16 instructions. */
-+#define AARCH64_FEATURE_RAS (1ULL << 26) /* RAS Extensions. */
-+#define AARCH64_FEATURE_PROFILE (1ULL << 27) /* Statistical Profiling. */
-+#define AARCH64_FEATURE_SVE (1ULL << 28) /* SVE instructions. */
-+#define AARCH64_FEATURE_RCPC (1ULL << 29) /* RCPC instructions. */
-+#define AARCH64_FEATURE_COMPNUM (1ULL << 30) /* Complex # instructions. */
-+#define AARCH64_FEATURE_DOTPROD (1ULL << 31) /* Dot Product instructions. */
-+#define AARCH64_FEATURE_SM4 (1ULL << 32) /* SM3 & SM4 instructions. */
-+#define AARCH64_FEATURE_SHA2 (1ULL << 33) /* SHA2 instructions. */
-+#define AARCH64_FEATURE_SHA3 (1ULL << 34) /* SHA3 instructions. */
-+#define AARCH64_FEATURE_AES (1ULL << 35) /* AES instructions. */
-+#define AARCH64_FEATURE_F16_FML (1ULL << 36) /* v8.2 FP16FML ins. */
-+#define AARCH64_FEATURE_V8_5 (1ULL << 37) /* ARMv8.5 processors. */
-+#define AARCH64_FEATURE_FLAGMANIP (1ULL << 38) /* v8.5 Flag Manipulation version 2. */
-+#define AARCH64_FEATURE_FRINTTS (1ULL << 39) /* FRINT[32,64][Z,X] insns. */
-+#define AARCH64_FEATURE_SB (1ULL << 40) /* SB instruction. */
-+#define AARCH64_FEATURE_PREDRES (1ULL << 41) /* Execution and Data Prediction Restriction instructions. */
-+#define AARCH64_FEATURE_CVADP (1ULL << 42) /* DC CVADP. */
-+#define AARCH64_FEATURE_RNG (1ULL << 43) /* Random Number instructions. */
-+#define AARCH64_FEATURE_BTI (1ULL << 44) /* BTI instructions. */
-+#define AARCH64_FEATURE_SCXTNUM (1ULL << 45) /* SCXTNUM_ELx. */
-+#define AARCH64_FEATURE_ID_PFR2 (1ULL << 46) /* ID_PFR2 instructions. */
-+#define AARCH64_FEATURE_SSBS (1ULL << 47) /* SSBS mechanism enabled. */
-+#define AARCH64_FEATURE_MEMTAG (1ULL << 48) /* Memory Tagging Extension. */
-+#define AARCH64_FEATURE_TME (1ULL << 49) /* Transactional Memory Extension. */
-+#define AARCH64_FEATURE_I8MM (1ULL << 52) /* Matrix Multiply instructions. */
-+#define AARCH64_FEATURE_F32MM (1ULL << 53)
-+#define AARCH64_FEATURE_F64MM (1ULL << 54)
-+#define AARCH64_FEATURE_FLAGM (1ULL << 55) /* v8.4 Flag Manipulation. */
-+
-+/* Crypto instructions are the combination of AES and SHA2. */
-+#define AARCH64_FEATURE_CRYPTO (AARCH64_FEATURE_SHA2 | AARCH64_FEATURE_AES)
-
- /* Architectures are the sum of the base and extensions. */
- #define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
-- AARCH64_FEATURE_FP \
-+ AARCH64_FEATURE_V8_A \
-+ | AARCH64_FEATURE_FP \
-+ | AARCH64_FEATURE_RAS \
- | AARCH64_FEATURE_SIMD)
- #define AARCH64_ARCH_V8_1 AARCH64_FEATURE (AARCH64_ARCH_V8, \
- AARCH64_FEATURE_CRC \
-@@ -75,16 +108,38 @@ typedef uint32_t aarch64_insn;
- | AARCH64_FEATURE_LOR \
- | AARCH64_FEATURE_RDMA)
- #define AARCH64_ARCH_V8_2 AARCH64_FEATURE (AARCH64_ARCH_V8_1, \
-- AARCH64_FEATURE_V8_2 \
-- | AARCH64_FEATURE_RAS)
-+ AARCH64_FEATURE_V8_2)
- #define AARCH64_ARCH_V8_3 AARCH64_FEATURE (AARCH64_ARCH_V8_2, \
- AARCH64_FEATURE_V8_3 \
-+ | AARCH64_FEATURE_PAC \
- | AARCH64_FEATURE_RCPC \
- | AARCH64_FEATURE_COMPNUM)
- #define AARCH64_ARCH_V8_4 AARCH64_FEATURE (AARCH64_ARCH_V8_3, \
- AARCH64_FEATURE_V8_4 \
- | AARCH64_FEATURE_DOTPROD \
-+ | AARCH64_FEATURE_FLAGM \
- | AARCH64_FEATURE_F16_FML)
-+#define AARCH64_ARCH_V8_5 AARCH64_FEATURE (AARCH64_ARCH_V8_4, \
-+ AARCH64_FEATURE_V8_5 \
-+ | AARCH64_FEATURE_FLAGMANIP \
-+ | AARCH64_FEATURE_FRINTTS \
-+ | AARCH64_FEATURE_SB \
-+ | AARCH64_FEATURE_PREDRES \
-+ | AARCH64_FEATURE_CVADP \
-+ | AARCH64_FEATURE_BTI \
-+ | AARCH64_FEATURE_SCXTNUM \
-+ | AARCH64_FEATURE_ID_PFR2 \
-+ | AARCH64_FEATURE_SSBS)
-+#define AARCH64_ARCH_V8_6 AARCH64_FEATURE (AARCH64_ARCH_V8_5, \
-+ AARCH64_FEATURE_V8_6 \
-+ | AARCH64_FEATURE_BFLOAT16 \
-+ | AARCH64_FEATURE_I8MM)
-+#define AARCH64_ARCH_V8_7 AARCH64_FEATURE (AARCH64_ARCH_V8_6, \
-+ AARCH64_FEATURE_V8_7 \
-+ | AARCH64_FEATURE_LS64)
-+#define AARCH64_ARCH_V8_R (AARCH64_FEATURE (AARCH64_ARCH_V8_4, \
-+ AARCH64_FEATURE_V8_R) \
-+ & ~(AARCH64_FEATURE_V8_A | AARCH64_FEATURE_LOR))
-
- #define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0)
- #define AARCH64_ANY AARCH64_FEATURE (-1, 0) /* Any basic core. */
-@@ -147,6 +202,8 @@ enum aarch64_opnd
- AARCH64_OPND_Rm, /* Integer register as source. */
- AARCH64_OPND_Rt, /* Integer register used in ld/st instructions. */
- AARCH64_OPND_Rt2, /* Integer register used in ld/st pair instructions. */
-+ AARCH64_OPND_Rt_LS64, /* Integer register used in LS64 instructions. */
-+ AARCH64_OPND_Rt_SP, /* Integer Rt or SP used in STG instructions. */
- AARCH64_OPND_Rs, /* Integer register used in ld/st exclusive. */
- AARCH64_OPND_Ra, /* Integer register used in ddp_3src instructions. */
- AARCH64_OPND_Rt_SYS, /* Integer register used in system instructions. */
-@@ -178,6 +235,8 @@ enum aarch64_opnd
- AARCH64_OPND_Ed, /* AdvSIMD Vector Element Vd. */
- AARCH64_OPND_En, /* AdvSIMD Vector Element Vn. */
- AARCH64_OPND_Em, /* AdvSIMD Vector Element Vm. */
-+ AARCH64_OPND_Em16, /* AdvSIMD Vector Element Vm restricted to V0 - V15 when
-+ qualifier is S_H. */
- AARCH64_OPND_LVn, /* AdvSIMD Vector register list used in e.g. TBL. */
- AARCH64_OPND_LVt, /* AdvSIMD Vector register list used in ld/st. */
- AARCH64_OPND_LVt_AL, /* AdvSIMD Vector register list for loading single
-@@ -207,9 +266,12 @@ enum aarch64_opnd
- AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field. */
- AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field. */
- AARCH64_OPND_UIMM4, /* Unsigned 4-bit immediate in the CRm field. */
-+ AARCH64_OPND_UIMM4_ADDG,/* Unsigned 4-bit immediate in addg/subg. */
- AARCH64_OPND_UIMM7, /* Unsigned 7-bit immediate in the CRm:op2 fields. */
-+ AARCH64_OPND_UIMM10, /* Unsigned 10-bit immediate in addg/subg. */
- AARCH64_OPND_BIT_NUM, /* Immediate. */
- AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions. */
-+ AARCH64_OPND_UNDEFINED,/* imm16 operand in undefined instruction. */
- AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions. */
- AARCH64_OPND_SIMM5, /* 5-bit signed immediate in the imm5 field. */
- AARCH64_OPND_NZCV, /* Flag bit specifier giving an alternative value for
-@@ -245,7 +307,11 @@ enum aarch64_opnd
- the mnemonic name for LDUR/STUR instructions
- wherever there is no ambiguity. */
- AARCH64_OPND_ADDR_SIMM10, /* Address of signed 10-bit immediate. */
-+ AARCH64_OPND_ADDR_SIMM11, /* Address with a signed 11-bit (multiple of
-+ 16) immediate. */
- AARCH64_OPND_ADDR_UIMM12, /* Address of unsigned 12-bit immediate. */
-+ AARCH64_OPND_ADDR_SIMM13, /* Address with a signed 13-bit (multiple of
-+ 16) immediate. */
- AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures. */
- AARCH64_OPND_ADDR_OFFSET, /* Address with an optional 9-bit immediate. */
- AARCH64_OPND_SIMD_ADDR_POST, /* Address of ld/st multiple post-indexed. */
-@@ -256,12 +322,16 @@ enum aarch64_opnd
- AARCH64_OPND_SYSREG_DC, /* System register <dc_op> operand. */
- AARCH64_OPND_SYSREG_IC, /* System register <ic_op> operand. */
- AARCH64_OPND_SYSREG_TLBI, /* System register <tlbi_op> operand. */
-+ AARCH64_OPND_SYSREG_SR, /* System register RCTX operand. */
- AARCH64_OPND_BARRIER, /* Barrier operand. */
-+ AARCH64_OPND_BARRIER_DSB_NXS, /* Barrier operand for DSB nXS variant. */
- AARCH64_OPND_BARRIER_ISB, /* Barrier operand for ISB. */
- AARCH64_OPND_PRFOP, /* Prefetch operation. */
- AARCH64_OPND_BARRIER_PSB, /* Barrier operand for PSB. */
-+ AARCH64_OPND_BTI_TARGET, /* BTI {<target>}. */
-
- AARCH64_OPND_SVE_ADDR_RI_S4x16, /* SVE [<Xn|SP>, #<simm4>*16]. */
-+ AARCH64_OPND_SVE_ADDR_RI_S4x32, /* SVE [<Xn|SP>, #<simm4>*32]. */
- AARCH64_OPND_SVE_ADDR_RI_S4xVL, /* SVE [<Xn|SP>, #<simm4>, MUL VL]. */
- AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, /* SVE [<Xn|SP>, #<simm4>*2, MUL VL]. */
- AARCH64_OPND_SVE_ADDR_RI_S4x3xVL, /* SVE [<Xn|SP>, #<simm4>*3, MUL VL]. */
-@@ -272,6 +342,7 @@ enum aarch64_opnd
- AARCH64_OPND_SVE_ADDR_RI_U6x2, /* SVE [<Xn|SP>, #<uimm6>*2]. */
- AARCH64_OPND_SVE_ADDR_RI_U6x4, /* SVE [<Xn|SP>, #<uimm6>*4]. */
- AARCH64_OPND_SVE_ADDR_RI_U6x8, /* SVE [<Xn|SP>, #<uimm6>*8]. */
-+ AARCH64_OPND_SVE_ADDR_R, /* SVE [<Xn|SP>]. */
- AARCH64_OPND_SVE_ADDR_RR, /* SVE [<Xn|SP>, <Xm|XZR>]. */
- AARCH64_OPND_SVE_ADDR_RR_LSL1, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #1]. */
- AARCH64_OPND_SVE_ADDR_RR_LSL2, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #2]. */
-@@ -280,6 +351,7 @@ enum aarch64_opnd
- AARCH64_OPND_SVE_ADDR_RX_LSL1, /* SVE [<Xn|SP>, <Xm>, LSL #1]. */
- AARCH64_OPND_SVE_ADDR_RX_LSL2, /* SVE [<Xn|SP>, <Xm>, LSL #2]. */
- AARCH64_OPND_SVE_ADDR_RX_LSL3, /* SVE [<Xn|SP>, <Xm>, LSL #3]. */
-+ AARCH64_OPND_SVE_ADDR_ZX, /* SVE [Zn.<T>{, <Xm>}]. */
- AARCH64_OPND_SVE_ADDR_RZ, /* SVE [<Xn|SP>, Zm.D]. */
- AARCH64_OPND_SVE_ADDR_RZ_LSL1, /* SVE [<Xn|SP>, Zm.D, LSL #1]. */
- AARCH64_OPND_SVE_ADDR_RZ_LSL2, /* SVE [<Xn|SP>, Zm.D, LSL #2]. */
-@@ -315,6 +387,7 @@ enum aarch64_opnd
- AARCH64_OPND_SVE_I1_ZERO_ONE, /* SVE choice between 0.0 and 1.0. */
- AARCH64_OPND_SVE_IMM_ROT1, /* SVE 1-bit rotate operand (90 or 270). */
- AARCH64_OPND_SVE_IMM_ROT2, /* SVE 2-bit rotate operand (N*90). */
-+ AARCH64_OPND_SVE_IMM_ROT3, /* SVE cadd 1-bit rotate (90 or 270). */
- AARCH64_OPND_SVE_INV_LIMM, /* SVE inverted logical immediate. */
- AARCH64_OPND_SVE_LIMM, /* SVE logical immediate. */
- AARCH64_OPND_SVE_LIMM_MOV, /* SVE logical immediate for MOV. */
-@@ -333,8 +406,10 @@ enum aarch64_opnd
- AARCH64_OPND_SVE_Rn_SP, /* Integer Rn or SP, alt. SVE position. */
- AARCH64_OPND_SVE_SHLIMM_PRED, /* SVE shift left amount (predicated). */
- AARCH64_OPND_SVE_SHLIMM_UNPRED, /* SVE shift left amount (unpredicated). */
-+ AARCH64_OPND_SVE_SHLIMM_UNPRED_22, /* SVE 3 bit shift left unpred. */
- AARCH64_OPND_SVE_SHRIMM_PRED, /* SVE shift right amount (predicated). */
- AARCH64_OPND_SVE_SHRIMM_UNPRED, /* SVE shift right amount (unpredicated). */
-+ AARCH64_OPND_SVE_SHRIMM_UNPRED_22, /* SVE 3 bit shift right unpred. */
- AARCH64_OPND_SVE_SIMM5, /* SVE signed 5-bit immediate. */
- AARCH64_OPND_SVE_SIMM5B, /* SVE secondary signed 5-bit immediate. */
- AARCH64_OPND_SVE_SIMM6, /* SVE signed 6-bit immediate. */
-@@ -354,12 +429,15 @@ enum aarch64_opnd
- AARCH64_OPND_SVE_Zm_16, /* SVE vector register in Zm, bits [20,16]. */
- AARCH64_OPND_SVE_Zm3_INDEX, /* z0-z7[0-3] in Zm, bits [20,16]. */
- AARCH64_OPND_SVE_Zm3_22_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 22. */
-+ AARCH64_OPND_SVE_Zm3_11_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 11. */
-+ AARCH64_OPND_SVE_Zm4_11_INDEX, /* z0-z15[0-3] in Zm plus bit 11. */
- AARCH64_OPND_SVE_Zm4_INDEX, /* z0-z15[0-1] in Zm, bits [20,16]. */
- AARCH64_OPND_SVE_Zn, /* SVE vector register in Zn. */
- AARCH64_OPND_SVE_Zn_INDEX, /* Indexed SVE vector register, for DUP. */
- AARCH64_OPND_SVE_ZnxN, /* SVE vector register list in Zn. */
- AARCH64_OPND_SVE_Zt, /* SVE vector register in Zt. */
- AARCH64_OPND_SVE_ZtxN, /* SVE vector register list in Zt. */
-+ AARCH64_OPND_TME_UIMM16, /* TME unsigned 16-bit immediate. */
- AARCH64_OPND_SM3_IMM2, /* SM3 encodes lane in bits [13, 14]. */
- };
-
-@@ -396,11 +474,13 @@ enum aarch64_opnd_qualifier
- AARCH64_OPND_QLF_S_S,
- AARCH64_OPND_QLF_S_D,
- AARCH64_OPND_QLF_S_Q,
-- /* This type qualifier has a special meaning in that it means that 4 x 1 byte
-- are selected by the instruction. Other than that it has no difference
-- with AARCH64_OPND_QLF_S_B in encoding. It is here purely for syntactical
-- reasons and is an exception from normal AArch64 disassembly scheme. */
-+ /* These type qualifiers have a special meaning in that they mean 4 x 1 byte
-+ or 2 x 2 byte are selected by the instruction. Other than that they have
-+ no difference with AARCH64_OPND_QLF_S_B in encoding. They are here purely
-+ for syntactical reasons and is an exception from normal AArch64
-+ disassembly scheme. */
- AARCH64_OPND_QLF_S_4B,
-+ AARCH64_OPND_QLF_S_2H,
-
- /* Qualifying an operand which is a SIMD vector register or a SIMD vector
- register list; indicating register shape.
-@@ -423,6 +503,10 @@ enum aarch64_opnd_qualifier
- AARCH64_OPND_QLF_P_Z,
- AARCH64_OPND_QLF_P_M,
-
-+ /* Used in scaled signed immediate that are scaled by a Tag granule
-+ like in stg, st2g, etc. */
-+ AARCH64_OPND_QLF_imm_tag,
-+
- /* Constraint on value. */
- AARCH64_OPND_QLF_CR, /* CRn, CRm. */
- AARCH64_OPND_QLF_imm_0_7,
-@@ -446,6 +530,7 @@ enum aarch64_opnd_qualifier
-
- enum aarch64_insn_class
- {
-+ aarch64_misc,
- addsub_carry,
- addsub_ext,
- addsub_imm,
-@@ -527,11 +612,19 @@ enum aarch64_insn_class
- sve_size_bhs,
- sve_size_bhsd,
- sve_size_hsd,
-+ sve_size_hsd2,
- sve_size_sd,
-+ sve_size_bh,
-+ sve_size_sd2,
-+ sve_size_13,
-+ sve_shift_tsz_hsd,
-+ sve_shift_tsz_bhsd,
-+ sve_size_tsz_bhs,
- testbranch,
- cryptosm3,
- cryptosm4,
- dotproduct,
-+ bfloat16,
- };
-
- /* Opcode enumerators. */
-@@ -638,6 +731,17 @@ enum aarch64_op
- OP_TOTAL_NUM, /* Pseudo. */
- };
-
-+/* Error types. */
-+enum err_type
-+{
-+ ERR_OK,
-+ ERR_UND,
-+ ERR_UNP,
-+ ERR_NYI,
-+ ERR_VFI,
-+ ERR_NR_ENTRIES
-+};
-+
- /* Maximum number of operands an instruction can have. */
- #define AARCH64_MAX_OPND_NUM 6
- /* Maximum number of qualifier sequences an instruction can have. */
-@@ -659,6 +763,13 @@ empty_qualifier_sequence_p (const aarch6
- return TRUE;
- }
-
-+/* Forward declare error reporting type. */
-+typedef struct aarch64_operand_error aarch64_operand_error;
-+/* Forward declare instruction sequence type. */
-+typedef struct aarch64_instr_sequence aarch64_instr_sequence;
-+/* Forward declare instruction definition. */
-+typedef struct aarch64_inst aarch64_inst;
-+
- /* This structure holds information for a particular opcode. */
-
- struct aarch64_opcode
-@@ -697,14 +808,19 @@ struct aarch64_opcode
- aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM];
-
- /* Flags providing information about this instruction */
-- uint32_t flags;
-+ uint64_t flags;
-+
-+ /* Extra constraints on the instruction that the verifier checks. */
-+ uint32_t constraints;
-
- /* If nonzero, this operand and operand 0 are both registers and
- are required to have the same register number. */
- unsigned char tied_operand;
-
- /* If non-NULL, a function to verify that a given instruction is valid. */
-- bfd_boolean (* verifier) (const struct aarch64_opcode *, const aarch64_insn);
-+ enum err_type (* verifier) (const struct aarch64_inst *, const aarch64_insn,
-+ bfd_vma, bfd_boolean, aarch64_operand_error *,
-+ struct aarch64_instr_sequence *);
- };
-
- typedef struct aarch64_opcode aarch64_opcode;
-@@ -764,7 +880,22 @@ extern aarch64_opcode aarch64_opcode_tab
- #define F_LSE_SZ (1 << 27)
- /* Require an exact qualifier match, even for NIL qualifiers. */
- #define F_STRICT (1ULL << 28)
--/* Next bit is 29. */
-+/* This system instruction is used to read system registers. */
-+#define F_SYS_READ (1ULL << 29)
-+/* This system instruction is used to write system registers. */
-+#define F_SYS_WRITE (1ULL << 30)
-+/* This instruction has an extra constraint on it that imposes a requirement on
-+ subsequent instructions. */
-+#define F_SCAN (1ULL << 31)
-+/* Next bit is 32. */
-+
-+/* Instruction constraints. */
-+/* This instruction has a predication constraint on the instruction at PC+4. */
-+#define C_SCAN_MOVPRFX (1U << 0)
-+/* This instruction's operation width is determined by the operand with the
-+ largest element size. */
-+#define C_MAX_ELEM (1U << 1)
-+/* Next bit is 2. */
-
- static inline bfd_boolean
- alias_opcode_p (const aarch64_opcode *opcode)
-@@ -826,21 +957,26 @@ struct aarch64_name_value_pair
-
- extern const struct aarch64_name_value_pair aarch64_operand_modifiers [];
- extern const struct aarch64_name_value_pair aarch64_barrier_options [16];
-+extern const struct aarch64_name_value_pair aarch64_barrier_dsb_nxs_options [4];
- extern const struct aarch64_name_value_pair aarch64_prfops [32];
- extern const struct aarch64_name_value_pair aarch64_hint_options [];
-
-+#define AARCH64_MAX_SYSREG_NAME_LEN 32
-+
- typedef struct
- {
- const char * name;
- aarch64_insn value;
- uint32_t flags;
-+
-+ /* A set of features, all of which are required for this system register to be
-+ available. */
-+ aarch64_feature_set features;
- } aarch64_sys_reg;
-
- extern const aarch64_sys_reg aarch64_sys_regs [];
- extern const aarch64_sys_reg aarch64_pstatefields [];
--extern bfd_boolean aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *);
--extern bfd_boolean aarch64_sys_reg_supported_p (const aarch64_feature_set,
-- const aarch64_sys_reg *);
-+extern bfd_boolean aarch64_sys_reg_deprecated_p (const uint32_t);
- extern bfd_boolean aarch64_pstatefield_supported_p (const aarch64_feature_set,
- const aarch64_sys_reg *);
-
-@@ -854,12 +990,14 @@ typedef struct
- extern bfd_boolean aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *);
- extern bfd_boolean
- aarch64_sys_ins_reg_supported_p (const aarch64_feature_set,
-- const aarch64_sys_ins_reg *);
-+ const char *reg_name, aarch64_insn,
-+ uint32_t, aarch64_feature_set);
-
- extern const aarch64_sys_ins_reg aarch64_sys_regs_ic [];
- extern const aarch64_sys_ins_reg aarch64_sys_regs_dc [];
- extern const aarch64_sys_ins_reg aarch64_sys_regs_at [];
- extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi [];
-+extern const aarch64_sys_ins_reg aarch64_sys_regs_sr [];
-
- /* Shift/extending operator kinds.
- N.B. order is important; keep aarch64_operand_modifiers synced. */
-@@ -956,9 +1094,17 @@ struct aarch64_opnd_info
- unsigned preind : 1; /* Pre-indexed. */
- unsigned postind : 1; /* Post-indexed. */
- } addr;
-+
-+ struct
-+ {
-+ /* The encoding of the system register. */
-+ aarch64_insn value;
-+
-+ /* The system register flags. */
-+ uint32_t flags;
-+ } sysreg;
-+
- const aarch64_cond *cond;
-- /* The encoding of the system register. */
-- aarch64_insn sysreg;
- /* The encoding of the PSTATE field. */
- aarch64_insn pstatefield;
- const aarch64_sys_ins_reg *sysins_op;
-@@ -1017,7 +1163,13 @@ struct aarch64_inst
- aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM];
- };
-
--typedef struct aarch64_inst aarch64_inst;
-+/* Defining the HINT #imm values for the aarch64_hint_options. */
-+#define HINT_OPD_CSYNC 0x11
-+#define HINT_OPD_C 0x22
-+#define HINT_OPD_J 0x24
-+#define HINT_OPD_JC 0x26
-+#define HINT_OPD_NULL 0x00
-+
-
- /* Diagnosis related declaration and interface. */
-
-@@ -1092,16 +1244,30 @@ struct aarch64_operand_error
- int index;
- const char *error;
- int data[3]; /* Some data for extra information. */
-+ bfd_boolean non_fatal;
- };
-
--typedef struct aarch64_operand_error aarch64_operand_error;
-+/* AArch64 sequence structure used to track instructions with F_SCAN
-+ dependencies for both assembler and disassembler. */
-+struct aarch64_instr_sequence
-+{
-+ /* The instruction that caused this sequence to be opened. */
-+ aarch64_inst *instr;
-+ /* The number of instructions the above instruction allows one to be kept in the
-+ sequence before an automatic close is done. */
-+ int num_insns;
-+ /* The instructions currently added to the sequence. */
-+ aarch64_inst **current_insns;
-+ /* The number of instructions already in the sequence. */
-+ int next_insn;
-+};
-
- /* Encoding entrypoint. */
-
- extern int
- aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *,
- aarch64_insn *, aarch64_opnd_qualifier_t *,
-- aarch64_operand_error *);
-+ aarch64_operand_error *, aarch64_instr_sequence *);
-
- extern const aarch64_opcode *
- aarch64_replace_opcode (struct aarch64_inst *,
-@@ -1116,7 +1282,9 @@ aarch64_get_opcode (enum aarch64_op);
- /* Generate the string representation of an operand. */
- extern void
- aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *,
-- const aarch64_opnd_info *, int, int *, bfd_vma *);
-+ const aarch64_opnd_info *, int, int *, bfd_vma *,
-+ char **,
-+ aarch64_feature_set features);
-
- /* Miscellaneous interface. */
-
-@@ -1127,6 +1295,9 @@ extern aarch64_opnd_qualifier_t
- aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int,
- const aarch64_opnd_qualifier_t, int);
-
-+extern bfd_boolean
-+aarch64_is_destructive_by_operands (const aarch64_opcode *);
-+
- extern int
- aarch64_num_of_operands (const aarch64_opcode *);
-
-@@ -1136,8 +1307,12 @@ aarch64_stack_pointer_p (const aarch64_o
- extern int
- aarch64_zero_register_p (const aarch64_opnd_info *);
-
--extern int
--aarch64_decode_insn (aarch64_insn, aarch64_inst *, bfd_boolean);
-+extern enum err_type
-+aarch64_decode_insn (aarch64_insn, aarch64_inst *, bfd_boolean,
-+ aarch64_operand_error *);
-+
-+extern void
-+init_insn_sequence (const struct aarch64_inst *, aarch64_instr_sequence *);
-
- /* Given an operand qualifier, return the expected data element size
- of a qualified operand. */
-Only in binutils-2.30/ld: ChangeLog.orig
-Only in binutils-2.30/ld: ChangeLog.rej
-diff -rup binutils-2.30/ld/emulparams/aarch64elf.sh binutils-2.30.new/ld/emulparams/aarch64elf.sh
---- binutils-2.30/ld/emulparams/aarch64elf.sh 2018-01-13 13:31:16.000000000 +0000
-+++ binutils-2.30.new/ld/emulparams/aarch64elf.sh 2021-03-23 16:19:53.200776080 +0000
-@@ -1,6 +1,6 @@
- ARCH=aarch64
- MACHINE=
--NOP=0
-+NOP=0x1f2003d5
-
- SCRIPT_NAME=elf
- ELFSIZE=64
-diff -rup binutils-2.30/ld/emulparams/aarch64linux.sh binutils-2.30.new/ld/emulparams/aarch64linux.sh
---- binutils-2.30/ld/emulparams/aarch64linux.sh 2018-01-13 13:31:16.000000000 +0000
-+++ binutils-2.30.new/ld/emulparams/aarch64linux.sh 2021-03-23 16:19:53.204776053 +0000
-@@ -1,6 +1,6 @@
- ARCH=aarch64
- MACHINE=
--NOP=0
-+NOP=0x1f2003d5
-
- SCRIPT_NAME=elf
- ELFSIZE=64
-Only in binutils-2.30/ld: ldlang.c.orig
-Only in binutils-2.30/ld: ldlang.c.rej
-diff -rup binutils-2.30/ld/testsuite/ld-aarch64/emit-relocs-534.d binutils-2.30.new/ld/testsuite/ld-aarch64/emit-relocs-534.d
---- binutils-2.30/ld/testsuite/ld-aarch64/emit-relocs-534.d 2018-01-13 13:31:16.000000000 +0000
-+++ binutils-2.30.new/ld/testsuite/ld-aarch64/emit-relocs-534.d 2021-03-23 16:19:53.549773708 +0000
-@@ -5,5 +5,5 @@
- 0000000000010000 <.text>:
- 10000: 798009d6 ldrsh x22, \[x14, #4\]
- 10000: R_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC v2
-- 10004: 79a71a28 ldrsh x8, \[x17, #5004\]
-+ 10004: 79871a28 ldrsh x8, \[x17, #908\]
- 10004: R_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC v3
-diff -rup binutils-2.30/ld/testsuite/ld-aarch64/erratum835769.d binutils-2.30.new/ld/testsuite/ld-aarch64/erratum835769.d
---- binutils-2.30/ld/testsuite/ld-aarch64/erratum835769.d 2018-01-13 13:31:16.000000000 +0000
-+++ binutils-2.30.new/ld/testsuite/ld-aarch64/erratum835769.d 2021-03-23 16:19:53.543773748 +0000
-@@ -33,7 +33,8 @@ Disassembly of section .text:
- [ \t0-9a-f]+:[ \t]+aa0503e0[ \t]+mov[ \t]+x0, x5
- [ \t0-9a-f]+:[ \t]+d65f03c0[ \t]+ret
-
--[ \t0-9a-f]+:[ \t]+14000007[ \t]+b[ \t]+[0-9a-f]+ <__erratum_835769_veneer_0\+0x8>
-+[ \t0-9a-f]+:[ \t]+14000008[ \t]+b[ \t]+[0-9a-f]+ <__erratum_835769_veneer_0\+0x8>
-+[ \t0-9a-f]+:[ \t]+d503201f[ \t]+nop
- [0-9a-f]+ <__erratum_835769_veneer_2>:
- [ \t0-9a-f]+:[ \t]+9b031885[ \t]+madd[ \t]+x5, x4, x3, x6
- [ \t0-9a-f]+:[ \t0-9a-z]+[ \t]+b[ \t]+[0-9a-f]+ <a7str\+0x[0-9a-f]+>
-diff -rup binutils-2.30/ld/testsuite/ld-aarch64/erratum843419.d binutils-2.30.new/ld/testsuite/ld-aarch64/erratum843419.d
---- binutils-2.30/ld/testsuite/ld-aarch64/erratum843419.d 2018-01-13 13:31:16.000000000 +0000
-+++ binutils-2.30.new/ld/testsuite/ld-aarch64/erratum843419.d 2021-03-23 16:19:53.544773742 +0000
-@@ -17,23 +17,24 @@ Disassembly of section .e843419:
- [ ]*20000ff8: 90100000 adrp x0, 40000000 <[_a-zA-Z0-9]+>
- [ ]*20000ffc: f800c007 stur x7, \[x0, #12\]
- [ ]*20001000: d2800128 mov x8, #0x9 // #9
--[ ]*20001004: 14000008 b 20001024 <e843419@0002_00000013_1004>
-+[ ]*20001004: 1400000. b 2000102. <e843419@0002_00000013_1004>
- [ ]*20001008: 8b050020 add x0, x1, x5
- [ ]*2000100c: b9400fe7 ldr w7, \[sp, #12\]
- [ ]*20001010: 0b0700e0 add w0, w7, w7
- [ ]*20001014: 910043ff add sp, sp, #0x10
--[ ]*20001018: 14000005 b 2000102c <__e835769_veneer>
-+[ ]*20001018: 1400000. b 200010.. <__e835769_veneer>
- [ ]*2000101c: d65f03c0 ret
--[ ]*20001020: 14000400 b 20002020 <__e835769_veneer\+0xff4>
-+[ ]*20001020: 14000400 b 200020.. <__e835769_veneer\+0xff.>
-+[ \t0-9a-f]+:[ \t]+d503201f[ \t]+nop
-
--0*20001024 <e843419@0002_00000013_1004>:
--[ ]*20001024: f9000008 str x8, \[x0\]
--[ ]*20001028: 17fffff8 b 20001008 <e843419_1\+0x10>
--
--0*2000102c <__e835769_veneer>:
--[ ]*2000102c: f0f17ff0 adrp x16, 3000000 <e835769>
--[ ]*20001030: 91000210 add x16, x16, #0x0
--[ ]*20001034: d61f0200 br x16
-+0*2000102. <e843419@0002_00000013_1004>:
-+[ ]*2000102.: f9000008 str x8, \[x0\]
-+[ ]*2000102.: 17fffff. b 20001008 <e843419_1\+0x10>
-+
-+0*200010.. <__e835769_veneer>:
-+[ ]*200010..: f0f17ff0 adrp x16, 3000000 <e835769>
-+[ ]*200010..: 91000210 add x16, x16, #0x0
-+[ ]*200010..: d61f0200 br x16
- ...
-
- Disassembly of section .e835769:
-@@ -42,14 +43,15 @@ Disassembly of section .e835769:
- [ ]*3000000: b8408c87 ldr w7, \[x4, #8\]!
- [ ]*3000004: 1b017c06 mul w6, w0, w1
- [ ]*3000008: f9400084 ldr x4, \[x4\]
--[ ]*300000c: 14000004 b 300001c <__erratum_835769_veneer_0>
-+[ ]*300000c: 1400000. b 30000.. <__erratum_835769_veneer_0>
- [ ]*3000010: aa0503e0 mov x0, x5
- [ ]*3000014: d65f03c0 ret
--[ ]*3000018: 14000400 b 3001018 <__erratum_835769_veneer_0\+0xffc>
-+[ ]*3000018: 14000400 b 3001018 <__erratum_835769_veneer_0\+0xff.>
-+[ \t0-9a-f]+:[ \t]+d503201f[ \t]+nop
-
--0*300001c <__erratum_835769_veneer_0>:
--[ ]*300001c: 9b031845 madd x5, x2, x3, x6
--[ ]*3000020: 17fffffc b 3000010 <e835769\+0x10>
-+0*30000.. <__erratum_835769_veneer_0>:
-+[ ]*30000..: 9b031845 madd x5, x2, x3, x6
-+[ ]*30000..: 17fffff. b 3000010 <e835769\+0x10>
- ...
-
- Disassembly of section .text:
-@@ -58,12 +60,13 @@ Disassembly of section .text:
- [ ]*400000: d10043ff sub sp, sp, #0x10
- [ ]*400004: d28001a7 mov x7, #0xd // #13
- [ ]*400008: b9000fe7 str w7, \[sp, #12\]
--[ ]*40000c: 14000003 b 400018 <__e843419_veneer>
-+[ ]*40000c: 1400000. b 40001. <__e843419_veneer>
- [ ]*400010: d65f03c0 ret
--[ ]*400014: 14000400 b 401014 <__e843419_veneer\+0xffc>
-+[ ]*400014: 14000400 b 401014 <__e843419_veneer\+0xff.>
-+[ \t0-9a-f]+:[ \t]+d503201f[ \t]+nop
-
--0*400018 <__e843419_veneer>:
--[ ]*400018: 900fe010 adrp x16, 20000000 <e843419>
--[ ]*40001c: 91000210 add x16, x16, #0x0
--[ ]*400020: d61f0200 br x16
-+0*4000.. <__e843419_veneer>:
-+[ ]*4000..: 900fe010 adrp x16, 20000000 <e843419>
-+[ ]*4000..: 91000210 add x16, x16, #0x0
-+[ ]*4000..: d61f0200 br x16
- ...
-diff -rup binutils-2.30/ld/testsuite/ld-aarch64/farcall-b-defsym.d binutils-2.30.new/ld/testsuite/ld-aarch64/farcall-b-defsym.d
---- binutils-2.30/ld/testsuite/ld-aarch64/farcall-b-defsym.d 2018-01-13 13:31:16.000000000 +0000
-+++ binutils-2.30.new/ld/testsuite/ld-aarch64/farcall-b-defsym.d 2021-03-23 16:19:53.549773708 +0000
-@@ -8,11 +8,12 @@
- Disassembly of section .text:
-
- 0+1000 <_start>:
-- +1000: 14000003 b 100c <__bar_veneer>
-+ +1000: 14000004 b 1010 <__bar_veneer>
- +1004: d65f03c0 ret
--[ \t]+1008:[ \t]+14000007[ \t]+b[ \t]+1024 <__bar_veneer\+0x18>
--0+100c <__bar_veneer>:
-- 100c: 90040010 adrp x16, 8001000 <bar>
-- 1010: 91000210 add x16, x16, #0x0
-- 1014: d61f0200 br x16
-+[ \t]+1008:[ \t]+14000008[ \t]+b[ \t]+1028 <__bar_veneer\+0x18>
-+[ \t]+100c:[ \t]+d503201f[ \t]+nop
-+0+1010 <__bar_veneer>:
-+ 1010: 90040010 adrp x16, 8001000 <bar>
-+ 1014: 91000210 add x16, x16, #0x0
-+ 1018: d61f0200 br x16
- ...
-diff -rup binutils-2.30/ld/testsuite/ld-aarch64/farcall-b-none-function.d binutils-2.30.new/ld/testsuite/ld-aarch64/farcall-b-none-function.d
---- binutils-2.30/ld/testsuite/ld-aarch64/farcall-b-none-function.d 2018-01-13 13:31:16.000000000 +0000
-+++ binutils-2.30.new/ld/testsuite/ld-aarch64/farcall-b-none-function.d 2021-03-23 16:19:53.547773721 +0000
-@@ -8,14 +8,15 @@
- Disassembly of section .text:
-
- .* <_start>:
-- 1000: 14000003 b 100c <__bar_veneer>
-+ 1000: 14000004 b 1010 <__bar_veneer>
- 1004: d65f03c0 ret
-- 1008: 14000007 b 1024 <__bar_veneer\+0x18>
-+ 1008: 14000008 b 1028 <__bar_veneer\+0x18>
-+ 100c: d503201f nop
-
- .* <__bar_veneer>:
-- 100c: 90040010 adrp x16, 8001000 <bar>
-- 1010: 91000210 add x16, x16, #0x0
-- 1014: d61f0200 br x16
-+ 1010: 90040010 adrp x16, 8001000 <bar>
-+ 1014: 91000210 add x16, x16, #0x0
-+ 1018: d61f0200 br x16
- ...
-
- Disassembly of section .foo:
-diff -rup binutils-2.30/ld/testsuite/ld-aarch64/farcall-b-plt.d binutils-2.30.new/ld/testsuite/ld-aarch64/farcall-b-plt.d
---- binutils-2.30/ld/testsuite/ld-aarch64/farcall-b-plt.d 2018-01-13 13:31:16.000000000 +0000
-+++ binutils-2.30.new/ld/testsuite/ld-aarch64/farcall-b-plt.d 2021-03-23 16:19:53.534773810 +0000
-@@ -1,5 +1,6 @@
- #name: aarch64-farcall-b-plt
- #source: farcall-b-plt.s
-+#target: [check_shared_lib_support]
- #as:
- #ld: -shared
- #objdump: -dr
-@@ -29,7 +30,9 @@ Disassembly of section .text:
- ...
- .*: .* b .* <__foo_veneer>
- .*: d65f03c0 ret
-+.*: .* nop
- .*: .* b .* <__foo_veneer\+.*>
-+.*: .* nop
-
- .* <__foo_veneer>:
- .*: .* adrp x16, 0 <.*>
-diff -rup binutils-2.30/ld/testsuite/ld-aarch64/farcall-b-section.d binutils-2.30.new/ld/testsuite/ld-aarch64/farcall-b-section.d
---- binutils-2.30/ld/testsuite/ld-aarch64/farcall-b-section.d 2018-01-13 13:31:16.000000000 +0000
-+++ binutils-2.30.new/ld/testsuite/ld-aarch64/farcall-b-section.d 2021-03-23 16:19:53.543773748 +0000
-@@ -8,21 +8,22 @@
- Disassembly of section .text:
-
- .* <_start>:
-- 1000: 14000008 b 1020 <___veneer>
-- 1004: 14000003 b 1010 <___veneer>
-+ 1000: 14000009 b 1024 <___veneer>
-+ 1004: 14000004 b 1014 <___veneer>
- 1008: d65f03c0 ret
-- 100c: 1400000d b 1040 <___veneer\+0x20>
-+ 100c: 1400000e b 1044 <___veneer\+0x20>
-+ 1010: d503201f nop
-
- .* <___veneer>:
-- 1010: 90040010 adrp x16, 8001000 <bar>
-- 1014: 91001210 add x16, x16, #0x4
-- 1018: d61f0200 br x16
-- 101c: 00000000 .inst 0x00000000 ; undefined
-+ 1014: 90040010 adrp x16, 8001000 <bar>
-+ 1018: 91001210 add x16, x16, #0x4
-+ 101c: d61f0200 br x16
-+ 1020: 00000000 udf #0
-
- .* <___veneer>:
-- 1020: 90040010 adrp x16, 8001000 <bar>
-- 1024: 91000210 add x16, x16, #0x0
-- 1028: d61f0200 br x16
-+ 1024: 90040010 adrp x16, 8001000 <bar>
-+ 1028: 91000210 add x16, x16, #0x0
-+ 102c: d61f0200 br x16
- ...
-
- Disassembly of section .foo:
-diff -rup binutils-2.30/ld/testsuite/ld-aarch64/farcall-b.d binutils-2.30.new/ld/testsuite/ld-aarch64/farcall-b.d
---- binutils-2.30/ld/testsuite/ld-aarch64/farcall-b.d 2018-01-13 13:31:16.000000000 +0000
-+++ binutils-2.30.new/ld/testsuite/ld-aarch64/farcall-b.d 2021-03-23 16:19:53.545773735 +0000
-@@ -8,13 +8,14 @@
- Disassembly of section .text:
-
- 0+1000 <_start>:
-- +1000: 14000003 b 100c <__bar_veneer>
-+ +1000: 14000004 b 1010 <__bar_veneer>
- +1004: d65f03c0 ret
--[ \t]+1008:[ \t]+14000007[ \t]+b[ \t]+1024 <__bar_veneer\+0x18>
--0+100c <__bar_veneer>:
-- 100c: 90040010 adrp x16, 8001000 <bar>
-- 1010: 91000210 add x16, x16, #0x0
-- 1014: d61f0200 br x16
-+[ \t]+1008:[ \t]+14000008[ \t]+b[ \t]+1028 <__bar_veneer\+0x18>
-+[ \t]+100c:[ \t]+d503201f[ \t]+nop
-+0+1010 <__bar_veneer>:
-+ 1010: 90040010 adrp x16, 8001000 <bar>
-+ 1014: 91000210 add x16, x16, #0x0
-+ 1018: d61f0200 br x16
- ...
-
- Disassembly of section .foo:
-diff -rup binutils-2.30/ld/testsuite/ld-aarch64/farcall-back.d binutils-2.30.new/ld/testsuite/ld-aarch64/farcall-back.d
---- binutils-2.30/ld/testsuite/ld-aarch64/farcall-back.d 2018-01-13 13:31:16.000000000 +0000
-+++ binutils-2.30.new/ld/testsuite/ld-aarch64/farcall-back.d 2021-03-23 16:19:53.544773742 +0000
-@@ -9,66 +9,68 @@
- Disassembly of section .text:
-
- 0000000000001000 <_start>:
-- 1000: 14000413 b 204c <__bar1_veneer>
-- 1004: 94000412 bl 204c <__bar1_veneer>
-- 1008: 14000407 b 2024 <__bar2_veneer>
-- 100c: 94000406 bl 2024 <__bar2_veneer>
-- 1010: 14000409 b 2034 <__bar3_veneer>
-- 1014: 94000408 bl 2034 <__bar3_veneer>
-+ 1000: 14000414 b 2050 <__bar1_veneer>
-+ 1004: 94000413 bl 2050 <__bar1_veneer>
-+ 1008: 14000408 b 2028 <__bar2_veneer>
-+ 100c: 94000407 bl 2028 <__bar2_veneer>
-+ 1010: 1400040a b 2038 <__bar3_veneer>
-+ 1014: 94000409 bl 2038 <__bar3_veneer>
- 1018: d65f03c0 ret
- ...
-
- 000000000000201c <_back>:
- 201c: d65f03c0 ret
-
--[ \t]+2020:[ \t]+14000013[ \t]+b[ \t]+206c <__bar1_veneer\+0x20>
--0000000000002024 <__bar2_veneer>:
-- 2024: f07ffff0 adrp x16, 100001000 <bar1\+0x1000>
-- 2028: 91002210 add x16, x16, #0x8
-- 202c: d61f0200 br x16
-- 2030: 00000000 .inst 0x00000000 ; undefined
--
--0000000000002034 <__bar3_veneer>:
-- 2034: 58000090 ldr x16, 2044 <__bar3_veneer\+0x10>
-- 2038: 10000011 adr x17, 2038 <__bar3_veneer\+0x4>
-- 203c: 8b110210 add x16, x16, x17
-- 2040: d61f0200 br x16
-- 2044: ffffffd8 .word 0xffffffd8
-- 2048: 00000000 .word 0x00000000
--
--000000000000204c <__bar1_veneer>:
-- 204c: d07ffff0 adrp x16, 100000000 <bar1>
-- 2050: 91000210 add x16, x16, #0x0
-- 2054: d61f0200 br x16
-+[ \t]+2020:[ \t]+14000014[ \t]+b[ \t]+2070 <__bar1_veneer\+0x20>
-+[ \t]+2024:[ \t]+d503201f[ \t]+nop
-+0000000000002028 <__bar2_veneer>:
-+ 2028: f07ffff0 adrp x16, 100001000 <bar1\+0x1000>
-+ 202c: 91002210 add x16, x16, #0x8
-+ 2030: d61f0200 br x16
-+ 2034: 00000000 udf #0
-+
-+0000000000002038 <__bar3_veneer>:
-+ 2038: 58000090 ldr x16, 2048 <__bar3_veneer\+0x10>
-+ 203c: 10000011 adr x17, 203c <__bar3_veneer\+0x4>
-+ 2040: 8b110210 add x16, x16, x17
-+ 2044: d61f0200 br x16
-+ 2048: ffffffd4 .word 0xffffffd4
-+ 204c: 00000000 .word 0x00000000
-+
-+0000000000002050 <__bar1_veneer>:
-+ 2050: d07ffff0 adrp x16, 100000000 <bar1>
-+ 2054: 91000210 add x16, x16, #0x0
-+ 2058: d61f0200 br x16
- ...
-
- Disassembly of section .foo:
-
- 0000000100000000 <bar1>:
- 100000000: d65f03c0 ret
-- 100000004: 14000806 b 10000201c <___start_veneer>
-+ 100000004: 14000807 b 100002020 <___start_veneer>
- ...
-
- 0000000100001008 <bar2>:
- 100001008: d65f03c0 ret
-- 10000100c: 14000404 b 10000201c <___start_veneer>
-+ 10000100c: 14000405 b 100002020 <___start_veneer>
- ...
-
- 0000000100002010 <bar3>:
- 100002010: d65f03c0 ret
-- 100002014: 14000008 b 100002034 <___back_veneer>
-+ 100002014: 14000009 b 100002038 <___back_veneer>
-
--[ \t]+100002018:[ \t]+1400000d[ \t]+b[ \t]+10000204c <___back_veneer\+0x18>
--000000010000201c <___start_veneer>:
-- 10000201c: 58000090 ldr x16, 10000202c <___start_veneer\+0x10>
-- 100002020: 10000011 adr x17, 100002020 <___start_veneer\+0x4>
-- 100002024: 8b110210 add x16, x16, x17
-- 100002028: d61f0200 br x16
-- 10000202c: ffffefe0 .word 0xffffefe0
-- 100002030: fffffffe .word 0xfffffffe
--
--0000000100002034 <___back_veneer>:
-- 100002034: 90800010 adrp x16, 2000 <_start\+0x1000>
-- 100002038: 91007210 add x16, x16, #0x1c
-- 10000203c: d61f0200 br x16
-+[ \t]+100002018:[ \t]+1400000e[ \t]+b[ \t]+100002050 <___back_veneer\+0x18>
-+[ \t]+10000201c:[ \t]+d503201f[ \t]+nop
-+0000000100002020 <___start_veneer>:
-+ 100002020: 58000090 ldr x16, 100002030 <___start_veneer\+0x10>
-+ 100002024: 10000011 adr x17, 100002024 <___start_veneer\+0x4>
-+ 100002028: 8b110210 add x16, x16, x17
-+ 10000202c: d61f0200 br x16
-+ 100002030: ffffefdc .word 0xffffefdc
-+ 100002034: fffffffe .word 0xfffffffe
-+
-+0000000100002038 <___back_veneer>:
-+ 100002038: 90800010 adrp x16, 2000 <_start\+0x1000>
-+ 10000203c: 91007210 add x16, x16, #0x1c
-+ 100002040: d61f0200 br x16
- ...
-diff -rup binutils-2.30/ld/testsuite/ld-aarch64/farcall-bl-defsym.d binutils-2.30.new/ld/testsuite/ld-aarch64/farcall-bl-defsym.d
---- binutils-2.30/ld/testsuite/ld-aarch64/farcall-bl-defsym.d 2018-01-13 13:31:16.000000000 +0000
-+++ binutils-2.30.new/ld/testsuite/ld-aarch64/farcall-bl-defsym.d 2021-03-23 16:19:53.543773748 +0000
-@@ -8,11 +8,12 @@
- Disassembly of section .text:
-
- 0+1000 <_start>:
-- +1000: 94000003 bl 100c <__bar_veneer>
-- +1004: d65f03c0 ret
--[ \t]+1008:[ \t]+14000007[ \t]+b[ \t]+1024 <__bar_veneer\+0x18>
--0+100c <__bar_veneer>:
-- 100c: 90040010 adrp x16, 8001000 <bar>
-- 1010: 91000210 add x16, x16, #0x0
-- 1014: d61f0200 br x16
-+[ \t]+1000:[ \t]+94000004[ \t]+bl[ \t]+1010 <__bar_veneer>
-+[ \t]+1004:[ \t]+d65f03c0[ \t]+ret
-+[ \t]+1008:[ \t]+14000008[ \t]+b[ \t]+1028 <__bar_veneer\+0x18>
-+[ \t]+100c:[ \t]+d503201f[ \t]+nop
-+0+1010 <__bar_veneer>:
-+[ \t]+1010:[ \t]+90040010[ \t]+adrp[ \t]+x16, 8001000 <bar>
-+[ \t]+1014:[ \t]+91000210[ \t]+add[ \t]+x16, x16, #0x0
-+[ \t]+1018:[ \t]+d61f0200[ \t]+br[ \t]+x16
- ...
-diff -rup binutils-2.30/ld/testsuite/ld-aarch64/farcall-bl-none-function.d binutils-2.30.new/ld/testsuite/ld-aarch64/farcall-bl-none-function.d
---- binutils-2.30/ld/testsuite/ld-aarch64/farcall-bl-none-function.d 2018-01-13 13:31:16.000000000 +0000
-+++ binutils-2.30.new/ld/testsuite/ld-aarch64/farcall-bl-none-function.d 2021-03-23 16:19:53.544773742 +0000
-@@ -8,14 +8,15 @@
- Disassembly of section .text:
-
- .* <_start>:
-- 1000: 94000003 bl 100c <__bar_veneer>
-+ 1000: 94000004 bl 1010 <__bar_veneer>
- 1004: d65f03c0 ret
-- 1008: 14000007 b 1024 <__bar_veneer\+0x18>
-+ 1008: 14000008 b 1028 <__bar_veneer\+0x18>
-+ 100c: d503201f nop
-
- .* <__bar_veneer>:
-- 100c: 90040010 adrp x16, 8001000 <bar>
-- 1010: 91000210 add x16, x16, #0x0
-- 1014: d61f0200 br x16
-+ 1010: 90040010 adrp x16, 8001000 <bar>
-+ 1014: 91000210 add x16, x16, #0x0
-+ 1018: d61f0200 br x16
- ...
-
- Disassembly of section .foo:
-diff -rup binutils-2.30/ld/testsuite/ld-aarch64/farcall-bl-plt.d binutils-2.30.new/ld/testsuite/ld-aarch64/farcall-bl-plt.d
---- binutils-2.30/ld/testsuite/ld-aarch64/farcall-bl-plt.d 2018-01-13 13:31:16.000000000 +0000
-+++ binutils-2.30.new/ld/testsuite/ld-aarch64/farcall-bl-plt.d 2021-03-23 16:19:53.547773721 +0000
-@@ -1,5 +1,6 @@
- #name: aarch64-farcall-bl-plt
- #source: farcall-bl-plt.s
-+#target: [check_shared_lib_support]
- #as:
- #ld: -shared
- #objdump: -dr
-@@ -29,7 +30,9 @@ Disassembly of section .text:
- ...
- .*: .* bl .* <__foo_veneer>
- .*: d65f03c0 ret
-+.*: .* nop
- .*: .* b .* <__foo_veneer\+.*>
-+.*: .* nop
-
- .* <__foo_veneer>:
- .*: .* adrp x16, 0 <.*>
-diff -rup binutils-2.30/ld/testsuite/ld-aarch64/farcall-bl-section.d binutils-2.30.new/ld/testsuite/ld-aarch64/farcall-bl-section.d
---- binutils-2.30/ld/testsuite/ld-aarch64/farcall-bl-section.d 2018-01-13 13:31:16.000000000 +0000
-+++ binutils-2.30.new/ld/testsuite/ld-aarch64/farcall-bl-section.d 2021-03-23 16:19:53.549773708 +0000
-@@ -8,21 +8,22 @@
- Disassembly of section .text:
-
- .* <_start>:
-- 1000: 94000008 bl 1020 <___veneer>
-- 1004: 94000003 bl 1010 <___veneer>
-+ 1000: 94000009 bl 1024 <___veneer>
-+ 1004: 94000004 bl 1014 <___veneer>
- 1008: d65f03c0 ret
-- 100c: 1400000d b 1040 <___veneer\+0x20>
-+ 100c: 1400000e b 1044 <___veneer\+0x20>
-+ 1010: d503201f nop
-
- .* <___veneer>:
-- 1010: 90040010 adrp x16, 8001000 <bar>
-- 1014: 91001210 add x16, x16, #0x4
-- 1018: d61f0200 br x16
-- 101c: 00000000 .inst 0x00000000 ; undefined
-+ 1014: 90040010 adrp x16, 8001000 <bar>
-+ 1018: 91001210 add x16, x16, #0x4
-+ 101c: d61f0200 br x16
-+ 1020: 00000000 udf #0
-
- .* <___veneer>:
-- 1020: 90040010 adrp x16, 8001000 <bar>
-- 1024: 91000210 add x16, x16, #0x0
-- 1028: d61f0200 br x16
-+ 1024: 90040010 adrp x16, 8001000 <bar>
-+ 1028: 91000210 add x16, x16, #0x0
-+ 102c: d61f0200 br x16
- ...
-
- Disassembly of section .foo:
-diff -rup binutils-2.30/ld/testsuite/ld-aarch64/farcall-bl.d binutils-2.30.new/ld/testsuite/ld-aarch64/farcall-bl.d
---- binutils-2.30/ld/testsuite/ld-aarch64/farcall-bl.d 2018-01-13 13:31:16.000000000 +0000
-+++ binutils-2.30.new/ld/testsuite/ld-aarch64/farcall-bl.d 2021-03-23 16:19:53.548773715 +0000
-@@ -8,13 +8,14 @@
- Disassembly of section .text:
-
- 0+1000 <_start>:
-- +1000: 94000003 bl 100c <__bar_veneer>
-- +1004: d65f03c0 ret
--[ \t]+1008:[ \t]+14000007[ \t]+b[ \t]+1024 <__bar_veneer\+0x18>
--0+100c <__bar_veneer>:
-- 100c: 90040010 adrp x16, 8001000 <bar>
-- 1010: 91000210 add x16, x16, #0x0
-- 1014: d61f0200 br x16
-+[ \t]+1000:[ \t]+94000004[ \t]+ bl[ \t]+1010 <__bar_veneer>
-+[ \t]+1004:[ \t]+d65f03c0[ \t]+ret
-+[ \t]+1008:[ \t]+14000008[ \t]+b[ \t]+1028 <__bar_veneer\+0x18>
-+[ \t]+100c:[ \t]+d503201f[ \t]+nop
-+0+1010 <__bar_veneer>:
-+[ \t]+1010:[ \t]+90040010[ \t]+adrp[ \t]+x16, 8001000 <bar>
-+[ \t]+1014:[ \t]+91000210[ \t]+add[ \t]+x16, x16, #0x0
-+[ \t]+1018:[ \t]+d61f0200[ \t]+br[ \t]+x16
- ...
-
- Disassembly of section .foo:
-diff -rup binutils-2.30/ld/testsuite/ld-aarch64/ifunc-21.d binutils-2.30.new/ld/testsuite/ld-aarch64/ifunc-21.d
---- binutils-2.30/ld/testsuite/ld-aarch64/ifunc-21.d 2018-01-13 13:31:16.000000000 +0000
-+++ binutils-2.30.new/ld/testsuite/ld-aarch64/ifunc-21.d 2021-03-23 16:19:53.544773742 +0000
-@@ -11,7 +11,7 @@ Contents of section .text:
- [0-9a-f]+ .*
- Contents of section .got.plt:
- [0-9a-f]+ 0+ 0+ 0+ 0+ .*
-- (103b8|10408) 0+ 0+ [0-9a-f]+ [0-9a-f]+ .*
-+ (103.8|10408) 0+ 0+ [0-9a-f]+ [0-9a-f]+ .*
-
- Disassembly of section .text:
-
-@@ -20,7 +20,7 @@ Disassembly of section .text:
-
- .* <bar>:
- .*: 90000080 adrp x0, 10000 <.*>
-- .*: .* ldr x0, \[x0, #(960|1040)\]
-+ .*: .* ldr x0, \[x0, #(896|960|976|1040)\]
- .*: d65f03c0 ret
-
--#pass
-\ No newline at end of file
-+#pass
-diff -rup binutils-2.30/ld/testsuite/ld-elf/elf.exp binutils-2.30.new/ld/testsuite/ld-elf/elf.exp
---- binutils-2.30/ld/testsuite/ld-elf/elf.exp 2021-03-23 16:21:44.845017097 +0000
-+++ binutils-2.30.new/ld/testsuite/ld-elf/elf.exp 2021-03-23 16:19:53.755772308 +0000
-@@ -210,7 +210,7 @@ if { [check_shared_lib_support] } then {
- {"Build pr20995-2.so"
- "-shared -z relro" "" ""
- {pr20995c.s} {{readelf {-l --wide} pr20995-2so.r}} "pr20995-2.so"}
-- } "tic6x-*-*" "arm*-*-eabi*" "hppa*64*-*-hpux*"
-+ } "tic6x-*-*" "arm*-*-eabi*" "hppa*64*-*-hpux*" "aarch64*-*-*"
-
- # These targets don't copy dynamic variables into .bss.
- setup_xfail "alpha-*-*" "bfin-*-*" "ia64-*-*" "xtensa-*-*"
-@@ -225,7 +225,7 @@ if { [check_shared_lib_support] } then {
- # xfail on arm*-*-eabi* is particularly because of no support of GNU_RELRO.
- # Please see the link above for details.
- setup_xfail "alpha-*-*" "bfin-*-*" "ia64-*-*" "xtensa-*-*" "arm*-*-eabi*"
-- setup_xfail "hppa*64*-*-hpux*"
-+ setup_xfail "hppa*64*-*-hpux*" "aarch*-*-*"
- run_ld_link_tests [list \
- [list \
- "pr20995-2" \
-diff -rup binutils-2.30/opcodes/aarch64-asm-2.c binutils-2.30.new/opcodes/aarch64-asm-2.c
---- binutils-2.30/opcodes/aarch64-asm-2.c 2018-01-13 13:31:16.000000000 +0000
-+++ binutils-2.30.new/opcodes/aarch64-asm-2.c 2021-03-23 16:19:53.174776257 +0000
-@@ -1,5 +1,5 @@
- /* This file is automatically generated by aarch64-gen. Do not edit! */
--/* Copyright (C) 2012-2018 Free Software Foundation, Inc.
-+/* Copyright (C) 2012-2021 Free Software Foundation, Inc.
- Contributed by ARM Ltd.
-
- This file is part of the GNU opcodes library.
-@@ -58,520 +58,544 @@ aarch64_find_real_opcode (const aarch64_
- case 17: /* subs */
- value = 17; /* --> subs. */
- break;
-- case 21: /* cmn */
-- case 20: /* adds */
-- value = 20; /* --> adds. */
-- break;
-- case 23: /* neg */
-- case 22: /* sub */
-- value = 22; /* --> sub. */
-- break;
-- case 26: /* negs */
-- case 25: /* cmp */
-- case 24: /* subs */
-- value = 24; /* --> subs. */
-- break;
-- case 151: /* mov */
-- case 150: /* umov */
-- value = 150; /* --> umov. */
-+ case 23: /* cmn */
-+ case 22: /* adds */
-+ value = 22; /* --> adds. */
-+ break;
-+ case 25: /* neg */
-+ case 24: /* sub */
-+ value = 24; /* --> sub. */
-+ break;
-+ case 27: /* cmp */
-+ case 28: /* negs */
-+ case 26: /* subs */
-+ value = 26; /* --> subs. */
- break;
- case 153: /* mov */
-- case 152: /* ins */
-- value = 152; /* --> ins. */
-+ case 152: /* umov */
-+ value = 152; /* --> umov. */
- break;
- case 155: /* mov */
- case 154: /* ins */
- value = 154; /* --> ins. */
- break;
-- case 237: /* mvn */
-- case 236: /* not */
-- value = 236; /* --> not. */
-- break;
-- case 312: /* mov */
-- case 311: /* orr */
-- value = 311; /* --> orr. */
-- break;
-- case 383: /* sxtl */
-- case 382: /* sshll */
-- value = 382; /* --> sshll. */
-- break;
-- case 385: /* sxtl2 */
-- case 384: /* sshll2 */
-- value = 384; /* --> sshll2. */
-- break;
-- case 407: /* uxtl */
-- case 406: /* ushll */
-- value = 406; /* --> ushll. */
-- break;
-- case 409: /* uxtl2 */
-- case 408: /* ushll2 */
-- value = 408; /* --> ushll2. */
-- break;
-- case 530: /* mov */
-- case 529: /* dup */
-- value = 529; /* --> dup. */
-- break;
-- case 617: /* sxtw */
-- case 616: /* sxth */
-- case 615: /* sxtb */
-- case 618: /* asr */
-- case 614: /* sbfx */
-- case 613: /* sbfiz */
-- case 612: /* sbfm */
-- value = 612; /* --> sbfm. */
-- break;
-- case 621: /* bfc */
-- case 622: /* bfxil */
-- case 620: /* bfi */
-- case 619: /* bfm */
-- value = 619; /* --> bfm. */
-- break;
-- case 627: /* uxth */
-- case 626: /* uxtb */
-- case 629: /* lsr */
-- case 628: /* lsl */
-- case 625: /* ubfx */
-- case 624: /* ubfiz */
-- case 623: /* ubfm */
-- value = 623; /* --> ubfm. */
-- break;
-- case 659: /* cset */
-- case 658: /* cinc */
-- case 657: /* csinc */
-- value = 657; /* --> csinc. */
-- break;
-- case 662: /* csetm */
-- case 661: /* cinv */
-- case 660: /* csinv */
-- value = 660; /* --> csinv. */
-- break;
-- case 664: /* cneg */
-- case 663: /* csneg */
-- value = 663; /* --> csneg. */
-- break;
-- case 682: /* rev */
-- case 683: /* rev64 */
-- value = 682; /* --> rev. */
-- break;
-- case 708: /* lsl */
-- case 707: /* lslv */
-- value = 707; /* --> lslv. */
-- break;
-- case 710: /* lsr */
-- case 709: /* lsrv */
-- value = 709; /* --> lsrv. */
-- break;
-- case 712: /* asr */
-- case 711: /* asrv */
-- value = 711; /* --> asrv. */
-- break;
-- case 714: /* ror */
-- case 713: /* rorv */
-- value = 713; /* --> rorv. */
-- break;
-- case 725: /* mul */
-- case 724: /* madd */
-- value = 724; /* --> madd. */
-- break;
-- case 727: /* mneg */
-- case 726: /* msub */
-- value = 726; /* --> msub. */
-- break;
-- case 729: /* smull */
-- case 728: /* smaddl */
-- value = 728; /* --> smaddl. */
-- break;
-- case 731: /* smnegl */
-- case 730: /* smsubl */
-- value = 730; /* --> smsubl. */
-- break;
-- case 734: /* umull */
-- case 733: /* umaddl */
-- value = 733; /* --> umaddl. */
-- break;
-- case 736: /* umnegl */
-- case 735: /* umsubl */
-- value = 735; /* --> umsubl. */
-- break;
-- case 747: /* ror */
-- case 746: /* extr */
-- value = 746; /* --> extr. */
-- break;
-- case 960: /* bic */
-- case 959: /* and */
-- value = 959; /* --> and. */
-- break;
-- case 962: /* mov */
-- case 961: /* orr */
-- value = 961; /* --> orr. */
-- break;
-- case 965: /* tst */
-- case 964: /* ands */
-- value = 964; /* --> ands. */
-- break;
-- case 970: /* uxtw */
-- case 969: /* mov */
-- case 968: /* orr */
-- value = 968; /* --> orr. */
-- break;
-- case 972: /* mvn */
-- case 971: /* orn */
-- value = 971; /* --> orn. */
-- break;
-- case 976: /* tst */
-- case 975: /* ands */
-- value = 975; /* --> ands. */
-- break;
-- case 1102: /* staddb */
-- case 1006: /* ldaddb */
-- value = 1006; /* --> ldaddb. */
-- break;
-- case 1103: /* staddh */
-- case 1007: /* ldaddh */
-- value = 1007; /* --> ldaddh. */
-- break;
-- case 1104: /* stadd */
-- case 1008: /* ldadd */
-- value = 1008; /* --> ldadd. */
-- break;
-- case 1105: /* staddlb */
-- case 1010: /* ldaddlb */
-- value = 1010; /* --> ldaddlb. */
-- break;
-- case 1106: /* staddlh */
-- case 1013: /* ldaddlh */
-- value = 1013; /* --> ldaddlh. */
-- break;
-- case 1107: /* staddl */
-- case 1016: /* ldaddl */
-- value = 1016; /* --> ldaddl. */
-- break;
-- case 1108: /* stclrb */
-- case 1018: /* ldclrb */
-- value = 1018; /* --> ldclrb. */
-- break;
-- case 1109: /* stclrh */
-- case 1019: /* ldclrh */
-- value = 1019; /* --> ldclrh. */
-- break;
-- case 1110: /* stclr */
-- case 1020: /* ldclr */
-- value = 1020; /* --> ldclr. */
-- break;
-- case 1111: /* stclrlb */
-- case 1022: /* ldclrlb */
-- value = 1022; /* --> ldclrlb. */
-- break;
-- case 1112: /* stclrlh */
-- case 1025: /* ldclrlh */
-- value = 1025; /* --> ldclrlh. */
-- break;
-- case 1113: /* stclrl */
-- case 1028: /* ldclrl */
-- value = 1028; /* --> ldclrl. */
-- break;
-- case 1114: /* steorb */
-- case 1030: /* ldeorb */
-- value = 1030; /* --> ldeorb. */
-- break;
-- case 1115: /* steorh */
-- case 1031: /* ldeorh */
-- value = 1031; /* --> ldeorh. */
-- break;
-- case 1116: /* steor */
-- case 1032: /* ldeor */
-- value = 1032; /* --> ldeor. */
-- break;
-- case 1117: /* steorlb */
-- case 1034: /* ldeorlb */
-- value = 1034; /* --> ldeorlb. */
-- break;
-- case 1118: /* steorlh */
-- case 1037: /* ldeorlh */
-- value = 1037; /* --> ldeorlh. */
-- break;
-- case 1119: /* steorl */
-- case 1040: /* ldeorl */
-- value = 1040; /* --> ldeorl. */
-- break;
-- case 1120: /* stsetb */
-- case 1042: /* ldsetb */
-- value = 1042; /* --> ldsetb. */
-- break;
-- case 1121: /* stseth */
-- case 1043: /* ldseth */
-- value = 1043; /* --> ldseth. */
-- break;
-- case 1122: /* stset */
-- case 1044: /* ldset */
-- value = 1044; /* --> ldset. */
-- break;
-- case 1123: /* stsetlb */
-- case 1046: /* ldsetlb */
-- value = 1046; /* --> ldsetlb. */
-- break;
-- case 1124: /* stsetlh */
-- case 1049: /* ldsetlh */
-- value = 1049; /* --> ldsetlh. */
-- break;
-- case 1125: /* stsetl */
-- case 1052: /* ldsetl */
-- value = 1052; /* --> ldsetl. */
-- break;
-- case 1126: /* stsmaxb */
-- case 1054: /* ldsmaxb */
-- value = 1054; /* --> ldsmaxb. */
-- break;
-- case 1127: /* stsmaxh */
-- case 1055: /* ldsmaxh */
-- value = 1055; /* --> ldsmaxh. */
-- break;
-- case 1128: /* stsmax */
-- case 1056: /* ldsmax */
-- value = 1056; /* --> ldsmax. */
-- break;
-- case 1129: /* stsmaxlb */
-- case 1058: /* ldsmaxlb */
-- value = 1058; /* --> ldsmaxlb. */
-- break;
-- case 1130: /* stsmaxlh */
-- case 1061: /* ldsmaxlh */
-- value = 1061; /* --> ldsmaxlh. */
-- break;
-- case 1131: /* stsmaxl */
-- case 1064: /* ldsmaxl */
-- value = 1064; /* --> ldsmaxl. */
-- break;
-- case 1132: /* stsminb */
-- case 1066: /* ldsminb */
-- value = 1066; /* --> ldsminb. */
-- break;
-- case 1133: /* stsminh */
-- case 1067: /* ldsminh */
-- value = 1067; /* --> ldsminh. */
-- break;
-- case 1134: /* stsmin */
-- case 1068: /* ldsmin */
-- value = 1068; /* --> ldsmin. */
-- break;
-- case 1135: /* stsminlb */
-- case 1070: /* ldsminlb */
-- value = 1070; /* --> ldsminlb. */
-- break;
-- case 1136: /* stsminlh */
-- case 1073: /* ldsminlh */
-- value = 1073; /* --> ldsminlh. */
-- break;
-- case 1137: /* stsminl */
-- case 1076: /* ldsminl */
-- value = 1076; /* --> ldsminl. */
-- break;
-- case 1138: /* stumaxb */
-- case 1078: /* ldumaxb */
-- value = 1078; /* --> ldumaxb. */
-- break;
-- case 1139: /* stumaxh */
-- case 1079: /* ldumaxh */
-- value = 1079; /* --> ldumaxh. */
-- break;
-- case 1140: /* stumax */
-- case 1080: /* ldumax */
-- value = 1080; /* --> ldumax. */
-- break;
-- case 1141: /* stumaxlb */
-- case 1082: /* ldumaxlb */
-- value = 1082; /* --> ldumaxlb. */
-- break;
-- case 1142: /* stumaxlh */
-- case 1085: /* ldumaxlh */
-- value = 1085; /* --> ldumaxlh. */
-- break;
-- case 1143: /* stumaxl */
-- case 1088: /* ldumaxl */
-- value = 1088; /* --> ldumaxl. */
-- break;
-- case 1144: /* stuminb */
-- case 1090: /* lduminb */
-- value = 1090; /* --> lduminb. */
-- break;
-- case 1145: /* stuminh */
-- case 1091: /* lduminh */
-- value = 1091; /* --> lduminh. */
-- break;
-- case 1146: /* stumin */
-- case 1092: /* ldumin */
-- value = 1092; /* --> ldumin. */
-- break;
-- case 1147: /* stuminlb */
-- case 1094: /* lduminlb */
-- value = 1094; /* --> lduminlb. */
-- break;
-- case 1148: /* stuminlh */
-- case 1097: /* lduminlh */
-- value = 1097; /* --> lduminlh. */
-- break;
-- case 1149: /* stuminl */
-- case 1100: /* lduminl */
-- value = 1100; /* --> lduminl. */
-- break;
-- case 1151: /* mov */
-- case 1150: /* movn */
-- value = 1150; /* --> movn. */
-- break;
-- case 1153: /* mov */
-- case 1152: /* movz */
-- value = 1152; /* --> movz. */
-- break;
-- case 1192: /* autibsp */
-- case 1191: /* autibz */
-- case 1190: /* autiasp */
-- case 1189: /* autiaz */
-- case 1188: /* pacibsp */
-- case 1187: /* pacibz */
-- case 1186: /* paciasp */
-- case 1185: /* paciaz */
-- case 1172: /* psb */
-- case 1171: /* esb */
-- case 1170: /* autib1716 */
-- case 1169: /* autia1716 */
-- case 1168: /* pacib1716 */
-- case 1167: /* pacia1716 */
-- case 1166: /* xpaclri */
-- case 1165: /* sevl */
-- case 1164: /* sev */
-- case 1163: /* wfi */
-- case 1162: /* wfe */
-- case 1161: /* yield */
-- case 1160: /* csdb */
-- case 1159: /* nop */
-- case 1158: /* hint */
-- value = 1158; /* --> hint. */
-- break;
-- case 1181: /* tlbi */
-- case 1180: /* ic */
-- case 1179: /* dc */
-- case 1178: /* at */
-- case 1177: /* sys */
-- value = 1177; /* --> sys. */
-- break;
-- case 1974: /* bic */
-- case 1240: /* and */
-- value = 1240; /* --> and. */
-- break;
-- case 1223: /* mov */
-- case 1242: /* and */
-- value = 1242; /* --> and. */
-- break;
-- case 1227: /* movs */
-- case 1243: /* ands */
-- value = 1243; /* --> ands. */
-- break;
-- case 1975: /* cmple */
-- case 1278: /* cmpge */
-- value = 1278; /* --> cmpge. */
-- break;
-- case 1978: /* cmplt */
-- case 1281: /* cmpgt */
-- value = 1281; /* --> cmpgt. */
-- break;
-- case 1976: /* cmplo */
-- case 1283: /* cmphi */
-- value = 1283; /* --> cmphi. */
-- break;
-- case 1977: /* cmpls */
-- case 1286: /* cmphs */
-- value = 1286; /* --> cmphs. */
-- break;
-- case 1220: /* mov */
-- case 1308: /* cpy */
-- value = 1308; /* --> cpy. */
-- break;
-- case 1222: /* mov */
-- case 1309: /* cpy */
-- value = 1309; /* --> cpy. */
-- break;
-- case 1985: /* fmov */
-- case 1225: /* mov */
-- case 1310: /* cpy */
-- value = 1310; /* --> cpy. */
-- break;
-- case 1215: /* mov */
-- case 1322: /* dup */
-- value = 1322; /* --> dup. */
-- break;
-- case 1217: /* mov */
-- case 1214: /* mov */
-- case 1323: /* dup */
-- value = 1323; /* --> dup. */
-- break;
-- case 1984: /* fmov */
-- case 1219: /* mov */
-- case 1324: /* dup */
-- value = 1324; /* --> dup. */
-- break;
-- case 1218: /* mov */
-- case 1325: /* dupm */
-- value = 1325; /* --> dupm. */
-- break;
-- case 1979: /* eon */
-- case 1327: /* eor */
-- value = 1327; /* --> eor. */
-- break;
-- case 1228: /* not */
-- case 1329: /* eor */
-- value = 1329; /* --> eor. */
-- break;
-- case 1229: /* nots */
-- case 1330: /* eors */
-- value = 1330; /* --> eors. */
-- break;
-- case 1980: /* facle */
-- case 1335: /* facge */
-- value = 1335; /* --> facge. */
-- break;
-- case 1981: /* faclt */
-- case 1336: /* facgt */
-- value = 1336; /* --> facgt. */
-- break;
-- case 1982: /* fcmle */
-- case 1349: /* fcmge */
-- value = 1349; /* --> fcmge. */
-- break;
-- case 1983: /* fcmlt */
-- case 1351: /* fcmgt */
-- value = 1351; /* --> fcmgt. */
-- break;
-- case 1212: /* fmov */
-- case 1357: /* fcpy */
-- value = 1357; /* --> fcpy. */
-- break;
-- case 1211: /* fmov */
-- case 1380: /* fdup */
-- value = 1380; /* --> fdup. */
-- break;
-- case 1213: /* mov */
-- case 1695: /* orr */
-- value = 1695; /* --> orr. */
-- break;
-- case 1986: /* orn */
-- case 1696: /* orr */
-- value = 1696; /* --> orr. */
-- break;
-- case 1216: /* mov */
-- case 1698: /* orr */
-- value = 1698; /* --> orr. */
-- break;
-- case 1226: /* movs */
-- case 1699: /* orrs */
-- value = 1699; /* --> orrs. */
-- break;
-- case 1221: /* mov */
-- case 1761: /* sel */
-- value = 1761; /* --> sel. */
-- break;
-- case 1224: /* mov */
-- case 1762: /* sel */
-- value = 1762; /* --> sel. */
-+ case 157: /* mov */
-+ case 156: /* ins */
-+ value = 156; /* --> ins. */
-+ break;
-+ case 243: /* mvn */
-+ case 242: /* not */
-+ value = 242; /* --> not. */
-+ break;
-+ case 318: /* mov */
-+ case 317: /* orr */
-+ value = 317; /* --> orr. */
-+ break;
-+ case 389: /* sxtl */
-+ case 388: /* sshll */
-+ value = 388; /* --> sshll. */
-+ break;
-+ case 391: /* sxtl2 */
-+ case 390: /* sshll2 */
-+ value = 390; /* --> sshll2. */
-+ break;
-+ case 413: /* uxtl */
-+ case 412: /* ushll */
-+ value = 412; /* --> ushll. */
-+ break;
-+ case 415: /* uxtl2 */
-+ case 414: /* ushll2 */
-+ value = 414; /* --> ushll2. */
-+ break;
-+ case 536: /* mov */
-+ case 535: /* dup */
-+ value = 535; /* --> dup. */
-+ break;
-+ case 623: /* sxtw */
-+ case 622: /* sxth */
-+ case 621: /* sxtb */
-+ case 624: /* asr */
-+ case 620: /* sbfx */
-+ case 619: /* sbfiz */
-+ case 618: /* sbfm */
-+ value = 618; /* --> sbfm. */
-+ break;
-+ case 627: /* bfc */
-+ case 628: /* bfxil */
-+ case 626: /* bfi */
-+ case 625: /* bfm */
-+ value = 625; /* --> bfm. */
-+ break;
-+ case 633: /* uxth */
-+ case 632: /* uxtb */
-+ case 635: /* lsr */
-+ case 634: /* lsl */
-+ case 631: /* ubfx */
-+ case 630: /* ubfiz */
-+ case 629: /* ubfm */
-+ value = 629; /* --> ubfm. */
-+ break;
-+ case 665: /* cset */
-+ case 664: /* cinc */
-+ case 663: /* csinc */
-+ value = 663; /* --> csinc. */
-+ break;
-+ case 668: /* csetm */
-+ case 667: /* cinv */
-+ case 666: /* csinv */
-+ value = 666; /* --> csinv. */
-+ break;
-+ case 670: /* cneg */
-+ case 669: /* csneg */
-+ value = 669; /* --> csneg. */
-+ break;
-+ case 688: /* rev */
-+ case 689: /* rev64 */
-+ value = 688; /* --> rev. */
-+ break;
-+ case 714: /* lsl */
-+ case 713: /* lslv */
-+ value = 713; /* --> lslv. */
-+ break;
-+ case 716: /* lsr */
-+ case 715: /* lsrv */
-+ value = 715; /* --> lsrv. */
-+ break;
-+ case 718: /* asr */
-+ case 717: /* asrv */
-+ value = 717; /* --> asrv. */
-+ break;
-+ case 720: /* ror */
-+ case 719: /* rorv */
-+ value = 719; /* --> rorv. */
-+ break;
-+ case 723: /* cmpp */
-+ case 722: /* subps */
-+ value = 722; /* --> subps. */
-+ break;
-+ case 736: /* mul */
-+ case 735: /* madd */
-+ value = 735; /* --> madd. */
-+ break;
-+ case 738: /* mneg */
-+ case 737: /* msub */
-+ value = 737; /* --> msub. */
-+ break;
-+ case 740: /* smull */
-+ case 739: /* smaddl */
-+ value = 739; /* --> smaddl. */
-+ break;
-+ case 742: /* smnegl */
-+ case 741: /* smsubl */
-+ value = 741; /* --> smsubl. */
-+ break;
-+ case 745: /* umull */
-+ case 744: /* umaddl */
-+ value = 744; /* --> umaddl. */
-+ break;
-+ case 747: /* umnegl */
-+ case 746: /* umsubl */
-+ value = 746; /* --> umsubl. */
-+ break;
-+ case 759: /* ror */
-+ case 758: /* extr */
-+ value = 758; /* --> extr. */
-+ break;
-+ case 996: /* bic */
-+ case 995: /* and */
-+ value = 995; /* --> and. */
-+ break;
-+ case 998: /* mov */
-+ case 997: /* orr */
-+ value = 997; /* --> orr. */
-+ break;
-+ case 1001: /* tst */
-+ case 1000: /* ands */
-+ value = 1000; /* --> ands. */
-+ break;
-+ case 1006: /* uxtw */
-+ case 1005: /* mov */
-+ case 1004: /* orr */
-+ value = 1004; /* --> orr. */
-+ break;
-+ case 1008: /* mvn */
-+ case 1007: /* orn */
-+ value = 1007; /* --> orn. */
-+ break;
-+ case 1012: /* tst */
-+ case 1011: /* ands */
-+ value = 1011; /* --> ands. */
-+ break;
-+ case 1138: /* staddb */
-+ case 1042: /* ldaddb */
-+ value = 1042; /* --> ldaddb. */
-+ break;
-+ case 1139: /* staddh */
-+ case 1043: /* ldaddh */
-+ value = 1043; /* --> ldaddh. */
-+ break;
-+ case 1140: /* stadd */
-+ case 1044: /* ldadd */
-+ value = 1044; /* --> ldadd. */
-+ break;
-+ case 1141: /* staddlb */
-+ case 1046: /* ldaddlb */
-+ value = 1046; /* --> ldaddlb. */
-+ break;
-+ case 1142: /* staddlh */
-+ case 1049: /* ldaddlh */
-+ value = 1049; /* --> ldaddlh. */
-+ break;
-+ case 1143: /* staddl */
-+ case 1052: /* ldaddl */
-+ value = 1052; /* --> ldaddl. */
-+ break;
-+ case 1144: /* stclrb */
-+ case 1054: /* ldclrb */
-+ value = 1054; /* --> ldclrb. */
-+ break;
-+ case 1145: /* stclrh */
-+ case 1055: /* ldclrh */
-+ value = 1055; /* --> ldclrh. */
-+ break;
-+ case 1146: /* stclr */
-+ case 1056: /* ldclr */
-+ value = 1056; /* --> ldclr. */
-+ break;
-+ case 1147: /* stclrlb */
-+ case 1058: /* ldclrlb */
-+ value = 1058; /* --> ldclrlb. */
-+ break;
-+ case 1148: /* stclrlh */
-+ case 1061: /* ldclrlh */
-+ value = 1061; /* --> ldclrlh. */
-+ break;
-+ case 1149: /* stclrl */
-+ case 1064: /* ldclrl */
-+ value = 1064; /* --> ldclrl. */
-+ break;
-+ case 1150: /* steorb */
-+ case 1066: /* ldeorb */
-+ value = 1066; /* --> ldeorb. */
-+ break;
-+ case 1151: /* steorh */
-+ case 1067: /* ldeorh */
-+ value = 1067; /* --> ldeorh. */
-+ break;
-+ case 1152: /* steor */
-+ case 1068: /* ldeor */
-+ value = 1068; /* --> ldeor. */
-+ break;
-+ case 1153: /* steorlb */
-+ case 1070: /* ldeorlb */
-+ value = 1070; /* --> ldeorlb. */
-+ break;
-+ case 1154: /* steorlh */
-+ case 1073: /* ldeorlh */
-+ value = 1073; /* --> ldeorlh. */
-+ break;
-+ case 1155: /* steorl */
-+ case 1076: /* ldeorl */
-+ value = 1076; /* --> ldeorl. */
-+ break;
-+ case 1156: /* stsetb */
-+ case 1078: /* ldsetb */
-+ value = 1078; /* --> ldsetb. */
-+ break;
-+ case 1157: /* stseth */
-+ case 1079: /* ldseth */
-+ value = 1079; /* --> ldseth. */
-+ break;
-+ case 1158: /* stset */
-+ case 1080: /* ldset */
-+ value = 1080; /* --> ldset. */
-+ break;
-+ case 1159: /* stsetlb */
-+ case 1082: /* ldsetlb */
-+ value = 1082; /* --> ldsetlb. */
-+ break;
-+ case 1160: /* stsetlh */
-+ case 1085: /* ldsetlh */
-+ value = 1085; /* --> ldsetlh. */
-+ break;
-+ case 1161: /* stsetl */
-+ case 1088: /* ldsetl */
-+ value = 1088; /* --> ldsetl. */
-+ break;
-+ case 1162: /* stsmaxb */
-+ case 1090: /* ldsmaxb */
-+ value = 1090; /* --> ldsmaxb. */
-+ break;
-+ case 1163: /* stsmaxh */
-+ case 1091: /* ldsmaxh */
-+ value = 1091; /* --> ldsmaxh. */
-+ break;
-+ case 1164: /* stsmax */
-+ case 1092: /* ldsmax */
-+ value = 1092; /* --> ldsmax. */
-+ break;
-+ case 1165: /* stsmaxlb */
-+ case 1094: /* ldsmaxlb */
-+ value = 1094; /* --> ldsmaxlb. */
-+ break;
-+ case 1166: /* stsmaxlh */
-+ case 1097: /* ldsmaxlh */
-+ value = 1097; /* --> ldsmaxlh. */
-+ break;
-+ case 1167: /* stsmaxl */
-+ case 1100: /* ldsmaxl */
-+ value = 1100; /* --> ldsmaxl. */
-+ break;
-+ case 1168: /* stsminb */
-+ case 1102: /* ldsminb */
-+ value = 1102; /* --> ldsminb. */
-+ break;
-+ case 1169: /* stsminh */
-+ case 1103: /* ldsminh */
-+ value = 1103; /* --> ldsminh. */
-+ break;
-+ case 1170: /* stsmin */
-+ case 1104: /* ldsmin */
-+ value = 1104; /* --> ldsmin. */
-+ break;
-+ case 1171: /* stsminlb */
-+ case 1106: /* ldsminlb */
-+ value = 1106; /* --> ldsminlb. */
-+ break;
-+ case 1172: /* stsminlh */
-+ case 1109: /* ldsminlh */
-+ value = 1109; /* --> ldsminlh. */
-+ break;
-+ case 1173: /* stsminl */
-+ case 1112: /* ldsminl */
-+ value = 1112; /* --> ldsminl. */
-+ break;
-+ case 1174: /* stumaxb */
-+ case 1114: /* ldumaxb */
-+ value = 1114; /* --> ldumaxb. */
-+ break;
-+ case 1175: /* stumaxh */
-+ case 1115: /* ldumaxh */
-+ value = 1115; /* --> ldumaxh. */
-+ break;
-+ case 1176: /* stumax */
-+ case 1116: /* ldumax */
-+ value = 1116; /* --> ldumax. */
-+ break;
-+ case 1177: /* stumaxlb */
-+ case 1118: /* ldumaxlb */
-+ value = 1118; /* --> ldumaxlb. */
-+ break;
-+ case 1178: /* stumaxlh */
-+ case 1121: /* ldumaxlh */
-+ value = 1121; /* --> ldumaxlh. */
-+ break;
-+ case 1179: /* stumaxl */
-+ case 1124: /* ldumaxl */
-+ value = 1124; /* --> ldumaxl. */
-+ break;
-+ case 1180: /* stuminb */
-+ case 1126: /* lduminb */
-+ value = 1126; /* --> lduminb. */
-+ break;
-+ case 1181: /* stuminh */
-+ case 1127: /* lduminh */
-+ value = 1127; /* --> lduminh. */
-+ break;
-+ case 1182: /* stumin */
-+ case 1128: /* ldumin */
-+ value = 1128; /* --> ldumin. */
-+ break;
-+ case 1183: /* stuminlb */
-+ case 1130: /* lduminlb */
-+ value = 1130; /* --> lduminlb. */
-+ break;
-+ case 1184: /* stuminlh */
-+ case 1133: /* lduminlh */
-+ value = 1133; /* --> lduminlh. */
-+ break;
-+ case 1185: /* stuminl */
-+ case 1136: /* lduminl */
-+ value = 1136; /* --> lduminl. */
-+ break;
-+ case 1187: /* mov */
-+ case 1186: /* movn */
-+ value = 1186; /* --> movn. */
-+ break;
-+ case 1189: /* mov */
-+ case 1188: /* movz */
-+ value = 1188; /* --> movz. */
-+ break;
-+ case 1246: /* autibsp */
-+ case 1245: /* autibz */
-+ case 1244: /* autiasp */
-+ case 1243: /* autiaz */
-+ case 1242: /* pacibsp */
-+ case 1241: /* pacibz */
-+ case 1240: /* paciasp */
-+ case 1239: /* paciaz */
-+ case 1215: /* tsb */
-+ case 1214: /* psb */
-+ case 1213: /* esb */
-+ case 1212: /* autib1716 */
-+ case 1211: /* autia1716 */
-+ case 1210: /* pacib1716 */
-+ case 1209: /* pacia1716 */
-+ case 1208: /* xpaclri */
-+ case 1206: /* sevl */
-+ case 1205: /* sev */
-+ case 1204: /* wfi */
-+ case 1203: /* wfe */
-+ case 1202: /* yield */
-+ case 1201: /* bti */
-+ case 1200: /* csdb */
-+ case 1199: /* nop */
-+ case 1198: /* hint */
-+ value = 1198; /* --> hint. */
-+ break;
-+ case 1221: /* pssbb */
-+ case 1220: /* ssbb */
-+ case 1219: /* dfb */
-+ case 1217: /* dsb */
-+ value = 1217; /* --> dsb. */
-+ break;
-+ case 1218: /* dsb */
-+ value = 1218; /* --> dsb. */
-+ break;
-+ case 1234: /* cpp */
-+ case 1233: /* dvp */
-+ case 1232: /* cfp */
-+ case 1229: /* tlbi */
-+ case 1228: /* ic */
-+ case 1227: /* dc */
-+ case 1226: /* at */
-+ case 1225: /* sys */
-+ value = 1225; /* --> sys. */
-+ break;
-+ case 1230: /* wfet */
-+ value = 1230; /* --> wfet. */
-+ break;
-+ case 1231: /* wfit */
-+ value = 1231; /* --> wfit. */
-+ break;
-+ case 2044: /* bic */
-+ case 1294: /* and */
-+ value = 1294; /* --> and. */
-+ break;
-+ case 1277: /* mov */
-+ case 1296: /* and */
-+ value = 1296; /* --> and. */
-+ break;
-+ case 1281: /* movs */
-+ case 1297: /* ands */
-+ value = 1297; /* --> ands. */
-+ break;
-+ case 2045: /* cmple */
-+ case 1332: /* cmpge */
-+ value = 1332; /* --> cmpge. */
-+ break;
-+ case 2048: /* cmplt */
-+ case 1335: /* cmpgt */
-+ value = 1335; /* --> cmpgt. */
-+ break;
-+ case 2046: /* cmplo */
-+ case 1337: /* cmphi */
-+ value = 1337; /* --> cmphi. */
-+ break;
-+ case 2047: /* cmpls */
-+ case 1340: /* cmphs */
-+ value = 1340; /* --> cmphs. */
-+ break;
-+ case 1274: /* mov */
-+ case 1362: /* cpy */
-+ value = 1362; /* --> cpy. */
-+ break;
-+ case 1276: /* mov */
-+ case 1363: /* cpy */
-+ value = 1363; /* --> cpy. */
-+ break;
-+ case 2055: /* fmov */
-+ case 1279: /* mov */
-+ case 1364: /* cpy */
-+ value = 1364; /* --> cpy. */
-+ break;
-+ case 1269: /* mov */
-+ case 1376: /* dup */
-+ value = 1376; /* --> dup. */
-+ break;
-+ case 1271: /* mov */
-+ case 1268: /* mov */
-+ case 1377: /* dup */
-+ value = 1377; /* --> dup. */
-+ break;
-+ case 2054: /* fmov */
-+ case 1273: /* mov */
-+ case 1378: /* dup */
-+ value = 1378; /* --> dup. */
-+ break;
-+ case 1272: /* mov */
-+ case 1379: /* dupm */
-+ value = 1379; /* --> dupm. */
-+ break;
-+ case 2049: /* eon */
-+ case 1381: /* eor */
-+ value = 1381; /* --> eor. */
-+ break;
-+ case 1282: /* not */
-+ case 1383: /* eor */
-+ value = 1383; /* --> eor. */
-+ break;
-+ case 1283: /* nots */
-+ case 1384: /* eors */
-+ value = 1384; /* --> eors. */
-+ break;
-+ case 2050: /* facle */
-+ case 1389: /* facge */
-+ value = 1389; /* --> facge. */
-+ break;
-+ case 2051: /* faclt */
-+ case 1390: /* facgt */
-+ value = 1390; /* --> facgt. */
-+ break;
-+ case 2052: /* fcmle */
-+ case 1403: /* fcmge */
-+ value = 1403; /* --> fcmge. */
-+ break;
-+ case 2053: /* fcmlt */
-+ case 1405: /* fcmgt */
-+ value = 1405; /* --> fcmgt. */
-+ break;
-+ case 1266: /* fmov */
-+ case 1411: /* fcpy */
-+ value = 1411; /* --> fcpy. */
-+ break;
-+ case 1265: /* fmov */
-+ case 1434: /* fdup */
-+ value = 1434; /* --> fdup. */
-+ break;
-+ case 1267: /* mov */
-+ case 1765: /* orr */
-+ value = 1765; /* --> orr. */
-+ break;
-+ case 2056: /* orn */
-+ case 1766: /* orr */
-+ value = 1766; /* --> orr. */
-+ break;
-+ case 1270: /* mov */
-+ case 1768: /* orr */
-+ value = 1768; /* --> orr. */
-+ break;
-+ case 1280: /* movs */
-+ case 1769: /* orrs */
-+ value = 1769; /* --> orrs. */
-+ break;
-+ case 1275: /* mov */
-+ case 1831: /* sel */
-+ value = 1831; /* --> sel. */
-+ break;
-+ case 1278: /* mov */
-+ case 1832: /* sel */
-+ value = 1832; /* --> sel. */
- break;
- default: return NULL;
- }
-@@ -579,10 +603,11 @@ aarch64_find_real_opcode (const aarch64_
- return aarch64_opcode_table + value;
- }
-
--const char*
-+bfd_boolean
- aarch64_insert_operand (const aarch64_operand *self,
- const aarch64_opnd_info *info,
-- aarch64_insn *code, const aarch64_inst *inst)
-+ aarch64_insn *code, const aarch64_inst *inst,
-+ aarch64_operand_error *errors)
- {
- /* Use the index as the key. */
- int key = self - aarch64_operands;
-@@ -599,12 +624,12 @@ aarch64_insert_operand (const aarch64_op
- case 9:
- case 10:
- case 11:
-- case 15:
-- case 16:
-+ case 12:
-+ case 13:
- case 17:
- case 18:
-+ case 19:
- case 20:
-- case 21:
- case 22:
- case 23:
- case 24:
-@@ -613,54 +638,54 @@ aarch64_insert_operand (const aarch64_op
- case 27:
- case 28:
- case 29:
-- case 151:
-- case 152:
-- case 153:
-- case 154:
-- case 155:
-- case 156:
-- case 157:
-- case 158:
-- case 159:
-- case 160:
-+ case 30:
-+ case 31:
-+ case 166:
-+ case 167:
-+ case 168:
-+ case 169:
-+ case 170:
-+ case 171:
-+ case 172:
- case 173:
- case 174:
- case 175:
-- case 176:
-- case 177:
-- case 178:
-- case 179:
-- case 180:
-- case 181:
-- case 185:
-- case 188:
-- return aarch64_ins_regno (self, info, code, inst);
-- case 13:
-- return aarch64_ins_reg_extended (self, info, code, inst);
-- case 14:
-- return aarch64_ins_reg_shifted (self, info, code, inst);
-- case 19:
-- return aarch64_ins_ft (self, info, code, inst);
-- case 30:
-- case 31:
-- case 32:
- case 190:
-- return aarch64_ins_reglane (self, info, code, inst);
-+ case 191:
-+ case 192:
-+ case 193:
-+ case 194:
-+ case 195:
-+ case 196:
-+ case 197:
-+ case 198:
-+ case 204:
-+ case 207:
-+ return aarch64_ins_regno (self, info, code, inst, errors);
-+ case 15:
-+ return aarch64_ins_reg_extended (self, info, code, inst, errors);
-+ case 16:
-+ return aarch64_ins_reg_shifted (self, info, code, inst, errors);
-+ case 21:
-+ return aarch64_ins_ft (self, info, code, inst, errors);
-+ case 32:
- case 33:
-- return aarch64_ins_reglist (self, info, code, inst);
- case 34:
-- return aarch64_ins_ldst_reglist (self, info, code, inst);
- case 35:
-- return aarch64_ins_ldst_reglist_r (self, info, code, inst);
-+ case 210:
-+ return aarch64_ins_reglane (self, info, code, inst, errors);
- case 36:
-- return aarch64_ins_ldst_elemlist (self, info, code, inst);
-+ return aarch64_ins_reglist (self, info, code, inst, errors);
- case 37:
-+ return aarch64_ins_ldst_reglist (self, info, code, inst, errors);
- case 38:
-+ return aarch64_ins_ldst_reglist_r (self, info, code, inst, errors);
- case 39:
-+ return aarch64_ins_ldst_elemlist (self, info, code, inst, errors);
- case 40:
-- case 50:
-- case 51:
-- case 52:
-+ case 41:
-+ case 42:
-+ case 43:
- case 53:
- case 54:
- case 55:
-@@ -672,112 +697,115 @@ aarch64_insert_operand (const aarch64_op
- case 61:
- case 62:
- case 63:
-- case 75:
-- case 76:
-- case 77:
-- case 78:
-- case 148:
-- case 150:
-- case 165:
-- case 166:
-- case 167:
-- case 168:
-- case 169:
-- case 170:
-- case 171:
-- case 172:
-- return aarch64_ins_imm (self, info, code, inst);
-- case 41:
-- case 42:
-- return aarch64_ins_advsimd_imm_shift (self, info, code, inst);
-- case 43:
-- case 44:
-- case 45:
-- return aarch64_ins_advsimd_imm_modified (self, info, code, inst);
-- case 49:
-- case 139:
-- return aarch64_ins_fpimm (self, info, code, inst);
- case 64:
-- case 146:
-- return aarch64_ins_limm (self, info, code, inst);
- case 65:
-- return aarch64_ins_aimm (self, info, code, inst);
- case 66:
-- return aarch64_ins_imm_half (self, info, code, inst);
- case 67:
-- return aarch64_ins_fbits (self, info, code, inst);
-+ case 68:
- case 69:
-+ case 81:
-+ case 82:
-+ case 83:
-+ case 84:
-+ case 163:
-+ case 165:
-+ case 182:
-+ case 183:
-+ case 184:
-+ case 185:
-+ case 186:
-+ case 187:
-+ case 188:
-+ case 189:
-+ case 209:
-+ return aarch64_ins_imm (self, info, code, inst, errors);
-+ case 44:
-+ case 45:
-+ return aarch64_ins_advsimd_imm_shift (self, info, code, inst, errors);
-+ case 46:
-+ case 47:
-+ case 48:
-+ return aarch64_ins_advsimd_imm_modified (self, info, code, inst, errors);
-+ case 52:
-+ case 153:
-+ return aarch64_ins_fpimm (self, info, code, inst, errors);
- case 70:
-- case 144:
-- return aarch64_ins_imm_rotate2 (self, info, code, inst);
-+ case 161:
-+ return aarch64_ins_limm (self, info, code, inst, errors);
- case 71:
-- case 143:
-- return aarch64_ins_imm_rotate1 (self, info, code, inst);
-+ return aarch64_ins_aimm (self, info, code, inst, errors);
- case 72:
-+ return aarch64_ins_imm_half (self, info, code, inst, errors);
- case 73:
-- return aarch64_ins_cond (self, info, code, inst);
-+ return aarch64_ins_fbits (self, info, code, inst, errors);
-+ case 75:
-+ case 76:
-+ case 158:
-+ return aarch64_ins_imm_rotate2 (self, info, code, inst, errors);
-+ case 77:
-+ case 157:
-+ case 159:
-+ return aarch64_ins_imm_rotate1 (self, info, code, inst, errors);
-+ case 78:
- case 79:
-- case 86:
-- return aarch64_ins_addr_simple (self, info, code, inst);
-- case 80:
-- return aarch64_ins_addr_regoff (self, info, code, inst);
-- case 81:
-- case 82:
-- case 83:
-- return aarch64_ins_addr_simm (self, info, code, inst);
-- case 84:
-- return aarch64_ins_addr_simm10 (self, info, code, inst);
-+ return aarch64_ins_cond (self, info, code, inst, errors);
- case 85:
-- return aarch64_ins_addr_uimm12 (self, info, code, inst);
-+ case 94:
-+ return aarch64_ins_addr_simple (self, info, code, inst, errors);
-+ case 86:
-+ return aarch64_ins_addr_regoff (self, info, code, inst, errors);
- case 87:
-- return aarch64_ins_addr_offset (self, info, code, inst);
- case 88:
-- return aarch64_ins_simd_addr_post (self, info, code, inst);
- case 89:
-- return aarch64_ins_sysreg (self, info, code, inst);
-- case 90:
-- return aarch64_ins_pstatefield (self, info, code, inst);
- case 91:
-- case 92:
- case 93:
-- case 94:
-- return aarch64_ins_sysins_op (self, info, code, inst);
-+ return aarch64_ins_addr_simm (self, info, code, inst, errors);
-+ case 90:
-+ return aarch64_ins_addr_simm10 (self, info, code, inst, errors);
-+ case 92:
-+ return aarch64_ins_addr_uimm12 (self, info, code, inst, errors);
- case 95:
-+ return aarch64_ins_addr_offset (self, info, code, inst, errors);
- case 96:
-- return aarch64_ins_barrier (self, info, code, inst);
-+ return aarch64_ins_simd_addr_post (self, info, code, inst, errors);
- case 97:
-- return aarch64_ins_prfop (self, info, code, inst);
-+ return aarch64_ins_sysreg (self, info, code, inst, errors);
- case 98:
-- return aarch64_ins_hint (self, info, code, inst);
-+ return aarch64_ins_pstatefield (self, info, code, inst, errors);
- case 99:
-- return aarch64_ins_sve_addr_ri_s4 (self, info, code, inst);
- case 100:
- case 101:
- case 102:
- case 103:
-- return aarch64_ins_sve_addr_ri_s4xvl (self, info, code, inst);
-+ return aarch64_ins_sysins_op (self, info, code, inst, errors);
- case 104:
-- return aarch64_ins_sve_addr_ri_s6xvl (self, info, code, inst);
-- case 105:
-- return aarch64_ins_sve_addr_ri_s9xvl (self, info, code, inst);
- case 106:
-+ return aarch64_ins_barrier (self, info, code, inst, errors);
-+ case 105:
-+ return aarch64_ins_barrier_dsb_nxs (self, info, code, inst, errors);
- case 107:
-+ return aarch64_ins_prfop (self, info, code, inst, errors);
- case 108:
-+ return aarch64_ins_none (self, info, code, inst, errors);
- case 109:
-- return aarch64_ins_sve_addr_ri_u6 (self, info, code, inst);
-+ return aarch64_ins_hint (self, info, code, inst, errors);
- case 110:
- case 111:
-+ return aarch64_ins_sve_addr_ri_s4 (self, info, code, inst, errors);
- case 112:
- case 113:
- case 114:
- case 115:
-+ return aarch64_ins_sve_addr_ri_s4xvl (self, info, code, inst, errors);
- case 116:
-+ return aarch64_ins_sve_addr_ri_s6xvl (self, info, code, inst, errors);
- case 117:
-+ return aarch64_ins_sve_addr_ri_s9xvl (self, info, code, inst, errors);
- case 118:
- case 119:
- case 120:
- case 121:
-- return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst);
-+ return aarch64_ins_sve_addr_ri_u6 (self, info, code, inst, errors);
- case 122:
- case 123:
- case 124:
-@@ -786,49 +814,68 @@ aarch64_insert_operand (const aarch64_op
- case 127:
- case 128:
- case 129:
-- return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst);
- case 130:
- case 131:
- case 132:
- case 133:
-- return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst);
- case 134:
-- return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst);
- case 135:
-- return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst);
-+ return aarch64_ins_sve_addr_rr_lsl (self, info, code, inst, errors);
- case 136:
-- return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst);
- case 137:
-- return aarch64_ins_sve_aimm (self, info, code, inst);
- case 138:
-- return aarch64_ins_sve_asimm (self, info, code, inst);
-+ case 139:
- case 140:
-- return aarch64_ins_sve_float_half_one (self, info, code, inst);
- case 141:
-- return aarch64_ins_sve_float_half_two (self, info, code, inst);
- case 142:
-- return aarch64_ins_sve_float_zero_one (self, info, code, inst);
-+ case 143:
-+ return aarch64_ins_sve_addr_rz_xtw (self, info, code, inst, errors);
-+ case 144:
- case 145:
-- return aarch64_ins_inv_limm (self, info, code, inst);
-+ case 146:
- case 147:
-- return aarch64_ins_sve_limm_mov (self, info, code, inst);
-+ return aarch64_ins_sve_addr_zi_u5 (self, info, code, inst, errors);
-+ case 148:
-+ return aarch64_ins_sve_addr_zz_lsl (self, info, code, inst, errors);
- case 149:
-- return aarch64_ins_sve_scale (self, info, code, inst);
-- case 161:
-+ return aarch64_ins_sve_addr_zz_sxtw (self, info, code, inst, errors);
-+ case 150:
-+ return aarch64_ins_sve_addr_zz_uxtw (self, info, code, inst, errors);
-+ case 151:
-+ return aarch64_ins_sve_aimm (self, info, code, inst, errors);
-+ case 152:
-+ return aarch64_ins_sve_asimm (self, info, code, inst, errors);
-+ case 154:
-+ return aarch64_ins_sve_float_half_one (self, info, code, inst, errors);
-+ case 155:
-+ return aarch64_ins_sve_float_half_two (self, info, code, inst, errors);
-+ case 156:
-+ return aarch64_ins_sve_float_zero_one (self, info, code, inst, errors);
-+ case 160:
-+ return aarch64_ins_inv_limm (self, info, code, inst, errors);
- case 162:
-- return aarch64_ins_sve_shlimm (self, info, code, inst);
-- case 163:
-+ return aarch64_ins_sve_limm_mov (self, info, code, inst, errors);
- case 164:
-- return aarch64_ins_sve_shrimm (self, info, code, inst);
-- case 182:
-- case 183:
-- case 184:
-- return aarch64_ins_sve_quad_index (self, info, code, inst);
-- case 186:
-- return aarch64_ins_sve_index (self, info, code, inst);
-- case 187:
-- case 189:
-- return aarch64_ins_sve_reglist (self, info, code, inst);
-+ return aarch64_ins_sve_scale (self, info, code, inst, errors);
-+ case 176:
-+ case 177:
-+ case 178:
-+ return aarch64_ins_sve_shlimm (self, info, code, inst, errors);
-+ case 179:
-+ case 180:
-+ case 181:
-+ return aarch64_ins_sve_shrimm (self, info, code, inst, errors);
-+ case 199:
-+ case 200:
-+ case 201:
-+ case 202:
-+ case 203:
-+ return aarch64_ins_sve_quad_index (self, info, code, inst, errors);
-+ case 205:
-+ return aarch64_ins_sve_index (self, info, code, inst, errors);
-+ case 206:
-+ case 208:
-+ return aarch64_ins_sve_reglist (self, info, code, inst, errors);
- default: assert (0); abort ();
- }
- }
-diff -rup binutils-2.30/opcodes/aarch64-asm.c binutils-2.30.new/opcodes/aarch64-asm.c
---- binutils-2.30/opcodes/aarch64-asm.c 2018-01-13 13:31:16.000000000 +0000
-+++ binutils-2.30.new/opcodes/aarch64-asm.c 2021-03-23 16:19:53.184776189 +0000
-@@ -1,5 +1,5 @@
- /* aarch64-asm.c -- AArch64 assembler support.
-- Copyright (C) 2012-2018 Free Software Foundation, Inc.
-+ Copyright (C) 2012-2021 Free Software Foundation, Inc.
- Contributed by ARM Ltd.
-
- This file is part of the GNU opcodes library.
-@@ -22,6 +22,7 @@
- #include <stdarg.h>
- #include "libiberty.h"
- #include "aarch64-asm.h"
-+#include "opintl.h"
-
- /* Utilities. */
-
-@@ -77,22 +78,35 @@ insert_all_fields (const aarch64_operand
-
- /* Operand inserters. */
-
-+/* Insert nothing. */
-+bfd_boolean
-+aarch64_ins_none (const aarch64_operand *self ATTRIBUTE_UNUSED,
-+ const aarch64_opnd_info *info ATTRIBUTE_UNUSED,
-+ aarch64_insn *code ATTRIBUTE_UNUSED,
-+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
-+{
-+ return TRUE;
-+}
-+
- /* Insert register number. */
--const char *
-+bfd_boolean
- aarch64_ins_regno (const aarch64_operand *self, const aarch64_opnd_info *info,
- aarch64_insn *code,
-- const aarch64_inst *inst ATTRIBUTE_UNUSED)
-+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- insert_field (self->fields[0], code, info->reg.regno, 0);
-- return NULL;
-+ return TRUE;
- }
-
- /* Insert register number, index and/or other data for SIMD register element
- operand, e.g. the last source operand in
- SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]. */
--const char *
-+bfd_boolean
- aarch64_ins_reglane (const aarch64_operand *self, const aarch64_opnd_info *info,
-- aarch64_insn *code, const aarch64_inst *inst)
-+ aarch64_insn *code, const aarch64_inst *inst,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- /* regno */
- insert_field (self->fields[0], code, info->reglane.regno, inst->opcode->mask);
-@@ -127,6 +141,7 @@ aarch64_ins_reglane (const aarch64_opera
- switch (info->qualifier)
- {
- case AARCH64_OPND_QLF_S_4B:
-+ case AARCH64_OPND_QLF_S_2H:
- /* L:H */
- assert (reglane_index < 4);
- insert_fields (code, reglane_index, 0, 2, FLD_L, FLD_H);
-@@ -173,28 +188,30 @@ aarch64_ins_reglane (const aarch64_opera
- assert (0);
- }
- }
-- return NULL;
-+ return TRUE;
- }
-
- /* Insert regno and len field of a register list operand, e.g. Vn in TBL. */
--const char *
-+bfd_boolean
- aarch64_ins_reglist (const aarch64_operand *self, const aarch64_opnd_info *info,
- aarch64_insn *code,
-- const aarch64_inst *inst ATTRIBUTE_UNUSED)
-+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- /* R */
- insert_field (self->fields[0], code, info->reglist.first_regno, 0);
- /* len */
- insert_field (FLD_len, code, info->reglist.num_regs - 1, 0);
-- return NULL;
-+ return TRUE;
- }
-
- /* Insert Rt and opcode fields for a register list operand, e.g. Vt
- in AdvSIMD load/store instructions. */
--const char *
-+bfd_boolean
- aarch64_ins_ldst_reglist (const aarch64_operand *self ATTRIBUTE_UNUSED,
- const aarch64_opnd_info *info, aarch64_insn *code,
-- const aarch64_inst *inst)
-+ const aarch64_inst *inst,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- aarch64_insn value = 0;
- /* Number of elements in each structure to be loaded/stored. */
-@@ -229,15 +246,16 @@ aarch64_ins_ldst_reglist (const aarch64_
- }
- insert_field (FLD_opcode, code, value, 0);
-
-- return NULL;
-+ return TRUE;
- }
-
- /* Insert Rt and S fields for a register list operand, e.g. Vt in AdvSIMD load
- single structure to all lanes instructions. */
--const char *
-+bfd_boolean
- aarch64_ins_ldst_reglist_r (const aarch64_operand *self ATTRIBUTE_UNUSED,
- const aarch64_opnd_info *info, aarch64_insn *code,
-- const aarch64_inst *inst)
-+ const aarch64_inst *inst,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- aarch64_insn value;
- /* The opcode dependent area stores the number of elements in
-@@ -254,15 +272,16 @@ aarch64_ins_ldst_reglist_r (const aarch6
- value = (aarch64_insn) 1;
- insert_field (FLD_S, code, value, 0);
-
-- return NULL;
-+ return TRUE;
- }
-
- /* Insert Q, opcode<2:1>, S, size and Rt fields for a register element list
- operand e.g. Vt in AdvSIMD load/store single element instructions. */
--const char *
-+bfd_boolean
- aarch64_ins_ldst_elemlist (const aarch64_operand *self ATTRIBUTE_UNUSED,
- const aarch64_opnd_info *info, aarch64_insn *code,
-- const aarch64_inst *inst ATTRIBUTE_UNUSED)
-+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- aarch64_field field = {0, 0};
- aarch64_insn QSsize = 0; /* fields Q:S:size. */
-@@ -302,16 +321,17 @@ aarch64_ins_ldst_elemlist (const aarch64
- gen_sub_field (FLD_asisdlso_opcode, 1, 2, &field);
- insert_field_2 (&field, code, opcodeh2, 0);
-
-- return NULL;
-+ return TRUE;
- }
-
- /* Insert fields immh:immb and/or Q for e.g. the shift immediate in
- SSHR <Vd>.<T>, <Vn>.<T>, #<shift>
- or SSHR <V><d>, <V><n>, #<shift>. */
--const char *
-+bfd_boolean
- aarch64_ins_advsimd_imm_shift (const aarch64_operand *self ATTRIBUTE_UNUSED,
- const aarch64_opnd_info *info,
-- aarch64_insn *code, const aarch64_inst *inst)
-+ aarch64_insn *code, const aarch64_inst *inst,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- unsigned val = aarch64_get_qualifier_standard_value (info->qualifier);
- aarch64_insn Q, imm;
-@@ -357,45 +377,51 @@ aarch64_ins_advsimd_imm_shift (const aar
- imm = info->imm.value + (8 << (unsigned)val);
- insert_fields (code, imm, 0, 2, FLD_immb, FLD_immh);
-
-- return NULL;
-+ return TRUE;
- }
-
- /* Insert fields for e.g. the immediate operands in
- BFM <Wd>, <Wn>, #<immr>, #<imms>. */
--const char *
-+bfd_boolean
- aarch64_ins_imm (const aarch64_operand *self, const aarch64_opnd_info *info,
- aarch64_insn *code,
-- const aarch64_inst *inst ATTRIBUTE_UNUSED)
-+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- int64_t imm;
-
- imm = info->imm.value;
- if (operand_need_shift_by_two (self))
- imm >>= 2;
-+ if (operand_need_shift_by_four (self))
-+ imm >>= 4;
- insert_all_fields (self, code, imm);
-- return NULL;
-+ return TRUE;
- }
-
- /* Insert immediate and its shift amount for e.g. the last operand in
- MOVZ <Wd>, #<imm16>{, LSL #<shift>}. */
--const char *
-+bfd_boolean
- aarch64_ins_imm_half (const aarch64_operand *self, const aarch64_opnd_info *info,
-- aarch64_insn *code, const aarch64_inst *inst)
-+ aarch64_insn *code, const aarch64_inst *inst,
-+ aarch64_operand_error *errors)
- {
- /* imm16 */
-- aarch64_ins_imm (self, info, code, inst);
-+ aarch64_ins_imm (self, info, code, inst, errors);
- /* hw */
- insert_field (FLD_hw, code, info->shifter.amount >> 4, 0);
-- return NULL;
-+ return TRUE;
- }
-
- /* Insert cmode and "a:b:c:d:e:f:g:h" fields for e.g. the last operand in
- MOVI <Vd>.<T>, #<imm8> {, LSL #<amount>}. */
--const char *
-+bfd_boolean
- aarch64_ins_advsimd_imm_modified (const aarch64_operand *self ATTRIBUTE_UNUSED,
- const aarch64_opnd_info *info,
- aarch64_insn *code,
-- const aarch64_inst *inst ATTRIBUTE_UNUSED)
-+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors
-+ ATTRIBUTE_UNUSED)
- {
- enum aarch64_opnd_qualifier opnd0_qualifier = inst->operands[0].qualifier;
- uint64_t imm = info->imm.value;
-@@ -417,7 +443,7 @@ aarch64_ins_advsimd_imm_modified (const
- insert_fields (code, imm, 0, 2, FLD_defgh, FLD_abc);
-
- if (kind == AARCH64_MOD_NONE)
-- return NULL;
-+ return TRUE;
-
- /* shift amount partially in cmode */
- assert (kind == AARCH64_MOD_LSL || kind == AARCH64_MOD_MSL);
-@@ -429,7 +455,7 @@ aarch64_ins_advsimd_imm_modified (const
- /* For 8-bit move immediate, the optional LSL #0 does not require
- encoding. */
- if (esize == 1)
-- return NULL;
-+ return TRUE;
- amount >>= 3;
- if (esize == 4)
- gen_sub_field (FLD_cmode, 1, 2, &field); /* per word */
-@@ -444,120 +470,130 @@ aarch64_ins_advsimd_imm_modified (const
- }
- insert_field_2 (&field, code, amount, 0);
-
-- return NULL;
-+ return TRUE;
- }
-
- /* Insert fields for an 8-bit floating-point immediate. */
--const char *
-+bfd_boolean
- aarch64_ins_fpimm (const aarch64_operand *self, const aarch64_opnd_info *info,
- aarch64_insn *code,
-- const aarch64_inst *inst ATTRIBUTE_UNUSED)
-+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- insert_all_fields (self, code, info->imm.value);
-- return NULL;
-+ return TRUE;
- }
-
- /* Insert 1-bit rotation immediate (#90 or #270). */
--const char *
-+bfd_boolean
- aarch64_ins_imm_rotate1 (const aarch64_operand *self,
- const aarch64_opnd_info *info,
-- aarch64_insn *code, const aarch64_inst *inst)
-+ aarch64_insn *code, const aarch64_inst *inst,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- uint64_t rot = (info->imm.value - 90) / 180;
- assert (rot < 2U);
- insert_field (self->fields[0], code, rot, inst->opcode->mask);
-- return NULL;
-+ return TRUE;
- }
-
- /* Insert 2-bit rotation immediate (#0, #90, #180 or #270). */
--const char *
-+bfd_boolean
- aarch64_ins_imm_rotate2 (const aarch64_operand *self,
- const aarch64_opnd_info *info,
-- aarch64_insn *code, const aarch64_inst *inst)
-+ aarch64_insn *code, const aarch64_inst *inst,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- uint64_t rot = info->imm.value / 90;
- assert (rot < 4U);
- insert_field (self->fields[0], code, rot, inst->opcode->mask);
-- return NULL;
-+ return TRUE;
- }
-
- /* Insert #<fbits> for the immediate operand in fp fix-point instructions,
- e.g. SCVTF <Dd>, <Wn>, #<fbits>. */
--const char *
-+bfd_boolean
- aarch64_ins_fbits (const aarch64_operand *self, const aarch64_opnd_info *info,
- aarch64_insn *code,
-- const aarch64_inst *inst ATTRIBUTE_UNUSED)
-+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- insert_field (self->fields[0], code, 64 - info->imm.value, 0);
-- return NULL;
-+ return TRUE;
- }
-
- /* Insert arithmetic immediate for e.g. the last operand in
- SUBS <Wd>, <Wn|WSP>, #<imm> {, <shift>}. */
--const char *
-+bfd_boolean
- aarch64_ins_aimm (const aarch64_operand *self, const aarch64_opnd_info *info,
-- aarch64_insn *code, const aarch64_inst *inst ATTRIBUTE_UNUSED)
-+ aarch64_insn *code, const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- /* shift */
- aarch64_insn value = info->shifter.amount ? 1 : 0;
- insert_field (self->fields[0], code, value, 0);
- /* imm12 (unsigned) */
- insert_field (self->fields[1], code, info->imm.value, 0);
-- return NULL;
-+ return TRUE;
- }
-
- /* Common routine shared by aarch64_ins{,_inv}_limm. INVERT_P says whether
- the operand should be inverted before encoding. */
--static const char *
-+static bfd_boolean
- aarch64_ins_limm_1 (const aarch64_operand *self,
- const aarch64_opnd_info *info, aarch64_insn *code,
-- const aarch64_inst *inst, bfd_boolean invert_p)
-+ const aarch64_inst *inst, bfd_boolean invert_p,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
-+ bfd_boolean res;
- aarch64_insn value;
- uint64_t imm = info->imm.value;
- int esize = aarch64_get_qualifier_esize (inst->operands[0].qualifier);
-
- if (invert_p)
- imm = ~imm;
-- /* The constraint check should have guaranteed this wouldn't happen. */
-- assert (aarch64_logical_immediate_p (imm, esize, &value));
--
-- insert_fields (code, value, 0, 3, self->fields[2], self->fields[1],
-- self->fields[0]);
-- return NULL;
-+ /* The constraint check should guarantee that this will work. */
-+ res = aarch64_logical_immediate_p (imm, esize, &value);
-+ if (res)
-+ insert_fields (code, value, 0, 3, self->fields[2], self->fields[1],
-+ self->fields[0]);
-+ return res;
- }
-
- /* Insert logical/bitmask immediate for e.g. the last operand in
- ORR <Wd|WSP>, <Wn>, #<imm>. */
--const char *
-+bfd_boolean
- aarch64_ins_limm (const aarch64_operand *self, const aarch64_opnd_info *info,
-- aarch64_insn *code, const aarch64_inst *inst)
-+ aarch64_insn *code, const aarch64_inst *inst,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- return aarch64_ins_limm_1 (self, info, code, inst,
-- inst->opcode->op == OP_BIC);
-+ inst->opcode->op == OP_BIC, errors);
- }
-
- /* Insert a logical/bitmask immediate for the BIC alias of AND (etc.). */
--const char *
-+bfd_boolean
- aarch64_ins_inv_limm (const aarch64_operand *self,
- const aarch64_opnd_info *info, aarch64_insn *code,
-- const aarch64_inst *inst)
-+ const aarch64_inst *inst,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
-- return aarch64_ins_limm_1 (self, info, code, inst, TRUE);
-+ return aarch64_ins_limm_1 (self, info, code, inst, TRUE, errors);
- }
-
- /* Encode Ft for e.g. STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]
- or LDP <Qt1>, <Qt2>, [<Xn|SP>], #<imm>. */
--const char *
-+bfd_boolean
- aarch64_ins_ft (const aarch64_operand *self, const aarch64_opnd_info *info,
-- aarch64_insn *code, const aarch64_inst *inst)
-+ aarch64_insn *code, const aarch64_inst *inst,
-+ aarch64_operand_error *errors)
- {
- aarch64_insn value = 0;
-
- assert (info->idx == 0);
-
- /* Rt */
-- aarch64_ins_regno (self, info, code, inst);
-+ aarch64_ins_regno (self, info, code, inst, errors);
- if (inst->opcode->iclass == ldstpair_indexed
- || inst->opcode->iclass == ldstnapair_offs
- || inst->opcode->iclass == ldstpair_off
-@@ -580,26 +616,28 @@ aarch64_ins_ft (const aarch64_operand *s
- insert_fields (code, value, 0, 2, FLD_ldst_size, FLD_opc1);
- }
-
-- return NULL;
-+ return TRUE;
- }
-
- /* Encode the address operand for e.g. STXRB <Ws>, <Wt>, [<Xn|SP>{,#0}]. */
--const char *
-+bfd_boolean
- aarch64_ins_addr_simple (const aarch64_operand *self ATTRIBUTE_UNUSED,
- const aarch64_opnd_info *info, aarch64_insn *code,
-- const aarch64_inst *inst ATTRIBUTE_UNUSED)
-+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- /* Rn */
- insert_field (FLD_Rn, code, info->addr.base_regno, 0);
-- return NULL;
-+ return TRUE;
- }
-
- /* Encode the address operand for e.g.
- STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
--const char *
-+bfd_boolean
- aarch64_ins_addr_regoff (const aarch64_operand *self ATTRIBUTE_UNUSED,
- const aarch64_opnd_info *info, aarch64_insn *code,
-- const aarch64_inst *inst ATTRIBUTE_UNUSED)
-+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- aarch64_insn S;
- enum aarch64_modifier_kind kind = info->shifter.kind;
-@@ -624,15 +662,16 @@ aarch64_ins_addr_regoff (const aarch64_o
- S = info->shifter.operator_present && info->shifter.amount_present;
- insert_field (FLD_S, code, S, 0);
-
-- return NULL;
-+ return TRUE;
- }
-
- /* Encode the address operand for e.g.
- stlur <Xt>, [<Xn|SP>{, <amount>}]. */
--const char *
-+bfd_boolean
- aarch64_ins_addr_offset (const aarch64_operand *self ATTRIBUTE_UNUSED,
- const aarch64_opnd_info *info, aarch64_insn *code,
-- const aarch64_inst *inst ATTRIBUTE_UNUSED)
-+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- /* Rn */
- insert_field (self->fields[0], code, info->addr.base_regno, 0);
-@@ -647,15 +686,16 @@ aarch64_ins_addr_offset (const aarch64_o
- assert (info->addr.preind == 1 && info->addr.postind == 0);
- insert_field (self->fields[2], code, 1, 0);
- }
-- return NULL;
-+ return TRUE;
- }
-
- /* Encode the address operand for e.g. LDRSW <Xt>, [<Xn|SP>, #<simm>]!. */
--const char *
-+bfd_boolean
- aarch64_ins_addr_simm (const aarch64_operand *self,
- const aarch64_opnd_info *info,
- aarch64_insn *code,
-- const aarch64_inst *inst ATTRIBUTE_UNUSED)
-+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- int imm;
-
-@@ -663,7 +703,8 @@ aarch64_ins_addr_simm (const aarch64_ope
- insert_field (FLD_Rn, code, info->addr.base_regno, 0);
- /* simm (imm9 or imm7) */
- imm = info->addr.offset.imm;
-- if (self->fields[0] == FLD_imm7)
-+ if (self->fields[0] == FLD_imm7
-+ || info->qualifier == AARCH64_OPND_QLF_imm_tag)
- /* scaled immediate in ld/st pair instructions.. */
- imm >>= get_logsz (aarch64_get_qualifier_esize (info->qualifier));
- insert_field (self->fields[0], code, imm, 0);
-@@ -679,15 +720,16 @@ aarch64_ins_addr_simm (const aarch64_ope
- insert_field (self->fields[1], code, 1, 0);
- }
-
-- return NULL;
-+ return TRUE;
- }
-
- /* Encode the address operand for e.g. LDRAA <Xt>, [<Xn|SP>{, #<simm>}]. */
--const char *
-+bfd_boolean
- aarch64_ins_addr_simm10 (const aarch64_operand *self,
- const aarch64_opnd_info *info,
- aarch64_insn *code,
-- const aarch64_inst *inst ATTRIBUTE_UNUSED)
-+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- int imm;
-
-@@ -703,15 +745,16 @@ aarch64_ins_addr_simm10 (const aarch64_o
- assert (info->addr.preind == 1 && info->addr.postind == 0);
- insert_field (self->fields[3], code, 1, 0);
- }
-- return NULL;
-+ return TRUE;
- }
-
- /* Encode the address operand for e.g. LDRSW <Xt>, [<Xn|SP>{, #<pimm>}]. */
--const char *
-+bfd_boolean
- aarch64_ins_addr_uimm12 (const aarch64_operand *self,
- const aarch64_opnd_info *info,
- aarch64_insn *code,
-- const aarch64_inst *inst ATTRIBUTE_UNUSED)
-+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- int shift = get_logsz (aarch64_get_qualifier_esize (info->qualifier));
-
-@@ -719,15 +762,16 @@ aarch64_ins_addr_uimm12 (const aarch64_o
- insert_field (self->fields[0], code, info->addr.base_regno, 0);
- /* uimm12 */
- insert_field (self->fields[1], code,info->addr.offset.imm >> shift, 0);
-- return NULL;
-+ return TRUE;
- }
-
- /* Encode the address operand for e.g.
- LD1 {<Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>}, [<Xn|SP>], <Xm|#<amount>>. */
--const char *
-+bfd_boolean
- aarch64_ins_simd_addr_post (const aarch64_operand *self ATTRIBUTE_UNUSED,
- const aarch64_opnd_info *info, aarch64_insn *code,
-- const aarch64_inst *inst ATTRIBUTE_UNUSED)
-+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- /* Rn */
- insert_field (FLD_Rn, code, info->addr.base_regno, 0);
-@@ -736,100 +780,153 @@ aarch64_ins_simd_addr_post (const aarch6
- insert_field (FLD_Rm, code, info->addr.offset.regno, 0);
- else
- insert_field (FLD_Rm, code, 0x1f, 0);
-- return NULL;
-+ return TRUE;
- }
-
- /* Encode the condition operand for e.g. CSEL <Xd>, <Xn>, <Xm>, <cond>. */
--const char *
-+bfd_boolean
- aarch64_ins_cond (const aarch64_operand *self ATTRIBUTE_UNUSED,
- const aarch64_opnd_info *info, aarch64_insn *code,
-- const aarch64_inst *inst ATTRIBUTE_UNUSED)
-+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- /* cond */
- insert_field (FLD_cond, code, info->cond->value, 0);
-- return NULL;
-+ return TRUE;
- }
-
- /* Encode the system register operand for e.g. MRS <Xt>, <systemreg>. */
--const char *
-+bfd_boolean
- aarch64_ins_sysreg (const aarch64_operand *self ATTRIBUTE_UNUSED,
- const aarch64_opnd_info *info, aarch64_insn *code,
-- const aarch64_inst *inst ATTRIBUTE_UNUSED)
-+ const aarch64_inst *inst,
-+ aarch64_operand_error *detail ATTRIBUTE_UNUSED)
- {
-+ /* If a system instruction check if we have any restrictions on which
-+ registers it can use. */
-+ if (inst->opcode->iclass == ic_system)
-+ {
-+ uint64_t opcode_flags
-+ = inst->opcode->flags & (F_SYS_READ | F_SYS_WRITE);
-+ uint32_t sysreg_flags
-+ = info->sysreg.flags & (F_REG_READ | F_REG_WRITE);
-+
-+ /* Check to see if it's read-only, else check if it's write only.
-+ if it's both or unspecified don't care. */
-+ if (opcode_flags == F_SYS_READ
-+ && sysreg_flags
-+ && sysreg_flags != F_REG_READ)
-+ {
-+ detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
-+ detail->error = _("specified register cannot be read from");
-+ detail->index = info->idx;
-+ detail->non_fatal = TRUE;
-+ }
-+ else if (opcode_flags == F_SYS_WRITE
-+ && sysreg_flags
-+ && sysreg_flags != F_REG_WRITE)
-+ {
-+ detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
-+ detail->error = _("specified register cannot be written to");
-+ detail->index = info->idx;
-+ detail->non_fatal = TRUE;
-+ }
-+ }
- /* op0:op1:CRn:CRm:op2 */
-- insert_fields (code, info->sysreg, inst->opcode->mask, 5,
-+ insert_fields (code, info->sysreg.value, inst->opcode->mask, 5,
- FLD_op2, FLD_CRm, FLD_CRn, FLD_op1, FLD_op0);
-- return NULL;
-+ return TRUE;
- }
-
- /* Encode the PSTATE field operand for e.g. MSR <pstatefield>, #<imm>. */
--const char *
-+bfd_boolean
- aarch64_ins_pstatefield (const aarch64_operand *self ATTRIBUTE_UNUSED,
- const aarch64_opnd_info *info, aarch64_insn *code,
-- const aarch64_inst *inst ATTRIBUTE_UNUSED)
-+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- /* op1:op2 */
- insert_fields (code, info->pstatefield, inst->opcode->mask, 2,
- FLD_op2, FLD_op1);
-- return NULL;
-+ return TRUE;
- }
-
- /* Encode the system instruction op operand for e.g. AT <at_op>, <Xt>. */
--const char *
-+bfd_boolean
- aarch64_ins_sysins_op (const aarch64_operand *self ATTRIBUTE_UNUSED,
- const aarch64_opnd_info *info, aarch64_insn *code,
-- const aarch64_inst *inst ATTRIBUTE_UNUSED)
-+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- /* op1:CRn:CRm:op2 */
- insert_fields (code, info->sysins_op->value, inst->opcode->mask, 4,
- FLD_op2, FLD_CRm, FLD_CRn, FLD_op1);
-- return NULL;
-+ return TRUE;
- }
-
- /* Encode the memory barrier option operand for e.g. DMB <option>|#<imm>. */
-
--const char *
-+bfd_boolean
- aarch64_ins_barrier (const aarch64_operand *self ATTRIBUTE_UNUSED,
- const aarch64_opnd_info *info, aarch64_insn *code,
-- const aarch64_inst *inst ATTRIBUTE_UNUSED)
-+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- /* CRm */
- insert_field (FLD_CRm, code, info->barrier->value, 0);
-- return NULL;
-+ return TRUE;
-+}
-+
-+/* Encode the memory barrier option operand for DSB <option>nXS|#<imm>. */
-+
-+bfd_boolean
-+aarch64_ins_barrier_dsb_nxs (const aarch64_operand *self ATTRIBUTE_UNUSED,
-+ const aarch64_opnd_info *info, aarch64_insn *code,
-+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
-+{
-+ /* For the DSB nXS barrier variant: is a 5-bit unsigned immediate,
-+ encoded in CRm<3:2>. */
-+ aarch64_insn value = (info->barrier->value >> 2) - 4;
-+ insert_field (FLD_CRm_dsb_nxs, code, value, 0);
-+ return TRUE;
- }
-
- /* Encode the prefetch operation option operand for e.g.
- PRFM <prfop>, [<Xn|SP>{, #<pimm>}]. */
-
--const char *
-+bfd_boolean
- aarch64_ins_prfop (const aarch64_operand *self ATTRIBUTE_UNUSED,
- const aarch64_opnd_info *info, aarch64_insn *code,
-- const aarch64_inst *inst ATTRIBUTE_UNUSED)
-+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- /* prfop in Rt */
- insert_field (FLD_Rt, code, info->prfop->value, 0);
-- return NULL;
-+ return TRUE;
- }
-
- /* Encode the hint number for instructions that alias HINT but take an
- operand. */
-
--const char *
-+bfd_boolean
- aarch64_ins_hint (const aarch64_operand *self ATTRIBUTE_UNUSED,
- const aarch64_opnd_info *info, aarch64_insn *code,
-- const aarch64_inst *inst ATTRIBUTE_UNUSED)
-+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- /* CRm:op2. */
- insert_fields (code, info->hint_option->value, 0, 2, FLD_op2, FLD_CRm);
-- return NULL;
-+ return TRUE;
- }
-
- /* Encode the extended register operand for e.g.
- STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
--const char *
-+bfd_boolean
- aarch64_ins_reg_extended (const aarch64_operand *self ATTRIBUTE_UNUSED,
- const aarch64_opnd_info *info, aarch64_insn *code,
-- const aarch64_inst *inst ATTRIBUTE_UNUSED)
-+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- enum aarch64_modifier_kind kind;
-
-@@ -844,15 +941,16 @@ aarch64_ins_reg_extended (const aarch64_
- /* imm3 */
- insert_field (FLD_imm3, code, info->shifter.amount, 0);
-
-- return NULL;
-+ return TRUE;
- }
-
- /* Encode the shifted register operand for e.g.
- SUBS <Xd>, <Xn>, <Xm> {, <shift> #<amount>}. */
--const char *
-+bfd_boolean
- aarch64_ins_reg_shifted (const aarch64_operand *self ATTRIBUTE_UNUSED,
- const aarch64_opnd_info *info, aarch64_insn *code,
-- const aarch64_inst *inst ATTRIBUTE_UNUSED)
-+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- /* Rm */
- insert_field (FLD_Rm, code, info->reg.regno, 0);
-@@ -862,39 +960,41 @@ aarch64_ins_reg_shifted (const aarch64_o
- /* imm6 */
- insert_field (FLD_imm6, code, info->shifter.amount, 0);
-
-- return NULL;
-+ return TRUE;
- }
-
- /* Encode an SVE address [<base>, #<simm4>*<factor>, MUL VL],
- where <simm4> is a 4-bit signed value and where <factor> is 1 plus
- SELF's operand-dependent value. fields[0] specifies the field that
- holds <base>. <simm4> is encoded in the SVE_imm4 field. */
--const char *
-+bfd_boolean
- aarch64_ins_sve_addr_ri_s4xvl (const aarch64_operand *self,
- const aarch64_opnd_info *info,
- aarch64_insn *code,
-- const aarch64_inst *inst ATTRIBUTE_UNUSED)
-+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- int factor = 1 + get_operand_specific_data (self);
- insert_field (self->fields[0], code, info->addr.base_regno, 0);
- insert_field (FLD_SVE_imm4, code, info->addr.offset.imm / factor, 0);
-- return NULL;
-+ return TRUE;
- }
-
- /* Encode an SVE address [<base>, #<simm6>*<factor>, MUL VL],
- where <simm6> is a 6-bit signed value and where <factor> is 1 plus
- SELF's operand-dependent value. fields[0] specifies the field that
- holds <base>. <simm6> is encoded in the SVE_imm6 field. */
--const char *
-+bfd_boolean
- aarch64_ins_sve_addr_ri_s6xvl (const aarch64_operand *self,
- const aarch64_opnd_info *info,
- aarch64_insn *code,
-- const aarch64_inst *inst ATTRIBUTE_UNUSED)
-+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- int factor = 1 + get_operand_specific_data (self);
- insert_field (self->fields[0], code, info->addr.base_regno, 0);
- insert_field (FLD_SVE_imm6, code, info->addr.offset.imm / factor, 0);
-- return NULL;
-+ return TRUE;
- }
-
- /* Encode an SVE address [<base>, #<simm9>*<factor>, MUL VL],
-@@ -902,68 +1002,73 @@ aarch64_ins_sve_addr_ri_s6xvl (const aar
- SELF's operand-dependent value. fields[0] specifies the field that
- holds <base>. <simm9> is encoded in the concatenation of the SVE_imm6
- and imm3 fields, with imm3 being the less-significant part. */
--const char *
-+bfd_boolean
- aarch64_ins_sve_addr_ri_s9xvl (const aarch64_operand *self,
- const aarch64_opnd_info *info,
- aarch64_insn *code,
-- const aarch64_inst *inst ATTRIBUTE_UNUSED)
-+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- int factor = 1 + get_operand_specific_data (self);
- insert_field (self->fields[0], code, info->addr.base_regno, 0);
- insert_fields (code, info->addr.offset.imm / factor, 0,
- 2, FLD_imm3, FLD_SVE_imm6);
-- return NULL;
-+ return TRUE;
- }
-
- /* Encode an SVE address [X<n>, #<SVE_imm4> << <shift>], where <SVE_imm4>
- is a 4-bit signed number and where <shift> is SELF's operand-dependent
- value. fields[0] specifies the base register field. */
--const char *
-+bfd_boolean
- aarch64_ins_sve_addr_ri_s4 (const aarch64_operand *self,
- const aarch64_opnd_info *info, aarch64_insn *code,
-- const aarch64_inst *inst ATTRIBUTE_UNUSED)
-+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- int factor = 1 << get_operand_specific_data (self);
- insert_field (self->fields[0], code, info->addr.base_regno, 0);
- insert_field (FLD_SVE_imm4, code, info->addr.offset.imm / factor, 0);
-- return NULL;
-+ return TRUE;
- }
-
- /* Encode an SVE address [X<n>, #<SVE_imm6> << <shift>], where <SVE_imm6>
- is a 6-bit unsigned number and where <shift> is SELF's operand-dependent
- value. fields[0] specifies the base register field. */
--const char *
-+bfd_boolean
- aarch64_ins_sve_addr_ri_u6 (const aarch64_operand *self,
- const aarch64_opnd_info *info, aarch64_insn *code,
-- const aarch64_inst *inst ATTRIBUTE_UNUSED)
-+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- int factor = 1 << get_operand_specific_data (self);
- insert_field (self->fields[0], code, info->addr.base_regno, 0);
- insert_field (FLD_SVE_imm6, code, info->addr.offset.imm / factor, 0);
-- return NULL;
-+ return TRUE;
- }
-
- /* Encode an SVE address [X<n>, X<m>{, LSL #<shift>}], where <shift>
- is SELF's operand-dependent value. fields[0] specifies the base
- register field and fields[1] specifies the offset register field. */
--const char *
-+bfd_boolean
- aarch64_ins_sve_addr_rr_lsl (const aarch64_operand *self,
- const aarch64_opnd_info *info, aarch64_insn *code,
-- const aarch64_inst *inst ATTRIBUTE_UNUSED)
-+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- insert_field (self->fields[0], code, info->addr.base_regno, 0);
- insert_field (self->fields[1], code, info->addr.offset.regno, 0);
-- return NULL;
-+ return TRUE;
- }
-
- /* Encode an SVE address [X<n>, Z<m>.<T>, (S|U)XTW {#<shift>}], where
- <shift> is SELF's operand-dependent value. fields[0] specifies the
- base register field, fields[1] specifies the offset register field and
- fields[2] is a single-bit field that selects SXTW over UXTW. */
--const char *
-+bfd_boolean
- aarch64_ins_sve_addr_rz_xtw (const aarch64_operand *self,
- const aarch64_opnd_info *info, aarch64_insn *code,
-- const aarch64_inst *inst ATTRIBUTE_UNUSED)
-+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- insert_field (self->fields[0], code, info->addr.base_regno, 0);
- insert_field (self->fields[1], code, info->addr.offset.regno, 0);
-@@ -971,77 +1076,83 @@ aarch64_ins_sve_addr_rz_xtw (const aarch
- insert_field (self->fields[2], code, 0, 0);
- else
- insert_field (self->fields[2], code, 1, 0);
-- return NULL;
-+ return TRUE;
- }
-
- /* Encode an SVE address [Z<n>.<T>, #<imm5> << <shift>], where <imm5> is a
- 5-bit unsigned number and where <shift> is SELF's operand-dependent value.
- fields[0] specifies the base register field. */
--const char *
-+bfd_boolean
- aarch64_ins_sve_addr_zi_u5 (const aarch64_operand *self,
- const aarch64_opnd_info *info, aarch64_insn *code,
-- const aarch64_inst *inst ATTRIBUTE_UNUSED)
-+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- int factor = 1 << get_operand_specific_data (self);
- insert_field (self->fields[0], code, info->addr.base_regno, 0);
- insert_field (FLD_imm5, code, info->addr.offset.imm / factor, 0);
-- return NULL;
-+ return TRUE;
- }
-
- /* Encode an SVE address [Z<n>.<T>, Z<m>.<T>{, <modifier> {#<msz>}}],
- where <modifier> is fixed by the instruction and where <msz> is a
- 2-bit unsigned number. fields[0] specifies the base register field
- and fields[1] specifies the offset register field. */
--static const char *
-+static bfd_boolean
- aarch64_ext_sve_addr_zz (const aarch64_operand *self,
-- const aarch64_opnd_info *info, aarch64_insn *code)
-+ const aarch64_opnd_info *info, aarch64_insn *code,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- insert_field (self->fields[0], code, info->addr.base_regno, 0);
- insert_field (self->fields[1], code, info->addr.offset.regno, 0);
- insert_field (FLD_SVE_msz, code, info->shifter.amount, 0);
-- return NULL;
-+ return TRUE;
- }
-
- /* Encode an SVE address [Z<n>.<T>, Z<m>.<T>{, LSL #<msz>}], where
- <msz> is a 2-bit unsigned number. fields[0] specifies the base register
- field and fields[1] specifies the offset register field. */
--const char *
-+bfd_boolean
- aarch64_ins_sve_addr_zz_lsl (const aarch64_operand *self,
- const aarch64_opnd_info *info, aarch64_insn *code,
-- const aarch64_inst *inst ATTRIBUTE_UNUSED)
-+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors)
- {
-- return aarch64_ext_sve_addr_zz (self, info, code);
-+ return aarch64_ext_sve_addr_zz (self, info, code, errors);
- }
-
- /* Encode an SVE address [Z<n>.<T>, Z<m>.<T>, SXTW {#<msz>}], where
- <msz> is a 2-bit unsigned number. fields[0] specifies the base register
- field and fields[1] specifies the offset register field. */
--const char *
-+bfd_boolean
- aarch64_ins_sve_addr_zz_sxtw (const aarch64_operand *self,
- const aarch64_opnd_info *info,
- aarch64_insn *code,
-- const aarch64_inst *inst ATTRIBUTE_UNUSED)
-+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors)
- {
-- return aarch64_ext_sve_addr_zz (self, info, code);
-+ return aarch64_ext_sve_addr_zz (self, info, code, errors);
- }
-
- /* Encode an SVE address [Z<n>.<T>, Z<m>.<T>, UXTW {#<msz>}], where
- <msz> is a 2-bit unsigned number. fields[0] specifies the base register
- field and fields[1] specifies the offset register field. */
--const char *
-+bfd_boolean
- aarch64_ins_sve_addr_zz_uxtw (const aarch64_operand *self,
- const aarch64_opnd_info *info,
- aarch64_insn *code,
-- const aarch64_inst *inst ATTRIBUTE_UNUSED)
-+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors)
- {
-- return aarch64_ext_sve_addr_zz (self, info, code);
-+ return aarch64_ext_sve_addr_zz (self, info, code, errors);
- }
-
- /* Encode an SVE ADD/SUB immediate. */
--const char *
-+bfd_boolean
- aarch64_ins_sve_aimm (const aarch64_operand *self,
- const aarch64_opnd_info *info, aarch64_insn *code,
-- const aarch64_inst *inst ATTRIBUTE_UNUSED)
-+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- if (info->shifter.amount == 8)
- insert_all_fields (self, code, (info->imm.value & 0xff) | 256);
-@@ -1049,87 +1160,94 @@ aarch64_ins_sve_aimm (const aarch64_oper
- insert_all_fields (self, code, ((info->imm.value / 256) & 0xff) | 256);
- else
- insert_all_fields (self, code, info->imm.value & 0xff);
-- return NULL;
-+ return TRUE;
- }
-
- /* Encode an SVE CPY/DUP immediate. */
--const char *
-+bfd_boolean
- aarch64_ins_sve_asimm (const aarch64_operand *self,
- const aarch64_opnd_info *info, aarch64_insn *code,
-- const aarch64_inst *inst)
-+ const aarch64_inst *inst,
-+ aarch64_operand_error *errors)
- {
-- return aarch64_ins_sve_aimm (self, info, code, inst);
-+ return aarch64_ins_sve_aimm (self, info, code, inst, errors);
- }
-
- /* Encode Zn[MM], where MM has a 7-bit triangular encoding. The fields
- array specifies which field to use for Zn. MM is encoded in the
- concatenation of imm5 and SVE_tszh, with imm5 being the less
- significant part. */
--const char *
-+bfd_boolean
- aarch64_ins_sve_index (const aarch64_operand *self,
- const aarch64_opnd_info *info, aarch64_insn *code,
-- const aarch64_inst *inst ATTRIBUTE_UNUSED)
-+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- unsigned int esize = aarch64_get_qualifier_esize (info->qualifier);
- insert_field (self->fields[0], code, info->reglane.regno, 0);
- insert_fields (code, (info->reglane.index * 2 + 1) * esize, 0,
- 2, FLD_imm5, FLD_SVE_tszh);
-- return NULL;
-+ return TRUE;
- }
-
- /* Encode a logical/bitmask immediate for the MOV alias of SVE DUPM. */
--const char *
-+bfd_boolean
- aarch64_ins_sve_limm_mov (const aarch64_operand *self,
- const aarch64_opnd_info *info, aarch64_insn *code,
-- const aarch64_inst *inst)
-+ const aarch64_inst *inst,
-+ aarch64_operand_error *errors)
- {
-- return aarch64_ins_limm (self, info, code, inst);
-+ return aarch64_ins_limm (self, info, code, inst, errors);
- }
-
- /* Encode Zn[MM], where Zn occupies the least-significant part of the field
- and where MM occupies the most-significant part. The operand-dependent
- value specifies the number of bits in Zn. */
--const char *
-+bfd_boolean
- aarch64_ins_sve_quad_index (const aarch64_operand *self,
- const aarch64_opnd_info *info, aarch64_insn *code,
-- const aarch64_inst *inst ATTRIBUTE_UNUSED)
-+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- unsigned int reg_bits = get_operand_specific_data (self);
- assert (info->reglane.regno < (1U << reg_bits));
- unsigned int val = (info->reglane.index << reg_bits) + info->reglane.regno;
- insert_all_fields (self, code, val);
-- return NULL;
-+ return TRUE;
- }
-
- /* Encode {Zn.<T> - Zm.<T>}. The fields array specifies which field
- to use for Zn. */
--const char *
-+bfd_boolean
- aarch64_ins_sve_reglist (const aarch64_operand *self,
- const aarch64_opnd_info *info, aarch64_insn *code,
-- const aarch64_inst *inst ATTRIBUTE_UNUSED)
-+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- insert_field (self->fields[0], code, info->reglist.first_regno, 0);
-- return NULL;
-+ return TRUE;
- }
-
- /* Encode <pattern>{, MUL #<amount>}. The fields array specifies which
- fields to use for <pattern>. <amount> - 1 is encoded in the SVE_imm4
- field. */
--const char *
-+bfd_boolean
- aarch64_ins_sve_scale (const aarch64_operand *self,
- const aarch64_opnd_info *info, aarch64_insn *code,
-- const aarch64_inst *inst ATTRIBUTE_UNUSED)
-+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- insert_all_fields (self, code, info->imm.value);
- insert_field (FLD_SVE_imm4, code, info->shifter.amount - 1, 0);
-- return NULL;
-+ return TRUE;
- }
-
- /* Encode an SVE shift left immediate. */
--const char *
-+bfd_boolean
- aarch64_ins_sve_shlimm (const aarch64_operand *self,
- const aarch64_opnd_info *info, aarch64_insn *code,
-- const aarch64_inst *inst)
-+ const aarch64_inst *inst,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- const aarch64_opnd_info *prev_operand;
- unsigned int esize;
-@@ -1138,68 +1256,73 @@ aarch64_ins_sve_shlimm (const aarch64_op
- prev_operand = &inst->operands[info->idx - 1];
- esize = aarch64_get_qualifier_esize (prev_operand->qualifier);
- insert_all_fields (self, code, 8 * esize + info->imm.value);
-- return NULL;
-+ return TRUE;
- }
-
- /* Encode an SVE shift right immediate. */
--const char *
-+bfd_boolean
- aarch64_ins_sve_shrimm (const aarch64_operand *self,
- const aarch64_opnd_info *info, aarch64_insn *code,
-- const aarch64_inst *inst)
-+ const aarch64_inst *inst,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- const aarch64_opnd_info *prev_operand;
- unsigned int esize;
-
-- assert (info->idx > 0);
-- prev_operand = &inst->operands[info->idx - 1];
-+ unsigned int opnd_backshift = get_operand_specific_data (self);
-+ assert (info->idx >= (int)opnd_backshift);
-+ prev_operand = &inst->operands[info->idx - opnd_backshift];
- esize = aarch64_get_qualifier_esize (prev_operand->qualifier);
- insert_all_fields (self, code, 16 * esize - info->imm.value);
-- return NULL;
-+ return TRUE;
- }
-
- /* Encode a single-bit immediate that selects between #0.5 and #1.0.
- The fields array specifies which field to use. */
--const char *
-+bfd_boolean
- aarch64_ins_sve_float_half_one (const aarch64_operand *self,
- const aarch64_opnd_info *info,
- aarch64_insn *code,
-- const aarch64_inst *inst ATTRIBUTE_UNUSED)
-+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- if (info->imm.value == 0x3f000000)
- insert_field (self->fields[0], code, 0, 0);
- else
- insert_field (self->fields[0], code, 1, 0);
-- return NULL;
-+ return TRUE;
- }
-
- /* Encode a single-bit immediate that selects between #0.5 and #2.0.
- The fields array specifies which field to use. */
--const char *
-+bfd_boolean
- aarch64_ins_sve_float_half_two (const aarch64_operand *self,
- const aarch64_opnd_info *info,
- aarch64_insn *code,
-- const aarch64_inst *inst ATTRIBUTE_UNUSED)
-+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- if (info->imm.value == 0x3f000000)
- insert_field (self->fields[0], code, 0, 0);
- else
- insert_field (self->fields[0], code, 1, 0);
-- return NULL;
-+ return TRUE;
- }
-
- /* Encode a single-bit immediate that selects between #0.0 and #1.0.
- The fields array specifies which field to use. */
--const char *
-+bfd_boolean
- aarch64_ins_sve_float_zero_one (const aarch64_operand *self,
- const aarch64_opnd_info *info,
- aarch64_insn *code,
-- const aarch64_inst *inst ATTRIBUTE_UNUSED)
-+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- if (info->imm.value == 0)
- insert_field (self->fields[0], code, 0, 0);
- else
- insert_field (self->fields[0], code, 1, 0);
-- return NULL;
-+ return TRUE;
- }
-
- /* Miscellaneous encoding functions. */
-@@ -1519,6 +1642,7 @@ do_special_encoding (struct aarch64_inst
- static void
- aarch64_encode_variant_using_iclass (struct aarch64_inst *inst)
- {
-+ int variant = 0;
- switch (inst->opcode->iclass)
- {
- case sve_cpy:
-@@ -1529,6 +1653,8 @@ aarch64_encode_variant_using_iclass (str
- case sve_index:
- case sve_shift_pred:
- case sve_shift_unpred:
-+ case sve_shift_tsz_hsd:
-+ case sve_shift_tsz_bhsd:
- /* For indices and shift amounts, the variant is encoded as
- part of the immediate. */
- break;
-@@ -1561,10 +1687,33 @@ aarch64_encode_variant_using_iclass (str
- insert_field (FLD_size, &inst->value, aarch64_get_variant (inst) + 1, 0);
- break;
-
-+ case sve_size_bh:
- case sve_size_sd:
- insert_field (FLD_SVE_sz, &inst->value, aarch64_get_variant (inst), 0);
- break;
-
-+ case sve_size_sd2:
-+ insert_field (FLD_SVE_sz2, &inst->value, aarch64_get_variant (inst), 0);
-+ break;
-+
-+ case sve_size_hsd2:
-+ insert_field (FLD_SVE_size, &inst->value,
-+ aarch64_get_variant (inst) + 1, 0);
-+ break;
-+
-+ case sve_size_tsz_bhs:
-+ insert_fields (&inst->value,
-+ (1 << aarch64_get_variant (inst)),
-+ 0, 2, FLD_SVE_tszl_19, FLD_SVE_sz);
-+ break;
-+
-+ case sve_size_13:
-+ variant = aarch64_get_variant (inst) + 1;
-+ if (variant == 2)
-+ variant = 3;
-+ insert_field (FLD_size, &inst->value, variant, 0);
-+ break;
-+
- default:
- break;
- }
-@@ -1845,7 +1994,7 @@ convert_to_real (aarch64_inst *inst, con
- break;
- }
-
--convert_to_real_return:
-+ convert_to_real_return:
- aarch64_replace_opcode (inst, real);
- }
-
-@@ -1853,11 +2002,12 @@ convert_to_real_return:
- Return the encoded result in *CODE and if QLF_SEQ is not NULL, return the
- matched operand qualifier sequence in *QLF_SEQ. */
-
--int
-+bfd_boolean
- aarch64_opcode_encode (const aarch64_opcode *opcode,
- const aarch64_inst *inst_ori, aarch64_insn *code,
- aarch64_opnd_qualifier_t *qlf_seq,
-- aarch64_operand_error *mismatch_detail)
-+ aarch64_operand_error *mismatch_detail,
-+ aarch64_instr_sequence* insn_sequence)
- {
- int i;
- const aarch64_opcode *aliased;
-@@ -1930,8 +2080,10 @@ aarch64_opcode_encode (const aarch64_opc
- continue;
- }
- opnd = &aarch64_operands[type];
-- if (operand_has_inserter (opnd))
-- aarch64_insert_operand (opnd, info, &inst->value, inst);
-+ if (operand_has_inserter (opnd)
-+ && !aarch64_insert_operand (opnd, info, &inst->value, inst,
-+ mismatch_detail))
-+ return FALSE;
- }
-
- /* Call opcode encoders indicated by flags. */
-@@ -1942,10 +2094,42 @@ aarch64_opcode_encode (const aarch64_opc
- variant. */
- aarch64_encode_variant_using_iclass (inst);
-
--encoding_exit:
-+ /* Run a verifier if the instruction has one set. */
-+ if (opcode->verifier)
-+ {
-+ enum err_type result = opcode->verifier (inst, *code, 0, TRUE,
-+ mismatch_detail, insn_sequence);
-+ switch (result)
-+ {
-+ case ERR_UND:
-+ case ERR_UNP:
-+ case ERR_NYI:
-+ return FALSE;
-+ default:
-+ break;
-+ }
-+ }
-+
-+ /* Always run constrain verifiers, this is needed because constrains need to
-+ maintain a global state. Regardless if the instruction has the flag set
-+ or not. */
-+ enum err_type result = verify_constraints (inst, *code, 0, TRUE,
-+ mismatch_detail, insn_sequence);
-+ switch (result)
-+ {
-+ case ERR_UND:
-+ case ERR_UNP:
-+ case ERR_NYI:
-+ return FALSE;
-+ default:
-+ break;
-+ }
-+
-+
-+ encoding_exit:
- DEBUG_TRACE ("exit with %s", opcode->name);
-
- *code = inst->value;
-
-- return 1;
-+ return TRUE;
- }
-diff -rup binutils-2.30/opcodes/aarch64-asm.h binutils-2.30.new/opcodes/aarch64-asm.h
---- binutils-2.30/opcodes/aarch64-asm.h 2018-01-13 13:31:16.000000000 +0000
-+++ binutils-2.30.new/opcodes/aarch64-asm.h 2021-03-23 16:19:53.170776284 +0000
-@@ -1,5 +1,5 @@
- /* aarch64-asm.h -- Header file for aarch64-asm.c and aarch64-asm-2.c.
-- Copyright (C) 2012-2018 Free Software Foundation, Inc.
-+ Copyright (C) 2012-2021 Free Software Foundation, Inc.
- Contributed by ARM Ltd.
-
- This file is part of the GNU opcodes library.
-@@ -30,16 +30,19 @@ const aarch64_opcode* aarch64_find_real_
-
- /* Switch-table-based high-level operand inserter. */
-
--const char* aarch64_insert_operand (const aarch64_operand *,
-+bfd_boolean aarch64_insert_operand (const aarch64_operand *,
- const aarch64_opnd_info *, aarch64_insn *,
-- const aarch64_inst *);
-+ const aarch64_inst *,
-+ aarch64_operand_error *);
-
- /* Operand inserters. */
-
- #define AARCH64_DECL_OPD_INSERTER(x) \
-- const char* aarch64_##x (const aarch64_operand *, const aarch64_opnd_info *, \
-- aarch64_insn *, const aarch64_inst *)
-+ bfd_boolean aarch64_##x (const aarch64_operand *, const aarch64_opnd_info *, \
-+ aarch64_insn *, const aarch64_inst *, \
-+ aarch64_operand_error *)
-
-+AARCH64_DECL_OPD_INSERTER (ins_none);
- AARCH64_DECL_OPD_INSERTER (ins_regno);
- AARCH64_DECL_OPD_INSERTER (ins_reglane);
- AARCH64_DECL_OPD_INSERTER (ins_reglist);
-@@ -68,6 +71,7 @@ AARCH64_DECL_OPD_INSERTER (ins_sysreg);
- AARCH64_DECL_OPD_INSERTER (ins_pstatefield);
- AARCH64_DECL_OPD_INSERTER (ins_sysins_op);
- AARCH64_DECL_OPD_INSERTER (ins_barrier);
-+AARCH64_DECL_OPD_INSERTER (ins_barrier_dsb_nxs);
- AARCH64_DECL_OPD_INSERTER (ins_hint);
- AARCH64_DECL_OPD_INSERTER (ins_prfop);
- AARCH64_DECL_OPD_INSERTER (ins_reg_extended);
-diff -rup binutils-2.30/opcodes/aarch64-dis-2.c binutils-2.30.new/opcodes/aarch64-dis-2.c
---- binutils-2.30/opcodes/aarch64-dis-2.c 2018-01-13 13:31:16.000000000 +0000
-+++ binutils-2.30.new/opcodes/aarch64-dis-2.c 2021-03-23 16:19:53.169776291 +0000
-@@ -1,5 +1,5 @@
- /* This file is automatically generated by aarch64-gen. Do not edit! */
--/* Copyright (C) 2012-2018 Free Software Foundation, Inc.
-+/* Copyright (C) 2012-2021 Free Software Foundation, Inc.
- Contributed by ARM Ltd.
-
- This file is part of the GNU opcodes library.
-@@ -34,21 +34,32 @@ aarch64_opcode_lookup_1 (uint32_t word)
- {
- if (((word >> 24) & 0x1) == 0)
- {
-- if (((word >> 31) & 0x1) == 0)
-+ if (((word >> 28) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
-- 0xxx0000xxxxxxxxxxxxxxxxxxxxxxxx
-- adr. */
-- return 1155;
-+ xxx00000xxxxxxxxxxxxxxxxxxxxxxxx
-+ udf. */
-+ return 754;
- }
- else
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 1xxx0000xxxxxxxxxxxxxxxxxxxxxxxx
-- adrp. */
-- return 1156;
-+ if (((word >> 31) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 0xx10000xxxxxxxxxxxxxxxxxxxxxxxx
-+ adr. */
-+ return 1191;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 1xx10000xxxxxxxxxxxxxxxxxxxxxxxx
-+ adrp. */
-+ return 1192;
-+ }
- }
- }
- else
-@@ -115,7 +126,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0000100x000xxxxx0xxxxxxxxxxxxxxx
- stxrb. */
-- return 910;
-+ return 937;
- }
- else
- {
-@@ -123,7 +134,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0100100x000xxxxx0xxxxxxxxxxxxxxx
- stxrh. */
-- return 916;
-+ return 943;
- }
- }
- else
-@@ -132,7 +143,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 1x00100x000xxxxx0xxxxxxxxxxxxxxx
- stxr. */
-- return 922;
-+ return 949;
- }
- }
- else
-@@ -143,7 +154,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0x00100x001xxxxx0xxxxxxxxxxxxxxx
- casp. */
-- return 990;
-+ return 1026;
- }
- else
- {
-@@ -151,7 +162,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 1x00100x001xxxxx0xxxxxxxxxxxxxxx
- stxp. */
-- return 924;
-+ return 951;
- }
- }
- }
-@@ -167,7 +178,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0000100x000xxxxx1xxxxxxxxxxxxxxx
- stlxrb. */
-- return 911;
-+ return 938;
- }
- else
- {
-@@ -175,7 +186,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0100100x000xxxxx1xxxxxxxxxxxxxxx
- stlxrh. */
-- return 917;
-+ return 944;
- }
- }
- else
-@@ -184,7 +195,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 1x00100x000xxxxx1xxxxxxxxxxxxxxx
- stlxr. */
-- return 923;
-+ return 950;
- }
- }
- else
-@@ -195,7 +206,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0x00100x001xxxxx1xxxxxxxxxxxxxxx
- caspl. */
-- return 992;
-+ return 1028;
- }
- else
- {
-@@ -203,18 +214,29 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 1x00100x001xxxxx1xxxxxxxxxxxxxxx
- stlxp. */
-- return 925;
-+ return 952;
- }
- }
- }
- }
- else
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- xx10100x00xxxxxxxxxxxxxxxxxxxxxx
-- stnp. */
-- return 941;
-+ if (((word >> 30) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ x010100x00xxxxxxxxxxxxxxxxxxxxxx
-+ stnp. */
-+ return 971;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ x110100x00xxxxxxxxxxxxxxxxxxxxxx
-+ stgp. */
-+ return 980;
-+ }
- }
- }
- else
-@@ -231,7 +253,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0x00100x100xxxxx0xxxxxxxxxxxxxxx
- stllrb. */
-- return 939;
-+ return 969;
- }
- else
- {
-@@ -239,7 +261,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 1x00100x100xxxxx0xxxxxxxxxxxxxxx
- stllr. */
-- return 938;
-+ return 968;
- }
- }
- else
-@@ -252,7 +274,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0000100x101xxxxx0xxxxxxxxxxxxxxx
- casb. */
-- return 978;
-+ return 1014;
- }
- else
- {
-@@ -260,7 +282,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0100100x101xxxxx0xxxxxxxxxxxxxxx
- cash. */
-- return 979;
-+ return 1015;
- }
- }
- else
-@@ -269,7 +291,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 1x00100x101xxxxx0xxxxxxxxxxxxxxx
- cas. */
-- return 980;
-+ return 1016;
- }
- }
- }
-@@ -285,7 +307,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0000100x100xxxxx1xxxxxxxxxxxxxxx
- stlrb. */
-- return 914;
-+ return 941;
- }
- else
- {
-@@ -293,7 +315,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0100100x100xxxxx1xxxxxxxxxxxxxxx
- stlrh. */
-- return 920;
-+ return 947;
- }
- }
- else
-@@ -302,7 +324,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 1x00100x100xxxxx1xxxxxxxxxxxxxxx
- stlr. */
-- return 930;
-+ return 957;
- }
- }
- else
-@@ -315,7 +337,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0000100x101xxxxx1xxxxxxxxxxxxxxx
- caslb. */
-- return 982;
-+ return 1018;
- }
- else
- {
-@@ -323,7 +345,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0100100x101xxxxx1xxxxxxxxxxxxxxx
- caslh. */
-- return 985;
-+ return 1021;
- }
- }
- else
-@@ -332,18 +354,29 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 1x00100x101xxxxx1xxxxxxxxxxxxxxx
- casl. */
-- return 988;
-+ return 1024;
- }
- }
- }
- }
- else
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- xx10100x10xxxxxxxxxxxxxxxxxxxxxx
-- stp. */
-- return 950;
-+ if (((word >> 30) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ x010100x10xxxxxxxxxxxxxxxxxxxxxx
-+ stp. */
-+ return 981;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ x110100x10xxxxxxxxxxxxxxxxxxxxxx
-+ stgp. */
-+ return 986;
-+ }
- }
- }
- }
-@@ -365,7 +398,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0000100x010xxxxx0xxxxxxxxxxxxxxx
- ldxrb. */
-- return 912;
-+ return 939;
- }
- else
- {
-@@ -373,7 +406,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0100100x010xxxxx0xxxxxxxxxxxxxxx
- ldxrh. */
-- return 918;
-+ return 945;
- }
- }
- else
-@@ -382,7 +415,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 1x00100x010xxxxx0xxxxxxxxxxxxxxx
- ldxr. */
-- return 926;
-+ return 953;
- }
- }
- else
-@@ -393,7 +426,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0x00100x011xxxxx0xxxxxxxxxxxxxxx
- caspa. */
-- return 991;
-+ return 1027;
- }
- else
- {
-@@ -401,7 +434,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 1x00100x011xxxxx0xxxxxxxxxxxxxxx
- ldxp. */
-- return 928;
-+ return 955;
- }
- }
- }
-@@ -417,7 +450,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0000100x010xxxxx1xxxxxxxxxxxxxxx
- ldaxrb. */
-- return 913;
-+ return 940;
- }
- else
- {
-@@ -425,7 +458,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0100100x010xxxxx1xxxxxxxxxxxxxxx
- ldaxrh. */
-- return 919;
-+ return 946;
- }
- }
- else
-@@ -434,7 +467,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 1x00100x010xxxxx1xxxxxxxxxxxxxxx
- ldaxr. */
-- return 927;
-+ return 954;
- }
- }
- else
-@@ -445,7 +478,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0x00100x011xxxxx1xxxxxxxxxxxxxxx
- caspal. */
-- return 993;
-+ return 1029;
- }
- else
- {
-@@ -453,7 +486,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 1x00100x011xxxxx1xxxxxxxxxxxxxxx
- ldaxp. */
-- return 929;
-+ return 956;
- }
- }
- }
-@@ -466,7 +499,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x010100x01xxxxxxxxxxxxxxxxxxxxxx
- ldnp. */
-- return 942;
-+ return 972;
- }
- else
- {
-@@ -474,7 +507,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x110100x01xxxxxxxxxxxxxxxxxxxxxx
- ldpsw. */
-- return 949;
-+ return 979;
- }
- }
- }
-@@ -494,7 +527,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0000100x110xxxxx0xxxxxxxxxxxxxxx
- ldlarb. */
-- return 936;
-+ return 966;
- }
- else
- {
-@@ -502,7 +535,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0100100x110xxxxx0xxxxxxxxxxxxxxx
- ldlarh. */
-- return 937;
-+ return 967;
- }
- }
- else
-@@ -511,7 +544,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 1x00100x110xxxxx0xxxxxxxxxxxxxxx
- ldlar. */
-- return 935;
-+ return 965;
- }
- }
- else
-@@ -524,7 +557,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0000100x111xxxxx0xxxxxxxxxxxxxxx
- casab. */
-- return 981;
-+ return 1017;
- }
- else
- {
-@@ -532,7 +565,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0100100x111xxxxx0xxxxxxxxxxxxxxx
- casah. */
-- return 984;
-+ return 1020;
- }
- }
- else
-@@ -541,7 +574,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 1x00100x111xxxxx0xxxxxxxxxxxxxxx
- casa. */
-- return 987;
-+ return 1023;
- }
- }
- }
-@@ -557,7 +590,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0000100x110xxxxx1xxxxxxxxxxxxxxx
- ldarb. */
-- return 915;
-+ return 942;
- }
- else
- {
-@@ -565,7 +598,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0100100x110xxxxx1xxxxxxxxxxxxxxx
- ldarh. */
-- return 921;
-+ return 948;
- }
- }
- else
-@@ -574,7 +607,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 1x00100x110xxxxx1xxxxxxxxxxxxxxx
- ldar. */
-- return 931;
-+ return 958;
- }
- }
- else
-@@ -587,7 +620,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0000100x111xxxxx1xxxxxxxxxxxxxxx
- casalb. */
-- return 983;
-+ return 1019;
- }
- else
- {
-@@ -595,7 +628,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0100100x111xxxxx1xxxxxxxxxxxxxxx
- casalh. */
-- return 986;
-+ return 1022;
- }
- }
- else
-@@ -604,7 +637,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 1x00100x111xxxxx1xxxxxxxxxxxxxxx
- casal. */
-- return 989;
-+ return 1025;
- }
- }
- }
-@@ -617,7 +650,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x010100x11xxxxxxxxxxxxxxxxxxxxxx
- ldp. */
-- return 951;
-+ return 982;
- }
- else
- {
-@@ -625,7 +658,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x110100x11xxxxxxxxxxxxxxxxxxxxxx
- ldpsw. */
-- return 954;
-+ return 985;
- }
- }
- }
-@@ -643,7 +676,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0x011000xxxxxxxxxxxxxxxxxxxxxxxx
- ldr. */
-- return 955;
-+ return 987;
- }
- else
- {
-@@ -653,7 +686,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 10011000xxxxxxxxxxxxxxxxxxxxxxxx
- ldrsw. */
-- return 957;
-+ return 989;
- }
- else
- {
-@@ -661,7 +694,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 11011000xxxxxxxxxxxxxxxxxxxxxxxx
- prfm. */
-- return 958;
-+ return 990;
- }
- }
- }
-@@ -685,7 +718,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 00111000000xxxxxxxxx00xxxxxxxxxx
- sturb. */
-- return 896;
-+ return 922;
- }
- else
- {
-@@ -693,7 +726,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 01111000000xxxxxxxxx00xxxxxxxxxx
- sturh. */
-- return 901;
-+ return 927;
- }
- }
- else
-@@ -702,7 +735,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 1x111000000xxxxxxxxx00xxxxxxxxxx
- stur. */
-- return 904;
-+ return 930;
- }
- }
- else
-@@ -715,7 +748,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 00111000010xxxxxxxxx00xxxxxxxxxx
- ldurb. */
-- return 897;
-+ return 923;
- }
- else
- {
-@@ -723,7 +756,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 01111000010xxxxxxxxx00xxxxxxxxxx
- ldurh. */
-- return 902;
-+ return 928;
- }
- }
- else
-@@ -732,7 +765,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 1x111000010xxxxxxxxx00xxxxxxxxxx
- ldur. */
-- return 905;
-+ return 931;
- }
- }
- }
-@@ -746,7 +779,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001110001x0xxxxxxxxx00xxxxxxxxxx
- ldursb. */
-- return 898;
-+ return 924;
- }
- else
- {
-@@ -754,7 +787,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 101110001x0xxxxxxxxx00xxxxxxxxxx
- ldursw. */
-- return 906;
-+ return 932;
- }
- }
- else
-@@ -765,7 +798,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 011110001x0xxxxxxxxx00xxxxxxxxxx
- ldursh. */
-- return 903;
-+ return 929;
- }
- else
- {
-@@ -773,7 +806,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 111110001x0xxxxxxxxx00xxxxxxxxxx
- prfum. */
-- return 907;
-+ return 933;
- }
- }
- }
-@@ -800,7 +833,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 00111000001xxxxx000000xxxxxxxxxx
- ldaddb. */
-- return 1006;
-+ return 1042;
- }
- else
- {
-@@ -808,7 +841,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 01111000001xxxxx000000xxxxxxxxxx
- ldaddh. */
-- return 1007;
-+ return 1043;
- }
- }
- else
-@@ -817,7 +850,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 1x111000001xxxxx000000xxxxxxxxxx
- ldadd. */
-- return 1008;
-+ return 1044;
- }
- }
- else
-@@ -830,7 +863,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 00111000101xxxxx000000xxxxxxxxxx
- ldaddab. */
-- return 1009;
-+ return 1045;
- }
- else
- {
-@@ -838,7 +871,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 01111000101xxxxx000000xxxxxxxxxx
- ldaddah. */
-- return 1012;
-+ return 1048;
- }
- }
- else
-@@ -847,7 +880,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 1x111000101xxxxx000000xxxxxxxxxx
- ldadda. */
-- return 1015;
-+ return 1051;
- }
- }
- }
-@@ -863,7 +896,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 00111000011xxxxx000000xxxxxxxxxx
- ldaddlb. */
-- return 1010;
-+ return 1046;
- }
- else
- {
-@@ -871,7 +904,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 01111000011xxxxx000000xxxxxxxxxx
- ldaddlh. */
-- return 1013;
-+ return 1049;
- }
- }
- else
-@@ -880,7 +913,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 1x111000011xxxxx000000xxxxxxxxxx
- ldaddl. */
-- return 1016;
-+ return 1052;
- }
- }
- else
-@@ -893,7 +926,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 00111000111xxxxx000000xxxxxxxxxx
- ldaddalb. */
-- return 1011;
-+ return 1047;
- }
- else
- {
-@@ -901,7 +934,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 01111000111xxxxx000000xxxxxxxxxx
- ldaddalh. */
-- return 1014;
-+ return 1050;
- }
- }
- else
-@@ -910,7 +943,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 1x111000111xxxxx000000xxxxxxxxxx
- ldaddal. */
-- return 1017;
-+ return 1053;
- }
- }
- }
-@@ -929,7 +962,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 00111000001xxxxx100000xxxxxxxxxx
- swpb. */
-- return 994;
-+ return 1030;
- }
- else
- {
-@@ -937,7 +970,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 01111000001xxxxx100000xxxxxxxxxx
- swph. */
-- return 995;
-+ return 1031;
- }
- }
- else
-@@ -946,7 +979,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 1x111000001xxxxx100000xxxxxxxxxx
- swp. */
-- return 996;
-+ return 1032;
- }
- }
- else
-@@ -959,7 +992,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 00111000101xxxxx100000xxxxxxxxxx
- swpab. */
-- return 997;
-+ return 1033;
- }
- else
- {
-@@ -967,7 +1000,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 01111000101xxxxx100000xxxxxxxxxx
- swpah. */
-- return 1000;
-+ return 1036;
- }
- }
- else
-@@ -976,7 +1009,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 1x111000101xxxxx100000xxxxxxxxxx
- swpa. */
-- return 1003;
-+ return 1039;
- }
- }
- }
-@@ -992,7 +1025,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 00111000011xxxxx100000xxxxxxxxxx
- swplb. */
-- return 998;
-+ return 1034;
- }
- else
- {
-@@ -1000,7 +1033,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 01111000011xxxxx100000xxxxxxxxxx
- swplh. */
-- return 1001;
-+ return 1037;
- }
- }
- else
-@@ -1009,7 +1042,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 1x111000011xxxxx100000xxxxxxxxxx
- swpl. */
-- return 1004;
-+ return 1040;
- }
- }
- else
-@@ -1022,7 +1055,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 00111000111xxxxx100000xxxxxxxxxx
- swpalb. */
-- return 999;
-+ return 1035;
- }
- else
- {
-@@ -1030,7 +1063,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 01111000111xxxxx100000xxxxxxxxxx
- swpalh. */
-- return 1002;
-+ return 1038;
- }
- }
- else
-@@ -1039,7 +1072,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 1x111000111xxxxx100000xxxxxxxxxx
- swpal. */
-- return 1005;
-+ return 1041;
- }
- }
- }
-@@ -1061,7 +1094,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 00111000001xxxxx010000xxxxxxxxxx
- ldsmaxb. */
-- return 1054;
-+ return 1090;
- }
- else
- {
-@@ -1069,7 +1102,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 01111000001xxxxx010000xxxxxxxxxx
- ldsmaxh. */
-- return 1055;
-+ return 1091;
- }
- }
- else
-@@ -1078,7 +1111,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 1x111000001xxxxx010000xxxxxxxxxx
- ldsmax. */
-- return 1056;
-+ return 1092;
- }
- }
- else
-@@ -1091,7 +1124,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 00111000101xxxxx010000xxxxxxxxxx
- ldsmaxab. */
-- return 1057;
-+ return 1093;
- }
- else
- {
-@@ -1099,7 +1132,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 01111000101xxxxx010000xxxxxxxxxx
- ldsmaxah. */
-- return 1060;
-+ return 1096;
- }
- }
- else
-@@ -1108,7 +1141,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 1x111000101xxxxx010000xxxxxxxxxx
- ldsmaxa. */
-- return 1063;
-+ return 1099;
- }
- }
- }
-@@ -1124,7 +1157,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 00111000011xxxxx010000xxxxxxxxxx
- ldsmaxlb. */
-- return 1058;
-+ return 1094;
- }
- else
- {
-@@ -1132,7 +1165,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 01111000011xxxxx010000xxxxxxxxxx
- ldsmaxlh. */
-- return 1061;
-+ return 1097;
- }
- }
- else
-@@ -1141,7 +1174,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 1x111000011xxxxx010000xxxxxxxxxx
- ldsmaxl. */
-- return 1064;
-+ return 1100;
- }
- }
- else
-@@ -1154,7 +1187,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 00111000111xxxxx010000xxxxxxxxxx
- ldsmaxalb. */
-- return 1059;
-+ return 1095;
- }
- else
- {
-@@ -1162,7 +1195,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 01111000111xxxxx010000xxxxxxxxxx
- ldsmaxalh. */
-- return 1062;
-+ return 1098;
- }
- }
- else
-@@ -1171,7 +1204,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 1x111000111xxxxx010000xxxxxxxxxx
- ldsmaxal. */
-- return 1065;
-+ return 1101;
- }
- }
- }
-@@ -1186,7 +1219,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 00111000xx1xxxxx110000xxxxxxxxxx
- ldaprb. */
-- return 932;
-+ return 959;
- }
- else
- {
-@@ -1194,7 +1227,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 01111000xx1xxxxx110000xxxxxxxxxx
- ldaprh. */
-- return 933;
-+ return 960;
- }
- }
- else
-@@ -1203,7 +1236,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 1x111000xx1xxxxx110000xxxxxxxxxx
- ldapr. */
-- return 934;
-+ return 961;
- }
- }
- }
-@@ -1212,132 +1245,143 @@ aarch64_opcode_lookup_1 (uint32_t word)
- {
- if (((word >> 14) & 0x1) == 0)
- {
-- if (((word >> 22) & 0x1) == 0)
-+ if (((word >> 15) & 0x1) == 0)
- {
-- if (((word >> 23) & 0x1) == 0)
-+ if (((word >> 22) & 0x1) == 0)
- {
-- if (((word >> 31) & 0x1) == 0)
-+ if (((word >> 23) & 0x1) == 0)
- {
-- if (((word >> 30) & 0x1) == 0)
-+ if (((word >> 31) & 0x1) == 0)
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 00111000001xxxxxx01000xxxxxxxxxx
-- ldeorb. */
-- return 1030;
-+ if (((word >> 30) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 00111000001xxxxx001000xxxxxxxxxx
-+ ldeorb. */
-+ return 1066;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 01111000001xxxxx001000xxxxxxxxxx
-+ ldeorh. */
-+ return 1067;
-+ }
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
-- 01111000001xxxxxx01000xxxxxxxxxx
-- ldeorh. */
-- return 1031;
-+ 1x111000001xxxxx001000xxxxxxxxxx
-+ ldeor. */
-+ return 1068;
- }
- }
- else
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 1x111000001xxxxxx01000xxxxxxxxxx
-- ldeor. */
-- return 1032;
-- }
-- }
-- else
-- {
-- if (((word >> 31) & 0x1) == 0)
-- {
-- if (((word >> 30) & 0x1) == 0)
-+ if (((word >> 31) & 0x1) == 0)
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 00111000101xxxxxx01000xxxxxxxxxx
-- ldeorab. */
-- return 1033;
-+ if (((word >> 30) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 00111000101xxxxx001000xxxxxxxxxx
-+ ldeorab. */
-+ return 1069;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 01111000101xxxxx001000xxxxxxxxxx
-+ ldeorah. */
-+ return 1072;
-+ }
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
-- 01111000101xxxxxx01000xxxxxxxxxx
-- ldeorah. */
-- return 1036;
-+ 1x111000101xxxxx001000xxxxxxxxxx
-+ ldeora. */
-+ return 1075;
- }
- }
-- else
-- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 1x111000101xxxxxx01000xxxxxxxxxx
-- ldeora. */
-- return 1039;
-- }
- }
-- }
-- else
-- {
-- if (((word >> 23) & 0x1) == 0)
-+ else
- {
-- if (((word >> 31) & 0x1) == 0)
-+ if (((word >> 23) & 0x1) == 0)
- {
-- if (((word >> 30) & 0x1) == 0)
-+ if (((word >> 31) & 0x1) == 0)
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 00111000011xxxxxx01000xxxxxxxxxx
-- ldeorlb. */
-- return 1034;
-+ if (((word >> 30) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 00111000011xxxxx001000xxxxxxxxxx
-+ ldeorlb. */
-+ return 1070;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 01111000011xxxxx001000xxxxxxxxxx
-+ ldeorlh. */
-+ return 1073;
-+ }
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
-- 01111000011xxxxxx01000xxxxxxxxxx
-- ldeorlh. */
-- return 1037;
-+ 1x111000011xxxxx001000xxxxxxxxxx
-+ ldeorl. */
-+ return 1076;
- }
- }
- else
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 1x111000011xxxxxx01000xxxxxxxxxx
-- ldeorl. */
-- return 1040;
-- }
-- }
-- else
-- {
-- if (((word >> 31) & 0x1) == 0)
-- {
-- if (((word >> 30) & 0x1) == 0)
-+ if (((word >> 31) & 0x1) == 0)
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 00111000111xxxxxx01000xxxxxxxxxx
-- ldeoralb. */
-- return 1035;
-+ if (((word >> 30) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 00111000111xxxxx001000xxxxxxxxxx
-+ ldeoralb. */
-+ return 1071;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 01111000111xxxxx001000xxxxxxxxxx
-+ ldeoralh. */
-+ return 1074;
-+ }
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
-- 01111000111xxxxxx01000xxxxxxxxxx
-- ldeoralh. */
-- return 1038;
-+ 1x111000111xxxxx001000xxxxxxxxxx
-+ ldeoral. */
-+ return 1077;
- }
- }
-- else
-- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 1x111000111xxxxxx01000xxxxxxxxxx
-- ldeoral. */
-- return 1041;
-- }
- }
- }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ xx111000xx1xxxxx101000xxxxxxxxxx
-+ st64bv0. */
-+ return 994;
-+ }
- }
- else
- {
-@@ -1353,7 +1397,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 00111000001xxxxxx11000xxxxxxxxxx
- ldumaxb. */
-- return 1078;
-+ return 1114;
- }
- else
- {
-@@ -1361,7 +1405,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 01111000001xxxxxx11000xxxxxxxxxx
- ldumaxh. */
-- return 1079;
-+ return 1115;
- }
- }
- else
-@@ -1370,7 +1414,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 1x111000001xxxxxx11000xxxxxxxxxx
- ldumax. */
-- return 1080;
-+ return 1116;
- }
- }
- else
-@@ -1383,7 +1427,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 00111000101xxxxxx11000xxxxxxxxxx
- ldumaxab. */
-- return 1081;
-+ return 1117;
- }
- else
- {
-@@ -1391,7 +1435,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 01111000101xxxxxx11000xxxxxxxxxx
- ldumaxah. */
-- return 1084;
-+ return 1120;
- }
- }
- else
-@@ -1400,7 +1444,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 1x111000101xxxxxx11000xxxxxxxxxx
- ldumaxa. */
-- return 1087;
-+ return 1123;
- }
- }
- }
-@@ -1416,7 +1460,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 00111000011xxxxxx11000xxxxxxxxxx
- ldumaxlb. */
-- return 1082;
-+ return 1118;
- }
- else
- {
-@@ -1424,7 +1468,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 01111000011xxxxxx11000xxxxxxxxxx
- ldumaxlh. */
-- return 1085;
-+ return 1121;
- }
- }
- else
-@@ -1433,7 +1477,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 1x111000011xxxxxx11000xxxxxxxxxx
- ldumaxl. */
-- return 1088;
-+ return 1124;
- }
- }
- else
-@@ -1446,7 +1490,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 00111000111xxxxxx11000xxxxxxxxxx
- ldumaxalb. */
-- return 1083;
-+ return 1119;
- }
- else
- {
-@@ -1454,7 +1498,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 01111000111xxxxxx11000xxxxxxxxxx
- ldumaxalh. */
-- return 1086;
-+ return 1122;
- }
- }
- else
-@@ -1463,7 +1507,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 1x111000111xxxxxx11000xxxxxxxxxx
- ldumaxal. */
-- return 1089;
-+ return 1125;
- }
- }
- }
-@@ -1476,393 +1520,426 @@ aarch64_opcode_lookup_1 (uint32_t word)
- {
- if (((word >> 14) & 0x1) == 0)
- {
-- if (((word >> 22) & 0x1) == 0)
-+ if (((word >> 15) & 0x1) == 0)
- {
-- if (((word >> 23) & 0x1) == 0)
-+ if (((word >> 22) & 0x1) == 0)
- {
-- if (((word >> 31) & 0x1) == 0)
-+ if (((word >> 23) & 0x1) == 0)
- {
-- if (((word >> 30) & 0x1) == 0)
-+ if (((word >> 31) & 0x1) == 0)
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 00111000001xxxxxx00100xxxxxxxxxx
-- ldclrb. */
-- return 1018;
-+ if (((word >> 30) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 00111000001xxxxx000100xxxxxxxxxx
-+ ldclrb. */
-+ return 1054;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 01111000001xxxxx000100xxxxxxxxxx
-+ ldclrh. */
-+ return 1055;
-+ }
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
-- 01111000001xxxxxx00100xxxxxxxxxx
-- ldclrh. */
-- return 1019;
-+ 1x111000001xxxxx000100xxxxxxxxxx
-+ ldclr. */
-+ return 1056;
- }
- }
- else
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 1x111000001xxxxxx00100xxxxxxxxxx
-- ldclr. */
-- return 1020;
-- }
-- }
-- else
-- {
-- if (((word >> 31) & 0x1) == 0)
-- {
-- if (((word >> 30) & 0x1) == 0)
-+ if (((word >> 31) & 0x1) == 0)
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 00111000101xxxxxx00100xxxxxxxxxx
-- ldclrab. */
-- return 1021;
-+ if (((word >> 30) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 00111000101xxxxx000100xxxxxxxxxx
-+ ldclrab. */
-+ return 1057;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 01111000101xxxxx000100xxxxxxxxxx
-+ ldclrah. */
-+ return 1060;
-+ }
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
-- 01111000101xxxxxx00100xxxxxxxxxx
-- ldclrah. */
-- return 1024;
-+ 1x111000101xxxxx000100xxxxxxxxxx
-+ ldclra. */
-+ return 1063;
- }
- }
-- else
-- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 1x111000101xxxxxx00100xxxxxxxxxx
-- ldclra. */
-- return 1027;
-- }
- }
-- }
-- else
-- {
-- if (((word >> 23) & 0x1) == 0)
-+ else
- {
-- if (((word >> 31) & 0x1) == 0)
-+ if (((word >> 23) & 0x1) == 0)
- {
-- if (((word >> 30) & 0x1) == 0)
-+ if (((word >> 31) & 0x1) == 0)
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 00111000011xxxxxx00100xxxxxxxxxx
-- ldclrlb. */
-- return 1022;
-+ if (((word >> 30) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 00111000011xxxxx000100xxxxxxxxxx
-+ ldclrlb. */
-+ return 1058;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 01111000011xxxxx000100xxxxxxxxxx
-+ ldclrlh. */
-+ return 1061;
-+ }
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
-- 01111000011xxxxxx00100xxxxxxxxxx
-- ldclrlh. */
-- return 1025;
-+ 1x111000011xxxxx000100xxxxxxxxxx
-+ ldclrl. */
-+ return 1064;
- }
- }
- else
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 1x111000011xxxxxx00100xxxxxxxxxx
-- ldclrl. */
-- return 1028;
-- }
-- }
-- else
-- {
-- if (((word >> 31) & 0x1) == 0)
-- {
-- if (((word >> 30) & 0x1) == 0)
-+ if (((word >> 31) & 0x1) == 0)
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 00111000111xxxxxx00100xxxxxxxxxx
-- ldclralb. */
-- return 1023;
-+ if (((word >> 30) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 00111000111xxxxx000100xxxxxxxxxx
-+ ldclralb. */
-+ return 1059;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 01111000111xxxxx000100xxxxxxxxxx
-+ ldclralh. */
-+ return 1062;
-+ }
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
-- 01111000111xxxxxx00100xxxxxxxxxx
-- ldclralh. */
-- return 1026;
-+ 1x111000111xxxxx000100xxxxxxxxxx
-+ ldclral. */
-+ return 1065;
- }
- }
-- else
-- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 1x111000111xxxxxx00100xxxxxxxxxx
-- ldclral. */
-- return 1029;
-- }
- }
- }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ xx111000xx1xxxxx100100xxxxxxxxxx
-+ st64b. */
-+ return 992;
-+ }
- }
- else
- {
-- if (((word >> 22) & 0x1) == 0)
-+ if (((word >> 15) & 0x1) == 0)
- {
-- if (((word >> 23) & 0x1) == 0)
-+ if (((word >> 22) & 0x1) == 0)
- {
-- if (((word >> 31) & 0x1) == 0)
-+ if (((word >> 23) & 0x1) == 0)
- {
-- if (((word >> 30) & 0x1) == 0)
-+ if (((word >> 31) & 0x1) == 0)
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 00111000001xxxxxx10100xxxxxxxxxx
-- ldsminb. */
-- return 1066;
-+ if (((word >> 30) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 00111000001xxxxx010100xxxxxxxxxx
-+ ldsminb. */
-+ return 1102;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 01111000001xxxxx010100xxxxxxxxxx
-+ ldsminh. */
-+ return 1103;
-+ }
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
-- 01111000001xxxxxx10100xxxxxxxxxx
-- ldsminh. */
-- return 1067;
-+ 1x111000001xxxxx010100xxxxxxxxxx
-+ ldsmin. */
-+ return 1104;
- }
- }
- else
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 1x111000001xxxxxx10100xxxxxxxxxx
-- ldsmin. */
-- return 1068;
-- }
-- }
-- else
-- {
-- if (((word >> 31) & 0x1) == 0)
-- {
-- if (((word >> 30) & 0x1) == 0)
-+ if (((word >> 31) & 0x1) == 0)
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 00111000101xxxxxx10100xxxxxxxxxx
-- ldsminab. */
-- return 1069;
-+ if (((word >> 30) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 00111000101xxxxx010100xxxxxxxxxx
-+ ldsminab. */
-+ return 1105;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 01111000101xxxxx010100xxxxxxxxxx
-+ ldsminah. */
-+ return 1108;
-+ }
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
-- 01111000101xxxxxx10100xxxxxxxxxx
-- ldsminah. */
-- return 1072;
-+ 1x111000101xxxxx010100xxxxxxxxxx
-+ ldsmina. */
-+ return 1111;
- }
- }
-- else
-- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 1x111000101xxxxxx10100xxxxxxxxxx
-- ldsmina. */
-- return 1075;
-- }
- }
-- }
-- else
-- {
-- if (((word >> 23) & 0x1) == 0)
-+ else
- {
-- if (((word >> 31) & 0x1) == 0)
-+ if (((word >> 23) & 0x1) == 0)
- {
-- if (((word >> 30) & 0x1) == 0)
-+ if (((word >> 31) & 0x1) == 0)
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 00111000011xxxxxx10100xxxxxxxxxx
-- ldsminlb. */
-- return 1070;
-+ if (((word >> 30) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 00111000011xxxxx010100xxxxxxxxxx
-+ ldsminlb. */
-+ return 1106;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 01111000011xxxxx010100xxxxxxxxxx
-+ ldsminlh. */
-+ return 1109;
-+ }
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
-- 01111000011xxxxxx10100xxxxxxxxxx
-- ldsminlh. */
-- return 1073;
-+ 1x111000011xxxxx010100xxxxxxxxxx
-+ ldsminl. */
-+ return 1112;
- }
- }
- else
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 1x111000011xxxxxx10100xxxxxxxxxx
-- ldsminl. */
-- return 1076;
-- }
-- }
-- else
-- {
-- if (((word >> 31) & 0x1) == 0)
-- {
-- if (((word >> 30) & 0x1) == 0)
-+ if (((word >> 31) & 0x1) == 0)
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 00111000111xxxxxx10100xxxxxxxxxx
-- ldsminalb. */
-- return 1071;
-+ if (((word >> 30) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 00111000111xxxxx010100xxxxxxxxxx
-+ ldsminalb. */
-+ return 1107;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 01111000111xxxxx010100xxxxxxxxxx
-+ ldsminalh. */
-+ return 1110;
-+ }
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
-- 01111000111xxxxxx10100xxxxxxxxxx
-- ldsminalh. */
-- return 1074;
-+ 1x111000111xxxxx010100xxxxxxxxxx
-+ ldsminal. */
-+ return 1113;
- }
- }
-- else
-- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 1x111000111xxxxxx10100xxxxxxxxxx
-- ldsminal. */
-- return 1077;
-- }
- }
- }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ xx111000xx1xxxxx110100xxxxxxxxxx
-+ ld64b. */
-+ return 991;
-+ }
- }
- }
- else
- {
- if (((word >> 14) & 0x1) == 0)
- {
-- if (((word >> 22) & 0x1) == 0)
-+ if (((word >> 15) & 0x1) == 0)
- {
-- if (((word >> 23) & 0x1) == 0)
-+ if (((word >> 22) & 0x1) == 0)
- {
-- if (((word >> 31) & 0x1) == 0)
-+ if (((word >> 23) & 0x1) == 0)
- {
-- if (((word >> 30) & 0x1) == 0)
-+ if (((word >> 31) & 0x1) == 0)
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 00111000001xxxxxx01100xxxxxxxxxx
-- ldsetb. */
-- return 1042;
-+ if (((word >> 30) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 00111000001xxxxx001100xxxxxxxxxx
-+ ldsetb. */
-+ return 1078;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 01111000001xxxxx001100xxxxxxxxxx
-+ ldseth. */
-+ return 1079;
-+ }
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
-- 01111000001xxxxxx01100xxxxxxxxxx
-- ldseth. */
-- return 1043;
-+ 1x111000001xxxxx001100xxxxxxxxxx
-+ ldset. */
-+ return 1080;
- }
- }
- else
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 1x111000001xxxxxx01100xxxxxxxxxx
-- ldset. */
-- return 1044;
-- }
-- }
-- else
-- {
-- if (((word >> 31) & 0x1) == 0)
-- {
-- if (((word >> 30) & 0x1) == 0)
-+ if (((word >> 31) & 0x1) == 0)
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 00111000101xxxxxx01100xxxxxxxxxx
-- ldsetab. */
-- return 1045;
-+ if (((word >> 30) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 00111000101xxxxx001100xxxxxxxxxx
-+ ldsetab. */
-+ return 1081;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 01111000101xxxxx001100xxxxxxxxxx
-+ ldsetah. */
-+ return 1084;
-+ }
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
-- 01111000101xxxxxx01100xxxxxxxxxx
-- ldsetah. */
-- return 1048;
-+ 1x111000101xxxxx001100xxxxxxxxxx
-+ ldseta. */
-+ return 1087;
- }
- }
-- else
-- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 1x111000101xxxxxx01100xxxxxxxxxx
-- ldseta. */
-- return 1051;
-- }
- }
-- }
-- else
-- {
-- if (((word >> 23) & 0x1) == 0)
-+ else
- {
-- if (((word >> 31) & 0x1) == 0)
-+ if (((word >> 23) & 0x1) == 0)
- {
-- if (((word >> 30) & 0x1) == 0)
-+ if (((word >> 31) & 0x1) == 0)
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 00111000011xxxxxx01100xxxxxxxxxx
-- ldsetlb. */
-- return 1046;
-+ if (((word >> 30) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 00111000011xxxxx001100xxxxxxxxxx
-+ ldsetlb. */
-+ return 1082;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 01111000011xxxxx001100xxxxxxxxxx
-+ ldsetlh. */
-+ return 1085;
-+ }
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
-- 01111000011xxxxxx01100xxxxxxxxxx
-- ldsetlh. */
-- return 1049;
-+ 1x111000011xxxxx001100xxxxxxxxxx
-+ ldsetl. */
-+ return 1088;
- }
- }
- else
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 1x111000011xxxxxx01100xxxxxxxxxx
-- ldsetl. */
-- return 1052;
-- }
-- }
-- else
-- {
-- if (((word >> 31) & 0x1) == 0)
-- {
-- if (((word >> 30) & 0x1) == 0)
-+ if (((word >> 31) & 0x1) == 0)
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 00111000111xxxxxx01100xxxxxxxxxx
-- ldsetalb. */
-- return 1047;
-+ if (((word >> 30) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 00111000111xxxxx001100xxxxxxxxxx
-+ ldsetalb. */
-+ return 1083;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 01111000111xxxxx001100xxxxxxxxxx
-+ ldsetalh. */
-+ return 1086;
-+ }
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
-- 01111000111xxxxxx01100xxxxxxxxxx
-- ldsetalh. */
-- return 1050;
-+ 1x111000111xxxxx001100xxxxxxxxxx
-+ ldsetal. */
-+ return 1089;
- }
- }
-- else
-- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 1x111000111xxxxxx01100xxxxxxxxxx
-- ldsetal. */
-- return 1053;
-- }
- }
- }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ xx111000xx1xxxxx101100xxxxxxxxxx
-+ st64bv. */
-+ return 993;
-+ }
- }
- else
- {
-@@ -1878,7 +1955,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 00111000001xxxxxx11100xxxxxxxxxx
- lduminb. */
-- return 1090;
-+ return 1126;
- }
- else
- {
-@@ -1886,7 +1963,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 01111000001xxxxxx11100xxxxxxxxxx
- lduminh. */
-- return 1091;
-+ return 1127;
- }
- }
- else
-@@ -1895,7 +1972,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 1x111000001xxxxxx11100xxxxxxxxxx
- ldumin. */
-- return 1092;
-+ return 1128;
- }
- }
- else
-@@ -1908,7 +1985,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 00111000101xxxxxx11100xxxxxxxxxx
- lduminab. */
-- return 1093;
-+ return 1129;
- }
- else
- {
-@@ -1916,7 +1993,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 01111000101xxxxxx11100xxxxxxxxxx
- lduminah. */
-- return 1096;
-+ return 1132;
- }
- }
- else
-@@ -1925,7 +2002,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 1x111000101xxxxxx11100xxxxxxxxxx
- ldumina. */
-- return 1099;
-+ return 1135;
- }
- }
- }
-@@ -1941,7 +2018,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 00111000011xxxxxx11100xxxxxxxxxx
- lduminlb. */
-- return 1094;
-+ return 1130;
- }
- else
- {
-@@ -1949,7 +2026,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 01111000011xxxxxx11100xxxxxxxxxx
- lduminlh. */
-- return 1097;
-+ return 1133;
- }
- }
- else
-@@ -1958,7 +2035,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 1x111000011xxxxxx11100xxxxxxxxxx
- lduminl. */
-- return 1100;
-+ return 1136;
- }
- }
- else
-@@ -1971,7 +2048,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 00111000111xxxxxx11100xxxxxxxxxx
- lduminalb. */
-- return 1095;
-+ return 1131;
- }
- else
- {
-@@ -1979,7 +2056,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 01111000111xxxxxx11100xxxxxxxxxx
- lduminalh. */
-- return 1098;
-+ return 1134;
- }
- }
- else
-@@ -1988,7 +2065,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 1x111000111xxxxxx11100xxxxxxxxxx
- lduminal. */
-- return 1101;
-+ return 1137;
- }
- }
- }
-@@ -2013,7 +2090,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 00111000000xxxxxxxxx10xxxxxxxxxx
- sttrb. */
-- return 887;
-+ return 913;
- }
- else
- {
-@@ -2021,7 +2098,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 01111000000xxxxxxxxx10xxxxxxxxxx
- sttrh. */
-- return 890;
-+ return 916;
- }
- }
- else
-@@ -2030,7 +2107,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 1x111000000xxxxxxxxx10xxxxxxxxxx
- sttr. */
-- return 893;
-+ return 919;
- }
- }
- else
-@@ -2043,7 +2120,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 00111000010xxxxxxxxx10xxxxxxxxxx
- ldtrb. */
-- return 888;
-+ return 914;
- }
- else
- {
-@@ -2051,7 +2128,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 01111000010xxxxxxxxx10xxxxxxxxxx
- ldtrh. */
-- return 891;
-+ return 917;
- }
- }
- else
-@@ -2060,7 +2137,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 1x111000010xxxxxxxxx10xxxxxxxxxx
- ldtr. */
-- return 894;
-+ return 920;
- }
- }
- }
-@@ -2074,7 +2151,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001110001x0xxxxxxxxx10xxxxxxxxxx
- ldtrsb. */
-- return 889;
-+ return 915;
- }
- else
- {
-@@ -2082,7 +2159,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 101110001x0xxxxxxxxx10xxxxxxxxxx
- ldtrsw. */
-- return 895;
-+ return 921;
- }
- }
- else
-@@ -2091,7 +2168,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x11110001x0xxxxxxxxx10xxxxxxxxxx
- ldtrsh. */
-- return 892;
-+ return 918;
- }
- }
- }
-@@ -2109,7 +2186,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 00111000001xxxxxxxxx10xxxxxxxxxx
- strb. */
-- return 875;
-+ return 901;
- }
- else
- {
-@@ -2117,7 +2194,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 01111000001xxxxxxxxx10xxxxxxxxxx
- strh. */
-- return 880;
-+ return 906;
- }
- }
- else
-@@ -2126,7 +2203,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 1x111000001xxxxxxxxx10xxxxxxxxxx
- str. */
-- return 883;
-+ return 909;
- }
- }
- else
-@@ -2139,7 +2216,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 00111000011xxxxxxxxx10xxxxxxxxxx
- ldrb. */
-- return 876;
-+ return 902;
- }
- else
- {
-@@ -2147,7 +2224,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 01111000011xxxxxxxxx10xxxxxxxxxx
- ldrh. */
-- return 881;
-+ return 907;
- }
- }
- else
-@@ -2156,7 +2233,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 1x111000011xxxxxxxxx10xxxxxxxxxx
- ldr. */
-- return 884;
-+ return 910;
- }
- }
- }
-@@ -2170,7 +2247,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001110001x1xxxxxxxxx10xxxxxxxxxx
- ldrsb. */
-- return 877;
-+ return 903;
- }
- else
- {
-@@ -2178,7 +2255,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 101110001x1xxxxxxxxx10xxxxxxxxxx
- ldrsw. */
-- return 885;
-+ return 911;
- }
- }
- else
-@@ -2189,7 +2266,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 011110001x1xxxxxxxxx10xxxxxxxxxx
- ldrsh. */
-- return 882;
-+ return 908;
- }
- else
- {
-@@ -2197,7 +2274,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 111110001x1xxxxxxxxx10xxxxxxxxxx
- prfm. */
-- return 886;
-+ return 912;
- }
- }
- }
-@@ -2220,7 +2297,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 00111000000xxxxxxxxxx1xxxxxxxxxx
- strb. */
-- return 852;
-+ return 870;
- }
- else
- {
-@@ -2228,7 +2305,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 01111000000xxxxxxxxxx1xxxxxxxxxx
- strh. */
-- return 857;
-+ return 875;
- }
- }
- else
-@@ -2237,7 +2314,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 1x111000000xxxxxxxxxx1xxxxxxxxxx
- str. */
-- return 860;
-+ return 878;
- }
- }
- else
-@@ -2250,7 +2327,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 00111000010xxxxxxxxxx1xxxxxxxxxx
- ldrb. */
-- return 853;
-+ return 871;
- }
- else
- {
-@@ -2258,7 +2335,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 01111000010xxxxxxxxxx1xxxxxxxxxx
- ldrh. */
-- return 858;
-+ return 876;
- }
- }
- else
-@@ -2267,7 +2344,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 1x111000010xxxxxxxxxx1xxxxxxxxxx
- ldr. */
-- return 861;
-+ return 879;
- }
- }
- }
-@@ -2281,7 +2358,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001110001x0xxxxxxxxxx1xxxxxxxxxx
- ldrsb. */
-- return 854;
-+ return 872;
- }
- else
- {
-@@ -2289,7 +2366,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 101110001x0xxxxxxxxxx1xxxxxxxxxx
- ldrsw. */
-- return 862;
-+ return 880;
- }
- }
- else
-@@ -2298,7 +2375,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x11110001x0xxxxxxxxxx1xxxxxxxxxx
- ldrsh. */
-- return 859;
-+ return 877;
- }
- }
- }
-@@ -2310,7 +2387,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx1110000x1xxxxxxxxxx1xxxxxxxxxx
- ldraa. */
-- return 908;
-+ return 935;
- }
- else
- {
-@@ -2318,7 +2395,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx1110001x1xxxxxxxxxx1xxxxxxxxxx
- ldrab. */
-- return 909;
-+ return 936;
- }
- }
- }
-@@ -2332,43 +2409,76 @@ aarch64_opcode_lookup_1 (uint32_t word)
- {
- if (((word >> 29) & 0x1) == 0)
- {
-- if (((word >> 30) & 0x1) == 0)
-+ if (((word >> 10) & 0x1) == 0)
- {
-- if (((word >> 31) & 0x1) == 0)
-+ if (((word >> 11) & 0x1) == 0)
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 0001100100xxxxxxxxxxxxxxxxxxxxxx
-- stlurb. */
-- return 2028;
-+ if (((word >> 21) & 0x1) == 0)
-+ {
-+ if (((word >> 30) & 0x1) == 0)
-+ {
-+ if (((word >> 31) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 00011001000xxxxxxxxx00xxxxxxxxxx
-+ stlurb. */
-+ return 2388;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 10011001000xxxxxxxxx00xxxxxxxxxx
-+ stlur. */
-+ return 2396;
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 31) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 01011001000xxxxxxxxx00xxxxxxxxxx
-+ stlurh. */
-+ return 2392;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 11011001000xxxxxxxxx00xxxxxxxxxx
-+ stlur. */
-+ return 2399;
-+ }
-+ }
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ xx011001001xxxxxxxxx00xxxxxxxxxx
-+ stzgm. */
-+ return 964;
-+ }
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
-- 1001100100xxxxxxxxxxxxxxxxxxxxxx
-- stlur. */
-- return 2036;
-+ xx01100100xxxxxxxxxx10xxxxxxxxxx
-+ stg. */
-+ return 881;
- }
- }
- else
- {
-- if (((word >> 31) & 0x1) == 0)
-- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 0101100100xxxxxxxxxxxxxxxxxxxxxx
-- stlurh. */
-- return 2032;
-- }
-- else
-- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 1101100100xxxxxxxxxxxxxxxxxxxxxx
-- stlur. */
-- return 2039;
-- }
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ xx01100100xxxxxxxxxxx1xxxxxxxxxx
-+ stg. */
-+ return 885;
- }
- }
- else
-@@ -2381,7 +2491,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0011100100xxxxxxxxxxxxxxxxxxxxxx
- strb. */
-- return 863;
-+ return 889;
- }
- else
- {
-@@ -2389,7 +2499,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0111100100xxxxxxxxxxxxxxxxxxxxxx
- strh. */
-- return 868;
-+ return 894;
- }
- }
- else
-@@ -2398,7 +2508,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 1x11100100xxxxxxxxxxxxxxxxxxxxxx
- str. */
-- return 871;
-+ return 897;
- }
- }
- }
-@@ -2406,43 +2516,76 @@ aarch64_opcode_lookup_1 (uint32_t word)
- {
- if (((word >> 29) & 0x1) == 0)
- {
-- if (((word >> 30) & 0x1) == 0)
-+ if (((word >> 10) & 0x1) == 0)
- {
-- if (((word >> 31) & 0x1) == 0)
-+ if (((word >> 11) & 0x1) == 0)
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 0001100101xxxxxxxxxxxxxxxxxxxxxx
-- ldapurb. */
-- return 2029;
-+ if (((word >> 21) & 0x1) == 0)
-+ {
-+ if (((word >> 30) & 0x1) == 0)
-+ {
-+ if (((word >> 31) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 00011001010xxxxxxxxx00xxxxxxxxxx
-+ ldapurb. */
-+ return 2389;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 10011001010xxxxxxxxx00xxxxxxxxxx
-+ ldapur. */
-+ return 2397;
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 31) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 01011001010xxxxxxxxx00xxxxxxxxxx
-+ ldapurh. */
-+ return 2393;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 11011001010xxxxxxxxx00xxxxxxxxxx
-+ ldapur. */
-+ return 2400;
-+ }
-+ }
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ xx011001011xxxxxxxxx00xxxxxxxxxx
-+ ldg. */
-+ return 934;
-+ }
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
-- 1001100101xxxxxxxxxxxxxxxxxxxxxx
-- ldapur. */
-- return 2037;
-+ xx01100101xxxxxxxxxx10xxxxxxxxxx
-+ stzg. */
-+ return 882;
- }
- }
- else
- {
-- if (((word >> 31) & 0x1) == 0)
-- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 0101100101xxxxxxxxxxxxxxxxxxxxxx
-- ldapurh. */
-- return 2033;
-- }
-- else
-- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 1101100101xxxxxxxxxxxxxxxxxxxxxx
-- ldapur. */
-- return 2040;
-- }
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ xx01100101xxxxxxxxxxx1xxxxxxxxxx
-+ stzg. */
-+ return 886;
- }
- }
- else
-@@ -2455,7 +2598,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0011100101xxxxxxxxxxxxxxxxxxxxxx
- ldrb. */
-- return 864;
-+ return 890;
- }
- else
- {
-@@ -2463,7 +2606,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0111100101xxxxxxxxxxxxxxxxxxxxxx
- ldrh. */
-- return 869;
-+ return 895;
- }
- }
- else
-@@ -2472,7 +2615,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 1x11100101xxxxxxxxxxxxxxxxxxxxxx
- ldr. */
-- return 872;
-+ return 898;
- }
- }
- }
-@@ -2481,53 +2624,119 @@ aarch64_opcode_lookup_1 (uint32_t word)
- {
- if (((word >> 29) & 0x1) == 0)
- {
-- if (((word >> 22) & 0x1) == 0)
-+ if (((word >> 10) & 0x1) == 0)
- {
-- if (((word >> 30) & 0x1) == 0)
-+ if (((word >> 11) & 0x1) == 0)
- {
-- if (((word >> 31) & 0x1) == 0)
-+ if (((word >> 21) & 0x1) == 0)
-+ {
-+ if (((word >> 22) & 0x1) == 0)
-+ {
-+ if (((word >> 30) & 0x1) == 0)
-+ {
-+ if (((word >> 31) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 00011001100xxxxxxxxx00xxxxxxxxxx
-+ ldapursb. */
-+ return 2391;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 10011001100xxxxxxxxx00xxxxxxxxxx
-+ ldapursw. */
-+ return 2398;
-+ }
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ x1011001100xxxxxxxxx00xxxxxxxxxx
-+ ldapursh. */
-+ return 2395;
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 30) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ x0011001110xxxxxxxxx00xxxxxxxxxx
-+ ldapursb. */
-+ return 2390;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ x1011001110xxxxxxxxx00xxxxxxxxxx
-+ ldapursh. */
-+ return 2394;
-+ }
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 22) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ xx011001101xxxxxxxxx00xxxxxxxxxx
-+ stgm. */
-+ return 963;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ xx011001111xxxxxxxxx00xxxxxxxxxx
-+ ldgm. */
-+ return 962;
-+ }
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 22) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
-- 0001100110xxxxxxxxxxxxxxxxxxxxxx
-- ldapursb. */
-- return 2031;
-+ xx01100110xxxxxxxxxx10xxxxxxxxxx
-+ st2g. */
-+ return 883;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
-- 1001100110xxxxxxxxxxxxxxxxxxxxxx
-- ldapursw. */
-- return 2038;
-+ xx01100111xxxxxxxxxx10xxxxxxxxxx
-+ stz2g. */
-+ return 884;
- }
- }
-- else
-- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- x101100110xxxxxxxxxxxxxxxxxxxxxx
-- ldapursh. */
-- return 2035;
-- }
- }
- else
- {
-- if (((word >> 30) & 0x1) == 0)
-+ if (((word >> 22) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
-- x001100111xxxxxxxxxxxxxxxxxxxxxx
-- ldapursb. */
-- return 2030;
-+ xx01100110xxxxxxxxxxx1xxxxxxxxxx
-+ st2g. */
-+ return 887;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
-- x101100111xxxxxxxxxxxxxxxxxxxxxx
-- ldapursh. */
-- return 2034;
-+ xx01100111xxxxxxxxxxx1xxxxxxxxxx
-+ stz2g. */
-+ return 888;
- }
- }
- }
-@@ -2541,7 +2750,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001110011xxxxxxxxxxxxxxxxxxxxxxx
- ldrsb. */
-- return 865;
-+ return 891;
- }
- else
- {
-@@ -2549,7 +2758,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 101110011xxxxxxxxxxxxxxxxxxxxxxx
- ldrsw. */
-- return 873;
-+ return 899;
- }
- }
- else
-@@ -2560,7 +2769,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 011110011xxxxxxxxxxxxxxxxxxxxxxx
- ldrsh. */
-- return 870;
-+ return 896;
- }
- else
- {
-@@ -2568,7 +2777,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 111110011xxxxxxxxxxxxxxxxxxxxxxx
- prfm. */
-- return 874;
-+ return 900;
- }
- }
- }
-@@ -2593,7 +2802,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x00x00100xxxxxxxxxxxxxxxxxxxxxxx
- and. */
-- return 959;
-+ return 995;
- }
- else
- {
-@@ -2601,7 +2810,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x10x00100xxxxxxxxxxxxxxxxxxxxxxx
- eor. */
-- return 963;
-+ return 999;
- }
- }
- else
-@@ -2612,7 +2821,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x01x00100xxxxxxxxxxxxxxxxxxxxxxx
- orr. */
-- return 961;
-+ return 997;
- }
- else
- {
-@@ -2620,7 +2829,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x11x00100xxxxxxxxxxxxxxxxxxxxxxx
- ands. */
-- return 964;
-+ return 1000;
- }
- }
- }
-@@ -2634,7 +2843,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x00x00101xxxxxxxxxxxxxxxxxxxxxxx
- movn. */
-- return 1150;
-+ return 1186;
- }
- else
- {
-@@ -2642,7 +2851,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x10x00101xxxxxxxxxxxxxxxxxxxxxxx
- movz. */
-- return 1152;
-+ return 1188;
- }
- }
- else
-@@ -2651,7 +2860,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx1x00101xxxxxxxxxxxxxxxxxxxxxxx
- movk. */
-- return 1154;
-+ return 1190;
- }
- }
- }
-@@ -2669,7 +2878,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x0001010xx0xxxxxxxxxxxxxxxxxxxxx
- and. */
-- return 966;
-+ return 1002;
- }
- else
- {
-@@ -2677,7 +2886,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1001010xx0xxxxxxxxxxxxxxxxxxxxx
- eor. */
-- return 973;
-+ return 1009;
- }
- }
- else
-@@ -2688,7 +2897,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x0101010xx0xxxxxxxxxxxxxxxxxxxxx
- orr. */
-- return 968;
-+ return 1004;
- }
- else
- {
-@@ -2696,7 +2905,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1101010xx0xxxxxxxxxxxxxxxxxxxxx
- ands. */
-- return 975;
-+ return 1011;
- }
- }
- }
-@@ -2757,7 +2966,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x0x11010100xxxxxxxxx00xxxxxxxxxx
- csel. */
-- return 656;
-+ return 662;
- }
- else
- {
-@@ -2765,7 +2974,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1x11010100xxxxxxxxx00xxxxxxxxxx
- csinv. */
-- return 660;
-+ return 666;
- }
- }
- }
-@@ -2779,7 +2988,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x0x11010010xxxxxxxxx00xxxxxxxxxx
- ccmn. */
-- return 654;
-+ return 660;
- }
- else
- {
-@@ -2787,7 +2996,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1x11010010xxxxxxxxx00xxxxxxxxxx
- ccmp. */
-- return 655;
-+ return 661;
- }
- }
- else
-@@ -2798,21 +3007,43 @@ aarch64_opcode_lookup_1 (uint32_t word)
- {
- if (((word >> 14) & 0x1) == 0)
- {
-- if (((word >> 16) & 0x1) == 0)
-+ if (((word >> 29) & 0x1) == 0)
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- xxx11010110xxxx0x00000xxxxxxxxxx
-- rbit. */
-- return 679;
-+ if (((word >> 30) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ x0011010110xxxxxx00000xxxxxxxxxx
-+ subp. */
-+ return 721;
-+ }
-+ else
-+ {
-+ if (((word >> 16) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ x1011010110xxxx0x00000xxxxxxxxxx
-+ rbit. */
-+ return 685;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ x1011010110xxxx1x00000xxxxxxxxxx
-+ pacia. */
-+ return 693;
-+ }
-+ }
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
-- xxx11010110xxxx1x00000xxxxxxxxxx
-- pacia. */
-- return 687;
-+ xx111010110xxxxxx00000xxxxxxxxxx
-+ subps. */
-+ return 722;
- }
- }
- else
-@@ -2823,7 +3054,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x0x11010110xxxxxx10000xxxxxxxxxx
- crc32b. */
-- return 716;
-+ return 727;
- }
- else
- {
-@@ -2831,7 +3062,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1x11010110xxxxxx10000xxxxxxxxxx
- xpaci. */
-- return 703;
-+ return 709;
- }
- }
- }
-@@ -2843,7 +3074,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x0x11010110xxxxxxx1000xxxxxxxxxx
- lslv. */
-- return 707;
-+ return 713;
- }
- else
- {
-@@ -2851,7 +3082,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1x11010110xxxxxxx1000xxxxxxxxxx
- paciza. */
-- return 695;
-+ return 701;
- }
- }
- }
-@@ -2861,21 +3092,32 @@ aarch64_opcode_lookup_1 (uint32_t word)
- {
- if (((word >> 14) & 0x1) == 0)
- {
-- if (((word >> 16) & 0x1) == 0)
-+ if (((word >> 30) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
-- xxx11010110xxxx0x00100xxxxxxxxxx
-- clz. */
-- return 684;
-+ x0x11010110xxxxxx00100xxxxxxxxxx
-+ irg. */
-+ return 724;
- }
- else
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- xxx11010110xxxx1x00100xxxxxxxxxx
-- autia. */
-- return 691;
-+ if (((word >> 16) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ x1x11010110xxxx0x00100xxxxxxxxxx
-+ clz. */
-+ return 690;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ x1x11010110xxxx1x00100xxxxxxxxxx
-+ autia. */
-+ return 697;
-+ }
- }
- }
- else
-@@ -2884,7 +3126,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xxx11010110xxxxxx10100xxxxxxxxxx
- crc32cb. */
-- return 720;
-+ return 731;
- }
- }
- else
-@@ -2895,7 +3137,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x0x11010110xxxxxxx1100xxxxxxxxxx
- pacga. */
-- return 715;
-+ return 726;
- }
- else
- {
-@@ -2903,7 +3145,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1x11010110xxxxxxx1100xxxxxxxxxx
- autiza. */
-- return 699;
-+ return 705;
- }
- }
- }
-@@ -2920,7 +3162,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xxx11010x00xxxxxx0xx10xxxxxxxxxx
- setf8. */
-- return 2026;
-+ return 2386;
- }
- else
- {
-@@ -2928,7 +3170,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xxx11010x00xxxxxx1xx10xxxxxxxxxx
- setf16. */
-- return 2027;
-+ return 2387;
- }
- }
- else
-@@ -2941,7 +3183,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x0x11010010xxxxxxxxx10xxxxxxxxxx
- ccmn. */
-- return 652;
-+ return 658;
- }
- else
- {
-@@ -2949,7 +3191,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1x11010010xxxxxxxxx10xxxxxxxxxx
- ccmp. */
-- return 653;
-+ return 659;
- }
- }
- else
-@@ -2966,7 +3208,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x0x11010110xxxxxx00010xxxxxxxxxx
- udiv. */
-- return 705;
-+ return 711;
- }
- else
- {
-@@ -2978,7 +3220,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 01x11010110xxxx0x00010xxxxxxxxxx
- rev. */
-- return 681;
-+ return 687;
- }
- else
- {
-@@ -2986,7 +3228,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 11x11010110xxxx0x00010xxxxxxxxxx
- rev32. */
-- return 686;
-+ return 692;
- }
- }
- else
-@@ -2995,7 +3237,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1x11010110xxxx1x00010xxxxxxxxxx
- pacda. */
-- return 689;
-+ return 695;
- }
- }
- }
-@@ -3005,7 +3247,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xxx11010110xxxxxx10010xxxxxxxxxx
- crc32w. */
-- return 718;
-+ return 729;
- }
- }
- else
-@@ -3016,7 +3258,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x0x11010110xxxxxxx1010xxxxxxxxxx
- asrv. */
-- return 711;
-+ return 717;
- }
- else
- {
-@@ -3024,7 +3266,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1x11010110xxxxxxx1010xxxxxxxxxx
- pacdza. */
-- return 697;
-+ return 703;
- }
- }
- }
-@@ -3038,7 +3280,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xxx11010110xxxxxx00110xxxxxxxxxx
- autda. */
-- return 693;
-+ return 699;
- }
- else
- {
-@@ -3046,7 +3288,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xxx11010110xxxxxx10110xxxxxxxxxx
- crc32cw. */
-- return 722;
-+ return 733;
- }
- }
- else
-@@ -3055,7 +3297,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xxx11010110xxxxxxx1110xxxxxxxxxx
- autdza. */
-- return 701;
-+ return 707;
- }
- }
- }
-@@ -3074,7 +3316,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xxx11010000xxxxxxxxx01xxxxxxxxxx
- rmif. */
-- return 2025;
-+ return 2385;
- }
- else
- {
-@@ -3084,7 +3326,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x0x11010100xxxxxxxxx01xxxxxxxxxx
- csinc. */
-- return 657;
-+ return 663;
- }
- else
- {
-@@ -3092,7 +3334,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1x11010100xxxxxxxxx01xxxxxxxxxx
- csneg. */
-- return 663;
-+ return 669;
- }
- }
- }
-@@ -3110,7 +3352,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xxx11010x10xxxx0x00001xxxxxxxxxx
- rev16. */
-- return 680;
-+ return 686;
- }
- else
- {
-@@ -3118,7 +3360,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xxx11010x10xxxx1x00001xxxxxxxxxx
- pacib. */
-- return 688;
-+ return 694;
- }
- }
- else
-@@ -3129,7 +3371,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x0x11010x10xxxxxx10001xxxxxxxxxx
- crc32h. */
-- return 717;
-+ return 728;
- }
- else
- {
-@@ -3137,7 +3379,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1x11010x10xxxxxx10001xxxxxxxxxx
- xpacd. */
-- return 704;
-+ return 710;
- }
- }
- }
-@@ -3149,7 +3391,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x0x11010x10xxxxxxx1001xxxxxxxxxx
- lsrv. */
-- return 709;
-+ return 715;
- }
- else
- {
-@@ -3157,7 +3399,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1x11010x10xxxxxxx1001xxxxxxxxxx
- pacizb. */
-- return 696;
-+ return 702;
- }
- }
- }
-@@ -3167,21 +3409,32 @@ aarch64_opcode_lookup_1 (uint32_t word)
- {
- if (((word >> 14) & 0x1) == 0)
- {
-- if (((word >> 16) & 0x1) == 0)
-+ if (((word >> 30) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
-- xxx11010x10xxxx0x00101xxxxxxxxxx
-- cls. */
-- return 685;
-+ x0x11010x10xxxxxx00101xxxxxxxxxx
-+ gmi. */
-+ return 725;
- }
- else
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- xxx11010x10xxxx1x00101xxxxxxxxxx
-- autib. */
-- return 692;
-+ if (((word >> 16) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ x1x11010x10xxxx0x00101xxxxxxxxxx
-+ cls. */
-+ return 691;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ x1x11010x10xxxx1x00101xxxxxxxxxx
-+ autib. */
-+ return 698;
-+ }
- }
- }
- else
-@@ -3190,7 +3443,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xxx11010x10xxxxxx10101xxxxxxxxxx
- crc32ch. */
-- return 721;
-+ return 732;
- }
- }
- else
-@@ -3199,7 +3452,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xxx11010x10xxxxxxx1101xxxxxxxxxx
- autizb. */
-- return 700;
-+ return 706;
- }
- }
- }
-@@ -3218,7 +3471,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x0x11010xx0xxxxxx00011xxxxxxxxxx
- sdiv. */
-- return 706;
-+ return 712;
- }
- else
- {
-@@ -3228,7 +3481,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1x11010xx0xxxx0x00011xxxxxxxxxx
- rev. */
-- return 682;
-+ return 688;
- }
- else
- {
-@@ -3236,7 +3489,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1x11010xx0xxxx1x00011xxxxxxxxxx
- pacdb. */
-- return 690;
-+ return 696;
- }
- }
- }
-@@ -3246,7 +3499,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xxx11010xx0xxxxxx10011xxxxxxxxxx
- crc32x. */
-- return 719;
-+ return 730;
- }
- }
- else
-@@ -3257,7 +3510,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x0x11010xx0xxxxxxx1011xxxxxxxxxx
- rorv. */
-- return 713;
-+ return 719;
- }
- else
- {
-@@ -3265,7 +3518,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1x11010xx0xxxxxxx1011xxxxxxxxxx
- pacdzb. */
-- return 698;
-+ return 704;
- }
- }
- }
-@@ -3279,7 +3532,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xxx11010xx0xxxxxx00111xxxxxxxxxx
- autdb. */
-- return 694;
-+ return 700;
- }
- else
- {
-@@ -3287,7 +3540,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xxx11010xx0xxxxxx10111xxxxxxxxxx
- crc32cx. */
-- return 723;
-+ return 734;
- }
- }
- else
-@@ -3296,7 +3549,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xxx11010xx0xxxxxxx1111xxxxxxxxxx
- autdzb. */
-- return 702;
-+ return 708;
- }
- }
- }
-@@ -3313,7 +3566,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x00x1010xx1xxxxxxxxxxxxxxxxxxxxx
- bic. */
-- return 967;
-+ return 1003;
- }
- else
- {
-@@ -3321,7 +3574,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x10x1010xx1xxxxxxxxxxxxxxxxxxxxx
- eon. */
-- return 974;
-+ return 1010;
- }
- }
- else
-@@ -3332,7 +3585,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x01x1010xx1xxxxxxxxxxxxxxxxxxxxx
- orn. */
-- return 971;
-+ return 1007;
- }
- else
- {
-@@ -3340,7 +3593,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x11x1010xx1xxxxxxxxxxxxxxxxxxxxx
- bics. */
-- return 977;
-+ return 1013;
- }
- }
- }
-@@ -3360,7 +3613,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x00x00110xxxxxxxxxxxxxxxxxxxxxxx
- sbfm. */
-- return 612;
-+ return 618;
- }
- else
- {
-@@ -3368,7 +3621,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x10x00110xxxxxxxxxxxxxxxxxxxxxxx
- ubfm. */
-- return 623;
-+ return 629;
- }
- }
- else
-@@ -3377,7 +3630,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx1x00110xxxxxxxxxxxxxxxxxxxxxxx
- bfm. */
-- return 619;
-+ return 625;
- }
- }
- else
-@@ -3386,7 +3639,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xxxx00111xxxxxxxxxxxxxxxxxxxxxxx
- extr. */
-- return 746;
-+ return 758;
- }
- }
- else
-@@ -3403,7 +3656,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x0001011xx0xxxxxxxxxxxxxxxxxxxxx
- add. */
-- return 19;
-+ return 21;
- }
- else
- {
-@@ -3411,7 +3664,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1001011xx0xxxxxxxxxxxxxxxxxxxxx
- sub. */
-- return 22;
-+ return 24;
- }
- }
- else
-@@ -3422,7 +3675,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x0101011xx0xxxxxxxxxxxxxxxxxxxxx
- adds. */
-- return 20;
-+ return 22;
- }
- else
- {
-@@ -3430,7 +3683,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1101011xx0xxxxxxxxxxxxxxxxxxxxx
- subs. */
-- return 24;
-+ return 26;
- }
- }
- }
-@@ -3444,7 +3697,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xxx11011x00xxxxx0xxxxxxxxxxxxxxx
- madd. */
-- return 724;
-+ return 735;
- }
- else
- {
-@@ -3454,7 +3707,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xxx11011010xxxxx0xxxxxxxxxxxxxxx
- smulh. */
-- return 732;
-+ return 743;
- }
- else
- {
-@@ -3462,7 +3715,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xxx11011110xxxxx0xxxxxxxxxxxxxxx
- umulh. */
-- return 737;
-+ return 748;
- }
- }
- }
-@@ -3472,7 +3725,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xxx11011xx0xxxxx1xxxxxxxxxxxxxxx
- msub. */
-- return 726;
-+ return 737;
- }
- }
- }
-@@ -3529,7 +3782,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xxx110110x1xxxxx0xxxxxxxxxxxxxxx
- smaddl. */
-- return 728;
-+ return 739;
- }
- else
- {
-@@ -3537,7 +3790,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xxx110110x1xxxxx1xxxxxxxxxxxxxxx
- smsubl. */
-- return 730;
-+ return 741;
- }
- }
- }
-@@ -3549,7 +3802,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xxxx10111x1xxxxx0xxxxxxxxxxxxxxx
- umaddl. */
-- return 733;
-+ return 744;
- }
- else
- {
-@@ -3557,7 +3810,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xxxx10111x1xxxxx1xxxxxxxxxxxxxxx
- umsubl. */
-- return 735;
-+ return 746;
- }
- }
- }
-@@ -3601,7 +3854,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x0xx000000000xxxxxxxxxxxxx
- add. */
-- return 1233;
-+ return 1287;
- }
- else
- {
-@@ -3609,7 +3862,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x0xx010000000xxxxxxxxxxxxx
- mul. */
-- return 1686;
-+ return 1756;
- }
- }
- else
-@@ -3620,7 +3873,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x0xx001000000xxxxxxxxxxxxx
- smax. */
-- return 1765;
-+ return 1835;
- }
- else
- {
-@@ -3628,7 +3881,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x0xx011000000xxxxxxxxxxxxx
- orr. */
-- return 1697;
-+ return 1767;
- }
- }
- }
-@@ -3640,7 +3893,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x0xx0x0100000xxxxxxxxxxxxx
- sdiv. */
-- return 1756;
-+ return 1826;
- }
- else
- {
-@@ -3648,7 +3901,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x0xx0x1100000xxxxxxxxxxxxx
- sabd. */
-- return 1747;
-+ return 1817;
- }
- }
- }
-@@ -3662,7 +3915,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x0xx0x0010000xxxxxxxxxxxxx
- smulh. */
-- return 1770;
-+ return 1840;
- }
- else
- {
-@@ -3672,7 +3925,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x0xx001010000xxxxxxxxxxxxx
- smin. */
-- return 1768;
-+ return 1838;
- }
- else
- {
-@@ -3680,7 +3933,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x0xx011010000xxxxxxxxxxxxx
- and. */
-- return 1241;
-+ return 1295;
- }
- }
- }
-@@ -3690,7 +3943,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x0xx0xx110000xxxxxxxxxxxxx
- sdivr. */
-- return 1757;
-+ return 1827;
- }
- }
- }
-@@ -3706,7 +3959,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x0xx0x0001000xxxxxxxxxxxxx
- sub. */
-- return 1886;
-+ return 1956;
- }
- else
- {
-@@ -3716,7 +3969,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x0xx001001000xxxxxxxxxxxxx
- umax. */
-- return 1914;
-+ return 1984;
- }
- else
- {
-@@ -3724,7 +3977,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x0xx011001000xxxxxxxxxxxxx
- eor. */
-- return 1328;
-+ return 1382;
- }
- }
- }
-@@ -3736,7 +3989,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x0xx0x0101000xxxxxxxxxxxxx
- udiv. */
-- return 1908;
-+ return 1978;
- }
- else
- {
-@@ -3744,7 +3997,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x0xx0x1101000xxxxxxxxxxxxx
- uabd. */
-- return 1899;
-+ return 1969;
- }
- }
- }
-@@ -3760,7 +4013,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x0xx000011000xxxxxxxxxxxxx
- subr. */
-- return 1888;
-+ return 1958;
- }
- else
- {
-@@ -3768,7 +4021,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x0xx010011000xxxxxxxxxxxxx
- umulh. */
-- return 1919;
-+ return 1989;
- }
- }
- else
-@@ -3779,7 +4032,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x0xx001011000xxxxxxxxxxxxx
- umin. */
-- return 1917;
-+ return 1987;
- }
- else
- {
-@@ -3787,7 +4040,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x0xx011011000xxxxxxxxxxxxx
- bic. */
-- return 1253;
-+ return 1307;
- }
- }
- }
-@@ -3797,7 +4050,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x0xx0xx111000xxxxxxxxxxxxx
- udivr. */
-- return 1909;
-+ return 1979;
- }
- }
- }
-@@ -3810,7 +4063,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 100001x00x0xxxxx000xxxxxxxxxxxxx
- ld1sb. */
-- return 1515;
-+ return 1569;
- }
- else
- {
-@@ -3818,48 +4071,81 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 100001x01x0xxxxx000xxxxxxxxxxxxx
- ld1sh. */
-- return 1526;
-+ return 1580;
- }
- }
- }
- else
- {
-- if (((word >> 23) & 0x1) == 0)
-- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- x10001x00x0xxxxx000xxxxxxxxxxxxx
-- ld1sb. */
-- return 1519;
-- }
-- else
-+ if (((word >> 31) & 0x1) == 0)
- {
-- if (((word >> 31) & 0x1) == 0)
-+ if (((word >> 12) & 0x1) == 0)
- {
- if (((word >> 10) & 0x1) == 0)
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 010001x01x0xxxxx000xx0xxxxxxxxxx
-- sdot. */
-- return 1758;
-+ if (((word >> 11) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0xx0xxxxx000000xxxxxxxxxx
-+ sdot. */
-+ return 1828;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0xx0xxxxx000010xxxxxxxxxx
-+ sqdmlalbt. */
-+ return 2178;
-+ }
- }
- else
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 010001x01x0xxxxx000xx1xxxxxxxxxx
-- udot. */
-- return 1910;
-+ if (((word >> 11) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0xx0xxxxx000001xxxxxxxxxx
-+ udot. */
-+ return 1980;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0xx0xxxxx000011xxxxxxxxxx
-+ sqdmlslbt. */
-+ return 2185;
-+ }
- }
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
-+ 010001x0xx0xxxxx0001xxxxxxxxxxxx
-+ cdot. */
-+ return 2067;
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 23) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 110001x00x0xxxxx000xxxxxxxxxxxxx
-+ ld1sb. */
-+ return 1573;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
- 110001x01x0xxxxx000xxxxxxxxxxxxx
- ld1sh. */
-- return 1530;
-+ return 1584;
- }
- }
- }
-@@ -3880,7 +4166,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x0xx1xxxxx000000xxxxxxxxxx
- add. */
-- return 1231;
-+ return 1285;
- }
- else
- {
-@@ -3888,7 +4174,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x0xx1xxxxx000100xxxxxxxxxx
- sqadd. */
-- return 1772;
-+ return 1842;
- }
- }
- else
-@@ -3897,7 +4183,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x0xx1xxxxx000x10xxxxxxxxxx
- sqsub. */
-- return 1802;
-+ return 1872;
- }
- }
- else
-@@ -3910,7 +4196,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x0xx1xxxxx000001xxxxxxxxxx
- sub. */
-- return 1884;
-+ return 1954;
- }
- else
- {
-@@ -3918,7 +4204,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x0xx1xxxxx000101xxxxxxxxxx
- uqadd. */
-- return 1920;
-+ return 1990;
- }
- }
- else
-@@ -3927,7 +4213,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x0xx1xxxxx000x11xxxxxxxxxx
- uqsub. */
-- return 1950;
-+ return 2020;
- }
- }
- }
-@@ -3939,7 +4225,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 100001x00x1xxxxx000xxxxxxxxxxxxx
- prfb. */
-- return 1705;
-+ return 1775;
- }
- else
- {
-@@ -3947,7 +4233,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 100001x01x1xxxxx000xxxxxxxxxxxxx
- ld1sh. */
-- return 1527;
-+ return 1581;
- }
- }
- }
-@@ -3955,52 +4241,206 @@ aarch64_opcode_lookup_1 (uint32_t word)
- {
- if (((word >> 23) & 0x1) == 0)
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- x10001x00x1xxxxx000xxxxxxxxxxxxx
-- prfb. */
-- return 1706;
-- }
-- else
-- {
- if (((word >> 31) & 0x1) == 0)
- {
- if (((word >> 10) & 0x1) == 0)
- {
-- if (((word >> 22) & 0x1) == 0)
-+ if (((word >> 11) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
-- 010001x0101xxxxx000xx0xxxxxxxxxx
-- sdot. */
-- return 1759;
-+ 010001x00x1xxxxx000x00xxxxxxxxxx
-+ sqrdmlah. */
-+ return 2203;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
-- 010001x0111xxxxx000xx0xxxxxxxxxx
-- sdot. */
-- return 1760;
-+ 010001x00x1xxxxx000x10xxxxxxxxxx
-+ mla. */
-+ return 2110;
- }
- }
- else
- {
-- if (((word >> 22) & 0x1) == 0)
-+ if (((word >> 11) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
-- 010001x0101xxxxx000xx1xxxxxxxxxx
-- udot. */
-- return 1911;
-+ 010001x00x1xxxxx000x01xxxxxxxxxx
-+ sqrdmlsh. */
-+ return 2207;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
-- 010001x0111xxxxx000xx1xxxxxxxxxx
-- udot. */
-- return 1912;
-+ 010001x00x1xxxxx000x11xxxxxxxxxx
-+ mls. */
-+ return 2113;
-+ }
-+ }
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 110001x00x1xxxxx000xxxxxxxxxxxxx
-+ prfb. */
-+ return 1776;
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 31) & 0x1) == 0)
-+ {
-+ if (((word >> 10) & 0x1) == 0)
-+ {
-+ if (((word >> 11) & 0x1) == 0)
-+ {
-+ if (((word >> 12) & 0x1) == 0)
-+ {
-+ if (((word >> 22) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0101xxxxx000000xxxxxxxxxx
-+ sdot. */
-+ return 1829;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0111xxxxx000000xxxxxxxxxx
-+ sdot. */
-+ return 1830;
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 22) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0101xxxxx000100xxxxxxxxxx
-+ sqrdmlah. */
-+ return 2204;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0111xxxxx000100xxxxxxxxxx
-+ sqrdmlah. */
-+ return 2205;
-+ }
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 12) & 0x1) == 0)
-+ {
-+ if (((word >> 22) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0101xxxxx000010xxxxxxxxxx
-+ mla. */
-+ return 2111;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0111xxxxx000010xxxxxxxxxx
-+ mla. */
-+ return 2112;
-+ }
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x01x1xxxxx000110xxxxxxxxxx
-+ usdot. */
-+ return 2405;
-+ }
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 11) & 0x1) == 0)
-+ {
-+ if (((word >> 12) & 0x1) == 0)
-+ {
-+ if (((word >> 22) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0101xxxxx000001xxxxxxxxxx
-+ udot. */
-+ return 1981;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0111xxxxx000001xxxxxxxxxx
-+ udot. */
-+ return 1982;
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 22) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0101xxxxx000101xxxxxxxxxx
-+ sqrdmlsh. */
-+ return 2208;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0111xxxxx000101xxxxxxxxxx
-+ sqrdmlsh. */
-+ return 2209;
-+ }
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 12) & 0x1) == 0)
-+ {
-+ if (((word >> 22) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0101xxxxx000011xxxxxxxxxx
-+ mls. */
-+ return 2114;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0111xxxxx000011xxxxxxxxxx
-+ mls. */
-+ return 2115;
-+ }
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x01x1xxxxx000111xxxxxxxxxx
-+ sudot. */
-+ return 2406;
-+ }
- }
- }
- }
-@@ -4010,7 +4450,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 110001x01x1xxxxx000xxxxxxxxxxxxx
- ld1sh. */
-- return 1531;
-+ return 1585;
- }
- }
- }
-@@ -4018,13 +4458,13 @@ aarch64_opcode_lookup_1 (uint32_t word)
- }
- else
- {
-- if (((word >> 30) & 0x1) == 0)
-+ if (((word >> 31) & 0x1) == 0)
- {
-- if (((word >> 31) & 0x1) == 0)
-+ if (((word >> 21) & 0x1) == 0)
- {
-- if (((word >> 21) & 0x1) == 0)
-+ if (((word >> 16) & 0x1) == 0)
- {
-- if (((word >> 16) & 0x1) == 0)
-+ if (((word >> 17) & 0x1) == 0)
- {
- if (((word >> 18) & 0x1) == 0)
- {
-@@ -4034,185 +4474,614 @@ aarch64_opcode_lookup_1 (uint32_t word)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
-- 000001x0xx0000x0100xxxxxxxxxxxxx
-+ 0x0001x0xx000000100xxxxxxxxxxxxx
- asr. */
-- return 1249;
-+ return 1303;
- }
- else
- {
-+ if (((word >> 30) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 000001x0xx010000100xxxxxxxxxxxxx
-+ asr. */
-+ return 1301;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0xx010000100xxxxxxxxxxxxx
-+ shadd. */
-+ return 2144;
-+ }
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 20) & 0x1) == 0)
-+ {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
-- 000001x0xx0100x0100xxxxxxxxxxxxx
-- asr. */
-- return 1247;
-+ 0x0001x0xx001000100xxxxxxxxxxxxx
-+ sqshl. */
-+ return 2222;
-+ }
-+ else
-+ {
-+ if (((word >> 30) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 000001x0xx011000100xxxxxxxxxxxxx
-+ asr. */
-+ return 1302;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0xx011000100xxxxxxxxxxxxx
-+ sqadd. */
-+ return 2173;
-+ }
-+ }
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 19) & 0x1) == 0)
-+ {
-+ if (((word >> 20) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 0x0001x0xx000100100xxxxxxxxxxxxx
-+ asrd. */
-+ return 1304;
-+ }
-+ else
-+ {
-+ if (((word >> 30) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 000001x0xx010100100xxxxxxxxxxxxx
-+ asrr. */
-+ return 1305;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0xx010100100xxxxxxxxxxxxx
-+ srhadd. */
-+ return 2235;
-+ }
- }
- }
- else
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 000001x0xx0x10x0100xxxxxxxxxxxxx
-- asr. */
-- return 1248;
-+ if (((word >> 20) & 0x1) == 0)
-+ {
-+ if (((word >> 30) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 000001x0xx001100100xxxxxxxxxxxxx
-+ srshr. */
-+ return 2239;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0xx001100100xxxxxxxxxxxxx
-+ sqshlr. */
-+ return 2223;
-+ }
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 0x0001x0xx011100100xxxxxxxxxxxxx
-+ suqadd. */
-+ return 2259;
-+ }
-+ }
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 18) & 0x1) == 0)
-+ {
-+ if (((word >> 19) & 0x1) == 0)
-+ {
-+ if (((word >> 20) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 0x0001x0xx000010100xxxxxxxxxxxxx
-+ srshl. */
-+ return 2237;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 0x0001x0xx010010100xxxxxxxxxxxxx
-+ shsub. */
-+ return 2147;
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 20) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 0x0001x0xx001010100xxxxxxxxxxxxx
-+ sqrshl. */
-+ return 2215;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 0x0001x0xx011010100xxxxxxxxxxxxx
-+ sqsub. */
-+ return 2229;
-+ }
- }
- }
- else
- {
-- if (((word >> 20) & 0x1) == 0)
-+ if (((word >> 19) & 0x1) == 0)
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 000001x0xx00x1x0100xxxxxxxxxxxxx
-- asrd. */
-- return 1250;
-+ if (((word >> 20) & 0x1) == 0)
-+ {
-+ if (((word >> 30) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 000001x0xx000110100xxxxxxxxxxxxx
-+ sqshl. */
-+ return 2221;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0xx000110100xxxxxxxxxxxxx
-+ srshlr. */
-+ return 2238;
-+ }
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 0x0001x0xx010110100xxxxxxxxxxxxx
-+ shsubr. */
-+ return 2148;
-+ }
- }
- else
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 000001x0xx01x1x0100xxxxxxxxxxxxx
-- asrr. */
-- return 1251;
-+ if (((word >> 20) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 0x0001x0xx001110100xxxxxxxxxxxxx
-+ sqrshlr. */
-+ return 2216;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 0x0001x0xx011110100xxxxxxxxxxxxx
-+ sqsubr. */
-+ return 2230;
-+ }
- }
- }
- }
-- else
-+ }
-+ else
-+ {
-+ if (((word >> 17) & 0x1) == 0)
- {
-- if (((word >> 17) & 0x1) == 0)
-+ if (((word >> 18) & 0x1) == 0)
- {
-- if (((word >> 18) & 0x1) == 0)
-+ if (((word >> 19) & 0x1) == 0)
- {
-- if (((word >> 19) & 0x1) == 0)
-+ if (((word >> 20) & 0x1) == 0)
- {
-- if (((word >> 20) & 0x1) == 0)
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 0x0001x0xx000001100xxxxxxxxxxxxx
-+ lsr. */
-+ return 1747;
-+ }
-+ else
-+ {
-+ if (((word >> 30) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
-- 000001x0xx000001100xxxxxxxxxxxxx
-+ 000001x0xx010001100xxxxxxxxxxxxx
- lsr. */
-- return 1677;
-+ return 1745;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
-- 000001x0xx010001100xxxxxxxxxxxxx
-+ 010001x0xx010001100xxxxxxxxxxxxx
-+ uhadd. */
-+ return 2272;
-+ }
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 20) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 0x0001x0xx001001100xxxxxxxxxxxxx
-+ uqshl. */
-+ return 2302;
-+ }
-+ else
-+ {
-+ if (((word >> 30) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 000001x0xx011001100xxxxxxxxxxxxx
- lsr. */
-- return 1675;
-+ return 1746;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0xx011001100xxxxxxxxxxxxx
-+ uqadd. */
-+ return 2296;
- }
- }
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 19) & 0x1) == 0)
-+ {
-+ if (((word >> 30) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 000001x0xx0x0101100xxxxxxxxxxxxx
-+ lsrr. */
-+ return 1748;
-+ }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
-- 000001x0xx0x1001100xxxxxxxxxxxxx
-- lsr. */
-- return 1676;
-+ 010001x0xx0x0101100xxxxxxxxxxxxx
-+ urhadd. */
-+ return 2311;
- }
- }
- else
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 000001x0xx0xx101100xxxxxxxxxxxxx
-- lsrr. */
-- return 1678;
-+ if (((word >> 20) & 0x1) == 0)
-+ {
-+ if (((word >> 30) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 000001x0xx001101100xxxxxxxxxxxxx
-+ urshr. */
-+ return 2314;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0xx001101100xxxxxxxxxxxxx
-+ uqshlr. */
-+ return 2303;
-+ }
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 0x0001x0xx011101100xxxxxxxxxxxxx
-+ usqadd. */
-+ return 2319;
-+ }
- }
- }
-- else
-+ }
-+ else
-+ {
-+ if (((word >> 18) & 0x1) == 0)
- {
-- if (((word >> 18) & 0x1) == 0)
-+ if (((word >> 19) & 0x1) == 0)
- {
-- if (((word >> 19) & 0x1) == 0)
-+ if (((word >> 20) & 0x1) == 0)
- {
-- if (((word >> 20) & 0x1) == 0)
-+ if (((word >> 30) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 000001x0xx000011100xxxxxxxxxxxxx
- lsl. */
-- return 1671;
-+ return 1741;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
-+ 010001x0xx000011100xxxxxxxxxxxxx
-+ urshl. */
-+ return 2312;
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 30) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
- 000001x0xx010011100xxxxxxxxxxxxx
- lsl. */
-- return 1669;
-+ return 1739;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0xx010011100xxxxxxxxxxxxx
-+ uhsub. */
-+ return 2273;
- }
- }
-- else
-+ }
-+ else
-+ {
-+ if (((word >> 20) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
-- 000001x0xx0x1011100xxxxxxxxxxxxx
-- lsl. */
-- return 1670;
-+ 0x0001x0xx001011100xxxxxxxxxxxxx
-+ uqrshl. */
-+ return 2297;
-+ }
-+ else
-+ {
-+ if (((word >> 30) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 000001x0xx011011100xxxxxxxxxxxxx
-+ lsl. */
-+ return 1740;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0xx011011100xxxxxxxxxxxxx
-+ uqsub. */
-+ return 2306;
-+ }
-+ }
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 19) & 0x1) == 0)
-+ {
-+ if (((word >> 20) & 0x1) == 0)
-+ {
-+ if (((word >> 30) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 000001x0xx000111100xxxxxxxxxxxxx
-+ uqshl. */
-+ return 2301;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0xx000111100xxxxxxxxxxxxx
-+ urshlr. */
-+ return 2313;
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 30) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 000001x0xx010111100xxxxxxxxxxxxx
-+ lslr. */
-+ return 1742;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0xx010111100xxxxxxxxxxxxx
-+ uhsubr. */
-+ return 2274;
-+ }
- }
- }
- else
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 000001x0xx0xx111100xxxxxxxxxxxxx
-- lslr. */
-- return 1672;
-+ if (((word >> 20) & 0x1) == 0)
-+ {
-+ if (((word >> 30) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 000001x0xx001111100xxxxxxxxxxxxx
-+ sqshlu. */
-+ return 2224;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0xx001111100xxxxxxxxxxxxx
-+ uqrshlr. */
-+ return 2298;
-+ }
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 0x0001x0xx011111100xxxxxxxxxxxxx
-+ uqsubr. */
-+ return 2307;
-+ }
- }
- }
- }
- }
-- else
-+ }
-+ else
-+ {
-+ if (((word >> 10) & 0x1) == 0)
- {
-- if (((word >> 10) & 0x1) == 0)
-+ if (((word >> 12) & 0x1) == 0)
- {
-- if (((word >> 12) & 0x1) == 0)
-+ if (((word >> 30) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 000001x0xx1xxxxx1000x0xxxxxxxxxx
- asr. */
-- return 1245;
-+ return 1299;
- }
- else
- {
-+ if (((word >> 22) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0x01xxxxx1000x0xxxxxxxxxx
-+ smlalb. */
-+ return 2152;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0x11xxxxx1000x0xxxxxxxxxx
-+ smlalb. */
-+ return 2153;
-+ }
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 30) & 0x1) == 0)
-+ {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 000001x0xx1xxxxx1001x0xxxxxxxxxx
- asr. */
-- return 1246;
-+ return 1300;
-+ }
-+ else
-+ {
-+ if (((word >> 22) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0x01xxxxx1001x0xxxxxxxxxx
-+ umlalb. */
-+ return 2277;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0x11xxxxx1001x0xxxxxxxxxx
-+ umlalb. */
-+ return 2278;
-+ }
- }
- }
-- else
-+ }
-+ else
-+ {
-+ if (((word >> 12) & 0x1) == 0)
- {
-- if (((word >> 11) & 0x1) == 0)
-+ if (((word >> 30) & 0x1) == 0)
- {
-- if (((word >> 12) & 0x1) == 0)
-+ if (((word >> 11) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 000001x0xx1xxxxx100001xxxxxxxxxx
- lsr. */
-- return 1673;
-+ return 1743;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
-- 000001x0xx1xxxxx100101xxxxxxxxxx
-- lsr. */
-- return 1674;
-+ 000001x0xx1xxxxx100011xxxxxxxxxx
-+ lsl. */
-+ return 1737;
- }
- }
- else
- {
-- if (((word >> 12) & 0x1) == 0)
-+ if (((word >> 22) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
-- 000001x0xx1xxxxx100011xxxxxxxxxx
-- lsl. */
-- return 1667;
-+ 010001x0x01xxxxx1000x1xxxxxxxxxx
-+ smlalt. */
-+ return 2155;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0x11xxxxx1000x1xxxxxxxxxx
-+ smlalt. */
-+ return 2156;
-+ }
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 30) & 0x1) == 0)
-+ {
-+ if (((word >> 11) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 000001x0xx1xxxxx100101xxxxxxxxxx
-+ lsr. */
-+ return 1744;
- }
- else
- {
-@@ -4220,113 +5089,157 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x0xx1xxxxx100111xxxxxxxxxx
- lsl. */
-- return 1668;
-+ return 1738;
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 22) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0x01xxxxx1001x1xxxxxxxxxx
-+ umlalt. */
-+ return 2280;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0x11xxxxx1001x1xxxxxxxxxx
-+ umlalt. */
-+ return 2281;
- }
- }
- }
- }
- }
-- else
-+ }
-+ else
-+ {
-+ if (((word >> 22) & 0x1) == 0)
- {
-- if (((word >> 22) & 0x1) == 0)
-+ if (((word >> 21) & 0x1) == 0)
- {
- if (((word >> 23) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
-- 100001x000xxxxxx100xxxxxxxxxxxxx
-- ld1sb. */
-- return 1521;
-+ 1x0001x0000xxxxx100xxxxxxxxxxxxx
-+ ldnt1sb. */
-+ return 2104;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
-- 100001x010xxxxxx100xxxxxxxxxxxxx
-- ld1sh. */
-- return 1534;
-+ 1x0001x0100xxxxx100xxxxxxxxxxxxx
-+ ldnt1sh. */
-+ return 2105;
- }
- }
- else
- {
- if (((word >> 23) & 0x1) == 0)
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 100001x001xxxxxx100xxxxxxxxxxxxx
-- ld1rb. */
-- return 1491;
-+ if (((word >> 30) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 100001x0001xxxxx100xxxxxxxxxxxxx
-+ ld1sb. */
-+ return 1575;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 110001x0001xxxxx100xxxxxxxxxxxxx
-+ ld1sb. */
-+ return 1579;
-+ }
- }
- else
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 100001x011xxxxxx100xxxxxxxxxxxxx
-- ld1rsw. */
-- return 1512;
-+ if (((word >> 30) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 100001x0101xxxxx100xxxxxxxxxxxxx
-+ ld1sh. */
-+ return 1588;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 110001x0101xxxxx100xxxxxxxxxxxxx
-+ ld1sh. */
-+ return 1591;
-+ }
- }
- }
- }
-- }
-- else
-- {
-- if (((word >> 21) & 0x1) == 0)
-- {
-- if (((word >> 23) & 0x1) == 0)
-- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- x10001x00x0xxxxx100xxxxxxxxxxxxx
-- ld1sb. */
-- return 1520;
-- }
-- else
-- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- x10001x01x0xxxxx100xxxxxxxxxxxxx
-- ld1sh. */
-- return 1532;
-- }
-- }
- else
- {
-- if (((word >> 22) & 0x1) == 0)
-+ if (((word >> 23) & 0x1) == 0)
- {
-- if (((word >> 23) & 0x1) == 0)
-+ if (((word >> 30) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
-- x10001x0001xxxxx100xxxxxxxxxxxxx
-- ld1sb. */
-- return 1525;
-+ 100001x001xxxxxx100xxxxxxxxxxxxx
-+ ld1rb. */
-+ return 1545;
- }
- else
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- x10001x0101xxxxx100xxxxxxxxxxxxx
-- ld1sh. */
-- return 1537;
-+ if (((word >> 21) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 110001x0010xxxxx100xxxxxxxxxxxxx
-+ ld1sb. */
-+ return 1574;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 110001x0011xxxxx100xxxxxxxxxxxxx
-+ prfb. */
-+ return 1777;
-+ }
- }
- }
- else
- {
-- if (((word >> 23) & 0x1) == 0)
-+ if (((word >> 30) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
-- x10001x0011xxxxx100xxxxxxxxxxxxx
-- prfb. */
-- return 1707;
-+ 100001x011xxxxxx100xxxxxxxxxxxxx
-+ ld1rsw. */
-+ return 1566;
- }
- else
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- x10001x0111xxxxx100xxxxxxxxxxxxx
-- ld1sh. */
-- return 1533;
-+ if (((word >> 21) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 110001x0110xxxxx100xxxxxxxxxxxxx
-+ ld1sh. */
-+ return 1586;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 110001x0111xxxxx100xxxxxxxxxxxxx
-+ ld1sh. */
-+ return 1587;
-+ }
- }
- }
- }
-@@ -4347,7 +5260,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x0xx0xxxxx010xxxxxxxxxxxxx
- mla. */
-- return 1680;
-+ return 1750;
- }
- else
- {
-@@ -4357,7 +5270,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 100001x00x0xxxxx010xxxxxxxxxxxxx
- ld1b. */
-- return 1457;
-+ return 1511;
- }
- else
- {
-@@ -4365,27 +5278,115 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 100001x01x0xxxxx010xxxxxxxxxxxxx
- ld1h. */
-- return 1477;
-+ return 1531;
- }
- }
- }
- else
- {
-- if (((word >> 23) & 0x1) == 0)
-+ if (((word >> 31) & 0x1) == 0)
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- x10001x00x0xxxxx010xxxxxxxxxxxxx
-- ld1b. */
-- return 1462;
-+ if (((word >> 10) & 0x1) == 0)
-+ {
-+ if (((word >> 11) & 0x1) == 0)
-+ {
-+ if (((word >> 12) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0xx0xxxxx010000xxxxxxxxxx
-+ smlalb. */
-+ return 2154;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0xx0xxxxx010100xxxxxxxxxx
-+ smlslb. */
-+ return 2160;
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 12) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0xx0xxxxx010010xxxxxxxxxx
-+ umlalb. */
-+ return 2279;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0xx0xxxxx010110xxxxxxxxxx
-+ umlslb. */
-+ return 2285;
-+ }
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 11) & 0x1) == 0)
-+ {
-+ if (((word >> 12) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0xx0xxxxx010001xxxxxxxxxx
-+ smlalt. */
-+ return 2157;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0xx0xxxxx010101xxxxxxxxxx
-+ smlslt. */
-+ return 2163;
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 12) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0xx0xxxxx010011xxxxxxxxxx
-+ umlalt. */
-+ return 2282;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0xx0xxxxx010111xxxxxxxxxx
-+ umlslt. */
-+ return 2288;
-+ }
-+ }
-+ }
- }
- else
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- x10001x01x0xxxxx010xxxxxxxxxxxxx
-- ld1h. */
-- return 1482;
-+ if (((word >> 23) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 110001x00x0xxxxx010xxxxxxxxxxxxx
-+ ld1b. */
-+ return 1516;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 110001x01x0xxxxx010xxxxxxxxxxxxx
-+ ld1h. */
-+ return 1536;
-+ }
- }
- }
- }
-@@ -4405,7 +5406,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x0xx1xxxxx010000xxxxxxxxxx
- index. */
-- return 1448;
-+ return 1502;
- }
- else
- {
-@@ -4413,7 +5414,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x0xx1xxxxx010001xxxxxxxxxx
- index. */
-- return 1449;
-+ return 1503;
- }
- }
- else
-@@ -4426,7 +5427,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x0001xxxxx01010xxxxxxxxxxx
- addvl. */
-- return 1235;
-+ return 1289;
- }
- else
- {
-@@ -4434,7 +5435,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x0101xxxxx01010xxxxxxxxxxx
- rdvl. */
-- return 1741;
-+ return 1811;
- }
- }
- else
-@@ -4443,7 +5444,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x0x11xxxxx01010xxxxxxxxxxx
- addpl. */
-- return 1234;
-+ return 1288;
- }
- }
- }
-@@ -4455,7 +5456,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x0xx1xxxxx010x10xxxxxxxxxx
- index. */
-- return 1450;
-+ return 1504;
- }
- else
- {
-@@ -4463,7 +5464,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x0xx1xxxxx010x11xxxxxxxxxx
- index. */
-- return 1447;
-+ return 1501;
- }
- }
- }
-@@ -4475,7 +5476,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 100001x00x1xxxxx010xxxxxxxxxxxxx
- prfw. */
-- return 1725;
-+ return 1795;
- }
- else
- {
-@@ -4483,7 +5484,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 100001x01x1xxxxx010xxxxxxxxxxxxx
- ld1h. */
-- return 1478;
-+ return 1532;
- }
- }
- }
-@@ -4495,15 +5496,37 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x10001x00x1xxxxx010xxxxxxxxxxxxx
- prfw. */
-- return 1727;
-+ return 1797;
- }
- else
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- x10001x01x1xxxxx010xxxxxxxxxxxxx
-- ld1h. */
-- return 1483;
-+ if (((word >> 31) & 0x1) == 0)
-+ {
-+ if (((word >> 22) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0101xxxxx010xxxxxxxxxxxxx
-+ cdot. */
-+ return 2069;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0111xxxxx010xxxxxxxxxxxxx
-+ cdot. */
-+ return 2068;
-+ }
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 110001x01x1xxxxx010xxxxxxxxxxxxx
-+ ld1h. */
-+ return 1537;
-+ }
- }
- }
- }
-@@ -4520,7 +5543,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x0xx0xxxxx110xxxxxxxxxxxxx
- mad. */
-- return 1679;
-+ return 1749;
- }
- else
- {
-@@ -4536,7 +5559,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x0x010xxxx110x00xxxxxxxxxx
- sqincw. */
-- return 1799;
-+ return 1869;
- }
- else
- {
-@@ -4546,7 +5569,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x00110xxxx110x00xxxxxxxxxx
- sqinch. */
-- return 1793;
-+ return 1863;
- }
- else
- {
-@@ -4554,7 +5577,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x01110xxxx110x00xxxxxxxxxx
- sqincd. */
-- return 1790;
-+ return 1860;
- }
- }
- }
-@@ -4566,7 +5589,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x0x011xxxx110x00xxxxxxxxxx
- incw. */
-- return 1445;
-+ return 1499;
- }
- else
- {
-@@ -4576,7 +5599,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x00111xxxx110x00xxxxxxxxxx
- inch. */
-- return 1441;
-+ return 1495;
- }
- else
- {
-@@ -4584,7 +5607,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x01111xxxx110x00xxxxxxxxxx
- incd. */
-- return 1439;
-+ return 1493;
- }
- }
- }
-@@ -4597,7 +5620,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x0x01xxxxx110x10xxxxxxxxxx
- sqdecw. */
-- return 1785;
-+ return 1855;
- }
- else
- {
-@@ -4607,7 +5630,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x0011xxxxx110x10xxxxxxxxxx
- sqdech. */
-- return 1779;
-+ return 1849;
- }
- else
- {
-@@ -4615,7 +5638,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x0111xxxxx110x10xxxxxxxxxx
- sqdecd. */
-- return 1776;
-+ return 1846;
- }
- }
- }
-@@ -4632,7 +5655,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x0x010xxxx110x01xxxxxxxxxx
- uqincw. */
-- return 1947;
-+ return 2017;
- }
- else
- {
-@@ -4642,7 +5665,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x00110xxxx110x01xxxxxxxxxx
- uqinch. */
-- return 1941;
-+ return 2011;
- }
- else
- {
-@@ -4650,7 +5673,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x01110xxxx110x01xxxxxxxxxx
- uqincd. */
-- return 1938;
-+ return 2008;
- }
- }
- }
-@@ -4662,7 +5685,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x0x011xxxx110x01xxxxxxxxxx
- decw. */
-- return 1320;
-+ return 1374;
- }
- else
- {
-@@ -4672,7 +5695,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x00111xxxx110x01xxxxxxxxxx
- dech. */
-- return 1316;
-+ return 1370;
- }
- else
- {
-@@ -4680,7 +5703,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x01111xxxx110x01xxxxxxxxxx
- decd. */
-- return 1314;
-+ return 1368;
- }
- }
- }
-@@ -4693,7 +5716,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x0x01xxxxx110x11xxxxxxxxxx
- uqdecw. */
-- return 1933;
-+ return 2003;
- }
- else
- {
-@@ -4703,7 +5726,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x0011xxxxx110x11xxxxxxxxxx
- uqdech. */
-- return 1927;
-+ return 1997;
- }
- else
- {
-@@ -4711,7 +5734,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x0111xxxxx110x11xxxxxxxxxx
- uqdecd. */
-- return 1924;
-+ return 1994;
- }
- }
- }
-@@ -4730,7 +5753,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 100001x0000xxxxx110xxxxxxxxxxxxx
- prfb. */
-- return 1704;
-+ return 1774;
- }
- else
- {
-@@ -4738,7 +5761,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 100001x0100xxxxx110xxxxxxxxxxxxx
- prfh. */
-- return 1719;
-+ return 1789;
- }
- }
- else
-@@ -4749,7 +5772,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 100001x0001xxxxx110xxxxxxxxxxxxx
- ld1b. */
-- return 1464;
-+ return 1518;
- }
- else
- {
-@@ -4757,7 +5780,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 100001x0101xxxxx110xxxxxxxxxxxxx
- ld1h. */
-- return 1486;
-+ return 1540;
- }
- }
- }
-@@ -4769,7 +5792,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 100001x001xxxxxx110xxxxxxxxxxxxx
- ld1rb. */
-- return 1493;
-+ return 1547;
- }
- else
- {
-@@ -4777,7 +5800,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 100001x011xxxxxx110xxxxxxxxxxxxx
- ld1rh. */
-- return 1497;
-+ return 1551;
- }
- }
- }
-@@ -4786,21 +5809,43 @@ aarch64_opcode_lookup_1 (uint32_t word)
- {
- if (((word >> 21) & 0x1) == 0)
- {
-- if (((word >> 23) & 0x1) == 0)
-+ if (((word >> 22) & 0x1) == 0)
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- x10001x00x0xxxxx110xxxxxxxxxxxxx
-- ld1b. */
-- return 1463;
-+ if (((word >> 23) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ x10001x0000xxxxx110xxxxxxxxxxxxx
-+ ldnt1b. */
-+ return 2100;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ x10001x0100xxxxx110xxxxxxxxxxxxx
-+ ldnt1h. */
-+ return 2103;
-+ }
- }
- else
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- x10001x01x0xxxxx110xxxxxxxxxxxxx
-- ld1h. */
-- return 1484;
-+ if (((word >> 23) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ x10001x0010xxxxx110xxxxxxxxxxxxx
-+ ld1b. */
-+ return 1517;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ x10001x0110xxxxx110xxxxxxxxxxxxx
-+ ld1h. */
-+ return 1538;
-+ }
- }
- }
- else
-@@ -4813,15 +5858,59 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x10001x0001xxxxx110xxxxxxxxxxxxx
- ld1b. */
-- return 1469;
-+ return 1523;
- }
- else
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- x10001x0101xxxxx110xxxxxxxxxxxxx
-- ld1h. */
-- return 1490;
-+ if (((word >> 31) & 0x1) == 0)
-+ {
-+ if (((word >> 10) & 0x1) == 0)
-+ {
-+ if (((word >> 12) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0101xxxxx1100x0xxxxxxxxxx
-+ smullb. */
-+ return 2165;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0101xxxxx1101x0xxxxxxxxxx
-+ umullb. */
-+ return 2290;
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 12) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0101xxxxx1100x1xxxxxxxxxx
-+ smullt. */
-+ return 2168;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0101xxxxx1101x1xxxxxxxxxx
-+ umullt. */
-+ return 2293;
-+ }
-+ }
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 110001x0101xxxxx110xxxxxxxxxxxxx
-+ ld1h. */
-+ return 1544;
-+ }
- }
- }
- else
-@@ -4832,15 +5921,59 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x10001x0011xxxxx110xxxxxxxxxxxxx
- prfw. */
-- return 1728;
-+ return 1798;
- }
- else
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- x10001x0111xxxxx110xxxxxxxxxxxxx
-- ld1h. */
-- return 1485;
-+ if (((word >> 31) & 0x1) == 0)
-+ {
-+ if (((word >> 10) & 0x1) == 0)
-+ {
-+ if (((word >> 12) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0111xxxxx1100x0xxxxxxxxxx
-+ smullb. */
-+ return 2166;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0111xxxxx1101x0xxxxxxxxxx
-+ umullb. */
-+ return 2291;
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 12) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0111xxxxx1100x1xxxxxxxxxx
-+ smullt. */
-+ return 2169;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0111xxxxx1101x1xxxxxxxxxx
-+ umullt. */
-+ return 2294;
-+ }
-+ }
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 110001x0111xxxxx110xxxxxxxxxxxxx
-+ ld1h. */
-+ return 1539;
-+ }
- }
- }
- }
-@@ -4872,7 +6005,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x0xx000x00001xxxxxxxxxxxxx
- saddv. */
-- return 1748;
-+ return 1818;
- }
- else
- {
-@@ -4880,7 +6013,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x0xx000x01001xxxxxxxxxxxxx
- uaddv. */
-- return 1900;
-+ return 1970;
- }
- }
- else
-@@ -4889,7 +6022,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x0xx010x0x001xxxxxxxxxxxxx
- movprfx. */
-- return 1683;
-+ return 1753;
- }
- }
- else
-@@ -4902,7 +6035,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x0xx001x00001xxxxxxxxxxxxx
- smaxv. */
-- return 1766;
-+ return 1836;
- }
- else
- {
-@@ -4910,7 +6043,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x0xx011x00001xxxxxxxxxxxxx
- orv. */
-- return 1700;
-+ return 1770;
- }
- }
- else
-@@ -4921,7 +6054,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x0xx001x01001xxxxxxxxxxxxx
- umaxv. */
-- return 1915;
-+ return 1985;
- }
- else
- {
-@@ -4929,7 +6062,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x0xx011x01001xxxxxxxxxxxxx
- eorv. */
-- return 1331;
-+ return 1385;
- }
- }
- }
-@@ -4944,7 +6077,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x0xx00xx10001xxxxxxxxxxxxx
- sminv. */
-- return 1769;
-+ return 1839;
- }
- else
- {
-@@ -4952,7 +6085,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x0xx01xx10001xxxxxxxxxxxxx
- andv. */
-- return 1244;
-+ return 1298;
- }
- }
- else
-@@ -4961,7 +6094,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x0xx0xxx11001xxxxxxxxxxxxx
- uminv. */
-- return 1918;
-+ return 1988;
- }
- }
- }
-@@ -4973,7 +6106,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 100001x00x0xxxxx001xxxxxxxxxxxxx
- ldff1sb. */
-- return 1607;
-+ return 1669;
- }
- else
- {
-@@ -4981,113 +6114,300 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 100001x01x0xxxxx001xxxxxxxxxxxxx
- ldff1sh. */
-- return 1615;
-+ return 1680;
- }
- }
- }
- else
- {
-- if (((word >> 23) & 0x1) == 0)
-+ if (((word >> 31) & 0x1) == 0)
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- x10001x00x0xxxxx001xxxxxxxxxxxxx
-- ldff1sb. */
-- return 1611;
-+ if (((word >> 12) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0xx0xxxxx0010xxxxxxxxxxxx
-+ cmla. */
-+ return 2070;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0xx0xxxxx0011xxxxxxxxxxxx
-+ sqrdcmlah. */
-+ return 2202;
-+ }
- }
- else
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- x10001x01x0xxxxx001xxxxxxxxxxxxx
-- ldff1sh. */
-- return 1619;
-+ if (((word >> 23) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 110001x00x0xxxxx001xxxxxxxxxxxxx
-+ ldff1sb. */
-+ return 1676;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 110001x01x0xxxxx001xxxxxxxxxxxxx
-+ ldff1sh. */
-+ return 1686;
-+ }
- }
- }
- }
- else
- {
-- if (((word >> 23) & 0x1) == 0)
-+ if (((word >> 30) & 0x1) == 0)
- {
-- if (((word >> 30) & 0x1) == 0)
-+ if (((word >> 31) & 0x1) == 0)
- {
-- if (((word >> 31) & 0x1) == 0)
-+ if (((word >> 10) & 0x1) == 0)
- {
-- if (((word >> 22) & 0x1) == 0)
-+ if (((word >> 11) & 0x1) == 0)
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 000001x0001xxxxx001xxxxxxxxxxxxx
-- and. */
-- return 1239;
-+ if (((word >> 22) & 0x1) == 0)
-+ {
-+ if (((word >> 23) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 000001x0001xxxxx001x00xxxxxxxxxx
-+ and. */
-+ return 1293;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 000001x0101xxxxx001x00xxxxxxxxxx
-+ eor. */
-+ return 1380;
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 23) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 000001x0011xxxxx001x00xxxxxxxxxx
-+ orr. */
-+ return 1765;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 000001x0111xxxxx001x00xxxxxxxxxx
-+ bic. */
-+ return 1306;
-+ }
-+ }
- }
- else
- {
-+ if (((word >> 22) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 000001x0x01xxxxx001x10xxxxxxxxxx
-+ eor3. */
-+ return 2073;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 000001x0x11xxxxx001x10xxxxxxxxxx
-+ bcax. */
-+ return 2062;
-+ }
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 11) & 0x1) == 0)
-+ {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
-- 000001x0011xxxxx001xxxxxxxxxxxxx
-- orr. */
-- return 1695;
-+ 000001x0xx1xxxxx001x01xxxxxxxxxx
-+ xar. */
-+ return 2335;
-+ }
-+ else
-+ {
-+ if (((word >> 22) & 0x1) == 0)
-+ {
-+ if (((word >> 23) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 000001x0001xxxxx001x11xxxxxxxxxx
-+ bsl. */
-+ return 2063;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 000001x0101xxxxx001x11xxxxxxxxxx
-+ bsl2n. */
-+ return 2065;
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 23) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 000001x0011xxxxx001x11xxxxxxxxxx
-+ bsl1n. */
-+ return 2064;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 000001x0111xxxxx001x11xxxxxxxxxx
-+ nbsl. */
-+ return 2120;
-+ }
-+ }
- }
- }
-- else
-+ }
-+ else
-+ {
-+ if (((word >> 23) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 100001x00x1xxxxx001xxxxxxxxxxxxx
- prfh. */
-- return 1718;
-+ return 1788;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 100001x01x1xxxxx001xxxxxxxxxxxxx
-+ ldff1sh. */
-+ return 1681;
- }
- }
-- else
-+ }
-+ else
-+ {
-+ if (((word >> 23) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x10001x00x1xxxxx001xxxxxxxxxxxxx
- prfh. */
-- return 1720;
-+ return 1790;
- }
-- }
-- else
-- {
-- if (((word >> 30) & 0x1) == 0)
-+ else
- {
- if (((word >> 31) & 0x1) == 0)
- {
-- if (((word >> 22) & 0x1) == 0)
-+ if (((word >> 10) & 0x1) == 0)
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 000001x0101xxxxx001xxxxxxxxxxxxx
-- eor. */
-- return 1326;
-+ if (((word >> 12) & 0x1) == 0)
-+ {
-+ if (((word >> 22) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0101xxxxx0010x0xxxxxxxxxx
-+ sqdmlalb. */
-+ return 2175;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0111xxxxx0010x0xxxxxxxxxx
-+ sqdmlalb. */
-+ return 2176;
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 22) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0101xxxxx0011x0xxxxxxxxxx
-+ sqdmlslb. */
-+ return 2182;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0111xxxxx0011x0xxxxxxxxxx
-+ sqdmlslb. */
-+ return 2183;
-+ }
-+ }
- }
- else
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 000001x0111xxxxx001xxxxxxxxxxxxx
-- bic. */
-- return 1252;
-+ if (((word >> 12) & 0x1) == 0)
-+ {
-+ if (((word >> 22) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0101xxxxx0010x1xxxxxxxxxx
-+ sqdmlalt. */
-+ return 2179;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0111xxxxx0010x1xxxxxxxxxx
-+ sqdmlalt. */
-+ return 2180;
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 22) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0101xxxxx0011x1xxxxxxxxxx
-+ sqdmlslt. */
-+ return 2186;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0111xxxxx0011x1xxxxxxxxxx
-+ sqdmlslt. */
-+ return 2187;
-+ }
-+ }
- }
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
-- 100001x01x1xxxxx001xxxxxxxxxxxxx
-+ 110001x01x1xxxxx001xxxxxxxxxxxxx
- ldff1sh. */
-- return 1616;
-+ return 1687;
- }
- }
-- else
-- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- x10001x01x1xxxxx001xxxxxxxxxxxxx
-- ldff1sh. */
-- return 1620;
-- }
- }
- }
- }
-@@ -5111,7 +6431,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x0xx0x0000101xxxxxxxxxxxxx
- sxtb. */
-- return 1891;
-+ return 1961;
- }
- else
- {
-@@ -5119,7 +6439,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x0xx0x1000101xxxxxxxxxxxxx
- cls. */
-- return 1272;
-+ return 1326;
- }
- }
- else
-@@ -5130,7 +6450,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x0xx0x0100101xxxxxxxxxxxxx
- sxtw. */
-- return 1893;
-+ return 1963;
- }
- else
- {
-@@ -5138,7 +6458,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x0xx0x1100101xxxxxxxxxxxxx
- fabs. */
-- return 1334;
-+ return 1388;
- }
- }
- }
-@@ -5152,7 +6472,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x0xx0x0010101xxxxxxxxxxxxx
- sxth. */
-- return 1892;
-+ return 1962;
- }
- else
- {
-@@ -5160,7 +6480,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x0xx0x1010101xxxxxxxxxxxxx
- cnt. */
-- return 1301;
-+ return 1355;
- }
- }
- else
-@@ -5171,7 +6491,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x0xx0x0110101xxxxxxxxxxxxx
- abs. */
-- return 1230;
-+ return 1284;
- }
- else
- {
-@@ -5179,7 +6499,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x0xx0x1110101xxxxxxxxxxxxx
- not. */
-- return 1692;
-+ return 1762;
- }
- }
- }
-@@ -5196,7 +6516,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x0xx0x0001101xxxxxxxxxxxxx
- uxtb. */
-- return 1954;
-+ return 2024;
- }
- else
- {
-@@ -5204,7 +6524,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x0xx0x1001101xxxxxxxxxxxxx
- clz. */
-- return 1273;
-+ return 1327;
- }
- }
- else
-@@ -5215,7 +6535,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x0xx0x0101101xxxxxxxxxxxxx
- uxtw. */
-- return 1956;
-+ return 2026;
- }
- else
- {
-@@ -5223,7 +6543,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x0xx0x1101101xxxxxxxxxxxxx
- fneg. */
-- return 1411;
-+ return 1465;
- }
- }
- }
-@@ -5237,7 +6557,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x0xx0x0011101xxxxxxxxxxxxx
- uxth. */
-- return 1955;
-+ return 2025;
- }
- else
- {
-@@ -5245,7 +6565,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x0xx0x1011101xxxxxxxxxxxxx
- cnot. */
-- return 1300;
-+ return 1354;
- }
- }
- else
-@@ -5254,7 +6574,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x0xx0xx111101xxxxxxxxxxxxx
- neg. */
-- return 1689;
-+ return 1759;
- }
- }
- }
-@@ -5271,7 +6591,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x0001xxxxx1010xxxxxxxxxxxx
- adr. */
-- return 1236;
-+ return 1290;
- }
- else
- {
-@@ -5279,7 +6599,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x0011xxxxx1010xxxxxxxxxxxx
- adr. */
-- return 1237;
-+ return 1291;
- }
- }
- else
-@@ -5288,7 +6608,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x01x1xxxxx1010xxxxxxxxxxxx
- adr. */
-- return 1238;
-+ return 1292;
- }
- }
- else
-@@ -5301,7 +6621,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x0xx1xxxxx101100xxxxxxxxxx
- ftssel. */
-- return 1437;
-+ return 1491;
- }
- else
- {
-@@ -5309,7 +6629,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x0xx1xxxxx101110xxxxxxxxxx
- fexpa. */
-- return 1381;
-+ return 1435;
- }
- }
- else
-@@ -5318,7 +6638,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x0xx1xxxxx1011x1xxxxxxxxxx
- movprfx. */
-- return 1682;
-+ return 1752;
- }
- }
- }
-@@ -5327,21 +6647,43 @@ aarch64_opcode_lookup_1 (uint32_t word)
- {
- if (((word >> 22) & 0x1) == 0)
- {
-- if (((word >> 23) & 0x1) == 0)
-+ if (((word >> 21) & 0x1) == 0)
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 100001x000xxxxxx101xxxxxxxxxxxxx
-- ldff1sb. */
-- return 1613;
-+ if (((word >> 23) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 100001x0000xxxxx101xxxxxxxxxxxxx
-+ ldnt1b. */
-+ return 2099;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 100001x0100xxxxx101xxxxxxxxxxxxx
-+ ldnt1h. */
-+ return 2102;
-+ }
- }
- else
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 100001x010xxxxxx101xxxxxxxxxxxxx
-- ldff1sh. */
-- return 1623;
-+ if (((word >> 23) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 100001x0001xxxxx101xxxxxxxxxxxxx
-+ ldff1sb. */
-+ return 1678;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 100001x0101xxxxx101xxxxxxxxxxxxx
-+ ldff1sh. */
-+ return 1690;
-+ }
- }
- }
- else
-@@ -5352,7 +6694,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 100001x001xxxxxx101xxxxxxxxxxxxx
- ld1rb. */
-- return 1492;
-+ return 1546;
- }
- else
- {
-@@ -5360,7 +6702,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 100001x011xxxxxx101xxxxxxxxxxxxx
- ld1rh. */
-- return 1496;
-+ return 1550;
- }
- }
- }
-@@ -5369,21 +6711,142 @@ aarch64_opcode_lookup_1 (uint32_t word)
- {
- if (((word >> 21) & 0x1) == 0)
- {
-- if (((word >> 23) & 0x1) == 0)
-+ if (((word >> 31) & 0x1) == 0)
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- x10001x00x0xxxxx101xxxxxxxxxxxxx
-- ldff1sb. */
-- return 1612;
-+ if (((word >> 16) & 0x1) == 0)
-+ {
-+ if (((word >> 17) & 0x1) == 0)
-+ {
-+ if (((word >> 18) & 0x1) == 0)
-+ {
-+ if (((word >> 19) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0xx0x0000101xxxxxxxxxxxxx
-+ urecpe. */
-+ return 2310;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0xx0x1000101xxxxxxxxxxxxx
-+ sqabs. */
-+ return 2172;
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 20) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0xx00x100101xxxxxxxxxxxxx
-+ sadalp. */
-+ return 2136;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0xx01x100101xxxxxxxxxxxxx
-+ smaxp. */
-+ return 2150;
-+ }
-+ }
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0xx0xxx10101xxxxxxxxxxxxx
-+ sminp. */
-+ return 2151;
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 17) & 0x1) == 0)
-+ {
-+ if (((word >> 18) & 0x1) == 0)
-+ {
-+ if (((word >> 19) & 0x1) == 0)
-+ {
-+ if (((word >> 20) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0xx000001101xxxxxxxxxxxxx
-+ ursqrte. */
-+ return 2315;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0xx010001101xxxxxxxxxxxxx
-+ addp. */
-+ return 2061;
-+ }
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0xx0x1001101xxxxxxxxxxxxx
-+ sqneg. */
-+ return 2199;
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 20) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0xx00x101101xxxxxxxxxxxxx
-+ uadalp. */
-+ return 2267;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0xx01x101101xxxxxxxxxxxxx
-+ umaxp. */
-+ return 2275;
-+ }
-+ }
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0xx0xxx11101xxxxxxxxxxxxx
-+ uminp. */
-+ return 2276;
-+ }
-+ }
- }
- else
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- x10001x01x0xxxxx101xxxxxxxxxxxxx
-- ldff1sh. */
-- return 1621;
-+ if (((word >> 23) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 110001x00x0xxxxx101xxxxxxxxxxxxx
-+ ldff1sb. */
-+ return 1677;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 110001x01x0xxxxx101xxxxxxxxxxxxx
-+ ldff1sh. */
-+ return 1688;
-+ }
- }
- }
- else
-@@ -5396,15 +6859,59 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x10001x0001xxxxx101xxxxxxxxxxxxx
- ldff1sb. */
-- return 1614;
-+ return 1679;
- }
- else
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- x10001x0101xxxxx101xxxxxxxxxxxxx
-- ldff1sh. */
-- return 1624;
-+ if (((word >> 31) & 0x1) == 0)
-+ {
-+ if (((word >> 10) & 0x1) == 0)
-+ {
-+ if (((word >> 12) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0101xxxxx1010x0xxxxxxxxxx
-+ smlslb. */
-+ return 2158;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0101xxxxx1011x0xxxxxxxxxx
-+ umlslb. */
-+ return 2283;
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 12) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0101xxxxx1010x1xxxxxxxxxx
-+ smlslt. */
-+ return 2161;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0101xxxxx1011x1xxxxxxxxxx
-+ umlslt. */
-+ return 2286;
-+ }
-+ }
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 110001x0101xxxxx101xxxxxxxxxxxxx
-+ ldff1sh. */
-+ return 1691;
-+ }
- }
- }
- else
-@@ -5415,15 +6922,59 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x10001x0011xxxxx101xxxxxxxxxxxxx
- prfh. */
-- return 1721;
-+ return 1791;
- }
- else
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- x10001x0111xxxxx101xxxxxxxxxxxxx
-- ldff1sh. */
-- return 1622;
-+ if (((word >> 31) & 0x1) == 0)
-+ {
-+ if (((word >> 10) & 0x1) == 0)
-+ {
-+ if (((word >> 12) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0111xxxxx1010x0xxxxxxxxxx
-+ smlslb. */
-+ return 2159;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0111xxxxx1011x0xxxxxxxxxx
-+ umlslb. */
-+ return 2284;
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 12) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0111xxxxx1010x1xxxxxxxxxx
-+ smlslt. */
-+ return 2162;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0111xxxxx1011x1xxxxxxxxxx
-+ umlslt. */
-+ return 2287;
-+ }
-+ }
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 110001x0111xxxxx101xxxxxxxxxxxxx
-+ ldff1sh. */
-+ return 1689;
-+ }
- }
- }
- }
-@@ -5444,7 +6995,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x0xx0xxxxx011xxxxxxxxxxxxx
- mls. */
-- return 1681;
-+ return 1751;
- }
- else
- {
-@@ -5454,7 +7005,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 100001x00x0xxxxx011xxxxxxxxxxxxx
- ldff1b. */
-- return 1581;
-+ return 1635;
- }
- else
- {
-@@ -5462,68 +7013,255 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 100001x01x0xxxxx011xxxxxxxxxxxxx
- ldff1h. */
-- return 1596;
-+ return 1655;
- }
- }
- }
- else
- {
-- if (((word >> 23) & 0x1) == 0)
-+ if (((word >> 31) & 0x1) == 0)
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- x10001x00x0xxxxx011xxxxxxxxxxxxx
-- ldff1b. */
-- return 1586;
-+ if (((word >> 10) & 0x1) == 0)
-+ {
-+ if (((word >> 11) & 0x1) == 0)
-+ {
-+ if (((word >> 12) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0xx0xxxxx011000xxxxxxxxxx
-+ sqdmlalb. */
-+ return 2177;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0xx0xxxxx011100xxxxxxxxxx
-+ sqrdmlah. */
-+ return 2206;
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 12) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0xx0xxxxx011010xxxxxxxxxx
-+ sqdmlslb. */
-+ return 2184;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0xx0xxxxx011110xxxxxxxxxx
-+ usdot. */
-+ return 2404;
-+ }
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 11) & 0x1) == 0)
-+ {
-+ if (((word >> 12) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0xx0xxxxx011001xxxxxxxxxx
-+ sqdmlalt. */
-+ return 2181;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0xx0xxxxx011101xxxxxxxxxx
-+ sqrdmlsh. */
-+ return 2210;
-+ }
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0xx0xxxxx011x11xxxxxxxxxx
-+ sqdmlslt. */
-+ return 2188;
-+ }
-+ }
- }
- else
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- x10001x01x0xxxxx011xxxxxxxxxxxxx
-- ldff1h. */
-- return 1601;
-+ if (((word >> 23) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 110001x00x0xxxxx011xxxxxxxxxxxxx
-+ ldff1b. */
-+ return 1644;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 110001x01x0xxxxx011xxxxxxxxxxxxx
-+ ldff1h. */
-+ return 1663;
-+ }
- }
- }
- }
- else
- {
-- if (((word >> 23) & 0x1) == 0)
-+ if (((word >> 30) & 0x1) == 0)
- {
-- if (((word >> 30) & 0x1) == 0)
-+ if (((word >> 31) & 0x1) == 0)
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- x00001x00x1xxxxx011xxxxxxxxxxxxx
-- prfd. */
-- return 1711;
-+ if (((word >> 10) & 0x1) == 0)
-+ {
-+ if (((word >> 11) & 0x1) == 0)
-+ {
-+ if (((word >> 12) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 000001x0xx1xxxxx011000xxxxxxxxxx
-+ mul. */
-+ return 2119;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 000001x0xx1xxxxx011100xxxxxxxxxx
-+ sqdmulh. */
-+ return 2192;
-+ }
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 000001x0xx1xxxxx011x10xxxxxxxxxx
-+ smulh. */
-+ return 2164;
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 11) & 0x1) == 0)
-+ {
-+ if (((word >> 12) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 000001x0xx1xxxxx011001xxxxxxxxxx
-+ pmul. */
-+ return 2122;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 000001x0xx1xxxxx011101xxxxxxxxxx
-+ sqrdmulh. */
-+ return 2214;
-+ }
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 000001x0xx1xxxxx011x11xxxxxxxxxx
-+ umulh. */
-+ return 2289;
-+ }
-+ }
- }
- else
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- x10001x00x1xxxxx011xxxxxxxxxxxxx
-- prfd. */
-- return 1713;
-+ if (((word >> 23) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 100001x00x1xxxxx011xxxxxxxxxxxxx
-+ prfd. */
-+ return 1781;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 100001x01x1xxxxx011xxxxxxxxxxxxx
-+ ldff1h. */
-+ return 1656;
-+ }
- }
- }
- else
- {
-- if (((word >> 30) & 0x1) == 0)
-+ if (((word >> 23) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
-- x00001x01x1xxxxx011xxxxxxxxxxxxx
-- ldff1h. */
-- return 1597;
-+ x10001x00x1xxxxx011xxxxxxxxxxxxx
-+ prfd. */
-+ return 1783;
- }
- else
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- x10001x01x1xxxxx011xxxxxxxxxxxxx
-- ldff1h. */
-- return 1602;
-+ if (((word >> 31) & 0x1) == 0)
-+ {
-+ if (((word >> 12) & 0x1) == 0)
-+ {
-+ if (((word >> 22) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0101xxxxx0110xxxxxxxxxxxx
-+ cmla. */
-+ return 2071;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0111xxxxx0110xxxxxxxxxxxx
-+ cmla. */
-+ return 2072;
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 22) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0101xxxxx0111xxxxxxxxxxxx
-+ sqrdcmlah. */
-+ return 2200;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0111xxxxx0111xxxxxxxxxxxx
-+ sqrdcmlah. */
-+ return 2201;
-+ }
-+ }
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 110001x01x1xxxxx011xxxxxxxxxxxxx
-+ ldff1h. */
-+ return 1664;
-+ }
- }
- }
- }
-@@ -5540,7 +7278,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x0xx0xxxxx111xxxxxxxxxxxxx
- msb. */
-- return 1684;
-+ return 1754;
- }
- else
- {
-@@ -5560,7 +7298,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x00010xxxx111000xxxxxxxxxx
- cntb. */
-- return 1302;
-+ return 1356;
- }
- else
- {
-@@ -5568,7 +7306,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x01010xxxx111000xxxxxxxxxx
- cntw. */
-- return 1306;
-+ return 1360;
- }
- }
- else
-@@ -5579,7 +7317,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x00110xxxx111000xxxxxxxxxx
- cnth. */
-- return 1304;
-+ return 1358;
- }
- else
- {
-@@ -5587,7 +7325,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x01110xxxx111000xxxxxxxxxx
- cntd. */
-- return 1303;
-+ return 1357;
- }
- }
- }
-@@ -5601,7 +7339,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x00011xxxx111000xxxxxxxxxx
- incb. */
-- return 1438;
-+ return 1492;
- }
- else
- {
-@@ -5609,7 +7347,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x01011xxxx111000xxxxxxxxxx
- incw. */
-- return 1446;
-+ return 1500;
- }
- }
- else
-@@ -5620,7 +7358,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x00111xxxx111000xxxxxxxxxx
- inch. */
-- return 1442;
-+ return 1496;
- }
- else
- {
-@@ -5628,7 +7366,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x01111xxxx111000xxxxxxxxxx
- incd. */
-- return 1440;
-+ return 1494;
- }
- }
- }
-@@ -5645,7 +7383,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x00010xxxx111100xxxxxxxxxx
- sqincb. */
-- return 1789;
-+ return 1859;
- }
- else
- {
-@@ -5653,7 +7391,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x01010xxxx111100xxxxxxxxxx
- sqincw. */
-- return 1801;
-+ return 1871;
- }
- }
- else
-@@ -5664,7 +7402,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x00110xxxx111100xxxxxxxxxx
- sqinch. */
-- return 1795;
-+ return 1865;
- }
- else
- {
-@@ -5672,7 +7410,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x01110xxxx111100xxxxxxxxxx
- sqincd. */
-- return 1792;
-+ return 1862;
- }
- }
- }
-@@ -5686,7 +7424,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x00011xxxx111100xxxxxxxxxx
- sqincb. */
-- return 1788;
-+ return 1858;
- }
- else
- {
-@@ -5694,7 +7432,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x01011xxxx111100xxxxxxxxxx
- sqincw. */
-- return 1800;
-+ return 1870;
- }
- }
- else
-@@ -5705,7 +7443,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x00111xxxx111100xxxxxxxxxx
- sqinch. */
-- return 1794;
-+ return 1864;
- }
- else
- {
-@@ -5713,7 +7451,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x01111xxxx111100xxxxxxxxxx
- sqincd. */
-- return 1791;
-+ return 1861;
- }
- }
- }
-@@ -5731,7 +7469,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x00010xxxx111x10xxxxxxxxxx
- sqdecb. */
-- return 1775;
-+ return 1845;
- }
- else
- {
-@@ -5739,7 +7477,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x01010xxxx111x10xxxxxxxxxx
- sqdecw. */
-- return 1787;
-+ return 1857;
- }
- }
- else
-@@ -5750,7 +7488,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x00110xxxx111x10xxxxxxxxxx
- sqdech. */
-- return 1781;
-+ return 1851;
- }
- else
- {
-@@ -5758,7 +7496,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x01110xxxx111x10xxxxxxxxxx
- sqdecd. */
-- return 1778;
-+ return 1848;
- }
- }
- }
-@@ -5772,7 +7510,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x00011xxxx111x10xxxxxxxxxx
- sqdecb. */
-- return 1774;
-+ return 1844;
- }
- else
- {
-@@ -5780,7 +7518,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x01011xxxx111x10xxxxxxxxxx
- sqdecw. */
-- return 1786;
-+ return 1856;
- }
- }
- else
-@@ -5791,7 +7529,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x00111xxxx111x10xxxxxxxxxx
- sqdech. */
-- return 1780;
-+ return 1850;
- }
- else
- {
-@@ -5799,7 +7537,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x01111xxxx111x10xxxxxxxxxx
- sqdecd. */
-- return 1777;
-+ return 1847;
- }
- }
- }
-@@ -5819,7 +7557,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x0001xxxxx111001xxxxxxxxxx
- decb. */
-- return 1313;
-+ return 1367;
- }
- else
- {
-@@ -5827,7 +7565,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x0101xxxxx111001xxxxxxxxxx
- decw. */
-- return 1321;
-+ return 1375;
- }
- }
- else
-@@ -5838,7 +7576,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x0011xxxxx111001xxxxxxxxxx
- dech. */
-- return 1317;
-+ return 1371;
- }
- else
- {
-@@ -5846,7 +7584,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x0111xxxxx111001xxxxxxxxxx
- decd. */
-- return 1315;
-+ return 1369;
- }
- }
- }
-@@ -5862,7 +7600,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x00010xxxx111101xxxxxxxxxx
- uqincb. */
-- return 1936;
-+ return 2006;
- }
- else
- {
-@@ -5870,7 +7608,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x01010xxxx111101xxxxxxxxxx
- uqincw. */
-- return 1948;
-+ return 2018;
- }
- }
- else
-@@ -5881,7 +7619,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x00110xxxx111101xxxxxxxxxx
- uqinch. */
-- return 1942;
-+ return 2012;
- }
- else
- {
-@@ -5889,7 +7627,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x01110xxxx111101xxxxxxxxxx
- uqincd. */
-- return 1939;
-+ return 2009;
- }
- }
- }
-@@ -5903,7 +7641,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x00011xxxx111101xxxxxxxxxx
- uqincb. */
-- return 1937;
-+ return 2007;
- }
- else
- {
-@@ -5911,7 +7649,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x01011xxxx111101xxxxxxxxxx
- uqincw. */
-- return 1949;
-+ return 2019;
- }
- }
- else
-@@ -5922,7 +7660,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x00111xxxx111101xxxxxxxxxx
- uqinch. */
-- return 1943;
-+ return 2013;
- }
- else
- {
-@@ -5930,7 +7668,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x01111xxxx111101xxxxxxxxxx
- uqincd. */
-- return 1940;
-+ return 2010;
- }
- }
- }
-@@ -5948,7 +7686,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x00010xxxx111x11xxxxxxxxxx
- uqdecb. */
-- return 1922;
-+ return 1992;
- }
- else
- {
-@@ -5956,7 +7694,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x01010xxxx111x11xxxxxxxxxx
- uqdecw. */
-- return 1934;
-+ return 2004;
- }
- }
- else
-@@ -5967,7 +7705,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x00110xxxx111x11xxxxxxxxxx
- uqdech. */
-- return 1928;
-+ return 1998;
- }
- else
- {
-@@ -5975,7 +7713,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x01110xxxx111x11xxxxxxxxxx
- uqdecd. */
-- return 1925;
-+ return 1995;
- }
- }
- }
-@@ -5989,7 +7727,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x00011xxxx111x11xxxxxxxxxx
- uqdecb. */
-- return 1923;
-+ return 1993;
- }
- else
- {
-@@ -5997,7 +7735,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x01011xxxx111x11xxxxxxxxxx
- uqdecw. */
-- return 1935;
-+ return 2005;
- }
- }
- else
-@@ -6008,7 +7746,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x00111xxxx111x11xxxxxxxxxx
- uqdech. */
-- return 1929;
-+ return 1999;
- }
- else
- {
-@@ -6016,7 +7754,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x01111xxxx111x11xxxxxxxxxx
- uqdecd. */
-- return 1926;
-+ return 1996;
- }
- }
- }
-@@ -6036,7 +7774,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 100001x0000xxxxx111xxxxxxxxxxxxx
- prfb. */
-- return 1708;
-+ return 1778;
- }
- else
- {
-@@ -6044,7 +7782,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 100001x0100xxxxx111xxxxxxxxxxxxx
- prfh. */
-- return 1722;
-+ return 1792;
- }
- }
- else
-@@ -6055,7 +7793,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 100001x0001xxxxx111xxxxxxxxxxxxx
- ldff1b. */
-- return 1588;
-+ return 1646;
- }
- else
- {
-@@ -6063,7 +7801,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 100001x0101xxxxx111xxxxxxxxxxxxx
- ldff1h. */
-- return 1605;
-+ return 1667;
- }
- }
- }
-@@ -6075,7 +7813,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 100001x001xxxxxx111xxxxxxxxxxxxx
- ld1rb. */
-- return 1494;
-+ return 1548;
- }
- else
- {
-@@ -6083,7 +7821,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 100001x011xxxxxx111xxxxxxxxxxxxx
- ld1rh. */
-- return 1498;
-+ return 1552;
- }
- }
- }
-@@ -6100,7 +7838,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x10001x0000xxxxx111xxxxxxxxxxxxx
- prfb. */
-- return 1710;
-+ return 1780;
- }
- else
- {
-@@ -6108,7 +7846,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x10001x0100xxxxx111xxxxxxxxxxxxx
- prfh. */
-- return 1724;
-+ return 1794;
- }
- }
- else
-@@ -6119,7 +7857,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x10001x0010xxxxx111xxxxxxxxxxxxx
- ldff1b. */
-- return 1587;
-+ return 1645;
- }
- else
- {
-@@ -6127,48 +7865,191 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x10001x0110xxxxx111xxxxxxxxxxxxx
- ldff1h. */
-- return 1603;
-+ return 1665;
- }
- }
- }
- else
- {
-- if (((word >> 22) & 0x1) == 0)
-+ if (((word >> 23) & 0x1) == 0)
- {
-- if (((word >> 23) & 0x1) == 0)
-+ if (((word >> 31) & 0x1) == 0)
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- x10001x0001xxxxx111xxxxxxxxxxxxx
-- ldff1b. */
-- return 1589;
-+ if (((word >> 10) & 0x1) == 0)
-+ {
-+ if (((word >> 11) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x00x1xxxxx111x00xxxxxxxxxx
-+ sqdmulh. */
-+ return 2189;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x00x1xxxxx111x10xxxxxxxxxx
-+ mul. */
-+ return 2116;
-+ }
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x00x1xxxxx111xx1xxxxxxxxxx
-+ sqrdmulh. */
-+ return 2211;
-+ }
- }
- else
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- x10001x0101xxxxx111xxxxxxxxxxxxx
-- ldff1h. */
-- return 1606;
-+ if (((word >> 22) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 110001x0001xxxxx111xxxxxxxxxxxxx
-+ ldff1b. */
-+ return 1647;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 110001x0011xxxxx111xxxxxxxxxxxxx
-+ prfd. */
-+ return 1784;
-+ }
- }
- }
- else
- {
-- if (((word >> 23) & 0x1) == 0)
-+ if (((word >> 22) & 0x1) == 0)
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- x10001x0011xxxxx111xxxxxxxxxxxxx
-- prfd. */
-- return 1714;
-+ if (((word >> 31) & 0x1) == 0)
-+ {
-+ if (((word >> 10) & 0x1) == 0)
-+ {
-+ if (((word >> 12) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0101xxxxx1110x0xxxxxxxxxx
-+ sqdmullb. */
-+ return 2193;
-+ }
-+ else
-+ {
-+ if (((word >> 11) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0101xxxxx111100xxxxxxxxxx
-+ sqdmulh. */
-+ return 2190;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0101xxxxx111110xxxxxxxxxx
-+ mul. */
-+ return 2117;
-+ }
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 12) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0101xxxxx1110x1xxxxxxxxxx
-+ sqdmullt. */
-+ return 2196;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0101xxxxx1111x1xxxxxxxxxx
-+ sqrdmulh. */
-+ return 2212;
-+ }
-+ }
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 110001x0101xxxxx111xxxxxxxxxxxxx
-+ ldff1h. */
-+ return 1668;
-+ }
- }
- else
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- x10001x0111xxxxx111xxxxxxxxxxxxx
-- ldff1h. */
-- return 1604;
-+ if (((word >> 31) & 0x1) == 0)
-+ {
-+ if (((word >> 10) & 0x1) == 0)
-+ {
-+ if (((word >> 12) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0111xxxxx1110x0xxxxxxxxxx
-+ sqdmullb. */
-+ return 2194;
-+ }
-+ else
-+ {
-+ if (((word >> 11) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0111xxxxx111100xxxxxxxxxx
-+ sqdmulh. */
-+ return 2191;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0111xxxxx111110xxxxxxxxxx
-+ mul. */
-+ return 2118;
-+ }
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 12) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0111xxxxx1110x1xxxxxxxxxx
-+ sqdmullt. */
-+ return 2197;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x0111xxxxx1111x1xxxxxxxxxx
-+ sqrdmulh. */
-+ return 2213;
-+ }
-+ }
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 110001x0111xxxxx111xxxxxxxxxxxxx
-+ ldff1h. */
-+ return 1666;
-+ }
- }
- }
- }
-@@ -6197,7 +8078,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001001x0xx0xxxxx000xxxxxxxx0xxxx
- cmphs. */
-- return 1286;
-+ return 1340;
- }
- else
- {
-@@ -6205,7 +8086,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001001x0xx0xxxxx000xxxxxxxx1xxxx
- cmphi. */
-- return 1283;
-+ return 1337;
- }
- }
- else
-@@ -6216,7 +8097,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 101001x00x0xxxxx000xxxxxxxxxxxxx
- ld1rqb. */
-- return 1500;
-+ return 1554;
- }
- else
- {
-@@ -6224,7 +8105,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 101001x01x0xxxxx000xxxxxxxxxxxxx
- ld1rqh. */
-- return 1504;
-+ return 1558;
- }
- }
- }
-@@ -6238,7 +8119,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001001x0xx0xxxxx010xxxxxxxx0xxxx
- cmpge. */
-- return 1277;
-+ return 1331;
- }
- else
- {
-@@ -6246,7 +8127,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001001x0xx0xxxxx010xxxxxxxx1xxxx
- cmpgt. */
-- return 1280;
-+ return 1334;
- }
- }
- else
-@@ -6259,7 +8140,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 101001x0000xxxxx010xxxxxxxxxxxxx
- ld1b. */
-- return 1458;
-+ return 1512;
- }
- else
- {
-@@ -6267,7 +8148,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 101001x0100xxxxx010xxxxxxxxxxxxx
- ld1sw. */
-- return 1538;
-+ return 1592;
- }
- }
- else
-@@ -6278,7 +8159,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 101001x0010xxxxx010xxxxxxxxxxxxx
- ld1b. */
-- return 1460;
-+ return 1514;
- }
- else
- {
-@@ -6286,7 +8167,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 101001x0110xxxxx010xxxxxxxxxxxxx
- ld1h. */
-- return 1480;
-+ return 1534;
- }
- }
- }
-@@ -6304,7 +8185,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001001x0xx0xxxxx001xxxxxxxx0xxxx
- cmpeq. */
-- return 1274;
-+ return 1328;
- }
- else
- {
-@@ -6312,7 +8193,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001001x0xx0xxxxx001xxxxxxxx1xxxx
- cmpne. */
-- return 1297;
-+ return 1351;
- }
- }
- else
-@@ -6323,7 +8204,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 101001x00x0xxxxx001xxxxxxxxxxxxx
- ld1rqb. */
-- return 1499;
-+ return 1553;
- }
- else
- {
-@@ -6331,7 +8212,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 101001x01x0xxxxx001xxxxxxxxxxxxx
- ld1rqh. */
-- return 1503;
-+ return 1557;
- }
- }
- }
-@@ -6345,7 +8226,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001001x0xx0xxxxx011xxxxxxxx0xxxx
- cmplt. */
-- return 1295;
-+ return 1349;
- }
- else
- {
-@@ -6353,7 +8234,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001001x0xx0xxxxx011xxxxxxxx1xxxx
- cmple. */
-- return 1289;
-+ return 1343;
- }
- }
- else
-@@ -6366,7 +8247,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 101001x0000xxxxx011xxxxxxxxxxxxx
- ldff1b. */
-- return 1582;
-+ return 1636;
- }
- else
- {
-@@ -6374,7 +8255,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 101001x0100xxxxx011xxxxxxxxxxxxx
- ldff1sw. */
-- return 1625;
-+ return 1692;
- }
- }
- else
-@@ -6385,7 +8266,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 101001x0010xxxxx011xxxxxxxxxxxxx
- ldff1b. */
-- return 1584;
-+ return 1640;
- }
- else
- {
-@@ -6393,7 +8274,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 101001x0110xxxxx011xxxxxxxxxxxxx
- ldff1h. */
-- return 1599;
-+ return 1659;
- }
- }
- }
-@@ -6408,7 +8289,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 011001x0xx0xxxxx0xxxxxxxxxxxxxxx
- fcmla. */
-- return 1343;
-+ return 1397;
- }
- else
- {
-@@ -6420,7 +8301,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 111001x0x00xxxxx0x0xxxxxxxxxxxxx
- st1b. */
-- return 1804;
-+ return 1874;
- }
- else
- {
-@@ -6430,7 +8311,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 111001x0010xxxxx0x0xxxxxxxxxxxxx
- st1b. */
-- return 1808;
-+ return 1878;
- }
- else
- {
-@@ -6438,48 +8319,92 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 111001x0110xxxxx0x0xxxxxxxxxxxxx
- st1h. */
-- return 1829;
-+ return 1899;
- }
- }
- }
- else
- {
-- if (((word >> 22) & 0x1) == 0)
-+ if (((word >> 14) & 0x1) == 0)
- {
-- if (((word >> 23) & 0x1) == 0)
-+ if (((word >> 22) & 0x1) == 0)
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 111001x0000xxxxx0x1xxxxxxxxxxxxx
-- stnt1b. */
-- return 1874;
-+ if (((word >> 23) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 111001x0000xxxxx001xxxxxxxxxxxxx
-+ stnt1b. */
-+ return 2251;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 111001x0100xxxxx001xxxxxxxxxxxxx
-+ stnt1h. */
-+ return 2254;
-+ }
- }
- else
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 111001x0100xxxxx0x1xxxxxxxxxxxxx
-- stnt1h. */
-- return 1878;
-+ if (((word >> 23) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 111001x0010xxxxx001xxxxxxxxxxxxx
-+ stnt1b. */
-+ return 2250;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 111001x0110xxxxx001xxxxxxxxxxxxx
-+ stnt1h. */
-+ return 2253;
-+ }
- }
- }
- else
- {
-- if (((word >> 23) & 0x1) == 0)
-+ if (((word >> 22) & 0x1) == 0)
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 111001x0010xxxxx0x1xxxxxxxxxxxxx
-- st3b. */
-- return 1858;
-+ if (((word >> 23) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 111001x0000xxxxx011xxxxxxxxxxxxx
-+ stnt1b. */
-+ return 1944;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 111001x0100xxxxx011xxxxxxxxxxxxx
-+ stnt1h. */
-+ return 1948;
-+ }
- }
- else
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 111001x0110xxxxx0x1xxxxxxxxxxxxx
-- st3h. */
-- return 1862;
-+ if (((word >> 23) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 111001x0010xxxxx011xxxxxxxxxxxxx
-+ st3b. */
-+ return 1928;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 111001x0110xxxxx011xxxxxxxxxxxxx
-+ st3h. */
-+ return 1932;
-+ }
- }
- }
- }
-@@ -6500,7 +8425,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x01001x0xx0xxxxx100xxxxxxxx0xxxx
- cmpge. */
-- return 1278;
-+ return 1332;
- }
- else
- {
-@@ -6508,7 +8433,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x01001x0xx0xxxxx100xxxxxxxx1xxxx
- cmpgt. */
-- return 1281;
-+ return 1335;
- }
- }
- else
-@@ -6521,7 +8446,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001001x0xx0xxxxx110xxxxxxxx0xxxx
- cmphs. */
-- return 1287;
-+ return 1341;
- }
- else
- {
-@@ -6529,7 +8454,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001001x0xx0xxxxx110xxxxxxxx1xxxx
- cmphi. */
-- return 1284;
-+ return 1338;
- }
- }
- else
-@@ -6542,7 +8467,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 101001x0000xxxxx110xxxxxxxxxxxxx
- ldnt1b. */
-- return 1657;
-+ return 1727;
- }
- else
- {
-@@ -6550,7 +8475,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 101001x0100xxxxx110xxxxxxxxxxxxx
- ldnt1h. */
-- return 1661;
-+ return 1731;
- }
- }
- else
-@@ -6561,7 +8486,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 101001x0010xxxxx110xxxxxxxxxxxxx
- ld3b. */
-- return 1565;
-+ return 1619;
- }
- else
- {
-@@ -6569,7 +8494,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 101001x0110xxxxx110xxxxxxxxxxxxx
- ld3h. */
-- return 1569;
-+ return 1623;
- }
- }
- }
-@@ -6579,11 +8504,66 @@ aarch64_opcode_lookup_1 (uint32_t word)
- {
- if (((word >> 31) & 0x1) == 0)
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 011001x0xx0xxxxx1x0xxxxxxxxxxxxx
-- fcadd. */
-- return 1342;
-+ if (((word >> 17) & 0x1) == 0)
-+ {
-+ if (((word >> 18) & 0x1) == 0)
-+ {
-+ if (((word >> 20) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 011001x0xx00x00x1x0xxxxxxxxxxxxx
-+ fcadd. */
-+ return 1396;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 011001x0xx01x00x1x0xxxxxxxxxxxxx
-+ faddp. */
-+ return 2077;
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 16) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 011001x0xx0xx1001x0xxxxxxxxxxxxx
-+ fmaxnmp. */
-+ return 2085;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 011001x0xx0xx1011x0xxxxxxxxxxxxx
-+ fminnmp. */
-+ return 2087;
-+ }
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 16) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 011001x0xx0xxx101x0xxxxxxxxxxxxx
-+ fmaxp. */
-+ return 2086;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 011001x0xx0xxx111x0xxxxxxxxxxxxx
-+ fminp. */
-+ return 2088;
-+ }
-+ }
- }
- else
- {
-@@ -6595,7 +8575,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 111001x0000xxxxx1x0xxxxxxxxxxxxx
- st1b. */
-- return 1805;
-+ return 1875;
- }
- else
- {
-@@ -6603,7 +8583,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 111001x0100xxxxx1x0xxxxxxxxxxxxx
- st1h. */
-- return 1824;
-+ return 1894;
- }
- }
- else
-@@ -6614,7 +8594,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 111001x0010xxxxx1x0xxxxxxxxxxxxx
- st1b. */
-- return 1809;
-+ return 1879;
- }
- else
- {
-@@ -6622,7 +8602,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 111001x0110xxxxx1x0xxxxxxxxxxxxx
- st1h. */
-- return 1830;
-+ return 1900;
- }
- }
- }
-@@ -6642,7 +8622,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001001x0xx0xxxxx101xxxxxxxx0xxxx
- cmpeq. */
-- return 1275;
-+ return 1329;
- }
- else
- {
-@@ -6650,7 +8630,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001001x0xx0xxxxx101xxxxxxxx1xxxx
- cmpne. */
-- return 1298;
-+ return 1352;
- }
- }
- else
-@@ -6665,7 +8645,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 101001x00000xxxx101xxxxxxxxxxxxx
- ld1b. */
-- return 1465;
-+ return 1519;
- }
- else
- {
-@@ -6673,7 +8653,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 101001x01000xxxx101xxxxxxxxxxxxx
- ld1sw. */
-- return 1543;
-+ return 1597;
- }
- }
- else
-@@ -6684,7 +8664,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 101001x00100xxxx101xxxxxxxxxxxxx
- ld1b. */
-- return 1467;
-+ return 1521;
- }
- else
- {
-@@ -6692,7 +8672,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 101001x01100xxxx101xxxxxxxxxxxxx
- ld1h. */
-- return 1488;
-+ return 1542;
- }
- }
- }
-@@ -6706,7 +8686,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 101001x00001xxxx101xxxxxxxxxxxxx
- ldnf1b. */
-- return 1641;
-+ return 1711;
- }
- else
- {
-@@ -6714,7 +8694,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 101001x01001xxxx101xxxxxxxxxxxxx
- ldnf1sw. */
-- return 1654;
-+ return 1724;
- }
- }
- else
-@@ -6725,7 +8705,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 101001x00101xxxx101xxxxxxxxxxxxx
- ldnf1b. */
-- return 1643;
-+ return 1713;
- }
- else
- {
-@@ -6733,7 +8713,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 101001x01101xxxx101xxxxxxxxxxxxx
- ldnf1h. */
-- return 1647;
-+ return 1717;
- }
- }
- }
-@@ -6745,19 +8725,63 @@ aarch64_opcode_lookup_1 (uint32_t word)
- {
- if (((word >> 23) & 0x1) == 0)
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- x11001x0000xxxxx101xxxxxxxxxxxxx
-- st1b. */
-- return 1806;
-+ if (((word >> 31) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 011001x0000xxxxx101xxxxxxxxxxxxx
-+ fcvtxnt. */
-+ return 2083;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 111001x0000xxxxx101xxxxxxxxxxxxx
-+ st1b. */
-+ return 1876;
-+ }
- }
- else
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- x11001x0100xxxxx101xxxxxxxxxxxxx
-- st1h. */
-- return 1825;
-+ if (((word >> 31) & 0x1) == 0)
-+ {
-+ if (((word >> 16) & 0x1) == 0)
-+ {
-+ if (((word >> 17) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 011001x0100xxx00101xxxxxxxxxxxxx
-+ fcvtnt. */
-+ return 2080;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 011001x0100xxx10101xxxxxxxxxxxxx
-+ bfcvtnt. */
-+ return 2433;
-+ }
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 011001x0100xxxx1101xxxxxxxxxxxxx
-+ fcvtlt. */
-+ return 2078;
-+ }
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 111001x0100xxxxx101xxxxxxxxxxxxx
-+ st1h. */
-+ return 1895;
-+ }
- }
- }
- else
-@@ -6768,15 +8792,37 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x11001x0010xxxxx101xxxxxxxxxxxxx
- st1b. */
-- return 1813;
-+ return 1883;
- }
- else
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- x11001x0110xxxxx101xxxxxxxxxxxxx
-- st1h. */
-- return 1834;
-+ if (((word >> 31) & 0x1) == 0)
-+ {
-+ if (((word >> 16) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 011001x0110xxxx0101xxxxxxxxxxxxx
-+ fcvtnt. */
-+ return 2081;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 011001x0110xxxx1101xxxxxxxxxxxxx
-+ fcvtlt. */
-+ return 2079;
-+ }
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 111001x0110xxxxx101xxxxxxxxxxxxx
-+ st1h. */
-+ return 1904;
-+ }
- }
- }
- }
-@@ -6793,7 +8839,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001001x0xx0xxxxx111xxxxxxxx0xxxx
- cmplo. */
-- return 1291;
-+ return 1345;
- }
- else
- {
-@@ -6801,7 +8847,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001001x0xx0xxxxx111xxxxxxxx1xxxx
- cmpls. */
-- return 1293;
-+ return 1347;
- }
- }
- else
-@@ -6814,7 +8860,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 101001x0000xxxxx111xxxxxxxxxxxxx
- ldnt1b. */
-- return 1658;
-+ return 1728;
- }
- else
- {
-@@ -6822,7 +8868,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 101001x0100xxxxx111xxxxxxxxxxxxx
- ldnt1h. */
-- return 1662;
-+ return 1732;
- }
- }
- else
-@@ -6833,7 +8879,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 101001x0010xxxxx111xxxxxxxxxxxxx
- ld3b. */
-- return 1566;
-+ return 1620;
- }
- else
- {
-@@ -6841,7 +8887,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 101001x0110xxxxx111xxxxxxxxxxxxx
- ld3h. */
-- return 1570;
-+ return 1624;
- }
- }
- }
-@@ -6856,7 +8902,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x11001x0x000xxxx111xxxxxxxxxxxxx
- st1b. */
-- return 1811;
-+ return 1881;
- }
- else
- {
-@@ -6866,7 +8912,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x11001x00100xxxx111xxxxxxxxxxxxx
- st1b. */
-- return 1814;
-+ return 1884;
- }
- else
- {
-@@ -6874,7 +8920,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x11001x01100xxxx111xxxxxxxxxxxxx
- st1h. */
-- return 1835;
-+ return 1905;
- }
- }
- }
-@@ -6888,7 +8934,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x11001x00001xxxx111xxxxxxxxxxxxx
- stnt1b. */
-- return 1875;
-+ return 1945;
- }
- else
- {
-@@ -6896,7 +8942,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x11001x01001xxxx111xxxxxxxxxxxxx
- stnt1h. */
-- return 1879;
-+ return 1949;
- }
- }
- else
-@@ -6907,7 +8953,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x11001x00101xxxx111xxxxxxxxxxxxx
- st3b. */
-- return 1859;
-+ return 1929;
- }
- else
- {
-@@ -6915,7 +8961,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x11001x01101xxxx111xxxxxxxxxxxxx
- st3h. */
-- return 1863;
-+ return 1933;
- }
- }
- }
-@@ -6938,7 +8984,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001001x0xx1xxxxxxx0xxxxxxxx0xxxx
- cmphs. */
-- return 1288;
-+ return 1342;
- }
- else
- {
-@@ -6946,90 +8992,112 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001001x0xx1xxxxxxx0xxxxxxxx1xxxx
- cmphi. */
-- return 1285;
-+ return 1339;
- }
- }
- else
- {
-- if (((word >> 15) & 0x1) == 0)
-+ if (((word >> 14) & 0x1) == 0)
- {
-- if (((word >> 22) & 0x1) == 0)
-+ if (((word >> 23) & 0x1) == 0)
- {
-- if (((word >> 23) & 0x1) == 0)
-- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 101001x0001xxxxx0x0xxxxxxxxxxxxx
-- ld1b. */
-- return 1459;
-- }
-- else
-- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 101001x0101xxxxx0x0xxxxxxxxxxxxx
-- ld1h. */
-- return 1479;
-- }
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 101001x00x1xxxxxx00xxxxxxxxxxxxx
-+ ld1rob. */
-+ return 2409;
- }
- else
- {
-- if (((word >> 23) & 0x1) == 0)
-- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 101001x0011xxxxx0x0xxxxxxxxxxxxx
-- ld1b. */
-- return 1461;
-- }
-- else
-- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 101001x0111xxxxx0x0xxxxxxxxxxxxx
-- ld1h. */
-- return 1481;
-- }
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 101001x01x1xxxxxx00xxxxxxxxxxxxx
-+ ld1roh. */
-+ return 2410;
- }
- }
- else
- {
-- if (((word >> 22) & 0x1) == 0)
-+ if (((word >> 15) & 0x1) == 0)
- {
-- if (((word >> 23) & 0x1) == 0)
-+ if (((word >> 22) & 0x1) == 0)
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 101001x0001xxxxx1x0xxxxxxxxxxxxx
-- ld2b. */
-- return 1557;
-+ if (((word >> 23) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 101001x0001xxxxx010xxxxxxxxxxxxx
-+ ld1b. */
-+ return 1513;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 101001x0101xxxxx010xxxxxxxxxxxxx
-+ ld1h. */
-+ return 1533;
-+ }
- }
- else
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 101001x0101xxxxx1x0xxxxxxxxxxxxx
-- ld2h. */
-- return 1561;
-+ if (((word >> 23) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 101001x0011xxxxx010xxxxxxxxxxxxx
-+ ld1b. */
-+ return 1515;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 101001x0111xxxxx010xxxxxxxxxxxxx
-+ ld1h. */
-+ return 1535;
-+ }
- }
- }
- else
- {
-- if (((word >> 23) & 0x1) == 0)
-+ if (((word >> 22) & 0x1) == 0)
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 101001x0011xxxxx1x0xxxxxxxxxxxxx
-- ld4b. */
-- return 1573;
-+ if (((word >> 23) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 101001x0001xxxxx110xxxxxxxxxxxxx
-+ ld2b. */
-+ return 1611;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 101001x0101xxxxx110xxxxxxxxxxxxx
-+ ld2h. */
-+ return 1615;
-+ }
- }
- else
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 101001x0111xxxxx1x0xxxxxxxxxxxxx
-- ld4h. */
-- return 1577;
-+ if (((word >> 23) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 101001x0011xxxxx110xxxxxxxxxxxxx
-+ ld4b. */
-+ return 1627;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 101001x0111xxxxx110xxxxxxxxxxxxx
-+ ld4h. */
-+ return 1631;
-+ }
- }
- }
- }
-@@ -7051,7 +9119,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x11001x00x1xxxxx0000x0xxxxxxxxxx
- fmla. */
-- return 1396;
-+ return 1450;
- }
- else
- {
-@@ -7061,7 +9129,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x11001x0101xxxxx0000x0xxxxxxxxxx
- fmla. */
-- return 1397;
-+ return 1451;
- }
- else
- {
-@@ -7069,7 +9137,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x11001x0111xxxxx0000x0xxxxxxxxxx
- fmla. */
-- return 1398;
-+ return 1452;
- }
- }
- }
-@@ -7081,7 +9149,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x11001x00x1xxxxx0000x1xxxxxxxxxx
- fmls. */
-- return 1400;
-+ return 1454;
- }
- else
- {
-@@ -7091,7 +9159,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x11001x0101xxxxx0000x1xxxxxxxxxx
- fmls. */
-- return 1401;
-+ return 1455;
- }
- else
- {
-@@ -7099,7 +9167,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x11001x0111xxxxx0000x1xxxxxxxxxx
- fmls. */
-- return 1402;
-+ return 1456;
- }
- }
- }
-@@ -7112,7 +9180,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x11001x0x01xxxxx0001xxxxxxxxxxxx
- fcmla. */
-- return 1344;
-+ return 1398;
- }
- else
- {
-@@ -7120,7 +9188,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x11001x0x11xxxxx0001xxxxxxxxxxxx
- fcmla. */
-- return 1345;
-+ return 1399;
- }
- }
- }
-@@ -7134,34 +9202,89 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x11001x0001xxxxx010xxxxxxxxxxxxx
- st1b. */
-- return 1807;
-+ return 1877;
- }
- else
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- x11001x0101xxxxx010xxxxxxxxxxxxx
-- st1h. */
-- return 1826;
-+ if (((word >> 31) & 0x1) == 0)
-+ {
-+ if (((word >> 10) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 011001x0101xxxxx010xx0xxxxxxxxxx
-+ fmlalb. */
-+ return 2089;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 011001x0101xxxxx010xx1xxxxxxxxxx
-+ fmlalt. */
-+ return 2091;
-+ }
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 111001x0101xxxxx010xxxxxxxxxxxxx
-+ st1h. */
-+ return 1896;
-+ }
- }
- }
- else
- {
- if (((word >> 23) & 0x1) == 0)
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- x11001x0011xxxxx010xxxxxxxxxxxxx
-- st1b. */
-- return 1810;
-+ if (((word >> 31) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 011001x0011xxxxx010xxxxxxxxxxxxx
-+ bfdot. */
-+ return 2430;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 111001x0011xxxxx010xxxxxxxxxxxxx
-+ st1b. */
-+ return 1880;
-+ }
- }
- else
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- x11001x0111xxxxx010xxxxxxxxxxxxx
-- st1h. */
-- return 1831;
-+ if (((word >> 31) & 0x1) == 0)
-+ {
-+ if (((word >> 10) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 011001x0111xxxxx010xx0xxxxxxxxxx
-+ bfmlalb. */
-+ return 2437;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 011001x0111xxxxx010xx1xxxxxxxxxx
-+ bfmlalt. */
-+ return 2436;
-+ }
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 111001x0111xxxxx010xxxxxxxxxxxxx
-+ st1h. */
-+ return 1901;
-+ }
- }
- }
- }
-@@ -7170,19 +9293,74 @@ aarch64_opcode_lookup_1 (uint32_t word)
- {
- if (((word >> 22) & 0x1) == 0)
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- x11001x0x01xxxxx1x0xxxxxxxxxxxxx
-- st1h. */
-- return 1827;
-+ if (((word >> 31) & 0x1) == 0)
-+ {
-+ if (((word >> 10) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 011001x0x01xxxxx1x0xx0xxxxxxxxxx
-+ fmlalb. */
-+ return 2090;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 011001x0x01xxxxx1x0xx1xxxxxxxxxx
-+ fmlalt. */
-+ return 2092;
-+ }
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 111001x0x01xxxxx1x0xxxxxxxxxxxxx
-+ st1h. */
-+ return 1897;
-+ }
- }
- else
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- x11001x0x11xxxxx1x0xxxxxxxxxxxxx
-- st1h. */
-- return 1832;
-+ if (((word >> 23) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ x11001x0011xxxxx1x0xxxxxxxxxxxxx
-+ bfdot. */
-+ return 2429;
-+ }
-+ else
-+ {
-+ if (((word >> 31) & 0x1) == 0)
-+ {
-+ if (((word >> 10) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 011001x0111xxxxx1x0xx0xxxxxxxxxx
-+ bfmlalb. */
-+ return 2435;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 011001x0111xxxxx1x0xx1xxxxxxxxxx
-+ bfmlalt. */
-+ return 2434;
-+ }
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 111001x0111xxxxx1x0xxxxxxxxxxxxx
-+ st1h. */
-+ return 1902;
-+ }
-+ }
- }
- }
- }
-@@ -7199,7 +9377,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001001x0xx1xxxxxxx1xxxxxxxx0xxxx
- cmplo. */
-- return 1292;
-+ return 1346;
- }
- else
- {
-@@ -7207,92 +9385,114 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001001x0xx1xxxxxxx1xxxxxxxx1xxxx
- cmpls. */
-- return 1294;
-+ return 1348;
- }
- }
- else
- {
- if (((word >> 14) & 0x1) == 0)
- {
-- if (((word >> 20) & 0x1) == 0)
-+ if (((word >> 15) & 0x1) == 0)
- {
-- if (((word >> 22) & 0x1) == 0)
-+ if (((word >> 23) & 0x1) == 0)
- {
-- if (((word >> 23) & 0x1) == 0)
-- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 101001x00010xxxxx01xxxxxxxxxxxxx
-- ld1b. */
-- return 1466;
-- }
-- else
-- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 101001x01010xxxxx01xxxxxxxxxxxxx
-- ld1h. */
-- return 1487;
-- }
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 101001x00x1xxxxx001xxxxxxxxxxxxx
-+ ld1rob. */
-+ return 2413;
- }
- else
- {
-- if (((word >> 23) & 0x1) == 0)
-- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 101001x00110xxxxx01xxxxxxxxxxxxx
-- ld1b. */
-- return 1468;
-- }
-- else
-- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 101001x01110xxxxx01xxxxxxxxxxxxx
-- ld1h. */
-- return 1489;
-- }
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 101001x01x1xxxxx001xxxxxxxxxxxxx
-+ ld1roh. */
-+ return 2414;
- }
- }
- else
- {
-- if (((word >> 22) & 0x1) == 0)
-+ if (((word >> 20) & 0x1) == 0)
- {
-- if (((word >> 23) & 0x1) == 0)
-+ if (((word >> 22) & 0x1) == 0)
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 101001x00011xxxxx01xxxxxxxxxxxxx
-- ldnf1b. */
-- return 1642;
-+ if (((word >> 23) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 101001x00010xxxx101xxxxxxxxxxxxx
-+ ld1b. */
-+ return 1520;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 101001x01010xxxx101xxxxxxxxxxxxx
-+ ld1h. */
-+ return 1541;
-+ }
- }
- else
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 101001x01011xxxxx01xxxxxxxxxxxxx
-- ldnf1h. */
-- return 1646;
-+ if (((word >> 23) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 101001x00110xxxx101xxxxxxxxxxxxx
-+ ld1b. */
-+ return 1522;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 101001x01110xxxx101xxxxxxxxxxxxx
-+ ld1h. */
-+ return 1543;
-+ }
- }
- }
- else
- {
-- if (((word >> 23) & 0x1) == 0)
-+ if (((word >> 22) & 0x1) == 0)
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 101001x00111xxxxx01xxxxxxxxxxxxx
-- ldnf1b. */
-- return 1644;
-+ if (((word >> 23) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 101001x00011xxxx101xxxxxxxxxxxxx
-+ ldnf1b. */
-+ return 1712;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 101001x01011xxxx101xxxxxxxxxxxxx
-+ ldnf1h. */
-+ return 1716;
-+ }
- }
- else
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 101001x01111xxxxx01xxxxxxxxxxxxx
-- ldnf1h. */
-- return 1648;
-+ if (((word >> 23) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 101001x00111xxxx101xxxxxxxxxxxxx
-+ ldnf1b. */
-+ return 1714;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 101001x01111xxxx101xxxxxxxxxxxxx
-+ ldnf1h. */
-+ return 1718;
-+ }
- }
- }
- }
-@@ -7309,7 +9509,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 101001x0001xxxxx011xxxxxxxxxxxxx
- ldff1b. */
-- return 1583;
-+ return 1638;
- }
- else
- {
-@@ -7317,7 +9517,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 101001x0101xxxxx011xxxxxxxxxxxxx
- ldff1h. */
-- return 1598;
-+ return 1657;
- }
- }
- else
-@@ -7328,7 +9528,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 101001x0011xxxxx011xxxxxxxxxxxxx
- ldff1b. */
-- return 1585;
-+ return 1642;
- }
- else
- {
-@@ -7336,7 +9536,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 101001x0111xxxxx011xxxxxxxxxxxxx
- ldff1h. */
-- return 1600;
-+ return 1661;
- }
- }
- }
-@@ -7350,7 +9550,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 101001x0001xxxxx111xxxxxxxxxxxxx
- ld2b. */
-- return 1558;
-+ return 1612;
- }
- else
- {
-@@ -7358,7 +9558,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 101001x0101xxxxx111xxxxxxxxxxxxx
- ld2h. */
-- return 1562;
-+ return 1616;
- }
- }
- else
-@@ -7369,7 +9569,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 101001x0011xxxxx111xxxxxxxxxxxxx
- ld4b. */
-- return 1574;
-+ return 1628;
- }
- else
- {
-@@ -7377,7 +9577,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 101001x0111xxxxx111xxxxxxxxxxxxx
- ld4h. */
-- return 1578;
-+ return 1632;
- }
- }
- }
-@@ -7396,7 +9596,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x11001x00x1xxxxx001xxxxxxxxxxxxx
- fmul. */
-- return 1407;
-+ return 1461;
- }
- else
- {
-@@ -7406,7 +9606,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x11001x0101xxxxx001xxxxxxxxxxxxx
- fmul. */
-- return 1408;
-+ return 1462;
- }
- else
- {
-@@ -7414,7 +9614,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x11001x0111xxxxx001xxxxxxxxxxxxx
- fmul. */
-- return 1409;
-+ return 1463;
- }
- }
- }
-@@ -7422,11 +9622,33 @@ aarch64_opcode_lookup_1 (uint32_t word)
- {
- if (((word >> 22) & 0x1) == 0)
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- x11001x0x01xxxxx101xxxxxxxxxxxxx
-- st1h. */
-- return 1828;
-+ if (((word >> 31) & 0x1) == 0)
-+ {
-+ if (((word >> 10) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 011001x0x01xxxxx101xx0xxxxxxxxxx
-+ fmlslb. */
-+ return 2094;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 011001x0x01xxxxx101xx1xxxxxxxxxx
-+ fmlslt. */
-+ return 2096;
-+ }
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 111001x0x01xxxxx101xxxxxxxxxxxxx
-+ st1h. */
-+ return 1898;
-+ }
- }
- else
- {
-@@ -7436,7 +9658,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x11001x0011xxxxx101xxxxxxxxxxxxx
- st1b. */
-- return 1815;
-+ return 1885;
- }
- else
- {
-@@ -7444,7 +9666,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x11001x0111xxxxx101xxxxxxxxxxxxx
- st1h. */
-- return 1836;
-+ return 1906;
- }
- }
- }
-@@ -7461,15 +9683,37 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x11001x0001xxxxx011xxxxxxxxxxxxx
- st2b. */
-- return 1850;
-+ return 1920;
- }
- else
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- x11001x0101xxxxx011xxxxxxxxxxxxx
-- st2h. */
-- return 1854;
-+ if (((word >> 31) & 0x1) == 0)
-+ {
-+ if (((word >> 10) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 011001x0101xxxxx011xx0xxxxxxxxxx
-+ fmlslb. */
-+ return 2093;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 011001x0101xxxxx011xx1xxxxxxxxxx
-+ fmlslt. */
-+ return 2095;
-+ }
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 111001x0101xxxxx011xxxxxxxxxxxxx
-+ st2h. */
-+ return 1924;
-+ }
- }
- }
- else
-@@ -7480,7 +9724,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x11001x0011xxxxx011xxxxxxxxxxxxx
- st4b. */
-- return 1866;
-+ return 1936;
- }
- else
- {
-@@ -7488,91 +9732,124 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x11001x0111xxxxx011xxxxxxxxxxxxx
- st4h. */
-- return 1870;
-+ return 1940;
- }
- }
- }
- else
- {
-- if (((word >> 20) & 0x1) == 0)
-+ if (((word >> 22) & 0x1) == 0)
- {
-- if (((word >> 22) & 0x1) == 0)
-+ if (((word >> 23) & 0x1) == 0)
- {
-- if (((word >> 23) & 0x1) == 0)
-+ if (((word >> 20) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x11001x00010xxxx111xxxxxxxxxxxxx
- st1b. */
-- return 1812;
-+ return 1882;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
-- x11001x01010xxxx111xxxxxxxxxxxxx
-- st1h. */
-- return 1833;
-+ x11001x00011xxxx111xxxxxxxxxxxxx
-+ st2b. */
-+ return 1921;
- }
- }
- else
- {
-- if (((word >> 23) & 0x1) == 0)
-+ if (((word >> 31) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
-- x11001x00110xxxx111xxxxxxxxxxxxx
-- st1b. */
-- return 1816;
-+ 011001x0101xxxxx111xxxxxxxxxxxxx
-+ fmmla. */
-+ return 2407;
- }
- else
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- x11001x01110xxxx111xxxxxxxxxxxxx
-- st1h. */
-- return 1837;
-+ if (((word >> 20) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 111001x01010xxxx111xxxxxxxxxxxxx
-+ st1h. */
-+ return 1903;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 111001x01011xxxx111xxxxxxxxxxxxx
-+ st2h. */
-+ return 1925;
-+ }
- }
- }
- }
- else
- {
-- if (((word >> 22) & 0x1) == 0)
-+ if (((word >> 23) & 0x1) == 0)
- {
-- if (((word >> 23) & 0x1) == 0)
-+ if (((word >> 31) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
-- x11001x00011xxxx111xxxxxxxxxxxxx
-- st2b. */
-- return 1851;
-+ 011001x0011xxxxx111xxxxxxxxxxxxx
-+ bfmmla. */
-+ return 2431;
- }
- else
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- x11001x01011xxxx111xxxxxxxxxxxxx
-- st2h. */
-- return 1855;
-+ if (((word >> 20) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 111001x00110xxxx111xxxxxxxxxxxxx
-+ st1b. */
-+ return 1886;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 111001x00111xxxx111xxxxxxxxxxxxx
-+ st4b. */
-+ return 1937;
-+ }
- }
- }
- else
- {
-- if (((word >> 23) & 0x1) == 0)
-+ if (((word >> 31) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
-- x11001x00111xxxx111xxxxxxxxxxxxx
-- st4b. */
-- return 1867;
-+ 011001x0111xxxxx111xxxxxxxxxxxxx
-+ fmmla. */
-+ return 2408;
- }
- else
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- x11001x01111xxxx111xxxxxxxxxxxxx
-- st4h. */
-- return 1871;
-+ if (((word >> 20) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 111001x01110xxxx111xxxxxxxxxxxxx
-+ st1h. */
-+ return 1907;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 111001x01111xxxx111xxxxxxxxxxxxx
-+ st4h. */
-+ return 1941;
-+ }
- }
- }
- }
-@@ -7603,7 +9880,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x10000xxxxxxxxxxxxxxxxxxxx
- orr. */
-- return 1696;
-+ return 1766;
- }
- else
- {
-@@ -7611,7 +9888,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x11000xxxxxxxxxxxxxxxxxxxx
- and. */
-- return 1240;
-+ return 1294;
- }
- }
- else
-@@ -7622,7 +9899,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x10100xxxxxxxxxxxxxxxxxxxx
- eor. */
-- return 1327;
-+ return 1381;
- }
- else
- {
-@@ -7630,7 +9907,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x11100xxxxxxxxxxxxxxxxxxxx
- dupm. */
-- return 1325;
-+ return 1379;
- }
- }
- }
-@@ -7642,7 +9919,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x1xx01xxxx0xxxxxxxxxxxxxxx
- cpy. */
-- return 1310;
-+ return 1364;
- }
- else
- {
-@@ -7650,7 +9927,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x1xx01xxxx1xxxxxxxxxxxxxxx
- fcpy. */
-- return 1357;
-+ return 1411;
- }
- }
- }
-@@ -7662,11 +9939,88 @@ aarch64_opcode_lookup_1 (uint32_t word)
- {
- if (((word >> 15) & 0x1) == 0)
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 000001x1xx1xxxxx000xxxxxxxxxxxxx
-- ext. */
-- return 1332;
-+ if (((word >> 22) & 0x1) == 0)
-+ {
-+ if (((word >> 23) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 000001x1001xxxxx000xxxxxxxxxxxxx
-+ ext. */
-+ return 1386;
-+ }
-+ else
-+ {
-+ if (((word >> 10) & 0x1) == 0)
-+ {
-+ if (((word >> 11) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 000001x1101xxxxx000x00xxxxxxxxxx
-+ zip1. */
-+ return 2417;
-+ }
-+ else
-+ {
-+ if (((word >> 12) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 000001x1101xxxxx000010xxxxxxxxxx
-+ uzp1. */
-+ return 2419;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 000001x1101xxxxx000110xxxxxxxxxx
-+ trn1. */
-+ return 2421;
-+ }
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 11) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 000001x1101xxxxx000x01xxxxxxxxxx
-+ zip2. */
-+ return 2418;
-+ }
-+ else
-+ {
-+ if (((word >> 12) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 000001x1101xxxxx000011xxxxxxxxxx
-+ uzp2. */
-+ return 2420;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 000001x1101xxxxx000111xxxxxxxxxx
-+ trn2. */
-+ return 2422;
-+ }
-+ }
-+ }
-+ }
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 000001x1x11xxxxx000xxxxxxxxxxxxx
-+ ext. */
-+ return 2076;
-+ }
- }
- else
- {
-@@ -7682,7 +10036,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x1xx1x0000100xxxxxxxxxxxxx
- cpy. */
-- return 1308;
-+ return 1362;
- }
- else
- {
-@@ -7690,7 +10044,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x1xx1x1000100xxxxxxxxxxxxx
- clasta. */
-- return 1266;
-+ return 1320;
- }
- }
- else
-@@ -7701,7 +10055,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x1xx1x0100100xxxxxxxxxxxxx
- revb. */
-- return 1744;
-+ return 1814;
- }
- else
- {
-@@ -7709,7 +10063,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x1xx1x1100100xxxxxxxxxxxxx
- splice. */
-- return 1771;
-+ return 1841;
- }
- }
- }
-@@ -7723,7 +10077,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x1xx1x0010100xxxxxxxxxxxxx
- lasta. */
-- return 1454;
-+ return 1508;
- }
- else
- {
-@@ -7731,7 +10085,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x1xx1x1010100xxxxxxxxxxxxx
- clasta. */
-- return 1267;
-+ return 1321;
- }
- }
- else
-@@ -7740,7 +10094,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x1xx1xx110100xxxxxxxxxxxxx
- revw. */
-- return 1746;
-+ return 1816;
- }
- }
- }
-@@ -7756,7 +10110,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x1xx1x0001100xxxxxxxxxxxxx
- compact. */
-- return 1307;
-+ return 1361;
- }
- else
- {
-@@ -7764,16 +10118,27 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x1xx1x1001100xxxxxxxxxxxxx
- clastb. */
-- return 1269;
-+ return 1323;
- }
- }
- else
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 000001x1xx1xx101100xxxxxxxxxxxxx
-- revh. */
-- return 1745;
-+ if (((word >> 19) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 000001x1xx1x0101100xxxxxxxxxxxxx
-+ revh. */
-+ return 1815;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 000001x1xx1x1101100xxxxxxxxxxxxx
-+ splice. */
-+ return 2171;
-+ }
- }
- }
- else
-@@ -7786,7 +10151,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x1xx1x0011100xxxxxxxxxxxxx
- lastb. */
-- return 1456;
-+ return 1510;
- }
- else
- {
-@@ -7794,7 +10159,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x1xx1x1011100xxxxxxxxxxxxx
- clastb. */
-- return 1270;
-+ return 1324;
- }
- }
- else
-@@ -7803,7 +10168,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x1xx1xx111100xxxxxxxxxxxxx
- rbit. */
-- return 1737;
-+ return 1807;
- }
- }
- }
-@@ -7813,110 +10178,132 @@ aarch64_opcode_lookup_1 (uint32_t word)
- {
- if (((word >> 15) & 0x1) == 0)
- {
-- if (((word >> 11) & 0x1) == 0)
-+ if (((word >> 10) & 0x1) == 0)
- {
-- if (((word >> 12) & 0x1) == 0)
-+ if (((word >> 11) & 0x1) == 0)
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 000001x1xx1xxxxx00100xxxxxxxxxxx
-- dup. */
-- return 1323;
-+ if (((word >> 12) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 000001x1xx1xxxxx001000xxxxxxxxxx
-+ dup. */
-+ return 1377;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 000001x1xx1xxxxx001100xxxxxxxxxx
-+ tbl. */
-+ return 1964;
-+ }
- }
- else
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 000001x1xx1xxxxx00110xxxxxxxxxxx
-- tbl. */
-- return 1894;
-- }
-- }
-- else
-- {
-- if (((word >> 16) & 0x1) == 0)
-- {
-- if (((word >> 17) & 0x1) == 0)
-+ if (((word >> 12) & 0x1) == 0)
- {
-- if (((word >> 18) & 0x1) == 0)
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 000001x1xx1xxxxx001010xxxxxxxxxx
-+ tbl. */
-+ return 2260;
-+ }
-+ else
-+ {
-+ if (((word >> 16) & 0x1) == 0)
- {
-- if (((word >> 19) & 0x1) == 0)
-+ if (((word >> 17) & 0x1) == 0)
- {
-- if (((word >> 20) & 0x1) == 0)
-+ if (((word >> 18) & 0x1) == 0)
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 000001x1xx100000001x1xxxxxxxxxxx
-- dup. */
-- return 1322;
-+ if (((word >> 19) & 0x1) == 0)
-+ {
-+ if (((word >> 20) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 000001x1xx100000001110xxxxxxxxxx
-+ dup. */
-+ return 1376;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 000001x1xx110000001110xxxxxxxxxx
-+ sunpklo. */
-+ return 1960;
-+ }
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 000001x1xx1x1000001110xxxxxxxxxx
-+ rev. */
-+ return 1813;
-+ }
- }
- else
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 000001x1xx110000001x1xxxxxxxxxxx
-- sunpklo. */
-- return 1890;
-+ if (((word >> 20) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 000001x1xx10x100001110xxxxxxxxxx
-+ insr. */
-+ return 1505;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 000001x1xx11x100001110xxxxxxxxxx
-+ insr. */
-+ return 1506;
-+ }
- }
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
-- 000001x1xx1x1000001x1xxxxxxxxxxx
-- rev. */
-- return 1743;
-+ 000001x1xx1xxx10001110xxxxxxxxxx
-+ uunpklo. */
-+ return 2023;
- }
- }
- else
- {
-- if (((word >> 20) & 0x1) == 0)
-+ if (((word >> 17) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
-- 000001x1xx10x100001x1xxxxxxxxxxx
-- insr. */
-- return 1451;
-+ 000001x1xx1xxx01001110xxxxxxxxxx
-+ sunpkhi. */
-+ return 1959;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
-- 000001x1xx11x100001x1xxxxxxxxxxx
-- insr. */
-- return 1452;
-+ 000001x1xx1xxx11001110xxxxxxxxxx
-+ uunpkhi. */
-+ return 2022;
- }
- }
- }
-- else
-- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 000001x1xx1xxx10001x1xxxxxxxxxxx
-- uunpklo. */
-- return 1953;
-- }
-- }
-- else
-- {
-- if (((word >> 17) & 0x1) == 0)
-- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 000001x1xx1xxx01001x1xxxxxxxxxxx
-- sunpkhi. */
-- return 1889;
-- }
-- else
-- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 000001x1xx1xxx11001x1xxxxxxxxxxx
-- uunpkhi. */
-- return 1952;
-- }
- }
- }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 000001x1xx1xxxxx001xx1xxxxxxxxxx
-+ tbx. */
-+ return 2261;
-+ }
- }
- else
- {
-@@ -7930,7 +10317,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x1xx100xx0101xxxxxxxxxxxxx
- lasta. */
-- return 1453;
-+ return 1507;
- }
- else
- {
-@@ -7938,7 +10325,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x1xx110xx0101xxxxxxxxxxxxx
- clasta. */
-- return 1268;
-+ return 1322;
- }
- }
- else
-@@ -7947,7 +10334,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x1xx1x1xx0101xxxxxxxxxxxxx
- cpy. */
-- return 1309;
-+ return 1363;
- }
- }
- else
-@@ -7958,7 +10345,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x1xx10xxx1101xxxxxxxxxxxxx
- lastb. */
-- return 1455;
-+ return 1509;
- }
- else
- {
-@@ -7966,7 +10353,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x1xx11xxx1101xxxxxxxxxxxxx
- clastb. */
-- return 1271;
-+ return 1325;
- }
- }
- }
-@@ -7990,7 +10377,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x1xx10xxxx010000xxxxxxxxxx
- zip1. */
-- return 1970;
-+ return 2040;
- }
- else
- {
-@@ -8002,7 +10389,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x1xx11x0x0010000xxxxxxxxxx
- punpklo. */
-- return 1736;
-+ return 1806;
- }
- else
- {
-@@ -8010,7 +10397,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x1xx11x1x0010000xxxxxxxxxx
- rev. */
-- return 1742;
-+ return 1812;
- }
- }
- else
-@@ -8019,7 +10406,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x1xx11xxx1010000xxxxxxxxxx
- punpkhi. */
-- return 1735;
-+ return 1805;
- }
- }
- }
-@@ -8029,7 +10416,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x1xx1xxxxx011000xxxxxxxxxx
- zip1. */
-- return 1971;
-+ return 2041;
- }
- }
- else
-@@ -8040,7 +10427,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x1xx1xxxxx010100xxxxxxxxxx
- trn1. */
-- return 1895;
-+ return 1965;
- }
- else
- {
-@@ -8048,7 +10435,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x1xx1xxxxx011100xxxxxxxxxx
- trn1. */
-- return 1896;
-+ return 1966;
- }
- }
- }
-@@ -8060,7 +10447,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x1xx1xxxxx010x10xxxxxxxxxx
- uzp1. */
-- return 1957;
-+ return 2027;
- }
- else
- {
-@@ -8068,7 +10455,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x1xx1xxxxx011x10xxxxxxxxxx
- uzp1. */
-- return 1958;
-+ return 2028;
- }
- }
- }
-@@ -8084,7 +10471,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x1xx1xxxxx010001xxxxxxxxxx
- zip2. */
-- return 1972;
-+ return 2042;
- }
- else
- {
-@@ -8092,7 +10479,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x1xx1xxxxx011001xxxxxxxxxx
- zip2. */
-- return 1973;
-+ return 2043;
- }
- }
- else
-@@ -8103,7 +10490,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x1xx1xxxxx010101xxxxxxxxxx
- trn2. */
-- return 1897;
-+ return 1967;
- }
- else
- {
-@@ -8111,7 +10498,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x1xx1xxxxx011101xxxxxxxxxx
- trn2. */
-- return 1898;
-+ return 1968;
- }
- }
- }
-@@ -8123,7 +10510,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x1xx1xxxxx010x11xxxxxxxxxx
- uzp2. */
-- return 1959;
-+ return 2029;
- }
- else
- {
-@@ -8131,7 +10518,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x1xx1xxxxx011x11xxxxxxxxxx
- uzp2. */
-- return 1960;
-+ return 2030;
- }
- }
- }
-@@ -8142,7 +10529,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000001x1xx1xxxxx11xxxxxxxxxxxxxx
- sel. */
-- return 1761;
-+ return 1831;
- }
- }
- }
-@@ -8161,7 +10548,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 100001x1x0xxxxxx000xxxxxxxxxxxxx
- ldr. */
-- return 1665;
-+ return 1735;
- }
- else
- {
-@@ -8169,7 +10556,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 100001x1x1xxxxxx000xxxxxxxxxxxxx
- prfb. */
-- return 1709;
-+ return 1779;
- }
- }
- else
-@@ -8180,7 +10567,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 100001x10xxxxxxx100xxxxxxxxxxxxx
- ld1rsh. */
-- return 1510;
-+ return 1564;
- }
- else
- {
-@@ -8188,7 +10575,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 100001x11xxxxxxx100xxxxxxxxxxxxx
- ld1rsb. */
-- return 1507;
-+ return 1561;
- }
- }
- }
-@@ -8204,7 +10591,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 100001x10x0xxxxx010xxxxxxxxxxxxx
- ld1w. */
-- return 1545;
-+ return 1599;
- }
- else
- {
-@@ -8212,7 +10599,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 100001x10x1xxxxx010xxxxxxxxxxxxx
- ld1w. */
-- return 1546;
-+ return 1600;
- }
- }
- else
-@@ -8223,7 +10610,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 100001x110xxxxxx010xxxxxxxxxxxxx
- ldr. */
-- return 1666;
-+ return 1736;
- }
- else
- {
-@@ -8231,7 +10618,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 100001x111xxxxxx010xxxxxxxxxxxxx
- prfw. */
-- return 1730;
-+ return 1800;
- }
- }
- }
-@@ -8247,7 +10634,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 100001x1000xxxxx110xxxxxxxxxxxxx
- prfw. */
-- return 1726;
-+ return 1796;
- }
- else
- {
-@@ -8255,7 +10642,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 100001x1100xxxxx110xxxxxxxxxxxxx
- prfd. */
-- return 1712;
-+ return 1782;
- }
- }
- else
-@@ -8264,7 +10651,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 100001x1x01xxxxx110xxxxxxxxxxxxx
- ld1w. */
-- return 1553;
-+ return 1607;
- }
- }
- else
-@@ -8275,7 +10662,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 100001x101xxxxxx110xxxxxxxxxxxxx
- ld1rw. */
-- return 1513;
-+ return 1567;
- }
- else
- {
-@@ -8283,7 +10670,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 100001x111xxxxxx110xxxxxxxxxxxxx
- ld1rsb. */
-- return 1509;
-+ return 1563;
- }
- }
- }
-@@ -8299,25 +10686,36 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 100001x1xxxxxxxx001xxxxxxxxxxxxx
- prfh. */
-- return 1723;
-+ return 1793;
- }
- else
- {
-- if (((word >> 23) & 0x1) == 0)
-+ if (((word >> 22) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
-- 100001x10xxxxxxx101xxxxxxxxxxxxx
-- ld1rsh. */
-- return 1511;
-+ 100001x1x0xxxxxx101xxxxxxxxxxxxx
-+ ldnt1w. */
-+ return 2107;
- }
- else
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 100001x11xxxxxxx101xxxxxxxxxxxxx
-- ld1rsb. */
-- return 1508;
-+ if (((word >> 23) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 100001x101xxxxxx101xxxxxxxxxxxxx
-+ ld1rsh. */
-+ return 1565;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 100001x111xxxxxx101xxxxxxxxxxxxx
-+ ld1rsb. */
-+ return 1562;
-+ }
- }
- }
- }
-@@ -8333,7 +10731,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 100001x10x0xxxxx011xxxxxxxxxxxxx
- ldff1w. */
-- return 1631;
-+ return 1699;
- }
- else
- {
-@@ -8341,7 +10739,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 100001x10x1xxxxx011xxxxxxxxxxxxx
- ldff1w. */
-- return 1632;
-+ return 1700;
- }
- }
- else
-@@ -8350,7 +10748,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 100001x11xxxxxxx011xxxxxxxxxxxxx
- prfd. */
-- return 1716;
-+ return 1786;
- }
- }
- else
-@@ -8365,7 +10763,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 100001x1000xxxxx111xxxxxxxxxxxxx
- prfw. */
-- return 1729;
-+ return 1799;
- }
- else
- {
-@@ -8373,7 +10771,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 100001x1100xxxxx111xxxxxxxxxxxxx
- prfd. */
-- return 1715;
-+ return 1785;
- }
- }
- else
-@@ -8382,7 +10780,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 100001x1x01xxxxx111xxxxxxxxxxxxx
- ldff1w. */
-- return 1639;
-+ return 1709;
- }
- }
- else
-@@ -8393,7 +10791,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 100001x101xxxxxx111xxxxxxxxxxxxx
- ld1rw. */
-- return 1514;
-+ return 1568;
- }
- else
- {
-@@ -8401,7 +10799,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 100001x111xxxxxx111xxxxxxxxxxxxx
- ld1rd. */
-- return 1495;
-+ return 1549;
- }
- }
- }
-@@ -8419,48 +10817,345 @@ aarch64_opcode_lookup_1 (uint32_t word)
- {
- if (((word >> 21) & 0x1) == 0)
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- x10001x1xx0xxxxx000xxxxxxxxxxxxx
-- ld1sw. */
-- return 1539;
-+ if (((word >> 31) & 0x1) == 0)
-+ {
-+ if (((word >> 10) & 0x1) == 0)
-+ {
-+ if (((word >> 11) & 0x1) == 0)
-+ {
-+ if (((word >> 12) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1xx0xxxxx000000xxxxxxxxxx
-+ saddlb. */
-+ return 2137;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1xx0xxxxx000100xxxxxxxxxx
-+ ssublb. */
-+ return 2244;
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 12) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1xx0xxxxx000010xxxxxxxxxx
-+ uaddlb. */
-+ return 2268;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1xx0xxxxx000110xxxxxxxxxx
-+ usublb. */
-+ return 2321;
-+ }
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 11) & 0x1) == 0)
-+ {
-+ if (((word >> 12) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1xx0xxxxx000001xxxxxxxxxx
-+ saddlt. */
-+ return 2139;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1xx0xxxxx000101xxxxxxxxxx
-+ ssublt. */
-+ return 2246;
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 12) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1xx0xxxxx000011xxxxxxxxxx
-+ uaddlt. */
-+ return 2269;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1xx0xxxxx000111xxxxxxxxxx
-+ usublt. */
-+ return 2322;
-+ }
-+ }
-+ }
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 110001x1xx0xxxxx000xxxxxxxxxxxxx
-+ ld1sw. */
-+ return 1593;
-+ }
- }
- else
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- x10001x1xx1xxxxx000xxxxxxxxxxxxx
-- ld1sw. */
-- return 1540;
-+ if (((word >> 31) & 0x1) == 0)
-+ {
-+ if (((word >> 10) & 0x1) == 0)
-+ {
-+ if (((word >> 11) & 0x1) == 0)
-+ {
-+ if (((word >> 12) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1xx1xxxxx000000xxxxxxxxxx
-+ sqshrunb. */
-+ return 2227;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1xx1xxxxx000100xxxxxxxxxx
-+ shrnb. */
-+ return 2145;
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 12) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1xx1xxxxx000010xxxxxxxxxx
-+ sqrshrunb. */
-+ return 2219;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1xx1xxxxx000110xxxxxxxxxx
-+ rshrnb. */
-+ return 2127;
-+ }
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 11) & 0x1) == 0)
-+ {
-+ if (((word >> 12) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1xx1xxxxx000001xxxxxxxxxx
-+ sqshrunt. */
-+ return 2228;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1xx1xxxxx000101xxxxxxxxxx
-+ shrnt. */
-+ return 2146;
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 12) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1xx1xxxxx000011xxxxxxxxxx
-+ sqrshrunt. */
-+ return 2220;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1xx1xxxxx000111xxxxxxxxxx
-+ rshrnt. */
-+ return 2128;
-+ }
-+ }
-+ }
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 110001x1xx1xxxxx000xxxxxxxxxxxxx
-+ ld1sw. */
-+ return 1594;
-+ }
- }
- }
- else
- {
- if (((word >> 21) & 0x1) == 0)
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- x10001x1xx0xxxxx100xxxxxxxxxxxxx
-- ld1sw. */
-- return 1541;
-+ if (((word >> 31) & 0x1) == 0)
-+ {
-+ if (((word >> 10) & 0x1) == 0)
-+ {
-+ if (((word >> 11) & 0x1) == 0)
-+ {
-+ if (((word >> 12) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1xx0xxxxx100000xxxxxxxxxx
-+ saddlbt. */
-+ return 2138;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1xx0xxxxx100100xxxxxxxxxx
-+ eorbt. */
-+ return 2074;
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 12) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1xx0xxxxx100010xxxxxxxxxx
-+ ssublbt. */
-+ return 2245;
-+ }
-+ else
-+ {
-+ if (((word >> 22) & 0x1) == 0)
-+ {
-+ if (((word >> 23) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1000xxxxx100110xxxxxxxxxx
-+ smmla. */
-+ return 2401;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1100xxxxx100110xxxxxxxxxx
-+ usmmla. */
-+ return 2403;
-+ }
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1x10xxxxx100110xxxxxxxxxx
-+ ummla. */
-+ return 2402;
-+ }
-+ }
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 11) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1xx0xxxxx100x01xxxxxxxxxx
-+ eortb. */
-+ return 2075;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1xx0xxxxx100x11xxxxxxxxxx
-+ ssubltb. */
-+ return 2247;
-+ }
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 22) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 110001x1x00xxxxx100xxxxxxxxxxxxx
-+ ldnt1sw. */
-+ return 2106;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 110001x1x10xxxxx100xxxxxxxxxxxxx
-+ ld1sw. */
-+ return 1595;
-+ }
-+ }
- }
- else
- {
-- if (((word >> 22) & 0x1) == 0)
-+ if (((word >> 31) & 0x1) == 0)
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- x10001x1x01xxxxx100xxxxxxxxxxxxx
-- ld1sw. */
-- return 1544;
-+ if (((word >> 4) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1xx1xxxxx100xxxxxxxx0xxxx
-+ match. */
-+ return 2109;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1xx1xxxxx100xxxxxxxx1xxxx
-+ nmatch. */
-+ return 2121;
-+ }
- }
- else
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- x10001x1x11xxxxx100xxxxxxxxxxxxx
-- ld1sw. */
-- return 1542;
-+ if (((word >> 22) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 110001x1x01xxxxx100xxxxxxxxxxxxx
-+ ld1sw. */
-+ return 1598;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 110001x1x11xxxxx100xxxxxxxxxxxxx
-+ ld1sw. */
-+ return 1596;
-+ }
- }
- }
- }
-@@ -8471,32 +11166,186 @@ aarch64_opcode_lookup_1 (uint32_t word)
- {
- if (((word >> 21) & 0x1) == 0)
- {
-- if (((word >> 23) & 0x1) == 0)
-+ if (((word >> 31) & 0x1) == 0)
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- x10001x10x0xxxxx010xxxxxxxxxxxxx
-- ld1w. */
-- return 1549;
-+ if (((word >> 10) & 0x1) == 0)
-+ {
-+ if (((word >> 11) & 0x1) == 0)
-+ {
-+ if (((word >> 12) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1xx0xxxxx010000xxxxxxxxxx
-+ saddwb. */
-+ return 2140;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1xx0xxxxx010100xxxxxxxxxx
-+ ssubwb. */
-+ return 2248;
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 12) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1xx0xxxxx010010xxxxxxxxxx
-+ uaddwb. */
-+ return 2270;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1xx0xxxxx010110xxxxxxxxxx
-+ usubwb. */
-+ return 2323;
-+ }
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 11) & 0x1) == 0)
-+ {
-+ if (((word >> 12) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1xx0xxxxx010001xxxxxxxxxx
-+ saddwt. */
-+ return 2141;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1xx0xxxxx010101xxxxxxxxxx
-+ ssubwt. */
-+ return 2249;
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 12) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1xx0xxxxx010011xxxxxxxxxx
-+ uaddwt. */
-+ return 2271;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1xx0xxxxx010111xxxxxxxxxx
-+ usubwt. */
-+ return 2324;
-+ }
-+ }
-+ }
- }
- else
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- x10001x11x0xxxxx010xxxxxxxxxxxxx
-- ld1d. */
-- return 1471;
-+ if (((word >> 23) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 110001x10x0xxxxx010xxxxxxxxxxxxx
-+ ld1w. */
-+ return 1603;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 110001x11x0xxxxx010xxxxxxxxxxxxx
-+ ld1d. */
-+ return 1525;
-+ }
- }
- }
- else
- {
- if (((word >> 23) & 0x1) == 0)
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- x10001x10x1xxxxx010xxxxxxxxxxxxx
-- ld1w. */
-- return 1550;
-+ if (((word >> 31) & 0x1) == 0)
-+ {
-+ if (((word >> 10) & 0x1) == 0)
-+ {
-+ if (((word >> 11) & 0x1) == 0)
-+ {
-+ if (((word >> 12) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x10x1xxxxx010000xxxxxxxxxx
-+ sqxtnb. */
-+ return 2231;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x10x1xxxxx010100xxxxxxxxxx
-+ sqxtunb. */
-+ return 2233;
-+ }
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x10x1xxxxx010x10xxxxxxxxxx
-+ uqxtnb. */
-+ return 2308;
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 11) & 0x1) == 0)
-+ {
-+ if (((word >> 12) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x10x1xxxxx010001xxxxxxxxxx
-+ sqxtnt. */
-+ return 2232;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x10x1xxxxx010101xxxxxxxxxx
-+ sqxtunt. */
-+ return 2234;
-+ }
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x10x1xxxxx010x11xxxxxxxxxx
-+ uqxtnt. */
-+ return 2309;
-+ }
-+ }
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 110001x10x1xxxxx010xxxxxxxxxxxxx
-+ ld1w. */
-+ return 1604;
-+ }
- }
- else
- {
-@@ -8504,7 +11353,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x10001x11x1xxxxx010xxxxxxxxxxxxx
- ld1d. */
-- return 1472;
-+ return 1526;
- }
- }
- }
-@@ -8512,61 +11361,204 @@ aarch64_opcode_lookup_1 (uint32_t word)
- {
- if (((word >> 21) & 0x1) == 0)
- {
-- if (((word >> 23) & 0x1) == 0)
-+ if (((word >> 31) & 0x1) == 0)
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- x10001x10x0xxxxx110xxxxxxxxxxxxx
-- ld1w. */
-- return 1551;
-+ if (((word >> 11) & 0x1) == 0)
-+ {
-+ if (((word >> 10) & 0x1) == 0)
-+ {
-+ if (((word >> 12) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1xx0xxxxx110000xxxxxxxxxx
-+ sabalb. */
-+ return 2132;
-+ }
-+ else
-+ {
-+ if (((word >> 23) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x10x0xxxxx110100xxxxxxxxxx
-+ adclb. */
-+ return 2057;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x11x0xxxxx110100xxxxxxxxxx
-+ sbclb. */
-+ return 2142;
-+ }
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 12) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1xx0xxxxx110001xxxxxxxxxx
-+ sabalt. */
-+ return 2133;
-+ }
-+ else
-+ {
-+ if (((word >> 23) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x10x0xxxxx110101xxxxxxxxxx
-+ adclt. */
-+ return 2058;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x11x0xxxxx110101xxxxxxxxxx
-+ sbclt. */
-+ return 2143;
-+ }
-+ }
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 12) & 0x1) == 0)
-+ {
-+ if (((word >> 10) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1xx0xxxxx110010xxxxxxxxxx
-+ uabalb. */
-+ return 2263;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1xx0xxxxx110011xxxxxxxxxx
-+ uabalt. */
-+ return 2264;
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 16) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1xx0xxxx011011xxxxxxxxxxx
-+ cadd. */
-+ return 2066;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1xx0xxxx111011xxxxxxxxxxx
-+ sqcadd. */
-+ return 2174;
-+ }
-+ }
-+ }
- }
- else
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- x10001x11x0xxxxx110xxxxxxxxxxxxx
-- ld1d. */
-- return 1473;
-+ if (((word >> 22) & 0x1) == 0)
-+ {
-+ if (((word >> 23) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 110001x1000xxxxx110xxxxxxxxxxxxx
-+ ldnt1w. */
-+ return 2108;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 110001x1100xxxxx110xxxxxxxxxxxxx
-+ ldnt1d. */
-+ return 2101;
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 23) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 110001x1010xxxxx110xxxxxxxxxxxxx
-+ ld1w. */
-+ return 1605;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 110001x1110xxxxx110xxxxxxxxxxxxx
-+ ld1d. */
-+ return 1527;
-+ }
-+ }
- }
- }
- else
- {
-- if (((word >> 22) & 0x1) == 0)
-+ if (((word >> 23) & 0x1) == 0)
- {
-- if (((word >> 23) & 0x1) == 0)
-+ if (((word >> 22) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x10001x1001xxxxx110xxxxxxxxxxxxx
- ld1w. */
-- return 1556;
-+ return 1610;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
-- x10001x1101xxxxx110xxxxxxxxxxxxx
-- ld1d. */
-- return 1476;
-+ x10001x1011xxxxx110xxxxxxxxxxxxx
-+ ld1w. */
-+ return 1606;
- }
- }
- else
- {
-- if (((word >> 23) & 0x1) == 0)
-+ if (((word >> 31) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
-- x10001x1011xxxxx110xxxxxxxxxxxxx
-- ld1w. */
-- return 1552;
-+ 010001x11x1xxxxx110xxxxxxxxxxxxx
-+ histcnt. */
-+ return 2097;
- }
- else
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- x10001x1111xxxxx110xxxxxxxxxxxxx
-- ld1d. */
-- return 1474;
-+ if (((word >> 22) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 110001x1101xxxxx110xxxxxxxxxxxxx
-+ ld1d. */
-+ return 1530;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 110001x1111xxxxx110xxxxxxxxxxxxx
-+ ld1d. */
-+ return 1528;
-+ }
- }
- }
- }
-@@ -8581,116 +11573,490 @@ aarch64_opcode_lookup_1 (uint32_t word)
- {
- if (((word >> 21) & 0x1) == 0)
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- x10001x1xx0xxxxx001xxxxxxxxxxxxx
-- ldff1sw. */
-- return 1626;
-- }
-- else
-- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- x10001x1xx1xxxxx001xxxxxxxxxxxxx
-- ldff1sw. */
-- return 1627;
-- }
-- }
-- else
-- {
-- if (((word >> 21) & 0x1) == 0)
-- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- x10001x1xx0xxxxx101xxxxxxxxxxxxx
-- ldff1sw. */
-- return 1628;
-- }
-- else
-- {
-- if (((word >> 22) & 0x1) == 0)
-+ if (((word >> 31) & 0x1) == 0)
-+ {
-+ if (((word >> 10) & 0x1) == 0)
-+ {
-+ if (((word >> 11) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1xx0xxxxx001x00xxxxxxxxxx
-+ sabdlb. */
-+ return 2134;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1xx0xxxxx001x10xxxxxxxxxx
-+ uabdlb. */
-+ return 2265;
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 11) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1xx0xxxxx001x01xxxxxxxxxx
-+ sabdlt. */
-+ return 2135;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1xx0xxxxx001x11xxxxxxxxxx
-+ uabdlt. */
-+ return 2266;
-+ }
-+ }
-+ }
-+ else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
-- x10001x1x01xxxxx101xxxxxxxxxxxxx
-+ 110001x1xx0xxxxx001xxxxxxxxxxxxx
- ldff1sw. */
-- return 1630;
-+ return 1694;
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 31) & 0x1) == 0)
-+ {
-+ if (((word >> 10) & 0x1) == 0)
-+ {
-+ if (((word >> 11) & 0x1) == 0)
-+ {
-+ if (((word >> 12) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1xx1xxxxx001000xxxxxxxxxx
-+ sqshrnb. */
-+ return 2225;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1xx1xxxxx001100xxxxxxxxxx
-+ uqshrnb. */
-+ return 2304;
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 12) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1xx1xxxxx001010xxxxxxxxxx
-+ sqrshrnb. */
-+ return 2217;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1xx1xxxxx001110xxxxxxxxxx
-+ uqrshrnb. */
-+ return 2299;
-+ }
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 11) & 0x1) == 0)
-+ {
-+ if (((word >> 12) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1xx1xxxxx001001xxxxxxxxxx
-+ sqshrnt. */
-+ return 2226;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1xx1xxxxx001101xxxxxxxxxx
-+ uqshrnt. */
-+ return 2305;
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 12) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1xx1xxxxx001011xxxxxxxxxx
-+ sqrshrnt. */
-+ return 2218;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1xx1xxxxx001111xxxxxxxxxx
-+ uqrshrnt. */
-+ return 2300;
-+ }
-+ }
-+ }
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
-- x10001x1x11xxxxx101xxxxxxxxxxxxx
-+ 110001x1xx1xxxxx001xxxxxxxxxxxxx
- ldff1sw. */
-- return 1629;
-+ return 1695;
- }
- }
- }
-- }
-- else
-- {
-- if (((word >> 15) & 0x1) == 0)
-+ else
- {
- if (((word >> 21) & 0x1) == 0)
- {
-- if (((word >> 23) & 0x1) == 0)
-+ if (((word >> 31) & 0x1) == 0)
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- x10001x10x0xxxxx011xxxxxxxxxxxxx
-- ldff1w. */
-- return 1635;
-+ if (((word >> 10) & 0x1) == 0)
-+ {
-+ if (((word >> 11) & 0x1) == 0)
-+ {
-+ if (((word >> 12) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1xx0xxxxx101000xxxxxxxxxx
-+ sshllb. */
-+ return 2241;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1xx0xxxxx101100xxxxxxxxxx
-+ bext. */
-+ return 2346;
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 12) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1xx0xxxxx101010xxxxxxxxxx
-+ ushllb. */
-+ return 2317;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1xx0xxxxx101110xxxxxxxxxx
-+ bgrp. */
-+ return 2347;
-+ }
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 11) & 0x1) == 0)
-+ {
-+ if (((word >> 12) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1xx0xxxxx101001xxxxxxxxxx
-+ sshllt. */
-+ return 2242;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1xx0xxxxx101101xxxxxxxxxx
-+ bdep. */
-+ return 2345;
-+ }
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1xx0xxxxx101x11xxxxxxxxxx
-+ ushllt. */
-+ return 2318;
-+ }
-+ }
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
-- x10001x11x0xxxxx011xxxxxxxxxxxxx
-- ldff1d. */
-- return 1591;
-+ 110001x1xx0xxxxx101xxxxxxxxxxxxx
-+ ldff1sw. */
-+ return 1696;
- }
- }
- else
- {
-- if (((word >> 23) & 0x1) == 0)
-+ if (((word >> 22) & 0x1) == 0)
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- x10001x10x1xxxxx011xxxxxxxxxxxxx
-- ldff1w. */
-- return 1636;
-+ if (((word >> 31) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1x01xxxxx101xxxxxxxxxxxxx
-+ histseg. */
-+ return 2098;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 110001x1x01xxxxx101xxxxxxxxxxxxx
-+ ldff1sw. */
-+ return 1698;
-+ }
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
-- x10001x11x1xxxxx011xxxxxxxxxxxxx
-- ldff1d. */
-- return 1592;
-+ x10001x1x11xxxxx101xxxxxxxxxxxxx
-+ ldff1sw. */
-+ return 1697;
- }
- }
- }
-- else
-+ }
-+ else
-+ {
-+ if (((word >> 15) & 0x1) == 0)
- {
- if (((word >> 21) & 0x1) == 0)
- {
-- if (((word >> 22) & 0x1) == 0)
-+ if (((word >> 31) & 0x1) == 0)
-+ {
-+ if (((word >> 10) & 0x1) == 0)
-+ {
-+ if (((word >> 11) & 0x1) == 0)
-+ {
-+ if (((word >> 12) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1xx0xxxxx011000xxxxxxxxxx
-+ sqdmullb. */
-+ return 2195;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1xx0xxxxx011100xxxxxxxxxx
-+ smullb. */
-+ return 2167;
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 12) & 0x1) == 0)
-+ {
-+ if (((word >> 22) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1x00xxxxx011010xxxxxxxxxx
-+ pmullb. */
-+ return 2342;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1x10xxxxx011010xxxxxxxxxx
-+ pmullb. */
-+ return 2123;
-+ }
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1xx0xxxxx011110xxxxxxxxxx
-+ umullb. */
-+ return 2292;
-+ }
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 11) & 0x1) == 0)
-+ {
-+ if (((word >> 12) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1xx0xxxxx011001xxxxxxxxxx
-+ sqdmullt. */
-+ return 2198;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1xx0xxxxx011101xxxxxxxxxx
-+ smullt. */
-+ return 2170;
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 12) & 0x1) == 0)
-+ {
-+ if (((word >> 22) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1x00xxxxx011011xxxxxxxxxx
-+ pmullt. */
-+ return 2343;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1x10xxxxx011011xxxxxxxxxx
-+ pmullt. */
-+ return 2124;
-+ }
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1xx0xxxxx011111xxxxxxxxxx
-+ umullt. */
-+ return 2295;
-+ }
-+ }
-+ }
-+ }
-+ else
- {
- if (((word >> 23) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
-- x10001x1000xxxxx111xxxxxxxxxxxxx
-- prfw. */
-- return 1731;
-+ 110001x10x0xxxxx011xxxxxxxxxxxxx
-+ ldff1w. */
-+ return 1705;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
-- x10001x1100xxxxx111xxxxxxxxxxxxx
-- prfd. */
-- return 1717;
-+ 110001x11x0xxxxx011xxxxxxxxxxxxx
-+ ldff1d. */
-+ return 1650;
-+ }
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 31) & 0x1) == 0)
-+ {
-+ if (((word >> 10) & 0x1) == 0)
-+ {
-+ if (((word >> 11) & 0x1) == 0)
-+ {
-+ if (((word >> 12) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1xx1xxxxx011000xxxxxxxxxx
-+ addhnb. */
-+ return 2059;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1xx1xxxxx011100xxxxxxxxxx
-+ subhnb. */
-+ return 2257;
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 12) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1xx1xxxxx011010xxxxxxxxxx
-+ raddhnb. */
-+ return 2125;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1xx1xxxxx011110xxxxxxxxxx
-+ rsubhnb. */
-+ return 2129;
-+ }
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 11) & 0x1) == 0)
-+ {
-+ if (((word >> 12) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1xx1xxxxx011001xxxxxxxxxx
-+ addhnt. */
-+ return 2060;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1xx1xxxxx011101xxxxxxxxxx
-+ subhnt. */
-+ return 2258;
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 12) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1xx1xxxxx011011xxxxxxxxxx
-+ raddhnt. */
-+ return 2126;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1xx1xxxxx011111xxxxxxxxxx
-+ rsubhnt. */
-+ return 2130;
-+ }
-+ }
- }
- }
- else
-@@ -8699,17 +12065,149 @@ aarch64_opcode_lookup_1 (uint32_t word)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
-- x10001x1010xxxxx111xxxxxxxxxxxxx
-+ 110001x10x1xxxxx011xxxxxxxxxxxxx
- ldff1w. */
-- return 1637;
-+ return 1706;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
-- x10001x1110xxxxx111xxxxxxxxxxxxx
-+ 110001x11x1xxxxx011xxxxxxxxxxxxx
- ldff1d. */
-- return 1593;
-+ return 1651;
-+ }
-+ }
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 21) & 0x1) == 0)
-+ {
-+ if (((word >> 31) & 0x1) == 0)
-+ {
-+ if (((word >> 10) & 0x1) == 0)
-+ {
-+ if (((word >> 11) & 0x1) == 0)
-+ {
-+ if (((word >> 12) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1xx0xxxxx111000xxxxxxxxxx
-+ ssra. */
-+ return 2243;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1xx0xxxxx111100xxxxxxxxxx
-+ sri. */
-+ return 2236;
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 12) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1xx0xxxxx111010xxxxxxxxxx
-+ srsra. */
-+ return 2240;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1xx0xxxxx111110xxxxxxxxxx
-+ saba. */
-+ return 2131;
-+ }
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 11) & 0x1) == 0)
-+ {
-+ if (((word >> 12) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1xx0xxxxx111001xxxxxxxxxx
-+ usra. */
-+ return 2320;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1xx0xxxxx111101xxxxxxxxxx
-+ sli. */
-+ return 2149;
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 12) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1xx0xxxxx111011xxxxxxxxxx
-+ ursra. */
-+ return 2316;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1xx0xxxxx111111xxxxxxxxxx
-+ uaba. */
-+ return 2262;
-+ }
-+ }
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 22) & 0x1) == 0)
-+ {
-+ if (((word >> 23) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 110001x1000xxxxx111xxxxxxxxxxxxx
-+ prfw. */
-+ return 1801;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 110001x1100xxxxx111xxxxxxxxxxxxx
-+ prfd. */
-+ return 1787;
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 23) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 110001x1010xxxxx111xxxxxxxxxxxxx
-+ ldff1w. */
-+ return 1707;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 110001x1110xxxxx111xxxxxxxxxxxxx
-+ ldff1d. */
-+ return 1652;
-+ }
- }
- }
- }
-@@ -8719,11 +12217,88 @@ aarch64_opcode_lookup_1 (uint32_t word)
- {
- if (((word >> 23) & 0x1) == 0)
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- x10001x1001xxxxx111xxxxxxxxxxxxx
-- ldff1w. */
-- return 1640;
-+ if (((word >> 31) & 0x1) == 0)
-+ {
-+ if (((word >> 10) & 0x1) == 0)
-+ {
-+ if (((word >> 12) & 0x1) == 0)
-+ {
-+ if (((word >> 16) & 0x1) == 0)
-+ {
-+ if (((word >> 17) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1001xxx001110x0xxxxxxxxxx
-+ aesmc. */
-+ return 2341;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1001xxx101110x0xxxxxxxxxx
-+ aese. */
-+ return 2339;
-+ }
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1001xxxx11110x0xxxxxxxxxx
-+ sm4e. */
-+ return 2336;
-+ }
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1001xxxxx1111x0xxxxxxxxxx
-+ sm4ekey. */
-+ return 2337;
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 12) & 0x1) == 0)
-+ {
-+ if (((word >> 17) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1001xxx0x1110x1xxxxxxxxxx
-+ aesimc. */
-+ return 2340;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1001xxx1x1110x1xxxxxxxxxx
-+ aesd. */
-+ return 2338;
-+ }
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010001x1001xxxxx1111x1xxxxxxxxxx
-+ rax1. */
-+ return 2344;
-+ }
-+ }
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 110001x1001xxxxx111xxxxxxxxxxxxx
-+ ldff1w. */
-+ return 1710;
-+ }
- }
- else
- {
-@@ -8731,7 +12306,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x10001x1101xxxxx111xxxxxxxxxxxxx
- ldff1d. */
-- return 1595;
-+ return 1654;
- }
- }
- else
-@@ -8742,7 +12317,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x10001x1011xxxxx111xxxxxxxxxxxxx
- ldff1w. */
-- return 1638;
-+ return 1708;
- }
- else
- {
-@@ -8750,7 +12325,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x10001x1111xxxxx111xxxxxxxxxxxxx
- ldff1d. */
-- return 1594;
-+ return 1653;
- }
- }
- }
-@@ -8779,7 +12354,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001001x1xx0xxxxx000xxxxxxxx0xxxx
- cmpge. */
-- return 1279;
-+ return 1333;
- }
- else
- {
-@@ -8787,7 +12362,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001001x1xx0xxxxx000xxxxxxxx1xxxx
- cmpgt. */
-- return 1282;
-+ return 1336;
- }
- }
- else
-@@ -8798,7 +12373,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 101001x10x0xxxxx000xxxxxxxxxxxxx
- ld1rqw. */
-- return 1506;
-+ return 1560;
- }
- else
- {
-@@ -8806,92 +12381,202 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 101001x11x0xxxxx000xxxxxxxxxxxxx
- ld1rqd. */
-- return 1502;
-+ return 1556;
- }
- }
- }
- else
- {
-- if (((word >> 4) & 0x1) == 0)
-+ if (((word >> 31) & 0x1) == 0)
- {
-- if (((word >> 11) & 0x1) == 0)
-+ if (((word >> 4) & 0x1) == 0)
- {
-- if (((word >> 12) & 0x1) == 0)
-+ if (((word >> 10) & 0x1) == 0)
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- x01001x1xx1xxxxx00000xxxxxx0xxxx
-- whilelt. */
-- return 1967;
-+ if (((word >> 11) & 0x1) == 0)
-+ {
-+ if (((word >> 12) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 001001x1xx1xxxxx000000xxxxx0xxxx
-+ whilege. */
-+ return 2325;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 001001x1xx1xxxxx000100xxxxx0xxxx
-+ whilege. */
-+ return 2326;
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 12) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 001001x1xx1xxxxx000010xxxxx0xxxx
-+ whilehs. */
-+ return 2331;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 001001x1xx1xxxxx000110xxxxx0xxxx
-+ whilehs. */
-+ return 2332;
-+ }
-+ }
- }
- else
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- x01001x1xx1xxxxx00010xxxxxx0xxxx
-- whilelt. */
-- return 1968;
-+ if (((word >> 11) & 0x1) == 0)
-+ {
-+ if (((word >> 12) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 001001x1xx1xxxxx000001xxxxx0xxxx
-+ whilelt. */
-+ return 2037;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 001001x1xx1xxxxx000101xxxxx0xxxx
-+ whilelt. */
-+ return 2038;
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 12) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 001001x1xx1xxxxx000011xxxxx0xxxx
-+ whilelo. */
-+ return 2033;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 001001x1xx1xxxxx000111xxxxx0xxxx
-+ whilelo. */
-+ return 2034;
-+ }
-+ }
- }
- }
- else
- {
-- if (((word >> 12) & 0x1) == 0)
-+ if (((word >> 10) & 0x1) == 0)
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- x01001x1xx1xxxxx00001xxxxxx0xxxx
-- whilelo. */
-- return 1963;
-+ if (((word >> 11) & 0x1) == 0)
-+ {
-+ if (((word >> 12) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 001001x1xx1xxxxx000000xxxxx1xxxx
-+ whilegt. */
-+ return 2327;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 001001x1xx1xxxxx000100xxxxx1xxxx
-+ whilegt. */
-+ return 2328;
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 12) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 001001x1xx1xxxxx000010xxxxx1xxxx
-+ whilehi. */
-+ return 2329;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 001001x1xx1xxxxx000110xxxxx1xxxx
-+ whilehi. */
-+ return 2330;
-+ }
-+ }
- }
- else
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- x01001x1xx1xxxxx00011xxxxxx0xxxx
-- whilelo. */
-- return 1964;
-+ if (((word >> 11) & 0x1) == 0)
-+ {
-+ if (((word >> 12) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 001001x1xx1xxxxx000001xxxxx1xxxx
-+ whilele. */
-+ return 2031;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 001001x1xx1xxxxx000101xxxxx1xxxx
-+ whilele. */
-+ return 2032;
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 12) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 001001x1xx1xxxxx000011xxxxx1xxxx
-+ whilels. */
-+ return 2035;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 001001x1xx1xxxxx000111xxxxx1xxxx
-+ whilels. */
-+ return 2036;
-+ }
-+ }
- }
- }
- }
- else
- {
-- if (((word >> 11) & 0x1) == 0)
-+ if (((word >> 23) & 0x1) == 0)
- {
-- if (((word >> 12) & 0x1) == 0)
-- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- x01001x1xx1xxxxx00000xxxxxx1xxxx
-- whilele. */
-- return 1961;
-- }
-- else
-- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- x01001x1xx1xxxxx00010xxxxxx1xxxx
-- whilele. */
-- return 1962;
-- }
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 101001x10x1xxxxx000xxxxxxxxxxxxx
-+ ld1row. */
-+ return 2411;
- }
- else
- {
-- if (((word >> 12) & 0x1) == 0)
-- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- x01001x1xx1xxxxx00001xxxxxx1xxxx
-- whilels. */
-- return 1965;
-- }
-- else
-- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- x01001x1xx1xxxxx00011xxxxxx1xxxx
-- whilels. */
-- return 1966;
-- }
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 101001x11x1xxxxx000xxxxxxxxxxxxx
-+ ld1rod. */
-+ return 2412;
- }
- }
- }
-@@ -8910,7 +12595,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 011001x1xx0xxxxx000x00xxxxxxxxxx
- fadd. */
-- return 1337;
-+ return 1391;
- }
- else
- {
-@@ -8920,7 +12605,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 011001x1xx0xxxxx000010xxxxxxxxxx
- fmul. */
-- return 1404;
-+ return 1458;
- }
- else
- {
-@@ -8928,7 +12613,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 011001x1xx0xxxxx000110xxxxxxxxxx
- frecps. */
-- return 1417;
-+ return 1471;
- }
- }
- }
-@@ -8940,7 +12625,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 011001x1xx0xxxxx000x01xxxxxxxxxx
- fsub. */
-- return 1430;
-+ return 1484;
- }
- else
- {
-@@ -8950,7 +12635,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 011001x1xx0xxxxx000011xxxxxxxxxx
- ftsmul. */
-- return 1436;
-+ return 1490;
- }
- else
- {
-@@ -8958,7 +12643,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 011001x1xx0xxxxx000111xxxxxxxxxx
- frsqrts. */
-- return 1427;
-+ return 1481;
- }
- }
- }
-@@ -8969,7 +12654,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 011001x1xx1xxxxx000xxxxxxxxxxxxx
- fmla. */
-- return 1395;
-+ return 1449;
- }
- }
- else
-@@ -8978,7 +12663,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 111001x1xxxxxxxx000xxxxxxxxxxxxx
- str. */
-- return 1882;
-+ return 1952;
- }
- }
- }
-@@ -8996,7 +12681,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001001x1xx0xxxxx001xxxxxxxx0xxxx
- cmplt. */
-- return 1296;
-+ return 1350;
- }
- else
- {
-@@ -9004,7 +12689,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001001x1xx0xxxxx001xxxxxxxx1xxxx
- cmple. */
-- return 1290;
-+ return 1344;
- }
- }
- else
-@@ -9015,7 +12700,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 101001x10x0xxxxx001xxxxxxxxxxxxx
- ld1rqw. */
-- return 1505;
-+ return 1559;
- }
- else
- {
-@@ -9023,159 +12708,192 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 101001x11x0xxxxx001xxxxxxxxxxxxx
- ld1rqd. */
-- return 1501;
-+ return 1555;
- }
- }
- }
- else
- {
-- if (((word >> 16) & 0x1) == 0)
-+ if (((word >> 31) & 0x1) == 0)
- {
-- if (((word >> 17) & 0x1) == 0)
-+ if (((word >> 16) & 0x1) == 0)
- {
-- if (((word >> 18) & 0x1) == 0)
-+ if (((word >> 17) & 0x1) == 0)
- {
-- if (((word >> 19) & 0x1) == 0)
-+ if (((word >> 18) & 0x1) == 0)
- {
-- if (((word >> 20) & 0x1) == 0)
-- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- x11001x1xx000000001xxxxxxxxxxxxx
-- faddv. */
-- return 1341;
-- }
-- else
-+ if (((word >> 19) & 0x1) == 0)
- {
-- if (((word >> 4) & 0x1) == 0)
-+ if (((word >> 20) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
-- x11001x1xx010000001xxxxxxxx0xxxx
-- fcmge. */
-- return 1348;
-+ 011001x1xx000000001xxxxxxxxxxxxx
-+ faddv. */
-+ return 1395;
- }
- else
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- x11001x1xx010000001xxxxxxxx1xxxx
-- fcmgt. */
-- return 1350;
-+ if (((word >> 4) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 011001x1xx010000001xxxxxxxx0xxxx
-+ fcmge. */
-+ return 1402;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 011001x1xx010000001xxxxxxxx1xxxx
-+ fcmgt. */
-+ return 1404;
-+ }
- }
- }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 011001x1xx0x1000001xxxxxxxxxxxxx
-+ fadda. */
-+ return 1394;
-+ }
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
-- x11001x1xx0x1000001xxxxxxxxxxxxx
-- fadda. */
-- return 1340;
-+ 011001x1xx0xx100001xxxxxxxxxxxxx
-+ fmaxnmv. */
-+ return 1441;
- }
- }
- else
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- x11001x1xx0xx100001xxxxxxxxxxxxx
-- fmaxnmv. */
-- return 1387;
-- }
-- }
-- else
-- {
-- if (((word >> 18) & 0x1) == 0)
-- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- x11001x1xx0xx010001xxxxxxxxxxxxx
-- fcmeq. */
-- return 1346;
-- }
-- else
-- {
-- if (((word >> 19) & 0x1) == 0)
-+ if (((word >> 18) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
-- x11001x1xx0x0110001xxxxxxxxxxxxx
-- fmaxv. */
-- return 1388;
-+ 011001x1xx0xx010001xxxxxxxxxxxxx
-+ fcmeq. */
-+ return 1400;
- }
- else
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- x11001x1xx0x1110001xxxxxxxxxxxxx
-- frecpe. */
-- return 1416;
-+ if (((word >> 19) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 011001x1xx0x0110001xxxxxxxxxxxxx
-+ fmaxv. */
-+ return 1442;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 011001x1xx0x1110001xxxxxxxxxxxxx
-+ frecpe. */
-+ return 1470;
-+ }
- }
- }
- }
-- }
-- else
-- {
-- if (((word >> 17) & 0x1) == 0)
-+ else
- {
-- if (((word >> 18) & 0x1) == 0)
-+ if (((word >> 17) & 0x1) == 0)
- {
-- if (((word >> 4) & 0x1) == 0)
-+ if (((word >> 18) & 0x1) == 0)
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- x11001x1xx0xx001001xxxxxxxx0xxxx
-- fcmlt. */
-- return 1353;
-+ if (((word >> 4) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 011001x1xx0xx001001xxxxxxxx0xxxx
-+ fcmlt. */
-+ return 1407;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 011001x1xx0xx001001xxxxxxxx1xxxx
-+ fcmle. */
-+ return 1406;
-+ }
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
-- x11001x1xx0xx001001xxxxxxxx1xxxx
-- fcmle. */
-- return 1352;
-+ 011001x1xx0xx101001xxxxxxxxxxxxx
-+ fminnmv. */
-+ return 1447;
- }
- }
- else
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- x11001x1xx0xx101001xxxxxxxxxxxxx
-- fminnmv. */
-- return 1393;
-+ if (((word >> 18) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 011001x1xx0xx011001xxxxxxxxxxxxx
-+ fcmne. */
-+ return 1408;
-+ }
-+ else
-+ {
-+ if (((word >> 19) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 011001x1xx0x0111001xxxxxxxxxxxxx
-+ fminv. */
-+ return 1448;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 011001x1xx0x1111001xxxxxxxxxxxxx
-+ frsqrte. */
-+ return 1480;
-+ }
-+ }
- }
- }
-- else
-+ }
-+ else
-+ {
-+ if (((word >> 22) & 0x1) == 0)
- {
-- if (((word >> 18) & 0x1) == 0)
-+ if (((word >> 23) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
-- x11001x1xx0xx011001xxxxxxxxxxxxx
-- fcmne. */
-- return 1354;
-+ 111001x1000xxxxx001xxxxxxxxxxxxx
-+ stnt1w. */
-+ return 2256;
- }
- else
- {
-- if (((word >> 19) & 0x1) == 0)
-- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- x11001x1xx0x0111001xxxxxxxxxxxxx
-- fminv. */
-- return 1394;
-- }
-- else
-- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- x11001x1xx0x1111001xxxxxxxxxxxxx
-- frsqrte. */
-- return 1426;
-- }
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 111001x1100xxxxx001xxxxxxxxxxxxx
-+ stnt1d. */
-+ return 2252;
- }
- }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 111001x1x10xxxxx001xxxxxxxxxxxxx
-+ stnt1w. */
-+ return 2255;
-+ }
- }
- }
- }
-@@ -9183,21 +12901,65 @@ aarch64_opcode_lookup_1 (uint32_t word)
- {
- if (((word >> 30) & 0x1) == 0)
- {
-- if (((word >> 4) & 0x1) == 0)
-+ if (((word >> 31) & 0x1) == 0)
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- x01001x1xx1xxxxx001xxxxxxxx0xxxx
-- ctermeq. */
-- return 1311;
-+ if (((word >> 4) & 0x1) == 0)
-+ {
-+ if (((word >> 12) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 001001x1xx1xxxxx0010xxxxxxx0xxxx
-+ ctermeq. */
-+ return 1365;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 001001x1xx1xxxxx0011xxxxxxx0xxxx
-+ whilewr. */
-+ return 2334;
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 12) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 001001x1xx1xxxxx0010xxxxxxx1xxxx
-+ ctermne. */
-+ return 1366;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 001001x1xx1xxxxx0011xxxxxxx1xxxx
-+ whilerw. */
-+ return 2333;
-+ }
-+ }
- }
- else
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- x01001x1xx1xxxxx001xxxxxxxx1xxxx
-- ctermne. */
-- return 1312;
-+ if (((word >> 23) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 101001x10x1xxxxx001xxxxxxxxxxxxx
-+ ld1row. */
-+ return 2415;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 101001x11x1xxxxx001xxxxxxxxxxxxx
-+ ld1rod. */
-+ return 2416;
-+ }
- }
- }
- else
-@@ -9206,7 +12968,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x11001x1xx1xxxxx001xxxxxxxxxxxxx
- fmls. */
-- return 1399;
-+ return 1453;
- }
- }
- }
-@@ -9233,7 +12995,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001001x10000xxxx01xxxx0xxxx0xxxx
- and. */
-- return 1242;
-+ return 1296;
- }
- else
- {
-@@ -9241,7 +13003,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001001x10000xxxx01xxxx0xxxx1xxxx
- bic. */
-- return 1254;
-+ return 1308;
- }
- }
- else
-@@ -9252,7 +13014,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001001x100010xxx01xxxx0xxxxxxxxx
- brka. */
-- return 1256;
-+ return 1310;
- }
- else
- {
-@@ -9260,7 +13022,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001001x100011xxx01xxxx0xxxxxxxxx
- brkn. */
-- return 1260;
-+ return 1314;
- }
- }
- }
-@@ -9272,7 +13034,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001001x1000xxxxx01xxxx1xxxx0xxxx
- eor. */
-- return 1329;
-+ return 1383;
- }
- else
- {
-@@ -9280,7 +13042,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001001x1000xxxxx01xxxx1xxxx1xxxx
- sel. */
-- return 1762;
-+ return 1832;
- }
- }
- }
-@@ -9292,7 +13054,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 101001x1000xxxxx010xxxxxxxxxxxxx
- ld1sh. */
-- return 1528;
-+ return 1582;
- }
- else
- {
-@@ -9300,7 +13062,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 101001x1000xxxxx011xxxxxxxxxxxxx
- ldff1sh. */
-- return 1617;
-+ return 1682;
- }
- }
- }
-@@ -9318,7 +13080,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001001x11000xxxx01xxxx0xxxx0xxxx
- orr. */
-- return 1698;
-+ return 1768;
- }
- else
- {
-@@ -9326,7 +13088,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001001x11000xxxx01xxxx0xxxx1xxxx
- orn. */
-- return 1693;
-+ return 1763;
- }
- }
- else
-@@ -9335,7 +13097,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001001x11001xxxx01xxxx0xxxxxxxxx
- brkb. */
-- return 1258;
-+ return 1312;
- }
- }
- else
-@@ -9346,7 +13108,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001001x1100xxxxx01xxxx1xxxx0xxxx
- nor. */
-- return 1690;
-+ return 1760;
- }
- else
- {
-@@ -9354,7 +13116,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001001x1100xxxxx01xxxx1xxxx1xxxx
- nand. */
-- return 1687;
-+ return 1757;
- }
- }
- }
-@@ -9366,7 +13128,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 101001x1100xxxxx010xxxxxxxxxxxxx
- ld1sb. */
-- return 1516;
-+ return 1570;
- }
- else
- {
-@@ -9374,7 +13136,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 101001x1100xxxxx011xxxxxxxxxxxxx
- ldff1sb. */
-- return 1608;
-+ return 1670;
- }
- }
- }
-@@ -9395,7 +13157,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001001x10100xxxx01xxxx0xxxx0xxxx
- ands. */
-- return 1243;
-+ return 1297;
- }
- else
- {
-@@ -9405,7 +13167,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001001x101010xxx01xxxx0xxxx0xxxx
- brkas. */
-- return 1257;
-+ return 1311;
- }
- else
- {
-@@ -9413,7 +13175,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001001x101011xxx01xxxx0xxxx0xxxx
- brkns. */
-- return 1261;
-+ return 1315;
- }
- }
- }
-@@ -9423,7 +13185,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001001x1010xxxxx01xxxx1xxxx0xxxx
- eors. */
-- return 1330;
-+ return 1384;
- }
- }
- else
-@@ -9432,7 +13194,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001001x1010xxxxx01xxxxxxxxx1xxxx
- bics. */
-- return 1255;
-+ return 1309;
- }
- }
- else
-@@ -9443,7 +13205,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 101001x1010xxxxx010xxxxxxxxxxxxx
- ld1w. */
-- return 1547;
-+ return 1601;
- }
- else
- {
-@@ -9451,7 +13213,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 101001x1010xxxxx011xxxxxxxxxxxxx
- ldff1w. */
-- return 1633;
-+ return 1701;
- }
- }
- }
-@@ -9469,7 +13231,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001001x11100xxxx01xxxx0xxxx0xxxx
- orrs. */
-- return 1699;
-+ return 1769;
- }
- else
- {
-@@ -9477,7 +13239,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001001x11101xxxx01xxxx0xxxx0xxxx
- brkbs. */
-- return 1259;
-+ return 1313;
- }
- }
- else
-@@ -9486,7 +13248,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001001x1110xxxxx01xxxx1xxxx0xxxx
- nors. */
-- return 1691;
-+ return 1761;
- }
- }
- else
-@@ -9497,7 +13259,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001001x1110xxxxx01xxxx0xxxx1xxxx
- orns. */
-- return 1694;
-+ return 1764;
- }
- else
- {
-@@ -9505,7 +13267,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001001x1110xxxxx01xxxx1xxxx1xxxx
- nands. */
-- return 1688;
-+ return 1758;
- }
- }
- }
-@@ -9517,7 +13279,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 101001x1110xxxxx010xxxxxxxxxxxxx
- ld1sb. */
-- return 1518;
-+ return 1572;
- }
- else
- {
-@@ -9525,7 +13287,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 101001x1110xxxxx011xxxxxxxxxxxxx
- ldff1sb. */
-- return 1610;
-+ return 1674;
- }
- }
- }
-@@ -9543,7 +13305,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x01001x1001xxxxx010xxxxxxxxxxxxx
- ld1sh. */
-- return 1529;
-+ return 1583;
- }
- else
- {
-@@ -9551,7 +13313,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x01001x1101xxxxx010xxxxxxxxxxxxx
- ld1sb. */
-- return 1517;
-+ return 1571;
- }
- }
- else
-@@ -9562,7 +13324,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x01001x1011xxxxx010xxxxxxxxxxxxx
- ld1w. */
-- return 1548;
-+ return 1602;
- }
- else
- {
-@@ -9570,7 +13332,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x01001x1111xxxxx010xxxxxxxxxxxxx
- ld1d. */
-- return 1470;
-+ return 1524;
- }
- }
- }
-@@ -9584,7 +13346,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x01001x1001xxxxx011xxxxxxxxxxxxx
- ldff1sh. */
-- return 1618;
-+ return 1684;
- }
- else
- {
-@@ -9592,7 +13354,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x01001x1101xxxxx011xxxxxxxxxxxxx
- ldff1sb. */
-- return 1609;
-+ return 1672;
- }
- }
- else
-@@ -9603,7 +13365,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x01001x1011xxxxx011xxxxxxxxxxxxx
- ldff1w. */
-- return 1634;
-+ return 1703;
- }
- else
- {
-@@ -9611,7 +13373,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x01001x1111xxxxx011xxxxxxxxxxxxx
- ldff1d. */
-- return 1590;
-+ return 1648;
- }
- }
- }
-@@ -9631,7 +13393,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 011001x1xx0xxxxx010xxxxxxxx0xxxx
- fcmge. */
-- return 1349;
-+ return 1403;
- }
- else
- {
-@@ -9639,7 +13401,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 011001x1xx0xxxxx010xxxxxxxx1xxxx
- fcmgt. */
-- return 1351;
-+ return 1405;
- }
- }
- else
-@@ -9648,7 +13410,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 011001x1xx1xxxxx010xxxxxxxxxxxxx
- fnmla. */
-- return 1413;
-+ return 1467;
- }
- }
- else
-@@ -9659,7 +13421,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 111001x1x0xxxxxx010xxxxxxxxxxxxx
- str. */
-- return 1883;
-+ return 1953;
- }
- else
- {
-@@ -9669,7 +13431,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 111001x1x10xxxxx010xxxxxxxxxxxxx
- st1w. */
-- return 1842;
-+ return 1912;
- }
- else
- {
-@@ -9679,7 +13441,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 111001x1011xxxxx010xxxxxxxxxxxxx
- st1w. */
-- return 1844;
-+ return 1914;
- }
- else
- {
-@@ -9687,7 +13449,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 111001x1111xxxxx010xxxxxxxxxxxxx
- st1d. */
-- return 1821;
-+ return 1891;
- }
- }
- }
-@@ -9705,7 +13467,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 011001x1xx0xxxxx011xxxxxxxx0xxxx
- fcmeq. */
-- return 1347;
-+ return 1401;
- }
- else
- {
-@@ -9713,7 +13475,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 011001x1xx0xxxxx011xxxxxxxx1xxxx
- fcmne. */
-- return 1355;
-+ return 1409;
- }
- }
- else
-@@ -9726,7 +13488,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 111001x1000xxxxx011xxxxxxxxxxxxx
- stnt1w. */
-- return 1880;
-+ return 1950;
- }
- else
- {
-@@ -9734,7 +13496,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 111001x1100xxxxx011xxxxxxxxxxxxx
- stnt1d. */
-- return 1876;
-+ return 1946;
- }
- }
- else
-@@ -9745,7 +13507,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 111001x1010xxxxx011xxxxxxxxxxxxx
- st3w. */
-- return 1864;
-+ return 1934;
- }
- else
- {
-@@ -9753,7 +13515,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 111001x1110xxxxx011xxxxxxxxxxxxx
- st3d. */
-- return 1860;
-+ return 1930;
- }
- }
- }
-@@ -9766,7 +13528,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 011001x1xx1xxxxx011xxxxxxxxxxxxx
- fnmls. */
-- return 1414;
-+ return 1468;
- }
- else
- {
-@@ -9778,7 +13540,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 111001x1001xxxxx011xxxxxxxxxxxxx
- st2w. */
-- return 1856;
-+ return 1926;
- }
- else
- {
-@@ -9786,7 +13548,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 111001x1101xxxxx011xxxxxxxxxxxxx
- st2d. */
-- return 1852;
-+ return 1922;
- }
- }
- else
-@@ -9797,7 +13559,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 111001x1011xxxxx011xxxxxxxxxxxxx
- st4w. */
-- return 1872;
-+ return 1942;
- }
- else
- {
-@@ -9805,7 +13567,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 111001x1111xxxxx011xxxxxxxxxxxxx
- st4d. */
-- return 1868;
-+ return 1938;
- }
- }
- }
-@@ -9830,7 +13592,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x01001x1xx0xxxxx100xxxxxxxx0xxxx
- cmpeq. */
-- return 1276;
-+ return 1330;
- }
- else
- {
-@@ -9838,7 +13600,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x01001x1xx0xxxxx100xxxxxxxx1xxxx
- cmpne. */
-- return 1299;
-+ return 1353;
- }
- }
- else
-@@ -9853,7 +13615,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x01001x10000xxxx101xxxxxxxxxxxxx
- ld1sh. */
-- return 1535;
-+ return 1589;
- }
- else
- {
-@@ -9861,7 +13623,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x01001x11000xxxx101xxxxxxxxxxxxx
- ld1sb. */
-- return 1522;
-+ return 1576;
- }
- }
- else
-@@ -9872,7 +13634,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x01001x10100xxxx101xxxxxxxxxxxxx
- ld1w. */
-- return 1554;
-+ return 1608;
- }
- else
- {
-@@ -9880,7 +13642,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x01001x11100xxxx101xxxxxxxxxxxxx
- ld1sb. */
-- return 1524;
-+ return 1578;
- }
- }
- }
-@@ -9894,7 +13656,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x01001x10001xxxx101xxxxxxxxxxxxx
- ldnf1sh. */
-- return 1652;
-+ return 1722;
- }
- else
- {
-@@ -9902,7 +13664,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x01001x11001xxxx101xxxxxxxxxxxxx
- ldnf1sb. */
-- return 1649;
-+ return 1719;
- }
- }
- else
-@@ -9913,7 +13675,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x01001x10101xxxx101xxxxxxxxxxxxx
- ldnf1w. */
-- return 1655;
-+ return 1725;
- }
- else
- {
-@@ -9921,7 +13683,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x01001x11101xxxx101xxxxxxxxxxxxx
- ldnf1sb. */
-- return 1651;
-+ return 1721;
- }
- }
- }
-@@ -9941,7 +13703,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001001x1x000xxxx11xxxxxxxxx0xxxx
- brkpa. */
-- return 1262;
-+ return 1316;
- }
- else
- {
-@@ -9949,7 +13711,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001001x1x100xxxx11xxxxxxxxx0xxxx
- brkpas. */
-- return 1263;
-+ return 1317;
- }
- }
- else
-@@ -9962,7 +13724,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001001x1xx010xx011xxxxxxxxx0xxxx
- ptest. */
-- return 1732;
-+ return 1802;
- }
- else
- {
-@@ -9976,7 +13738,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001001x1xx011xx01100x0xxxxx0xxxx
- pfirst. */
-- return 1702;
-+ return 1772;
- }
- else
- {
-@@ -9984,7 +13746,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001001x1xx011xx01110x0xxxxx0xxxx
- ptrue. */
-- return 1733;
-+ return 1803;
- }
- }
- else
-@@ -9995,7 +13757,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001001x1x0011xx011x1x0xxxxx0xxxx
- rdffr. */
-- return 1739;
-+ return 1809;
- }
- else
- {
-@@ -10003,7 +13765,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001001x1x1011xx011x1x0xxxxx0xxxx
- rdffrs. */
-- return 1740;
-+ return 1810;
- }
- }
- }
-@@ -10013,7 +13775,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001001x1xx011xx011xxx1xxxxx0xxxx
- pfalse. */
-- return 1701;
-+ return 1771;
- }
- }
- }
-@@ -10027,7 +13789,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001001x1xx01xxx111x0x0xxxxx0xxxx
- ptrues. */
-- return 1734;
-+ return 1804;
- }
- else
- {
-@@ -10035,7 +13797,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001001x1xx01xxx111x1x0xxxxx0xxxx
- rdffr. */
-- return 1738;
-+ return 1808;
- }
- }
- else
-@@ -10044,7 +13806,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001001x1xx01xxx111xxx1xxxxx0xxxx
- pnext. */
-- return 1703;
-+ return 1773;
- }
- }
- }
-@@ -10057,7 +13819,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001001x1x00xxxxx11xxxxxxxxx1xxxx
- brkpb. */
-- return 1264;
-+ return 1318;
- }
- else
- {
-@@ -10065,7 +13827,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001001x1x10xxxxx11xxxxxxxxx1xxxx
- brkpbs. */
-- return 1265;
-+ return 1319;
- }
- }
- }
-@@ -10081,7 +13843,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 101001x1000xxxxx110xxxxxxxxxxxxx
- ldnt1w. */
-- return 1663;
-+ return 1733;
- }
- else
- {
-@@ -10089,7 +13851,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 101001x1100xxxxx110xxxxxxxxxxxxx
- ldnt1d. */
-- return 1659;
-+ return 1729;
- }
- }
- else
-@@ -10100,7 +13862,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 101001x1010xxxxx110xxxxxxxxxxxxx
- ld3w. */
-- return 1571;
-+ return 1625;
- }
- else
- {
-@@ -10108,7 +13870,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 101001x1110xxxxx110xxxxxxxxxxxxx
- ld3d. */
-- return 1567;
-+ return 1621;
- }
- }
- }
-@@ -10122,7 +13884,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 101001x1000xxxxx111xxxxxxxxxxxxx
- ldnt1w. */
-- return 1664;
-+ return 1734;
- }
- else
- {
-@@ -10130,7 +13892,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 101001x1100xxxxx111xxxxxxxxxxxxx
- ldnt1d. */
-- return 1660;
-+ return 1730;
- }
- }
- else
-@@ -10141,7 +13903,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 101001x1010xxxxx111xxxxxxxxxxxxx
- ld3w. */
-- return 1572;
-+ return 1626;
- }
- else
- {
-@@ -10149,7 +13911,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 101001x1110xxxxx111xxxxxxxxxxxxx
- ld3d. */
-- return 1568;
-+ return 1622;
- }
- }
- }
-@@ -10178,7 +13940,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 011001x1xx000000100xxxxxxxxxxxxx
- fadd. */
-- return 1338;
-+ return 1392;
- }
- else
- {
-@@ -10186,7 +13948,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 011001x1xx000100100xxxxxxxxxxxxx
- fmaxnm. */
-- return 1385;
-+ return 1439;
- }
- }
- else
-@@ -10197,7 +13959,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 011001x1xx000010100xxxxxxxxxxxxx
- fmul. */
-- return 1405;
-+ return 1459;
- }
- else
- {
-@@ -10205,7 +13967,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 011001x1xx000110100xxxxxxxxxxxxx
- fmax. */
-- return 1383;
-+ return 1437;
- }
- }
- }
-@@ -10219,7 +13981,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 011001x1xx000001100xxxxxxxxxxxxx
- fsub. */
-- return 1431;
-+ return 1485;
- }
- else
- {
-@@ -10227,7 +13989,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 011001x1xx000101100xxxxxxxxxxxxx
- fminnm. */
-- return 1391;
-+ return 1445;
- }
- }
- else
-@@ -10238,7 +14000,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 011001x1xx000011100xxxxxxxxxxxxx
- fsubr. */
-- return 1433;
-+ return 1487;
- }
- else
- {
-@@ -10246,7 +14008,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 011001x1xx000111100xxxxxxxxxxxxx
- fmin. */
-- return 1389;
-+ return 1443;
- }
- }
- }
-@@ -10257,7 +14019,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 011001x1xx010xxx100xxxxxxxxxxxxx
- ftmad. */
-- return 1435;
-+ return 1489;
- }
- }
- else
-@@ -10274,7 +14036,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 011001x1xx001000100xxxxxxxxxxxxx
- fabd. */
-- return 1333;
-+ return 1387;
- }
- else
- {
-@@ -10282,7 +14044,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 011001x1xx011000100xxxxxxxxxxxxx
- fadd. */
-- return 1339;
-+ return 1393;
- }
- }
- else
-@@ -10293,7 +14055,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 011001x1xx001100100xxxxxxxxxxxxx
- fdivr. */
-- return 1379;
-+ return 1433;
- }
- else
- {
-@@ -10301,7 +14063,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 011001x1xx011100100xxxxxxxxxxxxx
- fmaxnm. */
-- return 1386;
-+ return 1440;
- }
- }
- }
-@@ -10315,7 +14077,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 011001x1xx001010100xxxxxxxxxxxxx
- fmulx. */
-- return 1410;
-+ return 1464;
- }
- else
- {
-@@ -10323,7 +14085,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 011001x1xx011010100xxxxxxxxxxxxx
- fmul. */
-- return 1406;
-+ return 1460;
- }
- }
- else
-@@ -10332,7 +14094,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 011001x1xx0x1110100xxxxxxxxxxxxx
- fmax. */
-- return 1384;
-+ return 1438;
- }
- }
- }
-@@ -10348,7 +14110,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 011001x1xx001001100xxxxxxxxxxxxx
- fscale. */
-- return 1428;
-+ return 1482;
- }
- else
- {
-@@ -10356,7 +14118,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 011001x1xx011001100xxxxxxxxxxxxx
- fsub. */
-- return 1432;
-+ return 1486;
- }
- }
- else
-@@ -10367,7 +14129,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 011001x1xx001101100xxxxxxxxxxxxx
- fdiv. */
-- return 1378;
-+ return 1432;
- }
- else
- {
-@@ -10375,7 +14137,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 011001x1xx011101100xxxxxxxxxxxxx
- fminnm. */
-- return 1392;
-+ return 1446;
- }
- }
- }
-@@ -10387,7 +14149,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 011001x1xx0x1011100xxxxxxxxxxxxx
- fsubr. */
-- return 1434;
-+ return 1488;
- }
- else
- {
-@@ -10395,7 +14157,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 011001x1xx0x1111100xxxxxxxxxxxxx
- fmin. */
-- return 1390;
-+ return 1444;
- }
- }
- }
-@@ -10409,7 +14171,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 011001x1xx0xxxxx110xxxxxxxx0xxxx
- fcmuo. */
-- return 1356;
-+ return 1410;
- }
- else
- {
-@@ -10417,7 +14179,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 011001x1xx0xxxxx110xxxxxxxx1xxxx
- facge. */
-- return 1335;
-+ return 1389;
- }
- }
- }
-@@ -10431,7 +14193,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 111001x1000xxxxx1x0xxxxxxxxxxxxx
- st1w. */
-- return 1838;
-+ return 1908;
- }
- else
- {
-@@ -10439,7 +14201,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 111001x1100xxxxx1x0xxxxxxxxxxxxx
- st1d. */
-- return 1817;
-+ return 1887;
- }
- }
- else
-@@ -10448,7 +14210,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 111001x1x10xxxxx1x0xxxxxxxxxxxxx
- st1w. */
-- return 1843;
-+ return 1913;
- }
- }
- }
-@@ -10460,11 +14222,11 @@ aarch64_opcode_lookup_1 (uint32_t word)
- {
- if (((word >> 16) & 0x1) == 0)
- {
-- if (((word >> 17) & 0x1) == 0)
-+ if (((word >> 19) & 0x1) == 0)
- {
-- if (((word >> 18) & 0x1) == 0)
-+ if (((word >> 17) & 0x1) == 0)
- {
-- if (((word >> 19) & 0x1) == 0)
-+ if (((word >> 18) & 0x1) == 0)
- {
- if (((word >> 20) & 0x1) == 0)
- {
-@@ -10472,7 +14234,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 011001x1xx000000101xxxxxxxxxxxxx
- frintn. */
-- return 1422;
-+ return 1476;
- }
- else
- {
-@@ -10480,51 +14242,18 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 011001x1xx010000101xxxxxxxxxxxxx
- scvtf. */
-- return 1752;
-+ return 1822;
- }
- }
- else
- {
- if (((word >> 20) & 0x1) == 0)
- {
-- if (((word >> 22) & 0x1) == 0)
-- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 011001x1x0001000101xxxxxxxxxxxxx
-- fcvt. */
-- return 1358;
-- }
-- else
-- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 011001x1x1001000101xxxxxxxxxxxxx
-- fcvt. */
-- return 1360;
-- }
-- }
-- else
-- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 011001x1xx011000101xxxxxxxxxxxxx
-- fcvtzs. */
-- return 1368;
-- }
-- }
-- }
-- else
-- {
-- if (((word >> 19) & 0x1) == 0)
-- {
-- if (((word >> 20) & 0x1) == 0)
-- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 011001x1xx000100101xxxxxxxxxxxxx
- frinta. */
-- return 1419;
-+ return 1473;
- }
- else
- {
-@@ -10534,7 +14263,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 011001x1x0010100101xxxxxxxxxxxxx
- scvtf. */
-- return 1751;
-+ return 1821;
- }
- else
- {
-@@ -10544,7 +14273,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 011001x101010100101xxxxxxxxxxxxx
- scvtf. */
-- return 1750;
-+ return 1820;
- }
- else
- {
-@@ -10552,49 +14281,60 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 011001x111010100101xxxxxxxxxxxxx
- scvtf. */
-- return 1754;
-+ return 1824;
- }
- }
- }
- }
-+ }
-+ else
-+ {
-+ if (((word >> 18) & 0x1) == 0)
-+ {
-+ if (((word >> 20) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 011001x1xx000010101xxxxxxxxxxxxx
-+ frintm. */
-+ return 1475;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 011001x1xx010010101xxxxxxxxxxxxx
-+ scvtf. */
-+ return 1819;
-+ }
-+ }
- else
- {
- if (((word >> 20) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
-- 011001x1xx001100101xxxxxxxxxxxxx
-- frecpx. */
-- return 1418;
-+ 011001x1xx000110101xxxxxxxxxxxxx
-+ frintx. */
-+ return 1478;
- }
- else
- {
-- if (((word >> 22) & 0x1) == 0)
-+ if (((word >> 23) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
-- 011001x1x0011100101xxxxxxxxxxxxx
-- fcvtzs. */
-- return 1367;
-+ 011001x10x010110101xxxxxxxxxxxxx
-+ scvtf. */
-+ return 1823;
- }
- else
- {
-- if (((word >> 23) & 0x1) == 0)
-- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 011001x101011100101xxxxxxxxxxxxx
-- fcvtzs. */
-- return 1365;
-- }
-- else
-- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 011001x111011100101xxxxxxxxxxxxx
-- fcvtzs. */
-- return 1369;
-- }
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 011001x11x010110101xxxxxxxxxxxxx
-+ scvtf. */
-+ return 1825;
- }
- }
- }
-@@ -10602,96 +14342,151 @@ aarch64_opcode_lookup_1 (uint32_t word)
- }
- else
- {
-- if (((word >> 18) & 0x1) == 0)
-+ if (((word >> 20) & 0x1) == 0)
- {
-- if (((word >> 19) & 0x1) == 0)
-+ if (((word >> 17) & 0x1) == 0)
- {
-- if (((word >> 20) & 0x1) == 0)
-+ if (((word >> 18) & 0x1) == 0)
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 011001x1xx000010101xxxxxxxxxxxxx
-- frintm. */
-- return 1421;
-+ if (((word >> 22) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 011001x1x0001000101xxxxxxxxxxxxx
-+ fcvt. */
-+ return 1412;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 011001x1x1001000101xxxxxxxxxxxxx
-+ fcvt. */
-+ return 1414;
-+ }
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
-- 011001x1xx010010101xxxxxxxxxxxxx
-- scvtf. */
-- return 1749;
-+ 011001x1xx001100101xxxxxxxxxxxxx
-+ frecpx. */
-+ return 1472;
- }
- }
- else
- {
-- if (((word >> 20) & 0x1) == 0)
-+ if (((word >> 22) & 0x1) == 0)
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 011001x1xx001010101xxxxxxxxxxxxx
-- fcvt. */
-- return 1362;
-+ if (((word >> 23) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 011001x100001x10101xxxxxxxxxxxxx
-+ fcvtx. */
-+ return 2082;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 011001x110001x10101xxxxxxxxxxxxx
-+ bfcvt. */
-+ return 2432;
-+ }
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
-- 011001x1xx011010101xxxxxxxxxxxxx
-- fcvtzs. */
-- return 1364;
-+ 011001x1x1001x10101xxxxxxxxxxxxx
-+ fcvt. */
-+ return 1416;
- }
- }
- }
- else
- {
-- if (((word >> 19) & 0x1) == 0)
-+ if (((word >> 22) & 0x1) == 0)
- {
-- if (((word >> 20) & 0x1) == 0)
-+ if (((word >> 23) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
-- 011001x1xx000110101xxxxxxxxxxxxx
-- frintx. */
-- return 1424;
-+ 011001x100011xx0101xxxxxxxxxxxxx
-+ flogb. */
-+ return 2084;
- }
- else
- {
-- if (((word >> 23) & 0x1) == 0)
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 011001x110011xx0101xxxxxxxxxxxxx
-+ fcvtzs. */
-+ return 1421;
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 17) & 0x1) == 0)
-+ {
-+ if (((word >> 18) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
-- 011001x10x010110101xxxxxxxxxxxxx
-- scvtf. */
-- return 1753;
-+ 011001x1x1011000101xxxxxxxxxxxxx
-+ fcvtzs. */
-+ return 1422;
- }
- else
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 011001x11x010110101xxxxxxxxxxxxx
-- scvtf. */
-- return 1755;
-+ if (((word >> 23) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 011001x101011100101xxxxxxxxxxxxx
-+ fcvtzs. */
-+ return 1419;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 011001x111011100101xxxxxxxxxxxxx
-+ fcvtzs. */
-+ return 1423;
-+ }
- }
- }
-- }
-- else
-- {
-- if (((word >> 23) & 0x1) == 0)
-- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 011001x10x0x1110101xxxxxxxxxxxxx
-- fcvtzs. */
-- return 1366;
-- }
- else
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 011001x11x0x1110101xxxxxxxxxxxxx
-- fcvtzs. */
-- return 1370;
-+ if (((word >> 18) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 011001x1x1011010101xxxxxxxxxxxxx
-+ fcvtzs. */
-+ return 1418;
-+ }
-+ else
-+ {
-+ if (((word >> 23) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 011001x101011110101xxxxxxxxxxxxx
-+ fcvtzs. */
-+ return 1420;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 011001x111011110101xxxxxxxxxxxxx
-+ fcvtzs. */
-+ return 1424;
-+ }
-+ }
- }
- }
- }
-@@ -10711,7 +14506,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 011001x1xx000001101xxxxxxxxxxxxx
- frintp. */
-- return 1423;
-+ return 1477;
- }
- else
- {
-@@ -10719,7 +14514,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 011001x1xx010001101xxxxxxxxxxxxx
- ucvtf. */
-- return 1904;
-+ return 1974;
- }
- }
- else
-@@ -10732,7 +14527,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 011001x1x0001001101xxxxxxxxxxxxx
- fcvt. */
-- return 1359;
-+ return 1413;
- }
- else
- {
-@@ -10740,7 +14535,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 011001x1x1001001101xxxxxxxxxxxxx
- fcvt. */
-- return 1361;
-+ return 1415;
- }
- }
- else
-@@ -10749,7 +14544,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 011001x1xx011001101xxxxxxxxxxxxx
- fcvtzu. */
-- return 1375;
-+ return 1429;
- }
- }
- }
-@@ -10763,7 +14558,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 011001x1x00x0101101xxxxxxxxxxxxx
- ucvtf. */
-- return 1903;
-+ return 1973;
- }
- else
- {
-@@ -10773,7 +14568,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 011001x1010x0101101xxxxxxxxxxxxx
- ucvtf. */
-- return 1902;
-+ return 1972;
- }
- else
- {
-@@ -10781,7 +14576,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 011001x1110x0101101xxxxxxxxxxxxx
- ucvtf. */
-- return 1906;
-+ return 1976;
- }
- }
- }
-@@ -10793,7 +14588,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 011001x1xx001101101xxxxxxxxxxxxx
- fsqrt. */
-- return 1429;
-+ return 1483;
- }
- else
- {
-@@ -10803,7 +14598,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 011001x1x0011101101xxxxxxxxxxxxx
- fcvtzu. */
-- return 1374;
-+ return 1428;
- }
- else
- {
-@@ -10813,7 +14608,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 011001x101011101101xxxxxxxxxxxxx
- fcvtzu. */
-- return 1372;
-+ return 1426;
- }
- else
- {
-@@ -10821,7 +14616,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 011001x111011101101xxxxxxxxxxxxx
- fcvtzu. */
-- return 1376;
-+ return 1430;
- }
- }
- }
-@@ -10840,7 +14635,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 011001x1xx000011101xxxxxxxxxxxxx
- frintz. */
-- return 1425;
-+ return 1479;
- }
- else
- {
-@@ -10848,7 +14643,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 011001x1xx010011101xxxxxxxxxxxxx
- ucvtf. */
-- return 1901;
-+ return 1971;
- }
- }
- else
-@@ -10859,7 +14654,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 011001x1xx001011101xxxxxxxxxxxxx
- fcvt. */
-- return 1363;
-+ return 1417;
- }
- else
- {
-@@ -10867,7 +14662,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 011001x1xx011011101xxxxxxxxxxxxx
- fcvtzu. */
-- return 1371;
-+ return 1425;
- }
- }
- }
-@@ -10881,7 +14676,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 011001x1xx000111101xxxxxxxxxxxxx
- frinti. */
-- return 1420;
-+ return 1474;
- }
- else
- {
-@@ -10891,7 +14686,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 011001x10x010111101xxxxxxxxxxxxx
- ucvtf. */
-- return 1905;
-+ return 1975;
- }
- else
- {
-@@ -10899,7 +14694,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 011001x11x010111101xxxxxxxxxxxxx
- ucvtf. */
-- return 1907;
-+ return 1977;
- }
- }
- }
-@@ -10911,7 +14706,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 011001x10x0x1111101xxxxxxxxxxxxx
- fcvtzu. */
-- return 1373;
-+ return 1427;
- }
- else
- {
-@@ -10919,7 +14714,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 011001x11x0x1111101xxxxxxxxxxxxx
- fcvtzu. */
-- return 1377;
-+ return 1431;
- }
- }
- }
-@@ -10936,7 +14731,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 111001x1000xxxxx101xxxxxxxxxxxxx
- st1w. */
-- return 1839;
-+ return 1909;
- }
- else
- {
-@@ -10944,7 +14739,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 111001x1100xxxxx101xxxxxxxxxxxxx
- st1d. */
-- return 1818;
-+ return 1888;
- }
- }
- else
-@@ -10955,7 +14750,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 111001x1010xxxxx101xxxxxxxxxxxxx
- st1w. */
-- return 1846;
-+ return 1916;
- }
- else
- {
-@@ -10963,7 +14758,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 111001x1110xxxxx101xxxxxxxxxxxxx
- st1d. */
-- return 1822;
-+ return 1892;
- }
- }
- }
-@@ -10976,7 +14771,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 011001x1xx0xxxxx111xxxxxxxxxxxxx
- facgt. */
-- return 1336;
-+ return 1390;
- }
- else
- {
-@@ -10986,7 +14781,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 111001x1xx00xxxx111xxxxxxxxxxxxx
- st1w. */
-- return 1847;
-+ return 1917;
- }
- else
- {
-@@ -10998,7 +14793,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 111001x10001xxxx111xxxxxxxxxxxxx
- stnt1w. */
-- return 1881;
-+ return 1951;
- }
- else
- {
-@@ -11006,7 +14801,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 111001x11001xxxx111xxxxxxxxxxxxx
- stnt1d. */
-- return 1877;
-+ return 1947;
- }
- }
- else
-@@ -11017,7 +14812,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 111001x10101xxxx111xxxxxxxxxxxxx
- st3w. */
-- return 1865;
-+ return 1935;
- }
- else
- {
-@@ -11025,7 +14820,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 111001x11101xxxx111xxxxxxxxxxxxx
- st3d. */
-- return 1861;
-+ return 1931;
- }
- }
- }
-@@ -11056,7 +14851,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001001x1xx10000010xxxxxxxxxxxxxx
- cntp. */
-- return 1305;
-+ return 1359;
- }
- else
- {
-@@ -11070,7 +14865,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001001x1xx10100010x000xxxxxxxxxx
- sqincp. */
-- return 1796;
-+ return 1866;
- }
- else
- {
-@@ -11078,7 +14873,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001001x1xx10100010x100xxxxxxxxxx
- wrffr. */
-- return 1969;
-+ return 2039;
- }
- }
- else
-@@ -11087,7 +14882,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001001x1xx10100010xx10xxxxxxxxxx
- sqincp. */
-- return 1798;
-+ return 1868;
- }
- }
- else
-@@ -11096,7 +14891,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001001x1xx10100010xxx1xxxxxxxxxx
- sqincp. */
-- return 1797;
-+ return 1867;
- }
- }
- }
-@@ -11110,7 +14905,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001001x1xx10x10010x00xxxxxxxxxxx
- incp. */
-- return 1443;
-+ return 1497;
- }
- else
- {
-@@ -11118,7 +14913,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001001x1xx10x10010x10xxxxxxxxxxx
- setffr. */
-- return 1763;
-+ return 1833;
- }
- }
- else
-@@ -11127,7 +14922,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001001x1xx10x10010xx1xxxxxxxxxxx
- incp. */
-- return 1444;
-+ return 1498;
- }
- }
- }
-@@ -11141,7 +14936,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001001x1xx10xx1010xx00xxxxxxxxxx
- sqdecp. */
-- return 1782;
-+ return 1852;
- }
- else
- {
-@@ -11149,7 +14944,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001001x1xx10xx1010xx10xxxxxxxxxx
- sqdecp. */
-- return 1784;
-+ return 1854;
- }
- }
- else
-@@ -11158,7 +14953,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001001x1xx10xx1010xxx1xxxxxxxxxx
- sqdecp. */
-- return 1783;
-+ return 1853;
- }
- }
- }
-@@ -11176,7 +14971,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001001x1xx10x00110xx00xxxxxxxxxx
- uqincp. */
-- return 1944;
-+ return 2014;
- }
- else
- {
-@@ -11184,7 +14979,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001001x1xx10x10110xx00xxxxxxxxxx
- decp. */
-- return 1318;
-+ return 1372;
- }
- }
- else
-@@ -11193,7 +14988,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001001x1xx10xx1110xx00xxxxxxxxxx
- uqdecp. */
-- return 1930;
-+ return 2000;
- }
- }
- else
-@@ -11206,7 +15001,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001001x1xx10x00110xx10xxxxxxxxxx
- uqincp. */
-- return 1945;
-+ return 2015;
- }
- else
- {
-@@ -11214,7 +15009,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001001x1xx10x10110xx10xxxxxxxxxx
- decp. */
-- return 1319;
-+ return 1373;
- }
- }
- else
-@@ -11223,7 +15018,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001001x1xx10xx1110xx10xxxxxxxxxx
- uqdecp. */
-- return 1931;
-+ return 2001;
- }
- }
- }
-@@ -11235,7 +15030,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001001x1xx10xx0110xxx1xxxxxxxxxx
- uqincp. */
-- return 1946;
-+ return 2016;
- }
- else
- {
-@@ -11243,7 +15038,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001001x1xx10xx1110xxx1xxxxxxxxxx
- uqdecp. */
-- return 1932;
-+ return 2002;
- }
- }
- }
-@@ -11258,7 +15053,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 101001x10010xxxx10xxxxxxxxxxxxxx
- ld1sh. */
-- return 1536;
-+ return 1590;
- }
- else
- {
-@@ -11266,7 +15061,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 101001x11010xxxx10xxxxxxxxxxxxxx
- ld1sb. */
-- return 1523;
-+ return 1577;
- }
- }
- else
-@@ -11277,7 +15072,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 101001x10110xxxx10xxxxxxxxxxxxxx
- ld1w. */
-- return 1555;
-+ return 1609;
- }
- else
- {
-@@ -11285,7 +15080,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 101001x11110xxxx10xxxxxxxxxxxxxx
- ld1d. */
-- return 1475;
-+ return 1529;
- }
- }
- }
-@@ -11300,7 +15095,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x01001x10011xxxx10xxxxxxxxxxxxxx
- ldnf1sh. */
-- return 1653;
-+ return 1723;
- }
- else
- {
-@@ -11308,7 +15103,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x01001x11011xxxx10xxxxxxxxxxxxxx
- ldnf1sb. */
-- return 1650;
-+ return 1720;
- }
- }
- else
-@@ -11319,7 +15114,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x01001x10111xxxx10xxxxxxxxxxxxxx
- ldnf1w. */
-- return 1656;
-+ return 1726;
- }
- else
- {
-@@ -11327,7 +15122,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x01001x11111xxxx10xxxxxxxxxxxxxx
- ldnf1d. */
-- return 1645;
-+ return 1715;
- }
- }
- }
-@@ -11350,7 +15145,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001001x1xx10000011xxxxxxxxxxxxxx
- add. */
-- return 1232;
-+ return 1286;
- }
- else
- {
-@@ -11358,7 +15153,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001001x1xx11000011xxxxxxxxxxxxxx
- mul. */
-- return 1685;
-+ return 1755;
- }
- }
- else
-@@ -11369,7 +15164,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001001x1xx10100011xxxxxxxxxxxxxx
- smax. */
-- return 1764;
-+ return 1834;
- }
- else
- {
-@@ -11377,7 +15172,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001001x1xx11100011xxxxxxxxxxxxxx
- dup. */
-- return 1324;
-+ return 1378;
- }
- }
- }
-@@ -11387,7 +15182,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001001x1xx1xx10011xxxxxxxxxxxxxx
- sqadd. */
-- return 1773;
-+ return 1843;
- }
- }
- else
-@@ -11398,7 +15193,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001001x1xx1xx01011xxxxxxxxxxxxxx
- smin. */
-- return 1767;
-+ return 1837;
- }
- else
- {
-@@ -11406,7 +15201,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001001x1xx1xx11011xxxxxxxxxxxxxx
- sqsub. */
-- return 1803;
-+ return 1873;
- }
- }
- }
-@@ -11422,7 +15217,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001001x1xx1x000111xxxxxxxxxxxxxx
- sub. */
-- return 1885;
-+ return 1955;
- }
- else
- {
-@@ -11432,7 +15227,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001001x1xx10100111xxxxxxxxxxxxxx
- umax. */
-- return 1913;
-+ return 1983;
- }
- else
- {
-@@ -11440,7 +15235,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001001x1xx11100111xxxxxxxxxxxxxx
- fdup. */
-- return 1380;
-+ return 1434;
- }
- }
- }
-@@ -11450,7 +15245,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001001x1xx1xx10111xxxxxxxxxxxxxx
- uqadd. */
-- return 1921;
-+ return 1991;
- }
- }
- else
-@@ -11463,7 +15258,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001001x1xx1x001111xxxxxxxxxxxxxx
- subr. */
-- return 1887;
-+ return 1957;
- }
- else
- {
-@@ -11471,7 +15266,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001001x1xx1x101111xxxxxxxxxxxxxx
- umin. */
-- return 1916;
-+ return 1986;
- }
- }
- else
-@@ -11480,7 +15275,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 001001x1xx1xx11111xxxxxxxxxxxxxx
- uqsub. */
-- return 1951;
-+ return 2021;
- }
- }
- }
-@@ -11497,7 +15292,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 101001x1001xxxxx110xxxxxxxxxxxxx
- ld2w. */
-- return 1563;
-+ return 1617;
- }
- else
- {
-@@ -11505,7 +15300,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 101001x1101xxxxx110xxxxxxxxxxxxx
- ld2d. */
-- return 1559;
-+ return 1613;
- }
- }
- else
-@@ -11516,7 +15311,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 101001x1011xxxxx110xxxxxxxxxxxxx
- ld4w. */
-- return 1579;
-+ return 1633;
- }
- else
- {
-@@ -11524,7 +15319,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 101001x1111xxxxx110xxxxxxxxxxxxx
- ld4d. */
-- return 1575;
-+ return 1629;
- }
- }
- }
-@@ -11538,7 +15333,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 101001x1001xxxxx111xxxxxxxxxxxxx
- ld2w. */
-- return 1564;
-+ return 1618;
- }
- else
- {
-@@ -11546,7 +15341,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 101001x1101xxxxx111xxxxxxxxxxxxx
- ld2d. */
-- return 1560;
-+ return 1614;
- }
- }
- else
-@@ -11557,7 +15352,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 101001x1011xxxxx111xxxxxxxxxxxxx
- ld4w. */
-- return 1580;
-+ return 1634;
- }
- else
- {
-@@ -11565,7 +15360,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 101001x1111xxxxx111xxxxxxxxxxxxx
- ld4d. */
-- return 1576;
-+ return 1630;
- }
- }
- }
-@@ -11584,7 +15379,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 011001x1xx1xxxxx100xxxxxxxxxxxxx
- fmad. */
-- return 1382;
-+ return 1436;
- }
- else
- {
-@@ -11592,7 +15387,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 011001x1xx1xxxxx110xxxxxxxxxxxxx
- fnmad. */
-- return 1412;
-+ return 1466;
- }
- }
- else
-@@ -11605,7 +15400,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 111001x1001xxxxx1x0xxxxxxxxxxxxx
- st1w. */
-- return 1840;
-+ return 1910;
- }
- else
- {
-@@ -11613,7 +15408,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 111001x1101xxxxx1x0xxxxxxxxxxxxx
- st1d. */
-- return 1819;
-+ return 1889;
- }
- }
- else
-@@ -11622,7 +15417,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 111001x1x11xxxxx1x0xxxxxxxxxxxxx
- st1w. */
-- return 1845;
-+ return 1915;
- }
- }
- }
-@@ -11636,7 +15431,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 011001x1xx1xxxxx101xxxxxxxxxxxxx
- fmsb. */
-- return 1403;
-+ return 1457;
- }
- else
- {
-@@ -11648,7 +15443,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 111001x1001xxxxx101xxxxxxxxxxxxx
- st1w. */
-- return 1841;
-+ return 1911;
- }
- else
- {
-@@ -11656,7 +15451,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 111001x1101xxxxx101xxxxxxxxxxxxx
- st1d. */
-- return 1820;
-+ return 1890;
- }
- }
- else
-@@ -11665,7 +15460,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 111001x1x11xxxxx101xxxxxxxxxxxxx
- st1w. */
-- return 1848;
-+ return 1918;
- }
- }
- }
-@@ -11677,7 +15472,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 011001x1xx1xxxxx111xxxxxxxxxxxxx
- fnmsb. */
-- return 1415;
-+ return 1469;
- }
- else
- {
-@@ -11689,7 +15484,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 111001x10x10xxxx111xxxxxxxxxxxxx
- st1w. */
-- return 1849;
-+ return 1919;
- }
- else
- {
-@@ -11697,7 +15492,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 111001x11x10xxxx111xxxxxxxxxxxxx
- st1d. */
-- return 1823;
-+ return 1893;
- }
- }
- else
-@@ -11710,7 +15505,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 111001x10011xxxx111xxxxxxxxxxxxx
- st2w. */
-- return 1857;
-+ return 1927;
- }
- else
- {
-@@ -11718,7 +15513,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 111001x11011xxxx111xxxxxxxxxxxxx
- st2d. */
-- return 1853;
-+ return 1923;
- }
- }
- else
-@@ -11729,7 +15524,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 111001x10111xxxx111xxxxxxxxxxxxx
- st4w. */
-- return 1873;
-+ return 1943;
- }
- else
- {
-@@ -11737,7 +15532,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 111001x11111xxxx111xxxxxxxxxxxxx
- st4d. */
-- return 1869;
-+ return 1939;
- }
- }
- }
-@@ -11762,7 +15557,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 000101xxxxxxxxxxxxxxxxxxxxxxxxxx
- b. */
-- return 630;
-+ return 636;
- }
- else
- {
-@@ -11770,7 +15565,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 100101xxxxxxxxxxxxxxxxxxxxxxxxxx
- bl. */
-- return 631;
-+ return 637;
- }
- }
- else
-@@ -11787,7 +15582,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 01010100xxxxxxxxxxxxxxxxxxx0xxxx
- b.c. */
-- return 651;
-+ return 657;
- }
- else
- {
-@@ -11801,15 +15596,26 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 11010100xx0xxxxxxxxxxxxxxxx0xx00
- hlt. */
-- return 742;
-+ return 753;
- }
- else
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 11010100xx1xxxxxxxxxxxxxxxx0xx00
-- brk. */
-- return 741;
-+ if (((word >> 22) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 11010100x01xxxxxxxxxxxxxxxx0xx00
-+ brk. */
-+ return 752;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 11010100x11xxxxxxxxxxxxxxxx0xx00
-+ tcancel. */
-+ return 1196;
-+ }
- }
- }
- else
-@@ -11820,7 +15626,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 11010100xx0xxxxxxxxxxxxxxxx0xx10
- hvc. */
-- return 739;
-+ return 750;
- }
- else
- {
-@@ -11828,7 +15634,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 11010100xx1xxxxxxxxxxxxxxxx0xx10
- dcps2. */
-- return 744;
-+ return 756;
- }
- }
- }
-@@ -11842,7 +15648,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 11010100xx0xxxxxxxxxxxxxxxx0xx01
- svc. */
-- return 738;
-+ return 749;
- }
- else
- {
-@@ -11850,7 +15656,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 11010100xx1xxxxxxxxxxxxxxxx0xx01
- dcps1. */
-- return 743;
-+ return 755;
- }
- }
- else
-@@ -11861,7 +15667,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 11010100xx0xxxxxxxxxxxxxxxx0xx11
- smc. */
-- return 740;
-+ return 751;
- }
- else
- {
-@@ -11869,7 +15675,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 11010100xx1xxxxxxxxxxxxxxxx0xx11
- dcps3. */
-- return 745;
-+ return 757;
- }
- }
- }
-@@ -11887,7 +15693,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1010110000xxxxxxxxxxxxxxxx0xxxx
- br. */
-- return 632;
-+ return 638;
- }
- else
- {
-@@ -11895,7 +15701,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1010110100xxxxxxxxxxxxxxxx0xxxx
- eret. */
-- return 635;
-+ return 641;
- }
- }
- else
-@@ -11904,7 +15710,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1010110x10xxxxxxxxxxxxxxxx0xxxx
- ret. */
-- return 634;
-+ return 640;
- }
- }
- else
-@@ -11915,7 +15721,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x10101100x1xxxxxxxxxxxxxxxx0xxxx
- blr. */
-- return 633;
-+ return 639;
- }
- else
- {
-@@ -11923,7 +15729,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x10101101x1xxxxxxxxxxxxxxxx0xxxx
- drps. */
-- return 636;
-+ return 642;
- }
- }
- }
-@@ -11942,7 +15748,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x10101x0000xxxxxxxxxx0xxxxx1xxxx
- braaz. */
-- return 641;
-+ return 647;
- }
- else
- {
-@@ -11950,7 +15756,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x10101x0100xxxxxxxxxx0xxxxx1xxxx
- eretaa. */
-- return 647;
-+ return 653;
- }
- }
- else
-@@ -11959,7 +15765,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x10101x0x10xxxxxxxxxx0xxxxx1xxxx
- retaa. */
-- return 645;
-+ return 651;
- }
- }
- else
-@@ -11968,7 +15774,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x10101x0xx1xxxxxxxxxx0xxxxx1xxxx
- blraaz. */
-- return 643;
-+ return 649;
- }
- }
- else
-@@ -11983,7 +15789,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x10101x0000xxxxxxxxxx1xxxxx1xxxx
- brabz. */
-- return 642;
-+ return 648;
- }
- else
- {
-@@ -11991,7 +15797,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x10101x0100xxxxxxxxxx1xxxxx1xxxx
- eretab. */
-- return 648;
-+ return 654;
- }
- }
- else
-@@ -12000,7 +15806,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x10101x0x10xxxxxxxxxx1xxxxx1xxxx
- retab. */
-- return 646;
-+ return 652;
- }
- }
- else
-@@ -12009,7 +15815,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x10101x0xx1xxxxxxxxxx1xxxxx1xxxx
- blrabz. */
-- return 644;
-+ return 650;
- }
- }
- }
-@@ -12023,8 +15829,8 @@ aarch64_opcode_lookup_1 (uint32_t word)
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1010101xx0xxxxxxxxxxxxxxxxxxxxx
-- msr. */
-- return 1157;
-+ xaflag. */
-+ return 811;
- }
- else
- {
-@@ -12034,7 +15840,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1010111xx0xxxxxxxxxx0xxxxxxxxxx
- braa. */
-- return 637;
-+ return 643;
- }
- else
- {
-@@ -12042,7 +15848,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1010111xx0xxxxxxxxxx1xxxxxxxxxx
- brab. */
-- return 638;
-+ return 644;
- }
- }
- }
-@@ -12053,8 +15859,8 @@ aarch64_opcode_lookup_1 (uint32_t word)
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1010101xx1xxxxxxxxxxxxxxxxxxxxx
-- sysl. */
-- return 1183;
-+ tstart. */
-+ return 1193;
- }
- else
- {
-@@ -12064,7 +15870,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1010111xx1xxxxxxxxxx0xxxxxxxxxx
- blraa. */
-- return 639;
-+ return 645;
- }
- else
- {
-@@ -12072,7 +15878,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1010111xx1xxxxxxxxxx1xxxxxxxxxx
- blrab. */
-- return 640;
-+ return 646;
- }
- }
- }
-@@ -12089,7 +15895,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx110100xxxxxxxxxxxxxxxxxxxxxxxx
- cbz. */
-- return 649;
-+ return 655;
- }
- else
- {
-@@ -12097,7 +15903,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx110110xxxxxxxxxxxxxxxxxxxxxxxx
- tbz. */
-- return 1193;
-+ return 1247;
- }
- }
- else
-@@ -12108,7 +15914,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx110101xxxxxxxxxxxxxxxxxxxxxxxx
- cbnz. */
-- return 650;
-+ return 656;
- }
- else
- {
-@@ -12116,7 +15922,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx110111xxxxxxxxxxxxxxxxxxxxxxxx
- tbnz. */
-- return 1194;
-+ return 1248;
- }
- }
- }
-@@ -12140,7 +15946,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx00110000xxxxxxxxxxxxxxxxxxxxxx
- st4. */
-- return 434;
-+ return 440;
- }
- else
- {
-@@ -12148,7 +15954,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx10110000xxxxxxxxxxxxxxxxxxxxxx
- stnp. */
-- return 943;
-+ return 973;
- }
- }
- else
-@@ -12163,7 +15969,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx001101000xxxxxxx0xxxxxxxxxxxxx
- st1. */
-- return 450;
-+ return 456;
- }
- else
- {
-@@ -12171,7 +15977,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx001101001xxxxxxx0xxxxxxxxxxxxx
- st2. */
-- return 452;
-+ return 458;
- }
- }
- else
-@@ -12182,7 +15988,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx001101000xxxxxxx1xxxxxxxxxxxxx
- st3. */
-- return 451;
-+ return 457;
- }
- else
- {
-@@ -12190,7 +15996,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx001101001xxxxxxx1xxxxxxxxxxxxx
- st4. */
-- return 453;
-+ return 459;
- }
- }
- }
-@@ -12200,7 +16006,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx10110100xxxxxxxxxxxxxxxxxxxxxx
- stp. */
-- return 947;
-+ return 977;
- }
- }
- }
-@@ -12216,7 +16022,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx001100100xxxxxxxxxxxxxxxxxxxxx
- st4. */
-- return 442;
-+ return 448;
- }
- else
- {
-@@ -12226,7 +16032,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx001101100xxxxxxx0xxxxxxxxxxxxx
- st1. */
-- return 462;
-+ return 468;
- }
- else
- {
-@@ -12234,7 +16040,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx001101100xxxxxxx1xxxxxxxxxxxxx
- st3. */
-- return 463;
-+ return 469;
- }
- }
- }
-@@ -12246,7 +16052,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx00110x101xxxxxxx0xxxxxxxxxxxxx
- st2. */
-- return 464;
-+ return 470;
- }
- else
- {
-@@ -12254,7 +16060,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx00110x101xxxxxxx1xxxxxxxxxxxxx
- st4. */
-- return 465;
-+ return 471;
- }
- }
- }
-@@ -12264,7 +16070,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx10110x10xxxxxxxxxxxxxxxxxxxxxx
- stp. */
-- return 952;
-+ return 983;
- }
- }
- }
-@@ -12280,7 +16086,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx00110001xxxxxxxxxxxxxxxxxxxxxx
- ld4. */
-- return 438;
-+ return 444;
- }
- else
- {
-@@ -12288,7 +16094,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx10110001xxxxxxxxxxxxxxxxxxxxxx
- ldnp. */
-- return 944;
-+ return 974;
- }
- }
- else
-@@ -12303,7 +16109,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx001101010xxxxxxx0xxxxxxxxxxxxx
- ld1. */
-- return 454;
-+ return 460;
- }
- else
- {
-@@ -12311,7 +16117,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx001101011xxxxxxx0xxxxxxxxxxxxx
- ld2. */
-- return 458;
-+ return 464;
- }
- }
- else
-@@ -12322,7 +16128,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx001101010xxxxxxx1xxxxxxxxxxxxx
- ld3. */
-- return 455;
-+ return 461;
- }
- else
- {
-@@ -12330,7 +16136,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx001101011xxxxxxx1xxxxxxxxxxxxx
- ld4. */
-- return 459;
-+ return 465;
- }
- }
- }
-@@ -12340,7 +16146,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx10110101xxxxxxxxxxxxxxxxxxxxxx
- ldp. */
-- return 948;
-+ return 978;
- }
- }
- }
-@@ -12356,7 +16162,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx001100110xxxxxxxxxxxxxxxxxxxxx
- ld4. */
-- return 446;
-+ return 452;
- }
- else
- {
-@@ -12366,7 +16172,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx001101110xxxxxxx0xxxxxxxxxxxxx
- ld1. */
-- return 466;
-+ return 472;
- }
- else
- {
-@@ -12374,7 +16180,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx001101110xxxxxxx1xxxxxxxxxxxxx
- ld3. */
-- return 467;
-+ return 473;
- }
- }
- }
-@@ -12386,7 +16192,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx00110x111xxxxxxx0xxxxxxxxxxxxx
- ld2. */
-- return 470;
-+ return 476;
- }
- else
- {
-@@ -12394,7 +16200,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx00110x111xxxxxxx1xxxxxxxxxxxxx
- ld4. */
-- return 471;
-+ return 477;
- }
- }
- }
-@@ -12404,7 +16210,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx10110x11xxxxxxxxxxxxxxxxxxxxxx
- ldp. */
-- return 953;
-+ return 984;
- }
- }
- }
-@@ -12419,7 +16225,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx011100xxxxxxxxxxxxxxxxxxxxxxxx
- ldr. */
-- return 956;
-+ return 988;
- }
- else
- {
-@@ -12433,7 +16239,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx111100x0xxxxxxxxxx00xxxxxxxxxx
- stur. */
-- return 899;
-+ return 925;
- }
- else
- {
-@@ -12441,7 +16247,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx111100x1xxxxxxxxxx00xxxxxxxxxx
- ldur. */
-- return 900;
-+ return 926;
- }
- }
- else
-@@ -12452,7 +16258,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx111100x0xxxxxxxxxx10xxxxxxxxxx
- str. */
-- return 878;
-+ return 904;
- }
- else
- {
-@@ -12460,7 +16266,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx111100x1xxxxxxxxxx10xxxxxxxxxx
- ldr. */
-- return 879;
-+ return 905;
- }
- }
- }
-@@ -12472,7 +16278,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx111100x0xxxxxxxxxxx1xxxxxxxxxx
- str. */
-- return 855;
-+ return 873;
- }
- else
- {
-@@ -12480,7 +16286,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx111100x1xxxxxxxxxxx1xxxxxxxxxx
- ldr. */
-- return 856;
-+ return 874;
- }
- }
- }
-@@ -12493,7 +16299,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xxx11101x0xxxxxxxxxxxxxxxxxxxxxx
- str. */
-- return 866;
-+ return 892;
- }
- else
- {
-@@ -12501,7 +16307,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xxx11101x1xxxxxxxxxxxxxxxxxxxxxx
- ldr. */
-- return 867;
-+ return 893;
- }
- }
- }
-@@ -12528,7 +16334,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0x001110xx0xxxxxxxx000xxxxxxxxxx
- tbl. */
-- return 414;
-+ return 420;
- }
- else
- {
-@@ -12536,7 +16342,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0x001110xx0xxxxxxxx100xxxxxxxxxx
- tbx. */
-- return 415;
-+ return 421;
- }
- }
- else
-@@ -12549,7 +16355,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0x001110xx0xxxxxx0x010xxxxxxxxxx
- trn1. */
-- return 257;
-+ return 263;
- }
- else
- {
-@@ -12557,7 +16363,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0x001110xx0xxxxxx1x010xxxxxxxxxx
- trn2. */
-- return 260;
-+ return 266;
- }
- }
- else
-@@ -12570,7 +16376,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0x001110xx0xxxxxx00110xxxxxxxxxx
- uzp1. */
-- return 256;
-+ return 262;
- }
- else
- {
-@@ -12578,7 +16384,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0x001110xx0xxxxxx10110xxxxxxxxxx
- uzp2. */
-- return 259;
-+ return 265;
- }
- }
- else
-@@ -12589,7 +16395,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0x001110xx0xxxxxx01110xxxxxxxxxx
- zip1. */
-- return 258;
-+ return 264;
- }
- else
- {
-@@ -12597,7 +16403,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0x001110xx0xxxxxx11110xxxxxxxxxx
- zip2. */
-- return 261;
-+ return 267;
- }
- }
- }
-@@ -12617,7 +16423,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0x001110x00xxxxxxx0001xxxxxxxxxx
- dup. */
-- return 147;
-+ return 149;
- }
- else
- {
-@@ -12627,7 +16433,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0x001110010xxxxxxx0001xxxxxxxxxx
- fmaxnm. */
-- return 286;
-+ return 292;
- }
- else
- {
-@@ -12635,17 +16441,28 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0x001110110xxxxxxx0001xxxxxxxxxx
- fminnm. */
-- return 302;
-+ return 308;
- }
- }
- }
- else
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 0x001110xx0xxxxxxx1001xxxxxxxxxx
-- fcmeq. */
-- return 294;
-+ if (((word >> 15) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 0x001110xx0xxxxx0x1001xxxxxxxxxx
-+ fcmeq. */
-+ return 300;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 0x001110xx0xxxxx1x1001xxxxxxxxxx
-+ smmla. */
-+ return 2423;
-+ }
- }
- }
- else
-@@ -12660,7 +16477,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0x0011100x0xxxxx0x0101xxxxxxxxxx
- fadd. */
-- return 290;
-+ return 296;
- }
- else
- {
-@@ -12668,7 +16485,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0x0011101x0xxxxx0x0101xxxxxxxxxx
- fsub. */
-- return 306;
-+ return 312;
- }
- }
- else
-@@ -12677,7 +16494,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0x001110xx0xxxxx1x0101xxxxxxxxxx
- sdot. */
-- return 1988;
-+ return 2349;
- }
- }
- else
-@@ -12688,7 +16505,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0x0011100x0xxxxxxx1101xxxxxxxxxx
- fmax. */
-- return 296;
-+ return 302;
- }
- else
- {
-@@ -12696,7 +16513,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0x0011101x0xxxxxxx1101xxxxxxxxxx
- fmin. */
-- return 308;
-+ return 314;
- }
- }
- }
-@@ -12713,7 +16530,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0x001110x00xxxxxxx0011xxxxxxxxxx
- dup. */
-- return 148;
-+ return 150;
- }
- else
- {
-@@ -12723,7 +16540,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0x001110010xxxxxxx0011xxxxxxxxxx
- fmla. */
-- return 288;
-+ return 294;
- }
- else
- {
-@@ -12731,38 +16548,60 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0x001110110xxxxxxx0011xxxxxxxxxx
- fmls. */
-- return 304;
-+ return 310;
- }
- }
- }
- else
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 0x001110xx0xxxxxxx1011xxxxxxxxxx
-- smov. */
-- return 149;
-+ if (((word >> 15) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 0x001110xx0xxxxx0x1011xxxxxxxxxx
-+ smov. */
-+ return 151;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 0x001110xx0xxxxx1x1011xxxxxxxxxx
-+ usmmla. */
-+ return 2425;
-+ }
- }
- }
- else
- {
- if (((word >> 13) & 0x1) == 0)
- {
-- if (((word >> 22) & 0x1) == 0)
-+ if (((word >> 15) & 0x1) == 0)
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 0x001110x00xxxxxxx0111xxxxxxxxxx
-- ins. */
-- return 152;
-+ if (((word >> 22) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 0x001110x00xxxxx0x0111xxxxxxxxxx
-+ ins. */
-+ return 154;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 0x001110x10xxxxx0x0111xxxxxxxxxx
-+ fmulx. */
-+ return 298;
-+ }
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
-- 0x001110x10xxxxxxx0111xxxxxxxxxx
-- fmulx. */
-- return 292;
-+ 0x001110xx0xxxxx1x0111xxxxxxxxxx
-+ usdot. */
-+ return 2426;
- }
- }
- else
-@@ -12773,7 +16612,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0x001110x00xxxxxxx1111xxxxxxxxxx
- umov. */
-- return 150;
-+ return 152;
- }
- else
- {
-@@ -12783,7 +16622,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0x001110010xxxxxxx1111xxxxxxxxxx
- frecps. */
-- return 298;
-+ return 304;
- }
- else
- {
-@@ -12791,7 +16630,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0x001110110xxxxxxx1111xxxxxxxxxx
- frsqrts. */
-- return 310;
-+ return 316;
- }
- }
- }
-@@ -12809,7 +16648,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 1x001110000xxxxxxxxxxxxxxxxxxxxx
- eor3. */
-- return 1995;
-+ return 2356;
- }
- else
- {
-@@ -12817,7 +16656,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 1x001110100xxxxxxxxxxxxxxxxxxxxx
- xar. */
-- return 1997;
-+ return 2358;
- }
- }
- else
-@@ -12828,7 +16667,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 1x001110x10xxxxx0xxxxxxxxxxxxxxx
- sm3ss1. */
-- return 1999;
-+ return 2360;
- }
- else
- {
-@@ -12842,7 +16681,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 1x001110010xxxxx1xxx00xxxxxxxxxx
- sm3tt1a. */
-- return 2000;
-+ return 2361;
- }
- else
- {
-@@ -12850,7 +16689,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 1x001110110xxxxx1xxx00xxxxxxxxxx
- sha512su0. */
-- return 1993;
-+ return 2354;
- }
- }
- else
-@@ -12859,7 +16698,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 1x001110x10xxxxx1xxx10xxxxxxxxxx
- sm3tt2a. */
-- return 2002;
-+ return 2363;
- }
- }
- else
-@@ -12872,7 +16711,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 1x001110010xxxxx1xxx01xxxxxxxxxx
- sm3tt1b. */
-- return 2001;
-+ return 2362;
- }
- else
- {
-@@ -12880,7 +16719,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 1x001110110xxxxx1xxx01xxxxxxxxxx
- sm4e. */
-- return 2006;
-+ return 2367;
- }
- }
- else
-@@ -12889,7 +16728,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 1x001110x10xxxxx1xxx11xxxxxxxxxx
- sm3tt2b. */
-- return 2003;
-+ return 2364;
- }
- }
- }
-@@ -12904,7 +16743,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx101110xx0xxxxxxxxxx0xxxxxxxxxx
- ext. */
-- return 130;
-+ return 132;
- }
- else
- {
-@@ -12916,7 +16755,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx101110x00xxxxx0xxxx1xxxxxxxxxx
- ins. */
-- return 154;
-+ return 156;
- }
- else
- {
-@@ -12932,7 +16771,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx101110010xxxxx0x0001xxxxxxxxxx
- fmaxnmp. */
-- return 337;
-+ return 343;
- }
- else
- {
-@@ -12940,7 +16779,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx101110110xxxxx0x0001xxxxxxxxxx
- fminnmp. */
-- return 353;
-+ return 359;
- }
- }
- else
-@@ -12951,7 +16790,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx101110010xxxxx0x1001xxxxxxxxxx
- fcmge. */
-- return 343;
-+ return 349;
- }
- else
- {
-@@ -12959,7 +16798,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx101110110xxxxx0x1001xxxxxxxxxx
- fcmgt. */
-- return 357;
-+ return 363;
- }
- }
- }
-@@ -12973,7 +16812,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx101110010xxxxx0x0101xxxxxxxxxx
- faddp. */
-- return 339;
-+ return 345;
- }
- else
- {
-@@ -12981,7 +16820,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx101110110xxxxx0x0101xxxxxxxxxx
- fabd. */
-- return 355;
-+ return 361;
- }
- }
- else
-@@ -12992,7 +16831,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx101110010xxxxx0x1101xxxxxxxxxx
- fmaxp. */
-- return 347;
-+ return 353;
- }
- else
- {
-@@ -13000,7 +16839,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx101110110xxxxx0x1101xxxxxxxxxx
- fminp. */
-- return 361;
-+ return 367;
- }
- }
- }
-@@ -13015,7 +16854,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx101110010xxxxx0xx011xxxxxxxxxx
- facge. */
-- return 345;
-+ return 351;
- }
- else
- {
-@@ -13023,7 +16862,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx101110110xxxxx0xx011xxxxxxxxxx
- facgt. */
-- return 359;
-+ return 365;
- }
- }
- else
-@@ -13034,7 +16873,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx101110x10xxxxx0x0111xxxxxxxxxx
- fmul. */
-- return 341;
-+ return 347;
- }
- else
- {
-@@ -13042,7 +16881,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx101110x10xxxxx0x1111xxxxxxxxxx
- fdiv. */
-- return 349;
-+ return 355;
- }
- }
- }
-@@ -13062,7 +16901,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx101110xx0xxxxx100001xxxxxxxxxx
- sqrdmlah. */
-- return 364;
-+ return 370;
- }
- else
- {
-@@ -13070,7 +16909,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx101110xx0xxxxx100101xxxxxxxxxx
- udot. */
-- return 1987;
-+ return 2348;
- }
- }
- else
-@@ -13079,7 +16918,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx101110xx0xxxxx100x11xxxxxxxxxx
- sqrdmlsh. */
-- return 365;
-+ return 371;
- }
- }
- else
-@@ -13088,16 +16927,71 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx101110xx0xxxxx110xx1xxxxxxxxxx
- fcmla. */
-- return 366;
-+ return 372;
- }
- }
- else
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- xx101110xx0xxxxx1x1xx1xxxxxxxxxx
-- fcadd. */
-- return 367;
-+ if (((word >> 11) & 0x1) == 0)
-+ {
-+ if (((word >> 14) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ xx101110xx0xxxxx101x01xxxxxxxxxx
-+ ummla. */
-+ return 2424;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ xx101110xx0xxxxx111x01xxxxxxxxxx
-+ fcadd. */
-+ return 373;
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 12) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ xx101110xx0xxxxx1x1011xxxxxxxxxx
-+ bfmmla. */
-+ return 2440;
-+ }
-+ else
-+ {
-+ if (((word >> 23) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ xx1011100x0xxxxx1x1111xxxxxxxxxx
-+ bfdot. */
-+ return 2438;
-+ }
-+ else
-+ {
-+ if (((word >> 30) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ x01011101x0xxxxx1x1111xxxxxxxxxx
-+ bfmlalb. */
-+ return 2445;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ x11011101x0xxxxx1x1111xxxxxxxxxx
-+ bfmlalt. */
-+ return 2444;
-+ }
-+ }
-+ }
-+ }
- }
- }
- }
-@@ -13117,7 +17011,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x0011110xx0xxx00xxxxxxxxxxxxxxxx
- fcvtzs. */
-- return 752;
-+ return 764;
- }
- else
- {
-@@ -13125,7 +17019,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x0011110xx0xxx10xxxxxxxxxxxxxxxx
- scvtf. */
-- return 748;
-+ return 760;
- }
- }
- else
-@@ -13136,7 +17030,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x0011110xx0xxx01xxxxxxxxxxxxxxxx
- fcvtzu. */
-- return 754;
-+ return 766;
- }
- else
- {
-@@ -13144,7 +17038,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x0011110xx0xxx11xxxxxxxxxxxxxxxx
- ucvtf. */
-- return 750;
-+ return 762;
- }
- }
- }
-@@ -13162,7 +17056,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1011110xx0xxxxxx000x0xxxxxxxxxx
- sha1c. */
-- return 672;
-+ return 678;
- }
- else
- {
-@@ -13170,7 +17064,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1011110xx0xxxxxx100x0xxxxxxxxxx
- sha256h. */
-- return 676;
-+ return 682;
- }
- }
- else
-@@ -13181,7 +17075,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1011110xx0xxxxxx010x0xxxxxxxxxx
- sha1m. */
-- return 674;
-+ return 680;
- }
- else
- {
-@@ -13189,7 +17083,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1011110xx0xxxxxx110x0xxxxxxxxxx
- sha256su1. */
-- return 678;
-+ return 684;
- }
- }
- }
-@@ -13203,7 +17097,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1011110xx0xxxxxx001x0xxxxxxxxxx
- sha1p. */
-- return 673;
-+ return 679;
- }
- else
- {
-@@ -13211,7 +17105,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1011110xx0xxxxxx101x0xxxxxxxxxx
- sha256h2. */
-- return 677;
-+ return 683;
- }
- }
- else
-@@ -13220,7 +17114,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1011110xx0xxxxxxx11x0xxxxxxxxxx
- sha1su0. */
-- return 675;
-+ return 681;
- }
- }
- }
-@@ -13234,7 +17128,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1011110xx0xxxxxxx0x01xxxxxxxxxx
- dup. */
-- return 529;
-+ return 535;
- }
- else
- {
-@@ -13242,7 +17136,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1011110xx0xxxxxxx1x01xxxxxxxxxx
- fcmeq. */
-- return 550;
-+ return 556;
- }
- }
- else
-@@ -13253,7 +17147,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1011110xx0xxxxxxx0x11xxxxxxxxxx
- fmulx. */
-- return 548;
-+ return 554;
- }
- else
- {
-@@ -13263,7 +17157,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x10111100x0xxxxxxx1x11xxxxxxxxxx
- frecps. */
-- return 552;
-+ return 558;
- }
- else
- {
-@@ -13271,7 +17165,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x10111101x0xxxxxxx1x11xxxxxxxxxx
- frsqrts. */
-- return 554;
-+ return 560;
- }
- }
- }
-@@ -13290,7 +17184,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx111110xx0xxxxxxx000xxxxxxxxxxx
- sqrdmlah. */
-- return 582;
-+ return 588;
- }
- else
- {
-@@ -13300,7 +17194,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx1111100x0xxxxxxx100xxxxxxxxxxx
- fcmge. */
-- return 567;
-+ return 573;
- }
- else
- {
-@@ -13308,7 +17202,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx1111101x0xxxxxxx100xxxxxxxxxxx
- fcmgt. */
-- return 573;
-+ return 579;
- }
- }
- }
-@@ -13318,7 +17212,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx111110xx0xxxxxxxx10xxxxxxxxxxx
- fabd. */
-- return 571;
-+ return 577;
- }
- }
- else
-@@ -13329,7 +17223,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx111110xx0xxxxxxx0x1xxxxxxxxxxx
- sqrdmlsh. */
-- return 583;
-+ return 589;
- }
- else
- {
-@@ -13339,7 +17233,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx1111100x0xxxxxxx1x1xxxxxxxxxxx
- facge. */
-- return 569;
-+ return 575;
- }
- else
- {
-@@ -13347,7 +17241,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx1111101x0xxxxxxx1x1xxxxxxxxxxx
- facgt. */
-- return 575;
-+ return 581;
- }
- }
- }
-@@ -13380,7 +17274,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 00001110xx1xxxxx000000xxxxxxxxxx
- saddl. */
-- return 42;
-+ return 44;
- }
- else
- {
-@@ -13388,7 +17282,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 01001110xx1xxxxx000000xxxxxxxxxx
- saddl2. */
-- return 43;
-+ return 45;
- }
- }
- else
-@@ -13399,7 +17293,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 00001110xx1xxxxx010000xxxxxxxxxx
- addhn. */
-- return 50;
-+ return 52;
- }
- else
- {
-@@ -13407,7 +17301,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 01001110xx1xxxxx010000xxxxxxxxxx
- addhn2. */
-- return 51;
-+ return 53;
- }
- }
- }
-@@ -13421,7 +17315,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 00001110xx1xxxxx001000xxxxxxxxxx
- ssubl. */
-- return 46;
-+ return 48;
- }
- else
- {
-@@ -13429,7 +17323,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 01001110xx1xxxxx001000xxxxxxxxxx
- ssubl2. */
-- return 47;
-+ return 49;
- }
- }
- else
-@@ -13440,7 +17334,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 00001110xx1xxxxx011000xxxxxxxxxx
- subhn. */
-- return 54;
-+ return 56;
- }
- else
- {
-@@ -13448,7 +17342,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 01001110xx1xxxxx011000xxxxxxxxxx
- subhn2. */
-- return 55;
-+ return 57;
- }
- }
- }
-@@ -13465,7 +17359,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 00001110xx1xxxxx000100xxxxxxxxxx
- saddw. */
-- return 44;
-+ return 46;
- }
- else
- {
-@@ -13473,7 +17367,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 01001110xx1xxxxx000100xxxxxxxxxx
- saddw2. */
-- return 45;
-+ return 47;
- }
- }
- else
-@@ -13484,7 +17378,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 00001110xx1xxxxx010100xxxxxxxxxx
- sabal. */
-- return 52;
-+ return 54;
- }
- else
- {
-@@ -13492,7 +17386,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 01001110xx1xxxxx010100xxxxxxxxxx
- sabal2. */
-- return 53;
-+ return 55;
- }
- }
- }
-@@ -13506,7 +17400,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 00001110xx1xxxxx001100xxxxxxxxxx
- ssubw. */
-- return 48;
-+ return 50;
- }
- else
- {
-@@ -13514,7 +17408,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 01001110xx1xxxxx001100xxxxxxxxxx
- ssubw2. */
-- return 49;
-+ return 51;
- }
- }
- else
-@@ -13525,7 +17419,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 00001110xx1xxxxx011100xxxxxxxxxx
- sabdl. */
-- return 56;
-+ return 58;
- }
- else
- {
-@@ -13533,7 +17427,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 01001110xx1xxxxx011100xxxxxxxxxx
- sabdl2. */
-- return 57;
-+ return 59;
- }
- }
- }
-@@ -13551,7 +17445,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0x001110xx1xxxxx000010xxxxxxxxxx
- rev64. */
-- return 156;
-+ return 162;
- }
- else
- {
-@@ -13563,7 +17457,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0x001110xx1x0xx0010010xxxxxxxxxx
- cls. */
-- return 160;
-+ return 166;
- }
- else
- {
-@@ -13571,7 +17465,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0x001110xx1x1xx0010010xxxxxxxxxx
- aese. */
-- return 665;
-+ return 671;
- }
- }
- else
-@@ -13582,7 +17476,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 00001110xx1xxxx1010010xxxxxxxxxx
- sqxtn. */
-- return 170;
-+ return 176;
- }
- else
- {
-@@ -13590,7 +17484,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 01001110xx1xxxx1010010xxxxxxxxxx
- sqxtn2. */
-- return 171;
-+ return 177;
- }
- }
- }
-@@ -13605,7 +17499,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0x001110xx1xxxx0001010xxxxxxxxxx
- saddlp. */
-- return 158;
-+ return 164;
- }
- else
- {
-@@ -13615,7 +17509,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 00001110xx1xxxx1001010xxxxxxxxxx
- xtn. */
-- return 168;
-+ return 174;
- }
- else
- {
-@@ -13623,7 +17517,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 01001110xx1xxxx1001010xxxxxxxxxx
- xtn2. */
-- return 169;
-+ return 175;
- }
- }
- }
-@@ -13637,7 +17531,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0x001110xx1x0xx0011010xxxxxxxxxx
- sadalp. */
-- return 162;
-+ return 168;
- }
- else
- {
-@@ -13645,26 +17539,48 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0x001110xx1x1xx0011010xxxxxxxxxx
- aesmc. */
-- return 667;
-+ return 673;
- }
- }
- else
- {
-- if (((word >> 30) & 0x1) == 0)
-+ if (((word >> 23) & 0x1) == 0)
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 00001110xx1xxxx1011010xxxxxxxxxx
-- fcvtn. */
-- return 172;
-+ if (((word >> 30) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 000011100x1xxxx1011010xxxxxxxxxx
-+ fcvtn. */
-+ return 178;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010011100x1xxxx1011010xxxxxxxxxx
-+ fcvtn2. */
-+ return 179;
-+ }
- }
- else
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- 01001110xx1xxxx1011010xxxxxxxxxx
-- fcvtn2. */
-- return 173;
-+ if (((word >> 30) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 000011101x1xxxx1011010xxxxxxxxxx
-+ bfcvtn. */
-+ return 2441;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ 010011101x1xxxx1011010xxxxxxxxxx
-+ bfcvtn2. */
-+ return 2442;
-+ }
- }
- }
- }
-@@ -13680,7 +17596,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0x001110xx1xxxxx000110xxxxxxxxxx
- rev16. */
-- return 157;
-+ return 163;
- }
- else
- {
-@@ -13690,7 +17606,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0x001110xx1x0xxx010110xxxxxxxxxx
- cnt. */
-- return 161;
-+ return 167;
- }
- else
- {
-@@ -13698,7 +17614,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0x001110xx1x1xxx010110xxxxxxxxxx
- aesd. */
-- return 666;
-+ return 672;
- }
- }
- }
-@@ -13712,7 +17628,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0x001110xx10xxxx001110xxxxxxxxxx
- suqadd. */
-- return 159;
-+ return 165;
- }
- else
- {
-@@ -13720,7 +17636,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0x001110xx11xxxx001110xxxxxxxxxx
- saddlv. */
-- return 27;
-+ return 29;
- }
- }
- else
-@@ -13733,7 +17649,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0x001110xx1x0xx0011110xxxxxxxxxx
- sqabs. */
-- return 163;
-+ return 169;
- }
- else
- {
-@@ -13741,7 +17657,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0x001110xx1x1xx0011110xxxxxxxxxx
- aesimc. */
-- return 668;
-+ return 674;
- }
- }
- else
-@@ -13752,7 +17668,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 00001110xx1xxxx1011110xxxxxxxxxx
- fcvtl. */
-- return 174;
-+ return 180;
- }
- else
- {
-@@ -13760,7 +17676,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 01001110xx1xxxx1011110xxxxxxxxxx
- fcvtl2. */
-- return 175;
-+ return 181;
- }
- }
- }
-@@ -13782,7 +17698,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0x001110xx1xxxxx000001xxxxxxxxxx
- shadd. */
-- return 262;
-+ return 268;
- }
- else
- {
-@@ -13790,7 +17706,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0x001110xx1xxxxx010001xxxxxxxxxx
- sshl. */
-- return 269;
-+ return 275;
- }
- }
- else
-@@ -13801,7 +17717,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0x001110xx1xxxxx001001xxxxxxxxxx
- shsub. */
-- return 265;
-+ return 271;
- }
- else
- {
-@@ -13809,7 +17725,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0x001110xx1xxxxx011001xxxxxxxxxx
- smax. */
-- return 273;
-+ return 279;
- }
- }
- }
-@@ -13823,7 +17739,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0x001110xx1xxxxx000101xxxxxxxxxx
- srhadd. */
-- return 264;
-+ return 270;
- }
- else
- {
-@@ -13831,7 +17747,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0x001110xx1xxxxx010101xxxxxxxxxx
- srshl. */
-- return 271;
-+ return 277;
- }
- }
- else
-@@ -13842,7 +17758,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0x001110xx1xxxxx001101xxxxxxxxxx
- cmgt. */
-- return 267;
-+ return 273;
- }
- else
- {
-@@ -13850,7 +17766,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0x001110xx1xxxxx011101xxxxxxxxxx
- sabd. */
-- return 275;
-+ return 281;
- }
- }
- }
-@@ -13867,7 +17783,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0x001110xx1xxxxx000011xxxxxxxxxx
- sqadd. */
-- return 263;
-+ return 269;
- }
- else
- {
-@@ -13875,7 +17791,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0x001110xx1xxxxx010011xxxxxxxxxx
- sqshl. */
-- return 270;
-+ return 276;
- }
- }
- else
-@@ -13886,7 +17802,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0x001110xx1xxxxx001011xxxxxxxxxx
- sqsub. */
-- return 266;
-+ return 272;
- }
- else
- {
-@@ -13894,7 +17810,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0x001110xx1xxxxx011011xxxxxxxxxx
- smin. */
-- return 274;
-+ return 280;
- }
- }
- }
-@@ -13912,7 +17828,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0x001110001xxxxx000111xxxxxxxxxx
- and. */
-- return 299;
-+ return 305;
- }
- else
- {
-@@ -13920,7 +17836,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0x001110101xxxxx000111xxxxxxxxxx
- orr. */
-- return 311;
-+ return 317;
- }
- }
- else
-@@ -13931,7 +17847,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0x001110011xxxxx000111xxxxxxxxxx
- bic. */
-- return 300;
-+ return 306;
- }
- else
- {
-@@ -13939,7 +17855,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0x001110111xxxxx000111xxxxxxxxxx
- orn. */
-- return 313;
-+ return 319;
- }
- }
- }
-@@ -13949,7 +17865,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0x001110xx1xxxxx010111xxxxxxxxxx
- sqrshl. */
-- return 272;
-+ return 278;
- }
- }
- else
-@@ -13960,7 +17876,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0x001110xx1xxxxx001111xxxxxxxxxx
- cmge. */
-- return 268;
-+ return 274;
- }
- else
- {
-@@ -13968,7 +17884,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0x001110xx1xxxxx011111xxxxxxxxxx
- saba. */
-- return 276;
-+ return 282;
- }
- }
- }
-@@ -13981,7 +17897,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 1x001110xx1xxxxx0xxxxxxxxxxxxxxx
- bcax. */
-- return 1998;
-+ return 2359;
- }
- }
- else
-@@ -14002,7 +17918,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x0101110xx1xxxxx000000xxxxxxxxxx
- uaddl. */
-- return 74;
-+ return 76;
- }
- else
- {
-@@ -14010,7 +17926,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1101110xx1xxxxx000000xxxxxxxxxx
- uaddl2. */
-- return 75;
-+ return 77;
- }
- }
- else
-@@ -14021,7 +17937,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x0101110xx1xxxxx010000xxxxxxxxxx
- raddhn. */
-- return 82;
-+ return 84;
- }
- else
- {
-@@ -14029,7 +17945,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1101110xx1xxxxx010000xxxxxxxxxx
- raddhn2. */
-- return 83;
-+ return 85;
- }
- }
- }
-@@ -14043,7 +17959,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x0101110xx1xxxxx001000xxxxxxxxxx
- usubl. */
-- return 78;
-+ return 80;
- }
- else
- {
-@@ -14051,7 +17967,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1101110xx1xxxxx001000xxxxxxxxxx
- usubl2. */
-- return 79;
-+ return 81;
- }
- }
- else
-@@ -14062,7 +17978,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x0101110xx1xxxxx011000xxxxxxxxxx
- rsubhn. */
-- return 86;
-+ return 88;
- }
- else
- {
-@@ -14070,7 +17986,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1101110xx1xxxxx011000xxxxxxxxxx
- rsubhn2. */
-- return 87;
-+ return 89;
- }
- }
- }
-@@ -14087,7 +18003,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x0101110xx1xxxxx000100xxxxxxxxxx
- uaddw. */
-- return 76;
-+ return 78;
- }
- else
- {
-@@ -14095,7 +18011,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1101110xx1xxxxx000100xxxxxxxxxx
- uaddw2. */
-- return 77;
-+ return 79;
- }
- }
- else
-@@ -14106,7 +18022,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x0101110xx1xxxxx010100xxxxxxxxxx
- uabal. */
-- return 84;
-+ return 86;
- }
- else
- {
-@@ -14114,7 +18030,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1101110xx1xxxxx010100xxxxxxxxxx
- uabal2. */
-- return 85;
-+ return 87;
- }
- }
- }
-@@ -14128,7 +18044,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x0101110xx1xxxxx001100xxxxxxxxxx
- usubw. */
-- return 80;
-+ return 82;
- }
- else
- {
-@@ -14136,7 +18052,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1101110xx1xxxxx001100xxxxxxxxxx
- usubw2. */
-- return 81;
-+ return 83;
- }
- }
- else
-@@ -14147,7 +18063,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x0101110xx1xxxxx011100xxxxxxxxxx
- uabdl. */
-- return 88;
-+ return 90;
- }
- else
- {
-@@ -14155,7 +18071,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1101110xx1xxxxx011100xxxxxxxxxx
- uabdl2. */
-- return 89;
-+ return 91;
- }
- }
- }
-@@ -14173,7 +18089,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx101110xx1xxxxx000010xxxxxxxxxx
- rev32. */
-- return 207;
-+ return 213;
- }
- else
- {
-@@ -14183,7 +18099,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx101110xx1xxxx0010010xxxxxxxxxx
- clz. */
-- return 210;
-+ return 216;
- }
- else
- {
-@@ -14193,7 +18109,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x0101110xx1xxxx1010010xxxxxxxxxx
- uqxtn. */
-- return 220;
-+ return 226;
- }
- else
- {
-@@ -14201,7 +18117,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1101110xx1xxxx1010010xxxxxxxxxx
- uqxtn2. */
-- return 221;
-+ return 227;
- }
- }
- }
-@@ -14216,7 +18132,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx101110xx1xxxx0001010xxxxxxxxxx
- uaddlp. */
-- return 208;
-+ return 214;
- }
- else
- {
-@@ -14226,7 +18142,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x0101110xx1xxxx1001010xxxxxxxxxx
- sqxtun. */
-- return 216;
-+ return 222;
- }
- else
- {
-@@ -14234,7 +18150,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1101110xx1xxxx1001010xxxxxxxxxx
- sqxtun2. */
-- return 217;
-+ return 223;
- }
- }
- }
-@@ -14246,7 +18162,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx101110xx1xxxx0011010xxxxxxxxxx
- uadalp. */
-- return 211;
-+ return 217;
- }
- else
- {
-@@ -14256,7 +18172,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x0101110xx1xxxx1011010xxxxxxxxxx
- fcvtxn. */
-- return 222;
-+ return 228;
- }
- else
- {
-@@ -14264,7 +18180,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1101110xx1xxxx1011010xxxxxxxxxx
- fcvtxn2. */
-- return 223;
-+ return 229;
- }
- }
- }
-@@ -14280,7 +18196,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx101110x01xxxxx0x0110xxxxxxxxxx
- not. */
-- return 236;
-+ return 242;
- }
- else
- {
-@@ -14288,7 +18204,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx101110x11xxxxx0x0110xxxxxxxxxx
- rbit. */
-- return 238;
-+ return 244;
- }
- }
- else
-@@ -14303,7 +18219,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx101110xx10xxx0001110xxxxxxxxxx
- usqadd. */
-- return 209;
-+ return 215;
- }
- else
- {
-@@ -14311,7 +18227,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx101110xx11xxx0001110xxxxxxxxxx
- uaddlv. */
-- return 31;
-+ return 33;
- }
- }
- else
-@@ -14322,7 +18238,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x0101110xx1xxxx1001110xxxxxxxxxx
- shll. */
-- return 218;
-+ return 224;
- }
- else
- {
-@@ -14330,7 +18246,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1101110xx1xxxx1001110xxxxxxxxxx
- shll2. */
-- return 219;
-+ return 225;
- }
- }
- }
-@@ -14340,7 +18256,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx101110xx1xxxxx011110xxxxxxxxxx
- sqneg. */
-- return 212;
-+ return 218;
- }
- }
- }
-@@ -14360,7 +18276,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx101110xx1xxxxx000001xxxxxxxxxx
- uhadd. */
-- return 314;
-+ return 320;
- }
- else
- {
-@@ -14368,7 +18284,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx101110xx1xxxxx010001xxxxxxxxxx
- ushl. */
-- return 321;
-+ return 327;
- }
- }
- else
-@@ -14379,7 +18295,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx101110xx1xxxxx001001xxxxxxxxxx
- uhsub. */
-- return 317;
-+ return 323;
- }
- else
- {
-@@ -14387,7 +18303,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx101110xx1xxxxx011001xxxxxxxxxx
- umax. */
-- return 325;
-+ return 331;
- }
- }
- }
-@@ -14401,7 +18317,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx101110xx1xxxxx000101xxxxxxxxxx
- urhadd. */
-- return 316;
-+ return 322;
- }
- else
- {
-@@ -14409,7 +18325,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx101110xx1xxxxx010101xxxxxxxxxx
- urshl. */
-- return 323;
-+ return 329;
- }
- }
- else
-@@ -14420,7 +18336,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx101110xx1xxxxx001101xxxxxxxxxx
- cmhi. */
-- return 319;
-+ return 325;
- }
- else
- {
-@@ -14428,7 +18344,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx101110xx1xxxxx011101xxxxxxxxxx
- uabd. */
-- return 327;
-+ return 333;
- }
- }
- }
-@@ -14445,7 +18361,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx101110xx1xxxxx000011xxxxxxxxxx
- uqadd. */
-- return 315;
-+ return 321;
- }
- else
- {
-@@ -14453,7 +18369,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx101110xx1xxxxx010011xxxxxxxxxx
- uqshl. */
-- return 322;
-+ return 328;
- }
- }
- else
-@@ -14464,7 +18380,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx101110xx1xxxxx001011xxxxxxxxxx
- uqsub. */
-- return 318;
-+ return 324;
- }
- else
- {
-@@ -14472,7 +18388,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx101110xx1xxxxx011011xxxxxxxxxx
- umin. */
-- return 326;
-+ return 332;
- }
- }
- }
-@@ -14490,7 +18406,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx101110001xxxxx000111xxxxxxxxxx
- eor. */
-- return 350;
-+ return 356;
- }
- else
- {
-@@ -14498,7 +18414,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx101110101xxxxx000111xxxxxxxxxx
- bit. */
-- return 362;
-+ return 368;
- }
- }
- else
-@@ -14509,7 +18425,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx101110011xxxxx000111xxxxxxxxxx
- bsl. */
-- return 351;
-+ return 357;
- }
- else
- {
-@@ -14517,7 +18433,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx101110111xxxxx000111xxxxxxxxxx
- bif. */
-- return 363;
-+ return 369;
- }
- }
- }
-@@ -14527,7 +18443,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx101110xx1xxxxx010111xxxxxxxxxx
- uqrshl. */
-- return 324;
-+ return 330;
- }
- }
- else
-@@ -14538,7 +18454,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx101110xx1xxxxx001111xxxxxxxxxx
- cmhs. */
-- return 320;
-+ return 326;
- }
- else
- {
-@@ -14546,7 +18462,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx101110xx1xxxxx011111xxxxxxxxxx
- uaba. */
-- return 328;
-+ return 334;
- }
- }
- }
-@@ -14574,7 +18490,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x0001110xx1xxxxx100000xxxxxxxxxx
- smlal. */
-- return 58;
-+ return 60;
- }
- else
- {
-@@ -14584,7 +18500,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 01001110xx1xxxxx100000xxxxxxxxxx
- smlal2. */
-- return 59;
-+ return 61;
- }
- else
- {
-@@ -14592,7 +18508,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 11001110xx1xxxxx100000xxxxxxxxxx
- sha512h. */
-- return 1991;
-+ return 2352;
- }
- }
- }
-@@ -14604,7 +18520,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x0101110xx1xxxxx100000xxxxxxxxxx
- umlal. */
-- return 90;
-+ return 92;
- }
- else
- {
-@@ -14612,7 +18528,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1101110xx1xxxxx100000xxxxxxxxxx
- umlal2. */
-- return 91;
-+ return 93;
- }
- }
- }
-@@ -14626,7 +18542,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x0001110xx1xxxxx110000xxxxxxxxxx
- smull. */
-- return 66;
-+ return 68;
- }
- else
- {
-@@ -14636,7 +18552,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 01001110xx1xxxxx110000xxxxxxxxxx
- smull2. */
-- return 67;
-+ return 69;
- }
- else
- {
-@@ -14644,7 +18560,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 11001110xx1xxxxx110000xxxxxxxxxx
- sm3partw1. */
-- return 2004;
-+ return 2365;
- }
- }
- }
-@@ -14656,7 +18572,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x0101110xx1xxxxx110000xxxxxxxxxx
- umull. */
-- return 94;
-+ return 96;
- }
- else
- {
-@@ -14664,7 +18580,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1101110xx1xxxxx110000xxxxxxxxxx
- umull2. */
-- return 95;
-+ return 97;
- }
- }
- }
-@@ -14681,7 +18597,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x0001110xx1xxxxx101000xxxxxxxxxx
- smlsl. */
-- return 62;
-+ return 64;
- }
- else
- {
-@@ -14689,7 +18605,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1001110xx1xxxxx101000xxxxxxxxxx
- smlsl2. */
-- return 63;
-+ return 65;
- }
- }
- else
-@@ -14700,7 +18616,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x0101110xx1xxxxx101000xxxxxxxxxx
- umlsl. */
-- return 92;
-+ return 94;
- }
- else
- {
-@@ -14708,7 +18624,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1101110xx1xxxxx101000xxxxxxxxxx
- umlsl2. */
-- return 93;
-+ return 95;
- }
- }
- }
-@@ -14722,7 +18638,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x0x01110x01xxxxx111000xxxxxxxxxx
- pmull. */
-- return 70;
-+ return 72;
- }
- else
- {
-@@ -14730,7 +18646,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1x01110x01xxxxx111000xxxxxxxxxx
- pmull2. */
-- return 72;
-+ return 74;
- }
- }
- else
-@@ -14741,7 +18657,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x0x01110x11xxxxx111000xxxxxxxxxx
- pmull. */
-- return 71;
-+ return 73;
- }
- else
- {
-@@ -14749,7 +18665,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1x01110x11xxxxx111000xxxxxxxxxx
- pmull2. */
-- return 73;
-+ return 75;
- }
- }
- }
-@@ -14767,7 +18683,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x0x01110xx1xxxxx100100xxxxxxxxxx
- sqdmlal. */
-- return 60;
-+ return 62;
- }
- else
- {
-@@ -14775,7 +18691,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1x01110xx1xxxxx100100xxxxxxxxxx
- sqdmlal2. */
-- return 61;
-+ return 63;
- }
- }
- else
-@@ -14786,7 +18702,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x0x01110xx1xxxxx110100xxxxxxxxxx
- sqdmull. */
-- return 68;
-+ return 70;
- }
- else
- {
-@@ -14794,7 +18710,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1x01110xx1xxxxx110100xxxxxxxxxx
- sqdmull2. */
-- return 69;
-+ return 71;
- }
- }
- }
-@@ -14806,7 +18722,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x0x01110xx1xxxxx1x1100xxxxxxxxxx
- sqdmlsl. */
-- return 64;
-+ return 66;
- }
- else
- {
-@@ -14814,7 +18730,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1x01110xx1xxxxx1x1100xxxxxxxxxx
- sqdmlsl2. */
-- return 65;
-+ return 67;
- }
- }
- }
-@@ -14837,7 +18753,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0x001110xx1xxxx0100010xxxxxxxxxx
- cmgt. */
-- return 164;
-+ return 170;
- }
- else
- {
-@@ -14849,7 +18765,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0x0011100x1x0xx1100010xxxxxxxxxx
- frintn. */
-- return 176;
-+ return 182;
- }
- else
- {
-@@ -14857,7 +18773,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0x0011101x1x0xx1100010xxxxxxxxxx
- frintp. */
-- return 196;
-+ return 202;
- }
- }
- else
-@@ -14868,7 +18784,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0x0011100x1x1xx1100010xxxxxxxxxx
- frintn. */
-- return 177;
-+ return 183;
- }
- else
- {
-@@ -14876,7 +18792,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0x0011101x1x1xx1100010xxxxxxxxxx
- frintp. */
-- return 197;
-+ return 203;
- }
- }
- }
-@@ -14887,7 +18803,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 1x001110xx1xxxxx100010xxxxxxxxxx
- sha512su1. */
-- return 1994;
-+ return 2355;
- }
- }
- else
-@@ -14898,7 +18814,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx101110xx1xxxx0100010xxxxxxxxxx
- cmge. */
-- return 213;
-+ return 219;
- }
- else
- {
-@@ -14908,7 +18824,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx101110xx1x0xx1100010xxxxxxxxxx
- frinta. */
-- return 224;
-+ return 230;
- }
- else
- {
-@@ -14916,7 +18832,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx101110xx1x1xx1100010xxxxxxxxxx
- frinta. */
-- return 225;
-+ return 231;
- }
- }
- }
-@@ -14935,7 +18851,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0x0011100x1xxxx0110010xxxxxxxxxx
- fmaxnmv. */
-- return 35;
-+ return 37;
- }
- else
- {
-@@ -14945,7 +18861,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0x0011100x1x0xx1110010xxxxxxxxxx
- fcvtas. */
-- return 184;
-+ return 190;
- }
- else
- {
-@@ -14953,7 +18869,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0x0011100x1x1xx1110010xxxxxxxxxx
- fcvtas. */
-- return 185;
-+ return 191;
- }
- }
- }
-@@ -14963,7 +18879,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 1x0011100x1xxxxx110010xxxxxxxxxx
- sm4ekey. */
-- return 2007;
-+ return 2368;
- }
- }
- else
-@@ -14974,7 +18890,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx1011100x1xxxx0110010xxxxxxxxxx
- fmaxnmv. */
-- return 34;
-+ return 36;
- }
- else
- {
-@@ -14984,7 +18900,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx1011100x1x0xx1110010xxxxxxxxxx
- fcvtau. */
-- return 232;
-+ return 238;
- }
- else
- {
-@@ -14992,7 +18908,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx1011100x1x1xx1110010xxxxxxxxxx
- fcvtau. */
-- return 233;
-+ return 239;
- }
- }
- }
-@@ -15011,7 +18927,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx0011101x100xx0110010xxxxxxxxxx
- fcmgt. */
-- return 188;
-+ return 194;
- }
- else
- {
-@@ -15019,7 +18935,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx1011101x100xx0110010xxxxxxxxxx
- fcmge. */
-- return 239;
-+ return 245;
- }
- }
- else
-@@ -15030,7 +18946,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx0011101x110xx0110010xxxxxxxxxx
- fminnmv. */
-- return 39;
-+ return 41;
- }
- else
- {
-@@ -15038,7 +18954,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx1011101x110xx0110010xxxxxxxxxx
- fminnmv. */
-- return 38;
-+ return 40;
- }
- }
- }
-@@ -15050,7 +18966,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx0011101x1x1xx0110010xxxxxxxxxx
- fcmgt. */
-- return 189;
-+ return 195;
- }
- else
- {
-@@ -15058,7 +18974,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx1011101x1x1xx0110010xxxxxxxxxx
- fcmge. */
-- return 240;
-+ return 246;
- }
- }
- }
-@@ -15070,7 +18986,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx0011101x1xxxx1110010xxxxxxxxxx
- urecpe. */
-- return 204;
-+ return 210;
- }
- else
- {
-@@ -15078,7 +18994,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx1011101x1xxxx1110010xxxxxxxxxx
- ursqrte. */
-- return 251;
-+ return 257;
- }
- }
- }
-@@ -15096,7 +19012,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xxx01110xx10xxx0101010xxxxxxxxxx
- cmlt. */
-- return 166;
-+ return 172;
- }
- else
- {
-@@ -15106,7 +19022,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx001110xx11xxx0101010xxxxxxxxxx
- smaxv. */
-- return 28;
-+ return 30;
- }
- else
- {
-@@ -15114,7 +19030,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx101110xx11xxx0101010xxxxxxxxxx
- umaxv. */
-- return 32;
-+ return 34;
- }
- }
- }
-@@ -15132,7 +19048,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx0011100x100xx1101010xxxxxxxxxx
- fcvtns. */
-- return 180;
-+ return 186;
- }
- else
- {
-@@ -15140,7 +19056,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx1011100x100xx1101010xxxxxxxxxx
- fcvtnu. */
-- return 228;
-+ return 234;
- }
- }
- else
-@@ -15151,7 +19067,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx0011101x100xx1101010xxxxxxxxxx
- fcvtps. */
-- return 200;
-+ return 206;
- }
- else
- {
-@@ -15159,7 +19075,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx1011101x100xx1101010xxxxxxxxxx
- fcvtpu. */
-- return 247;
-+ return 253;
- }
- }
- }
-@@ -15171,7 +19087,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx001110xx110xx1101010xxxxxxxxxx
- sminv. */
-- return 29;
-+ return 31;
- }
- else
- {
-@@ -15179,7 +19095,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx101110xx110xx1101010xxxxxxxxxx
- uminv. */
-- return 33;
-+ return 35;
- }
- }
- }
-@@ -15193,7 +19109,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx0011100x1x1xx1101010xxxxxxxxxx
- fcvtns. */
-- return 181;
-+ return 187;
- }
- else
- {
-@@ -15201,7 +19117,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx1011100x1x1xx1101010xxxxxxxxxx
- fcvtnu. */
-- return 229;
-+ return 235;
- }
- }
- else
-@@ -15212,7 +19128,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx0011101x1x1xx1101010xxxxxxxxxx
- fcvtps. */
-- return 201;
-+ return 207;
- }
- else
- {
-@@ -15220,7 +19136,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx1011101x1x1xx1101010xxxxxxxxxx
- fcvtpu. */
-- return 248;
-+ return 254;
- }
- }
- }
-@@ -15228,21 +19144,43 @@ aarch64_opcode_lookup_1 (uint32_t word)
- }
- else
- {
-- if (((word >> 19) & 0x1) == 0)
-+ if (((word >> 16) & 0x1) == 0)
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- xxx01110xx1x0xxx111010xxxxxxxxxx
-- fcmlt. */
-- return 192;
-+ if (((word >> 19) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ xxx01110xx1x0xx0111010xxxxxxxxxx
-+ fcmlt. */
-+ return 198;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ xxx01110xx1x1xx0111010xxxxxxxxxx
-+ fcmlt. */
-+ return 199;
-+ }
- }
- else
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- xxx01110xx1x1xxx111010xxxxxxxxxx
-- fcmlt. */
-- return 193;
-+ if (((word >> 29) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ xx001110xx1xxxx1111010xxxxxxxxxx
-+ frint32z. */
-+ return 158;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ xx101110xx1xxxx1111010xxxxxxxxxx
-+ frint32x. */
-+ return 159;
-+ }
- }
- }
- }
-@@ -15261,7 +19199,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx001110xx1xxxx0100110xxxxxxxxxx
- cmeq. */
-- return 165;
-+ return 171;
- }
- else
- {
-@@ -15269,7 +19207,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx101110xx1xxxx0100110xxxxxxxxxx
- cmle. */
-- return 214;
-+ return 220;
- }
- }
- else
-@@ -15284,7 +19222,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx0011100x1x0xx1100110xxxxxxxxxx
- frintm. */
-- return 178;
-+ return 184;
- }
- else
- {
-@@ -15292,7 +19230,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx1011100x1x0xx1100110xxxxxxxxxx
- frintx. */
-- return 226;
-+ return 232;
- }
- }
- else
-@@ -15303,7 +19241,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx0011101x1x0xx1100110xxxxxxxxxx
- frintz. */
-- return 198;
-+ return 204;
- }
- else
- {
-@@ -15311,7 +19249,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx1011101x1x0xx1100110xxxxxxxxxx
- frinti. */
-- return 245;
-+ return 251;
- }
- }
- }
-@@ -15325,7 +19263,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx0011100x1x1xx1100110xxxxxxxxxx
- frintm. */
-- return 179;
-+ return 185;
- }
- else
- {
-@@ -15333,7 +19271,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx1011100x1x1xx1100110xxxxxxxxxx
- frintx. */
-- return 227;
-+ return 233;
- }
- }
- else
-@@ -15344,7 +19282,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx0011101x1x1xx1100110xxxxxxxxxx
- frintz. */
-- return 199;
-+ return 205;
- }
- else
- {
-@@ -15352,7 +19290,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx1011101x1x1xx1100110xxxxxxxxxx
- frinti. */
-- return 246;
-+ return 252;
- }
- }
- }
-@@ -15370,7 +19308,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx001110xx1x0xx0110110xxxxxxxxxx
- fcmeq. */
-- return 190;
-+ return 196;
- }
- else
- {
-@@ -15378,7 +19316,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx101110xx1x0xx0110110xxxxxxxxxx
- fcmle. */
-- return 241;
-+ return 247;
- }
- }
- else
-@@ -15389,7 +19327,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx001110xx1x1xx0110110xxxxxxxxxx
- fcmeq. */
-- return 191;
-+ return 197;
- }
- else
- {
-@@ -15397,7 +19335,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx101110xx1x1xx0110110xxxxxxxxxx
- fcmle. */
-- return 242;
-+ return 248;
- }
- }
- }
-@@ -15413,7 +19351,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx0011100x1x0xx1110110xxxxxxxxxx
- scvtf. */
-- return 186;
-+ return 192;
- }
- else
- {
-@@ -15421,7 +19359,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx1011100x1x0xx1110110xxxxxxxxxx
- ucvtf. */
-- return 234;
-+ return 240;
- }
- }
- else
-@@ -15432,7 +19370,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx0011101x1x0xx1110110xxxxxxxxxx
- frecpe. */
-- return 205;
-+ return 211;
- }
- else
- {
-@@ -15440,7 +19378,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx1011101x1x0xx1110110xxxxxxxxxx
- frsqrte. */
-- return 252;
-+ return 258;
- }
- }
- }
-@@ -15454,7 +19392,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx0011100x1x1xx1110110xxxxxxxxxx
- scvtf. */
-- return 187;
-+ return 193;
- }
- else
- {
-@@ -15462,7 +19400,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx1011100x1x1xx1110110xxxxxxxxxx
- ucvtf. */
-- return 235;
-+ return 241;
- }
- }
- else
-@@ -15473,7 +19411,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx0011101x1x1xx1110110xxxxxxxxxx
- frecpe. */
-- return 206;
-+ return 212;
- }
- else
- {
-@@ -15481,7 +19419,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx1011101x1x1xx1110110xxxxxxxxxx
- frsqrte. */
-- return 253;
-+ return 259;
- }
- }
- }
-@@ -15500,7 +19438,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx001110xx1xxxx0101110xxxxxxxxxx
- abs. */
-- return 167;
-+ return 173;
- }
- else
- {
-@@ -15508,7 +19446,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx101110xx1xxxx0101110xxxxxxxxxx
- neg. */
-- return 215;
-+ return 221;
- }
- }
- else
-@@ -15525,7 +19463,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx0011100x100xx1101110xxxxxxxxxx
- fcvtms. */
-- return 182;
-+ return 188;
- }
- else
- {
-@@ -15533,7 +19471,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx1011100x100xx1101110xxxxxxxxxx
- fcvtmu. */
-- return 230;
-+ return 236;
- }
- }
- else
-@@ -15544,7 +19482,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx0011101x100xx1101110xxxxxxxxxx
- fcvtzs. */
-- return 202;
-+ return 208;
- }
- else
- {
-@@ -15552,7 +19490,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx1011101x100xx1101110xxxxxxxxxx
- fcvtzu. */
-- return 249;
-+ return 255;
- }
- }
- }
-@@ -15562,7 +19500,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xxx01110xx110xx1101110xxxxxxxxxx
- addv. */
-- return 30;
-+ return 32;
- }
- }
- else
-@@ -15575,7 +19513,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx0011100x1x1xx1101110xxxxxxxxxx
- fcvtms. */
-- return 183;
-+ return 189;
- }
- else
- {
-@@ -15583,7 +19521,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx1011100x1x1xx1101110xxxxxxxxxx
- fcvtmu. */
-- return 231;
-+ return 237;
- }
- }
- else
-@@ -15594,7 +19532,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx0011101x1x1xx1101110xxxxxxxxxx
- fcvtzs. */
-- return 203;
-+ return 209;
- }
- else
- {
-@@ -15602,7 +19540,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx1011101x1x1xx1101110xxxxxxxxxx
- fcvtzu. */
-- return 250;
-+ return 256;
- }
- }
- }
-@@ -15622,7 +19560,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx001110xx100xx0111110xxxxxxxxxx
- fabs. */
-- return 194;
-+ return 200;
- }
- else
- {
-@@ -15630,7 +19568,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx101110xx100xx0111110xxxxxxxxxx
- fneg. */
-- return 243;
-+ return 249;
- }
- }
- else
-@@ -15643,7 +19581,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx0011100x110xx0111110xxxxxxxxxx
- fmaxv. */
-- return 37;
-+ return 39;
- }
- else
- {
-@@ -15651,7 +19589,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx1011100x110xx0111110xxxxxxxxxx
- fmaxv. */
-- return 36;
-+ return 38;
- }
- }
- else
-@@ -15662,7 +19600,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx0011101x110xx0111110xxxxxxxxxx
- fminv. */
-- return 41;
-+ return 43;
- }
- else
- {
-@@ -15670,7 +19608,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx1011101x110xx0111110xxxxxxxxxx
- fminv. */
-- return 40;
-+ return 42;
- }
- }
- }
-@@ -15683,7 +19621,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx001110xx1x1xx0111110xxxxxxxxxx
- fabs. */
-- return 195;
-+ return 201;
- }
- else
- {
-@@ -15691,7 +19629,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx101110xx1x1xx0111110xxxxxxxxxx
- fneg. */
-- return 244;
-+ return 250;
- }
- }
- }
-@@ -15699,11 +19637,33 @@ aarch64_opcode_lookup_1 (uint32_t word)
- {
- if (((word >> 19) & 0x1) == 0)
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- xxx01110xx1x0xx1111110xxxxxxxxxx
-- fsqrt. */
-- return 254;
-+ if (((word >> 23) & 0x1) == 0)
-+ {
-+ if (((word >> 29) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ xx0011100x1x0xx1111110xxxxxxxxxx
-+ frint64z. */
-+ return 160;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ xx1011100x1x0xx1111110xxxxxxxxxx
-+ frint64x. */
-+ return 161;
-+ }
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ xxx011101x1x0xx1111110xxxxxxxxxx
-+ fsqrt. */
-+ return 260;
-+ }
- }
- else
- {
-@@ -15711,7 +19671,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xxx01110xx1x1xx1111110xxxxxxxxxx
- fsqrt. */
-- return 255;
-+ return 261;
- }
- }
- }
-@@ -15737,7 +19697,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0x001110xx1xxxxx100001xxxxxxxxxx
- add. */
-- return 277;
-+ return 283;
- }
- else
- {
-@@ -15745,7 +19705,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 1x001110xx1xxxxx100001xxxxxxxxxx
- sha512h2. */
-- return 1992;
-+ return 2353;
- }
- }
- else
-@@ -15754,7 +19714,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx101110xx1xxxxx100001xxxxxxxxxx
- sub. */
-- return 329;
-+ return 335;
- }
- }
- else
-@@ -15769,7 +19729,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0x0011100x1xxxxx110001xxxxxxxxxx
- fmaxnm. */
-- return 285;
-+ return 291;
- }
- else
- {
-@@ -15777,7 +19737,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 1x0011100x1xxxxx110001xxxxxxxxxx
- sm3partw2. */
-- return 2005;
-+ return 2366;
- }
- }
- else
-@@ -15786,7 +19746,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx1011100x1xxxxx110001xxxxxxxxxx
- fmaxnmp. */
-- return 336;
-+ return 342;
- }
- }
- else
-@@ -15797,7 +19757,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx0011101x1xxxxx110001xxxxxxxxxx
- fminnm. */
-- return 301;
-+ return 307;
- }
- else
- {
-@@ -15805,7 +19765,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx1011101x1xxxxx110001xxxxxxxxxx
- fminnmp. */
-- return 352;
-+ return 358;
- }
- }
- }
-@@ -15820,7 +19780,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx001110xx1xxxxx101001xxxxxxxxxx
- smaxp. */
-- return 281;
-+ return 287;
- }
- else
- {
-@@ -15828,7 +19788,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx101110xx1xxxxx101001xxxxxxxxxx
- umaxp. */
-- return 333;
-+ return 339;
- }
- }
- else
-@@ -15841,7 +19801,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx0011100x1xxxxx111001xxxxxxxxxx
- fcmeq. */
-- return 293;
-+ return 299;
- }
- else
- {
-@@ -15849,7 +19809,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx1011100x1xxxxx111001xxxxxxxxxx
- fcmge. */
-- return 342;
-+ return 348;
- }
- }
- else
-@@ -15858,7 +19818,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xxx011101x1xxxxx111001xxxxxxxxxx
- fcmgt. */
-- return 356;
-+ return 362;
- }
- }
- }
-@@ -15875,7 +19835,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx001110xx1xxxxx100101xxxxxxxxxx
- mla. */
-- return 279;
-+ return 285;
- }
- else
- {
-@@ -15883,7 +19843,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx101110xx1xxxxx100101xxxxxxxxxx
- mls. */
-- return 331;
-+ return 337;
- }
- }
- else
-@@ -15896,7 +19856,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx0011100x1xxxxx110101xxxxxxxxxx
- fadd. */
-- return 289;
-+ return 295;
- }
- else
- {
-@@ -15904,7 +19864,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx1011100x1xxxxx110101xxxxxxxxxx
- faddp. */
-- return 338;
-+ return 344;
- }
- }
- else
-@@ -15915,7 +19875,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx0011101x1xxxxx110101xxxxxxxxxx
- fsub. */
-- return 305;
-+ return 311;
- }
- else
- {
-@@ -15923,7 +19883,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx1011101x1xxxxx110101xxxxxxxxxx
- fabd. */
-- return 354;
-+ return 360;
- }
- }
- }
-@@ -15938,7 +19898,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx001110xx1xxxxx101101xxxxxxxxxx
- sqdmulh. */
-- return 283;
-+ return 289;
- }
- else
- {
-@@ -15946,7 +19906,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx101110xx1xxxxx101101xxxxxxxxxx
- sqrdmulh. */
-- return 335;
-+ return 341;
- }
- }
- else
-@@ -15959,7 +19919,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx0011100x1xxxxx111101xxxxxxxxxx
- fmax. */
-- return 295;
-+ return 301;
- }
- else
- {
-@@ -15967,7 +19927,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx1011100x1xxxxx111101xxxxxxxxxx
- fmaxp. */
-- return 346;
-+ return 352;
- }
- }
- else
-@@ -15978,7 +19938,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx0011101x1xxxxx111101xxxxxxxxxx
- fmin. */
-- return 307;
-+ return 313;
- }
- else
- {
-@@ -15986,7 +19946,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx1011101x1xxxxx111101xxxxxxxxxx
- fminp. */
-- return 360;
-+ return 366;
- }
- }
- }
-@@ -16009,7 +19969,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 0x001110xx1xxxxx100011xxxxxxxxxx
- cmtst. */
-- return 278;
-+ return 284;
- }
- else
- {
-@@ -16017,7 +19977,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- 1x001110xx1xxxxx100011xxxxxxxxxx
- rax1. */
-- return 1996;
-+ return 2357;
- }
- }
- else
-@@ -16026,7 +19986,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx101110xx1xxxxx100011xxxxxxxxxx
- cmeq. */
-- return 330;
-+ return 336;
- }
- }
- else
-@@ -16039,7 +19999,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx0011100x1xxxxx110011xxxxxxxxxx
- fmla. */
-- return 287;
-+ return 293;
- }
- else
- {
-@@ -16049,7 +20009,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x01011100x1xxxxx110011xxxxxxxxxx
- fmlal2. */
-- return 2010;
-+ return 2371;
- }
- else
- {
-@@ -16057,7 +20017,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x11011100x1xxxxx110011xxxxxxxxxx
- fmlal2. */
-- return 2014;
-+ return 2375;
- }
- }
- }
-@@ -16069,7 +20029,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx0011101x1xxxxx110011xxxxxxxxxx
- fmls. */
-- return 303;
-+ return 309;
- }
- else
- {
-@@ -16079,7 +20039,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x01011101x1xxxxx110011xxxxxxxxxx
- fmlsl2. */
-- return 2011;
-+ return 2372;
- }
- else
- {
-@@ -16087,7 +20047,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x11011101x1xxxxx110011xxxxxxxxxx
- fmlsl2. */
-- return 2015;
-+ return 2376;
- }
- }
- }
-@@ -16103,7 +20063,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx001110xx1xxxxx101011xxxxxxxxxx
- sminp. */
-- return 282;
-+ return 288;
- }
- else
- {
-@@ -16111,7 +20071,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx101110xx1xxxxx101011xxxxxxxxxx
- uminp. */
-- return 334;
-+ return 340;
- }
- }
- else
-@@ -16126,7 +20086,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x00011100x1xxxxx111011xxxxxxxxxx
- fmlal. */
-- return 2008;
-+ return 2369;
- }
- else
- {
-@@ -16134,7 +20094,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x10011100x1xxxxx111011xxxxxxxxxx
- fmlal. */
-- return 2012;
-+ return 2373;
- }
- }
- else
-@@ -16143,7 +20103,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx1011100x1xxxxx111011xxxxxxxxxx
- facge. */
-- return 344;
-+ return 350;
- }
- }
- else
-@@ -16156,7 +20116,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x00011101x1xxxxx111011xxxxxxxxxx
- fmlsl. */
-- return 2009;
-+ return 2370;
- }
- else
- {
-@@ -16164,7 +20124,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x10011101x1xxxxx111011xxxxxxxxxx
- fmlsl. */
-- return 2013;
-+ return 2374;
- }
- }
- else
-@@ -16173,7 +20133,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx1011101x1xxxxx111011xxxxxxxxxx
- facgt. */
-- return 358;
-+ return 364;
- }
- }
- }
-@@ -16191,7 +20151,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx001110xx1xxxxx100111xxxxxxxxxx
- mul. */
-- return 280;
-+ return 286;
- }
- else
- {
-@@ -16199,7 +20159,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx101110xx1xxxxx100111xxxxxxxxxx
- pmul. */
-- return 332;
-+ return 338;
- }
- }
- else
-@@ -16210,7 +20170,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx001110xx1xxxxx110111xxxxxxxxxx
- fmulx. */
-- return 291;
-+ return 297;
- }
- else
- {
-@@ -16218,7 +20178,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx101110xx1xxxxx110111xxxxxxxxxx
- fmul. */
-- return 340;
-+ return 346;
- }
- }
- }
-@@ -16230,7 +20190,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xxx01110xx1xxxxx101111xxxxxxxxxx
- addp. */
-- return 284;
-+ return 290;
- }
- else
- {
-@@ -16242,7 +20202,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx0011100x1xxxxx111111xxxxxxxxxx
- frecps. */
-- return 297;
-+ return 303;
- }
- else
- {
-@@ -16250,7 +20210,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx1011100x1xxxxx111111xxxxxxxxxx
- fdiv. */
-- return 348;
-+ return 354;
- }
- }
- else
-@@ -16259,7 +20219,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xxx011101x1xxxxx111111xxxxxxxxxx
- frsqrts. */
-- return 309;
-+ return 315;
- }
- }
- }
-@@ -16294,7 +20254,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xxx11110xx100000x00000xxxxxxxxxx
- fcvtns. */
-- return 756;
-+ return 768;
- }
- else
- {
-@@ -16302,7 +20262,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xxx11110xx110000x00000xxxxxxxxxx
- fcvtms. */
-- return 776;
-+ return 788;
- }
- }
- else
-@@ -16313,7 +20273,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xxx11110xx101000x00000xxxxxxxxxx
- fcvtps. */
-- return 772;
-+ return 784;
- }
- else
- {
-@@ -16321,7 +20281,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xxx11110xx111000x00000xxxxxxxxxx
- fcvtzs. */
-- return 780;
-+ return 792;
- }
- }
- }
-@@ -16331,7 +20291,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xxx11110xx1xx100x00000xxxxxxxxxx
- fcvtas. */
-- return 764;
-+ return 776;
- }
- }
- else
-@@ -16342,7 +20302,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xxx11110xx1xx010x00000xxxxxxxxxx
- scvtf. */
-- return 760;
-+ return 772;
- }
- else
- {
-@@ -16352,7 +20312,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xxx11110xx1x0110x00000xxxxxxxxxx
- fmov. */
-- return 768;
-+ return 780;
- }
- else
- {
-@@ -16362,7 +20322,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xxx11110xx101110x00000xxxxxxxxxx
- fmov. */
-- return 784;
-+ return 796;
- }
- else
- {
-@@ -16370,7 +20330,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xxx11110xx111110x00000xxxxxxxxxx
- fjcvtzs. */
-- return 786;
-+ return 798;
- }
- }
- }
-@@ -16390,7 +20350,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xxx11110xx100001x00000xxxxxxxxxx
- fcvtnu. */
-- return 758;
-+ return 770;
- }
- else
- {
-@@ -16398,7 +20358,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xxx11110xx110001x00000xxxxxxxxxx
- fcvtmu. */
-- return 778;
-+ return 790;
- }
- }
- else
-@@ -16409,7 +20369,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xxx11110xx101001x00000xxxxxxxxxx
- fcvtpu. */
-- return 774;
-+ return 786;
- }
- else
- {
-@@ -16417,7 +20377,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xxx11110xx111001x00000xxxxxxxxxx
- fcvtzu. */
-- return 782;
-+ return 794;
- }
- }
- }
-@@ -16427,7 +20387,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xxx11110xx1xx101x00000xxxxxxxxxx
- fcvtau. */
-- return 766;
-+ return 778;
- }
- }
- else
-@@ -16438,7 +20398,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xxx11110xx1xx011x00000xxxxxxxxxx
- ucvtf. */
-- return 762;
-+ return 774;
- }
- else
- {
-@@ -16448,7 +20408,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xxx11110xx1x0111x00000xxxxxxxxxx
- fmov. */
-- return 770;
-+ return 782;
- }
- else
- {
-@@ -16456,7 +20416,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xxx11110xx1x1111x00000xxxxxxxxxx
- fmov. */
-- return 785;
-+ return 797;
- }
- }
- }
-@@ -16472,11 +20432,22 @@ aarch64_opcode_lookup_1 (uint32_t word)
- {
- if (((word >> 18) & 0x1) == 0)
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- xxx11110xx1xx000010000xxxxxxxxxx
-- fmov. */
-- return 799;
-+ if (((word >> 19) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ xxx11110xx1x0000010000xxxxxxxxxx
-+ fmov. */
-+ return 817;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ xxx11110xx1x1000010000xxxxxxxxxx
-+ frint32z. */
-+ return 813;
-+ }
- }
- else
- {
-@@ -16484,18 +20455,29 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xxx11110xx1xx100010000xxxxxxxxxx
- frintn. */
-- return 808;
-+ return 826;
- }
- }
- else
- {
- if (((word >> 18) & 0x1) == 0)
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- xxx11110xx1xx001010000xxxxxxxxxx
-- fneg. */
-- return 803;
-+ if (((word >> 19) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ xxx11110xx1x0001010000xxxxxxxxxx
-+ fneg. */
-+ return 821;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ xxx11110xx1x1001010000xxxxxxxxxx
-+ frint64z. */
-+ return 815;
-+ }
- }
- else
- {
-@@ -16503,7 +20485,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xxx11110xx1xx101010000xxxxxxxxxx
- frintm. */
-- return 812;
-+ return 830;
- }
- }
- }
-@@ -16513,11 +20495,22 @@ aarch64_opcode_lookup_1 (uint32_t word)
- {
- if (((word >> 18) & 0x1) == 0)
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- xxx11110xx1xx000110000xxxxxxxxxx
-- fabs. */
-- return 801;
-+ if (((word >> 19) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ xxx11110xx1x0000110000xxxxxxxxxx
-+ fabs. */
-+ return 819;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ xxx11110xx1x1000110000xxxxxxxxxx
-+ frint32x. */
-+ return 814;
-+ }
- }
- else
- {
-@@ -16525,18 +20518,29 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xxx11110xx1xx100110000xxxxxxxxxx
- frintp. */
-- return 810;
-+ return 828;
- }
- }
- else
- {
- if (((word >> 18) & 0x1) == 0)
- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- xxx11110xx1xx001110000xxxxxxxxxx
-- fsqrt. */
-- return 805;
-+ if (((word >> 19) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ xxx11110xx1x0001110000xxxxxxxxxx
-+ fsqrt. */
-+ return 823;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ xxx11110xx1x1001110000xxxxxxxxxx
-+ frint64x. */
-+ return 816;
-+ }
- }
- else
- {
-@@ -16544,7 +20548,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xxx11110xx1xx101110000xxxxxxxxxx
- frintz. */
-- return 814;
-+ return 832;
- }
- }
- }
-@@ -16557,7 +20561,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xxx11110xx1xx01xx10000xxxxxxxxxx
- fcvt. */
-- return 807;
-+ return 825;
- }
- else
- {
-@@ -16569,7 +20573,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xxx11110xx1xx110010000xxxxxxxxxx
- frinta. */
-- return 816;
-+ return 834;
- }
- else
- {
-@@ -16577,7 +20581,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xxx11110xx1xx111010000xxxxxxxxxx
- frintx. */
-- return 818;
-+ return 836;
- }
- }
- else
-@@ -16586,7 +20590,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xxx11110xx1xx11x110000xxxxxxxxxx
- frinti. */
-- return 820;
-+ return 838;
- }
- }
- }
-@@ -16602,7 +20606,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xxx11110xx1xxxxxxx1000xxxxx00xxx
- fcmp. */
-- return 791;
-+ return 803;
- }
- else
- {
-@@ -16610,7 +20614,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xxx11110xx1xxxxxxx1000xxxxx10xxx
- fcmpe. */
-- return 793;
-+ return 805;
- }
- }
- else
-@@ -16621,7 +20625,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xxx11110xx1xxxxxxx1000xxxxx01xxx
- fcmp. */
-- return 795;
-+ return 807;
- }
- else
- {
-@@ -16629,7 +20633,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xxx11110xx1xxxxxxx1000xxxxx11xxx
- fcmpe. */
-- return 797;
-+ return 809;
- }
- }
- }
-@@ -16642,7 +20646,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x0x11110xx1xxxxxxxx100xxxxxxxxxx
- fmov. */
-- return 848;
-+ return 866;
- }
- else
- {
-@@ -16654,7 +20658,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1x11110xx1xxxxxx00100xxxxxxxxxx
- sqdmlal. */
-- return 416;
-+ return 422;
- }
- else
- {
-@@ -16662,7 +20666,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1x11110xx1xxxxxx10100xxxxxxxxxx
- sqdmull. */
-- return 418;
-+ return 424;
- }
- }
- else
-@@ -16671,7 +20675,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1x11110xx1xxxxxxx1100xxxxxxxxxx
- sqdmlsl. */
-- return 417;
-+ return 423;
- }
- }
- }
-@@ -16692,7 +20696,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x0x11110xx1xxxxx000010xxxxxxxxxx
- fmul. */
-- return 822;
-+ return 840;
- }
- else
- {
-@@ -16700,7 +20704,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1x11110xx1xxxxx000010xxxxxxxxxx
- sha1h. */
-- return 669;
-+ return 675;
- }
- }
- else
-@@ -16713,7 +20717,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x0011110xx1xxxxx100010xxxxxxxxxx
- fnmul. */
-- return 838;
-+ return 856;
- }
- else
- {
-@@ -16721,7 +20725,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1011110xx1xxxxx100010xxxxxxxxxx
- cmgt. */
-- return 476;
-+ return 482;
- }
- }
- else
-@@ -16730,7 +20734,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx111110xx1xxxxx100010xxxxxxxxxx
- cmge. */
-- return 505;
-+ return 511;
- }
- }
- }
-@@ -16746,7 +20750,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x0011110xx1xxxxx010010xxxxxxxxxx
- fmax. */
-- return 830;
-+ return 848;
- }
- else
- {
-@@ -16754,7 +20758,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1011110xx1xxxxx010010xxxxxxxxxx
- sqxtn. */
-- return 480;
-+ return 486;
- }
- }
- else
-@@ -16763,7 +20767,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx111110xx1xxxxx010010xxxxxxxxxx
- uqxtn. */
-- return 509;
-+ return 515;
- }
- }
- else
-@@ -16780,7 +20784,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx011110xx100xx0110010xxxxxxxxxx
- fcmgt. */
-- return 489;
-+ return 495;
- }
- else
- {
-@@ -16788,7 +20792,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx111110xx100xx0110010xxxxxxxxxx
- fcmge. */
-- return 519;
-+ return 525;
- }
- }
- else
-@@ -16801,7 +20805,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx0111100x110xx0110010xxxxxxxxxx
- fmaxnmp. */
-- return 533;
-+ return 539;
- }
- else
- {
-@@ -16809,7 +20813,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx1111100x110xx0110010xxxxxxxxxx
- fmaxnmp. */
-- return 532;
-+ return 538;
- }
- }
- else
-@@ -16820,7 +20824,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx0111101x110xx0110010xxxxxxxxxx
- fminnmp. */
-- return 539;
-+ return 545;
- }
- else
- {
-@@ -16828,7 +20832,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx1111101x110xx0110010xxxxxxxxxx
- fminnmp. */
-- return 538;
-+ return 544;
- }
- }
- }
-@@ -16841,7 +20845,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx011110xx1x1xx0110010xxxxxxxxxx
- fcmgt. */
-- return 490;
-+ return 496;
- }
- else
- {
-@@ -16849,7 +20853,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx111110xx1x1xx0110010xxxxxxxxxx
- fcmge. */
-- return 520;
-+ return 526;
- }
- }
- }
-@@ -16863,7 +20867,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx011110xx1x0xx1110010xxxxxxxxxx
- fcvtas. */
-- return 485;
-+ return 491;
- }
- else
- {
-@@ -16871,7 +20875,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx111110xx1x0xx1110010xxxxxxxxxx
- fcvtau. */
-- return 515;
-+ return 521;
- }
- }
- else
-@@ -16882,7 +20886,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx011110xx1x1xx1110010xxxxxxxxxx
- fcvtas. */
-- return 486;
-+ return 492;
- }
- else
- {
-@@ -16890,7 +20894,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx111110xx1x1xx1110010xxxxxxxxxx
- fcvtau. */
-- return 516;
-+ return 522;
- }
- }
- }
-@@ -16911,7 +20915,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x0011110xx1xxxxx001010xxxxxxxxxx
- fadd. */
-- return 826;
-+ return 844;
- }
- else
- {
-@@ -16919,7 +20923,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1011110xx1xxxxx001010xxxxxxxxxx
- sha256su0. */
-- return 671;
-+ return 677;
- }
- }
- else
-@@ -16928,7 +20932,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx111110xx1xxxxx001010xxxxxxxxxx
- sqxtun. */
-- return 508;
-+ return 514;
- }
- }
- else
-@@ -16939,7 +20943,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xxx11110xx1xxxx0101010xxxxxxxxxx
- cmlt. */
-- return 478;
-+ return 484;
- }
- else
- {
-@@ -16953,7 +20957,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx0111100x1x0xx1101010xxxxxxxxxx
- fcvtns. */
-- return 481;
-+ return 487;
- }
- else
- {
-@@ -16961,7 +20965,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx1111100x1x0xx1101010xxxxxxxxxx
- fcvtnu. */
-- return 511;
-+ return 517;
- }
- }
- else
-@@ -16972,7 +20976,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx0111101x1x0xx1101010xxxxxxxxxx
- fcvtps. */
-- return 495;
-+ return 501;
- }
- else
- {
-@@ -16980,7 +20984,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx1111101x1x0xx1101010xxxxxxxxxx
- fcvtpu. */
-- return 523;
-+ return 529;
- }
- }
- }
-@@ -16994,7 +20998,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx0111100x1x1xx1101010xxxxxxxxxx
- fcvtns. */
-- return 482;
-+ return 488;
- }
- else
- {
-@@ -17002,7 +21006,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx1111100x1x1xx1101010xxxxxxxxxx
- fcvtnu. */
-- return 512;
-+ return 518;
- }
- }
- else
-@@ -17013,7 +21017,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx0111101x1x1xx1101010xxxxxxxxxx
- fcvtps. */
-- return 496;
-+ return 502;
- }
- else
- {
-@@ -17021,7 +21025,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx1111101x1x1xx1101010xxxxxxxxxx
- fcvtpu. */
-- return 524;
-+ return 530;
- }
- }
- }
-@@ -17038,7 +21042,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx011110xx1xxxxx011010xxxxxxxxxx
- fmaxnm. */
-- return 834;
-+ return 852;
- }
- else
- {
-@@ -17046,7 +21050,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx111110xx1xxxxx011010xxxxxxxxxx
- fcvtxn. */
-- return 510;
-+ return 516;
- }
- }
- else
-@@ -17057,7 +21061,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xxx11110xx1x0xxx111010xxxxxxxxxx
- fcmlt. */
-- return 493;
-+ return 499;
- }
- else
- {
-@@ -17065,7 +21069,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xxx11110xx1x1xxx111010xxxxxxxxxx
- fcmlt. */
-- return 494;
-+ return 500;
- }
- }
- }
-@@ -17085,7 +21089,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x0x11110xx1xxxxx000110xxxxxxxxxx
- fdiv. */
-- return 824;
-+ return 842;
- }
- else
- {
-@@ -17093,7 +21097,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1x11110xx1xxxxx000110xxxxxxxxxx
- sha1su1. */
-- return 670;
-+ return 676;
- }
- }
- else
-@@ -17104,7 +21108,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx011110xx1xxxxx100110xxxxxxxxxx
- cmeq. */
-- return 477;
-+ return 483;
- }
- else
- {
-@@ -17112,7 +21116,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx111110xx1xxxxx100110xxxxxxxxxx
- cmle. */
-- return 506;
-+ return 512;
- }
- }
- }
-@@ -17124,7 +21128,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xxx11110xx1xxxxx010110xxxxxxxxxx
- fmin. */
-- return 832;
-+ return 850;
- }
- else
- {
-@@ -17140,7 +21144,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx011110xx100xx0110110xxxxxxxxxx
- fcmeq. */
-- return 491;
-+ return 497;
- }
- else
- {
-@@ -17148,7 +21152,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx111110xx100xx0110110xxxxxxxxxx
- fcmle. */
-- return 521;
-+ return 527;
- }
- }
- else
-@@ -17159,7 +21163,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx011110xx110xx0110110xxxxxxxxxx
- faddp. */
-- return 535;
-+ return 541;
- }
- else
- {
-@@ -17167,7 +21171,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx111110xx110xx0110110xxxxxxxxxx
- faddp. */
-- return 534;
-+ return 540;
- }
- }
- }
-@@ -17179,7 +21183,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx011110xx1x1xx0110110xxxxxxxxxx
- fcmeq. */
-- return 492;
-+ return 498;
- }
- else
- {
-@@ -17187,7 +21191,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx111110xx1x1xx0110110xxxxxxxxxx
- fcmle. */
-- return 522;
-+ return 528;
- }
- }
- }
-@@ -17203,7 +21207,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx0111100x1x0xx1110110xxxxxxxxxx
- scvtf. */
-- return 487;
-+ return 493;
- }
- else
- {
-@@ -17211,7 +21215,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx1111100x1x0xx1110110xxxxxxxxxx
- ucvtf. */
-- return 517;
-+ return 523;
- }
- }
- else
-@@ -17222,7 +21226,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx0111101x1x0xx1110110xxxxxxxxxx
- frecpe. */
-- return 499;
-+ return 505;
- }
- else
- {
-@@ -17230,7 +21234,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx1111101x1x0xx1110110xxxxxxxxxx
- frsqrte. */
-- return 527;
-+ return 533;
- }
- }
- }
-@@ -17244,7 +21248,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx0111100x1x1xx1110110xxxxxxxxxx
- scvtf. */
-- return 488;
-+ return 494;
- }
- else
- {
-@@ -17252,7 +21256,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx1111100x1x1xx1110110xxxxxxxxxx
- ucvtf. */
-- return 518;
-+ return 524;
- }
- }
- else
-@@ -17263,7 +21267,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx0111101x1x1xx1110110xxxxxxxxxx
- frecpe. */
-- return 500;
-+ return 506;
- }
- else
- {
-@@ -17271,7 +21275,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx1111101x1x1xx1110110xxxxxxxxxx
- frsqrte. */
-- return 528;
-+ return 534;
- }
- }
- }
-@@ -17293,7 +21297,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x0011110xx1xxxxx001110xxxxxxxxxx
- fsub. */
-- return 828;
-+ return 846;
- }
- else
- {
-@@ -17301,7 +21305,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1011110xx1xxxxx001110xxxxxxxxxx
- suqadd. */
-- return 474;
-+ return 480;
- }
- }
- else
-@@ -17310,7 +21314,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx111110xx1xxxxx001110xxxxxxxxxx
- usqadd. */
-- return 503;
-+ return 509;
- }
- }
- else
-@@ -17323,7 +21327,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx011110xx1xxxx0101110xxxxxxxxxx
- abs. */
-- return 479;
-+ return 485;
- }
- else
- {
-@@ -17331,7 +21335,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx111110xx1xxxx0101110xxxxxxxxxx
- neg. */
-- return 507;
-+ return 513;
- }
- }
- else
-@@ -17348,7 +21352,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx0111100x100xx1101110xxxxxxxxxx
- fcvtms. */
-- return 483;
-+ return 489;
- }
- else
- {
-@@ -17356,7 +21360,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx1111100x100xx1101110xxxxxxxxxx
- fcvtmu. */
-- return 513;
-+ return 519;
- }
- }
- else
-@@ -17367,7 +21371,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx0111101x100xx1101110xxxxxxxxxx
- fcvtzs. */
-- return 497;
-+ return 503;
- }
- else
- {
-@@ -17375,7 +21379,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx1111101x100xx1101110xxxxxxxxxx
- fcvtzu. */
-- return 525;
-+ return 531;
- }
- }
- }
-@@ -17385,7 +21389,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xxx11110xx110xx1101110xxxxxxxxxx
- addp. */
-- return 531;
-+ return 537;
- }
- }
- else
-@@ -17398,7 +21402,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx0111100x1x1xx1101110xxxxxxxxxx
- fcvtms. */
-- return 484;
-+ return 490;
- }
- else
- {
-@@ -17406,7 +21410,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx1111100x1x1xx1101110xxxxxxxxxx
- fcvtmu. */
-- return 514;
-+ return 520;
- }
- }
- else
-@@ -17417,7 +21421,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx0111101x1x1xx1101110xxxxxxxxxx
- fcvtzs. */
-- return 498;
-+ return 504;
- }
- else
- {
-@@ -17425,7 +21429,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx1111101x1x1xx1101110xxxxxxxxxx
- fcvtzu. */
-- return 526;
-+ return 532;
- }
- }
- }
-@@ -17444,7 +21448,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x0011110xx1xxxxx011110xxxxxxxxxx
- fminnm. */
-- return 836;
-+ return 854;
- }
- else
- {
-@@ -17452,7 +21456,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1011110xx1xxxxx011110xxxxxxxxxx
- sqabs. */
-- return 475;
-+ return 481;
- }
- }
- else
-@@ -17461,7 +21465,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx111110xx1xxxxx011110xxxxxxxxxx
- sqneg. */
-- return 504;
-+ return 510;
- }
- }
- else
-@@ -17476,7 +21480,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx0111100x1xxxx0111110xxxxxxxxxx
- fmaxp. */
-- return 537;
-+ return 543;
- }
- else
- {
-@@ -17484,7 +21488,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx1111100x1xxxx0111110xxxxxxxxxx
- fmaxp. */
-- return 536;
-+ return 542;
- }
- }
- else
-@@ -17495,7 +21499,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx0111101x1xxxx0111110xxxxxxxxxx
- fminp. */
-- return 541;
-+ return 547;
- }
- else
- {
-@@ -17503,7 +21507,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx1111101x1xxxx0111110xxxxxxxxxx
- fminp. */
-- return 540;
-+ return 546;
- }
- }
- }
-@@ -17515,7 +21519,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xxx11110xx1x0xx1111110xxxxxxxxxx
- frecpx. */
-- return 501;
-+ return 507;
- }
- else
- {
-@@ -17523,7 +21527,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xxx11110xx1x1xx1111110xxxxxxxxxx
- frecpx. */
-- return 502;
-+ return 508;
- }
- }
- }
-@@ -17546,7 +21550,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x0011110xx1xxxxxxxxx01xxxxx0xxxx
- fccmp. */
-- return 787;
-+ return 799;
- }
- else
- {
-@@ -17554,7 +21558,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x0011110xx1xxxxxxxxx01xxxxx1xxxx
- fccmpe. */
-- return 789;
-+ return 801;
- }
- }
- else
-@@ -17569,7 +21573,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1011110xx1xxxxxx00001xxxxxxxxxx
- add. */
-- return 559;
-+ return 565;
- }
- else
- {
-@@ -17577,7 +21581,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1011110xx1xxxxxx10001xxxxxxxxxx
- sshl. */
-- return 557;
-+ return 563;
- }
- }
- else
-@@ -17586,7 +21590,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1011110xx1xxxxxxx1001xxxxxxxxxx
- fcmeq. */
-- return 549;
-+ return 555;
- }
- }
- else
-@@ -17597,7 +21601,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1011110xx1xxxxxxx0101xxxxxxxxxx
- srshl. */
-- return 558;
-+ return 564;
- }
- else
- {
-@@ -17607,7 +21611,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1011110xx1xxxxx0x1101xxxxxxxxxx
- cmgt. */
-- return 555;
-+ return 561;
- }
- else
- {
-@@ -17615,7 +21619,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1011110xx1xxxxx1x1101xxxxxxxxxx
- sqdmulh. */
-- return 546;
-+ return 552;
- }
- }
- }
-@@ -17633,7 +21637,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx111110xx1xxxxxx00001xxxxxxxxxx
- sub. */
-- return 580;
-+ return 586;
- }
- else
- {
-@@ -17641,7 +21645,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx111110xx1xxxxxx10001xxxxxxxxxx
- ushl. */
-- return 578;
-+ return 584;
- }
- }
- else
-@@ -17652,7 +21656,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx1111100x1xxxxxxx1001xxxxxxxxxx
- fcmge. */
-- return 566;
-+ return 572;
- }
- else
- {
-@@ -17660,7 +21664,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx1111101x1xxxxxxx1001xxxxxxxxxx
- fcmgt. */
-- return 572;
-+ return 578;
- }
- }
- }
-@@ -17674,7 +21678,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx111110xx1xxxxx0x0101xxxxxxxxxx
- urshl. */
-- return 579;
-+ return 585;
- }
- else
- {
-@@ -17682,7 +21686,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx111110xx1xxxxx1x0101xxxxxxxxxx
- fabd. */
-- return 570;
-+ return 576;
- }
- }
- else
-@@ -17693,7 +21697,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx111110xx1xxxxx0x1101xxxxxxxxxx
- cmhi. */
-- return 576;
-+ return 582;
- }
- else
- {
-@@ -17701,7 +21705,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx111110xx1xxxxx1x1101xxxxxxxxxx
- sqrdmulh. */
-- return 565;
-+ return 571;
- }
- }
- }
-@@ -17717,7 +21721,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x0011110xx1xxxxxxxxx11xxxxxxxxxx
- fcsel. */
-- return 850;
-+ return 868;
- }
- else
- {
-@@ -17733,7 +21737,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1011110xx1xxxxx000011xxxxxxxxxx
- sqadd. */
-- return 542;
-+ return 548;
- }
- else
- {
-@@ -17741,7 +21745,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1011110xx1xxxxx100011xxxxxxxxxx
- cmtst. */
-- return 560;
-+ return 566;
- }
- }
- else
-@@ -17750,7 +21754,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1011110xx1xxxxxx10011xxxxxxxxxx
- sqshl. */
-- return 544;
-+ return 550;
- }
- }
- else
-@@ -17759,7 +21763,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1011110xx1xxxxxxx1011xxxxxxxxxx
- sqsub. */
-- return 543;
-+ return 549;
- }
- }
- else
-@@ -17772,7 +21776,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1011110xx1xxxxx0x0111xxxxxxxxxx
- sqrshl. */
-- return 545;
-+ return 551;
- }
- else
- {
-@@ -17780,7 +21784,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1011110xx1xxxxx1x0111xxxxxxxxxx
- fmulx. */
-- return 547;
-+ return 553;
- }
- }
- else
-@@ -17791,7 +21795,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1011110xx1xxxxxx01111xxxxxxxxxx
- cmge. */
-- return 556;
-+ return 562;
- }
- else
- {
-@@ -17801,7 +21805,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x10111100x1xxxxxx11111xxxxxxxxxx
- frecps. */
-- return 551;
-+ return 557;
- }
- else
- {
-@@ -17809,7 +21813,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x10111101x1xxxxxx11111xxxxxxxxxx
- frsqrts. */
-- return 553;
-+ return 559;
- }
- }
- }
-@@ -17830,7 +21834,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx111110xx1xxxxx000011xxxxxxxxxx
- uqadd. */
-- return 561;
-+ return 567;
- }
- else
- {
-@@ -17838,7 +21842,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx111110xx1xxxxx100011xxxxxxxxxx
- cmeq. */
-- return 581;
-+ return 587;
- }
- }
- else
-@@ -17847,7 +21851,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx111110xx1xxxxxx10011xxxxxxxxxx
- uqshl. */
-- return 563;
-+ return 569;
- }
- }
- else
-@@ -17858,7 +21862,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx111110xx1xxxxxx01011xxxxxxxxxx
- uqsub. */
-- return 562;
-+ return 568;
- }
- else
- {
-@@ -17868,7 +21872,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx1111100x1xxxxxx11011xxxxxxxxxx
- facge. */
-- return 568;
-+ return 574;
- }
- else
- {
-@@ -17876,7 +21880,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx1111101x1xxxxxx11011xxxxxxxxxx
- facgt. */
-- return 574;
-+ return 580;
- }
- }
- }
-@@ -17889,7 +21893,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx111110xx1xxxxxxx0111xxxxxxxxxx
- uqrshl. */
-- return 564;
-+ return 570;
- }
- else
- {
-@@ -17897,7 +21901,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx111110xx1xxxxxxx1111xxxxxxxxxx
- cmhs. */
-- return 577;
-+ return 583;
- }
- }
- }
-@@ -17928,7 +21932,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x0001111xxxxxxxx0000x0xxxxxxxxxx
- fmlal. */
-- return 2016;
-+ return 2377;
- }
- else
- {
-@@ -17936,7 +21940,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1001111xxxxxxxx0000x0xxxxxxxxxx
- fmlal. */
-- return 2020;
-+ return 2381;
- }
- }
- else
-@@ -17945,7 +21949,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx101111xxxxxxxx0000x0xxxxxxxxxx
- mla. */
-- return 117;
-+ return 119;
- }
- }
- else
-@@ -17958,7 +21962,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x0001111xxxxxxxx0100x0xxxxxxxxxx
- fmlsl. */
-- return 2017;
-+ return 2378;
- }
- else
- {
-@@ -17966,7 +21970,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1001111xxxxxxxx0100x0xxxxxxxxxx
- fmlsl. */
-- return 2021;
-+ return 2382;
- }
- }
- else
-@@ -17975,7 +21979,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx101111xxxxxxxx0100x0xxxxxxxxxx
- mls. */
-- return 120;
-+ return 122;
- }
- }
- }
-@@ -17991,7 +21995,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x0001111xxxxxxxx0010x0xxxxxxxxxx
- smlal. */
-- return 96;
-+ return 98;
- }
- else
- {
-@@ -17999,7 +22003,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1001111xxxxxxxx0010x0xxxxxxxxxx
- smlal2. */
-- return 97;
-+ return 99;
- }
- }
- else
-@@ -18010,7 +22014,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x0101111xxxxxxxx0010x0xxxxxxxxxx
- umlal. */
-- return 118;
-+ return 120;
- }
- else
- {
-@@ -18018,7 +22022,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1101111xxxxxxxx0010x0xxxxxxxxxx
- umlal2. */
-- return 119;
-+ return 121;
- }
- }
- }
-@@ -18032,7 +22036,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x0001111xxxxxxxx0110x0xxxxxxxxxx
- smlsl. */
-- return 100;
-+ return 102;
- }
- else
- {
-@@ -18040,7 +22044,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1001111xxxxxxxx0110x0xxxxxxxxxx
- smlsl2. */
-- return 101;
-+ return 103;
- }
- }
- else
-@@ -18051,7 +22055,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x0101111xxxxxxxx0110x0xxxxxxxxxx
- umlsl. */
-- return 121;
-+ return 123;
- }
- else
- {
-@@ -18059,7 +22063,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1101111xxxxxxxx0110x0xxxxxxxxxx
- umlsl2. */
-- return 122;
-+ return 124;
- }
- }
- }
-@@ -18079,7 +22083,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx0011110xxxxxxx0001x0xxxxxxxxxx
- fmla. */
-- return 112;
-+ return 114;
- }
- else
- {
-@@ -18087,7 +22091,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx0011111xxxxxxx0001x0xxxxxxxxxx
- fmla. */
-- return 111;
-+ return 113;
- }
- }
- else
-@@ -18098,7 +22102,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx0011110xxxxxxx0101x0xxxxxxxxxx
- fmls. */
-- return 114;
-+ return 116;
- }
- else
- {
-@@ -18106,7 +22110,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx0011111xxxxxxx0101x0xxxxxxxxxx
- fmls. */
-- return 113;
-+ return 115;
- }
- }
- }
-@@ -18120,7 +22124,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x0001111xxxxxxxx0011x0xxxxxxxxxx
- sqdmlal. */
-- return 98;
-+ return 100;
- }
- else
- {
-@@ -18128,7 +22132,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1001111xxxxxxxx0011x0xxxxxxxxxx
- sqdmlal2. */
-- return 99;
-+ return 101;
- }
- }
- else
-@@ -18139,7 +22143,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x0001111xxxxxxxx0111x0xxxxxxxxxx
- sqdmlsl. */
-- return 102;
-+ return 104;
- }
- else
- {
-@@ -18147,7 +22151,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1001111xxxxxxxx0111x0xxxxxxxxxx
- sqdmlsl2. */
-- return 103;
-+ return 105;
- }
- }
- }
-@@ -18158,7 +22162,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx101111xxxxxxxx0xx1x0xxxxxxxxxx
- fcmla. */
-- return 129;
-+ return 131;
- }
- }
- }
-@@ -18172,7 +22176,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx001111xxxxxxxx0xx0x1xxxxxxxxxx
- movi. */
-- return 131;
-+ return 133;
- }
- else
- {
-@@ -18180,7 +22184,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx101111xxxxxxxx0xx0x1xxxxxxxxxx
- mvni. */
-- return 139;
-+ return 141;
- }
- }
- else
-@@ -18191,7 +22195,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx001111xxxxxxxx0xx1x1xxxxxxxxxx
- orr. */
-- return 132;
-+ return 134;
- }
- else
- {
-@@ -18199,7 +22203,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx101111xxxxxxxx0xx1x1xxxxxxxxxx
- bic. */
-- return 140;
-+ return 142;
- }
- }
- }
-@@ -18216,7 +22220,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x0011111xx0xxxxx0xxxxxxxxxxxxxxx
- fmadd. */
-- return 840;
-+ return 858;
- }
- else
- {
-@@ -18224,7 +22228,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x0011111xx1xxxxx0xxxxxxxxxxxxxxx
- fnmadd. */
-- return 844;
-+ return 862;
- }
- }
- else
-@@ -18241,7 +22245,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x10111110xxxxxxx000xx0xxxxxxxxxx
- fmla. */
-- return 425;
-+ return 431;
- }
- else
- {
-@@ -18249,7 +22253,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x10111111xxxxxxx000xx0xxxxxxxxxx
- fmla. */
-- return 424;
-+ return 430;
- }
- }
- else
-@@ -18260,7 +22264,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x10111110xxxxxxx010xx0xxxxxxxxxx
- fmls. */
-- return 427;
-+ return 433;
- }
- else
- {
-@@ -18268,7 +22272,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x10111111xxxxxxx010xx0xxxxxxxxxx
- fmls. */
-- return 426;
-+ return 432;
- }
- }
- }
-@@ -18280,7 +22284,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1011111xxxxxxxx001xx0xxxxxxxxxx
- sqdmlal. */
-- return 419;
-+ return 425;
- }
- else
- {
-@@ -18288,7 +22292,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1011111xxxxxxxx011xx0xxxxxxxxxx
- sqdmlsl. */
-- return 420;
-+ return 426;
- }
- }
- }
-@@ -18302,7 +22306,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1011111xxxxxxxx0x00x1xxxxxxxxxx
- sshr. */
-- return 584;
-+ return 590;
- }
- else
- {
-@@ -18310,7 +22314,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1011111xxxxxxxx0x10x1xxxxxxxxxx
- srshr. */
-- return 586;
-+ return 592;
- }
- }
- else
-@@ -18323,7 +22327,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1011111xxxxxxxx0001x1xxxxxxxxxx
- ssra. */
-- return 585;
-+ return 591;
- }
- else
- {
-@@ -18331,7 +22335,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1011111xxxxxxxx0101x1xxxxxxxxxx
- shl. */
-- return 588;
-+ return 594;
- }
- }
- else
-@@ -18342,7 +22346,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1011111xxxxxxxx0011x1xxxxxxxxxx
- srsra. */
-- return 587;
-+ return 593;
- }
- else
- {
-@@ -18350,7 +22354,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1011111xxxxxxxx0111x1xxxxxxxxxx
- sqshl. */
-- return 589;
-+ return 595;
- }
- }
- }
-@@ -18369,7 +22373,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx111111xxxxxxxx0000xxxxxxxxxxxx
- ushr. */
-- return 596;
-+ return 602;
- }
- else
- {
-@@ -18377,7 +22381,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx111111xxxxxxxx0100xxxxxxxxxxxx
- sri. */
-- return 600;
-+ return 606;
- }
- }
- else
-@@ -18388,7 +22392,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx111111xxxxxxxx0010xxxxxxxxxxxx
- urshr. */
-- return 598;
-+ return 604;
- }
- else
- {
-@@ -18396,7 +22400,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx111111xxxxxxxx0110xxxxxxxxxxxx
- sqshlu. */
-- return 602;
-+ return 608;
- }
- }
- }
-@@ -18410,7 +22414,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx111111xxxxxxxx0001xxxxxxxxxxxx
- usra. */
-- return 597;
-+ return 603;
- }
- else
- {
-@@ -18418,7 +22422,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx111111xxxxxxxx0101xxxxxxxxxxxx
- sli. */
-- return 601;
-+ return 607;
- }
- }
- else
-@@ -18429,7 +22433,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx111111xxxxxxxx0011xxxxxxxxxxxx
- ursra. */
-- return 599;
-+ return 605;
- }
- else
- {
-@@ -18437,7 +22441,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx111111xxxxxxxx0111xxxxxxxxxxxx
- uqshl. */
-- return 603;
-+ return 609;
- }
- }
- }
-@@ -18448,13 +22452,13 @@ aarch64_opcode_lookup_1 (uint32_t word)
- {
- if (((word >> 28) & 0x1) == 0)
- {
-- if (((word >> 14) & 0x1) == 0)
-+ if (((word >> 10) & 0x1) == 0)
- {
-- if (((word >> 10) & 0x1) == 0)
-+ if (((word >> 12) & 0x1) == 0)
- {
-- if (((word >> 12) & 0x1) == 0)
-+ if (((word >> 13) & 0x1) == 0)
- {
-- if (((word >> 13) & 0x1) == 0)
-+ if (((word >> 14) & 0x1) == 0)
- {
- if (((word >> 29) & 0x1) == 0)
- {
-@@ -18462,7 +22466,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx001111xxxxxxxx1000x0xxxxxxxxxx
- mul. */
-- return 104;
-+ return 106;
- }
- else
- {
-@@ -18472,7 +22476,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x0101111xxxxxxxx1000x0xxxxxxxxxx
- fmlal2. */
-- return 2018;
-+ return 2379;
- }
- else
- {
-@@ -18480,7 +22484,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1101111xxxxxxxx1000x0xxxxxxxxxx
- fmlal2. */
-- return 2022;
-+ return 2383;
- }
- }
- }
-@@ -18488,13 +22492,46 @@ aarch64_opcode_lookup_1 (uint32_t word)
- {
- if (((word >> 29) & 0x1) == 0)
- {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ xx001111xxxxxxxx1100x0xxxxxxxxxx
-+ sqdmulh. */
-+ return 111;
-+ }
-+ else
-+ {
-+ if (((word >> 30) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ x0101111xxxxxxxx1100x0xxxxxxxxxx
-+ fmlsl2. */
-+ return 2380;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ x1101111xxxxxxxx1100x0xxxxxxxxxx
-+ fmlsl2. */
-+ return 2384;
-+ }
-+ }
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 14) & 0x1) == 0)
-+ {
-+ if (((word >> 29) & 0x1) == 0)
-+ {
- if (((word >> 30) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x0001111xxxxxxxx1010x0xxxxxxxxxx
- smull. */
-- return 105;
-+ return 107;
- }
- else
- {
-@@ -18502,7 +22539,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1001111xxxxxxxx1010x0xxxxxxxxxx
- smull2. */
-- return 106;
-+ return 108;
- }
- }
- else
-@@ -18513,7 +22550,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x0101111xxxxxxxx1010x0xxxxxxxxxx
- umull. */
-- return 123;
-+ return 125;
- }
- else
- {
-@@ -18521,14 +22558,36 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1101111xxxxxxxx1010x0xxxxxxxxxx
- umull2. */
-- return 124;
-+ return 126;
- }
- }
- }
-+ else
-+ {
-+ if (((word >> 29) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ xx001111xxxxxxxx1110x0xxxxxxxxxx
-+ sdot. */
-+ return 2351;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ xx101111xxxxxxxx1110x0xxxxxxxxxx
-+ udot. */
-+ return 2350;
-+ }
-+ }
- }
-- else
-+ }
-+ else
-+ {
-+ if (((word >> 13) & 0x1) == 0)
- {
-- if (((word >> 13) & 0x1) == 0)
-+ if (((word >> 14) & 0x1) == 0)
- {
- if (((word >> 23) & 0x1) == 0)
- {
-@@ -18538,7 +22597,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx0011110xxxxxxx1001x0xxxxxxxxxx
- fmul. */
-- return 116;
-+ return 118;
- }
- else
- {
-@@ -18546,7 +22605,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx1011110xxxxxxx1001x0xxxxxxxxxx
- fmulx. */
-- return 126;
-+ return 128;
- }
- }
- else
-@@ -18557,7 +22616,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx0011111xxxxxxx1001x0xxxxxxxxxx
- fmul. */
-- return 115;
-+ return 117;
- }
- else
- {
-@@ -18565,19 +22624,41 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx1011111xxxxxxx1001x0xxxxxxxxxx
- fmulx. */
-- return 125;
-+ return 127;
- }
- }
- }
- else
- {
-+ if (((word >> 29) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ xx001111xxxxxxxx1101x0xxxxxxxxxx
-+ sqrdmulh. */
-+ return 112;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ xx101111xxxxxxxx1101x0xxxxxxxxxx
-+ sqrdmlah. */
-+ return 129;
-+ }
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 14) & 0x1) == 0)
-+ {
- if (((word >> 30) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x0x01111xxxxxxxx1011x0xxxxxxxxxx
- sqdmull. */
-- return 107;
-+ return 109;
- }
- else
- {
-@@ -18585,14 +22666,80 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1x01111xxxxxxxx1011x0xxxxxxxxxx
- sqdmull2. */
-- return 108;
-+ return 110;
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 29) & 0x1) == 0)
-+ {
-+ if (((word >> 22) & 0x1) == 0)
-+ {
-+ if (((word >> 23) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ xx00111100xxxxxx1111x0xxxxxxxxxx
-+ sudot. */
-+ return 2428;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ xx00111110xxxxxx1111x0xxxxxxxxxx
-+ usdot. */
-+ return 2427;
-+ }
-+ }
-+ else
-+ {
-+ if (((word >> 23) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ xx00111101xxxxxx1111x0xxxxxxxxxx
-+ bfdot. */
-+ return 2439;
-+ }
-+ else
-+ {
-+ if (((word >> 30) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ x000111111xxxxxx1111x0xxxxxxxxxx
-+ bfmlalb. */
-+ return 2447;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ x100111111xxxxxx1111x0xxxxxxxxxx
-+ bfmlalt. */
-+ return 2446;
-+ }
-+ }
-+ }
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ xx101111xxxxxxxx1111x0xxxxxxxxxx
-+ sqrdmlsh. */
-+ return 130;
- }
- }
- }
- }
-- else
-+ }
-+ else
-+ {
-+ if (((word >> 11) & 0x1) == 0)
- {
-- if (((word >> 11) & 0x1) == 0)
-+ if (((word >> 14) & 0x1) == 0)
- {
- if (((word >> 12) & 0x1) == 0)
- {
-@@ -18602,7 +22749,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx001111xxxxxxxx10x001xxxxxxxxxx
- movi. */
-- return 133;
-+ return 135;
- }
- else
- {
-@@ -18610,7 +22757,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx101111xxxxxxxx10x001xxxxxxxxxx
- mvni. */
-- return 141;
-+ return 143;
- }
- }
- else
-@@ -18621,7 +22768,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx001111xxxxxxxx10x101xxxxxxxxxx
- orr. */
-- return 134;
-+ return 136;
- }
- else
- {
-@@ -18629,245 +22776,179 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx101111xxxxxxxx10x101xxxxxxxxxx
- bic. */
-- return 142;
-+ return 144;
- }
- }
- }
- else
- {
-- if (((word >> 12) & 0x1) == 0)
-+ if (((word >> 13) & 0x1) == 0)
- {
- if (((word >> 29) & 0x1) == 0)
- {
-- if (((word >> 30) & 0x1) == 0)
-- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- x0001111xxxxxxxx10x011xxxxxxxxxx
-- rshrn. */
-- return 376;
-- }
-- else
-- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- x1001111xxxxxxxx10x011xxxxxxxxxx
-- rshrn2. */
-- return 377;
-- }
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ xx001111xxxxxxxx110x01xxxxxxxxxx
-+ movi. */
-+ return 137;
- }
- else
- {
-- if (((word >> 30) & 0x1) == 0)
-- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- x0101111xxxxxxxx10x011xxxxxxxxxx
-- sqrshrun. */
-- return 400;
-- }
-- else
-- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- x1101111xxxxxxxx10x011xxxxxxxxxx
-- sqrshrun2. */
-- return 401;
-- }
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ xx101111xxxxxxxx110x01xxxxxxxxxx
-+ mvni. */
-+ return 145;
- }
- }
- else
- {
-- if (((word >> 29) & 0x1) == 0)
-+ if (((word >> 12) & 0x1) == 0)
- {
-- if (((word >> 30) & 0x1) == 0)
-+ if (((word >> 29) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
-- x0001111xxxxxxxx10x111xxxxxxxxxx
-- sqrshrn. */
-- return 380;
-+ xx001111xxxxxxxx111001xxxxxxxxxx
-+ movi. */
-+ return 138;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
-- x1001111xxxxxxxx10x111xxxxxxxxxx
-- sqrshrn2. */
-- return 381;
-+ xx101111xxxxxxxx111001xxxxxxxxxx
-+ movi. */
-+ return 146;
- }
- }
- else
- {
-- if (((word >> 30) & 0x1) == 0)
-+ if (((word >> 29) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
-- x0101111xxxxxxxx10x111xxxxxxxxxx
-- uqrshrn. */
-- return 404;
-+ xx001111xxxxxxxx111101xxxxxxxxxx
-+ fmov. */
-+ return 139;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
-- x1101111xxxxxxxx10x111xxxxxxxxxx
-- uqrshrn2. */
-- return 405;
-+ xx101111xxxxxxxx111101xxxxxxxxxx
-+ fmov. */
-+ return 148;
- }
- }
- }
- }
- }
-- }
-- else
-- {
-- if (((word >> 13) & 0x1) == 0)
-+ else
- {
-- if (((word >> 10) & 0x1) == 0)
-+ if (((word >> 12) & 0x1) == 0)
- {
-- if (((word >> 12) & 0x1) == 0)
-+ if (((word >> 29) & 0x1) == 0)
- {
-- if (((word >> 29) & 0x1) == 0)
-+ if (((word >> 30) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
-- xx001111xxxxxxxx1100x0xxxxxxxxxx
-- sqdmulh. */
-- return 109;
-+ x0001111xxxxxxxx1xx011xxxxxxxxxx
-+ rshrn. */
-+ return 382;
- }
- else
- {
-- if (((word >> 30) & 0x1) == 0)
-- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- x0101111xxxxxxxx1100x0xxxxxxxxxx
-- fmlsl2. */
-- return 2019;
-- }
-- else
-- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- x1101111xxxxxxxx1100x0xxxxxxxxxx
-- fmlsl2. */
-- return 2023;
-- }
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ x1001111xxxxxxxx1xx011xxxxxxxxxx
-+ rshrn2. */
-+ return 383;
- }
- }
- else
- {
-- if (((word >> 29) & 0x1) == 0)
-+ if (((word >> 30) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
-- xx001111xxxxxxxx1101x0xxxxxxxxxx
-- sqrdmulh. */
-- return 110;
-+ x0101111xxxxxxxx1xx011xxxxxxxxxx
-+ sqrshrun. */
-+ return 406;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
-- xx101111xxxxxxxx1101x0xxxxxxxxxx
-- sqrdmlah. */
-- return 127;
-+ x1101111xxxxxxxx1xx011xxxxxxxxxx
-+ sqrshrun2. */
-+ return 407;
- }
- }
- }
- else
- {
-- if (((word >> 29) & 0x1) == 0)
-- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- xx001111xxxxxxxx110xx1xxxxxxxxxx
-- movi. */
-- return 135;
-- }
-- else
-- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- xx101111xxxxxxxx110xx1xxxxxxxxxx
-- mvni. */
-- return 143;
-- }
-- }
-- }
-- else
-- {
-- if (((word >> 12) & 0x1) == 0)
-- {
-- if (((word >> 29) & 0x1) == 0)
-- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- xx001111xxxxxxxx1110xxxxxxxxxxxx
-- movi. */
-- return 136;
-- }
-- else
-- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- xx101111xxxxxxxx1110xxxxxxxxxxxx
-- movi. */
-- return 144;
-- }
-- }
-- else
-- {
-- if (((word >> 10) & 0x1) == 0)
-- {
-- /* 33222222222211111111110000000000
-- 10987654321098765432109876543210
-- xxx01111xxxxxxxx1111x0xxxxxxxxxx
-- sqrdmlsh. */
-- return 128;
-- }
-- else
-+ if (((word >> 13) & 0x1) == 0)
- {
-- if (((word >> 11) & 0x1) == 0)
-+ if (((word >> 29) & 0x1) == 0)
- {
-- if (((word >> 29) & 0x1) == 0)
-+ if (((word >> 30) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
-- xx001111xxxxxxxx111101xxxxxxxxxx
-- fmov. */
-- return 137;
-+ x0001111xxxxxxxx1x0111xxxxxxxxxx
-+ sqrshrn. */
-+ return 386;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
-- xx101111xxxxxxxx111101xxxxxxxxxx
-- fmov. */
-- return 146;
-+ x1001111xxxxxxxx1x0111xxxxxxxxxx
-+ sqrshrn2. */
-+ return 387;
- }
- }
- else
- {
-- if (((word >> 29) & 0x1) == 0)
-+ if (((word >> 30) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
-- xx001111xxxxxxxx111111xxxxxxxxxx
-- fmov. */
-- return 138;
-+ x0101111xxxxxxxx1x0111xxxxxxxxxx
-+ uqrshrn. */
-+ return 410;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
-- xx101111xxxxxxxx111111xxxxxxxxxx
-- fcvtzu. */
-- return 412;
-+ x1101111xxxxxxxx1x0111xxxxxxxxxx
-+ uqrshrn2. */
-+ return 411;
- }
- }
- }
-+ else
-+ {
-+ if (((word >> 29) & 0x1) == 0)
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ xx001111xxxxxxxx1x1111xxxxxxxxxx
-+ fmov. */
-+ return 140;
-+ }
-+ else
-+ {
-+ /* 33222222222211111111110000000000
-+ 10987654321098765432109876543210
-+ xx101111xxxxxxxx1x1111xxxxxxxxxx
-+ fcvtzu. */
-+ return 418;
-+ }
-+ }
- }
- }
- }
-@@ -18884,7 +22965,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x0011111xx0xxxxx1xxxxxxxxxxxxxxx
- fmsub. */
-- return 842;
-+ return 860;
- }
- else
- {
-@@ -18892,7 +22973,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x0011111xx1xxxxx1xxxxxxxxxxxxxxx
- fnmsub. */
-- return 846;
-+ return 864;
- }
- }
- else
-@@ -18905,7 +22986,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1011111xxxxxxxx1xx0x0xxxxxxxxxx
- sqdmulh. */
-- return 422;
-+ return 428;
- }
- else
- {
-@@ -18919,7 +23000,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x10111110xxxxxxx1001x0xxxxxxxxxx
- fmul. */
-- return 429;
-+ return 435;
- }
- else
- {
-@@ -18927,7 +23008,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x10111111xxxxxxx1001x0xxxxxxxxxx
- fmul. */
-- return 428;
-+ return 434;
- }
- }
- else
-@@ -18936,7 +23017,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1011111xxxxxxxx1101x0xxxxxxxxxx
- sqrdmulh. */
-- return 423;
-+ return 429;
- }
- }
- else
-@@ -18945,7 +23026,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1011111xxxxxxxx1x11x0xxxxxxxxxx
- sqdmull. */
-- return 421;
-+ return 427;
- }
- }
- }
-@@ -18959,7 +23040,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1011111xxxxxxxx1xx001xxxxxxxxxx
- scvtf. */
-- return 592;
-+ return 598;
- }
- else
- {
-@@ -18967,7 +23048,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1011111xxxxxxxx1xx101xxxxxxxxxx
- sqshrn. */
-- return 590;
-+ return 596;
- }
- }
- else
-@@ -18978,7 +23059,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1011111xxxxxxxx1x0x11xxxxxxxxxx
- sqrshrn. */
-- return 591;
-+ return 597;
- }
- else
- {
-@@ -18986,7 +23067,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- x1011111xxxxxxxx1x1x11xxxxxxxxxx
- fcvtzs. */
-- return 594;
-+ return 600;
- }
- }
- }
-@@ -19006,7 +23087,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx1111110xxxxxxx100xx0xxxxxxxxxx
- fmulx. */
-- return 431;
-+ return 437;
- }
- else
- {
-@@ -19014,7 +23095,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx1111111xxxxxxx100xx0xxxxxxxxxx
- fmulx. */
-- return 430;
-+ return 436;
- }
- }
- else
-@@ -19023,7 +23104,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx111111xxxxxxxx110xx0xxxxxxxxxx
- sqrdmlah. */
-- return 432;
-+ return 438;
- }
- }
- else
-@@ -19032,7 +23113,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx111111xxxxxxxx1x1xx0xxxxxxxxxx
- sqrdmlsh. */
-- return 433;
-+ return 439;
- }
- }
- else
-@@ -19047,7 +23128,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx111111xxxxxxxx1x0001xxxxxxxxxx
- sqshrun. */
-- return 604;
-+ return 610;
- }
- else
- {
-@@ -19055,7 +23136,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx111111xxxxxxxx1x1001xxxxxxxxxx
- ucvtf. */
-- return 608;
-+ return 614;
- }
- }
- else
-@@ -19064,7 +23145,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx111111xxxxxxxx1xx101xxxxxxxxxx
- uqshrn. */
-- return 606;
-+ return 612;
- }
- }
- else
-@@ -19075,7 +23156,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx111111xxxxxxxx1xx011xxxxxxxxxx
- sqrshrun. */
-- return 605;
-+ return 611;
- }
- else
- {
-@@ -19085,7 +23166,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx111111xxxxxxxx1x0111xxxxxxxxxx
- uqrshrn. */
-- return 607;
-+ return 613;
- }
- else
- {
-@@ -19093,7 +23174,7 @@ aarch64_opcode_lookup_1 (uint32_t word)
- 10987654321098765432109876543210
- xx111111xxxxxxxx1x1111xxxxxxxxxx
- fcvtzu. */
-- return 610;
-+ return 616;
- }
- }
- }
-@@ -19124,211 +23205,257 @@ aarch64_find_next_opcode (const aarch64_
- int value;
- switch (key)
- {
-- case 941: value = 945; break; /* stnp --> stp. */
-- case 945: return NULL; /* stp --> NULL. */
-- case 939: value = 940; break; /* stllrb --> stllrh. */
-- case 940: return NULL; /* stllrh --> NULL. */
-- case 942: value = 946; break; /* ldnp --> ldp. */
-- case 946: return NULL; /* ldp --> NULL. */
-- case 1157: value = 1158; break; /* msr --> hint. */
-- case 1158: value = 1173; break; /* hint --> clrex. */
-- case 1173: value = 1174; break; /* clrex --> dsb. */
-- case 1174: value = 1175; break; /* dsb --> dmb. */
-- case 1175: value = 1176; break; /* dmb --> isb. */
-- case 1176: value = 1177; break; /* isb --> sys. */
-- case 1177: value = 1182; break; /* sys --> msr. */
-- case 1182: value = 2024; break; /* msr --> cfinv. */
-- case 2024: return NULL; /* cfinv --> NULL. */
-- case 1183: value = 1184; break; /* sysl --> mrs. */
-- case 1184: return NULL; /* mrs --> NULL. */
-- case 434: value = 435; break; /* st4 --> st1. */
-- case 435: value = 436; break; /* st1 --> st2. */
-- case 436: value = 437; break; /* st2 --> st3. */
-- case 437: return NULL; /* st3 --> NULL. */
-- case 442: value = 443; break; /* st4 --> st1. */
-- case 443: value = 444; break; /* st1 --> st2. */
-- case 444: value = 445; break; /* st2 --> st3. */
-- case 445: return NULL; /* st3 --> NULL. */
-- case 438: value = 439; break; /* ld4 --> ld1. */
-- case 439: value = 440; break; /* ld1 --> ld2. */
-- case 440: value = 441; break; /* ld2 --> ld3. */
-- case 441: return NULL; /* ld3 --> NULL. */
-- case 454: value = 456; break; /* ld1 --> ld1r. */
-- case 456: return NULL; /* ld1r --> NULL. */
-- case 458: value = 460; break; /* ld2 --> ld2r. */
-- case 460: return NULL; /* ld2r --> NULL. */
-- case 455: value = 457; break; /* ld3 --> ld3r. */
-- case 457: return NULL; /* ld3r --> NULL. */
-- case 459: value = 461; break; /* ld4 --> ld4r. */
-- case 461: return NULL; /* ld4r --> NULL. */
-- case 446: value = 447; break; /* ld4 --> ld1. */
-- case 447: value = 448; break; /* ld1 --> ld2. */
-- case 448: value = 449; break; /* ld2 --> ld3. */
-- case 449: return NULL; /* ld3 --> NULL. */
-- case 466: value = 468; break; /* ld1 --> ld1r. */
-- case 468: return NULL; /* ld1r --> NULL. */
-- case 467: value = 469; break; /* ld3 --> ld3r. */
-- case 469: return NULL; /* ld3r --> NULL. */
-- case 470: value = 472; break; /* ld2 --> ld2r. */
-- case 472: return NULL; /* ld2r --> NULL. */
-- case 471: value = 473; break; /* ld4 --> ld4r. */
-- case 473: return NULL; /* ld4r --> NULL. */
-- case 752: value = 753; break; /* fcvtzs --> fcvtzs. */
-- case 753: return NULL; /* fcvtzs --> NULL. */
-- case 748: value = 749; break; /* scvtf --> scvtf. */
-- case 749: return NULL; /* scvtf --> NULL. */
-- case 754: value = 755; break; /* fcvtzu --> fcvtzu. */
-- case 755: return NULL; /* fcvtzu --> NULL. */
-- case 750: value = 751; break; /* ucvtf --> ucvtf. */
-- case 751: return NULL; /* ucvtf --> NULL. */
-- case 756: value = 757; break; /* fcvtns --> fcvtns. */
-- case 757: return NULL; /* fcvtns --> NULL. */
-- case 776: value = 777; break; /* fcvtms --> fcvtms. */
-- case 777: return NULL; /* fcvtms --> NULL. */
-- case 772: value = 773; break; /* fcvtps --> fcvtps. */
-- case 773: return NULL; /* fcvtps --> NULL. */
-- case 780: value = 781; break; /* fcvtzs --> fcvtzs. */
-- case 781: return NULL; /* fcvtzs --> NULL. */
-- case 764: value = 765; break; /* fcvtas --> fcvtas. */
-- case 765: return NULL; /* fcvtas --> NULL. */
-+ case 12: value = 19; break; /* add --> addg. */
-+ case 19: return NULL; /* addg --> NULL. */
-+ case 16: value = 20; break; /* sub --> subg. */
-+ case 20: return NULL; /* subg --> NULL. */
-+ case 971: value = 975; break; /* stnp --> stp. */
-+ case 975: return NULL; /* stp --> NULL. */
-+ case 969: value = 970; break; /* stllrb --> stllrh. */
-+ case 970: return NULL; /* stllrh --> NULL. */
-+ case 972: value = 976; break; /* ldnp --> ldp. */
-+ case 976: return NULL; /* ldp --> NULL. */
-+ case 1636: value = 1637; break; /* ldff1b --> ldff1b. */
-+ case 1637: return NULL; /* ldff1b --> NULL. */
-+ case 1692: value = 1693; break; /* ldff1sw --> ldff1sw. */
-+ case 1693: return NULL; /* ldff1sw --> NULL. */
-+ case 1640: value = 1641; break; /* ldff1b --> ldff1b. */
-+ case 1641: return NULL; /* ldff1b --> NULL. */
-+ case 1659: value = 1660; break; /* ldff1h --> ldff1h. */
-+ case 1660: return NULL; /* ldff1h --> NULL. */
-+ case 1638: value = 1639; break; /* ldff1b --> ldff1b. */
-+ case 1639: return NULL; /* ldff1b --> NULL. */
-+ case 1657: value = 1658; break; /* ldff1h --> ldff1h. */
-+ case 1658: return NULL; /* ldff1h --> NULL. */
-+ case 1642: value = 1643; break; /* ldff1b --> ldff1b. */
-+ case 1643: return NULL; /* ldff1b --> NULL. */
-+ case 1661: value = 1662; break; /* ldff1h --> ldff1h. */
-+ case 1662: return NULL; /* ldff1h --> NULL. */
-+ case 1682: value = 1683; break; /* ldff1sh --> ldff1sh. */
-+ case 1683: return NULL; /* ldff1sh --> NULL. */
-+ case 1670: value = 1671; break; /* ldff1sb --> ldff1sb. */
-+ case 1671: return NULL; /* ldff1sb --> NULL. */
-+ case 1701: value = 1702; break; /* ldff1w --> ldff1w. */
-+ case 1702: return NULL; /* ldff1w --> NULL. */
-+ case 1674: value = 1675; break; /* ldff1sb --> ldff1sb. */
-+ case 1675: return NULL; /* ldff1sb --> NULL. */
-+ case 1684: value = 1685; break; /* ldff1sh --> ldff1sh. */
-+ case 1685: return NULL; /* ldff1sh --> NULL. */
-+ case 1672: value = 1673; break; /* ldff1sb --> ldff1sb. */
-+ case 1673: return NULL; /* ldff1sb --> NULL. */
-+ case 1703: value = 1704; break; /* ldff1w --> ldff1w. */
-+ case 1704: return NULL; /* ldff1w --> NULL. */
-+ case 1648: value = 1649; break; /* ldff1d --> ldff1d. */
-+ case 1649: return NULL; /* ldff1d --> NULL. */
-+ case 811: value = 812; break; /* xaflag --> axflag. */
-+ case 812: value = 1194; break; /* axflag --> tcommit. */
-+ case 1194: value = 1197; break; /* tcommit --> msr. */
-+ case 1197: value = 1198; break; /* msr --> hint. */
-+ case 1198: value = 1207; break; /* hint --> dgh. */
-+ case 1207: value = 1216; break; /* dgh --> clrex. */
-+ case 1216: value = 1217; break; /* clrex --> dsb. */
-+ case 1217: value = 1218; break; /* dsb --> dsb. */
-+ case 1218: value = 1222; break; /* dsb --> dmb. */
-+ case 1222: value = 1223; break; /* dmb --> isb. */
-+ case 1223: value = 1224; break; /* isb --> sb. */
-+ case 1224: value = 1225; break; /* sb --> sys. */
-+ case 1225: value = 1230; break; /* sys --> wfet. */
-+ case 1230: value = 1231; break; /* wfet --> wfit. */
-+ case 1231: value = 1235; break; /* wfit --> cfinv. */
-+ case 1235: value = 1236; break; /* cfinv --> msr. */
-+ case 1236: return NULL; /* msr --> NULL. */
-+ case 1193: value = 1195; break; /* tstart --> ttest. */
-+ case 1195: value = 1237; break; /* ttest --> sysl. */
-+ case 1237: value = 1238; break; /* sysl --> mrs. */
-+ case 1238: return NULL; /* mrs --> NULL. */
-+ case 440: value = 441; break; /* st4 --> st1. */
-+ case 441: value = 442; break; /* st1 --> st2. */
-+ case 442: value = 443; break; /* st2 --> st3. */
-+ case 443: return NULL; /* st3 --> NULL. */
-+ case 448: value = 449; break; /* st4 --> st1. */
-+ case 449: value = 450; break; /* st1 --> st2. */
-+ case 450: value = 451; break; /* st2 --> st3. */
-+ case 451: return NULL; /* st3 --> NULL. */
-+ case 444: value = 445; break; /* ld4 --> ld1. */
-+ case 445: value = 446; break; /* ld1 --> ld2. */
-+ case 446: value = 447; break; /* ld2 --> ld3. */
-+ case 447: return NULL; /* ld3 --> NULL. */
-+ case 460: value = 462; break; /* ld1 --> ld1r. */
-+ case 462: return NULL; /* ld1r --> NULL. */
-+ case 464: value = 466; break; /* ld2 --> ld2r. */
-+ case 466: return NULL; /* ld2r --> NULL. */
-+ case 461: value = 463; break; /* ld3 --> ld3r. */
-+ case 463: return NULL; /* ld3r --> NULL. */
-+ case 465: value = 467; break; /* ld4 --> ld4r. */
-+ case 467: return NULL; /* ld4r --> NULL. */
-+ case 452: value = 453; break; /* ld4 --> ld1. */
-+ case 453: value = 454; break; /* ld1 --> ld2. */
-+ case 454: value = 455; break; /* ld2 --> ld3. */
-+ case 455: return NULL; /* ld3 --> NULL. */
-+ case 472: value = 474; break; /* ld1 --> ld1r. */
-+ case 474: return NULL; /* ld1r --> NULL. */
-+ case 473: value = 475; break; /* ld3 --> ld3r. */
-+ case 475: return NULL; /* ld3r --> NULL. */
-+ case 476: value = 478; break; /* ld2 --> ld2r. */
-+ case 478: return NULL; /* ld2r --> NULL. */
-+ case 477: value = 479; break; /* ld4 --> ld4r. */
-+ case 479: return NULL; /* ld4r --> NULL. */
-+ case 764: value = 765; break; /* fcvtzs --> fcvtzs. */
-+ case 765: return NULL; /* fcvtzs --> NULL. */
- case 760: value = 761; break; /* scvtf --> scvtf. */
- case 761: return NULL; /* scvtf --> NULL. */
-- case 768: value = 769; break; /* fmov --> fmov. */
-- case 769: return NULL; /* fmov --> NULL. */
-- case 758: value = 759; break; /* fcvtnu --> fcvtnu. */
-- case 759: return NULL; /* fcvtnu --> NULL. */
-- case 778: value = 779; break; /* fcvtmu --> fcvtmu. */
-- case 779: return NULL; /* fcvtmu --> NULL. */
-- case 774: value = 775; break; /* fcvtpu --> fcvtpu. */
-- case 775: return NULL; /* fcvtpu --> NULL. */
-- case 782: value = 783; break; /* fcvtzu --> fcvtzu. */
-- case 783: return NULL; /* fcvtzu --> NULL. */
-- case 766: value = 767; break; /* fcvtau --> fcvtau. */
-- case 767: return NULL; /* fcvtau --> NULL. */
-+ case 766: value = 767; break; /* fcvtzu --> fcvtzu. */
-+ case 767: return NULL; /* fcvtzu --> NULL. */
- case 762: value = 763; break; /* ucvtf --> ucvtf. */
- case 763: return NULL; /* ucvtf --> NULL. */
-- case 770: value = 771; break; /* fmov --> fmov. */
-- case 771: return NULL; /* fmov --> NULL. */
-- case 799: value = 800; break; /* fmov --> fmov. */
-- case 800: return NULL; /* fmov --> NULL. */
-- case 808: value = 809; break; /* frintn --> frintn. */
-- case 809: return NULL; /* frintn --> NULL. */
-- case 803: value = 804; break; /* fneg --> fneg. */
-- case 804: return NULL; /* fneg --> NULL. */
-- case 812: value = 813; break; /* frintm --> frintm. */
-- case 813: return NULL; /* frintm --> NULL. */
-- case 801: value = 802; break; /* fabs --> fabs. */
-- case 802: return NULL; /* fabs --> NULL. */
-- case 810: value = 811; break; /* frintp --> frintp. */
-- case 811: return NULL; /* frintp --> NULL. */
-- case 805: value = 806; break; /* fsqrt --> fsqrt. */
-- case 806: return NULL; /* fsqrt --> NULL. */
-- case 814: value = 815; break; /* frintz --> frintz. */
-- case 815: return NULL; /* frintz --> NULL. */
-- case 816: value = 817; break; /* frinta --> frinta. */
-- case 817: return NULL; /* frinta --> NULL. */
-- case 818: value = 819; break; /* frintx --> frintx. */
-- case 819: return NULL; /* frintx --> NULL. */
-- case 820: value = 821; break; /* frinti --> frinti. */
-- case 821: return NULL; /* frinti --> NULL. */
-- case 791: value = 792; break; /* fcmp --> fcmp. */
-- case 792: return NULL; /* fcmp --> NULL. */
-- case 793: value = 794; break; /* fcmpe --> fcmpe. */
-- case 794: return NULL; /* fcmpe --> NULL. */
-- case 795: value = 796; break; /* fcmp --> fcmp. */
-- case 796: return NULL; /* fcmp --> NULL. */
-- case 797: value = 798; break; /* fcmpe --> fcmpe. */
-- case 798: return NULL; /* fcmpe --> NULL. */
-- case 848: value = 849; break; /* fmov --> fmov. */
-- case 849: return NULL; /* fmov --> NULL. */
-- case 822: value = 823; break; /* fmul --> fmul. */
-- case 823: return NULL; /* fmul --> NULL. */
-- case 838: value = 839; break; /* fnmul --> fnmul. */
-- case 839: return NULL; /* fnmul --> NULL. */
-- case 830: value = 831; break; /* fmax --> fmax. */
-- case 831: return NULL; /* fmax --> NULL. */
-- case 826: value = 827; break; /* fadd --> fadd. */
-- case 827: return NULL; /* fadd --> NULL. */
-- case 834: value = 835; break; /* fmaxnm --> fmaxnm. */
-- case 835: return NULL; /* fmaxnm --> NULL. */
-- case 824: value = 825; break; /* fdiv --> fdiv. */
-- case 825: return NULL; /* fdiv --> NULL. */
-- case 832: value = 833; break; /* fmin --> fmin. */
-- case 833: return NULL; /* fmin --> NULL. */
-- case 828: value = 829; break; /* fsub --> fsub. */
-- case 829: return NULL; /* fsub --> NULL. */
-- case 836: value = 837; break; /* fminnm --> fminnm. */
-- case 837: return NULL; /* fminnm --> NULL. */
-- case 787: value = 788; break; /* fccmp --> fccmp. */
-- case 788: return NULL; /* fccmp --> NULL. */
-- case 789: value = 790; break; /* fccmpe --> fccmpe. */
-- case 790: return NULL; /* fccmpe --> NULL. */
-- case 850: value = 851; break; /* fcsel --> fcsel. */
-- case 851: return NULL; /* fcsel --> NULL. */
-- case 131: value = 368; break; /* movi --> sshr. */
-- case 368: value = 370; break; /* sshr --> srshr. */
-- case 370: return NULL; /* srshr --> NULL. */
-- case 139: value = 390; break; /* mvni --> ushr. */
-- case 390: value = 392; break; /* ushr --> urshr. */
-- case 392: value = 394; break; /* urshr --> sri. */
-- case 394: value = 396; break; /* sri --> sqshlu. */
-- case 396: return NULL; /* sqshlu --> NULL. */
-- case 132: value = 369; break; /* orr --> ssra. */
-- case 369: value = 371; break; /* ssra --> srsra. */
-- case 371: value = 372; break; /* srsra --> shl. */
-- case 372: value = 373; break; /* shl --> sqshl. */
-- case 373: return NULL; /* sqshl --> NULL. */
-- case 140: value = 391; break; /* bic --> usra. */
-- case 391: value = 393; break; /* usra --> ursra. */
-- case 393: value = 395; break; /* ursra --> sli. */
-- case 395: value = 397; break; /* sli --> uqshl. */
-- case 397: return NULL; /* uqshl --> NULL. */
-- case 840: value = 841; break; /* fmadd --> fmadd. */
-- case 841: return NULL; /* fmadd --> NULL. */
-- case 844: value = 845; break; /* fnmadd --> fnmadd. */
-- case 845: return NULL; /* fnmadd --> NULL. */
-- case 133: value = 374; break; /* movi --> shrn. */
-- case 374: value = 375; break; /* shrn --> shrn2. */
-- case 375: value = 382; break; /* shrn2 --> sshll. */
-- case 382: value = 384; break; /* sshll --> sshll2. */
-- case 384: return NULL; /* sshll2 --> NULL. */
-- case 141: value = 398; break; /* mvni --> sqshrun. */
-- case 398: value = 399; break; /* sqshrun --> sqshrun2. */
-- case 399: value = 406; break; /* sqshrun2 --> ushll. */
-- case 406: value = 408; break; /* ushll --> ushll2. */
-- case 408: return NULL; /* ushll2 --> NULL. */
-- case 134: value = 378; break; /* orr --> sqshrn. */
-- case 378: value = 379; break; /* sqshrn --> sqshrn2. */
-- case 379: return NULL; /* sqshrn2 --> NULL. */
-- case 142: value = 402; break; /* bic --> uqshrn. */
-- case 402: value = 403; break; /* uqshrn --> uqshrn2. */
-- case 403: return NULL; /* uqshrn2 --> NULL. */
-- case 136: value = 386; break; /* movi --> scvtf. */
-- case 386: value = 387; break; /* scvtf --> scvtf. */
-- case 387: value = 1990; break; /* scvtf --> sdot. */
-- case 1990: return NULL; /* sdot --> NULL. */
-- case 144: value = 145; break; /* movi --> movi. */
-- case 145: value = 410; break; /* movi --> ucvtf. */
-- case 410: value = 411; break; /* ucvtf --> ucvtf. */
-- case 411: value = 1989; break; /* ucvtf --> udot. */
-- case 1989: return NULL; /* udot --> NULL. */
-- case 138: value = 388; break; /* fmov --> fcvtzs. */
-- case 388: value = 389; break; /* fcvtzs --> fcvtzs. */
-- case 389: return NULL; /* fcvtzs --> NULL. */
-- case 412: value = 413; break; /* fcvtzu --> fcvtzu. */
-- case 413: return NULL; /* fcvtzu --> NULL. */
-- case 842: value = 843; break; /* fmsub --> fmsub. */
-- case 843: return NULL; /* fmsub --> NULL. */
-- case 846: value = 847; break; /* fnmsub --> fnmsub. */
-- case 847: return NULL; /* fnmsub --> NULL. */
-- case 592: value = 593; break; /* scvtf --> scvtf. */
-- case 593: return NULL; /* scvtf --> NULL. */
-- case 594: value = 595; break; /* fcvtzs --> fcvtzs. */
-- case 595: return NULL; /* fcvtzs --> NULL. */
-- case 608: value = 609; break; /* ucvtf --> ucvtf. */
-- case 609: return NULL; /* ucvtf --> NULL. */
-- case 610: value = 611; break; /* fcvtzu --> fcvtzu. */
-- case 611: return NULL; /* fcvtzu --> NULL. */
-+ case 768: value = 769; break; /* fcvtns --> fcvtns. */
-+ case 769: return NULL; /* fcvtns --> NULL. */
-+ case 788: value = 789; break; /* fcvtms --> fcvtms. */
-+ case 789: return NULL; /* fcvtms --> NULL. */
-+ case 784: value = 785; break; /* fcvtps --> fcvtps. */
-+ case 785: return NULL; /* fcvtps --> NULL. */
-+ case 792: value = 793; break; /* fcvtzs --> fcvtzs. */
-+ case 793: return NULL; /* fcvtzs --> NULL. */
-+ case 776: value = 777; break; /* fcvtas --> fcvtas. */
-+ case 777: return NULL; /* fcvtas --> NULL. */
-+ case 772: value = 773; break; /* scvtf --> scvtf. */
-+ case 773: return NULL; /* scvtf --> NULL. */
-+ case 780: value = 781; break; /* fmov --> fmov. */
-+ case 781: return NULL; /* fmov --> NULL. */
-+ case 770: value = 771; break; /* fcvtnu --> fcvtnu. */
-+ case 771: return NULL; /* fcvtnu --> NULL. */
-+ case 790: value = 791; break; /* fcvtmu --> fcvtmu. */
-+ case 791: return NULL; /* fcvtmu --> NULL. */
-+ case 786: value = 787; break; /* fcvtpu --> fcvtpu. */
-+ case 787: return NULL; /* fcvtpu --> NULL. */
-+ case 794: value = 795; break; /* fcvtzu --> fcvtzu. */
-+ case 795: return NULL; /* fcvtzu --> NULL. */
-+ case 778: value = 779; break; /* fcvtau --> fcvtau. */
-+ case 779: return NULL; /* fcvtau --> NULL. */
-+ case 774: value = 775; break; /* ucvtf --> ucvtf. */
-+ case 775: return NULL; /* ucvtf --> NULL. */
-+ case 782: value = 783; break; /* fmov --> fmov. */
-+ case 783: return NULL; /* fmov --> NULL. */
-+ case 817: value = 818; break; /* fmov --> fmov. */
-+ case 818: return NULL; /* fmov --> NULL. */
-+ case 826: value = 827; break; /* frintn --> frintn. */
-+ case 827: return NULL; /* frintn --> NULL. */
-+ case 821: value = 822; break; /* fneg --> fneg. */
-+ case 822: return NULL; /* fneg --> NULL. */
-+ case 830: value = 831; break; /* frintm --> frintm. */
-+ case 831: return NULL; /* frintm --> NULL. */
-+ case 819: value = 820; break; /* fabs --> fabs. */
-+ case 820: return NULL; /* fabs --> NULL. */
-+ case 828: value = 829; break; /* frintp --> frintp. */
-+ case 829: return NULL; /* frintp --> NULL. */
-+ case 823: value = 824; break; /* fsqrt --> fsqrt. */
-+ case 824: return NULL; /* fsqrt --> NULL. */
-+ case 832: value = 833; break; /* frintz --> frintz. */
-+ case 833: return NULL; /* frintz --> NULL. */
-+ case 825: value = 2443; break; /* fcvt --> bfcvt. */
-+ case 2443: return NULL; /* bfcvt --> NULL. */
-+ case 834: value = 835; break; /* frinta --> frinta. */
-+ case 835: return NULL; /* frinta --> NULL. */
-+ case 836: value = 837; break; /* frintx --> frintx. */
-+ case 837: return NULL; /* frintx --> NULL. */
-+ case 838: value = 839; break; /* frinti --> frinti. */
-+ case 839: return NULL; /* frinti --> NULL. */
-+ case 803: value = 804; break; /* fcmp --> fcmp. */
-+ case 804: return NULL; /* fcmp --> NULL. */
-+ case 805: value = 806; break; /* fcmpe --> fcmpe. */
-+ case 806: return NULL; /* fcmpe --> NULL. */
-+ case 807: value = 808; break; /* fcmp --> fcmp. */
-+ case 808: return NULL; /* fcmp --> NULL. */
-+ case 809: value = 810; break; /* fcmpe --> fcmpe. */
-+ case 810: return NULL; /* fcmpe --> NULL. */
-+ case 866: value = 867; break; /* fmov --> fmov. */
-+ case 867: return NULL; /* fmov --> NULL. */
-+ case 840: value = 841; break; /* fmul --> fmul. */
-+ case 841: return NULL; /* fmul --> NULL. */
-+ case 856: value = 857; break; /* fnmul --> fnmul. */
-+ case 857: return NULL; /* fnmul --> NULL. */
-+ case 848: value = 849; break; /* fmax --> fmax. */
-+ case 849: return NULL; /* fmax --> NULL. */
-+ case 844: value = 845; break; /* fadd --> fadd. */
-+ case 845: return NULL; /* fadd --> NULL. */
-+ case 852: value = 853; break; /* fmaxnm --> fmaxnm. */
-+ case 853: return NULL; /* fmaxnm --> NULL. */
-+ case 842: value = 843; break; /* fdiv --> fdiv. */
-+ case 843: return NULL; /* fdiv --> NULL. */
-+ case 850: value = 851; break; /* fmin --> fmin. */
-+ case 851: return NULL; /* fmin --> NULL. */
-+ case 846: value = 847; break; /* fsub --> fsub. */
-+ case 847: return NULL; /* fsub --> NULL. */
-+ case 854: value = 855; break; /* fminnm --> fminnm. */
-+ case 855: return NULL; /* fminnm --> NULL. */
-+ case 799: value = 800; break; /* fccmp --> fccmp. */
-+ case 800: return NULL; /* fccmp --> NULL. */
-+ case 801: value = 802; break; /* fccmpe --> fccmpe. */
-+ case 802: return NULL; /* fccmpe --> NULL. */
-+ case 868: value = 869; break; /* fcsel --> fcsel. */
-+ case 869: return NULL; /* fcsel --> NULL. */
-+ case 133: value = 374; break; /* movi --> sshr. */
-+ case 374: value = 376; break; /* sshr --> srshr. */
-+ case 376: return NULL; /* srshr --> NULL. */
-+ case 141: value = 396; break; /* mvni --> ushr. */
-+ case 396: value = 398; break; /* ushr --> urshr. */
-+ case 398: value = 400; break; /* urshr --> sri. */
-+ case 400: value = 402; break; /* sri --> sqshlu. */
-+ case 402: return NULL; /* sqshlu --> NULL. */
-+ case 134: value = 375; break; /* orr --> ssra. */
-+ case 375: value = 377; break; /* ssra --> srsra. */
-+ case 377: value = 378; break; /* srsra --> shl. */
-+ case 378: value = 379; break; /* shl --> sqshl. */
-+ case 379: return NULL; /* sqshl --> NULL. */
-+ case 142: value = 397; break; /* bic --> usra. */
-+ case 397: value = 399; break; /* usra --> ursra. */
-+ case 399: value = 401; break; /* ursra --> sli. */
-+ case 401: value = 403; break; /* sli --> uqshl. */
-+ case 403: return NULL; /* uqshl --> NULL. */
-+ case 858: value = 859; break; /* fmadd --> fmadd. */
-+ case 859: return NULL; /* fmadd --> NULL. */
-+ case 862: value = 863; break; /* fnmadd --> fnmadd. */
-+ case 863: return NULL; /* fnmadd --> NULL. */
-+ case 135: value = 380; break; /* movi --> shrn. */
-+ case 380: value = 381; break; /* shrn --> shrn2. */
-+ case 381: value = 388; break; /* shrn2 --> sshll. */
-+ case 388: value = 390; break; /* sshll --> sshll2. */
-+ case 390: return NULL; /* sshll2 --> NULL. */
-+ case 143: value = 404; break; /* mvni --> sqshrun. */
-+ case 404: value = 405; break; /* sqshrun --> sqshrun2. */
-+ case 405: value = 412; break; /* sqshrun2 --> ushll. */
-+ case 412: value = 414; break; /* ushll --> ushll2. */
-+ case 414: return NULL; /* ushll2 --> NULL. */
-+ case 136: value = 384; break; /* orr --> sqshrn. */
-+ case 384: value = 385; break; /* sqshrn --> sqshrn2. */
-+ case 385: return NULL; /* sqshrn2 --> NULL. */
-+ case 144: value = 408; break; /* bic --> uqshrn. */
-+ case 408: value = 409; break; /* uqshrn --> uqshrn2. */
-+ case 409: return NULL; /* uqshrn2 --> NULL. */
-+ case 138: value = 392; break; /* movi --> scvtf. */
-+ case 392: value = 393; break; /* scvtf --> scvtf. */
-+ case 393: return NULL; /* scvtf --> NULL. */
-+ case 146: value = 147; break; /* movi --> movi. */
-+ case 147: value = 416; break; /* movi --> ucvtf. */
-+ case 416: value = 417; break; /* ucvtf --> ucvtf. */
-+ case 417: return NULL; /* ucvtf --> NULL. */
-+ case 140: value = 394; break; /* fmov --> fcvtzs. */
-+ case 394: value = 395; break; /* fcvtzs --> fcvtzs. */
-+ case 395: return NULL; /* fcvtzs --> NULL. */
-+ case 418: value = 419; break; /* fcvtzu --> fcvtzu. */
-+ case 419: return NULL; /* fcvtzu --> NULL. */
-+ case 860: value = 861; break; /* fmsub --> fmsub. */
-+ case 861: return NULL; /* fmsub --> NULL. */
-+ case 864: value = 865; break; /* fnmsub --> fnmsub. */
-+ case 865: return NULL; /* fnmsub --> NULL. */
-+ case 598: value = 599; break; /* scvtf --> scvtf. */
-+ case 599: return NULL; /* scvtf --> NULL. */
-+ case 600: value = 601; break; /* fcvtzs --> fcvtzs. */
-+ case 601: return NULL; /* fcvtzs --> NULL. */
-+ case 614: value = 615; break; /* ucvtf --> ucvtf. */
-+ case 615: return NULL; /* ucvtf --> NULL. */
-+ case 616: value = 617; break; /* fcvtzu --> fcvtzu. */
-+ case 617: return NULL; /* fcvtzu --> NULL. */
- default: return NULL;
- }
-
-@@ -19350,124 +23477,129 @@ aarch64_find_alias_opcode (const aarch64
- case 12: value = 13; break; /* add --> mov. */
- case 14: value = 15; break; /* adds --> cmn. */
- case 17: value = 18; break; /* subs --> cmp. */
-- case 20: value = 21; break; /* adds --> cmn. */
-- case 22: value = 23; break; /* sub --> neg. */
-- case 24: value = 26; break; /* subs --> negs. */
-- case 150: value = 151; break; /* umov --> mov. */
-- case 152: value = 153; break; /* ins --> mov. */
-+ case 22: value = 23; break; /* adds --> cmn. */
-+ case 24: value = 25; break; /* sub --> neg. */
-+ case 26: value = 27; break; /* subs --> cmp. */
-+ case 152: value = 153; break; /* umov --> mov. */
- case 154: value = 155; break; /* ins --> mov. */
-- case 236: value = 237; break; /* not --> mvn. */
-- case 311: value = 312; break; /* orr --> mov. */
-- case 382: value = 383; break; /* sshll --> sxtl. */
-- case 384: value = 385; break; /* sshll2 --> sxtl2. */
-- case 406: value = 407; break; /* ushll --> uxtl. */
-- case 408: value = 409; break; /* ushll2 --> uxtl2. */
-- case 529: value = 530; break; /* dup --> mov. */
-- case 612: value = 617; break; /* sbfm --> sxtw. */
-- case 619: value = 621; break; /* bfm --> bfc. */
-- case 623: value = 627; break; /* ubfm --> uxth. */
-- case 657: value = 659; break; /* csinc --> cset. */
-- case 660: value = 662; break; /* csinv --> csetm. */
-- case 663: value = 664; break; /* csneg --> cneg. */
-- case 682: value = 682; break; /* rev --> rev. */
-- case 707: value = 708; break; /* lslv --> lsl. */
-- case 709: value = 710; break; /* lsrv --> lsr. */
-- case 711: value = 712; break; /* asrv --> asr. */
-- case 713: value = 714; break; /* rorv --> ror. */
-- case 724: value = 725; break; /* madd --> mul. */
-- case 726: value = 727; break; /* msub --> mneg. */
-- case 728: value = 729; break; /* smaddl --> smull. */
-- case 730: value = 731; break; /* smsubl --> smnegl. */
-- case 733: value = 734; break; /* umaddl --> umull. */
-- case 735: value = 736; break; /* umsubl --> umnegl. */
-- case 746: value = 747; break; /* extr --> ror. */
-- case 959: value = 960; break; /* and --> bic. */
-- case 961: value = 962; break; /* orr --> mov. */
-- case 964: value = 965; break; /* ands --> tst. */
-- case 968: value = 970; break; /* orr --> uxtw. */
-- case 971: value = 972; break; /* orn --> mvn. */
-- case 975: value = 976; break; /* ands --> tst. */
-- case 1006: value = 1102; break; /* ldaddb --> staddb. */
-- case 1007: value = 1103; break; /* ldaddh --> staddh. */
-- case 1008: value = 1104; break; /* ldadd --> stadd. */
-- case 1010: value = 1105; break; /* ldaddlb --> staddlb. */
-- case 1013: value = 1106; break; /* ldaddlh --> staddlh. */
-- case 1016: value = 1107; break; /* ldaddl --> staddl. */
-- case 1018: value = 1108; break; /* ldclrb --> stclrb. */
-- case 1019: value = 1109; break; /* ldclrh --> stclrh. */
-- case 1020: value = 1110; break; /* ldclr --> stclr. */
-- case 1022: value = 1111; break; /* ldclrlb --> stclrlb. */
-- case 1025: value = 1112; break; /* ldclrlh --> stclrlh. */
-- case 1028: value = 1113; break; /* ldclrl --> stclrl. */
-- case 1030: value = 1114; break; /* ldeorb --> steorb. */
-- case 1031: value = 1115; break; /* ldeorh --> steorh. */
-- case 1032: value = 1116; break; /* ldeor --> steor. */
-- case 1034: value = 1117; break; /* ldeorlb --> steorlb. */
-- case 1037: value = 1118; break; /* ldeorlh --> steorlh. */
-- case 1040: value = 1119; break; /* ldeorl --> steorl. */
-- case 1042: value = 1120; break; /* ldsetb --> stsetb. */
-- case 1043: value = 1121; break; /* ldseth --> stseth. */
-- case 1044: value = 1122; break; /* ldset --> stset. */
-- case 1046: value = 1123; break; /* ldsetlb --> stsetlb. */
-- case 1049: value = 1124; break; /* ldsetlh --> stsetlh. */
-- case 1052: value = 1125; break; /* ldsetl --> stsetl. */
-- case 1054: value = 1126; break; /* ldsmaxb --> stsmaxb. */
-- case 1055: value = 1127; break; /* ldsmaxh --> stsmaxh. */
-- case 1056: value = 1128; break; /* ldsmax --> stsmax. */
-- case 1058: value = 1129; break; /* ldsmaxlb --> stsmaxlb. */
-- case 1061: value = 1130; break; /* ldsmaxlh --> stsmaxlh. */
-- case 1064: value = 1131; break; /* ldsmaxl --> stsmaxl. */
-- case 1066: value = 1132; break; /* ldsminb --> stsminb. */
-- case 1067: value = 1133; break; /* ldsminh --> stsminh. */
-- case 1068: value = 1134; break; /* ldsmin --> stsmin. */
-- case 1070: value = 1135; break; /* ldsminlb --> stsminlb. */
-- case 1073: value = 1136; break; /* ldsminlh --> stsminlh. */
-- case 1076: value = 1137; break; /* ldsminl --> stsminl. */
-- case 1078: value = 1138; break; /* ldumaxb --> stumaxb. */
-- case 1079: value = 1139; break; /* ldumaxh --> stumaxh. */
-- case 1080: value = 1140; break; /* ldumax --> stumax. */
-- case 1082: value = 1141; break; /* ldumaxlb --> stumaxlb. */
-- case 1085: value = 1142; break; /* ldumaxlh --> stumaxlh. */
-- case 1088: value = 1143; break; /* ldumaxl --> stumaxl. */
-- case 1090: value = 1144; break; /* lduminb --> stuminb. */
-- case 1091: value = 1145; break; /* lduminh --> stuminh. */
-- case 1092: value = 1146; break; /* ldumin --> stumin. */
-- case 1094: value = 1147; break; /* lduminlb --> stuminlb. */
-- case 1097: value = 1148; break; /* lduminlh --> stuminlh. */
-- case 1100: value = 1149; break; /* lduminl --> stuminl. */
-- case 1150: value = 1151; break; /* movn --> mov. */
-- case 1152: value = 1153; break; /* movz --> mov. */
-- case 1158: value = 1192; break; /* hint --> autibsp. */
-- case 1177: value = 1181; break; /* sys --> tlbi. */
-- case 1240: value = 1974; break; /* and --> bic. */
-- case 1242: value = 1223; break; /* and --> mov. */
-- case 1243: value = 1227; break; /* ands --> movs. */
-- case 1278: value = 1975; break; /* cmpge --> cmple. */
-- case 1281: value = 1978; break; /* cmpgt --> cmplt. */
-- case 1283: value = 1976; break; /* cmphi --> cmplo. */
-- case 1286: value = 1977; break; /* cmphs --> cmpls. */
-- case 1308: value = 1220; break; /* cpy --> mov. */
-- case 1309: value = 1222; break; /* cpy --> mov. */
-- case 1310: value = 1985; break; /* cpy --> fmov. */
-- case 1322: value = 1215; break; /* dup --> mov. */
-- case 1323: value = 1217; break; /* dup --> mov. */
-- case 1324: value = 1984; break; /* dup --> fmov. */
-- case 1325: value = 1218; break; /* dupm --> mov. */
-- case 1327: value = 1979; break; /* eor --> eon. */
-- case 1329: value = 1228; break; /* eor --> not. */
-- case 1330: value = 1229; break; /* eors --> nots. */
-- case 1335: value = 1980; break; /* facge --> facle. */
-- case 1336: value = 1981; break; /* facgt --> faclt. */
-- case 1349: value = 1982; break; /* fcmge --> fcmle. */
-- case 1351: value = 1983; break; /* fcmgt --> fcmlt. */
-- case 1357: value = 1212; break; /* fcpy --> fmov. */
-- case 1380: value = 1211; break; /* fdup --> fmov. */
-- case 1695: value = 1213; break; /* orr --> mov. */
-- case 1696: value = 1986; break; /* orr --> orn. */
-- case 1698: value = 1216; break; /* orr --> mov. */
-- case 1699: value = 1226; break; /* orrs --> movs. */
-- case 1761: value = 1221; break; /* sel --> mov. */
-- case 1762: value = 1224; break; /* sel --> mov. */
-+ case 156: value = 157; break; /* ins --> mov. */
-+ case 242: value = 243; break; /* not --> mvn. */
-+ case 317: value = 318; break; /* orr --> mov. */
-+ case 388: value = 389; break; /* sshll --> sxtl. */
-+ case 390: value = 391; break; /* sshll2 --> sxtl2. */
-+ case 412: value = 413; break; /* ushll --> uxtl. */
-+ case 414: value = 415; break; /* ushll2 --> uxtl2. */
-+ case 535: value = 536; break; /* dup --> mov. */
-+ case 618: value = 623; break; /* sbfm --> sxtw. */
-+ case 625: value = 627; break; /* bfm --> bfc. */
-+ case 629: value = 633; break; /* ubfm --> uxth. */
-+ case 663: value = 665; break; /* csinc --> cset. */
-+ case 666: value = 668; break; /* csinv --> csetm. */
-+ case 669: value = 670; break; /* csneg --> cneg. */
-+ case 688: value = 688; break; /* rev --> rev. */
-+ case 713: value = 714; break; /* lslv --> lsl. */
-+ case 715: value = 716; break; /* lsrv --> lsr. */
-+ case 717: value = 718; break; /* asrv --> asr. */
-+ case 719: value = 720; break; /* rorv --> ror. */
-+ case 722: value = 723; break; /* subps --> cmpp. */
-+ case 735: value = 736; break; /* madd --> mul. */
-+ case 737: value = 738; break; /* msub --> mneg. */
-+ case 739: value = 740; break; /* smaddl --> smull. */
-+ case 741: value = 742; break; /* smsubl --> smnegl. */
-+ case 744: value = 745; break; /* umaddl --> umull. */
-+ case 746: value = 747; break; /* umsubl --> umnegl. */
-+ case 758: value = 759; break; /* extr --> ror. */
-+ case 995: value = 996; break; /* and --> bic. */
-+ case 997: value = 998; break; /* orr --> mov. */
-+ case 1000: value = 1001; break; /* ands --> tst. */
-+ case 1004: value = 1006; break; /* orr --> uxtw. */
-+ case 1007: value = 1008; break; /* orn --> mvn. */
-+ case 1011: value = 1012; break; /* ands --> tst. */
-+ case 1042: value = 1138; break; /* ldaddb --> staddb. */
-+ case 1043: value = 1139; break; /* ldaddh --> staddh. */
-+ case 1044: value = 1140; break; /* ldadd --> stadd. */
-+ case 1046: value = 1141; break; /* ldaddlb --> staddlb. */
-+ case 1049: value = 1142; break; /* ldaddlh --> staddlh. */
-+ case 1052: value = 1143; break; /* ldaddl --> staddl. */
-+ case 1054: value = 1144; break; /* ldclrb --> stclrb. */
-+ case 1055: value = 1145; break; /* ldclrh --> stclrh. */
-+ case 1056: value = 1146; break; /* ldclr --> stclr. */
-+ case 1058: value = 1147; break; /* ldclrlb --> stclrlb. */
-+ case 1061: value = 1148; break; /* ldclrlh --> stclrlh. */
-+ case 1064: value = 1149; break; /* ldclrl --> stclrl. */
-+ case 1066: value = 1150; break; /* ldeorb --> steorb. */
-+ case 1067: value = 1151; break; /* ldeorh --> steorh. */
-+ case 1068: value = 1152; break; /* ldeor --> steor. */
-+ case 1070: value = 1153; break; /* ldeorlb --> steorlb. */
-+ case 1073: value = 1154; break; /* ldeorlh --> steorlh. */
-+ case 1076: value = 1155; break; /* ldeorl --> steorl. */
-+ case 1078: value = 1156; break; /* ldsetb --> stsetb. */
-+ case 1079: value = 1157; break; /* ldseth --> stseth. */
-+ case 1080: value = 1158; break; /* ldset --> stset. */
-+ case 1082: value = 1159; break; /* ldsetlb --> stsetlb. */
-+ case 1085: value = 1160; break; /* ldsetlh --> stsetlh. */
-+ case 1088: value = 1161; break; /* ldsetl --> stsetl. */
-+ case 1090: value = 1162; break; /* ldsmaxb --> stsmaxb. */
-+ case 1091: value = 1163; break; /* ldsmaxh --> stsmaxh. */
-+ case 1092: value = 1164; break; /* ldsmax --> stsmax. */
-+ case 1094: value = 1165; break; /* ldsmaxlb --> stsmaxlb. */
-+ case 1097: value = 1166; break; /* ldsmaxlh --> stsmaxlh. */
-+ case 1100: value = 1167; break; /* ldsmaxl --> stsmaxl. */
-+ case 1102: value = 1168; break; /* ldsminb --> stsminb. */
-+ case 1103: value = 1169; break; /* ldsminh --> stsminh. */
-+ case 1104: value = 1170; break; /* ldsmin --> stsmin. */
-+ case 1106: value = 1171; break; /* ldsminlb --> stsminlb. */
-+ case 1109: value = 1172; break; /* ldsminlh --> stsminlh. */
-+ case 1112: value = 1173; break; /* ldsminl --> stsminl. */
-+ case 1114: value = 1174; break; /* ldumaxb --> stumaxb. */
-+ case 1115: value = 1175; break; /* ldumaxh --> stumaxh. */
-+ case 1116: value = 1176; break; /* ldumax --> stumax. */
-+ case 1118: value = 1177; break; /* ldumaxlb --> stumaxlb. */
-+ case 1121: value = 1178; break; /* ldumaxlh --> stumaxlh. */
-+ case 1124: value = 1179; break; /* ldumaxl --> stumaxl. */
-+ case 1126: value = 1180; break; /* lduminb --> stuminb. */
-+ case 1127: value = 1181; break; /* lduminh --> stuminh. */
-+ case 1128: value = 1182; break; /* ldumin --> stumin. */
-+ case 1130: value = 1183; break; /* lduminlb --> stuminlb. */
-+ case 1133: value = 1184; break; /* lduminlh --> stuminlh. */
-+ case 1136: value = 1185; break; /* lduminl --> stuminl. */
-+ case 1186: value = 1187; break; /* movn --> mov. */
-+ case 1188: value = 1189; break; /* movz --> mov. */
-+ case 1198: value = 1246; break; /* hint --> autibsp. */
-+ case 1217: value = 1221; break; /* dsb --> pssbb. */
-+ case 1218: value = 1218; break; /* dsb --> dsb. */
-+ case 1225: value = 1234; break; /* sys --> cpp. */
-+ case 1230: value = 1230; break; /* wfet --> wfet. */
-+ case 1231: value = 1231; break; /* wfit --> wfit. */
-+ case 1294: value = 2044; break; /* and --> bic. */
-+ case 1296: value = 1277; break; /* and --> mov. */
-+ case 1297: value = 1281; break; /* ands --> movs. */
-+ case 1332: value = 2045; break; /* cmpge --> cmple. */
-+ case 1335: value = 2048; break; /* cmpgt --> cmplt. */
-+ case 1337: value = 2046; break; /* cmphi --> cmplo. */
-+ case 1340: value = 2047; break; /* cmphs --> cmpls. */
-+ case 1362: value = 1274; break; /* cpy --> mov. */
-+ case 1363: value = 1276; break; /* cpy --> mov. */
-+ case 1364: value = 2055; break; /* cpy --> fmov. */
-+ case 1376: value = 1269; break; /* dup --> mov. */
-+ case 1377: value = 1271; break; /* dup --> mov. */
-+ case 1378: value = 2054; break; /* dup --> fmov. */
-+ case 1379: value = 1272; break; /* dupm --> mov. */
-+ case 1381: value = 2049; break; /* eor --> eon. */
-+ case 1383: value = 1282; break; /* eor --> not. */
-+ case 1384: value = 1283; break; /* eors --> nots. */
-+ case 1389: value = 2050; break; /* facge --> facle. */
-+ case 1390: value = 2051; break; /* facgt --> faclt. */
-+ case 1403: value = 2052; break; /* fcmge --> fcmle. */
-+ case 1405: value = 2053; break; /* fcmgt --> fcmlt. */
-+ case 1411: value = 1266; break; /* fcpy --> fmov. */
-+ case 1434: value = 1265; break; /* fdup --> fmov. */
-+ case 1765: value = 1267; break; /* orr --> mov. */
-+ case 1766: value = 2056; break; /* orr --> orn. */
-+ case 1768: value = 1270; break; /* orr --> mov. */
-+ case 1769: value = 1280; break; /* orrs --> movs. */
-+ case 1831: value = 1275; break; /* sel --> mov. */
-+ case 1832: value = 1278; break; /* sel --> mov. */
- default: return NULL;
- }
-
-@@ -19489,177 +23621,187 @@ aarch64_find_next_alias_opcode (const aa
- case 13: value = 12; break; /* mov --> add. */
- case 15: value = 14; break; /* cmn --> adds. */
- case 18: value = 17; break; /* cmp --> subs. */
-- case 21: value = 20; break; /* cmn --> adds. */
-- case 23: value = 22; break; /* neg --> sub. */
-- case 26: value = 25; break; /* negs --> cmp. */
-- case 25: value = 24; break; /* cmp --> subs. */
-- case 151: value = 150; break; /* mov --> umov. */
-- case 153: value = 152; break; /* mov --> ins. */
-+ case 23: value = 22; break; /* cmn --> adds. */
-+ case 25: value = 24; break; /* neg --> sub. */
-+ case 27: value = 28; break; /* cmp --> negs. */
-+ case 28: value = 26; break; /* negs --> subs. */
-+ case 153: value = 152; break; /* mov --> umov. */
- case 155: value = 154; break; /* mov --> ins. */
-- case 237: value = 236; break; /* mvn --> not. */
-- case 312: value = 311; break; /* mov --> orr. */
-- case 383: value = 382; break; /* sxtl --> sshll. */
-- case 385: value = 384; break; /* sxtl2 --> sshll2. */
-- case 407: value = 406; break; /* uxtl --> ushll. */
-- case 409: value = 408; break; /* uxtl2 --> ushll2. */
-- case 530: value = 529; break; /* mov --> dup. */
-- case 617: value = 616; break; /* sxtw --> sxth. */
-- case 616: value = 615; break; /* sxth --> sxtb. */
-- case 615: value = 618; break; /* sxtb --> asr. */
-- case 618: value = 614; break; /* asr --> sbfx. */
-- case 614: value = 613; break; /* sbfx --> sbfiz. */
-- case 613: value = 612; break; /* sbfiz --> sbfm. */
-- case 621: value = 622; break; /* bfc --> bfxil. */
-- case 622: value = 620; break; /* bfxil --> bfi. */
-- case 620: value = 619; break; /* bfi --> bfm. */
-- case 627: value = 626; break; /* uxth --> uxtb. */
-- case 626: value = 629; break; /* uxtb --> lsr. */
-- case 629: value = 628; break; /* lsr --> lsl. */
-- case 628: value = 625; break; /* lsl --> ubfx. */
-- case 625: value = 624; break; /* ubfx --> ubfiz. */
-- case 624: value = 623; break; /* ubfiz --> ubfm. */
-- case 659: value = 658; break; /* cset --> cinc. */
-- case 658: value = 657; break; /* cinc --> csinc. */
-- case 662: value = 661; break; /* csetm --> cinv. */
-- case 661: value = 660; break; /* cinv --> csinv. */
-- case 664: value = 663; break; /* cneg --> csneg. */
-- case 682: value = 683; break; /* rev --> rev64. */
-- case 708: value = 707; break; /* lsl --> lslv. */
-- case 710: value = 709; break; /* lsr --> lsrv. */
-- case 712: value = 711; break; /* asr --> asrv. */
-- case 714: value = 713; break; /* ror --> rorv. */
-- case 725: value = 724; break; /* mul --> madd. */
-- case 727: value = 726; break; /* mneg --> msub. */
-- case 729: value = 728; break; /* smull --> smaddl. */
-- case 731: value = 730; break; /* smnegl --> smsubl. */
-- case 734: value = 733; break; /* umull --> umaddl. */
-- case 736: value = 735; break; /* umnegl --> umsubl. */
-- case 747: value = 746; break; /* ror --> extr. */
-- case 960: value = 959; break; /* bic --> and. */
-- case 962: value = 961; break; /* mov --> orr. */
-- case 965: value = 964; break; /* tst --> ands. */
-- case 970: value = 969; break; /* uxtw --> mov. */
-- case 969: value = 968; break; /* mov --> orr. */
-- case 972: value = 971; break; /* mvn --> orn. */
-- case 976: value = 975; break; /* tst --> ands. */
-- case 1102: value = 1006; break; /* staddb --> ldaddb. */
-- case 1103: value = 1007; break; /* staddh --> ldaddh. */
-- case 1104: value = 1008; break; /* stadd --> ldadd. */
-- case 1105: value = 1010; break; /* staddlb --> ldaddlb. */
-- case 1106: value = 1013; break; /* staddlh --> ldaddlh. */
-- case 1107: value = 1016; break; /* staddl --> ldaddl. */
-- case 1108: value = 1018; break; /* stclrb --> ldclrb. */
-- case 1109: value = 1019; break; /* stclrh --> ldclrh. */
-- case 1110: value = 1020; break; /* stclr --> ldclr. */
-- case 1111: value = 1022; break; /* stclrlb --> ldclrlb. */
-- case 1112: value = 1025; break; /* stclrlh --> ldclrlh. */
-- case 1113: value = 1028; break; /* stclrl --> ldclrl. */
-- case 1114: value = 1030; break; /* steorb --> ldeorb. */
-- case 1115: value = 1031; break; /* steorh --> ldeorh. */
-- case 1116: value = 1032; break; /* steor --> ldeor. */
-- case 1117: value = 1034; break; /* steorlb --> ldeorlb. */
-- case 1118: value = 1037; break; /* steorlh --> ldeorlh. */
-- case 1119: value = 1040; break; /* steorl --> ldeorl. */
-- case 1120: value = 1042; break; /* stsetb --> ldsetb. */
-- case 1121: value = 1043; break; /* stseth --> ldseth. */
-- case 1122: value = 1044; break; /* stset --> ldset. */
-- case 1123: value = 1046; break; /* stsetlb --> ldsetlb. */
-- case 1124: value = 1049; break; /* stsetlh --> ldsetlh. */
-- case 1125: value = 1052; break; /* stsetl --> ldsetl. */
-- case 1126: value = 1054; break; /* stsmaxb --> ldsmaxb. */
-- case 1127: value = 1055; break; /* stsmaxh --> ldsmaxh. */
-- case 1128: value = 1056; break; /* stsmax --> ldsmax. */
-- case 1129: value = 1058; break; /* stsmaxlb --> ldsmaxlb. */
-- case 1130: value = 1061; break; /* stsmaxlh --> ldsmaxlh. */
-- case 1131: value = 1064; break; /* stsmaxl --> ldsmaxl. */
-- case 1132: value = 1066; break; /* stsminb --> ldsminb. */
-- case 1133: value = 1067; break; /* stsminh --> ldsminh. */
-- case 1134: value = 1068; break; /* stsmin --> ldsmin. */
-- case 1135: value = 1070; break; /* stsminlb --> ldsminlb. */
-- case 1136: value = 1073; break; /* stsminlh --> ldsminlh. */
-- case 1137: value = 1076; break; /* stsminl --> ldsminl. */
-- case 1138: value = 1078; break; /* stumaxb --> ldumaxb. */
-- case 1139: value = 1079; break; /* stumaxh --> ldumaxh. */
-- case 1140: value = 1080; break; /* stumax --> ldumax. */
-- case 1141: value = 1082; break; /* stumaxlb --> ldumaxlb. */
-- case 1142: value = 1085; break; /* stumaxlh --> ldumaxlh. */
-- case 1143: value = 1088; break; /* stumaxl --> ldumaxl. */
-- case 1144: value = 1090; break; /* stuminb --> lduminb. */
-- case 1145: value = 1091; break; /* stuminh --> lduminh. */
-- case 1146: value = 1092; break; /* stumin --> ldumin. */
-- case 1147: value = 1094; break; /* stuminlb --> lduminlb. */
-- case 1148: value = 1097; break; /* stuminlh --> lduminlh. */
-- case 1149: value = 1100; break; /* stuminl --> lduminl. */
-- case 1151: value = 1150; break; /* mov --> movn. */
-- case 1153: value = 1152; break; /* mov --> movz. */
-- case 1192: value = 1191; break; /* autibsp --> autibz. */
-- case 1191: value = 1190; break; /* autibz --> autiasp. */
-- case 1190: value = 1189; break; /* autiasp --> autiaz. */
-- case 1189: value = 1188; break; /* autiaz --> pacibsp. */
-- case 1188: value = 1187; break; /* pacibsp --> pacibz. */
-- case 1187: value = 1186; break; /* pacibz --> paciasp. */
-- case 1186: value = 1185; break; /* paciasp --> paciaz. */
-- case 1185: value = 1172; break; /* paciaz --> psb. */
-- case 1172: value = 1171; break; /* psb --> esb. */
-- case 1171: value = 1170; break; /* esb --> autib1716. */
-- case 1170: value = 1169; break; /* autib1716 --> autia1716. */
-- case 1169: value = 1168; break; /* autia1716 --> pacib1716. */
-- case 1168: value = 1167; break; /* pacib1716 --> pacia1716. */
-- case 1167: value = 1166; break; /* pacia1716 --> xpaclri. */
-- case 1166: value = 1165; break; /* xpaclri --> sevl. */
-- case 1165: value = 1164; break; /* sevl --> sev. */
-- case 1164: value = 1163; break; /* sev --> wfi. */
-- case 1163: value = 1162; break; /* wfi --> wfe. */
-- case 1162: value = 1161; break; /* wfe --> yield. */
-- case 1161: value = 1160; break; /* yield --> csdb. */
-- case 1160: value = 1159; break; /* csdb --> nop. */
-- case 1159: value = 1158; break; /* nop --> hint. */
-- case 1181: value = 1180; break; /* tlbi --> ic. */
-- case 1180: value = 1179; break; /* ic --> dc. */
-- case 1179: value = 1178; break; /* dc --> at. */
-- case 1178: value = 1177; break; /* at --> sys. */
-- case 1974: value = 1240; break; /* bic --> and. */
-- case 1223: value = 1242; break; /* mov --> and. */
-- case 1227: value = 1243; break; /* movs --> ands. */
-- case 1975: value = 1278; break; /* cmple --> cmpge. */
-- case 1978: value = 1281; break; /* cmplt --> cmpgt. */
-- case 1976: value = 1283; break; /* cmplo --> cmphi. */
-- case 1977: value = 1286; break; /* cmpls --> cmphs. */
-- case 1220: value = 1308; break; /* mov --> cpy. */
-- case 1222: value = 1309; break; /* mov --> cpy. */
-- case 1985: value = 1225; break; /* fmov --> mov. */
-- case 1225: value = 1310; break; /* mov --> cpy. */
-- case 1215: value = 1322; break; /* mov --> dup. */
-- case 1217: value = 1214; break; /* mov --> mov. */
-- case 1214: value = 1323; break; /* mov --> dup. */
-- case 1984: value = 1219; break; /* fmov --> mov. */
-- case 1219: value = 1324; break; /* mov --> dup. */
-- case 1218: value = 1325; break; /* mov --> dupm. */
-- case 1979: value = 1327; break; /* eon --> eor. */
-- case 1228: value = 1329; break; /* not --> eor. */
-- case 1229: value = 1330; break; /* nots --> eors. */
-- case 1980: value = 1335; break; /* facle --> facge. */
-- case 1981: value = 1336; break; /* faclt --> facgt. */
-- case 1982: value = 1349; break; /* fcmle --> fcmge. */
-- case 1983: value = 1351; break; /* fcmlt --> fcmgt. */
-- case 1212: value = 1357; break; /* fmov --> fcpy. */
-- case 1211: value = 1380; break; /* fmov --> fdup. */
-- case 1213: value = 1695; break; /* mov --> orr. */
-- case 1986: value = 1696; break; /* orn --> orr. */
-- case 1216: value = 1698; break; /* mov --> orr. */
-- case 1226: value = 1699; break; /* movs --> orrs. */
-- case 1221: value = 1761; break; /* mov --> sel. */
-- case 1224: value = 1762; break; /* mov --> sel. */
-+ case 157: value = 156; break; /* mov --> ins. */
-+ case 243: value = 242; break; /* mvn --> not. */
-+ case 318: value = 317; break; /* mov --> orr. */
-+ case 389: value = 388; break; /* sxtl --> sshll. */
-+ case 391: value = 390; break; /* sxtl2 --> sshll2. */
-+ case 413: value = 412; break; /* uxtl --> ushll. */
-+ case 415: value = 414; break; /* uxtl2 --> ushll2. */
-+ case 536: value = 535; break; /* mov --> dup. */
-+ case 623: value = 622; break; /* sxtw --> sxth. */
-+ case 622: value = 621; break; /* sxth --> sxtb. */
-+ case 621: value = 624; break; /* sxtb --> asr. */
-+ case 624: value = 620; break; /* asr --> sbfx. */
-+ case 620: value = 619; break; /* sbfx --> sbfiz. */
-+ case 619: value = 618; break; /* sbfiz --> sbfm. */
-+ case 627: value = 628; break; /* bfc --> bfxil. */
-+ case 628: value = 626; break; /* bfxil --> bfi. */
-+ case 626: value = 625; break; /* bfi --> bfm. */
-+ case 633: value = 632; break; /* uxth --> uxtb. */
-+ case 632: value = 635; break; /* uxtb --> lsr. */
-+ case 635: value = 634; break; /* lsr --> lsl. */
-+ case 634: value = 631; break; /* lsl --> ubfx. */
-+ case 631: value = 630; break; /* ubfx --> ubfiz. */
-+ case 630: value = 629; break; /* ubfiz --> ubfm. */
-+ case 665: value = 664; break; /* cset --> cinc. */
-+ case 664: value = 663; break; /* cinc --> csinc. */
-+ case 668: value = 667; break; /* csetm --> cinv. */
-+ case 667: value = 666; break; /* cinv --> csinv. */
-+ case 670: value = 669; break; /* cneg --> csneg. */
-+ case 688: value = 689; break; /* rev --> rev64. */
-+ case 714: value = 713; break; /* lsl --> lslv. */
-+ case 716: value = 715; break; /* lsr --> lsrv. */
-+ case 718: value = 717; break; /* asr --> asrv. */
-+ case 720: value = 719; break; /* ror --> rorv. */
-+ case 723: value = 722; break; /* cmpp --> subps. */
-+ case 736: value = 735; break; /* mul --> madd. */
-+ case 738: value = 737; break; /* mneg --> msub. */
-+ case 740: value = 739; break; /* smull --> smaddl. */
-+ case 742: value = 741; break; /* smnegl --> smsubl. */
-+ case 745: value = 744; break; /* umull --> umaddl. */
-+ case 747: value = 746; break; /* umnegl --> umsubl. */
-+ case 759: value = 758; break; /* ror --> extr. */
-+ case 996: value = 995; break; /* bic --> and. */
-+ case 998: value = 997; break; /* mov --> orr. */
-+ case 1001: value = 1000; break; /* tst --> ands. */
-+ case 1006: value = 1005; break; /* uxtw --> mov. */
-+ case 1005: value = 1004; break; /* mov --> orr. */
-+ case 1008: value = 1007; break; /* mvn --> orn. */
-+ case 1012: value = 1011; break; /* tst --> ands. */
-+ case 1138: value = 1042; break; /* staddb --> ldaddb. */
-+ case 1139: value = 1043; break; /* staddh --> ldaddh. */
-+ case 1140: value = 1044; break; /* stadd --> ldadd. */
-+ case 1141: value = 1046; break; /* staddlb --> ldaddlb. */
-+ case 1142: value = 1049; break; /* staddlh --> ldaddlh. */
-+ case 1143: value = 1052; break; /* staddl --> ldaddl. */
-+ case 1144: value = 1054; break; /* stclrb --> ldclrb. */
-+ case 1145: value = 1055; break; /* stclrh --> ldclrh. */
-+ case 1146: value = 1056; break; /* stclr --> ldclr. */
-+ case 1147: value = 1058; break; /* stclrlb --> ldclrlb. */
-+ case 1148: value = 1061; break; /* stclrlh --> ldclrlh. */
-+ case 1149: value = 1064; break; /* stclrl --> ldclrl. */
-+ case 1150: value = 1066; break; /* steorb --> ldeorb. */
-+ case 1151: value = 1067; break; /* steorh --> ldeorh. */
-+ case 1152: value = 1068; break; /* steor --> ldeor. */
-+ case 1153: value = 1070; break; /* steorlb --> ldeorlb. */
-+ case 1154: value = 1073; break; /* steorlh --> ldeorlh. */
-+ case 1155: value = 1076; break; /* steorl --> ldeorl. */
-+ case 1156: value = 1078; break; /* stsetb --> ldsetb. */
-+ case 1157: value = 1079; break; /* stseth --> ldseth. */
-+ case 1158: value = 1080; break; /* stset --> ldset. */
-+ case 1159: value = 1082; break; /* stsetlb --> ldsetlb. */
-+ case 1160: value = 1085; break; /* stsetlh --> ldsetlh. */
-+ case 1161: value = 1088; break; /* stsetl --> ldsetl. */
-+ case 1162: value = 1090; break; /* stsmaxb --> ldsmaxb. */
-+ case 1163: value = 1091; break; /* stsmaxh --> ldsmaxh. */
-+ case 1164: value = 1092; break; /* stsmax --> ldsmax. */
-+ case 1165: value = 1094; break; /* stsmaxlb --> ldsmaxlb. */
-+ case 1166: value = 1097; break; /* stsmaxlh --> ldsmaxlh. */
-+ case 1167: value = 1100; break; /* stsmaxl --> ldsmaxl. */
-+ case 1168: value = 1102; break; /* stsminb --> ldsminb. */
-+ case 1169: value = 1103; break; /* stsminh --> ldsminh. */
-+ case 1170: value = 1104; break; /* stsmin --> ldsmin. */
-+ case 1171: value = 1106; break; /* stsminlb --> ldsminlb. */
-+ case 1172: value = 1109; break; /* stsminlh --> ldsminlh. */
-+ case 1173: value = 1112; break; /* stsminl --> ldsminl. */
-+ case 1174: value = 1114; break; /* stumaxb --> ldumaxb. */
-+ case 1175: value = 1115; break; /* stumaxh --> ldumaxh. */
-+ case 1176: value = 1116; break; /* stumax --> ldumax. */
-+ case 1177: value = 1118; break; /* stumaxlb --> ldumaxlb. */
-+ case 1178: value = 1121; break; /* stumaxlh --> ldumaxlh. */
-+ case 1179: value = 1124; break; /* stumaxl --> ldumaxl. */
-+ case 1180: value = 1126; break; /* stuminb --> lduminb. */
-+ case 1181: value = 1127; break; /* stuminh --> lduminh. */
-+ case 1182: value = 1128; break; /* stumin --> ldumin. */
-+ case 1183: value = 1130; break; /* stuminlb --> lduminlb. */
-+ case 1184: value = 1133; break; /* stuminlh --> lduminlh. */
-+ case 1185: value = 1136; break; /* stuminl --> lduminl. */
-+ case 1187: value = 1186; break; /* mov --> movn. */
-+ case 1189: value = 1188; break; /* mov --> movz. */
-+ case 1246: value = 1245; break; /* autibsp --> autibz. */
-+ case 1245: value = 1244; break; /* autibz --> autiasp. */
-+ case 1244: value = 1243; break; /* autiasp --> autiaz. */
-+ case 1243: value = 1242; break; /* autiaz --> pacibsp. */
-+ case 1242: value = 1241; break; /* pacibsp --> pacibz. */
-+ case 1241: value = 1240; break; /* pacibz --> paciasp. */
-+ case 1240: value = 1239; break; /* paciasp --> paciaz. */
-+ case 1239: value = 1215; break; /* paciaz --> tsb. */
-+ case 1215: value = 1214; break; /* tsb --> psb. */
-+ case 1214: value = 1213; break; /* psb --> esb. */
-+ case 1213: value = 1212; break; /* esb --> autib1716. */
-+ case 1212: value = 1211; break; /* autib1716 --> autia1716. */
-+ case 1211: value = 1210; break; /* autia1716 --> pacib1716. */
-+ case 1210: value = 1209; break; /* pacib1716 --> pacia1716. */
-+ case 1209: value = 1208; break; /* pacia1716 --> xpaclri. */
-+ case 1208: value = 1206; break; /* xpaclri --> sevl. */
-+ case 1206: value = 1205; break; /* sevl --> sev. */
-+ case 1205: value = 1204; break; /* sev --> wfi. */
-+ case 1204: value = 1203; break; /* wfi --> wfe. */
-+ case 1203: value = 1202; break; /* wfe --> yield. */
-+ case 1202: value = 1201; break; /* yield --> bti. */
-+ case 1201: value = 1200; break; /* bti --> csdb. */
-+ case 1200: value = 1199; break; /* csdb --> nop. */
-+ case 1199: value = 1198; break; /* nop --> hint. */
-+ case 1221: value = 1220; break; /* pssbb --> ssbb. */
-+ case 1220: value = 1219; break; /* ssbb --> dfb. */
-+ case 1219: value = 1217; break; /* dfb --> dsb. */
-+ case 1234: value = 1233; break; /* cpp --> dvp. */
-+ case 1233: value = 1232; break; /* dvp --> cfp. */
-+ case 1232: value = 1229; break; /* cfp --> tlbi. */
-+ case 1229: value = 1228; break; /* tlbi --> ic. */
-+ case 1228: value = 1227; break; /* ic --> dc. */
-+ case 1227: value = 1226; break; /* dc --> at. */
-+ case 1226: value = 1225; break; /* at --> sys. */
-+ case 2044: value = 1294; break; /* bic --> and. */
-+ case 1277: value = 1296; break; /* mov --> and. */
-+ case 1281: value = 1297; break; /* movs --> ands. */
-+ case 2045: value = 1332; break; /* cmple --> cmpge. */
-+ case 2048: value = 1335; break; /* cmplt --> cmpgt. */
-+ case 2046: value = 1337; break; /* cmplo --> cmphi. */
-+ case 2047: value = 1340; break; /* cmpls --> cmphs. */
-+ case 1274: value = 1362; break; /* mov --> cpy. */
-+ case 1276: value = 1363; break; /* mov --> cpy. */
-+ case 2055: value = 1279; break; /* fmov --> mov. */
-+ case 1279: value = 1364; break; /* mov --> cpy. */
-+ case 1269: value = 1376; break; /* mov --> dup. */
-+ case 1271: value = 1268; break; /* mov --> mov. */
-+ case 1268: value = 1377; break; /* mov --> dup. */
-+ case 2054: value = 1273; break; /* fmov --> mov. */
-+ case 1273: value = 1378; break; /* mov --> dup. */
-+ case 1272: value = 1379; break; /* mov --> dupm. */
-+ case 2049: value = 1381; break; /* eon --> eor. */
-+ case 1282: value = 1383; break; /* not --> eor. */
-+ case 1283: value = 1384; break; /* nots --> eors. */
-+ case 2050: value = 1389; break; /* facle --> facge. */
-+ case 2051: value = 1390; break; /* faclt --> facgt. */
-+ case 2052: value = 1403; break; /* fcmle --> fcmge. */
-+ case 2053: value = 1405; break; /* fcmlt --> fcmgt. */
-+ case 1266: value = 1411; break; /* fmov --> fcpy. */
-+ case 1265: value = 1434; break; /* fmov --> fdup. */
-+ case 1267: value = 1765; break; /* mov --> orr. */
-+ case 2056: value = 1766; break; /* orn --> orr. */
-+ case 1270: value = 1768; break; /* mov --> orr. */
-+ case 1280: value = 1769; break; /* movs --> orrs. */
-+ case 1275: value = 1831; break; /* mov --> sel. */
-+ case 1278: value = 1832; break; /* mov --> sel. */
- default: return NULL;
- }
-
- return aarch64_opcode_table + value;
- }
-
--int
-+bfd_boolean
- aarch64_extract_operand (const aarch64_operand *self,
- aarch64_opnd_info *info,
-- aarch64_insn code, const aarch64_inst *inst)
-+ aarch64_insn code, const aarch64_inst *inst,
-+ aarch64_operand_error *errors)
- {
- /* Use the index as the key. */
- int key = self - aarch64_operands;
-@@ -19672,15 +23814,15 @@ aarch64_extract_operand (const aarch64_o
- case 5:
- case 6:
- case 7:
-+ case 8:
- case 9:
-- case 10:
- case 11:
-- case 15:
-- case 16:
-+ case 12:
-+ case 13:
- case 17:
- case 18:
-+ case 19:
- case 20:
-- case 21:
- case 22:
- case 23:
- case 24:
-@@ -19689,58 +23831,58 @@ aarch64_extract_operand (const aarch64_o
- case 27:
- case 28:
- case 29:
-- case 151:
-- case 152:
-- case 153:
-- case 154:
-- case 155:
-- case 156:
-- case 157:
-- case 158:
-- case 159:
-- case 160:
-+ case 30:
-+ case 31:
-+ case 166:
-+ case 167:
-+ case 168:
-+ case 169:
-+ case 170:
-+ case 171:
-+ case 172:
- case 173:
- case 174:
- case 175:
-- case 176:
-- case 177:
-- case 178:
-- case 179:
-- case 180:
-- case 181:
-- case 185:
-- case 188:
-- return aarch64_ext_regno (self, info, code, inst);
-- case 8:
-- return aarch64_ext_regrt_sysins (self, info, code, inst);
-- case 12:
-- return aarch64_ext_regno_pair (self, info, code, inst);
-- case 13:
-- return aarch64_ext_reg_extended (self, info, code, inst);
-+ case 190:
-+ case 191:
-+ case 192:
-+ case 193:
-+ case 194:
-+ case 195:
-+ case 196:
-+ case 197:
-+ case 198:
-+ case 204:
-+ case 207:
-+ return aarch64_ext_regno (self, info, code, inst, errors);
-+ case 10:
-+ return aarch64_ext_regrt_sysins (self, info, code, inst, errors);
- case 14:
-- return aarch64_ext_reg_shifted (self, info, code, inst);
-- case 19:
-- return aarch64_ext_ft (self, info, code, inst);
-- case 30:
-- case 31:
-+ return aarch64_ext_regno_pair (self, info, code, inst, errors);
-+ case 15:
-+ return aarch64_ext_reg_extended (self, info, code, inst, errors);
-+ case 16:
-+ return aarch64_ext_reg_shifted (self, info, code, inst, errors);
-+ case 21:
-+ return aarch64_ext_ft (self, info, code, inst, errors);
- case 32:
-- case 190:
-- return aarch64_ext_reglane (self, info, code, inst);
- case 33:
-- return aarch64_ext_reglist (self, info, code, inst);
- case 34:
-- return aarch64_ext_ldst_reglist (self, info, code, inst);
- case 35:
-- return aarch64_ext_ldst_reglist_r (self, info, code, inst);
-+ case 210:
-+ return aarch64_ext_reglane (self, info, code, inst, errors);
- case 36:
-- return aarch64_ext_ldst_elemlist (self, info, code, inst);
-+ return aarch64_ext_reglist (self, info, code, inst, errors);
- case 37:
-+ return aarch64_ext_ldst_reglist (self, info, code, inst, errors);
- case 38:
-+ return aarch64_ext_ldst_reglist_r (self, info, code, inst, errors);
- case 39:
-+ return aarch64_ext_ldst_elemlist (self, info, code, inst, errors);
- case 40:
-- case 50:
-- case 51:
-- case 52:
-+ case 41:
-+ case 42:
-+ case 43:
- case 53:
- case 54:
- case 55:
-@@ -19752,115 +23894,118 @@ aarch64_extract_operand (const aarch64_o
- case 61:
- case 62:
- case 63:
-- case 74:
-- case 75:
-- case 76:
-- case 77:
-- case 78:
-- case 148:
-- case 150:
-- case 165:
-- case 166:
-- case 167:
-- case 168:
-- case 169:
-- case 170:
-- case 171:
-- case 172:
-- return aarch64_ext_imm (self, info, code, inst);
-- case 41:
-- case 42:
-- return aarch64_ext_advsimd_imm_shift (self, info, code, inst);
-- case 43:
-- case 44:
-- case 45:
-- return aarch64_ext_advsimd_imm_modified (self, info, code, inst);
-- case 46:
-- return aarch64_ext_shll_imm (self, info, code, inst);
-- case 49:
-- case 139:
-- return aarch64_ext_fpimm (self, info, code, inst);
- case 64:
-- case 146:
-- return aarch64_ext_limm (self, info, code, inst);
- case 65:
-- return aarch64_ext_aimm (self, info, code, inst);
- case 66:
-- return aarch64_ext_imm_half (self, info, code, inst);
- case 67:
-- return aarch64_ext_fbits (self, info, code, inst);
-+ case 68:
- case 69:
-- case 70:
-- case 144:
-- return aarch64_ext_imm_rotate2 (self, info, code, inst);
-- case 71:
-- case 143:
-- return aarch64_ext_imm_rotate1 (self, info, code, inst);
-- case 72:
-- case 73:
-- return aarch64_ext_cond (self, info, code, inst);
-- case 79:
-- case 86:
-- return aarch64_ext_addr_simple (self, info, code, inst);
- case 80:
-- return aarch64_ext_addr_regoff (self, info, code, inst);
- case 81:
- case 82:
- case 83:
-- return aarch64_ext_addr_simm (self, info, code, inst);
- case 84:
-- return aarch64_ext_addr_simm10 (self, info, code, inst);
-+ case 163:
-+ case 165:
-+ case 182:
-+ case 183:
-+ case 184:
-+ case 185:
-+ case 186:
-+ case 187:
-+ case 188:
-+ case 189:
-+ case 209:
-+ return aarch64_ext_imm (self, info, code, inst, errors);
-+ case 44:
-+ case 45:
-+ return aarch64_ext_advsimd_imm_shift (self, info, code, inst, errors);
-+ case 46:
-+ case 47:
-+ case 48:
-+ return aarch64_ext_advsimd_imm_modified (self, info, code, inst, errors);
-+ case 49:
-+ return aarch64_ext_shll_imm (self, info, code, inst, errors);
-+ case 52:
-+ case 153:
-+ return aarch64_ext_fpimm (self, info, code, inst, errors);
-+ case 70:
-+ case 161:
-+ return aarch64_ext_limm (self, info, code, inst, errors);
-+ case 71:
-+ return aarch64_ext_aimm (self, info, code, inst, errors);
-+ case 72:
-+ return aarch64_ext_imm_half (self, info, code, inst, errors);
-+ case 73:
-+ return aarch64_ext_fbits (self, info, code, inst, errors);
-+ case 75:
-+ case 76:
-+ case 158:
-+ return aarch64_ext_imm_rotate2 (self, info, code, inst, errors);
-+ case 77:
-+ case 157:
-+ case 159:
-+ return aarch64_ext_imm_rotate1 (self, info, code, inst, errors);
-+ case 78:
-+ case 79:
-+ return aarch64_ext_cond (self, info, code, inst, errors);
- case 85:
-- return aarch64_ext_addr_uimm12 (self, info, code, inst);
-+ case 94:
-+ return aarch64_ext_addr_simple (self, info, code, inst, errors);
-+ case 86:
-+ return aarch64_ext_addr_regoff (self, info, code, inst, errors);
- case 87:
-- return aarch64_ext_addr_offset (self, info, code, inst);
- case 88:
-- return aarch64_ext_simd_addr_post (self, info, code, inst);
- case 89:
-- return aarch64_ext_sysreg (self, info, code, inst);
-- case 90:
-- return aarch64_ext_pstatefield (self, info, code, inst);
- case 91:
-- case 92:
- case 93:
-- case 94:
-- return aarch64_ext_sysins_op (self, info, code, inst);
-+ return aarch64_ext_addr_simm (self, info, code, inst, errors);
-+ case 90:
-+ return aarch64_ext_addr_simm10 (self, info, code, inst, errors);
-+ case 92:
-+ return aarch64_ext_addr_uimm12 (self, info, code, inst, errors);
- case 95:
-+ return aarch64_ext_addr_offset (self, info, code, inst, errors);
- case 96:
-- return aarch64_ext_barrier (self, info, code, inst);
-+ return aarch64_ext_simd_addr_post (self, info, code, inst, errors);
- case 97:
-- return aarch64_ext_prfop (self, info, code, inst);
-+ return aarch64_ext_sysreg (self, info, code, inst, errors);
- case 98:
-- return aarch64_ext_hint (self, info, code, inst);
-+ return aarch64_ext_pstatefield (self, info, code, inst, errors);
- case 99:
-- return aarch64_ext_sve_addr_ri_s4 (self, info, code, inst);
- case 100:
- case 101:
- case 102:
- case 103:
-- return aarch64_ext_sve_addr_ri_s4xvl (self, info, code, inst);
-+ return aarch64_ext_sysins_op (self, info, code, inst, errors);
- case 104:
-- return aarch64_ext_sve_addr_ri_s6xvl (self, info, code, inst);
-- case 105:
-- return aarch64_ext_sve_addr_ri_s9xvl (self, info, code, inst);
- case 106:
-+ return aarch64_ext_barrier (self, info, code, inst, errors);
-+ case 105:
-+ return aarch64_ext_barrier_dsb_nxs (self, info, code, inst, errors);
- case 107:
-+ return aarch64_ext_prfop (self, info, code, inst, errors);
- case 108:
-+ return aarch64_ext_none (self, info, code, inst, errors);
- case 109:
-- return aarch64_ext_sve_addr_ri_u6 (self, info, code, inst);
-+ return aarch64_ext_hint (self, info, code, inst, errors);
- case 110:
- case 111:
-+ return aarch64_ext_sve_addr_ri_s4 (self, info, code, inst, errors);
- case 112:
- case 113:
- case 114:
- case 115:
-+ return aarch64_ext_sve_addr_ri_s4xvl (self, info, code, inst, errors);
- case 116:
-+ return aarch64_ext_sve_addr_ri_s6xvl (self, info, code, inst, errors);
- case 117:
-+ return aarch64_ext_sve_addr_ri_s9xvl (self, info, code, inst, errors);
- case 118:
- case 119:
- case 120:
- case 121:
-- return aarch64_ext_sve_addr_rr_lsl (self, info, code, inst);
-+ return aarch64_ext_sve_addr_ri_u6 (self, info, code, inst, errors);
- case 122:
- case 123:
- case 124:
-@@ -19869,49 +24014,68 @@ aarch64_extract_operand (const aarch64_o
- case 127:
- case 128:
- case 129:
-- return aarch64_ext_sve_addr_rz_xtw (self, info, code, inst);
- case 130:
- case 131:
- case 132:
- case 133:
-- return aarch64_ext_sve_addr_zi_u5 (self, info, code, inst);
- case 134:
-- return aarch64_ext_sve_addr_zz_lsl (self, info, code, inst);
- case 135:
-- return aarch64_ext_sve_addr_zz_sxtw (self, info, code, inst);
-+ return aarch64_ext_sve_addr_rr_lsl (self, info, code, inst, errors);
- case 136:
-- return aarch64_ext_sve_addr_zz_uxtw (self, info, code, inst);
- case 137:
-- return aarch64_ext_sve_aimm (self, info, code, inst);
- case 138:
-- return aarch64_ext_sve_asimm (self, info, code, inst);
-+ case 139:
- case 140:
-- return aarch64_ext_sve_float_half_one (self, info, code, inst);
- case 141:
-- return aarch64_ext_sve_float_half_two (self, info, code, inst);
- case 142:
-- return aarch64_ext_sve_float_zero_one (self, info, code, inst);
-+ case 143:
-+ return aarch64_ext_sve_addr_rz_xtw (self, info, code, inst, errors);
-+ case 144:
- case 145:
-- return aarch64_ext_inv_limm (self, info, code, inst);
-+ case 146:
- case 147:
-- return aarch64_ext_sve_limm_mov (self, info, code, inst);
-+ return aarch64_ext_sve_addr_zi_u5 (self, info, code, inst, errors);
-+ case 148:
-+ return aarch64_ext_sve_addr_zz_lsl (self, info, code, inst, errors);
- case 149:
-- return aarch64_ext_sve_scale (self, info, code, inst);
-- case 161:
-+ return aarch64_ext_sve_addr_zz_sxtw (self, info, code, inst, errors);
-+ case 150:
-+ return aarch64_ext_sve_addr_zz_uxtw (self, info, code, inst, errors);
-+ case 151:
-+ return aarch64_ext_sve_aimm (self, info, code, inst, errors);
-+ case 152:
-+ return aarch64_ext_sve_asimm (self, info, code, inst, errors);
-+ case 154:
-+ return aarch64_ext_sve_float_half_one (self, info, code, inst, errors);
-+ case 155:
-+ return aarch64_ext_sve_float_half_two (self, info, code, inst, errors);
-+ case 156:
-+ return aarch64_ext_sve_float_zero_one (self, info, code, inst, errors);
-+ case 160:
-+ return aarch64_ext_inv_limm (self, info, code, inst, errors);
- case 162:
-- return aarch64_ext_sve_shlimm (self, info, code, inst);
-- case 163:
-+ return aarch64_ext_sve_limm_mov (self, info, code, inst, errors);
- case 164:
-- return aarch64_ext_sve_shrimm (self, info, code, inst);
-- case 182:
-- case 183:
-- case 184:
-- return aarch64_ext_sve_quad_index (self, info, code, inst);
-- case 186:
-- return aarch64_ext_sve_index (self, info, code, inst);
-- case 187:
-- case 189:
-- return aarch64_ext_sve_reglist (self, info, code, inst);
-+ return aarch64_ext_sve_scale (self, info, code, inst, errors);
-+ case 176:
-+ case 177:
-+ case 178:
-+ return aarch64_ext_sve_shlimm (self, info, code, inst, errors);
-+ case 179:
-+ case 180:
-+ case 181:
-+ return aarch64_ext_sve_shrimm (self, info, code, inst, errors);
-+ case 199:
-+ case 200:
-+ case 201:
-+ case 202:
-+ case 203:
-+ return aarch64_ext_sve_quad_index (self, info, code, inst, errors);
-+ case 205:
-+ return aarch64_ext_sve_index (self, info, code, inst, errors);
-+ case 206:
-+ case 208:
-+ return aarch64_ext_sve_reglist (self, info, code, inst, errors);
- default: assert (0); abort ();
- }
- }
-diff -rup binutils-2.30/opcodes/aarch64-dis.c binutils-2.30.new/opcodes/aarch64-dis.c
---- binutils-2.30/opcodes/aarch64-dis.c 2018-01-13 13:31:16.000000000 +0000
-+++ binutils-2.30.new/opcodes/aarch64-dis.c 2021-03-23 16:19:53.187776169 +0000
-@@ -1,5 +1,5 @@
- /* aarch64-dis.c -- AArch64 disassembler.
-- Copyright (C) 2009-2018 Free Software Foundation, Inc.
-+ Copyright (C) 2009-2021 Free Software Foundation, Inc.
- Contributed by ARM Ltd.
-
- This file is part of the GNU opcodes library.
-@@ -26,11 +26,6 @@
- #include "aarch64-dis.h"
- #include "elf-bfd.h"
-
--#define ERR_OK 0
--#define ERR_UND -1
--#define ERR_UNP -3
--#define ERR_NYI -5
--
- #define INSNLEN 4
-
- /* Cached mapping symbol state. */
-@@ -40,13 +35,18 @@ enum map_type
- MAP_DATA
- };
-
-+static aarch64_feature_set arch_variant; /* See select_aarch64_variant. */
- static enum map_type last_type;
- static int last_mapping_sym = -1;
- static bfd_vma last_mapping_addr = 0;
-
- /* Other options */
- static int no_aliases = 0; /* If set disassemble as most general inst. */
--
-+ static int no_notes = 1; /* If set do not print disassemble notes in the
-+ output as comments. */
-+
-+/* Currently active instruction sequence. */
-+static aarch64_instr_sequence insn_sequence;
-
- static void
- set_default_aarch64_dis_options (struct disassemble_info *info ATTRIBUTE_UNUSED)
-@@ -69,6 +69,18 @@ parse_aarch64_dis_option (const char *op
- return;
- }
-
-+ if (CONST_STRNEQ (option, "no-notes"))
-+ {
-+ no_notes = 1;
-+ return;
-+ }
-+
-+ if (CONST_STRNEQ (option, "notes"))
-+ {
-+ no_notes = 0;
-+ return;
-+ }
-+
- #ifdef DEBUG_AARCH64
- if (CONST_STRNEQ (option, "debug_dump"))
- {
-@@ -166,18 +178,15 @@ extract_all_fields (const aarch64_operan
- }
-
- /* Sign-extend bit I of VALUE. */
--static inline int32_t
-+static inline uint64_t
- sign_extend (aarch64_insn value, unsigned i)
- {
-- uint32_t ret = value;
-+ uint64_t ret, sign;
-
- assert (i < 32);
-- if ((value >> i) & 0x1)
-- {
-- uint32_t val = (uint32_t)(-1) << i;
-- ret = ret | val;
-- }
-- return (int32_t) ret;
-+ ret = value;
-+ sign = (uint64_t) 1 << i;
-+ return ((ret & (sign + sign - 1)) ^ sign) - sign;
- }
-
- /* N.B. the following inline helpfer functions create a dependency on the
-@@ -242,31 +251,44 @@ get_expected_qualifier (const aarch64_in
-
- /* Operand extractors. */
-
--int
-+bfd_boolean
-+aarch64_ext_none (const aarch64_operand *self ATTRIBUTE_UNUSED,
-+ aarch64_opnd_info *info ATTRIBUTE_UNUSED,
-+ const aarch64_insn code ATTRIBUTE_UNUSED,
-+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
-+{
-+ return TRUE;
-+}
-+
-+bfd_boolean
- aarch64_ext_regno (const aarch64_operand *self, aarch64_opnd_info *info,
- const aarch64_insn code,
-- const aarch64_inst *inst ATTRIBUTE_UNUSED)
-+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- info->reg.regno = extract_field (self->fields[0], code, 0);
-- return 1;
-+ return TRUE;
- }
-
--int
-+bfd_boolean
- aarch64_ext_regno_pair (const aarch64_operand *self ATTRIBUTE_UNUSED, aarch64_opnd_info *info,
- const aarch64_insn code ATTRIBUTE_UNUSED,
-- const aarch64_inst *inst ATTRIBUTE_UNUSED)
-+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- assert (info->idx == 1
- || info->idx ==3);
- info->reg.regno = inst->operands[info->idx - 1].reg.regno + 1;
-- return 1;
-+ return TRUE;
- }
-
- /* e.g. IC <ic_op>{, <Xt>}. */
--int
-+bfd_boolean
- aarch64_ext_regrt_sysins (const aarch64_operand *self, aarch64_opnd_info *info,
- const aarch64_insn code,
-- const aarch64_inst *inst ATTRIBUTE_UNUSED)
-+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- info->reg.regno = extract_field (self->fields[0], code, 0);
- assert (info->idx == 1
-@@ -277,14 +299,15 @@ aarch64_ext_regrt_sysins (const aarch64_
- not. */
- info->present = aarch64_sys_ins_reg_has_xt (inst->operands[0].sysins_op);
-
-- return 1;
-+ return TRUE;
- }
-
- /* e.g. SQDMLAL <Va><d>, <Vb><n>, <Vm>.<Ts>[<index>]. */
--int
-+bfd_boolean
- aarch64_ext_reglane (const aarch64_operand *self, aarch64_opnd_info *info,
- const aarch64_insn code,
-- const aarch64_inst *inst ATTRIBUTE_UNUSED)
-+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- /* regno */
- info->reglane.regno = extract_field (self->fields[0], code,
-@@ -320,7 +343,7 @@ aarch64_ext_reglane (const aarch64_opera
- while (++pos <= 3 && (value & 0x1) == 0)
- value >>= 1;
- if (pos > 3)
-- return 0;
-+ return FALSE;
- info->qualifier = get_sreg_qualifier_from_value (pos);
- info->reglane.index = (unsigned) (value >> 1);
- }
-@@ -332,12 +355,13 @@ aarch64_ext_reglane (const aarch64_opera
- switch (info->qualifier)
- {
- case AARCH64_OPND_QLF_S_4B:
-+ case AARCH64_OPND_QLF_S_2H:
- /* L:H */
- info->reglane.index = extract_fields (code, 0, 2, FLD_H, FLD_L);
- info->reglane.regno &= 0x1f;
- break;
- default:
-- return 0;
-+ return FALSE;
- }
- }
- else if (inst->opcode->iclass == cryptosm3)
-@@ -355,10 +379,18 @@ aarch64_ext_reglane (const aarch64_opera
- switch (info->qualifier)
- {
- case AARCH64_OPND_QLF_S_H:
-- /* h:l:m */
-- info->reglane.index = extract_fields (code, 0, 3, FLD_H, FLD_L,
-- FLD_M);
-- info->reglane.regno &= 0xf;
-+ if (info->type == AARCH64_OPND_Em16)
-+ {
-+ /* h:l:m */
-+ info->reglane.index = extract_fields (code, 0, 3, FLD_H, FLD_L,
-+ FLD_M);
-+ info->reglane.regno &= 0xf;
-+ }
-+ else
-+ {
-+ /* h:l */
-+ info->reglane.index = extract_fields (code, 0, 2, FLD_H, FLD_L);
-+ }
- break;
- case AARCH64_OPND_QLF_S_S:
- /* h:l */
-@@ -369,38 +401,41 @@ aarch64_ext_reglane (const aarch64_opera
- info->reglane.index = extract_field (FLD_H, code, 0);
- break;
- default:
-- return 0;
-+ return FALSE;
- }
-
-- if (inst->opcode->op == OP_FCMLA_ELEM)
-+ if (inst->opcode->op == OP_FCMLA_ELEM
-+ && info->qualifier != AARCH64_OPND_QLF_S_H)
- {
- /* Complex operand takes two elements. */
- if (info->reglane.index & 1)
-- return 0;
-+ return FALSE;
- info->reglane.index /= 2;
- }
- }
-
-- return 1;
-+ return TRUE;
- }
-
--int
-+bfd_boolean
- aarch64_ext_reglist (const aarch64_operand *self, aarch64_opnd_info *info,
- const aarch64_insn code,
-- const aarch64_inst *inst ATTRIBUTE_UNUSED)
-+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- /* R */
- info->reglist.first_regno = extract_field (self->fields[0], code, 0);
- /* len */
- info->reglist.num_regs = extract_field (FLD_len, code, 0) + 1;
-- return 1;
-+ return TRUE;
- }
-
- /* Decode Rt and opcode fields of Vt in AdvSIMD load/store instructions. */
--int
-+bfd_boolean
- aarch64_ext_ldst_reglist (const aarch64_operand *self ATTRIBUTE_UNUSED,
- aarch64_opnd_info *info, const aarch64_insn code,
-- const aarch64_inst *inst)
-+ const aarch64_inst *inst,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- aarch64_insn value;
- /* Number of elements in each structure to be loaded/stored. */
-@@ -431,20 +466,21 @@ aarch64_ext_ldst_reglist (const aarch64_
- value = extract_field (FLD_opcode, code, 0);
- /* PR 21595: Check for a bogus value. */
- if (value >= ARRAY_SIZE (data))
-- return 0;
-+ return FALSE;
- if (expected_num != data[value].num_elements || data[value].is_reserved)
-- return 0;
-+ return FALSE;
- info->reglist.num_regs = data[value].num_regs;
-
-- return 1;
-+ return TRUE;
- }
-
- /* Decode Rt and S fields of Vt in AdvSIMD load single structure to all
- lanes instructions. */
--int
-+bfd_boolean
- aarch64_ext_ldst_reglist_r (const aarch64_operand *self ATTRIBUTE_UNUSED,
- aarch64_opnd_info *info, const aarch64_insn code,
-- const aarch64_inst *inst)
-+ const aarch64_inst *inst,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- aarch64_insn value;
-
-@@ -462,15 +498,16 @@ aarch64_ext_ldst_reglist_r (const aarch6
- if (info->reglist.num_regs == 1 && value == (aarch64_insn) 1)
- info->reglist.num_regs = 2;
-
-- return 1;
-+ return TRUE;
- }
-
- /* Decode Q, opcode<2:1>, S, size and Rt fields of Vt in AdvSIMD
- load/store single element instructions. */
--int
-+bfd_boolean
- aarch64_ext_ldst_elemlist (const aarch64_operand *self ATTRIBUTE_UNUSED,
- aarch64_opnd_info *info, const aarch64_insn code,
-- const aarch64_inst *inst ATTRIBUTE_UNUSED)
-+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- aarch64_field field = {0, 0};
- aarch64_insn QSsize; /* fields Q:S:size. */
-@@ -493,7 +530,7 @@ aarch64_ext_ldst_elemlist (const aarch64
- case 0x1:
- if (QSsize & 0x1)
- /* UND. */
-- return 0;
-+ return FALSE;
- info->qualifier = AARCH64_OPND_QLF_S_H;
- /* Index encoded in "Q:S:size<1>". */
- info->reglist.index = QSsize >> 1;
-@@ -501,7 +538,7 @@ aarch64_ext_ldst_elemlist (const aarch64
- case 0x2:
- if ((QSsize >> 1) & 0x1)
- /* UND. */
-- return 0;
-+ return FALSE;
- if ((QSsize & 0x1) == 0)
- {
- info->qualifier = AARCH64_OPND_QLF_S_S;
-@@ -512,14 +549,14 @@ aarch64_ext_ldst_elemlist (const aarch64
- {
- if (extract_field (FLD_S, code, 0))
- /* UND */
-- return 0;
-+ return FALSE;
- info->qualifier = AARCH64_OPND_QLF_S_D;
- /* Index encoded in "Q". */
- info->reglist.index = QSsize >> 3;
- }
- break;
- default:
-- return 0;
-+ return FALSE;
- }
-
- info->reglist.has_index = 1;
-@@ -529,17 +566,18 @@ aarch64_ext_ldst_elemlist (const aarch64
- info->reglist.num_regs = get_opcode_dependent_value (inst->opcode);
- assert (info->reglist.num_regs >= 1 && info->reglist.num_regs <= 4);
-
-- return 1;
-+ return TRUE;
- }
-
- /* Decode fields immh:immb and/or Q for e.g.
- SSHR <Vd>.<T>, <Vn>.<T>, #<shift>
- or SSHR <V><d>, <V><n>, #<shift>. */
-
--int
-+bfd_boolean
- aarch64_ext_advsimd_imm_shift (const aarch64_operand *self ATTRIBUTE_UNUSED,
- aarch64_opnd_info *info, const aarch64_insn code,
-- const aarch64_inst *inst)
-+ const aarch64_inst *inst,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- int pos;
- aarch64_insn Q, imm, immh;
-@@ -547,7 +585,7 @@ aarch64_ext_advsimd_imm_shift (const aar
-
- immh = extract_field (FLD_immh, code, 0);
- if (immh == 0)
-- return 0;
-+ return FALSE;
- imm = extract_fields (code, 0, 2, FLD_immh, FLD_immb);
- pos = 4;
- /* Get highest set bit in immh. */
-@@ -595,14 +633,15 @@ aarch64_ext_advsimd_imm_shift (const aar
- 1xxx (UInt(immh:immb)-64) */
- info->imm.value = imm - (8 << pos);
-
-- return 1;
-+ return TRUE;
- }
-
- /* Decode shift immediate for e.g. sshr (imm). */
--int
-+bfd_boolean
- aarch64_ext_shll_imm (const aarch64_operand *self ATTRIBUTE_UNUSED,
- aarch64_opnd_info *info, const aarch64_insn code,
-- const aarch64_inst *inst ATTRIBUTE_UNUSED)
-+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- int64_t imm;
- aarch64_insn val;
-@@ -612,20 +651,21 @@ aarch64_ext_shll_imm (const aarch64_oper
- case 0: imm = 8; break;
- case 1: imm = 16; break;
- case 2: imm = 32; break;
-- default: return 0;
-+ default: return FALSE;
- }
- info->imm.value = imm;
-- return 1;
-+ return TRUE;
- }
-
- /* Decode imm for e.g. BFM <Wd>, <Wn>, #<immr>, #<imms>.
- value in the field(s) will be extracted as unsigned immediate value. */
--int
-+bfd_boolean
- aarch64_ext_imm (const aarch64_operand *self, aarch64_opnd_info *info,
- const aarch64_insn code,
-- const aarch64_inst *inst ATTRIBUTE_UNUSED)
-+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
-- int64_t imm;
-+ uint64_t imm;
-
- imm = extract_all_fields (self, code);
-
-@@ -634,33 +674,37 @@ aarch64_ext_imm (const aarch64_operand *
-
- if (operand_need_shift_by_two (self))
- imm <<= 2;
-+ else if (operand_need_shift_by_four (self))
-+ imm <<= 4;
-
- if (info->type == AARCH64_OPND_ADDR_ADRP)
- imm <<= 12;
-
- info->imm.value = imm;
-- return 1;
-+ return TRUE;
- }
-
- /* Decode imm and its shifter for e.g. MOVZ <Wd>, #<imm16>{, LSL #<shift>}. */
--int
-+bfd_boolean
- aarch64_ext_imm_half (const aarch64_operand *self, aarch64_opnd_info *info,
- const aarch64_insn code,
-- const aarch64_inst *inst ATTRIBUTE_UNUSED)
-+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors)
- {
-- aarch64_ext_imm (self, info, code, inst);
-+ aarch64_ext_imm (self, info, code, inst, errors);
- info->shifter.kind = AARCH64_MOD_LSL;
- info->shifter.amount = extract_field (FLD_hw, code, 0) << 4;
-- return 1;
-+ return TRUE;
- }
-
- /* Decode cmode and "a:b:c:d:e:f:g:h" for e.g.
- MOVI <Vd>.<T>, #<imm8> {, LSL #<amount>}. */
--int
-+bfd_boolean
- aarch64_ext_advsimd_imm_modified (const aarch64_operand *self ATTRIBUTE_UNUSED,
- aarch64_opnd_info *info,
- const aarch64_insn code,
-- const aarch64_inst *inst ATTRIBUTE_UNUSED)
-+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- uint64_t imm;
- enum aarch64_opnd_qualifier opnd0_qualifier = inst->operands[0].qualifier;
-@@ -704,7 +748,7 @@ aarch64_ext_advsimd_imm_modified (const
- case 4: gen_sub_field (FLD_cmode, 1, 2, &field); break; /* per word */
- case 2: gen_sub_field (FLD_cmode, 1, 1, &field); break; /* per half */
- case 1: gen_sub_field (FLD_cmode, 1, 0, &field); break; /* per byte */
-- default: assert (0); return 0;
-+ default: assert (0); return FALSE;
- }
- /* 00: 0; 01: 8; 10:16; 11:24. */
- info->shifter.amount = extract_field_2 (&field, code, 0) << 3;
-@@ -717,63 +761,68 @@ aarch64_ext_advsimd_imm_modified (const
- break;
- default:
- assert (0);
-- return 0;
-+ return FALSE;
- }
-
-- return 1;
-+ return TRUE;
- }
-
- /* Decode an 8-bit floating-point immediate. */
--int
-+bfd_boolean
- aarch64_ext_fpimm (const aarch64_operand *self, aarch64_opnd_info *info,
- const aarch64_insn code,
-- const aarch64_inst *inst ATTRIBUTE_UNUSED)
-+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- info->imm.value = extract_all_fields (self, code);
- info->imm.is_fp = 1;
-- return 1;
-+ return TRUE;
- }
-
- /* Decode a 1-bit rotate immediate (#90 or #270). */
--int
-+bfd_boolean
- aarch64_ext_imm_rotate1 (const aarch64_operand *self, aarch64_opnd_info *info,
- const aarch64_insn code,
-- const aarch64_inst *inst ATTRIBUTE_UNUSED)
-+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- uint64_t rot = extract_field (self->fields[0], code, 0);
- assert (rot < 2U);
- info->imm.value = rot * 180 + 90;
-- return 1;
-+ return TRUE;
- }
-
- /* Decode a 2-bit rotate immediate (#0, #90, #180 or #270). */
--int
-+bfd_boolean
- aarch64_ext_imm_rotate2 (const aarch64_operand *self, aarch64_opnd_info *info,
- const aarch64_insn code,
-- const aarch64_inst *inst ATTRIBUTE_UNUSED)
-+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- uint64_t rot = extract_field (self->fields[0], code, 0);
- assert (rot < 4U);
- info->imm.value = rot * 90;
-- return 1;
-+ return TRUE;
- }
-
- /* Decode scale for e.g. SCVTF <Dd>, <Wn>, #<fbits>. */
--int
-+bfd_boolean
- aarch64_ext_fbits (const aarch64_operand *self ATTRIBUTE_UNUSED,
- aarch64_opnd_info *info, const aarch64_insn code,
-- const aarch64_inst *inst ATTRIBUTE_UNUSED)
-+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- info->imm.value = 64- extract_field (FLD_scale, code, 0);
-- return 1;
-+ return TRUE;
- }
-
- /* Decode arithmetic immediate for e.g.
- SUBS <Wd>, <Wn|WSP>, #<imm> {, <shift>}. */
--int
-+bfd_boolean
- aarch64_ext_aimm (const aarch64_operand *self ATTRIBUTE_UNUSED,
- aarch64_opnd_info *info, const aarch64_insn code,
-- const aarch64_inst *inst ATTRIBUTE_UNUSED)
-+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- aarch64_insn value;
-
-@@ -781,18 +830,18 @@ aarch64_ext_aimm (const aarch64_operand
- /* shift */
- value = extract_field (FLD_shift, code, 0);
- if (value >= 2)
-- return 0;
-+ return FALSE;
- info->shifter.amount = value ? 12 : 0;
- /* imm12 (unsigned) */
- info->imm.value = extract_field (FLD_imm12, code, 0);
-
-- return 1;
-+ return TRUE;
- }
-
- /* Return true if VALUE is a valid logical immediate encoding, storing the
- decoded value in *RESULT if so. ESIZE is the number of bytes in the
- decoded immediate. */
--static int
-+static bfd_boolean
- decode_limm (uint32_t esize, aarch64_insn value, int64_t *result)
- {
- uint64_t imm, mask;
-@@ -820,7 +869,7 @@ decode_limm (uint32_t esize, aarch64_ins
- case 0x30 ... 0x37: /* 110xxx */ simd_size = 8; S &= 0x7; break;
- case 0x38 ... 0x3b: /* 1110xx */ simd_size = 4; S &= 0x3; break;
- case 0x3c ... 0x3d: /* 11110x */ simd_size = 2; S &= 0x1; break;
-- default: return 0;
-+ default: return FALSE;
- }
- mask = (1ull << simd_size) - 1;
- /* Top bits are IGNORED. */
-@@ -828,11 +877,11 @@ decode_limm (uint32_t esize, aarch64_ins
- }
-
- if (simd_size > esize * 8)
-- return 0;
-+ return FALSE;
-
- /* NOTE: if S = simd_size - 1 we get 0xf..f which is rejected. */
- if (S == simd_size - 1)
-- return 0;
-+ return FALSE;
- /* S+1 consecutive bits to 1. */
- /* NOTE: S can't be 63 due to detection above. */
- imm = (1ull << (S + 1)) - 1;
-@@ -858,14 +907,15 @@ decode_limm (uint32_t esize, aarch64_ins
-
- *result = imm & ~((uint64_t) -1 << (esize * 4) << (esize * 4));
-
-- return 1;
-+ return TRUE;
- }
-
- /* Decode a logical immediate for e.g. ORR <Wd|WSP>, <Wn>, #<imm>. */
--int
-+bfd_boolean
- aarch64_ext_limm (const aarch64_operand *self,
- aarch64_opnd_info *info, const aarch64_insn code,
-- const aarch64_inst *inst)
-+ const aarch64_inst *inst,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- uint32_t esize;
- aarch64_insn value;
-@@ -877,23 +927,25 @@ aarch64_ext_limm (const aarch64_operand
- }
-
- /* Decode a logical immediate for the BIC alias of AND (etc.). */
--int
-+bfd_boolean
- aarch64_ext_inv_limm (const aarch64_operand *self,
- aarch64_opnd_info *info, const aarch64_insn code,
-- const aarch64_inst *inst)
-+ const aarch64_inst *inst,
-+ aarch64_operand_error *errors)
- {
-- if (!aarch64_ext_limm (self, info, code, inst))
-- return 0;
-+ if (!aarch64_ext_limm (self, info, code, inst, errors))
-+ return FALSE;
- info->imm.value = ~info->imm.value;
-- return 1;
-+ return TRUE;
- }
-
- /* Decode Ft for e.g. STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]
- or LDP <Qt1>, <Qt2>, [<Xn|SP>], #<imm>. */
--int
-+bfd_boolean
- aarch64_ext_ft (const aarch64_operand *self ATTRIBUTE_UNUSED,
- aarch64_opnd_info *info,
-- const aarch64_insn code, const aarch64_inst *inst)
-+ const aarch64_insn code, const aarch64_inst *inst,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- aarch64_insn value;
-
-@@ -913,7 +965,7 @@ aarch64_ext_ft (const aarch64_operand *s
- case 0: qualifier = AARCH64_OPND_QLF_S_S; break;
- case 1: qualifier = AARCH64_OPND_QLF_S_D; break;
- case 2: qualifier = AARCH64_OPND_QLF_S_Q; break;
-- default: return 0;
-+ default: return FALSE;
- }
- info->qualifier = qualifier;
- }
-@@ -922,31 +974,33 @@ aarch64_ext_ft (const aarch64_operand *s
- /* opc1:size */
- value = extract_fields (code, 0, 2, FLD_opc1, FLD_ldst_size);
- if (value > 0x4)
-- return 0;
-+ return FALSE;
- info->qualifier = get_sreg_qualifier_from_value (value);
- }
-
-- return 1;
-+ return TRUE;
- }
-
- /* Decode the address operand for e.g. STXRB <Ws>, <Wt>, [<Xn|SP>{,#0}]. */
--int
-+bfd_boolean
- aarch64_ext_addr_simple (const aarch64_operand *self ATTRIBUTE_UNUSED,
- aarch64_opnd_info *info,
- aarch64_insn code,
-- const aarch64_inst *inst ATTRIBUTE_UNUSED)
-+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- /* Rn */
- info->addr.base_regno = extract_field (FLD_Rn, code, 0);
-- return 1;
-+ return TRUE;
- }
-
- /* Decode the address operand for e.g.
- stlur <Xt>, [<Xn|SP>{, <amount>}]. */
--int
-+bfd_boolean
- aarch64_ext_addr_offset (const aarch64_operand *self ATTRIBUTE_UNUSED,
- aarch64_opnd_info *info,
-- aarch64_insn code, const aarch64_inst *inst)
-+ aarch64_insn code, const aarch64_inst *inst,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- info->qualifier = get_expected_qualifier (inst, info->idx);
-
-@@ -960,15 +1014,16 @@ aarch64_ext_addr_offset (const aarch64_o
- info->addr.writeback = 1;
- info->addr.preind = 1;
- }
-- return 1;
-+ return TRUE;
- }
-
- /* Decode the address operand for e.g.
- STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
--int
-+bfd_boolean
- aarch64_ext_addr_regoff (const aarch64_operand *self ATTRIBUTE_UNUSED,
- aarch64_opnd_info *info,
-- aarch64_insn code, const aarch64_inst *inst)
-+ aarch64_insn code, const aarch64_inst *inst,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- aarch64_insn S, value;
-
-@@ -1004,13 +1059,14 @@ aarch64_ext_addr_regoff (const aarch64_o
- info->shifter.amount_present = 1;
- }
-
-- return 1;
-+ return TRUE;
- }
-
- /* Decode the address operand for e.g. LDRSW <Xt>, [<Xn|SP>], #<simm>. */
--int
-+bfd_boolean
- aarch64_ext_addr_simm (const aarch64_operand *self, aarch64_opnd_info *info,
-- aarch64_insn code, const aarch64_inst *inst)
-+ aarch64_insn code, const aarch64_inst *inst,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- aarch64_insn imm;
- info->qualifier = get_expected_qualifier (inst, info->idx);
-@@ -1020,7 +1076,8 @@ aarch64_ext_addr_simm (const aarch64_ope
- /* simm (imm9 or imm7) */
- imm = extract_field (self->fields[0], code, 0);
- info->addr.offset.imm = sign_extend (imm, fields[self->fields[0]].width - 1);
-- if (self->fields[0] == FLD_imm7)
-+ if (self->fields[0] == FLD_imm7
-+ || info->qualifier == AARCH64_OPND_QLF_imm_tag)
- /* scaled immediate in ld/st pair instructions. */
- info->addr.offset.imm *= aarch64_get_qualifier_esize (info->qualifier);
- /* qualifier */
-@@ -1039,14 +1096,15 @@ aarch64_ext_addr_simm (const aarch64_ope
- info->addr.postind = 1;
- }
-
-- return 1;
-+ return TRUE;
- }
-
- /* Decode the address operand for e.g. LDRSW <Xt>, [<Xn|SP>{, #<simm>}]. */
--int
-+bfd_boolean
- aarch64_ext_addr_uimm12 (const aarch64_operand *self, aarch64_opnd_info *info,
- aarch64_insn code,
-- const aarch64_inst *inst ATTRIBUTE_UNUSED)
-+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- int shift;
- info->qualifier = get_expected_qualifier (inst, info->idx);
-@@ -1055,14 +1113,15 @@ aarch64_ext_addr_uimm12 (const aarch64_o
- info->addr.base_regno = extract_field (self->fields[0], code, 0);
- /* uimm12 */
- info->addr.offset.imm = extract_field (self->fields[1], code, 0) << shift;
-- return 1;
-+ return TRUE;
- }
-
- /* Decode the address operand for e.g. LDRAA <Xt>, [<Xn|SP>{, #<simm>}]. */
--int
-+bfd_boolean
- aarch64_ext_addr_simm10 (const aarch64_operand *self, aarch64_opnd_info *info,
- aarch64_insn code,
-- const aarch64_inst *inst ATTRIBUTE_UNUSED)
-+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- aarch64_insn imm;
-
-@@ -1076,15 +1135,16 @@ aarch64_ext_addr_simm10 (const aarch64_o
- info->addr.writeback = 1;
- info->addr.preind = 1;
- }
-- return 1;
-+ return TRUE;
- }
-
- /* Decode the address operand for e.g.
- LD1 {<Vt>.<T>, <Vt2>.<T>, <Vt3>.<T>}, [<Xn|SP>], <Xm|#<amount>>. */
--int
-+bfd_boolean
- aarch64_ext_simd_addr_post (const aarch64_operand *self ATTRIBUTE_UNUSED,
- aarch64_opnd_info *info,
-- aarch64_insn code, const aarch64_inst *inst)
-+ aarch64_insn code, const aarch64_inst *inst,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- /* The opcode dependent area stores the number of elements in
- each structure to be loaded/stored. */
-@@ -1110,57 +1170,76 @@ aarch64_ext_simd_addr_post (const aarch6
- info->addr.offset.is_reg = 1;
- info->addr.writeback = 1;
-
-- return 1;
-+ return TRUE;
- }
-
- /* Decode the condition operand for e.g. CSEL <Xd>, <Xn>, <Xm>, <cond>. */
--int
-+bfd_boolean
- aarch64_ext_cond (const aarch64_operand *self ATTRIBUTE_UNUSED,
- aarch64_opnd_info *info,
-- aarch64_insn code, const aarch64_inst *inst ATTRIBUTE_UNUSED)
-+ aarch64_insn code, const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- aarch64_insn value;
- /* cond */
- value = extract_field (FLD_cond, code, 0);
- info->cond = get_cond_from_value (value);
-- return 1;
-+ return TRUE;
- }
-
- /* Decode the system register operand for e.g. MRS <Xt>, <systemreg>. */
--int
-+bfd_boolean
- aarch64_ext_sysreg (const aarch64_operand *self ATTRIBUTE_UNUSED,
- aarch64_opnd_info *info,
- aarch64_insn code,
-- const aarch64_inst *inst ATTRIBUTE_UNUSED)
-+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- /* op0:op1:CRn:CRm:op2 */
-- info->sysreg = extract_fields (code, 0, 5, FLD_op0, FLD_op1, FLD_CRn,
-- FLD_CRm, FLD_op2);
-- return 1;
-+ info->sysreg.value = extract_fields (code, 0, 5, FLD_op0, FLD_op1, FLD_CRn,
-+ FLD_CRm, FLD_op2);
-+ info->sysreg.flags = 0;
-+
-+ /* If a system instruction, check which restrictions should be on the register
-+ value during decoding, these will be enforced then. */
-+ if (inst->opcode->iclass == ic_system)
-+ {
-+ /* Check to see if it's read-only, else check if it's write only.
-+ if it's both or unspecified don't care. */
-+ if ((inst->opcode->flags & (F_SYS_READ | F_SYS_WRITE)) == F_SYS_READ)
-+ info->sysreg.flags = F_REG_READ;
-+ else if ((inst->opcode->flags & (F_SYS_READ | F_SYS_WRITE))
-+ == F_SYS_WRITE)
-+ info->sysreg.flags = F_REG_WRITE;
-+ }
-+
-+ return TRUE;
- }
-
- /* Decode the PSTATE field operand for e.g. MSR <pstatefield>, #<imm>. */
--int
-+bfd_boolean
- aarch64_ext_pstatefield (const aarch64_operand *self ATTRIBUTE_UNUSED,
- aarch64_opnd_info *info, aarch64_insn code,
-- const aarch64_inst *inst ATTRIBUTE_UNUSED)
-+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- int i;
- /* op1:op2 */
- info->pstatefield = extract_fields (code, 0, 2, FLD_op1, FLD_op2);
- for (i = 0; aarch64_pstatefields[i].name != NULL; ++i)
- if (aarch64_pstatefields[i].value == (aarch64_insn)info->pstatefield)
-- return 1;
-+ return TRUE;
- /* Reserved value in <pstatefield>. */
-- return 0;
-+ return FALSE;
- }
-
- /* Decode the system instruction op operand for e.g. AT <at_op>, <Xt>. */
--int
-+bfd_boolean
- aarch64_ext_sysins_op (const aarch64_operand *self ATTRIBUTE_UNUSED,
- aarch64_opnd_info *info,
- aarch64_insn code,
-- const aarch64_inst *inst ATTRIBUTE_UNUSED)
-+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- int i;
- aarch64_insn value;
-@@ -1176,7 +1255,13 @@ aarch64_ext_sysins_op (const aarch64_ope
- case AARCH64_OPND_SYSREG_DC: sysins_ops = aarch64_sys_regs_dc; break;
- case AARCH64_OPND_SYSREG_IC: sysins_ops = aarch64_sys_regs_ic; break;
- case AARCH64_OPND_SYSREG_TLBI: sysins_ops = aarch64_sys_regs_tlbi; break;
-- default: assert (0); return 0;
-+ case AARCH64_OPND_SYSREG_SR:
-+ sysins_ops = aarch64_sys_regs_sr;
-+ /* Let's remove op2 for rctx. Refer to comments in the definition of
-+ aarch64_sys_regs_sr[]. */
-+ value = value & ~(0x7);
-+ break;
-+ default: assert (0); return FALSE;
- }
-
- for (i = 0; sysins_ops[i].name != NULL; ++i)
-@@ -1187,46 +1272,64 @@ aarch64_ext_sysins_op (const aarch64_ope
- info->sysins_op->name,
- (unsigned)info->sysins_op->value,
- aarch64_sys_ins_reg_has_xt (info->sysins_op), i);
-- return 1;
-+ return TRUE;
- }
-
-- return 0;
-+ return FALSE;
- }
-
- /* Decode the memory barrier option operand for e.g. DMB <option>|#<imm>. */
-
--int
-+bfd_boolean
- aarch64_ext_barrier (const aarch64_operand *self ATTRIBUTE_UNUSED,
- aarch64_opnd_info *info,
- aarch64_insn code,
-- const aarch64_inst *inst ATTRIBUTE_UNUSED)
-+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- /* CRm */
- info->barrier = aarch64_barrier_options + extract_field (FLD_CRm, code, 0);
-- return 1;
-+ return TRUE;
-+}
-+
-+/* Decode the memory barrier option operand for DSB <option>nXS|#<imm>. */
-+
-+bfd_boolean
-+aarch64_ext_barrier_dsb_nxs (const aarch64_operand *self ATTRIBUTE_UNUSED,
-+ aarch64_opnd_info *info,
-+ aarch64_insn code,
-+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
-+{
-+ /* For the DSB nXS barrier variant immediate is encoded in 2-bit field. */
-+ aarch64_insn field = extract_field (FLD_CRm_dsb_nxs, code, 0);
-+ info->barrier = aarch64_barrier_dsb_nxs_options + field;
-+ return TRUE;
- }
-
- /* Decode the prefetch operation option operand for e.g.
- PRFM <prfop>, [<Xn|SP>{, #<pimm>}]. */
-
--int
-+bfd_boolean
- aarch64_ext_prfop (const aarch64_operand *self ATTRIBUTE_UNUSED,
- aarch64_opnd_info *info,
-- aarch64_insn code, const aarch64_inst *inst ATTRIBUTE_UNUSED)
-+ aarch64_insn code, const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- /* prfop in Rt */
- info->prfop = aarch64_prfops + extract_field (FLD_Rt, code, 0);
-- return 1;
-+ return TRUE;
- }
-
- /* Decode the hint number for an alias taking an operand. Set info->hint_option
- to the matching name/value pair in aarch64_hint_options. */
-
--int
-+bfd_boolean
- aarch64_ext_hint (const aarch64_operand *self ATTRIBUTE_UNUSED,
- aarch64_opnd_info *info,
- aarch64_insn code,
-- const aarch64_inst *inst ATTRIBUTE_UNUSED)
-+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- /* CRm:op2. */
- unsigned hint_number;
-@@ -1236,23 +1339,24 @@ aarch64_ext_hint (const aarch64_operand
-
- for (i = 0; aarch64_hint_options[i].name != NULL; i++)
- {
-- if (hint_number == aarch64_hint_options[i].value)
-+ if (hint_number == HINT_VAL (aarch64_hint_options[i].value))
- {
- info->hint_option = &(aarch64_hint_options[i]);
-- return 1;
-+ return TRUE;
- }
- }
-
-- return 0;
-+ return FALSE;
- }
-
- /* Decode the extended register operand for e.g.
- STR <Qt>, [<Xn|SP>, <R><m>{, <extend> {<amount>}}]. */
--int
-+bfd_boolean
- aarch64_ext_reg_extended (const aarch64_operand *self ATTRIBUTE_UNUSED,
- aarch64_opnd_info *info,
- aarch64_insn code,
-- const aarch64_inst *inst ATTRIBUTE_UNUSED)
-+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- aarch64_insn value;
-
-@@ -1276,16 +1380,17 @@ aarch64_ext_reg_extended (const aarch64_
- || info->shifter.kind == AARCH64_MOD_SXTX))
- info->qualifier = AARCH64_OPND_QLF_X;
-
-- return 1;
-+ return TRUE;
- }
-
- /* Decode the shifted register operand for e.g.
- SUBS <Xd>, <Xn>, <Xm> {, <shift> #<amount>}. */
--int
-+bfd_boolean
- aarch64_ext_reg_shifted (const aarch64_operand *self ATTRIBUTE_UNUSED,
- aarch64_opnd_info *info,
- aarch64_insn code,
-- const aarch64_inst *inst ATTRIBUTE_UNUSED)
-+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- aarch64_insn value;
-
-@@ -1299,21 +1404,21 @@ aarch64_ext_reg_shifted (const aarch64_o
- && inst->opcode->iclass != log_shift)
- /* ROR is not available for the shifted register operand in arithmetic
- instructions. */
-- return 0;
-+ return FALSE;
- /* imm6 */
- info->shifter.amount = extract_field (FLD_imm6, code, 0);
-
- /* This makes the constraint checking happy. */
- info->shifter.operator_present = 1;
-
-- return 1;
-+ return TRUE;
- }
-
- /* Decode an SVE address [<base>, #<offset>*<factor>, MUL VL],
- where <offset> is given by the OFFSET parameter and where <factor> is
- 1 plus SELF's operand-dependent value. fields[0] specifies the field
- that holds <base>. */
--static int
-+static bfd_boolean
- aarch64_ext_sve_addr_reg_mul_vl (const aarch64_operand *self,
- aarch64_opnd_info *info, aarch64_insn code,
- int64_t offset)
-@@ -1328,17 +1433,18 @@ aarch64_ext_sve_addr_reg_mul_vl (const a
- info->shifter.amount = 1;
- info->shifter.operator_present = (info->addr.offset.imm != 0);
- info->shifter.amount_present = FALSE;
-- return 1;
-+ return TRUE;
- }
-
- /* Decode an SVE address [<base>, #<simm4>*<factor>, MUL VL],
- where <simm4> is a 4-bit signed value and where <factor> is 1 plus
- SELF's operand-dependent value. fields[0] specifies the field that
- holds <base>. <simm4> is encoded in the SVE_imm4 field. */
--int
-+bfd_boolean
- aarch64_ext_sve_addr_ri_s4xvl (const aarch64_operand *self,
- aarch64_opnd_info *info, aarch64_insn code,
-- const aarch64_inst *inst ATTRIBUTE_UNUSED)
-+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- int offset;
-
-@@ -1351,10 +1457,11 @@ aarch64_ext_sve_addr_ri_s4xvl (const aar
- where <simm6> is a 6-bit signed value and where <factor> is 1 plus
- SELF's operand-dependent value. fields[0] specifies the field that
- holds <base>. <simm6> is encoded in the SVE_imm6 field. */
--int
-+bfd_boolean
- aarch64_ext_sve_addr_ri_s6xvl (const aarch64_operand *self,
- aarch64_opnd_info *info, aarch64_insn code,
-- const aarch64_inst *inst ATTRIBUTE_UNUSED)
-+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- int offset;
-
-@@ -1368,11 +1475,12 @@ aarch64_ext_sve_addr_ri_s6xvl (const aar
- SELF's operand-dependent value. fields[0] specifies the field that
- holds <base>. <simm9> is encoded in the concatenation of the SVE_imm6
- and imm3 fields, with imm3 being the less-significant part. */
--int
-+bfd_boolean
- aarch64_ext_sve_addr_ri_s9xvl (const aarch64_operand *self,
- aarch64_opnd_info *info,
- aarch64_insn code,
-- const aarch64_inst *inst ATTRIBUTE_UNUSED)
-+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- int offset;
-
-@@ -1384,7 +1492,7 @@ aarch64_ext_sve_addr_ri_s9xvl (const aar
- /* Decode an SVE address [<base>, #<offset> << <shift>], where <offset>
- is given by the OFFSET parameter and where <shift> is SELF's operand-
- dependent value. fields[0] specifies the base register field <base>. */
--static int
-+static bfd_boolean
- aarch64_ext_sve_addr_reg_imm (const aarch64_operand *self,
- aarch64_opnd_info *info, aarch64_insn code,
- int64_t offset)
-@@ -1396,16 +1504,17 @@ aarch64_ext_sve_addr_reg_imm (const aarc
- info->addr.preind = TRUE;
- info->shifter.operator_present = FALSE;
- info->shifter.amount_present = FALSE;
-- return 1;
-+ return TRUE;
- }
-
- /* Decode an SVE address [X<n>, #<SVE_imm4> << <shift>], where <SVE_imm4>
- is a 4-bit signed number and where <shift> is SELF's operand-dependent
- value. fields[0] specifies the base register field. */
--int
-+bfd_boolean
- aarch64_ext_sve_addr_ri_s4 (const aarch64_operand *self,
- aarch64_opnd_info *info, aarch64_insn code,
-- const aarch64_inst *inst ATTRIBUTE_UNUSED)
-+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- int offset = sign_extend (extract_field (FLD_SVE_imm4, code, 0), 3);
- return aarch64_ext_sve_addr_reg_imm (self, info, code, offset);
-@@ -1414,10 +1523,11 @@ aarch64_ext_sve_addr_ri_s4 (const aarch6
- /* Decode an SVE address [X<n>, #<SVE_imm6> << <shift>], where <SVE_imm6>
- is a 6-bit unsigned number and where <shift> is SELF's operand-dependent
- value. fields[0] specifies the base register field. */
--int
-+bfd_boolean
- aarch64_ext_sve_addr_ri_u6 (const aarch64_operand *self,
- aarch64_opnd_info *info, aarch64_insn code,
-- const aarch64_inst *inst ATTRIBUTE_UNUSED)
-+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- int offset = extract_field (FLD_SVE_imm6, code, 0);
- return aarch64_ext_sve_addr_reg_imm (self, info, code, offset);
-@@ -1426,16 +1536,17 @@ aarch64_ext_sve_addr_ri_u6 (const aarch6
- /* Decode an SVE address [X<n>, X<m>{, LSL #<shift>}], where <shift>
- is SELF's operand-dependent value. fields[0] specifies the base
- register field and fields[1] specifies the offset register field. */
--int
-+bfd_boolean
- aarch64_ext_sve_addr_rr_lsl (const aarch64_operand *self,
- aarch64_opnd_info *info, aarch64_insn code,
-- const aarch64_inst *inst ATTRIBUTE_UNUSED)
-+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- int index_regno;
-
- index_regno = extract_field (self->fields[1], code, 0);
- if (index_regno == 31 && (self->flags & OPD_F_NO_ZR) != 0)
-- return 0;
-+ return FALSE;
-
- info->addr.base_regno = extract_field (self->fields[0], code, 0);
- info->addr.offset.regno = index_regno;
-@@ -1446,17 +1557,18 @@ aarch64_ext_sve_addr_rr_lsl (const aarch
- info->shifter.amount = get_operand_specific_data (self);
- info->shifter.operator_present = (info->shifter.amount != 0);
- info->shifter.amount_present = (info->shifter.amount != 0);
-- return 1;
-+ return TRUE;
- }
-
- /* Decode an SVE address [X<n>, Z<m>.<T>, (S|U)XTW {#<shift>}], where
- <shift> is SELF's operand-dependent value. fields[0] specifies the
- base register field, fields[1] specifies the offset register field and
- fields[2] is a single-bit field that selects SXTW over UXTW. */
--int
-+bfd_boolean
- aarch64_ext_sve_addr_rz_xtw (const aarch64_operand *self,
- aarch64_opnd_info *info, aarch64_insn code,
-- const aarch64_inst *inst ATTRIBUTE_UNUSED)
-+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- info->addr.base_regno = extract_field (self->fields[0], code, 0);
- info->addr.offset.regno = extract_field (self->fields[1], code, 0);
-@@ -1470,16 +1582,17 @@ aarch64_ext_sve_addr_rz_xtw (const aarch
- info->shifter.amount = get_operand_specific_data (self);
- info->shifter.operator_present = TRUE;
- info->shifter.amount_present = (info->shifter.amount != 0);
-- return 1;
-+ return TRUE;
- }
-
- /* Decode an SVE address [Z<n>.<T>, #<imm5> << <shift>], where <imm5> is a
- 5-bit unsigned number and where <shift> is SELF's operand-dependent value.
- fields[0] specifies the base register field. */
--int
-+bfd_boolean
- aarch64_ext_sve_addr_zi_u5 (const aarch64_operand *self,
- aarch64_opnd_info *info, aarch64_insn code,
-- const aarch64_inst *inst ATTRIBUTE_UNUSED)
-+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- int offset = extract_field (FLD_imm5, code, 0);
- return aarch64_ext_sve_addr_reg_imm (self, info, code, offset);
-@@ -1489,7 +1602,7 @@ aarch64_ext_sve_addr_zi_u5 (const aarch6
- where <modifier> is given by KIND and where <msz> is a 2-bit unsigned
- number. fields[0] specifies the base register field and fields[1]
- specifies the offset register field. */
--static int
-+static bfd_boolean
- aarch64_ext_sve_addr_zz (const aarch64_operand *self, aarch64_opnd_info *info,
- aarch64_insn code, enum aarch64_modifier_kind kind)
- {
-@@ -1503,16 +1616,17 @@ aarch64_ext_sve_addr_zz (const aarch64_o
- info->shifter.operator_present = (kind != AARCH64_MOD_LSL
- || info->shifter.amount != 0);
- info->shifter.amount_present = (info->shifter.amount != 0);
-- return 1;
-+ return TRUE;
- }
-
- /* Decode an SVE address [Z<n>.<T>, Z<m>.<T>{, LSL #<msz>}], where
- <msz> is a 2-bit unsigned number. fields[0] specifies the base register
- field and fields[1] specifies the offset register field. */
--int
-+bfd_boolean
- aarch64_ext_sve_addr_zz_lsl (const aarch64_operand *self,
- aarch64_opnd_info *info, aarch64_insn code,
-- const aarch64_inst *inst ATTRIBUTE_UNUSED)
-+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- return aarch64_ext_sve_addr_zz (self, info, code, AARCH64_MOD_LSL);
- }
-@@ -1520,10 +1634,11 @@ aarch64_ext_sve_addr_zz_lsl (const aarch
- /* Decode an SVE address [Z<n>.<T>, Z<m>.<T>, SXTW {#<msz>}], where
- <msz> is a 2-bit unsigned number. fields[0] specifies the base register
- field and fields[1] specifies the offset register field. */
--int
-+bfd_boolean
- aarch64_ext_sve_addr_zz_sxtw (const aarch64_operand *self,
- aarch64_opnd_info *info, aarch64_insn code,
-- const aarch64_inst *inst ATTRIBUTE_UNUSED)
-+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- return aarch64_ext_sve_addr_zz (self, info, code, AARCH64_MOD_SXTW);
- }
-@@ -1531,17 +1646,18 @@ aarch64_ext_sve_addr_zz_sxtw (const aarc
- /* Decode an SVE address [Z<n>.<T>, Z<m>.<T>, UXTW {#<msz>}], where
- <msz> is a 2-bit unsigned number. fields[0] specifies the base register
- field and fields[1] specifies the offset register field. */
--int
-+bfd_boolean
- aarch64_ext_sve_addr_zz_uxtw (const aarch64_operand *self,
- aarch64_opnd_info *info, aarch64_insn code,
-- const aarch64_inst *inst ATTRIBUTE_UNUSED)
-+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- return aarch64_ext_sve_addr_zz (self, info, code, AARCH64_MOD_UXTW);
- }
-
- /* Finish decoding an SVE arithmetic immediate, given that INFO already
- has the raw field value and that the low 8 bits decode to VALUE. */
--static int
-+static bfd_boolean
- decode_sve_aimm (aarch64_opnd_info *info, int64_t value)
- {
- info->shifter.kind = AARCH64_MOD_LSL;
-@@ -1557,82 +1673,88 @@ decode_sve_aimm (aarch64_opnd_info *info
- info->shifter.operator_present = (info->shifter.amount != 0);
- info->shifter.amount_present = (info->shifter.amount != 0);
- info->imm.value = value;
-- return 1;
-+ return TRUE;
- }
-
- /* Decode an SVE ADD/SUB immediate. */
--int
-+bfd_boolean
- aarch64_ext_sve_aimm (const aarch64_operand *self,
- aarch64_opnd_info *info, const aarch64_insn code,
-- const aarch64_inst *inst)
-+ const aarch64_inst *inst,
-+ aarch64_operand_error *errors)
- {
-- return (aarch64_ext_imm (self, info, code, inst)
-+ return (aarch64_ext_imm (self, info, code, inst, errors)
- && decode_sve_aimm (info, (uint8_t) info->imm.value));
- }
-
- /* Decode an SVE CPY/DUP immediate. */
--int
-+bfd_boolean
- aarch64_ext_sve_asimm (const aarch64_operand *self,
- aarch64_opnd_info *info, const aarch64_insn code,
-- const aarch64_inst *inst)
-+ const aarch64_inst *inst,
-+ aarch64_operand_error *errors)
- {
-- return (aarch64_ext_imm (self, info, code, inst)
-+ return (aarch64_ext_imm (self, info, code, inst, errors)
- && decode_sve_aimm (info, (int8_t) info->imm.value));
- }
-
- /* Decode a single-bit immediate that selects between #0.5 and #1.0.
- The fields array specifies which field to use. */
--int
-+bfd_boolean
- aarch64_ext_sve_float_half_one (const aarch64_operand *self,
- aarch64_opnd_info *info, aarch64_insn code,
-- const aarch64_inst *inst ATTRIBUTE_UNUSED)
-+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- if (extract_field (self->fields[0], code, 0))
- info->imm.value = 0x3f800000;
- else
- info->imm.value = 0x3f000000;
- info->imm.is_fp = TRUE;
-- return 1;
-+ return TRUE;
- }
-
- /* Decode a single-bit immediate that selects between #0.5 and #2.0.
- The fields array specifies which field to use. */
--int
-+bfd_boolean
- aarch64_ext_sve_float_half_two (const aarch64_operand *self,
- aarch64_opnd_info *info, aarch64_insn code,
-- const aarch64_inst *inst ATTRIBUTE_UNUSED)
-+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- if (extract_field (self->fields[0], code, 0))
- info->imm.value = 0x40000000;
- else
- info->imm.value = 0x3f000000;
- info->imm.is_fp = TRUE;
-- return 1;
-+ return TRUE;
- }
-
- /* Decode a single-bit immediate that selects between #0.0 and #1.0.
- The fields array specifies which field to use. */
--int
-+bfd_boolean
- aarch64_ext_sve_float_zero_one (const aarch64_operand *self,
- aarch64_opnd_info *info, aarch64_insn code,
-- const aarch64_inst *inst ATTRIBUTE_UNUSED)
-+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- if (extract_field (self->fields[0], code, 0))
- info->imm.value = 0x3f800000;
- else
- info->imm.value = 0x0;
- info->imm.is_fp = TRUE;
-- return 1;
-+ return TRUE;
- }
-
- /* Decode Zn[MM], where MM has a 7-bit triangular encoding. The fields
- array specifies which field to use for Zn. MM is encoded in the
- concatenation of imm5 and SVE_tszh, with imm5 being the less
- significant part. */
--int
-+bfd_boolean
- aarch64_ext_sve_index (const aarch64_operand *self,
- aarch64_opnd_info *info, aarch64_insn code,
-- const aarch64_inst *inst ATTRIBUTE_UNUSED)
-+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- int val;
-
-@@ -1643,66 +1765,69 @@ aarch64_ext_sve_index (const aarch64_ope
- while ((val & 1) == 0)
- val /= 2;
- info->reglane.index = val / 2;
-- return 1;
-+ return TRUE;
- }
-
- /* Decode a logical immediate for the MOV alias of SVE DUPM. */
--int
-+bfd_boolean
- aarch64_ext_sve_limm_mov (const aarch64_operand *self,
- aarch64_opnd_info *info, const aarch64_insn code,
-- const aarch64_inst *inst)
-+ const aarch64_inst *inst,
-+ aarch64_operand_error *errors)
- {
- int esize = aarch64_get_qualifier_esize (inst->operands[0].qualifier);
-- return (aarch64_ext_limm (self, info, code, inst)
-+ return (aarch64_ext_limm (self, info, code, inst, errors)
- && aarch64_sve_dupm_mov_immediate_p (info->imm.value, esize));
- }
-
- /* Decode Zn[MM], where Zn occupies the least-significant part of the field
- and where MM occupies the most-significant part. The operand-dependent
- value specifies the number of bits in Zn. */
--int
-+bfd_boolean
- aarch64_ext_sve_quad_index (const aarch64_operand *self,
- aarch64_opnd_info *info, aarch64_insn code,
-- const aarch64_inst *inst ATTRIBUTE_UNUSED)
-+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- unsigned int reg_bits = get_operand_specific_data (self);
- unsigned int val = extract_all_fields (self, code);
- info->reglane.regno = val & ((1 << reg_bits) - 1);
- info->reglane.index = val >> reg_bits;
-- return 1;
-+ return TRUE;
- }
-
- /* Decode {Zn.<T> - Zm.<T>}. The fields array specifies which field
- to use for Zn. The opcode-dependent value specifies the number
- of registers in the list. */
--int
-+bfd_boolean
- aarch64_ext_sve_reglist (const aarch64_operand *self,
- aarch64_opnd_info *info, aarch64_insn code,
-- const aarch64_inst *inst ATTRIBUTE_UNUSED)
-+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- info->reglist.first_regno = extract_field (self->fields[0], code, 0);
- info->reglist.num_regs = get_opcode_dependent_value (inst->opcode);
-- return 1;
-+ return TRUE;
- }
-
- /* Decode <pattern>{, MUL #<amount>}. The fields array specifies which
- fields to use for <pattern>. <amount> - 1 is encoded in the SVE_imm4
- field. */
--int
-+bfd_boolean
- aarch64_ext_sve_scale (const aarch64_operand *self,
- aarch64_opnd_info *info, aarch64_insn code,
-- const aarch64_inst *inst)
-+ const aarch64_inst *inst, aarch64_operand_error *errors)
- {
- int val;
-
-- if (!aarch64_ext_imm (self, info, code, inst))
-- return 0;
-+ if (!aarch64_ext_imm (self, info, code, inst, errors))
-+ return FALSE;
- val = extract_field (FLD_SVE_imm4, code, 0);
- info->shifter.kind = AARCH64_MOD_MUL;
- info->shifter.amount = val + 1;
- info->shifter.operator_present = (val != 0);
- info->shifter.amount_present = (val != 0);
-- return 1;
-+ return TRUE;
- }
-
- /* Return the top set bit in VALUE, which is expected to be relatively
-@@ -1716,31 +1841,31 @@ get_top_bit (uint64_t value)
- }
-
- /* Decode an SVE shift-left immediate. */
--int
-+bfd_boolean
- aarch64_ext_sve_shlimm (const aarch64_operand *self,
- aarch64_opnd_info *info, const aarch64_insn code,
-- const aarch64_inst *inst)
-+ const aarch64_inst *inst, aarch64_operand_error *errors)
- {
-- if (!aarch64_ext_imm (self, info, code, inst)
-+ if (!aarch64_ext_imm (self, info, code, inst, errors)
- || info->imm.value == 0)
-- return 0;
-+ return FALSE;
-
- info->imm.value -= get_top_bit (info->imm.value);
-- return 1;
-+ return TRUE;
- }
-
- /* Decode an SVE shift-right immediate. */
--int
-+bfd_boolean
- aarch64_ext_sve_shrimm (const aarch64_operand *self,
- aarch64_opnd_info *info, const aarch64_insn code,
-- const aarch64_inst *inst)
-+ const aarch64_inst *inst, aarch64_operand_error *errors)
- {
-- if (!aarch64_ext_imm (self, info, code, inst)
-+ if (!aarch64_ext_imm (self, info, code, inst, errors)
- || info->imm.value == 0)
-- return 0;
-+ return FALSE;
-
- info->imm.value = get_top_bit (info->imm.value) * 2 - info->imm.value;
-- return 1;
-+ return TRUE;
- }
-
- /* Bitfields that are commonly used to encode certain operands' information
-@@ -2474,8 +2599,9 @@ convert_to_alias (aarch64_inst *inst, co
- }
- }
-
--static int aarch64_opcode_decode (const aarch64_opcode *, const aarch64_insn,
-- aarch64_inst *, int);
-+static bfd_boolean
-+aarch64_opcode_decode (const aarch64_opcode *, const aarch64_insn,
-+ aarch64_inst *, int, aarch64_operand_error *errors);
-
- /* Given the instruction information in *INST, check if the instruction has
- any alias form that can be used to represent *INST. If the answer is yes,
-@@ -2531,7 +2657,8 @@ static int aarch64_opcode_decode (const
- aarch64_find_next_alias_opcode (in opcodes/aarch64-dis-2.c) to help. */
-
- static void
--determine_disassembling_preference (struct aarch64_inst *inst)
-+determine_disassembling_preference (struct aarch64_inst *inst,
-+ aarch64_operand_error *errors)
- {
- const aarch64_opcode *opcode;
- const aarch64_opcode *alias;
-@@ -2578,6 +2705,13 @@ determine_disassembling_preference (stru
- DEBUG_TRACE ("skip %s as base opcode not match", alias->name);
- continue;
- }
-+
-+ if (!AARCH64_CPU_HAS_FEATURE (arch_variant, *alias->avariant))
-+ {
-+ DEBUG_TRACE ("skip %s: we're missing features", alias->name);
-+ continue;
-+ }
-+
- /* No need to do any complicated transformation on operands, if the alias
- opcode does not have any operand. */
- if (aarch64_num_of_operands (alias) == 0 && alias->opcode == inst->value)
-@@ -2594,8 +2728,10 @@ determine_disassembling_preference (stru
- successfully converted to the form of ALIAS. */
- if (convert_to_alias (©, alias) == 1)
- {
-+ int res;
- aarch64_replace_opcode (©, alias);
-- assert (aarch64_match_operands_constraint (©, NULL));
-+ res = aarch64_match_operands_constraint (©, NULL);
-+ assert (res == 1);
- DEBUG_TRACE ("succeed with %s via conversion", alias->name);
- memcpy (inst, ©, sizeof (aarch64_inst));
- return;
-@@ -2606,7 +2742,7 @@ determine_disassembling_preference (stru
- /* Directly decode the alias opcode. */
- aarch64_inst temp;
- memset (&temp, '\0', sizeof (aarch64_inst));
-- if (aarch64_opcode_decode (alias, inst->value, &temp, 1) == 1)
-+ if (aarch64_opcode_decode (alias, inst->value, &temp, 1, errors) == 1)
- {
- DEBUG_TRACE ("succeed with %s via direct decoding", alias->name);
- memcpy (inst, &temp, sizeof (aarch64_inst));
-@@ -2702,10 +2838,64 @@ aarch64_decode_variant_using_iclass (aar
- variant = i - 1;
- break;
-
-+ case sve_size_bh:
- case sve_size_sd:
- variant = extract_field (FLD_SVE_sz, inst->value, 0);
- break;
-
-+ case sve_size_sd2:
-+ variant = extract_field (FLD_SVE_sz2, inst->value, 0);
-+ break;
-+
-+ case sve_size_hsd2:
-+ i = extract_field (FLD_SVE_size, inst->value, 0);
-+ if (i < 1)
-+ return FALSE;
-+ variant = i - 1;
-+ break;
-+
-+ case sve_size_13:
-+ /* Ignore low bit of this field since that is set in the opcode for
-+ instructions of this iclass. */
-+ i = (extract_field (FLD_size, inst->value, 0) & 2);
-+ variant = (i >> 1);
-+ break;
-+
-+ case sve_shift_tsz_bhsd:
-+ i = extract_fields (inst->value, 0, 2, FLD_SVE_tszh, FLD_SVE_tszl_19);
-+ if (i == 0)
-+ return FALSE;
-+ while (i != 1)
-+ {
-+ i >>= 1;
-+ variant += 1;
-+ }
-+ break;
-+
-+ case sve_size_tsz_bhs:
-+ i = extract_fields (inst->value, 0, 2, FLD_SVE_sz, FLD_SVE_tszl_19);
-+ if (i == 0)
-+ return FALSE;
-+ while (i != 1)
-+ {
-+ if (i & 1)
-+ return FALSE;
-+ i >>= 1;
-+ variant += 1;
-+ }
-+ break;
-+
-+ case sve_shift_tsz_hsd:
-+ i = extract_fields (inst->value, 0, 2, FLD_SVE_sz, FLD_SVE_tszl_19);
-+ if (i == 0)
-+ return FALSE;
-+ while (i != 1)
-+ {
-+ i >>= 1;
-+ variant += 1;
-+ }
-+ break;
-+
- default:
- /* No mapping between instruction class and qualifiers. */
- return TRUE;
-@@ -2723,9 +2913,10 @@ aarch64_decode_variant_using_iclass (aar
- determined and used to disassemble CODE; this is done just before the
- return. */
-
--static int
-+static bfd_boolean
- aarch64_opcode_decode (const aarch64_opcode *opcode, const aarch64_insn code,
-- aarch64_inst *inst, int noaliases_p)
-+ aarch64_inst *inst, int noaliases_p,
-+ aarch64_operand_error *errors)
- {
- int i;
-
-@@ -2733,6 +2924,9 @@ aarch64_opcode_decode (const aarch64_opc
-
- assert (opcode && inst);
-
-+ /* Clear inst. */
-+ memset (inst, '\0', sizeof (aarch64_inst));
-+
- /* Check the base opcode. */
- if ((code & opcode->mask) != (opcode->opcode & opcode->mask))
- {
-@@ -2740,9 +2934,6 @@ aarch64_opcode_decode (const aarch64_opc
- goto decode_fail;
- }
-
-- /* Clear inst. */
-- memset (inst, '\0', sizeof (aarch64_inst));
--
- inst->opcode = opcode;
- inst->value = code;
-
-@@ -2781,7 +2972,8 @@ aarch64_opcode_decode (const aarch64_opc
- break;
- opnd = &aarch64_operands[type];
- if (operand_has_extractor (opnd)
-- && (! aarch64_extract_operand (opnd, &inst->operands[i], code, inst)))
-+ && (! aarch64_extract_operand (opnd, &inst->operands[i], code, inst,
-+ errors)))
- {
- DEBUG_TRACE ("operand decoder FAIL at operand %d", i);
- goto decode_fail;
-@@ -2789,7 +2981,8 @@ aarch64_opcode_decode (const aarch64_opc
- }
-
- /* If the opcode has a verifier, then check it now. */
-- if (opcode->verifier && ! opcode->verifier (opcode, code))
-+ if (opcode->verifier
-+ && opcode->verifier (inst, code, 0, FALSE, errors, NULL) != ERR_OK)
- {
- DEBUG_TRACE ("operand verifier FAIL");
- goto decode_fail;
-@@ -2804,17 +2997,17 @@ aarch64_opcode_decode (const aarch64_opc
- alias and should be disassembled in the form of its alias instead.
- If the answer is yes, *INST will be updated. */
- if (!noaliases_p)
-- determine_disassembling_preference (inst);
-+ determine_disassembling_preference (inst, errors);
- DEBUG_TRACE ("SUCCESS");
-- return 1;
-+ return TRUE;
- }
- else
- {
- DEBUG_TRACE ("constraint matching FAIL");
- }
-
--decode_fail:
-- return 0;
-+ decode_fail:
-+ return FALSE;
- }
-
- /* This does some user-friendly fix-up to *INST. It is currently focus on
-@@ -2844,9 +3037,10 @@ user_friendly_fixup (aarch64_inst *inst)
- opcode may be filled in *INSN if NOALIASES_P is FALSE. Return zero on
- success. */
-
--int
-+enum err_type
- aarch64_decode_insn (aarch64_insn insn, aarch64_inst *inst,
-- bfd_boolean noaliases_p)
-+ bfd_boolean noaliases_p,
-+ aarch64_operand_error *errors)
- {
- const aarch64_opcode *opcode = aarch64_opcode_lookup (insn);
-
-@@ -2873,7 +3067,7 @@ aarch64_decode_insn (aarch64_insn insn,
- {
- /* But only one opcode can be decoded successfully for, as the
- decoding routine will check the constraint carefully. */
-- if (aarch64_opcode_decode (opcode, insn, inst, noaliases_p) == 1)
-+ if (aarch64_opcode_decode (opcode, insn, inst, noaliases_p, errors) == 1)
- return ERR_OK;
- opcode = aarch64_find_next_opcode (opcode);
- }
-@@ -2885,8 +3079,10 @@ aarch64_decode_insn (aarch64_insn insn,
-
- static void
- print_operands (bfd_vma pc, const aarch64_opcode *opcode,
-- const aarch64_opnd_info *opnds, struct disassemble_info *info)
-+ const aarch64_opnd_info *opnds, struct disassemble_info *info,
-+ bfd_boolean *has_notes)
- {
-+ char *notes = NULL;
- int i, pcrel_p, num_printed;
- for (i = 0, num_printed = 0; i < AARCH64_MAX_OPND_NUM; ++i)
- {
-@@ -2902,7 +3098,7 @@ print_operands (bfd_vma pc, const aarch6
-
- /* Generate the operand string in STR. */
- aarch64_print_operand (str, sizeof (str), pc, opcode, opnds, i, &pcrel_p,
-- &info->target);
-+ &info->target, ¬es, arch_variant);
-
- /* Print the delimiter (taking account of omitted operand(s)). */
- if (str[0] != '\0')
-@@ -2915,6 +3111,12 @@ print_operands (bfd_vma pc, const aarch6
- else
- (*info->fprintf_func) (info->stream, "%s", str);
- }
-+
-+ if (notes && !no_notes)
-+ {
-+ *has_notes = TRUE;
-+ (*info->fprintf_func) (info->stream, " // note: %s", notes);
-+ }
- }
-
- /* Set NAME to a copy of INST's mnemonic with the "." suffix removed. */
-@@ -2972,15 +3174,63 @@ print_comment (const aarch64_inst *inst,
- }
- }
-
-+/* Build notes from verifiers into a string for printing. */
-+
-+static void
-+print_verifier_notes (aarch64_operand_error *detail,
-+ struct disassemble_info *info)
-+{
-+ if (no_notes)
-+ return;
-+
-+ /* The output of the verifier cannot be a fatal error, otherwise the assembly
-+ would not have succeeded. We can safely ignore these. */
-+ assert (detail->non_fatal);
-+ assert (detail->error);
-+
-+ /* If there are multiple verifier messages, concat them up to 1k. */
-+ (*info->fprintf_func) (info->stream, " // note: %s", detail->error);
-+ if (detail->index >= 0)
-+ (*info->fprintf_func) (info->stream, " at operand %d", detail->index + 1);
-+}
-+
- /* Print the instruction according to *INST. */
-
- static void
- print_aarch64_insn (bfd_vma pc, const aarch64_inst *inst,
-- struct disassemble_info *info)
-+ const aarch64_insn code,
-+ struct disassemble_info *info,
-+ aarch64_operand_error *mismatch_details)
- {
-+ bfd_boolean has_notes = FALSE;
-+
- print_mnemonic_name (inst, info);
-- print_operands (pc, inst->opcode, inst->operands, info);
-+ print_operands (pc, inst->opcode, inst->operands, info, &has_notes);
- print_comment (inst, info);
-+
-+ /* We've already printed a note, not enough space to print more so exit.
-+ Usually notes shouldn't overlap so it shouldn't happen that we have a note
-+ from a register and instruction at the same time. */
-+ if (has_notes)
-+ return;
-+
-+ /* Always run constraint verifiers, this is needed because constraints need to
-+ maintain a global state regardless of whether the instruction has the flag
-+ set or not. */
-+ enum err_type result = verify_constraints (inst, code, pc, FALSE,
-+ mismatch_details, &insn_sequence);
-+ switch (result)
-+ {
-+ case ERR_UND:
-+ case ERR_UNP:
-+ case ERR_NYI:
-+ assert (0);
-+ case ERR_VFI:
-+ print_verifier_notes (mismatch_details, info);
-+ break;
-+ default:
-+ break;
-+ }
- }
-
- /* Entry-point of the instruction disassembler and printer. */
-@@ -2988,17 +3238,18 @@ print_aarch64_insn (bfd_vma pc, const aa
- static void
- print_insn_aarch64_word (bfd_vma pc,
- uint32_t word,
-- struct disassemble_info *info)
-+ struct disassemble_info *info,
-+ aarch64_operand_error *errors)
- {
-- static const char *err_msg[6] =
-+ static const char *err_msg[ERR_NR_ENTRIES+1] =
- {
-- [ERR_OK] = "_",
-- [-ERR_UND] = "undefined",
-- [-ERR_UNP] = "unpredictable",
-- [-ERR_NYI] = "NYI"
-+ [ERR_OK] = "_",
-+ [ERR_UND] = "undefined",
-+ [ERR_UNP] = "unpredictable",
-+ [ERR_NYI] = "NYI"
- };
-
-- int ret;
-+ enum err_type ret;
- aarch64_inst inst;
-
- info->insn_info_valid = 1;
-@@ -3015,7 +3266,7 @@ print_insn_aarch64_word (bfd_vma pc,
- addresses, since the addend is not currently pc-relative. */
- pc = 0;
-
-- ret = aarch64_decode_insn (word, &inst, no_aliases);
-+ ret = aarch64_decode_insn (word, &inst, no_aliases, errors);
-
- if (((word >> 21) & 0x3ff) == 1)
- {
-@@ -3032,11 +3283,11 @@ print_insn_aarch64_word (bfd_vma pc,
- /* Handle undefined instructions. */
- info->insn_type = dis_noninsn;
- (*info->fprintf_func) (info->stream,".inst\t0x%08x ; %s",
-- word, err_msg[-ret]);
-+ word, err_msg[ret]);
- break;
- case ERR_OK:
- user_friendly_fixup (&inst);
-- print_aarch64_insn (pc, &inst, info);
-+ print_aarch64_insn (pc, &inst, word, info, errors);
- break;
- default:
- abort ();
-@@ -3068,7 +3319,8 @@ aarch64_symbol_is_valid (asymbol * sym,
- static void
- print_insn_data (bfd_vma pc ATTRIBUTE_UNUSED,
- uint32_t word,
-- struct disassemble_info *info)
-+ struct disassemble_info *info,
-+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
- {
- switch (info->bytes_per_chunk)
- {
-@@ -3093,6 +3345,7 @@ static int
- get_sym_code_type (struct disassemble_info *info, int n,
- enum map_type *map_type)
- {
-+ asymbol * as;
- elf_symbol_type *es;
- unsigned int type;
- const char *name;
-@@ -3101,7 +3354,14 @@ get_sym_code_type (struct disassemble_in
- if (info->section != NULL && info->section != info->symtab[n]->section)
- return FALSE;
-
-- es = *(elf_symbol_type **)(info->symtab + n);
-+ if (n >= info->symtab_size)
-+ return FALSE;
-+
-+ as = info->symtab[n];
-+ if (bfd_asymbol_flavour (as) != bfd_target_elf_flavour)
-+ return FALSE;
-+ es = (elf_symbol_type *) as;
-+
- type = ELF_ST_TYPE (es->internal_elf_sym.st_info);
-
- /* If the symbol has function type then use that. */
-@@ -3124,6 +3384,24 @@ get_sym_code_type (struct disassemble_in
- return FALSE;
- }
-
-+/* Set the feature bits in arch_variant in order to get the correct disassembly
-+ for the chosen architecture variant.
-+
-+ Currently we only restrict disassembly for Armv8-R and otherwise enable all
-+ non-R-profile features. */
-+static void
-+select_aarch64_variant (unsigned mach)
-+{
-+ switch (mach)
-+ {
-+ case bfd_mach_aarch64_8R:
-+ arch_variant = AARCH64_ARCH_V8_R;
-+ break;
-+ default:
-+ arch_variant = AARCH64_ANY & ~(AARCH64_FEATURE_V8_R);
-+ }
-+}
-+
- /* Entry-point of the AArch64 disassembler. */
-
- int
-@@ -3132,10 +3410,13 @@ print_insn_aarch64 (bfd_vma pc,
- {
- bfd_byte buffer[INSNLEN];
- int status;
-- void (*printer) (bfd_vma, uint32_t, struct disassemble_info *);
-+ void (*printer) (bfd_vma, uint32_t, struct disassemble_info *,
-+ aarch64_operand_error *);
- bfd_boolean found = FALSE;
- unsigned int size = 4;
- unsigned long data;
-+ aarch64_operand_error errors;
-+ static bfd_boolean set_features;
-
- if (info->disassembler_options)
- {
-@@ -3147,17 +3428,35 @@ print_insn_aarch64 (bfd_vma pc,
- info->disassembler_options = NULL;
- }
-
-+ if (!set_features)
-+ {
-+ select_aarch64_variant (info->mach);
-+ set_features = TRUE;
-+ }
-+
- /* Aarch64 instructions are always little-endian */
- info->endian_code = BFD_ENDIAN_LITTLE;
-
-+ /* Default to DATA. A text section is required by the ABI to contain an
-+ INSN mapping symbol at the start. A data section has no such
-+ requirement, hence if no mapping symbol is found the section must
-+ contain only data. This however isn't very useful if the user has
-+ fully stripped the binaries. If this is the case use the section
-+ attributes to determine the default. If we have no section default to
-+ INSN as well, as we may be disassembling some raw bytes on a baremetal
-+ HEX file or similar. */
-+ enum map_type type = MAP_DATA;
-+ if ((info->section && info->section->flags & SEC_CODE) || !info->section)
-+ type = MAP_INSN;
-+
- /* First check the full symtab for a mapping symbol, even if there
- are no usable non-mapping symbols for this address. */
- if (info->symtab_size != 0
- && bfd_asymbol_flavour (*info->symtab) == bfd_target_elf_flavour)
- {
-- enum map_type type = MAP_INSN;
- int last_sym = -1;
-- bfd_vma addr;
-+ bfd_vma addr, section_vma = 0;
-+ bfd_boolean can_use_search_opt_p;
- int n;
-
- if (pc <= last_mapping_addr)
-@@ -3166,10 +3465,19 @@ print_insn_aarch64 (bfd_vma pc,
- /* Start scanning at the start of the function, or wherever
- we finished last time. */
- n = info->symtab_pos + 1;
-- if (n < last_mapping_sym)
-+
-+ /* If the last stop offset is different from the current one it means we
-+ are disassembling a different glob of bytes. As such the optimization
-+ would not be safe and we should start over. */
-+ can_use_search_opt_p = last_mapping_sym >= 0;
-+
-+ if (n >= last_mapping_sym && can_use_search_opt_p)
- n = last_mapping_sym;
-
-- /* Scan up to the location being disassembled. */
-+ /* Look down while we haven't passed the location being disassembled.
-+ The reason for this is that there's no defined order between a symbol
-+ and an mapping symbol that may be at the same address. We may have to
-+ look at least one position ahead. */
- for (; n < info->symtab_size; n++)
- {
- addr = bfd_asymbol_value (info->symtab[n]);
-@@ -3185,13 +3493,24 @@ print_insn_aarch64 (bfd_vma pc,
- if (!found)
- {
- n = info->symtab_pos;
-- if (n < last_mapping_sym)
-+ if (n >= last_mapping_sym && can_use_search_opt_p)
- n = last_mapping_sym;
-
- /* No mapping symbol found at this address. Look backwards
-- for a preceeding one. */
-+ for a preceeding one, but don't go pass the section start
-+ otherwise a data section with no mapping symbol can pick up
-+ a text mapping symbol of a preceeding section. The documentation
-+ says section can be NULL, in which case we will seek up all the
-+ way to the top. */
-+ if (info->section)
-+ section_vma = info->section->vma;
-+
- for (; n >= 0; n--)
- {
-+ addr = bfd_asymbol_value (info->symtab[n]);
-+ if (addr < section_vma)
-+ break;
-+
- if (get_sym_code_type (info, n, &type))
- {
- last_sym = n;
-@@ -3228,8 +3547,11 @@ print_insn_aarch64 (bfd_vma pc,
- size = (pc & 1) ? 1 : 2;
- }
- }
-+ else
-+ last_type = type;
-
-- if (last_type == MAP_DATA)
-+ /* PR 10263: Disassemble data if requested to do so by the user. */
-+ if (last_type == MAP_DATA && ((info->flags & DISASSEMBLE_DATA) == 0))
- {
- /* size was set above. */
- info->bytes_per_chunk = size;
-@@ -3253,7 +3575,7 @@ print_insn_aarch64 (bfd_vma pc,
- data = bfd_get_bits (buffer, size * 8,
- info->display_endian == BFD_ENDIAN_BIG);
-
-- (*printer) (pc, data, info);
-+ (*printer) (pc, data, info, &errors);
-
- return size;
- }
-@@ -3271,6 +3593,12 @@ with the -M switch (multiple options sho
- fprintf (stream, _("\n\
- aliases Do print instruction aliases.\n"));
-
-+ fprintf (stream, _("\n\
-+ no-notes Don't print instruction notes.\n"));
-+
-+ fprintf (stream, _("\n\
-+ notes Do print instruction notes.\n"));
-+
- #ifdef DEBUG_AARCH64
- fprintf (stream, _("\n\
- debug_dump Temp switch for debug trace.\n"));
-diff -rup binutils-2.30/opcodes/aarch64-dis.h binutils-2.30.new/opcodes/aarch64-dis.h
---- binutils-2.30/opcodes/aarch64-dis.h 2018-01-13 13:31:16.000000000 +0000
-+++ binutils-2.30.new/opcodes/aarch64-dis.h 2021-03-23 16:19:53.173776264 +0000
-@@ -1,5 +1,5 @@
- /* aarch64-dis.h -- Header file for aarch64-dis.c and aarch64-dis-2.c.
-- Copyright (C) 2012-2018 Free Software Foundation, Inc.
-+ Copyright (C) 2012-2021 Free Software Foundation, Inc.
- Contributed by ARM Ltd.
-
- This file is part of the GNU opcodes library.
-@@ -50,15 +50,19 @@ const aarch64_opcode* aarch64_find_next_
-
- /* Switch-table-based high-level operand extractor. */
-
--int aarch64_extract_operand (const aarch64_operand *, aarch64_opnd_info *,
-- const aarch64_insn, const aarch64_inst *);
-+bfd_boolean
-+aarch64_extract_operand (const aarch64_operand *, aarch64_opnd_info *,
-+ const aarch64_insn, const aarch64_inst *,
-+ aarch64_operand_error *);
-
- /* Operand extractors. */
-
- #define AARCH64_DECL_OPD_EXTRACTOR(x) \
-- int aarch64_##x (const aarch64_operand *, aarch64_opnd_info *, \
-- const aarch64_insn, const aarch64_inst *)
-+ bfd_boolean aarch64_##x (const aarch64_operand *, aarch64_opnd_info *, \
-+ const aarch64_insn, const aarch64_inst *, \
-+ aarch64_operand_error *)
-
-+AARCH64_DECL_OPD_EXTRACTOR (ext_none);
- AARCH64_DECL_OPD_EXTRACTOR (ext_regno);
- AARCH64_DECL_OPD_EXTRACTOR (ext_regno_pair);
- AARCH64_DECL_OPD_EXTRACTOR (ext_regrt_sysins);
-@@ -90,6 +94,7 @@ AARCH64_DECL_OPD_EXTRACTOR (ext_sysreg);
- AARCH64_DECL_OPD_EXTRACTOR (ext_pstatefield);
- AARCH64_DECL_OPD_EXTRACTOR (ext_sysins_op);
- AARCH64_DECL_OPD_EXTRACTOR (ext_barrier);
-+AARCH64_DECL_OPD_EXTRACTOR (ext_barrier_dsb_nxs);
- AARCH64_DECL_OPD_EXTRACTOR (ext_hint);
- AARCH64_DECL_OPD_EXTRACTOR (ext_prfop);
- AARCH64_DECL_OPD_EXTRACTOR (ext_reg_extended);
-diff -rup binutils-2.30/opcodes/aarch64-gen.c binutils-2.30.new/opcodes/aarch64-gen.c
---- binutils-2.30/opcodes/aarch64-gen.c 2018-01-13 13:31:16.000000000 +0000
-+++ binutils-2.30.new/opcodes/aarch64-gen.c 2021-03-23 16:19:53.174776257 +0000
-@@ -1,6 +1,6 @@
- /* aarch64-gen.c -- Generate tables and routines for opcode lookup and
- instruction encoding and decoding.
-- Copyright (C) 2012-2018 Free Software Foundation, Inc.
-+ Copyright (C) 2012-2021 Free Software Foundation, Inc.
- Contributed by ARM Ltd.
-
- This file is part of the GNU opcodes library.
-@@ -249,7 +249,7 @@ divide_table_1 (struct bittree *bittree,
- goto divide_table_1_finish;
- }
-
--divide_table_1_try_again:
-+ divide_table_1_try_again:
- mask_and = -1;
- ent = opcode;
- while (ent)
-@@ -339,7 +339,7 @@ divide_table_1_try_again:
- divide_table_1 (bittree->bits[0], list0.next);
- divide_table_1 (bittree->bits[1], list1.next);
-
--divide_table_1_finish:
-+ divide_table_1_finish:
- if (debug)
- printf ("Leave from depth %d\n", depth);
- --depth;
-@@ -984,10 +984,11 @@ print_operand_inserter (void)
- printf ("Enter print_operand_inserter\n");
-
- printf ("\n");
-- printf ("const char*\n");
-+ printf ("bfd_boolean\n");
- printf ("aarch64_insert_operand (const aarch64_operand *self,\n\
- const aarch64_opnd_info *info,\n\
-- aarch64_insn *code, const aarch64_inst *inst)\n");
-+ aarch64_insn *code, const aarch64_inst *inst,\n\
-+ aarch64_operand_error *errors)\n");
- printf ("{\n");
- printf (" /* Use the index as the key. */\n");
- printf (" int key = self - aarch64_operands;\n");
-@@ -1017,7 +1018,7 @@ print_operand_inserter (void)
- opnd2->processed = 1;
- }
- }
-- printf (" return aarch64_%s (self, info, code, inst);\n",
-+ printf (" return aarch64_%s (self, info, code, inst, errors);\n",
- opnd->inserter);
- }
- }
-@@ -1040,10 +1041,11 @@ print_operand_extractor (void)
- printf ("Enter print_operand_extractor\n");
-
- printf ("\n");
-- printf ("int\n");
-+ printf ("bfd_boolean\n");
- printf ("aarch64_extract_operand (const aarch64_operand *self,\n\
- aarch64_opnd_info *info,\n\
-- aarch64_insn code, const aarch64_inst *inst)\n");
-+ aarch64_insn code, const aarch64_inst *inst,\n\
-+ aarch64_operand_error *errors)\n");
- printf ("{\n");
- printf (" /* Use the index as the key. */\n");
- printf (" int key = self - aarch64_operands;\n");
-@@ -1073,7 +1075,7 @@ print_operand_extractor (void)
- opnd2->processed = 1;
- }
- }
-- printf (" return aarch64_%s (self, info, code, inst);\n",
-+ printf (" return aarch64_%s (self, info, code, inst, errors);\n",
- opnd->extractor);
- }
- }
-@@ -1244,7 +1246,7 @@ main (int argc, char **argv)
- print_divide_result (decoder_tree);
-
- printf ("/* This file is automatically generated by aarch64-gen. Do not edit! */\n");
-- printf ("/* Copyright (C) 2012-2018 Free Software Foundation, Inc.\n\
-+ printf ("/* Copyright (C) 2012-2021 Free Software Foundation, Inc.\n\
- Contributed by ARM Ltd.\n\
- \n\
- This file is part of the GNU opcodes library.\n\
-diff -rup binutils-2.30/opcodes/aarch64-opc-2.c binutils-2.30.new/opcodes/aarch64-opc-2.c
---- binutils-2.30/opcodes/aarch64-opc-2.c 2018-01-13 13:31:16.000000000 +0000
-+++ binutils-2.30.new/opcodes/aarch64-opc-2.c 2021-03-23 16:19:53.181776209 +0000
-@@ -1,5 +1,5 @@
- /* This file is automatically generated by aarch64-gen. Do not edit! */
--/* Copyright (C) 2012-2018 Free Software Foundation, Inc.
-+/* Copyright (C) 2012-2021 Free Software Foundation, Inc.
- Contributed by ARM Ltd.
-
- This file is part of the GNU opcodes library.
-@@ -30,6 +30,8 @@ const struct aarch64_operand aarch64_ope
- {AARCH64_OPND_CLASS_INT_REG, "Rm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "an integer register"},
- {AARCH64_OPND_CLASS_INT_REG, "Rt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rt}, "an integer register"},
- {AARCH64_OPND_CLASS_INT_REG, "Rt2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rt2}, "an integer register"},
-+ {AARCH64_OPND_CLASS_INT_REG, "Rt_LS64", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rt}, "an integer register"},
-+ {AARCH64_OPND_CLASS_INT_REG, "Rt_SP", OPD_F_MAYBE_SP | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rt}, "an integer or stack pointer register"},
- {AARCH64_OPND_CLASS_INT_REG, "Rs", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rs}, "an integer register"},
- {AARCH64_OPND_CLASS_INT_REG, "Ra", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Ra}, "an integer register"},
- {AARCH64_OPND_CLASS_INT_REG, "Rt_SYS", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rt}, "an integer register"},
-@@ -57,6 +59,7 @@ const struct aarch64_operand aarch64_ope
- {AARCH64_OPND_CLASS_SIMD_ELEMENT, "Ed", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "a SIMD vector element"},
- {AARCH64_OPND_CLASS_SIMD_ELEMENT, "En", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "a SIMD vector element"},
- {AARCH64_OPND_CLASS_SIMD_ELEMENT, "Em", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "a SIMD vector element"},
-+ {AARCH64_OPND_CLASS_SIMD_ELEMENT, "Em16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rm}, "a SIMD vector element limited to V0-V15"},
- {AARCH64_OPND_CLASS_SIMD_REGLIST, "LVn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "a SIMD vector register list"},
- {AARCH64_OPND_CLASS_SIMD_REGLIST, "LVt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a SIMD vector register list"},
- {AARCH64_OPND_CLASS_SIMD_REGLIST, "LVt_AL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a SIMD vector register list"},
-@@ -82,9 +85,12 @@ const struct aarch64_operand aarch64_ope
- {AARCH64_OPND_CLASS_IMMEDIATE, "UIMM3_OP1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_op1}, "a 3-bit unsigned immediate"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "UIMM3_OP2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_op2}, "a 3-bit unsigned immediate"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "UIMM4", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CRm}, "a 4-bit unsigned immediate"},
-+ {AARCH64_OPND_CLASS_IMMEDIATE, "UIMM4_ADDG", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm4_3}, "a 4-bit unsigned Logical Address Tag modifier"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "UIMM7", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CRm, FLD_op2}, "a 7-bit unsigned immediate"},
-+ {AARCH64_OPND_CLASS_IMMEDIATE, "UIMM10", OPD_F_SHIFT_BY_4 | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_immr}, "a 10-bit unsigned multiple of 16"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "BIT_NUM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_b5, FLD_b40}, "the bit number to be tested"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "EXCEPTION", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm16}, "a 16-bit unsigned immediate"},
-+ {AARCH64_OPND_CLASS_IMMEDIATE, "UNDEFINED", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm16_2}, "a 16-bit unsigned immediate"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "CCMP_IMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm5}, "a 5-bit unsigned immediate"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "SIMM5", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm5}, "a 5-bit signed immediate"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "NZCV", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_nzcv}, "a flag bit specifier giving an alternative value for each flag"},
-@@ -108,8 +114,10 @@ const struct aarch64_operand aarch64_ope
- {AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM7", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm7,FLD_index2}, "an address with 7-bit signed immediate offset"},
- {AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM9", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm9,FLD_index}, "an address with 9-bit signed immediate offset"},
- {AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM9_2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm9,FLD_index}, "an address with 9-bit negative or unaligned immediate offset"},
-- {AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM10", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_S_imm10,FLD_imm9,FLD_index}, "an address with 10-bit scaled, signed immediate offset"},
-+ {AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM10", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_S_imm10,FLD_imm9,FLD_index}, "an address with an optional 10-bit scaled, signed immediate offset"},
-+ {AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM11", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm7,FLD_index2}, "an address with 11-bit signed immediate (multiple of 16) offset"},
- {AARCH64_OPND_CLASS_ADDRESS, "ADDR_UIMM12", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_imm12}, "an address with scaled, unsigned immediate offset"},
-+ {AARCH64_OPND_CLASS_ADDRESS, "ADDR_SIMM13", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm9,FLD_index}, "an address with 13-bit signed immediate (multiple of 16) offset"},
- {AARCH64_OPND_CLASS_ADDRESS, "SIMD_ADDR_SIMPLE", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an address with base register (no offset)"},
- {AARCH64_OPND_CLASS_ADDRESS, "ADDR_OFFSET", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_imm9,FLD_index}, "an address with an optional 8-bit signed immediate offset"},
- {AARCH64_OPND_CLASS_ADDRESS, "SIMD_ADDR_POST", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a post-indexed address with immediate or register increment"},
-@@ -119,11 +127,15 @@ const struct aarch64_operand aarch64_ope
- {AARCH64_OPND_CLASS_SYSTEM, "SYSREG_DC", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a data cache maintenance operation specifier"},
- {AARCH64_OPND_CLASS_SYSTEM, "SYSREG_IC", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "an instruction cache maintenance operation specifier"},
- {AARCH64_OPND_CLASS_SYSTEM, "SYSREG_TLBI", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a TBL invalidation operation specifier"},
-+ {AARCH64_OPND_CLASS_SYSTEM, "SYSREG_SR", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a Speculation Restriction option name (RCTX)"},
- {AARCH64_OPND_CLASS_SYSTEM, "BARRIER", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a barrier option name"},
-+ {AARCH64_OPND_CLASS_SYSTEM, "BARRIER_DSB_NXS", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "the DSB nXS option qualifier name SY, ISH, NSH, OSH or an optional 5-bit unsigned immediate"},
- {AARCH64_OPND_CLASS_SYSTEM, "BARRIER_ISB", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "the ISB option name SY or an optional 4-bit unsigned immediate"},
- {AARCH64_OPND_CLASS_SYSTEM, "PRFOP", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "a prefetch operation specifier"},
-- {AARCH64_OPND_CLASS_SYSTEM, "BARRIER_PSB", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "the PSB option name CSYNC"},
-+ {AARCH64_OPND_CLASS_SYSTEM, "BARRIER_PSB", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "the PSB/TSB option name CSYNC"},
-+ {AARCH64_OPND_CLASS_SYSTEM, "BTI", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {}, "BTI targets j/c/jc"},
- {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S4x16", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 4-bit signed offset, multiplied by 16"},
-+ {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S4x32", 5 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 4-bit signed offset, multiplied by 32"},
- {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S4xVL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 4-bit signed offset, multiplied by VL"},
- {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S4x2xVL", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 4-bit signed offset, multiplied by 2*VL"},
- {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_S4x3xVL", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 4-bit signed offset, multiplied by 3*VL"},
-@@ -134,6 +146,7 @@ const struct aarch64_operand aarch64_ope
- {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_U6x2", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 6-bit unsigned offset, multiplied by 2"},
- {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_U6x4", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 6-bit unsigned offset, multiplied by 4"},
- {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RI_U6x8", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an address with a 6-bit unsigned offset, multiplied by 8"},
-+ {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_R", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with an optional scalar register offset"},
- {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RR", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset"},
- {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RR_LSL1", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset"},
- {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RR_LSL2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset"},
-@@ -142,6 +155,7 @@ const struct aarch64_operand aarch64_ope
- {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RX_LSL1", (1 << OPD_F_OD_LSB) | OPD_F_NO_ZR | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset"},
- {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RX_LSL2", (2 << OPD_F_OD_LSB) | OPD_F_NO_ZR | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset"},
- {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RX_LSL3", (3 << OPD_F_OD_LSB) | OPD_F_NO_ZR | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_Rm}, "an address with a scalar register offset"},
-+ {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_ZX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn,FLD_Rm}, "vector of address with a scalar register offset"},
- {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_SVE_Zm_16}, "an address with a vector register offset"},
- {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_LSL1", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_SVE_Zm_16}, "an address with a vector register offset"},
- {AARCH64_OPND_CLASS_ADDRESS, "SVE_ADDR_RZ_LSL2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_SVE_Zm_16}, "an address with a vector register offset"},
-@@ -169,6 +183,7 @@ const struct aarch64_operand aarch64_ope
- {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_I1_ZERO_ONE", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i1}, "either 0.0 or 1.0"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_IMM_ROT1", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_rot1}, "a 1-bit rotation specifier for complex arithmetic operations"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_IMM_ROT2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_rot2}, "a 2-bit rotation specifier for complex arithmetic operations"},
-+ {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_IMM_ROT3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_rot3}, "a 1-bit rotation specifier for complex arithmetic operations"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_INV_LIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_N,FLD_SVE_immr,FLD_SVE_imms}, "an inverted 13-bit logical immediate"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_LIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_N,FLD_SVE_immr,FLD_SVE_imms}, "a 13-bit logical immediate"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_LIMM_MOV", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_N,FLD_SVE_immr,FLD_SVE_imms}, "a 13-bit logical move immediate"},
-@@ -187,8 +202,10 @@ const struct aarch64_operand aarch64_ope
- {AARCH64_OPND_CLASS_INT_REG, "SVE_Rn_SP", OPD_F_MAYBE_SP | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Rn}, "an integer register or SP"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHLIMM_PRED", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_tszh,FLD_SVE_imm5}, "a shift-left immediate operand"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHLIMM_UNPRED", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_tszh,FLD_imm5}, "a shift-left immediate operand"},
-- {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHRIMM_PRED", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_tszh,FLD_SVE_imm5}, "a shift-right immediate operand"},
-- {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHRIMM_UNPRED", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_tszh,FLD_imm5}, "a shift-right immediate operand"},
-+ {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHLIMM_UNPRED_22", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_sz, FLD_SVE_tszl_19, FLD_SVE_imm3}, "a shift-left immediate operand"},
-+ {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHRIMM_PRED", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_tszh,FLD_SVE_imm5}, "a shift-right immediate operand"},
-+ {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHRIMM_UNPRED", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_tszh,FLD_imm5}, "a shift-right immediate operand"},
-+ {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SHRIMM_UNPRED_22", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_sz, FLD_SVE_tszl_19, FLD_SVE_imm3}, "a shift-right immediate operand"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SIMM5", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm5}, "a 5-bit signed immediate"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SIMM5B", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm5b}, "a 5-bit signed immediate"},
- {AARCH64_OPND_CLASS_IMMEDIATE, "SVE_SIMM6", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imms}, "a 6-bit signed immediate"},
-@@ -208,12 +225,15 @@ const struct aarch64_operand aarch64_ope
- {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm_16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_16}, "an SVE vector register"},
- {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_16}, "an indexed SVE vector register"},
- {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_22_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i3h, FLD_SVE_Zm_16}, "an indexed SVE vector register"},
-+ {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm3_11_INDEX", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i3h2, FLD_SVE_i3l, FLD_SVE_imm3}, "an indexed SVE vector register"},
-+ {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm4_11_INDEX", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_i2h, FLD_SVE_i3l, FLD_SVE_imm4}, "an indexed SVE vector register"},
- {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zm4_INDEX", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_16}, "an indexed SVE vector register"},
- {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "an SVE vector register"},
- {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zn_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "an indexed SVE vector register"},
- {AARCH64_OPND_CLASS_SVE_REG, "SVE_ZnxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zn}, "a list of SVE vector registers"},
- {AARCH64_OPND_CLASS_SVE_REG, "SVE_Zt", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zt}, "an SVE vector register"},
- {AARCH64_OPND_CLASS_SVE_REG, "SVE_ZtxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zt}, "a list of SVE vector registers"},
-+ {AARCH64_OPND_CLASS_IMMEDIATE, "TME_UIMM16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm16}, "a 16-bit unsigned immediate for TME tcancel"},
- {AARCH64_OPND_CLASS_SIMD_ELEMENT, "SM3_IMM2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SM3_imm2}, "an indexed SM3 vector immediate"},
- {AARCH64_OPND_CLASS_NIL, "", 0, {0}, "DUMMY"},
- };
-@@ -224,86 +244,86 @@ const struct aarch64_operand aarch64_ope
- static const unsigned op_enum_table [] =
- {
- 0,
-- 863,
-- 864,
-- 865,
-- 868,
-- 869,
-- 870,
-- 871,
-- 872,
-- 866,
-- 867,
-- 873,
-- 874,
-+ 889,
-+ 890,
-+ 891,
-+ 894,
-+ 895,
- 896,
- 897,
- 898,
-- 901,
-- 902,
-- 903,
-- 904,
-- 905,
-+ 892,
-+ 893,
- 899,
- 900,
-- 906,
-- 907,
-- 955,
-- 956,
-- 957,
-- 958,
-+ 922,
-+ 923,
-+ 924,
-+ 927,
-+ 928,
-+ 929,
-+ 930,
-+ 931,
-+ 925,
-+ 926,
-+ 932,
-+ 933,
-+ 987,
-+ 988,
-+ 989,
-+ 990,
- 12,
-- 630,
-+ 636,
-+ 637,
-+ 1186,
-+ 1188,
-+ 1190,
-+ 998,
-+ 1189,
-+ 1187,
-+ 318,
-+ 624,
-+ 635,
-+ 634,
-+ 996,
- 631,
-- 1150,
-- 1152,
-- 1154,
-- 962,
-- 1153,
-- 1151,
-- 312,
-- 618,
-- 629,
- 628,
-- 960,
-- 625,
-- 622,
-- 614,
-- 613,
- 620,
-- 621,
-- 624,
-+ 619,
- 626,
- 627,
-- 970,
-- 658,
-- 661,
-+ 630,
-+ 632,
-+ 633,
-+ 1006,
- 664,
-- 659,
-- 662,
-- 807,
-- 172,
-- 173,
-- 174,
-- 175,
-- 510,
-- 747,
-- 383,
-- 385,
-- 407,
-- 409,
-- 1216,
-- 1221,
-- 1214,
-- 1213,
-- 1217,
-- 1224,
-- 1226,
-- 1227,
-- 1223,
-- 1229,
-- 1228,
-- 129,
-+ 667,
-+ 670,
-+ 665,
-+ 668,
-+ 825,
-+ 178,
-+ 179,
-+ 180,
-+ 181,
-+ 516,
-+ 759,
-+ 389,
-+ 391,
-+ 413,
-+ 415,
-+ 1270,
-+ 1275,
-+ 1268,
-+ 1267,
-+ 1271,
-+ 1278,
-+ 1280,
-+ 1281,
-+ 1277,
-+ 1283,
-+ 1282,
-+ 131,
- };
-
- /* Given the opcode enumerator OP, return the pointer to the corresponding
-diff -rup binutils-2.30/opcodes/aarch64-opc.c binutils-2.30.new/opcodes/aarch64-opc.c
---- binutils-2.30/opcodes/aarch64-opc.c 2018-01-13 13:31:16.000000000 +0000
-+++ binutils-2.30.new/opcodes/aarch64-opc.c 2021-03-23 16:19:53.181776209 +0000
-@@ -1,5 +1,5 @@
- /* aarch64-opc.c -- AArch64 opcode support.
-- Copyright (C) 2009-2018 Free Software Foundation, Inc.
-+ Copyright (C) 2009-2021 Free Software Foundation, Inc.
- Contributed by ARM Ltd.
-
- This file is part of the GNU opcodes library.
-@@ -22,7 +22,7 @@
- #include <assert.h>
- #include <stdlib.h>
- #include <stdio.h>
--#include <stdint.h>
-+#include "bfd_stdint.h"
- #include <stdarg.h>
- #include <inttypes.h>
-
-@@ -243,6 +243,7 @@ const aarch64_field fields[] =
- { 15, 6 }, /* imm6_2: in rmif instructions. */
- { 11, 4 }, /* imm4: in advsimd ext and advsimd ins instructions. */
- { 0, 4 }, /* imm4_2: in rmif instructions. */
-+ { 10, 4 }, /* imm4_3: in adddg/subg instructions. */
- { 16, 5 }, /* imm5: in conditional compare (immediate) instructions. */
- { 15, 7 }, /* imm7: in load/store pair pre/post index instructions. */
- { 13, 8 }, /* imm8: in floating-point scalar move immediate inst. */
-@@ -250,6 +251,7 @@ const aarch64_field fields[] =
- { 10, 12 }, /* imm12: in ld/st unsigned imm or add/sub shifted inst. */
- { 5, 14 }, /* imm14: in test bit and branch instructions. */
- { 5, 16 }, /* imm16: in exception instructions. */
-+ { 0, 16 }, /* imm16_2: in udf instruction. */
- { 0, 26 }, /* imm26: in unconditional branch instructions. */
- { 10, 6 }, /* imms: in bitfield and logical immediate instructions. */
- { 16, 6 }, /* immr: in bitfield and logical immediate instructions. */
-@@ -293,6 +295,9 @@ const aarch64_field fields[] =
- { 0, 5 }, /* SVE_Zt: SVE vector register, bits [4,0]. */
- { 5, 1 }, /* SVE_i1: single-bit immediate. */
- { 22, 1 }, /* SVE_i3h: high bit of 3-bit immediate. */
-+ { 11, 1 }, /* SVE_i3l: low bit of 3-bit immediate. */
-+ { 19, 2 }, /* SVE_i3h2: two high bits of 3bit immediate, bits [20,19]. */
-+ { 20, 1 }, /* SVE_i2h: high bit of 2bit immediate, bits. */
- { 16, 3 }, /* SVE_imm3: 3-bit immediate field. */
- { 16, 4 }, /* SVE_imm4: 4-bit immediate field. */
- { 5, 5 }, /* SVE_imm5: 5-bit immediate field. */
-@@ -308,7 +313,10 @@ const aarch64_field fields[] =
- { 0, 4 }, /* SVE_prfop: prefetch operation for SVE PRF[BHWD]. */
- { 16, 1 }, /* SVE_rot1: 1-bit rotation amount. */
- { 10, 2 }, /* SVE_rot2: 2-bit rotation amount. */
-+ { 10, 1 }, /* SVE_rot3: 1-bit rotation amount at bit 10. */
- { 22, 1 }, /* SVE_sz: 1-bit element size select. */
-+ { 17, 2 }, /* SVE_size: 2-bit element size, bits [18,17]. */
-+ { 30, 1 }, /* SVE_sz2: 1-bit element size select. */
- { 16, 4 }, /* SVE_tsz: triangular size select. */
- { 22, 2 }, /* SVE_tszh: triangular size select high, bits [23,22]. */
- { 8, 2 }, /* SVE_tszl_8: triangular size select low, bits [9,8]. */
-@@ -319,6 +327,8 @@ const aarch64_field fields[] =
- { 13, 2 }, /* rotate2: Indexed element FCMLA immediate rotate. */
- { 12, 1 }, /* rotate3: FCADD immediate rotate. */
- { 12, 2 }, /* SM3: Indexed element SM3 2 bits index immediate. */
-+ { 22, 1 }, /* sz: 1-bit element size select. */
-+ { 10, 2 }, /* CRm_dsb_nxs: 2-bit imm. encoded in CRm<3:2>. */
- };
-
- enum aarch64_operand_class
-@@ -457,6 +467,14 @@ const struct aarch64_name_value_pair aar
- { "sy", 0xf },
- };
-
-+const struct aarch64_name_value_pair aarch64_barrier_dsb_nxs_options[4] =
-+{ /* CRm<3:2> #imm */
-+ { "oshnxs", 16 }, /* 00 16 */
-+ { "nshnxs", 20 }, /* 01 20 */
-+ { "ishnxs", 24 }, /* 10 24 */
-+ { "synxs", 28 }, /* 11 28 */
-+};
-+
- /* Table describing the operands supported by the aliases of the HINT
- instruction.
-
-@@ -466,8 +484,13 @@ const struct aarch64_name_value_pair aar
-
- const struct aarch64_name_value_pair aarch64_hint_options[] =
- {
-- { "csync", 0x11 }, /* PSB CSYNC. */
-- { NULL, 0x0 },
-+ /* BTI. This is also the F_DEFAULT entry for AARCH64_OPND_BTI_TARGET. */
-+ { " ", HINT_ENCODE (HINT_OPD_F_NOPRINT, 0x20) },
-+ { "csync", HINT_OPD_CSYNC }, /* PSB CSYNC. */
-+ { "c", HINT_OPD_C }, /* BTI C. */
-+ { "j", HINT_OPD_J }, /* BTI J. */
-+ { "jc", HINT_OPD_JC }, /* BTI JC. */
-+ { NULL, HINT_OPD_NULL },
- };
-
- /* op -> op: load = 0 instruction = 1 store = 2
-@@ -533,7 +556,7 @@ value_fit_signed_field_p (int64_t value,
- assert (width < 32);
- if (width < sizeof (value) * 8)
- {
-- int64_t lim = (int64_t)1 << (width - 1);
-+ int64_t lim = (uint64_t) 1 << (width - 1);
- if (value >= -lim && value < lim)
- return 1;
- }
-@@ -547,7 +570,7 @@ value_fit_unsigned_field_p (int64_t valu
- assert (width < 32);
- if (width < sizeof (value) * 8)
- {
-- int64_t lim = (int64_t)1 << width;
-+ int64_t lim = (uint64_t) 1 << width;
- if (value >= 0 && value < lim)
- return 1;
- }
-@@ -698,7 +721,8 @@ struct operand_qualifier_data aarch64_op
- {4, 1, 0x2, "s", OQK_OPD_VARIANT},
- {8, 1, 0x3, "d", OQK_OPD_VARIANT},
- {16, 1, 0x4, "q", OQK_OPD_VARIANT},
-- {1, 4, 0x0, "4b", OQK_OPD_VARIANT},
-+ {4, 1, 0x0, "4b", OQK_OPD_VARIANT},
-+ {4, 1, 0x0, "2h", OQK_OPD_VARIANT},
-
- {1, 4, 0x0, "4b", OQK_OPD_VARIANT},
- {1, 8, 0x0, "8b", OQK_OPD_VARIANT},
-@@ -715,6 +739,9 @@ struct operand_qualifier_data aarch64_op
- {0, 0, 0, "z", OQK_OPD_VARIANT},
- {0, 0, 0, "m", OQK_OPD_VARIANT},
-
-+ /* Qualifier for scaled immediate for Tag granule (stg,st2g,etc). */
-+ {16, 0, 0, "tag", OQK_OPD_VARIANT},
-+
- /* Qualifiers constraining the value range.
- First 3 fields:
- Lower bound, higher bound, unused. */
-@@ -832,6 +859,25 @@ dump_match_qualifiers (const struct aarc
- }
- #endif /* DEBUG_AARCH64 */
-
-+/* This function checks if the given instruction INSN is a destructive
-+ instruction based on the usage of the registers. It does not recognize
-+ unary destructive instructions. */
-+bfd_boolean
-+aarch64_is_destructive_by_operands (const aarch64_opcode *opcode)
-+{
-+ int i = 0;
-+ const enum aarch64_opnd *opnds = opcode->operands;
-+
-+ if (opnds[0] == AARCH64_OPND_NIL)
-+ return FALSE;
-+
-+ while (opnds[++i] != AARCH64_OPND_NIL)
-+ if (opnds[i] == opnds[0])
-+ return TRUE;
-+
-+ return FALSE;
-+}
-+
- /* TODO improve this, we can have an extra field at the runtime to
- store the number of operands rather than calculating it every time. */
-
-@@ -1027,7 +1073,7 @@ match_operands_qualifier (aarch64_inst *
- amount will be returned in *SHIFT_AMOUNT. */
-
- bfd_boolean
--aarch64_wide_constant_p (int64_t value, int is32, unsigned int *shift_amount)
-+aarch64_wide_constant_p (uint64_t value, int is32, unsigned int *shift_amount)
- {
- int amount;
-
-@@ -1038,22 +1084,21 @@ aarch64_wide_constant_p (int64_t value,
- /* Allow all zeros or all ones in top 32-bits, so that
- 32-bit constant expressions like ~0x80000000 are
- permitted. */
-- uint64_t ext = value;
-- if (ext >> 32 != 0 && ext >> 32 != (uint64_t) 0xffffffff)
-+ if (value >> 32 != 0 && value >> 32 != 0xffffffff)
- /* Immediate out of range. */
- return FALSE;
-- value &= (int64_t) 0xffffffff;
-+ value &= 0xffffffff;
- }
-
- /* first, try movz then movn */
- amount = -1;
-- if ((value & ((int64_t) 0xffff << 0)) == value)
-+ if ((value & ((uint64_t) 0xffff << 0)) == value)
- amount = 0;
-- else if ((value & ((int64_t) 0xffff << 16)) == value)
-+ else if ((value & ((uint64_t) 0xffff << 16)) == value)
- amount = 16;
-- else if (!is32 && (value & ((int64_t) 0xffff << 32)) == value)
-+ else if (!is32 && (value & ((uint64_t) 0xffff << 32)) == value)
- amount = 32;
-- else if (!is32 && (value & ((int64_t) 0xffff << 48)) == value)
-+ else if (!is32 && (value & ((uint64_t) 0xffff << 48)) == value)
- amount = 48;
-
- if (amount == -1)
-@@ -1484,6 +1529,8 @@ operand_general_constraint_met_p (const
- {
- case AARCH64_OPND_SVE_Zm3_INDEX:
- case AARCH64_OPND_SVE_Zm3_22_INDEX:
-+ case AARCH64_OPND_SVE_Zm3_11_INDEX:
-+ case AARCH64_OPND_SVE_Zm4_11_INDEX:
- case AARCH64_OPND_SVE_Zm4_INDEX:
- size = get_operand_fields_width (get_operand_from_code (type));
- shift = get_operand_specific_data (&aarch64_operands[type]);
-@@ -1497,7 +1544,7 @@ operand_general_constraint_met_p (const
- : _("z0-z7 expected"));
- return 0;
- }
-- mask = (1 << (size - shift)) - 1;
-+ mask = (1u << (size - shift)) - 1;
- if (!value_in_range_p (opnd->reglane.index, 0, mask))
- {
- set_elem_idx_out_of_range_error (mismatch_detail, idx, 0, mask);
-@@ -1643,6 +1690,36 @@ operand_general_constraint_met_p (const
- }
- break;
-
-+ case AARCH64_OPND_ADDR_SIMM11:
-+ /* Signed 11 bits immediate offset (multiple of 16). */
-+ if (!value_in_range_p (opnd->addr.offset.imm, -1024, 1008))
-+ {
-+ set_offset_out_of_range_error (mismatch_detail, idx, -1024, 1008);
-+ return 0;
-+ }
-+
-+ if (!value_aligned_p (opnd->addr.offset.imm, 16))
-+ {
-+ set_unaligned_error (mismatch_detail, idx, 16);
-+ return 0;
-+ }
-+ break;
-+
-+ case AARCH64_OPND_ADDR_SIMM13:
-+ /* Signed 13 bits immediate offset (multiple of 16). */
-+ if (!value_in_range_p (opnd->addr.offset.imm, -4096, 4080))
-+ {
-+ set_offset_out_of_range_error (mismatch_detail, idx, -4096, 4080);
-+ return 0;
-+ }
-+
-+ if (!value_aligned_p (opnd->addr.offset.imm, 16))
-+ {
-+ set_unaligned_error (mismatch_detail, idx, 16);
-+ return 0;
-+ }
-+ break;
-+
- case AARCH64_OPND_SIMD_ADDR_POST:
- /* AdvSIMD load/store multiple structures, post-index. */
- assert (idx == 1);
-@@ -1831,10 +1908,23 @@ operand_general_constraint_met_p (const
- break;
-
- case AARCH64_OPND_SVE_ADDR_RI_S4x16:
-+ case AARCH64_OPND_SVE_ADDR_RI_S4x32:
- min_value = -8;
- max_value = 7;
- goto sve_imm_offset;
-
-+ case AARCH64_OPND_SVE_ADDR_ZX:
-+ /* Everything is already ensured by parse_operands or
-+ aarch64_ext_sve_addr_rr_lsl (because this is a very specific
-+ argument type). */
-+ assert (opnd->addr.offset.is_reg);
-+ assert (opnd->addr.preind);
-+ assert ((aarch64_operands[type].flags & OPD_F_NO_ZR) == 0);
-+ assert (opnd->shifter.kind == AARCH64_MOD_LSL);
-+ assert (opnd->shifter.operator_present == 0);
-+ break;
-+
-+ case AARCH64_OPND_SVE_ADDR_R:
- case AARCH64_OPND_SVE_ADDR_RR:
- case AARCH64_OPND_SVE_ADDR_RR_LSL1:
- case AARCH64_OPND_SVE_ADDR_RR_LSL2:
-@@ -2065,7 +2155,10 @@ operand_general_constraint_met_p (const
- case AARCH64_OPND_NZCV:
- case AARCH64_OPND_CCMP_IMM:
- case AARCH64_OPND_EXCEPTION:
-+ case AARCH64_OPND_UNDEFINED:
-+ case AARCH64_OPND_TME_UIMM16:
- case AARCH64_OPND_UIMM4:
-+ case AARCH64_OPND_UIMM4_ADDG:
- case AARCH64_OPND_UIMM7:
- case AARCH64_OPND_UIMM3_OP1:
- case AARCH64_OPND_UIMM3_OP2:
-@@ -2078,7 +2171,22 @@ operand_general_constraint_met_p (const
- if (!value_fit_unsigned_field_p (opnd->imm.value, size))
- {
- set_imm_out_of_range_error (mismatch_detail, idx, 0,
-- (1 << size) - 1);
-+ (1u << size) - 1);
-+ return 0;
-+ }
-+ break;
-+
-+ case AARCH64_OPND_UIMM10:
-+ /* Scaled unsigned 10 bits immediate offset. */
-+ if (!value_in_range_p (opnd->imm.value, 0, 1008))
-+ {
-+ set_imm_out_of_range_error (mismatch_detail, idx, 0, 1008);
-+ return 0;
-+ }
-+
-+ if (!value_aligned_p (opnd->imm.value, 16))
-+ {
-+ set_unaligned_error (mismatch_detail, idx, 16);
- return 0;
- }
- break;
-@@ -2154,6 +2262,7 @@ operand_general_constraint_met_p (const
-
- case AARCH64_OPND_IMM_ROT3:
- case AARCH64_OPND_SVE_IMM_ROT1:
-+ case AARCH64_OPND_SVE_IMM_ROT3:
- if (opnd->imm.value != 90 && opnd->imm.value != 270)
- {
- set_other_error (mismatch_detail, idx,
-@@ -2434,6 +2543,7 @@ operand_general_constraint_met_p (const
-
- case AARCH64_OPND_SVE_SHLIMM_PRED:
- case AARCH64_OPND_SVE_SHLIMM_UNPRED:
-+ case AARCH64_OPND_SVE_SHLIMM_UNPRED_22:
- size = aarch64_get_qualifier_esize (opnds[idx - 1].qualifier);
- if (!value_in_range_p (opnd->imm.value, 0, 8 * size - 1))
- {
-@@ -2445,10 +2555,12 @@ operand_general_constraint_met_p (const
-
- case AARCH64_OPND_SVE_SHRIMM_PRED:
- case AARCH64_OPND_SVE_SHRIMM_UNPRED:
-- size = aarch64_get_qualifier_esize (opnds[idx - 1].qualifier);
-+ case AARCH64_OPND_SVE_SHRIMM_UNPRED_22:
-+ num = (type == AARCH64_OPND_SVE_SHRIMM_UNPRED_22) ? 2 : 1;
-+ size = aarch64_get_qualifier_esize (opnds[idx - num].qualifier);
- if (!value_in_range_p (opnd->imm.value, 1, 8 * size))
- {
-- set_imm_out_of_range_error (mismatch_detail, idx, 1, 8 * size);
-+ set_imm_out_of_range_error (mismatch_detail, idx, 1, 8*size);
- return 0;
- }
- break;
-@@ -2465,9 +2577,11 @@ operand_general_constraint_met_p (const
- assert (idx == 0 && opnds[1].type == AARCH64_OPND_UIMM4);
- /* MSR UAO, #uimm4
- MSR PAN, #uimm4
-+ MSR SSBS,#uimm4
- The immediate must be #0 or #1. */
- if ((opnd->pstatefield == 0x03 /* UAO. */
- || opnd->pstatefield == 0x04 /* PAN. */
-+ || opnd->pstatefield == 0x19 /* SSBS. */
- || opnd->pstatefield == 0x1a) /* DIT. */
- && opnds[1].imm.value > 1)
- {
-@@ -2500,6 +2614,7 @@ operand_general_constraint_met_p (const
- else
- num = 16;
- num = num / aarch64_get_qualifier_esize (qualifier) - 1;
-+ assert (aarch64_get_qualifier_nelem (qualifier) == 1);
-
- /* Index out-of-range. */
- if (!value_in_range_p (opnd->reglane.index, 0, num))
-@@ -2515,7 +2630,7 @@ operand_general_constraint_met_p (const
- 01 0:Rm
- 10 M:Rm
- 11 RESERVED */
-- if (type == AARCH64_OPND_Em && qualifier == AARCH64_OPND_QLF_S_H
-+ if (type == AARCH64_OPND_Em16 && qualifier == AARCH64_OPND_QLF_S_H
- && !value_in_range_p (opnd->reglane.regno, 0, 15))
- {
- set_regno_out_of_range_error (mismatch_detail, idx, 0, 15);
-@@ -2957,7 +3072,12 @@ print_immediate_offset_address (char *bu
- if (opnd->addr.writeback)
- {
- if (opnd->addr.preind)
-- snprintf (buf, size, "[%s, #%d]!", base, opnd->addr.offset.imm);
-+ {
-+ if (opnd->type == AARCH64_OPND_ADDR_SIMM10 && !opnd->addr.offset.imm)
-+ snprintf (buf, size, "[%s]!", base);
-+ else
-+ snprintf (buf, size, "[%s, #%d]!", base, opnd->addr.offset.imm);
-+ }
- else
- snprintf (buf, size, "[%s], #%d", base, opnd->addr.offset.imm);
- }
-@@ -3032,7 +3152,8 @@ void
- aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
- const aarch64_opcode *opcode,
- const aarch64_opnd_info *opnds, int idx, int *pcrel_p,
-- bfd_vma *address)
-+ bfd_vma *address, char** notes,
-+ aarch64_feature_set features)
- {
- unsigned int i, num_conds;
- const char *name = NULL;
-@@ -3053,6 +3174,7 @@ aarch64_print_operand (char *buf, size_t
- case AARCH64_OPND_Rt2:
- case AARCH64_OPND_Rs:
- case AARCH64_OPND_Ra:
-+ case AARCH64_OPND_Rt_LS64:
- case AARCH64_OPND_Rt_SYS:
- case AARCH64_OPND_PAIRREG:
- case AARCH64_OPND_SVE_Rm:
-@@ -3077,6 +3199,7 @@ aarch64_print_operand (char *buf, size_t
-
- case AARCH64_OPND_Rd_SP:
- case AARCH64_OPND_Rn_SP:
-+ case AARCH64_OPND_Rt_SP:
- case AARCH64_OPND_SVE_Rn_SP:
- case AARCH64_OPND_Rm_SP:
- assert (opnd->qualifier == AARCH64_OPND_QLF_W
-@@ -3160,6 +3283,7 @@ aarch64_print_operand (char *buf, size_t
- case AARCH64_OPND_Ed:
- case AARCH64_OPND_En:
- case AARCH64_OPND_Em:
-+ case AARCH64_OPND_Em16:
- case AARCH64_OPND_SM3_IMM2:
- snprintf (buf, size, "v%d.%s[%" PRIi64 "]", opnd->reglane.regno,
- aarch64_get_qualifier_name (opnd->qualifier),
-@@ -3218,6 +3342,8 @@ aarch64_print_operand (char *buf, size_t
-
- case AARCH64_OPND_SVE_Zm3_INDEX:
- case AARCH64_OPND_SVE_Zm3_22_INDEX:
-+ case AARCH64_OPND_SVE_Zm3_11_INDEX:
-+ case AARCH64_OPND_SVE_Zm4_11_INDEX:
- case AARCH64_OPND_SVE_Zm4_INDEX:
- case AARCH64_OPND_SVE_Zn_INDEX:
- snprintf (buf, size, "z%d.%s[%" PRIi64 "]", opnd->reglane.regno,
-@@ -3244,12 +3370,16 @@ aarch64_print_operand (char *buf, size_t
- case AARCH64_OPND_IMM0:
- case AARCH64_OPND_IMMR:
- case AARCH64_OPND_IMMS:
-+ case AARCH64_OPND_UNDEFINED:
- case AARCH64_OPND_FBITS:
-+ case AARCH64_OPND_TME_UIMM16:
- case AARCH64_OPND_SIMM5:
- case AARCH64_OPND_SVE_SHLIMM_PRED:
- case AARCH64_OPND_SVE_SHLIMM_UNPRED:
-+ case AARCH64_OPND_SVE_SHLIMM_UNPRED_22:
- case AARCH64_OPND_SVE_SHRIMM_PRED:
- case AARCH64_OPND_SVE_SHRIMM_UNPRED:
-+ case AARCH64_OPND_SVE_SHRIMM_UNPRED_22:
- case AARCH64_OPND_SVE_SIMM5:
- case AARCH64_OPND_SVE_SIMM5B:
- case AARCH64_OPND_SVE_SIMM6:
-@@ -3263,6 +3393,7 @@ aarch64_print_operand (char *buf, size_t
- case AARCH64_OPND_IMM_ROT3:
- case AARCH64_OPND_SVE_IMM_ROT1:
- case AARCH64_OPND_SVE_IMM_ROT2:
-+ case AARCH64_OPND_SVE_IMM_ROT3:
- snprintf (buf, size, "#%" PRIi64, opnd->imm.value);
- break;
-
-@@ -3405,7 +3536,9 @@ aarch64_print_operand (char *buf, size_t
- case AARCH64_OPND_NZCV:
- case AARCH64_OPND_EXCEPTION:
- case AARCH64_OPND_UIMM4:
-+ case AARCH64_OPND_UIMM4_ADDG:
- case AARCH64_OPND_UIMM7:
-+ case AARCH64_OPND_UIMM10:
- if (optional_operand_p (opcode, idx) == TRUE
- && (opnd->imm.value ==
- (int64_t) get_optional_operand_default_value (opcode)))
-@@ -3476,6 +3609,7 @@ aarch64_print_operand (char *buf, size_t
- break;
-
- case AARCH64_OPND_ADDR_REGOFF:
-+ case AARCH64_OPND_SVE_ADDR_R:
- case AARCH64_OPND_SVE_ADDR_RR:
- case AARCH64_OPND_SVE_ADDR_RR_LSL1:
- case AARCH64_OPND_SVE_ADDR_RR_LSL2:
-@@ -3489,6 +3623,13 @@ aarch64_print_operand (char *buf, size_t
- get_offset_int_reg_name (opnd));
- break;
-
-+ case AARCH64_OPND_SVE_ADDR_ZX:
-+ print_register_offset_address
-+ (buf, size, opnd,
-+ get_addr_sve_reg_name (opnd->addr.base_regno, opnd->qualifier),
-+ get_64bit_int_reg_name (opnd->addr.offset.regno, 0));
-+ break;
-+
- case AARCH64_OPND_SVE_ADDR_RZ:
- case AARCH64_OPND_SVE_ADDR_RZ_LSL1:
- case AARCH64_OPND_SVE_ADDR_RZ_LSL2:
-@@ -3510,8 +3651,11 @@ aarch64_print_operand (char *buf, size_t
- case AARCH64_OPND_ADDR_SIMM9:
- case AARCH64_OPND_ADDR_SIMM9_2:
- case AARCH64_OPND_ADDR_SIMM10:
-+ case AARCH64_OPND_ADDR_SIMM11:
-+ case AARCH64_OPND_ADDR_SIMM13:
- case AARCH64_OPND_ADDR_OFFSET:
- case AARCH64_OPND_SVE_ADDR_RI_S4x16:
-+ case AARCH64_OPND_SVE_ADDR_RI_S4x32:
- case AARCH64_OPND_SVE_ADDR_RI_S4xVL:
- case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL:
- case AARCH64_OPND_SVE_ADDR_RI_S4x3xVL:
-@@ -3554,15 +3698,45 @@ aarch64_print_operand (char *buf, size_t
-
- case AARCH64_OPND_SYSREG:
- for (i = 0; aarch64_sys_regs[i].name; ++i)
-- if (aarch64_sys_regs[i].value == opnd->sysreg
-- && ! aarch64_sys_reg_deprecated_p (&aarch64_sys_regs[i]))
-- break;
-- if (aarch64_sys_regs[i].name)
-- snprintf (buf, size, "%s", aarch64_sys_regs[i].name);
-+ {
-+ const aarch64_sys_reg *sr = aarch64_sys_regs + i;
-+
-+ bfd_boolean exact_match
-+ = (!(sr->flags & (F_REG_READ | F_REG_WRITE))
-+ || (sr->flags & opnd->sysreg.flags) == opnd->sysreg.flags)
-+ && AARCH64_CPU_HAS_FEATURE (features, sr->features);
-+
-+ /* Try and find an exact match, But if that fails, return the first
-+ partial match that was found. */
-+ if (aarch64_sys_regs[i].value == opnd->sysreg.value
-+ && ! aarch64_sys_reg_deprecated_p (aarch64_sys_regs[i].flags)
-+ && (name == NULL || exact_match))
-+ {
-+ name = aarch64_sys_regs[i].name;
-+ if (exact_match)
-+ {
-+ if (notes)
-+ *notes = NULL;
-+ break;
-+ }
-+
-+ /* If we didn't match exactly, that means the presense of a flag
-+ indicates what we didn't want for this instruction. e.g. If
-+ F_REG_READ is there, that means we were looking for a write
-+ register. See aarch64_ext_sysreg. */
-+ if (aarch64_sys_regs[i].flags & F_REG_WRITE)
-+ *notes = _("reading from a write-only register");
-+ else if (aarch64_sys_regs[i].flags & F_REG_READ)
-+ *notes = _("writing to a read-only register");
-+ }
-+ }
-+
-+ if (name)
-+ snprintf (buf, size, "%s", name);
- else
- {
- /* Implementation defined system register. */
-- unsigned int value = opnd->sysreg;
-+ unsigned int value = opnd->sysreg.value;
- snprintf (buf, size, "s%u_%u_c%u_c%u_%u", (value >> 14) & 0x3,
- (value >> 11) & 0x7, (value >> 7) & 0xf, (value >> 3) & 0xf,
- value & 0x7);
-@@ -3581,10 +3755,12 @@ aarch64_print_operand (char *buf, size_t
- case AARCH64_OPND_SYSREG_DC:
- case AARCH64_OPND_SYSREG_IC:
- case AARCH64_OPND_SYSREG_TLBI:
-+ case AARCH64_OPND_SYSREG_SR:
- snprintf (buf, size, "%s", opnd->sysins_op->name);
- break;
-
- case AARCH64_OPND_BARRIER:
-+ case AARCH64_OPND_BARRIER_DSB_NXS:
- snprintf (buf, size, "%s", opnd->barrier->name);
- break;
-
-@@ -3604,7 +3780,12 @@ aarch64_print_operand (char *buf, size_t
- break;
-
- case AARCH64_OPND_BARRIER_PSB:
-- snprintf (buf, size, "%s", opnd->hint_option->name);
-+ snprintf (buf, size, "csync");
-+ break;
-+
-+ case AARCH64_OPND_BTI_TARGET:
-+ if ((HINT_FLAG (opnd->hint_option->value) & HINT_OPD_F_NOPRINT) == 0)
-+ snprintf (buf, size, "%s", opnd->hint_option->name);
- break;
-
- default:
-@@ -3636,625 +3817,884 @@ aarch64_print_operand (char *buf, size_t
- #define C14 14
- #define C15 15
-
--#ifdef F_DEPRECATED
--#undef F_DEPRECATED
--#endif
--#define F_DEPRECATED 0x1 /* Deprecated system register. */
-+#define SYSREG(name, encoding, flags, features) \
-+ { name, encoding, flags, features }
-
--#ifdef F_ARCHEXT
--#undef F_ARCHEXT
--#endif
--#define F_ARCHEXT 0x2 /* Architecture dependent system register. */
-+#define SR_CORE(n,e,f) SYSREG (n,e,f,0)
-
--#ifdef F_HASXT
--#undef F_HASXT
--#endif
--#define F_HASXT 0x4 /* System instruction register <Xt>
-- operand. */
-+#define SR_FEAT(n,e,f,feat) \
-+ SYSREG ((n), (e), (f) | F_ARCHEXT, AARCH64_FEATURE_##feat)
-+
-+#define SR_FEAT2(n,e,f,fe1,fe2) \
-+ SYSREG ((n), (e), (f) | F_ARCHEXT, \
-+ AARCH64_FEATURE_##fe1 | AARCH64_FEATURE_##fe2)
-+
-+#define SR_RNG(n,e,f) SR_FEAT2(n,e,f,RNG,V8_5)
-+#define SR_V8_1_A(n,e,f) SR_FEAT2(n,e,f,V8_A,V8_1)
-+#define SR_V8_4_A(n,e,f) SR_FEAT2(n,e,f,V8_A,V8_4)
-+
-+#define SR_V8_A(n,e,f) SR_FEAT (n,e,f,V8_A)
-+#define SR_V8_R(n,e,f) SR_FEAT (n,e,f,V8_R)
-+#define SR_V8_1(n,e,f) SR_FEAT (n,e,f,V8_1)
-+#define SR_V8_2(n,e,f) SR_FEAT (n,e,f,V8_2)
-+#define SR_V8_3(n,e,f) SR_FEAT (n,e,f,V8_3)
-+#define SR_V8_4(n,e,f) SR_FEAT (n,e,f,V8_4)
-+#define SR_V8_4(n,e,f) SR_FEAT (n,e,f,V8_4)
-+#define SR_PAN(n,e,f) SR_FEAT (n,e,f,PAN)
-+#define SR_RAS(n,e,f) SR_FEAT (n,e,f,RAS)
-+#define SR_SSBS(n,e,f) SR_FEAT (n,e,f,SSBS)
-+#define SR_SVE(n,e,f) SR_FEAT (n,e,f,SVE)
-+#define SR_ID_PFR2(n,e,f) SR_FEAT (n,e,f,ID_PFR2)
-+#define SR_PROFILE(n,e,f) SR_FEAT (n,e,f,PROFILE)
-+#define SR_MEMTAG(n,e,f) SR_FEAT (n,e,f,MEMTAG)
-+#define SR_SCXTNUM(n,e,f) SR_FEAT (n,e,f,SCXTNUM)
-+
-+#define SR_EXPAND_ELx(f,x) \
-+ f (x, 1), \
-+ f (x, 2), \
-+ f (x, 3), \
-+ f (x, 4), \
-+ f (x, 5), \
-+ f (x, 6), \
-+ f (x, 7), \
-+ f (x, 8), \
-+ f (x, 9), \
-+ f (x, 10), \
-+ f (x, 11), \
-+ f (x, 12), \
-+ f (x, 13), \
-+ f (x, 14), \
-+ f (x, 15),
-+
-+#define SR_EXPAND_EL12(f) \
-+ SR_EXPAND_ELx (f,1) \
-+ SR_EXPAND_ELx (f,2)
-
-+/* TODO there is one more issues need to be resolved
-+ 1. handle cpu-implementation-defined system registers.
-
--/* TODO there are two more issues need to be resolved
-- 1. handle read-only and write-only system registers
-- 2. handle cpu-implementation-defined system registers. */
-+ Note that the F_REG_{READ,WRITE} flags mean read-only and write-only
-+ respectively. If neither of these are set then the register is read-write. */
- const aarch64_sys_reg aarch64_sys_regs [] =
- {
-- { "spsr_el1", CPEN_(0,C0,0), 0 }, /* = spsr_svc */
-- { "spsr_el12", CPEN_ (5, C0, 0), F_ARCHEXT },
-- { "elr_el1", CPEN_(0,C0,1), 0 },
-- { "elr_el12", CPEN_ (5, C0, 1), F_ARCHEXT },
-- { "sp_el0", CPEN_(0,C1,0), 0 },
-- { "spsel", CPEN_(0,C2,0), 0 },
-- { "daif", CPEN_(3,C2,1), 0 },
-- { "currentel", CPEN_(0,C2,2), 0 }, /* RO */
-- { "pan", CPEN_(0,C2,3), F_ARCHEXT },
-- { "uao", CPEN_ (0, C2, 4), F_ARCHEXT },
-- { "nzcv", CPEN_(3,C2,0), 0 },
-- { "fpcr", CPEN_(3,C4,0), 0 },
-- { "fpsr", CPEN_(3,C4,1), 0 },
-- { "dspsr_el0", CPEN_(3,C5,0), 0 },
-- { "dlr_el0", CPEN_(3,C5,1), 0 },
-- { "spsr_el2", CPEN_(4,C0,0), 0 }, /* = spsr_hyp */
-- { "elr_el2", CPEN_(4,C0,1), 0 },
-- { "sp_el1", CPEN_(4,C1,0), 0 },
-- { "spsr_irq", CPEN_(4,C3,0), 0 },
-- { "spsr_abt", CPEN_(4,C3,1), 0 },
-- { "spsr_und", CPEN_(4,C3,2), 0 },
-- { "spsr_fiq", CPEN_(4,C3,3), 0 },
-- { "spsr_el3", CPEN_(6,C0,0), 0 },
-- { "elr_el3", CPEN_(6,C0,1), 0 },
-- { "sp_el2", CPEN_(6,C1,0), 0 },
-- { "spsr_svc", CPEN_(0,C0,0), F_DEPRECATED }, /* = spsr_el1 */
-- { "spsr_hyp", CPEN_(4,C0,0), F_DEPRECATED }, /* = spsr_el2 */
-- { "midr_el1", CPENC(3,0,C0,C0,0), 0 }, /* RO */
-- { "ctr_el0", CPENC(3,3,C0,C0,1), 0 }, /* RO */
-- { "mpidr_el1", CPENC(3,0,C0,C0,5), 0 }, /* RO */
-- { "revidr_el1", CPENC(3,0,C0,C0,6), 0 }, /* RO */
-- { "aidr_el1", CPENC(3,1,C0,C0,7), 0 }, /* RO */
-- { "dczid_el0", CPENC(3,3,C0,C0,7), 0 }, /* RO */
-- { "id_dfr0_el1", CPENC(3,0,C0,C1,2), 0 }, /* RO */
-- { "id_pfr0_el1", CPENC(3,0,C0,C1,0), 0 }, /* RO */
-- { "id_pfr1_el1", CPENC(3,0,C0,C1,1), 0 }, /* RO */
-- { "id_afr0_el1", CPENC(3,0,C0,C1,3), 0 }, /* RO */
-- { "id_mmfr0_el1", CPENC(3,0,C0,C1,4), 0 }, /* RO */
-- { "id_mmfr1_el1", CPENC(3,0,C0,C1,5), 0 }, /* RO */
-- { "id_mmfr2_el1", CPENC(3,0,C0,C1,6), 0 }, /* RO */
-- { "id_mmfr3_el1", CPENC(3,0,C0,C1,7), 0 }, /* RO */
-- { "id_mmfr4_el1", CPENC(3,0,C0,C2,6), 0 }, /* RO */
-- { "id_isar0_el1", CPENC(3,0,C0,C2,0), 0 }, /* RO */
-- { "id_isar1_el1", CPENC(3,0,C0,C2,1), 0 }, /* RO */
-- { "id_isar2_el1", CPENC(3,0,C0,C2,2), 0 }, /* RO */
-- { "id_isar3_el1", CPENC(3,0,C0,C2,3), 0 }, /* RO */
-- { "id_isar4_el1", CPENC(3,0,C0,C2,4), 0 }, /* RO */
-- { "id_isar5_el1", CPENC(3,0,C0,C2,5), 0 }, /* RO */
-- { "mvfr0_el1", CPENC(3,0,C0,C3,0), 0 }, /* RO */
-- { "mvfr1_el1", CPENC(3,0,C0,C3,1), 0 }, /* RO */
-- { "mvfr2_el1", CPENC(3,0,C0,C3,2), 0 }, /* RO */
-- { "ccsidr_el1", CPENC(3,1,C0,C0,0), 0 }, /* RO */
-- { "id_aa64pfr0_el1", CPENC(3,0,C0,C4,0), 0 }, /* RO */
-- { "id_aa64pfr1_el1", CPENC(3,0,C0,C4,1), 0 }, /* RO */
-- { "id_aa64dfr0_el1", CPENC(3,0,C0,C5,0), 0 }, /* RO */
-- { "id_aa64dfr1_el1", CPENC(3,0,C0,C5,1), 0 }, /* RO */
-- { "id_aa64isar0_el1", CPENC(3,0,C0,C6,0), 0 }, /* RO */
-- { "id_aa64isar1_el1", CPENC(3,0,C0,C6,1), 0 }, /* RO */
-- { "id_aa64mmfr0_el1", CPENC(3,0,C0,C7,0), 0 }, /* RO */
-- { "id_aa64mmfr1_el1", CPENC(3,0,C0,C7,1), 0 }, /* RO */
-- { "id_aa64mmfr2_el1", CPENC (3, 0, C0, C7, 2), F_ARCHEXT }, /* RO */
-- { "id_aa64afr0_el1", CPENC(3,0,C0,C5,4), 0 }, /* RO */
-- { "id_aa64afr1_el1", CPENC(3,0,C0,C5,5), 0 }, /* RO */
-- { "id_aa64zfr0_el1", CPENC (3, 0, C0, C4, 4), F_ARCHEXT }, /* RO */
-- { "clidr_el1", CPENC(3,1,C0,C0,1), 0 }, /* RO */
-- { "csselr_el1", CPENC(3,2,C0,C0,0), 0 }, /* RO */
-- { "vpidr_el2", CPENC(3,4,C0,C0,0), 0 },
-- { "vmpidr_el2", CPENC(3,4,C0,C0,5), 0 },
-- { "sctlr_el1", CPENC(3,0,C1,C0,0), 0 },
-- { "sctlr_el2", CPENC(3,4,C1,C0,0), 0 },
-- { "sctlr_el3", CPENC(3,6,C1,C0,0), 0 },
-- { "sctlr_el12", CPENC (3, 5, C1, C0, 0), F_ARCHEXT },
-- { "actlr_el1", CPENC(3,0,C1,C0,1), 0 },
-- { "actlr_el2", CPENC(3,4,C1,C0,1), 0 },
-- { "actlr_el3", CPENC(3,6,C1,C0,1), 0 },
-- { "cpacr_el1", CPENC(3,0,C1,C0,2), 0 },
-- { "cpacr_el12", CPENC (3, 5, C1, C0, 2), F_ARCHEXT },
-- { "cptr_el2", CPENC(3,4,C1,C1,2), 0 },
-- { "cptr_el3", CPENC(3,6,C1,C1,2), 0 },
-- { "scr_el3", CPENC(3,6,C1,C1,0), 0 },
-- { "hcr_el2", CPENC(3,4,C1,C1,0), 0 },
-- { "mdcr_el2", CPENC(3,4,C1,C1,1), 0 },
-- { "mdcr_el3", CPENC(3,6,C1,C3,1), 0 },
-- { "hstr_el2", CPENC(3,4,C1,C1,3), 0 },
-- { "hacr_el2", CPENC(3,4,C1,C1,7), 0 },
-- { "zcr_el1", CPENC (3, 0, C1, C2, 0), F_ARCHEXT },
-- { "zcr_el12", CPENC (3, 5, C1, C2, 0), F_ARCHEXT },
-- { "zcr_el2", CPENC (3, 4, C1, C2, 0), F_ARCHEXT },
-- { "zcr_el3", CPENC (3, 6, C1, C2, 0), F_ARCHEXT },
-- { "zidr_el1", CPENC (3, 0, C0, C0, 7), F_ARCHEXT },
-- { "ttbr0_el1", CPENC(3,0,C2,C0,0), 0 },
-- { "ttbr1_el1", CPENC(3,0,C2,C0,1), 0 },
-- { "ttbr0_el2", CPENC(3,4,C2,C0,0), 0 },
-- { "ttbr1_el2", CPENC (3, 4, C2, C0, 1), F_ARCHEXT },
-- { "ttbr0_el3", CPENC(3,6,C2,C0,0), 0 },
-- { "ttbr0_el12", CPENC (3, 5, C2, C0, 0), F_ARCHEXT },
-- { "ttbr1_el12", CPENC (3, 5, C2, C0, 1), F_ARCHEXT },
-- { "vttbr_el2", CPENC(3,4,C2,C1,0), 0 },
-- { "tcr_el1", CPENC(3,0,C2,C0,2), 0 },
-- { "tcr_el2", CPENC(3,4,C2,C0,2), 0 },
-- { "tcr_el3", CPENC(3,6,C2,C0,2), 0 },
-- { "tcr_el12", CPENC (3, 5, C2, C0, 2), F_ARCHEXT },
-- { "vtcr_el2", CPENC(3,4,C2,C1,2), 0 },
-- { "apiakeylo_el1", CPENC (3, 0, C2, C1, 0), F_ARCHEXT },
-- { "apiakeyhi_el1", CPENC (3, 0, C2, C1, 1), F_ARCHEXT },
-- { "apibkeylo_el1", CPENC (3, 0, C2, C1, 2), F_ARCHEXT },
-- { "apibkeyhi_el1", CPENC (3, 0, C2, C1, 3), F_ARCHEXT },
-- { "apdakeylo_el1", CPENC (3, 0, C2, C2, 0), F_ARCHEXT },
-- { "apdakeyhi_el1", CPENC (3, 0, C2, C2, 1), F_ARCHEXT },
-- { "apdbkeylo_el1", CPENC (3, 0, C2, C2, 2), F_ARCHEXT },
-- { "apdbkeyhi_el1", CPENC (3, 0, C2, C2, 3), F_ARCHEXT },
-- { "apgakeylo_el1", CPENC (3, 0, C2, C3, 0), F_ARCHEXT },
-- { "apgakeyhi_el1", CPENC (3, 0, C2, C3, 1), F_ARCHEXT },
-- { "afsr0_el1", CPENC(3,0,C5,C1,0), 0 },
-- { "afsr1_el1", CPENC(3,0,C5,C1,1), 0 },
-- { "afsr0_el2", CPENC(3,4,C5,C1,0), 0 },
-- { "afsr1_el2", CPENC(3,4,C5,C1,1), 0 },
-- { "afsr0_el3", CPENC(3,6,C5,C1,0), 0 },
-- { "afsr0_el12", CPENC (3, 5, C5, C1, 0), F_ARCHEXT },
-- { "afsr1_el3", CPENC(3,6,C5,C1,1), 0 },
-- { "afsr1_el12", CPENC (3, 5, C5, C1, 1), F_ARCHEXT },
-- { "esr_el1", CPENC(3,0,C5,C2,0), 0 },
-- { "esr_el2", CPENC(3,4,C5,C2,0), 0 },
-- { "esr_el3", CPENC(3,6,C5,C2,0), 0 },
-- { "esr_el12", CPENC (3, 5, C5, C2, 0), F_ARCHEXT },
-- { "vsesr_el2", CPENC (3, 4, C5, C2, 3), F_ARCHEXT }, /* RO */
-- { "fpexc32_el2", CPENC(3,4,C5,C3,0), 0 },
-- { "erridr_el1", CPENC (3, 0, C5, C3, 0), F_ARCHEXT }, /* RO */
-- { "errselr_el1", CPENC (3, 0, C5, C3, 1), F_ARCHEXT },
-- { "erxfr_el1", CPENC (3, 0, C5, C4, 0), F_ARCHEXT }, /* RO */
-- { "erxctlr_el1", CPENC (3, 0, C5, C4, 1), F_ARCHEXT },
-- { "erxstatus_el1", CPENC (3, 0, C5, C4, 2), F_ARCHEXT },
-- { "erxaddr_el1", CPENC (3, 0, C5, C4, 3), F_ARCHEXT },
-- { "erxmisc0_el1", CPENC (3, 0, C5, C5, 0), F_ARCHEXT },
-- { "erxmisc1_el1", CPENC (3, 0, C5, C5, 1), F_ARCHEXT },
-- { "far_el1", CPENC(3,0,C6,C0,0), 0 },
-- { "far_el2", CPENC(3,4,C6,C0,0), 0 },
-- { "far_el3", CPENC(3,6,C6,C0,0), 0 },
-- { "far_el12", CPENC (3, 5, C6, C0, 0), F_ARCHEXT },
-- { "hpfar_el2", CPENC(3,4,C6,C0,4), 0 },
-- { "par_el1", CPENC(3,0,C7,C4,0), 0 },
-- { "mair_el1", CPENC(3,0,C10,C2,0), 0 },
-- { "mair_el2", CPENC(3,4,C10,C2,0), 0 },
-- { "mair_el3", CPENC(3,6,C10,C2,0), 0 },
-- { "mair_el12", CPENC (3, 5, C10, C2, 0), F_ARCHEXT },
-- { "amair_el1", CPENC(3,0,C10,C3,0), 0 },
-- { "amair_el2", CPENC(3,4,C10,C3,0), 0 },
-- { "amair_el3", CPENC(3,6,C10,C3,0), 0 },
-- { "amair_el12", CPENC (3, 5, C10, C3, 0), F_ARCHEXT },
-- { "vbar_el1", CPENC(3,0,C12,C0,0), 0 },
-- { "vbar_el2", CPENC(3,4,C12,C0,0), 0 },
-- { "vbar_el3", CPENC(3,6,C12,C0,0), 0 },
-- { "vbar_el12", CPENC (3, 5, C12, C0, 0), F_ARCHEXT },
-- { "rvbar_el1", CPENC(3,0,C12,C0,1), 0 }, /* RO */
-- { "rvbar_el2", CPENC(3,4,C12,C0,1), 0 }, /* RO */
-- { "rvbar_el3", CPENC(3,6,C12,C0,1), 0 }, /* RO */
-- { "rmr_el1", CPENC(3,0,C12,C0,2), 0 },
-- { "rmr_el2", CPENC(3,4,C12,C0,2), 0 },
-- { "rmr_el3", CPENC(3,6,C12,C0,2), 0 },
-- { "isr_el1", CPENC(3,0,C12,C1,0), 0 }, /* RO */
-- { "disr_el1", CPENC (3, 0, C12, C1, 1), F_ARCHEXT },
-- { "vdisr_el2", CPENC (3, 4, C12, C1, 1), F_ARCHEXT },
-- { "contextidr_el1", CPENC(3,0,C13,C0,1), 0 },
-- { "contextidr_el2", CPENC (3, 4, C13, C0, 1), F_ARCHEXT },
-- { "contextidr_el12", CPENC (3, 5, C13, C0, 1), F_ARCHEXT },
-- { "tpidr_el0", CPENC(3,3,C13,C0,2), 0 },
-- { "tpidrro_el0", CPENC(3,3,C13,C0,3), 0 }, /* RO */
-- { "tpidr_el1", CPENC(3,0,C13,C0,4), 0 },
-- { "tpidr_el2", CPENC(3,4,C13,C0,2), 0 },
-- { "tpidr_el3", CPENC(3,6,C13,C0,2), 0 },
-- { "teecr32_el1", CPENC(2,2,C0, C0,0), 0 }, /* See section 3.9.7.1 */
-- { "cntfrq_el0", CPENC(3,3,C14,C0,0), 0 }, /* RO */
-- { "cntpct_el0", CPENC(3,3,C14,C0,1), 0 }, /* RO */
-- { "cntvct_el0", CPENC(3,3,C14,C0,2), 0 }, /* RO */
-- { "cntvoff_el2", CPENC(3,4,C14,C0,3), 0 },
-- { "cntkctl_el1", CPENC(3,0,C14,C1,0), 0 },
-- { "cntkctl_el12", CPENC (3, 5, C14, C1, 0), F_ARCHEXT },
-- { "cnthctl_el2", CPENC(3,4,C14,C1,0), 0 },
-- { "cntp_tval_el0", CPENC(3,3,C14,C2,0), 0 },
-- { "cntp_tval_el02", CPENC (3, 5, C14, C2, 0), F_ARCHEXT },
-- { "cntp_ctl_el0", CPENC(3,3,C14,C2,1), 0 },
-- { "cntp_ctl_el02", CPENC (3, 5, C14, C2, 1), F_ARCHEXT },
-- { "cntp_cval_el0", CPENC(3,3,C14,C2,2), 0 },
-- { "cntp_cval_el02", CPENC (3, 5, C14, C2, 2), F_ARCHEXT },
-- { "cntv_tval_el0", CPENC(3,3,C14,C3,0), 0 },
-- { "cntv_tval_el02", CPENC (3, 5, C14, C3, 0), F_ARCHEXT },
-- { "cntv_ctl_el0", CPENC(3,3,C14,C3,1), 0 },
-- { "cntv_ctl_el02", CPENC (3, 5, C14, C3, 1), F_ARCHEXT },
-- { "cntv_cval_el0", CPENC(3,3,C14,C3,2), 0 },
-- { "cntv_cval_el02", CPENC (3, 5, C14, C3, 2), F_ARCHEXT },
-- { "cnthp_tval_el2", CPENC(3,4,C14,C2,0), 0 },
-- { "cnthp_ctl_el2", CPENC(3,4,C14,C2,1), 0 },
-- { "cnthp_cval_el2", CPENC(3,4,C14,C2,2), 0 },
-- { "cntps_tval_el1", CPENC(3,7,C14,C2,0), 0 },
-- { "cntps_ctl_el1", CPENC(3,7,C14,C2,1), 0 },
-- { "cntps_cval_el1", CPENC(3,7,C14,C2,2), 0 },
-- { "cnthv_tval_el2", CPENC (3, 4, C14, C3, 0), F_ARCHEXT },
-- { "cnthv_ctl_el2", CPENC (3, 4, C14, C3, 1), F_ARCHEXT },
-- { "cnthv_cval_el2", CPENC (3, 4, C14, C3, 2), F_ARCHEXT },
-- { "dacr32_el2", CPENC(3,4,C3,C0,0), 0 },
-- { "ifsr32_el2", CPENC(3,4,C5,C0,1), 0 },
-- { "teehbr32_el1", CPENC(2,2,C1,C0,0), 0 },
-- { "sder32_el3", CPENC(3,6,C1,C1,1), 0 },
-- { "mdscr_el1", CPENC(2,0,C0, C2, 2), 0 },
-- { "mdccsr_el0", CPENC(2,3,C0, C1, 0), 0 }, /* r */
-- { "mdccint_el1", CPENC(2,0,C0, C2, 0), 0 },
-- { "dbgdtr_el0", CPENC(2,3,C0, C4, 0), 0 },
-- { "dbgdtrrx_el0", CPENC(2,3,C0, C5, 0), 0 }, /* r */
-- { "dbgdtrtx_el0", CPENC(2,3,C0, C5, 0), 0 }, /* w */
-- { "osdtrrx_el1", CPENC(2,0,C0, C0, 2), 0 }, /* r */
-- { "osdtrtx_el1", CPENC(2,0,C0, C3, 2), 0 }, /* w */
-- { "oseccr_el1", CPENC(2,0,C0, C6, 2), 0 },
-- { "dbgvcr32_el2", CPENC(2,4,C0, C7, 0), 0 },
-- { "dbgbvr0_el1", CPENC(2,0,C0, C0, 4), 0 },
-- { "dbgbvr1_el1", CPENC(2,0,C0, C1, 4), 0 },
-- { "dbgbvr2_el1", CPENC(2,0,C0, C2, 4), 0 },
-- { "dbgbvr3_el1", CPENC(2,0,C0, C3, 4), 0 },
-- { "dbgbvr4_el1", CPENC(2,0,C0, C4, 4), 0 },
-- { "dbgbvr5_el1", CPENC(2,0,C0, C5, 4), 0 },
-- { "dbgbvr6_el1", CPENC(2,0,C0, C6, 4), 0 },
-- { "dbgbvr7_el1", CPENC(2,0,C0, C7, 4), 0 },
-- { "dbgbvr8_el1", CPENC(2,0,C0, C8, 4), 0 },
-- { "dbgbvr9_el1", CPENC(2,0,C0, C9, 4), 0 },
-- { "dbgbvr10_el1", CPENC(2,0,C0, C10,4), 0 },
-- { "dbgbvr11_el1", CPENC(2,0,C0, C11,4), 0 },
-- { "dbgbvr12_el1", CPENC(2,0,C0, C12,4), 0 },
-- { "dbgbvr13_el1", CPENC(2,0,C0, C13,4), 0 },
-- { "dbgbvr14_el1", CPENC(2,0,C0, C14,4), 0 },
-- { "dbgbvr15_el1", CPENC(2,0,C0, C15,4), 0 },
-- { "dbgbcr0_el1", CPENC(2,0,C0, C0, 5), 0 },
-- { "dbgbcr1_el1", CPENC(2,0,C0, C1, 5), 0 },
-- { "dbgbcr2_el1", CPENC(2,0,C0, C2, 5), 0 },
-- { "dbgbcr3_el1", CPENC(2,0,C0, C3, 5), 0 },
-- { "dbgbcr4_el1", CPENC(2,0,C0, C4, 5), 0 },
-- { "dbgbcr5_el1", CPENC(2,0,C0, C5, 5), 0 },
-- { "dbgbcr6_el1", CPENC(2,0,C0, C6, 5), 0 },
-- { "dbgbcr7_el1", CPENC(2,0,C0, C7, 5), 0 },
-- { "dbgbcr8_el1", CPENC(2,0,C0, C8, 5), 0 },
-- { "dbgbcr9_el1", CPENC(2,0,C0, C9, 5), 0 },
-- { "dbgbcr10_el1", CPENC(2,0,C0, C10,5), 0 },
-- { "dbgbcr11_el1", CPENC(2,0,C0, C11,5), 0 },
-- { "dbgbcr12_el1", CPENC(2,0,C0, C12,5), 0 },
-- { "dbgbcr13_el1", CPENC(2,0,C0, C13,5), 0 },
-- { "dbgbcr14_el1", CPENC(2,0,C0, C14,5), 0 },
-- { "dbgbcr15_el1", CPENC(2,0,C0, C15,5), 0 },
-- { "dbgwvr0_el1", CPENC(2,0,C0, C0, 6), 0 },
-- { "dbgwvr1_el1", CPENC(2,0,C0, C1, 6), 0 },
-- { "dbgwvr2_el1", CPENC(2,0,C0, C2, 6), 0 },
-- { "dbgwvr3_el1", CPENC(2,0,C0, C3, 6), 0 },
-- { "dbgwvr4_el1", CPENC(2,0,C0, C4, 6), 0 },
-- { "dbgwvr5_el1", CPENC(2,0,C0, C5, 6), 0 },
-- { "dbgwvr6_el1", CPENC(2,0,C0, C6, 6), 0 },
-- { "dbgwvr7_el1", CPENC(2,0,C0, C7, 6), 0 },
-- { "dbgwvr8_el1", CPENC(2,0,C0, C8, 6), 0 },
-- { "dbgwvr9_el1", CPENC(2,0,C0, C9, 6), 0 },
-- { "dbgwvr10_el1", CPENC(2,0,C0, C10,6), 0 },
-- { "dbgwvr11_el1", CPENC(2,0,C0, C11,6), 0 },
-- { "dbgwvr12_el1", CPENC(2,0,C0, C12,6), 0 },
-- { "dbgwvr13_el1", CPENC(2,0,C0, C13,6), 0 },
-- { "dbgwvr14_el1", CPENC(2,0,C0, C14,6), 0 },
-- { "dbgwvr15_el1", CPENC(2,0,C0, C15,6), 0 },
-- { "dbgwcr0_el1", CPENC(2,0,C0, C0, 7), 0 },
-- { "dbgwcr1_el1", CPENC(2,0,C0, C1, 7), 0 },
-- { "dbgwcr2_el1", CPENC(2,0,C0, C2, 7), 0 },
-- { "dbgwcr3_el1", CPENC(2,0,C0, C3, 7), 0 },
-- { "dbgwcr4_el1", CPENC(2,0,C0, C4, 7), 0 },
-- { "dbgwcr5_el1", CPENC(2,0,C0, C5, 7), 0 },
-- { "dbgwcr6_el1", CPENC(2,0,C0, C6, 7), 0 },
-- { "dbgwcr7_el1", CPENC(2,0,C0, C7, 7), 0 },
-- { "dbgwcr8_el1", CPENC(2,0,C0, C8, 7), 0 },
-- { "dbgwcr9_el1", CPENC(2,0,C0, C9, 7), 0 },
-- { "dbgwcr10_el1", CPENC(2,0,C0, C10,7), 0 },
-- { "dbgwcr11_el1", CPENC(2,0,C0, C11,7), 0 },
-- { "dbgwcr12_el1", CPENC(2,0,C0, C12,7), 0 },
-- { "dbgwcr13_el1", CPENC(2,0,C0, C13,7), 0 },
-- { "dbgwcr14_el1", CPENC(2,0,C0, C14,7), 0 },
-- { "dbgwcr15_el1", CPENC(2,0,C0, C15,7), 0 },
-- { "mdrar_el1", CPENC(2,0,C1, C0, 0), 0 }, /* r */
-- { "oslar_el1", CPENC(2,0,C1, C0, 4), 0 }, /* w */
-- { "oslsr_el1", CPENC(2,0,C1, C1, 4), 0 }, /* r */
-- { "osdlr_el1", CPENC(2,0,C1, C3, 4), 0 },
-- { "dbgprcr_el1", CPENC(2,0,C1, C4, 4), 0 },
-- { "dbgclaimset_el1", CPENC(2,0,C7, C8, 6), 0 },
-- { "dbgclaimclr_el1", CPENC(2,0,C7, C9, 6), 0 },
-- { "dbgauthstatus_el1", CPENC(2,0,C7, C14,6), 0 }, /* r */
-- { "pmblimitr_el1", CPENC (3, 0, C9, C10, 0), F_ARCHEXT }, /* rw */
-- { "pmbptr_el1", CPENC (3, 0, C9, C10, 1), F_ARCHEXT }, /* rw */
-- { "pmbsr_el1", CPENC (3, 0, C9, C10, 3), F_ARCHEXT }, /* rw */
-- { "pmbidr_el1", CPENC (3, 0, C9, C10, 7), F_ARCHEXT }, /* ro */
-- { "pmscr_el1", CPENC (3, 0, C9, C9, 0), F_ARCHEXT }, /* rw */
-- { "pmsicr_el1", CPENC (3, 0, C9, C9, 2), F_ARCHEXT }, /* rw */
-- { "pmsirr_el1", CPENC (3, 0, C9, C9, 3), F_ARCHEXT }, /* rw */
-- { "pmsfcr_el1", CPENC (3, 0, C9, C9, 4), F_ARCHEXT }, /* rw */
-- { "pmsevfr_el1", CPENC (3, 0, C9, C9, 5), F_ARCHEXT }, /* rw */
-- { "pmslatfr_el1", CPENC (3, 0, C9, C9, 6), F_ARCHEXT }, /* rw */
-- { "pmsidr_el1", CPENC (3, 0, C9, C9, 7), F_ARCHEXT }, /* ro */
-- { "pmscr_el2", CPENC (3, 4, C9, C9, 0), F_ARCHEXT }, /* rw */
-- { "pmscr_el12", CPENC (3, 5, C9, C9, 0), F_ARCHEXT }, /* rw */
-- { "pmcr_el0", CPENC(3,3,C9,C12, 0), 0 },
-- { "pmcntenset_el0", CPENC(3,3,C9,C12, 1), 0 },
-- { "pmcntenclr_el0", CPENC(3,3,C9,C12, 2), 0 },
-- { "pmovsclr_el0", CPENC(3,3,C9,C12, 3), 0 },
-- { "pmswinc_el0", CPENC(3,3,C9,C12, 4), 0 }, /* w */
-- { "pmselr_el0", CPENC(3,3,C9,C12, 5), 0 },
-- { "pmceid0_el0", CPENC(3,3,C9,C12, 6), 0 }, /* r */
-- { "pmceid1_el0", CPENC(3,3,C9,C12, 7), 0 }, /* r */
-- { "pmccntr_el0", CPENC(3,3,C9,C13, 0), 0 },
-- { "pmxevtyper_el0", CPENC(3,3,C9,C13, 1), 0 },
-- { "pmxevcntr_el0", CPENC(3,3,C9,C13, 2), 0 },
-- { "pmuserenr_el0", CPENC(3,3,C9,C14, 0), 0 },
-- { "pmintenset_el1", CPENC(3,0,C9,C14, 1), 0 },
-- { "pmintenclr_el1", CPENC(3,0,C9,C14, 2), 0 },
-- { "pmovsset_el0", CPENC(3,3,C9,C14, 3), 0 },
-- { "pmevcntr0_el0", CPENC(3,3,C14,C8, 0), 0 },
-- { "pmevcntr1_el0", CPENC(3,3,C14,C8, 1), 0 },
-- { "pmevcntr2_el0", CPENC(3,3,C14,C8, 2), 0 },
-- { "pmevcntr3_el0", CPENC(3,3,C14,C8, 3), 0 },
-- { "pmevcntr4_el0", CPENC(3,3,C14,C8, 4), 0 },
-- { "pmevcntr5_el0", CPENC(3,3,C14,C8, 5), 0 },
-- { "pmevcntr6_el0", CPENC(3,3,C14,C8, 6), 0 },
-- { "pmevcntr7_el0", CPENC(3,3,C14,C8, 7), 0 },
-- { "pmevcntr8_el0", CPENC(3,3,C14,C9, 0), 0 },
-- { "pmevcntr9_el0", CPENC(3,3,C14,C9, 1), 0 },
-- { "pmevcntr10_el0", CPENC(3,3,C14,C9, 2), 0 },
-- { "pmevcntr11_el0", CPENC(3,3,C14,C9, 3), 0 },
-- { "pmevcntr12_el0", CPENC(3,3,C14,C9, 4), 0 },
-- { "pmevcntr13_el0", CPENC(3,3,C14,C9, 5), 0 },
-- { "pmevcntr14_el0", CPENC(3,3,C14,C9, 6), 0 },
-- { "pmevcntr15_el0", CPENC(3,3,C14,C9, 7), 0 },
-- { "pmevcntr16_el0", CPENC(3,3,C14,C10,0), 0 },
-- { "pmevcntr17_el0", CPENC(3,3,C14,C10,1), 0 },
-- { "pmevcntr18_el0", CPENC(3,3,C14,C10,2), 0 },
-- { "pmevcntr19_el0", CPENC(3,3,C14,C10,3), 0 },
-- { "pmevcntr20_el0", CPENC(3,3,C14,C10,4), 0 },
-- { "pmevcntr21_el0", CPENC(3,3,C14,C10,5), 0 },
-- { "pmevcntr22_el0", CPENC(3,3,C14,C10,6), 0 },
-- { "pmevcntr23_el0", CPENC(3,3,C14,C10,7), 0 },
-- { "pmevcntr24_el0", CPENC(3,3,C14,C11,0), 0 },
-- { "pmevcntr25_el0", CPENC(3,3,C14,C11,1), 0 },
-- { "pmevcntr26_el0", CPENC(3,3,C14,C11,2), 0 },
-- { "pmevcntr27_el0", CPENC(3,3,C14,C11,3), 0 },
-- { "pmevcntr28_el0", CPENC(3,3,C14,C11,4), 0 },
-- { "pmevcntr29_el0", CPENC(3,3,C14,C11,5), 0 },
-- { "pmevcntr30_el0", CPENC(3,3,C14,C11,6), 0 },
-- { "pmevtyper0_el0", CPENC(3,3,C14,C12,0), 0 },
-- { "pmevtyper1_el0", CPENC(3,3,C14,C12,1), 0 },
-- { "pmevtyper2_el0", CPENC(3,3,C14,C12,2), 0 },
-- { "pmevtyper3_el0", CPENC(3,3,C14,C12,3), 0 },
-- { "pmevtyper4_el0", CPENC(3,3,C14,C12,4), 0 },
-- { "pmevtyper5_el0", CPENC(3,3,C14,C12,5), 0 },
-- { "pmevtyper6_el0", CPENC(3,3,C14,C12,6), 0 },
-- { "pmevtyper7_el0", CPENC(3,3,C14,C12,7), 0 },
-- { "pmevtyper8_el0", CPENC(3,3,C14,C13,0), 0 },
-- { "pmevtyper9_el0", CPENC(3,3,C14,C13,1), 0 },
-- { "pmevtyper10_el0", CPENC(3,3,C14,C13,2), 0 },
-- { "pmevtyper11_el0", CPENC(3,3,C14,C13,3), 0 },
-- { "pmevtyper12_el0", CPENC(3,3,C14,C13,4), 0 },
-- { "pmevtyper13_el0", CPENC(3,3,C14,C13,5), 0 },
-- { "pmevtyper14_el0", CPENC(3,3,C14,C13,6), 0 },
-- { "pmevtyper15_el0", CPENC(3,3,C14,C13,7), 0 },
-- { "pmevtyper16_el0", CPENC(3,3,C14,C14,0), 0 },
-- { "pmevtyper17_el0", CPENC(3,3,C14,C14,1), 0 },
-- { "pmevtyper18_el0", CPENC(3,3,C14,C14,2), 0 },
-- { "pmevtyper19_el0", CPENC(3,3,C14,C14,3), 0 },
-- { "pmevtyper20_el0", CPENC(3,3,C14,C14,4), 0 },
-- { "pmevtyper21_el0", CPENC(3,3,C14,C14,5), 0 },
-- { "pmevtyper22_el0", CPENC(3,3,C14,C14,6), 0 },
-- { "pmevtyper23_el0", CPENC(3,3,C14,C14,7), 0 },
-- { "pmevtyper24_el0", CPENC(3,3,C14,C15,0), 0 },
-- { "pmevtyper25_el0", CPENC(3,3,C14,C15,1), 0 },
-- { "pmevtyper26_el0", CPENC(3,3,C14,C15,2), 0 },
-- { "pmevtyper27_el0", CPENC(3,3,C14,C15,3), 0 },
-- { "pmevtyper28_el0", CPENC(3,3,C14,C15,4), 0 },
-- { "pmevtyper29_el0", CPENC(3,3,C14,C15,5), 0 },
-- { "pmevtyper30_el0", CPENC(3,3,C14,C15,6), 0 },
-- { "pmccfiltr_el0", CPENC(3,3,C14,C15,7), 0 },
--
-- { "dit", CPEN_ (3, C2, 5), F_ARCHEXT },
-- { "vstcr_el2", CPENC(3, 4, C2, C6, 2), F_ARCHEXT },
-- { "vsttbr_el2", CPENC(3, 4, C2, C6, 0), F_ARCHEXT },
-- { "cnthvs_tval_el2", CPENC(3, 4, C14, C4, 0), F_ARCHEXT },
-- { "cnthvs_cval_el2", CPENC(3, 4, C14, C4, 2), F_ARCHEXT },
-- { "cnthvs_ctl_el2", CPENC(3, 4, C14, C4, 1), F_ARCHEXT },
-- { "cnthps_tval_el2", CPENC(3, 4, C14, C5, 0), F_ARCHEXT },
-- { "cnthps_cval_el2", CPENC(3, 4, C14, C5, 2), F_ARCHEXT },
-- { "cnthps_ctl_el2", CPENC(3, 4, C14, C5, 1), F_ARCHEXT },
-- { "sder32_el2", CPENC(3, 4, C1, C3, 1), F_ARCHEXT },
-- { "vncr_el2", CPENC(3, 4, C2, C2, 0), F_ARCHEXT },
-- { 0, CPENC(0,0,0,0,0), 0 },
-+ SR_CORE ("spsr_el1", CPEN_ (0,C0,0), 0), /* = spsr_svc. */
-+ SR_V8_1 ("spsr_el12", CPEN_ (5,C0,0), 0),
-+ SR_CORE ("elr_el1", CPEN_ (0,C0,1), 0),
-+ SR_V8_1 ("elr_el12", CPEN_ (5,C0,1), 0),
-+ SR_CORE ("sp_el0", CPEN_ (0,C1,0), 0),
-+ SR_CORE ("spsel", CPEN_ (0,C2,0), 0),
-+ SR_CORE ("daif", CPEN_ (3,C2,1), 0),
-+ SR_CORE ("currentel", CPEN_ (0,C2,2), F_REG_READ),
-+ SR_PAN ("pan", CPEN_ (0,C2,3), 0),
-+ SR_V8_2 ("uao", CPEN_ (0,C2,4), 0),
-+ SR_CORE ("nzcv", CPEN_ (3,C2,0), 0),
-+ SR_SSBS ("ssbs", CPEN_ (3,C2,6), 0),
-+ SR_CORE ("fpcr", CPEN_ (3,C4,0), 0),
-+ SR_CORE ("fpsr", CPEN_ (3,C4,1), 0),
-+ SR_CORE ("dspsr_el0", CPEN_ (3,C5,0), 0),
-+ SR_CORE ("dlr_el0", CPEN_ (3,C5,1), 0),
-+ SR_CORE ("spsr_el2", CPEN_ (4,C0,0), 0), /* = spsr_hyp. */
-+ SR_CORE ("elr_el2", CPEN_ (4,C0,1), 0),
-+ SR_CORE ("sp_el1", CPEN_ (4,C1,0), 0),
-+ SR_CORE ("spsr_irq", CPEN_ (4,C3,0), 0),
-+ SR_CORE ("spsr_abt", CPEN_ (4,C3,1), 0),
-+ SR_CORE ("spsr_und", CPEN_ (4,C3,2), 0),
-+ SR_CORE ("spsr_fiq", CPEN_ (4,C3,3), 0),
-+ SR_CORE ("spsr_el3", CPEN_ (6,C0,0), 0),
-+ SR_CORE ("elr_el3", CPEN_ (6,C0,1), 0),
-+ SR_CORE ("sp_el2", CPEN_ (6,C1,0), 0),
-+ SR_CORE ("spsr_svc", CPEN_ (0,C0,0), F_DEPRECATED), /* = spsr_el1. */
-+ SR_CORE ("spsr_hyp", CPEN_ (4,C0,0), F_DEPRECATED), /* = spsr_el2. */
-+ SR_CORE ("midr_el1", CPENC (3,0,C0,C0,0), F_REG_READ),
-+ SR_CORE ("ctr_el0", CPENC (3,3,C0,C0,1), F_REG_READ),
-+ SR_CORE ("mpidr_el1", CPENC (3,0,C0,C0,5), F_REG_READ),
-+ SR_CORE ("revidr_el1", CPENC (3,0,C0,C0,6), F_REG_READ),
-+ SR_CORE ("aidr_el1", CPENC (3,1,C0,C0,7), F_REG_READ),
-+ SR_CORE ("dczid_el0", CPENC (3,3,C0,C0,7), F_REG_READ),
-+ SR_CORE ("id_dfr0_el1", CPENC (3,0,C0,C1,2), F_REG_READ),
-+ SR_CORE ("id_pfr0_el1", CPENC (3,0,C0,C1,0), F_REG_READ),
-+ SR_CORE ("id_pfr1_el1", CPENC (3,0,C0,C1,1), F_REG_READ),
-+ SR_ID_PFR2 ("id_pfr2_el1", CPENC (3,0,C0,C3,4), F_REG_READ),
-+ SR_CORE ("id_afr0_el1", CPENC (3,0,C0,C1,3), F_REG_READ),
-+ SR_CORE ("id_mmfr0_el1", CPENC (3,0,C0,C1,4), F_REG_READ),
-+ SR_CORE ("id_mmfr1_el1", CPENC (3,0,C0,C1,5), F_REG_READ),
-+ SR_CORE ("id_mmfr2_el1", CPENC (3,0,C0,C1,6), F_REG_READ),
-+ SR_CORE ("id_mmfr3_el1", CPENC (3,0,C0,C1,7), F_REG_READ),
-+ SR_CORE ("id_mmfr4_el1", CPENC (3,0,C0,C2,6), F_REG_READ),
-+ SR_CORE ("id_isar0_el1", CPENC (3,0,C0,C2,0), F_REG_READ),
-+ SR_CORE ("id_isar1_el1", CPENC (3,0,C0,C2,1), F_REG_READ),
-+ SR_CORE ("id_isar2_el1", CPENC (3,0,C0,C2,2), F_REG_READ),
-+ SR_CORE ("id_isar3_el1", CPENC (3,0,C0,C2,3), F_REG_READ),
-+ SR_CORE ("id_isar4_el1", CPENC (3,0,C0,C2,4), F_REG_READ),
-+ SR_CORE ("id_isar5_el1", CPENC (3,0,C0,C2,5), F_REG_READ),
-+ SR_CORE ("mvfr0_el1", CPENC (3,0,C0,C3,0), F_REG_READ),
-+ SR_CORE ("mvfr1_el1", CPENC (3,0,C0,C3,1), F_REG_READ),
-+ SR_CORE ("mvfr2_el1", CPENC (3,0,C0,C3,2), F_REG_READ),
-+ SR_CORE ("ccsidr_el1", CPENC (3,1,C0,C0,0), F_REG_READ),
-+ SR_CORE ("id_aa64pfr0_el1", CPENC (3,0,C0,C4,0), F_REG_READ),
-+ SR_CORE ("id_aa64pfr1_el1", CPENC (3,0,C0,C4,1), F_REG_READ),
-+ SR_CORE ("id_aa64dfr0_el1", CPENC (3,0,C0,C5,0), F_REG_READ),
-+ SR_CORE ("id_aa64dfr1_el1", CPENC (3,0,C0,C5,1), F_REG_READ),
-+ SR_CORE ("id_aa64isar0_el1", CPENC (3,0,C0,C6,0), F_REG_READ),
-+ SR_CORE ("id_aa64isar1_el1", CPENC (3,0,C0,C6,1), F_REG_READ),
-+ SR_CORE ("id_aa64mmfr0_el1", CPENC (3,0,C0,C7,0), F_REG_READ),
-+ SR_CORE ("id_aa64mmfr1_el1", CPENC (3,0,C0,C7,1), F_REG_READ),
-+ SR_CORE ("id_aa64mmfr2_el1", CPENC (3,0,C0,C7,2), F_REG_READ),
-+ SR_CORE ("id_aa64afr0_el1", CPENC (3,0,C0,C5,4), F_REG_READ),
-+ SR_CORE ("id_aa64afr1_el1", CPENC (3,0,C0,C5,5), F_REG_READ),
-+ SR_SVE ("id_aa64zfr0_el1", CPENC (3,0,C0,C4,4), F_REG_READ),
-+ SR_CORE ("clidr_el1", CPENC (3,1,C0,C0,1), F_REG_READ),
-+ SR_CORE ("csselr_el1", CPENC (3,2,C0,C0,0), 0),
-+ SR_CORE ("vpidr_el2", CPENC (3,4,C0,C0,0), 0),
-+ SR_CORE ("vmpidr_el2", CPENC (3,4,C0,C0,5), 0),
-+ SR_CORE ("sctlr_el1", CPENC (3,0,C1,C0,0), 0),
-+ SR_CORE ("sctlr_el2", CPENC (3,4,C1,C0,0), 0),
-+ SR_CORE ("sctlr_el3", CPENC (3,6,C1,C0,0), 0),
-+ SR_V8_1 ("sctlr_el12", CPENC (3,5,C1,C0,0), 0),
-+ SR_CORE ("actlr_el1", CPENC (3,0,C1,C0,1), 0),
-+ SR_CORE ("actlr_el2", CPENC (3,4,C1,C0,1), 0),
-+ SR_CORE ("actlr_el3", CPENC (3,6,C1,C0,1), 0),
-+ SR_CORE ("cpacr_el1", CPENC (3,0,C1,C0,2), 0),
-+ SR_V8_1 ("cpacr_el12", CPENC (3,5,C1,C0,2), 0),
-+ SR_CORE ("cptr_el2", CPENC (3,4,C1,C1,2), 0),
-+ SR_CORE ("cptr_el3", CPENC (3,6,C1,C1,2), 0),
-+ SR_CORE ("scr_el3", CPENC (3,6,C1,C1,0), 0),
-+ SR_CORE ("hcr_el2", CPENC (3,4,C1,C1,0), 0),
-+ SR_CORE ("mdcr_el2", CPENC (3,4,C1,C1,1), 0),
-+ SR_CORE ("mdcr_el3", CPENC (3,6,C1,C3,1), 0),
-+ SR_CORE ("hstr_el2", CPENC (3,4,C1,C1,3), 0),
-+ SR_CORE ("hacr_el2", CPENC (3,4,C1,C1,7), 0),
-+ SR_SVE ("zcr_el1", CPENC (3,0,C1,C2,0), 0),
-+ SR_SVE ("zcr_el12", CPENC (3,5,C1,C2,0), 0),
-+ SR_SVE ("zcr_el2", CPENC (3,4,C1,C2,0), 0),
-+ SR_SVE ("zcr_el3", CPENC (3,6,C1,C2,0), 0),
-+ SR_SVE ("zidr_el1", CPENC (3,0,C0,C0,7), 0),
-+ SR_CORE ("ttbr0_el1", CPENC (3,0,C2,C0,0), 0),
-+ SR_CORE ("ttbr1_el1", CPENC (3,0,C2,C0,1), 0),
-+ SR_V8_A ("ttbr0_el2", CPENC (3,4,C2,C0,0), 0),
-+ SR_V8_1_A ("ttbr1_el2", CPENC (3,4,C2,C0,1), 0),
-+ SR_CORE ("ttbr0_el3", CPENC (3,6,C2,C0,0), 0),
-+ SR_V8_1 ("ttbr0_el12", CPENC (3,5,C2,C0,0), 0),
-+ SR_V8_1 ("ttbr1_el12", CPENC (3,5,C2,C0,1), 0),
-+ SR_V8_A ("vttbr_el2", CPENC (3,4,C2,C1,0), 0),
-+ SR_CORE ("tcr_el1", CPENC (3,0,C2,C0,2), 0),
-+ SR_CORE ("tcr_el2", CPENC (3,4,C2,C0,2), 0),
-+ SR_CORE ("tcr_el3", CPENC (3,6,C2,C0,2), 0),
-+ SR_V8_1 ("tcr_el12", CPENC (3,5,C2,C0,2), 0),
-+ SR_CORE ("vtcr_el2", CPENC (3,4,C2,C1,2), 0),
-+ SR_V8_3 ("apiakeylo_el1", CPENC (3,0,C2,C1,0), 0),
-+ SR_V8_3 ("apiakeyhi_el1", CPENC (3,0,C2,C1,1), 0),
-+ SR_V8_3 ("apibkeylo_el1", CPENC (3,0,C2,C1,2), 0),
-+ SR_V8_3 ("apibkeyhi_el1", CPENC (3,0,C2,C1,3), 0),
-+ SR_V8_3 ("apdakeylo_el1", CPENC (3,0,C2,C2,0), 0),
-+ SR_V8_3 ("apdakeyhi_el1", CPENC (3,0,C2,C2,1), 0),
-+ SR_V8_3 ("apdbkeylo_el1", CPENC (3,0,C2,C2,2), 0),
-+ SR_V8_3 ("apdbkeyhi_el1", CPENC (3,0,C2,C2,3), 0),
-+ SR_V8_3 ("apgakeylo_el1", CPENC (3,0,C2,C3,0), 0),
-+ SR_V8_3 ("apgakeyhi_el1", CPENC (3,0,C2,C3,1), 0),
-+ SR_CORE ("afsr0_el1", CPENC (3,0,C5,C1,0), 0),
-+ SR_CORE ("afsr1_el1", CPENC (3,0,C5,C1,1), 0),
-+ SR_CORE ("afsr0_el2", CPENC (3,4,C5,C1,0), 0),
-+ SR_CORE ("afsr1_el2", CPENC (3,4,C5,C1,1), 0),
-+ SR_CORE ("afsr0_el3", CPENC (3,6,C5,C1,0), 0),
-+ SR_V8_1 ("afsr0_el12", CPENC (3,5,C5,C1,0), 0),
-+ SR_CORE ("afsr1_el3", CPENC (3,6,C5,C1,1), 0),
-+ SR_V8_1 ("afsr1_el12", CPENC (3,5,C5,C1,1), 0),
-+ SR_CORE ("esr_el1", CPENC (3,0,C5,C2,0), 0),
-+ SR_CORE ("esr_el2", CPENC (3,4,C5,C2,0), 0),
-+ SR_CORE ("esr_el3", CPENC (3,6,C5,C2,0), 0),
-+ SR_V8_1 ("esr_el12", CPENC (3,5,C5,C2,0), 0),
-+ SR_RAS ("vsesr_el2", CPENC (3,4,C5,C2,3), 0),
-+ SR_CORE ("fpexc32_el2", CPENC (3,4,C5,C3,0), 0),
-+ SR_RAS ("erridr_el1", CPENC (3,0,C5,C3,0), F_REG_READ),
-+ SR_RAS ("errselr_el1", CPENC (3,0,C5,C3,1), 0),
-+ SR_RAS ("erxfr_el1", CPENC (3,0,C5,C4,0), F_REG_READ),
-+ SR_RAS ("erxctlr_el1", CPENC (3,0,C5,C4,1), 0),
-+ SR_RAS ("erxstatus_el1", CPENC (3,0,C5,C4,2), 0),
-+ SR_RAS ("erxaddr_el1", CPENC (3,0,C5,C4,3), 0),
-+ SR_RAS ("erxmisc0_el1", CPENC (3,0,C5,C5,0), 0),
-+ SR_RAS ("erxmisc1_el1", CPENC (3,0,C5,C5,1), 0),
-+ SR_RAS ("erxmisc2_el1", CPENC (3,0,C5,C5,2), 0),
-+ SR_RAS ("erxmisc3_el1", CPENC (3,0,C5,C5,3), 0),
-+ SR_RAS ("erxpfgcdn_el1", CPENC (3,0,C5,C4,6), 0),
-+ SR_RAS ("erxpfgctl_el1", CPENC (3,0,C5,C4,5), 0),
-+ SR_RAS ("erxpfgf_el1", CPENC (3,0,C5,C4,4), F_REG_READ),
-+ SR_CORE ("far_el1", CPENC (3,0,C6,C0,0), 0),
-+ SR_CORE ("far_el2", CPENC (3,4,C6,C0,0), 0),
-+ SR_CORE ("far_el3", CPENC (3,6,C6,C0,0), 0),
-+ SR_V8_1 ("far_el12", CPENC (3,5,C6,C0,0), 0),
-+ SR_CORE ("hpfar_el2", CPENC (3,4,C6,C0,4), 0),
-+ SR_CORE ("par_el1", CPENC (3,0,C7,C4,0), 0),
-+ SR_CORE ("mair_el1", CPENC (3,0,C10,C2,0), 0),
-+ SR_CORE ("mair_el2", CPENC (3,4,C10,C2,0), 0),
-+ SR_CORE ("mair_el3", CPENC (3,6,C10,C2,0), 0),
-+ SR_V8_1 ("mair_el12", CPENC (3,5,C10,C2,0), 0),
-+ SR_CORE ("amair_el1", CPENC (3,0,C10,C3,0), 0),
-+ SR_CORE ("amair_el2", CPENC (3,4,C10,C3,0), 0),
-+ SR_CORE ("amair_el3", CPENC (3,6,C10,C3,0), 0),
-+ SR_V8_1 ("amair_el12", CPENC (3,5,C10,C3,0), 0),
-+ SR_CORE ("vbar_el1", CPENC (3,0,C12,C0,0), 0),
-+ SR_CORE ("vbar_el2", CPENC (3,4,C12,C0,0), 0),
-+ SR_CORE ("vbar_el3", CPENC (3,6,C12,C0,0), 0),
-+ SR_V8_1 ("vbar_el12", CPENC (3,5,C12,C0,0), 0),
-+ SR_CORE ("rvbar_el1", CPENC (3,0,C12,C0,1), F_REG_READ),
-+ SR_CORE ("rvbar_el2", CPENC (3,4,C12,C0,1), F_REG_READ),
-+ SR_CORE ("rvbar_el3", CPENC (3,6,C12,C0,1), F_REG_READ),
-+ SR_CORE ("rmr_el1", CPENC (3,0,C12,C0,2), 0),
-+ SR_CORE ("rmr_el2", CPENC (3,4,C12,C0,2), 0),
-+ SR_CORE ("rmr_el3", CPENC (3,6,C12,C0,2), 0),
-+ SR_CORE ("isr_el1", CPENC (3,0,C12,C1,0), F_REG_READ),
-+ SR_RAS ("disr_el1", CPENC (3,0,C12,C1,1), 0),
-+ SR_RAS ("vdisr_el2", CPENC (3,4,C12,C1,1), 0),
-+ SR_CORE ("contextidr_el1", CPENC (3,0,C13,C0,1), 0),
-+ SR_V8_1 ("contextidr_el2", CPENC (3,4,C13,C0,1), 0),
-+ SR_V8_1 ("contextidr_el12", CPENC (3,5,C13,C0,1), 0),
-+ SR_RNG ("rndr", CPENC (3,3,C2,C4,0), F_REG_READ),
-+ SR_RNG ("rndrrs", CPENC (3,3,C2,C4,1), F_REG_READ),
-+ SR_MEMTAG ("tco", CPENC (3,3,C4,C2,7), 0),
-+ SR_MEMTAG ("tfsre0_el1", CPENC (3,0,C5,C6,1), 0),
-+ SR_MEMTAG ("tfsr_el1", CPENC (3,0,C5,C6,0), 0),
-+ SR_MEMTAG ("tfsr_el2", CPENC (3,4,C5,C6,0), 0),
-+ SR_MEMTAG ("tfsr_el3", CPENC (3,6,C5,C6,0), 0),
-+ SR_MEMTAG ("tfsr_el12", CPENC (3,5,C5,C6,0), 0),
-+ SR_MEMTAG ("rgsr_el1", CPENC (3,0,C1,C0,5), 0),
-+ SR_MEMTAG ("gcr_el1", CPENC (3,0,C1,C0,6), 0),
-+ SR_MEMTAG ("gmid_el1", CPENC (3,1,C0,C0,4), F_REG_READ),
-+ SR_CORE ("tpidr_el0", CPENC (3,3,C13,C0,2), 0),
-+ SR_CORE ("tpidrro_el0", CPENC (3,3,C13,C0,3), 0),
-+ SR_CORE ("tpidr_el1", CPENC (3,0,C13,C0,4), 0),
-+ SR_CORE ("tpidr_el2", CPENC (3,4,C13,C0,2), 0),
-+ SR_CORE ("tpidr_el3", CPENC (3,6,C13,C0,2), 0),
-+ SR_SCXTNUM ("scxtnum_el0", CPENC (3,3,C13,C0,7), 0),
-+ SR_SCXTNUM ("scxtnum_el1", CPENC (3,0,C13,C0,7), 0),
-+ SR_SCXTNUM ("scxtnum_el2", CPENC (3,4,C13,C0,7), 0),
-+ SR_SCXTNUM ("scxtnum_el12", CPENC (3,5,C13,C0,7), 0),
-+ SR_SCXTNUM ("scxtnum_el3", CPENC (3,6,C13,C0,7), 0),
-+ SR_CORE ("teecr32_el1", CPENC (2,2,C0, C0,0), 0), /* See section 3.9.7.1. */
-+ SR_CORE ("cntfrq_el0", CPENC (3,3,C14,C0,0), 0),
-+ SR_CORE ("cntpct_el0", CPENC (3,3,C14,C0,1), F_REG_READ),
-+ SR_CORE ("cntvct_el0", CPENC (3,3,C14,C0,2), F_REG_READ),
-+ SR_CORE ("cntvoff_el2", CPENC (3,4,C14,C0,3), 0),
-+ SR_CORE ("cntkctl_el1", CPENC (3,0,C14,C1,0), 0),
-+ SR_V8_1 ("cntkctl_el12", CPENC (3,5,C14,C1,0), 0),
-+ SR_CORE ("cnthctl_el2", CPENC (3,4,C14,C1,0), 0),
-+ SR_CORE ("cntp_tval_el0", CPENC (3,3,C14,C2,0), 0),
-+ SR_V8_1 ("cntp_tval_el02", CPENC (3,5,C14,C2,0), 0),
-+ SR_CORE ("cntp_ctl_el0", CPENC (3,3,C14,C2,1), 0),
-+ SR_V8_1 ("cntp_ctl_el02", CPENC (3,5,C14,C2,1), 0),
-+ SR_CORE ("cntp_cval_el0", CPENC (3,3,C14,C2,2), 0),
-+ SR_V8_1 ("cntp_cval_el02", CPENC (3,5,C14,C2,2), 0),
-+ SR_CORE ("cntv_tval_el0", CPENC (3,3,C14,C3,0), 0),
-+ SR_V8_1 ("cntv_tval_el02", CPENC (3,5,C14,C3,0), 0),
-+ SR_CORE ("cntv_ctl_el0", CPENC (3,3,C14,C3,1), 0),
-+ SR_V8_1 ("cntv_ctl_el02", CPENC (3,5,C14,C3,1), 0),
-+ SR_CORE ("cntv_cval_el0", CPENC (3,3,C14,C3,2), 0),
-+ SR_V8_1 ("cntv_cval_el02", CPENC (3,5,C14,C3,2), 0),
-+ SR_CORE ("cnthp_tval_el2", CPENC (3,4,C14,C2,0), 0),
-+ SR_CORE ("cnthp_ctl_el2", CPENC (3,4,C14,C2,1), 0),
-+ SR_CORE ("cnthp_cval_el2", CPENC (3,4,C14,C2,2), 0),
-+ SR_CORE ("cntps_tval_el1", CPENC (3,7,C14,C2,0), 0),
-+ SR_CORE ("cntps_ctl_el1", CPENC (3,7,C14,C2,1), 0),
-+ SR_CORE ("cntps_cval_el1", CPENC (3,7,C14,C2,2), 0),
-+ SR_V8_1 ("cnthv_tval_el2", CPENC (3,4,C14,C3,0), 0),
-+ SR_V8_1 ("cnthv_ctl_el2", CPENC (3,4,C14,C3,1), 0),
-+ SR_V8_1 ("cnthv_cval_el2", CPENC (3,4,C14,C3,2), 0),
-+ SR_CORE ("dacr32_el2", CPENC (3,4,C3,C0,0), 0),
-+ SR_CORE ("ifsr32_el2", CPENC (3,4,C5,C0,1), 0),
-+ SR_CORE ("teehbr32_el1", CPENC (2,2,C1,C0,0), 0),
-+ SR_CORE ("sder32_el3", CPENC (3,6,C1,C1,1), 0),
-+ SR_CORE ("mdscr_el1", CPENC (2,0,C0,C2,2), 0),
-+ SR_CORE ("mdccsr_el0", CPENC (2,3,C0,C1,0), F_REG_READ),
-+ SR_CORE ("mdccint_el1", CPENC (2,0,C0,C2,0), 0),
-+ SR_CORE ("dbgdtr_el0", CPENC (2,3,C0,C4,0), 0),
-+ SR_CORE ("dbgdtrrx_el0", CPENC (2,3,C0,C5,0), F_REG_READ),
-+ SR_CORE ("dbgdtrtx_el0", CPENC (2,3,C0,C5,0), F_REG_WRITE),
-+ SR_CORE ("osdtrrx_el1", CPENC (2,0,C0,C0,2), 0),
-+ SR_CORE ("osdtrtx_el1", CPENC (2,0,C0,C3,2), 0),
-+ SR_CORE ("oseccr_el1", CPENC (2,0,C0,C6,2), 0),
-+ SR_CORE ("dbgvcr32_el2", CPENC (2,4,C0,C7,0), 0),
-+ SR_CORE ("dbgbvr0_el1", CPENC (2,0,C0,C0,4), 0),
-+ SR_CORE ("dbgbvr1_el1", CPENC (2,0,C0,C1,4), 0),
-+ SR_CORE ("dbgbvr2_el1", CPENC (2,0,C0,C2,4), 0),
-+ SR_CORE ("dbgbvr3_el1", CPENC (2,0,C0,C3,4), 0),
-+ SR_CORE ("dbgbvr4_el1", CPENC (2,0,C0,C4,4), 0),
-+ SR_CORE ("dbgbvr5_el1", CPENC (2,0,C0,C5,4), 0),
-+ SR_CORE ("dbgbvr6_el1", CPENC (2,0,C0,C6,4), 0),
-+ SR_CORE ("dbgbvr7_el1", CPENC (2,0,C0,C7,4), 0),
-+ SR_CORE ("dbgbvr8_el1", CPENC (2,0,C0,C8,4), 0),
-+ SR_CORE ("dbgbvr9_el1", CPENC (2,0,C0,C9,4), 0),
-+ SR_CORE ("dbgbvr10_el1", CPENC (2,0,C0,C10,4), 0),
-+ SR_CORE ("dbgbvr11_el1", CPENC (2,0,C0,C11,4), 0),
-+ SR_CORE ("dbgbvr12_el1", CPENC (2,0,C0,C12,4), 0),
-+ SR_CORE ("dbgbvr13_el1", CPENC (2,0,C0,C13,4), 0),
-+ SR_CORE ("dbgbvr14_el1", CPENC (2,0,C0,C14,4), 0),
-+ SR_CORE ("dbgbvr15_el1", CPENC (2,0,C0,C15,4), 0),
-+ SR_CORE ("dbgbcr0_el1", CPENC (2,0,C0,C0,5), 0),
-+ SR_CORE ("dbgbcr1_el1", CPENC (2,0,C0,C1,5), 0),
-+ SR_CORE ("dbgbcr2_el1", CPENC (2,0,C0,C2,5), 0),
-+ SR_CORE ("dbgbcr3_el1", CPENC (2,0,C0,C3,5), 0),
-+ SR_CORE ("dbgbcr4_el1", CPENC (2,0,C0,C4,5), 0),
-+ SR_CORE ("dbgbcr5_el1", CPENC (2,0,C0,C5,5), 0),
-+ SR_CORE ("dbgbcr6_el1", CPENC (2,0,C0,C6,5), 0),
-+ SR_CORE ("dbgbcr7_el1", CPENC (2,0,C0,C7,5), 0),
-+ SR_CORE ("dbgbcr8_el1", CPENC (2,0,C0,C8,5), 0),
-+ SR_CORE ("dbgbcr9_el1", CPENC (2,0,C0,C9,5), 0),
-+ SR_CORE ("dbgbcr10_el1", CPENC (2,0,C0,C10,5), 0),
-+ SR_CORE ("dbgbcr11_el1", CPENC (2,0,C0,C11,5), 0),
-+ SR_CORE ("dbgbcr12_el1", CPENC (2,0,C0,C12,5), 0),
-+ SR_CORE ("dbgbcr13_el1", CPENC (2,0,C0,C13,5), 0),
-+ SR_CORE ("dbgbcr14_el1", CPENC (2,0,C0,C14,5), 0),
-+ SR_CORE ("dbgbcr15_el1", CPENC (2,0,C0,C15,5), 0),
-+ SR_CORE ("dbgwvr0_el1", CPENC (2,0,C0,C0,6), 0),
-+ SR_CORE ("dbgwvr1_el1", CPENC (2,0,C0,C1,6), 0),
-+ SR_CORE ("dbgwvr2_el1", CPENC (2,0,C0,C2,6), 0),
-+ SR_CORE ("dbgwvr3_el1", CPENC (2,0,C0,C3,6), 0),
-+ SR_CORE ("dbgwvr4_el1", CPENC (2,0,C0,C4,6), 0),
-+ SR_CORE ("dbgwvr5_el1", CPENC (2,0,C0,C5,6), 0),
-+ SR_CORE ("dbgwvr6_el1", CPENC (2,0,C0,C6,6), 0),
-+ SR_CORE ("dbgwvr7_el1", CPENC (2,0,C0,C7,6), 0),
-+ SR_CORE ("dbgwvr8_el1", CPENC (2,0,C0,C8,6), 0),
-+ SR_CORE ("dbgwvr9_el1", CPENC (2,0,C0,C9,6), 0),
-+ SR_CORE ("dbgwvr10_el1", CPENC (2,0,C0,C10,6), 0),
-+ SR_CORE ("dbgwvr11_el1", CPENC (2,0,C0,C11,6), 0),
-+ SR_CORE ("dbgwvr12_el1", CPENC (2,0,C0,C12,6), 0),
-+ SR_CORE ("dbgwvr13_el1", CPENC (2,0,C0,C13,6), 0),
-+ SR_CORE ("dbgwvr14_el1", CPENC (2,0,C0,C14,6), 0),
-+ SR_CORE ("dbgwvr15_el1", CPENC (2,0,C0,C15,6), 0),
-+ SR_CORE ("dbgwcr0_el1", CPENC (2,0,C0,C0,7), 0),
-+ SR_CORE ("dbgwcr1_el1", CPENC (2,0,C0,C1,7), 0),
-+ SR_CORE ("dbgwcr2_el1", CPENC (2,0,C0,C2,7), 0),
-+ SR_CORE ("dbgwcr3_el1", CPENC (2,0,C0,C3,7), 0),
-+ SR_CORE ("dbgwcr4_el1", CPENC (2,0,C0,C4,7), 0),
-+ SR_CORE ("dbgwcr5_el1", CPENC (2,0,C0,C5,7), 0),
-+ SR_CORE ("dbgwcr6_el1", CPENC (2,0,C0,C6,7), 0),
-+ SR_CORE ("dbgwcr7_el1", CPENC (2,0,C0,C7,7), 0),
-+ SR_CORE ("dbgwcr8_el1", CPENC (2,0,C0,C8,7), 0),
-+ SR_CORE ("dbgwcr9_el1", CPENC (2,0,C0,C9,7), 0),
-+ SR_CORE ("dbgwcr10_el1", CPENC (2,0,C0,C10,7), 0),
-+ SR_CORE ("dbgwcr11_el1", CPENC (2,0,C0,C11,7), 0),
-+ SR_CORE ("dbgwcr12_el1", CPENC (2,0,C0,C12,7), 0),
-+ SR_CORE ("dbgwcr13_el1", CPENC (2,0,C0,C13,7), 0),
-+ SR_CORE ("dbgwcr14_el1", CPENC (2,0,C0,C14,7), 0),
-+ SR_CORE ("dbgwcr15_el1", CPENC (2,0,C0,C15,7), 0),
-+ SR_CORE ("mdrar_el1", CPENC (2,0,C1,C0,0), F_REG_READ),
-+ SR_CORE ("oslar_el1", CPENC (2,0,C1,C0,4), F_REG_WRITE),
-+ SR_CORE ("oslsr_el1", CPENC (2,0,C1,C1,4), F_REG_READ),
-+ SR_CORE ("osdlr_el1", CPENC (2,0,C1,C3,4), 0),
-+ SR_CORE ("dbgprcr_el1", CPENC (2,0,C1,C4,4), 0),
-+ SR_CORE ("dbgclaimset_el1", CPENC (2,0,C7,C8,6), 0),
-+ SR_CORE ("dbgclaimclr_el1", CPENC (2,0,C7,C9,6), 0),
-+ SR_CORE ("dbgauthstatus_el1", CPENC (2,0,C7,C14,6), F_REG_READ),
-+ SR_PROFILE ("pmblimitr_el1", CPENC (3,0,C9,C10,0), 0),
-+ SR_PROFILE ("pmbptr_el1", CPENC (3,0,C9,C10,1), 0),
-+ SR_PROFILE ("pmbsr_el1", CPENC (3,0,C9,C10,3), 0),
-+ SR_PROFILE ("pmbidr_el1", CPENC (3,0,C9,C10,7), F_REG_READ),
-+ SR_PROFILE ("pmscr_el1", CPENC (3,0,C9,C9,0), 0),
-+ SR_PROFILE ("pmsicr_el1", CPENC (3,0,C9,C9,2), 0),
-+ SR_PROFILE ("pmsirr_el1", CPENC (3,0,C9,C9,3), 0),
-+ SR_PROFILE ("pmsfcr_el1", CPENC (3,0,C9,C9,4), 0),
-+ SR_PROFILE ("pmsevfr_el1", CPENC (3,0,C9,C9,5), 0),
-+ SR_PROFILE ("pmslatfr_el1", CPENC (3,0,C9,C9,6), 0),
-+ SR_PROFILE ("pmsidr_el1", CPENC (3,0,C9,C9,7), 0),
-+ SR_PROFILE ("pmscr_el2", CPENC (3,4,C9,C9,0), 0),
-+ SR_PROFILE ("pmscr_el12", CPENC (3,5,C9,C9,0), 0),
-+ SR_CORE ("pmcr_el0", CPENC (3,3,C9,C12,0), 0),
-+ SR_CORE ("pmcntenset_el0", CPENC (3,3,C9,C12,1), 0),
-+ SR_CORE ("pmcntenclr_el0", CPENC (3,3,C9,C12,2), 0),
-+ SR_CORE ("pmovsclr_el0", CPENC (3,3,C9,C12,3), 0),
-+ SR_CORE ("pmswinc_el0", CPENC (3,3,C9,C12,4), F_REG_WRITE),
-+ SR_CORE ("pmselr_el0", CPENC (3,3,C9,C12,5), 0),
-+ SR_CORE ("pmceid0_el0", CPENC (3,3,C9,C12,6), F_REG_READ),
-+ SR_CORE ("pmceid1_el0", CPENC (3,3,C9,C12,7), F_REG_READ),
-+ SR_CORE ("pmccntr_el0", CPENC (3,3,C9,C13,0), 0),
-+ SR_CORE ("pmxevtyper_el0", CPENC (3,3,C9,C13,1), 0),
-+ SR_CORE ("pmxevcntr_el0", CPENC (3,3,C9,C13,2), 0),
-+ SR_CORE ("pmuserenr_el0", CPENC (3,3,C9,C14,0), 0),
-+ SR_CORE ("pmintenset_el1", CPENC (3,0,C9,C14,1), 0),
-+ SR_CORE ("pmintenclr_el1", CPENC (3,0,C9,C14,2), 0),
-+ SR_CORE ("pmovsset_el0", CPENC (3,3,C9,C14,3), 0),
-+ SR_CORE ("pmevcntr0_el0", CPENC (3,3,C14,C8,0), 0),
-+ SR_CORE ("pmevcntr1_el0", CPENC (3,3,C14,C8,1), 0),
-+ SR_CORE ("pmevcntr2_el0", CPENC (3,3,C14,C8,2), 0),
-+ SR_CORE ("pmevcntr3_el0", CPENC (3,3,C14,C8,3), 0),
-+ SR_CORE ("pmevcntr4_el0", CPENC (3,3,C14,C8,4), 0),
-+ SR_CORE ("pmevcntr5_el0", CPENC (3,3,C14,C8,5), 0),
-+ SR_CORE ("pmevcntr6_el0", CPENC (3,3,C14,C8,6), 0),
-+ SR_CORE ("pmevcntr7_el0", CPENC (3,3,C14,C8,7), 0),
-+ SR_CORE ("pmevcntr8_el0", CPENC (3,3,C14,C9,0), 0),
-+ SR_CORE ("pmevcntr9_el0", CPENC (3,3,C14,C9,1), 0),
-+ SR_CORE ("pmevcntr10_el0", CPENC (3,3,C14,C9,2), 0),
-+ SR_CORE ("pmevcntr11_el0", CPENC (3,3,C14,C9,3), 0),
-+ SR_CORE ("pmevcntr12_el0", CPENC (3,3,C14,C9,4), 0),
-+ SR_CORE ("pmevcntr13_el0", CPENC (3,3,C14,C9,5), 0),
-+ SR_CORE ("pmevcntr14_el0", CPENC (3,3,C14,C9,6), 0),
-+ SR_CORE ("pmevcntr15_el0", CPENC (3,3,C14,C9,7), 0),
-+ SR_CORE ("pmevcntr16_el0", CPENC (3,3,C14,C10,0), 0),
-+ SR_CORE ("pmevcntr17_el0", CPENC (3,3,C14,C10,1), 0),
-+ SR_CORE ("pmevcntr18_el0", CPENC (3,3,C14,C10,2), 0),
-+ SR_CORE ("pmevcntr19_el0", CPENC (3,3,C14,C10,3), 0),
-+ SR_CORE ("pmevcntr20_el0", CPENC (3,3,C14,C10,4), 0),
-+ SR_CORE ("pmevcntr21_el0", CPENC (3,3,C14,C10,5), 0),
-+ SR_CORE ("pmevcntr22_el0", CPENC (3,3,C14,C10,6), 0),
-+ SR_CORE ("pmevcntr23_el0", CPENC (3,3,C14,C10,7), 0),
-+ SR_CORE ("pmevcntr24_el0", CPENC (3,3,C14,C11,0), 0),
-+ SR_CORE ("pmevcntr25_el0", CPENC (3,3,C14,C11,1), 0),
-+ SR_CORE ("pmevcntr26_el0", CPENC (3,3,C14,C11,2), 0),
-+ SR_CORE ("pmevcntr27_el0", CPENC (3,3,C14,C11,3), 0),
-+ SR_CORE ("pmevcntr28_el0", CPENC (3,3,C14,C11,4), 0),
-+ SR_CORE ("pmevcntr29_el0", CPENC (3,3,C14,C11,5), 0),
-+ SR_CORE ("pmevcntr30_el0", CPENC (3,3,C14,C11,6), 0),
-+ SR_CORE ("pmevtyper0_el0", CPENC (3,3,C14,C12,0), 0),
-+ SR_CORE ("pmevtyper1_el0", CPENC (3,3,C14,C12,1), 0),
-+ SR_CORE ("pmevtyper2_el0", CPENC (3,3,C14,C12,2), 0),
-+ SR_CORE ("pmevtyper3_el0", CPENC (3,3,C14,C12,3), 0),
-+ SR_CORE ("pmevtyper4_el0", CPENC (3,3,C14,C12,4), 0),
-+ SR_CORE ("pmevtyper5_el0", CPENC (3,3,C14,C12,5), 0),
-+ SR_CORE ("pmevtyper6_el0", CPENC (3,3,C14,C12,6), 0),
-+ SR_CORE ("pmevtyper7_el0", CPENC (3,3,C14,C12,7), 0),
-+ SR_CORE ("pmevtyper8_el0", CPENC (3,3,C14,C13,0), 0),
-+ SR_CORE ("pmevtyper9_el0", CPENC (3,3,C14,C13,1), 0),
-+ SR_CORE ("pmevtyper10_el0", CPENC (3,3,C14,C13,2), 0),
-+ SR_CORE ("pmevtyper11_el0", CPENC (3,3,C14,C13,3), 0),
-+ SR_CORE ("pmevtyper12_el0", CPENC (3,3,C14,C13,4), 0),
-+ SR_CORE ("pmevtyper13_el0", CPENC (3,3,C14,C13,5), 0),
-+ SR_CORE ("pmevtyper14_el0", CPENC (3,3,C14,C13,6), 0),
-+ SR_CORE ("pmevtyper15_el0", CPENC (3,3,C14,C13,7), 0),
-+ SR_CORE ("pmevtyper16_el0", CPENC (3,3,C14,C14,0), 0),
-+ SR_CORE ("pmevtyper17_el0", CPENC (3,3,C14,C14,1), 0),
-+ SR_CORE ("pmevtyper18_el0", CPENC (3,3,C14,C14,2), 0),
-+ SR_CORE ("pmevtyper19_el0", CPENC (3,3,C14,C14,3), 0),
-+ SR_CORE ("pmevtyper20_el0", CPENC (3,3,C14,C14,4), 0),
-+ SR_CORE ("pmevtyper21_el0", CPENC (3,3,C14,C14,5), 0),
-+ SR_CORE ("pmevtyper22_el0", CPENC (3,3,C14,C14,6), 0),
-+ SR_CORE ("pmevtyper23_el0", CPENC (3,3,C14,C14,7), 0),
-+ SR_CORE ("pmevtyper24_el0", CPENC (3,3,C14,C15,0), 0),
-+ SR_CORE ("pmevtyper25_el0", CPENC (3,3,C14,C15,1), 0),
-+ SR_CORE ("pmevtyper26_el0", CPENC (3,3,C14,C15,2), 0),
-+ SR_CORE ("pmevtyper27_el0", CPENC (3,3,C14,C15,3), 0),
-+ SR_CORE ("pmevtyper28_el0", CPENC (3,3,C14,C15,4), 0),
-+ SR_CORE ("pmevtyper29_el0", CPENC (3,3,C14,C15,5), 0),
-+ SR_CORE ("pmevtyper30_el0", CPENC (3,3,C14,C15,6), 0),
-+ SR_CORE ("pmccfiltr_el0", CPENC (3,3,C14,C15,7), 0),
-+
-+ SR_V8_4 ("dit", CPEN_ (3,C2,5), 0),
-+ SR_V8_4 ("vstcr_el2", CPENC (3,4,C2,C6,2), 0),
-+ SR_V8_4_A ("vsttbr_el2", CPENC (3,4,C2,C6,0), 0),
-+ SR_V8_4 ("cnthvs_tval_el2", CPENC (3,4,C14,C4,0), 0),
-+ SR_V8_4 ("cnthvs_cval_el2", CPENC (3,4,C14,C4,2), 0),
-+ SR_V8_4 ("cnthvs_ctl_el2", CPENC (3,4,C14,C4,1), 0),
-+ SR_V8_4 ("cnthps_tval_el2", CPENC (3,4,C14,C5,0), 0),
-+ SR_V8_4 ("cnthps_cval_el2", CPENC (3,4,C14,C5,2), 0),
-+ SR_V8_4 ("cnthps_ctl_el2", CPENC (3,4,C14,C5,1), 0),
-+ SR_V8_4 ("sder32_el2", CPENC (3,4,C1,C3,1), 0),
-+ SR_V8_4 ("vncr_el2", CPENC (3,4,C2,C2,0), 0),
-+
-+ SR_CORE ("mpam0_el1", CPENC (3,0,C10,C5,1), 0),
-+ SR_CORE ("mpam1_el1", CPENC (3,0,C10,C5,0), 0),
-+ SR_CORE ("mpam1_el12", CPENC (3,5,C10,C5,0), 0),
-+ SR_CORE ("mpam2_el2", CPENC (3,4,C10,C5,0), 0),
-+ SR_CORE ("mpam3_el3", CPENC (3,6,C10,C5,0), 0),
-+ SR_CORE ("mpamhcr_el2", CPENC (3,4,C10,C4,0), 0),
-+ SR_CORE ("mpamidr_el1", CPENC (3,0,C10,C4,4), F_REG_READ),
-+ SR_CORE ("mpamvpm0_el2", CPENC (3,4,C10,C6,0), 0),
-+ SR_CORE ("mpamvpm1_el2", CPENC (3,4,C10,C6,1), 0),
-+ SR_CORE ("mpamvpm2_el2", CPENC (3,4,C10,C6,2), 0),
-+ SR_CORE ("mpamvpm3_el2", CPENC (3,4,C10,C6,3), 0),
-+ SR_CORE ("mpamvpm4_el2", CPENC (3,4,C10,C6,4), 0),
-+ SR_CORE ("mpamvpm5_el2", CPENC (3,4,C10,C6,5), 0),
-+ SR_CORE ("mpamvpm6_el2", CPENC (3,4,C10,C6,6), 0),
-+ SR_CORE ("mpamvpm7_el2", CPENC (3,4,C10,C6,7), 0),
-+ SR_CORE ("mpamvpmv_el2", CPENC (3,4,C10,C4,1), 0),
-+
-+ SR_V8_R ("mpuir_el1", CPENC (3,0,C0,C0,4), F_REG_READ),
-+ SR_V8_R ("mpuir_el2", CPENC (3,4,C0,C0,4), F_REG_READ),
-+ SR_V8_R ("prbar_el1", CPENC (3,0,C6,C8,0), 0),
-+ SR_V8_R ("prbar_el2", CPENC (3,4,C6,C8,0), 0),
-+
-+#define ENC_BARLAR(x,n,lar) \
-+ CPENC (3, (x-1) << 2, C6, 8 | (n >> 1), ((n & 1) << 2) | lar)
-+
-+#define PRBARn_ELx(x,n) SR_V8_R ("prbar" #n "_el" #x, ENC_BARLAR (x,n,0), 0)
-+#define PRLARn_ELx(x,n) SR_V8_R ("prlar" #n "_el" #x, ENC_BARLAR (x,n,1), 0)
-+
-+ SR_EXPAND_EL12 (PRBARn_ELx)
-+ SR_V8_R ("prenr_el1", CPENC (3,0,C6,C1,1), 0),
-+ SR_V8_R ("prenr_el2", CPENC (3,4,C6,C1,1), 0),
-+ SR_V8_R ("prlar_el1", CPENC (3,0,C6,C8,1), 0),
-+ SR_V8_R ("prlar_el2", CPENC (3,4,C6,C8,1), 0),
-+ SR_EXPAND_EL12 (PRLARn_ELx)
-+ SR_V8_R ("prselr_el1", CPENC (3,0,C6,C2,1), 0),
-+ SR_V8_R ("prselr_el2", CPENC (3,4,C6,C2,1), 0),
-+ SR_V8_R ("vsctlr_el2", CPENC (3,4,C2,C0,0), 0),
-+
-+ SR_CORE("trbbaser_el1", CPENC (3,0,C9,C11,2), 0),
-+ SR_CORE("trbidr_el1", CPENC (3,0,C9,C11,7), F_REG_READ),
-+ SR_CORE("trblimitr_el1", CPENC (3,0,C9,C11,0), 0),
-+ SR_CORE("trbmar_el1", CPENC (3,0,C9,C11,4), 0),
-+ SR_CORE("trbptr_el1", CPENC (3,0,C9,C11,1), 0),
-+ SR_CORE("trbsr_el1", CPENC (3,0,C9,C11,3), 0),
-+ SR_CORE("trbtrg_el1", CPENC (3,0,C9,C11,6), 0),
-+
-+ SR_CORE ("trcextinselr0", CPENC (2,1,C0,C8,4), 0),
-+ SR_CORE ("trcextinselr1", CPENC (2,1,C0,C9,4), 0),
-+ SR_CORE ("trcextinselr2", CPENC (2,1,C0,C10,4), 0),
-+ SR_CORE ("trcextinselr3", CPENC (2,1,C0,C11,4), 0),
-+ SR_CORE ("trcrsr", CPENC (2,1,C0,C10,0), 0),
-+
-+ SR_CORE ("trcauthstatus", CPENC (2,1,C7,C14,6), F_REG_READ),
-+ SR_CORE ("trccidr0", CPENC (2,1,C7,C12,7), F_REG_READ),
-+ SR_CORE ("trccidr1", CPENC (2,1,C7,C13,7), F_REG_READ),
-+ SR_CORE ("trccidr2", CPENC (2,1,C7,C14,7), F_REG_READ),
-+ SR_CORE ("trccidr3", CPENC (2,1,C7,C15,7), F_REG_READ),
-+ SR_CORE ("trcdevaff0", CPENC (2,1,C7,C10,6), F_REG_READ),
-+ SR_CORE ("trcdevaff1", CPENC (2,1,C7,C11,6), F_REG_READ),
-+ SR_CORE ("trcdevarch", CPENC (2,1,C7,C15,6), F_REG_READ),
-+ SR_CORE ("trcdevid", CPENC (2,1,C7,C2,7), F_REG_READ),
-+ SR_CORE ("trcdevtype", CPENC (2,1,C7,C3,7), F_REG_READ),
-+ SR_CORE ("trcidr0", CPENC (2,1,C0,C8,7), F_REG_READ),
-+ SR_CORE ("trcidr1", CPENC (2,1,C0,C9,7), F_REG_READ),
-+ SR_CORE ("trcidr2", CPENC (2,1,C0,C10,7), F_REG_READ),
-+ SR_CORE ("trcidr3", CPENC (2,1,C0,C11,7), F_REG_READ),
-+ SR_CORE ("trcidr4", CPENC (2,1,C0,C12,7), F_REG_READ),
-+ SR_CORE ("trcidr5", CPENC (2,1,C0,C13,7), F_REG_READ),
-+ SR_CORE ("trcidr6", CPENC (2,1,C0,C14,7), F_REG_READ),
-+ SR_CORE ("trcidr7", CPENC (2,1,C0,C15,7), F_REG_READ),
-+ SR_CORE ("trcidr8", CPENC (2,1,C0,C0,6), F_REG_READ),
-+ SR_CORE ("trcidr9", CPENC (2,1,C0,C1,6), F_REG_READ),
-+ SR_CORE ("trcidr10", CPENC (2,1,C0,C2,6), F_REG_READ),
-+ SR_CORE ("trcidr11", CPENC (2,1,C0,C3,6), F_REG_READ),
-+ SR_CORE ("trcidr12", CPENC (2,1,C0,C4,6), F_REG_READ),
-+ SR_CORE ("trcidr13", CPENC (2,1,C0,C5,6), F_REG_READ),
-+ SR_CORE ("trclsr", CPENC (2,1,C7,C13,6), F_REG_READ),
-+ SR_CORE ("trcoslsr", CPENC (2,1,C1,C1,4), F_REG_READ),
-+ SR_CORE ("trcpdsr", CPENC (2,1,C1,C5,4), F_REG_READ),
-+ SR_CORE ("trcpidr0", CPENC (2,1,C7,C8,7), F_REG_READ),
-+ SR_CORE ("trcpidr1", CPENC (2,1,C7,C9,7), F_REG_READ),
-+ SR_CORE ("trcpidr2", CPENC (2,1,C7,C10,7), F_REG_READ),
-+ SR_CORE ("trcpidr3", CPENC (2,1,C7,C11,7), F_REG_READ),
-+ SR_CORE ("trcpidr4", CPENC (2,1,C7,C4,7), F_REG_READ),
-+ SR_CORE ("trcpidr5", CPENC (2,1,C7,C5,7), F_REG_READ),
-+ SR_CORE ("trcpidr6", CPENC (2,1,C7,C6,7), F_REG_READ),
-+ SR_CORE ("trcpidr7", CPENC (2,1,C7,C7,7), F_REG_READ),
-+ SR_CORE ("trcstatr", CPENC (2,1,C0,C3,0), F_REG_READ),
-+ SR_CORE ("trcacatr0", CPENC (2,1,C2,C0,2), 0),
-+ SR_CORE ("trcacatr1", CPENC (2,1,C2,C2,2), 0),
-+ SR_CORE ("trcacatr2", CPENC (2,1,C2,C4,2), 0),
-+ SR_CORE ("trcacatr3", CPENC (2,1,C2,C6,2), 0),
-+ SR_CORE ("trcacatr4", CPENC (2,1,C2,C8,2), 0),
-+ SR_CORE ("trcacatr5", CPENC (2,1,C2,C10,2), 0),
-+ SR_CORE ("trcacatr6", CPENC (2,1,C2,C12,2), 0),
-+ SR_CORE ("trcacatr7", CPENC (2,1,C2,C14,2), 0),
-+ SR_CORE ("trcacatr8", CPENC (2,1,C2,C0,3), 0),
-+ SR_CORE ("trcacatr9", CPENC (2,1,C2,C2,3), 0),
-+ SR_CORE ("trcacatr10", CPENC (2,1,C2,C4,3), 0),
-+ SR_CORE ("trcacatr11", CPENC (2,1,C2,C6,3), 0),
-+ SR_CORE ("trcacatr12", CPENC (2,1,C2,C8,3), 0),
-+ SR_CORE ("trcacatr13", CPENC (2,1,C2,C10,3), 0),
-+ SR_CORE ("trcacatr14", CPENC (2,1,C2,C12,3), 0),
-+ SR_CORE ("trcacatr15", CPENC (2,1,C2,C14,3), 0),
-+ SR_CORE ("trcacvr0", CPENC (2,1,C2,C0,0), 0),
-+ SR_CORE ("trcacvr1", CPENC (2,1,C2,C2,0), 0),
-+ SR_CORE ("trcacvr2", CPENC (2,1,C2,C4,0), 0),
-+ SR_CORE ("trcacvr3", CPENC (2,1,C2,C6,0), 0),
-+ SR_CORE ("trcacvr4", CPENC (2,1,C2,C8,0), 0),
-+ SR_CORE ("trcacvr5", CPENC (2,1,C2,C10,0), 0),
-+ SR_CORE ("trcacvr6", CPENC (2,1,C2,C12,0), 0),
-+ SR_CORE ("trcacvr7", CPENC (2,1,C2,C14,0), 0),
-+ SR_CORE ("trcacvr8", CPENC (2,1,C2,C0,1), 0),
-+ SR_CORE ("trcacvr9", CPENC (2,1,C2,C2,1), 0),
-+ SR_CORE ("trcacvr10", CPENC (2,1,C2,C4,1), 0),
-+ SR_CORE ("trcacvr11", CPENC (2,1,C2,C6,1), 0),
-+ SR_CORE ("trcacvr12", CPENC (2,1,C2,C8,1), 0),
-+ SR_CORE ("trcacvr13", CPENC (2,1,C2,C10,1), 0),
-+ SR_CORE ("trcacvr14", CPENC (2,1,C2,C12,1), 0),
-+ SR_CORE ("trcacvr15", CPENC (2,1,C2,C14,1), 0),
-+ SR_CORE ("trcauxctlr", CPENC (2,1,C0,C6,0), 0),
-+ SR_CORE ("trcbbctlr", CPENC (2,1,C0,C15,0), 0),
-+ SR_CORE ("trcccctlr", CPENC (2,1,C0,C14,0), 0),
-+ SR_CORE ("trccidcctlr0", CPENC (2,1,C3,C0,2), 0),
-+ SR_CORE ("trccidcctlr1", CPENC (2,1,C3,C1,2), 0),
-+ SR_CORE ("trccidcvr0", CPENC (2,1,C3,C0,0), 0),
-+ SR_CORE ("trccidcvr1", CPENC (2,1,C3,C2,0), 0),
-+ SR_CORE ("trccidcvr2", CPENC (2,1,C3,C4,0), 0),
-+ SR_CORE ("trccidcvr3", CPENC (2,1,C3,C6,0), 0),
-+ SR_CORE ("trccidcvr4", CPENC (2,1,C3,C8,0), 0),
-+ SR_CORE ("trccidcvr5", CPENC (2,1,C3,C10,0), 0),
-+ SR_CORE ("trccidcvr6", CPENC (2,1,C3,C12,0), 0),
-+ SR_CORE ("trccidcvr7", CPENC (2,1,C3,C14,0), 0),
-+ SR_CORE ("trcclaimclr", CPENC (2,1,C7,C9,6), 0),
-+ SR_CORE ("trcclaimset", CPENC (2,1,C7,C8,6), 0),
-+ SR_CORE ("trccntctlr0", CPENC (2,1,C0,C4,5), 0),
-+ SR_CORE ("trccntctlr1", CPENC (2,1,C0,C5,5), 0),
-+ SR_CORE ("trccntctlr2", CPENC (2,1,C0,C6,5), 0),
-+ SR_CORE ("trccntctlr3", CPENC (2,1,C0,C7,5), 0),
-+ SR_CORE ("trccntrldvr0", CPENC (2,1,C0,C0,5), 0),
-+ SR_CORE ("trccntrldvr1", CPENC (2,1,C0,C1,5), 0),
-+ SR_CORE ("trccntrldvr2", CPENC (2,1,C0,C2,5), 0),
-+ SR_CORE ("trccntrldvr3", CPENC (2,1,C0,C3,5), 0),
-+ SR_CORE ("trccntvr0", CPENC (2,1,C0,C8,5), 0),
-+ SR_CORE ("trccntvr1", CPENC (2,1,C0,C9,5), 0),
-+ SR_CORE ("trccntvr2", CPENC (2,1,C0,C10,5), 0),
-+ SR_CORE ("trccntvr3", CPENC (2,1,C0,C11,5), 0),
-+ SR_CORE ("trcconfigr", CPENC (2,1,C0,C4,0), 0),
-+ SR_CORE ("trcdvcmr0", CPENC (2,1,C2,C0,6), 0),
-+ SR_CORE ("trcdvcmr1", CPENC (2,1,C2,C4,6), 0),
-+ SR_CORE ("trcdvcmr2", CPENC (2,1,C2,C8,6), 0),
-+ SR_CORE ("trcdvcmr3", CPENC (2,1,C2,C12,6), 0),
-+ SR_CORE ("trcdvcmr4", CPENC (2,1,C2,C0,7), 0),
-+ SR_CORE ("trcdvcmr5", CPENC (2,1,C2,C4,7), 0),
-+ SR_CORE ("trcdvcmr6", CPENC (2,1,C2,C8,7), 0),
-+ SR_CORE ("trcdvcmr7", CPENC (2,1,C2,C12,7), 0),
-+ SR_CORE ("trcdvcvr0", CPENC (2,1,C2,C0,4), 0),
-+ SR_CORE ("trcdvcvr1", CPENC (2,1,C2,C4,4), 0),
-+ SR_CORE ("trcdvcvr2", CPENC (2,1,C2,C8,4), 0),
-+ SR_CORE ("trcdvcvr3", CPENC (2,1,C2,C12,4), 0),
-+ SR_CORE ("trcdvcvr4", CPENC (2,1,C2,C0,5), 0),
-+ SR_CORE ("trcdvcvr5", CPENC (2,1,C2,C4,5), 0),
-+ SR_CORE ("trcdvcvr6", CPENC (2,1,C2,C8,5), 0),
-+ SR_CORE ("trcdvcvr7", CPENC (2,1,C2,C12,5), 0),
-+ SR_CORE ("trceventctl0r", CPENC (2,1,C0,C8,0), 0),
-+ SR_CORE ("trceventctl1r", CPENC (2,1,C0,C9,0), 0),
-+ SR_CORE ("trcextinselr0", CPENC (2,1,C0,C8,4), 0),
-+ SR_CORE ("trcextinselr", CPENC (2,1,C0,C8,4), 0),
-+ SR_CORE ("trcextinselr1", CPENC (2,1,C0,C9,4), 0),
-+ SR_CORE ("trcextinselr2", CPENC (2,1,C0,C10,4), 0),
-+ SR_CORE ("trcextinselr3", CPENC (2,1,C0,C11,4), 0),
-+ SR_CORE ("trcimspec0", CPENC (2,1,C0,C0,7), 0),
-+ SR_CORE ("trcimspec0", CPENC (2,1,C0,C0,7), 0),
-+ SR_CORE ("trcimspec1", CPENC (2,1,C0,C1,7), 0),
-+ SR_CORE ("trcimspec2", CPENC (2,1,C0,C2,7), 0),
-+ SR_CORE ("trcimspec3", CPENC (2,1,C0,C3,7), 0),
-+ SR_CORE ("trcimspec4", CPENC (2,1,C0,C4,7), 0),
-+ SR_CORE ("trcimspec5", CPENC (2,1,C0,C5,7), 0),
-+ SR_CORE ("trcimspec6", CPENC (2,1,C0,C6,7), 0),
-+ SR_CORE ("trcimspec7", CPENC (2,1,C0,C7,7), 0),
-+ SR_CORE ("trcitctrl", CPENC (2,1,C7,C0,4), 0),
-+ SR_CORE ("trcpdcr", CPENC (2,1,C1,C4,4), 0),
-+ SR_CORE ("trcprgctlr", CPENC (2,1,C0,C1,0), 0),
-+ SR_CORE ("trcprocselr", CPENC (2,1,C0,C2,0), 0),
-+ SR_CORE ("trcqctlr", CPENC (2,1,C0,C1,1), 0),
-+ SR_CORE ("trcrsctlr2", CPENC (2,1,C1,C2,0), 0),
-+ SR_CORE ("trcrsctlr3", CPENC (2,1,C1,C3,0), 0),
-+ SR_CORE ("trcrsctlr4", CPENC (2,1,C1,C4,0), 0),
-+ SR_CORE ("trcrsctlr5", CPENC (2,1,C1,C5,0), 0),
-+ SR_CORE ("trcrsctlr6", CPENC (2,1,C1,C6,0), 0),
-+ SR_CORE ("trcrsctlr7", CPENC (2,1,C1,C7,0), 0),
-+ SR_CORE ("trcrsctlr8", CPENC (2,1,C1,C8,0), 0),
-+ SR_CORE ("trcrsctlr9", CPENC (2,1,C1,C9,0), 0),
-+ SR_CORE ("trcrsctlr10", CPENC (2,1,C1,C10,0), 0),
-+ SR_CORE ("trcrsctlr11", CPENC (2,1,C1,C11,0), 0),
-+ SR_CORE ("trcrsctlr12", CPENC (2,1,C1,C12,0), 0),
-+ SR_CORE ("trcrsctlr13", CPENC (2,1,C1,C13,0), 0),
-+ SR_CORE ("trcrsctlr14", CPENC (2,1,C1,C14,0), 0),
-+ SR_CORE ("trcrsctlr15", CPENC (2,1,C1,C15,0), 0),
-+ SR_CORE ("trcrsctlr16", CPENC (2,1,C1,C0,1), 0),
-+ SR_CORE ("trcrsctlr17", CPENC (2,1,C1,C1,1), 0),
-+ SR_CORE ("trcrsctlr18", CPENC (2,1,C1,C2,1), 0),
-+ SR_CORE ("trcrsctlr19", CPENC (2,1,C1,C3,1), 0),
-+ SR_CORE ("trcrsctlr20", CPENC (2,1,C1,C4,1), 0),
-+ SR_CORE ("trcrsctlr21", CPENC (2,1,C1,C5,1), 0),
-+ SR_CORE ("trcrsctlr22", CPENC (2,1,C1,C6,1), 0),
-+ SR_CORE ("trcrsctlr23", CPENC (2,1,C1,C7,1), 0),
-+ SR_CORE ("trcrsctlr24", CPENC (2,1,C1,C8,1), 0),
-+ SR_CORE ("trcrsctlr25", CPENC (2,1,C1,C9,1), 0),
-+ SR_CORE ("trcrsctlr26", CPENC (2,1,C1,C10,1), 0),
-+ SR_CORE ("trcrsctlr27", CPENC (2,1,C1,C11,1), 0),
-+ SR_CORE ("trcrsctlr28", CPENC (2,1,C1,C12,1), 0),
-+ SR_CORE ("trcrsctlr29", CPENC (2,1,C1,C13,1), 0),
-+ SR_CORE ("trcrsctlr30", CPENC (2,1,C1,C14,1), 0),
-+ SR_CORE ("trcrsctlr31", CPENC (2,1,C1,C15,1), 0),
-+ SR_CORE ("trcseqevr0", CPENC (2,1,C0,C0,4), 0),
-+ SR_CORE ("trcseqevr1", CPENC (2,1,C0,C1,4), 0),
-+ SR_CORE ("trcseqevr2", CPENC (2,1,C0,C2,4), 0),
-+ SR_CORE ("trcseqrstevr", CPENC (2,1,C0,C6,4), 0),
-+ SR_CORE ("trcseqstr", CPENC (2,1,C0,C7,4), 0),
-+ SR_CORE ("trcssccr0", CPENC (2,1,C1,C0,2), 0),
-+ SR_CORE ("trcssccr1", CPENC (2,1,C1,C1,2), 0),
-+ SR_CORE ("trcssccr2", CPENC (2,1,C1,C2,2), 0),
-+ SR_CORE ("trcssccr3", CPENC (2,1,C1,C3,2), 0),
-+ SR_CORE ("trcssccr4", CPENC (2,1,C1,C4,2), 0),
-+ SR_CORE ("trcssccr5", CPENC (2,1,C1,C5,2), 0),
-+ SR_CORE ("trcssccr6", CPENC (2,1,C1,C6,2), 0),
-+ SR_CORE ("trcssccr7", CPENC (2,1,C1,C7,2), 0),
-+ SR_CORE ("trcsscsr0", CPENC (2,1,C1,C8,2), 0),
-+ SR_CORE ("trcsscsr1", CPENC (2,1,C1,C9,2), 0),
-+ SR_CORE ("trcsscsr2", CPENC (2,1,C1,C10,2), 0),
-+ SR_CORE ("trcsscsr3", CPENC (2,1,C1,C11,2), 0),
-+ SR_CORE ("trcsscsr4", CPENC (2,1,C1,C12,2), 0),
-+ SR_CORE ("trcsscsr5", CPENC (2,1,C1,C13,2), 0),
-+ SR_CORE ("trcsscsr6", CPENC (2,1,C1,C14,2), 0),
-+ SR_CORE ("trcsscsr7", CPENC (2,1,C1,C15,2), 0),
-+ SR_CORE ("trcsspcicr0", CPENC (2,1,C1,C0,3), 0),
-+ SR_CORE ("trcsspcicr1", CPENC (2,1,C1,C1,3), 0),
-+ SR_CORE ("trcsspcicr2", CPENC (2,1,C1,C2,3), 0),
-+ SR_CORE ("trcsspcicr3", CPENC (2,1,C1,C3,3), 0),
-+ SR_CORE ("trcsspcicr4", CPENC (2,1,C1,C4,3), 0),
-+ SR_CORE ("trcsspcicr5", CPENC (2,1,C1,C5,3), 0),
-+ SR_CORE ("trcsspcicr6", CPENC (2,1,C1,C6,3), 0),
-+ SR_CORE ("trcsspcicr7", CPENC (2,1,C1,C7,3), 0),
-+ SR_CORE ("trcstallctlr", CPENC (2,1,C0,C11,0), 0),
-+ SR_CORE ("trcsyncpr", CPENC (2,1,C0,C13,0), 0),
-+ SR_CORE ("trctraceidr", CPENC (2,1,C0,C0,1), 0),
-+ SR_CORE ("trctsctlr", CPENC (2,1,C0,C12,0), 0),
-+ SR_CORE ("trcvdarcctlr", CPENC (2,1,C0,C10,2), 0),
-+ SR_CORE ("trcvdctlr", CPENC (2,1,C0,C8,2), 0),
-+ SR_CORE ("trcvdsacctlr", CPENC (2,1,C0,C9,2), 0),
-+ SR_CORE ("trcvictlr", CPENC (2,1,C0,C0,2), 0),
-+ SR_CORE ("trcviiectlr", CPENC (2,1,C0,C1,2), 0),
-+ SR_CORE ("trcvipcssctlr", CPENC (2,1,C0,C3,2), 0),
-+ SR_CORE ("trcvissctlr", CPENC (2,1,C0,C2,2), 0),
-+ SR_CORE ("trcvmidcctlr0", CPENC (2,1,C3,C2,2), 0),
-+ SR_CORE ("trcvmidcctlr1", CPENC (2,1,C3,C3,2), 0),
-+ SR_CORE ("trcvmidcvr0", CPENC (2,1,C3,C0,1), 0),
-+ SR_CORE ("trcvmidcvr1", CPENC (2,1,C3,C2,1), 0),
-+ SR_CORE ("trcvmidcvr2", CPENC (2,1,C3,C4,1), 0),
-+ SR_CORE ("trcvmidcvr3", CPENC (2,1,C3,C6,1), 0),
-+ SR_CORE ("trcvmidcvr4", CPENC (2,1,C3,C8,1), 0),
-+ SR_CORE ("trcvmidcvr5", CPENC (2,1,C3,C10,1), 0),
-+ SR_CORE ("trcvmidcvr6", CPENC (2,1,C3,C12,1), 0),
-+ SR_CORE ("trcvmidcvr7", CPENC (2,1,C3,C14,1), 0),
-+ SR_CORE ("trclar", CPENC (2,1,C7,C12,6), F_REG_WRITE),
-+ SR_CORE ("trcoslar", CPENC (2,1,C1,C0,4), F_REG_WRITE),
-+
-+ SR_CORE ("csrcr_el0", CPENC (2,3,C8,C0,0), 0),
-+ SR_CORE ("csrptr_el0", CPENC (2,3,C8,C0,1), 0),
-+ SR_CORE ("csridr_el0", CPENC (2,3,C8,C0,2), F_REG_READ),
-+ SR_CORE ("csrptridx_el0", CPENC (2,3,C8,C0,3), F_REG_READ),
-+ SR_CORE ("csrcr_el1", CPENC (2,0,C8,C0,0), 0),
-+ SR_CORE ("csrcr_el12", CPENC (2,5,C8,C0,0), 0),
-+ SR_CORE ("csrptr_el1", CPENC (2,0,C8,C0,1), 0),
-+ SR_CORE ("csrptr_el12", CPENC (2,5,C8,C0,1), 0),
-+ SR_CORE ("csrptridx_el1", CPENC (2,0,C8,C0,3), F_REG_READ),
-+ SR_CORE ("csrcr_el2", CPENC (2,4,C8,C0,0), 0),
-+ SR_CORE ("csrptr_el2", CPENC (2,4,C8,C0,1), 0),
-+ SR_CORE ("csrptridx_el2", CPENC (2,4,C8,C0,3), F_REG_READ),
-+
-+ SR_CORE ("lorc_el1", CPENC (3,0,C10,C4,3), 0),
-+ SR_CORE ("lorea_el1", CPENC (3,0,C10,C4,1), 0),
-+ SR_CORE ("lorn_el1", CPENC (3,0,C10,C4,2), 0),
-+ SR_CORE ("lorsa_el1", CPENC (3,0,C10,C4,0), 0),
-+ SR_CORE ("icc_ctlr_el3", CPENC (3,6,C12,C12,4), 0),
-+ SR_CORE ("icc_sre_el1", CPENC (3,0,C12,C12,5), 0),
-+ SR_CORE ("icc_sre_el2", CPENC (3,4,C12,C9,5), 0),
-+ SR_CORE ("icc_sre_el3", CPENC (3,6,C12,C12,5), 0),
-+ SR_CORE ("ich_vtr_el2", CPENC (3,4,C12,C11,1), F_REG_READ),
-+
-+ SR_CORE ("brbcr_el1", CPENC (2,1,C9,C0,0), 0),
-+ SR_CORE ("brbcr_el12", CPENC (2,5,C9,C0,0), 0),
-+ SR_CORE ("brbfcr_el1", CPENC (2,1,C9,C0,1), 0),
-+ SR_CORE ("brbts_el1", CPENC (2,1,C9,C0,2), 0),
-+ SR_CORE ("brbinfinj_el1", CPENC (2,1,C9,C1,0), 0),
-+ SR_CORE ("brbsrcinj_el1", CPENC (2,1,C9,C1,1), 0),
-+ SR_CORE ("brbtgtinj_el1", CPENC (2,1,C9,C1,2), 0),
-+ SR_CORE ("brbidr0_el1", CPENC (2,1,C9,C2,0), F_REG_READ),
-+ SR_CORE ("brbcr_el2", CPENC (2,4,C9,C0,0), 0),
-+ SR_CORE ("brbsrc0_el1", CPENC (2,1,C8,C0,1), F_REG_READ),
-+ SR_CORE ("brbsrc1_el1", CPENC (2,1,C8,C1,1), F_REG_READ),
-+ SR_CORE ("brbsrc2_el1", CPENC (2,1,C8,C2,1), F_REG_READ),
-+ SR_CORE ("brbsrc3_el1", CPENC (2,1,C8,C3,1), F_REG_READ),
-+ SR_CORE ("brbsrc4_el1", CPENC (2,1,C8,C4,1), F_REG_READ),
-+ SR_CORE ("brbsrc5_el1", CPENC (2,1,C8,C5,1), F_REG_READ),
-+ SR_CORE ("brbsrc6_el1", CPENC (2,1,C8,C6,1), F_REG_READ),
-+ SR_CORE ("brbsrc7_el1", CPENC (2,1,C8,C7,1), F_REG_READ),
-+ SR_CORE ("brbsrc8_el1", CPENC (2,1,C8,C8,1), F_REG_READ),
-+ SR_CORE ("brbsrc9_el1", CPENC (2,1,C8,C9,1), F_REG_READ),
-+ SR_CORE ("brbsrc10_el1", CPENC (2,1,C8,C10,1), F_REG_READ),
-+ SR_CORE ("brbsrc11_el1", CPENC (2,1,C8,C11,1), F_REG_READ),
-+ SR_CORE ("brbsrc12_el1", CPENC (2,1,C8,C12,1), F_REG_READ),
-+ SR_CORE ("brbsrc13_el1", CPENC (2,1,C8,C13,1), F_REG_READ),
-+ SR_CORE ("brbsrc14_el1", CPENC (2,1,C8,C14,1), F_REG_READ),
-+ SR_CORE ("brbsrc15_el1", CPENC (2,1,C8,C15,1), F_REG_READ),
-+ SR_CORE ("brbsrc16_el1", CPENC (2,1,C8,C0,5), F_REG_READ),
-+ SR_CORE ("brbsrc17_el1", CPENC (2,1,C8,C1,5), F_REG_READ),
-+ SR_CORE ("brbsrc18_el1", CPENC (2,1,C8,C2,5), F_REG_READ),
-+ SR_CORE ("brbsrc19_el1", CPENC (2,1,C8,C3,5), F_REG_READ),
-+ SR_CORE ("brbsrc20_el1", CPENC (2,1,C8,C4,5), F_REG_READ),
-+ SR_CORE ("brbsrc21_el1", CPENC (2,1,C8,C5,5), F_REG_READ),
-+ SR_CORE ("brbsrc22_el1", CPENC (2,1,C8,C6,5), F_REG_READ),
-+ SR_CORE ("brbsrc23_el1", CPENC (2,1,C8,C7,5), F_REG_READ),
-+ SR_CORE ("brbsrc24_el1", CPENC (2,1,C8,C8,5), F_REG_READ),
-+ SR_CORE ("brbsrc25_el1", CPENC (2,1,C8,C9,5), F_REG_READ),
-+ SR_CORE ("brbsrc26_el1", CPENC (2,1,C8,C10,5), F_REG_READ),
-+ SR_CORE ("brbsrc27_el1", CPENC (2,1,C8,C11,5), F_REG_READ),
-+ SR_CORE ("brbsrc28_el1", CPENC (2,1,C8,C12,5), F_REG_READ),
-+ SR_CORE ("brbsrc29_el1", CPENC (2,1,C8,C13,5), F_REG_READ),
-+ SR_CORE ("brbsrc30_el1", CPENC (2,1,C8,C14,5), F_REG_READ),
-+ SR_CORE ("brbsrc31_el1", CPENC (2,1,C8,C15,5), F_REG_READ),
-+ SR_CORE ("brbtgt0_el1", CPENC (2,1,C8,C0,2), F_REG_READ),
-+ SR_CORE ("brbtgt1_el1", CPENC (2,1,C8,C1,2), F_REG_READ),
-+ SR_CORE ("brbtgt2_el1", CPENC (2,1,C8,C2,2), F_REG_READ),
-+ SR_CORE ("brbtgt3_el1", CPENC (2,1,C8,C3,2), F_REG_READ),
-+ SR_CORE ("brbtgt4_el1", CPENC (2,1,C8,C4,2), F_REG_READ),
-+ SR_CORE ("brbtgt5_el1", CPENC (2,1,C8,C5,2), F_REG_READ),
-+ SR_CORE ("brbtgt6_el1", CPENC (2,1,C8,C6,2), F_REG_READ),
-+ SR_CORE ("brbtgt7_el1", CPENC (2,1,C8,C7,2), F_REG_READ),
-+ SR_CORE ("brbtgt8_el1", CPENC (2,1,C8,C8,2), F_REG_READ),
-+ SR_CORE ("brbtgt9_el1", CPENC (2,1,C8,C9,2), F_REG_READ),
-+ SR_CORE ("brbtgt10_el1", CPENC (2,1,C8,C10,2), F_REG_READ),
-+ SR_CORE ("brbtgt11_el1", CPENC (2,1,C8,C11,2), F_REG_READ),
-+ SR_CORE ("brbtgt12_el1", CPENC (2,1,C8,C12,2), F_REG_READ),
-+ SR_CORE ("brbtgt13_el1", CPENC (2,1,C8,C13,2), F_REG_READ),
-+ SR_CORE ("brbtgt14_el1", CPENC (2,1,C8,C14,2), F_REG_READ),
-+ SR_CORE ("brbtgt15_el1", CPENC (2,1,C8,C15,2), F_REG_READ),
-+ SR_CORE ("brbtgt16_el1", CPENC (2,1,C8,C0,6), F_REG_READ),
-+ SR_CORE ("brbtgt17_el1", CPENC (2,1,C8,C1,6), F_REG_READ),
-+ SR_CORE ("brbtgt18_el1", CPENC (2,1,C8,C2,6), F_REG_READ),
-+ SR_CORE ("brbtgt19_el1", CPENC (2,1,C8,C3,6), F_REG_READ),
-+ SR_CORE ("brbtgt20_el1", CPENC (2,1,C8,C4,6), F_REG_READ),
-+ SR_CORE ("brbtgt21_el1", CPENC (2,1,C8,C5,6), F_REG_READ),
-+ SR_CORE ("brbtgt22_el1", CPENC (2,1,C8,C6,6), F_REG_READ),
-+ SR_CORE ("brbtgt23_el1", CPENC (2,1,C8,C7,6), F_REG_READ),
-+ SR_CORE ("brbtgt24_el1", CPENC (2,1,C8,C8,6), F_REG_READ),
-+ SR_CORE ("brbtgt25_el1", CPENC (2,1,C8,C9,6), F_REG_READ),
-+ SR_CORE ("brbtgt26_el1", CPENC (2,1,C8,C10,6), F_REG_READ),
-+ SR_CORE ("brbtgt27_el1", CPENC (2,1,C8,C11,6), F_REG_READ),
-+ SR_CORE ("brbtgt28_el1", CPENC (2,1,C8,C12,6), F_REG_READ),
-+ SR_CORE ("brbtgt29_el1", CPENC (2,1,C8,C13,6), F_REG_READ),
-+ SR_CORE ("brbtgt30_el1", CPENC (2,1,C8,C14,6), F_REG_READ),
-+ SR_CORE ("brbtgt31_el1", CPENC (2,1,C8,C15,6), F_REG_READ),
-+ SR_CORE ("brbinf0_el1", CPENC (2,1,C8,C0,0), F_REG_READ),
-+ SR_CORE ("brbinf1_el1", CPENC (2,1,C8,C1,0), F_REG_READ),
-+ SR_CORE ("brbinf2_el1", CPENC (2,1,C8,C2,0), F_REG_READ),
-+ SR_CORE ("brbinf3_el1", CPENC (2,1,C8,C3,0), F_REG_READ),
-+ SR_CORE ("brbinf4_el1", CPENC (2,1,C8,C4,0), F_REG_READ),
-+ SR_CORE ("brbinf5_el1", CPENC (2,1,C8,C5,0), F_REG_READ),
-+ SR_CORE ("brbinf6_el1", CPENC (2,1,C8,C6,0), F_REG_READ),
-+ SR_CORE ("brbinf7_el1", CPENC (2,1,C8,C7,0), F_REG_READ),
-+ SR_CORE ("brbinf8_el1", CPENC (2,1,C8,C8,0), F_REG_READ),
-+ SR_CORE ("brbinf9_el1", CPENC (2,1,C8,C9,0), F_REG_READ),
-+ SR_CORE ("brbinf10_el1", CPENC (2,1,C8,C10,0), F_REG_READ),
-+ SR_CORE ("brbinf11_el1", CPENC (2,1,C8,C11,0), F_REG_READ),
-+ SR_CORE ("brbinf12_el1", CPENC (2,1,C8,C12,0), F_REG_READ),
-+ SR_CORE ("brbinf13_el1", CPENC (2,1,C8,C13,0), F_REG_READ),
-+ SR_CORE ("brbinf14_el1", CPENC (2,1,C8,C14,0), F_REG_READ),
-+ SR_CORE ("brbinf15_el1", CPENC (2,1,C8,C15,0), F_REG_READ),
-+ SR_CORE ("brbinf16_el1", CPENC (2,1,C8,C0,4), F_REG_READ),
-+ SR_CORE ("brbinf17_el1", CPENC (2,1,C8,C1,4), F_REG_READ),
-+ SR_CORE ("brbinf18_el1", CPENC (2,1,C8,C2,4), F_REG_READ),
-+ SR_CORE ("brbinf19_el1", CPENC (2,1,C8,C3,4), F_REG_READ),
-+ SR_CORE ("brbinf20_el1", CPENC (2,1,C8,C4,4), F_REG_READ),
-+ SR_CORE ("brbinf21_el1", CPENC (2,1,C8,C5,4), F_REG_READ),
-+ SR_CORE ("brbinf22_el1", CPENC (2,1,C8,C6,4), F_REG_READ),
-+ SR_CORE ("brbinf23_el1", CPENC (2,1,C8,C7,4), F_REG_READ),
-+ SR_CORE ("brbinf24_el1", CPENC (2,1,C8,C8,4), F_REG_READ),
-+ SR_CORE ("brbinf25_el1", CPENC (2,1,C8,C9,4), F_REG_READ),
-+ SR_CORE ("brbinf26_el1", CPENC (2,1,C8,C10,4), F_REG_READ),
-+ SR_CORE ("brbinf27_el1", CPENC (2,1,C8,C11,4), F_REG_READ),
-+ SR_CORE ("brbinf28_el1", CPENC (2,1,C8,C12,4), F_REG_READ),
-+ SR_CORE ("brbinf29_el1", CPENC (2,1,C8,C13,4), F_REG_READ),
-+ SR_CORE ("brbinf30_el1", CPENC (2,1,C8,C14,4), F_REG_READ),
-+ SR_CORE ("brbinf31_el1", CPENC (2,1,C8,C15,4), F_REG_READ),
-+
-+ SR_CORE ("accdata_el1", CPENC (3,0,C13,C0,5), 0),
-+
-+ { 0, CPENC (0,0,0,0,0), 0, 0 }
- };
-
- bfd_boolean
--aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *reg)
-+aarch64_sys_reg_deprecated_p (const uint32_t reg_flags)
- {
-- return (reg->flags & F_DEPRECATED) != 0;
--}
--
--bfd_boolean
--aarch64_sys_reg_supported_p (const aarch64_feature_set features,
-- const aarch64_sys_reg *reg)
--{
-- if (!(reg->flags & F_ARCHEXT))
-- return TRUE;
--
-- /* PAN. Values are from aarch64_sys_regs. */
-- if (reg->value == CPEN_(0,C2,3)
-- && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_PAN))
-- return FALSE;
--
-- /* Virtualization host extensions: system registers. */
-- if ((reg->value == CPENC (3, 4, C2, C0, 1)
-- || reg->value == CPENC (3, 4, C13, C0, 1)
-- || reg->value == CPENC (3, 4, C14, C3, 0)
-- || reg->value == CPENC (3, 4, C14, C3, 1)
-- || reg->value == CPENC (3, 4, C14, C3, 2))
-- && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_1))
-- return FALSE;
--
-- /* Virtualization host extensions: *_el12 names of *_el1 registers. */
-- if ((reg->value == CPEN_ (5, C0, 0)
-- || reg->value == CPEN_ (5, C0, 1)
-- || reg->value == CPENC (3, 5, C1, C0, 0)
-- || reg->value == CPENC (3, 5, C1, C0, 2)
-- || reg->value == CPENC (3, 5, C2, C0, 0)
-- || reg->value == CPENC (3, 5, C2, C0, 1)
-- || reg->value == CPENC (3, 5, C2, C0, 2)
-- || reg->value == CPENC (3, 5, C5, C1, 0)
-- || reg->value == CPENC (3, 5, C5, C1, 1)
-- || reg->value == CPENC (3, 5, C5, C2, 0)
-- || reg->value == CPENC (3, 5, C6, C0, 0)
-- || reg->value == CPENC (3, 5, C10, C2, 0)
-- || reg->value == CPENC (3, 5, C10, C3, 0)
-- || reg->value == CPENC (3, 5, C12, C0, 0)
-- || reg->value == CPENC (3, 5, C13, C0, 1)
-- || reg->value == CPENC (3, 5, C14, C1, 0))
-- && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_1))
-- return FALSE;
--
-- /* Virtualization host extensions: *_el02 names of *_el0 registers. */
-- if ((reg->value == CPENC (3, 5, C14, C2, 0)
-- || reg->value == CPENC (3, 5, C14, C2, 1)
-- || reg->value == CPENC (3, 5, C14, C2, 2)
-- || reg->value == CPENC (3, 5, C14, C3, 0)
-- || reg->value == CPENC (3, 5, C14, C3, 1)
-- || reg->value == CPENC (3, 5, C14, C3, 2))
-- && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_1))
-- return FALSE;
--
-- /* ARMv8.2 features. */
--
-- /* ID_AA64MMFR2_EL1. */
-- if (reg->value == CPENC (3, 0, C0, C7, 2)
-- && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
-- return FALSE;
--
-- /* PSTATE.UAO. */
-- if (reg->value == CPEN_ (0, C2, 4)
-- && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
-- return FALSE;
--
-- /* RAS extension. */
--
-- /* ERRIDR_EL1, ERRSELR_EL1, ERXFR_EL1, ERXCTLR_EL1, ERXSTATUS_EL, ERXADDR_EL1,
-- ERXMISC0_EL1 AND ERXMISC1_EL1. */
-- if ((reg->value == CPENC (3, 0, C5, C3, 0)
-- || reg->value == CPENC (3, 0, C5, C3, 1)
-- || reg->value == CPENC (3, 0, C5, C3, 2)
-- || reg->value == CPENC (3, 0, C5, C3, 3)
-- || reg->value == CPENC (3, 0, C5, C4, 0)
-- || reg->value == CPENC (3, 0, C5, C4, 1)
-- || reg->value == CPENC (3, 0, C5, C4, 2)
-- || reg->value == CPENC (3, 0, C5, C4, 3)
-- || reg->value == CPENC (3, 0, C5, C5, 0)
-- || reg->value == CPENC (3, 0, C5, C5, 1))
-- && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_RAS))
-- return FALSE;
--
-- /* VSESR_EL2, DISR_EL1 and VDISR_EL2. */
-- if ((reg->value == CPENC (3, 4, C5, C2, 3)
-- || reg->value == CPENC (3, 0, C12, C1, 1)
-- || reg->value == CPENC (3, 4, C12, C1, 1))
-- && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_RAS))
-- return FALSE;
--
-- /* Statistical Profiling extension. */
-- if ((reg->value == CPENC (3, 0, C9, C10, 0)
-- || reg->value == CPENC (3, 0, C9, C10, 1)
-- || reg->value == CPENC (3, 0, C9, C10, 3)
-- || reg->value == CPENC (3, 0, C9, C10, 7)
-- || reg->value == CPENC (3, 0, C9, C9, 0)
-- || reg->value == CPENC (3, 0, C9, C9, 2)
-- || reg->value == CPENC (3, 0, C9, C9, 3)
-- || reg->value == CPENC (3, 0, C9, C9, 4)
-- || reg->value == CPENC (3, 0, C9, C9, 5)
-- || reg->value == CPENC (3, 0, C9, C9, 6)
-- || reg->value == CPENC (3, 0, C9, C9, 7)
-- || reg->value == CPENC (3, 4, C9, C9, 0)
-- || reg->value == CPENC (3, 5, C9, C9, 0))
-- && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_PROFILE))
-- return FALSE;
--
-- /* ARMv8.3 Pointer authentication keys. */
-- if ((reg->value == CPENC (3, 0, C2, C1, 0)
-- || reg->value == CPENC (3, 0, C2, C1, 1)
-- || reg->value == CPENC (3, 0, C2, C1, 2)
-- || reg->value == CPENC (3, 0, C2, C1, 3)
-- || reg->value == CPENC (3, 0, C2, C2, 0)
-- || reg->value == CPENC (3, 0, C2, C2, 1)
-- || reg->value == CPENC (3, 0, C2, C2, 2)
-- || reg->value == CPENC (3, 0, C2, C2, 3)
-- || reg->value == CPENC (3, 0, C2, C3, 0)
-- || reg->value == CPENC (3, 0, C2, C3, 1))
-- && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_3))
-- return FALSE;
--
-- /* SVE. */
-- if ((reg->value == CPENC (3, 0, C0, C4, 4)
-- || reg->value == CPENC (3, 0, C1, C2, 0)
-- || reg->value == CPENC (3, 4, C1, C2, 0)
-- || reg->value == CPENC (3, 6, C1, C2, 0)
-- || reg->value == CPENC (3, 5, C1, C2, 0)
-- || reg->value == CPENC (3, 0, C0, C0, 7))
-- && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_SVE))
-- return FALSE;
--
-- /* ARMv8.4 features. */
--
-- /* PSTATE.DIT. */
-- if (reg->value == CPEN_ (3, C2, 5)
-- && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_4))
-- return FALSE;
--
-- /* Virtualization extensions. */
-- if ((reg->value == CPENC(3, 4, C2, C6, 2)
-- || reg->value == CPENC(3, 4, C2, C6, 0)
-- || reg->value == CPENC(3, 4, C14, C4, 0)
-- || reg->value == CPENC(3, 4, C14, C4, 2)
-- || reg->value == CPENC(3, 4, C14, C4, 1)
-- || reg->value == CPENC(3, 4, C14, C5, 0)
-- || reg->value == CPENC(3, 4, C14, C5, 2)
-- || reg->value == CPENC(3, 4, C14, C5, 1)
-- || reg->value == CPENC(3, 4, C1, C3, 1)
-- || reg->value == CPENC(3, 4, C2, C2, 0))
-- && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_4))
-- return FALSE;
--
-- /* ARMv8.4 TLB instructions. */
-- if ((reg->value == CPENS (0, C8, C1, 0)
-- || reg->value == CPENS (0, C8, C1, 1)
-- || reg->value == CPENS (0, C8, C1, 2)
-- || reg->value == CPENS (0, C8, C1, 3)
-- || reg->value == CPENS (0, C8, C1, 5)
-- || reg->value == CPENS (0, C8, C1, 7)
-- || reg->value == CPENS (4, C8, C4, 0)
-- || reg->value == CPENS (4, C8, C4, 4)
-- || reg->value == CPENS (4, C8, C1, 1)
-- || reg->value == CPENS (4, C8, C1, 5)
-- || reg->value == CPENS (4, C8, C1, 6)
-- || reg->value == CPENS (6, C8, C1, 1)
-- || reg->value == CPENS (6, C8, C1, 5)
-- || reg->value == CPENS (4, C8, C1, 0)
-- || reg->value == CPENS (4, C8, C1, 4)
-- || reg->value == CPENS (6, C8, C1, 0)
-- || reg->value == CPENS (0, C8, C6, 1)
-- || reg->value == CPENS (0, C8, C6, 3)
-- || reg->value == CPENS (0, C8, C6, 5)
-- || reg->value == CPENS (0, C8, C6, 7)
-- || reg->value == CPENS (0, C8, C2, 1)
-- || reg->value == CPENS (0, C8, C2, 3)
-- || reg->value == CPENS (0, C8, C2, 5)
-- || reg->value == CPENS (0, C8, C2, 7)
-- || reg->value == CPENS (0, C8, C5, 1)
-- || reg->value == CPENS (0, C8, C5, 3)
-- || reg->value == CPENS (0, C8, C5, 5)
-- || reg->value == CPENS (0, C8, C5, 7)
-- || reg->value == CPENS (4, C8, C0, 2)
-- || reg->value == CPENS (4, C8, C0, 6)
-- || reg->value == CPENS (4, C8, C4, 2)
-- || reg->value == CPENS (4, C8, C4, 6)
-- || reg->value == CPENS (4, C8, C4, 3)
-- || reg->value == CPENS (4, C8, C4, 7)
-- || reg->value == CPENS (4, C8, C6, 1)
-- || reg->value == CPENS (4, C8, C6, 5)
-- || reg->value == CPENS (4, C8, C2, 1)
-- || reg->value == CPENS (4, C8, C2, 5)
-- || reg->value == CPENS (4, C8, C5, 1)
-- || reg->value == CPENS (4, C8, C5, 5)
-- || reg->value == CPENS (6, C8, C6, 1)
-- || reg->value == CPENS (6, C8, C6, 5)
-- || reg->value == CPENS (6, C8, C2, 1)
-- || reg->value == CPENS (6, C8, C2, 5)
-- || reg->value == CPENS (6, C8, C5, 1)
-- || reg->value == CPENS (6, C8, C5, 5))
-- && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_4))
-- return FALSE;
--
-- return TRUE;
-+ return (reg_flags & F_DEPRECATED) != 0;
- }
-
- /* The CPENC below is fairly misleading, the fields
-@@ -4266,13 +4706,15 @@ aarch64_sys_reg_supported_p (const aarch
- 0b011010 (0x1a). */
- const aarch64_sys_reg aarch64_pstatefields [] =
- {
-- { "spsel", 0x05, 0 },
-- { "daifset", 0x1e, 0 },
-- { "daifclr", 0x1f, 0 },
-- { "pan", 0x04, F_ARCHEXT },
-- { "uao", 0x03, F_ARCHEXT },
-- { "dit", 0x1a, F_ARCHEXT },
-- { 0, CPENC(0,0,0,0,0), 0 },
-+ SR_CORE ("spsel", 0x05, 0),
-+ SR_CORE ("daifset", 0x1e, 0),
-+ SR_CORE ("daifclr", 0x1f, 0),
-+ SR_PAN ("pan", 0x04, 0),
-+ SR_V8_2 ("uao", 0x03, 0),
-+ SR_SSBS ("ssbs", 0x19, 0),
-+ SR_V8_4 ("dit", 0x1a, 0),
-+ SR_MEMTAG ("tco", 0x1c, 0),
-+ { 0, CPENC (0,0,0,0,0), 0, 0 },
- };
-
- bfd_boolean
-@@ -4282,22 +4724,7 @@ aarch64_pstatefield_supported_p (const a
- if (!(reg->flags & F_ARCHEXT))
- return TRUE;
-
-- /* PAN. Values are from aarch64_pstatefields. */
-- if (reg->value == 0x04
-- && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_PAN))
-- return FALSE;
--
-- /* UAO. Values are from aarch64_pstatefields. */
-- if (reg->value == 0x03
-- && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
-- return FALSE;
--
-- /* DIT. Values are from aarch64_pstatefields. */
-- if (reg->value == 0x1a
-- && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_4))
-- return FALSE;
--
-- return TRUE;
-+ return AARCH64_CPU_HAS_ALL_FEATURES (features, reg->features);
- }
-
- const aarch64_sys_ins_reg aarch64_sys_regs_ic[] =
-@@ -4311,14 +4738,33 @@ const aarch64_sys_ins_reg aarch64_sys_re
- const aarch64_sys_ins_reg aarch64_sys_regs_dc[] =
- {
- { "zva", CPENS (3, C7, C4, 1), F_HASXT },
-+ { "gva", CPENS (3, C7, C4, 3), F_HASXT | F_ARCHEXT },
-+ { "gzva", CPENS (3, C7, C4, 4), F_HASXT | F_ARCHEXT },
- { "ivac", CPENS (0, C7, C6, 1), F_HASXT },
-+ { "igvac", CPENS (0, C7, C6, 3), F_HASXT | F_ARCHEXT },
-+ { "igsw", CPENS (0, C7, C6, 4), F_HASXT | F_ARCHEXT },
- { "isw", CPENS (0, C7, C6, 2), F_HASXT },
-+ { "igdvac", CPENS (0, C7, C6, 5), F_HASXT | F_ARCHEXT },
-+ { "igdsw", CPENS (0, C7, C6, 6), F_HASXT | F_ARCHEXT },
- { "cvac", CPENS (3, C7, C10, 1), F_HASXT },
-+ { "cgvac", CPENS (3, C7, C10, 3), F_HASXT | F_ARCHEXT },
-+ { "cgdvac", CPENS (3, C7, C10, 5), F_HASXT | F_ARCHEXT },
- { "csw", CPENS (0, C7, C10, 2), F_HASXT },
-+ { "cgsw", CPENS (0, C7, C10, 4), F_HASXT | F_ARCHEXT },
-+ { "cgdsw", CPENS (0, C7, C10, 6), F_HASXT | F_ARCHEXT },
- { "cvau", CPENS (3, C7, C11, 1), F_HASXT },
- { "cvap", CPENS (3, C7, C12, 1), F_HASXT | F_ARCHEXT },
-+ { "cgvap", CPENS (3, C7, C12, 3), F_HASXT | F_ARCHEXT },
-+ { "cgdvap", CPENS (3, C7, C12, 5), F_HASXT | F_ARCHEXT },
-+ { "cvadp", CPENS (3, C7, C13, 1), F_HASXT | F_ARCHEXT },
-+ { "cgvadp", CPENS (3, C7, C13, 3), F_HASXT | F_ARCHEXT },
-+ { "cgdvadp", CPENS (3, C7, C13, 5), F_HASXT | F_ARCHEXT },
- { "civac", CPENS (3, C7, C14, 1), F_HASXT },
-+ { "cigvac", CPENS (3, C7, C14, 3), F_HASXT | F_ARCHEXT },
-+ { "cigdvac", CPENS (3, C7, C14, 5), F_HASXT | F_ARCHEXT },
- { "cisw", CPENS (0, C7, C14, 2), F_HASXT },
-+ { "cigsw", CPENS (0, C7, C14, 4), F_HASXT | F_ARCHEXT },
-+ { "cigdsw", CPENS (0, C7, C14, 6), F_HASXT | F_ARCHEXT },
- { 0, CPENS(0,0,0,0), 0 }
- };
-
-@@ -4427,6 +4873,17 @@ const aarch64_sys_ins_reg aarch64_sys_re
- { 0, CPENS(0,0,0,0), 0 }
- };
-
-+const aarch64_sys_ins_reg aarch64_sys_regs_sr[] =
-+{
-+ /* RCTX is somewhat unique in a way that it has different values
-+ (op2) based on the instruction in which it is used (cfp/dvp/cpp).
-+ Thus op2 is masked out and instead encoded directly in the
-+ aarch64_opcode_table entries for the respective instructions. */
-+ { "rctx", CPENS(3,C7,C3,0), F_HASXT | F_ARCHEXT | F_REG_WRITE}, /* WO */
-+
-+ { 0, CPENS(0,0,0,0), 0 }
-+};
-+
- bfd_boolean
- aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *sys_ins_reg)
- {
-@@ -4435,23 +4892,120 @@ aarch64_sys_ins_reg_has_xt (const aarch6
-
- extern bfd_boolean
- aarch64_sys_ins_reg_supported_p (const aarch64_feature_set features,
-- const aarch64_sys_ins_reg *reg)
-+ const char *reg_name,
-+ aarch64_insn reg_value,
-+ uint32_t reg_flags,
-+ aarch64_feature_set reg_features)
- {
-- if (!(reg->flags & F_ARCHEXT))
-+ /* Armv8-R has no EL3. */
-+ if (AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_R))
-+ {
-+ const char *suffix = strrchr (reg_name, '_');
-+ if (suffix && !strcmp (suffix, "_el3"))
-+ return FALSE;
-+ }
-+
-+ if (!(reg_flags & F_ARCHEXT))
-+ return TRUE;
-+
-+ if (reg_features
-+ && AARCH64_CPU_HAS_ALL_FEATURES (features, reg_features))
-+ return TRUE;
-+
-+ /* ARMv8.4 TLB instructions. */
-+ if ((reg_value == CPENS (0, C8, C1, 0)
-+ || reg_value == CPENS (0, C8, C1, 1)
-+ || reg_value == CPENS (0, C8, C1, 2)
-+ || reg_value == CPENS (0, C8, C1, 3)
-+ || reg_value == CPENS (0, C8, C1, 5)
-+ || reg_value == CPENS (0, C8, C1, 7)
-+ || reg_value == CPENS (4, C8, C4, 0)
-+ || reg_value == CPENS (4, C8, C4, 4)
-+ || reg_value == CPENS (4, C8, C1, 1)
-+ || reg_value == CPENS (4, C8, C1, 5)
-+ || reg_value == CPENS (4, C8, C1, 6)
-+ || reg_value == CPENS (6, C8, C1, 1)
-+ || reg_value == CPENS (6, C8, C1, 5)
-+ || reg_value == CPENS (4, C8, C1, 0)
-+ || reg_value == CPENS (4, C8, C1, 4)
-+ || reg_value == CPENS (6, C8, C1, 0)
-+ || reg_value == CPENS (0, C8, C6, 1)
-+ || reg_value == CPENS (0, C8, C6, 3)
-+ || reg_value == CPENS (0, C8, C6, 5)
-+ || reg_value == CPENS (0, C8, C6, 7)
-+ || reg_value == CPENS (0, C8, C2, 1)
-+ || reg_value == CPENS (0, C8, C2, 3)
-+ || reg_value == CPENS (0, C8, C2, 5)
-+ || reg_value == CPENS (0, C8, C2, 7)
-+ || reg_value == CPENS (0, C8, C5, 1)
-+ || reg_value == CPENS (0, C8, C5, 3)
-+ || reg_value == CPENS (0, C8, C5, 5)
-+ || reg_value == CPENS (0, C8, C5, 7)
-+ || reg_value == CPENS (4, C8, C0, 2)
-+ || reg_value == CPENS (4, C8, C0, 6)
-+ || reg_value == CPENS (4, C8, C4, 2)
-+ || reg_value == CPENS (4, C8, C4, 6)
-+ || reg_value == CPENS (4, C8, C4, 3)
-+ || reg_value == CPENS (4, C8, C4, 7)
-+ || reg_value == CPENS (4, C8, C6, 1)
-+ || reg_value == CPENS (4, C8, C6, 5)
-+ || reg_value == CPENS (4, C8, C2, 1)
-+ || reg_value == CPENS (4, C8, C2, 5)
-+ || reg_value == CPENS (4, C8, C5, 1)
-+ || reg_value == CPENS (4, C8, C5, 5)
-+ || reg_value == CPENS (6, C8, C6, 1)
-+ || reg_value == CPENS (6, C8, C6, 5)
-+ || reg_value == CPENS (6, C8, C2, 1)
-+ || reg_value == CPENS (6, C8, C2, 5)
-+ || reg_value == CPENS (6, C8, C5, 1)
-+ || reg_value == CPENS (6, C8, C5, 5))
-+ && AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_4))
- return TRUE;
-
- /* DC CVAP. Values are from aarch64_sys_regs_dc. */
-- if (reg->value == CPENS (3, C7, C12, 1)
-- && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
-- return FALSE;
-+ if (reg_value == CPENS (3, C7, C12, 1)
-+ && AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
-+ return TRUE;
-+
-+ /* DC CVADP. Values are from aarch64_sys_regs_dc. */
-+ if (reg_value == CPENS (3, C7, C13, 1)
-+ && AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_CVADP))
-+ return TRUE;
-+
-+ /* DC <dc_op> for ARMv8.5-A Memory Tagging Extension. */
-+ if ((reg_value == CPENS (0, C7, C6, 3)
-+ || reg_value == CPENS (0, C7, C6, 4)
-+ || reg_value == CPENS (0, C7, C10, 4)
-+ || reg_value == CPENS (0, C7, C14, 4)
-+ || reg_value == CPENS (3, C7, C10, 3)
-+ || reg_value == CPENS (3, C7, C12, 3)
-+ || reg_value == CPENS (3, C7, C13, 3)
-+ || reg_value == CPENS (3, C7, C14, 3)
-+ || reg_value == CPENS (3, C7, C4, 3)
-+ || reg_value == CPENS (0, C7, C6, 5)
-+ || reg_value == CPENS (0, C7, C6, 6)
-+ || reg_value == CPENS (0, C7, C10, 6)
-+ || reg_value == CPENS (0, C7, C14, 6)
-+ || reg_value == CPENS (3, C7, C10, 5)
-+ || reg_value == CPENS (3, C7, C12, 5)
-+ || reg_value == CPENS (3, C7, C13, 5)
-+ || reg_value == CPENS (3, C7, C14, 5)
-+ || reg_value == CPENS (3, C7, C4, 4))
-+ && AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_MEMTAG))
-+ return TRUE;
-
- /* AT S1E1RP, AT S1E1WP. Values are from aarch64_sys_regs_at. */
-- if ((reg->value == CPENS (0, C7, C9, 0)
-- || reg->value == CPENS (0, C7, C9, 1))
-- && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
-- return FALSE;
-+ if ((reg_value == CPENS (0, C7, C9, 0)
-+ || reg_value == CPENS (0, C7, C9, 1))
-+ && AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
-+ return TRUE;
-
-- return TRUE;
-+ /* CFP/DVP/CPP RCTX : Value are from aarch64_sys_regs_sr. */
-+ if (reg_value == CPENS (3, C7, C3, 0)
-+ && AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_PREDRES))
-+ return TRUE;
-+
-+ return FALSE;
- }
-
- #undef C0
-@@ -4474,9 +5028,12 @@ aarch64_sys_ins_reg_supported_p (const a
- #define BIT(INSN,BT) (((INSN) >> (BT)) & 1)
- #define BITS(INSN,HI,LO) (((INSN) >> (LO)) & ((1 << (((HI) - (LO)) + 1)) - 1))
-
--static bfd_boolean
--verify_ldpsw (const struct aarch64_opcode * opcode ATTRIBUTE_UNUSED,
-- const aarch64_insn insn)
-+static enum err_type
-+verify_ldpsw (const struct aarch64_inst *inst ATTRIBUTE_UNUSED,
-+ const aarch64_insn insn, bfd_vma pc ATTRIBUTE_UNUSED,
-+ bfd_boolean encoding ATTRIBUTE_UNUSED,
-+ aarch64_operand_error *mismatch_detail ATTRIBUTE_UNUSED,
-+ aarch64_instr_sequence *insn_sequence ATTRIBUTE_UNUSED)
- {
- int t = BITS (insn, 4, 0);
- int n = BITS (insn, 9, 5);
-@@ -4486,19 +5043,370 @@ verify_ldpsw (const struct aarch64_opcod
- {
- /* Write back enabled. */
- if ((t == n || t2 == n) && n != 31)
-- return FALSE;
-+ return ERR_UND;
- }
-
- if (BIT (insn, 22))
- {
- /* Load */
- if (t == t2)
-- return FALSE;
-+ return ERR_UND;
- }
-
-- return TRUE;
-+ return ERR_OK;
- }
-
-+/* Verifier for vector by element 3 operands functions where the
-+ conditions `if sz:L == 11 then UNDEFINED` holds. */
-+
-+static enum err_type
-+verify_elem_sd (const struct aarch64_inst *inst, const aarch64_insn insn,
-+ bfd_vma pc ATTRIBUTE_UNUSED, bfd_boolean encoding,
-+ aarch64_operand_error *mismatch_detail ATTRIBUTE_UNUSED,
-+ aarch64_instr_sequence *insn_sequence ATTRIBUTE_UNUSED)
-+{
-+ const aarch64_insn undef_pattern = 0x3;
-+ aarch64_insn value;
-+
-+ assert (inst->opcode);
-+ assert (inst->opcode->operands[2] == AARCH64_OPND_Em);
-+ value = encoding ? inst->value : insn;
-+ assert (value);
-+
-+ if (undef_pattern == extract_fields (value, 0, 2, FLD_sz, FLD_L))
-+ return ERR_UND;
-+
-+ return ERR_OK;
-+}
-+
-+/* Initialize an instruction sequence insn_sequence with the instruction INST.
-+ If INST is NULL the given insn_sequence is cleared and the sequence is left
-+ uninitialized. */
-+
-+void
-+init_insn_sequence (const struct aarch64_inst *inst,
-+ aarch64_instr_sequence *insn_sequence)
-+{
-+ int num_req_entries = 0;
-+ insn_sequence->next_insn = 0;
-+ insn_sequence->num_insns = num_req_entries;
-+ if (insn_sequence->instr)
-+ XDELETE (insn_sequence->instr);
-+ insn_sequence->instr = NULL;
-+
-+ if (inst)
-+ {
-+ insn_sequence->instr = XNEW (aarch64_inst);
-+ memcpy (insn_sequence->instr, inst, sizeof (aarch64_inst));
-+ }
-+
-+ /* Handle all the cases here. May need to think of something smarter than
-+ a giant if/else chain if this grows. At that time, a lookup table may be
-+ best. */
-+ if (inst && inst->opcode->constraints & C_SCAN_MOVPRFX)
-+ num_req_entries = 1;
-+
-+ if (insn_sequence->current_insns)
-+ XDELETEVEC (insn_sequence->current_insns);
-+ insn_sequence->current_insns = NULL;
-+
-+ if (num_req_entries != 0)
-+ {
-+ size_t size = num_req_entries * sizeof (aarch64_inst);
-+ insn_sequence->current_insns
-+ = (aarch64_inst**) XNEWVEC (aarch64_inst, num_req_entries);
-+ memset (insn_sequence->current_insns, 0, size);
-+ }
-+}
-+
-+
-+/* This function verifies that the instruction INST adheres to its specified
-+ constraints. If it does then ERR_OK is returned, if not then ERR_VFI is
-+ returned and MISMATCH_DETAIL contains the reason why verification failed.
-+
-+ The function is called both during assembly and disassembly. If assembling
-+ then ENCODING will be TRUE, else FALSE. If dissassembling PC will be set
-+ and will contain the PC of the current instruction w.r.t to the section.
-+
-+ If ENCODING and PC=0 then you are at a start of a section. The constraints
-+ are verified against the given state insn_sequence which is updated as it
-+ transitions through the verification. */
-+
-+enum err_type
-+verify_constraints (const struct aarch64_inst *inst,
-+ const aarch64_insn insn ATTRIBUTE_UNUSED,
-+ bfd_vma pc,
-+ bfd_boolean encoding,
-+ aarch64_operand_error *mismatch_detail,
-+ aarch64_instr_sequence *insn_sequence)
-+{
-+ assert (inst);
-+ assert (inst->opcode);
-+
-+ const struct aarch64_opcode *opcode = inst->opcode;
-+ if (!opcode->constraints && !insn_sequence->instr)
-+ return ERR_OK;
-+
-+ assert (insn_sequence);
-+
-+ enum err_type res = ERR_OK;
-+
-+ /* This instruction puts a constraint on the insn_sequence. */
-+ if (opcode->flags & F_SCAN)
-+ {
-+ if (insn_sequence->instr)
-+ {
-+ mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
-+ mismatch_detail->error = _("instruction opens new dependency "
-+ "sequence without ending previous one");
-+ mismatch_detail->index = -1;
-+ mismatch_detail->non_fatal = TRUE;
-+ res = ERR_VFI;
-+ }
-+
-+ init_insn_sequence (inst, insn_sequence);
-+ return res;
-+ }
-+
-+ /* Verify constraints on an existing sequence. */
-+ if (insn_sequence->instr)
-+ {
-+ const struct aarch64_opcode* inst_opcode = insn_sequence->instr->opcode;
-+ /* If we're decoding and we hit PC=0 with an open sequence then we haven't
-+ closed a previous one that we should have. */
-+ if (!encoding && pc == 0)
-+ {
-+ mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
-+ mismatch_detail->error = _("previous `movprfx' sequence not closed");
-+ mismatch_detail->index = -1;
-+ mismatch_detail->non_fatal = TRUE;
-+ res = ERR_VFI;
-+ /* Reset the sequence. */
-+ init_insn_sequence (NULL, insn_sequence);
-+ return res;
-+ }
-+
-+ /* Validate C_SCAN_MOVPRFX constraints. Move this to a lookup table. */
-+ if (inst_opcode->constraints & C_SCAN_MOVPRFX)
-+ {
-+ /* Check to see if the MOVPRFX SVE instruction is followed by an SVE
-+ instruction for better error messages. */
-+ if (!opcode->avariant
-+ || !(*opcode->avariant &
-+ (AARCH64_FEATURE_SVE | AARCH64_FEATURE_SVE2)))
-+ {
-+ mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
-+ mismatch_detail->error = _("SVE instruction expected after "
-+ "`movprfx'");
-+ mismatch_detail->index = -1;
-+ mismatch_detail->non_fatal = TRUE;
-+ res = ERR_VFI;
-+ goto done;
-+ }
-+
-+ /* Check to see if the MOVPRFX SVE instruction is followed by an SVE
-+ instruction that is allowed to be used with a MOVPRFX. */
-+ if (!(opcode->constraints & C_SCAN_MOVPRFX))
-+ {
-+ mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
-+ mismatch_detail->error = _("SVE `movprfx' compatible instruction "
-+ "expected");
-+ mismatch_detail->index = -1;
-+ mismatch_detail->non_fatal = TRUE;
-+ res = ERR_VFI;
-+ goto done;
-+ }
-+
-+ /* Next check for usage of the predicate register. */
-+ aarch64_opnd_info blk_dest = insn_sequence->instr->operands[0];
-+ aarch64_opnd_info blk_pred, inst_pred;
-+ memset (&blk_pred, 0, sizeof (aarch64_opnd_info));
-+ memset (&inst_pred, 0, sizeof (aarch64_opnd_info));
-+ bfd_boolean predicated = FALSE;
-+ assert (blk_dest.type == AARCH64_OPND_SVE_Zd);
-+
-+ /* Determine if the movprfx instruction used is predicated or not. */
-+ if (insn_sequence->instr->operands[1].type == AARCH64_OPND_SVE_Pg3)
-+ {
-+ predicated = TRUE;
-+ blk_pred = insn_sequence->instr->operands[1];
-+ }
-+
-+ unsigned char max_elem_size = 0;
-+ unsigned char current_elem_size;
-+ int num_op_used = 0, last_op_usage = 0;
-+ int i, inst_pred_idx = -1;
-+ int num_ops = aarch64_num_of_operands (opcode);
-+ for (i = 0; i < num_ops; i++)
-+ {
-+ aarch64_opnd_info inst_op = inst->operands[i];
-+ switch (inst_op.type)
-+ {
-+ case AARCH64_OPND_SVE_Zd:
-+ case AARCH64_OPND_SVE_Zm_5:
-+ case AARCH64_OPND_SVE_Zm_16:
-+ case AARCH64_OPND_SVE_Zn:
-+ case AARCH64_OPND_SVE_Zt:
-+ case AARCH64_OPND_SVE_Vm:
-+ case AARCH64_OPND_SVE_Vn:
-+ case AARCH64_OPND_Va:
-+ case AARCH64_OPND_Vn:
-+ case AARCH64_OPND_Vm:
-+ case AARCH64_OPND_Sn:
-+ case AARCH64_OPND_Sm:
-+ if (inst_op.reg.regno == blk_dest.reg.regno)
-+ {
-+ num_op_used++;
-+ last_op_usage = i;
-+ }
-+ current_elem_size
-+ = aarch64_get_qualifier_esize (inst_op.qualifier);
-+ if (current_elem_size > max_elem_size)
-+ max_elem_size = current_elem_size;
-+ break;
-+ case AARCH64_OPND_SVE_Pd:
-+ case AARCH64_OPND_SVE_Pg3:
-+ case AARCH64_OPND_SVE_Pg4_5:
-+ case AARCH64_OPND_SVE_Pg4_10:
-+ case AARCH64_OPND_SVE_Pg4_16:
-+ case AARCH64_OPND_SVE_Pm:
-+ case AARCH64_OPND_SVE_Pn:
-+ case AARCH64_OPND_SVE_Pt:
-+ inst_pred = inst_op;
-+ inst_pred_idx = i;
-+ break;
-+ default:
-+ break;
-+ }
-+ }
-+
-+ assert (max_elem_size != 0);
-+ aarch64_opnd_info inst_dest = inst->operands[0];
-+ /* Determine the size that should be used to compare against the
-+ movprfx size. */
-+ current_elem_size
-+ = opcode->constraints & C_MAX_ELEM
-+ ? max_elem_size
-+ : aarch64_get_qualifier_esize (inst_dest.qualifier);
-+
-+ /* If movprfx is predicated do some extra checks. */
-+ if (predicated)
-+ {
-+ /* The instruction must be predicated. */
-+ if (inst_pred_idx < 0)
-+ {
-+ mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
-+ mismatch_detail->error = _("predicated instruction expected "
-+ "after `movprfx'");
-+ mismatch_detail->index = -1;
-+ mismatch_detail->non_fatal = TRUE;
-+ res = ERR_VFI;
-+ goto done;
-+ }
-+
-+ /* The instruction must have a merging predicate. */
-+ if (inst_pred.qualifier != AARCH64_OPND_QLF_P_M)
-+ {
-+ mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
-+ mismatch_detail->error = _("merging predicate expected due "
-+ "to preceding `movprfx'");
-+ mismatch_detail->index = inst_pred_idx;
-+ mismatch_detail->non_fatal = TRUE;
-+ res = ERR_VFI;
-+ goto done;
-+ }
-+
-+ /* The same register must be used in instruction. */
-+ if (blk_pred.reg.regno != inst_pred.reg.regno)
-+ {
-+ mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
-+ mismatch_detail->error = _("predicate register differs "
-+ "from that in preceding "
-+ "`movprfx'");
-+ mismatch_detail->index = inst_pred_idx;
-+ mismatch_detail->non_fatal = TRUE;
-+ res = ERR_VFI;
-+ goto done;
-+ }
-+ }
-+
-+ /* Destructive operations by definition must allow one usage of the
-+ same register. */
-+ int allowed_usage
-+ = aarch64_is_destructive_by_operands (opcode) ? 2 : 1;
-+
-+ /* Operand is not used at all. */
-+ if (num_op_used == 0)
-+ {
-+ mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
-+ mismatch_detail->error = _("output register of preceding "
-+ "`movprfx' not used in current "
-+ "instruction");
-+ mismatch_detail->index = 0;
-+ mismatch_detail->non_fatal = TRUE;
-+ res = ERR_VFI;
-+ goto done;
-+ }
-+
-+ /* We now know it's used, now determine exactly where it's used. */
-+ if (blk_dest.reg.regno != inst_dest.reg.regno)
-+ {
-+ mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
-+ mismatch_detail->error = _("output register of preceding "
-+ "`movprfx' expected as output");
-+ mismatch_detail->index = 0;
-+ mismatch_detail->non_fatal = TRUE;
-+ res = ERR_VFI;
-+ goto done;
-+ }
-+
-+ /* Operand used more than allowed for the specific opcode type. */
-+ if (num_op_used > allowed_usage)
-+ {
-+ mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
-+ mismatch_detail->error = _("output register of preceding "
-+ "`movprfx' used as input");
-+ mismatch_detail->index = last_op_usage;
-+ mismatch_detail->non_fatal = TRUE;
-+ res = ERR_VFI;
-+ goto done;
-+ }
-+
-+ /* Now the only thing left is the qualifiers checks. The register
-+ must have the same maximum element size. */
-+ if (inst_dest.qualifier
-+ && blk_dest.qualifier
-+ && current_elem_size
-+ != aarch64_get_qualifier_esize (blk_dest.qualifier))
-+ {
-+ mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
-+ mismatch_detail->error = _("register size not compatible with "
-+ "previous `movprfx'");
-+ mismatch_detail->index = 0;
-+ mismatch_detail->non_fatal = TRUE;
-+ res = ERR_VFI;
-+ goto done;
-+ }
-+ }
-+
-+ done:
-+ /* Add the new instruction to the sequence. */
-+ memcpy (insn_sequence->current_insns + insn_sequence->next_insn++,
-+ inst, sizeof (aarch64_inst));
-+
-+ /* Check if sequence is now full. */
-+ if (insn_sequence->next_insn >= insn_sequence->num_insns)
-+ {
-+ /* Sequence is full, but we don't have anything special to do for now,
-+ so clear and reset it. */
-+ init_insn_sequence (NULL, insn_sequence);
-+ }
-+ }
-+
-+ return res;
-+}
-+
-+
- /* Return true if VALUE cannot be moved into an SVE register using DUP
- (with any element size, not just ESIZE) and if using DUPM would
- therefore be OK. ESIZE is the number of bytes in the immediate. */
-diff -rup binutils-2.30/opcodes/aarch64-opc.h binutils-2.30.new/opcodes/aarch64-opc.h
---- binutils-2.30/opcodes/aarch64-opc.h 2018-01-13 13:31:16.000000000 +0000
-+++ binutils-2.30.new/opcodes/aarch64-opc.h 2021-03-23 16:19:53.187776169 +0000
-@@ -1,5 +1,5 @@
- /* aarch64-opc.h -- Header file for aarch64-opc.c and aarch64-opc-2.c.
-- Copyright (C) 2012-2018 Free Software Foundation, Inc.
-+ Copyright (C) 2012-2021 Free Software Foundation, Inc.
- Contributed by ARM Ltd.
-
- This file is part of the GNU opcodes library.
-@@ -70,6 +70,7 @@ enum aarch64_field_kind
- FLD_imm6_2,
- FLD_imm4,
- FLD_imm4_2,
-+ FLD_imm4_3,
- FLD_imm5,
- FLD_imm7,
- FLD_imm8,
-@@ -77,6 +78,7 @@ enum aarch64_field_kind
- FLD_imm12,
- FLD_imm14,
- FLD_imm16,
-+ FLD_imm16_2,
- FLD_imm26,
- FLD_imms,
- FLD_immr,
-@@ -120,6 +122,9 @@ enum aarch64_field_kind
- FLD_SVE_Zt,
- FLD_SVE_i1,
- FLD_SVE_i3h,
-+ FLD_SVE_i3l,
-+ FLD_SVE_i3h2,
-+ FLD_SVE_i2h,
- FLD_SVE_imm3,
- FLD_SVE_imm4,
- FLD_SVE_imm5,
-@@ -135,7 +140,10 @@ enum aarch64_field_kind
- FLD_SVE_prfop,
- FLD_SVE_rot1,
- FLD_SVE_rot2,
-+ FLD_SVE_rot3,
- FLD_SVE_sz,
-+ FLD_SVE_size,
-+ FLD_SVE_sz2,
- FLD_SVE_tsz,
- FLD_SVE_tszh,
- FLD_SVE_tszl_8,
-@@ -145,7 +153,9 @@ enum aarch64_field_kind
- FLD_rotate1,
- FLD_rotate2,
- FLD_rotate3,
-- FLD_SM3_imm2
-+ FLD_SM3_imm2,
-+ FLD_sz,
-+ FLD_CRm_dsb_nxs
- };
-
- /* Field description. */
-@@ -183,6 +193,10 @@ typedef struct aarch64_operand aarch64_o
-
- extern const aarch64_operand aarch64_operands[];
-
-+enum err_type
-+verify_constraints (const struct aarch64_inst *, const aarch64_insn, bfd_vma,
-+ bfd_boolean, aarch64_operand_error *, aarch64_instr_sequence*);
-+
- /* Operand flags. */
-
- #define OPD_F_HAS_INSERTER 0x00000001
-@@ -195,6 +209,38 @@ extern const aarch64_operand aarch64_ope
- #define OPD_F_OD_MASK 0x000000e0 /* Operand-dependent data. */
- #define OPD_F_OD_LSB 5
- #define OPD_F_NO_ZR 0x00000100 /* ZR index not allowed. */
-+#define OPD_F_SHIFT_BY_4 0x00000200 /* Need to left shift the field
-+ value by 4 to get the value
-+ of an immediate operand. */
-+
-+
-+/* Register flags. */
-+
-+#undef F_DEPRECATED
-+#define F_DEPRECATED (1 << 0) /* Deprecated system register. */
-+
-+#undef F_ARCHEXT
-+#define F_ARCHEXT (1 << 1) /* Architecture dependent system register. */
-+
-+#undef F_HASXT
-+#define F_HASXT (1 << 2) /* System instruction register <Xt>
-+ operand. */
-+
-+#undef F_REG_READ
-+#define F_REG_READ (1 << 3) /* Register can only be used to read values
-+ out of. */
-+
-+#undef F_REG_WRITE
-+#define F_REG_WRITE (1 << 4) /* Register can only be written to but not
-+ read from. */
-+
-+/* HINT operand flags. */
-+#define HINT_OPD_F_NOPRINT (1 << 0) /* Should not be printed. */
-+
-+/* Encode 7-bit HINT #imm in the lower 8 bits. Use higher bits for flags. */
-+#define HINT_ENCODE(flag, val) ((flag << 8) | val)
-+#define HINT_FLAG(val) (val >> 8)
-+#define HINT_VAL(val) (val & 0xff)
-
- static inline bfd_boolean
- operand_has_inserter (const aarch64_operand *operand)
-@@ -221,6 +267,12 @@ operand_need_shift_by_two (const aarch64
- }
-
- static inline bfd_boolean
-+operand_need_shift_by_four (const aarch64_operand *operand)
-+{
-+ return (operand->flags & OPD_F_SHIFT_BY_4) ? TRUE : FALSE;
-+}
-+
-+static inline bfd_boolean
- operand_maybe_stack_pointer (const aarch64_operand *operand)
- {
- return (operand->flags & OPD_F_MAYBE_SP) ? TRUE : FALSE;
-@@ -435,7 +487,7 @@ enum aarch64_modifier_kind
- aarch64_get_operand_modifier_from_value (aarch64_insn, bfd_boolean);
-
-
--bfd_boolean aarch64_wide_constant_p (int64_t, int, unsigned int *);
-+bfd_boolean aarch64_wide_constant_p (uint64_t, int, unsigned int *);
- bfd_boolean aarch64_logical_immediate_p (uint64_t, int, aarch64_insn *);
- int aarch64_shrink_expanded_imm8 (uint64_t);
-
-diff -rup binutils-2.30/opcodes/aarch64-tbl.h binutils-2.30.new/opcodes/aarch64-tbl.h
---- binutils-2.30/opcodes/aarch64-tbl.h 2018-01-13 13:31:16.000000000 +0000
-+++ binutils-2.30.new/opcodes/aarch64-tbl.h 2021-03-23 16:19:53.185776182 +0000
-@@ -1,6 +1,6 @@
- /* aarch64-tbl.h -- AArch64 opcode description table and instruction
- operand description table.
-- Copyright (C) 2012-2018 Free Software Foundation, Inc.
-+ Copyright (C) 2012-2021 Free Software Foundation, Inc.
-
- This file is part of the GNU opcodes library.
-
-@@ -74,6 +74,12 @@
- QLF2(X,NIL), \
- }
-
-+/* e.g. TCANCEL #<imm>. */
-+#define QL_IMM_NIL \
-+{ \
-+ QLF1(NIL), \
-+}
-+
- /* e.g. B.<cond> <label>. */
- #define QL_PCREL_NIL \
- { \
-@@ -125,6 +131,13 @@
- QLF1(X), \
- }
-
-+/* e.g. STG <Xt|SP>, [<Xn|SP>, #<imm9>]. */
-+#define QL_LDST_AT \
-+{ \
-+ QLF2(X, imm_tag), \
-+ QLF2(SP, imm_tag), \
-+}
-+
- /* e.g. RBIT <Wd>, <Wn>. */
- #define QL_I2SAME \
- { \
-@@ -240,6 +253,12 @@
- QLF4(X,X,imm_0_63,imm_0_63), \
- }
-
-+/* e.g. ADDG <Xd>, <Xn>, #<uimm10>, #<uimm4>. */
-+#define QL_ADDG \
-+{ \
-+ QLF4(X,X,NIL,imm_0_15), \
-+} \
-+
- /* e.g. BFC <Wd>, #<immr>, #<imms>. */
- #define QL_BF1 \
- { \
-@@ -295,6 +314,13 @@
- QLF2(S_S,X), \
- }
-
-+/* e.g. FMOV <Dd>, <Xn>. */
-+#define QL_INT2FP_FMOV \
-+{ \
-+ QLF2(S_S,W), \
-+ QLF2(S_D,X), \
-+}
-+
- /* e.g. SCVTF <Hd>, <Wn>. */
- #define QL_INT2FP_H \
- { \
-@@ -311,6 +337,13 @@
- QLF2(X,S_S), \
- }
-
-+/* e.g. FMOV <Xd>, <Dn>. */
-+#define QL_FP2INT_FMOV \
-+{ \
-+ QLF2(W,S_S), \
-+ QLF2(X,S_D), \
-+}
-+
- /* e.g. FCVTNS <Hd>, <Wn>. */
- #define QL_FP2INT_H \
- { \
-@@ -1110,6 +1143,12 @@
- QLF3(W, X, NIL), \
- }
-
-+/* e.g. ST64B <Xs>, <Xt>, [<Xn|SP>]. */
-+#define QL_X2NIL \
-+{ \
-+ QLF3(X, X, NIL), \
-+}
-+
- /* e.g. LDRAA <Xt>, [<Xn|SP>{,#imm}]. */
- #define QL_X1NIL \
- { \
-@@ -1192,12 +1231,24 @@
- QLF2(NIL, S_D), \
- }
-
-+/* e.g. LDG <Xt>, [<Xn|SP>{, #<simm>}]. */
-+#define QL_LDG \
-+{ \
-+ QLF2(X, imm_tag), \
-+}
-+
- /* e.g. LDPSW <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}]. */
- #define QL_LDST_PAIR_X32 \
- { \
- QLF3(X, X, S_S), \
- }
-
-+/* e.g. STGP <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}]. */
-+#define QL_STGP \
-+{ \
-+ QLF3(X, X, imm_tag), \
-+}
-+
- /* e.g. STP <Wt1>, <Wt2>, [<Xn|SP>, #<imm>]!. */
- #define QL_LDST_PAIR_R \
- { \
-@@ -1417,6 +1468,14 @@
- { \
- QLF2(S_B,S_B), \
- }
-+#define OP_SVE_BBU \
-+{ \
-+ QLF3(S_B,S_B,NIL), \
-+}
-+#define OP_SVE_BBB \
-+{ \
-+ QLF3(S_B,S_B,S_B), \
-+}
- #define OP_SVE_BBBU \
- { \
- QLF4(S_B,S_B,S_B,NIL), \
-@@ -1466,6 +1525,14 @@
- { \
- QLF3(S_D,S_D,S_D), \
- }
-+#define OP_SVE_QQQ \
-+{ \
-+ QLF3(S_Q,S_Q,S_Q), \
-+}
-+#define OP_SVE_DDDD \
-+{ \
-+ QLF4(S_D,S_D,S_D,S_D), \
-+}
- #define OP_SVE_DMD \
- { \
- QLF3(S_D,P_M,S_D), \
-@@ -1515,6 +1582,14 @@
- { \
- QLF2(S_H,S_B), \
- }
-+#define OP_SVE_HHH \
-+{ \
-+ QLF3(S_H,S_H,S_H), \
-+}
-+#define OP_SVE_HHHU \
-+{ \
-+ QLF4(S_H,S_H,S_H,NIL), \
-+}
- #define OP_SVE_HMH \
- { \
- QLF3(S_H,P_M,S_H), \
-@@ -1562,10 +1637,22 @@
- { \
- QLF3(S_S,P_M,S_D), \
- }
-+#define OP_SVE_SSS \
-+{ \
-+ QLF3(S_S,S_S,S_S), \
-+}
-+#define OP_SVE_SSSU \
-+{ \
-+ QLF4(S_S,S_S,S_S,NIL), \
-+}
- #define OP_SVE_SMH \
- { \
- QLF3(S_S,P_M,S_H), \
- }
-+#define OP_SVE_SHH \
-+{ \
-+ QLF3(S_S,S_H,S_H), \
-+}
- #define OP_SVE_SMS \
- { \
- QLF3(S_S,P_M,S_S), \
-@@ -1586,6 +1673,22 @@
- { \
- QLF3(S_S,P_Z,S_S), \
- }
-+#define OP_SVE_SBB \
-+{ \
-+ QLF3(S_S,S_B,S_B), \
-+}
-+#define OP_SVE_SBBU \
-+{ \
-+ QLF4(S_S,S_B,S_B,NIL), \
-+}
-+#define OP_SVE_DSS \
-+{ \
-+ QLF3(S_D,S_S,S_S), \
-+}
-+#define OP_SVE_DHHU \
-+{ \
-+ QLF4(S_D,S_H,S_H,NIL), \
-+}
- #define OP_SVE_SZU \
- { \
- QLF3(S_S,P_Z,NIL), \
-@@ -1671,6 +1774,18 @@
- QLF3(S_S,P_M,S_S), \
- QLF3(S_D,P_M,S_D), \
- }
-+#define OP_SVE_VMV_HSD_BHS \
-+{ \
-+ QLF3(S_H,P_M,S_B), \
-+ QLF3(S_S,P_M,S_H), \
-+ QLF3(S_D,P_M,S_S), \
-+}
-+#define OP_SVE_VVU_HSD_BHS \
-+{ \
-+ QLF3(S_H,S_B,NIL), \
-+ QLF3(S_S,S_H,NIL), \
-+ QLF3(S_D,S_S,NIL), \
-+}
- #define OP_SVE_VMV_SD \
- { \
- QLF3(S_S,P_M,S_S), \
-@@ -1810,12 +1925,24 @@
- { \
- QLF4(S_S,S_S,S_S,NIL), \
- }
-+#define OP_SVE_VVVU_SD_BH \
-+{ \
-+ QLF4(S_S,S_B,S_B,NIL), \
-+ QLF4(S_D,S_H,S_H,NIL), \
-+}
- #define OP_SVE_VVVU_HSD \
- { \
- QLF4(S_H,S_H,S_H,NIL), \
- QLF4(S_S,S_S,S_S,NIL), \
- QLF4(S_D,S_D,S_D,NIL), \
- }
-+#define OP_SVE_VVVU_BHSD \
-+{ \
-+ QLF4(S_B,S_B,S_B,NIL), \
-+ QLF4(S_H,S_H,S_H,NIL), \
-+ QLF4(S_S,S_S,S_S,NIL), \
-+ QLF4(S_D,S_D,S_D,NIL), \
-+}
- #define OP_SVE_VVV_BHSD \
- { \
- QLF3(S_B,S_B,S_B), \
-@@ -1845,15 +1972,53 @@
- { \
- QLF3(S_S,S_S,S_S), \
- }
-+#define OP_SVE_VVV_HD_BS \
-+{ \
-+ QLF3(S_H,S_B,S_B), \
-+ QLF3(S_D,S_S,S_S), \
-+}
- #define OP_SVE_VVV_S_B \
- { \
- QLF3(S_S,S_B,S_B), \
- }
-+#define OP_SVE_VVV_Q_D \
-+{ \
-+ QLF3(S_Q,S_D,S_D), \
-+}
-+#define OP_SVE_VVV_HSD_BHS \
-+{ \
-+ QLF3(S_H,S_B,S_B), \
-+ QLF3(S_S,S_H,S_H), \
-+ QLF3(S_D,S_S,S_S), \
-+}
-+#define OP_SVE_VVV_HSD_BHS2 \
-+{ \
-+ QLF3(S_H,S_H,S_B), \
-+ QLF3(S_S,S_S,S_H), \
-+ QLF3(S_D,S_D,S_S), \
-+}
-+#define OP_SVE_VVV_BHS_HSD \
-+{ \
-+ QLF3(S_B,S_H,S_H), \
-+ QLF3(S_H,S_S,S_S), \
-+ QLF3(S_S,S_D,S_D), \
-+}
-+#define OP_SVE_VV_BHS_HSD \
-+{ \
-+ QLF2(S_B,S_H), \
-+ QLF2(S_H,S_S), \
-+ QLF2(S_S,S_D), \
-+}
- #define OP_SVE_VVV_SD_BH \
- { \
- QLF3(S_S,S_B,S_B), \
- QLF3(S_D,S_H,S_H), \
- }
-+#define OP_SVE_VVV_SD \
-+{ \
-+ QLF3(S_S,S_S,S_S), \
-+ QLF3(S_D,S_D,S_D), \
-+}
- #define OP_SVE_VV_BHSD \
- { \
- QLF2(S_B,S_B), \
-@@ -1875,6 +2040,12 @@
- QLF2(S_S,S_S), \
- QLF2(S_D,S_D), \
- }
-+#define OP_SVE_VVU_BHS_HSD \
-+{ \
-+ QLF3(S_B,S_H,NIL), \
-+ QLF3(S_H,S_S,NIL), \
-+ QLF3(S_S,S_D,NIL), \
-+}
- #define OP_SVE_VV_HSD_BHS \
- { \
- QLF2(S_H,S_B), \
-@@ -1926,6 +2097,21 @@
- QLF4(S_S,P_Z,S_S,S_S), \
- QLF4(S_D,P_Z,S_D,S_D), \
- }
-+#define OP_SVE_VZVV_SD \
-+{ \
-+ QLF4(S_S,P_Z,S_S,S_S), \
-+ QLF4(S_D,P_Z,S_D,S_D), \
-+}
-+#define OP_SVE_VZVV_BH \
-+{ \
-+ QLF4(S_B,P_Z,S_B,S_B), \
-+ QLF4(S_H,P_Z,S_H,S_H), \
-+}
-+#define OP_SVE_VZV_SD \
-+{ \
-+ QLF3(S_S,P_Z,S_S), \
-+ QLF3(S_D,P_Z,S_D), \
-+}
- #define OP_SVE_VZV_HSD \
- { \
- QLF3(S_H,P_Z,S_H), \
-@@ -2085,6 +2271,56 @@
- { \
- QLF2(X, NIL), \
- }
-+
-+/* e.g. BFDOT <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb> */
-+#define QL_BFDOT64 \
-+{ \
-+ QLF3(V_2S, V_4H, V_4H),\
-+ QLF3(V_4S, V_8H, V_8H),\
-+}
-+
-+/* e.g. BFDOT <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.2H[<index>] */
-+#define QL_BFDOT64I \
-+{ \
-+ QLF3(V_2S, V_4H, S_2H),\
-+ QLF3(V_4S, V_8H, S_2H),\
-+}
-+
-+/* e.g. SMMLA <Vd>.4S, <Vn>.16B, <Vm>.16B */
-+#define QL_MMLA64 \
-+{ \
-+ QLF3(V_4S, V_16B, V_16B),\
-+}
-+
-+/* e.g. BFMMLA <Vd>.4s, <Vn>.8h, <Vm>.8h */
-+#define QL_BFMMLA \
-+{ \
-+ QLF3(V_4S, V_8H, V_8H),\
-+}
-+
-+/* e.g. BFCVT <Hd>, <Sn> */
-+#define QL_BFCVT64 \
-+{ \
-+ QLF2(S_H,S_S), \
-+}
-+
-+/* e.g. BFCVT <Hd>, <Sn> */
-+#define QL_BFCVTN64 \
-+{ \
-+ QLF2(V_4H,V_4S), \
-+}
-+
-+/* e.g. BFCVT <Hd>, <Sn> */
-+#define QL_BFCVTN2_64 \
-+{ \
-+ QLF2(V_8H,V_4S), \
-+}
-+
-+/* e.g. BFMLAL2 <Vd>.4s, <Vn>.8h, <Vm>.H[<index>] */
-+#define QL_V3BFML4S \
-+{ \
-+ QLF3(V_4S, V_8H, S_H), \
-+}
-
- /* Opcode table. */
-
-@@ -2094,9 +2330,6 @@ static const aarch64_feature_set aarch64
- AARCH64_FEATURE (AARCH64_FEATURE_FP, 0);
- static const aarch64_feature_set aarch64_feature_simd =
- AARCH64_FEATURE (AARCH64_FEATURE_SIMD, 0);
--static const aarch64_feature_set aarch64_feature_crypto =
-- AARCH64_FEATURE (AARCH64_FEATURE_CRYPTO | AARCH64_FEATURE_AES
-- | AARCH64_FEATURE_SHA2 | AARCH64_FEATURE_SIMD | AARCH64_FEATURE_FP, 0);
- static const aarch64_feature_set aarch64_feature_crc =
- AARCH64_FEATURE (AARCH64_FEATURE_CRC, 0);
- static const aarch64_feature_set aarch64_feature_lse =
-@@ -2105,22 +2338,20 @@ static const aarch64_feature_set aarch64
- AARCH64_FEATURE (AARCH64_FEATURE_LOR, 0);
- static const aarch64_feature_set aarch64_feature_rdma =
- AARCH64_FEATURE (AARCH64_FEATURE_RDMA, 0);
--static const aarch64_feature_set aarch64_feature_ras =
-- AARCH64_FEATURE (AARCH64_FEATURE_RAS, 0);
- static const aarch64_feature_set aarch64_feature_v8_2 =
- AARCH64_FEATURE (AARCH64_FEATURE_V8_2, 0);
- static const aarch64_feature_set aarch64_feature_fp_f16 =
- AARCH64_FEATURE (AARCH64_FEATURE_F16 | AARCH64_FEATURE_FP, 0);
- static const aarch64_feature_set aarch64_feature_simd_f16 =
- AARCH64_FEATURE (AARCH64_FEATURE_F16 | AARCH64_FEATURE_SIMD, 0);
--static const aarch64_feature_set aarch64_feature_stat_profile =
-- AARCH64_FEATURE (AARCH64_FEATURE_PROFILE, 0);
- static const aarch64_feature_set aarch64_feature_sve =
- AARCH64_FEATURE (AARCH64_FEATURE_SVE, 0);
- static const aarch64_feature_set aarch64_feature_v8_3 =
- AARCH64_FEATURE (AARCH64_FEATURE_V8_3, 0);
- static const aarch64_feature_set aarch64_feature_fp_v8_3 =
- AARCH64_FEATURE (AARCH64_FEATURE_V8_3 | AARCH64_FEATURE_FP, 0);
-+static const aarch64_feature_set aarch64_feature_pac =
-+ AARCH64_FEATURE (AARCH64_FEATURE_PAC, 0);
- static const aarch64_feature_set aarch64_feature_compnum =
- AARCH64_FEATURE (AARCH64_FEATURE_COMPNUM, 0);
- static const aarch64_feature_set aarch64_feature_rcpc =
-@@ -2133,9 +2364,6 @@ static const aarch64_feature_set aarch64
- AARCH64_FEATURE (AARCH64_FEATURE_V8 | AARCH64_FEATURE_AES, 0);
- static const aarch64_feature_set aarch64_feature_v8_4 =
- AARCH64_FEATURE (AARCH64_FEATURE_V8_4, 0);
--static const aarch64_feature_set aarch64_feature_crypto_v8_2 =
-- AARCH64_FEATURE (AARCH64_FEATURE_V8_2 | AARCH64_FEATURE_CRYPTO
-- | AARCH64_FEATURE_SIMD | AARCH64_FEATURE_FP, 0);
- static const aarch64_feature_set aarch64_feature_sm4 =
- AARCH64_FEATURE (AARCH64_FEATURE_V8_2 | AARCH64_FEATURE_SM4
- | AARCH64_FEATURE_SIMD | AARCH64_FEATURE_FP, 0);
-@@ -2145,23 +2373,70 @@ static const aarch64_feature_set aarch64
- static const aarch64_feature_set aarch64_feature_fp_16_v8_2 =
- AARCH64_FEATURE (AARCH64_FEATURE_V8_2 | AARCH64_FEATURE_F16_FML
- | AARCH64_FEATURE_F16 | AARCH64_FEATURE_FP, 0);
-+static const aarch64_feature_set aarch64_feature_v8_5 =
-+ AARCH64_FEATURE (AARCH64_FEATURE_V8_5, 0);
-+static const aarch64_feature_set aarch64_feature_flagmanip =
-+ AARCH64_FEATURE (AARCH64_FEATURE_FLAGMANIP, 0);
-+static const aarch64_feature_set aarch64_feature_frintts =
-+ AARCH64_FEATURE (AARCH64_FEATURE_FRINTTS, 0);
-+static const aarch64_feature_set aarch64_feature_sb =
-+ AARCH64_FEATURE (AARCH64_FEATURE_SB, 0);
-+static const aarch64_feature_set aarch64_feature_predres =
-+ AARCH64_FEATURE (AARCH64_FEATURE_PREDRES, 0);
-+static const aarch64_feature_set aarch64_feature_memtag =
-+ AARCH64_FEATURE (AARCH64_FEATURE_V8_5 | AARCH64_FEATURE_MEMTAG, 0);
-+static const aarch64_feature_set aarch64_feature_bfloat16 =
-+ AARCH64_FEATURE (AARCH64_FEATURE_BFLOAT16, 0);
-+static const aarch64_feature_set aarch64_feature_bfloat16_sve =
-+ AARCH64_FEATURE (AARCH64_FEATURE_BFLOAT16 | AARCH64_FEATURE_SVE, 0);
-+static const aarch64_feature_set aarch64_feature_tme =
-+ AARCH64_FEATURE (AARCH64_FEATURE_TME, 0);
-+static const aarch64_feature_set aarch64_feature_sve2 =
-+ AARCH64_FEATURE (AARCH64_FEATURE_SVE2, 0);
-+static const aarch64_feature_set aarch64_feature_sve2aes =
-+ AARCH64_FEATURE (AARCH64_FEATURE_SVE2 | AARCH64_FEATURE_SVE2_AES, 0);
-+static const aarch64_feature_set aarch64_feature_sve2sha3 =
-+ AARCH64_FEATURE (AARCH64_FEATURE_SVE2 | AARCH64_FEATURE_SVE2_SHA3, 0);
-+static const aarch64_feature_set aarch64_feature_sve2sm4 =
-+ AARCH64_FEATURE (AARCH64_FEATURE_SVE2 | AARCH64_FEATURE_SVE2_SM4, 0);
-+static const aarch64_feature_set aarch64_feature_sve2bitperm =
-+ AARCH64_FEATURE (AARCH64_FEATURE_SVE2 | AARCH64_FEATURE_SVE2_BITPERM, 0);
-+static const aarch64_feature_set aarch64_feature_v8_6 =
-+ AARCH64_FEATURE (AARCH64_FEATURE_V8_6, 0);
-+static const aarch64_feature_set aarch64_feature_v8_7 =
-+ AARCH64_FEATURE (AARCH64_FEATURE_V8_7, 0);
-+static const aarch64_feature_set aarch64_feature_i8mm =
-+ AARCH64_FEATURE (AARCH64_FEATURE_V8_2 | AARCH64_FEATURE_I8MM, 0);
-+static const aarch64_feature_set aarch64_feature_i8mm_sve =
-+ AARCH64_FEATURE (AARCH64_FEATURE_V8_2 | AARCH64_FEATURE_I8MM
-+ | AARCH64_FEATURE_SVE, 0);
-+static const aarch64_feature_set aarch64_feature_f32mm_sve =
-+ AARCH64_FEATURE (AARCH64_FEATURE_V8_2 | AARCH64_FEATURE_F32MM
-+ | AARCH64_FEATURE_SVE, 0);
-+static const aarch64_feature_set aarch64_feature_f64mm_sve =
-+ AARCH64_FEATURE (AARCH64_FEATURE_V8_2 | AARCH64_FEATURE_F64MM
-+ | AARCH64_FEATURE_SVE, 0);
-+static const aarch64_feature_set aarch64_feature_v8_r =
-+ AARCH64_FEATURE (AARCH64_FEATURE_V8_R, 0);
-+static const aarch64_feature_set aarch64_feature_ls64 =
-+ AARCH64_FEATURE (AARCH64_FEATURE_V8_6 | AARCH64_FEATURE_LS64, 0);
-+static const aarch64_feature_set aarch64_feature_flagm =
-+ AARCH64_FEATURE (AARCH64_FEATURE_FLAGM, 0);
-
- #define CORE &aarch64_feature_v8
- #define FP &aarch64_feature_fp
- #define SIMD &aarch64_feature_simd
--#define CRYPTO &aarch64_feature_crypto
- #define CRC &aarch64_feature_crc
- #define LSE &aarch64_feature_lse
- #define LOR &aarch64_feature_lor
- #define RDMA &aarch64_feature_rdma
- #define FP_F16 &aarch64_feature_fp_f16
- #define SIMD_F16 &aarch64_feature_simd_f16
--#define RAS &aarch64_feature_ras
--#define STAT_PROFILE &aarch64_feature_stat_profile
- #define ARMV8_2 &aarch64_feature_v8_2
- #define SVE &aarch64_feature_sve
- #define ARMV8_3 &aarch64_feature_v8_3
- #define FP_V8_3 &aarch64_feature_fp_v8_3
-+#define PAC &aarch64_feature_pac
- #define COMPNUM &aarch64_feature_compnum
- #define RCPC &aarch64_feature_rcpc
- #define SHA2 &aarch64_feature_sha2
-@@ -2169,57 +2444,145 @@ static const aarch64_feature_set aarch64
- #define ARMV8_4 &aarch64_feature_v8_4
- #define SHA3 &aarch64_feature_sha3
- #define SM4 &aarch64_feature_sm4
--#define CRYPTO_V8_2 &aarch64_feature_crypto_v8_2
- #define FP_F16_V8_2 &aarch64_feature_fp_16_v8_2
- #define DOTPROD &aarch64_feature_dotprod
-+#define ARMV8_5 &aarch64_feature_v8_5
-+#define FLAGMANIP &aarch64_feature_flagmanip
-+#define FRINTTS &aarch64_feature_frintts
-+#define SB &aarch64_feature_sb
-+#define PREDRES &aarch64_feature_predres
-+#define MEMTAG &aarch64_feature_memtag
-+#define TME &aarch64_feature_tme
-+#define SVE2 &aarch64_feature_sve2
-+#define SVE2_AES &aarch64_feature_sve2aes
-+#define SVE2_SHA3 &aarch64_feature_sve2sha3
-+#define SVE2_SM4 &aarch64_feature_sve2sm4
-+#define SVE2_BITPERM &aarch64_feature_sve2bitperm
-+#define ARMV8_6 &aarch64_feature_v8_6
-+#define ARMV8_6_SVE &aarch64_feature_v8_6
-+#define BFLOAT16_SVE &aarch64_feature_bfloat16_sve
-+#define BFLOAT16 &aarch64_feature_bfloat16
-+#define I8MM_SVE &aarch64_feature_i8mm_sve
-+#define F32MM_SVE &aarch64_feature_f32mm_sve
-+#define F64MM_SVE &aarch64_feature_f64mm_sve
-+#define I8MM &aarch64_feature_i8mm
-+#define ARMV8_R &aarch64_feature_v8_r
-+#define ARMV8_7 &aarch64_feature_v8_7
-+#define LS64 &aarch64_feature_ls64
-+#define FLAGM &aarch64_feature_flagm
-
- #define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
-- { NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, NULL }
-+ { NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, 0, NULL }
- #define __FP_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
-- { NAME, OPCODE, MASK, CLASS, OP, FP, OPS, QUALS, FLAGS, 0, NULL }
-+ { NAME, OPCODE, MASK, CLASS, OP, FP, OPS, QUALS, FLAGS, 0, 0, NULL }
- #define SIMD_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
-- { NAME, OPCODE, MASK, CLASS, OP, SIMD, OPS, QUALS, FLAGS, 0, NULL }
--#define CRYP_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
-- { NAME, OPCODE, MASK, CLASS, 0, CRYPTO, OPS, QUALS, FLAGS, 0, NULL }
-+ { NAME, OPCODE, MASK, CLASS, OP, SIMD, OPS, QUALS, FLAGS, 0, 0, NULL }
-+#define _SIMD_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,VERIFIER) \
-+ { NAME, OPCODE, MASK, CLASS, OP, SIMD, OPS, QUALS, FLAGS, 0, 0, VERIFIER }
- #define _CRC_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
-- { NAME, OPCODE, MASK, CLASS, 0, CRC, OPS, QUALS, FLAGS, 0, NULL }
-+ { NAME, OPCODE, MASK, CLASS, 0, CRC, OPS, QUALS, FLAGS, 0, 0, NULL }
- #define _LSE_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
-- { NAME, OPCODE, MASK, CLASS, 0, LSE, OPS, QUALS, FLAGS, 0, NULL }
-+ { NAME, OPCODE, MASK, CLASS, 0, LSE, OPS, QUALS, FLAGS, 0, 0, NULL }
- #define _LOR_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
-- { NAME, OPCODE, MASK, CLASS, 0, LOR, OPS, QUALS, FLAGS, 0, NULL }
-+ { NAME, OPCODE, MASK, CLASS, 0, LOR, OPS, QUALS, FLAGS, 0, 0, NULL }
- #define RDMA_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
-- { NAME, OPCODE, MASK, CLASS, 0, RDMA, OPS, QUALS, FLAGS, 0, NULL }
-+ { NAME, OPCODE, MASK, CLASS, 0, RDMA, OPS, QUALS, FLAGS, 0, 0, NULL }
- #define FF16_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
-- { NAME, OPCODE, MASK, CLASS, 0, FP_F16, OPS, QUALS, FLAGS, 0, NULL }
-+ { NAME, OPCODE, MASK, CLASS, 0, FP_F16, OPS, QUALS, FLAGS, 0, 0, NULL }
- #define SF16_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
-- { NAME, OPCODE, MASK, CLASS, 0, SIMD_F16, OPS, QUALS, FLAGS, 0, NULL }
-+ { NAME, OPCODE, MASK, CLASS, 0, SIMD_F16, OPS, QUALS, FLAGS, 0, 0, NULL }
- #define V8_2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
-- { NAME, OPCODE, MASK, CLASS, OP, ARMV8_2, OPS, QUALS, FLAGS, 0, NULL }
-+ { NAME, OPCODE, MASK, CLASS, OP, ARMV8_2, OPS, QUALS, FLAGS, 0, 0, NULL }
- #define _SVE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
- { NAME, OPCODE, MASK, CLASS, OP, SVE, OPS, QUALS, \
-- FLAGS | F_STRICT, TIED, NULL }
-+ FLAGS | F_STRICT, 0, TIED, NULL }
-+#define _SVE_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \
-+ { NAME, OPCODE, MASK, CLASS, OP, SVE, OPS, QUALS, \
-+ FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL }
- #define V8_3_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
-- { NAME, OPCODE, MASK, CLASS, 0, ARMV8_3, OPS, QUALS, FLAGS, 0, NULL }
-+ { NAME, OPCODE, MASK, CLASS, 0, ARMV8_3, OPS, QUALS, FLAGS, 0, 0, NULL }
-+#define PAC_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
-+ { NAME, OPCODE, MASK, CLASS, 0, PAC, OPS, QUALS, FLAGS, 0, 0, NULL }
- #define CNUM_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
-- { NAME, OPCODE, MASK, CLASS, OP, COMPNUM, OPS, QUALS, FLAGS, 0, NULL }
-+ { NAME, OPCODE, MASK, CLASS, OP, COMPNUM, OPS, QUALS, FLAGS, 0, 0, NULL }
- #define RCPC_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
-- { NAME, OPCODE, MASK, CLASS, 0, RCPC, OPS, QUALS, FLAGS, 0, NULL }
-+ { NAME, OPCODE, MASK, CLASS, 0, RCPC, OPS, QUALS, FLAGS, 0, 0, NULL }
- #define SHA2_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
-- { NAME, OPCODE, MASK, CLASS, 0, SHA2, OPS, QUALS, FLAGS, 0, NULL }
-+ { NAME, OPCODE, MASK, CLASS, 0, SHA2, OPS, QUALS, FLAGS, 0, 0, NULL }
- #define AES_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
-- { NAME, OPCODE, MASK, CLASS, 0, AES, OPS, QUALS, FLAGS, 0, NULL }
-+ { NAME, OPCODE, MASK, CLASS, 0, AES, OPS, QUALS, FLAGS, 0, 0, NULL }
- #define V8_4_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
-- { NAME, OPCODE, MASK, CLASS, 0, ARMV8_4, OPS, QUALS, FLAGS, 0, NULL }
--#define CRYPTO_V8_2_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
-- { NAME, OPCODE, MASK, CLASS, 0, CRYPTO_V8_2, OPS, QUALS, FLAGS, 0, NULL }
-+ { NAME, OPCODE, MASK, CLASS, 0, ARMV8_4, OPS, QUALS, FLAGS, 0, 0, NULL }
- #define SHA3_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
-- { NAME, OPCODE, MASK, CLASS, 0, SHA3, OPS, QUALS, FLAGS, 0, NULL }
-+ { NAME, OPCODE, MASK, CLASS, 0, SHA3, OPS, QUALS, FLAGS, 0, 0, NULL }
- #define SM4_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
-- { NAME, OPCODE, MASK, CLASS, 0, SM4, OPS, QUALS, FLAGS, 0, NULL }
-+ { NAME, OPCODE, MASK, CLASS, 0, SM4, OPS, QUALS, FLAGS, 0, 0, NULL }
- #define FP16_V8_2_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
-- { NAME, OPCODE, MASK, CLASS, 0, FP_F16_V8_2, OPS, QUALS, FLAGS, 0, NULL }
-+ { NAME, OPCODE, MASK, CLASS, 0, FP_F16_V8_2, OPS, QUALS, FLAGS, 0, 0, NULL }
- #define DOT_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
-- { NAME, OPCODE, MASK, CLASS, 0, DOTPROD, OPS, QUALS, FLAGS, 0, NULL }
-+ { NAME, OPCODE, MASK, CLASS, 0, DOTPROD, OPS, QUALS, FLAGS, 0, 0, NULL }
-+#define V8_5_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
-+ { NAME, OPCODE, MASK, CLASS, 0, ARMV8_5, OPS, QUALS, FLAGS, 0, 0, NULL }
-+#define FLAGMANIP_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
-+ { NAME, OPCODE, MASK, CLASS, 0, FLAGMANIP, OPS, QUALS, FLAGS, 0, 0, NULL }
-+#define FRINTTS_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
-+ { NAME, OPCODE, MASK, CLASS, 0, FRINTTS, OPS, QUALS, FLAGS, 0, 0, NULL }
-+#define SB_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
-+ { NAME, OPCODE, MASK, CLASS, 0, SB, OPS, QUALS, FLAGS, 0, 0, NULL }
-+#define PREDRES_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
-+ { NAME, OPCODE, MASK, CLASS, 0, PREDRES, OPS, QUALS, FLAGS, 0, 0, NULL }
-+#define MEMTAG_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
-+ { NAME, OPCODE, MASK, CLASS, 0, MEMTAG, OPS, QUALS, FLAGS, 0, 0, NULL }
-+#define _TME_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
-+ { NAME, OPCODE, MASK, CLASS, OP, TME, OPS, QUALS, FLAGS, 0, 0, NULL }
-+#define SVE2_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
-+ { NAME, OPCODE, MASK, CLASS, OP, SVE2, OPS, QUALS, \
-+ FLAGS | F_STRICT, 0, TIED, NULL }
-+#define SVE2_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \
-+ { NAME, OPCODE, MASK, CLASS, OP, SVE2, OPS, QUALS, \
-+ FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL }
-+#define SVE2AES_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
-+ { NAME, OPCODE, MASK, CLASS, OP, SVE2_AES, OPS, QUALS, \
-+ FLAGS | F_STRICT, 0, TIED, NULL }
-+#define SVE2SHA3_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
-+ { NAME, OPCODE, MASK, CLASS, OP, SVE2_SHA3, OPS, QUALS, \
-+ FLAGS | F_STRICT, 0, TIED, NULL }
-+#define SVE2SM4_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
-+ { NAME, OPCODE, MASK, CLASS, OP, SVE2_SM4, OPS, QUALS, \
-+ FLAGS | F_STRICT, 0, TIED, NULL }
-+#define SVE2SM4_INSNC(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS,TIED) \
-+ { NAME, OPCODE, MASK, CLASS, OP, SVE2_SM4, OPS, QUALS, \
-+ FLAGS | F_STRICT, CONSTRAINTS, TIED, NULL }
-+#define SVE2BITPERM_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,TIED) \
-+ { NAME, OPCODE, MASK, CLASS, OP, SVE2_BITPERM, OPS, QUALS, \
-+ FLAGS | F_STRICT, 0, TIED, NULL }
-+#define V8_6_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
-+ { NAME, OPCODE, MASK, CLASS, 0, ARMV8_6, OPS, QUALS, FLAGS, 0, 0, NULL }
-+#define BFLOAT16_SVE_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
-+ { NAME, OPCODE, MASK, CLASS, 0, BFLOAT16_SVE, OPS, QUALS, FLAGS, 0, 0, NULL }
-+#define BFLOAT16_SVE_INSNC(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS, CONSTRAINTS, TIED) \
-+ { NAME, OPCODE, MASK, CLASS, 0, BFLOAT16_SVE, OPS, QUALS, FLAGS | F_STRICT, \
-+ CONSTRAINTS, TIED, NULL }
-+#define BFLOAT16_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
-+ { NAME, OPCODE, MASK, CLASS, 0, BFLOAT16, OPS, QUALS, FLAGS, 0, 0, NULL }
-+#define INT8MATMUL_SVE_INSNC(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS, CONSTRAINTS, TIED) \
-+ { NAME, OPCODE, MASK, CLASS, 0, I8MM_SVE, OPS, QUALS, FLAGS, CONSTRAINTS, TIED, NULL }
-+#define INT8MATMUL_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
-+ { NAME, OPCODE, MASK, CLASS, 0, I8MM, OPS, QUALS, FLAGS, 0, 0, NULL }
-+#define F64MATMUL_SVE_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS,TIED) \
-+ { NAME, OPCODE, MASK, CLASS, 0, F64MM_SVE, OPS, QUALS, FLAGS, 0, TIED, NULL }
-+#define F64MATMUL_SVE_INSNC(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS, CONSTRAINTS, TIED) \
-+ { NAME, OPCODE, MASK, CLASS, 0, F64MM_SVE, OPS, QUALS, FLAGS, CONSTRAINTS, TIED, NULL }
-+#define F32MATMUL_SVE_INSNC(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS, CONSTRAINTS, TIED) \
-+ { NAME, OPCODE, MASK, CLASS, 0, F32MM_SVE, OPS, QUALS, FLAGS, CONSTRAINTS, TIED, NULL }
-+#define V8_R_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
-+ { NAME, OPCODE, MASK, CLASS, 0, ARMV8_R, OPS, QUALS, FLAGS, 0, 0, NULL }
-+#define V8_7_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
-+ { NAME, OPCODE, MASK, CLASS, 0, ARMV8_7, OPS, QUALS, FLAGS, 0, 0, NULL }
-+#define _LS64_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
-+ { NAME, OPCODE, MASK, CLASS, 0, LS64, OPS, QUALS, FLAGS, 0, 0, NULL }
-+#define FLAGM_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
-+ { NAME, OPCODE, MASK, CLASS, 0, FLAGM, OPS, QUALS, FLAGS, 0, 0, NULL }
-
- struct aarch64_opcode aarch64_opcode_table[] =
- {
-@@ -2245,6 +2608,8 @@ struct aarch64_opcode aarch64_opcode_tab
- CORE_INSN ("sub", 0x51000000, 0x7f000000, addsub_imm, 0, OP3 (Rd_SP, Rn_SP, AIMM), QL_R2NIL, F_SF),
- CORE_INSN ("subs", 0x71000000, 0x7f000000, addsub_imm, 0, OP3 (Rd, Rn_SP, AIMM), QL_R2NIL, F_HAS_ALIAS | F_SF),
- CORE_INSN ("cmp", 0x7100001f, 0x7f00001f, addsub_imm, 0, OP2 (Rn_SP, AIMM), QL_R1NIL, F_ALIAS | F_SF),
-+ MEMTAG_INSN ("addg", 0x91800000, 0xffc0c000, addsub_imm, OP4 (Rd_SP, Rn_SP, UIMM10, UIMM4_ADDG), QL_ADDG, 0),
-+ MEMTAG_INSN ("subg", 0xd1800000, 0xffc0c000, addsub_imm, OP4 (Rd_SP, Rn_SP, UIMM10, UIMM4_ADDG), QL_ADDG, 0),
- /* Add/subtract (shifted register). */
- CORE_INSN ("add", 0x0b000000, 0x7f200000, addsub_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_SF),
- CORE_INSN ("adds", 0x2b000000, 0x7f200000, addsub_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF),
-@@ -2252,7 +2617,7 @@ struct aarch64_opcode aarch64_opcode_tab
- CORE_INSN ("sub", 0x4b000000, 0x7f200000, addsub_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF),
- CORE_INSN ("neg", 0x4b0003e0, 0x7f2003e0, addsub_shift, 0, OP2 (Rd, Rm_SFT), QL_I2SAME, F_ALIAS | F_SF),
- CORE_INSN ("subs", 0x6b000000, 0x7f200000, addsub_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF),
-- CORE_INSN ("cmp", 0x6b00001f, 0x7f20001f, addsub_shift, 0, OP2 (Rn, Rm_SFT), QL_I2SAME, F_ALIAS | F_SF),
-+ CORE_INSN ("cmp", 0x6b00001f, 0x7f20001f, addsub_shift, 0, OP2 (Rn, Rm_SFT), QL_I2SAME, F_ALIAS | F_SF | F_P1),
- CORE_INSN ("negs", 0x6b0003e0, 0x7f2003e0, addsub_shift, 0, OP2 (Rd, Rm_SFT), QL_I2SAME, F_ALIAS | F_SF),
- /* AdvSIMD across lanes. */
- SIMD_INSN ("saddlv", 0x0e303800, 0xbf3ffc00, asimdall, 0, OP2 (Fd, Vn), QL_XLANES_L, F_SIZEQ),
-@@ -2326,39 +2691,39 @@ struct aarch64_opcode aarch64_opcode_tab
- SIMD_INSN ("umull", 0x2e20c000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS, F_SIZEQ),
- SIMD_INSN ("umull2", 0x6e20c000, 0xff20fc00, asimddiff, 0, OP3 (Vd, Vn, Vm), QL_V3LONGBHS2, F_SIZEQ),
- /* AdvSIMD vector x indexed element. */
-- SIMD_INSN ("smlal", 0x0f002000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ),
-- SIMD_INSN ("smlal2", 0x4f002000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ),
-- SIMD_INSN ("sqdmlal", 0x0f003000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ),
-- SIMD_INSN ("sqdmlal2",0x4f003000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ),
-- SIMD_INSN ("smlsl", 0x0f006000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ),
-- SIMD_INSN ("smlsl2", 0x4f006000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ),
-- SIMD_INSN ("sqdmlsl", 0x0f007000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ),
-- SIMD_INSN ("sqdmlsl2",0x4f007000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ),
-- SIMD_INSN ("mul", 0x0f008000, 0xbf00f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ),
-- SIMD_INSN ("smull", 0x0f00a000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ),
-- SIMD_INSN ("smull2", 0x4f00a000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ),
-- SIMD_INSN ("sqdmull", 0x0f00b000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ),
-- SIMD_INSN ("sqdmull2",0x4f00b000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ),
-- SIMD_INSN ("sqdmulh", 0x0f00c000, 0xbf00f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ),
-- SIMD_INSN ("sqrdmulh",0x0f00d000, 0xbf00f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ),
-- SIMD_INSN ("fmla", 0x0f801000, 0xbf80f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_FP, F_SIZEQ),
-- SF16_INSN ("fmla", 0x0f001000, 0xbfc0f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT_FP_H, F_SIZEQ),
-- SIMD_INSN ("fmls", 0x0f805000, 0xbf80f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_FP, F_SIZEQ),
-- SF16_INSN ("fmls", 0x0f005000, 0xbfc0f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT_FP_H, F_SIZEQ),
-- SIMD_INSN ("fmul", 0x0f809000, 0xbf80f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_FP, F_SIZEQ),
-- SF16_INSN ("fmul", 0x0f009000, 0xbfc0f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT_FP_H, F_SIZEQ),
-- SIMD_INSN ("mla", 0x2f000000, 0xbf00f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ),
-- SIMD_INSN ("umlal", 0x2f002000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ),
-- SIMD_INSN ("umlal2", 0x6f002000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ),
-- SIMD_INSN ("mls", 0x2f004000, 0xbf00f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ),
-- SIMD_INSN ("umlsl", 0x2f006000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ),
-- SIMD_INSN ("umlsl2", 0x6f006000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ),
-- SIMD_INSN ("umull", 0x2f00a000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_L, F_SIZEQ),
-- SIMD_INSN ("umull2", 0x6f00a000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_L2, F_SIZEQ),
-- SIMD_INSN ("fmulx", 0x2f809000, 0xbf80f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_FP, F_SIZEQ),
-- SF16_INSN ("fmulx", 0x2f009000, 0xbfc0f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT_FP_H, F_SIZEQ),
-- RDMA_INSN ("sqrdmlah",0x2f00d000, 0xbf00f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ),
-- RDMA_INSN ("sqrdmlsh",0x2f00f000, 0xbf00f400, asimdelem, OP3 (Vd, Vn, Em), QL_ELEMENT, F_SIZEQ),
-+ SIMD_INSN ("smlal", 0x0f002000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L, F_SIZEQ),
-+ SIMD_INSN ("smlal2", 0x4f002000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L2, F_SIZEQ),
-+ SIMD_INSN ("sqdmlal", 0x0f003000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L, F_SIZEQ),
-+ SIMD_INSN ("sqdmlal2",0x4f003000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L2, F_SIZEQ),
-+ SIMD_INSN ("smlsl", 0x0f006000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L, F_SIZEQ),
-+ SIMD_INSN ("smlsl2", 0x4f006000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L2, F_SIZEQ),
-+ SIMD_INSN ("sqdmlsl", 0x0f007000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L, F_SIZEQ),
-+ SIMD_INSN ("sqdmlsl2",0x4f007000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L2, F_SIZEQ),
-+ SIMD_INSN ("mul", 0x0f008000, 0xbf00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT, F_SIZEQ),
-+ SIMD_INSN ("smull", 0x0f00a000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L, F_SIZEQ),
-+ SIMD_INSN ("smull2", 0x4f00a000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L2, F_SIZEQ),
-+ SIMD_INSN ("sqdmull", 0x0f00b000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L, F_SIZEQ),
-+ SIMD_INSN ("sqdmull2",0x4f00b000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L2, F_SIZEQ),
-+ SIMD_INSN ("sqdmulh", 0x0f00c000, 0xbf00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT, F_SIZEQ),
-+ SIMD_INSN ("sqrdmulh",0x0f00d000, 0xbf00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT, F_SIZEQ),
-+ _SIMD_INSN ("fmla", 0x0f801000, 0xbf80f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_FP, F_SIZEQ, VERIFIER (elem_sd)),
-+ SF16_INSN ("fmla", 0x0f001000, 0xbfc0f400, asimdelem, OP3 (Vd, Vn, Em16), QL_ELEMENT_FP_H, F_SIZEQ),
-+ _SIMD_INSN ("fmls", 0x0f805000, 0xbf80f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_FP, F_SIZEQ, VERIFIER (elem_sd)),
-+ SF16_INSN ("fmls", 0x0f005000, 0xbfc0f400, asimdelem, OP3 (Vd, Vn, Em16), QL_ELEMENT_FP_H, F_SIZEQ),
-+ _SIMD_INSN ("fmul", 0x0f809000, 0xbf80f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_FP, F_SIZEQ, VERIFIER (elem_sd)),
-+ SF16_INSN ("fmul", 0x0f009000, 0xbfc0f400, asimdelem, OP3 (Vd, Vn, Em16), QL_ELEMENT_FP_H, F_SIZEQ),
-+ SIMD_INSN ("mla", 0x2f000000, 0xbf00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT, F_SIZEQ),
-+ SIMD_INSN ("umlal", 0x2f002000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L, F_SIZEQ),
-+ SIMD_INSN ("umlal2", 0x6f002000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L2, F_SIZEQ),
-+ SIMD_INSN ("mls", 0x2f004000, 0xbf00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT, F_SIZEQ),
-+ SIMD_INSN ("umlsl", 0x2f006000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L, F_SIZEQ),
-+ SIMD_INSN ("umlsl2", 0x6f006000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L2, F_SIZEQ),
-+ SIMD_INSN ("umull", 0x2f00a000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L, F_SIZEQ),
-+ SIMD_INSN ("umull2", 0x6f00a000, 0xff00f400, asimdelem, 0, OP3 (Vd, Vn, Em16), QL_ELEMENT_L2, F_SIZEQ),
-+ _SIMD_INSN ("fmulx", 0x2f809000, 0xbf80f400, asimdelem, 0, OP3 (Vd, Vn, Em), QL_ELEMENT_FP, F_SIZEQ, VERIFIER (elem_sd)),
-+ SF16_INSN ("fmulx", 0x2f009000, 0xbfc0f400, asimdelem, OP3 (Vd, Vn, Em16), QL_ELEMENT_FP_H, F_SIZEQ),
-+ RDMA_INSN ("sqrdmlah",0x2f00d000, 0xbf00f400, asimdelem, OP3 (Vd, Vn, Em16), QL_ELEMENT, F_SIZEQ),
-+ RDMA_INSN ("sqrdmlsh",0x2f00f000, 0xbf00f400, asimdelem, OP3 (Vd, Vn, Em16), QL_ELEMENT, F_SIZEQ),
- CNUM_INSN ("fcmla", 0x2f001000, 0xbf009400, asimdelem, OP_FCMLA_ELEM, OP4 (Vd, Vn, Em, IMM_ROT2), QL_ELEMENT_ROT, F_SIZEQ),
- /* AdvSIMD EXT. */
- SIMD_INSN ("ext", 0x2e000000, 0xbfe08400, asimdext, 0, OP4 (Vd, Vn, Vm, IDX), QL_VEXT, F_SIZEQ),
-@@ -2390,6 +2755,10 @@ struct aarch64_opcode aarch64_opcode_tab
- SIMD_INSN ("ins", 0x6e000400, 0xffe08400, asimdins, 0, OP2 (Ed, En), QL_S_2SAME, F_HAS_ALIAS),
- SIMD_INSN ("mov", 0x6e000400, 0xffe08400, asimdins, 0, OP2 (Ed, En), QL_S_2SAME, F_ALIAS),
- /* AdvSIMD two-reg misc. */
-+ FRINTTS_INSN ("frint32z", 0x0e21e800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ),
-+ FRINTTS_INSN ("frint32x", 0x2e21e800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ),
-+ FRINTTS_INSN ("frint64z", 0x0e21f800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ),
-+ FRINTTS_INSN ("frint64x", 0x2e21f800, 0xbfbffc00, asimdmisc, OP2 (Vd, Vn), QL_V2SAMESD, F_SIZEQ),
- SIMD_INSN ("rev64", 0x0e200800, 0xbf3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMEBHS, F_SIZEQ),
- SIMD_INSN ("rev16", 0x0e201800, 0xbf3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2SAMEB, F_SIZEQ),
- SIMD_INSN ("saddlp",0x0e202800, 0xbf3ffc00, asimdmisc, 0, OP2 (Vd, Vn), QL_V2PAIRWISELONGBHS, F_SIZEQ),
-@@ -2601,8 +2970,8 @@ struct aarch64_opcode aarch64_opcode_tab
- SIMD_INSN ("bit", 0x2ea01c00, 0xbfe0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ),
- SIMD_INSN ("bif", 0x2ee01c00, 0xbfe0fc00, asimdsame, 0, OP3 (Vd, Vn, Vm), QL_V3SAMEB, F_SIZEQ),
- /* AdvSIMD three same extension. */
-- RDMA_INSN ("sqrdmlah",0x2e008400, 0xbf20fe00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEHS, F_SIZEQ),
-- RDMA_INSN ("sqrdmlsh",0x2e008c00, 0xbf20fe00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEHS, F_SIZEQ),
-+ RDMA_INSN ("sqrdmlah",0x2e008400, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEHS, F_SIZEQ),
-+ RDMA_INSN ("sqrdmlsh",0x2e008c00, 0xbf20fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3SAMEHS, F_SIZEQ),
- CNUM_INSN ("fcmla", 0x2e00c400, 0xbf20e400, asimdsame, 0, OP4 (Vd, Vn, Vm, IMM_ROT1), QL_V3SAMEHSD_ROT, F_SIZEQ),
- CNUM_INSN ("fcadd", 0x2e00e400, 0xbf20ec00, asimdsame, 0, OP4 (Vd, Vn, Vm, IMM_ROT3), QL_V3SAMEHSD_ROT, F_SIZEQ),
- /* AdvSIMD shift by immediate. */
-@@ -2660,21 +3029,21 @@ struct aarch64_opcode aarch64_opcode_tab
- SIMD_INSN ("sqdmlsl", 0x5e20b000, 0xff20fc00, asisddiff, 0, OP3 (Sd, Sn, Sm), QL_SISDL_HS, F_SSIZE),
- SIMD_INSN ("sqdmull", 0x5e20d000, 0xff20fc00, asisddiff, 0, OP3 (Sd, Sn, Sm), QL_SISDL_HS, F_SSIZE),
- /* AdvSIMD scalar x indexed element. */
-- SIMD_INSN ("sqdmlal", 0x5f003000, 0xff00f400, asisdelem, 0, OP3 (Sd, Sn, Em), QL_SISDL_HS, F_SSIZE),
-- SIMD_INSN ("sqdmlsl", 0x5f007000, 0xff00f400, asisdelem, 0, OP3 (Sd, Sn, Em), QL_SISDL_HS, F_SSIZE),
-- SIMD_INSN ("sqdmull", 0x5f00b000, 0xff00f400, asisdelem, 0, OP3 (Sd, Sn, Em), QL_SISDL_HS, F_SSIZE),
-- SIMD_INSN ("sqdmulh", 0x5f00c000, 0xff00f400, asisdelem, 0, OP3 (Sd, Sn, Em), QL_SISD_HS, F_SSIZE),
-- SIMD_INSN ("sqrdmulh", 0x5f00d000, 0xff00f400, asisdelem, 0, OP3 (Sd, Sn, Em), QL_SISD_HS, F_SSIZE),
-- SIMD_INSN ("fmla", 0x5f801000, 0xff80f400, asisdelem, 0, OP3 (Sd, Sn, Em), QL_FP3, F_SSIZE),
-- SF16_INSN ("fmla", 0x5f001000, 0xffc0f400, asisdelem, OP3 (Sd, Sn, Em), QL_FP3_H, F_SSIZE),
-- SIMD_INSN ("fmls", 0x5f805000, 0xff80f400, asisdelem, 0, OP3 (Sd, Sn, Em), QL_FP3, F_SSIZE),
-- SF16_INSN ("fmls", 0x5f005000, 0xffc0f400, asisdelem, OP3 (Sd, Sn, Em), QL_FP3_H, F_SSIZE),
-- SIMD_INSN ("fmul", 0x5f809000, 0xff80f400, asisdelem, 0, OP3 (Sd, Sn, Em), QL_FP3, F_SSIZE),
-- SF16_INSN ("fmul", 0x5f009000, 0xffc0f400, asisdelem, OP3 (Sd, Sn, Em), QL_FP3_H, F_SSIZE),
-- SIMD_INSN ("fmulx", 0x7f809000, 0xff80f400, asisdelem, 0, OP3 (Sd, Sn, Em), QL_FP3, F_SSIZE),
-- SF16_INSN ("fmulx", 0x7f009000, 0xffc0f400, asisdelem, OP3 (Sd, Sn, Em), QL_FP3_H, F_SSIZE),
-- RDMA_INSN ("sqrdmlah", 0x7f00d000, 0xff00f400, asisdelem, OP3 (Sd, Sn, Em), QL_SISD_HS, F_SSIZE),
-- RDMA_INSN ("sqrdmlsh", 0x7f00f000, 0xff00f400, asisdelem, OP3 (Sd, Sn, Em), QL_SISD_HS, F_SSIZE),
-+ SIMD_INSN ("sqdmlal", 0x5f003000, 0xff00f400, asisdelem, 0, OP3 (Sd, Sn, Em16), QL_SISDL_HS, F_SSIZE),
-+ SIMD_INSN ("sqdmlsl", 0x5f007000, 0xff00f400, asisdelem, 0, OP3 (Sd, Sn, Em16), QL_SISDL_HS, F_SSIZE),
-+ SIMD_INSN ("sqdmull", 0x5f00b000, 0xff00f400, asisdelem, 0, OP3 (Sd, Sn, Em16), QL_SISDL_HS, F_SSIZE),
-+ SIMD_INSN ("sqdmulh", 0x5f00c000, 0xff00f400, asisdelem, 0, OP3 (Sd, Sn, Em16), QL_SISD_HS, F_SSIZE),
-+ SIMD_INSN ("sqrdmulh", 0x5f00d000, 0xff00f400, asisdelem, 0, OP3 (Sd, Sn, Em16), QL_SISD_HS, F_SSIZE),
-+ _SIMD_INSN ("fmla", 0x5f801000, 0xff80f400, asisdelem, 0, OP3 (Sd, Sn, Em), QL_FP3, F_SSIZE, VERIFIER (elem_sd)),
-+ SF16_INSN ("fmla", 0x5f001000, 0xffc0f400, asisdelem, OP3 (Sd, Sn, Em16), QL_FP3_H, F_SSIZE),
-+ _SIMD_INSN ("fmls", 0x5f805000, 0xff80f400, asisdelem, 0, OP3 (Sd, Sn, Em), QL_FP3, F_SSIZE, VERIFIER (elem_sd)),
-+ SF16_INSN ("fmls", 0x5f005000, 0xffc0f400, asisdelem, OP3 (Sd, Sn, Em16), QL_FP3_H, F_SSIZE),
-+ _SIMD_INSN ("fmul", 0x5f809000, 0xff80f400, asisdelem, 0, OP3 (Sd, Sn, Em), QL_FP3, F_SSIZE, VERIFIER (elem_sd)),
-+ SF16_INSN ("fmul", 0x5f009000, 0xffc0f400, asisdelem, OP3 (Sd, Sn, Em16), QL_FP3_H, F_SSIZE),
-+ _SIMD_INSN ("fmulx", 0x7f809000, 0xff80f400, asisdelem, 0, OP3 (Sd, Sn, Em), QL_FP3, F_SSIZE, VERIFIER (elem_sd)),
-+ SF16_INSN ("fmulx", 0x7f009000, 0xffc0f400, asisdelem, OP3 (Sd, Sn, Em16), QL_FP3_H, F_SSIZE),
-+ RDMA_INSN ("sqrdmlah", 0x7f00d000, 0xff00f400, asisdelem, OP3 (Sd, Sn, Em16), QL_SISD_HS, F_SSIZE),
-+ RDMA_INSN ("sqrdmlsh", 0x7f00f000, 0xff00f400, asisdelem, OP3 (Sd, Sn, Em16), QL_SISD_HS, F_SSIZE),
- /* AdvSIMD load/store multiple structures. */
- SIMD_INSN ("st4", 0xc000000, 0xbfff0000, asisdlse, 0, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST, F_SIZEQ | F_OD(4)),
- SIMD_INSN ("st1", 0xc000000, 0xbfff0000, asisdlse, 0, OP2 (LVt, SIMD_ADDR_SIMPLE), QL_SIMD_LDST_ANY, F_SIZEQ | F_OD(1)),
-@@ -2891,18 +3260,18 @@ struct aarch64_opcode aarch64_opcode_tab
- CORE_INSN ("ret", 0xd65f0000, 0xfffffc1f, branch_reg, 0, OP1 (Rn), QL_I1X, F_OPD0_OPT | F_DEFAULT (30)),
- CORE_INSN ("eret", 0xd69f03e0, 0xffffffff, branch_reg, 0, OP0 (), {}, 0),
- CORE_INSN ("drps", 0xd6bf03e0, 0xffffffff, branch_reg, 0, OP0 (), {}, 0),
-- V8_3_INSN ("braa", 0xd71f0800, 0xfffffc00, branch_reg, OP2 (Rn, Rd_SP), QL_I2SAMEX, 0),
-- V8_3_INSN ("brab", 0xd71f0c00, 0xfffffc00, branch_reg, OP2 (Rn, Rd_SP), QL_I2SAMEX, 0),
-- V8_3_INSN ("blraa", 0xd73f0800, 0xfffffc00, branch_reg, OP2 (Rn, Rd_SP), QL_I2SAMEX, 0),
-- V8_3_INSN ("blrab", 0xd73f0c00, 0xfffffc00, branch_reg, OP2 (Rn, Rd_SP), QL_I2SAMEX, 0),
-- V8_3_INSN ("braaz", 0xd61f081f, 0xfffffc1f, branch_reg, OP1 (Rn), QL_I1X, 0),
-- V8_3_INSN ("brabz", 0xd61f0c1f, 0xfffffc1f, branch_reg, OP1 (Rn), QL_I1X, 0),
-- V8_3_INSN ("blraaz", 0xd63f081f, 0xfffffc1f, branch_reg, OP1 (Rn), QL_I1X, 0),
-- V8_3_INSN ("blrabz", 0xd63f0c1f, 0xfffffc1f, branch_reg, OP1 (Rn), QL_I1X, 0),
-- V8_3_INSN ("retaa", 0xd65f0bff, 0xffffffff, branch_reg, OP0 (), {}, 0),
-- V8_3_INSN ("retab", 0xd65f0fff, 0xffffffff, branch_reg, OP0 (), {}, 0),
-- V8_3_INSN ("eretaa", 0xd69f0bff, 0xffffffff, branch_reg, OP0 (), {}, 0),
-- V8_3_INSN ("eretab", 0xd69f0fff, 0xffffffff, branch_reg, OP0 (), {}, 0),
-+ PAC_INSN ("braa", 0xd71f0800, 0xfffffc00, branch_reg, OP2 (Rn, Rd_SP), QL_I2SAMEX, 0),
-+ PAC_INSN ("brab", 0xd71f0c00, 0xfffffc00, branch_reg, OP2 (Rn, Rd_SP), QL_I2SAMEX, 0),
-+ PAC_INSN ("blraa", 0xd73f0800, 0xfffffc00, branch_reg, OP2 (Rn, Rd_SP), QL_I2SAMEX, 0),
-+ PAC_INSN ("blrab", 0xd73f0c00, 0xfffffc00, branch_reg, OP2 (Rn, Rd_SP), QL_I2SAMEX, 0),
-+ PAC_INSN ("braaz", 0xd61f081f, 0xfffffc1f, branch_reg, OP1 (Rn), QL_I1X, 0),
-+ PAC_INSN ("brabz", 0xd61f0c1f, 0xfffffc1f, branch_reg, OP1 (Rn), QL_I1X, 0),
-+ PAC_INSN ("blraaz", 0xd63f081f, 0xfffffc1f, branch_reg, OP1 (Rn), QL_I1X, 0),
-+ PAC_INSN ("blrabz", 0xd63f0c1f, 0xfffffc1f, branch_reg, OP1 (Rn), QL_I1X, 0),
-+ PAC_INSN ("retaa", 0xd65f0bff, 0xffffffff, branch_reg, OP0 (), {}, 0),
-+ PAC_INSN ("retab", 0xd65f0fff, 0xffffffff, branch_reg, OP0 (), {}, 0),
-+ PAC_INSN ("eretaa", 0xd69f0bff, 0xffffffff, branch_reg, OP0 (), {}, 0),
-+ PAC_INSN ("eretab", 0xd69f0fff, 0xffffffff, branch_reg, OP0 (), {}, 0),
- /* Compare & branch (immediate). */
- CORE_INSN ("cbz", 0x34000000, 0x7f000000, compbranch, 0, OP2 (Rt, ADDR_PCREL19), QL_R_PCREL, F_SF),
- CORE_INSN ("cbnz", 0x35000000, 0x7f000000, compbranch, 0, OP2 (Rt, ADDR_PCREL19), QL_R_PCREL, F_SF),
-@@ -2950,24 +3319,24 @@ struct aarch64_opcode aarch64_opcode_tab
- CORE_INSN ("clz", 0x5ac01000, 0x7ffffc00, dp_1src, 0, OP2 (Rd, Rn), QL_I2SAME, F_SF),
- CORE_INSN ("cls", 0x5ac01400, 0x7ffffc00, dp_1src, 0, OP2 (Rd, Rn), QL_I2SAME, F_SF),
- CORE_INSN ("rev32", 0xdac00800, 0xfffffc00, dp_1src, 0, OP2 (Rd, Rn), QL_I2SAMEX, 0),
-- V8_3_INSN ("pacia", 0xdac10000, 0xfffffc00, dp_1src, OP2 (Rd, Rn_SP), QL_I2SAMEX, 0),
-- V8_3_INSN ("pacib", 0xdac10400, 0xfffffc00, dp_1src, OP2 (Rd, Rn_SP), QL_I2SAMEX, 0),
-- V8_3_INSN ("pacda", 0xdac10800, 0xfffffc00, dp_1src, OP2 (Rd, Rn_SP), QL_I2SAMEX, 0),
-- V8_3_INSN ("pacdb", 0xdac10c00, 0xfffffc00, dp_1src, OP2 (Rd, Rn_SP), QL_I2SAMEX, 0),
-- V8_3_INSN ("autia", 0xdac11000, 0xfffffc00, dp_1src, OP2 (Rd, Rn_SP), QL_I2SAMEX, 0),
-- V8_3_INSN ("autib", 0xdac11400, 0xfffffc00, dp_1src, OP2 (Rd, Rn_SP), QL_I2SAMEX, 0),
-- V8_3_INSN ("autda", 0xdac11800, 0xfffffc00, dp_1src, OP2 (Rd, Rn_SP), QL_I2SAMEX, 0),
-- V8_3_INSN ("autdb", 0xdac11c00, 0xfffffc00, dp_1src, OP2 (Rd, Rn_SP), QL_I2SAMEX, 0),
-- V8_3_INSN ("paciza", 0xdac123e0, 0xffffffe0, dp_1src, OP1 (Rd), QL_I1X, 0),
-- V8_3_INSN ("pacizb", 0xdac127e0, 0xffffffe0, dp_1src, OP1 (Rd), QL_I1X, 0),
-- V8_3_INSN ("pacdza", 0xdac12be0, 0xffffffe0, dp_1src, OP1 (Rd), QL_I1X, 0),
-- V8_3_INSN ("pacdzb", 0xdac12fe0, 0xffffffe0, dp_1src, OP1 (Rd), QL_I1X, 0),
-- V8_3_INSN ("autiza", 0xdac133e0, 0xffffffe0, dp_1src, OP1 (Rd), QL_I1X, 0),
-- V8_3_INSN ("autizb", 0xdac137e0, 0xffffffe0, dp_1src, OP1 (Rd), QL_I1X, 0),
-- V8_3_INSN ("autdza", 0xdac13be0, 0xffffffe0, dp_1src, OP1 (Rd), QL_I1X, 0),
-- V8_3_INSN ("autdzb", 0xdac13fe0, 0xffffffe0, dp_1src, OP1 (Rd), QL_I1X, 0),
-- V8_3_INSN ("xpaci", 0xdac143e0, 0xffffffe0, dp_1src, OP1 (Rd), QL_I1X, 0),
-- V8_3_INSN ("xpacd", 0xdac147e0, 0xffffffe0, dp_1src, OP1 (Rd), QL_I1X, 0),
-+ PAC_INSN ("pacia", 0xdac10000, 0xfffffc00, dp_1src, OP2 (Rd, Rn_SP), QL_I2SAMEX, 0),
-+ PAC_INSN ("pacib", 0xdac10400, 0xfffffc00, dp_1src, OP2 (Rd, Rn_SP), QL_I2SAMEX, 0),
-+ PAC_INSN ("pacda", 0xdac10800, 0xfffffc00, dp_1src, OP2 (Rd, Rn_SP), QL_I2SAMEX, 0),
-+ PAC_INSN ("pacdb", 0xdac10c00, 0xfffffc00, dp_1src, OP2 (Rd, Rn_SP), QL_I2SAMEX, 0),
-+ PAC_INSN ("autia", 0xdac11000, 0xfffffc00, dp_1src, OP2 (Rd, Rn_SP), QL_I2SAMEX, 0),
-+ PAC_INSN ("autib", 0xdac11400, 0xfffffc00, dp_1src, OP2 (Rd, Rn_SP), QL_I2SAMEX, 0),
-+ PAC_INSN ("autda", 0xdac11800, 0xfffffc00, dp_1src, OP2 (Rd, Rn_SP), QL_I2SAMEX, 0),
-+ PAC_INSN ("autdb", 0xdac11c00, 0xfffffc00, dp_1src, OP2 (Rd, Rn_SP), QL_I2SAMEX, 0),
-+ PAC_INSN ("paciza", 0xdac123e0, 0xffffffe0, dp_1src, OP1 (Rd), QL_I1X, 0),
-+ PAC_INSN ("pacizb", 0xdac127e0, 0xffffffe0, dp_1src, OP1 (Rd), QL_I1X, 0),
-+ PAC_INSN ("pacdza", 0xdac12be0, 0xffffffe0, dp_1src, OP1 (Rd), QL_I1X, 0),
-+ PAC_INSN ("pacdzb", 0xdac12fe0, 0xffffffe0, dp_1src, OP1 (Rd), QL_I1X, 0),
-+ PAC_INSN ("autiza", 0xdac133e0, 0xffffffe0, dp_1src, OP1 (Rd), QL_I1X, 0),
-+ PAC_INSN ("autizb", 0xdac137e0, 0xffffffe0, dp_1src, OP1 (Rd), QL_I1X, 0),
-+ PAC_INSN ("autdza", 0xdac13be0, 0xffffffe0, dp_1src, OP1 (Rd), QL_I1X, 0),
-+ PAC_INSN ("autdzb", 0xdac13fe0, 0xffffffe0, dp_1src, OP1 (Rd), QL_I1X, 0),
-+ PAC_INSN ("xpaci", 0xdac143e0, 0xffffffe0, dp_1src, OP1 (Rd), QL_I1X, 0),
-+ PAC_INSN ("xpacd", 0xdac147e0, 0xffffffe0, dp_1src, OP1 (Rd), QL_I1X, 0),
- /* Data-processing (2 source). */
- CORE_INSN ("udiv", 0x1ac00800, 0x7fe0fc00, dp_2src, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF),
- CORE_INSN ("sdiv", 0x1ac00c00, 0x7fe0fc00, dp_2src, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF),
-@@ -2979,7 +3348,12 @@ struct aarch64_opcode aarch64_opcode_tab
- CORE_INSN ("asr", 0x1ac02800, 0x7fe0fc00, dp_2src, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_ALIAS),
- CORE_INSN ("rorv", 0x1ac02c00, 0x7fe0fc00, dp_2src, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_HAS_ALIAS),
- CORE_INSN ("ror", 0x1ac02c00, 0x7fe0fc00, dp_2src, 0, OP3 (Rd, Rn, Rm), QL_I3SAMER, F_SF | F_ALIAS),
-- V8_3_INSN ("pacga", 0x9ac03000, 0xffe0fc00, dp_2src, OP3 (Rd, Rn, Rm_SP), QL_I3SAMEX, 0),
-+ MEMTAG_INSN ("subp", 0x9ac00000, 0xffe0fc00, dp_2src, OP3 (Rd, Rn_SP, Rm_SP), QL_I3SAMEX, 0),
-+ MEMTAG_INSN ("subps", 0xbac00000, 0xffe0fc00, dp_2src, OP3 (Rd, Rn_SP, Rm_SP), QL_I3SAMEX, F_HAS_ALIAS),
-+ MEMTAG_INSN ("cmpp", 0xbac0001f, 0xffe0fc1f, dp_2src, OP2 (Rn_SP, Rm_SP), QL_I2SAMEX, F_ALIAS),
-+ MEMTAG_INSN ("irg", 0x9ac01000, 0xffe0fc00, dp_2src, OP3 (Rd_SP, Rn_SP, Rm), QL_I3SAMEX, F_OPD2_OPT | F_DEFAULT (0x1f)),
-+ MEMTAG_INSN ("gmi", 0x9ac01400, 0xffe0fc00, dp_2src, OP3 (Rd, Rn_SP, Rm), QL_I3SAMEX, 0),
-+ PAC_INSN ("pacga", 0x9ac03000, 0xffe0fc00, dp_2src, OP3 (Rd, Rn, Rm_SP), QL_I3SAMEX, 0),
- /* CRC instructions. */
- _CRC_INSN ("crc32b", 0x1ac04000, 0xffe0fc00, dp_2src, OP3 (Rd, Rn, Rm), QL_I3SAMEW, 0),
- _CRC_INSN ("crc32h", 0x1ac04400, 0xffe0fc00, dp_2src, OP3 (Rd, Rn, Rm), QL_I3SAMEW, 0),
-@@ -3010,6 +3384,7 @@ struct aarch64_opcode aarch64_opcode_tab
- CORE_INSN ("smc", 0xd4000003, 0xffe0001f, exception, 0, OP1 (EXCEPTION), {}, 0),
- CORE_INSN ("brk", 0xd4200000, 0xffe0001f, exception, 0, OP1 (EXCEPTION), {}, 0),
- CORE_INSN ("hlt", 0xd4400000, 0xffe0001f, exception, 0, OP1 (EXCEPTION), {}, 0),
-+ CORE_INSN ("udf", 0x00000000, 0xffff0000, exception, 0, OP1 (UNDEFINED), {}, 0),
- CORE_INSN ("dcps1", 0xd4a00001, 0xffe0001f, exception, 0, OP1 (EXCEPTION), {}, F_OPD0_OPT | F_DEFAULT (0)),
- CORE_INSN ("dcps2", 0xd4a00002, 0xffe0001f, exception, 0, OP1 (EXCEPTION), {}, F_OPD0_OPT | F_DEFAULT (0)),
- CORE_INSN ("dcps3", 0xd4a00003, 0xffe0001f, exception, 0, OP1 (EXCEPTION), {}, F_OPD0_OPT | F_DEFAULT (0)),
-@@ -3038,9 +3413,9 @@ struct aarch64_opcode aarch64_opcode_tab
- FF16_INSN ("fcvtas",0x1ee40000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF),
- __FP_INSN ("fcvtau",0x1e250000, 0x7f3ffc00, float2int, 0, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF),
- FF16_INSN ("fcvtau",0x1ee50000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF),
-- __FP_INSN ("fmov", 0x1e260000, 0x7f3ffc00, float2int, 0, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF),
-+ __FP_INSN ("fmov", 0x1e260000, 0x7f3ffc00, float2int, 0, OP2 (Rd, Fn), QL_FP2INT_FMOV, F_FPTYPE | F_SF),
- FF16_INSN ("fmov", 0x1ee60000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF),
-- __FP_INSN ("fmov", 0x1e270000, 0x7f3ffc00, float2int, 0, OP2 (Fd, Rn), QL_INT2FP, F_FPTYPE | F_SF),
-+ __FP_INSN ("fmov", 0x1e270000, 0x7f3ffc00, float2int, 0, OP2 (Fd, Rn), QL_INT2FP_FMOV, F_FPTYPE | F_SF),
- FF16_INSN ("fmov", 0x1ee70000, 0x7f3ffc00, float2int, OP2 (Fd, Rn), QL_INT2FP_H, F_FPTYPE | F_SF),
- __FP_INSN ("fcvtps",0x1e280000, 0x7f3ffc00, float2int, 0, OP2 (Rd, Fn), QL_FP2INT, F_FPTYPE | F_SF),
- FF16_INSN ("fcvtps",0x1ee80000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF),
-@@ -3056,7 +3431,7 @@ struct aarch64_opcode aarch64_opcode_tab
- FF16_INSN ("fcvtzu",0x1ef90000, 0x7f3ffc00, float2int, OP2 (Rd, Fn), QL_FP2INT_H, F_FPTYPE | F_SF),
- __FP_INSN ("fmov", 0x9eae0000, 0xfffffc00, float2int, 0, OP2 (Rd, VnD1), QL_XVD1, 0),
- __FP_INSN ("fmov", 0x9eaf0000, 0xfffffc00, float2int, 0, OP2 (VdD1, Rn), QL_VD1X, 0),
-- {"fjcvtzs", 0x1e7e0000, 0xfffffc00, float2int, 0, FP_V8_3, OP2 (Rd, Fn), QL_FP2INT_W_D, 0, 0, NULL },
-+ {"fjcvtzs", 0x1e7e0000, 0xfffffc00, float2int, 0, FP_V8_3, OP2 (Rd, Fn), QL_FP2INT_W_D, 0, 0, 0, NULL },
- /* Floating-point conditional compare. */
- __FP_INSN ("fccmp", 0x1e200400, 0xff200c10, floatccmp, 0, OP4 (Fn, Fm, NZCV, COND), QL_FCCMP, F_FPTYPE),
- FF16_INSN ("fccmp", 0x1ee00400, 0xff200c10, floatccmp, OP4 (Fn, Fm, NZCV, COND), QL_FCCMP_H, F_FPTYPE),
-@@ -3071,6 +3446,13 @@ struct aarch64_opcode aarch64_opcode_tab
- FF16_INSN ("fcmp", 0x1ee02008, 0xff20fc1f, floatcmp, OP2 (Fn, FPIMM0), QL_FP2_H, F_FPTYPE),
- __FP_INSN ("fcmpe", 0x1e202018, 0xff20fc1f, floatcmp, 0, OP2 (Fn, FPIMM0), QL_DST_SD,F_FPTYPE),
- FF16_INSN ("fcmpe", 0x1ee02018, 0xff20fc1f, floatcmp, OP2 (Fn, FPIMM0), QL_FP2_H, F_FPTYPE),
-+ /* Data processing instructions ARMv8.5-A. */
-+ FLAGMANIP_INSN ("xaflag", 0xd500403f, 0xffffffff, 0, OP0 (), {}, 0),
-+ FLAGMANIP_INSN ("axflag", 0xd500405f, 0xffffffff, 0, OP0 (), {}, 0),
-+ FRINTTS_INSN ("frint32z", 0x1e284000, 0xffbffc00, floatdp1, OP2 (Fd, Fn), QL_FP2, F_FPTYPE),
-+ FRINTTS_INSN ("frint32x", 0x1e28c000, 0xffbffc00, floatdp1, OP2 (Fd, Fn), QL_FP2, F_FPTYPE),
-+ FRINTTS_INSN ("frint64z", 0x1e294000, 0xffbffc00, floatdp1, OP2 (Fd, Fn), QL_FP2, F_FPTYPE),
-+ FRINTTS_INSN ("frint64x", 0x1e29c000, 0xffbffc00, floatdp1, OP2 (Fd, Fn), QL_FP2, F_FPTYPE),
- /* Floating-point data-processing (1 source). */
- __FP_INSN ("fmov", 0x1e204000, 0xff3ffc00, floatdp1, 0, OP2 (Fd, Fn), QL_FP2, F_FPTYPE),
- FF16_INSN ("fmov", 0x1ee04000, 0xff3ffc00, floatdp1, OP2 (Fd, Fn), QL_FP2_H, F_FPTYPE),
-@@ -3141,6 +3523,15 @@ struct aarch64_opcode aarch64_opcode_tab
- CORE_INSN ("str", 0xb8000400, 0xbfe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_R, F_GPRSIZE_IN_Q),
- CORE_INSN ("ldr", 0xb8400400, 0xbfe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_R, F_GPRSIZE_IN_Q),
- CORE_INSN ("ldrsw", 0xb8800400, 0xffe00400, ldst_imm9, 0, OP2 (Rt, ADDR_SIMM9), QL_LDST_X32, 0),
-+ /* Load/store Allocation Tag instructions. */
-+ MEMTAG_INSN ("stg", 0xd9200800, 0xffe00c00, ldst_unscaled, OP2 (Rt_SP, ADDR_SIMM13), QL_LDST_AT, 0),
-+ MEMTAG_INSN ("stzg", 0xd9600800, 0xffe00c00, ldst_unscaled, OP2 (Rt_SP, ADDR_SIMM13), QL_LDST_AT, 0),
-+ MEMTAG_INSN ("st2g", 0xd9a00800, 0xffe00c00, ldst_unscaled, OP2 (Rt_SP, ADDR_SIMM13), QL_LDST_AT, 0),
-+ MEMTAG_INSN ("stz2g",0xd9e00800, 0xffe00c00, ldst_unscaled, OP2 (Rt_SP, ADDR_SIMM13), QL_LDST_AT, 0),
-+ MEMTAG_INSN ("stg", 0xd9200400, 0xffe00400, ldst_imm9, OP2 (Rt_SP, ADDR_SIMM13), QL_LDST_AT, 0),
-+ MEMTAG_INSN ("stzg", 0xd9600400, 0xffe00400, ldst_imm9, OP2 (Rt_SP, ADDR_SIMM13), QL_LDST_AT, 0),
-+ MEMTAG_INSN ("st2g", 0xd9a00400, 0xffe00400, ldst_imm9, OP2 (Rt_SP, ADDR_SIMM13), QL_LDST_AT, 0),
-+ MEMTAG_INSN ("stz2g",0xd9e00400, 0xffe00400, ldst_imm9, OP2 (Rt_SP, ADDR_SIMM13), QL_LDST_AT, 0),
- /* Load/store register (unsigned immediate). */
- CORE_INSN ("strb", 0x39000000, 0xffc00000, ldst_pos, OP_STRB_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_W8, 0),
- CORE_INSN ("ldrb", 0x39400000, 0xffc00000, ldst_pos, OP_LDRB_POS, OP2 (Rt, ADDR_UIMM12), QL_LDST_W8, 0),
-@@ -3190,9 +3581,10 @@ struct aarch64_opcode aarch64_opcode_tab
- CORE_INSN ("ldur", 0xb8400000, 0xbfe00c00, ldst_unscaled, OP_LDUR, OP2 (Rt, ADDR_SIMM9), QL_LDST_R, F_GPRSIZE_IN_Q),
- CORE_INSN ("ldursw", 0xb8800000, 0xffe00c00, ldst_unscaled, OP_LDURSW, OP2 (Rt, ADDR_SIMM9), QL_LDST_X32, 0),
- CORE_INSN ("prfum", 0xf8800000, 0xffe00c00, ldst_unscaled, OP_PRFUM, OP2 (PRFOP, ADDR_SIMM9), QL_LDST_PRFM, 0),
-+ MEMTAG_INSN ("ldg", 0xd9600000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_SIMM13), QL_LDG, 0),
- /* Load/store register (scaled signed immediate). */
-- V8_3_INSN ("ldraa", 0xf8200400, 0xffa00400, ldst_imm10, OP2 (Rt, ADDR_SIMM10), QL_X1NIL, 0),
-- V8_3_INSN ("ldrab", 0xf8a00400, 0xffa00400, ldst_imm10, OP2 (Rt, ADDR_SIMM10), QL_X1NIL, 0),
-+ PAC_INSN ("ldraa", 0xf8200400, 0xffa00400, ldst_imm10, OP2 (Rt, ADDR_SIMM10), QL_X1NIL, 0),
-+ PAC_INSN ("ldrab", 0xf8a00400, 0xffa00400, ldst_imm10, OP2 (Rt, ADDR_SIMM10), QL_X1NIL, 0),
- /* Load/store exclusive. */
- CORE_INSN ("stxrb", 0x8007c00, 0xffe08000, ldstexcl, 0, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0),
- CORE_INSN ("stlxrb", 0x800fc00, 0xffe08000, ldstexcl, 0, OP3 (Rs, Rt, ADDR_SIMPLE), QL_W2_LDST_EXC, 0),
-@@ -3205,7 +3597,7 @@ struct aarch64_opcode aarch64_opcode_tab
- CORE_INSN ("ldxrh", 0x485f7c00, 0xffe08000, ldstexcl, 0, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0),
- CORE_INSN ("ldaxrh", 0x485ffc00, 0xffe08000, ldstexcl, 0, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0),
- CORE_INSN ("stlrh", 0x489ffc00, 0xffe08000, ldstexcl, 0, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0),
-- CORE_INSN ("ldarh", 0x48dffc00, 0xffeffc00, ldstexcl, 0, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0),
-+ CORE_INSN ("ldarh", 0x48dffc00, 0xfffffc00, ldstexcl, 0, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0),
- CORE_INSN ("stxr", 0x88007c00, 0xbfe08000, ldstexcl, 0, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2_LDST_EXC, F_GPRSIZE_IN_Q),
- CORE_INSN ("stlxr", 0x8800fc00, 0xbfe08000, ldstexcl, 0, OP3 (Rs, Rt, ADDR_SIMPLE), QL_R2_LDST_EXC, F_GPRSIZE_IN_Q),
- CORE_INSN ("stxp", 0x88200000, 0xbfe08000, ldstexcl, 0, OP4 (Rs, Rt, Rt2, ADDR_SIMPLE), QL_R3_LDST_EXC, F_GPRSIZE_IN_Q),
-@@ -3219,6 +3611,9 @@ struct aarch64_opcode aarch64_opcode_tab
- RCPC_INSN ("ldaprb", 0x38bfc000, 0xfffffc00, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0),
- RCPC_INSN ("ldaprh", 0x78bfc000, 0xfffffc00, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0),
- RCPC_INSN ("ldapr", 0xb8bfc000, 0xbffffc00, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q),
-+ MEMTAG_INSN ("ldgm", 0xd9e00000, 0xfffffc00, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_X1NIL, 0),
-+ MEMTAG_INSN ("stgm", 0xd9a00000, 0xfffffc00, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_X1NIL, 0),
-+ MEMTAG_INSN ("stzgm", 0xd9200000, 0xfffffc00, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_X1NIL, 0),
- /* Limited Ordering Regions load/store instructions. */
- _LOR_INSN ("ldlar", 0x88df7c00, 0xbfe08000, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q),
- _LOR_INSN ("ldlarb", 0x08df7c00, 0xffe08000, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0),
-@@ -3236,18 +3631,25 @@ struct aarch64_opcode aarch64_opcode_tab
- CORE_INSN ("ldp", 0x29400000, 0x7ec00000, ldstpair_off, 0, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF),
- CORE_INSN ("stp", 0x2d000000, 0x3fc00000, ldstpair_off, 0, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0),
- CORE_INSN ("ldp", 0x2d400000, 0x3fc00000, ldstpair_off, 0, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0),
-- {"ldpsw", 0x69400000, 0xffc00000, ldstpair_off, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_X32, 0, 0, VERIFIER (ldpsw)},
-+ {"ldpsw", 0x69400000, 0xffc00000, ldstpair_off, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_X32, 0, 0, 0, VERIFIER (ldpsw)},
-+ MEMTAG_INSN ("stgp", 0x69000000, 0xffc00000, ldstpair_off, OP3 (Rt, Rt2, ADDR_SIMM11), QL_STGP, 0),
- /* Load/store register pair (indexed). */
- CORE_INSN ("stp", 0x28800000, 0x7ec00000, ldstpair_indexed, 0, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF),
- CORE_INSN ("ldp", 0x28c00000, 0x7ec00000, ldstpair_indexed, 0, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_SF),
- CORE_INSN ("stp", 0x2c800000, 0x3ec00000, ldstpair_indexed, 0, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0),
- CORE_INSN ("ldp", 0x2cc00000, 0x3ec00000, ldstpair_indexed, 0, OP3 (Ft, Ft2, ADDR_SIMM7), QL_LDST_PAIR_FP, 0),
-- {"ldpsw", 0x68c00000, 0xfec00000, ldstpair_indexed, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_X32, 0, 0, VERIFIER (ldpsw)},
-+ {"ldpsw", 0x68c00000, 0xfec00000, ldstpair_indexed, 0, CORE, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_X32, 0, 0, 0, VERIFIER (ldpsw)},
-+ MEMTAG_INSN ("stgp", 0x68800000, 0xfec00000, ldstpair_indexed, OP3 (Rt, Rt2, ADDR_SIMM11), QL_STGP, 0),
- /* Load register (literal). */
- CORE_INSN ("ldr", 0x18000000, 0xbf000000, loadlit, OP_LDR_LIT, OP2 (Rt, ADDR_PCREL19), QL_R_PCREL, F_GPRSIZE_IN_Q),
- CORE_INSN ("ldr", 0x1c000000, 0x3f000000, loadlit, OP_LDRV_LIT, OP2 (Ft, ADDR_PCREL19), QL_FP_PCREL, 0),
- CORE_INSN ("ldrsw", 0x98000000, 0xff000000, loadlit, OP_LDRSW_LIT, OP2 (Rt, ADDR_PCREL19), QL_X_PCREL, 0),
- CORE_INSN ("prfm", 0xd8000000, 0xff000000, loadlit, OP_PRFM_LIT, OP2 (PRFOP, ADDR_PCREL19), QL_PRFM_PCREL, 0),
-+ /* Atomic 64-byte load/store in Armv8.7. */
-+ _LS64_INSN ("ld64b", 0xf83fd000, 0xfffffc00, ldstexcl, OP2 (Rt_LS64, ADDR_SIMPLE), QL_X1NIL, 0),
-+ _LS64_INSN ("st64b", 0xf83f9000, 0xfffffc00, ldstexcl, OP2 (Rt_LS64, ADDR_SIMPLE), QL_X1NIL, 0),
-+ _LS64_INSN ("st64bv", 0xf820b000, 0xffe0fc00, ldstexcl, OP3 (Rs, Rt_LS64, ADDR_SIMPLE), QL_X2NIL, 0),
-+ _LS64_INSN ("st64bv0", 0xf820a000, 0xffe0fc00, ldstexcl, OP3 (Rs, Rt_LS64, ADDR_SIMPLE), QL_X2NIL, 0),
- /* Logical (immediate). */
- CORE_INSN ("and", 0x12000000, 0x7f800000, log_imm, 0, OP3 (Rd_SP, Rn, LIMM), QL_R2NIL, F_HAS_ALIAS | F_SF),
- CORE_INSN ("bic", 0x12000000, 0x7f800000, log_imm, OP_BIC, OP3 (Rd_SP, Rn, LIMM), QL_R2NIL, F_ALIAS | F_PSEUDO | F_SF),
-@@ -3260,7 +3662,7 @@ struct aarch64_opcode aarch64_opcode_tab
- CORE_INSN ("and", 0xa000000, 0x7f200000, log_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_SF),
- CORE_INSN ("bic", 0xa200000, 0x7f200000, log_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_SF),
- CORE_INSN ("orr", 0x2a000000, 0x7f200000, log_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF),
-- CORE_INSN ("mov", 0x2a0003e0, 0x7f2003e0, log_shift, 0, OP2 (Rd, Rm_SFT), QL_I2SAMER, F_ALIAS | F_SF),
-+ CORE_INSN ("mov", 0x2a0003e0, 0x7fe0ffe0, log_shift, 0, OP2 (Rd, Rm_SFT), QL_I2SAMER, F_ALIAS | F_SF),
- CORE_INSN ("uxtw", 0x2a0003e0, 0x7f2003e0, log_shift, OP_UXTW, OP2 (Rd, Rm), QL_I2SAMEW, F_ALIAS | F_PSEUDO),
- CORE_INSN ("orn", 0x2a200000, 0x7f200000, log_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF),
- CORE_INSN ("mvn", 0x2a2003e0, 0x7f2003e0, log_shift, 0, OP2 (Rd, Rm_SFT), QL_I2SAMER, F_ALIAS | F_SF),
-@@ -3451,43 +3853,69 @@ struct aarch64_opcode aarch64_opcode_tab
- /* PC-rel. addressing. */
- CORE_INSN ("adr", 0x10000000, 0x9f000000, pcreladdr, 0, OP2 (Rd, ADDR_PCREL21), QL_ADRP, 0),
- CORE_INSN ("adrp", 0x90000000, 0x9f000000, pcreladdr, 0, OP2 (Rd, ADDR_ADRP), QL_ADRP, 0),
-+ /* TME Instructions. */
-+ _TME_INSN ("tstart", 0xd5233060, 0xffffffe0, 0, 0, OP1 (Rd), QL_I1X, 0),
-+ _TME_INSN ("tcommit", 0xd503307f, 0xffffffff, 0, 0, OP0 (), {}, 0),
-+ _TME_INSN ("ttest", 0xd5233160, 0xffffffe0, 0, 0, OP1 (Rd), QL_I1X, 0),
-+ _TME_INSN ("tcancel", 0xd4600000, 0xffe0001f, 0, 0, OP1 (TME_UIMM16), QL_IMM_NIL, 0),
- /* System. */
-- CORE_INSN ("msr", 0xd500401f, 0xfff8f01f, ic_system, 0, OP2 (PSTATEFIELD, UIMM4), {}, 0),
-+ CORE_INSN ("msr", 0xd500401f, 0xfff8f01f, ic_system, 0, OP2 (PSTATEFIELD, UIMM4), {}, F_SYS_WRITE),
- CORE_INSN ("hint",0xd503201f, 0xfffff01f, ic_system, 0, OP1 (UIMM7), {}, F_HAS_ALIAS),
- CORE_INSN ("nop", 0xd503201f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
- CORE_INSN ("csdb",0xd503229f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
-+ CORE_INSN ("bti",0xd503241f, 0xffffff3f, ic_system, 0, OP1 (BTI_TARGET), {}, F_ALIAS | F_OPD0_OPT | F_DEFAULT (0x0)),
- CORE_INSN ("yield", 0xd503203f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
- CORE_INSN ("wfe", 0xd503205f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
- CORE_INSN ("wfi", 0xd503207f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
- CORE_INSN ("sev", 0xd503209f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
- CORE_INSN ("sevl",0xd50320bf, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
-- V8_3_INSN ("xpaclri", 0xd50320ff, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS),
-- V8_3_INSN ("pacia1716", 0xd503211f, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS),
-- V8_3_INSN ("pacib1716", 0xd503215f, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS),
-- V8_3_INSN ("autia1716", 0xd503219f, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS),
-- V8_3_INSN ("autib1716", 0xd50321df, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS),
-- {"esb", 0xd503221f, 0xffffffff, ic_system, 0, RAS, OP0 (), {}, F_ALIAS, 0, NULL},
-- {"psb", 0xd503223f, 0xffffffff, ic_system, 0, STAT_PROFILE, OP1 (BARRIER_PSB), {}, F_ALIAS, 0, NULL},
-+ CORE_INSN ("dgh", 0xd50320df, 0xffffffff, ic_system, 0, OP0 (), {}, 0),
-+ CORE_INSN ("xpaclri", 0xd50320ff, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
-+ CORE_INSN ("pacia1716", 0xd503211f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
-+ CORE_INSN ("pacib1716", 0xd503215f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
-+ CORE_INSN ("autia1716", 0xd503219f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
-+ CORE_INSN ("autib1716", 0xd50321df, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
-+ CORE_INSN ("esb", 0xd503221f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
-+ CORE_INSN ("psb", 0xd503223f, 0xffffffff, ic_system, 0, OP1 (BARRIER_PSB), {}, F_ALIAS),
-+ CORE_INSN ("tsb", 0xd503225f, 0xffffffff, ic_system, 0, OP1 (BARRIER_PSB), {}, F_ALIAS),
- CORE_INSN ("clrex", 0xd503305f, 0xfffff0ff, ic_system, 0, OP1 (UIMM4), {}, F_OPD0_OPT | F_DEFAULT (0xF)),
-- CORE_INSN ("dsb", 0xd503309f, 0xfffff0ff, ic_system, 0, OP1 (BARRIER), {}, 0),
-+ CORE_INSN ("dsb", 0xd503309f, 0xfffff0ff, ic_system, 0, OP1 (BARRIER), {}, F_HAS_ALIAS),
-+ V8_7_INSN ("dsb", 0xd503323f, 0xfffff3ff, ic_system, OP1 (BARRIER_DSB_NXS), {}, F_HAS_ALIAS),
-+ V8_R_INSN ("dfb", 0xd5033c9f, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS),
-+ CORE_INSN ("ssbb", 0xd503309f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
-+ CORE_INSN ("pssbb", 0xd503349f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
- CORE_INSN ("dmb", 0xd50330bf, 0xfffff0ff, ic_system, 0, OP1 (BARRIER), {}, 0),
- CORE_INSN ("isb", 0xd50330df, 0xfffff0ff, ic_system, 0, OP1 (BARRIER_ISB), {}, F_OPD0_OPT | F_DEFAULT (0xF)),
-+ SB_INSN ("sb", 0xd50330ff, 0xffffffff, ic_system, OP0 (), {}, 0),
- CORE_INSN ("sys", 0xd5080000, 0xfff80000, ic_system, 0, OP5 (UIMM3_OP1, CRn, CRm, UIMM3_OP2, Rt), QL_SYS, F_HAS_ALIAS | F_OPD4_OPT | F_DEFAULT (0x1F)),
- CORE_INSN ("at", 0xd5080000, 0xfff80000, ic_system, 0, OP2 (SYSREG_AT, Rt), QL_SRC_X, F_ALIAS),
- CORE_INSN ("dc", 0xd5080000, 0xfff80000, ic_system, 0, OP2 (SYSREG_DC, Rt), QL_SRC_X, F_ALIAS),
- CORE_INSN ("ic", 0xd5080000, 0xfff80000, ic_system, 0, OP2 (SYSREG_IC, Rt_SYS), QL_SRC_X, F_ALIAS | F_OPD1_OPT | F_DEFAULT (0x1F)),
- CORE_INSN ("tlbi",0xd5080000, 0xfff80000, ic_system, 0, OP2 (SYSREG_TLBI, Rt_SYS), QL_SRC_X, F_ALIAS | F_OPD1_OPT | F_DEFAULT (0x1F)),
-- CORE_INSN ("msr", 0xd5000000, 0xffe00000, ic_system, 0, OP2 (SYSREG, Rt), QL_SRC_X, 0),
-+ V8_7_INSN ("wfet", 0xd5031000, 0xffffffe0, ic_system, OP1 (Rd), QL_I1X, F_HAS_ALIAS),
-+ V8_7_INSN ("wfit", 0xd5031020, 0xffffffe0, ic_system, OP1 (Rd), QL_I1X, F_HAS_ALIAS),
-+ PREDRES_INSN ("cfp", 0xd50b7380, 0xffffffe0, ic_system, OP2 (SYSREG_SR, Rt), QL_SRC_X, F_ALIAS),
-+ PREDRES_INSN ("dvp", 0xd50b73a0, 0xffffffe0, ic_system, OP2 (SYSREG_SR, Rt), QL_SRC_X, F_ALIAS),
-+ PREDRES_INSN ("cpp", 0xd50b73e0, 0xffffffe0, ic_system, OP2 (SYSREG_SR, Rt), QL_SRC_X, F_ALIAS),
-+ /* Armv8.4-a flag setting instruction, However this encoding has an encoding clash with the msr
-+ below it. Usually we can resolve this by setting an alias condition on the flags, however that
-+ depends on the disassembly masks to be able to quickly find the alias. The problem is the
-+ cfinv instruction has no arguments, so all bits are set in the mask. Which means it will
-+ potentially alias with too many instructions and so the tree can't be constructed. As a work
-+ around we just place cfinv before msr. This means the order between these two shouldn't be
-+ changed. */
-+ FLAGM_INSN ("cfinv", 0xd500401f, 0xffffffff, ic_system, OP0 (), {}, 0),
-+ CORE_INSN ("msr", 0xd5000000, 0xffe00000, ic_system, 0, OP2 (SYSREG, Rt), QL_SRC_X, F_SYS_WRITE),
- CORE_INSN ("sysl",0xd5280000, 0xfff80000, ic_system, 0, OP5 (Rt, UIMM3_OP1, CRn, CRm, UIMM3_OP2), QL_SYSL, 0),
-- CORE_INSN ("mrs", 0xd5200000, 0xffe00000, ic_system, 0, OP2 (Rt, SYSREG), QL_DST_X, 0),
-- V8_3_INSN ("paciaz", 0xd503231f, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS),
-- V8_3_INSN ("paciasp", 0xd503233f, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS),
-- V8_3_INSN ("pacibz", 0xd503235f, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS),
-- V8_3_INSN ("pacibsp", 0xd503237f, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS),
-- V8_3_INSN ("autiaz", 0xd503239f, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS),
-- V8_3_INSN ("autiasp", 0xd50323bf, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS),
-- V8_3_INSN ("autibz", 0xd50323df, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS),
-- V8_3_INSN ("autibsp", 0xd50323ff, 0xffffffff, ic_system, OP0 (), {}, F_ALIAS),
-+ CORE_INSN ("mrs", 0xd5200000, 0xffe00000, ic_system, 0, OP2 (Rt, SYSREG), QL_DST_X, F_SYS_READ),
-+ CORE_INSN ("paciaz", 0xd503231f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
-+ CORE_INSN ("paciasp", 0xd503233f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
-+ CORE_INSN ("pacibz", 0xd503235f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
-+ CORE_INSN ("pacibsp", 0xd503237f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
-+ CORE_INSN ("autiaz", 0xd503239f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
-+ CORE_INSN ("autiasp", 0xd50323bf, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
-+ CORE_INSN ("autibz", 0xd50323df, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
-+ CORE_INSN ("autibsp", 0xd50323ff, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS),
- /* Test & branch (immediate). */
- CORE_INSN ("tbz", 0x36000000, 0x7f000000, testbranch, 0, OP3 (Rt, BIT_NUM, ADDR_PCREL14), QL_PCREL_14, 0),
- CORE_INSN ("tbnz",0x37000000, 0x7f000000, testbranch, 0, OP3 (Rt, BIT_NUM, ADDR_PCREL14), QL_PCREL_14, 0),
-@@ -3510,7 +3938,7 @@ struct aarch64_opcode aarch64_opcode_tab
- CORE_INSN ("ble", 0x5400000d, 0xff00001f, condbranch, 0, OP1 (ADDR_PCREL19), QL_PCREL_NIL, F_ALIAS | F_PSEUDO),
- /* SVE instructions. */
- _SVE_INSN ("fmov", 0x2539c000, 0xff3fe000, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_FPIMM8), OP_SVE_VU_HSD, F_ALIAS, 0),
-- _SVE_INSN ("fmov", 0x0510c000, 0xff30e000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg4_16, SVE_FPIMM8), OP_SVE_VMU_HSD, F_ALIAS, 0),
-+ _SVE_INSNC ("fmov", 0x0510c000, 0xff30e000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg4_16, SVE_FPIMM8), OP_SVE_VMU_HSD, F_ALIAS, C_SCAN_MOVPRFX, 0),
- _SVE_INSN ("mov", 0x04603000, 0xffe0fc00, sve_misc, OP_MOV_Z_Z, OP2 (SVE_Zd, SVE_Zn), OP_SVE_DD, F_ALIAS | F_MISC, 0),
- _SVE_INSN ("mov", 0x05202000, 0xff20fc00, sve_index, OP_MOV_Z_V, OP2 (SVE_Zd, SVE_VZn), OP_SVE_VV_BHSDQ, F_ALIAS | F_MISC, 0),
- _SVE_INSN ("mov", 0x05203800, 0xff3ffc00, sve_size_bhsd, 0, OP2 (SVE_Zd, Rn_SP), OP_SVE_VR_BHSD, F_ALIAS, 0),
-@@ -3518,40 +3946,40 @@ struct aarch64_opcode aarch64_opcode_tab
- _SVE_INSN ("mov", 0x05202000, 0xff20fc00, sve_index, OP_MOV_Z_Zi, OP2 (SVE_Zd, SVE_Zn_INDEX), OP_SVE_VV_BHSDQ, F_ALIAS | F_MISC, 0),
- _SVE_INSN ("mov", 0x05c00000, 0xfffc0000, sve_limm, 0, OP2 (SVE_Zd, SVE_LIMM_MOV), OP_SVE_VU_BHSD, F_ALIAS, 0),
- _SVE_INSN ("mov", 0x2538c000, 0xff3fc000, sve_size_bhsd, 0, OP2 (SVE_Zd, SVE_ASIMM), OP_SVE_VU_BHSD, F_ALIAS, 0),
-- _SVE_INSN ("mov", 0x05208000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Vn), OP_SVE_VMV_BHSD, F_ALIAS, 0),
-+ _SVE_INSNC ("mov", 0x05208000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Vn), OP_SVE_VMV_BHSD, F_ALIAS, C_SCAN_MOVPRFX, 0),
- _SVE_INSN ("mov", 0x0520c000, 0xff20c000, sve_size_bhsd, OP_MOV_Z_P_Z, OP3 (SVE_Zd, SVE_Pg4_10, SVE_Zn), OP_SVE_VMV_BHSD, F_ALIAS | F_MISC, 0),
-- _SVE_INSN ("mov", 0x0528a000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Pg3, Rn_SP), OP_SVE_VMR_BHSD, F_ALIAS, 0),
-+ _SVE_INSNC ("mov", 0x0528a000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Pg3, Rn_SP), OP_SVE_VMR_BHSD, F_ALIAS, C_SCAN_MOVPRFX, 0),
- _SVE_INSN ("mov", 0x25004000, 0xfff0c210, sve_misc, OP_MOVZ_P_P_P, OP3 (SVE_Pd, SVE_Pg4_10, SVE_Pn), OP_SVE_BZB, F_ALIAS | F_MISC, 0),
- _SVE_INSN ("mov", 0x25004210, 0xfff0c210, sve_misc, OP_MOVM_P_P_P, OP3 (SVE_Pd, SVE_Pg4_10, SVE_Pn), OP_SVE_BMB, F_ALIAS | F_MISC, 0),
-- _SVE_INSN ("mov", 0x05100000, 0xff308000, sve_cpy, 0, OP3 (SVE_Zd, SVE_Pg4_16, SVE_ASIMM), OP_SVE_VPU_BHSD, F_ALIAS, 0),
-+ _SVE_INSNC ("mov", 0x05100000, 0xff308000, sve_cpy, 0, OP3 (SVE_Zd, SVE_Pg4_16, SVE_ASIMM), OP_SVE_VPU_BHSD, F_ALIAS, C_SCAN_MOVPRFX, 0),
- _SVE_INSN ("movs", 0x25c04000, 0xfff0c210, sve_misc, OP_MOVS_P_P, OP2 (SVE_Pd, SVE_Pn), OP_SVE_BB, F_ALIAS | F_MISC, 0),
- _SVE_INSN ("movs", 0x25404000, 0xfff0c210, sve_misc, OP_MOVZS_P_P_P, OP3 (SVE_Pd, SVE_Pg4_10, SVE_Pn), OP_SVE_BZB, F_ALIAS | F_MISC, 0),
- _SVE_INSN ("not", 0x25004200, 0xfff0c210, sve_misc, OP_NOT_P_P_P_Z, OP3 (SVE_Pd, SVE_Pg4_10, SVE_Pn), OP_SVE_BZB, F_ALIAS | F_MISC, 0),
- _SVE_INSN ("nots", 0x25404200, 0xfff0c210, sve_misc, OP_NOTS_P_P_P_Z, OP3 (SVE_Pd, SVE_Pg4_10, SVE_Pn), OP_SVE_BZB, F_ALIAS | F_MISC, 0),
-- _SVE_INSN ("abs", 0x0416a000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_BHSD, 0, 0),
-+ _SVE_INSNC ("abs", 0x0416a000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_BHSD, 0, C_SCAN_MOVPRFX, 0),
- _SVE_INSN ("add", 0x04200000, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0),
-- _SVE_INSN ("add", 0x2520c000, 0xff3fc000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zd, SVE_AIMM), OP_SVE_VVU_BHSD, 0, 1),
-- _SVE_INSN ("add", 0x04000000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, 2),
-+ _SVE_INSNC ("add", 0x2520c000, 0xff3fc000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zd, SVE_AIMM), OP_SVE_VVU_BHSD, 0, C_SCAN_MOVPRFX, 1),
-+ _SVE_INSNC ("add", 0x04000000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2),
- _SVE_INSN ("addpl", 0x04605000, 0xffe0f800, sve_misc, 0, OP3 (Rd_SP, SVE_Rn_SP, SVE_SIMM6), OP_SVE_XXU, 0, 0),
- _SVE_INSN ("addvl", 0x04205000, 0xffe0f800, sve_misc, 0, OP3 (Rd_SP, SVE_Rn_SP, SVE_SIMM6), OP_SVE_XXU, 0, 0),
- _SVE_INSN ("adr", 0x0420a000, 0xffe0f000, sve_misc, 0, OP2 (SVE_Zd, SVE_ADDR_ZZ_SXTW), OP_SVE_DD, 0, 0),
- _SVE_INSN ("adr", 0x0460a000, 0xffe0f000, sve_misc, 0, OP2 (SVE_Zd, SVE_ADDR_ZZ_UXTW), OP_SVE_DD, 0, 0),
- _SVE_INSN ("adr", 0x04a0a000, 0xffa0f000, sve_size_sd, 0, OP2 (SVE_Zd, SVE_ADDR_ZZ_LSL), OP_SVE_VV_SD, 0, 0),
- _SVE_INSN ("and", 0x04203000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_DDD, 0, 0),
-- _SVE_INSN ("and", 0x05800000, 0xfffc0000, sve_limm, 0, OP3 (SVE_Zd, SVE_Zd, SVE_LIMM), OP_SVE_VVU_BHSD, F_HAS_ALIAS, 1),
-- _SVE_INSN ("and", 0x041a0000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, 2),
-+ _SVE_INSNC ("and", 0x05800000, 0xfffc0000, sve_limm, 0, OP3 (SVE_Zd, SVE_Zd, SVE_LIMM), OP_SVE_VVU_BHSD, F_HAS_ALIAS, C_SCAN_MOVPRFX, 1),
-+ _SVE_INSNC ("and", 0x041a0000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2),
- _SVE_INSN ("and", 0x25004000, 0xfff0c210, sve_misc, 0, OP4 (SVE_Pd, SVE_Pg4_10, SVE_Pn, SVE_Pm), OP_SVE_BZBB, F_HAS_ALIAS, 0),
- _SVE_INSN ("ands", 0x25404000, 0xfff0c210, sve_misc, 0, OP4 (SVE_Pd, SVE_Pg4_10, SVE_Pn, SVE_Pm), OP_SVE_BZBB, F_HAS_ALIAS, 0),
- _SVE_INSN ("andv", 0x041a2000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_BHSD, 0, 0),
- _SVE_INSN ("asr", 0x04208000, 0xff20fc00, sve_size_bhs, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVD_BHS, 0, 0),
- _SVE_INSN ("asr", 0x04209000, 0xff20fc00, sve_shift_unpred, 0, OP3 (SVE_Zd, SVE_Zn, SVE_SHRIMM_UNPRED), OP_SVE_VVU_BHSD, 0, 0),
-- _SVE_INSN ("asr", 0x04108000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, 2),
-- _SVE_INSN ("asr", 0x04188000, 0xff3fe000, sve_size_bhs, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVD_BHS, 0, 2),
-- _SVE_INSN ("asr", 0x04008000, 0xff3fe000, sve_shift_pred, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_SHRIMM_PRED), OP_SVE_VMVU_BHSD, 0, 2),
-- _SVE_INSN ("asrd", 0x04048000, 0xff3fe000, sve_shift_pred, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_SHRIMM_PRED), OP_SVE_VMVU_BHSD, 0, 2),
-- _SVE_INSN ("asrr", 0x04148000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, 2),
-+ _SVE_INSNC ("asr", 0x04108000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2),
-+ _SVE_INSNC ("asr", 0x04188000, 0xff3fe000, sve_size_bhs, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVD_BHS, 0, C_SCAN_MOVPRFX, 2),
-+ _SVE_INSNC ("asr", 0x04008000, 0xff3fe000, sve_shift_pred, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_SHRIMM_PRED), OP_SVE_VMVU_BHSD, 0, C_SCAN_MOVPRFX, 2),
-+ _SVE_INSNC ("asrd", 0x04048000, 0xff3fe000, sve_shift_pred, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_SHRIMM_PRED), OP_SVE_VMVU_BHSD, 0, C_SCAN_MOVPRFX, 2),
-+ _SVE_INSNC ("asrr", 0x04148000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2),
- _SVE_INSN ("bic", 0x04e03000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_DDD, 0, 0),
-- _SVE_INSN ("bic", 0x041b0000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, 2),
-+ _SVE_INSNC ("bic", 0x041b0000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2),
- _SVE_INSN ("bic", 0x25004010, 0xfff0c210, sve_misc, 0, OP4 (SVE_Pd, SVE_Pg4_10, SVE_Pn, SVE_Pm), OP_SVE_BZBB, 0, 0),
- _SVE_INSN ("bics", 0x25404010, 0xfff0c210, sve_misc, 0, OP4 (SVE_Pd, SVE_Pg4_10, SVE_Pn, SVE_Pm), OP_SVE_BZBB, 0, 0),
- _SVE_INSN ("brka", 0x25104000, 0xffffc200, sve_pred_zm, 0, OP3 (SVE_Pd, SVE_Pg4_10, SVE_Pn), OP_SVE_BPB, 0, 0),
-@@ -3564,14 +3992,14 @@ struct aarch64_opcode aarch64_opcode_tab
- _SVE_INSN ("brkpas", 0x2540c000, 0xfff0c210, sve_misc, 0, OP4 (SVE_Pd, SVE_Pg4_10, SVE_Pn, SVE_Pm), OP_SVE_BZBB, 0, 0),
- _SVE_INSN ("brkpb", 0x2500c010, 0xfff0c210, sve_misc, 0, OP4 (SVE_Pd, SVE_Pg4_10, SVE_Pn, SVE_Pm), OP_SVE_BZBB, 0, 0),
- _SVE_INSN ("brkpbs", 0x2540c010, 0xfff0c210, sve_misc, 0, OP4 (SVE_Pd, SVE_Pg4_10, SVE_Pn, SVE_Pm), OP_SVE_BZBB, 0, 0),
-- _SVE_INSN ("clasta", 0x05288000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VUVV_BHSD, 0, 2),
-+ _SVE_INSNC ("clasta", 0x05288000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VUVV_BHSD, 0, C_SCAN_MOVPRFX, 2),
- _SVE_INSN ("clasta", 0x052a8000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Vd, SVE_Pg3, SVE_Vd, SVE_Zm_5), OP_SVE_VUVV_BHSD, 0, 2),
- _SVE_INSN ("clasta", 0x0530a000, 0xff3fe000, sve_size_bhsd, 0, OP4 (Rd, SVE_Pg3, Rd, SVE_Zm_5), OP_SVE_RURV_BHSD, 0, 2),
-- _SVE_INSN ("clastb", 0x05298000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VUVV_BHSD, 0, 2),
-+ _SVE_INSNC ("clastb", 0x05298000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VUVV_BHSD, 0, C_SCAN_MOVPRFX, 2),
- _SVE_INSN ("clastb", 0x052b8000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Vd, SVE_Pg3, SVE_Vd, SVE_Zm_5), OP_SVE_VUVV_BHSD, 0, 2),
- _SVE_INSN ("clastb", 0x0531a000, 0xff3fe000, sve_size_bhsd, 0, OP4 (Rd, SVE_Pg3, Rd, SVE_Zm_5), OP_SVE_RURV_BHSD, 0, 2),
-- _SVE_INSN ("cls", 0x0418a000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_BHSD, 0, 0),
-- _SVE_INSN ("clz", 0x0419a000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_BHSD, 0, 0),
-+ _SVE_INSNC ("cls", 0x0418a000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_BHSD, 0, C_SCAN_MOVPRFX, 0),
-+ _SVE_INSNC ("clz", 0x0419a000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_BHSD, 0, C_SCAN_MOVPRFX, 0),
- _SVE_INSN ("cmpeq", 0x24002000, 0xff20e010, sve_size_bhs, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVD_BHS, 0, 0),
- _SVE_INSN ("cmpeq", 0x2400a000, 0xff20e010, sve_size_bhsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVV_BHSD, 0, 0),
- _SVE_INSN ("cmpeq", 0x25008000, 0xff20e010, sve_size_bhsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SIMM5), OP_SVE_VZVU_BHSD, 0, 0),
-@@ -3598,52 +4026,52 @@ struct aarch64_opcode aarch64_opcode_tab
- _SVE_INSN ("cmpne", 0x24002010, 0xff20e010, sve_size_bhs, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVD_BHS, 0, 0),
- _SVE_INSN ("cmpne", 0x2400a010, 0xff20e010, sve_size_bhsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVV_BHSD, 0, 0),
- _SVE_INSN ("cmpne", 0x25008010, 0xff20e010, sve_size_bhsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SIMM5), OP_SVE_VZVU_BHSD, 0, 0),
-- _SVE_INSN ("cnot", 0x041ba000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_BHSD, 0, 0),
-- _SVE_INSN ("cnt", 0x041aa000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_BHSD, 0, 0),
-+ _SVE_INSNC ("cnot", 0x041ba000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_BHSD, 0, C_SCAN_MOVPRFX, 0),
-+ _SVE_INSNC ("cnt", 0x041aa000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_BHSD, 0, C_SCAN_MOVPRFX, 0),
- _SVE_INSN ("cntb", 0x0420e000, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0),
- _SVE_INSN ("cntd", 0x04e0e000, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0),
- _SVE_INSN ("cnth", 0x0460e000, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0),
- _SVE_INSN ("cntp", 0x25208000, 0xff3fc200, sve_size_bhsd, 0, OP3 (Rd, SVE_Pg4_10, SVE_Pn), OP_SVE_XUV_BHSD, 0, 0),
- _SVE_INSN ("cntw", 0x04a0e000, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0),
- _SVE_INSN ("compact", 0x05a18000, 0xffbfe000, sve_size_sd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_SD, 0, 0),
-- _SVE_INSN ("cpy", 0x05208000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Vn), OP_SVE_VMV_BHSD, F_HAS_ALIAS, 0),
-- _SVE_INSN ("cpy", 0x0528a000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Pg3, Rn_SP), OP_SVE_VMR_BHSD, F_HAS_ALIAS, 0),
-- _SVE_INSN ("cpy", 0x05100000, 0xff308000, sve_cpy, 0, OP3 (SVE_Zd, SVE_Pg4_16, SVE_ASIMM), OP_SVE_VPU_BHSD, F_HAS_ALIAS, 0),
-+ _SVE_INSNC ("cpy", 0x05208000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Vn), OP_SVE_VMV_BHSD, F_HAS_ALIAS, C_SCAN_MOVPRFX, 0),
-+ _SVE_INSNC ("cpy", 0x0528a000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Pg3, Rn_SP), OP_SVE_VMR_BHSD, F_HAS_ALIAS, C_SCAN_MOVPRFX, 0),
-+ _SVE_INSNC ("cpy", 0x05100000, 0xff308000, sve_cpy, 0, OP3 (SVE_Zd, SVE_Pg4_16, SVE_ASIMM), OP_SVE_VPU_BHSD, F_HAS_ALIAS, C_SCAN_MOVPRFX, 0),
- _SVE_INSN ("ctermeq", 0x25a02000, 0xffa0fc1f, sve_size_sd, 0, OP2 (Rn, Rm), OP_SVE_RR, 0, 0),
- _SVE_INSN ("ctermne", 0x25a02010, 0xffa0fc1f, sve_size_sd, 0, OP2 (Rn, Rm), OP_SVE_RR, 0, 0),
- _SVE_INSN ("decb", 0x0430e400, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0),
-- _SVE_INSN ("decd", 0x04f0c400, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_DU, F_OPD1_OPT | F_DEFAULT(31), 0),
-+ _SVE_INSNC ("decd", 0x04f0c400, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_DU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0),
- _SVE_INSN ("decd", 0x04f0e400, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0),
-- _SVE_INSN ("dech", 0x0470c400, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_HU, F_OPD1_OPT | F_DEFAULT(31), 0),
-+ _SVE_INSNC ("dech", 0x0470c400, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_HU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0),
- _SVE_INSN ("dech", 0x0470e400, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0),
-- _SVE_INSN ("decp", 0x252d8000, 0xff3ffe00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Pg4_5), OP_SVE_VU_HSD, 0, 0),
-+ _SVE_INSNC ("decp", 0x252d8000, 0xff3ffe00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Pg4_5), OP_SVE_VU_HSD, 0, C_SCAN_MOVPRFX, 0),
- _SVE_INSN ("decp", 0x252d8800, 0xff3ffe00, sve_size_bhsd, 0, OP2 (Rd, SVE_Pg4_5), OP_SVE_XV_BHSD, 0, 0),
-- _SVE_INSN ("decw", 0x04b0c400, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_SU, F_OPD1_OPT | F_DEFAULT(31), 0),
-+ _SVE_INSNC ("decw", 0x04b0c400, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_SU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0),
- _SVE_INSN ("decw", 0x04b0e400, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0),
- _SVE_INSN ("dup", 0x05203800, 0xff3ffc00, sve_size_bhsd, 0, OP2 (SVE_Zd, Rn_SP), OP_SVE_VR_BHSD, F_HAS_ALIAS, 0),
- _SVE_INSN ("dup", 0x05202000, 0xff20fc00, sve_index, 0, OP2 (SVE_Zd, SVE_Zn_INDEX), OP_SVE_VV_BHSDQ, F_HAS_ALIAS, 0),
- _SVE_INSN ("dup", 0x2538c000, 0xff3fc000, sve_size_bhsd, 0, OP2 (SVE_Zd, SVE_ASIMM), OP_SVE_VU_BHSD, F_HAS_ALIAS, 0),
- _SVE_INSN ("dupm", 0x05c00000, 0xfffc0000, sve_limm, 0, OP2 (SVE_Zd, SVE_LIMM), OP_SVE_VU_BHSD, F_HAS_ALIAS, 0),
- _SVE_INSN ("eor", 0x04a03000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_DDD, 0, 0),
-- _SVE_INSN ("eor", 0x05400000, 0xfffc0000, sve_limm, 0, OP3 (SVE_Zd, SVE_Zd, SVE_LIMM), OP_SVE_VVU_BHSD, F_HAS_ALIAS, 1),
-- _SVE_INSN ("eor", 0x04190000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, 2),
-+ _SVE_INSNC ("eor", 0x05400000, 0xfffc0000, sve_limm, 0, OP3 (SVE_Zd, SVE_Zd, SVE_LIMM), OP_SVE_VVU_BHSD, F_HAS_ALIAS, C_SCAN_MOVPRFX, 1),
-+ _SVE_INSNC ("eor", 0x04190000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2),
- _SVE_INSN ("eor", 0x25004200, 0xfff0c210, sve_misc, 0, OP4 (SVE_Pd, SVE_Pg4_10, SVE_Pn, SVE_Pm), OP_SVE_BZBB, F_HAS_ALIAS, 0),
- _SVE_INSN ("eors", 0x25404200, 0xfff0c210, sve_misc, 0, OP4 (SVE_Pd, SVE_Pg4_10, SVE_Pn, SVE_Pm), OP_SVE_BZBB, F_HAS_ALIAS, 0),
- _SVE_INSN ("eorv", 0x04192000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_BHSD, 0, 0),
-- _SVE_INSN ("ext", 0x05200000, 0xffe0e000, sve_misc, 0, OP4 (SVE_Zd, SVE_Zd, SVE_Zm_5, SVE_UIMM8_53), OP_SVE_BBBU, 0, 1),
-- _SVE_INSN ("fabd", 0x65088000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, 2),
-- _SVE_INSN ("fabs", 0x041ca000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, 0),
-+ _SVE_INSNC ("ext", 0x05200000, 0xffe0e000, sve_misc, 0, OP4 (SVE_Zd, SVE_Zd, SVE_Zm_5, SVE_UIMM8_53), OP_SVE_BBBU, 0, C_SCAN_MOVPRFX, 1),
-+ _SVE_INSNC ("fabd", 0x65088000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 2),
-+ _SVE_INSNC ("fabs", 0x041ca000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, C_SCAN_MOVPRFX, 0),
- _SVE_INSN ("facge", 0x6500c010, 0xff20e010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVV_HSD, F_HAS_ALIAS, 0),
- _SVE_INSN ("facgt", 0x6500e010, 0xff20e010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVV_HSD, F_HAS_ALIAS, 0),
- _SVE_INSN ("fadd", 0x65000000, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD, 0, 0),
-- _SVE_INSN ("fadd", 0x65008000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, 2),
-- _SVE_INSN ("fadd", 0x65188000, 0xff3fe3c0, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_I1_HALF_ONE), OP_SVE_VMVU_HSD, 0, 2),
-+ _SVE_INSNC ("fadd", 0x65008000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 2),
-+ _SVE_INSNC ("fadd", 0x65188000, 0xff3fe3c0, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_I1_HALF_ONE), OP_SVE_VMVU_HSD, 0, C_SCAN_MOVPRFX, 2),
- _SVE_INSN ("fadda", 0x65182000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Vd, SVE_Pg3, SVE_Vd, SVE_Zm_5), OP_SVE_VUVV_HSD, 0, 2),
- _SVE_INSN ("faddv", 0x65002000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_HSD, 0, 0),
-- _SVE_INSN ("fcadd", 0x64008000, 0xff3ee000, sve_size_hsd, 0, OP5 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5, SVE_IMM_ROT1), OP_SVE_VMVVU_HSD, 0, 2),
-- _SVE_INSN ("fcmla", 0x64000000, 0xff208000, sve_size_hsd, 0, OP5 (SVE_Zd, SVE_Pg3, SVE_Zn, SVE_Zm_16, IMM_ROT2), OP_SVE_VMVVU_HSD, 0, 0),
-- _SVE_INSN ("fcmla", 0x64a01000, 0xffe0f000, sve_misc, 0, OP4 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX, SVE_IMM_ROT2), OP_SVE_VVVU_H, 0, 0),
-- _SVE_INSN ("fcmla", 0x64e01000, 0xffe0f000, sve_misc, 0, OP4 (SVE_Zd, SVE_Zn, SVE_Zm4_INDEX, SVE_IMM_ROT2), OP_SVE_VVVU_S, 0, 0),
-+ _SVE_INSNC ("fcadd", 0x64008000, 0xff3ee000, sve_size_hsd, 0, OP5 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5, SVE_IMM_ROT1), OP_SVE_VMVVU_HSD, 0, C_SCAN_MOVPRFX, 2),
-+ _SVE_INSNC ("fcmla", 0x64000000, 0xff208000, sve_size_hsd, 0, OP5 (SVE_Zd, SVE_Pg3, SVE_Zn, SVE_Zm_16, IMM_ROT2), OP_SVE_VMVVU_HSD, 0, C_SCAN_MOVPRFX, 0),
-+ _SVE_INSNC ("fcmla", 0x64a01000, 0xffe0f000, sve_misc, 0, OP4 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX, SVE_IMM_ROT2), OP_SVE_VVVU_H, 0, C_SCAN_MOVPRFX, 0),
-+ _SVE_INSNC ("fcmla", 0x64e01000, 0xffe0f000, sve_misc, 0, OP4 (SVE_Zd, SVE_Zn, SVE_Zm4_INDEX, SVE_IMM_ROT2), OP_SVE_VVVU_S, 0, C_SCAN_MOVPRFX, 0),
- _SVE_INSN ("fcmeq", 0x65122000, 0xff3fe010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, FPIMM0), OP_SVE_VZV_HSD, 0, 0),
- _SVE_INSN ("fcmeq", 0x65006000, 0xff20e010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVV_HSD, 0, 0),
- _SVE_INSN ("fcmge", 0x65102000, 0xff3fe010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, FPIMM0), OP_SVE_VZV_HSD, 0, 0),
-@@ -3655,102 +4083,102 @@ struct aarch64_opcode aarch64_opcode_tab
- _SVE_INSN ("fcmne", 0x65132000, 0xff3fe010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, FPIMM0), OP_SVE_VZV_HSD, 0, 0),
- _SVE_INSN ("fcmne", 0x65006010, 0xff20e010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVV_HSD, 0, 0),
- _SVE_INSN ("fcmuo", 0x6500c000, 0xff20e010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVV_HSD, 0, 0),
-- _SVE_INSN ("fcpy", 0x0510c000, 0xff30e000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg4_16, SVE_FPIMM8), OP_SVE_VMU_HSD, F_HAS_ALIAS, 0),
-- _SVE_INSN ("fcvt", 0x6588a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMS, 0, 0),
-- _SVE_INSN ("fcvt", 0x6589a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMH, 0, 0),
-- _SVE_INSN ("fcvt", 0x65c8a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMD, 0, 0),
-- _SVE_INSN ("fcvt", 0x65c9a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMH, 0, 0),
-- _SVE_INSN ("fcvt", 0x65caa000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMD, 0, 0),
-- _SVE_INSN ("fcvt", 0x65cba000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMS, 0, 0),
-- _SVE_INSN ("fcvtzs", 0x655aa000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMH, 0, 0),
-- _SVE_INSN ("fcvtzs", 0x655ca000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMH, 0, 0),
-- _SVE_INSN ("fcvtzs", 0x655ea000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMH, 0, 0),
-- _SVE_INSN ("fcvtzs", 0x659ca000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMS, 0, 0),
-- _SVE_INSN ("fcvtzs", 0x65d8a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMD, 0, 0),
-- _SVE_INSN ("fcvtzs", 0x65dca000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMS, 0, 0),
-- _SVE_INSN ("fcvtzs", 0x65dea000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMD, 0, 0),
-- _SVE_INSN ("fcvtzu", 0x655ba000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMH, 0, 0),
-- _SVE_INSN ("fcvtzu", 0x655da000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMH, 0, 0),
-- _SVE_INSN ("fcvtzu", 0x655fa000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMH, 0, 0),
-- _SVE_INSN ("fcvtzu", 0x659da000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMS, 0, 0),
-- _SVE_INSN ("fcvtzu", 0x65d9a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMD, 0, 0),
-- _SVE_INSN ("fcvtzu", 0x65dda000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMS, 0, 0),
-- _SVE_INSN ("fcvtzu", 0x65dfa000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMD, 0, 0),
-- _SVE_INSN ("fdiv", 0x650d8000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, 2),
-- _SVE_INSN ("fdivr", 0x650c8000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, 2),
-+ _SVE_INSNC ("fcpy", 0x0510c000, 0xff30e000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg4_16, SVE_FPIMM8), OP_SVE_VMU_HSD, F_HAS_ALIAS, C_SCAN_MOVPRFX, 0),
-+ _SVE_INSNC ("fcvt", 0x6588a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMS, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0),
-+ _SVE_INSNC ("fcvt", 0x6589a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMH, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0),
-+ _SVE_INSNC ("fcvt", 0x65c8a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMD, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0),
-+ _SVE_INSNC ("fcvt", 0x65c9a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMH, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0),
-+ _SVE_INSNC ("fcvt", 0x65caa000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMD, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0),
-+ _SVE_INSNC ("fcvt", 0x65cba000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMS, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0),
-+ _SVE_INSNC ("fcvtzs", 0x655aa000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMH, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0),
-+ _SVE_INSNC ("fcvtzs", 0x655ca000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMH, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0),
-+ _SVE_INSNC ("fcvtzs", 0x655ea000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMH, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0),
-+ _SVE_INSNC ("fcvtzs", 0x659ca000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMS, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0),
-+ _SVE_INSNC ("fcvtzs", 0x65d8a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMD, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0),
-+ _SVE_INSNC ("fcvtzs", 0x65dca000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMS, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0),
-+ _SVE_INSNC ("fcvtzs", 0x65dea000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMD, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0),
-+ _SVE_INSNC ("fcvtzu", 0x655ba000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMH, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0),
-+ _SVE_INSNC ("fcvtzu", 0x655da000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMH, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0),
-+ _SVE_INSNC ("fcvtzu", 0x655fa000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMH, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0),
-+ _SVE_INSNC ("fcvtzu", 0x659da000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMS, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0),
-+ _SVE_INSNC ("fcvtzu", 0x65d9a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMD, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0),
-+ _SVE_INSNC ("fcvtzu", 0x65dda000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMS, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0),
-+ _SVE_INSNC ("fcvtzu", 0x65dfa000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMD, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0),
-+ _SVE_INSNC ("fdiv", 0x650d8000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 2),
-+ _SVE_INSNC ("fdivr", 0x650c8000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 2),
- _SVE_INSN ("fdup", 0x2539c000, 0xff3fe000, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_FPIMM8), OP_SVE_VU_HSD, F_HAS_ALIAS, 0),
- _SVE_INSN ("fexpa", 0x0420b800, 0xff3ffc00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Zn), OP_SVE_VV_HSD, 0, 0),
-- _SVE_INSN ("fmad", 0x65208000, 0xff20e000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zm_5, SVE_Za_16), OP_SVE_VMVV_HSD, 0, 0),
-- _SVE_INSN ("fmax", 0x65068000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, 2),
-- _SVE_INSN ("fmax", 0x651e8000, 0xff3fe3c0, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_I1_ZERO_ONE), OP_SVE_VMVU_HSD, 0, 2),
-- _SVE_INSN ("fmaxnm", 0x65048000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, 2),
-- _SVE_INSN ("fmaxnm", 0x651c8000, 0xff3fe3c0, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_I1_ZERO_ONE), OP_SVE_VMVU_HSD, 0, 2),
-+ _SVE_INSNC ("fmad", 0x65208000, 0xff20e000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zm_5, SVE_Za_16), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 0),
-+ _SVE_INSNC ("fmax", 0x65068000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 2),
-+ _SVE_INSNC ("fmax", 0x651e8000, 0xff3fe3c0, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_I1_ZERO_ONE), OP_SVE_VMVU_HSD, 0, C_SCAN_MOVPRFX, 2),
-+ _SVE_INSNC ("fmaxnm", 0x65048000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 2),
-+ _SVE_INSNC ("fmaxnm", 0x651c8000, 0xff3fe3c0, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_I1_ZERO_ONE), OP_SVE_VMVU_HSD, 0, C_SCAN_MOVPRFX, 2),
- _SVE_INSN ("fmaxnmv", 0x65042000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_HSD, 0, 0),
- _SVE_INSN ("fmaxv", 0x65062000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_HSD, 0, 0),
-- _SVE_INSN ("fmin", 0x65078000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, 2),
-- _SVE_INSN ("fmin", 0x651f8000, 0xff3fe3c0, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_I1_ZERO_ONE), OP_SVE_VMVU_HSD, 0, 2),
-- _SVE_INSN ("fminnm", 0x65058000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, 2),
-- _SVE_INSN ("fminnm", 0x651d8000, 0xff3fe3c0, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_I1_ZERO_ONE), OP_SVE_VMVU_HSD, 0, 2),
-+ _SVE_INSNC ("fmin", 0x65078000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 2),
-+ _SVE_INSNC ("fmin", 0x651f8000, 0xff3fe3c0, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_I1_ZERO_ONE), OP_SVE_VMVU_HSD, 0, C_SCAN_MOVPRFX, 2),
-+ _SVE_INSNC ("fminnm", 0x65058000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 2),
-+ _SVE_INSNC ("fminnm", 0x651d8000, 0xff3fe3c0, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_I1_ZERO_ONE), OP_SVE_VMVU_HSD, 0, C_SCAN_MOVPRFX, 2),
- _SVE_INSN ("fminnmv", 0x65052000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_HSD, 0, 0),
- _SVE_INSN ("fminv", 0x65072000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_HSD, 0, 0),
-- _SVE_INSN ("fmla", 0x65200000, 0xff20e000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VMVV_HSD, 0, 0),
-- _SVE_INSN ("fmla", 0x64200000, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_22_INDEX), OP_SVE_VVV_H, 0, 0),
-- _SVE_INSN ("fmla", 0x64a00000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX), OP_SVE_VVV_S, 0, 0),
-- _SVE_INSN ("fmla", 0x64e00000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm4_INDEX), OP_SVE_VVV_D, 0, 0),
-- _SVE_INSN ("fmls", 0x65202000, 0xff20e000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VMVV_HSD, 0, 0),
-- _SVE_INSN ("fmls", 0x64200400, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_22_INDEX), OP_SVE_VVV_H, 0, 0),
-- _SVE_INSN ("fmls", 0x64a00400, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX), OP_SVE_VVV_S, 0, 0),
-- _SVE_INSN ("fmls", 0x64e00400, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm4_INDEX), OP_SVE_VVV_D, 0, 0),
-- _SVE_INSN ("fmsb", 0x6520a000, 0xff20e000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zm_5, SVE_Za_16), OP_SVE_VMVV_HSD, 0, 0),
-+ _SVE_INSNC ("fmla", 0x65200000, 0xff20e000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 0),
-+ _SVE_INSNC ("fmla", 0x64200000, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_22_INDEX), OP_SVE_VVV_H, 0, C_SCAN_MOVPRFX, 0),
-+ _SVE_INSNC ("fmla", 0x64a00000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX), OP_SVE_VVV_S, 0, C_SCAN_MOVPRFX, 0),
-+ _SVE_INSNC ("fmla", 0x64e00000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm4_INDEX), OP_SVE_VVV_D, 0, C_SCAN_MOVPRFX, 0),
-+ _SVE_INSNC ("fmls", 0x65202000, 0xff20e000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 0),
-+ _SVE_INSNC ("fmls", 0x64200400, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_22_INDEX), OP_SVE_VVV_H, 0, C_SCAN_MOVPRFX, 0),
-+ _SVE_INSNC ("fmls", 0x64a00400, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX), OP_SVE_VVV_S, 0, C_SCAN_MOVPRFX, 0),
-+ _SVE_INSNC ("fmls", 0x64e00400, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm4_INDEX), OP_SVE_VVV_D, 0, C_SCAN_MOVPRFX, 0),
-+ _SVE_INSNC ("fmsb", 0x6520a000, 0xff20e000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zm_5, SVE_Za_16), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 0),
- _SVE_INSN ("fmul", 0x65000800, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD, 0, 0),
-- _SVE_INSN ("fmul", 0x65028000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, 2),
-- _SVE_INSN ("fmul", 0x651a8000, 0xff3fe3c0, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_I1_HALF_TWO), OP_SVE_VMVU_HSD, 0, 2),
-+ _SVE_INSNC ("fmul", 0x65028000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 2),
-+ _SVE_INSNC ("fmul", 0x651a8000, 0xff3fe3c0, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_I1_HALF_TWO), OP_SVE_VMVU_HSD, 0, C_SCAN_MOVPRFX, 2),
- _SVE_INSN ("fmul", 0x64202000, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_22_INDEX), OP_SVE_VVV_H, 0, 0),
- _SVE_INSN ("fmul", 0x64a02000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX), OP_SVE_VVV_S, 0, 0),
- _SVE_INSN ("fmul", 0x64e02000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm4_INDEX), OP_SVE_VVV_D, 0, 0),
-- _SVE_INSN ("fmulx", 0x650a8000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, 2),
-- _SVE_INSN ("fneg", 0x041da000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, 0),
-- _SVE_INSN ("fnmad", 0x6520c000, 0xff20e000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zm_5, SVE_Za_16), OP_SVE_VMVV_HSD, 0, 0),
-- _SVE_INSN ("fnmla", 0x65204000, 0xff20e000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VMVV_HSD, 0, 0),
-- _SVE_INSN ("fnmls", 0x65206000, 0xff20e000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VMVV_HSD, 0, 0),
-- _SVE_INSN ("fnmsb", 0x6520e000, 0xff20e000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zm_5, SVE_Za_16), OP_SVE_VMVV_HSD, 0, 0),
-+ _SVE_INSNC ("fmulx", 0x650a8000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 2),
-+ _SVE_INSNC ("fneg", 0x041da000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, C_SCAN_MOVPRFX, 0),
-+ _SVE_INSNC ("fnmad", 0x6520c000, 0xff20e000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zm_5, SVE_Za_16), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 0),
-+ _SVE_INSNC ("fnmla", 0x65204000, 0xff20e000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 0),
-+ _SVE_INSNC ("fnmls", 0x65206000, 0xff20e000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 0),
-+ _SVE_INSNC ("fnmsb", 0x6520e000, 0xff20e000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zm_5, SVE_Za_16), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 0),
- _SVE_INSN ("frecpe", 0x650e3000, 0xff3ffc00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Zn), OP_SVE_VV_HSD, 0, 0),
- _SVE_INSN ("frecps", 0x65001800, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD, 0, 0),
-- _SVE_INSN ("frecpx", 0x650ca000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, 0),
-- _SVE_INSN ("frinta", 0x6504a000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, 0),
-- _SVE_INSN ("frinti", 0x6507a000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, 0),
-- _SVE_INSN ("frintm", 0x6502a000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, 0),
-- _SVE_INSN ("frintn", 0x6500a000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, 0),
-- _SVE_INSN ("frintp", 0x6501a000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, 0),
-- _SVE_INSN ("frintx", 0x6506a000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, 0),
-- _SVE_INSN ("frintz", 0x6503a000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, 0),
-+ _SVE_INSNC ("frecpx", 0x650ca000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, C_SCAN_MOVPRFX, 0),
-+ _SVE_INSNC ("frinta", 0x6504a000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, C_SCAN_MOVPRFX, 0),
-+ _SVE_INSNC ("frinti", 0x6507a000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, C_SCAN_MOVPRFX, 0),
-+ _SVE_INSNC ("frintm", 0x6502a000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, C_SCAN_MOVPRFX, 0),
-+ _SVE_INSNC ("frintn", 0x6500a000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, C_SCAN_MOVPRFX, 0),
-+ _SVE_INSNC ("frintp", 0x6501a000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, C_SCAN_MOVPRFX, 0),
-+ _SVE_INSNC ("frintx", 0x6506a000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, C_SCAN_MOVPRFX, 0),
-+ _SVE_INSNC ("frintz", 0x6503a000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, C_SCAN_MOVPRFX, 0),
- _SVE_INSN ("frsqrte", 0x650f3000, 0xff3ffc00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Zn), OP_SVE_VV_HSD, 0, 0),
- _SVE_INSN ("frsqrts", 0x65001c00, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD, 0, 0),
-- _SVE_INSN ("fscale", 0x65098000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, 2),
-- _SVE_INSN ("fsqrt", 0x650da000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, 0),
-+ _SVE_INSNC ("fscale", 0x65098000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 2),
-+ _SVE_INSNC ("fsqrt", 0x650da000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, C_SCAN_MOVPRFX, 0),
- _SVE_INSN ("fsub", 0x65000400, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD, 0, 0),
-- _SVE_INSN ("fsub", 0x65018000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, 2),
-- _SVE_INSN ("fsub", 0x65198000, 0xff3fe3c0, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_I1_HALF_ONE), OP_SVE_VMVU_HSD, 0, 2),
-- _SVE_INSN ("fsubr", 0x65038000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, 2),
-- _SVE_INSN ("fsubr", 0x651b8000, 0xff3fe3c0, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_I1_HALF_ONE), OP_SVE_VMVU_HSD, 0, 2),
-- _SVE_INSN ("ftmad", 0x65108000, 0xff38fc00, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Zd, SVE_Zm_5, SVE_UIMM3), OP_SVE_VVVU_HSD, 0, 1),
-+ _SVE_INSNC ("fsub", 0x65018000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 2),
-+ _SVE_INSNC ("fsub", 0x65198000, 0xff3fe3c0, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_I1_HALF_ONE), OP_SVE_VMVU_HSD, 0, C_SCAN_MOVPRFX, 2),
-+ _SVE_INSNC ("fsubr", 0x65038000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 2),
-+ _SVE_INSNC ("fsubr", 0x651b8000, 0xff3fe3c0, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_I1_HALF_ONE), OP_SVE_VMVU_HSD, 0, C_SCAN_MOVPRFX, 2),
-+ _SVE_INSNC ("ftmad", 0x65108000, 0xff38fc00, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Zd, SVE_Zm_5, SVE_UIMM3), OP_SVE_VVVU_HSD, 0, C_SCAN_MOVPRFX, 1),
- _SVE_INSN ("ftsmul", 0x65000c00, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD, 0, 0),
- _SVE_INSN ("ftssel", 0x0420b000, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD, 0, 0),
- _SVE_INSN ("incb", 0x0430e000, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0),
-- _SVE_INSN ("incd", 0x04f0c000, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_DU, F_OPD1_OPT | F_DEFAULT(31), 0),
-+ _SVE_INSNC ("incd", 0x04f0c000, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_DU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0),
- _SVE_INSN ("incd", 0x04f0e000, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0),
-- _SVE_INSN ("inch", 0x0470c000, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_HU, F_OPD1_OPT | F_DEFAULT(31), 0),
-+ _SVE_INSNC ("inch", 0x0470c000, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_HU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0),
- _SVE_INSN ("inch", 0x0470e000, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0),
-- _SVE_INSN ("incp", 0x252c8000, 0xff3ffe00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Pg4_5), OP_SVE_VU_HSD, 0, 0),
-+ _SVE_INSNC ("incp", 0x252c8000, 0xff3ffe00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Pg4_5), OP_SVE_VU_HSD, 0, C_SCAN_MOVPRFX, 0),
- _SVE_INSN ("incp", 0x252c8800, 0xff3ffe00, sve_size_bhsd, 0, OP2 (Rd, SVE_Pg4_5), OP_SVE_XV_BHSD, 0, 0),
-- _SVE_INSN ("incw", 0x04b0c000, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_SU, F_OPD1_OPT | F_DEFAULT(31), 0),
-+ _SVE_INSNC ("incw", 0x04b0c000, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_SU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0),
- _SVE_INSN ("incw", 0x04b0e000, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0),
- _SVE_INSN ("index", 0x04204c00, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, Rn, Rm), OP_SVE_VRR_BHSD, 0, 0),
- _SVE_INSN ("index", 0x04204000, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_SIMM5, SVE_SIMM5B), OP_SVE_VUU_BHSD, 0, 0),
- _SVE_INSN ("index", 0x04204400, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, Rn, SIMM5), OP_SVE_VRU_BHSD, 0, 0),
- _SVE_INSN ("index", 0x04204800, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_SIMM5, Rm), OP_SVE_VUR_BHSD, 0, 0),
-- _SVE_INSN ("insr", 0x05243800, 0xff3ffc00, sve_size_bhsd, 0, OP2 (SVE_Zd, SVE_Rm), OP_SVE_VR_BHSD, 0, 0),
-- _SVE_INSN ("insr", 0x05343800, 0xff3ffc00, sve_size_bhsd, 0, OP2 (SVE_Zd, SVE_Vm), OP_SVE_VV_BHSD, 0, 0),
-+ _SVE_INSNC ("insr", 0x05243800, 0xff3ffc00, sve_size_bhsd, 0, OP2 (SVE_Zd, SVE_Rm), OP_SVE_VR_BHSD, 0, C_SCAN_MOVPRFX, 0),
-+ _SVE_INSNC ("insr", 0x05343800, 0xff3ffc00, sve_size_bhsd, 0, OP2 (SVE_Zd, SVE_Vm), OP_SVE_VV_BHSD, 0, C_SCAN_MOVPRFX, 0),
- _SVE_INSN ("lasta", 0x0520a000, 0xff3fe000, sve_size_bhsd, 0, OP3 (Rd, SVE_Pg3, SVE_Zn), OP_SVE_RUV_BHSD, 0, 0),
- _SVE_INSN ("lasta", 0x05228000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_BHSD, 0, 0),
- _SVE_INSN ("lastb", 0x0521a000, 0xff3fe000, sve_size_bhsd, 0, OP3 (Rd, SVE_Pg3, SVE_Zn), OP_SVE_RUV_BHSD, 0, 0),
-@@ -3879,66 +4307,90 @@ struct aarch64_opcode aarch64_opcode_tab
- _SVE_INSN ("ld4h", 0xa4e0e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_HZU, F_OD(4), 0),
- _SVE_INSN ("ld4w", 0xa560c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL2), OP_SVE_SZU, F_OD(4), 0),
- _SVE_INSN ("ld4w", 0xa560e000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_SZU, F_OD(4), 0),
-+
- _SVE_INSN ("ldff1b", 0x84006000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_SZS, F_OD(1), 0),
- _SVE_INSN ("ldff1b", 0xa4006000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RR), OP_SVE_BZU, F_OD(1), 0),
-+ _SVE_INSN ("ldff1b", 0xa4006000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_R), OP_SVE_BZU, F_OD(1), 0),
- _SVE_INSN ("ldff1b", 0xa4206000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RR), OP_SVE_HZU, F_OD(1), 0),
-+ _SVE_INSN ("ldff1b", 0xa4206000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_R), OP_SVE_HZU, F_OD(1), 0),
- _SVE_INSN ("ldff1b", 0xa4406000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RR), OP_SVE_SZU, F_OD(1), 0),
-+ _SVE_INSN ("ldff1b", 0xa4406000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_R), OP_SVE_SZU, F_OD(1), 0),
- _SVE_INSN ("ldff1b", 0xa4606000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RR), OP_SVE_DZU, F_OD(1), 0),
-+ _SVE_INSN ("ldff1b", 0xa4606000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_R), OP_SVE_DZU, F_OD(1), 0),
- _SVE_INSN ("ldff1b", 0xc4006000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_DZD, F_OD(1), 0),
- _SVE_INSN ("ldff1b", 0xc440e000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ), OP_SVE_DZD, F_OD(1), 0),
- _SVE_INSN ("ldff1b", 0x8420e000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5), OP_SVE_SZS, F_OD(1), 0),
- _SVE_INSN ("ldff1b", 0xc420e000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5), OP_SVE_DZD, F_OD(1), 0),
-+
- _SVE_INSN ("ldff1d", 0xa5e06000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RR_LSL3), OP_SVE_DZU, F_OD(1), 0),
-+ _SVE_INSN ("ldff1d", 0xa5e06000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_R), OP_SVE_DZU, F_OD(1), 0),
- _SVE_INSN ("ldff1d", 0xc5806000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_DZD, F_OD(1), 0),
- _SVE_INSN ("ldff1d", 0xc5a06000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW3_22), OP_SVE_DZD, F_OD(1), 0),
- _SVE_INSN ("ldff1d", 0xc5c0e000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ), OP_SVE_DZD, F_OD(1), 0),
- _SVE_INSN ("ldff1d", 0xc5e0e000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_LSL3), OP_SVE_DZD, F_OD(1), 0),
- _SVE_INSN ("ldff1d", 0xc5a0e000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5x8), OP_SVE_DZD, F_OD(1), 0),
-+
- _SVE_INSN ("ldff1h", 0x84806000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_SZS, F_OD(1), 0),
- _SVE_INSN ("ldff1h", 0x84a06000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW1_22), OP_SVE_SZS, F_OD(1), 0),
- _SVE_INSN ("ldff1h", 0xa4a06000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RR_LSL1), OP_SVE_HZU, F_OD(1), 0),
-+ _SVE_INSN ("ldff1h", 0xa4a06000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_R), OP_SVE_HZU, F_OD(1), 0),
- _SVE_INSN ("ldff1h", 0xa4c06000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RR_LSL1), OP_SVE_SZU, F_OD(1), 0),
-+ _SVE_INSN ("ldff1h", 0xa4c06000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_R), OP_SVE_SZU, F_OD(1), 0),
- _SVE_INSN ("ldff1h", 0xa4e06000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RR_LSL1), OP_SVE_DZU, F_OD(1), 0),
-+ _SVE_INSN ("ldff1h", 0xa4e06000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_R), OP_SVE_DZU, F_OD(1), 0),
- _SVE_INSN ("ldff1h", 0xc4806000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_DZD, F_OD(1), 0),
- _SVE_INSN ("ldff1h", 0xc4a06000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW1_22), OP_SVE_DZD, F_OD(1), 0),
- _SVE_INSN ("ldff1h", 0xc4c0e000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ), OP_SVE_DZD, F_OD(1), 0),
- _SVE_INSN ("ldff1h", 0xc4e0e000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_LSL1), OP_SVE_DZD, F_OD(1), 0),
- _SVE_INSN ("ldff1h", 0x84a0e000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5x2), OP_SVE_SZS, F_OD(1), 0),
- _SVE_INSN ("ldff1h", 0xc4a0e000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5x2), OP_SVE_DZD, F_OD(1), 0),
-+
- _SVE_INSN ("ldff1sb", 0x84002000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_SZS, F_OD(1), 0),
- _SVE_INSN ("ldff1sb", 0xa5806000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RR), OP_SVE_DZU, F_OD(1), 0),
-+ _SVE_INSN ("ldff1sb", 0xa5806000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_R), OP_SVE_DZU, F_OD(1), 0),
- _SVE_INSN ("ldff1sb", 0xa5a06000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RR), OP_SVE_SZU, F_OD(1), 0),
-+ _SVE_INSN ("ldff1sb", 0xa5a06000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_R), OP_SVE_SZU, F_OD(1), 0),
- _SVE_INSN ("ldff1sb", 0xa5c06000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RR), OP_SVE_HZU, F_OD(1), 0),
-+ _SVE_INSN ("ldff1sb", 0xa5c06000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_R), OP_SVE_HZU, F_OD(1), 0),
- _SVE_INSN ("ldff1sb", 0xc4002000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_DZD, F_OD(1), 0),
- _SVE_INSN ("ldff1sb", 0xc440a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ), OP_SVE_DZD, F_OD(1), 0),
- _SVE_INSN ("ldff1sb", 0x8420a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5), OP_SVE_SZS, F_OD(1), 0),
- _SVE_INSN ("ldff1sb", 0xc420a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5), OP_SVE_DZD, F_OD(1), 0),
-+
- _SVE_INSN ("ldff1sh", 0x84802000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_SZS, F_OD(1), 0),
- _SVE_INSN ("ldff1sh", 0x84a02000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW1_22), OP_SVE_SZS, F_OD(1), 0),
- _SVE_INSN ("ldff1sh", 0xa5006000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RR_LSL1), OP_SVE_DZU, F_OD(1), 0),
-+ _SVE_INSN ("ldff1sh", 0xa5006000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_R), OP_SVE_DZU, F_OD(1), 0),
- _SVE_INSN ("ldff1sh", 0xa5206000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RR_LSL1), OP_SVE_SZU, F_OD(1), 0),
-+ _SVE_INSN ("ldff1sh", 0xa5206000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_R), OP_SVE_SZU, F_OD(1), 0),
- _SVE_INSN ("ldff1sh", 0xc4802000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_DZD, F_OD(1), 0),
- _SVE_INSN ("ldff1sh", 0xc4a02000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW1_22), OP_SVE_DZD, F_OD(1), 0),
- _SVE_INSN ("ldff1sh", 0xc4c0a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ), OP_SVE_DZD, F_OD(1), 0),
- _SVE_INSN ("ldff1sh", 0xc4e0a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_LSL1), OP_SVE_DZD, F_OD(1), 0),
- _SVE_INSN ("ldff1sh", 0x84a0a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5x2), OP_SVE_SZS, F_OD(1), 0),
- _SVE_INSN ("ldff1sh", 0xc4a0a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5x2), OP_SVE_DZD, F_OD(1), 0),
-+
- _SVE_INSN ("ldff1sw", 0xa4806000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RR_LSL2), OP_SVE_DZU, F_OD(1), 0),
-+ _SVE_INSN ("ldff1sw", 0xa4806000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_R), OP_SVE_DZU, F_OD(1), 0),
- _SVE_INSN ("ldff1sw", 0xc5002000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_DZD, F_OD(1), 0),
- _SVE_INSN ("ldff1sw", 0xc5202000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW2_22), OP_SVE_DZD, F_OD(1), 0),
- _SVE_INSN ("ldff1sw", 0xc540a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ), OP_SVE_DZD, F_OD(1), 0),
- _SVE_INSN ("ldff1sw", 0xc560a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_LSL2), OP_SVE_DZD, F_OD(1), 0),
- _SVE_INSN ("ldff1sw", 0xc520a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5x4), OP_SVE_DZD, F_OD(1), 0),
-+
- _SVE_INSN ("ldff1w", 0x85006000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_SZS, F_OD(1), 0),
- _SVE_INSN ("ldff1w", 0x85206000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW2_22), OP_SVE_SZS, F_OD(1), 0),
- _SVE_INSN ("ldff1w", 0xa5406000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RR_LSL2), OP_SVE_SZU, F_OD(1), 0),
-+ _SVE_INSN ("ldff1w", 0xa5406000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_R), OP_SVE_SZU, F_OD(1), 0),
- _SVE_INSN ("ldff1w", 0xa5606000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RR_LSL2), OP_SVE_DZU, F_OD(1), 0),
-+ _SVE_INSN ("ldff1w", 0xa5606000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_R), OP_SVE_DZU, F_OD(1), 0),
- _SVE_INSN ("ldff1w", 0xc5006000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_22), OP_SVE_DZD, F_OD(1), 0),
- _SVE_INSN ("ldff1w", 0xc5206000, 0xffa0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW2_22), OP_SVE_DZD, F_OD(1), 0),
- _SVE_INSN ("ldff1w", 0xc540e000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ), OP_SVE_DZD, F_OD(1), 0),
- _SVE_INSN ("ldff1w", 0xc560e000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_LSL2), OP_SVE_DZD, F_OD(1), 0),
- _SVE_INSN ("ldff1w", 0x8520e000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5x4), OP_SVE_SZS, F_OD(1), 0),
- _SVE_INSN ("ldff1w", 0xc520e000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZI_U5x4), OP_SVE_DZD, F_OD(1), 0),
-+
- _SVE_INSN ("ldnf1b", 0xa410a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_BZU, F_OD(1), 0),
- _SVE_INSN ("ldnf1b", 0xa430a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_HZU, F_OD(1), 0),
- _SVE_INSN ("ldnf1b", 0xa450a000, 0xfff0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4xVL), OP_SVE_SZU, F_OD(1), 0),
-@@ -3967,35 +4419,35 @@ struct aarch64_opcode aarch64_opcode_tab
- _SVE_INSN ("ldr", 0x85804000, 0xffc0e000, sve_misc, 0, OP2 (SVE_Zt, SVE_ADDR_RI_S9xVL), {}, 0, 0),
- _SVE_INSN ("lsl", 0x04208c00, 0xff20fc00, sve_size_bhs, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVD_BHS, 0, 0),
- _SVE_INSN ("lsl", 0x04209c00, 0xff20fc00, sve_shift_unpred, 0, OP3 (SVE_Zd, SVE_Zn, SVE_SHLIMM_UNPRED), OP_SVE_VVU_BHSD, 0, 0),
-- _SVE_INSN ("lsl", 0x04138000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, 2),
-- _SVE_INSN ("lsl", 0x041b8000, 0xff3fe000, sve_size_bhs, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVD_BHS, 0, 2),
-- _SVE_INSN ("lsl", 0x04038000, 0xff3fe000, sve_shift_pred, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_SHLIMM_PRED), OP_SVE_VMVU_BHSD, 0, 2),
-- _SVE_INSN ("lslr", 0x04178000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, 2),
-+ _SVE_INSNC ("lsl", 0x04138000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2),
-+ _SVE_INSNC ("lsl", 0x041b8000, 0xff3fe000, sve_size_bhs, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVD_BHS, 0, C_SCAN_MOVPRFX, 2),
-+ _SVE_INSNC ("lsl", 0x04038000, 0xff3fe000, sve_shift_pred, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_SHLIMM_PRED), OP_SVE_VMVU_BHSD, 0, C_SCAN_MOVPRFX, 2),
-+ _SVE_INSNC ("lslr", 0x04178000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2),
- _SVE_INSN ("lsr", 0x04208400, 0xff20fc00, sve_size_bhs, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVD_BHS, 0, 0),
- _SVE_INSN ("lsr", 0x04209400, 0xff20fc00, sve_shift_unpred, 0, OP3 (SVE_Zd, SVE_Zn, SVE_SHRIMM_UNPRED), OP_SVE_VVU_BHSD, 0, 0),
-- _SVE_INSN ("lsr", 0x04118000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, 2),
-- _SVE_INSN ("lsr", 0x04198000, 0xff3fe000, sve_size_bhs, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVD_BHS, 0, 2),
-- _SVE_INSN ("lsr", 0x04018000, 0xff3fe000, sve_shift_pred, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_SHRIMM_PRED), OP_SVE_VMVU_BHSD, 0, 2),
-- _SVE_INSN ("lsrr", 0x04158000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, 2),
-- _SVE_INSN ("mad", 0x0400c000, 0xff20e000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zm_16, SVE_Za_5), OP_SVE_VMVV_BHSD, 0, 0),
-- _SVE_INSN ("mla", 0x04004000, 0xff20e000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VMVV_BHSD, 0, 0),
-- _SVE_INSN ("mls", 0x04006000, 0xff20e000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VMVV_BHSD, 0, 0),
-- _SVE_INSN ("movprfx", 0x0420bc00, 0xfffffc00, sve_misc, 0, OP2 (SVE_Zd, SVE_Zn), {}, 0, 0),
-- _SVE_INSN ("movprfx", 0x04102000, 0xff3ee000, sve_movprfx, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VPV_BHSD, 0, 0),
-- _SVE_INSN ("msb", 0x0400e000, 0xff20e000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zm_16, SVE_Za_5), OP_SVE_VMVV_BHSD, 0, 0),
-- _SVE_INSN ("mul", 0x2530c000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zd, SVE_SIMM8), OP_SVE_VVU_BHSD, 0, 1),
-- _SVE_INSN ("mul", 0x04100000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, 2),
-+ _SVE_INSNC ("lsr", 0x04118000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2),
-+ _SVE_INSNC ("lsr", 0x04198000, 0xff3fe000, sve_size_bhs, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVD_BHS, 0, C_SCAN_MOVPRFX, 2),
-+ _SVE_INSNC ("lsr", 0x04018000, 0xff3fe000, sve_shift_pred, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_SHRIMM_PRED), OP_SVE_VMVU_BHSD, 0, C_SCAN_MOVPRFX, 2),
-+ _SVE_INSNC ("lsrr", 0x04158000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2),
-+ _SVE_INSNC ("mad", 0x0400c000, 0xff20e000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zm_16, SVE_Za_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 0),
-+ _SVE_INSNC ("mla", 0x04004000, 0xff20e000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 0),
-+ _SVE_INSNC ("mls", 0x04006000, 0xff20e000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 0),
-+ _SVE_INSNC ("movprfx", 0x0420bc00, 0xfffffc00, sve_misc, 0, OP2 (SVE_Zd, SVE_Zn), {}, F_SCAN, C_SCAN_MOVPRFX, 0),
-+ _SVE_INSNC ("movprfx", 0x04102000, 0xff3ee000, sve_movprfx, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VPV_BHSD, F_SCAN, C_SCAN_MOVPRFX, 0),
-+ _SVE_INSNC ("msb", 0x0400e000, 0xff20e000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zm_16, SVE_Za_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 0),
-+ _SVE_INSNC ("mul", 0x2530c000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zd, SVE_SIMM8), OP_SVE_VVU_BHSD, 0, C_SCAN_MOVPRFX, 1),
-+ _SVE_INSNC ("mul", 0x04100000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2),
- _SVE_INSN ("nand", 0x25804210, 0xfff0c210, sve_misc, 0, OP4 (SVE_Pd, SVE_Pg4_10, SVE_Pn, SVE_Pm), OP_SVE_BZBB, 0, 0),
- _SVE_INSN ("nands", 0x25c04210, 0xfff0c210, sve_misc, 0, OP4 (SVE_Pd, SVE_Pg4_10, SVE_Pn, SVE_Pm), OP_SVE_BZBB, 0, 0),
-- _SVE_INSN ("neg", 0x0417a000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_BHSD, 0, 0),
-+ _SVE_INSNC ("neg", 0x0417a000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_BHSD, 0, C_SCAN_MOVPRFX, 0),
- _SVE_INSN ("nor", 0x25804200, 0xfff0c210, sve_misc, 0, OP4 (SVE_Pd, SVE_Pg4_10, SVE_Pn, SVE_Pm), OP_SVE_BZBB, 0, 0),
- _SVE_INSN ("nors", 0x25c04200, 0xfff0c210, sve_misc, 0, OP4 (SVE_Pd, SVE_Pg4_10, SVE_Pn, SVE_Pm), OP_SVE_BZBB, 0, 0),
-- _SVE_INSN ("not", 0x041ea000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_BHSD, 0, 0),
-+ _SVE_INSNC ("not", 0x041ea000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_BHSD, 0, C_SCAN_MOVPRFX, 0),
- _SVE_INSN ("orn", 0x25804010, 0xfff0c210, sve_misc, 0, OP4 (SVE_Pd, SVE_Pg4_10, SVE_Pn, SVE_Pm), OP_SVE_BZBB, 0, 0),
- _SVE_INSN ("orns", 0x25c04010, 0xfff0c210, sve_misc, 0, OP4 (SVE_Pd, SVE_Pg4_10, SVE_Pn, SVE_Pm), OP_SVE_BZBB, 0, 0),
- _SVE_INSN ("orr", 0x04603000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_DDD, F_HAS_ALIAS, 0),
-- _SVE_INSN ("orr", 0x05000000, 0xfffc0000, sve_limm, 0, OP3 (SVE_Zd, SVE_Zd, SVE_LIMM), OP_SVE_VVU_BHSD, F_HAS_ALIAS, 1),
-- _SVE_INSN ("orr", 0x04180000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, 2),
-+ _SVE_INSNC ("orr", 0x05000000, 0xfffc0000, sve_limm, 0, OP3 (SVE_Zd, SVE_Zd, SVE_LIMM), OP_SVE_VVU_BHSD, F_HAS_ALIAS, C_SCAN_MOVPRFX, 1),
-+ _SVE_INSNC ("orr", 0x04180000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2),
- _SVE_INSN ("orr", 0x25804000, 0xfff0c210, sve_misc, 0, OP4 (SVE_Pd, SVE_Pg4_10, SVE_Pn, SVE_Pm), OP_SVE_BZBB, F_HAS_ALIAS, 0),
- _SVE_INSN ("orrs", 0x25c04000, 0xfff0c210, sve_misc, 0, OP4 (SVE_Pd, SVE_Pg4_10, SVE_Pn, SVE_Pm), OP_SVE_BZBB, F_HAS_ALIAS, 0),
- _SVE_INSN ("orv", 0x04182000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_BHSD, 0, 0),
-@@ -4035,73 +4487,73 @@ struct aarch64_opcode aarch64_opcode_tab
- _SVE_INSN ("ptrues", 0x2519e000, 0xff3ffc10, sve_size_bhsd, 0, OP2 (SVE_Pd, SVE_PATTERN), OP_SVE_VU_BHSD, F_OPD1_OPT | F_DEFAULT(31), 0),
- _SVE_INSN ("punpkhi", 0x05314000, 0xfffffe10, sve_misc, 0, OP2 (SVE_Pd, SVE_Pn), OP_SVE_HB, 0, 0),
- _SVE_INSN ("punpklo", 0x05304000, 0xfffffe10, sve_misc, 0, OP2 (SVE_Pd, SVE_Pn), OP_SVE_HB, 0, 0),
-- _SVE_INSN ("rbit", 0x05278000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_BHSD, 0, 0),
-+ _SVE_INSNC ("rbit", 0x05278000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_BHSD, 0, C_SCAN_MOVPRFX, 0),
- _SVE_INSN ("rdffr", 0x2519f000, 0xfffffff0, sve_misc, 0, OP1 (SVE_Pd), OP_SVE_B, 0, 0),
- _SVE_INSN ("rdffr", 0x2518f000, 0xfffffe10, sve_misc, 0, OP2 (SVE_Pd, SVE_Pg4_5), OP_SVE_BZ, 0, 0),
- _SVE_INSN ("rdffrs", 0x2558f000, 0xfffffe10, sve_misc, 0, OP2 (SVE_Pd, SVE_Pg4_5), OP_SVE_BZ, 0, 0),
- _SVE_INSN ("rdvl", 0x04bf5000, 0xfffff800, sve_misc, 0, OP2 (Rd, SVE_SIMM6), OP_SVE_XU, 0, 0),
- _SVE_INSN ("rev", 0x05344000, 0xff3ffe10, sve_size_bhsd, 0, OP2 (SVE_Pd, SVE_Pn), OP_SVE_VV_BHSD, 0, 0),
- _SVE_INSN ("rev", 0x05383800, 0xff3ffc00, sve_size_bhsd, 0, OP2 (SVE_Zd, SVE_Zn), OP_SVE_VV_BHSD, 0, 0),
-- _SVE_INSN ("revb", 0x05248000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, 0),
-- _SVE_INSN ("revh", 0x05a58000, 0xffbfe000, sve_size_sd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_SD, 0, 0),
-- _SVE_INSN ("revw", 0x05e68000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMD, 0, 0),
-- _SVE_INSN ("sabd", 0x040c0000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, 2),
-+ _SVE_INSNC ("revb", 0x05248000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, C_SCAN_MOVPRFX, 0),
-+ _SVE_INSNC ("revh", 0x05a58000, 0xffbfe000, sve_size_sd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_SD, 0, C_SCAN_MOVPRFX, 0),
-+ _SVE_INSNC ("revw", 0x05e68000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMD, 0, C_SCAN_MOVPRFX, 0),
-+ _SVE_INSNC ("sabd", 0x040c0000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2),
- _SVE_INSN ("saddv", 0x04002000, 0xff3fe000, sve_size_bhs, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_DUV_BHS, 0, 0),
-- _SVE_INSN ("scvtf", 0x6552a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMH, 0, 0),
-- _SVE_INSN ("scvtf", 0x6554a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMS, 0, 0),
-- _SVE_INSN ("scvtf", 0x6594a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMS, 0, 0),
-- _SVE_INSN ("scvtf", 0x65d0a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMS, 0, 0),
-- _SVE_INSN ("scvtf", 0x6556a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMD, 0, 0),
-- _SVE_INSN ("scvtf", 0x65d4a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMD, 0, 0),
-- _SVE_INSN ("scvtf", 0x65d6a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMD, 0, 0),
-- _SVE_INSN ("sdiv", 0x04940000, 0xffbfe000, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_SD, 0, 2),
-- _SVE_INSN ("sdivr", 0x04960000, 0xffbfe000, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_SD, 0, 2),
-- _SVE_INSN ("sdot", 0x44800000, 0xffa0fc00, sve_size_sd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_SD_BH, 0, 0),
-- _SVE_INSN ("sdot", 0x44a00000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX), OP_SVE_VVV_S_B, 0, 0),
-- _SVE_INSN ("sdot", 0x44e00000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm4_INDEX), OP_SVE_VVV_D_H, 0, 0),
-+ _SVE_INSNC ("scvtf", 0x6552a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMH, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0),
-+ _SVE_INSNC ("scvtf", 0x6554a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMS, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0),
-+ _SVE_INSNC ("scvtf", 0x6594a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMS, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0),
-+ _SVE_INSNC ("scvtf", 0x65d0a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMS, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0),
-+ _SVE_INSNC ("scvtf", 0x6556a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMD, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0),
-+ _SVE_INSNC ("scvtf", 0x65d4a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMD, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0),
-+ _SVE_INSNC ("scvtf", 0x65d6a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMD, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0),
-+ _SVE_INSNC ("sdiv", 0x04940000, 0xffbfe000, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_SD, 0, C_SCAN_MOVPRFX, 2),
-+ _SVE_INSNC ("sdivr", 0x04960000, 0xffbfe000, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_SD, 0, C_SCAN_MOVPRFX, 2),
-+ _SVE_INSNC ("sdot", 0x44800000, 0xffa0fc00, sve_size_sd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_SD_BH, 0, C_SCAN_MOVPRFX, 0),
-+ _SVE_INSNC ("sdot", 0x44a00000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX), OP_SVE_VVV_S_B, 0, C_SCAN_MOVPRFX, 0),
-+ _SVE_INSNC ("sdot", 0x44e00000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm4_INDEX), OP_SVE_VVV_D_H, 0, C_SCAN_MOVPRFX, 0),
- _SVE_INSN ("sel", 0x0520c000, 0xff20c000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg4_10, SVE_Zn, SVE_Zm_16), OP_SVE_VUVV_BHSD, F_HAS_ALIAS, 0),
- _SVE_INSN ("sel", 0x25004210, 0xfff0c210, sve_misc, 0, OP4 (SVE_Pd, SVE_Pg4_10, SVE_Pn, SVE_Pm), OP_SVE_BUBB, F_HAS_ALIAS, 0),
- _SVE_INSN ("setffr", 0x252c9000, 0xffffffff, sve_misc, 0, OP0 (), {}, 0, 0),
-- _SVE_INSN ("smax", 0x2528c000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zd, SVE_SIMM8), OP_SVE_VVU_BHSD, 0, 1),
-- _SVE_INSN ("smax", 0x04080000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, 2),
-+ _SVE_INSNC ("smax", 0x2528c000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zd, SVE_SIMM8), OP_SVE_VVU_BHSD, 0, C_SCAN_MOVPRFX, 1),
-+ _SVE_INSNC ("smax", 0x04080000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2),
- _SVE_INSN ("smaxv", 0x04082000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_BHSD, 0, 0),
-- _SVE_INSN ("smin", 0x252ac000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zd, SVE_SIMM8), OP_SVE_VVU_BHSD, 0, 1),
-- _SVE_INSN ("smin", 0x040a0000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, 2),
-+ _SVE_INSNC ("smin", 0x252ac000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zd, SVE_SIMM8), OP_SVE_VVU_BHSD, 0, C_SCAN_MOVPRFX, 1),
-+ _SVE_INSNC ("smin", 0x040a0000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2),
- _SVE_INSN ("sminv", 0x040a2000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_BHSD, 0, 0),
-- _SVE_INSN ("smulh", 0x04120000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, 2),
-- _SVE_INSN ("splice", 0x052c8000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VUVV_BHSD, 0, 2),
-+ _SVE_INSNC ("smulh", 0x04120000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2),
-+ _SVE_INSNC ("splice", 0x052c8000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VUVV_BHSD, 0, C_SCAN_MOVPRFX, 2),
- _SVE_INSN ("sqadd", 0x04201000, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0),
-- _SVE_INSN ("sqadd", 0x2524c000, 0xff3fc000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zd, SVE_AIMM), OP_SVE_VVU_BHSD, 0, 1),
-+ _SVE_INSNC ("sqadd", 0x2524c000, 0xff3fc000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zd, SVE_AIMM), OP_SVE_VVU_BHSD, 0, C_SCAN_MOVPRFX, 1),
- _SVE_INSN ("sqdecb", 0x0430f800, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0),
- _SVE_INSN ("sqdecb", 0x0420f800, 0xfff0fc00, sve_misc, 0, OP3 (Rd, Rd, SVE_PATTERN_SCALED), OP_SVE_XWU, F_OPD2_OPT | F_DEFAULT(31), 1),
-- _SVE_INSN ("sqdecd", 0x04e0c800, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_DU, F_OPD1_OPT | F_DEFAULT(31), 0),
-+ _SVE_INSNC ("sqdecd", 0x04e0c800, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_DU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0),
- _SVE_INSN ("sqdecd", 0x04f0f800, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0),
- _SVE_INSN ("sqdecd", 0x04e0f800, 0xfff0fc00, sve_misc, 0, OP3 (Rd, Rd, SVE_PATTERN_SCALED), OP_SVE_XWU, F_OPD2_OPT | F_DEFAULT(31), 1),
-- _SVE_INSN ("sqdech", 0x0460c800, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_HU, F_OPD1_OPT | F_DEFAULT(31), 0),
-+ _SVE_INSNC ("sqdech", 0x0460c800, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_HU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0),
- _SVE_INSN ("sqdech", 0x0470f800, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0),
- _SVE_INSN ("sqdech", 0x0460f800, 0xfff0fc00, sve_misc, 0, OP3 (Rd, Rd, SVE_PATTERN_SCALED), OP_SVE_XWU, F_OPD2_OPT | F_DEFAULT(31), 1),
-- _SVE_INSN ("sqdecp", 0x252a8000, 0xff3ffe00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Pg4_5), OP_SVE_VU_HSD, 0, 0),
-+ _SVE_INSNC ("sqdecp", 0x252a8000, 0xff3ffe00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Pg4_5), OP_SVE_VU_HSD, 0, C_SCAN_MOVPRFX, 0),
- _SVE_INSN ("sqdecp", 0x252a8c00, 0xff3ffe00, sve_size_bhsd, 0, OP2 (Rd, SVE_Pg4_5), OP_SVE_XV_BHSD, 0, 0),
- _SVE_INSN ("sqdecp", 0x252a8800, 0xff3ffe00, sve_size_bhsd, 0, OP3 (Rd, SVE_Pg4_5, Rd), OP_SVE_XVW_BHSD, 0, 2),
-- _SVE_INSN ("sqdecw", 0x04a0c800, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_SU, F_OPD1_OPT | F_DEFAULT(31), 0),
-+ _SVE_INSNC ("sqdecw", 0x04a0c800, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_SU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0),
- _SVE_INSN ("sqdecw", 0x04b0f800, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0),
- _SVE_INSN ("sqdecw", 0x04a0f800, 0xfff0fc00, sve_misc, 0, OP3 (Rd, Rd, SVE_PATTERN_SCALED), OP_SVE_XWU, F_OPD2_OPT | F_DEFAULT(31), 1),
- _SVE_INSN ("sqincb", 0x0430f000, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0),
- _SVE_INSN ("sqincb", 0x0420f000, 0xfff0fc00, sve_misc, 0, OP3 (Rd, Rd, SVE_PATTERN_SCALED), OP_SVE_XWU, F_OPD2_OPT | F_DEFAULT(31), 1),
-- _SVE_INSN ("sqincd", 0x04e0c000, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_DU, F_OPD1_OPT | F_DEFAULT(31), 0),
-+ _SVE_INSNC ("sqincd", 0x04e0c000, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_DU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0),
- _SVE_INSN ("sqincd", 0x04f0f000, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0),
- _SVE_INSN ("sqincd", 0x04e0f000, 0xfff0fc00, sve_misc, 0, OP3 (Rd, Rd, SVE_PATTERN_SCALED), OP_SVE_XWU, F_OPD2_OPT | F_DEFAULT(31), 1),
-- _SVE_INSN ("sqinch", 0x0460c000, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_HU, F_OPD1_OPT | F_DEFAULT(31), 0),
-+ _SVE_INSNC ("sqinch", 0x0460c000, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_HU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0),
- _SVE_INSN ("sqinch", 0x0470f000, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0),
- _SVE_INSN ("sqinch", 0x0460f000, 0xfff0fc00, sve_misc, 0, OP3 (Rd, Rd, SVE_PATTERN_SCALED), OP_SVE_XWU, F_OPD2_OPT | F_DEFAULT(31), 1),
-- _SVE_INSN ("sqincp", 0x25288000, 0xff3ffe00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Pg4_5), OP_SVE_VU_HSD, 0, 0),
-+ _SVE_INSNC ("sqincp", 0x25288000, 0xff3ffe00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Pg4_5), OP_SVE_VU_HSD, 0, C_SCAN_MOVPRFX, 0),
- _SVE_INSN ("sqincp", 0x25288c00, 0xff3ffe00, sve_size_bhsd, 0, OP2 (Rd, SVE_Pg4_5), OP_SVE_XV_BHSD, 0, 0),
- _SVE_INSN ("sqincp", 0x25288800, 0xff3ffe00, sve_size_bhsd, 0, OP3 (Rd, SVE_Pg4_5, Rd), OP_SVE_XVW_BHSD, 0, 2),
-- _SVE_INSN ("sqincw", 0x04a0c000, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_SU, F_OPD1_OPT | F_DEFAULT(31), 0),
-+ _SVE_INSNC ("sqincw", 0x04a0c000, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_SU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0),
- _SVE_INSN ("sqincw", 0x04b0f000, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0),
- _SVE_INSN ("sqincw", 0x04a0f000, 0xfff0fc00, sve_misc, 0, OP3 (Rd, Rd, SVE_PATTERN_SCALED), OP_SVE_XWU, F_OPD2_OPT | F_DEFAULT(31), 1),
- _SVE_INSN ("sqsub", 0x04201800, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0),
-- _SVE_INSN ("sqsub", 0x2526c000, 0xff3fc000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zd, SVE_AIMM), OP_SVE_VVU_BHSD, 0, 1),
-+ _SVE_INSNC ("sqsub", 0x2526c000, 0xff3fc000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zd, SVE_AIMM), OP_SVE_VVU_BHSD, 0, C_SCAN_MOVPRFX, 1),
- _SVE_INSN ("st1b", 0xe4004000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_BUU, F_OD(1), 0),
- _SVE_INSN ("st1b", 0xe4008000, 0xffe0a000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ_XTW_14), OP_SVE_DUD, F_OD(1), 0),
- _SVE_INSN ("st1b", 0xe400a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RZ), OP_SVE_DUD, F_OD(1), 0),
-@@ -4183,78 +4635,78 @@ struct aarch64_opcode aarch64_opcode_tab
- _SVE_INSN ("str", 0xe5800000, 0xffc0e010, sve_misc, 0, OP2 (SVE_Pt, SVE_ADDR_RI_S9xVL), {}, 0, 0),
- _SVE_INSN ("str", 0xe5804000, 0xffc0e000, sve_misc, 0, OP2 (SVE_Zt, SVE_ADDR_RI_S9xVL), {}, 0, 0),
- _SVE_INSN ("sub", 0x04200400, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0),
-- _SVE_INSN ("sub", 0x2521c000, 0xff3fc000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zd, SVE_AIMM), OP_SVE_VVU_BHSD, 0, 1),
-- _SVE_INSN ("sub", 0x04010000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, 2),
-- _SVE_INSN ("subr", 0x2523c000, 0xff3fc000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zd, SVE_AIMM), OP_SVE_VVU_BHSD, 0, 1),
-- _SVE_INSN ("subr", 0x04030000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, 2),
-+ _SVE_INSNC ("sub", 0x2521c000, 0xff3fc000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zd, SVE_AIMM), OP_SVE_VVU_BHSD, 0, C_SCAN_MOVPRFX, 1),
-+ _SVE_INSNC ("sub", 0x04010000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2),
-+ _SVE_INSNC ("subr", 0x2523c000, 0xff3fc000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zd, SVE_AIMM), OP_SVE_VVU_BHSD, 0, C_SCAN_MOVPRFX, 1),
-+ _SVE_INSNC ("subr", 0x04030000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2),
- _SVE_INSN ("sunpkhi", 0x05313800, 0xff3ffc00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Zn), OP_SVE_VV_HSD_BHS, 0, 0),
- _SVE_INSN ("sunpklo", 0x05303800, 0xff3ffc00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Zn), OP_SVE_VV_HSD_BHS, 0, 0),
-- _SVE_INSN ("sxtb", 0x0410a000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, 0),
-- _SVE_INSN ("sxth", 0x0492a000, 0xffbfe000, sve_size_sd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_SD, 0, 0),
-- _SVE_INSN ("sxtw", 0x04d4a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMD, 0, 0),
-+ _SVE_INSNC ("sxtb", 0x0410a000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, C_SCAN_MOVPRFX, 0),
-+ _SVE_INSNC ("sxth", 0x0492a000, 0xffbfe000, sve_size_sd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_SD, 0, C_SCAN_MOVPRFX, 0),
-+ _SVE_INSNC ("sxtw", 0x04d4a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMD, 0, C_SCAN_MOVPRFX, 0),
- _SVE_INSN ("tbl", 0x05203000, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_ZnxN, SVE_Zm_16), OP_SVE_VVV_BHSD, F_OD(1), 0),
- _SVE_INSN ("trn1", 0x05205000, 0xff30fe10, sve_size_bhsd, 0, OP3 (SVE_Pd, SVE_Pn, SVE_Pm), OP_SVE_VVV_BHSD, 0, 0),
- _SVE_INSN ("trn1", 0x05207000, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0),
- _SVE_INSN ("trn2", 0x05205400, 0xff30fe10, sve_size_bhsd, 0, OP3 (SVE_Pd, SVE_Pn, SVE_Pm), OP_SVE_VVV_BHSD, 0, 0),
- _SVE_INSN ("trn2", 0x05207400, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0),
-- _SVE_INSN ("uabd", 0x040d0000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, 2),
-+ _SVE_INSNC ("uabd", 0x040d0000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2),
- _SVE_INSN ("uaddv", 0x04012000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_DUV_BHSD, 0, 0),
-- _SVE_INSN ("ucvtf", 0x6553a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMH, 0, 0),
-- _SVE_INSN ("ucvtf", 0x6555a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMS, 0, 0),
-- _SVE_INSN ("ucvtf", 0x6595a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMS, 0, 0),
-- _SVE_INSN ("ucvtf", 0x65d1a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMS, 0, 0),
-- _SVE_INSN ("ucvtf", 0x6557a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMD, 0, 0),
-- _SVE_INSN ("ucvtf", 0x65d5a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMD, 0, 0),
-- _SVE_INSN ("ucvtf", 0x65d7a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMD, 0, 0),
-- _SVE_INSN ("udiv", 0x04950000, 0xffbfe000, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_SD, 0, 2),
-- _SVE_INSN ("udivr", 0x04970000, 0xffbfe000, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_SD, 0, 2),
-- _SVE_INSN ("udot", 0x44800400, 0xffa0fc00, sve_size_sd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_SD_BH, 0, 0),
-- _SVE_INSN ("udot", 0x44a00400, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX), OP_SVE_VVV_S_B, 0, 0),
-- _SVE_INSN ("udot", 0x44e00400, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm4_INDEX), OP_SVE_VVV_D_H, 0, 0),
-- _SVE_INSN ("umax", 0x2529c000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zd, SVE_UIMM8), OP_SVE_VVU_BHSD, 0, 1),
-- _SVE_INSN ("umax", 0x04090000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, 2),
-+ _SVE_INSNC ("ucvtf", 0x6553a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMH, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0),
-+ _SVE_INSNC ("ucvtf", 0x6555a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMS, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0),
-+ _SVE_INSNC ("ucvtf", 0x6595a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMS, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0),
-+ _SVE_INSNC ("ucvtf", 0x65d1a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMS, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0),
-+ _SVE_INSNC ("ucvtf", 0x6557a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMD, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0),
-+ _SVE_INSNC ("ucvtf", 0x65d5a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMD, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0),
-+ _SVE_INSNC ("ucvtf", 0x65d7a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMD, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0),
-+ _SVE_INSNC ("udiv", 0x04950000, 0xffbfe000, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_SD, 0, C_SCAN_MOVPRFX, 2),
-+ _SVE_INSNC ("udivr", 0x04970000, 0xffbfe000, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_SD, 0, C_SCAN_MOVPRFX, 2),
-+ _SVE_INSNC ("udot", 0x44800400, 0xffa0fc00, sve_size_sd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_SD_BH, 0, C_SCAN_MOVPRFX, 0),
-+ _SVE_INSNC ("udot", 0x44a00400, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX), OP_SVE_VVV_S_B, 0, C_SCAN_MOVPRFX, 0),
-+ _SVE_INSNC ("udot", 0x44e00400, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm4_INDEX), OP_SVE_VVV_D_H, 0, C_SCAN_MOVPRFX, 0),
-+ _SVE_INSNC ("umax", 0x2529c000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zd, SVE_UIMM8), OP_SVE_VVU_BHSD, 0, C_SCAN_MOVPRFX, 1),
-+ _SVE_INSNC ("umax", 0x04090000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2),
- _SVE_INSN ("umaxv", 0x04092000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_BHSD, 0, 0),
-- _SVE_INSN ("umin", 0x252bc000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zd, SVE_UIMM8), OP_SVE_VVU_BHSD, 0, 1),
-- _SVE_INSN ("umin", 0x040b0000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, 2),
-+ _SVE_INSNC ("umin", 0x252bc000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zd, SVE_UIMM8), OP_SVE_VVU_BHSD, 0, C_SCAN_MOVPRFX, 1),
-+ _SVE_INSNC ("umin", 0x040b0000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2),
- _SVE_INSN ("uminv", 0x040b2000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Vd, SVE_Pg3, SVE_Zn), OP_SVE_VUV_BHSD, 0, 0),
-- _SVE_INSN ("umulh", 0x04130000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, 2),
-+ _SVE_INSNC ("umulh", 0x04130000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2),
- _SVE_INSN ("uqadd", 0x04201400, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0),
-- _SVE_INSN ("uqadd", 0x2525c000, 0xff3fc000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zd, SVE_AIMM), OP_SVE_VVU_BHSD, 0, 1),
-+ _SVE_INSNC ("uqadd", 0x2525c000, 0xff3fc000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zd, SVE_AIMM), OP_SVE_VVU_BHSD, 0, C_SCAN_MOVPRFX, 1),
- _SVE_INSN ("uqdecb", 0x0420fc00, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_WU, F_OPD1_OPT | F_DEFAULT(31), 0),
- _SVE_INSN ("uqdecb", 0x0430fc00, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0),
-- _SVE_INSN ("uqdecd", 0x04e0cc00, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_DU, F_OPD1_OPT | F_DEFAULT(31), 0),
-+ _SVE_INSNC ("uqdecd", 0x04e0cc00, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_DU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0),
- _SVE_INSN ("uqdecd", 0x04e0fc00, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_WU, F_OPD1_OPT | F_DEFAULT(31), 0),
- _SVE_INSN ("uqdecd", 0x04f0fc00, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0),
-- _SVE_INSN ("uqdech", 0x0460cc00, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_HU, F_OPD1_OPT | F_DEFAULT(31), 0),
-+ _SVE_INSNC ("uqdech", 0x0460cc00, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_HU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0),
- _SVE_INSN ("uqdech", 0x0460fc00, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_WU, F_OPD1_OPT | F_DEFAULT(31), 0),
- _SVE_INSN ("uqdech", 0x0470fc00, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0),
-- _SVE_INSN ("uqdecp", 0x252b8000, 0xff3ffe00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Pg4_5), OP_SVE_VU_HSD, 0, 0),
-+ _SVE_INSNC ("uqdecp", 0x252b8000, 0xff3ffe00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Pg4_5), OP_SVE_VU_HSD, 0, C_SCAN_MOVPRFX, 0),
- _SVE_INSN ("uqdecp", 0x252b8800, 0xff3ffe00, sve_size_bhsd, 0, OP2 (Rd, SVE_Pg4_5), OP_SVE_WV_BHSD, 0, 0),
- _SVE_INSN ("uqdecp", 0x252b8c00, 0xff3ffe00, sve_size_bhsd, 0, OP2 (Rd, SVE_Pg4_5), OP_SVE_XV_BHSD, 0, 0),
-- _SVE_INSN ("uqdecw", 0x04a0cc00, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_SU, F_OPD1_OPT | F_DEFAULT(31), 0),
-+ _SVE_INSNC ("uqdecw", 0x04a0cc00, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_SU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0),
- _SVE_INSN ("uqdecw", 0x04a0fc00, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_WU, F_OPD1_OPT | F_DEFAULT(31), 0),
- _SVE_INSN ("uqdecw", 0x04b0fc00, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0),
- _SVE_INSN ("uqincb", 0x0420f400, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_WU, F_OPD1_OPT | F_DEFAULT(31), 0),
- _SVE_INSN ("uqincb", 0x0430f400, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0),
-- _SVE_INSN ("uqincd", 0x04e0c400, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_DU, F_OPD1_OPT | F_DEFAULT(31), 0),
-+ _SVE_INSNC ("uqincd", 0x04e0c400, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_DU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0),
- _SVE_INSN ("uqincd", 0x04e0f400, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_WU, F_OPD1_OPT | F_DEFAULT(31), 0),
- _SVE_INSN ("uqincd", 0x04f0f400, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0),
-- _SVE_INSN ("uqinch", 0x0460c400, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_HU, F_OPD1_OPT | F_DEFAULT(31), 0),
-+ _SVE_INSNC ("uqinch", 0x0460c400, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_HU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0),
- _SVE_INSN ("uqinch", 0x0460f400, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_WU, F_OPD1_OPT | F_DEFAULT(31), 0),
- _SVE_INSN ("uqinch", 0x0470f400, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0),
-- _SVE_INSN ("uqincp", 0x25298000, 0xff3ffe00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Pg4_5), OP_SVE_VU_HSD, 0, 0),
-+ _SVE_INSNC ("uqincp", 0x25298000, 0xff3ffe00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Pg4_5), OP_SVE_VU_HSD, 0, C_SCAN_MOVPRFX, 0),
- _SVE_INSN ("uqincp", 0x25298800, 0xff3ffe00, sve_size_bhsd, 0, OP2 (Rd, SVE_Pg4_5), OP_SVE_WV_BHSD, 0, 0),
- _SVE_INSN ("uqincp", 0x25298c00, 0xff3ffe00, sve_size_bhsd, 0, OP2 (Rd, SVE_Pg4_5), OP_SVE_XV_BHSD, 0, 0),
-- _SVE_INSN ("uqincw", 0x04a0c400, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_SU, F_OPD1_OPT | F_DEFAULT(31), 0),
-+ _SVE_INSNC ("uqincw", 0x04a0c400, 0xfff0fc00, sve_misc, 0, OP2 (SVE_Zd, SVE_PATTERN_SCALED), OP_SVE_SU, F_OPD1_OPT | F_DEFAULT(31), C_SCAN_MOVPRFX, 0),
- _SVE_INSN ("uqincw", 0x04a0f400, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_WU, F_OPD1_OPT | F_DEFAULT(31), 0),
- _SVE_INSN ("uqincw", 0x04b0f400, 0xfff0fc00, sve_misc, 0, OP2 (Rd, SVE_PATTERN_SCALED), OP_SVE_XU, F_OPD1_OPT | F_DEFAULT(31), 0),
- _SVE_INSN ("uqsub", 0x04201c00, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0),
-- _SVE_INSN ("uqsub", 0x2527c000, 0xff3fc000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zd, SVE_AIMM), OP_SVE_VVU_BHSD, 0, 1),
-+ _SVE_INSNC ("uqsub", 0x2527c000, 0xff3fc000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zd, SVE_AIMM), OP_SVE_VVU_BHSD, 0, C_SCAN_MOVPRFX, 1),
- _SVE_INSN ("uunpkhi", 0x05333800, 0xff3ffc00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Zn), OP_SVE_VV_HSD_BHS, 0, 0),
- _SVE_INSN ("uunpklo", 0x05323800, 0xff3ffc00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Zn), OP_SVE_VV_HSD_BHS, 0, 0),
-- _SVE_INSN ("uxtb", 0x0411a000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, 0),
-- _SVE_INSN ("uxth", 0x0493a000, 0xffbfe000, sve_size_sd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_SD, 0, 0),
-- _SVE_INSN ("uxtw", 0x04d5a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMD, 0, 0),
-+ _SVE_INSNC ("uxtb", 0x0411a000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, C_SCAN_MOVPRFX, 0),
-+ _SVE_INSNC ("uxth", 0x0493a000, 0xffbfe000, sve_size_sd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_SD, 0, C_SCAN_MOVPRFX, 0),
-+ _SVE_INSNC ("uxtw", 0x04d5a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMD, 0, C_SCAN_MOVPRFX, 0),
- _SVE_INSN ("uzp1", 0x05204800, 0xff30fe10, sve_size_bhsd, 0, OP3 (SVE_Pd, SVE_Pn, SVE_Pm), OP_SVE_VVV_BHSD, 0, 0),
- _SVE_INSN ("uzp1", 0x05206800, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0),
- _SVE_INSN ("uzp2", 0x05204c00, 0xff30fe10, sve_size_bhsd, 0, OP3 (SVE_Pd, SVE_Pn, SVE_Pm), OP_SVE_VVV_BHSD, 0, 0),
-@@ -4272,25 +4724,322 @@ struct aarch64_opcode aarch64_opcode_tab
- _SVE_INSN ("zip1", 0x05206000, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0),
- _SVE_INSN ("zip2", 0x05204400, 0xff30fe10, sve_size_bhsd, 0, OP3 (SVE_Pd, SVE_Pn, SVE_Pm), OP_SVE_VVV_BHSD, 0, 0),
- _SVE_INSN ("zip2", 0x05206400, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0),
-- _SVE_INSN ("bic", 0x05800000, 0xfffc0000, sve_limm, 0, OP3 (SVE_Zd, SVE_Zd, SVE_INV_LIMM), OP_SVE_VVU_BHSD, F_ALIAS | F_PSEUDO, 1),
-+ _SVE_INSNC ("bic", 0x05800000, 0xfffc0000, sve_limm, 0, OP3 (SVE_Zd, SVE_Zd, SVE_INV_LIMM), OP_SVE_VVU_BHSD, F_ALIAS | F_PSEUDO, C_SCAN_MOVPRFX, 1),
- _SVE_INSN ("cmple", 0x24008000, 0xff20e010, sve_size_bhsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zm_16, SVE_Zn), OP_SVE_VZVV_BHSD, F_ALIAS | F_PSEUDO, 0),
- _SVE_INSN ("cmplo", 0x24000010, 0xff20e010, sve_size_bhsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zm_16, SVE_Zn), OP_SVE_VZVV_BHSD, F_ALIAS | F_PSEUDO, 0),
- _SVE_INSN ("cmpls", 0x24000000, 0xff20e010, sve_size_bhsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zm_16, SVE_Zn), OP_SVE_VZVV_BHSD, F_ALIAS | F_PSEUDO, 0),
- _SVE_INSN ("cmplt", 0x24008010, 0xff20e010, sve_size_bhsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zm_16, SVE_Zn), OP_SVE_VZVV_BHSD, F_ALIAS | F_PSEUDO, 0),
-- _SVE_INSN ("eon", 0x05400000, 0xfffc0000, sve_limm, 0, OP3 (SVE_Zd, SVE_Zd, SVE_INV_LIMM), OP_SVE_VVU_BHSD, F_ALIAS | F_PSEUDO, 1),
-+ _SVE_INSNC ("eon", 0x05400000, 0xfffc0000, sve_limm, 0, OP3 (SVE_Zd, SVE_Zd, SVE_INV_LIMM), OP_SVE_VVU_BHSD, F_ALIAS | F_PSEUDO, C_SCAN_MOVPRFX, 1),
- _SVE_INSN ("facle", 0x6500c010, 0xff20e010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zm_16, SVE_Zn), OP_SVE_VZVV_HSD, F_ALIAS | F_PSEUDO, 0),
- _SVE_INSN ("faclt", 0x6500e010, 0xff20e010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zm_16, SVE_Zn), OP_SVE_VZVV_HSD, F_ALIAS | F_PSEUDO, 0),
- _SVE_INSN ("fcmle", 0x65004000, 0xff20e010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zm_16, SVE_Zn), OP_SVE_VZVV_HSD, F_ALIAS | F_PSEUDO, 0),
- _SVE_INSN ("fcmlt", 0x65004010, 0xff20e010, sve_size_hsd, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zm_16, SVE_Zn), OP_SVE_VZVV_HSD, F_ALIAS | F_PSEUDO, 0),
- _SVE_INSN ("fmov", 0x2538c000, 0xff3fffe0, sve_size_hsd, 0, OP2 (SVE_Zd, FPIMM0), OP_SVE_V_HSD, F_ALIAS | F_PSEUDO, 0),
-- _SVE_INSN ("fmov", 0x05104000, 0xff30ffe0, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg4_16, FPIMM0), OP_SVE_VM_HSD, F_ALIAS | F_PSEUDO, 0),
-- _SVE_INSN ("orn", 0x05000000, 0xfffc0000, sve_limm, 0, OP3 (SVE_Zd, SVE_Zd, SVE_INV_LIMM), OP_SVE_VVU_BHSD, F_ALIAS | F_PSEUDO, 1),
-+ _SVE_INSNC ("fmov", 0x05104000, 0xff30ffe0, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg4_16, FPIMM0), OP_SVE_VM_HSD, F_ALIAS | F_PSEUDO, C_SCAN_MOVPRFX, 0),
-+ _SVE_INSNC ("orn", 0x05000000, 0xfffc0000, sve_limm, 0, OP3 (SVE_Zd, SVE_Zd, SVE_INV_LIMM), OP_SVE_VVU_BHSD, F_ALIAS | F_PSEUDO, C_SCAN_MOVPRFX, 1),
-+
-+ /* SVE2 instructions. */
-+ SVE2_INSNC ("adclb", 0x4500d000, 0xffa0fc00, sve_size_sd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_SD, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSNC ("adclt", 0x4500d400, 0xffa0fc00, sve_size_sd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_SD, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSN ("addhnb", 0x45206000, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHS_HSD, 0, 0),
-+ SVE2_INSN ("addhnt", 0x45206400, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHS_HSD, 0, 0),
-+ SVE2_INSNC ("addp", 0x4411a000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zn), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2),
-+ SVE2_INSNC ("bcax", 0x04603800, 0xffe0fc00, sve_misc, 0, OP4 (SVE_Zd, SVE_Zd, SVE_Zm_16, SVE_Zn), OP_SVE_DDDD, 0, C_SCAN_MOVPRFX, 1),
-+ SVE2_INSNC ("bsl", 0x04203c00, 0xffe0fc00, sve_misc, 0, OP4 (SVE_Zd, SVE_Zd, SVE_Zm_16, SVE_Zn), OP_SVE_DDDD, 0, C_SCAN_MOVPRFX, 1),
-+ SVE2_INSNC ("bsl1n", 0x04603c00, 0xffe0fc00, sve_misc, 0, OP4 (SVE_Zd, SVE_Zd, SVE_Zm_16, SVE_Zn), OP_SVE_DDDD, 0, C_SCAN_MOVPRFX, 1),
-+ SVE2_INSNC ("bsl2n", 0x04a03c00, 0xffe0fc00, sve_misc, 0, OP4 (SVE_Zd, SVE_Zd, SVE_Zm_16, SVE_Zn), OP_SVE_DDDD, 0, C_SCAN_MOVPRFX, 1),
-+ SVE2_INSNC ("cadd", 0x4500d800, 0xff3ff800, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Zd, SVE_Zn, SVE_IMM_ROT3), OP_SVE_VVVU_BHSD, 0, C_SCAN_MOVPRFX, 1),
-+ SVE2_INSNC ("cdot", 0x44801000, 0xffa0f000, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Zn, SVE_Zm_16, SVE_IMM_ROT2), OP_SVE_VVVU_SD_BH, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSNC ("cdot", 0x44e04000, 0xffe0f000, sve_misc, 0, OP4 (SVE_Zd, SVE_Zn, SVE_Zm4_INDEX, SVE_IMM_ROT2), OP_SVE_DHHU, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSNC ("cdot", 0x44a04000, 0xffe0f000, sve_misc, 0, OP4 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX, SVE_IMM_ROT2), OP_SVE_SBBU, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSNC ("cmla", 0x44002000, 0xff20f000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Zn, SVE_Zm_16, SVE_IMM_ROT2), OP_SVE_VVVU_BHSD, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSNC ("cmla", 0x44a06000, 0xffe0f000, sve_misc, 0, OP4 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX, SVE_IMM_ROT2), OP_SVE_VVVU_H, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSNC ("cmla", 0x44e06000, 0xffe0f000, sve_misc, 0, OP4 (SVE_Zd, SVE_Zn, SVE_Zm4_INDEX, SVE_IMM_ROT2), OP_SVE_VVVU_S, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSNC ("eor3", 0x04203800, 0xffe0fc00, sve_misc, 0, OP4 (SVE_Zd, SVE_Zd, SVE_Zm_16, SVE_Zn), OP_SVE_DDDD, 0, C_SCAN_MOVPRFX, 1),
-+ SVE2_INSNC ("eorbt", 0x45009000, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSNC ("eortb", 0x45009400, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSN ("ext", 0x05600000, 0xffe0e000, sve_misc, 0, OP3 (SVE_Zd, SVE_ZnxN, SVE_UIMM8_53), OP_SVE_BBU, F_OD(2), 0),
-+ SVE2_INSNC ("faddp", 0x64108000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zn), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 2),
-+ SVE2_INSN ("fcvtlt", 0x6489a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMH, 0, 0),
-+ SVE2_INSN ("fcvtlt", 0x64cba000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_DMS, 0, 0),
-+ SVE2_INSN ("fcvtnt", 0x6488a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMS, 0, 0),
-+ SVE2_INSN ("fcvtnt", 0x64caa000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMD, 0, 0),
-+ SVE2_INSNC ("fcvtx", 0x650aa000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMD, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0),
-+ SVE2_INSN ("fcvtxnt", 0x640aa000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMD, 0, 0),
-+ SVE2_INSNC ("flogb", 0x6518a000, 0xfff9e000, sve_size_hsd2, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSNC ("fmaxnmp", 0x64148000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zn), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 2),
-+ SVE2_INSNC ("fmaxp", 0x64168000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zn), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 2),
-+ SVE2_INSNC ("fminnmp", 0x64158000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zn), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 2),
-+ SVE2_INSNC ("fminp", 0x64178000, 0xff3fe000, sve_size_hsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zn), OP_SVE_VMVV_HSD, 0, C_SCAN_MOVPRFX, 2),
-+ SVE2_INSNC ("fmlalb", 0x64a04000, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSNC ("fmlalb", 0x64a08000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSNC ("fmlalt", 0x64a04400, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSNC ("fmlalt", 0x64a08400, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSNC ("fmlslb", 0x64a06000, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSNC ("fmlslb", 0x64a0a000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSNC ("fmlslt", 0x64a06400, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSNC ("fmlslt", 0x64a0a400, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSN ("histcnt", 0x45a0c000, 0xffa0e000, sve_size_sd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVV_SD, 0, 0),
-+ SVE2_INSN ("histseg", 0x4520a000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_BBB, 0, 0),
-+ SVE2_INSN ("ldnt1b", 0x8400a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZX), OP_SVE_SZS, F_OD(1), 0),
-+ SVE2_INSN ("ldnt1b", 0xc400c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZX), OP_SVE_DZD, F_OD(1), 0),
-+ SVE2_INSN ("ldnt1d", 0xc580c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZX), OP_SVE_DZD, F_OD(1), 0),
-+ SVE2_INSN ("ldnt1h", 0x8480a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZX), OP_SVE_SZS, F_OD(1), 0),
-+ SVE2_INSN ("ldnt1h", 0xc480c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZX), OP_SVE_DZD, F_OD(1), 0),
-+ SVE2_INSN ("ldnt1sb", 0x84008000, 0xbfe0e000, sve_size_sd2, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZX), OP_SVE_VZV_SD, F_OD(1), 0),
-+ SVE2_INSN ("ldnt1sh", 0x84808000, 0xbfe0e000, sve_size_sd2, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZX), OP_SVE_VZV_SD, F_OD(1), 0),
-+ SVE2_INSN ("ldnt1sw", 0xc5008000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZX), OP_SVE_DZD, F_OD(1), 0),
-+ SVE2_INSN ("ldnt1w", 0x8500a000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZX), OP_SVE_SZS, F_OD(1), 0),
-+ SVE2_INSN ("ldnt1w", 0xc500c000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZX), OP_SVE_DZD, F_OD(1), 0),
-+ SVE2_INSN ("match", 0x45208000, 0xffa0e010, sve_size_bh, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVV_BH, 0, 0),
-+ SVE2_INSNC ("mla", 0x44200800, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_22_INDEX), OP_SVE_HHH, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSNC ("mla", 0x44a00800, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX), OP_SVE_SSS, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSNC ("mla", 0x44e00800, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm4_INDEX), OP_SVE_DDD, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSNC ("mls", 0x44200c00, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_22_INDEX), OP_SVE_HHH, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSNC ("mls", 0x44a00c00, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX), OP_SVE_SSS, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSNC ("mls", 0x44e00c00, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm4_INDEX), OP_SVE_DDD, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSN ("mul", 0x4420f800, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_22_INDEX), OP_SVE_HHH, 0, 0),
-+ SVE2_INSN ("mul", 0x44a0f800, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX), OP_SVE_SSS, 0, 0),
-+ SVE2_INSN ("mul", 0x44e0f800, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm4_INDEX), OP_SVE_DDD, 0, 0),
-+ SVE2_INSN ("mul", 0x04206000, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0),
-+ SVE2_INSNC ("nbsl", 0x04e03c00, 0xffe0fc00, sve_misc, 0, OP4 (SVE_Zd, SVE_Zd, SVE_Zm_16, SVE_Zn), OP_SVE_DDDD, 0, C_SCAN_MOVPRFX, 1),
-+ SVE2_INSN ("nmatch", 0x45208010, 0xffa0e010, sve_size_bh, 0, OP4 (SVE_Pd, SVE_Pg3, SVE_Zn, SVE_Zm_16), OP_SVE_VZVV_BH, 0, 0),
-+ SVE2_INSN ("pmul", 0x04206400, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_BBB, 0, 0),
-+ SVE2_INSN ("pmullb", 0x45406800, 0xff60fc00, sve_size_13, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HD_BS, 0, 0),
-+ SVE2_INSN ("pmullt", 0x45406c00, 0xff60fc00, sve_size_13, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HD_BS, 0, 0),
-+ SVE2_INSN ("raddhnb", 0x45206800, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHS_HSD, 0, 0),
-+ SVE2_INSN ("raddhnt", 0x45206c00, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHS_HSD, 0, 0),
-+ SVE2_INSN ("rshrnb", 0x45201800, 0xffa0fc00, sve_shift_tsz_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_SHRIMM_UNPRED_22), OP_SVE_VVU_BHS_HSD, 0, 0),
-+ SVE2_INSN ("rshrnt", 0x45201c00, 0xffa0fc00, sve_shift_tsz_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_SHRIMM_UNPRED_22), OP_SVE_VVU_BHS_HSD, 0, 0),
-+ SVE2_INSN ("rsubhnb", 0x45207800, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHS_HSD, 0, 0),
-+ SVE2_INSN ("rsubhnt", 0x45207c00, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHS_HSD, 0, 0),
-+ SVE2_INSNC ("saba", 0x4500f800, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSNC ("sabalb", 0x4500c000, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSNC ("sabalt", 0x4500c400, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSN ("sabdlb", 0x45003000, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS, 0, 0),
-+ SVE2_INSN ("sabdlt", 0x45003400, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS, 0, 0),
-+ SVE2_INSNC ("sadalp", 0x4404a000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD_BHS, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSN ("saddlb", 0x45000000, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS, 0, 0),
-+ SVE2_INSN ("saddlbt", 0x45008000, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS, 0, 0),
-+ SVE2_INSN ("saddlt", 0x45000400, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS, 0, 0),
-+ SVE2_INSN ("saddwb", 0x45004000, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS2, 0, 0),
-+ SVE2_INSN ("saddwt", 0x45004400, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS2, 0, 0),
-+ SVE2_INSNC ("sbclb", 0x4580d000, 0xffa0fc00, sve_size_sd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_SD, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSNC ("sbclt", 0x4580d400, 0xffa0fc00, sve_size_sd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_SD, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSNC ("shadd", 0x44108000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zn), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2),
-+ SVE2_INSN ("shrnb", 0x45201000, 0xffa0fc00, sve_shift_tsz_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_SHRIMM_UNPRED_22), OP_SVE_VVU_BHS_HSD, 0, 0),
-+ SVE2_INSN ("shrnt", 0x45201400, 0xffa0fc00, sve_shift_tsz_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_SHRIMM_UNPRED_22), OP_SVE_VVU_BHS_HSD, 0, 0),
-+ SVE2_INSNC ("shsub", 0x44128000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zn), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2),
-+ SVE2_INSNC ("shsubr", 0x44168000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zn), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2),
-+ SVE2_INSN ("sli", 0x4500f400, 0xff20fc00, sve_shift_tsz_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_SHLIMM_UNPRED), OP_SVE_VVU_BHSD, 0, 0),
-+ SVE2_INSNC ("smaxp", 0x4414a000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zn), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2),
-+ SVE2_INSNC ("sminp", 0x4416a000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zn), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2),
-+ SVE2_INSNC ("smlalb", 0x44a08000, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSNC ("smlalb", 0x44e08000, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm4_11_INDEX), OP_SVE_DSS, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSNC ("smlalb", 0x44004000, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSNC ("smlalt", 0x44a08400, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSNC ("smlalt", 0x44e08400, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm4_11_INDEX), OP_SVE_DSS, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSNC ("smlalt", 0x44004400, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSNC ("smlslb", 0x44a0a000, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSNC ("smlslb", 0x44e0a000, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm4_11_INDEX), OP_SVE_DSS, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSNC ("smlslb", 0x44005000, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSNC ("smlslt", 0x44a0a400, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSNC ("smlslt", 0x44e0a400, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm4_11_INDEX), OP_SVE_DSS, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSNC ("smlslt", 0x44005400, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSN ("smulh", 0x04206800, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0),
-+ SVE2_INSN ("smullb", 0x44a0c000, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_SHH, 0, 0),
-+ SVE2_INSN ("smullb", 0x44e0c000, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm4_11_INDEX), OP_SVE_DSS, 0, 0),
-+ SVE2_INSN ("smullb", 0x45007000, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS, 0, 0),
-+ SVE2_INSN ("smullt", 0x44a0c400, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_SHH, 0, 0),
-+ SVE2_INSN ("smullt", 0x44e0c400, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm4_11_INDEX), OP_SVE_DSS, 0, 0),
-+ SVE2_INSN ("smullt", 0x45007400, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS, 0, 0),
-+ SVE2_INSN ("splice", 0x052d8000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_ZnxN), OP_SVE_VUV_BHSD, F_OD(2), 0),
-+ SVE2_INSNC ("sqabs", 0x4408a000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_BHSD, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSNC ("sqadd", 0x44188000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zn), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2),
-+ SVE2_INSNC ("sqcadd", 0x4501d800, 0xff3ff800, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Zd, SVE_Zn, SVE_IMM_ROT3), OP_SVE_VVVU_BHSD, 0, C_SCAN_MOVPRFX, 1),
-+ SVE2_INSNC ("sqdmlalb", 0x44a02000, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSNC ("sqdmlalb", 0x44e02000, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm4_11_INDEX), OP_SVE_DSS, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSNC ("sqdmlalb", 0x44006000, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSNC ("sqdmlalbt", 0x44000800, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSNC ("sqdmlalt", 0x44a02400, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSNC ("sqdmlalt", 0x44e02400, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm4_11_INDEX), OP_SVE_DSS, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSNC ("sqdmlalt", 0x44006400, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSNC ("sqdmlslb", 0x44a03000, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSNC ("sqdmlslb", 0x44e03000, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm4_11_INDEX), OP_SVE_DSS, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSNC ("sqdmlslb", 0x44006800, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSNC ("sqdmlslbt", 0x44000c00, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSNC ("sqdmlslt", 0x44a03400, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSNC ("sqdmlslt", 0x44e03400, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm4_11_INDEX), OP_SVE_DSS, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSNC ("sqdmlslt", 0x44006c00, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSN ("sqdmulh", 0x4420f000, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_22_INDEX), OP_SVE_HHH, 0, 0),
-+ SVE2_INSN ("sqdmulh", 0x44a0f000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX), OP_SVE_SSS, 0, 0),
-+ SVE2_INSN ("sqdmulh", 0x44e0f000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm4_INDEX), OP_SVE_DDD, 0, 0),
-+ SVE2_INSN ("sqdmulh", 0x04207000, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0),
-+ SVE2_INSN ("sqdmullb", 0x44a0e000, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_SHH, 0, 0),
-+ SVE2_INSN ("sqdmullb", 0x44e0e000, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm4_11_INDEX), OP_SVE_DSS, 0, 0),
-+ SVE2_INSN ("sqdmullb", 0x45006000, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS, 0, 0),
-+ SVE2_INSN ("sqdmullt", 0x44a0e400, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_SHH, 0, 0),
-+ SVE2_INSN ("sqdmullt", 0x44e0e400, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm4_11_INDEX), OP_SVE_DSS, 0, 0),
-+ SVE2_INSN ("sqdmullt", 0x45006400, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS, 0, 0),
-+ SVE2_INSNC ("sqneg", 0x4409a000, 0xff3fe000, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_BHSD, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSNC ("sqrdcmlah", 0x44a07000, 0xffe0f000, sve_misc, 0, OP4 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX, SVE_IMM_ROT2), OP_SVE_HHHU, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSNC ("sqrdcmlah", 0x44e07000, 0xffe0f000, sve_misc, 0, OP4 (SVE_Zd, SVE_Zn, SVE_Zm4_INDEX, SVE_IMM_ROT2), OP_SVE_SSSU, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSNC ("sqrdcmlah", 0x44003000, 0xff20f000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Zn, SVE_Zm_16, SVE_IMM_ROT2), OP_SVE_VVVU_BHSD, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSNC ("sqrdmlah", 0x44201000, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_22_INDEX), OP_SVE_HHH, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSNC ("sqrdmlah", 0x44a01000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX), OP_SVE_SSS, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSNC ("sqrdmlah", 0x44e01000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm4_INDEX), OP_SVE_DDD, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSNC ("sqrdmlah", 0x44007000, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSNC ("sqrdmlsh", 0x44201400, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_22_INDEX), OP_SVE_HHH, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSNC ("sqrdmlsh", 0x44a01400, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX), OP_SVE_SSS, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSNC ("sqrdmlsh", 0x44e01400, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm4_INDEX), OP_SVE_DDD, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSNC ("sqrdmlsh", 0x44007400, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSN ("sqrdmulh", 0x4420f400, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_22_INDEX), OP_SVE_HHH, 0, 0),
-+ SVE2_INSN ("sqrdmulh", 0x44a0f400, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX), OP_SVE_SSS, 0, 0),
-+ SVE2_INSN ("sqrdmulh", 0x44e0f400, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm4_INDEX), OP_SVE_DDD, 0, 0),
-+ SVE2_INSN ("sqrdmulh", 0x04207400, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0),
-+ SVE2_INSNC ("sqrshl", 0x440a8000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zn), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2),
-+ SVE2_INSNC ("sqrshlr", 0x440e8000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zn), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2),
-+ SVE2_INSN ("sqrshrnb", 0x45202800, 0xffa0fc00, sve_shift_tsz_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_SHRIMM_UNPRED_22), OP_SVE_VVU_BHS_HSD, 0, 0),
-+ SVE2_INSN ("sqrshrnt", 0x45202c00, 0xffa0fc00, sve_shift_tsz_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_SHRIMM_UNPRED_22), OP_SVE_VVU_BHS_HSD, 0, 0),
-+ SVE2_INSN ("sqrshrunb", 0x45200800, 0xffa0fc00, sve_shift_tsz_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_SHRIMM_UNPRED_22), OP_SVE_VVU_BHS_HSD, 0, 0),
-+ SVE2_INSN ("sqrshrunt", 0x45200c00, 0xffa0fc00, sve_shift_tsz_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_SHRIMM_UNPRED_22), OP_SVE_VVU_BHS_HSD, 0, 0),
-+ SVE2_INSNC ("sqshl", 0x04068000, 0xff3fe000, sve_shift_pred, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_SHLIMM_PRED), OP_SVE_VMVU_BHSD, 0, C_SCAN_MOVPRFX, 2),
-+ SVE2_INSNC ("sqshl", 0x44088000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zn), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2),
-+ SVE2_INSNC ("sqshlr", 0x440c8000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zn), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2),
-+ SVE2_INSNC ("sqshlu", 0x040f8000, 0xff3fe000, sve_shift_pred, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_SHLIMM_PRED), OP_SVE_VMVU_BHSD, 0, C_SCAN_MOVPRFX, 2),
-+ SVE2_INSN ("sqshrnb", 0x45202000, 0xffa0fc00, sve_shift_tsz_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_SHRIMM_UNPRED_22), OP_SVE_VVU_BHS_HSD, 0, 0),
-+ SVE2_INSN ("sqshrnt", 0x45202400, 0xffa0fc00, sve_shift_tsz_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_SHRIMM_UNPRED_22), OP_SVE_VVU_BHS_HSD, 0, 0),
-+ SVE2_INSN ("sqshrunb", 0x45200000, 0xffa0fc00, sve_shift_tsz_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_SHRIMM_UNPRED_22), OP_SVE_VVU_BHS_HSD, 0, 0),
-+ SVE2_INSN ("sqshrunt", 0x45200400, 0xffa0fc00, sve_shift_tsz_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_SHRIMM_UNPRED_22), OP_SVE_VVU_BHS_HSD, 0, 0),
-+ SVE2_INSNC ("sqsub", 0x441a8000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zn), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2),
-+ SVE2_INSNC ("sqsubr", 0x441e8000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zn), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2),
-+ SVE2_INSN ("sqxtnb", 0x45204000, 0xffa7fc00, sve_size_tsz_bhs, 0, OP2 (SVE_Zd, SVE_Zn), OP_SVE_VV_BHS_HSD, 0, 0),
-+ SVE2_INSN ("sqxtnt", 0x45204400, 0xffa7fc00, sve_size_tsz_bhs, 0, OP2 (SVE_Zd, SVE_Zn), OP_SVE_VV_BHS_HSD, 0, 0),
-+ SVE2_INSN ("sqxtunb", 0x45205000, 0xffa7fc00, sve_size_tsz_bhs, 0, OP2 (SVE_Zd, SVE_Zn), OP_SVE_VV_BHS_HSD, 0, 0),
-+ SVE2_INSN ("sqxtunt", 0x45205400, 0xffa7fc00, sve_size_tsz_bhs, 0, OP2 (SVE_Zd, SVE_Zn), OP_SVE_VV_BHS_HSD, 0, 0),
-+ SVE2_INSNC ("srhadd", 0x44148000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zn), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2),
-+ SVE2_INSN ("sri", 0x4500f000, 0xff20fc00, sve_shift_tsz_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_SHRIMM_UNPRED), OP_SVE_VVU_BHSD, 0, 0),
-+ SVE2_INSNC ("srshl", 0x44028000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zn), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2),
-+ SVE2_INSNC ("srshlr", 0x44068000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zn), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2),
-+ SVE2_INSNC ("srshr", 0x040c8000, 0xff3fe000, sve_shift_pred, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_SHRIMM_PRED), OP_SVE_VMVU_BHSD, 0, C_SCAN_MOVPRFX, 2),
-+ SVE2_INSNC ("srsra", 0x4500e800, 0xff20fc00, sve_shift_tsz_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_SHRIMM_UNPRED), OP_SVE_VVU_BHSD, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSN ("sshllb", 0x4500a000, 0xffa0fc00, sve_shift_tsz_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_SHLIMM_UNPRED_22), OP_SVE_VVU_HSD_BHS, 0, 0),
-+ SVE2_INSN ("sshllt", 0x4500a400, 0xffa0fc00, sve_shift_tsz_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_SHLIMM_UNPRED_22), OP_SVE_VVU_HSD_BHS, 0, 0),
-+ SVE2_INSNC ("ssra", 0x4500e000, 0xff20fc00, sve_shift_tsz_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_SHRIMM_UNPRED), OP_SVE_VVU_BHSD, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSN ("ssublb", 0x45001000, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS, 0, 0),
-+ SVE2_INSN ("ssublbt", 0x45008800, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS, 0, 0),
-+ SVE2_INSN ("ssublt", 0x45001400, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS, 0, 0),
-+ SVE2_INSN ("ssubltb", 0x45008c00, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS, 0, 0),
-+ SVE2_INSN ("ssubwb", 0x45005000, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS2, 0, 0),
-+ SVE2_INSN ("ssubwt", 0x45005400, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS2, 0, 0),
-+ SVE2_INSN ("stnt1b", 0xe4402000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZX), OP_SVE_SUS, F_OD(1), 0),
-+ SVE2_INSN ("stnt1b", 0xe4002000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZX), OP_SVE_DUD, F_OD(1), 0),
-+ SVE2_INSN ("stnt1d", 0xe5802000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZX), OP_SVE_DUD, F_OD(1), 0),
-+ SVE2_INSN ("stnt1h", 0xe4c02000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZX), OP_SVE_SUS, F_OD(1), 0),
-+ SVE2_INSN ("stnt1h", 0xe4802000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZX), OP_SVE_DUD, F_OD(1), 0),
-+ SVE2_INSN ("stnt1w", 0xe5402000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZX), OP_SVE_SUS, F_OD(1), 0),
-+ SVE2_INSN ("stnt1w", 0xe5002000, 0xffe0e000, sve_misc, 0, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_ZX), OP_SVE_DUD, F_OD(1), 0),
-+ SVE2_INSN ("subhnb", 0x45207000, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHS_HSD, 0, 0),
-+ SVE2_INSN ("subhnt", 0x45207400, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHS_HSD, 0, 0),
-+ SVE2_INSNC ("suqadd", 0x441c8000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zn), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2),
-+ SVE2_INSN ("tbl", 0x05202800, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_ZnxN, SVE_Zm_16), OP_SVE_VVV_BHSD, F_OD(2), 0),
-+ SVE2_INSN ("tbx", 0x05202c00, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0),
-+ SVE2_INSNC ("uaba", 0x4500fc00, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSNC ("uabalb", 0x4500c800, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSNC ("uabalt", 0x4500cc00, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSN ("uabdlb", 0x45003800, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS, 0, 0),
-+ SVE2_INSN ("uabdlt", 0x45003c00, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS, 0, 0),
-+ SVE2_INSNC ("uadalp", 0x4405a000, 0xff3fe000, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_VMV_HSD_BHS, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSN ("uaddlb", 0x45000800, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS, 0, 0),
-+ SVE2_INSN ("uaddlt", 0x45000c00, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS, 0, 0),
-+ SVE2_INSN ("uaddwb", 0x45004800, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS2, 0, 0),
-+ SVE2_INSN ("uaddwt", 0x45004c00, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS2, 0, 0),
-+ SVE2_INSNC ("uhadd", 0x44118000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zn), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2),
-+ SVE2_INSNC ("uhsub", 0x44138000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zn), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2),
-+ SVE2_INSNC ("uhsubr", 0x44178000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zn), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2),
-+ SVE2_INSNC ("umaxp", 0x4415a000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zn), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2),
-+ SVE2_INSNC ("uminp", 0x4417a000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zn), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2),
-+ SVE2_INSNC ("umlalb", 0x44a09000, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSNC ("umlalb", 0x44e09000, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm4_11_INDEX), OP_SVE_DSS, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSNC ("umlalb", 0x44004800, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSNC ("umlalt", 0x44a09400, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSNC ("umlalt", 0x44e09400, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm4_11_INDEX), OP_SVE_DSS, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSNC ("umlalt", 0x44004c00, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSNC ("umlslb", 0x44a0b000, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSNC ("umlslb", 0x44e0b000, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm4_11_INDEX), OP_SVE_DSS, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSNC ("umlslb", 0x44005800, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSNC ("umlslt", 0x44a0b400, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSNC ("umlslt", 0x44e0b400, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm4_11_INDEX), OP_SVE_DSS, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSNC ("umlslt", 0x44005c00, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSN ("umulh", 0x04206c00, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0),
-+ SVE2_INSN ("umullb", 0x44a0d000, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_SHH, 0, 0),
-+ SVE2_INSN ("umullb", 0x44e0d000, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm4_11_INDEX), OP_SVE_DSS, 0, 0),
-+ SVE2_INSN ("umullb", 0x45007800, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS, 0, 0),
-+ SVE2_INSN ("umullt", 0x44a0d400, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_SHH, 0, 0),
-+ SVE2_INSN ("umullt", 0x44e0d400, 0xffe0f400, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm4_11_INDEX), OP_SVE_DSS, 0, 0),
-+ SVE2_INSN ("umullt", 0x45007c00, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS, 0, 0),
-+ SVE2_INSNC ("uqadd", 0x44198000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zn), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2),
-+ SVE2_INSNC ("uqrshl", 0x440b8000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zn), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2),
-+ SVE2_INSNC ("uqrshlr", 0x440f8000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zn), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2),
-+ SVE2_INSN ("uqrshrnb", 0x45203800, 0xffa0fc00, sve_shift_tsz_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_SHRIMM_UNPRED_22), OP_SVE_VVU_BHS_HSD, 0, 0),
-+ SVE2_INSN ("uqrshrnt", 0x45203c00, 0xffa0fc00, sve_shift_tsz_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_SHRIMM_UNPRED_22), OP_SVE_VVU_BHS_HSD, 0, 0),
-+ SVE2_INSNC ("uqshl", 0x04078000, 0xff3fe000, sve_shift_pred, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_SHLIMM_PRED), OP_SVE_VMVU_BHSD, 0, C_SCAN_MOVPRFX, 2),
-+ SVE2_INSNC ("uqshl", 0x44098000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zn), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2),
-+ SVE2_INSNC ("uqshlr", 0x440d8000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zn), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2),
-+ SVE2_INSN ("uqshrnb", 0x45203000, 0xffa0fc00, sve_shift_tsz_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_SHRIMM_UNPRED_22), OP_SVE_VVU_BHS_HSD, 0, 0),
-+ SVE2_INSN ("uqshrnt", 0x45203400, 0xffa0fc00, sve_shift_tsz_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_SHRIMM_UNPRED_22), OP_SVE_VVU_BHS_HSD, 0, 0),
-+ SVE2_INSNC ("uqsub", 0x441b8000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zn), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2),
-+ SVE2_INSNC ("uqsubr", 0x441f8000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zn), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2),
-+ SVE2_INSN ("uqxtnb", 0x45204800, 0xffa7fc00, sve_size_tsz_bhs, 0, OP2 (SVE_Zd, SVE_Zn), OP_SVE_VV_BHS_HSD, 0, 0),
-+ SVE2_INSN ("uqxtnt", 0x45204c00, 0xffa7fc00, sve_size_tsz_bhs, 0, OP2 (SVE_Zd, SVE_Zn), OP_SVE_VV_BHS_HSD, 0, 0),
-+ SVE2_INSNC ("urecpe", 0x4480a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMS, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSNC ("urhadd", 0x44158000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zn), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2),
-+ SVE2_INSNC ("urshl", 0x44038000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zn), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2),
-+ SVE2_INSNC ("urshlr", 0x44078000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zn), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2),
-+ SVE2_INSNC ("urshr", 0x040d8000, 0xff3fe000, sve_shift_pred, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_SHRIMM_PRED), OP_SVE_VMVU_BHSD, 0, C_SCAN_MOVPRFX, 2),
-+ SVE2_INSNC ("ursqrte", 0x4481a000, 0xffffe000, sve_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_SMS, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSNC ("ursra", 0x4500ec00, 0xff20fc00, sve_shift_tsz_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_SHRIMM_UNPRED), OP_SVE_VVU_BHSD, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSN ("ushllb", 0x4500a800, 0xffa0fc00, sve_shift_tsz_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_SHLIMM_UNPRED_22), OP_SVE_VVU_HSD_BHS, 0, 0),
-+ SVE2_INSN ("ushllt", 0x4500ac00, 0xffa0fc00, sve_shift_tsz_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_SHLIMM_UNPRED_22), OP_SVE_VVU_HSD_BHS, 0, 0),
-+ SVE2_INSNC ("usqadd", 0x441d8000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zn), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2),
-+ SVE2_INSNC ("usra", 0x4500e400, 0xff20fc00, sve_shift_tsz_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_SHRIMM_UNPRED), OP_SVE_VVU_BHSD, 0, C_SCAN_MOVPRFX, 0),
-+ SVE2_INSN ("usublb", 0x45001800, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS, 0, 0),
-+ SVE2_INSN ("usublt", 0x45001c00, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS, 0, 0),
-+ SVE2_INSN ("usubwb", 0x45005800, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS2, 0, 0),
-+ SVE2_INSN ("usubwt", 0x45005c00, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS2, 0, 0),
-+ SVE2_INSN ("whilege", 0x25200000, 0xff20fc10, sve_size_bhsd, 0, OP3 (SVE_Pd, Rn, Rm), OP_SVE_VWW_BHSD, 0, 0),
-+ SVE2_INSN ("whilege", 0x25201000, 0xff20fc10, sve_size_bhsd, 0, OP3 (SVE_Pd, Rn, Rm), OP_SVE_VXX_BHSD, 0, 0),
-+ SVE2_INSN ("whilegt", 0x25200010, 0xff20fc10, sve_size_bhsd, 0, OP3 (SVE_Pd, Rn, Rm), OP_SVE_VWW_BHSD, 0, 0),
-+ SVE2_INSN ("whilegt", 0x25201010, 0xff20fc10, sve_size_bhsd, 0, OP3 (SVE_Pd, Rn, Rm), OP_SVE_VXX_BHSD, 0, 0),
-+ SVE2_INSN ("whilehi", 0x25200810, 0xff20fc10, sve_size_bhsd, 0, OP3 (SVE_Pd, Rn, Rm), OP_SVE_VWW_BHSD, 0, 0),
-+ SVE2_INSN ("whilehi", 0x25201810, 0xff20fc10, sve_size_bhsd, 0, OP3 (SVE_Pd, Rn, Rm), OP_SVE_VXX_BHSD, 0, 0),
-+ SVE2_INSN ("whilehs", 0x25200800, 0xff20fc10, sve_size_bhsd, 0, OP3 (SVE_Pd, Rn, Rm), OP_SVE_VWW_BHSD, 0, 0),
-+ SVE2_INSN ("whilehs", 0x25201800, 0xff20fc10, sve_size_bhsd, 0, OP3 (SVE_Pd, Rn, Rm), OP_SVE_VXX_BHSD, 0, 0),
-+ SVE2_INSN ("whilerw", 0x25203010, 0xff20fc10, sve_size_bhsd, 0, OP3 (SVE_Pd, Rn, Rm), OP_SVE_VXX_BHSD, 0, 0),
-+ SVE2_INSN ("whilewr", 0x25203000, 0xff20fc10, sve_size_bhsd, 0, OP3 (SVE_Pd, Rn, Rm), OP_SVE_VXX_BHSD, 0, 0),
-+ SVE2_INSNC ("xar", 0x04203400, 0xff20fc00, sve_shift_tsz_bhsd, 0, OP4 (SVE_Zd, SVE_Zd, SVE_Zn, SVE_SHRIMM_UNPRED), OP_SVE_VVVU_BHSD, 0, C_SCAN_MOVPRFX, 1),
-+ /* SVE2_SM4 instructions. */
-+ SVE2SM4_INSN ("sm4e", 0x4523e000, 0xfffffc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zd, SVE_Zn), OP_SVE_SSS, 0, 1),
-+ SVE2SM4_INSN ("sm4ekey", 0x4520f000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SSS, 0, 0),
-+ /* SVE2_AES instructions. */
-+ SVE2AES_INSN ("aesd", 0x4522e400, 0xfffffc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zd, SVE_Zn), OP_SVE_BBB, 0, 1),
-+ SVE2AES_INSN ("aese", 0x4522e000, 0xfffffc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zd, SVE_Zn), OP_SVE_BBB, 0, 1),
-+ SVE2AES_INSN ("aesimc", 0x4520e400, 0xffffffe0, sve_misc, 0, OP2 (SVE_Zd, SVE_Zd), OP_SVE_BB, 0, 1),
-+ SVE2AES_INSN ("aesmc", 0x4520e000, 0xffffffe0, sve_misc, 0, OP2 (SVE_Zd, SVE_Zd), OP_SVE_BB, 0, 1),
-+ SVE2AES_INSN ("pmullb", 0x45006800, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_Q_D, 0, 0),
-+ SVE2AES_INSN ("pmullt", 0x45006c00, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_Q_D, 0, 0),
-+ /* SVE2_SHA3 instructions. */
-+ SVE2SHA3_INSN ("rax1", 0x4520f400, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_DDD, 0, 0),
-+ /* SVE2_BITPERM instructions. */
-+ SVE2BITPERM_INSN ("bdep", 0x4500b400, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0),
-+ SVE2BITPERM_INSN ("bext", 0x4500b000, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0),
-+ SVE2BITPERM_INSN ("bgrp", 0x4500b800, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0),
-
- /* SIMD Dot Product (optional in v8.2-A). */
- DOT_INSN ("udot", 0x2e009400, 0xbf20fc00, dotproduct, OP3 (Vd, Vn, Vm), QL_V3DOT, F_SIZEQ),
- DOT_INSN ("sdot", 0xe009400, 0xbf20fc00, dotproduct, OP3 (Vd, Vn, Vm), QL_V3DOT, F_SIZEQ),
-- DOT_INSN ("udot", 0x2f00e000, 0xbf00f000, dotproduct, OP3 (Vd, Vn, Em), QL_V2DOT, F_SIZEQ),
-- DOT_INSN ("sdot", 0xf00e000, 0xbf00f000, dotproduct, OP3 (Vd, Vn, Em), QL_V2DOT, F_SIZEQ),
-+ DOT_INSN ("udot", 0x2f00e000, 0xbf00f400, dotproduct, OP3 (Vd, Vn, Em), QL_V2DOT, F_SIZEQ),
-+ DOT_INSN ("sdot", 0xf00e000, 0xbf00f400, dotproduct, OP3 (Vd, Vn, Em), QL_V2DOT, F_SIZEQ),
- /* Crypto SHA2 (optional in ARMv8.2-a). */
- SHA2_INSN ("sha512h", 0xce608000, 0xffe0fc00, cryptosha2, OP3 (Fd, Fn, Vm), QL_SHA512UPT, 0),
- SHA2_INSN ("sha512h2", 0xce608400, 0xffe0fc00, cryptosha2, OP3 (Fd, Fn, Vm), QL_SHA512UPT, 0),
-@@ -4323,20 +5072,19 @@ struct aarch64_opcode aarch64_opcode_tab
- FP16_V8_2_INSN ("fmlal2", 0x6e20cc00, 0xffa0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3FML4S, 0),
- FP16_V8_2_INSN ("fmlsl2", 0x6ea0cc00, 0xffa0fc00, asimdsame, OP3 (Vd, Vn, Vm), QL_V3FML4S, 0),
-
-- FP16_V8_2_INSN ("fmlal", 0xf800000, 0xffc0f400, asimdelem, OP3 (Vd, Vn, Em), QL_V2FML2S, 0),
-- FP16_V8_2_INSN ("fmlsl", 0xf804000, 0xffc0f400, asimdelem, OP3 (Vd, Vn, Em), QL_V2FML2S, 0),
-- FP16_V8_2_INSN ("fmlal2", 0x2f808000, 0xffc0f400, asimdelem, OP3 (Vd, Vn, Em), QL_V2FML2S, 0),
-- FP16_V8_2_INSN ("fmlsl2", 0x2f80c000, 0xffc0f400, asimdelem, OP3 (Vd, Vn, Em), QL_V2FML2S, 0),
--
-- FP16_V8_2_INSN ("fmlal", 0x4f800000, 0xffc0f400, asimdelem, OP3 (Vd, Vn, Em), QL_V2FML4S, 0),
-- FP16_V8_2_INSN ("fmlsl", 0x4f804000, 0xffc0f400, asimdelem, OP3 (Vd, Vn, Em), QL_V2FML4S, 0),
-- FP16_V8_2_INSN ("fmlal2", 0x6f808000, 0xffc0f400, asimdelem, OP3 (Vd, Vn, Em), QL_V2FML4S, 0),
-- FP16_V8_2_INSN ("fmlsl2", 0x6f80c000, 0xffc0f400, asimdelem, OP3 (Vd, Vn, Em), QL_V2FML4S, 0),
-+ FP16_V8_2_INSN ("fmlal", 0xf800000, 0xffc0f400, asimdelem, OP3 (Vd, Vn, Em16), QL_V2FML2S, 0),
-+ FP16_V8_2_INSN ("fmlsl", 0xf804000, 0xffc0f400, asimdelem, OP3 (Vd, Vn, Em16), QL_V2FML2S, 0),
-+ FP16_V8_2_INSN ("fmlal2", 0x2f808000, 0xffc0f400, asimdelem, OP3 (Vd, Vn, Em16), QL_V2FML2S, 0),
-+ FP16_V8_2_INSN ("fmlsl2", 0x2f80c000, 0xffc0f400, asimdelem, OP3 (Vd, Vn, Em16), QL_V2FML2S, 0),
-+
-+ FP16_V8_2_INSN ("fmlal", 0x4f800000, 0xffc0f400, asimdelem, OP3 (Vd, Vn, Em16), QL_V2FML4S, 0),
-+ FP16_V8_2_INSN ("fmlsl", 0x4f804000, 0xffc0f400, asimdelem, OP3 (Vd, Vn, Em16), QL_V2FML4S, 0),
-+ FP16_V8_2_INSN ("fmlal2", 0x6f808000, 0xffc0f400, asimdelem, OP3 (Vd, Vn, Em16), QL_V2FML4S, 0),
-+ FP16_V8_2_INSN ("fmlsl2", 0x6f80c000, 0xffc0f400, asimdelem, OP3 (Vd, Vn, Em16), QL_V2FML4S, 0),
- /* System extensions ARMv8.4-a. */
-- V8_4_INSN ("cfinv", 0xd500401f, 0xffffffff, ic_system, OP0 (), {}, 0),
-- V8_4_INSN ("rmif", 0xba000400, 0xffe07c10, ic_system, OP3 (Rn, IMM_2, MASK), QL_RMIF, 0),
-- V8_4_INSN ("setf8", 0x3a00080d, 0xfffffc1f, ic_system, OP1 (Rn), QL_SETF, 0),
-- V8_4_INSN ("setf16", 0x3a00480d, 0xfffffc1f, ic_system, OP1 (Rn), QL_SETF, 0),
-+ FLAGM_INSN ("rmif", 0xba000400, 0xffe07c10, ic_system, OP3 (Rn, IMM_2, MASK), QL_RMIF, 0),
-+ FLAGM_INSN ("setf8", 0x3a00080d, 0xfffffc1f, ic_system, OP1 (Rn), QL_SETF, 0),
-+ FLAGM_INSN ("setf16", 0x3a00480d, 0xfffffc1f, ic_system, OP1 (Rn), QL_SETF, 0),
- /* Memory access instructions ARMv8.4-a. */
- V8_4_INSN ("stlurb" , 0x19000000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLW, 0),
- V8_4_INSN ("ldapurb", 0x19400000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLW, 0),
-@@ -4351,7 +5099,61 @@ struct aarch64_opcode aarch64_opcode_tab
- V8_4_INSN ("ldapursw", 0x99800000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLX, 0),
- V8_4_INSN ("stlur", 0xd9000000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLX, 0),
- V8_4_INSN ("ldapur", 0xd9400000, 0xffe00c00, ldst_unscaled, OP2 (Rt, ADDR_OFFSET), QL_STLX, 0),
-- {0, 0, 0, 0, 0, 0, {}, {}, 0, 0, NULL},
-+
-+ /* Matrix Multiply instructions. */
-+ INT8MATMUL_SVE_INSNC ("smmla", 0x45009800, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SBB, 0, C_SCAN_MOVPRFX, 0),
-+ INT8MATMUL_SVE_INSNC ("ummla", 0x45c09800, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SBB, 0, C_SCAN_MOVPRFX, 0),
-+ INT8MATMUL_SVE_INSNC ("usmmla", 0x45809800, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SBB, 0, C_SCAN_MOVPRFX, 0),
-+ INT8MATMUL_SVE_INSNC ("usdot", 0x44807800, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SBB, 0, C_SCAN_MOVPRFX, 0),
-+ INT8MATMUL_SVE_INSNC ("usdot", 0x44a01800, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX), OP_SVE_SBB, 0, C_SCAN_MOVPRFX, 0),
-+ INT8MATMUL_SVE_INSNC ("sudot", 0x44a01c00, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX), OP_SVE_SBB, 0, C_SCAN_MOVPRFX, 0),
-+ F32MATMUL_SVE_INSNC ("fmmla", 0x64a0e400, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_S, 0, C_SCAN_MOVPRFX, 0),
-+ F64MATMUL_SVE_INSNC ("fmmla", 0x64e0e400, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_D, 0, C_SCAN_MOVPRFX, 0),
-+ F64MATMUL_SVE_INSN ("ld1rob", 0xa4200000, 0xffe0e000, sve_misc, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_BZU, F_OD(1), 0),
-+ F64MATMUL_SVE_INSN ("ld1roh", 0xa4a00000, 0xffe0e000, sve_misc, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL1), OP_SVE_HZU, F_OD(1), 0),
-+ F64MATMUL_SVE_INSN ("ld1row", 0xa5200000, 0xffe0e000, sve_misc, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL2), OP_SVE_SZU, F_OD(1), 0),
-+ F64MATMUL_SVE_INSN ("ld1rod", 0xa5a00000, 0xffe0e000, sve_misc, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL3), OP_SVE_DZU, F_OD(1), 0),
-+ F64MATMUL_SVE_INSN ("ld1rob", 0xa4202000, 0xfff0e000, sve_misc, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x32), OP_SVE_BZU, F_OD(1), 0),
-+ F64MATMUL_SVE_INSN ("ld1roh", 0xa4a02000, 0xfff0e000, sve_misc, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x32), OP_SVE_HZU, F_OD(1), 0),
-+ F64MATMUL_SVE_INSN ("ld1row", 0xa5202000, 0xfff0e000, sve_misc, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x32), OP_SVE_SZU, F_OD(1), 0),
-+ F64MATMUL_SVE_INSN ("ld1rod", 0xa5a02000, 0xfff0e000, sve_misc, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x32), OP_SVE_DZU, F_OD(1), 0),
-+ F64MATMUL_SVE_INSN ("zip1", 0x05a00000, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_QQQ, 0, 0),
-+ F64MATMUL_SVE_INSN ("zip2", 0x05a00400, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_QQQ, 0, 0),
-+ F64MATMUL_SVE_INSN ("uzp1", 0x05a00800, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_QQQ, 0, 0),
-+ F64MATMUL_SVE_INSN ("uzp2", 0x05a00c00, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_QQQ, 0, 0),
-+ F64MATMUL_SVE_INSN ("trn1", 0x05a01800, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_QQQ, 0, 0),
-+ F64MATMUL_SVE_INSN ("trn2", 0x05a01c00, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_QQQ, 0, 0),
-+ /* Matrix Multiply advanced SIMD instructions. */
-+ INT8MATMUL_INSN ("smmla", 0x4e80a400, 0xffe0fc00, aarch64_misc, OP3 (Vd, Vn, Vm), QL_MMLA64, 0),
-+ INT8MATMUL_INSN ("ummla", 0x6e80a400, 0xffe0fc00, aarch64_misc, OP3 (Vd, Vn, Vm), QL_MMLA64, 0),
-+ INT8MATMUL_INSN ("usmmla", 0x4e80ac00, 0xffe0fc00, aarch64_misc, OP3 (Vd, Vn, Vm), QL_MMLA64, 0),
-+ INT8MATMUL_INSN ("usdot", 0x0e809c00, 0xbfe0fc00, aarch64_misc, OP3 (Vd, Vn, Vm), QL_V3DOT, F_SIZEQ),
-+ INT8MATMUL_INSN ("usdot", 0x0f80f000, 0xbfc0f400, dotproduct, OP3 (Vd, Vn, Em), QL_V2DOT, F_SIZEQ),
-+ INT8MATMUL_INSN ("sudot", 0x0f00f000, 0xbfc0f400, dotproduct, OP3 (Vd, Vn, Em), QL_V2DOT, F_SIZEQ),
-+
-+ /* BFloat instructions. */
-+ BFLOAT16_SVE_INSNC ("bfdot", 0x64608000, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0),
-+ BFLOAT16_SVE_INSNC ("bfdot", 0x64604000, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0),
-+ BFLOAT16_SVE_INSNC ("bfmmla", 0x6460e400, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0),
-+ BFLOAT16_SVE_INSNC ("bfcvt", 0x658aa000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMS, 0, C_SCAN_MOVPRFX | C_MAX_ELEM, 0),
-+ BFLOAT16_SVE_INSNC ("bfcvtnt", 0x648aa000, 0xffffe000, sve_misc, OP3 (SVE_Zd, SVE_Pg3, SVE_Zn), OP_SVE_HMS, 0, 0, 0),
-+ BFLOAT16_SVE_INSNC ("bfmlalt", 0x64e08400, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0),
-+ BFLOAT16_SVE_INSNC ("bfmlalb", 0x64e08000, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0),
-+ BFLOAT16_SVE_INSNC ("bfmlalt", 0x64e04400, 0xffe0f400, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0),
-+ BFLOAT16_SVE_INSNC ("bfmlalb", 0x64e04000, 0xffe0f400, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_11_INDEX), OP_SVE_SHH, 0, C_SCAN_MOVPRFX, 0),
-+ /* BFloat Advanced SIMD instructions. */
-+ BFLOAT16_INSN ("bfdot", 0x2e40fc00, 0xbfe0fc00, bfloat16, OP3 (Vd, Vn, Vm), QL_BFDOT64, F_SIZEQ),
-+ /* Using dotproduct as iclass to treat instruction similar to udot. */
-+ BFLOAT16_INSN ("bfdot", 0x0f40f000, 0xbfc0f400, dotproduct, OP3 (Vd, Vn, Em), QL_BFDOT64I, F_SIZEQ),
-+ BFLOAT16_INSN ("bfmmla", 0x6e40ec00, 0xffe0fc00, bfloat16, OP3 (Vd, Vn, Vm), QL_BFMMLA, F_SIZEQ),
-+ BFLOAT16_INSN ("bfcvtn", 0x0ea16800, 0xfffffc00, bfloat16, OP2 (Vd, Vn), QL_BFCVTN64, 0),
-+ BFLOAT16_INSN ("bfcvtn2", 0x4ea16800, 0xfffffc00, bfloat16, OP2 (Vd, Vn), QL_BFCVTN2_64, 0),
-+ BFLOAT16_INSN ("bfcvt", 0x1e634000, 0xfffffc00, bfloat16, OP2 (Fd, Fn), QL_BFCVT64, 0),
-+ BFLOAT16_INSN ("bfmlalt", 0x6ec0fc00, 0xffe0fc00, bfloat16, OP3 (Vd, Vn, Vm), QL_BFMMLA, 0),
-+ BFLOAT16_INSN ("bfmlalb", 0x2ec0fc00, 0xffe0fc00, bfloat16, OP3 (Vd, Vn, Vm), QL_BFMMLA, 0),
-+ BFLOAT16_INSN ("bfmlalt", 0x4fc0f000, 0xffc0f400, bfloat16, OP3 (Vd, Vn, Em16), QL_V3BFML4S, 0),
-+ BFLOAT16_INSN ("bfmlalb", 0x0fc0f000, 0xffc0f400, bfloat16, OP3 (Vd, Vn, Em16), QL_V3BFML4S, 0),
-+ {0, 0, 0, 0, 0, 0, {}, {}, 0, 0, 0, NULL},
- };
-
- #ifdef AARCH64_OPERANDS
-@@ -4377,6 +5179,9 @@ struct aarch64_opcode aarch64_opcode_tab
- Y(INT_REG, regno, "Rm", 0, F(FLD_Rm), "an integer register") \
- Y(INT_REG, regno, "Rt", 0, F(FLD_Rt), "an integer register") \
- Y(INT_REG, regno, "Rt2", 0, F(FLD_Rt2), "an integer register") \
-+ Y(INT_REG, regno, "Rt_LS64", 0, F(FLD_Rt), "an integer register") \
-+ Y(INT_REG, regno, "Rt_SP", OPD_F_MAYBE_SP, F(FLD_Rt), \
-+ "an integer or stack pointer register") \
- Y(INT_REG, regno, "Rs", 0, F(FLD_Rs), "an integer register") \
- Y(INT_REG, regno, "Ra", 0, F(FLD_Ra), "an integer register") \
- X(INT_REG, ins_regno, ext_regrt_sysins, "Rt_SYS", 0, F(FLD_Rt), \
-@@ -4416,6 +5221,8 @@ struct aarch64_opcode aarch64_opcode_tab
- "a SIMD vector element") \
- Y(SIMD_ELEMENT, reglane, "Em", 0, F(FLD_Rm), \
- "a SIMD vector element") \
-+ Y(SIMD_ELEMENT, reglane, "Em16", 0, F(FLD_Rm), \
-+ "a SIMD vector element limited to V0-V15") \
- Y(SIMD_REGLIST, reglist, "LVn", 0, F(FLD_Rn), \
- "a SIMD vector register list") \
- Y(SIMD_REGLIST, ldst_reglist, "LVt", 0, F(), \
-@@ -4462,12 +5269,18 @@ struct aarch64_opcode aarch64_opcode_tab
- "a 3-bit unsigned immediate") \
- Y(IMMEDIATE, imm, "UIMM4", 0, F(FLD_CRm), \
- "a 4-bit unsigned immediate") \
-+ Y(IMMEDIATE, imm, "UIMM4_ADDG", 0, F(FLD_imm4_3), \
-+ "a 4-bit unsigned Logical Address Tag modifier") \
- Y(IMMEDIATE, imm, "UIMM7", 0, F(FLD_CRm, FLD_op2), \
- "a 7-bit unsigned immediate") \
-+ Y(IMMEDIATE, imm, "UIMM10", OPD_F_SHIFT_BY_4, F(FLD_immr), \
-+ "a 10-bit unsigned multiple of 16") \
- Y(IMMEDIATE, imm, "BIT_NUM", 0, F(FLD_b5, FLD_b40), \
- "the bit number to be tested") \
- Y(IMMEDIATE, imm, "EXCEPTION", 0, F(FLD_imm16), \
- "a 16-bit unsigned immediate") \
-+ Y(IMMEDIATE, imm, "UNDEFINED", 0, F(FLD_imm16_2), \
-+ "a 16-bit unsigned immediate") \
- Y(IMMEDIATE, imm, "CCMP_IMM", 0, F(FLD_imm5), \
- "a 5-bit unsigned immediate") \
- Y(IMMEDIATE, imm, "SIMM5", OPD_F_SEXT, F(FLD_imm5), \
-@@ -4513,9 +5326,13 @@ struct aarch64_opcode aarch64_opcode_tab
- Y(ADDRESS, addr_simm, "ADDR_SIMM9_2", 0, F(FLD_imm9,FLD_index), \
- "an address with 9-bit negative or unaligned immediate offset") \
- Y(ADDRESS, addr_simm10, "ADDR_SIMM10", 0, F(FLD_Rn,FLD_S_imm10,FLD_imm9,FLD_index),\
-- "an address with 10-bit scaled, signed immediate offset") \
-+ "an address with an optional 10-bit scaled, signed immediate offset") \
-+ Y(ADDRESS, addr_simm, "ADDR_SIMM11", 0, F(FLD_imm7,FLD_index2),\
-+ "an address with 11-bit signed immediate (multiple of 16) offset")\
- Y(ADDRESS, addr_uimm12, "ADDR_UIMM12", 0, F(FLD_Rn,FLD_imm12), \
- "an address with scaled, unsigned immediate offset") \
-+ Y(ADDRESS, addr_simm, "ADDR_SIMM13", 0, F(FLD_imm9,FLD_index),\
-+ "an address with 13-bit signed immediate (multiple of 16) offset")\
- Y(ADDRESS, addr_simple, "SIMD_ADDR_SIMPLE", 0, F(), \
- "an address with base register (no offset)") \
- Y(ADDRESS, addr_offset, "ADDR_OFFSET", 0, F(FLD_Rn,FLD_imm9,FLD_index),\
-@@ -4533,17 +5350,26 @@ struct aarch64_opcode aarch64_opcode_tab
- "an instruction cache maintenance operation specifier") \
- Y(SYSTEM, sysins_op, "SYSREG_TLBI", 0, F(), \
- "a TBL invalidation operation specifier") \
-+ Y(SYSTEM, sysins_op, "SYSREG_SR", 0, F(), \
-+ "a Speculation Restriction option name (RCTX)") \
- Y(SYSTEM, barrier, "BARRIER", 0, F(), \
- "a barrier option name") \
-+ Y(SYSTEM, barrier_dsb_nxs, "BARRIER_DSB_NXS", 0, F(), \
-+ "the DSB nXS option qualifier name SY, ISH, NSH, OSH or an optional 5-bit unsigned immediate") \
- Y(SYSTEM, barrier, "BARRIER_ISB", 0, F(), \
- "the ISB option name SY or an optional 4-bit unsigned immediate") \
- Y(SYSTEM, prfop, "PRFOP", 0, F(), \
- "a prefetch operation specifier") \
-- Y(SYSTEM, hint, "BARRIER_PSB", 0, F (), \
-- "the PSB option name CSYNC") \
-+ Y(SYSTEM, none, "BARRIER_PSB", 0, F (), \
-+ "the PSB/TSB option name CSYNC") \
-+ Y(SYSTEM, hint, "BTI", 0, F (), \
-+ "BTI targets j/c/jc") \
- Y(ADDRESS, sve_addr_ri_s4, "SVE_ADDR_RI_S4x16", \
- 4 << OPD_F_OD_LSB, F(FLD_Rn), \
- "an address with a 4-bit signed offset, multiplied by 16") \
-+ Y(ADDRESS, sve_addr_ri_s4, "SVE_ADDR_RI_S4x32", \
-+ 5 << OPD_F_OD_LSB, F(FLD_Rn), \
-+ "an address with a 4-bit signed offset, multiplied by 32") \
- Y(ADDRESS, sve_addr_ri_s4xvl, "SVE_ADDR_RI_S4xVL", \
- 0 << OPD_F_OD_LSB, F(FLD_Rn), \
- "an address with a 4-bit signed offset, multiplied by VL") \
-@@ -4573,6 +5399,8 @@ struct aarch64_opcode aarch64_opcode_tab
- Y(ADDRESS, sve_addr_ri_u6, "SVE_ADDR_RI_U6x8", 3 << OPD_F_OD_LSB, \
- F(FLD_Rn), \
- "an address with a 6-bit unsigned offset, multiplied by 8") \
-+ Y(ADDRESS, sve_addr_rr_lsl, "SVE_ADDR_R", 0 << OPD_F_OD_LSB, \
-+ F(FLD_Rn,FLD_Rm), "an address with an optional scalar register offset") \
- Y(ADDRESS, sve_addr_rr_lsl, "SVE_ADDR_RR", 0 << OPD_F_OD_LSB, \
- F(FLD_Rn,FLD_Rm), "an address with a scalar register offset") \
- Y(ADDRESS, sve_addr_rr_lsl, "SVE_ADDR_RR_LSL1", 1 << OPD_F_OD_LSB, \
-@@ -4593,6 +5421,9 @@ struct aarch64_opcode aarch64_opcode_tab
- Y(ADDRESS, sve_addr_rr_lsl, "SVE_ADDR_RX_LSL3", \
- (3 << OPD_F_OD_LSB) | OPD_F_NO_ZR, F(FLD_Rn,FLD_Rm), \
- "an address with a scalar register offset") \
-+ Y(ADDRESS, sve_addr_rr_lsl, "SVE_ADDR_ZX", \
-+ 0 << OPD_F_OD_LSB , F(FLD_SVE_Zn,FLD_Rm), \
-+ "vector of address with a scalar register offset") \
- Y(ADDRESS, sve_addr_rr_lsl, "SVE_ADDR_RZ", 0 << OPD_F_OD_LSB, \
- F(FLD_Rn,FLD_SVE_Zm_16), \
- "an address with a vector register offset") \
-@@ -4665,6 +5496,8 @@ struct aarch64_opcode aarch64_opcode_tab
- "a 1-bit rotation specifier for complex arithmetic operations") \
- Y(IMMEDIATE, imm_rotate2, "SVE_IMM_ROT2", 0, F(FLD_SVE_rot2), \
- "a 2-bit rotation specifier for complex arithmetic operations") \
-+ Y(IMMEDIATE, imm_rotate1, "SVE_IMM_ROT3", 0, F(FLD_SVE_rot3), \
-+ "a 1-bit rotation specifier for complex arithmetic operations") \
- Y(IMMEDIATE, inv_limm, "SVE_INV_LIMM", 0, \
- F(FLD_SVE_N,FLD_SVE_immr,FLD_SVE_imms), \
- "an inverted 13-bit logical immediate") \
-@@ -4704,10 +5537,16 @@ struct aarch64_opcode aarch64_opcode_tab
- F(FLD_SVE_tszh,FLD_SVE_imm5), "a shift-left immediate operand") \
- Y(IMMEDIATE, sve_shlimm, "SVE_SHLIMM_UNPRED", 0, \
- F(FLD_SVE_tszh,FLD_imm5), "a shift-left immediate operand") \
-- Y(IMMEDIATE, sve_shrimm, "SVE_SHRIMM_PRED", 0, \
-+ Y(IMMEDIATE, sve_shlimm, "SVE_SHLIMM_UNPRED_22", 0, \
-+ F(FLD_SVE_sz, FLD_SVE_tszl_19, FLD_SVE_imm3), \
-+ "a shift-left immediate operand") \
-+ Y(IMMEDIATE, sve_shrimm, "SVE_SHRIMM_PRED", 1 << OPD_F_OD_LSB, \
- F(FLD_SVE_tszh,FLD_SVE_imm5), "a shift-right immediate operand") \
-- Y(IMMEDIATE, sve_shrimm, "SVE_SHRIMM_UNPRED", 0, \
-+ Y(IMMEDIATE, sve_shrimm, "SVE_SHRIMM_UNPRED", 1 << OPD_F_OD_LSB, \
- F(FLD_SVE_tszh,FLD_imm5), "a shift-right immediate operand") \
-+ Y(IMMEDIATE, sve_shrimm, "SVE_SHRIMM_UNPRED_22", 2 << OPD_F_OD_LSB, \
-+ F(FLD_SVE_sz, FLD_SVE_tszl_19, FLD_SVE_imm3), \
-+ "a shift-right immediate operand") \
- Y(IMMEDIATE, imm, "SVE_SIMM5", OPD_F_SEXT, F(FLD_SVE_imm5), \
- "a 5-bit signed immediate") \
- Y(IMMEDIATE, imm, "SVE_SIMM5B", OPD_F_SEXT, F(FLD_SVE_imm5b), \
-@@ -4744,6 +5583,12 @@ struct aarch64_opcode aarch64_opcode_tab
- Y(SVE_REG, sve_quad_index, "SVE_Zm3_22_INDEX", \
- 3 << OPD_F_OD_LSB, F(FLD_SVE_i3h, FLD_SVE_Zm_16), \
- "an indexed SVE vector register") \
-+ Y(SVE_REG, sve_quad_index, "SVE_Zm3_11_INDEX", \
-+ 3 << OPD_F_OD_LSB, F(FLD_SVE_i3h2, FLD_SVE_i3l, FLD_SVE_imm3), \
-+ "an indexed SVE vector register") \
-+ Y(SVE_REG, sve_quad_index, "SVE_Zm4_11_INDEX", \
-+ 4 << OPD_F_OD_LSB, F(FLD_SVE_i2h, FLD_SVE_i3l, FLD_SVE_imm4), \
-+ "an indexed SVE vector register") \
- Y(SVE_REG, sve_quad_index, "SVE_Zm4_INDEX", \
- 4 << OPD_F_OD_LSB, F(FLD_SVE_Zm_16), \
- "an indexed SVE vector register") \
-@@ -4757,5 +5602,7 @@ struct aarch64_opcode aarch64_opcode_tab
- "an SVE vector register") \
- Y(SVE_REG, sve_reglist, "SVE_ZtxN", 0, F(FLD_SVE_Zt), \
- "a list of SVE vector registers") \
-+ Y(IMMEDIATE, imm, "TME_UIMM16", 0, F(FLD_imm16), \
-+ "a 16-bit unsigned immediate for TME tcancel") \
- Y(SIMD_ELEMENT, reglane, "SM3_IMM2", 0, F(FLD_SM3_imm2), \
- "an indexed SM3 vector immediate")
---- /dev/null 2021-03-23 09:32:24.062139171 +0000
-+++ binutils-2.30.new/bfd/cpu-aarch64.h 2021-03-23 16:20:02.835710583 +0000
-@@ -0,0 +1,25 @@
-+/* ELF AArch64 mapping symbol support
-+ Copyright (C) 2019-2021 Free Software Foundation, Inc.
-+
-+ This file is part of BFD, the Binary File Descriptor library.
-+
-+ This program is free software; you can redistribute it and/or modify
-+ it under the terms of the GNU General Public License as published by
-+ the Free Software Foundation; either version 3 of the License, or
-+ (at your option) any later version.
-+
-+ This program is distributed in the hope that it will be useful,
-+ but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ GNU General Public License for more details.
-+
-+ You should have received a copy of the GNU General Public License
-+ along with this program; see the file COPYING3. If not,
-+ see <http://www.gnu.org/licenses/>. */
-+
-+#define BFD_AARCH64_SPECIAL_SYM_TYPE_MAP (1 << 0)
-+#define BFD_AARCH64_SPECIAL_SYM_TYPE_TAG (1 << 1)
-+#define BFD_AARCH64_SPECIAL_SYM_TYPE_OTHER (1 << 2)
-+#define BFD_AARCH64_SPECIAL_SYM_TYPE_ANY (~0)
-+extern bfd_boolean bfd_is_aarch64_special_symbol_name
-+ (const char * name, int type);
---- /dev/null 2021-03-23 09:32:24.062139171 +0000
-+++ binutils-2.30.new/gas/testsuite/gas/aarch64/armv8-ras-1_1-invalid.d 2021-03-23 16:19:56.776751772 +0000
-@@ -0,0 +1,3 @@
-+#name: Invalid RAS 1.1 System registers usage
-+#source: armv8-ras-1_1-invalid.s
-+#error-output: armv8-ras-1_1-invalid.l
---- /dev/null 2021-03-23 09:32:24.062139171 +0000
-+++ binutils-2.30.new/gas/testsuite/gas/aarch64/armv8-ras-1_1-invalid.l 2021-03-23 16:19:56.776751772 +0000
-@@ -0,0 +1,2 @@
-+.*: Assembler messages:
-+.*: Warning: specified register cannot be written to at operand 1 -- `msr erxpfgf_el1,x0'
---- /dev/null 2021-03-23 09:32:24.062139171 +0000
-+++ binutils-2.30.new/gas/testsuite/gas/aarch64/armv8-ras-1_1-invalid.s 2021-03-23 16:19:56.776751772 +0000
-@@ -0,0 +1,2 @@
-+/* Write to R/O RAS 1.1 system register. */
-+msr erxpfgf_el1, x0
---- /dev/null 2021-03-23 09:32:24.062139171 +0000
-+++ binutils-2.30.new/gas/testsuite/gas/aarch64/armv8-ras-1_1.d 2021-03-23 16:19:56.776751772 +0000
-@@ -0,0 +1,26 @@
-+#name: RAS 1.1 System registers
-+#objdump: -dr
-+
-+.*: file format .*
-+
-+Disassembly of section \.text:
-+
-+0+ <.*>:
-+.*: d5385540 mrs x0, erxmisc2_el1
-+.*: d5385560 mrs x0, erxmisc3_el1
-+.*: d53854c0 mrs x0, erxpfgcdn_el1
-+.*: d53854a0 mrs x0, erxpfgctl_el1
-+.*: d5185540 msr erxmisc2_el1, x0
-+.*: d5185560 msr erxmisc3_el1, x0
-+.*: d51854c0 msr erxpfgcdn_el1, x0
-+.*: d51854a0 msr erxpfgctl_el1, x0
-+.*: d5385480 mrs x0, erxpfgf_el1
-+.*: d5385540 mrs x0, erxmisc2_el1
-+.*: d5385560 mrs x0, erxmisc3_el1
-+.*: d53854c0 mrs x0, erxpfgcdn_el1
-+.*: d53854a0 mrs x0, erxpfgctl_el1
-+.*: d5185540 msr erxmisc2_el1, x0
-+.*: d5185560 msr erxmisc3_el1, x0
-+.*: d51854c0 msr erxpfgcdn_el1, x0
-+.*: d51854a0 msr erxpfgctl_el1, x0
-+.*: d5385480 mrs x0, erxpfgf_el1
---- /dev/null 2021-03-23 09:32:24.062139171 +0000
-+++ binutils-2.30.new/gas/testsuite/gas/aarch64/armv8-ras-1_1.s 2021-03-23 16:19:56.776751772 +0000
-@@ -0,0 +1,39 @@
-+/* Armv8-A RAS 1.1 extension system registers.
-+
-+Please note that early Armv8-a architectures do not officially support RAS
-+extension.
-+
-+Certain use cases require developers to enable only more generic architecture
-+(e.g. -march=armv8-a) during system development. Users must use RAS extension
-+registers bearing in mind that system they use must support it. */
-+
-+/* Arm8-A. */
-+.arch armv8-a
-+
-+ /* RAS 1.1 Read/Write registers. */
-+ mrs x0, erxmisc2_el1
-+ mrs x0, erxmisc3_el1
-+ mrs x0, erxpfgcdn_el1
-+ mrs x0, erxpfgctl_el1
-+ msr erxmisc2_el1, x0
-+ msr erxmisc3_el1, x0
-+ msr erxpfgcdn_el1, x0
-+ msr erxpfgctl_el1, x0
-+
-+ /* RAS 1.1 Read-only registers. */
-+ mrs x0, erxpfgf_el1
-+
-+/* Armv8-A + RAS. */
-+.arch armv8-a+ras
-+ /* RAS 1.1 Read/Write registers. */
-+ mrs x0, erxmisc2_el1
-+ mrs x0, erxmisc3_el1
-+ mrs x0, erxpfgcdn_el1
-+ mrs x0, erxpfgctl_el1
-+ msr erxmisc2_el1, x0
-+ msr erxmisc3_el1, x0
-+ msr erxpfgcdn_el1, x0
-+ msr erxpfgctl_el1, x0
-+
-+ /* RAS 1.1 Read-only registers. */
-+ mrs x0, erxpfgf_el1
---- /dev/null 2021-03-23 09:32:24.062139171 +0000
-+++ binutils-2.30.new/gas/testsuite/gas/aarch64/armv8_5-a-dp.d 2021-03-23 16:19:56.776751772 +0000
-@@ -0,0 +1,31 @@
-+#as: -march=armv8.5-a
-+# objdump: -d
-+
-+.*: .*
-+
-+
-+Disassembly of section \.text:
-+
-+0+0 <func>:
-+.*: d500403f xaflag
-+.*: d500405f axflag
-+.*: 1e284041 frint32z s1, s2
-+.*: 1e684062 frint32z d2, d3
-+.*: 1e28c041 frint32x s1, s2
-+.*: 1e68c062 frint32x d2, d3
-+.*: 1e294041 frint64z s1, s2
-+.*: 1e694062 frint64z d2, d3
-+.*: 1e29c041 frint64x s1, s2
-+.*: 1e69c062 frint64x d2, d3
-+.*: 4e61e820 frint32z v0.2d, v1.2d
-+.*: 0e21e820 frint32z v0.2s, v1.2s
-+.*: 4e21e820 frint32z v0.4s, v1.4s
-+.*: 6e61e820 frint32x v0.2d, v1.2d
-+.*: 2e21e820 frint32x v0.2s, v1.2s
-+.*: 6e21e820 frint32x v0.4s, v1.4s
-+.*: 4e61f820 frint64z v0.2d, v1.2d
-+.*: 0e21f820 frint64z v0.2s, v1.2s
-+.*: 4e21f820 frint64z v0.4s, v1.4s
-+.*: 6e61f820 frint64x v0.2d, v1.2d
-+.*: 2e21f820 frint64x v0.2s, v1.2s
-+.*: 6e21f820 frint64x v0.4s, v1.4s
---- /dev/null 2021-03-23 09:32:24.062139171 +0000
-+++ binutils-2.30.new/gas/testsuite/gas/aarch64/armv8_5-a-dp.s 2021-03-23 16:19:56.776751772 +0000
-@@ -0,0 +1,19 @@
-+ .macro expand, op, vec
-+ .irp sz, 32, 64
-+ .irp rnd, z, x
-+ .ifc \vec, 0
-+ \op\sz\rnd s1, s2
-+ \op\sz\rnd d2, d3
-+ .else
-+ \op\sz\rnd v0.2d, v1.2d
-+ \op\sz\rnd v0.2s, v1.2s
-+ \op\sz\rnd v0.4s, v1.4s
-+ .endif
-+ .endr
-+ .endr
-+ .endm
-+func:
-+ xaflag
-+ axflag
-+ expand frint,0
-+ expand frint,1
---- /dev/null 2021-03-23 09:32:24.062139171 +0000
-+++ binutils-2.30.new/gas/testsuite/gas/aarch64/armv8_5-a-memtag.d 2021-03-23 16:19:56.776751772 +0000
-@@ -0,0 +1,157 @@
-+#as: -march=armv8.5-a+memtag
-+# objdump: -d
-+
-+.*: .*
-+
-+
-+Disassembly of section \.text:
-+
-+0+0 <func>:
-+.*: 9ac01000 irg x0, x0, x0
-+.*: 9ac0101b irg x27, x0, x0
-+.*: 9ac01360 irg x0, x27, x0
-+.*: 9adb1000 irg x0, x0, x27
-+.*: 9adb137b irg x27, x27, x27
-+.*: 9adf101f irg sp, x0
-+.*: 9adf13e0 irg x0, sp
-+.*: 9ac01400 gmi x0, x0, x0
-+.*: 9ac0141b gmi x27, x0, x0
-+.*: 9ac01760 gmi x0, x27, x0
-+.*: 9adb1400 gmi x0, x0, x27
-+.*: 9adb177b gmi x27, x27, x27
-+.*: 9ac017e0 gmi x0, sp, x0
-+.*: 9ac0141f gmi xzr, x0, x0
-+.*: 91800000 addg x0, x0, #0x0, #0x0
-+.*: 9180001b addg x27, x0, #0x0, #0x0
-+.*: 91800360 addg x0, x27, #0x0, #0x0
-+.*: 9180037b addg x27, x27, #0x0, #0x0
-+.*: 91bf3fe0 addg x0, sp, #0x3f0, #0xf
-+.*: 91aa3c1f addg sp, x0, #0x2a0, #0xf
-+.*: d1800000 subg x0, x0, #0x0, #0x0
-+.*: d180001b subg x27, x0, #0x0, #0x0
-+.*: d1800360 subg x0, x27, #0x0, #0x0
-+.*: d180037b subg x27, x27, #0x0, #0x0
-+.*: d1bf3fe0 subg x0, sp, #0x3f0, #0xf
-+.*: d1bf141f subg sp, x0, #0x3f0, #0x5
-+.*: 9ac00000 subp x0, x0, x0
-+.*: 9ac0001b subp x27, x0, x0
-+.*: 9ac00360 subp x0, x27, x0
-+.*: 9adb0000 subp x0, x0, x27
-+.*: 9adb037b subp x27, x27, x27
-+.*: 9ac003e0 subp x0, sp, x0
-+.*: 9adf0000 subp x0, x0, sp
-+.*: 9ac0001f subp xzr, x0, x0
-+.*: bac00000 subps x0, x0, x0
-+.*: bac0001b subps x27, x0, x0
-+.*: bac00360 subps x0, x27, x0
-+.*: badb0000 subps x0, x0, x27
-+.*: badb037b subps x27, x27, x27
-+.*: bac003e0 subps x0, sp, x0
-+.*: badf0000 subps x0, x0, sp
-+.*: bac0001f cmpp x0, x0
-+.*: bac0001f cmpp x0, x0
-+.*: bac0037f cmpp x27, x0
-+.*: badb001f cmpp x0, x27
-+.*: badb037f cmpp x27, x27
-+.*: bac003ff cmpp sp, x0
-+.*: badf001f cmpp x0, sp
-+.*: d9200800 stg x0, \[x0\]
-+.*: d9200b60 stg x0, \[x27\]
-+.*: d920081f stg sp, \[x0\]
-+.*: d93fb81b stg x27, \[x0, #-80\]
-+.*: d9200c00 stg x0, \[x0, #0\]!
-+.*: d9200c1f stg sp, \[x0, #0\]!
-+.*: d920ac1b stg x27, \[x0, #160\]!
-+.*: d9200400 stg x0, \[x0\], #0
-+.*: d920041f stg sp, \[x0\], #0
-+.*: d93a641b stg x27, \[x0\], #-1440
-+.*: d92ffbe0 stg x0, \[sp, #4080\]
-+.*: d92ffbff stg sp, \[sp, #4080\]
-+.*: d9300bfb stg x27, \[sp, #-4096\]
-+.*: d92fffe0 stg x0, \[sp, #4080\]!
-+.*: d93007ff stg sp, \[sp\], #-4096
-+.*: d9600800 stzg x0, \[x0\]
-+.*: d9600b60 stzg x0, \[x27\]
-+.*: d960081f stzg sp, \[x0\]
-+.*: d97fb81b stzg x27, \[x0, #-80\]
-+.*: d9600c00 stzg x0, \[x0, #0\]!
-+.*: d9600c1f stzg sp, \[x0, #0\]!
-+.*: d960ac1b stzg x27, \[x0, #160\]!
-+.*: d9600400 stzg x0, \[x0\], #0
-+.*: d960041f stzg sp, \[x0\], #0
-+.*: d97a641b stzg x27, \[x0\], #-1440
-+.*: d96ffbe0 stzg x0, \[sp, #4080\]
-+.*: d96ffbff stzg sp, \[sp, #4080\]
-+.*: d9700bfb stzg x27, \[sp, #-4096\]
-+.*: d96fffe0 stzg x0, \[sp, #4080\]!
-+.*: d97007ff stzg sp, \[sp\], #-4096
-+.*: d9a00800 st2g x0, \[x0\]
-+.*: d9a00b60 st2g x0, \[x27\]
-+.*: d9a0081f st2g sp, \[x0\]
-+.*: d9bfb81b st2g x27, \[x0, #-80\]
-+.*: d9a00c00 st2g x0, \[x0, #0\]!
-+.*: d9a00c1f st2g sp, \[x0, #0\]!
-+.*: d9a0ac1b st2g x27, \[x0, #160\]!
-+.*: d9a00400 st2g x0, \[x0\], #0
-+.*: d9a0041f st2g sp, \[x0\], #0
-+.*: d9ba641b st2g x27, \[x0\], #-1440
-+.*: d9affbe0 st2g x0, \[sp, #4080\]
-+.*: d9affbff st2g sp, \[sp, #4080\]
-+.*: d9b00bfb st2g x27, \[sp, #-4096\]
-+.*: d9afffe0 st2g x0, \[sp, #4080\]!
-+.*: d9b007ff st2g sp, \[sp\], #-4096
-+.*: d9e00800 stz2g x0, \[x0\]
-+.*: d9e00b60 stz2g x0, \[x27\]
-+.*: d9e0081f stz2g sp, \[x0\]
-+.*: d9ffb81b stz2g x27, \[x0, #-80\]
-+.*: d9e00c00 stz2g x0, \[x0, #0\]!
-+.*: d9e00c1f stz2g sp, \[x0, #0\]!
-+.*: d9e0ac1b stz2g x27, \[x0, #160\]!
-+.*: d9e00400 stz2g x0, \[x0\], #0
-+.*: d9e0041f stz2g sp, \[x0\], #0
-+.*: d9fa641b stz2g x27, \[x0\], #-1440
-+.*: d9effbe0 stz2g x0, \[sp, #4080\]
-+.*: d9effbff stz2g sp, \[sp, #4080\]
-+.*: d9f00bfb stz2g x27, \[sp, #-4096\]
-+.*: d9efffe0 stz2g x0, \[sp, #4080\]!
-+.*: d9f007ff stz2g sp, \[sp\], #-4096
-+.*: 69000000 stgp x0, x0, \[x0\]
-+.*: 69006c00 stgp x0, x27, \[x0\]
-+.*: 6900001b stgp x27, x0, \[x0\]
-+.*: 69006c1b stgp x27, x27, \[x0\]
-+.*: 69000360 stgp x0, x0, \[x27\]
-+.*: 693d8000 stgp x0, x0, \[x0, #-80\]
-+.*: 69800000 stgp x0, x0, \[x0, #0\]!
-+.*: 69850000 stgp x0, x0, \[x0, #160\]!
-+.*: 68800000 stgp x0, x0, \[x0\], #0
-+.*: 68bb8000 stgp x0, x0, \[x0\], #-144
-+.*: 691f801f stgp xzr, x0, \[x0, #1008\]
-+.*: 69207c00 stgp x0, xzr, \[x0, #-1024\]
-+.*: 699f83e0 stgp x0, x0, \[sp, #1008\]!
-+.*: 68a003e0 stgp x0, x0, \[sp\], #-1024
-+.*: d9600000 ldg x0, \[x0\]
-+.*: d960001b ldg x27, \[x0\]
-+.*: d9600360 ldg x0, \[x27\]
-+.*: d960037b ldg x27, \[x27\]
-+.*: d96003e0 ldg x0, \[sp\]
-+.*: d960001f ldg xzr, \[x0\]
-+.*: d96ff000 ldg x0, \[x0, #4080\]
-+.*: d9700000 ldg x0, \[x0, #-4096\]
-+.*: d9200000 stzgm x0, \[x0\]
-+.*: d920001b stzgm x27, \[x0\]
-+.*: d9200360 stzgm x0, \[x27\]
-+.*: d9200379 stzgm x25, \[x27\]
-+.*: d92003e0 stzgm x0, \[sp\]
-+.*: d920001f stzgm xzr, \[x0\]
-+.*: d9e00000 ldgm x0, \[x0\]
-+.*: d9e0001b ldgm x27, \[x0\]
-+.*: d9e00360 ldgm x0, \[x27\]
-+.*: d9e00379 ldgm x25, \[x27\]
-+.*: d9e003e0 ldgm x0, \[sp\]
-+.*: d9e0001f ldgm xzr, \[x0\]
-+.*: d9a00000 stgm x0, \[x0\]
-+.*: d9a0001b stgm x27, \[x0\]
-+.*: d9a00360 stgm x0, \[x27\]
-+.*: d9a00379 stgm x25, \[x27\]
-+.*: d9a003e0 stgm x0, \[sp\]
-+.*: d9a0001f stgm xzr, \[x0\]
---- /dev/null 2021-03-23 09:32:24.062139171 +0000
-+++ binutils-2.30.new/gas/testsuite/gas/aarch64/armv8_5-a-memtag.s 2021-03-23 16:19:56.776751772 +0000
-@@ -0,0 +1,117 @@
-+func:
-+ # OP x[0,30], x[0,30], x[0,30]
-+ .macro expand_3_reg op
-+ \op x0, x0, x0
-+ \op x27, x0, x0
-+ \op x0, x27, x0
-+ \op x0, x0, x27
-+ \op x27, x27, x27
-+ .endm
-+
-+ # OP x[0,30], x[0,30], #[0,30], #[0,14]
-+ .macro expand_2_reg op
-+ \op x0, x0, #0, #0
-+ \op x27, x0, #0, #0
-+ \op x0, x27, #0, #0
-+ \op x27, x27, #0, #0
-+ .endm
-+
-+ .macro expand_stg op
-+ \op x0, [x0, #0]
-+ \op x0, [x27, #0]
-+ \op sp, [x0, #0]
-+ \op x27, [x0, #-80]
-+ \op x0, [x0, #0]!
-+ \op sp, [x0, #0]!
-+ \op x27, [x0, #160]!
-+ \op x0, [x0], #0
-+ \op sp, [x0], #0
-+ \op x27, [x0], #-1440
-+ \op x0, [sp, #4080]
-+ \op sp, [sp, #4080]
-+ \op x27, [sp, #-4096]
-+ \op x0, [sp, #4080]!
-+ \op sp, [sp], #-4096
-+ .endm
-+
-+ .macro expand_ldg_bulk op
-+ \op x0, [x0]
-+ \op x27, [x0]
-+ \op x0, [x27]
-+ \op x25, [x27]
-+ \op x0, [sp]
-+ \op xzr, [x0]
-+ .endm
-+
-+ # IRG
-+ expand_3_reg irg
-+ irg sp, x0
-+ irg x0, sp
-+
-+ # GMI
-+ expand_3_reg gmi
-+ gmi x0, sp, x0
-+ gmi xzr, x0, x0
-+
-+ # ADDG
-+ expand_2_reg addg
-+ addg x0, sp, #0x3f0, #0xf
-+ addg sp, x0, #0x2a0, #0xf
-+
-+ # SUBG
-+ expand_2_reg subg
-+ subg x0, sp, #0x3f0, #0xf
-+ subg sp, x0, #0x3f0, #0x5
-+
-+ # SUBP
-+ expand_3_reg subp
-+ subp x0, sp, x0
-+ subp x0, x0, sp
-+ subp xzr, x0, x0
-+
-+ # SUBPS
-+ expand_3_reg subps
-+ subps x0, sp, x0
-+ subps x0, x0, sp
-+ subps xzr, x0, x0
-+
-+ # CMPP
-+ cmpp x0, x0
-+ cmpp x27, x0
-+ cmpp x0, x27
-+ cmpp x27, x27
-+ cmpp sp, x0
-+ cmpp x0, sp
-+
-+ expand_stg stg
-+ expand_stg stzg
-+ expand_stg st2g
-+ expand_stg stz2g
-+
-+ stgp x0, x0, [x0, #0]
-+ stgp x0, x27, [x0, #0]
-+ stgp x27, x0, [x0, #0]
-+ stgp x27, x27, [x0, #0]
-+ stgp x0, x0, [x27, #0]
-+ stgp x0, x0, [x0, #-80]
-+ stgp x0, x0, [x0, #0]!
-+ stgp x0, x0, [x0, #160]!
-+ stgp x0, x0, [x0], #0
-+ stgp x0, x0, [x0], #-144
-+ stgp xzr, x0, [x0, #1008]
-+ stgp x0, xzr, [x0, #-1024]
-+ stgp x0, x0, [sp, #1008]!
-+ stgp x0, x0, [sp], #-1024
-+
-+ ldg x0, [x0, #0]
-+ ldg x27, [x0, #0]
-+ ldg x0, [x27, #0]
-+ ldg x27, [x27, #0]
-+ ldg x0, [sp, #0]
-+ ldg xzr, [x0, #0]
-+ ldg x0, [x0, #4080]
-+ ldg x0, [x0, #-4096]
-+
-+ expand_ldg_bulk stzgm
-+ expand_ldg_bulk ldgm
-+ expand_ldg_bulk stgm
---- /dev/null 2021-03-23 09:32:24.062139171 +0000
-+++ binutils-2.30.new/gas/testsuite/gas/aarch64/bfloat16-directive-be.d 2021-03-23 16:19:56.776751772 +0000
-@@ -0,0 +1,11 @@
-+# name: Big endian bfloat16 literal directives
-+# source: bfloat16-directive.s
-+# as: -mbig-endian
-+# objdump: -s --section=.data
-+
-+.*: +file format .*
-+
-+Contents of section \.data:
-+ 0000 41403dfc 000042f7 8000c2f7 7fff7f80 .*
-+ 0010 ff807f7f ff7f0080 80800001 8001007f .*
-+ 0020 807f3f80 bf804000 c000 .*
---- /dev/null 2021-03-23 09:32:24.062139171 +0000
-+++ binutils-2.30.new/gas/testsuite/gas/aarch64/bfloat16-directive-le.d 2021-03-23 16:19:56.776751772 +0000
-@@ -0,0 +1,11 @@
-+# name: Little endian bfloat16 literal directives
-+# source: bfloat16-directive.s
-+# as: -mlittle-endian
-+# objdump: -s --section=.data
-+
-+.*: +file format .*
-+
-+Contents of section \.data:
-+ 0000 4041fc3d 0000f742 0080f7c2 ff7f807f .*
-+ 0010 80ff7f7f 7fff8000 80800100 01807f00 .*
-+ 0020 7f80803f 80bf0040 00c0 .*
---- /dev/null 2021-03-23 09:32:24.062139171 +0000
-+++ binutils-2.30.new/gas/testsuite/gas/aarch64/bfloat16-directive.s 2021-03-23 16:19:56.776751772 +0000
-@@ -0,0 +1,19 @@
-+.data
-+ .bfloat16 12.0
-+ .bfloat16 0.123
-+ .bfloat16 +0.0
-+ .bfloat16 123.4
-+ .bfloat16 -0.0
-+ .bfloat16 -123.4
-+ .bfloat16 NaN
-+ .bfloat16 Inf
-+ .bfloat16 -Inf
-+ .bfloat16 3.390e+38
-+ .bfloat16 -3.390e+38
-+ .bfloat16 1.175e-38
-+ .bfloat16 -1.175e-38
-+ .bfloat16 9.194e-41
-+ .bfloat16 -9.194e-41
-+ .bfloat16 1.167e-38
-+ .bfloat16 -1.167e-38
-+ .bfloat16 1.0, -1, 2.0, -2
---- /dev/null 2021-03-23 09:32:24.062139171 +0000
-+++ binutils-2.30.new/gas/testsuite/gas/aarch64/bfloat16.d 2021-03-23 16:19:56.777751765 +0000
-@@ -0,0 +1,56 @@
-+#as: -march=armv8.6-a+bf16+sve
-+#objdump: -dr
-+
-+.*: file format .*
-+
-+
-+Disassembly of section \.text:
-+
-+0+ <\.text>:
-+ *[0-9a-f]+: 647b82b1 bfdot z17\.s, z21\.h, z27\.h
-+ *[0-9a-f]+: 64608000 bfdot z0\.s, z0\.h, z0\.h
-+ *[0-9a-f]+: 647d42b1 bfdot z17\.s, z21\.h, z5\.h\[3\]
-+ *[0-9a-f]+: 64784000 bfdot z0\.s, z0\.h, z0\.h\[3\]
-+ *[0-9a-f]+: 64604000 bfdot z0\.s, z0\.h, z0\.h\[0\]
-+ *[0-9a-f]+: 647be6b1 bfmmla z17\.s, z21\.h, z27\.h
-+ *[0-9a-f]+: 6460e400 bfmmla z0\.s, z0\.h, z0\.h
-+ *[0-9a-f]+: 658ab6b1 bfcvt z17\.h, p5/m, z21\.s
-+ *[0-9a-f]+: 658aa000 bfcvt z0\.h, p0/m, z0\.s
-+ *[0-9a-f]+: 648ab6b1 bfcvtnt z17\.h, p5/m, z21\.s
-+ *[0-9a-f]+: 648aa000 bfcvtnt z0\.h, p0/m, z0\.s
-+ *[0-9a-f]+: 64fb86b1 bfmlalt z17\.s, z21\.h, z27\.h
-+ *[0-9a-f]+: 64e08400 bfmlalt z0\.s, z0\.h, z0\.h
-+ *[0-9a-f]+: 64fb82b1 bfmlalb z17\.s, z21\.h, z27\.h
-+ *[0-9a-f]+: 64e08000 bfmlalb z0\.s, z0\.h, z0\.h
-+ *[0-9a-f]+: 64e546b1 bfmlalt z17\.s, z21\.h, z5\.h\[0\]
-+ *[0-9a-f]+: 64f84c00 bfmlalt z0\.s, z0\.h, z0\.h\[7\]
-+ *[0-9a-f]+: 64e542b1 bfmlalb z17\.s, z21\.h, z5\.h\[0\]
-+ *[0-9a-f]+: 64f84800 bfmlalb z0\.s, z0\.h, z0\.h\[7\]
-+ *[0-9a-f]+: 2e5bfeb1 bfdot v17\.2s, v21\.4h, v27\.4h
-+ *[0-9a-f]+: 2e40fc00 bfdot v0\.2s, v0\.4h, v0\.4h
-+ *[0-9a-f]+: 6e5bfeb1 bfdot v17\.4s, v21\.8h, v27\.8h
-+ *[0-9a-f]+: 6e40fc00 bfdot v0\.4s, v0\.8h, v0\.8h
-+ *[0-9a-f]+: 0f7bfab1 bfdot v17\.2s, v21\.4h, v27\.2h\[3\]
-+ *[0-9a-f]+: 0f60f800 bfdot v0\.2s, v0\.4h, v0\.2h\[3\]
-+ *[0-9a-f]+: 4f7bfab1 bfdot v17\.4s, v21\.8h, v27\.2h\[3\]
-+ *[0-9a-f]+: 4f60f800 bfdot v0\.4s, v0\.8h, v0\.2h\[3\]
-+ *[0-9a-f]+: 0f5bf2b1 bfdot v17\.2s, v21\.4h, v27\.2h\[0\]
-+ *[0-9a-f]+: 0f40f000 bfdot v0\.2s, v0\.4h, v0\.2h\[0\]
-+ *[0-9a-f]+: 4f5bf2b1 bfdot v17\.4s, v21\.8h, v27\.2h\[0\]
-+ *[0-9a-f]+: 4f40f000 bfdot v0\.4s, v0\.8h, v0\.2h\[0\]
-+ *[0-9a-f]+: 6e5beeb1 bfmmla v17\.4s, v21\.8h, v27\.8h
-+ *[0-9a-f]+: 6e40ec00 bfmmla v0\.4s, v0\.8h, v0\.8h
-+ *[0-9a-f]+: 2edbfeb1 bfmlalb v17\.4s, v21\.8h, v27\.8h
-+ *[0-9a-f]+: 2ec0fc00 bfmlalb v0\.4s, v0\.8h, v0\.8h
-+ *[0-9a-f]+: 6edbfeb1 bfmlalt v17\.4s, v21\.8h, v27\.8h
-+ *[0-9a-f]+: 6ec0fc00 bfmlalt v0\.4s, v0\.8h, v0\.8h
-+ *[0-9a-f]+: 0fcff2b1 bfmlalb v17\.4s, v21\.8h, v15\.h\[0\]
-+ *[0-9a-f]+: 0ff0f800 bfmlalb v0\.4s, v0\.8h, v0\.h\[7\]
-+ *[0-9a-f]+: 4fcff2b1 bfmlalt v17\.4s, v21\.8h, v15\.h\[0\]
-+ *[0-9a-f]+: 4ff0f800 bfmlalt v0\.4s, v0\.8h, v0\.h\[7\]
-+ *[0-9a-f]+: 0ea16ab1 bfcvtn v17\.4h, v21\.4s
-+ *[0-9a-f]+: 0ea16800 bfcvtn v0\.4h, v0\.4s
-+ *[0-9a-f]+: 4ea16ab1 bfcvtn2 v17\.8h, v21\.4s
-+ *[0-9a-f]+: 4ea16800 bfcvtn2 v0\.8h, v0\.4s
-+ *[0-9a-f]+: 1e6342b1 bfcvt h17, s21
-+ *[0-9a-f]+: 1e634000 bfcvt h0, s0
---- /dev/null 2021-03-23 09:32:24.062139171 +0000
-+++ binutils-2.30.new/gas/testsuite/gas/aarch64/bfloat16.s 2021-03-23 16:19:56.777751765 +0000
-@@ -0,0 +1,70 @@
-+/* The instructions with non-zero register numbers are there to ensure we have
-+ the correct argument positioning (i.e. check that the first argument is at
-+ the end of the word etc).
-+ The instructions with all-zero register numbers are to ensure the previous
-+ encoding didn't just "happen" to fit -- so that if we change the registers
-+ that changes the correct part of the word.
-+ Each of the numbered patterns begin and end with a 1, so we can replace
-+ them with all-zeros and see the entire range has changed. */
-+
-+// SVE
-+bfdot z17.s, z21.h, z27.h
-+bfdot z0.s, z0.h, z0.h
-+
-+bfdot z17.s, z21.h, z5.h[3]
-+bfdot z0.s, z0.h, z0.h[3]
-+bfdot z0.s, z0.h, z0.h[0]
-+
-+bfmmla z17.s, z21.h, z27.h
-+bfmmla z0.s, z0.h, z0.h
-+
-+bfcvt z17.h, p5/m, z21.s
-+bfcvt z0.h, p0/m, z0.s
-+bfcvtnt z17.h, p5/m, z21.s
-+bfcvtnt z0.h, p0/m, z0.s
-+
-+bfmlalt z17.s, z21.h, z27.h
-+bfmlalt z0.s, z0.h, z0.h
-+bfmlalb z17.s, z21.h, z27.h
-+bfmlalb z0.s, z0.h, z0.h
-+
-+bfmlalt z17.s, z21.h, z5.h[0]
-+bfmlalt z0.s, z0.h, z0.h[7]
-+bfmlalb z17.s, z21.h, z5.h[0]
-+bfmlalb z0.s, z0.h, z0.h[7]
-+
-+// SIMD
-+bfdot v17.2s, v21.4h, v27.4h
-+bfdot v0.2s, v0.4h, v0.4h
-+bfdot v17.4s, v21.8h, v27.8h
-+bfdot v0.4s, v0.8h, v0.8h
-+
-+bfdot v17.2s, v21.4h, v27.2h[3]
-+bfdot v0.2s, v0.4h, v0.2h[3]
-+bfdot v17.4s, v21.8h, v27.2h[3]
-+bfdot v0.4s, v0.8h, v0.2h[3]
-+bfdot v17.2s, v21.4h, v27.2h[0]
-+bfdot v0.2s, v0.4h, v0.2h[0]
-+bfdot v17.4s, v21.8h, v27.2h[0]
-+bfdot v0.4s, v0.8h, v0.2h[0]
-+
-+bfmmla v17.4s, v21.8h, v27.8h
-+bfmmla v0.4s, v0.8h, v0.8h
-+
-+bfmlalb v17.4s, v21.8h, v27.8h
-+bfmlalb v0.4s, v0.8h, v0.8h
-+bfmlalt v17.4s, v21.8h, v27.8h
-+bfmlalt v0.4s, v0.8h, v0.8h
-+
-+bfmlalb v17.4s, v21.8h, v15.h[0]
-+bfmlalb v0.4s, v0.8h, v0.h[7]
-+bfmlalt v17.4s, v21.8h, v15.h[0]
-+bfmlalt v0.4s, v0.8h, v0.h[7]
-+
-+bfcvtn v17.4h, v21.4s
-+bfcvtn v0.4h, v0.4s
-+bfcvtn2 v17.8h, v21.4s
-+bfcvtn2 v0.8h, v0.4s
-+
-+bfcvt h17, s21
-+bfcvt h0, s0
---- /dev/null 2021-03-23 09:32:24.062139171 +0000
-+++ binutils-2.30.new/gas/testsuite/gas/aarch64/dgh.d 2021-03-23 16:19:56.777751765 +0000
-@@ -0,0 +1,11 @@
-+#name: V8.6 Data Gathering Hint
-+#as: -march=armv8.6-a
-+#objdump: -dr
-+
-+.* file format .*
-+
-+Disassembly of section \.text:
-+
-+0+ <\.text>:
-+ *[0-9a-f]*: d50320df hint #0x6
-+ *[0-9a-f]*: d50320df hint #0x6
---- /dev/null 2021-03-23 09:32:24.062139171 +0000
-+++ binutils-2.30.new/gas/testsuite/gas/aarch64/dgh.s 2021-03-23 16:19:56.777751765 +0000
-@@ -0,0 +1,4 @@
-+# Test for the V8.6-a Data Gathering Hint instruction
-+
-+dgh
-+hint #6
---- /dev/null 2021-03-23 09:32:24.062139171 +0000
-+++ binutils-2.30.new/gas/testsuite/gas/aarch64/f32mm.d 2021-03-23 16:19:56.777751765 +0000
-@@ -0,0 +1,11 @@
-+#as: -march=armv8.6-a+sve+f32mm
-+#objdump: -dr
-+
-+.*: file format .*
-+
-+
-+Disassembly of section \.text:
-+
-+0+ <\.text>:
-+ *[0-9a-f]+: 64bbe6b1 fmmla z17\.s, z21\.s, z27\.s
-+ *[0-9a-f]+: 64a0e400 fmmla z0\.s, z0\.s, z0\.s
---- /dev/null 2021-03-23 09:32:24.062139171 +0000
-+++ binutils-2.30.new/gas/testsuite/gas/aarch64/f32mm.s 2021-03-23 16:19:56.777751765 +0000
-@@ -0,0 +1,12 @@
-+/* The instructions with non-zero register numbers are there to ensure we have
-+ the correct argument positioning (i.e. check that the first argument is at
-+ the end of the word etc).
-+ The instructions with all-zero register numbers are to ensure the previous
-+ encoding didn't just "happen" to fit -- so that if we change the registers
-+ that changes the correct part of the word.
-+ Each of the numbered patterns begin and end with a 1, so we can replace
-+ them with all-zeros and see the entire range has changed. */
-+
-+// SVE
-+fmmla z17.s, z21.s, z27.s
-+fmmla z0.s, z0.s, z0.s
---- /dev/null 2021-03-23 09:32:24.062139171 +0000
-+++ binutils-2.30.new/gas/testsuite/gas/aarch64/f64mm.d 2021-03-23 16:19:56.777751765 +0000
-@@ -0,0 +1,62 @@
-+#as: -march=armv8.6-a+sve+f64mm
-+#objdump: -dr
-+
-+.*: file format .*
-+
-+Disassembly of section \.text:
-+
-+0+ <\.text>:
-+ *[0-9a-f]+: 64fbe6b1 fmmla z17\.d, z21\.d, z27\.d
-+ *[0-9a-f]+: 64e0e400 fmmla z0\.d, z0\.d, z0\.d
-+ *[0-9a-f]+: a43b17f1 ld1rob {z17\.b}, p5/z, \[sp, x27\]
-+ *[0-9a-f]+: a42003e0 ld1rob {z0\.b}, p0/z, \[sp, x0\]
-+ *[0-9a-f]+: a4bb17f1 ld1roh {z17\.h}, p5/z, \[sp, x27, lsl #1\]
-+ *[0-9a-f]+: a4a003e0 ld1roh {z0\.h}, p0/z, \[sp, x0, lsl #1\]
-+ *[0-9a-f]+: a53b17f1 ld1row {z17\.s}, p5/z, \[sp, x27, lsl #2\]
-+ *[0-9a-f]+: a52003e0 ld1row {z0\.s}, p0/z, \[sp, x0, lsl #2\]
-+ *[0-9a-f]+: a5bb17f1 ld1rod {z17\.d}, p5/z, \[sp, x27, lsl #3\]
-+ *[0-9a-f]+: a5a003e0 ld1rod {z0\.d}, p0/z, \[sp, x0, lsl #3\]
-+ *[0-9a-f]+: a43b1411 ld1rob {z17\.b}, p5/z, \[x0, x27\]
-+ *[0-9a-f]+: a4200000 ld1rob {z0\.b}, p0/z, \[x0, x0\]
-+ *[0-9a-f]+: a4bb1411 ld1roh {z17\.h}, p5/z, \[x0, x27, lsl #1\]
-+ *[0-9a-f]+: a4a00000 ld1roh {z0\.h}, p0/z, \[x0, x0, lsl #1\]
-+ *[0-9a-f]+: a53b1411 ld1row {z17\.s}, p5/z, \[x0, x27, lsl #2\]
-+ *[0-9a-f]+: a5200000 ld1row {z0\.s}, p0/z, \[x0, x0, lsl #2\]
-+ *[0-9a-f]+: a5bb1411 ld1rod {z17\.d}, p5/z, \[x0, x27, lsl #3\]
-+ *[0-9a-f]+: a5a00000 ld1rod {z0\.d}, p0/z, \[x0, x0, lsl #3\]
-+ *[0-9a-f]+: a42037f1 ld1rob {z17\.b}, p5/z, \[sp\]
-+ *[0-9a-f]+: a42723e0 ld1rob {z0\.b}, p0/z, \[sp, #224\]
-+ *[0-9a-f]+: a42823e0 ld1rob {z0\.b}, p0/z, \[sp, #-256\]
-+ *[0-9a-f]+: a4a037f1 ld1roh {z17\.h}, p5/z, \[sp\]
-+ *[0-9a-f]+: a4a723e0 ld1roh {z0\.h}, p0/z, \[sp, #224\]
-+ *[0-9a-f]+: a4a823e0 ld1roh {z0\.h}, p0/z, \[sp, #-256\]
-+ *[0-9a-f]+: a52037f1 ld1row {z17\.s}, p5/z, \[sp\]
-+ *[0-9a-f]+: a52723e0 ld1row {z0\.s}, p0/z, \[sp, #224\]
-+ *[0-9a-f]+: a52823e0 ld1row {z0\.s}, p0/z, \[sp, #-256\]
-+ *[0-9a-f]+: a5a037f1 ld1rod {z17\.d}, p5/z, \[sp\]
-+ *[0-9a-f]+: a5a723e0 ld1rod {z0\.d}, p0/z, \[sp, #224\]
-+ *[0-9a-f]+: a5a823e0 ld1rod {z0\.d}, p0/z, \[sp, #-256\]
-+ *[0-9a-f]+: a4203411 ld1rob {z17\.b}, p5/z, \[x0\]
-+ *[0-9a-f]+: a4272000 ld1rob {z0\.b}, p0/z, \[x0, #224\]
-+ *[0-9a-f]+: a4282000 ld1rob {z0\.b}, p0/z, \[x0, #-256\]
-+ *[0-9a-f]+: a4a03411 ld1roh {z17\.h}, p5/z, \[x0\]
-+ *[0-9a-f]+: a4a72000 ld1roh {z0\.h}, p0/z, \[x0, #224\]
-+ *[0-9a-f]+: a4a82000 ld1roh {z0\.h}, p0/z, \[x0, #-256\]
-+ *[0-9a-f]+: a5203411 ld1row {z17\.s}, p5/z, \[x0\]
-+ *[0-9a-f]+: a5272000 ld1row {z0\.s}, p0/z, \[x0, #224\]
-+ *[0-9a-f]+: a5282000 ld1row {z0\.s}, p0/z, \[x0, #-256\]
-+ *[0-9a-f]+: a5a03411 ld1rod {z17\.d}, p5/z, \[x0\]
-+ *[0-9a-f]+: a5a72000 ld1rod {z0\.d}, p0/z, \[x0, #224\]
-+ *[0-9a-f]+: a5a82000 ld1rod {z0\.d}, p0/z, \[x0, #-256\]
-+ *[0-9a-f]+: 05a502b1 zip1 z17\.q, z21\.q, z5\.q
-+ *[0-9a-f]+: 05a00000 zip1 z0\.q, z0\.q, z0\.q
-+ *[0-9a-f]+: 05a506b1 zip2 z17\.q, z21\.q, z5\.q
-+ *[0-9a-f]+: 05a00400 zip2 z0\.q, z0\.q, z0\.q
-+ *[0-9a-f]+: 05a50ab1 uzp1 z17\.q, z21\.q, z5\.q
-+ *[0-9a-f]+: 05a00800 uzp1 z0\.q, z0\.q, z0\.q
-+ *[0-9a-f]+: 05a50eb1 uzp2 z17\.q, z21\.q, z5\.q
-+ *[0-9a-f]+: 05a00c00 uzp2 z0\.q, z0\.q, z0\.q
-+ *[0-9a-f]+: 05a51ab1 trn1 z17\.q, z21\.q, z5\.q
-+ *[0-9a-f]+: 05a01800 trn1 z0\.q, z0\.q, z0\.q
-+ *[0-9a-f]+: 05a51eb1 trn2 z17\.q, z21\.q, z5\.q
-+ *[0-9a-f]+: 05a01c00 trn2 z0\.q, z0\.q, z0\.q
---- /dev/null 2021-03-23 09:32:24.062139171 +0000
-+++ binutils-2.30.new/gas/testsuite/gas/aarch64/f64mm.s 2021-03-23 16:19:56.777751765 +0000
-@@ -0,0 +1,71 @@
-+/* The instructions with non-zero register numbers are there to ensure we have
-+ the correct argument positioning (i.e. check that the first argument is at
-+ the end of the word etc).
-+ The instructions with all-zero register numbers are to ensure the previous
-+ encoding didn't just "happen" to fit -- so that if we change the registers
-+ that changes the correct part of the word.
-+ Each of the numbered patterns begin and end with a 1, so we can replace
-+ them with all-zeros and see the entire range has changed. */
-+
-+// SVE
-+fmmla z17.d, z21.d, z27.d
-+fmmla z0.d, z0.d, z0.d
-+
-+ld1rob { z17.b }, p5/z, [sp, x27]
-+ld1rob { z0.b }, p0/z, [sp, x0]
-+ld1roh { z17.h }, p5/z, [sp, x27, lsl #1]
-+ld1roh { z0.h }, p0/z, [sp, x0, lsl #1]
-+ld1row { z17.s }, p5/z, [sp, x27, lsl #2]
-+ld1row { z0.s }, p0/z, [sp, x0, lsl #2]
-+ld1rod { z17.d }, p5/z, [sp, x27, lsl #3]
-+ld1rod { z0.d }, p0/z, [sp, x0, lsl #3]
-+
-+ld1rob { z17.b }, p5/z, [x0, x27]
-+ld1rob { z0.b }, p0/z, [x0, x0]
-+ld1roh { z17.h }, p5/z, [x0, x27, lsl #1]
-+ld1roh { z0.h }, p0/z, [x0, x0, lsl #1]
-+ld1row { z17.s }, p5/z, [x0, x27, lsl #2]
-+ld1row { z0.s }, p0/z, [x0, x0, lsl #2]
-+ld1rod { z17.d }, p5/z, [x0, x27, lsl #3]
-+ld1rod { z0.d }, p0/z, [x0, x0, lsl #3]
-+
-+ld1rob { z17.b }, p5/z, [sp, #0]
-+ld1rob { z0.b }, p0/z, [sp, #224]
-+ld1rob { z0.b }, p0/z, [sp, #-256]
-+ld1roh { z17.h }, p5/z, [sp, #0]
-+ld1roh { z0.h }, p0/z, [sp, #224]
-+ld1roh { z0.h }, p0/z, [sp, #-256]
-+ld1row { z17.s }, p5/z, [sp, #0]
-+ld1row { z0.s }, p0/z, [sp, #224]
-+ld1row { z0.s }, p0/z, [sp, #-256]
-+ld1rod { z17.d }, p5/z, [sp, #0]
-+ld1rod { z0.d }, p0/z, [sp, #224]
-+ld1rod { z0.d }, p0/z, [sp, #-256]
-+
-+ld1rob { z17.b }, p5/z, [x0, #0]
-+ld1rob { z0.b }, p0/z, [x0, #224]
-+ld1rob { z0.b }, p0/z, [x0, #-256]
-+ld1roh { z17.h }, p5/z, [x0, #0]
-+ld1roh { z0.h }, p0/z, [x0, #224]
-+ld1roh { z0.h }, p0/z, [x0, #-256]
-+ld1row { z17.s }, p5/z, [x0, #0]
-+ld1row { z0.s }, p0/z, [x0, #224]
-+ld1row { z0.s }, p0/z, [x0, #-256]
-+ld1rod { z17.d }, p5/z, [x0, #0]
-+ld1rod { z0.d }, p0/z, [x0, #224]
-+ld1rod { z0.d }, p0/z, [x0, #-256]
-+
-+zip1 z17.q, z21.q, z5.q
-+zip1 z0.q, z0.q, z0.q
-+zip2 z17.q, z21.q, z5.q
-+zip2 z0.q, z0.q, z0.q
-+
-+uzp1 z17.q, z21.q, z5.q
-+uzp1 z0.q, z0.q, z0.q
-+uzp2 z17.q, z21.q, z5.q
-+uzp2 z0.q, z0.q, z0.q
-+
-+trn1 z17.q, z21.q, z5.q
-+trn1 z0.q, z0.q, z0.q
-+trn2 z17.q, z21.q, z5.q
-+trn2 z0.q, z0.q, z0.q
---- /dev/null 2021-03-23 09:32:24.062139171 +0000
-+++ binutils-2.30.new/gas/testsuite/gas/aarch64/i8mm.d 2021-03-23 16:19:56.777751765 +0000
-@@ -0,0 +1,51 @@
-+#as: -march=armv8.6-a+sve
-+#objdump: -dr
-+
-+.*: file format .*
-+
-+
-+Disassembly of section \.text:
-+
-+0+ <\.text>:
-+ *[0-9a-f]+: 451b9ab1 smmla z17\.s, z21\.b, z27\.b
-+ *[0-9a-f]+: 45009800 smmla z0\.s, z0\.b, z0\.b
-+ *[0-9a-f]+: 45db9ab1 ummla z17\.s, z21\.b, z27\.b
-+ *[0-9a-f]+: 45c09800 ummla z0\.s, z0\.b, z0\.b
-+ *[0-9a-f]+: 459b9ab1 usmmla z17\.s, z21\.b, z27\.b
-+ *[0-9a-f]+: 45809800 usmmla z0\.s, z0\.b, z0\.b
-+ *[0-9a-f]+: 449b7ab1 usdot z17\.s, z21\.b, z27\.b
-+ *[0-9a-f]+: 44807800 usdot z0\.s, z0\.b, z0\.b
-+ *[0-9a-f]+: 44bf1ab1 usdot z17\.s, z21\.b, z7\.b\[3\]
-+ *[0-9a-f]+: 44b81800 usdot z0\.s, z0\.b, z0\.b\[3\]
-+ *[0-9a-f]+: 44a71ab1 usdot z17\.s, z21\.b, z7\.b\[0\]
-+ *[0-9a-f]+: 44a01800 usdot z0\.s, z0\.b, z0\.b\[0\]
-+ *[0-9a-f]+: 44bf1eb1 sudot z17\.s, z21\.b, z7\.b\[3\]
-+ *[0-9a-f]+: 44b81c00 sudot z0\.s, z0\.b, z0\.b\[3\]
-+ *[0-9a-f]+: 44a71eb1 sudot z17\.s, z21\.b, z7\.b\[0\]
-+ *[0-9a-f]+: 44a01c00 sudot z0\.s, z0\.b, z0\.b\[0\]
-+ *[0-9a-f]+: 4e9ba6b1 smmla v17\.4s, v21\.16b, v27\.16b
-+ *[0-9a-f]+: 4e9ba6b1 smmla v17\.4s, v21\.16b, v27\.16b
-+ *[0-9a-f]+: 6e9ba6b1 ummla v17\.4s, v21\.16b, v27\.16b
-+ *[0-9a-f]+: 6e80a400 ummla v0\.4s, v0\.16b, v0\.16b
-+ *[0-9a-f]+: 4e80ac00 usmmla v0\.4s, v0\.16b, v0\.16b
-+ *[0-9a-f]+: 4e9baeb1 usmmla v17\.4s, v21\.16b, v27\.16b
-+ *[0-9a-f]+: 0e9b9eb1 usdot v17\.2s, v21\.8b, v27\.8b
-+ *[0-9a-f]+: 0e809c00 usdot v0\.2s, v0\.8b, v0\.8b
-+ *[0-9a-f]+: 4e9b9eb1 usdot v17\.4s, v21\.16b, v27\.16b
-+ *[0-9a-f]+: 4e809c00 usdot v0\.4s, v0\.16b, v0\.16b
-+ *[0-9a-f]+: 0fbbfab1 usdot v17\.2s, v21\.8b, v27\.4b\[3\]
-+ *[0-9a-f]+: 0fa0f800 usdot v0\.2s, v0\.8b, v0\.4b\[3\]
-+ *[0-9a-f]+: 0f9bf2b1 usdot v17\.2s, v21\.8b, v27\.4b\[0\]
-+ *[0-9a-f]+: 0f80f000 usdot v0\.2s, v0\.8b, v0\.4b\[0\]
-+ *[0-9a-f]+: 4fbbfab1 usdot v17\.4s, v21\.16b, v27\.4b\[3\]
-+ *[0-9a-f]+: 4fa0f800 usdot v0\.4s, v0\.16b, v0\.4b\[3\]
-+ *[0-9a-f]+: 4f9bf2b1 usdot v17\.4s, v21\.16b, v27\.4b\[0\]
-+ *[0-9a-f]+: 4f80f000 usdot v0\.4s, v0\.16b, v0\.4b\[0\]
-+ *[0-9a-f]+: 0f3bfab1 sudot v17\.2s, v21\.8b, v27\.4b\[3\]
-+ *[0-9a-f]+: 0f20f800 sudot v0\.2s, v0\.8b, v0\.4b\[3\]
-+ *[0-9a-f]+: 0f1bf2b1 sudot v17\.2s, v21\.8b, v27\.4b\[0\]
-+ *[0-9a-f]+: 0f00f000 sudot v0\.2s, v0\.8b, v0\.4b\[0\]
-+ *[0-9a-f]+: 4f3bfab1 sudot v17\.4s, v21\.16b, v27\.4b\[3\]
-+ *[0-9a-f]+: 4f20f800 sudot v0\.4s, v0\.16b, v0\.4b\[3\]
-+ *[0-9a-f]+: 4f1bf2b1 sudot v17\.4s, v21\.16b, v27\.4b\[0\]
-+ *[0-9a-f]+: 4f00f000 sudot v0\.4s, v0\.16b, v0\.4b\[0\]
---- /dev/null 2021-03-23 09:32:24.062139171 +0000
-+++ binutils-2.30.new/gas/testsuite/gas/aarch64/i8mm.s 2021-03-23 16:19:56.777751765 +0000
-@@ -0,0 +1,64 @@
-+/* The instructions with non-zero register numbers are there to ensure we have
-+ the correct argument positioning (i.e. check that the first argument is at
-+ the end of the word etc).
-+ The instructions with all-zero register numbers are to ensure the previous
-+ encoding didn't just "happen" to fit -- so that if we change the registers
-+ that changes the correct part of the word.
-+ Each of the numbered patterns begin and end with a 1, so we can replace
-+ them with all-zeros and see the entire range has changed. */
-+
-+// SVE
-+smmla z17.s, z21.b, z27.b
-+smmla z0.s, z0.b, z0.b
-+
-+ummla z17.s, z21.b, z27.b
-+ummla z0.s, z0.b, z0.b
-+
-+usmmla z17.s, z21.b, z27.b
-+usmmla z0.s, z0.b, z0.b
-+
-+usdot z17.s, z21.b, z27.b
-+usdot z0.s, z0.b, z0.b
-+
-+usdot z17.s, z21.b, z7.b[3]
-+usdot z0.s, z0.b, z0.b[3]
-+usdot z17.s, z21.b, z7.b[0]
-+usdot z0.s, z0.b, z0.b[0]
-+
-+sudot z17.s, z21.b, z7.b[3]
-+sudot z0.s, z0.b, z0.b[3]
-+sudot z17.s, z21.b, z7.b[0]
-+sudot z0.s, z0.b, z0.b[0]
-+
-+// SIMD
-+smmla v17.4s, v21.16b, v27.16b
-+smmla v17.4s, v21.16b, v27.16b
-+
-+ummla v17.4s, v21.16b, v27.16b
-+ummla v0.4s, v0.16b, v0.16b
-+
-+usmmla v0.4s, v0.16b, v0.16b
-+usmmla v17.4s, v21.16b, v27.16b
-+
-+usdot v17.2s, v21.8b, v27.8b
-+usdot v0.2s, v0.8b, v0.8b
-+usdot v17.4s, v21.16b, v27.16b
-+usdot v0.4s, v0.16b, v0.16b
-+
-+usdot v17.2s, v21.8b, v27.4b[3]
-+usdot v0.2s, v0.8b, v0.4b[3]
-+usdot v17.2s, v21.8b, v27.4b[0]
-+usdot v0.2s, v0.8b, v0.4b[0]
-+usdot v17.4s, v21.16b, v27.4b[3]
-+usdot v0.4s, v0.16b, v0.4b[3]
-+usdot v17.4s, v21.16b, v27.4b[0]
-+usdot v0.4s, v0.16b, v0.4b[0]
-+
-+sudot v17.2s, v21.8b, v27.4b[3]
-+sudot v0.2s, v0.8b, v0.4b[3]
-+sudot v17.2s, v21.8b, v27.4b[0]
-+sudot v0.2s, v0.8b, v0.4b[0]
-+sudot v17.4s, v21.16b, v27.4b[3]
-+sudot v0.4s, v0.16b, v0.4b[3]
-+sudot v17.4s, v21.16b, v27.4b[0]
-+sudot v0.4s, v0.16b, v0.4b[0]
---- /dev/null 2021-03-23 09:32:24.062139171 +0000
-+++ binutils-2.30.new/gas/testsuite/gas/aarch64/illegal-bfloat16.d 2021-03-23 16:19:56.777751765 +0000
-@@ -0,0 +1,4 @@
-+#name: Illegal Bfloat16 instructions
-+#as: -march=armv8.6-a+bf16+sve
-+#source: illegal-bfloat16.s
-+#error-output: illegal-bfloat16.l
---- /dev/null 2021-03-23 09:32:24.062139171 +0000
-+++ binutils-2.30.new/gas/testsuite/gas/aarch64/illegal-bfloat16.l 2021-03-23 16:19:56.777751765 +0000
-@@ -0,0 +1,95 @@
-+[^ :]+: Assembler messages:
-+[^ :]+:[0-9]+: Error: operand mismatch -- `bfdot z0\.s,z1\.h,z2\.s'
-+[^ :]+:[0-9]+: Info: did you mean this\?
-+[^ :]+:[0-9]+: Info: bfdot z0\.s, z1\.h, z2\.h
-+[^ :]+:[0-9]+: Error: operand mismatch -- `bfdot z0\.s,z1\.h,z3\.s\[3\]'
-+[^ :]+:[0-9]+: Info: did you mean this\?
-+[^ :]+:[0-9]+: Info: bfdot z0\.s, z1\.h, z3\.h\[3\]
-+[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `bfdot z0\.s,z1\.h,z3\.h\[4\]'
-+[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `bfdot z0\.s,z1\.h,z8\.h\[3\]'
-+[^ :]+:[0-9]+: Error: operand mismatch -- `bfmmla z0\.s,z1\.h,z2\.s'
-+[^ :]+:[0-9]+: Info: did you mean this\?
-+[^ :]+:[0-9]+: Info: bfmmla z0\.s, z1\.h, z2\.h
-+[^ :]+:[0-9]+: Error: operand mismatch -- `bfcvt z0\.h,p1/z,z2\.s'
-+[^ :]+:[0-9]+: Info: did you mean this\?
-+[^ :]+:[0-9]+: Info: bfcvt z0\.h, p1/m, z2\.s
-+[^ :]+:[0-9]+: Error: operand mismatch -- `bfcvt z0\.h,p1/m,z2\.h'
-+[^ :]+:[0-9]+: Info: did you mean this\?
-+[^ :]+:[0-9]+: Info: bfcvt z0\.h, p1/m, z2\.s
-+[^ :]+:[0-9]+: Error: operand mismatch -- `bfcvtnt z0\.h,p1/z,z2\.s'
-+[^ :]+:[0-9]+: Info: did you mean this\?
-+[^ :]+:[0-9]+: Info: bfcvtnt z0\.h, p1/m, z2\.s
-+[^ :]+:[0-9]+: Error: operand mismatch -- `bfcvtnt z0\.h,p1/m,z2\.h'
-+[^ :]+:[0-9]+: Info: did you mean this\?
-+[^ :]+:[0-9]+: Info: bfcvtnt z0\.h, p1/m, z2\.s
-+[^ :]+:[0-9]+: Error: operand mismatch -- `bfmlalt z0\.s,z0\.h,z0\.s'
-+[^ :]+:[0-9]+: Info: did you mean this\?
-+[^ :]+:[0-9]+: Info: bfmlalt z0\.s, z0\.h, z0\.h
-+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `bfmlalt z32\.s,z0\.h,z0\.h'
-+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `bfmlalt z0\.s,z32\.h,z0\.h'
-+[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `bfmlalt z0\.s,z0\.h,z32\.h'
-+[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `bfmlalt z0\.s,z0\.h,z0\.h\[8\]'
-+[^ :]+:[0-9]+: Error: operand mismatch -- `bfmlalt z0\.s,z0\.h,z0\.s\[0\]'
-+[^ :]+:[0-9]+: Info: did you mean this\?
-+[^ :]+:[0-9]+: Info: bfmlalt z0\.s, z0\.h, z0\.h\[0\]
-+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `bfmlalt z32\.s,z0\.h,z0\.h\[0\]'
-+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `bfmlalt z0\.s,z32\.h,z0\.h\[0\]'
-+[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `bfmlalt z0\.s,z0\.h,z8\.h\[0\]'
-+[^ :]+:[0-9]+: Error: operand mismatch -- `bfmlalb z0\.s,z0\.h,z0\.s'
-+[^ :]+:[0-9]+: Info: did you mean this\?
-+[^ :]+:[0-9]+: Info: bfmlalb z0\.s, z0\.h, z0\.h
-+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `bfmlalb z32\.s,z0\.h,z0\.h'
-+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `bfmlalb z0\.s,z32\.h,z0\.h'
-+[^ :]+:[0-9]+: Error: operand 3 must be an indexed SVE vector register -- `bfmlalb z0\.s,z0\.h,z32\.h'
-+[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `bfmlalb z0\.s,z0\.h,z0\.h\[8\]'
-+[^ :]+:[0-9]+: Error: operand mismatch -- `bfmlalb z0\.s,z0\.h,z0\.s\[0\]'
-+[^ :]+:[0-9]+: Info: did you mean this\?
-+[^ :]+:[0-9]+: Info: bfmlalb z0\.s, z0\.h, z0\.h\[0\]
-+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `bfmlalb z32\.s,z0\.h,z0\.h\[0\]'
-+[^ :]+:[0-9]+: Error: operand 2 must be an SVE vector register -- `bfmlalb z0\.s,z32\.h,z0\.h\[0\]'
-+[^ :]+:[0-9]+: Error: z0-z7 expected at operand 3 -- `bfmlalb z0\.s,z0\.h,z8\.h\[0\]'
-+[^ :]+:[0-9]+: Error: operand mismatch -- `bfdot v0\.2s,v1\.4h,v2\.2s\[3\]'
-+[^ :]+:[0-9]+: Info: did you mean this\?
-+[^ :]+:[0-9]+: Info: bfdot v0\.2s, v1\.4h, v2\.2h\[3\]
-+[^ :]+:[0-9]+: Info: other valid variant\(s\):
-+[^ :]+:[0-9]+: Info: bfdot v0\.4s, v1\.8h, v2\.2h\[3\]
-+[^ :]+:[0-9]+: Error: register element index out of range 0 to 3 at operand 3 -- `bfdot v0\.4s,v1\.8h,v2\.2h\[4\]'
-+[^ :]+:[0-9]+: Error: invalid element size 8 and vector size combination s at operand 3 -- `bfmmla v0\.4s,v1\.8h,v2\.8s'
-+[^ :]+:[0-9]+: Error: operand mismatch -- `bfmmla v0\.4s,v1\.4h,v2\.8h'
-+[^ :]+:[0-9]+: Info: did you mean this\?
-+[^ :]+:[0-9]+: Info: bfmmla v0\.4s, v1\.8h, v2\.8h
-+[^ :]+:[0-9]+: Error: operand mismatch -- `bfmlalb v0\.4s,v0\.4h,v0\.8h'
-+[^ :]+:[0-9]+: Info: did you mean this\?
-+[^ :]+:[0-9]+: Info: bfmlalb v0\.4s, v0\.8h, v0\.8h
-+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `bfmlalb v32\.4s,v0\.8h,v0\.8h'
-+[^ :]+:[0-9]+: Error: operand 2 must be a SIMD vector register -- `bfmlalb v0\.4s,v32\.8h,v0\.8h'
-+[^ :]+:[0-9]+: Error: operand 3 must be a SIMD vector register -- `bfmlalb v0\.4s,v0\.8h,v32\.8h'
-+[^ :]+:[0-9]+: Error: operand mismatch -- `bfmlalt v0\.4s,v0\.8h,v0\.4h'
-+[^ :]+:[0-9]+: Info: did you mean this\?
-+[^ :]+:[0-9]+: Info: bfmlalt v0\.4s, v0\.8h, v0\.8h
-+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `bfmlalt v32\.4s,v0\.8h,v0\.8h'
-+[^ :]+:[0-9]+: Error: operand 2 must be a SIMD vector register -- `bfmlalt v0\.4s,v32\.8h,v0\.8h'
-+[^ :]+:[0-9]+: Error: operand 3 must be a SIMD vector register -- `bfmlalt v0\.4s,v0\.8h,v32\.8h'
-+[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `bfmlalb v0\.4s,v0\.8h,v0\.h\[8\]'
-+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `bfmlalb v32\.4s,v0\.8h,v0\.h\[0\]'
-+[^ :]+:[0-9]+: Error: operand 2 must be a SIMD vector register -- `bfmlalb v0\.4s,v32\.8h,v0\.h\[0\]'
-+[^ :]+:[0-9]+: Error: register number out of range 0 to 15 at operand 3 -- `bfmlalb v0\.4s,v0\.8h,v16\.h\[0\]'
-+[^ :]+:[0-9]+: Error: operand mismatch -- `bfmlalb v0\.4s,v0\.4h,v0\.h\[0\]'
-+[^ :]+:[0-9]+: Info: did you mean this\?
-+[^ :]+:[0-9]+: Info: bfmlalb v0\.4s, v0\.8h, v0\.h\[0\]
-+[^ :]+:[0-9]+: Error: operand mismatch -- `bfmlalb v0\.4s,v0\.8h,v0\.s\[0\]'
-+[^ :]+:[0-9]+: Info: did you mean this\?
-+[^ :]+:[0-9]+: Info: bfmlalb v0\.4s, v0\.8h, v0\.h\[0\]
-+[^ :]+:[0-9]+: Error: operand mismatch -- `bfmlalt v0\.4s,v0\.8h,v0\.s\[0\]'
-+[^ :]+:[0-9]+: Info: did you mean this\?
-+[^ :]+:[0-9]+: Info: bfmlalt v0\.4s, v0\.8h, v0\.h\[0\]
-+[^ :]+:[0-9]+: Error: operand mismatch -- `bfmlalt v0\.4s,v0\.4h,v0\.h\[0\]'
-+[^ :]+:[0-9]+: Info: did you mean this\?
-+[^ :]+:[0-9]+: Info: bfmlalt v0\.4s, v0\.8h, v0\.h\[0\]
-+[^ :]+:[0-9]+: Error: register element index out of range 0 to 7 at operand 3 -- `bfmlalt v0\.4s,v0\.8h,v0\.h\[8\]'
-+[^ :]+:[0-9]+: Error: operand 1 must be an SVE vector register -- `bfmlalt v32\.4s,v0\.8h,v0\.h\[0\]'
-+[^ :]+:[0-9]+: Error: operand 2 must be a SIMD vector register -- `bfmlalt v0\.4s,v32\.8h,v0\.h\[0\]'
-+[^ :]+:[0-9]+: Error: register number out of range 0 to 15 at operand 3 -- `bfmlalt v0\.4s,v0\.8h,v16\.h\[0\]'
-+[^ :]+:[0-9]+: Error: operand mismatch -- `bfcvt h0,h1'
-+[^ :]+:[0-9]+: Info: did you mean this\?
-+[^ :]+:[0-9]+: Info: bfcvt h0, s1
---- /dev/null 2021-03-23 09:32:24.062139171 +0000
-+++ binutils-2.30.new/gas/testsuite/gas/aarch64/illegal-bfloat16.s 2021-03-23 16:19:56.777751765 +0000
-@@ -0,0 +1,67 @@
-+// SVE
-+bfdot z0.s, z1.h, z2.s // Fails from size types
-+
-+bfdot z0.s, z1.h, z3.s[3] // Fails from size types
-+bfdot z0.s, z1.h, z3.h[4] // Fails from index size
-+bfdot z0.s, z1.h, z8.h[3] // Fails from vector number
-+
-+bfmmla z0.s, z1.h, z2.s // Fails from size types
-+
-+bfcvt z0.h, p1/z, z2.s // Fails from merge type
-+bfcvt z0.h, p1/m, z2.h // Fails from size type
-+
-+bfcvtnt z0.h, p1/z, z2.s // Fails from merge type
-+bfcvtnt z0.h, p1/m, z2.h // Fails from size type
-+
-+bfmlalt z0.s, z0.h, z0.s // Fails from size type
-+bfmlalt z32.s, z0.h, z0.h
-+bfmlalt z0.s, z32.h, z0.h
-+bfmlalt z0.s, z0.h, z32.h
-+
-+bfmlalt z0.s, z0.h, z0.h[8] // Fails from index size
-+bfmlalt z0.s, z0.h, z0.s[0] // Fails from size type
-+bfmlalt z32.s, z0.h, z0.h[0]
-+bfmlalt z0.s, z32.h, z0.h[0]
-+bfmlalt z0.s, z0.h, z8.h[0] // Fails from vector index
-+
-+bfmlalb z0.s, z0.h, z0.s // Fails from size type
-+bfmlalb z32.s, z0.h, z0.h
-+bfmlalb z0.s, z32.h, z0.h
-+bfmlalb z0.s, z0.h, z32.h
-+
-+bfmlalb z0.s, z0.h, z0.h[8] // Fails from index size
-+bfmlalb z0.s, z0.h, z0.s[0] // Fails from size type
-+bfmlalb z32.s, z0.h, z0.h[0]
-+bfmlalb z0.s, z32.h, z0.h[0]
-+bfmlalb z0.s, z0.h, z8.h[0] // Fails from vector index
-+
-+// SIMD
-+bfdot v0.2s, v1.4h, v2.2s[3] // Fails from size types
-+bfdot v0.4s, v1.8h, v2.2h[4] // Fails from index size
-+
-+bfmmla v0.4s, v1.8h, v2.8s // Fails from size types
-+bfmmla v0.4s, v1.4h, v2.8h // Fails from size types
-+
-+bfmlalb v0.4s, v0.4h, v0.8h
-+bfmlalb v32.4s, v0.8h, v0.8h
-+bfmlalb v0.4s, v32.8h, v0.8h
-+bfmlalb v0.4s, v0.8h, v32.8h
-+bfmlalt v0.4s, v0.8h, v0.4h
-+bfmlalt v32.4s, v0.8h, v0.8h
-+bfmlalt v0.4s, v32.8h, v0.8h
-+bfmlalt v0.4s, v0.8h, v32.8h
-+
-+bfmlalb v0.4s, v0.8h, v0.h[8]
-+bfmlalb v32.4s, v0.8h, v0.h[0]
-+bfmlalb v0.4s, v32.8h, v0.h[0]
-+bfmlalb v0.4s, v0.8h, v16.h[0]
-+bfmlalb v0.4s, v0.4h, v0.h[0]
-+bfmlalb v0.4s, v0.8h, v0.s[0]
-+bfmlalt v0.4s, v0.8h, v0.s[0]
-+bfmlalt v0.4s, v0.4h, v0.h[0]
-+bfmlalt v0.4s, v0.8h, v0.h[8]
-+bfmlalt v32.4s, v0.8h, v0.h[0]
-+bfmlalt v0.4s, v32.8h, v0.h[0]
-+bfmlalt v0.4s, v0.8h, v16.h[0]
-+
-+bfcvt h0, h1 // Fails from size types
---- /dev/null 2021-03-23 09:32:24.062139171 +0000
-+++ binutils-2.30.new/gas/testsuite/gas/aarch64/ls64.d 2021-03-23 16:19:56.778751758 +0000
-@@ -0,0 +1,58 @@
-+#name: LS64 instructions and system register
-+#objdump: -dr
-+
-+.*: file format .*
-+
-+Disassembly of section \.text:
-+
-+0+ <.*>:
-+.*: f83fd020 ld64b x0, \[x1\]
-+.*: f83fd022 ld64b x2, \[x1\]
-+.*: f83fd024 ld64b x4, \[x1\]
-+.*: f83fd026 ld64b x6, \[x1\]
-+.*: f83fd028 ld64b x8, \[x1\]
-+.*: f83fd02a ld64b x10, \[x1\]
-+.*: f83fd02c ld64b x12, \[x1\]
-+.*: f83fd02e ld64b x14, \[x1\]
-+.*: f83fd030 ld64b x16, \[x1\]
-+.*: f83fd032 ld64b x18, \[x1\]
-+.*: f83fd034 ld64b x20, \[x1\]
-+.*: f83fd036 ld64b x22, \[x1\]
-+.*: f83f9020 st64b x0, \[x1\]
-+.*: f83f9022 st64b x2, \[x1\]
-+.*: f83f9024 st64b x4, \[x1\]
-+.*: f83f9026 st64b x6, \[x1\]
-+.*: f83f9028 st64b x8, \[x1\]
-+.*: f83f902a st64b x10, \[x1\]
-+.*: f83f902c st64b x12, \[x1\]
-+.*: f83f902e st64b x14, \[x1\]
-+.*: f83f9030 st64b x16, \[x1\]
-+.*: f83f9032 st64b x18, \[x1\]
-+.*: f83f9034 st64b x20, \[x1\]
-+.*: f83f9036 st64b x22, \[x1\]
-+.*: f821b040 st64bv x1, x0, \[x2\]
-+.*: f820b042 st64bv x0, x2, \[x2\]
-+.*: f820b044 st64bv x0, x4, \[x2\]
-+.*: f820b046 st64bv x0, x6, \[x2\]
-+.*: f820b048 st64bv x0, x8, \[x2\]
-+.*: f820b04a st64bv x0, x10, \[x2\]
-+.*: f820b04c st64bv x0, x12, \[x2\]
-+.*: f820b04e st64bv x0, x14, \[x2\]
-+.*: f820b050 st64bv x0, x16, \[x2\]
-+.*: f820b052 st64bv x0, x18, \[x2\]
-+.*: f820b054 st64bv x0, x20, \[x2\]
-+.*: f820b056 st64bv x0, x22, \[x2\]
-+.*: f821a040 st64bv0 x1, x0, \[x2\]
-+.*: f820a042 st64bv0 x0, x2, \[x2\]
-+.*: f820a044 st64bv0 x0, x4, \[x2\]
-+.*: f820a046 st64bv0 x0, x6, \[x2\]
-+.*: f820a048 st64bv0 x0, x8, \[x2\]
-+.*: f820a04a st64bv0 x0, x10, \[x2\]
-+.*: f820a04c st64bv0 x0, x12, \[x2\]
-+.*: f820a04e st64bv0 x0, x14, \[x2\]
-+.*: f820a050 st64bv0 x0, x16, \[x2\]
-+.*: f820a052 st64bv0 x0, x18, \[x2\]
-+.*: f820a054 st64bv0 x0, x20, \[x2\]
-+.*: f820a056 st64bv0 x0, x22, \[x2\]
-+.*: d538d0a0 mrs x0, accdata_el1
-+.*: d518d0a0 msr accdata_el1, x0
---- /dev/null 2021-03-23 09:32:24.062139171 +0000
-+++ binutils-2.30.new/gas/testsuite/gas/aarch64/ls64.s 2021-03-23 16:19:56.778751758 +0000
-@@ -0,0 +1,63 @@
-+/* Atomic 64-byte load/store instructions. */
-+.arch armv8.6-a+ls64
-+
-+/* Single-copy Atomic 64-byte Load. */
-+ ld64b x0, [x1]
-+ ld64b x2, [x1]
-+ ld64b x4, [x1]
-+ ld64b x6, [x1]
-+ ld64b x8, [x1]
-+ ld64b x10, [x1]
-+ ld64b x12, [x1]
-+ ld64b x14, [x1]
-+ ld64b x16, [x1]
-+ ld64b x18, [x1]
-+ ld64b x20, [x1]
-+ ld64b x22, [x1]
-+
-+/* Single-copy Atomic 64-byte Store without Return. */
-+ st64b x0, [x1]
-+ st64b x2, [x1]
-+ st64b x4, [x1]
-+ st64b x6, [x1]
-+ st64b x8, [x1]
-+ st64b x10, [x1]
-+ st64b x12, [x1]
-+ st64b x14, [x1]
-+ st64b x16, [x1]
-+ st64b x18, [x1]
-+ st64b x20, [x1]
-+ st64b x22, [x1]
-+
-+/* Single-copy Atomic 64-byte Store with Return. */
-+ st64bv x1, x0, [x2]
-+ st64bv x0, x2, [x2]
-+ st64bv x0, x4, [x2]
-+ st64bv x0, x6, [x2]
-+ st64bv x0, x8, [x2]
-+ st64bv x0, x10, [x2]
-+ st64bv x0, x12, [x2]
-+ st64bv x0, x14, [x2]
-+ st64bv x0, x16, [x2]
-+ st64bv x0, x18, [x2]
-+ st64bv x0, x20, [x2]
-+ st64bv x0, x22, [x2]
-+
-+/* Single-copy Atomic 64-byte EL0 Store with Return. */
-+ st64bv0 x1, x0, [x2]
-+ st64bv0 x0, x2, [x2]
-+ st64bv0 x0, x4, [x2]
-+ st64bv0 x0, x6, [x2]
-+ st64bv0 x0, x8, [x2]
-+ st64bv0 x0, x10, [x2]
-+ st64bv0 x0, x12, [x2]
-+ st64bv0 x0, x14, [x2]
-+ st64bv0 x0, x16, [x2]
-+ st64bv0 x0, x18, [x2]
-+ st64bv0 x0, x20, [x2]
-+ st64bv0 x0, x22, [x2]
-+
-+.arch armv8-a
-+/* Accelerator Data system register. */
-+ mrs x0, accdata_el1
-+ msr accdata_el1, x0
---- /dev/null 2021-03-23 09:32:24.062139171 +0000
-+++ binutils-2.30.new/gas/testsuite/gas/aarch64/sve-bfloat-movprfx.d 2021-03-23 16:19:56.778751758 +0000
-@@ -0,0 +1,27 @@
-+#as: -march=armv8.6-a+bf16+sve
-+#objdump: -dr
-+
-+.* file format .*
-+
-+
-+Disassembly of section \.text:
-+
-+0+ <\.text>:
-+ *[0-9a-f]+: 0420bc20 movprfx z0, z1
-+ *[0-9a-f]+: 64638040 bfdot z0\.s, z2\.h, z3\.h
-+ *[0-9a-f]+: 0420bc20 movprfx z0, z1
-+ *[0-9a-f]+: 64634040 bfdot z0\.s, z2\.h, z3\.h\[0\]
-+ *[0-9a-f]+: 0420bc20 movprfx z0, z1
-+ *[0-9a-f]+: 6463e440 bfmmla z0\.s, z2\.h, z3\.h
-+ *[0-9a-f]+: 0420bc20 movprfx z0, z1
-+ *[0-9a-f]+: 64e38040 bfmlalb z0\.s, z2\.h, z3\.h
-+ *[0-9a-f]+: 0420bc20 movprfx z0, z1
-+ *[0-9a-f]+: 64e38440 bfmlalt z0\.s, z2\.h, z3\.h
-+ *[0-9a-f]+: 0420bc20 movprfx z0, z1
-+ *[0-9a-f]+: 64e34040 bfmlalb z0\.s, z2\.h, z3\.h\[0\]
-+ *[0-9a-f]+: 0420bc20 movprfx z0, z1
-+ *[0-9a-f]+: 64e34440 bfmlalt z0\.s, z2\.h, z3\.h\[0\]
-+ *[0-9a-f]+: 0420bc20 movprfx z0, z1
-+ *[0-9a-f]+: 658aa040 bfcvt z0\.h, p0/m, z2\.s
-+ *[0-9a-f]+: 04912020 movprfx z0\.s, p0/m, z1\.s
-+ *[0-9a-f]+: 658aa040 bfcvt z0\.h, p0/m, z2\.s
---- /dev/null 2021-03-23 09:32:24.062139171 +0000
-+++ binutils-2.30.new/gas/testsuite/gas/aarch64/sve-bfloat-movprfx.s 2021-03-23 16:19:56.778751758 +0000
-@@ -0,0 +1,31 @@
-+.text
-+.arch armv8.2-a+bf16+sve
-+
-+movprfx z0, z1
-+bfdot z0.s, z2.h, z3.h
-+
-+movprfx z0, z1
-+bfdot z0.s, z2.h, z3.h[0]
-+
-+movprfx z0, z1
-+bfmmla z0.s, z2.h, z3.h
-+
-+movprfx z0, z1
-+bfmlalb z0.s, z2.h, z3.h
-+
-+movprfx z0, z1
-+bfmlalt z0.s, z2.h, z3.h
-+
-+movprfx z0, z1
-+bfmlalb z0.s, z2.h, z3.h[0]
-+
-+movprfx z0, z1
-+bfmlalt z0.s, z2.h, z3.h[0]
-+
-+# Unpredicated movprfx + bfcvt
-+movprfx z0, z1
-+bfcvt z0.h, p0/m, z2.s
-+
-+# Predicated movprfx + bfcvt
-+movprfx z0.s, p0/m, z1.s
-+bfcvt z0.h, p0/m, z2.s
---- /dev/null 2021-03-23 09:32:24.062139171 +0000
-+++ binutils-2.30.new/gas/testsuite/gas/aarch64/sve-movprfx-mm.d 2021-03-23 16:19:56.778751758 +0000
-@@ -0,0 +1,24 @@
-+#as: -march=armv8.6-a+f32mm+f64mm+sve
-+#objdump: -dr
-+
-+.* file format .*
-+
-+Disassembly of section \.text:
-+
-+0+ <\.text>:
-+ *[0-9a-f]+: 0420bc11 movprfx z17, z0
-+ *[0-9a-f]+: 451b9ab1 smmla z17\.s, z21\.b, z27\.b
-+ *[0-9a-f]+: 0420bc11 movprfx z17, z0
-+ *[0-9a-f]+: 45db9ab1 ummla z17\.s, z21\.b, z27\.b
-+ *[0-9a-f]+: 0420bc11 movprfx z17, z0
-+ *[0-9a-f]+: 459b9ab1 usmmla z17\.s, z21\.b, z27\.b
-+ *[0-9a-f]+: 0420bc11 movprfx z17, z0
-+ *[0-9a-f]+: 449b7ab1 usdot z17\.s, z21\.b, z27\.b
-+ *[0-9a-f]+: 0420bc11 movprfx z17, z0
-+ *[0-9a-f]+: 44bf1ab1 usdot z17\.s, z21\.b, z7\.b\[3\]
-+ *[0-9a-f]+: 0420bc11 movprfx z17, z0
-+ *[0-9a-f]+: 44bf1eb1 sudot z17\.s, z21\.b, z7\.b\[3\]
-+ *[0-9a-f]+: 0420bc11 movprfx z17, z0
-+ *[0-9a-f]+: 64bbe6b1 fmmla z17\.s, z21\.s, z27\.s
-+ *[0-9a-f]+: 0420bc11 movprfx z17, z0
-+ *[0-9a-f]+: 64fbe6b1 fmmla z17\.d, z21\.d, z27\.d
---- /dev/null 2021-03-23 09:32:24.062139171 +0000
-+++ binutils-2.30.new/gas/testsuite/gas/aarch64/sve-movprfx-mm.s 2021-03-23 16:19:56.778751758 +0000
-@@ -0,0 +1,25 @@
-+/* MOVPRFX tests for matrix multiply instructions */
-+
-+movprfx z17, z0
-+smmla z17.s, z21.b, z27.b
-+
-+movprfx z17, z0
-+ummla z17.s, z21.b, z27.b
-+
-+movprfx z17, z0
-+usmmla z17.s, z21.b, z27.b
-+
-+movprfx z17, z0
-+usdot z17.s, z21.b, z27.b
-+
-+movprfx z17, z0
-+usdot z17.s, z21.b, z7.b[3]
-+
-+movprfx z17, z0
-+sudot z17.s, z21.b, z7.b[3]
-+
-+movprfx z17, z0
-+fmmla z17.s, z21.s, z27.s
-+
-+movprfx z17, z0
-+fmmla z17.d, z21.d, z27.d
---- binutils.nickc/bfd/elfnn-aarch64.c 2021-03-25 09:16:15.547456289 +0000
-+++ binutils-2.30/bfd/elfnn-aarch64.c 2021-03-25 10:26:47.910494843 +0000
-@@ -201,6 +201,14 @@
- || (R_TYPE) == BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12 \
- || (R_TYPE) == BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12 \
- || (R_TYPE) == BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC \
-+ || (R_TYPE) == BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12 \
-+ || (R_TYPE) == BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC \
-+ || (R_TYPE) == BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12 \
-+ || (R_TYPE) == BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC \
-+ || (R_TYPE) == BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12 \
-+ || (R_TYPE) == BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC \
-+ || (R_TYPE) == BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12 \
-+ || (R_TYPE) == BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC \
- || (R_TYPE) == BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0 \
- || (R_TYPE) == BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC \
- || (R_TYPE) == BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1 \
-@@ -617,6 +625,114 @@ static reloc_howto_type elfNN_aarch64_ho
- 0xffff, /* dst_mask */
- FALSE), /* pcrel_offset */
-
-+ /* Group relocations to create a 16, 32, 48 or 64 bit
-+ PC relative address inline. */
-+
-+ /* MOV[NZ]: ((S+A-P) >> 0) & 0xffff */
-+ HOWTO (AARCH64_R (MOVW_PREL_G0), /* type */
-+ 0, /* rightshift */
-+ 2, /* size (0 = byte, 1 = short, 2 = long) */
-+ 17, /* bitsize */
-+ TRUE, /* pc_relative */
-+ 0, /* bitpos */
-+ complain_overflow_signed, /* complain_on_overflow */
-+ bfd_elf_generic_reloc, /* special_function */
-+ AARCH64_R_STR (MOVW_PREL_G0), /* name */
-+ FALSE, /* partial_inplace */
-+ 0xffff, /* src_mask */
-+ 0xffff, /* dst_mask */
-+ TRUE), /* pcrel_offset */
-+
-+ /* MOVK: ((S+A-P) >> 0) & 0xffff [no overflow check] */
-+ HOWTO (AARCH64_R (MOVW_PREL_G0_NC), /* type */
-+ 0, /* rightshift */
-+ 2, /* size (0 = byte, 1 = short, 2 = long) */
-+ 16, /* bitsize */
-+ TRUE, /* pc_relative */
-+ 0, /* bitpos */
-+ complain_overflow_dont, /* complain_on_overflow */
-+ bfd_elf_generic_reloc, /* special_function */
-+ AARCH64_R_STR (MOVW_PREL_G0_NC), /* name */
-+ FALSE, /* partial_inplace */
-+ 0xffff, /* src_mask */
-+ 0xffff, /* dst_mask */
-+ TRUE), /* pcrel_offset */
-+
-+ /* MOV[NZ]: ((S+A-P) >> 16) & 0xffff */
-+ HOWTO (AARCH64_R (MOVW_PREL_G1), /* type */
-+ 16, /* rightshift */
-+ 2, /* size (0 = byte, 1 = short, 2 = long) */
-+ 17, /* bitsize */
-+ TRUE, /* pc_relative */
-+ 0, /* bitpos */
-+ complain_overflow_signed, /* complain_on_overflow */
-+ bfd_elf_generic_reloc, /* special_function */
-+ AARCH64_R_STR (MOVW_PREL_G1), /* name */
-+ FALSE, /* partial_inplace */
-+ 0xffff, /* src_mask */
-+ 0xffff, /* dst_mask */
-+ TRUE), /* pcrel_offset */
-+
-+ /* MOVK: ((S+A-P) >> 16) & 0xffff [no overflow check] */
-+ HOWTO64 (AARCH64_R (MOVW_PREL_G1_NC), /* type */
-+ 16, /* rightshift */
-+ 2, /* size (0 = byte, 1 = short, 2 = long) */
-+ 16, /* bitsize */
-+ TRUE, /* pc_relative */
-+ 0, /* bitpos */
-+ complain_overflow_dont, /* complain_on_overflow */
-+ bfd_elf_generic_reloc, /* special_function */
-+ AARCH64_R_STR (MOVW_PREL_G1_NC), /* name */
-+ FALSE, /* partial_inplace */
-+ 0xffff, /* src_mask */
-+ 0xffff, /* dst_mask */
-+ TRUE), /* pcrel_offset */
-+
-+ /* MOV[NZ]: ((S+A-P) >> 32) & 0xffff */
-+ HOWTO64 (AARCH64_R (MOVW_PREL_G2), /* type */
-+ 32, /* rightshift */
-+ 2, /* size (0 = byte, 1 = short, 2 = long) */
-+ 17, /* bitsize */
-+ TRUE, /* pc_relative */
-+ 0, /* bitpos */
-+ complain_overflow_signed, /* complain_on_overflow */
-+ bfd_elf_generic_reloc, /* special_function */
-+ AARCH64_R_STR (MOVW_PREL_G2), /* name */
-+ FALSE, /* partial_inplace */
-+ 0xffff, /* src_mask */
-+ 0xffff, /* dst_mask */
-+ TRUE), /* pcrel_offset */
-+
-+ /* MOVK: ((S+A-P) >> 32) & 0xffff [no overflow check] */
-+ HOWTO64 (AARCH64_R (MOVW_PREL_G2_NC), /* type */
-+ 32, /* rightshift */
-+ 2, /* size (0 = byte, 1 = short, 2 = long) */
-+ 16, /* bitsize */
-+ TRUE, /* pc_relative */
-+ 0, /* bitpos */
-+ complain_overflow_dont, /* complain_on_overflow */
-+ bfd_elf_generic_reloc, /* special_function */
-+ AARCH64_R_STR (MOVW_PREL_G2_NC), /* name */
-+ FALSE, /* partial_inplace */
-+ 0xffff, /* src_mask */
-+ 0xffff, /* dst_mask */
-+ TRUE), /* pcrel_offset */
-+
-+ /* MOV[NZ]: ((S+A-P) >> 48) & 0xffff */
-+ HOWTO64 (AARCH64_R (MOVW_PREL_G3), /* type */
-+ 48, /* rightshift */
-+ 2, /* size (0 = byte, 1 = short, 2 = long) */
-+ 16, /* bitsize */
-+ TRUE, /* pc_relative */
-+ 0, /* bitpos */
-+ complain_overflow_dont, /* complain_on_overflow */
-+ bfd_elf_generic_reloc, /* special_function */
-+ AARCH64_R_STR (MOVW_PREL_G3), /* name */
-+ FALSE, /* partial_inplace */
-+ 0xffff, /* src_mask */
-+ 0xffff, /* dst_mask */
-+ TRUE), /* pcrel_offset */
-+
- /* Relocations to generate 19, 21 and 33 bit PC-relative load/store
- addresses: PG(x) is (x & ~0xfff). */
-
-@@ -1527,6 +1643,126 @@ static reloc_howto_type elfNN_aarch64_ho
- 0xfff, /* dst_mask */
- FALSE), /* pcrel_offset */
-
-+ /* LD/ST16: bit[11:1] of byte offset to module TLS base address. */
-+ HOWTO (AARCH64_R (TLSLE_LDST16_TPREL_LO12), /* type */
-+ 1, /* rightshift */
-+ 2, /* size (0 = byte, 1 = short, 2 = long) */
-+ 11, /* bitsize */
-+ FALSE, /* pc_relative */
-+ 10, /* bitpos */
-+ complain_overflow_unsigned, /* complain_on_overflow */
-+ bfd_elf_generic_reloc, /* special_function */
-+ AARCH64_R_STR (TLSLE_LDST16_TPREL_LO12), /* name */
-+ FALSE, /* partial_inplace */
-+ 0x1ffc00, /* src_mask */
-+ 0x1ffc00, /* dst_mask */
-+ FALSE), /* pcrel_offset */
-+
-+ /* Same as BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12, but no overflow check. */
-+ HOWTO (AARCH64_R (TLSLE_LDST16_TPREL_LO12_NC), /* type */
-+ 1, /* rightshift */
-+ 2, /* size (0 = byte, 1 = short, 2 = long) */
-+ 11, /* bitsize */
-+ FALSE, /* pc_relative */
-+ 10, /* bitpos */
-+ complain_overflow_dont, /* complain_on_overflow */
-+ bfd_elf_generic_reloc, /* special_function */
-+ AARCH64_R_STR (TLSLE_LDST16_TPREL_LO12_NC), /* name */
-+ FALSE, /* partial_inplace */
-+ 0x1ffc00, /* src_mask */
-+ 0x1ffc00, /* dst_mask */
-+ FALSE), /* pcrel_offset */
-+
-+ /* LD/ST32: bit[11:2] of byte offset to module TLS base address. */
-+ HOWTO (AARCH64_R (TLSLE_LDST32_TPREL_LO12), /* type */
-+ 2, /* rightshift */
-+ 2, /* size (0 = byte, 1 = short, 2 = long) */
-+ 10, /* bitsize */
-+ FALSE, /* pc_relative */
-+ 10, /* bitpos */
-+ complain_overflow_unsigned, /* complain_on_overflow */
-+ bfd_elf_generic_reloc, /* special_function */
-+ AARCH64_R_STR (TLSLE_LDST32_TPREL_LO12), /* name */
-+ FALSE, /* partial_inplace */
-+ 0xffc00, /* src_mask */
-+ 0xffc00, /* dst_mask */
-+ FALSE), /* pcrel_offset */
-+
-+ /* Same as BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12, but no overflow check. */
-+ HOWTO (AARCH64_R (TLSLE_LDST32_TPREL_LO12_NC), /* type */
-+ 2, /* rightshift */
-+ 2, /* size (0 = byte, 1 = short, 2 = long) */
-+ 10, /* bitsize */
-+ FALSE, /* pc_relative */
-+ 10, /* bitpos */
-+ complain_overflow_dont, /* complain_on_overflow */
-+ bfd_elf_generic_reloc, /* special_function */
-+ AARCH64_R_STR (TLSLE_LDST32_TPREL_LO12_NC), /* name */
-+ FALSE, /* partial_inplace */
-+ 0xffc00, /* src_mask */
-+ 0xffc00, /* dst_mask */
-+ FALSE), /* pcrel_offset */
-+
-+ /* LD/ST64: bit[11:3] of byte offset to module TLS base address. */
-+ HOWTO (AARCH64_R (TLSLE_LDST64_TPREL_LO12), /* type */
-+ 3, /* rightshift */
-+ 2, /* size (0 = byte, 1 = short, 2 = long) */
-+ 9, /* bitsize */
-+ FALSE, /* pc_relative */
-+ 10, /* bitpos */
-+ complain_overflow_unsigned, /* complain_on_overflow */
-+ bfd_elf_generic_reloc, /* special_function */
-+ AARCH64_R_STR (TLSLE_LDST64_TPREL_LO12), /* name */
-+ FALSE, /* partial_inplace */
-+ 0x7fc00, /* src_mask */
-+ 0x7fc00, /* dst_mask */
-+ FALSE), /* pcrel_offset */
-+
-+ /* Same as BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12, but no overflow check. */
-+ HOWTO (AARCH64_R (TLSLE_LDST64_TPREL_LO12_NC), /* type */
-+ 3, /* rightshift */
-+ 2, /* size (0 = byte, 1 = short, 2 = long) */
-+ 9, /* bitsize */
-+ FALSE, /* pc_relative */
-+ 10, /* bitpos */
-+ complain_overflow_dont, /* complain_on_overflow */
-+ bfd_elf_generic_reloc, /* special_function */
-+ AARCH64_R_STR (TLSLE_LDST64_TPREL_LO12_NC), /* name */
-+ FALSE, /* partial_inplace */
-+ 0x7fc00, /* src_mask */
-+ 0x7fc00, /* dst_mask */
-+ FALSE), /* pcrel_offset */
-+
-+ /* LD/ST8: bit[11:0] of byte offset to module TLS base address. */
-+ HOWTO (AARCH64_R (TLSLE_LDST8_TPREL_LO12), /* type */
-+ 0, /* rightshift */
-+ 2, /* size (0 = byte, 1 = short, 2 = long) */
-+ 12, /* bitsize */
-+ FALSE, /* pc_relative */
-+ 10, /* bitpos */
-+ complain_overflow_unsigned, /* complain_on_overflow */
-+ bfd_elf_generic_reloc, /* special_function */
-+ AARCH64_R_STR (TLSLE_LDST8_TPREL_LO12), /* name */
-+ FALSE, /* partial_inplace */
-+ 0x3ffc00, /* src_mask */
-+ 0x3ffc00, /* dst_mask */
-+ FALSE), /* pcrel_offset */
-+
-+ /* Same as BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12, but no overflow check. */
-+ HOWTO (AARCH64_R (TLSLE_LDST8_TPREL_LO12_NC), /* type */
-+ 0, /* rightshift */
-+ 2, /* size (0 = byte, 1 = short, 2 = long) */
-+ 12, /* bitsize */
-+ FALSE, /* pc_relative */
-+ 10, /* bitpos */
-+ complain_overflow_dont, /* complain_on_overflow */
-+ bfd_elf_generic_reloc, /* special_function */
-+ AARCH64_R_STR (TLSLE_LDST8_TPREL_LO12_NC), /* name */
-+ FALSE, /* partial_inplace */
-+ 0x3ffc00, /* src_mask */
-+ 0x3ffc00, /* dst_mask */
-+ FALSE), /* pcrel_offset */
-+
- HOWTO (AARCH64_R (TLSDESC_LD_PREL19), /* type */
- 2, /* rightshift */
- 2, /* size (0 = byte, 1 = short, 2 = long) */
-@@ -5392,6 +5628,13 @@ bad_ifunc_reloc:
- case BFD_RELOC_AARCH64_ADR_HI21_PCREL:
- case BFD_RELOC_AARCH64_ADR_LO21_PCREL:
- case BFD_RELOC_AARCH64_LD_LO19_PCREL:
-+ case BFD_RELOC_AARCH64_MOVW_PREL_G0:
-+ case BFD_RELOC_AARCH64_MOVW_PREL_G0_NC:
-+ case BFD_RELOC_AARCH64_MOVW_PREL_G1:
-+ case BFD_RELOC_AARCH64_MOVW_PREL_G1_NC:
-+ case BFD_RELOC_AARCH64_MOVW_PREL_G2:
-+ case BFD_RELOC_AARCH64_MOVW_PREL_G2_NC:
-+ case BFD_RELOC_AARCH64_MOVW_PREL_G3:
- if (bfd_link_pic (info)
- && (input_section->flags & SEC_ALLOC) != 0
- && (input_section->flags & SEC_READONLY) != 0
-@@ -5409,6 +5652,23 @@ bad_ifunc_reloc:
- bfd_set_error (bfd_error_bad_value);
- return bfd_reloc_notsupported;
- }
-+ value = _bfd_aarch64_elf_resolve_relocation (bfd_r_type,
-+ place, value,
-+ signed_addend,
-+ weak_undef_p);
-+ break;
-+
-+ case BFD_RELOC_AARCH64_BRANCH19:
-+ case BFD_RELOC_AARCH64_TSTBR14:
-+ if (h && h->root.type == bfd_link_hash_undefined)
-+ {
-+ _bfd_error_handler
-+ /* xgettext:c-format */
-+ (_("%pB: conditional branch to undefined symbol `%s' "
-+ "not allowed"), input_bfd, h->root.root.string);
-+ bfd_set_error (bfd_error_bad_value);
-+ return bfd_reloc_notsupported;
-+ }
- /* Fall through. */
-
- case BFD_RELOC_AARCH64_16:
-@@ -5416,7 +5676,6 @@ bad_ifunc_reloc:
- case BFD_RELOC_AARCH64_32:
- #endif
- case BFD_RELOC_AARCH64_ADD_LO12:
-- case BFD_RELOC_AARCH64_BRANCH19:
- case BFD_RELOC_AARCH64_LDST128_LO12:
- case BFD_RELOC_AARCH64_LDST16_LO12:
- case BFD_RELOC_AARCH64_LDST32_LO12:
-@@ -5432,7 +5691,6 @@ bad_ifunc_reloc:
- case BFD_RELOC_AARCH64_MOVW_G2_NC:
- case BFD_RELOC_AARCH64_MOVW_G2_S:
- case BFD_RELOC_AARCH64_MOVW_G3:
-- case BFD_RELOC_AARCH64_TSTBR14:
- value = _bfd_aarch64_elf_resolve_relocation (bfd_r_type, place, value,
- signed_addend, weak_undef_p);
- break;
-@@ -5604,6 +5862,14 @@ bad_ifunc_reloc:
- case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12:
- case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12:
- case BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC:
-+ case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12:
-+ case BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC:
-+ case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12:
-+ case BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC:
-+ case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12:
-+ case BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC:
-+ case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12:
-+ case BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC:
- case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0:
- case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC:
- case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1:
-@@ -7318,9 +7584,6 @@ elfNN_aarch64_check_relocs (bfd *abfd, s
- case BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC:
- case BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21:
- case BFD_RELOC_AARCH64_TLSLD_ADR_PREL21:
-- case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1:
-- case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC:
-- case BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2:
- {
- unsigned got_type;
- unsigned old_got_type;
-diff -rup binutils.nickc/ld/testsuite/ld-aarch64/emit-relocs-534.d binutils-2.30/ld/testsuite/ld-aarch64/emit-relocs-534.d
---- binutils.nickc/ld/testsuite/ld-aarch64/emit-relocs-534.d 2021-03-25 09:15:07.899968264 +0000
-+++ binutils-2.30/ld/testsuite/ld-aarch64/emit-relocs-534.d 2021-03-25 10:42:15.528430527 +0000
-@@ -5,5 +5,5 @@
- 0000000000010000 <.text>:
- 10000: 798009d6 ldrsh x22, \[x14, #4\]
- 10000: R_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC v2
-- 10004: 79871a28 ldrsh x8, \[x17, #908\]
-+ 10004: 79.71a28 ldrsh x8, \[x17, #.*\]
- 10004: R_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC v3
-diff -rup binutils.nickc/ld/testsuite/ld-aarch64/erratum835769.d binutils-2.30/ld/testsuite/ld-aarch64/erratum835769.d
---- binutils.nickc/ld/testsuite/ld-aarch64/erratum835769.d 2021-03-25 09:15:09.604955360 +0000
-+++ binutils-2.30/ld/testsuite/ld-aarch64/erratum835769.d 2021-03-25 10:37:37.516539044 +0000
-@@ -33,8 +33,7 @@ Disassembly of section .text:
- [ \t0-9a-f]+:[ \t]+aa0503e0[ \t]+mov[ \t]+x0, x5
- [ \t0-9a-f]+:[ \t]+d65f03c0[ \t]+ret
-
--[ \t0-9a-f]+:[ \t]+14000008[ \t]+b[ \t]+[0-9a-f]+ <__erratum_835769_veneer_0\+0x8>
--[ \t0-9a-f]+:[ \t]+d503201f[ \t]+nop
-+[ \t0-9a-f]+:[ \t]+1400000.[ \t]+b[ \t]+[0-9a-f]+ <__erratum_835769_veneer_0\+0x8>
- [0-9a-f]+ <__erratum_835769_veneer_2>:
- [ \t0-9a-f]+:[ \t]+9b031885[ \t]+madd[ \t]+x5, x4, x3, x6
- [ \t0-9a-f]+:[ \t0-9a-z]+[ \t]+b[ \t]+[0-9a-f]+ <a7str\+0x[0-9a-f]+>
-diff -rup binutils.nickc/ld/testsuite/ld-aarch64/erratum843419.d binutils-2.30/ld/testsuite/ld-aarch64/erratum843419.d
---- binutils.nickc/ld/testsuite/ld-aarch64/erratum843419.d 2021-03-25 09:15:09.109959106 +0000
-+++ binutils-2.30/ld/testsuite/ld-aarch64/erratum843419.d 2021-03-25 10:39:46.650559662 +0000
-@@ -25,7 +25,6 @@ Disassembly of section .e843419:
- [ ]*20001018: 1400000. b 200010.. <__e835769_veneer>
- [ ]*2000101c: d65f03c0 ret
- [ ]*20001020: 14000400 b 200020.. <__e835769_veneer\+0xff.>
--[ \t0-9a-f]+:[ \t]+d503201f[ \t]+nop
-
- 0*2000102. <e843419@0002_00000013_1004>:
- [ ]*2000102.: f9000008 str x8, \[x0\]
-@@ -47,7 +46,6 @@ Disassembly of section .e835769:
- [ ]*3000010: aa0503e0 mov x0, x5
- [ ]*3000014: d65f03c0 ret
- [ ]*3000018: 14000400 b 3001018 <__erratum_835769_veneer_0\+0xff.>
--[ \t0-9a-f]+:[ \t]+d503201f[ \t]+nop
-
- 0*30000.. <__erratum_835769_veneer_0>:
- [ ]*30000..: 9b031845 madd x5, x2, x3, x6
-@@ -63,7 +61,6 @@ Disassembly of section .text:
- [ ]*40000c: 1400000. b 40001. <__e843419_veneer>
- [ ]*400010: d65f03c0 ret
- [ ]*400014: 14000400 b 401014 <__e843419_veneer\+0xff.>
--[ \t0-9a-f]+:[ \t]+d503201f[ \t]+nop
-
- 0*4000.. <__e843419_veneer>:
- [ ]*4000..: 900fe010 adrp x16, 20000000 <e843419>
-diff -rup binutils.nickc/ld/testsuite/ld-aarch64/farcall-b-defsym.d binutils-2.30/ld/testsuite/ld-aarch64/farcall-b-defsym.d
---- binutils.nickc/ld/testsuite/ld-aarch64/farcall-b-defsym.d 2021-03-25 09:15:09.151958788 +0000
-+++ binutils-2.30/ld/testsuite/ld-aarch64/farcall-b-defsym.d 2021-03-25 10:48:41.319504608 +0000
-@@ -8,12 +8,11 @@
- Disassembly of section .text:
-
- 0+1000 <_start>:
-- +1000: 14000004 b 1010 <__bar_veneer>
-+ +1000: 14000003 b 100c <__bar_veneer>
- +1004: d65f03c0 ret
--[ \t]+1008:[ \t]+14000008[ \t]+b[ \t]+1028 <__bar_veneer\+0x18>
--[ \t]+100c:[ \t]+d503201f[ \t]+nop
--0+1010 <__bar_veneer>:
-- 1010: 90040010 adrp x16, 8001000 <bar>
-- 1014: 91000210 add x16, x16, #0x0
-- 1018: d61f0200 br x16
-+[ \t]+1008:[ \t]+14000007[ \t]+b[ \t]+1024 <__bar_veneer\+0x18>
-+0+100c <__bar_veneer>:
-+ 100c: 90040010 adrp x16, 8001000 <bar>
-+ 1010: 91000210 add x16, x16, #0x0
-+ 1014: d61f0200 br x16
- ...
-diff -rup binutils.nickc/ld/testsuite/ld-aarch64/farcall-b-none-function.d binutils-2.30/ld/testsuite/ld-aarch64/farcall-b-none-function.d
---- binutils.nickc/ld/testsuite/ld-aarch64/farcall-b-none-function.d 2021-03-25 09:15:09.386957010 +0000
-+++ binutils-2.30/ld/testsuite/ld-aarch64/farcall-b-none-function.d 2021-03-25 10:49:16.060220092 +0000
-@@ -8,15 +8,14 @@
- Disassembly of section .text:
-
- .* <_start>:
-- 1000: 14000004 b 1010 <__bar_veneer>
-+ 1000: 14000003 b 100c <__bar_veneer>
- 1004: d65f03c0 ret
-- 1008: 14000008 b 1028 <__bar_veneer\+0x18>
-- 100c: d503201f nop
-+ 1008: 14000007 b 1024 <__bar_veneer\+0x18>
-
- .* <__bar_veneer>:
-- 1010: 90040010 adrp x16, 8001000 <bar>
-- 1014: 91000210 add x16, x16, #0x0
-- 1018: d61f0200 br x16
-+ 100c: 90040010 adrp x16, 8001000 <bar>
-+ 1010: 91000210 add x16, x16, #0x0
-+ 1014: d61f0200 br x16
- ...
-
- Disassembly of section .foo:
-diff -rup binutils.nickc/ld/testsuite/ld-aarch64/farcall-b-section.d binutils-2.30/ld/testsuite/ld-aarch64/farcall-b-section.d
---- binutils.nickc/ld/testsuite/ld-aarch64/farcall-b-section.d 2021-03-25 09:15:07.885968370 +0000
-+++ binutils-2.30/ld/testsuite/ld-aarch64/farcall-b-section.d 2021-03-25 10:52:05.924566309 +0000
-@@ -8,22 +8,21 @@
- Disassembly of section .text:
-
- .* <_start>:
-- 1000: 14000009 b 1024 <___veneer>
-- 1004: 14000004 b 1014 <___veneer>
-+ 1000: 14000008 b 1020 <___veneer>
-+ 1004: 14000003 b 1010 <___veneer>
- 1008: d65f03c0 ret
-- 100c: 1400000e b 1044 <___veneer\+0x20>
-- 1010: d503201f nop
-+ 100c: 1400000d b 1040 <___veneer\+0x20>
-
- .* <___veneer>:
-- 1014: 90040010 adrp x16, 8001000 <bar>
-- 1018: 91001210 add x16, x16, #0x4
-- 101c: d61f0200 br x16
-- 1020: 00000000 udf #0
-+ 1010: 90040010 adrp x16, 8001000 <bar>
-+ 1014: 91001210 add x16, x16, #0x4
-+ 1018: d61f0200 br x16
-+ 101c: 00000000 udf #0
-
- .* <___veneer>:
-- 1024: 90040010 adrp x16, 8001000 <bar>
-- 1028: 91000210 add x16, x16, #0x0
-- 102c: d61f0200 br x16
-+ 1020: 90040010 adrp x16, 8001000 <bar>
-+ 1024: 91000210 add x16, x16, #0x0
-+ 1028: d61f0200 br x16
- ...
-
- Disassembly of section .foo:
-diff -rup binutils.nickc/ld/testsuite/ld-aarch64/farcall-b.d binutils-2.30/ld/testsuite/ld-aarch64/farcall-b.d
---- binutils.nickc/ld/testsuite/ld-aarch64/farcall-b.d 2021-03-25 09:15:09.112959083 +0000
-+++ binutils-2.30/ld/testsuite/ld-aarch64/farcall-b.d 2021-03-25 10:49:09.608282913 +0000
-@@ -8,14 +8,13 @@
- Disassembly of section .text:
-
- 0+1000 <_start>:
-- +1000: 14000004 b 1010 <__bar_veneer>
-+ +1000: 14000003 b 100c <__bar_veneer>
- +1004: d65f03c0 ret
--[ \t]+1008:[ \t]+14000008[ \t]+b[ \t]+1028 <__bar_veneer\+0x18>
--[ \t]+100c:[ \t]+d503201f[ \t]+nop
--0+1010 <__bar_veneer>:
-- 1010: 90040010 adrp x16, 8001000 <bar>
-- 1014: 91000210 add x16, x16, #0x0
-- 1018: d61f0200 br x16
-+[ \t]+1008:[ \t]+14000007[ \t]+b[ \t]+1024 <__bar_veneer\+0x18>
-+0+100c <__bar_veneer>:
-+ 100c: 90040010 adrp x16, 8001000 <bar>
-+ 1010: 91000210 add x16, x16, #0x0
-+ 1014: d61f0200 br x16
- ...
-
- Disassembly of section .foo:
-diff -rup binutils.nickc/ld/testsuite/ld-aarch64/farcall-back.d binutils-2.30/ld/testsuite/ld-aarch64/farcall-back.d
---- binutils.nickc/ld/testsuite/ld-aarch64/farcall-back.d 2021-03-25 09:15:09.187958516 +0000
-+++ binutils-2.30/ld/testsuite/ld-aarch64/farcall-back.d 2021-03-25 10:47:37.574988061 +0000
-@@ -9,68 +9,66 @@
- Disassembly of section .text:
-
- 0000000000001000 <_start>:
-- 1000: 14000414 b 2050 <__bar1_veneer>
-- 1004: 94000413 bl 2050 <__bar1_veneer>
-- 1008: 14000408 b 2028 <__bar2_veneer>
-- 100c: 94000407 bl 2028 <__bar2_veneer>
-- 1010: 1400040a b 2038 <__bar3_veneer>
-- 1014: 94000409 bl 2038 <__bar3_veneer>
-- 1018: d65f03c0 ret
-+ 1000: 1400041. b 20.. <__bar1_veneer>
-+ 1004: 9400041. bl 20.. <__bar1_veneer>
-+ 1008: 1400040. b 20.. <__bar2_veneer>
-+ 100c: 9400040. bl 20.. <__bar2_veneer>
-+ 1010: 1400040. b 20.. <__bar3_veneer>
-+ 1014: 9400040. bl 20.. <__bar3_veneer>
-+ 1018: d65f03c. ret
- ...
-
- 000000000000201c <_back>:
- 201c: d65f03c0 ret
-
--[ \t]+2020:[ \t]+14000014[ \t]+b[ \t]+2070 <__bar1_veneer\+0x20>
--[ \t]+2024:[ \t]+d503201f[ \t]+nop
--0000000000002028 <__bar2_veneer>:
-- 2028: f07ffff0 adrp x16, 100001000 <bar1\+0x1000>
-- 202c: 91002210 add x16, x16, #0x8
-- 2030: d61f0200 br x16
-- 2034: 00000000 udf #0
--
--0000000000002038 <__bar3_veneer>:
-- 2038: 58000090 ldr x16, 2048 <__bar3_veneer\+0x10>
-- 203c: 10000011 adr x17, 203c <__bar3_veneer\+0x4>
-- 2040: 8b110210 add x16, x16, x17
-- 2044: d61f0200 br x16
-- 2048: ffffffd4 .word 0xffffffd4
-- 204c: 00000000 .word 0x00000000
--
--0000000000002050 <__bar1_veneer>:
-- 2050: d07ffff0 adrp x16, 100000000 <bar1>
-- 2054: 91000210 add x16, x16, #0x0
-- 2058: d61f0200 br x16
-+[ \t]+2020:[ \t]+1400001.[ \t]+b[ \t]+20.. <__bar1_veneer\+0x20>
-+00000000000020.. <__bar2_veneer>:
-+ 20..: f07ffff0 adrp x16, 100001000 <bar1\+0x1000>
-+ 20..: 91002210 add x16, x16, #0x8
-+ 20..: d61f0200 br x16
-+ 20..: 00000000 udf #0
-+
-+00000000000020.. <__bar3_veneer>:
-+ 20..: 58000090 ldr x16, 20.. <__bar3_veneer\+0x10>
-+ 20..: 10000011 adr x17, 20.. <__bar3_veneer\+0x4>
-+ 20..: 8b110210 add x16, x16, x17
-+ 20..: d61f0200 br x16
-+ 20..: ffffffd. .word 0xffffffd.
-+ 20..: 00000000 .word 0x00000000
-+
-+00000000000020.. <__bar1_veneer>:
-+ 20..: d07ffff0 adrp x16, 100000000 <bar1>
-+ 20..: 91000210 add x16, x16, #0x0
-+ 20..: d61f0200 br x16
- ...
-
- Disassembly of section .foo:
-
- 0000000100000000 <bar1>:
- 100000000: d65f03c0 ret
-- 100000004: 14000807 b 100002020 <___start_veneer>
-+ 100000004: 1400080. b 1000020.. <___start_veneer>
- ...
-
- 0000000100001008 <bar2>:
- 100001008: d65f03c0 ret
-- 10000100c: 14000405 b 100002020 <___start_veneer>
-+ 10000100c: 1400040. b 1000020.. <___start_veneer>
- ...
-
- 0000000100002010 <bar3>:
- 100002010: d65f03c0 ret
-- 100002014: 14000009 b 100002038 <___back_veneer>
-+ 100002014: 1400000. b 1000020.. <___back_veneer>
-
--[ \t]+100002018:[ \t]+1400000e[ \t]+b[ \t]+100002050 <___back_veneer\+0x18>
--[ \t]+10000201c:[ \t]+d503201f[ \t]+nop
--0000000100002020 <___start_veneer>:
-- 100002020: 58000090 ldr x16, 100002030 <___start_veneer\+0x10>
-- 100002024: 10000011 adr x17, 100002024 <___start_veneer\+0x4>
-- 100002028: 8b110210 add x16, x16, x17
-- 10000202c: d61f0200 br x16
-- 100002030: ffffefdc .word 0xffffefdc
-- 100002034: fffffffe .word 0xfffffffe
--
--0000000100002038 <___back_veneer>:
-- 100002038: 90800010 adrp x16, 2000 <_start\+0x1000>
-- 10000203c: 91007210 add x16, x16, #0x1c
-- 100002040: d61f0200 br x16
-+[ \t]+100002018:[ \t]+1400000.[ \t]+b[ \t]+1000020.. <___back_veneer\+0x18>
-+00000001000020.. <___start_veneer>:
-+ 1000020..: 580000.. ldr x16, 1000020.. <___start_veneer\+0x10>
-+ 1000020..: 100000.. adr x17, 1000020.. <___start_veneer\+0x4>
-+ 1000020..: 8b110210 add x16, x16, x17
-+ 1000020..: d61f0200 br x16
-+ 1000020..: ffffef.. .word 0xffffef..
-+ 1000020..: fffffffe .word 0xfffffffe
-+
-+00000001000020.. <___back_veneer>:
-+ 1000020..: 90800010 adrp x16, 2000 <_start\+0x1000>
-+ 1000020..: 91007210 add x16, x16, #0x1c
-+ 1000020..: d61f0200 br x16
- ...
-diff -rup binutils.nickc/ld/testsuite/ld-aarch64/farcall-bl-defsym.d binutils-2.30/ld/testsuite/ld-aarch64/farcall-bl-defsym.d
---- binutils.nickc/ld/testsuite/ld-aarch64/farcall-bl-defsym.d 2021-03-25 09:15:09.159958728 +0000
-+++ binutils-2.30/ld/testsuite/ld-aarch64/farcall-bl-defsym.d 2021-03-25 10:48:58.873371476 +0000
-@@ -8,12 +8,11 @@
- Disassembly of section .text:
-
- 0+1000 <_start>:
--[ \t]+1000:[ \t]+94000004[ \t]+bl[ \t]+1010 <__bar_veneer>
--[ \t]+1004:[ \t]+d65f03c0[ \t]+ret
--[ \t]+1008:[ \t]+14000008[ \t]+b[ \t]+1028 <__bar_veneer\+0x18>
--[ \t]+100c:[ \t]+d503201f[ \t]+nop
--0+1010 <__bar_veneer>:
--[ \t]+1010:[ \t]+90040010[ \t]+adrp[ \t]+x16, 8001000 <bar>
--[ \t]+1014:[ \t]+91000210[ \t]+add[ \t]+x16, x16, #0x0
--[ \t]+1018:[ \t]+d61f0200[ \t]+br[ \t]+x16
-+ +1000: 94000003 bl 100c <__bar_veneer>
-+ +1004: d65f03c0 ret
-+[ \t]+1008:[ \t]+14000007[ \t]+b[ \t]+1024 <__bar_veneer\+0x18>
-+0+100c <__bar_veneer>:
-+ 100c: 90040010 adrp x16, 8001000 <bar>
-+ 1010: 91000210 add x16, x16, #0x0
-+ 1014: d61f0200 br x16
- ...
-diff -rup binutils.nickc/ld/testsuite/ld-aarch64/farcall-bl-none-function.d binutils-2.30/ld/testsuite/ld-aarch64/farcall-bl-none-function.d
---- binutils.nickc/ld/testsuite/ld-aarch64/farcall-bl-none-function.d 2021-03-25 09:15:09.135958909 +0000
-+++ binutils-2.30/ld/testsuite/ld-aarch64/farcall-bl-none-function.d 2021-03-25 10:49:21.128170754 +0000
-@@ -8,15 +8,14 @@
- Disassembly of section .text:
-
- .* <_start>:
-- 1000: 94000004 bl 1010 <__bar_veneer>
-+ 1000: 94000003 bl 100c <__bar_veneer>
- 1004: d65f03c0 ret
-- 1008: 14000008 b 1028 <__bar_veneer\+0x18>
-- 100c: d503201f nop
-+ 1008: 14000007 b 1024 <__bar_veneer\+0x18>
-
- .* <__bar_veneer>:
-- 1010: 90040010 adrp x16, 8001000 <bar>
-- 1014: 91000210 add x16, x16, #0x0
-- 1018: d61f0200 br x16
-+ 100c: 90040010 adrp x16, 8001000 <bar>
-+ 1010: 91000210 add x16, x16, #0x0
-+ 1014: d61f0200 br x16
- ...
-
- Disassembly of section .foo:
-diff -rup binutils.nickc/ld/testsuite/ld-aarch64/farcall-bl-section.d binutils-2.30/ld/testsuite/ld-aarch64/farcall-bl-section.d
---- binutils.nickc/ld/testsuite/ld-aarch64/farcall-bl-section.d 2021-03-25 09:15:09.339957365 +0000
-+++ binutils-2.30/ld/testsuite/ld-aarch64/farcall-bl-section.d 2021-03-25 10:52:27.892352440 +0000
-@@ -8,22 +8,21 @@
- Disassembly of section .text:
-
- .* <_start>:
-- 1000: 94000009 bl 1024 <___veneer>
-- 1004: 94000004 bl 1014 <___veneer>
-+ 1000: 94000008 bl 1020 <___veneer>
-+ 1004: 94000003 bl 1010 <___veneer>
- 1008: d65f03c0 ret
-- 100c: 1400000e b 1044 <___veneer\+0x20>
-- 1010: d503201f nop
-+ 100c: 1400000d b 1040 <___veneer\+0x20>
-
- .* <___veneer>:
-- 1014: 90040010 adrp x16, 8001000 <bar>
-- 1018: 91001210 add x16, x16, #0x4
-- 101c: d61f0200 br x16
-- 1020: 00000000 udf #0
-+ 1010: 90040010 adrp x16, 8001000 <bar>
-+ 1014: 91001210 add x16, x16, #0x4
-+ 1018: d61f0200 br x16
-+ 101c: 00000000 udf #0
-
- .* <___veneer>:
-- 1024: 90040010 adrp x16, 8001000 <bar>
-- 1028: 91000210 add x16, x16, #0x0
-- 102c: d61f0200 br x16
-+ 1020: 90040010 adrp x16, 8001000 <bar>
-+ 1024: 91000210 add x16, x16, #0x0
-+ 1028: d61f0200 br x16
- ...
-
- Disassembly of section .foo:
-diff -rup binutils.nickc/ld/testsuite/ld-aarch64/farcall-bl.d binutils-2.30/ld/testsuite/ld-aarch64/farcall-bl.d
---- binutils.nickc/ld/testsuite/ld-aarch64/farcall-bl.d 2021-03-25 09:15:09.404956874 +0000
-+++ binutils-2.30/ld/testsuite/ld-aarch64/farcall-bl.d 2021-03-25 10:49:05.522321050 +0000
-@@ -8,14 +8,13 @@
- Disassembly of section .text:
-
- 0+1000 <_start>:
--[ \t]+1000:[ \t]+94000004[ \t]+ bl[ \t]+1010 <__bar_veneer>
--[ \t]+1004:[ \t]+d65f03c0[ \t]+ret
--[ \t]+1008:[ \t]+14000008[ \t]+b[ \t]+1028 <__bar_veneer\+0x18>
--[ \t]+100c:[ \t]+d503201f[ \t]+nop
--0+1010 <__bar_veneer>:
--[ \t]+1010:[ \t]+90040010[ \t]+adrp[ \t]+x16, 8001000 <bar>
--[ \t]+1014:[ \t]+91000210[ \t]+add[ \t]+x16, x16, #0x0
--[ \t]+1018:[ \t]+d61f0200[ \t]+br[ \t]+x16
-+ +1000: 94000003 bl 100c <__bar_veneer>
-+ +1004: d65f03c0 ret
-+[ \t]+1008:[ \t]+14000007[ \t]+b[ \t]+1024 <__bar_veneer\+0x18>
-+0+100c <__bar_veneer>:
-+ 100c: 90040010 adrp x16, 8001000 <bar>
-+ 1010: 91000210 add x16, x16, #0x0
-+ 1014: d61f0200 br x16
- ...
-
- Disassembly of section .foo:
---- binutils.nickc/ld/testsuite/ld-elf/shared.exp 2021-03-25 09:15:15.881907854 +0000
-+++ binutils-2.30/ld/testsuite/ld-elf/shared.exp 2021-03-25 11:56:11.928122725 +0000
-@@ -849,12 +849,6 @@ set build_cxx_tests {
- # "tmpdir/libdl3b.so" ""
- # {dl3main.cc} "dl3b" "dl3b.out" "" "c++"}
- set run_cxx_tests {
-- {"Run with libdl3a.so"
-- "-Wl,--no-as-needed tmpdir/libdl3a.so" ""
-- {dl3main.cc} "dl3a" "dl3a.out" "" "c++"}
-- {"Run with libdl3c.so"
-- "-Wl,--no-as-needed tmpdir/libdl3c.so" ""
-- {dl3main.cc} "dl3c" "dl3a.out" "" "c++"}
- {"Run with libnew1a.so"
- "-Wl,--no-as-needed tmpdir/libnew1a.so" ""
- {dl5.cc} "dl5a" "dl5.out" "-ansi" "c++"}
diff --git a/SPECS/binutils.spec b/SPECS/binutils.spec
index cdf7155..1a4924e 100644
--- a/SPECS/binutils.spec
+++ b/SPECS/binutils.spec
@@ -43,7 +43,7 @@
Summary: A GNU collection of binary utilities
Name: binutils%{?name_cross}%{?_with_debug:-debug}
Version: 2.30
-Release: 99%{?dist}
+Release: 101%{?dist}
License: GPLv3+
URL: https://sourceware.org/binutils
@@ -570,9 +570,10 @@ Patch86: binutils-CVE-2021-20197.patch
# Lifetime: Fixed in 2.35
Patch87: binutils-mark-all-weak-aliases.patch
-# Purpose: Enable support for ARMv8.6 ISA.
+# Purpose: Fix excessive memory consumption when attempting to parse corrupt
+# DWARF debug information.
# Lifetime: Fixed in 2.36
-Patch88: binutils-aarch64-armv8.6-support.patch
+Patch88: binutils-CVE-2021-3487.patch
#----------------------------------------------------------------------------
@@ -699,6 +700,14 @@ dynamic libraries.
Developers starting new projects are strongly encouraged to consider
using libelf instead of BFD.
+# BZ 1924068. Since applications that use the BFD library are
+# required to link against the static version, ensure that it retains
+# its debug informnation.
+# FIXME: Yes - this is being done twice. I have no idea why this
+# second invocation is necessary but if both are not present the
+# static archives will be stripped.
+%undefine __brp_strip_static_archive
+
#----------------------------------------------------------------------------
%prep
@@ -1240,6 +1249,13 @@ exit 0
#----------------------------------------------------------------------------
%changelog
+* Wed Apr 14 2021 Nick Clifton <nickc@redhat.com> - 2.30-101
+- Fix excessive memory consumption in the BFD librart when parsing corrupt DWARF information. (#1947134)
+
+* Fri Apr 09 2021 Nick Clifton <nickc@redhat.com> - 2.30-100
+- Do not strip the static BFD library. (For real this time). (#1924068)
+- Remove support for ARM v8.6 ISA. (#1875912)
+
* Thu Mar 25 2021 Nick Clifton <nickc@redhat.com> - 2.30-99
- Fix bug in previous patch to enable support for ARM v8.6 ISA. (#1875912)