diff --git a/.binutils.metadata b/.binutils.metadata
new file mode 100644
index 0000000..56f721c
--- /dev/null
+++ b/.binutils.metadata
@@ -0,0 +1,2 @@
+6e472ddae565a2b1447e6f2393809bb8799982cf SOURCES/binutils-2.27.tar.bz2
+d3e5c9fc829ed40648110da6fe46c2fb1ed8aadb SOURCES/standards.info.gz
diff --git a/.gitignore b/.gitignore
new file mode 100644
index 0000000..69ceadb
--- /dev/null
+++ b/.gitignore
@@ -0,0 +1,2 @@
+SOURCES/binutils-2.27.tar.bz2
+SOURCES/standards.info.gz
diff --git a/SOURCES/binutils-2.19.50.0.1-output-format.sed b/SOURCES/binutils-2.19.50.0.1-output-format.sed
new file mode 100644
index 0000000..fd770cb
--- /dev/null
+++ b/SOURCES/binutils-2.19.50.0.1-output-format.sed
@@ -0,0 +1,38 @@
+# Generate OUTPUT_FORMAT line for .so files from the system linker output.
+# Imported from glibc/Makerules.
+
+/ld.*[ ]-E[BL]/b f
+/collect.*[ ]-E[BL]/b f
+/OUTPUT_FORMAT[^)]*$/{N
+s/\n[ ]*/ /
+}
+t o
+: o
+s/^.*OUTPUT_FORMAT(\([^,]*\), \1, \1).*$/OUTPUT_FORMAT(\1)/
+t q
+s/^.*OUTPUT_FORMAT(\([^,]*\), \([^,]*\), \([^,]*\)).*$/\1,\2,\3/
+t s
+s/^.*OUTPUT_FORMAT(\([^,)]*\).*$)/OUTPUT_FORMAT(\1)/
+t q
+d
+: s
+s/"//g
+G
+s/\n//
+s/^\([^,]*\),\([^,]*\),\([^,]*\),B/OUTPUT_FORMAT(\2)/p
+s/^\([^,]*\),\([^,]*\),\([^,]*\),L/OUTPUT_FORMAT(\3)/p
+s/^\([^,]*\),\([^,]*\),\([^,]*\)/OUTPUT_FORMAT(\1)/p
+/,/s|^|*** BUG in libc/scripts/output-format.sed *** |p
+q
+: q
+s/"//g
+p
+q
+: f
+s/^.*[ ]-E\([BL]\)[ ].*$/,\1/
+t h
+s/^.*[ ]-E\([BL]\)$/,\1/
+t h
+d
+: h
+h
diff --git a/SOURCES/binutils-2.20.51.0.10-ppc64-pie.patch b/SOURCES/binutils-2.20.51.0.10-ppc64-pie.patch
new file mode 100644
index 0000000..8862d18
--- /dev/null
+++ b/SOURCES/binutils-2.20.51.0.10-ppc64-pie.patch
@@ -0,0 +1,14 @@
+*** ../binutils-2.23.51.0.2.orig/bfd/elf64-ppc.c 2012-09-11 12:13:00.637448573 +0100
+--- bfd/elf64-ppc.c 2012-09-11 12:13:17.922449052 +0100
+*************** ppc64_elf_relocate_section (bfd *output_
+*** 13523,13528 ****
+--- 13523,13531 ----
+ {
+ BFD_ASSERT (h->elf.dynindx != -1);
+ outrel.r_info = ELF64_R_INFO (h->elf.dynindx, r_type);
++ if (h->elf.dynindx == -1
++ && h->elf.root.type == bfd_link_hash_undefweak)
++ memset (&outrel, 0, sizeof outrel);
+ }
+ else
+ {
diff --git a/SOURCES/binutils-2.20.51.0.10-sec-merge-emit.patch b/SOURCES/binutils-2.20.51.0.10-sec-merge-emit.patch
new file mode 100644
index 0000000..238beb3
--- /dev/null
+++ b/SOURCES/binutils-2.20.51.0.10-sec-merge-emit.patch
@@ -0,0 +1,11 @@
+--- binutils-2.26.orig/bfd/merge.c 2016-01-25 10:11:33.505289018 +0000
++++ binutils-2.26/bfd/merge.c 2016-01-25 10:19:56.961381656 +0000
+@@ -334,7 +334,7 @@ sec_merge_emit (bfd *abfd, struct sec_me
+
+ /* Trailing alignment needed? */
+ off = sec->size - off;
+- if (off != 0)
++ if (off != 0 && alignment_power)
+ {
+ if (contents)
+ memcpy (contents + offset, pad, off);
diff --git a/SOURCES/binutils-2.20.51.0.2-libtool-lib64.patch b/SOURCES/binutils-2.20.51.0.2-libtool-lib64.patch
new file mode 100644
index 0000000..0c61a11
--- /dev/null
+++ b/SOURCES/binutils-2.20.51.0.2-libtool-lib64.patch
@@ -0,0 +1,302 @@
+diff -rcp ../binutils-2.20.51.0.7.original/bfd/configure ./bfd/configure
+*** ../binutils-2.20.51.0.7.original/bfd/configure 2010-04-08 14:53:48.000000000 +0100
+--- ./bfd/configure 2010-04-08 14:56:50.000000000 +0100
+*************** fi
+*** 10762,10771 ****
+ # before this can be enabled.
+ hardcode_into_libs=yes
+
+ # Append ld.so.conf contents to the search path
+ if test -f /etc/ld.so.conf; then
+ lt_ld_extra=`awk '/^include / { system(sprintf("cd /etc; cat %s 2>/dev/null", \$2)); skip = 1; } { if (!skip) print \$0; skip = 0; }' < /etc/ld.so.conf | $SED -e 's/#.*//;/^[ ]*hwcap[ ]/d;s/[:, ]/ /g;s/=[^=]*$//;s/=[^= ]* / /g;s/"//g;/^$/d' | tr '\n' ' '`
+! sys_lib_dlsearch_path_spec="/lib /usr/lib $lt_ld_extra"
+ fi
+
+ # We used to test for /lib/ld.so.1 and disable shared libraries on
+--- 10762,10795 ----
+ # before this can be enabled.
+ hardcode_into_libs=yes
+
++ # find out which ABI we are using
++ libsuff=
++ case "$host_cpu" in
++ x86_64*|s390*|powerpc*|ppc*|sparc*)
++ echo 'int i;' > conftest.$ac_ext
++ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
++ (eval $ac_compile) 2>&5
++ ac_status=$?
++ echo "$as_me:$LINENO: \$? = $ac_status" >&5
++ (exit $ac_status); }; then
++ case `/usr/bin/file conftest.$ac_objext` in
++ *64-bit*)
++ libsuff=64
++ if test x"$sys_lib_search_path_spec" = x"/lib /usr/lib /usr/local/lib"; then
++ sys_lib_search_path_spec="/lib${libsuff} /usr/lib${libsuff} /usr/local/lib${libsuff}"
++ fi
++ sys_lib_dlsearch_path_spec="/lib${libsuff} /usr/lib${libsuff}"
++ ;;
++ esac
++ fi
++ rm -rf conftest*
++ ;;
++ esac
++
+ # Append ld.so.conf contents to the search path
+ if test -f /etc/ld.so.conf; then
+ lt_ld_extra=`awk '/^include / { system(sprintf("cd /etc; cat %s 2>/dev/null", \$2)); skip = 1; } { if (!skip) print \$0; skip = 0; }' < /etc/ld.so.conf | $SED -e 's/#.*//;/^[ ]*hwcap[ ]/d;s/[:, ]/ /g;s/=[^=]*$//;s/=[^= ]* / /g;s/"//g;/^$/d' | tr '\n' ' '`
+! sys_lib_dlsearch_path_spec="/lib${libsuff} /usr/lib${libsuff} $lt_ld_extra"
+ fi
+
+ # We used to test for /lib/ld.so.1 and disable shared libraries on
+diff -rcp ../binutils-2.20.51.0.7.original/binutils/configure ./binutils/configure
+*** ../binutils-2.20.51.0.7.original/binutils/configure 2010-04-08 14:53:45.000000000 +0100
+--- ./binutils/configure 2010-04-08 14:56:21.000000000 +0100
+*************** fi
+*** 10560,10569 ****
+ # before this can be enabled.
+ hardcode_into_libs=yes
+
+ # Append ld.so.conf contents to the search path
+ if test -f /etc/ld.so.conf; then
+ lt_ld_extra=`awk '/^include / { system(sprintf("cd /etc; cat %s 2>/dev/null", \$2)); skip = 1; } { if (!skip) print \$0; skip = 0; }' < /etc/ld.so.conf | $SED -e 's/#.*//;/^[ ]*hwcap[ ]/d;s/[:, ]/ /g;s/=[^=]*$//;s/=[^= ]* / /g;s/"//g;/^$/d' | tr '\n' ' '`
+! sys_lib_dlsearch_path_spec="/lib /usr/lib $lt_ld_extra"
+ fi
+
+ # We used to test for /lib/ld.so.1 and disable shared libraries on
+--- 10560,10593 ----
+ # before this can be enabled.
+ hardcode_into_libs=yes
+
++ # find out which ABI we are using
++ libsuff=
++ case "$host_cpu" in
++ x86_64*|s390*|powerpc*|ppc*|sparc*)
++ echo 'int i;' > conftest.$ac_ext
++ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
++ (eval $ac_compile) 2>&5
++ ac_status=$?
++ echo "$as_me:$LINENO: \$? = $ac_status" >&5
++ (exit $ac_status); }; then
++ case `/usr/bin/file conftest.$ac_objext` in
++ *64-bit*)
++ libsuff=64
++ if test x"$sys_lib_search_path_spec" = x"/lib /usr/lib /usr/local/lib"; then
++ sys_lib_search_path_spec="/lib${libsuff} /usr/lib${libsuff} /usr/local/lib${libsuff}"
++ fi
++ sys_lib_dlsearch_path_spec="/lib${libsuff} /usr/lib${libsuff}"
++ ;;
++ esac
++ fi
++ rm -rf conftest*
++ ;;
++ esac
++
+ # Append ld.so.conf contents to the search path
+ if test -f /etc/ld.so.conf; then
+ lt_ld_extra=`awk '/^include / { system(sprintf("cd /etc; cat %s 2>/dev/null", \$2)); skip = 1; } { if (!skip) print \$0; skip = 0; }' < /etc/ld.so.conf | $SED -e 's/#.*//;/^[ ]*hwcap[ ]/d;s/[:, ]/ /g;s/=[^=]*$//;s/=[^= ]* / /g;s/"//g;/^$/d' | tr '\n' ' '`
+! sys_lib_dlsearch_path_spec="/lib${libsuff} /usr/lib${libsuff} $lt_ld_extra"
+ fi
+
+ # We used to test for /lib/ld.so.1 and disable shared libraries on
+diff -rcp ../binutils-2.20.51.0.7.original/gas/configure ./gas/configure
+*** ../binutils-2.20.51.0.7.original/gas/configure 2010-04-08 14:53:47.000000000 +0100
+--- ./gas/configure 2010-04-08 14:57:24.000000000 +0100
+*************** fi
+*** 10547,10556 ****
+ # before this can be enabled.
+ hardcode_into_libs=yes
+
+ # Append ld.so.conf contents to the search path
+ if test -f /etc/ld.so.conf; then
+ lt_ld_extra=`awk '/^include / { system(sprintf("cd /etc; cat %s 2>/dev/null", \$2)); skip = 1; } { if (!skip) print \$0; skip = 0; }' < /etc/ld.so.conf | $SED -e 's/#.*//;/^[ ]*hwcap[ ]/d;s/[:, ]/ /g;s/=[^=]*$//;s/=[^= ]* / /g;s/"//g;/^$/d' | tr '\n' ' '`
+! sys_lib_dlsearch_path_spec="/lib /usr/lib $lt_ld_extra"
+ fi
+
+ # We used to test for /lib/ld.so.1 and disable shared libraries on
+--- 10547,10580 ----
+ # before this can be enabled.
+ hardcode_into_libs=yes
+
++ # find out which ABI we are using
++ libsuff=
++ case "$host_cpu" in
++ x86_64*|s390*|powerpc*|ppc*|sparc*)
++ echo 'int i;' > conftest.$ac_ext
++ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
++ (eval $ac_compile) 2>&5
++ ac_status=$?
++ echo "$as_me:$LINENO: \$? = $ac_status" >&5
++ (exit $ac_status); }; then
++ case `/usr/bin/file conftest.$ac_objext` in
++ *64-bit*)
++ libsuff=64
++ if test x"$sys_lib_search_path_spec" = x"/lib /usr/lib /usr/local/lib"; then
++ sys_lib_search_path_spec="/lib${libsuff} /usr/lib${libsuff} /usr/local/lib${libsuff}"
++ fi
++ sys_lib_dlsearch_path_spec="/lib${libsuff} /usr/lib${libsuff}"
++ ;;
++ esac
++ fi
++ rm -rf conftest*
++ ;;
++ esac
++
+ # Append ld.so.conf contents to the search path
+ if test -f /etc/ld.so.conf; then
+ lt_ld_extra=`awk '/^include / { system(sprintf("cd /etc; cat %s 2>/dev/null", \$2)); skip = 1; } { if (!skip) print \$0; skip = 0; }' < /etc/ld.so.conf | $SED -e 's/#.*//;/^[ ]*hwcap[ ]/d;s/[:, ]/ /g;s/=[^=]*$//;s/=[^= ]* / /g;s/"//g;/^$/d' | tr '\n' ' '`
+! sys_lib_dlsearch_path_spec="/lib${libsuff} /usr/lib${libsuff} $lt_ld_extra"
+ fi
+
+ # We used to test for /lib/ld.so.1 and disable shared libraries on
+diff -rcp ../binutils-2.20.51.0.7.original/gprof/configure ./gprof/configure
+*** ../binutils-2.20.51.0.7.original/gprof/configure 2010-04-08 14:53:45.000000000 +0100
+--- ./gprof/configure 2010-04-08 14:57:50.000000000 +0100
+*************** fi
+*** 10485,10494 ****
+ # before this can be enabled.
+ hardcode_into_libs=yes
+
+ # Append ld.so.conf contents to the search path
+ if test -f /etc/ld.so.conf; then
+ lt_ld_extra=`awk '/^include / { system(sprintf("cd /etc; cat %s 2>/dev/null", \$2)); skip = 1; } { if (!skip) print \$0; skip = 0; }' < /etc/ld.so.conf | $SED -e 's/#.*//;/^[ ]*hwcap[ ]/d;s/[:, ]/ /g;s/=[^=]*$//;s/=[^= ]* / /g;s/"//g;/^$/d' | tr '\n' ' '`
+! sys_lib_dlsearch_path_spec="/lib /usr/lib $lt_ld_extra"
+ fi
+
+ # We used to test for /lib/ld.so.1 and disable shared libraries on
+--- 10485,10518 ----
+ # before this can be enabled.
+ hardcode_into_libs=yes
+
++ # find out which ABI we are using
++ libsuff=
++ case "$host_cpu" in
++ x86_64*|s390*|powerpc*|ppc*|sparc*)
++ echo 'int i;' > conftest.$ac_ext
++ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
++ (eval $ac_compile) 2>&5
++ ac_status=$?
++ echo "$as_me:$LINENO: \$? = $ac_status" >&5
++ (exit $ac_status); }; then
++ case `/usr/bin/file conftest.$ac_objext` in
++ *64-bit*)
++ libsuff=64
++ if test x"$sys_lib_search_path_spec" = x"/lib /usr/lib /usr/local/lib"; then
++ sys_lib_search_path_spec="/lib${libsuff} /usr/lib${libsuff} /usr/local/lib${libsuff}"
++ fi
++ sys_lib_dlsearch_path_spec="/lib${libsuff} /usr/lib${libsuff}"
++ ;;
++ esac
++ fi
++ rm -rf conftest*
++ ;;
++ esac
++
+ # Append ld.so.conf contents to the search path
+ if test -f /etc/ld.so.conf; then
+ lt_ld_extra=`awk '/^include / { system(sprintf("cd /etc; cat %s 2>/dev/null", \$2)); skip = 1; } { if (!skip) print \$0; skip = 0; }' < /etc/ld.so.conf | $SED -e 's/#.*//;/^[ ]*hwcap[ ]/d;s/[:, ]/ /g;s/=[^=]*$//;s/=[^= ]* / /g;s/"//g;/^$/d' | tr '\n' ' '`
+! sys_lib_dlsearch_path_spec="/lib${libsuff} /usr/lib${libsuff} $lt_ld_extra"
+ fi
+
+ # We used to test for /lib/ld.so.1 and disable shared libraries on
+diff -rcp ../binutils-2.20.51.0.7.original/ld/configure ./ld/configure
+*** ../binutils-2.20.51.0.7.original/ld/configure 2010-04-08 14:53:44.000000000 +0100
+--- ./ld/configure 2010-04-08 14:58:21.000000000 +0100
+*************** fi
+*** 10966,10975 ****
+ # before this can be enabled.
+ hardcode_into_libs=yes
+
+ # Append ld.so.conf contents to the search path
+ if test -f /etc/ld.so.conf; then
+ lt_ld_extra=`awk '/^include / { system(sprintf("cd /etc; cat %s 2>/dev/null", \$2)); skip = 1; } { if (!skip) print \$0; skip = 0; }' < /etc/ld.so.conf | $SED -e 's/#.*//;/^[ ]*hwcap[ ]/d;s/[:, ]/ /g;s/=[^=]*$//;s/=[^= ]* / /g;s/"//g;/^$/d' | tr '\n' ' '`
+! sys_lib_dlsearch_path_spec="/lib /usr/lib $lt_ld_extra"
+ fi
+
+ # We used to test for /lib/ld.so.1 and disable shared libraries on
+--- 10966,10999 ----
+ # before this can be enabled.
+ hardcode_into_libs=yes
+
++ # find out which ABI we are using
++ libsuff=
++ case "$host_cpu" in
++ x86_64*|s390*|powerpc*|ppc*|sparc*)
++ echo 'int i;' > conftest.$ac_ext
++ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
++ (eval $ac_compile) 2>&5
++ ac_status=$?
++ echo "$as_me:$LINENO: \$? = $ac_status" >&5
++ (exit $ac_status); }; then
++ case `/usr/bin/file conftest.$ac_objext` in
++ *64-bit*)
++ libsuff=64
++ if test x"$sys_lib_search_path_spec" = x"/lib /usr/lib /usr/local/lib"; then
++ sys_lib_search_path_spec="/lib${libsuff} /usr/lib${libsuff} /usr/local/lib${libsuff}"
++ fi
++ sys_lib_dlsearch_path_spec="/lib${libsuff} /usr/lib${libsuff}"
++ ;;
++ esac
++ fi
++ rm -rf conftest*
++ ;;
++ esac
++
+ # Append ld.so.conf contents to the search path
+ if test -f /etc/ld.so.conf; then
+ lt_ld_extra=`awk '/^include / { system(sprintf("cd /etc; cat %s 2>/dev/null", \$2)); skip = 1; } { if (!skip) print \$0; skip = 0; }' < /etc/ld.so.conf | $SED -e 's/#.*//;/^[ ]*hwcap[ ]/d;s/[:, ]/ /g;s/=[^=]*$//;s/=[^= ]* / /g;s/"//g;/^$/d' | tr '\n' ' '`
+! sys_lib_dlsearch_path_spec="/lib${libsuff} /usr/lib${libsuff} $lt_ld_extra"
+ fi
+
+ # We used to test for /lib/ld.so.1 and disable shared libraries on
+Only in .: .#libtool.m4
+Only in .: #libtool.m4#
+diff -rcp ../binutils-2.20.51.0.7.original/opcodes/configure ./opcodes/configure
+*** ../binutils-2.20.51.0.7.original/opcodes/configure 2010-04-08 14:53:45.000000000 +0100
+--- ./opcodes/configure 2010-04-08 14:59:10.000000000 +0100
+*************** fi
+*** 10496,10505 ****
+ # before this can be enabled.
+ hardcode_into_libs=yes
+
+ # Append ld.so.conf contents to the search path
+ if test -f /etc/ld.so.conf; then
+ lt_ld_extra=`awk '/^include / { system(sprintf("cd /etc; cat %s 2>/dev/null", \$2)); skip = 1; } { if (!skip) print \$0; skip = 0; }' < /etc/ld.so.conf | $SED -e 's/#.*//;/^[ ]*hwcap[ ]/d;s/[:, ]/ /g;s/=[^=]*$//;s/=[^= ]* / /g;s/"//g;/^$/d' | tr '\n' ' '`
+! sys_lib_dlsearch_path_spec="/lib /usr/lib $lt_ld_extra"
+ fi
+
+ # We used to test for /lib/ld.so.1 and disable shared libraries on
+--- 10496,10529 ----
+ # before this can be enabled.
+ hardcode_into_libs=yes
+
++ # find out which ABI we are using
++ libsuff=
++ case "$host_cpu" in
++ x86_64*|s390*|powerpc*|ppc*|sparc*)
++ echo 'int i;' > conftest.$ac_ext
++ if { (eval echo "$as_me:$LINENO: \"$ac_compile\"") >&5
++ (eval $ac_compile) 2>&5
++ ac_status=$?
++ echo "$as_me:$LINENO: \$? = $ac_status" >&5
++ (exit $ac_status); }; then
++ case `/usr/bin/file conftest.$ac_objext` in
++ *64-bit*)
++ libsuff=64
++ if test x"$sys_lib_search_path_spec" = x"/lib /usr/lib /usr/local/lib"; then
++ sys_lib_search_path_spec="/lib${libsuff} /usr/lib${libsuff} /usr/local/lib${libsuff}"
++ fi
++ sys_lib_dlsearch_path_spec="/lib${libsuff} /usr/lib${libsuff}"
++ ;;
++ esac
++ fi
++ rm -rf conftest*
++ ;;
++ esac
++
+ # Append ld.so.conf contents to the search path
+ if test -f /etc/ld.so.conf; then
+ lt_ld_extra=`awk '/^include / { system(sprintf("cd /etc; cat %s 2>/dev/null", \$2)); skip = 1; } { if (!skip) print \$0; skip = 0; }' < /etc/ld.so.conf | $SED -e 's/#.*//;/^[ ]*hwcap[ ]/d;s/[:, ]/ /g;s/=[^=]*$//;s/=[^= ]* / /g;s/"//g;/^$/d' | tr '\n' ' '`
+! sys_lib_dlsearch_path_spec="/lib${libsuff} /usr/lib${libsuff} $lt_ld_extra"
+ fi
+
+ # We used to test for /lib/ld.so.1 and disable shared libraries on
diff --git a/SOURCES/binutils-2.22.52.0.1-export-demangle.h.patch b/SOURCES/binutils-2.22.52.0.1-export-demangle.h.patch
new file mode 100644
index 0000000..84f82cd
--- /dev/null
+++ b/SOURCES/binutils-2.22.52.0.1-export-demangle.h.patch
@@ -0,0 +1,21 @@
+--- a/bfd/Makefile.am 2012-03-06 14:00:33.229957572 +0000
++++ b/bfd/Makefile.am 2012-04-27 16:46:05.410974817 +0100
+@@ -18,7 +18,7 @@
+ bfdlibdir = @bfdlibdir@
+ bfdincludedir = @bfdincludedir@
+ bfdlib_LTLIBRARIES = libbfd.la
+-bfdinclude_HEADERS = $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/bfdlink.h
++bfdinclude_HEADERS = $(BFD_H) $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h $(INCDIR)/bfdlink.h $(INCDIR)/demangle.h
+ else !INSTALL_LIBBFD
+ # Empty these so that the respective installation directories will not be created.
+ bfdlibdir =
+--- binutils-2.26.orig/bfd/Makefile.in 2016-01-25 10:23:35.054721634 +0000
++++ binutils-2.26/bfd/Makefile.in 2016-01-25 10:25:59.292607840 +0000
+@@ -350,6 +350,7 @@ libbfd_la_LDFLAGS = $(am__append_1) -rel
+ @INSTALL_LIBBFD_FALSE@bfdinclude_HEADERS = $(am__append_2)
+ @INSTALL_LIBBFD_TRUE@bfdinclude_HEADERS = $(BFD_H) \
+ @INSTALL_LIBBFD_TRUE@ $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h \
++@INSTALL_LIBBFD_TRUE@ $(INCDIR)/demangle.h \
+ @INSTALL_LIBBFD_TRUE@ $(INCDIR)/bfdlink.h $(am__append_2)
+ @INSTALL_LIBBFD_FALSE@rpath_bfdlibdir = @bfdlibdir@
+ @INSTALL_LIBBFD_FALSE@noinst_LTLIBRARIES = libbfd.la
diff --git a/SOURCES/binutils-2.22.52.0.4-no-config-h-check.patch b/SOURCES/binutils-2.22.52.0.4-no-config-h-check.patch
new file mode 100644
index 0000000..2fc32e3
--- /dev/null
+++ b/SOURCES/binutils-2.22.52.0.4-no-config-h-check.patch
@@ -0,0 +1,32 @@
+*** ../binutils-2.22.52.0.4.orig/bfd/bfd-in.h 2012-08-02 10:56:34.561769686 +0100
+--- bfd/bfd-in.h 2012-08-02 11:13:27.134797755 +0100
+***************
+*** 25,35 ****
+ #ifndef __BFD_H_SEEN__
+ #define __BFD_H_SEEN__
+
+- /* PR 14072: Ensure that config.h is included first. */
+- #if !defined PACKAGE && !defined PACKAGE_VERSION
+- #error config.h must be included before this header
+- #endif
+-
+ #ifdef __cplusplus
+ extern "C" {
+ #endif
+--- 25,30 ----
+*** ../binutils-2.22.52.0.4.orig/bfd/bfd-in2.h 2012-08-02 10:56:34.349769680 +0100
+--- bfd/bfd-in2.h 2012-08-02 11:13:40.015798113 +0100
+***************
+*** 32,42 ****
+ #ifndef __BFD_H_SEEN__
+ #define __BFD_H_SEEN__
+
+- /* PR 14072: Ensure that config.h is included first. */
+- #if !defined PACKAGE && !defined PACKAGE_VERSION
+- #error config.h must be included before this header
+- #endif
+-
+ #ifdef __cplusplus
+ extern "C" {
+ #endif
+--- 32,37 ----
diff --git a/SOURCES/binutils-2.23.52.0.1-find-separate-debug-file.patch b/SOURCES/binutils-2.23.52.0.1-find-separate-debug-file.patch
new file mode 100644
index 0000000..944f4fd
--- /dev/null
+++ b/SOURCES/binutils-2.23.52.0.1-find-separate-debug-file.patch
@@ -0,0 +1,38 @@
+--- a/bfd/opncls.c 2013-03-14 11:25:30.338306122 +0000
++++ b/bfd/opncls.c 2013-03-14 12:20:21.686397360 +0000
+@@ -1297,6 +1297,8 @@
+ bfd_malloc (strlen (debug_file_directory) + 1
+ + (canon_dirlen > dirlen ? canon_dirlen : dirlen)
+ + strlen (".debug/")
++#define FEDORA_LIB_DEBUG_DIR "/usr/lib/debug/"
++ + strlen (FEDORA_LIB_DEBUG_DIR) + strlen ("usr/")
+ + strlen (base)
+ + 1);
+ if (debugfile == NULL)
+@@ -1332,6 +1334,26 @@
+ if (check_func (debugfile, crc32))
+ goto found;
+
++ /* Then try in the global debug dir for Fedora libraries. */
++ sprintf (debugfile, "%s%s%s", FEDORA_LIB_DEBUG_DIR, dir, base);
++ if (separate_debug_file_exists (debugfile, crc32))
++ {
++ free (base);
++ free (dir);
++ free (canon_dir);
++ return debugfile;
++ }
++
++ /* Then try in the usr subdirectory of the global debug dir for Fedora libraries. */
++ sprintf (debugfile, "%s/usr%s%s", FEDORA_LIB_DEBUG_DIR, dir, base);
++ if (separate_debug_file_exists (debugfile, crc32))
++ {
++ free (base);
++ free (dir);
++ free (canon_dir);
++ return debugfile;
++ }
++
+ /* Then try in the global debugfile directory. */
+ strcpy (debugfile, debug_file_directory);
+ dirlen = strlen (debug_file_directory) - 1;
diff --git a/SOURCES/binutils-2.25-set-long-long.patch b/SOURCES/binutils-2.25-set-long-long.patch
new file mode 100644
index 0000000..1ea7418
--- /dev/null
+++ b/SOURCES/binutils-2.25-set-long-long.patch
@@ -0,0 +1,38 @@
+diff -up binutils-2.25.orig/bfd/configure.ac binutils-2.25/bfd/configure.ac
+--- binutils-2.25.orig/bfd/configure.ac 2014-12-24 10:34:45.590491143 +0000
++++ binutils-2.25/bfd/configure.ac 2014-12-24 10:36:12.997981992 +0000
+@@ -183,11 +183,13 @@ if test "x${ac_cv_sizeof_long}" = "x8";
+ BFD_HOST_64BIT_LONG=1
+ test -n "${HOST_64BIT_TYPE}" || HOST_64BIT_TYPE="long"
+ test -n "${HOST_U_64BIT_TYPE}" || HOST_U_64BIT_TYPE="unsigned long"
+-elif test "x${ac_cv_sizeof_long_long}" = "x8"; then
++fi
++if test "x${ac_cv_sizeof_long_long}" = "x8"; then
+ BFD_HOST_64BIT_LONG_LONG=1
+ test -n "${HOST_64BIT_TYPE}" || HOST_64BIT_TYPE="long long"
+ test -n "${HOST_U_64BIT_TYPE}" || HOST_U_64BIT_TYPE="unsigned long long"
+- if test "x${ac_cv_sizeof_void_p}" = "x8"; then
++ if test "x${ac_cv_sizeof_void_p}" = "x8" \
++ -a "x${ac_cv_sizeof_long}" != "x8"; then
+ BFD_HOSTPTR_T="unsigned long long"
+ fi
+ fi
+diff -up ../binutils-2.20.51.0.7.original/bfd/configure ./bfd/configure
+--- a/bfd/configure 2010-04-08 15:23:58.000000000 +0100
++++ b/bfd/configure 2010-04-08 15:24:06.000000000 +0100
+@@ -12819,11 +12819,13 @@
+ BFD_HOST_64BIT_LONG=1
+ test -n "${HOST_64BIT_TYPE}" || HOST_64BIT_TYPE="long"
+ test -n "${HOST_U_64BIT_TYPE}" || HOST_U_64BIT_TYPE="unsigned long"
+-elif test "x${ac_cv_sizeof_long_long}" = "x8"; then
++fi
++if test "x${ac_cv_sizeof_long_long}" = "x8"; then
+ BFD_HOST_64BIT_LONG_LONG=1
+ test -n "${HOST_64BIT_TYPE}" || HOST_64BIT_TYPE="long long"
+ test -n "${HOST_U_64BIT_TYPE}" || HOST_U_64BIT_TYPE="unsigned long long"
+- if test "x${ac_cv_sizeof_void_p}" = "x8"; then
++ if test "x${ac_cv_sizeof_void_p}" = "x8" \
++ -a "x${ac_cv_sizeof_long}" != "x8"; then
+ BFD_HOSTPTR_T="unsigned long long"
+ fi
+ fi
diff --git a/SOURCES/binutils-2.25-version.patch b/SOURCES/binutils-2.25-version.patch
new file mode 100644
index 0000000..d97e81b
--- /dev/null
+++ b/SOURCES/binutils-2.25-version.patch
@@ -0,0 +1,44 @@
+--- binutils-2.26.orig/bfd/Makefile.am 2016-01-25 10:11:33.505289018 +0000
++++ binutils-2.26/bfd/Makefile.am 2016-01-25 10:13:23.489964145 +0000
+@@ -1043,8 +1043,8 @@ DISTCLEANFILES = $(BUILD_CFILES) $(BUILD
+ bfdver.h: $(srcdir)/version.h $(srcdir)/development.sh $(srcdir)/Makefile.in
+ @echo "creating $@"
+ @bfd_version=`echo "$(VERSION)" | $(SED) -e 's/\([^\.]*\)\.*\([^\.]*\)\.*\([^\.]*\)\.*\([^\.]*\)\.*\([^\.]*\).*/\1.00\2.00\3.00\4.00\5/' -e 's/\([^\.]*\)\..*\(..\)\..*\(..\)\..*\(..\)\..*\(..\)$$/\1\2\3\4\5/'` ;\
+- bfd_version_string="\"$(VERSION)\"" ;\
+- bfd_soversion="$(VERSION)" ;\
++ bfd_version_string="\"$(VERSION)-%{release}\"" ;\
++ bfd_soversion="$(VERSION)-%{release}" ;\
+ bfd_version_package="\"$(PKGVERSION)\"" ;\
+ report_bugs_to="\"$(REPORT_BUGS_TO)\"" ;\
+ . $(srcdir)/development.sh ;\
+@@ -1055,7 +1055,7 @@ bfdver.h: $(srcdir)/version.h $(srcdir)/
+ fi ;\
+ $(SED) -e "s,@bfd_version@,$$bfd_version," \
+ -e "s,@bfd_version_string@,$$bfd_version_string," \
+- -e "s,@bfd_version_package@,$$bfd_version_package," \
++ -e "s,@bfd_version_package@,\"version \"," \
+ -e "s,@report_bugs_to@,$$report_bugs_to," \
+ < $(srcdir)/version.h > $@; \
+ echo "$${bfd_soversion}" > libtool-soversion
+--- binutils-2.26.orig/bfd/Makefile.in 2016-01-25 10:11:33.505289018 +0000
++++ binutils-2.26/bfd/Makefile.in 2016-01-25 10:14:17.818297941 +0000
+@@ -2111,8 +2111,8 @@ stmp-lcoff-h: $(LIBCOFF_H_FILES)
+ bfdver.h: $(srcdir)/version.h $(srcdir)/development.sh $(srcdir)/Makefile.in
+ @echo "creating $@"
+ @bfd_version=`echo "$(VERSION)" | $(SED) -e 's/\([^\.]*\)\.*\([^\.]*\)\.*\([^\.]*\)\.*\([^\.]*\)\.*\([^\.]*\).*/\1.00\2.00\3.00\4.00\5/' -e 's/\([^\.]*\)\..*\(..\)\..*\(..\)\..*\(..\)\..*\(..\)$$/\1\2\3\4\5/'` ;\
+- bfd_version_string="\"$(VERSION)\"" ;\
+- bfd_soversion="$(VERSION)" ;\
++ bfd_version_string="\"$(VERSION)-%{release}\"" ;\
++ bfd_soversion="$(VERSION)-%{release}" ;\
+ bfd_version_package="\"$(PKGVERSION)\"" ;\
+ report_bugs_to="\"$(REPORT_BUGS_TO)\"" ;\
+ . $(srcdir)/development.sh ;\
+@@ -2123,7 +2123,7 @@ bfdver.h: $(srcdir)/version.h $(srcdir)/
+ fi ;\
+ $(SED) -e "s,@bfd_version@,$$bfd_version," \
+ -e "s,@bfd_version_string@,$$bfd_version_string," \
+- -e "s,@bfd_version_package@,$$bfd_version_package," \
++ -e "s,@bfd_version_package@,\"version \"," \
+ -e "s,@report_bugs_to@,$$report_bugs_to," \
+ < $(srcdir)/version.h > $@; \
+ echo "$${bfd_soversion}" > libtool-soversion
diff --git a/SOURCES/binutils-2.25.1-objdump-speedup.patch b/SOURCES/binutils-2.25.1-objdump-speedup.patch
new file mode 100644
index 0000000..97f503d
--- /dev/null
+++ b/SOURCES/binutils-2.25.1-objdump-speedup.patch
@@ -0,0 +1,845 @@
+diff -rup binutils.orig/bfd/dwarf2.c binutils-2.25.1/bfd/dwarf2.c
+--- binutils.orig/bfd/dwarf2.c 2017-01-16 14:48:05.110778762 +0000
++++ binutils-2.25.1/bfd/dwarf2.c 2017-01-16 14:51:04.915885225 +0000
+@@ -144,16 +144,16 @@ struct dwarf2_debug
+ /* Length of the loaded .debug_str section. */
+ bfd_size_type dwarf_str_size;
+
+- /* Pointer to the .debug_ranges section loaded into memory. */
++ /* Pointer to the .debug_ranges section loaded into memory. */
+ bfd_byte *dwarf_ranges_buffer;
+
+- /* Length of the loaded .debug_ranges section. */
++ /* Length of the loaded .debug_ranges section. */
+ bfd_size_type dwarf_ranges_size;
+
+ /* If the most recent call to bfd_find_nearest_line was given an
+ address in an inlined function, preserve a pointer into the
+ calling chain for subsequent calls to bfd_find_inliner_info to
+- use. */
++ use. */
+ struct funcinfo *inliner_chain;
+
+ /* Section VMAs at the time the stash was built. */
+@@ -212,9 +212,12 @@ struct comp_unit
+ /* Keep the bfd convenient (for memory allocation). */
+ bfd *abfd;
+
+- /* The lowest and highest addresses contained in this compilation
+- unit as specified in the compilation unit header. */
++ /* Linked list of the low and high address ranges contained in this
++ compilation unit as specified in the compilation unit header. */
+ struct arange arange;
++ /* A single arange containing the lowest and highest
++ addresses covered by the compilation unit. */
++ struct arange minmax;
+
+ /* The DW_AT_name attribute (for error messages). */
+ char *name;
+@@ -256,6 +259,12 @@ struct comp_unit
+ /* A list of the functions found in this comp. unit. */
+ struct funcinfo *function_table;
+
++ /* A table of function information references searchable by address. */
++ struct lookup_funcinfo *lookup_funcinfo_table;
++
++ /* Number of functions in the function_table and sorted_function_table. */
++ bfd_size_type number_of_functions;
++
+ /* A list of the variables found in this comp. unit. */
+ struct varinfo *variable_table;
+
+@@ -390,7 +399,7 @@ struct info_hash_table
+ struct bfd_hash_table base;
+ };
+
+-/* Function to create a new entry in info hash table. */
++/* Function to create a new entry in info hash table. */
+
+ static struct bfd_hash_entry *
+ info_hash_table_newfunc (struct bfd_hash_entry *entry,
+@@ -476,7 +485,7 @@ insert_info_hash_table (struct info_hash
+ }
+
+ /* Look up an info entry list from an info hash table. Return NULL
+- if there is none. */
++ if there is none. */
+
+ static struct info_list_node *
+ lookup_info_hash_table (struct info_hash_table *hash_table, const char *key)
+@@ -517,8 +526,8 @@ read_section (bfd * abfd,
+ }
+ if (! msec)
+ {
+- (*_bfd_error_handler) (_("Dwarf Error: Can't find %s section."),
+- sec->uncompressed_name);
++ _bfd_error_handler (_("Dwarf Error: Can't find %s section."),
++ sec->uncompressed_name);
+ bfd_set_error (bfd_error_bad_value);
+ return FALSE;
+ }
+@@ -546,9 +555,10 @@ read_section (bfd * abfd,
+ that the client wants. Validate it here to avoid trouble later. */
+ if (offset != 0 && offset >= *section_size)
+ {
+- (*_bfd_error_handler) (_("Dwarf Error: Offset (%lu)"
+- " greater than or equal to %s size (%lu)."),
+- (long) offset, section_name, *section_size);
++ /* xgettext: c-format */
++ _bfd_error_handler (_("Dwarf Error: Offset (%lu)"
++ " greater than or equal to %s size (%lu)."),
++ (long) offset, section_name, *section_size);
+ bfd_set_error (bfd_error_bad_value);
+ return FALSE;
+ }
+@@ -1157,8 +1167,8 @@ read_attribute_value (struct attribute *
+ info_ptr = read_attribute_value (attr, form, unit, info_ptr, info_ptr_end);
+ break;
+ default:
+- (*_bfd_error_handler) (_("Dwarf Error: Invalid or unhandled FORM value: %#x."),
+- form);
++ _bfd_error_handler (_("Dwarf Error: Invalid or unhandled FORM value: %#x."),
++ form);
+ bfd_set_error (bfd_error_bad_value);
+ return NULL;
+ }
+@@ -1213,22 +1223,22 @@ non_mangled (int lang)
+
+ struct line_info
+ {
+- struct line_info* prev_line;
+- bfd_vma address;
+- char *filename;
+- unsigned int line;
+- unsigned int column;
+- unsigned int discriminator;
+- unsigned char op_index;
+- unsigned char end_sequence; /* End of (sequential) code sequence. */
++ struct line_info * prev_line;
++ bfd_vma address;
++ char * filename;
++ unsigned int line;
++ unsigned int column;
++ unsigned int discriminator;
++ unsigned char op_index;
++ unsigned char end_sequence; /* End of (sequential) code sequence. */
+ };
+
+ struct fileinfo
+ {
+- char *name;
+- unsigned int dir;
+- unsigned int time;
+- unsigned int size;
++ char * name;
++ unsigned int dir;
++ unsigned int time;
++ unsigned int size;
+ };
+
+ struct line_sequence
+@@ -1236,11 +1246,13 @@ struct line_sequence
+ bfd_vma low_pc;
+ struct line_sequence* prev_sequence;
+ struct line_info* last_line; /* Largest VMA. */
++ struct line_info** line_info_lookup;
++ bfd_size_type num_lines;
+ };
+
+ struct line_info_table
+ {
+- bfd* abfd;
++ bfd * abfd;
+ unsigned int num_files;
+ unsigned int num_dirs;
+ unsigned int num_sequences;
+@@ -1259,23 +1271,37 @@ struct line_info_table
+ struct funcinfo
+ {
+ /* Pointer to previous function in list of all functions. */
+- struct funcinfo *prev_func;
++ struct funcinfo * prev_func;
+ /* Pointer to function one scope higher. */
+- struct funcinfo *caller_func;
++ struct funcinfo * caller_func;
+ /* Source location file name where caller_func inlines this func. */
+- char *caller_file;
++ char * caller_file;
+ /* Source location file name. */
+- char *file;
++ char * file;
+ /* Source location line number where caller_func inlines this func. */
+- int caller_line;
++ int caller_line;
+ /* Source location line number. */
+- int line;
+- int tag;
+- bfd_boolean is_linkage;
+- const char *name;
+- struct arange arange;
++ int line;
++ int tag;
++ bfd_boolean is_linkage;
++ const char * name;
++ struct arange arange;
+ /* Where the symbol is defined. */
+- asection *sec;
++ asection * sec;
++};
++
++struct lookup_funcinfo
++{
++ /* Function information corresponding to this lookup table entry. */
++ struct funcinfo * funcinfo;
++
++ /* The lowest address for this specific function. */
++ bfd_vma low_addr;
++
++ /* The highest address of this function before the lookup table is sorted.
++ The highest address of all prior functions after the lookup table is
++ sorted, which is used for binary search. */
++ bfd_vma high_addr;
+ };
+
+ struct varinfo
+@@ -1446,7 +1472,7 @@ concat_filename (struct line_info_table
+ {
+ /* FILE == 0 means unknown. */
+ if (file)
+- (*_bfd_error_handler)
++ _bfd_error_handler
+ (_("Dwarf Error: mangled line number section (bad file number)."));
+ return strdup ("<unknown>");
+ }
+@@ -1502,7 +1528,7 @@ concat_filename (struct line_info_table
+ }
+
+ static bfd_boolean
+-arange_add (const struct comp_unit *unit, struct arange *first_arange,
++arange_add (struct comp_unit *unit, struct arange *first_arange,
+ bfd_vma low_pc, bfd_vma high_pc)
+ {
+ struct arange *arange;
+@@ -1514,11 +1540,16 @@ arange_add (const struct comp_unit *unit
+ /* If the first arange is empty, use it. */
+ if (first_arange->high == 0)
+ {
+- first_arange->low = low_pc;
+- first_arange->high = high_pc;
++ unit->minmax.low = first_arange->low = low_pc;
++ unit->minmax.high = first_arange->high = high_pc;
+ return TRUE;
+ }
+
++ if (unit->minmax.low > low_pc)
++ unit->minmax.low = low_pc;
++ if (unit->minmax.high < high_pc)
++ unit->minmax.high = high_pc;
++
+ /* Next see if we can cheaply extend an existing range. */
+ arange = first_arange;
+ do
+@@ -1538,7 +1569,7 @@ arange_add (const struct comp_unit *unit
+ while (arange);
+
+ /* Need to allocate a new arange and insert it into the arange list.
+- Order isn't significant, so just insert after the first arange. */
++ Order isn't significant, so just insert after the first arange. */
+ arange = (struct arange *) bfd_alloc (unit->abfd, sizeof (*arange));
+ if (arange == NULL)
+ return FALSE;
+@@ -1578,17 +1609,62 @@ compare_sequences (const void* a, const
+ return 0;
+ }
+
++/* Construct the line information table for quick lookup. */
++
++static bfd_boolean
++build_line_info_table (struct line_info_table * table,
++ struct line_sequence * seq)
++{
++ bfd_size_type amt;
++ struct line_info** line_info_lookup;
++ struct line_info* each_line;
++ unsigned int num_lines;
++ unsigned int line_index;
++
++ if (seq->line_info_lookup != NULL)
++ return TRUE;
++
++ /* Count the number of line information entries. We could do this while
++ scanning the debug information, but some entries may be added via
++ lcl_head without having a sequence handy to increment the number of
++ lines. */
++ num_lines = 0;
++ for (each_line = seq->last_line; each_line; each_line = each_line->prev_line)
++ num_lines++;
++
++ if (num_lines == 0)
++ return TRUE;
++
++ /* Allocate space for the line information lookup table. */
++ amt = sizeof (struct line_info*) * num_lines;
++ line_info_lookup = (struct line_info**) bfd_alloc (table->abfd, amt);
++ if (line_info_lookup == NULL)
++ return FALSE;
++
++ /* Create the line information lookup table. */
++ line_index = num_lines;
++ for (each_line = seq->last_line; each_line; each_line = each_line->prev_line)
++ line_info_lookup[--line_index] = each_line;
++
++ BFD_ASSERT (line_index == 0);
++
++ seq->num_lines = num_lines;
++ seq->line_info_lookup = line_info_lookup;
++
++ return TRUE;
++}
++
+ /* Sort the line sequences for quick lookup. */
+
+ static bfd_boolean
+ sort_line_sequences (struct line_info_table* table)
+ {
+- bfd_size_type amt;
+- struct line_sequence* sequences;
+- struct line_sequence* seq;
+- unsigned int n = 0;
+- unsigned int num_sequences = table->num_sequences;
+- bfd_vma last_high_pc;
++ bfd_size_type amt;
++ struct line_sequence* sequences;
++ struct line_sequence* seq;
++ unsigned int n = 0;
++ unsigned int num_sequences = table->num_sequences;
++ bfd_vma last_high_pc;
+
+ if (num_sequences == 0)
+ return TRUE;
+@@ -1609,6 +1685,8 @@ sort_line_sequences (struct line_info_ta
+ sequences[n].low_pc = seq->low_pc;
+ sequences[n].prev_sequence = NULL;
+ sequences[n].last_line = seq->last_line;
++ sequences[n].line_info_lookup = NULL;
++ sequences[n].num_lines = 0;
+ seq = seq->prev_sequence;
+ free (last_seq);
+ }
+@@ -1687,7 +1765,7 @@ decode_line_info (struct comp_unit *unit
+
+ if (stash->dwarf_line_size < 16)
+ {
+- (*_bfd_error_handler)
++ _bfd_error_handler
+ (_("Dwarf Error: Line info section is too small (%ld)"),
+ (long) stash->dwarf_line_size);
+ bfd_set_error (bfd_error_bad_value);
+@@ -1716,7 +1794,8 @@ decode_line_info (struct comp_unit *unit
+
+ if (lh.total_length > stash->dwarf_line_size)
+ {
+- (*_bfd_error_handler)
++ _bfd_error_handler
++ /* xgettext: c-format */
+ (_("Dwarf Error: Line info data is bigger (0x%lx) than the section (0x%lx)"),
+ (long) lh.total_length, (long) stash->dwarf_line_size);
+ bfd_set_error (bfd_error_bad_value);
+@@ -1728,7 +1807,7 @@ decode_line_info (struct comp_unit *unit
+ lh.version = read_2_bytes (abfd, line_ptr, line_end);
+ if (lh.version < 2 || lh.version > 4)
+ {
+- (*_bfd_error_handler)
++ _bfd_error_handler
+ (_("Dwarf Error: Unhandled .debug_line version %d."), lh.version);
+ bfd_set_error (bfd_error_bad_value);
+ return NULL;
+@@ -1737,7 +1816,7 @@ decode_line_info (struct comp_unit *unit
+
+ if (line_ptr + offset_size + (lh.version >=4 ? 6 : 5) >= line_end)
+ {
+- (*_bfd_error_handler)
++ _bfd_error_handler
+ (_("Dwarf Error: Ran out of room reading prologue"));
+ bfd_set_error (bfd_error_bad_value);
+ return NULL;
+@@ -1762,7 +1841,7 @@ decode_line_info (struct comp_unit *unit
+
+ if (lh.maximum_ops_per_insn == 0)
+ {
+- (*_bfd_error_handler)
++ _bfd_error_handler
+ (_("Dwarf Error: Invalid maximum operations per instruction."));
+ bfd_set_error (bfd_error_bad_value);
+ return NULL;
+@@ -1782,7 +1861,7 @@ decode_line_info (struct comp_unit *unit
+
+ if (line_ptr + (lh.opcode_base - 1) >= line_end)
+ {
+- (*_bfd_error_handler) (_("Dwarf Error: Ran out of room reading opcodes"));
++ _bfd_error_handler (_("Dwarf Error: Ran out of room reading opcodes"));
+ bfd_set_error (bfd_error_bad_value);
+ return NULL;
+ }
+@@ -1969,7 +2048,7 @@ decode_line_info (struct comp_unit *unit
+ line_ptr += exop_len - 1;
+ break;
+ default:
+- (*_bfd_error_handler)
++ _bfd_error_handler
+ (_("Dwarf Error: mangled line number section."));
+ bfd_set_error (bfd_error_bad_value);
+ line_fail:
+@@ -2089,7 +2168,7 @@ lookup_address_in_line_info_table (struc
+ unsigned int *discriminator_ptr)
+ {
+ struct line_sequence *seq = NULL;
+- struct line_info *each_line;
++ struct line_info *info;
+ int low, high, mid;
+
+ /* Binary search the array of sequences. */
+@@ -2107,26 +2186,43 @@ lookup_address_in_line_info_table (struc
+ break;
+ }
+
+- if (seq && addr >= seq->low_pc && addr < seq->last_line->address)
++ /* Check for a valid sequence. */
++ if (!seq || addr < seq->low_pc || addr >= seq->last_line->address)
++ goto fail;
++
++ if (!build_line_info_table (table, seq))
++ goto fail;
++
++ /* Binary search the array of line information. */
++ low = 0;
++ high = seq->num_lines;
++ info = NULL;
++ while (low < high)
+ {
+- /* Note: seq->last_line should be a descendingly sorted list. */
+- for (each_line = seq->last_line;
+- each_line;
+- each_line = each_line->prev_line)
+- if (addr >= each_line->address)
+- break;
++ mid = (low + high) / 2;
++ info = seq->line_info_lookup[mid];
++ if (addr < info->address)
++ high = mid;
++ else if (addr >= seq->line_info_lookup[mid + 1]->address)
++ low = mid + 1;
++ else
++ break;
++ }
+
+- if (each_line
+- && !(each_line->end_sequence || each_line == seq->last_line))
+- {
+- *filename_ptr = each_line->filename;
+- *linenumber_ptr = each_line->line;
+- if (discriminator_ptr)
+- *discriminator_ptr = each_line->discriminator;
+- return seq->last_line->address - seq->low_pc;
+- }
++ /* Check for a valid line information entry. */
++ if (info
++ && addr >= info->address
++ && addr < seq->line_info_lookup[mid + 1]->address
++ && !(info->end_sequence || info == seq->last_line))
++ {
++ *filename_ptr = info->filename;
++ *linenumber_ptr = info->line;
++ if (discriminator_ptr)
++ *discriminator_ptr = info->discriminator;
++ return seq->last_line->address - seq->low_pc;
+ }
+
++fail:
+ *filename_ptr = NULL;
+ return 0;
+ }
+@@ -2134,16 +2230,102 @@ lookup_address_in_line_info_table (struc
+ /* Read in the .debug_ranges section for future reference. */
+
+ static bfd_boolean
+-read_debug_ranges (struct comp_unit *unit)
++read_debug_ranges (struct comp_unit * unit)
+ {
+- struct dwarf2_debug *stash = unit->stash;
++ struct dwarf2_debug * stash = unit->stash;
++
+ return read_section (unit->abfd, &stash->debug_sections[debug_ranges],
+ stash->syms, 0,
+- &stash->dwarf_ranges_buffer, &stash->dwarf_ranges_size);
++ &stash->dwarf_ranges_buffer,
++ &stash->dwarf_ranges_size);
+ }
+
+ /* Function table functions. */
+
++static int
++compare_lookup_funcinfos (const void * a, const void * b)
++{
++ const struct lookup_funcinfo * lookup1 = a;
++ const struct lookup_funcinfo * lookup2 = b;
++
++ if (lookup1->low_addr < lookup2->low_addr)
++ return -1;
++ if (lookup1->low_addr > lookup2->low_addr)
++ return 1;
++ if (lookup1->high_addr < lookup2->high_addr)
++ return -1;
++ if (lookup1->high_addr > lookup2->high_addr)
++ return 1;
++
++ return 0;
++}
++
++static bfd_boolean
++build_lookup_funcinfo_table (struct comp_unit * unit)
++{
++ struct lookup_funcinfo *lookup_funcinfo_table = unit->lookup_funcinfo_table;
++ unsigned int number_of_functions = unit->number_of_functions;
++ struct funcinfo *each;
++ struct lookup_funcinfo *entry;
++ size_t func_index;
++ struct arange *range;
++ bfd_vma low_addr, high_addr;
++
++ if (lookup_funcinfo_table || number_of_functions == 0)
++ return TRUE;
++
++ /* Create the function info lookup table. */
++ lookup_funcinfo_table = (struct lookup_funcinfo *)
++ bfd_malloc (number_of_functions * sizeof (struct lookup_funcinfo));
++ if (lookup_funcinfo_table == NULL)
++ return FALSE;
++
++ /* Populate the function info lookup table. */
++ func_index = number_of_functions;
++ for (each = unit->function_table; each; each = each->prev_func)
++ {
++ entry = &lookup_funcinfo_table[--func_index];
++ entry->funcinfo = each;
++
++ /* Calculate the lowest and highest address for this function entry. */
++ low_addr = entry->funcinfo->arange.low;
++ high_addr = entry->funcinfo->arange.high;
++
++ for (range = entry->funcinfo->arange.next; range; range = range->next)
++ {
++ if (range->low < low_addr)
++ low_addr = range->low;
++ if (range->high > high_addr)
++ high_addr = range->high;
++ }
++
++ entry->low_addr = low_addr;
++ entry->high_addr = high_addr;
++ }
++
++ BFD_ASSERT (func_index == 0);
++
++ /* Sort the function by address. */
++ qsort (lookup_funcinfo_table,
++ number_of_functions,
++ sizeof (struct lookup_funcinfo),
++ compare_lookup_funcinfos);
++
++ /* Calculate the high watermark for each function in the lookup table. */
++ high_addr = lookup_funcinfo_table[0].high_addr;
++ for (func_index = 1; func_index < number_of_functions; func_index++)
++ {
++ entry = &lookup_funcinfo_table[func_index];
++ if (entry->high_addr > high_addr)
++ high_addr = entry->high_addr;
++ else
++ entry->high_addr = high_addr;
++ }
++
++ unit->lookup_funcinfo_table = lookup_funcinfo_table;
++ return TRUE;
++}
++
+ /* If ADDR is within UNIT's function tables, set FUNCTION_PTR, and return
+ TRUE. Note that we need to find the function that has the smallest range
+ that contains ADDR, to handle inlined functions without depending upon
+@@ -2154,37 +2336,77 @@ lookup_address_in_function_table (struct
+ bfd_vma addr,
+ struct funcinfo **function_ptr)
+ {
+- struct funcinfo* each_func;
++ unsigned int number_of_functions = unit->number_of_functions;
++ struct lookup_funcinfo* lookup_funcinfo = NULL;
++ struct funcinfo* funcinfo = NULL;
+ struct funcinfo* best_fit = NULL;
+ bfd_vma best_fit_len = 0;
++ bfd_size_type low, high, mid, first;
+ struct arange *arange;
+
+- for (each_func = unit->function_table;
+- each_func;
+- each_func = each_func->prev_func)
++ if (number_of_functions == 0)
++ return FALSE;
++
++ if (!build_lookup_funcinfo_table (unit))
++ return FALSE;
++
++ if (unit->lookup_funcinfo_table[number_of_functions - 1].high_addr < addr)
++ return FALSE;
++
++ /* Find the first function in the lookup table which may contain the
++ specified address. */
++ low = 0;
++ high = number_of_functions;
++ first = high;
++ while (low < high)
+ {
+- for (arange = &each_func->arange;
+- arange;
+- arange = arange->next)
++ mid = (low + high) / 2;
++ lookup_funcinfo = &unit->lookup_funcinfo_table[mid];
++ if (addr < lookup_funcinfo->low_addr)
++ high = mid;
++ else if (addr >= lookup_funcinfo->high_addr)
++ low = mid + 1;
++ else
++ high = first = mid;
++ }
++
++ /* Find the 'best' match for the address. The prior algorithm defined the
++ best match as the function with the smallest address range containing
++ the specified address. This definition should probably be changed to the
++ innermost inline routine containing the address, but right now we want
++ to get the same results we did before. */
++ while (first < number_of_functions)
++ {
++ if (addr < unit->lookup_funcinfo_table[first].low_addr)
++ break;
++ funcinfo = unit->lookup_funcinfo_table[first].funcinfo;
++
++ for (arange = &funcinfo->arange; arange; arange = arange->next)
+ {
+- if (addr >= arange->low && addr < arange->high)
++ if (addr < arange->low || addr >= arange->high)
++ continue;
++
++ if (!best_fit
++ || arange->high - arange->low < best_fit_len
++ /* The following comparison is designed to return the same
++ match as the previous algorithm for routines which have the
++ same best fit length. */
++ || (arange->high - arange->low == best_fit_len
++ && funcinfo > best_fit))
+ {
+- if (!best_fit
+- || arange->high - arange->low < best_fit_len)
+- {
+- best_fit = each_func;
+- best_fit_len = arange->high - arange->low;
+- }
++ best_fit = funcinfo;
++ best_fit_len = arange->high - arange->low;
+ }
+ }
+- }
+
+- if (best_fit)
+- {
+- *function_ptr = best_fit;
+- return TRUE;
++ first++;
+ }
+- return FALSE;
++
++ if (!best_fit)
++ return FALSE;
++
++ *function_ptr = best_fit;
++ return TRUE;
+ }
+
+ /* If SYM at ADDR is within function table of UNIT, set FILENAME_PTR
+@@ -2269,8 +2491,8 @@ lookup_symbol_in_variable_table (struct
+ *linenumber_ptr = each->line;
+ return TRUE;
+ }
+- else
+- return FALSE;
++
++ return FALSE;
+ }
+
+ static char *
+@@ -2326,7 +2548,7 @@ find_abstract_instance_name (struct comp
+ info_ptr = read_alt_indirect_ref (unit, die_ref);
+ if (info_ptr == NULL)
+ {
+- (*_bfd_error_handler)
++ _bfd_error_handler
+ (_("Dwarf Error: Unable to read alt ref %u."), die_ref);
+ bfd_set_error (bfd_error_bad_value);
+ return NULL;
+@@ -2350,7 +2572,7 @@ find_abstract_instance_name (struct comp
+ abbrev = lookup_abbrev (abbrev_number, unit->abbrevs);
+ if (! abbrev)
+ {
+- (*_bfd_error_handler)
++ _bfd_error_handler
+ (_("Dwarf Error: Could not find abbrev number %u."), abbrev_number);
+ bfd_set_error (bfd_error_bad_value);
+ }
+@@ -2494,7 +2716,7 @@ scan_unit_for_symbols (struct comp_unit
+ abbrev = lookup_abbrev (abbrev_number,unit->abbrevs);
+ if (! abbrev)
+ {
+- (*_bfd_error_handler)
++ _bfd_error_handler
+ (_("Dwarf Error: Could not find abbrev number %u."),
+ abbrev_number);
+ bfd_set_error (bfd_error_bad_value);
+@@ -2513,6 +2735,7 @@ scan_unit_for_symbols (struct comp_unit
+ func->tag = abbrev->tag;
+ func->prev_func = unit->function_table;
+ unit->function_table = func;
++ unit->number_of_functions++;
+ BFD_ASSERT (!unit->cached);
+
+ if (func->tag == DW_TAG_inlined_subroutine)
+@@ -2766,7 +2989,8 @@ parse_comp_unit (struct dwarf2_debug *st
+
+ if (addr_size > sizeof (bfd_vma))
+ {
+- (*_bfd_error_handler)
++ _bfd_error_handler
++ /* xgettext: c-format */
+ (_("Dwarf Error: found address size '%u', this reader"
+ " can not handle sizes greater than '%u'."),
+ addr_size,
+@@ -2777,7 +3001,7 @@ parse_comp_unit (struct dwarf2_debug *st
+
+ if (addr_size != 2 && addr_size != 4 && addr_size != 8)
+ {
+- (*_bfd_error_handler)
++ _bfd_error_handler
+ ("Dwarf Error: found address size '%u', this reader"
+ " can only handle address sizes '2', '4' and '8'.", addr_size);
+ bfd_set_error (bfd_error_bad_value);
+@@ -2845,7 +3069,7 @@ parse_comp_unit (struct dwarf2_debug *st
+ low_pc = attr.u.val;
+ /* If the compilation unit DIE has a DW_AT_low_pc attribute,
+ this is the base address to use when reading location
+- lists or range lists. */
++ lists or range lists. */
+ if (abbrev->tag == DW_TAG_compile_unit)
+ unit->base_address = low_pc;
+ break;
+@@ -2867,7 +3091,7 @@ parse_comp_unit (struct dwarf2_debug *st
+ /* PR 17512: file: 1fe726be. */
+ if (! is_str_attr (attr.form))
+ {
+- (*_bfd_error_handler)
++ _bfd_error_handler
+ (_("Dwarf Error: DW_AT_comp_dir attribute encountered with a non-string form."));
+ comp_dir = NULL;
+ }
+@@ -2919,6 +3143,11 @@ comp_unit_contains_address (struct comp_
+ if (unit->error)
+ return FALSE;
+
++ if (unit->minmax.high < addr || unit->minmax.low > addr)
++ return FALSE;
++
++ /* We know that the address *might* be contained within this comp
++ unit, but we cannot be sure until we check the specific ranges. */
+ arange = &unit->arange;
+ do
+ {
+@@ -3116,7 +3345,7 @@ comp_unit_hash_info (struct dwarf2_debug
+ each_func && okay;
+ each_func = each_func->prev_func)
+ {
+- /* Skip nameless functions. */
++ /* Skip nameless functions. */
+ if (each_func->name)
+ /* There is no need to copy name string into hash table as
+ name string is either in the dwarf string buffer or
+@@ -3498,7 +3727,7 @@ stash_maybe_update_info_hash_tables (str
+ return TRUE;
+ }
+
+-/* Check consistency of info hash tables. This is for debugging only. */
++/* Check consistency of info hash tables. This is for debugging only. */
+
+ static void ATTRIBUTE_UNUSED
+ stash_verify_info_hash_table (struct dwarf2_debug *stash)
+@@ -3930,7 +4159,7 @@ _bfd_dwarf2_find_nearest_line (bfd *abfd
+ stash_maybe_enable_info_hash_tables (abfd, stash);
+
+ /* Keep info hash table up to date if they are available. Note that we
+- may disable the hash tables if there is any error duing update. */
++ may disable the hash tables if there is any error duing update. */
+ if (stash->info_hash_status == STASH_INFO_HASH_ON)
+ stash_maybe_update_info_hash_tables (stash);
+
+@@ -4222,6 +4451,12 @@ _bfd_dwarf2_cleanup_debug_info (bfd *abf
+ function_table = function_table->prev_func;
+ }
+
++ if (each->lookup_funcinfo_table)
++ {
++ free (each->lookup_funcinfo_table);
++ each->lookup_funcinfo_table = NULL;
++ }
++
+ while (variable_table)
+ {
+ if (variable_table->file)
+diff -rup binutils.orig/binutils/objdump.c binutils-2.25.1/binutils/objdump.c
+--- binutils.orig/binutils/objdump.c 2017-01-16 14:48:06.214761408 +0000
++++ binutils-2.25.1/binutils/objdump.c 2017-01-16 14:50:19.313618730 +0000
+@@ -3439,7 +3439,7 @@ display_any_bfd (bfd *file, int level)
+ }
+
+ static void
+-display_file (char *filename, char *target)
++display_file (char *filename, char *target, bfd_boolean last_file)
+ {
+ bfd *file;
+
+@@ -3458,7 +3458,14 @@ display_file (char *filename, char *targ
+
+ display_any_bfd (file, 0);
+
+- bfd_close (file);
++ /* This is an optimization to improve the speed of objdump, especially when
++ dumping a file with lots of associated debug informatiom. Closing such
++ a file can take a non-trivial amount of time as there are lots of lists
++ to walk and buffers to free. This is only really necessary however if
++ we are about to load another file. Otherwise, if we are about to exit,
++ then we can save (a lot of) time by not bothering to do any tidying up. */
++ if (! last_file)
++ bfd_close (file);
+ }
+
+ int
+@@ -3736,10 +3743,13 @@ main (int argc, char **argv)
+ else
+ {
+ if (optind == argc)
+- display_file ("a.out", target);
++ display_file ("a.out", target, TRUE);
+ else
+ for (; optind < argc;)
+- display_file (argv[optind++], target);
++ {
++ display_file (argv[optind], target, optind == argc - 1);
++ optind++;
++ }
+ }
+
+ free_only_list ();
+
diff --git a/SOURCES/binutils-2.27-ARMv8.2.patch b/SOURCES/binutils-2.27-ARMv8.2.patch
new file mode 100644
index 0000000..63a54eb
--- /dev/null
+++ b/SOURCES/binutils-2.27-ARMv8.2.patch
@@ -0,0 +1,3590 @@
+diff -rup binutils.orig/gas/config/tc-arm.c binutils-2.27/gas/config/tc-arm.c
+--- binutils.orig/gas/config/tc-arm.c 2017-08-09 10:26:30.032741952 +0100
++++ binutils-2.27/gas/config/tc-arm.c 2017-08-09 11:17:17.747598541 +0100
+@@ -147,8 +147,10 @@ static const arm_feature_set *legacy_cpu
+ static const arm_feature_set *legacy_fpu = NULL;
+
+ static const arm_feature_set *mcpu_cpu_opt = NULL;
++static arm_feature_set *dyn_mcpu_ext_opt = NULL;
+ static const arm_feature_set *mcpu_fpu_opt = NULL;
+ static const arm_feature_set *march_cpu_opt = NULL;
++static arm_feature_set *dyn_march_ext_opt = NULL;
+ static const arm_feature_set *march_fpu_opt = NULL;
+ static const arm_feature_set *mfpu_opt = NULL;
+ static const arm_feature_set *object_arch = NULL;
+@@ -187,7 +189,6 @@ static const arm_feature_set arm_ext_v5j
+ static const arm_feature_set arm_ext_v6 = ARM_FEATURE_CORE_LOW (ARM_EXT_V6);
+ static const arm_feature_set arm_ext_v6k = ARM_FEATURE_CORE_LOW (ARM_EXT_V6K);
+ static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2);
+-static const arm_feature_set arm_ext_v6m = ARM_FEATURE_CORE_LOW (ARM_EXT_V6M);
+ static const arm_feature_set arm_ext_v6_notm =
+ ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM);
+ static const arm_feature_set arm_ext_v6_dsp =
+@@ -201,11 +202,11 @@ static const arm_feature_set arm_ext_v7
+ static const arm_feature_set arm_ext_v7a = ARM_FEATURE_CORE_LOW (ARM_EXT_V7A);
+ static const arm_feature_set arm_ext_v7r = ARM_FEATURE_CORE_LOW (ARM_EXT_V7R);
+ #ifdef OBJ_ELF
+-static const arm_feature_set arm_ext_v7m = ARM_FEATURE_CORE_LOW (ARM_EXT_V7M);
++static const arm_feature_set ATTRIBUTE_UNUSED arm_ext_v7m = ARM_FEATURE_CORE_LOW (ARM_EXT_V7M);
+ #endif
+ static const arm_feature_set arm_ext_v8 = ARM_FEATURE_CORE_LOW (ARM_EXT_V8);
+ static const arm_feature_set arm_ext_m =
+- ARM_FEATURE_CORE (ARM_EXT_V6M | ARM_EXT_OS | ARM_EXT_V7M,
++ ARM_FEATURE_CORE (ARM_EXT_V6M | ARM_EXT_V7M,
+ ARM_EXT2_V8M | ARM_EXT2_V8M_MAIN);
+ static const arm_feature_set arm_ext_mp = ARM_FEATURE_CORE_LOW (ARM_EXT_MP);
+ static const arm_feature_set arm_ext_sec = ARM_FEATURE_CORE_LOW (ARM_EXT_SEC);
+@@ -234,14 +235,16 @@ static const arm_feature_set arm_ext_ras
+ /* FP16 instructions. */
+ static const arm_feature_set arm_ext_fp16 =
+ ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST);
++static const arm_feature_set arm_ext_v8_3 =
++ ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A);
+
+ static const arm_feature_set arm_arch_any = ARM_ANY;
++#ifdef OBJ_ELF
++static const arm_feature_set fpu_any = FPU_ANY;
++#endif
+ static const arm_feature_set arm_arch_full ATTRIBUTE_UNUSED = ARM_FEATURE (-1, -1, -1);
+ static const arm_feature_set arm_arch_t2 = ARM_ARCH_THUMB2;
+ static const arm_feature_set arm_arch_none = ARM_ARCH_NONE;
+-#ifdef OBJ_ELF
+-static const arm_feature_set arm_arch_v6m_only = ARM_ARCH_V6M_ONLY;
+-#endif
+
+ static const arm_feature_set arm_cext_iwmmxt2 =
+ ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2);
+@@ -291,6 +294,8 @@ static const arm_feature_set crc_ext_arm
+ ARM_FEATURE_COPROC (CRC_EXT_ARMV8);
+ static const arm_feature_set fpu_neon_ext_v8_1 =
+ ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA);
++static const arm_feature_set fpu_neon_ext_dotprod =
++ ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD);
+
+ static int mfloat_abi_opt = -1;
+ /* Record user cpu selection for object attributes. */
+@@ -685,9 +690,11 @@ struct asm_opcode
+ #define T2_SUBS_PC_LR 0xf3de8f00
+
+ #define DATA_OP_SHIFT 21
++#define SBIT_SHIFT 20
+
+ #define T2_OPCODE_MASK 0xfe1fffff
+ #define T2_DATA_OP_SHIFT 21
++#define T2_SBIT_SHIFT 20
+
+ #define A_COND_MASK 0xf0000000
+ #define A_PUSH_POP_OP_MASK 0x0fff0000
+@@ -1276,6 +1283,7 @@ arm_reg_alt_syntax (char **ccp, char *st
+ if (*ccp != start && processor <= 15)
+ return processor;
+ }
++ /* Fall through. */
+
+ case REG_TYPE_MMXWC:
+ /* WC includes WCG. ??? I'm not sure this is true for all
+@@ -2705,7 +2713,7 @@ mapping_state (enum mstate state)
+
+ Some Thumb instructions are alignment-sensitive modulo 4 bytes,
+ but themselves require 2-byte alignment; this applies to some
+- PC- relative forms. However, these cases will invovle implicit
++ PC- relative forms. However, these cases will involve implicit
+ literal pool generation or an explicit .align >=2, both of
+ which will cause the section to me marked with sufficient
+ alignment. Thus, we don't handle those cases here. */
+@@ -3042,7 +3050,7 @@ s_ccs_ref (int unused ATTRIBUTE_UNUSED)
+ }
+
+ /* If name is not NULL, then it is used for marking the beginning of a
+- function, wherease if it is NULL then it means the function end. */
++ function, whereas if it is NULL then it means the function end. */
+ static void
+ asmfunc_debug (const char * name)
+ {
+@@ -3375,7 +3383,7 @@ tc_start_label_without_colon (void)
+ }
+
+ /* Can't use symbol_new here, so have to create a symbol and then at
+- a later date assign it a value. Thats what these functions do. */
++ a later date assign it a value. That's what these functions do. */
+
+ static void
+ symbol_locate (symbolS * symbolP,
+@@ -4964,9 +4972,13 @@ parse_ifimm_zero (char **in)
+ int error_code;
+
+ if (!is_immediate_prefix (**in))
+- return FALSE;
+-
+- ++*in;
++ {
++ /* In unified syntax, all prefixes are optional. */
++ if (!unified_syntax)
++ return FALSE;
++ }
++ else
++ ++*in;
+
+ /* Accept #0x0 as a synonym for #0. */
+ if (strncmp (*in, "0x", 2) == 0)
+@@ -6530,6 +6542,8 @@ enum operand_parse_code
+ OP_EXPi, /* same, with optional immediate prefix */
+ OP_EXPr, /* same, with optional relocation suffix */
+ OP_HALF, /* 0 .. 65535 or low/high reloc. */
++ OP_IROT1, /* VCADD rotate immediate: 90, 270. */
++ OP_IROT2, /* VCMLA rotate immediate: 0, 90, 180, 270. */
+
+ OP_CPSF, /* CPS flags */
+ OP_ENDI, /* Endianness specifier */
+@@ -6541,7 +6555,7 @@ enum operand_parse_code
+ OP_APSR_RR, /* ARM register or "APSR_nzcv". */
+
+ OP_RRnpc_I0, /* ARM register or literal 0 */
+- OP_RR_EXr, /* ARM register or expression with opt. reloc suff. */
++ OP_RR_EXr, /* ARM register or expression with opt. reloc stuff. */
+ OP_RR_EXi, /* ARM register or expression with imm prefix */
+ OP_RF_IF, /* FPA register or immediate */
+ OP_RIWR_RIWC, /* iWMMXt R or C reg */
+@@ -7178,8 +7192,14 @@ parse_operands (char *str, const unsigne
+ {
+ if (inst.operands[i].reg == REG_PC)
+ inst.error = BAD_PC;
+- else if (inst.operands[i].reg == REG_SP)
+- inst.error = BAD_SP;
++ else if (inst.operands[i].reg == REG_SP
++ /* The restriction on Rd/Rt/Rt2 on Thumb mode has been
++ relaxed since ARMv8-A. */
++ && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
++ {
++ gas_assert (thumb);
++ inst.error = BAD_SP;
++ }
+ }
+ break;
+
+@@ -7277,14 +7297,23 @@ parse_operands (char *str, const unsigne
+
+ /* Reject "bad registers" for Thumb-2 instructions. Many Thumb-2
+ instructions are unpredictable if these registers are used. This
+- is the BadReg predicate in ARM's Thumb-2 documentation. */
+-#define reject_bad_reg(reg) \
+- do \
+- if (reg == REG_SP || reg == REG_PC) \
+- { \
+- inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC; \
+- return; \
+- } \
++ is the BadReg predicate in ARM's Thumb-2 documentation.
++
++ Before ARMv8-A, REG_PC and REG_SP were not allowed in quite a few
++ places, while the restriction on REG_SP was relaxed since ARMv8-A. */
++#define reject_bad_reg(reg) \
++ do \
++ if (reg == REG_PC) \
++ { \
++ inst.error = BAD_PC; \
++ return; \
++ } \
++ else if (reg == REG_SP \
++ && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8)) \
++ { \
++ inst.error = BAD_SP; \
++ return; \
++ } \
+ while (0)
+
+ /* If REG is R13 (the stack pointer), warn that its use is
+@@ -7303,7 +7332,7 @@ parse_operands (char *str, const unsigne
+
+ The only binary encoding difference is the Coprocessor number. Coprocessor
+ 9 is used for half-precision calculations or conversions. The format of the
+- instruction is the same as the equivalent Coprocessor 10 instuction that
++ instruction is the same as the equivalent Coprocessor 10 instruction that
+ exists for Single-Precision operation. */
+
+ static void
+@@ -7426,6 +7455,24 @@ encode_arm_vfp_reg (int reg, enum vfp_re
+ static void
+ encode_arm_shift (int i)
+ {
++ /* Register-shifted register. */
++ if (inst.operands[i].immisreg)
++ {
++ int op_index;
++ for (op_index = 0; op_index <= i; ++op_index)
++ {
++ /* Check the operand only when it's presented. In pre-UAL syntax,
++ if the destination register is the same as the first operand, two
++ register form of the instruction can be used. */
++ if (inst.operands[op_index].present && inst.operands[op_index].isreg
++ && inst.operands[op_index].reg == REG_PC)
++ as_warn (UNPRED_REG ("r15"));
++ }
++
++ if (inst.operands[i].imm == REG_PC)
++ as_warn (UNPRED_REG ("r15"));
++ }
++
+ if (inst.operands[i].shift_kind == SHIFT_RRX)
+ inst.instruction |= SHIFT_ROR << 5;
+ else
+@@ -7930,17 +7977,13 @@ move_or_literal_pool (int i, enum lit_ty
+ {
+ if (thumb_p)
+ {
+- /* This can be encoded only for a low register. */
+- if ((v & ~0xFF) == 0 && (inst.operands[i].reg < 8))
+- {
+- /* This can be done with a mov(1) instruction. */
+- inst.instruction = T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8);
+- inst.instruction |= v;
+- return TRUE;
+- }
++ /* LDR should not use lead in a flag-setting instruction being
++ chosen so we do not check whether movs can be used. */
+
+- if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2)
++ if ((ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2)
+ || ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2_v8m))
++ && inst.operands[i].reg != 13
++ && inst.operands[i].reg != 15)
+ {
+ /* Check if on thumb2 it can be done with a mov.w, mvn or
+ movw instruction. */
+@@ -8326,6 +8369,12 @@ do_adr (void)
+ inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;
+ inst.reloc.pc_rel = 1;
+ inst.reloc.exp.X_add_number -= 8;
++
++ if (inst.reloc.exp.X_op == O_symbol
++ && inst.reloc.exp.X_add_symbol != NULL
++ && S_IS_DEFINED (inst.reloc.exp.X_add_symbol)
++ && THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol))
++ inst.reloc.exp.X_add_number += 1;
+ }
+
+ /* This is a pseudo-op of the form "adrl rd, label" to be converted
+@@ -8344,6 +8393,12 @@ do_adrl (void)
+ inst.reloc.pc_rel = 1;
+ inst.size = INSN_SIZE * 2;
+ inst.reloc.exp.X_add_number -= 8;
++
++ if (inst.reloc.exp.X_op == O_symbol
++ && inst.reloc.exp.X_add_symbol != NULL
++ && S_IS_DEFINED (inst.reloc.exp.X_add_symbol)
++ && THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol))
++ inst.reloc.exp.X_add_number += 1;
+ }
+
+ static void
+@@ -8622,7 +8677,7 @@ do_co_reg (void)
+ || inst.instruction == 0xfe000010)
+ /* MCR, MCR2 */
+ reject_bad_reg (Rd);
+- else
++ else if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
+ /* MRC, MRC2 */
+ constraint (Rd == REG_SP, BAD_SP);
+ }
+@@ -8691,6 +8746,14 @@ do_co_reg2c (void)
+ constraint (Rn == REG_PC, BAD_PC);
+ }
+
++ /* Only check the MRRC{2} variants. */
++ if ((inst.instruction & 0x0FF00000) == 0x0C500000)
++ {
++ /* If Rd == Rn, error that the operation is
++ unpredictable (example MRRC p3,#1,r1,r1,c4). */
++ constraint (Rd == Rn, BAD_OVERLAP);
++ }
++
+ inst.instruction |= inst.operands[0].reg << 8;
+ inst.instruction |= inst.operands[1].imm << 4;
+ inst.instruction |= Rd << 12;
+@@ -8916,7 +8979,7 @@ check_ldr_r15_aligned (void)
+ && (inst.operands[0].reg == REG_PC
+ && inst.operands[1].reg == REG_PC
+ && (inst.reloc.exp.X_add_number & 0x3)),
+- _("ldr to register 15 must be 4-byte alligned"));
++ _("ldr to register 15 must be 4-byte aligned"));
+ }
+
+ static void
+@@ -9025,9 +9088,9 @@ do_mov16 (void)
+
+ top = (inst.instruction & 0x00400000) != 0;
+ constraint (top && inst.reloc.type == BFD_RELOC_ARM_MOVW,
+- _(":lower16: not allowed this instruction"));
++ _(":lower16: not allowed in this instruction"));
+ constraint (!top && inst.reloc.type == BFD_RELOC_ARM_MOVT,
+- _(":upper16: not allowed instruction"));
++ _(":upper16: not allowed in this instruction"));
+ inst.instruction |= inst.operands[0].reg << 12;
+ if (inst.reloc.type == BFD_RELOC_UNUSED)
+ {
+@@ -9079,6 +9142,11 @@ do_vmrs (void)
+ return;
+ }
+
++ /* MVFR2 is only valid at ARMv8-A. */
++ if (inst.operands[1].reg == 5)
++ constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
++ _(BAD_FPU));
++
+ /* APSR_ sets isvec. All other refs to PC are illegal. */
+ if (!inst.operands[0].isvec && Rt == REG_PC)
+ {
+@@ -9105,6 +9173,11 @@ do_vmsr (void)
+ return;
+ }
+
++ /* MVFR2 is only valid for ARMv8-A. */
++ if (inst.operands[0].reg == 5)
++ constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
++ _(BAD_FPU));
++
+ /* If we get through parsing the register name, we just insert the number
+ generated into the instruction without further validation. */
+ inst.instruction |= (inst.operands[0].reg << 16);
+@@ -10453,7 +10526,7 @@ do_t_add_sub_w (void)
+ }
+
+ /* Parse an add or subtract instruction. We get here with inst.instruction
+- equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
++ equaling any of THUMB_OPCODE_add, adds, sub, or subs. */
+
+ static void
+ do_t_add_sub (void)
+@@ -10484,7 +10557,8 @@ do_t_add_sub (void)
+ {
+ int add;
+
+- constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);
++ if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
++ constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);
+
+ add = (inst.instruction == T_MNEM_add
+ || inst.instruction == T_MNEM_adds);
+@@ -10608,7 +10682,8 @@ do_t_add_sub (void)
+ }
+
+ constraint (Rd == REG_PC, BAD_PC);
+- constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);
++ if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
++ constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);
+ constraint (Rs == REG_PC, BAD_PC);
+ reject_bad_reg (Rn);
+
+@@ -10701,9 +10776,14 @@ do_t_adr (void)
+ inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;
+ inst.reloc.exp.X_add_number -= 4; /* PC relative adjust. */
+ inst.reloc.pc_rel = 1;
+-
+ inst.instruction |= Rd << 4;
+ }
++
++ if (inst.reloc.exp.X_op == O_symbol
++ && inst.reloc.exp.X_add_symbol != NULL
++ && S_IS_DEFINED (inst.reloc.exp.X_add_symbol)
++ && THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol))
++ inst.reloc.exp.X_add_number += 1;
+ }
+
+ /* Arithmetic instructions for which there is just one 16-bit
+@@ -11856,7 +11936,8 @@ do_t_mov_cmp (void)
+ /* This is mov.w. */
+ constraint (Rn == REG_PC, BAD_PC);
+ constraint (Rm == REG_PC, BAD_PC);
+- constraint (Rn == REG_SP && Rm == REG_SP, BAD_SP);
++ if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
++ constraint (Rn == REG_SP && Rm == REG_SP, BAD_SP);
+ }
+ }
+ else
+@@ -12082,12 +12163,12 @@ do_t_mov16 (void)
+ top = (inst.instruction & 0x00800000) != 0;
+ if (inst.reloc.type == BFD_RELOC_ARM_MOVW)
+ {
+- constraint (top, _(":lower16: not allowed this instruction"));
++ constraint (top, _(":lower16: not allowed in this instruction"));
+ inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVW;
+ }
+ else if (inst.reloc.type == BFD_RELOC_ARM_MOVT)
+ {
+- constraint (!top, _(":upper16: not allowed this instruction"));
++ constraint (!top, _(":upper16: not allowed in this instruction"));
+ inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVT;
+ }
+
+@@ -13049,17 +13130,6 @@ do_t_sxth (void)
+ static void
+ do_t_swi (void)
+ {
+- /* We have to do the following check manually as ARM_EXT_OS only applies
+- to ARM_EXT_V6M. */
+- if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6m))
+- {
+- if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_os)
+- /* This only applies to the v6m howver, not later architectures. */
+- && ! ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7))
+- as_bad (_("SVC is not permitted on this architecture"));
+- ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, arm_ext_os);
+- }
+-
+ inst.reloc.type = BFD_RELOC_ARM_SWI;
+ }
+
+@@ -13077,7 +13147,8 @@ do_t_tb (void)
+ Rn = inst.operands[0].reg;
+ Rm = inst.operands[0].imm;
+
+- constraint (Rn == REG_SP, BAD_SP);
++ if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))
++ constraint (Rn == REG_SP, BAD_SP);
+ reject_bad_reg (Rm);
+
+ constraint (!half && inst.operands[0].shifted,
+@@ -13317,6 +13388,8 @@ NEON_ENC_TAB
+ X(3, (D, Q, S), MIXED), \
+ X(4, (D, D, D, I), DOUBLE), \
+ X(4, (Q, Q, Q, I), QUAD), \
++ X(4, (D, D, S, I), DOUBLE), \
++ X(4, (Q, Q, S, I), QUAD), \
+ X(2, (F, F), SINGLE), \
+ X(3, (F, F, F), SINGLE), \
+ X(2, (F, I), SINGLE), \
+@@ -14390,6 +14463,11 @@ static void
+ do_vfp_nsyn_push (void)
+ {
+ nsyn_insert_sp ();
++
++ constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16,
++ _("register list must contain at least 1 and at most 16 "
++ "registers"));
++
+ if (inst.operands[1].issingle)
+ do_vfp_nsyn_opcode ("fstmdbs");
+ else
+@@ -14400,6 +14478,11 @@ static void
+ do_vfp_nsyn_pop (void)
+ {
+ nsyn_insert_sp ();
++
++ constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16,
++ _("register list must contain at least 1 and at most 16 "
++ "registers"));
++
+ if (inst.operands[1].issingle)
+ do_vfp_nsyn_opcode ("fldmias");
+ else
+@@ -14952,7 +15035,14 @@ do_neon_ceq (void)
+ scalars, which are encoded in 5 bits, M : Rm.
+ For 16-bit scalars, the register is encoded in Rm[2:0] and the index in
+ M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the
+- index in M. */
++ index in M.
++
++ Dot Product instructions are similar to multiply instructions except elsize
++ should always be 32.
++
++ This function translates SCALAR, which is GAS's internal encoding of indexed
++ scalar register, to raw encoding. There is also register and index range
++ check based on ELSIZE. */
+
+ static unsigned
+ neon_scalar_for_mul (unsigned scalar, unsigned elsize)
+@@ -17220,6 +17310,153 @@ do_vrintm (void)
+ do_vrint_1 (neon_cvt_mode_m);
+ }
+
++static unsigned
++neon_scalar_for_vcmla (unsigned opnd, unsigned elsize)
++{
++ unsigned regno = NEON_SCALAR_REG (opnd);
++ unsigned elno = NEON_SCALAR_INDEX (opnd);
++
++ if (elsize == 16 && elno < 2 && regno < 16)
++ return regno | (elno << 4);
++ else if (elsize == 32 && elno == 0)
++ return regno;
++
++ first_error (_("scalar out of range"));
++ return 0;
++}
++
++static void
++do_vcmla (void)
++{
++ constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_armv8),
++ _(BAD_FPU));
++ constraint (inst.reloc.exp.X_op != O_constant, _("expression too complex"));
++ unsigned rot = inst.reloc.exp.X_add_number;
++ constraint (rot != 0 && rot != 90 && rot != 180 && rot != 270,
++ _("immediate out of range"));
++ rot /= 90;
++ if (inst.operands[2].isscalar)
++ {
++ enum neon_shape rs = neon_select_shape (NS_DDSI, NS_QQSI, NS_NULL);
++ unsigned size = neon_check_type (3, rs, N_EQK, N_EQK,
++ N_KEY | N_F16 | N_F32).size;
++ unsigned m = neon_scalar_for_vcmla (inst.operands[2].reg, size);
++ inst.is_neon = 1;
++ inst.instruction = 0xfe000800;
++ inst.instruction |= LOW4 (inst.operands[0].reg) << 12;
++ inst.instruction |= HI1 (inst.operands[0].reg) << 22;
++ inst.instruction |= LOW4 (inst.operands[1].reg) << 16;
++ inst.instruction |= HI1 (inst.operands[1].reg) << 7;
++ inst.instruction |= LOW4 (m);
++ inst.instruction |= HI1 (m) << 5;
++ inst.instruction |= neon_quad (rs) << 6;
++ inst.instruction |= rot << 20;
++ inst.instruction |= (size == 32) << 23;
++ }
++ else
++ {
++ enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL);
++ unsigned size = neon_check_type (3, rs, N_EQK, N_EQK,
++ N_KEY | N_F16 | N_F32).size;
++ neon_three_same (neon_quad (rs), 0, -1);
++ inst.instruction &= 0x00ffffff; /* Undo neon_dp_fixup. */
++ inst.instruction |= 0xfc200800;
++ inst.instruction |= rot << 23;
++ inst.instruction |= (size == 32) << 20;
++ }
++}
++
++static void
++do_vcadd (void)
++{
++ constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_armv8),
++ _(BAD_FPU));
++ constraint (inst.reloc.exp.X_op != O_constant, _("expression too complex"));
++ unsigned rot = inst.reloc.exp.X_add_number;
++ constraint (rot != 90 && rot != 270, _("immediate out of range"));
++ enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL);
++ unsigned size = neon_check_type (3, rs, N_EQK, N_EQK,
++ N_KEY | N_F16 | N_F32).size;
++ neon_three_same (neon_quad (rs), 0, -1);
++ inst.instruction &= 0x00ffffff; /* Undo neon_dp_fixup. */
++ inst.instruction |= 0xfc800800;
++ inst.instruction |= (rot == 270) << 24;
++ inst.instruction |= (size == 32) << 20;
++}
++
++/* Dot Product instructions encoding support. */
++
++static void
++do_neon_dotproduct (int unsigned_p)
++{
++ enum neon_shape rs;
++ unsigned scalar_oprd2 = 0;
++ int high8;
++
++ if (inst.cond != COND_ALWAYS)
++ as_warn (_("Dot Product instructions cannot be conditional, the behaviour "
++ "is UNPREDICTABLE"));
++
++ constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_armv8),
++ _(BAD_FPU));
++
++ /* Dot Product instructions are in three-same D/Q register format or the third
++ operand can be a scalar index register. */
++ if (inst.operands[2].isscalar)
++ {
++ scalar_oprd2 = neon_scalar_for_mul (inst.operands[2].reg, 32);
++ high8 = 0xfe000000;
++ rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);
++ }
++ else
++ {
++ high8 = 0xfc000000;
++ rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);
++ }
++
++ if (unsigned_p)
++ neon_check_type (3, rs, N_EQK, N_EQK, N_KEY | N_U8);
++ else
++ neon_check_type (3, rs, N_EQK, N_EQK, N_KEY | N_S8);
++
++ /* The "U" bit in traditional Three Same encoding is fixed to 0 for Dot
++ Product instruction, so we pass 0 as the "ubit" parameter. And the
++ "Size" field are fixed to 0x2, so we pass 32 as the "size" parameter. */
++ neon_three_same (neon_quad (rs), 0, 32);
++
++ /* Undo neon_dp_fixup. Dot Product instructions are using a slightly
++ different NEON three-same encoding. */
++ inst.instruction &= 0x00ffffff;
++ inst.instruction |= high8;
++ /* Encode 'U' bit which indicates signedness. */
++ inst.instruction |= (unsigned_p ? 1 : 0) << 4;
++ /* Re-encode operand2 if it's indexed scalar operand. What has been encoded
++ from inst.operand[2].reg in neon_three_same is GAS's internal encoding, not
++ the instruction encoding. */
++ if (inst.operands[2].isscalar)
++ {
++ inst.instruction &= 0xffffffd0;
++ inst.instruction |= LOW4 (scalar_oprd2);
++ inst.instruction |= HI1 (scalar_oprd2) << 5;
++ }
++}
++
++/* Dot Product instructions for signed integer. */
++
++static void
++do_neon_dotproduct_s (void)
++{
++ return do_neon_dotproduct (0);
++}
++
++/* Dot Product instructions for unsigned integer. */
++
++static void
++do_neon_dotproduct_u (void)
++{
++ return do_neon_dotproduct (1);
++}
++
+ /* Crypto v1 instructions. */
+ static void
+ do_crypto_2op_1 (unsigned elttype, int op)
+@@ -17401,6 +17638,16 @@ do_crc32cw (void)
+ do_crc32_1 (1, 2);
+ }
+
++static void
++do_vjcvt (void)
++{
++ constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),
++ _(BAD_FPU));
++ neon_check_type (2, NS_FD, N_S32, N_F64);
++ do_vfp_sp_dp_cvt ();
++ do_vfp_cond_or_thumb ();
++}
++
+
+ /* Overall per-instruction processing. */
+
+@@ -17755,7 +18002,7 @@ opcode_lookup (char **str)
+ case OT_odd_infix_unc:
+ if (!unified_syntax)
+ return 0;
+- /* else fall through */
++ /* Fall through. */
+
+ case OT_csuffix:
+ case OT_csuffixF:
+@@ -17878,7 +18125,7 @@ now_it_add_mask (int cond)
+ set_it_insn_type_last () ditto
+ in_it_block () ditto
+ it_fsm_post_encode () from md_assemble ()
+- force_automatic_it_block_close () from label habdling functions
++ force_automatic_it_block_close () from label handling functions
+
+ Rationale:
+ 1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
+@@ -17911,7 +18158,7 @@ now_it_add_mask (int cond)
+ for covering other cases.
+
+ Calling handle_it_state () may not transition the IT block state to
+- OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be
++ OUTSIDE_IT_BLOCK immediately, since the (current) state could be
+ still queried. Instead, if the FSM determines that the state should
+ be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed
+ after the tencode () function: that's what it_fsm_post_encode () does.
+@@ -18002,7 +18249,7 @@ handle_it_state (void)
+ switch (inst.it_insn_type)
+ {
+ case OUTSIDE_IT_INSN:
+- /* The closure of the block shall happen immediatelly,
++ /* The closure of the block shall happen immediately,
+ so any in_it_block () call reports the block as closed. */
+ force_automatic_it_block_close ();
+ break;
+@@ -18236,6 +18483,13 @@ t32_insn_ok (arm_feature_set arch, const
+ && opcode->tencode == do_t_branch)
+ return TRUE;
+
++ /* MOV accepts T1/T3 encodings under Baseline, T3 encoding is 32bit. */
++ if (ARM_CPU_HAS_FEATURE (arch, arm_ext_v8m)
++ && opcode->tencode == do_t_mov_cmp
++ /* Make sure CMP instruction is not affected. */
++ && opcode->aencode == do_mov)
++ return TRUE;
++
+ /* Wide instruction variants of all instructions with narrow *and* wide
+ variants become available with ARMv6t2. Other opcodes are either
+ narrow-only or wide-only and are thus available if OPCODE is valid. */
+@@ -18296,7 +18550,10 @@ md_assemble (char *str)
+ || (thumb_mode == 1
+ && !ARM_CPU_HAS_FEATURE (variant, *opcode->tvariant)))
+ {
+- as_bad (_("selected processor does not support `%s' in Thumb mode"), str);
++ if (opcode->tencode == do_t_swi)
++ as_bad (_("SVC is not permitted on this architecture"));
++ else
++ as_bad (_("selected processor does not support `%s' in Thumb mode"), str);
+ return;
+ }
+ if (inst.cond != COND_ALWAYS && !unified_syntax
+@@ -18663,6 +18920,7 @@ static const struct reg_entry reg_names[
+ REGDEF(FPINST,9,VFC), REGDEF(FPINST2,10,VFC),
+ REGDEF(mvfr0,7,VFC), REGDEF(mvfr1,6,VFC),
+ REGDEF(MVFR0,7,VFC), REGDEF(MVFR1,6,VFC),
++ REGDEF(mvfr2,5,VFC), REGDEF(MVFR2,5,VFC),
+
+ /* Maverick DSP coprocessor registers. */
+ REGSET(mvf,MVF), REGSET(mvd,MVD), REGSET(mvfx,MVFX), REGSET(mvdx,MVDX),
+@@ -18780,24 +19038,32 @@ static const struct asm_psr psrs[] =
+ /* Table of V7M psr names. */
+ static const struct asm_psr v7m_psrs[] =
+ {
+- {"apsr", 0 }, {"APSR", 0 },
+- {"iapsr", 1 }, {"IAPSR", 1 },
+- {"eapsr", 2 }, {"EAPSR", 2 },
+- {"psr", 3 }, {"PSR", 3 },
+- {"xpsr", 3 }, {"XPSR", 3 }, {"xPSR", 3 },
+- {"ipsr", 5 }, {"IPSR", 5 },
+- {"epsr", 6 }, {"EPSR", 6 },
+- {"iepsr", 7 }, {"IEPSR", 7 },
+- {"msp", 8 }, {"MSP", 8 }, {"msp_s", 8 }, {"MSP_S", 8 },
+- {"psp", 9 }, {"PSP", 9 }, {"psp_s", 9 }, {"PSP_S", 9 },
+- {"primask", 16}, {"PRIMASK", 16},
+- {"basepri", 17}, {"BASEPRI", 17},
+- {"basepri_max", 18}, {"BASEPRI_MAX", 18},
+- {"basepri_max", 18}, {"BASEPRI_MASK", 18}, /* Typo, preserved for backwards compatibility. */
+- {"faultmask", 19}, {"FAULTMASK", 19},
+- {"control", 20}, {"CONTROL", 20},
+- {"msp_ns", 0x88}, {"MSP_NS", 0x88},
+- {"psp_ns", 0x89}, {"PSP_NS", 0x89}
++ {"apsr", 0x0 }, {"APSR", 0x0 },
++ {"iapsr", 0x1 }, {"IAPSR", 0x1 },
++ {"eapsr", 0x2 }, {"EAPSR", 0x2 },
++ {"psr", 0x3 }, {"PSR", 0x3 },
++ {"xpsr", 0x3 }, {"XPSR", 0x3 }, {"xPSR", 3 },
++ {"ipsr", 0x5 }, {"IPSR", 0x5 },
++ {"epsr", 0x6 }, {"EPSR", 0x6 },
++ {"iepsr", 0x7 }, {"IEPSR", 0x7 },
++ {"msp", 0x8 }, {"MSP", 0x8 },
++ {"psp", 0x9 }, {"PSP", 0x9 },
++ {"msplim", 0xa }, {"MSPLIM", 0xa },
++ {"psplim", 0xb }, {"PSPLIM", 0xb },
++ {"primask", 0x10}, {"PRIMASK", 0x10},
++ {"basepri", 0x11}, {"BASEPRI", 0x11},
++ {"basepri_max", 0x12}, {"BASEPRI_MAX", 0x12},
++ {"faultmask", 0x13}, {"FAULTMASK", 0x13},
++ {"control", 0x14}, {"CONTROL", 0x14},
++ {"msp_ns", 0x88}, {"MSP_NS", 0x88},
++ {"psp_ns", 0x89}, {"PSP_NS", 0x89},
++ {"msplim_ns", 0x8a}, {"MSPLIM_NS", 0x8a},
++ {"psplim_ns", 0x8b}, {"PSPLIM_NS", 0x8b},
++ {"primask_ns", 0x90}, {"PRIMASK_NS", 0x90},
++ {"basepri_ns", 0x91}, {"BASEPRI_NS", 0x91},
++ {"faultmask_ns", 0x93}, {"FAULTMASK_NS", 0x93},
++ {"control_ns", 0x94}, {"CONTROL_NS", 0x94},
++ {"sp_ns", 0x98}, {"SP_NS", 0x98 }
+ };
+
+ /* Table of all shift-in-operand names. */
+@@ -19112,8 +19378,6 @@ static const struct asm_opcode insns[] =
+ tC3("ldmia", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
+ tC3("ldmfd", 8900000, _ldmia, 2, (RRw, REGLST), ldmstm, t_ldmstm),
+
+- TCE("swi", f000000, df00, 1, (EXPi), swi, t_swi),
+- TCE("svc", f000000, df00, 1, (EXPi), swi, t_swi),
+ tCE("b", a000000, _b, 1, (EXPr), branch, t_branch),
+ TCE("bl", b000000, f000f800, 1, (EXPr), bl, t_branch23),
+
+@@ -19142,6 +19406,12 @@ static const struct asm_opcode insns[] =
+ TC3("rsbs", 0700000, ebd00000, 3, (RR, oRR, SH), arit, t_rsb),
+
+ #undef THUMB_VARIANT
++#define THUMB_VARIANT & arm_ext_os
++
++ TCE("swi", f000000, df00, 1, (EXPi), swi, t_swi),
++ TCE("svc", f000000, df00, 1, (EXPi), swi, t_swi),
++
++#undef THUMB_VARIANT
+ #define THUMB_VARIANT & arm_ext_v6
+
+ TCE("cpy", 1a00000, 4600, 2, (RR, RR), rd_rm, t_cpy),
+@@ -19729,6 +19999,21 @@ static const struct asm_opcode insns[] =
+ TUE ("esb", 320f010, f3af8010, 0, (), noargs, noargs),
+
+ #undef ARM_VARIANT
++#define ARM_VARIANT & arm_ext_v8_3
++#undef THUMB_VARIANT
++#define THUMB_VARIANT & arm_ext_v8_3
++ NCE (vjcvt, eb90bc0, 2, (RVS, RVD), vjcvt),
++ NUF (vcmla, 0, 4, (RNDQ, RNDQ, RNDQ_RNSC, EXPi), vcmla),
++ NUF (vcadd, 0, 4, (RNDQ, RNDQ, RNDQ, EXPi), vcadd),
++
++#undef ARM_VARIANT
++#define ARM_VARIANT & fpu_neon_ext_dotprod
++#undef THUMB_VARIANT
++#define THUMB_VARIANT & fpu_neon_ext_dotprod
++ NUF (vsdot, d00, 3, (RNDQ, RNDQ, RNDQ_RNSC), neon_dotproduct_s),
++ NUF (vudot, d00, 3, (RNDQ, RNDQ, RNDQ_RNSC), neon_dotproduct_u),
++
++#undef ARM_VARIANT
+ #define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
+ #undef THUMB_VARIANT
+ #define THUMB_VARIANT NULL
+@@ -21706,7 +21991,7 @@ arm_frag_align_code (int n, int max)
+ Note - despite the name this initialisation is not done when the frag
+ is created, but only when its type is assigned. A frag can be created
+ and used a long time before its type is set, so beware of assuming that
+- this initialisationis performed first. */
++ this initialisation is performed first. */
+
+ #ifndef OBJ_ELF
+ void
+@@ -21720,7 +22005,7 @@ arm_init_frag (fragS * fragP, int max_ch
+ void
+ arm_init_frag (fragS * fragP, int max_chars)
+ {
+- int frag_thumb_mode;
++ bfd_boolean frag_thumb_mode;
+
+ /* If the current ARM vs THUMB mode has not already
+ been recorded into this frag then do so now. */
+@@ -22731,6 +23016,23 @@ md_apply_fix (fixS * fixP,
+ changing the opcode. */
+ if (newimm == (unsigned int) FAIL)
+ newimm = negate_data_op (&temp, value);
++ /* MOV accepts both ARM modified immediate (A1 encoding) and
++ UINT16 (A2 encoding) when possible, MOVW only accepts UINT16.
++ When disassembling, MOV is preferred when there is no encoding
++ overlap. */
++ if (newimm == (unsigned int) FAIL
++ && ((temp >> DATA_OP_SHIFT) & 0xf) == OPCODE_MOV
++ && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2)
++ && !((temp >> SBIT_SHIFT) & 0x1)
++ && value >= 0 && value <= 0xffff)
++ {
++ /* Clear bits[23:20] to change encoding from A1 to A2. */
++ temp &= 0xff0fffff;
++ /* Encoding high 4bits imm. Code below will encode the remaining
++ low 12bits. */
++ temp |= (value & 0x0000f000) << 4;
++ newimm = value & 0x00000fff;
++ }
+ }
+
+ if (newimm == (unsigned int) FAIL)
+@@ -22816,6 +23118,7 @@ md_apply_fix (fixS * fixP,
+ case BFD_RELOC_ARM_OFFSET_IMM:
+ if (!fixP->fx_done && seg->use_rela_p)
+ value = 0;
++ /* Fall through. */
+
+ case BFD_RELOC_ARM_LITERAL:
+ sign = value > 0;
+@@ -23046,32 +23349,59 @@ md_apply_fix (fixS * fixP,
+ newval |= md_chars_to_number (buf+2, THUMB_SIZE);
+
+ newimm = FAIL;
+- if (fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
++ if ((fixP->fx_r_type == BFD_RELOC_ARM_T32_IMMEDIATE
++ /* ARMv8-M Baseline MOV will reach here, but it doesn't support
++ Thumb2 modified immediate encoding (T2). */
++ && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2))
+ || fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
+ {
+ newimm = encode_thumb32_immediate (value);
+ if (newimm == (unsigned int) FAIL)
+ newimm = thumb32_negate_data_op (&newval, value);
+ }
+- if (fixP->fx_r_type != BFD_RELOC_ARM_T32_IMMEDIATE
+- && newimm == (unsigned int) FAIL)
++ if (newimm == (unsigned int) FAIL)
+ {
+- /* Turn add/sum into addw/subw. */
+- if (fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
+- newval = (newval & 0xfeffffff) | 0x02000000;
+- /* No flat 12-bit imm encoding for addsw/subsw. */
+- if ((newval & 0x00100000) == 0)
++ if (fixP->fx_r_type != BFD_RELOC_ARM_T32_IMMEDIATE)
+ {
+- /* 12 bit immediate for addw/subw. */
+- if (value < 0)
++ /* Turn add/sum into addw/subw. */
++ if (fixP->fx_r_type == BFD_RELOC_ARM_T32_ADD_IMM)
++ newval = (newval & 0xfeffffff) | 0x02000000;
++ /* No flat 12-bit imm encoding for addsw/subsw. */
++ if ((newval & 0x00100000) == 0)
+ {
+- value = -value;
+- newval ^= 0x00a00000;
++ /* 12 bit immediate for addw/subw. */
++ if (value < 0)
++ {
++ value = -value;
++ newval ^= 0x00a00000;
++ }
++ if (value > 0xfff)
++ newimm = (unsigned int) FAIL;
++ else
++ newimm = value;
++ }
++ }
++ else
++ {
++ /* MOV accepts both Thumb2 modified immediate (T2 encoding) and
++ UINT16 (T3 encoding), MOVW only accepts UINT16. When
++ disassembling, MOV is preferred when there is no encoding
++ overlap.
++ NOTE: MOV is using ORR opcode under Thumb 2 mode. */
++ if (((newval >> T2_DATA_OP_SHIFT) & 0xf) == T2_OPCODE_ORR
++ && ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2_v8m)
++ && !((newval >> T2_SBIT_SHIFT) & 0x1)
++ && value >= 0 && value <=0xffff)
++ {
++ /* Toggle bit[25] to change encoding from T2 to T3. */
++ newval ^= 1 << 25;
++ /* Clear bits[19:16]. */
++ newval &= 0xfff0ffff;
++ /* Encoding high 4bits imm. Code below will encode the
++ remaining low 12bits. */
++ newval |= (value & 0x0000f000) << 4;
++ newimm = value & 0x00000fff;
+ }
+- if (value > 0xfff)
+- newimm = (unsigned int) FAIL;
+- else
+- newimm = value;
+ }
+ }
+
+@@ -23174,6 +23504,7 @@ md_apply_fix (fixS * fixP,
+ newval = md_chars_to_number (buf, INSN_SIZE);
+ fixP->fx_done = 0;
+ }
++ /* Fall through. */
+
+ case BFD_RELOC_ARM_PLT32:
+ #endif
+@@ -23210,7 +23541,7 @@ md_apply_fix (fixS * fixP,
+ /* We are going to store value (shifted right by two) in the
+ instruction, in a 24 bit, signed field. Bits 26 through 32 either
+ all clear or all set and bit 0 must be clear. For B/BL bit 1 must
+- also be be clear. */
++ also be clear. */
+ if (value & temp)
+ as_bad_where (fixP->fx_file, fixP->fx_line,
+ _("misaligned branch destination"));
+@@ -24066,6 +24397,7 @@ tc_gen_reloc (asection *section, fixS *f
+ code = BFD_RELOC_8_PCREL;
+ break;
+ }
++ /* Fall through. */
+
+ case BFD_RELOC_16:
+ if (fixp->fx_pcrel)
+@@ -24073,6 +24405,7 @@ tc_gen_reloc (asection *section, fixS *f
+ code = BFD_RELOC_16_PCREL;
+ break;
+ }
++ /* Fall through. */
+
+ case BFD_RELOC_32:
+ if (fixp->fx_pcrel)
+@@ -24080,6 +24413,7 @@ tc_gen_reloc (asection *section, fixS *f
+ code = BFD_RELOC_32_PCREL;
+ break;
+ }
++ /* Fall through. */
+
+ case BFD_RELOC_ARM_MOVW:
+ if (fixp->fx_pcrel)
+@@ -24087,6 +24421,7 @@ tc_gen_reloc (asection *section, fixS *f
+ code = BFD_RELOC_ARM_MOVW_PCREL;
+ break;
+ }
++ /* Fall through. */
+
+ case BFD_RELOC_ARM_MOVT:
+ if (fixp->fx_pcrel)
+@@ -24094,6 +24429,7 @@ tc_gen_reloc (asection *section, fixS *f
+ code = BFD_RELOC_ARM_MOVT_PCREL;
+ break;
+ }
++ /* Fall through. */
+
+ case BFD_RELOC_ARM_THUMB_MOVW:
+ if (fixp->fx_pcrel)
+@@ -24101,6 +24437,7 @@ tc_gen_reloc (asection *section, fixS *f
+ code = BFD_RELOC_ARM_THUMB_MOVW_PCREL;
+ break;
+ }
++ /* Fall through. */
+
+ case BFD_RELOC_ARM_THUMB_MOVT:
+ if (fixp->fx_pcrel)
+@@ -24108,6 +24445,7 @@ tc_gen_reloc (asection *section, fixS *f
+ code = BFD_RELOC_ARM_THUMB_MOVT_PCREL;
+ break;
+ }
++ /* Fall through. */
+
+ case BFD_RELOC_NONE:
+ case BFD_RELOC_ARM_PCREL_BRANCH:
+@@ -24791,7 +25129,12 @@ md_begin (void)
+ mcpu_cpu_opt = legacy_cpu;
+ }
+ else if (!mcpu_cpu_opt)
+- mcpu_cpu_opt = march_cpu_opt;
++ {
++ mcpu_cpu_opt = march_cpu_opt;
++ dyn_mcpu_ext_opt = dyn_march_ext_opt;
++ /* Avoid double free in arm_md_end. */
++ dyn_march_ext_opt = NULL;
++ }
+
+ if (legacy_fpu)
+ {
+@@ -24831,16 +25174,22 @@ md_begin (void)
+ mcpu_cpu_opt = &cpu_default;
+ selected_cpu = cpu_default;
+ }
+- else if (no_cpu_selected ())
+- selected_cpu = cpu_default;
++ else if (dyn_mcpu_ext_opt)
++ ARM_MERGE_FEATURE_SETS (selected_cpu, *mcpu_cpu_opt, *dyn_mcpu_ext_opt);
++ else
++ selected_cpu = *mcpu_cpu_opt;
+ #else
+- if (mcpu_cpu_opt)
++ if (mcpu_cpu_opt && dyn_mcpu_ext_opt)
++ ARM_MERGE_FEATURE_SETS (selected_cpu, *mcpu_cpu_opt, *dyn_mcpu_ext_opt);
++ else if (mcpu_cpu_opt)
+ selected_cpu = *mcpu_cpu_opt;
+ else
+ mcpu_cpu_opt = &arm_arch_any;
+ #endif
+
+ ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
++ if (dyn_mcpu_ext_opt)
++ ARM_MERGE_FEATURE_SETS (cpu_variant, cpu_variant, *dyn_mcpu_ext_opt);
+
+ autoselect_thumb_from_cpu_variant ();
+
+@@ -25215,6 +25564,7 @@ struct arm_cpu_option_table
+ const char *name;
+ size_t name_len;
+ const arm_feature_set value;
++ const arm_feature_set ext;
+ /* For some CPUs we assume an FPU unless the user explicitly sets
+ -mfpu=... */
+ const arm_feature_set default_fpu;
+@@ -25225,174 +25575,387 @@ struct arm_cpu_option_table
+
+ /* This list should, at a minimum, contain all the cpu names
+ recognized by GCC. */
+-#define ARM_CPU_OPT(N, V, DF, CN) { N, sizeof (N) - 1, V, DF, CN }
++#define ARM_CPU_OPT(N, CN, V, E, DF) { N, sizeof (N) - 1, V, E, DF, CN }
+ static const struct arm_cpu_option_table arm_cpus[] =
+ {
+- ARM_CPU_OPT ("all", ARM_ANY, FPU_ARCH_FPA, NULL),
+- ARM_CPU_OPT ("arm1", ARM_ARCH_V1, FPU_ARCH_FPA, NULL),
+- ARM_CPU_OPT ("arm2", ARM_ARCH_V2, FPU_ARCH_FPA, NULL),
+- ARM_CPU_OPT ("arm250", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL),
+- ARM_CPU_OPT ("arm3", ARM_ARCH_V2S, FPU_ARCH_FPA, NULL),
+- ARM_CPU_OPT ("arm6", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
+- ARM_CPU_OPT ("arm60", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
+- ARM_CPU_OPT ("arm600", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
+- ARM_CPU_OPT ("arm610", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
+- ARM_CPU_OPT ("arm620", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
+- ARM_CPU_OPT ("arm7", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
+- ARM_CPU_OPT ("arm7m", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL),
+- ARM_CPU_OPT ("arm7d", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
+- ARM_CPU_OPT ("arm7dm", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL),
+- ARM_CPU_OPT ("arm7di", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
+- ARM_CPU_OPT ("arm7dmi", ARM_ARCH_V3M, FPU_ARCH_FPA, NULL),
+- ARM_CPU_OPT ("arm70", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
+- ARM_CPU_OPT ("arm700", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
+- ARM_CPU_OPT ("arm700i", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
+- ARM_CPU_OPT ("arm710", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
+- ARM_CPU_OPT ("arm710t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
+- ARM_CPU_OPT ("arm720", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
+- ARM_CPU_OPT ("arm720t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
+- ARM_CPU_OPT ("arm740t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
+- ARM_CPU_OPT ("arm710c", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
+- ARM_CPU_OPT ("arm7100", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
+- ARM_CPU_OPT ("arm7500", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
+- ARM_CPU_OPT ("arm7500fe", ARM_ARCH_V3, FPU_ARCH_FPA, NULL),
+- ARM_CPU_OPT ("arm7t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
+- ARM_CPU_OPT ("arm7tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
+- ARM_CPU_OPT ("arm7tdmi-s", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
+- ARM_CPU_OPT ("arm8", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
+- ARM_CPU_OPT ("arm810", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
+- ARM_CPU_OPT ("strongarm", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
+- ARM_CPU_OPT ("strongarm1", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
+- ARM_CPU_OPT ("strongarm110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
+- ARM_CPU_OPT ("strongarm1100", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
+- ARM_CPU_OPT ("strongarm1110", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
+- ARM_CPU_OPT ("arm9", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
+- ARM_CPU_OPT ("arm920", ARM_ARCH_V4T, FPU_ARCH_FPA, "ARM920T"),
+- ARM_CPU_OPT ("arm920t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
+- ARM_CPU_OPT ("arm922t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
+- ARM_CPU_OPT ("arm940t", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
+- ARM_CPU_OPT ("arm9tdmi", ARM_ARCH_V4T, FPU_ARCH_FPA, NULL),
+- ARM_CPU_OPT ("fa526", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
+- ARM_CPU_OPT ("fa626", ARM_ARCH_V4, FPU_ARCH_FPA, NULL),
++ ARM_CPU_OPT ("all", NULL, ARM_ANY,
++ ARM_ARCH_NONE,
++ FPU_ARCH_FPA),
++ ARM_CPU_OPT ("arm1", NULL, ARM_ARCH_V1,
++ ARM_ARCH_NONE,
++ FPU_ARCH_FPA),
++ ARM_CPU_OPT ("arm2", NULL, ARM_ARCH_V2,
++ ARM_ARCH_NONE,
++ FPU_ARCH_FPA),
++ ARM_CPU_OPT ("arm250", NULL, ARM_ARCH_V2S,
++ ARM_ARCH_NONE,
++ FPU_ARCH_FPA),
++ ARM_CPU_OPT ("arm3", NULL, ARM_ARCH_V2S,
++ ARM_ARCH_NONE,
++ FPU_ARCH_FPA),
++ ARM_CPU_OPT ("arm6", NULL, ARM_ARCH_V3,
++ ARM_ARCH_NONE,
++ FPU_ARCH_FPA),
++ ARM_CPU_OPT ("arm60", NULL, ARM_ARCH_V3,
++ ARM_ARCH_NONE,
++ FPU_ARCH_FPA),
++ ARM_CPU_OPT ("arm600", NULL, ARM_ARCH_V3,
++ ARM_ARCH_NONE,
++ FPU_ARCH_FPA),
++ ARM_CPU_OPT ("arm610", NULL, ARM_ARCH_V3,
++ ARM_ARCH_NONE,
++ FPU_ARCH_FPA),
++ ARM_CPU_OPT ("arm620", NULL, ARM_ARCH_V3,
++ ARM_ARCH_NONE,
++ FPU_ARCH_FPA),
++ ARM_CPU_OPT ("arm7", NULL, ARM_ARCH_V3,
++ ARM_ARCH_NONE,
++ FPU_ARCH_FPA),
++ ARM_CPU_OPT ("arm7m", NULL, ARM_ARCH_V3M,
++ ARM_ARCH_NONE,
++ FPU_ARCH_FPA),
++ ARM_CPU_OPT ("arm7d", NULL, ARM_ARCH_V3,
++ ARM_ARCH_NONE,
++ FPU_ARCH_FPA),
++ ARM_CPU_OPT ("arm7dm", NULL, ARM_ARCH_V3M,
++ ARM_ARCH_NONE,
++ FPU_ARCH_FPA),
++ ARM_CPU_OPT ("arm7di", NULL, ARM_ARCH_V3,
++ ARM_ARCH_NONE,
++ FPU_ARCH_FPA),
++ ARM_CPU_OPT ("arm7dmi", NULL, ARM_ARCH_V3M,
++ ARM_ARCH_NONE,
++ FPU_ARCH_FPA),
++ ARM_CPU_OPT ("arm70", NULL, ARM_ARCH_V3,
++ ARM_ARCH_NONE,
++ FPU_ARCH_FPA),
++ ARM_CPU_OPT ("arm700", NULL, ARM_ARCH_V3,
++ ARM_ARCH_NONE,
++ FPU_ARCH_FPA),
++ ARM_CPU_OPT ("arm700i", NULL, ARM_ARCH_V3,
++ ARM_ARCH_NONE,
++ FPU_ARCH_FPA),
++ ARM_CPU_OPT ("arm710", NULL, ARM_ARCH_V3,
++ ARM_ARCH_NONE,
++ FPU_ARCH_FPA),
++ ARM_CPU_OPT ("arm710t", NULL, ARM_ARCH_V4T,
++ ARM_ARCH_NONE,
++ FPU_ARCH_FPA),
++ ARM_CPU_OPT ("arm720", NULL, ARM_ARCH_V3,
++ ARM_ARCH_NONE,
++ FPU_ARCH_FPA),
++ ARM_CPU_OPT ("arm720t", NULL, ARM_ARCH_V4T,
++ ARM_ARCH_NONE,
++ FPU_ARCH_FPA),
++ ARM_CPU_OPT ("arm740t", NULL, ARM_ARCH_V4T,
++ ARM_ARCH_NONE,
++ FPU_ARCH_FPA),
++ ARM_CPU_OPT ("arm710c", NULL, ARM_ARCH_V3,
++ ARM_ARCH_NONE,
++ FPU_ARCH_FPA),
++ ARM_CPU_OPT ("arm7100", NULL, ARM_ARCH_V3,
++ ARM_ARCH_NONE,
++ FPU_ARCH_FPA),
++ ARM_CPU_OPT ("arm7500", NULL, ARM_ARCH_V3,
++ ARM_ARCH_NONE,
++ FPU_ARCH_FPA),
++ ARM_CPU_OPT ("arm7500fe", NULL, ARM_ARCH_V3,
++ ARM_ARCH_NONE,
++ FPU_ARCH_FPA),
++ ARM_CPU_OPT ("arm7t", NULL, ARM_ARCH_V4T,
++ ARM_ARCH_NONE,
++ FPU_ARCH_FPA),
++ ARM_CPU_OPT ("arm7tdmi", NULL, ARM_ARCH_V4T,
++ ARM_ARCH_NONE,
++ FPU_ARCH_FPA),
++ ARM_CPU_OPT ("arm7tdmi-s", NULL, ARM_ARCH_V4T,
++ ARM_ARCH_NONE,
++ FPU_ARCH_FPA),
++ ARM_CPU_OPT ("arm8", NULL, ARM_ARCH_V4,
++ ARM_ARCH_NONE,
++ FPU_ARCH_FPA),
++ ARM_CPU_OPT ("arm810", NULL, ARM_ARCH_V4,
++ ARM_ARCH_NONE,
++ FPU_ARCH_FPA),
++ ARM_CPU_OPT ("strongarm", NULL, ARM_ARCH_V4,
++ ARM_ARCH_NONE,
++ FPU_ARCH_FPA),
++ ARM_CPU_OPT ("strongarm1", NULL, ARM_ARCH_V4,
++ ARM_ARCH_NONE,
++ FPU_ARCH_FPA),
++ ARM_CPU_OPT ("strongarm110", NULL, ARM_ARCH_V4,
++ ARM_ARCH_NONE,
++ FPU_ARCH_FPA),
++ ARM_CPU_OPT ("strongarm1100", NULL, ARM_ARCH_V4,
++ ARM_ARCH_NONE,
++ FPU_ARCH_FPA),
++ ARM_CPU_OPT ("strongarm1110", NULL, ARM_ARCH_V4,
++ ARM_ARCH_NONE,
++ FPU_ARCH_FPA),
++ ARM_CPU_OPT ("arm9", NULL, ARM_ARCH_V4T,
++ ARM_ARCH_NONE,
++ FPU_ARCH_FPA),
++ ARM_CPU_OPT ("arm920", "ARM920T", ARM_ARCH_V4T,
++ ARM_ARCH_NONE,
++ FPU_ARCH_FPA),
++ ARM_CPU_OPT ("arm920t", NULL, ARM_ARCH_V4T,
++ ARM_ARCH_NONE,
++ FPU_ARCH_FPA),
++ ARM_CPU_OPT ("arm922t", NULL, ARM_ARCH_V4T,
++ ARM_ARCH_NONE,
++ FPU_ARCH_FPA),
++ ARM_CPU_OPT ("arm940t", NULL, ARM_ARCH_V4T,
++ ARM_ARCH_NONE,
++ FPU_ARCH_FPA),
++ ARM_CPU_OPT ("arm9tdmi", NULL, ARM_ARCH_V4T,
++ ARM_ARCH_NONE,
++ FPU_ARCH_FPA),
++ ARM_CPU_OPT ("fa526", NULL, ARM_ARCH_V4,
++ ARM_ARCH_NONE,
++ FPU_ARCH_FPA),
++ ARM_CPU_OPT ("fa626", NULL, ARM_ARCH_V4,
++ ARM_ARCH_NONE,
++ FPU_ARCH_FPA),
++
+ /* For V5 or later processors we default to using VFP; but the user
+ should really set the FPU type explicitly. */
+- ARM_CPU_OPT ("arm9e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL),
+- ARM_CPU_OPT ("arm9e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
+- ARM_CPU_OPT ("arm926ej", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"),
+- ARM_CPU_OPT ("arm926ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, "ARM926EJ-S"),
+- ARM_CPU_OPT ("arm926ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL),
+- ARM_CPU_OPT ("arm946e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL),
+- ARM_CPU_OPT ("arm946e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM946E-S"),
+- ARM_CPU_OPT ("arm946e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
+- ARM_CPU_OPT ("arm966e-r0", ARM_ARCH_V5TExP, FPU_ARCH_VFP_V2, NULL),
+- ARM_CPU_OPT ("arm966e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM966E-S"),
+- ARM_CPU_OPT ("arm966e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
+- ARM_CPU_OPT ("arm968e-s", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
+- ARM_CPU_OPT ("arm10t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL),
+- ARM_CPU_OPT ("arm10tdmi", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL),
+- ARM_CPU_OPT ("arm10e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
+- ARM_CPU_OPT ("arm1020", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, "ARM1020E"),
+- ARM_CPU_OPT ("arm1020t", ARM_ARCH_V5T, FPU_ARCH_VFP_V1, NULL),
+- ARM_CPU_OPT ("arm1020e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
+- ARM_CPU_OPT ("arm1022e", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
+- ARM_CPU_OPT ("arm1026ejs", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2,
+- "ARM1026EJ-S"),
+- ARM_CPU_OPT ("arm1026ej-s", ARM_ARCH_V5TEJ, FPU_ARCH_VFP_V2, NULL),
+- ARM_CPU_OPT ("fa606te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
+- ARM_CPU_OPT ("fa616te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
+- ARM_CPU_OPT ("fa626te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
+- ARM_CPU_OPT ("fmp626", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
+- ARM_CPU_OPT ("fa726te", ARM_ARCH_V5TE, FPU_ARCH_VFP_V2, NULL),
+- ARM_CPU_OPT ("arm1136js", ARM_ARCH_V6, FPU_NONE, "ARM1136J-S"),
+- ARM_CPU_OPT ("arm1136j-s", ARM_ARCH_V6, FPU_NONE, NULL),
+- ARM_CPU_OPT ("arm1136jfs", ARM_ARCH_V6, FPU_ARCH_VFP_V2,
+- "ARM1136JF-S"),
+- ARM_CPU_OPT ("arm1136jf-s", ARM_ARCH_V6, FPU_ARCH_VFP_V2, NULL),
+- ARM_CPU_OPT ("mpcore", ARM_ARCH_V6K, FPU_ARCH_VFP_V2, "MPCore"),
+- ARM_CPU_OPT ("mpcorenovfp", ARM_ARCH_V6K, FPU_NONE, "MPCore"),
+- ARM_CPU_OPT ("arm1156t2-s", ARM_ARCH_V6T2, FPU_NONE, NULL),
+- ARM_CPU_OPT ("arm1156t2f-s", ARM_ARCH_V6T2, FPU_ARCH_VFP_V2, NULL),
+- ARM_CPU_OPT ("arm1176jz-s", ARM_ARCH_V6KZ, FPU_NONE, NULL),
+- ARM_CPU_OPT ("arm1176jzf-s", ARM_ARCH_V6KZ, FPU_ARCH_VFP_V2, NULL),
+- ARM_CPU_OPT ("cortex-a5", ARM_ARCH_V7A_MP_SEC,
+- FPU_NONE, "Cortex-A5"),
+- ARM_CPU_OPT ("cortex-a7", ARM_ARCH_V7VE, FPU_ARCH_NEON_VFP_V4,
+- "Cortex-A7"),
+- ARM_CPU_OPT ("cortex-a8", ARM_ARCH_V7A_SEC,
+- ARM_FEATURE_COPROC (FPU_VFP_V3
+- | FPU_NEON_EXT_V1),
+- "Cortex-A8"),
+- ARM_CPU_OPT ("cortex-a9", ARM_ARCH_V7A_MP_SEC,
+- ARM_FEATURE_COPROC (FPU_VFP_V3
+- | FPU_NEON_EXT_V1),
+- "Cortex-A9"),
+- ARM_CPU_OPT ("cortex-a12", ARM_ARCH_V7VE, FPU_ARCH_NEON_VFP_V4,
+- "Cortex-A12"),
+- ARM_CPU_OPT ("cortex-a15", ARM_ARCH_V7VE, FPU_ARCH_NEON_VFP_V4,
+- "Cortex-A15"),
+- ARM_CPU_OPT ("cortex-a17", ARM_ARCH_V7VE, FPU_ARCH_NEON_VFP_V4,
+- "Cortex-A17"),
+- ARM_CPU_OPT ("cortex-a32", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
+- "Cortex-A32"),
+- ARM_CPU_OPT ("cortex-a35", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
+- "Cortex-A35"),
+- ARM_CPU_OPT ("cortex-a53", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
+- "Cortex-A53"),
+- ARM_CPU_OPT ("cortex-a57", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
+- "Cortex-A57"),
+- ARM_CPU_OPT ("cortex-a72", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
+- "Cortex-A72"),
+- ARM_CPU_OPT ("cortex-a73", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
+- "Cortex-A73"),
+- ARM_CPU_OPT ("cortex-r4", ARM_ARCH_V7R, FPU_NONE, "Cortex-R4"),
+- ARM_CPU_OPT ("cortex-r4f", ARM_ARCH_V7R, FPU_ARCH_VFP_V3D16,
+- "Cortex-R4F"),
+- ARM_CPU_OPT ("cortex-r5", ARM_ARCH_V7R_IDIV,
+- FPU_NONE, "Cortex-R5"),
+- ARM_CPU_OPT ("cortex-r7", ARM_ARCH_V7R_IDIV,
+- FPU_ARCH_VFP_V3D16,
+- "Cortex-R7"),
+- ARM_CPU_OPT ("cortex-r8", ARM_ARCH_V7R_IDIV,
+- FPU_ARCH_VFP_V3D16,
+- "Cortex-R8"),
+- ARM_CPU_OPT ("cortex-m7", ARM_ARCH_V7EM, FPU_NONE, "Cortex-M7"),
+- ARM_CPU_OPT ("cortex-m4", ARM_ARCH_V7EM, FPU_NONE, "Cortex-M4"),
+- ARM_CPU_OPT ("cortex-m3", ARM_ARCH_V7M, FPU_NONE, "Cortex-M3"),
+- ARM_CPU_OPT ("cortex-m1", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M1"),
+- ARM_CPU_OPT ("cortex-m0", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M0"),
+- ARM_CPU_OPT ("cortex-m0plus", ARM_ARCH_V6SM, FPU_NONE, "Cortex-M0+"),
+- ARM_CPU_OPT ("exynos-m1", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
+- "Samsung " \
+- "Exynos M1"),
+- ARM_CPU_OPT ("qdf24xx", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
+- "Qualcomm "
+- "QDF24XX"),
++ ARM_CPU_OPT ("arm9e-r0", NULL, ARM_ARCH_V5TExP,
++ ARM_ARCH_NONE,
++ FPU_ARCH_VFP_V2),
++ ARM_CPU_OPT ("arm9e", NULL, ARM_ARCH_V5TE,
++ ARM_ARCH_NONE,
++ FPU_ARCH_VFP_V2),
++ ARM_CPU_OPT ("arm926ej", "ARM926EJ-S", ARM_ARCH_V5TEJ,
++ ARM_ARCH_NONE,
++ FPU_ARCH_VFP_V2),
++ ARM_CPU_OPT ("arm926ejs", "ARM926EJ-S", ARM_ARCH_V5TEJ,
++ ARM_ARCH_NONE,
++ FPU_ARCH_VFP_V2),
++ ARM_CPU_OPT ("arm926ej-s", NULL, ARM_ARCH_V5TEJ,
++ ARM_ARCH_NONE,
++ FPU_ARCH_VFP_V2),
++ ARM_CPU_OPT ("arm946e-r0", NULL, ARM_ARCH_V5TExP,
++ ARM_ARCH_NONE,
++ FPU_ARCH_VFP_V2),
++ ARM_CPU_OPT ("arm946e", "ARM946E-S", ARM_ARCH_V5TE,
++ ARM_ARCH_NONE,
++ FPU_ARCH_VFP_V2),
++ ARM_CPU_OPT ("arm946e-s", NULL, ARM_ARCH_V5TE,
++ ARM_ARCH_NONE,
++ FPU_ARCH_VFP_V2),
++ ARM_CPU_OPT ("arm966e-r0", NULL, ARM_ARCH_V5TExP,
++ ARM_ARCH_NONE,
++ FPU_ARCH_VFP_V2),
++ ARM_CPU_OPT ("arm966e", "ARM966E-S", ARM_ARCH_V5TE,
++ ARM_ARCH_NONE,
++ FPU_ARCH_VFP_V2),
++ ARM_CPU_OPT ("arm966e-s", NULL, ARM_ARCH_V5TE,
++ ARM_ARCH_NONE,
++ FPU_ARCH_VFP_V2),
++ ARM_CPU_OPT ("arm968e-s", NULL, ARM_ARCH_V5TE,
++ ARM_ARCH_NONE,
++ FPU_ARCH_VFP_V2),
++ ARM_CPU_OPT ("arm10t", NULL, ARM_ARCH_V5T,
++ ARM_ARCH_NONE,
++ FPU_ARCH_VFP_V1),
++ ARM_CPU_OPT ("arm10tdmi", NULL, ARM_ARCH_V5T,
++ ARM_ARCH_NONE,
++ FPU_ARCH_VFP_V1),
++ ARM_CPU_OPT ("arm10e", NULL, ARM_ARCH_V5TE,
++ ARM_ARCH_NONE,
++ FPU_ARCH_VFP_V2),
++ ARM_CPU_OPT ("arm1020", "ARM1020E", ARM_ARCH_V5TE,
++ ARM_ARCH_NONE,
++ FPU_ARCH_VFP_V2),
++ ARM_CPU_OPT ("arm1020t", NULL, ARM_ARCH_V5T,
++ ARM_ARCH_NONE,
++ FPU_ARCH_VFP_V1),
++ ARM_CPU_OPT ("arm1020e", NULL, ARM_ARCH_V5TE,
++ ARM_ARCH_NONE,
++ FPU_ARCH_VFP_V2),
++ ARM_CPU_OPT ("arm1022e", NULL, ARM_ARCH_V5TE,
++ ARM_ARCH_NONE,
++ FPU_ARCH_VFP_V2),
++ ARM_CPU_OPT ("arm1026ejs", "ARM1026EJ-S", ARM_ARCH_V5TEJ,
++ ARM_ARCH_NONE,
++ FPU_ARCH_VFP_V2),
++ ARM_CPU_OPT ("arm1026ej-s", NULL, ARM_ARCH_V5TEJ,
++ ARM_ARCH_NONE,
++ FPU_ARCH_VFP_V2),
++ ARM_CPU_OPT ("fa606te", NULL, ARM_ARCH_V5TE,
++ ARM_ARCH_NONE,
++ FPU_ARCH_VFP_V2),
++ ARM_CPU_OPT ("fa616te", NULL, ARM_ARCH_V5TE,
++ ARM_ARCH_NONE,
++ FPU_ARCH_VFP_V2),
++ ARM_CPU_OPT ("fa626te", NULL, ARM_ARCH_V5TE,
++ ARM_ARCH_NONE,
++ FPU_ARCH_VFP_V2),
++ ARM_CPU_OPT ("fmp626", NULL, ARM_ARCH_V5TE,
++ ARM_ARCH_NONE,
++ FPU_ARCH_VFP_V2),
++ ARM_CPU_OPT ("fa726te", NULL, ARM_ARCH_V5TE,
++ ARM_ARCH_NONE,
++ FPU_ARCH_VFP_V2),
++ ARM_CPU_OPT ("arm1136js", "ARM1136J-S", ARM_ARCH_V6,
++ ARM_ARCH_NONE,
++ FPU_NONE),
++ ARM_CPU_OPT ("arm1136j-s", NULL, ARM_ARCH_V6,
++ ARM_ARCH_NONE,
++ FPU_NONE),
++ ARM_CPU_OPT ("arm1136jfs", "ARM1136JF-S", ARM_ARCH_V6,
++ ARM_ARCH_NONE,
++ FPU_ARCH_VFP_V2),
++ ARM_CPU_OPT ("arm1136jf-s", NULL, ARM_ARCH_V6,
++ ARM_ARCH_NONE,
++ FPU_ARCH_VFP_V2),
++ ARM_CPU_OPT ("mpcore", "MPCore", ARM_ARCH_V6K,
++ ARM_ARCH_NONE,
++ FPU_ARCH_VFP_V2),
++ ARM_CPU_OPT ("mpcorenovfp", "MPCore", ARM_ARCH_V6K,
++ ARM_ARCH_NONE,
++ FPU_NONE),
++ ARM_CPU_OPT ("arm1156t2-s", NULL, ARM_ARCH_V6T2,
++ ARM_ARCH_NONE,
++ FPU_NONE),
++ ARM_CPU_OPT ("arm1156t2f-s", NULL, ARM_ARCH_V6T2,
++ ARM_ARCH_NONE,
++ FPU_ARCH_VFP_V2),
++ ARM_CPU_OPT ("arm1176jz-s", NULL, ARM_ARCH_V6KZ,
++ ARM_ARCH_NONE,
++ FPU_NONE),
++ ARM_CPU_OPT ("arm1176jzf-s", NULL, ARM_ARCH_V6KZ,
++ ARM_ARCH_NONE,
++ FPU_ARCH_VFP_V2),
++ ARM_CPU_OPT ("cortex-a5", "Cortex-A5", ARM_ARCH_V7A,
++ ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC),
++ FPU_NONE),
++ ARM_CPU_OPT ("cortex-a7", "Cortex-A7", ARM_ARCH_V7VE,
++ ARM_ARCH_NONE,
++ FPU_ARCH_NEON_VFP_V4),
++ ARM_CPU_OPT ("cortex-a8", "Cortex-A8", ARM_ARCH_V7A,
++ ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
++ ARM_FEATURE_COPROC (FPU_VFP_V3 | FPU_NEON_EXT_V1)),
++ ARM_CPU_OPT ("cortex-a9", "Cortex-A9", ARM_ARCH_V7A,
++ ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC),
++ ARM_FEATURE_COPROC (FPU_VFP_V3 | FPU_NEON_EXT_V1)),
++ ARM_CPU_OPT ("cortex-a12", "Cortex-A12", ARM_ARCH_V7VE,
++ ARM_ARCH_NONE,
++ FPU_ARCH_NEON_VFP_V4),
++ ARM_CPU_OPT ("cortex-a15", "Cortex-A15", ARM_ARCH_V7VE,
++ ARM_ARCH_NONE,
++ FPU_ARCH_NEON_VFP_V4),
++ ARM_CPU_OPT ("cortex-a17", "Cortex-A17", ARM_ARCH_V7VE,
++ ARM_ARCH_NONE,
++ FPU_ARCH_NEON_VFP_V4),
++ ARM_CPU_OPT ("cortex-a32", "Cortex-A32", ARM_ARCH_V8A,
++ ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
++ FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
++ ARM_CPU_OPT ("cortex-a35", "Cortex-A35", ARM_ARCH_V8A,
++ ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
++ FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
++ ARM_CPU_OPT ("cortex-a53", "Cortex-A53", ARM_ARCH_V8A,
++ ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
++ FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
++ ARM_CPU_OPT ("cortex-a55", "Cortex-A55", ARM_ARCH_V8_2A,
++ ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
++ FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
++ ARM_CPU_OPT ("cortex-a57", "Cortex-A57", ARM_ARCH_V8A,
++ ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
++ FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
++ ARM_CPU_OPT ("cortex-a72", "Cortex-A72", ARM_ARCH_V8A,
++ ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
++ FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
++ ARM_CPU_OPT ("cortex-a73", "Cortex-A73", ARM_ARCH_V8A,
++ ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
++ FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
++ ARM_CPU_OPT ("cortex-a75", "Cortex-A75", ARM_ARCH_V8_2A,
++ ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
++ FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
++ ARM_CPU_OPT ("cortex-r4", "Cortex-R4", ARM_ARCH_V7R,
++ ARM_ARCH_NONE,
++ FPU_NONE),
++ ARM_CPU_OPT ("cortex-r4f", "Cortex-R4F", ARM_ARCH_V7R,
++ ARM_ARCH_NONE,
++ FPU_ARCH_VFP_V3D16),
++ ARM_CPU_OPT ("cortex-r5", "Cortex-R5", ARM_ARCH_V7R,
++ ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
++ FPU_NONE),
++ ARM_CPU_OPT ("cortex-r7", "Cortex-R7", ARM_ARCH_V7R,
++ ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
++ FPU_ARCH_VFP_V3D16),
++ ARM_CPU_OPT ("cortex-r8", "Cortex-R8", ARM_ARCH_V7R,
++ ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV),
++ FPU_ARCH_VFP_V3D16),
++ ARM_CPU_OPT ("cortex-r52", "Cortex-R52", ARM_ARCH_V8R,
++ ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
++ FPU_ARCH_NEON_VFP_ARMV8),
++ ARM_CPU_OPT ("cortex-m33", "Cortex-M33", ARM_ARCH_V8M_MAIN,
++ ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP),
++ FPU_NONE),
++ ARM_CPU_OPT ("cortex-m23", "Cortex-M23", ARM_ARCH_V8M_BASE,
++ ARM_ARCH_NONE,
++ FPU_NONE),
++ ARM_CPU_OPT ("cortex-m7", "Cortex-M7", ARM_ARCH_V7EM,
++ ARM_ARCH_NONE,
++ FPU_NONE),
++ ARM_CPU_OPT ("cortex-m4", "Cortex-M4", ARM_ARCH_V7EM,
++ ARM_ARCH_NONE,
++ FPU_NONE),
++ ARM_CPU_OPT ("cortex-m3", "Cortex-M3", ARM_ARCH_V7M,
++ ARM_ARCH_NONE,
++ FPU_NONE),
++ ARM_CPU_OPT ("cortex-m1", "Cortex-M1", ARM_ARCH_V6SM,
++ ARM_ARCH_NONE,
++ FPU_NONE),
++ ARM_CPU_OPT ("cortex-m0", "Cortex-M0", ARM_ARCH_V6SM,
++ ARM_ARCH_NONE,
++ FPU_NONE),
++ ARM_CPU_OPT ("cortex-m0plus", "Cortex-M0+", ARM_ARCH_V6SM,
++ ARM_ARCH_NONE,
++ FPU_NONE),
++ ARM_CPU_OPT ("exynos-m1", "Samsung Exynos M1", ARM_ARCH_V8A,
++ ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
++ FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
+
+ /* ??? XSCALE is really an architecture. */
+- ARM_CPU_OPT ("xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL),
++ ARM_CPU_OPT ("xscale", NULL, ARM_ARCH_XSCALE,
++ ARM_ARCH_NONE,
++ FPU_ARCH_VFP_V2),
++
+ /* ??? iwmmxt is not a processor. */
+- ARM_CPU_OPT ("iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP_V2, NULL),
+- ARM_CPU_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP_V2, NULL),
+- ARM_CPU_OPT ("i80200", ARM_ARCH_XSCALE, FPU_ARCH_VFP_V2, NULL),
++ ARM_CPU_OPT ("iwmmxt", NULL, ARM_ARCH_IWMMXT,
++ ARM_ARCH_NONE,
++ FPU_ARCH_VFP_V2),
++ ARM_CPU_OPT ("iwmmxt2", NULL, ARM_ARCH_IWMMXT2,
++ ARM_ARCH_NONE,
++ FPU_ARCH_VFP_V2),
++ ARM_CPU_OPT ("i80200", NULL, ARM_ARCH_XSCALE,
++ ARM_ARCH_NONE,
++ FPU_ARCH_VFP_V2),
++
+ /* Maverick */
+- ARM_CPU_OPT ("ep9312", ARM_FEATURE_LOW (ARM_AEXT_V4T, ARM_CEXT_MAVERICK),
+- FPU_ARCH_MAVERICK, "ARM920T"),
++ ARM_CPU_OPT ("ep9312", "ARM920T",
++ ARM_FEATURE_LOW (ARM_AEXT_V4T, ARM_CEXT_MAVERICK),
++ ARM_ARCH_NONE, FPU_ARCH_MAVERICK),
++
+ /* Marvell processors. */
+- ARM_CPU_OPT ("marvell-pj4", ARM_FEATURE_CORE (ARM_AEXT_V7A | ARM_EXT_MP
+- | ARM_EXT_SEC,
+- ARM_EXT2_V6T2_V8M),
+- FPU_ARCH_VFP_V3D16, NULL),
+- ARM_CPU_OPT ("marvell-whitney", ARM_FEATURE_CORE (ARM_AEXT_V7A | ARM_EXT_MP
+- | ARM_EXT_SEC,
+- ARM_EXT2_V6T2_V8M),
+- FPU_ARCH_NEON_VFP_V4, NULL),
++ ARM_CPU_OPT ("marvell-pj4", NULL, ARM_ARCH_V7A,
++ ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC),
++ FPU_ARCH_VFP_V3D16),
++ ARM_CPU_OPT ("marvell-whitney", NULL, ARM_ARCH_V7A,
++ ARM_FEATURE_CORE_LOW (ARM_EXT_MP | ARM_EXT_SEC),
++ FPU_ARCH_NEON_VFP_V4),
++
+ /* APM X-Gene family. */
+- ARM_CPU_OPT ("xgene1", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
+- "APM X-Gene 1"),
+- ARM_CPU_OPT ("xgene2", ARM_ARCH_V8A, FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
+- "APM X-Gene 2"),
++ ARM_CPU_OPT ("xgene1", "APM X-Gene 1", ARM_ARCH_V8A,
++ ARM_ARCH_NONE,
++ FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
++ ARM_CPU_OPT ("xgene2", "APM X-Gene 2", ARM_ARCH_V8A,
++ ARM_FEATURE_COPROC (CRC_EXT_ARMV8),
++ FPU_ARCH_CRYPTO_NEON_VFP_ARMV8),
+
+- { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL }
++ { NULL, 0, ARM_ARCH_NONE, ARM_ARCH_NONE, ARM_ARCH_NONE, NULL }
+ };
+ #undef ARM_CPU_OPT
+
+@@ -25459,6 +26022,8 @@ static const struct arm_arch_option_tabl
+ ARM_ARCH_OPT ("armv8-a", ARM_ARCH_V8A, FPU_ARCH_VFP),
+ ARM_ARCH_OPT ("armv8.1-a", ARM_ARCH_V8_1A, FPU_ARCH_VFP),
+ ARM_ARCH_OPT ("armv8.2-a", ARM_ARCH_V8_2A, FPU_ARCH_VFP),
++ ARM_ARCH_OPT ("armv8.3-a", ARM_ARCH_V8_3A, FPU_ARCH_VFP),
++ ARM_ARCH_OPT ("armv8-r", ARM_ARCH_V8R, FPU_ARCH_VFP),
+ ARM_ARCH_OPT ("xscale", ARM_ARCH_XSCALE, FPU_ARCH_VFP),
+ ARM_ARCH_OPT ("iwmmxt", ARM_ARCH_IWMMXT, FPU_ARCH_VFP),
+ ARM_ARCH_OPT ("iwmmxt2", ARM_ARCH_IWMMXT2,FPU_ARCH_VFP),
+@@ -25490,6 +26055,9 @@ static const struct arm_option_extension
+ ARM_EXT_OPT ("crypto", FPU_ARCH_CRYPTO_NEON_VFP_ARMV8,
+ ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8),
+ ARM_FEATURE_CORE_LOW (ARM_EXT_V8)),
++ ARM_EXT_OPT ("dotprod", FPU_ARCH_DOTPROD_NEON_VFP_ARMV8,
++ ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
++ ARM_ARCH_V8_2A),
+ ARM_EXT_OPT ("dsp", ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP),
+ ARM_FEATURE_CORE_LOW (ARM_EXT_V5ExP | ARM_EXT_V6_DSP),
+ ARM_FEATURE_CORE (ARM_EXT_V7M, ARM_EXT2_V8M)),
+@@ -25502,6 +26070,13 @@ static const struct arm_option_extension
+ ARM_FEATURE_CORE_LOW (ARM_EXT_ADIV | ARM_EXT_DIV),
+ ARM_FEATURE_CORE_LOW (ARM_EXT_V7A),
+ ARM_FEATURE_CORE_LOW (ARM_EXT_V7R)),
++ /* Duplicate entry for the purpose of allowing ARMv7 to match in presence of
++ Thumb divide instruction. Due to this having the same name as the
++ previous entry, this will be ignored when doing command-line parsing and
++ only considered by build attribute selection code. */
++ ARM_EXT_OPT ("idiv", ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
++ ARM_FEATURE_CORE_LOW (ARM_EXT_DIV),
++ ARM_FEATURE_CORE_LOW (ARM_EXT_V7)),
+ ARM_EXT_OPT ("iwmmxt",ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT),
+ ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT), ARM_ARCH_NONE),
+ ARM_EXT_OPT ("iwmmxt2", ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2),
+@@ -25517,13 +26092,13 @@ static const struct arm_option_extension
+ ARM_FEATURE_CORE_LOW (ARM_EXT_V6M)),
+ ARM_EXT_OPT ("pan", ARM_FEATURE_CORE_HIGH (ARM_EXT2_PAN),
+ ARM_FEATURE (ARM_EXT_V8, ARM_EXT2_PAN, 0),
+- ARM_FEATURE_CORE_LOW (ARM_EXT_V8)),
++ ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A)),
+ ARM_EXT_OPT ("ras", ARM_FEATURE_CORE_HIGH (ARM_EXT2_RAS),
+ ARM_FEATURE (ARM_EXT_V8, ARM_EXT2_RAS, 0),
+- ARM_FEATURE_CORE_LOW (ARM_EXT_V8)),
++ ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A)),
+ ARM_EXT_OPT ("rdma", FPU_ARCH_NEON_VFP_ARMV8_1,
+ ARM_FEATURE_COPROC (FPU_NEON_ARMV8 | FPU_NEON_EXT_RDMA),
+- ARM_FEATURE_CORE_LOW (ARM_EXT_V8)),
++ ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8A)),
+ ARM_EXT_OPT2 ("sec", ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
+ ARM_FEATURE_CORE_LOW (ARM_EXT_SEC),
+ ARM_FEATURE_CORE_LOW (ARM_EXT_V6K),
+@@ -25581,6 +26156,7 @@ static const struct arm_option_fpu_value
+ {"arm1136jf-s", FPU_ARCH_VFP_V2},
+ {"maverick", FPU_ARCH_MAVERICK},
+ {"neon", FPU_ARCH_VFP_V3_PLUS_NEON_V1},
++ {"neon-vfpv3", FPU_ARCH_VFP_V3_PLUS_NEON_V1},
+ {"neon-fp16", FPU_ARCH_NEON_FP16},
+ {"vfpv4", FPU_ARCH_VFP_V4},
+ {"vfpv4-d16", FPU_ARCH_VFP_V4D16},
+@@ -25632,10 +26208,9 @@ struct arm_long_option_table
+ };
+
+ static bfd_boolean
+-arm_parse_extension (const char *str, const arm_feature_set **opt_p)
++arm_parse_extension (const char *str, const arm_feature_set *opt_set,
++ arm_feature_set **ext_set_p)
+ {
+- arm_feature_set *ext_set = XNEW (arm_feature_set);
+-
+ /* We insist on extensions being specified in alphabetical order, and with
+ extensions being added before being removed. We achieve this by having
+ the global ARM_EXTENSIONS table in alphabetical order, and using the
+@@ -25646,9 +26221,11 @@ arm_parse_extension (const char *str, co
+ const arm_feature_set arm_any = ARM_ANY;
+ int adding_value = -1;
+
+- /* Copy the feature set, so that we can modify it. */
+- *ext_set = **opt_p;
+- *opt_p = ext_set;
++ if (!*ext_set_p)
++ {
++ *ext_set_p = XNEW (arm_feature_set);
++ **ext_set_p = arm_arch_none;
++ }
+
+ while (str != NULL && *str != 0)
+ {
+@@ -25716,7 +26293,7 @@ arm_parse_extension (const char *str, co
+ /* Empty entry. */
+ if (ARM_FEATURE_EQUAL (opt->allowed_archs[i], arm_any))
+ continue;
+- if (ARM_FSET_CPU_SUBSET (opt->allowed_archs[i], *ext_set))
++ if (ARM_FSET_CPU_SUBSET (opt->allowed_archs[i], *opt_set))
+ break;
+ }
+ if (i == nb_allowed_archs)
+@@ -25727,10 +26304,15 @@ arm_parse_extension (const char *str, co
+
+ /* Add or remove the extension. */
+ if (adding_value)
+- ARM_MERGE_FEATURE_SETS (*ext_set, *ext_set, opt->merge_value);
++ ARM_MERGE_FEATURE_SETS (**ext_set_p, **ext_set_p,
++ opt->merge_value);
+ else
+- ARM_CLEAR_FEATURE (*ext_set, *ext_set, opt->clear_value);
++ ARM_CLEAR_FEATURE (**ext_set_p, **ext_set_p, opt->clear_value);
+
++ /* Allowing Thumb division instructions for ARMv7 in autodetection
++ rely on this break so that duplicate extensions (extensions
++ with the same name as a previous extension in the list) are not
++ considered for command-line parsing. */
+ break;
+ }
+
+@@ -25786,6 +26368,9 @@ arm_parse_cpu (const char *str)
+ if (opt->name_len == len && strncmp (opt->name, str, len) == 0)
+ {
+ mcpu_cpu_opt = &opt->value;
++ if (!dyn_mcpu_ext_opt)
++ dyn_mcpu_ext_opt = XNEW (arm_feature_set);
++ *dyn_mcpu_ext_opt = opt->ext;
+ mcpu_fpu_opt = &opt->default_fpu;
+ if (opt->canonical_name)
+ {
+@@ -25805,7 +26390,7 @@ arm_parse_cpu (const char *str)
+ }
+
+ if (ext != NULL)
+- return arm_parse_extension (ext, &mcpu_cpu_opt);
++ return arm_parse_extension (ext, mcpu_cpu_opt, &dyn_mcpu_ext_opt);
+
+ return TRUE;
+ }
+@@ -25840,7 +26425,7 @@ arm_parse_arch (const char *str)
+ strcpy (selected_cpu_name, opt->name);
+
+ if (ext != NULL)
+- return arm_parse_extension (ext, &march_cpu_opt);
++ return arm_parse_extension (ext, march_cpu_opt, &dyn_march_ext_opt);
+
+ return TRUE;
+ }
+@@ -26080,30 +26665,62 @@ typedef struct
+ arm_feature_set flags;
+ } cpu_arch_ver_table;
+
+-/* Mapping from CPU features to EABI CPU arch values. As a general rule, table
+- must be sorted least features first but some reordering is needed, eg. for
+- Thumb-2 instructions to be detected as coming from ARMv6T2. */
++/* Mapping from CPU features to EABI CPU arch values. Table must be sorted
++ chronologically for architectures, with an exception for ARMv6-M and
++ ARMv6S-M due to legacy reasons. No new architecture should have a
++ special case. This allows for build attribute selection results to be
++ stable when new architectures are added. */
+ static const cpu_arch_ver_table cpu_arch_ver[] =
+ {
++ {0, ARM_ARCH_V1},
++ {0, ARM_ARCH_V2},
++ {0, ARM_ARCH_V2S},
++ {0, ARM_ARCH_V3},
++ {0, ARM_ARCH_V3M},
++ {1, ARM_ARCH_V4xM},
+ {1, ARM_ARCH_V4},
++ {2, ARM_ARCH_V4TxM},
+ {2, ARM_ARCH_V4T},
++ {3, ARM_ARCH_V5xM},
+ {3, ARM_ARCH_V5},
++ {3, ARM_ARCH_V5TxM},
+ {3, ARM_ARCH_V5T},
++ {4, ARM_ARCH_V5TExP},
+ {4, ARM_ARCH_V5TE},
+ {5, ARM_ARCH_V5TEJ},
+ {6, ARM_ARCH_V6},
+- {9, ARM_ARCH_V6K},
+ {7, ARM_ARCH_V6Z},
++ {7, ARM_ARCH_V6KZ},
++ {9, ARM_ARCH_V6K},
++ {8, ARM_ARCH_V6T2},
++ {8, ARM_ARCH_V6KT2},
++ {8, ARM_ARCH_V6ZT2},
++ {8, ARM_ARCH_V6KZT2},
++
++ /* When assembling a file with only ARMv6-M or ARMv6S-M instruction, GNU as
++ always selected build attributes to match those of ARMv6-M
++ (resp. ARMv6S-M). However, due to these architectures being a strict
++ subset of ARMv7-M in terms of instructions available, ARMv7-M attributes
++ would be selected when fully respecting chronology of architectures.
++ It is thus necessary to make a special case of ARMv6-M and ARMv6S-M and
++ move them before ARMv7 architectures. */
+ {11, ARM_ARCH_V6M},
+ {12, ARM_ARCH_V6SM},
+- {8, ARM_ARCH_V6T2},
+- {10, ARM_ARCH_V7VE},
++
++ {10, ARM_ARCH_V7},
++ {10, ARM_ARCH_V7A},
+ {10, ARM_ARCH_V7R},
+ {10, ARM_ARCH_V7M},
++ {10, ARM_ARCH_V7VE},
++ {13, ARM_ARCH_V7EM},
+ {14, ARM_ARCH_V8A},
++ {14, ARM_ARCH_V8_1A},
++ {14, ARM_ARCH_V8_2A},
++ {14, ARM_ARCH_V8_3A},
+ {16, ARM_ARCH_V8M_BASE},
+ {17, ARM_ARCH_V8M_MAIN},
+- {0, ARM_ARCH_NONE}
++ {15, ARM_ARCH_V8R},
++ {-1, ARM_ARCH_NONE}
+ };
+
+ /* Set an attribute if it has not already been set by the user. */
+@@ -26125,92 +26742,210 @@ aeabi_set_attribute_string (int tag, con
+ bfd_elf_add_proc_attr_string (stdoutput, tag, value);
+ }
+
+-/* Set the public EABI object attributes. */
+-void
+-aeabi_set_public_attributes (void)
++/* Return whether features in the *NEEDED feature set are available via
++ extensions for the architecture whose feature set is *ARCH_FSET. */
++static bfd_boolean
++have_ext_for_needed_feat_p (const arm_feature_set *arch_fset,
++ const arm_feature_set *needed)
+ {
+- int arch;
+- char profile;
+- int virt_sec = 0;
+- int fp16_optional = 0;
+- arm_feature_set arm_arch = ARM_ARCH_NONE;
+- arm_feature_set flags;
+- arm_feature_set tmp;
+- arm_feature_set arm_arch_v8m_base = ARM_ARCH_V8M_BASE;
+- const cpu_arch_ver_table *p;
+-
+- /* Choose the architecture based on the capabilities of the requested cpu
+- (if any) and/or the instructions actually used. */
+- ARM_MERGE_FEATURE_SETS (flags, arm_arch_used, thumb_arch_used);
+- ARM_MERGE_FEATURE_SETS (flags, flags, *mfpu_opt);
+- ARM_MERGE_FEATURE_SETS (flags, flags, selected_cpu);
++ int i, nb_allowed_archs;
++ arm_feature_set ext_fset;
++ const struct arm_option_extension_value_table *opt;
+
+- if (ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any))
+- ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v1);
++ ext_fset = arm_arch_none;
++ for (opt = arm_extensions; opt->name != NULL; opt++)
++ {
++ /* Extension does not provide any feature we need. */
++ if (!ARM_CPU_HAS_FEATURE (*needed, opt->merge_value))
++ continue;
+
+- if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_any))
+- ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v4t);
++ nb_allowed_archs =
++ sizeof (opt->allowed_archs) / sizeof (opt->allowed_archs[0]);
++ for (i = 0; i < nb_allowed_archs; i++)
++ {
++ /* Empty entry. */
++ if (ARM_FEATURE_EQUAL (opt->allowed_archs[i], arm_arch_any))
++ break;
+
+- selected_cpu = flags;
++ /* Extension is available, add it. */
++ if (ARM_FSET_CPU_SUBSET (opt->allowed_archs[i], *arch_fset))
++ ARM_MERGE_FEATURE_SETS (ext_fset, ext_fset, opt->merge_value);
++ }
++ }
+
+- /* Allow the user to override the reported architecture. */
+- if (object_arch)
++ /* Can we enable all features in *needed? */
++ return ARM_FSET_CPU_SUBSET (*needed, ext_fset);
++}
++
++/* Select value for Tag_CPU_arch and Tag_CPU_arch_profile build attributes for
++ a given architecture feature set *ARCH_EXT_FSET including extension feature
++ set *EXT_FSET. Selection logic used depend on EXACT_MATCH:
++ - if true, check for an exact match of the architecture modulo extensions;
++ - otherwise, select build attribute value of the first superset
++ architecture released so that results remains stable when new architectures
++ are added.
++ For -march/-mcpu=all the build attribute value of the most featureful
++ architecture is returned. Tag_CPU_arch_profile result is returned in
++ PROFILE. */
++static int
++get_aeabi_cpu_arch_from_fset (const arm_feature_set *arch_ext_fset,
++ const arm_feature_set *ext_fset,
++ char *profile, int exact_match)
++{
++ arm_feature_set arch_fset;
++ const cpu_arch_ver_table *p_ver, *p_ver_ret = NULL;
++
++ /* Select most featureful architecture with all its extensions if building
++ for -march=all as the feature sets used to set build attributes. */
++ if (ARM_FEATURE_EQUAL (*arch_ext_fset, arm_arch_any))
+ {
+- ARM_CLEAR_FEATURE (flags, flags, arm_arch_any);
+- ARM_MERGE_FEATURE_SETS (flags, flags, *object_arch);
++ /* Force revisiting of decision for each new architecture. */
++ gas_assert (MAX_TAG_CPU_ARCH <= TAG_CPU_ARCH_V8M_MAIN);
++ *profile = 'A';
++ return TAG_CPU_ARCH_V8;
+ }
+
+- /* We need to make sure that the attributes do not identify us as v6S-M
+- when the only v6S-M feature in use is the Operating System Extensions. */
+- if (ARM_CPU_HAS_FEATURE (flags, arm_ext_os))
+- if (!ARM_CPU_HAS_FEATURE (flags, arm_arch_v6m_only))
+- ARM_CLEAR_FEATURE (flags, flags, arm_ext_os);
++ ARM_CLEAR_FEATURE (arch_fset, *arch_ext_fset, *ext_fset);
+
+- tmp = flags;
+- arch = 0;
+- for (p = cpu_arch_ver; p->val; p++)
++ for (p_ver = cpu_arch_ver; p_ver->val != -1; p_ver++)
+ {
+- if (ARM_CPU_HAS_FEATURE (tmp, p->flags))
++ arm_feature_set known_arch_fset;
++
++ ARM_CLEAR_FEATURE (known_arch_fset, p_ver->flags, fpu_any);
++ if (exact_match)
+ {
+- arch = p->val;
+- arm_arch = p->flags;
+- ARM_CLEAR_FEATURE (tmp, tmp, p->flags);
++ /* Base architecture match user-specified architecture and
++ extensions, eg. ARMv6S-M matching -march=armv6-m+os. */
++ if (ARM_FEATURE_EQUAL (*arch_ext_fset, known_arch_fset))
++ {
++ p_ver_ret = p_ver;
++ goto found;
++ }
++ /* Base architecture match user-specified architecture only
++ (eg. ARMv6-M in the same case as above). Record it in case we
++ find a match with above condition. */
++ else if (p_ver_ret == NULL
++ && ARM_FEATURE_EQUAL (arch_fset, known_arch_fset))
++ p_ver_ret = p_ver;
+ }
+- }
++ else
++ {
+
+- /* The table lookup above finds the last architecture to contribute
+- a new feature. Unfortunately, Tag13 is a subset of the union of
+- v6T2 and v7-M, so it is never seen as contributing a new feature.
+- We can not search for the last entry which is entirely used,
+- because if no CPU is specified we build up only those flags
+- actually used. Perhaps we should separate out the specified
+- and implicit cases. Avoid taking this path for -march=all by
+- checking for contradictory v7-A / v7-M features. */
+- if (arch == TAG_CPU_ARCH_V7
+- && !ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a)
+- && ARM_CPU_HAS_FEATURE (flags, arm_ext_v7m)
+- && ARM_CPU_HAS_FEATURE (flags, arm_ext_v6_dsp))
+- {
+- arch = TAG_CPU_ARCH_V7E_M;
+- arm_arch = (arm_feature_set) ARM_ARCH_V7EM;
++ /* Architecture has all features wanted. */
++ if (ARM_FSET_CPU_SUBSET (arch_fset, known_arch_fset))
++ {
++ arm_feature_set added_fset;
++
++ /* Compute features added by this architecture over the one
++ recorded in p_ver_ret. */
++ if (p_ver_ret != NULL)
++ ARM_CLEAR_FEATURE (added_fset, known_arch_fset,
++ p_ver_ret->flags);
++ /* First architecture that match incl. with extensions, or the
++ only difference in features over the recorded match is
++ features that were optional and are now mandatory. */
++ if (p_ver_ret == NULL
++ || ARM_FSET_CPU_SUBSET (added_fset, arch_fset))
++ {
++ p_ver_ret = p_ver;
++ goto found;
++ }
++ }
++ else if (p_ver_ret == NULL)
++ {
++ arm_feature_set needed_ext_fset;
++
++ ARM_CLEAR_FEATURE (needed_ext_fset, arch_fset, known_arch_fset);
++
++ /* Architecture has all features needed when using some
++ extensions. Record it and continue searching in case there
++ exist an architecture providing all needed features without
++ the need for extensions (eg. ARMv6S-M Vs ARMv6-M with
++ OS extension). */
++ if (have_ext_for_needed_feat_p (&known_arch_fset,
++ &needed_ext_fset))
++ p_ver_ret = p_ver;
++ }
++ }
+ }
+
+- ARM_CLEAR_FEATURE (tmp, flags, arm_arch_v8m_base);
+- if (arch == TAG_CPU_ARCH_V8M_BASE && ARM_CPU_HAS_FEATURE (tmp, arm_arch_any))
++ if (p_ver_ret == NULL)
++ return -1;
++
++found:
++ /* Tag_CPU_arch_profile. */
++ if (ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_v7a)
++ || ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_v8)
++ || (ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_atomics)
++ && !ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_v8m_m_only)))
++ *profile = 'A';
++ else if (ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_v7r))
++ *profile = 'R';
++ else if (ARM_CPU_HAS_FEATURE (p_ver_ret->flags, arm_ext_m))
++ *profile = 'M';
++ else
++ *profile = '\0';
++ return p_ver_ret->val;
++}
++
++/* Set the public EABI object attributes. */
++static void
++aeabi_set_public_attributes (void)
++{
++ char profile;
++ int arch = -1;
++ int virt_sec = 0;
++ int fp16_optional = 0;
++ int skip_exact_match = 0;
++ arm_feature_set flags, flags_arch, flags_ext;
++
++ /* Autodetection mode, choose the architecture based the instructions
++ actually used. */
++ if (no_cpu_selected ())
+ {
+- arch = TAG_CPU_ARCH_V8M_MAIN;
+- arm_arch = (arm_feature_set) ARM_ARCH_V8M_MAIN;
++ ARM_MERGE_FEATURE_SETS (flags, arm_arch_used, thumb_arch_used);
++
++ if (ARM_CPU_HAS_FEATURE (arm_arch_used, arm_arch_any))
++ ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v1);
++
++ if (ARM_CPU_HAS_FEATURE (thumb_arch_used, arm_arch_any))
++ ARM_MERGE_FEATURE_SETS (flags, flags, arm_ext_v4t);
++
++ /* Code run during relaxation relies on selected_cpu being set. */
++ selected_cpu = flags;
+ }
++ /* Otherwise, choose the architecture based on the capabilities of the
++ requested cpu. */
++ else
++ flags = selected_cpu;
++ ARM_MERGE_FEATURE_SETS (flags, flags, *mfpu_opt);
+
+- /* In cpu_arch_ver ARMv8-A is before ARMv8-M for atomics to be detected as
+- coming from ARMv8-A. However, since ARMv8-A has more instructions than
+- ARMv8-M, -march=all must be detected as ARMv8-A. */
+- if (arch == TAG_CPU_ARCH_V8M_MAIN
+- && ARM_FEATURE_CORE_EQUAL (selected_cpu, arm_arch_any))
++ /* Allow the user to override the reported architecture. */
++ if (object_arch)
+ {
+- arch = TAG_CPU_ARCH_V8;
+- arm_arch = (arm_feature_set) ARM_ARCH_V8A;
++ ARM_CLEAR_FEATURE (flags_arch, *object_arch, fpu_any);
++ flags_ext = arm_arch_none;
+ }
++ else
++ {
++ ARM_CLEAR_FEATURE (flags_arch, flags, fpu_any);
++ flags_ext = dyn_mcpu_ext_opt ? *dyn_mcpu_ext_opt : arm_arch_none;
++ skip_exact_match = ARM_FEATURE_EQUAL (selected_cpu, arm_arch_any);
++ }
++
++ /* When this function is run again after relaxation has happened there is no
++ way to determine whether an architecture or CPU was specified by the user:
++ - selected_cpu is set above for relaxation to work;
++ - march_cpu_opt is not set if only -mcpu or .cpu is used;
++ - mcpu_cpu_opt is set to arm_arch_any for autodetection.
++ Therefore, if not in -march=all case we first try an exact match and fall
++ back to autodetection. */
++ if (!skip_exact_match)
++ arch = get_aeabi_cpu_arch_from_fset (&flags_arch, &flags_ext, &profile, 1);
++ if (arch == -1)
++ arch = get_aeabi_cpu_arch_from_fset (&flags_arch, &flags_ext, &profile, 0);
++ if (arch == -1)
++ as_bad (_("no architecture contains all the instructions used\n"));
+
+ /* Tag_CPU_name. */
+ if (selected_cpu_name[0])
+@@ -26233,40 +26968,22 @@ aeabi_set_public_attributes (void)
+ aeabi_set_attribute_int (Tag_CPU_arch, arch);
+
+ /* Tag_CPU_arch_profile. */
+- if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7a)
+- || ARM_CPU_HAS_FEATURE (flags, arm_ext_v8)
+- || (ARM_CPU_HAS_FEATURE (flags, arm_ext_atomics)
+- && !ARM_CPU_HAS_FEATURE (flags, arm_ext_v8m_m_only)))
+- profile = 'A';
+- else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v7r))
+- profile = 'R';
+- else if (ARM_CPU_HAS_FEATURE (flags, arm_ext_m))
+- profile = 'M';
+- else
+- profile = '\0';
+-
+ if (profile != '\0')
+ aeabi_set_attribute_int (Tag_CPU_arch_profile, profile);
+
+ /* Tag_DSP_extension. */
+- if (ARM_CPU_HAS_FEATURE (flags, arm_ext_dsp))
+- {
+- arm_feature_set ext;
+-
+- /* DSP instructions not in architecture. */
+- ARM_CLEAR_FEATURE (ext, flags, arm_arch);
+- if (ARM_CPU_HAS_FEATURE (ext, arm_ext_dsp))
+- aeabi_set_attribute_int (Tag_DSP_extension, 1);
+- }
++ if (dyn_mcpu_ext_opt && ARM_CPU_HAS_FEATURE (*dyn_mcpu_ext_opt, arm_ext_dsp))
++ aeabi_set_attribute_int (Tag_DSP_extension, 1);
+
++ ARM_CLEAR_FEATURE (flags_arch, flags, fpu_any);
+ /* Tag_ARM_ISA_use. */
+ if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v1)
+- || arch == 0)
++ || ARM_FEATURE_ZERO (flags_arch))
+ aeabi_set_attribute_int (Tag_ARM_ISA_use, 1);
+
+ /* Tag_THUMB_ISA_use. */
+ if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v4t)
+- || arch == 0)
++ || ARM_FEATURE_ZERO (flags_arch))
+ {
+ int thumb_isa_use;
+
+@@ -26348,9 +27065,7 @@ aeabi_set_public_attributes (void)
+ by the base architecture.
+
+ For new architectures we will have to check these tests. */
+- gas_assert (arch <= TAG_CPU_ARCH_V8
+- || (arch >= TAG_CPU_ARCH_V8M_BASE
+- && arch <= TAG_CPU_ARCH_V8M_MAIN));
++ gas_assert (arch <= TAG_CPU_ARCH_V8M_MAIN);
+ if (ARM_CPU_HAS_FEATURE (flags, arm_ext_v8)
+ || ARM_CPU_HAS_FEATURE (flags, arm_ext_v8m))
+ aeabi_set_attribute_int (Tag_DIV_use, 0);
+@@ -26373,6 +27088,18 @@ aeabi_set_public_attributes (void)
+ aeabi_set_attribute_int (Tag_Virtualization_use, virt_sec);
+ }
+
++/* Post relaxation hook. Recompute ARM attributes now that relaxation is
++ finished and free extension feature bits which will not be used anymore. */
++void
++arm_md_post_relax (void)
++{
++ aeabi_set_public_attributes ();
++ XDELETE (dyn_mcpu_ext_opt);
++ dyn_mcpu_ext_opt = NULL;
++ XDELETE (dyn_march_ext_opt);
++ dyn_march_ext_opt = NULL;
++}
++
+ /* Add the default contents for the .ARM.attributes section. */
+ void
+ arm_md_end (void)
+@@ -26405,7 +27132,10 @@ s_arm_cpu (int ignored ATTRIBUTE_UNUSED)
+ if (streq (opt->name, name))
+ {
+ mcpu_cpu_opt = &opt->value;
+- selected_cpu = opt->value;
++ if (!dyn_mcpu_ext_opt)
++ dyn_mcpu_ext_opt = XNEW (arm_feature_set);
++ *dyn_mcpu_ext_opt = opt->ext;
++ ARM_MERGE_FEATURE_SETS (selected_cpu, *mcpu_cpu_opt, *dyn_mcpu_ext_opt);
+ if (opt->canonical_name)
+ strcpy (selected_cpu_name, opt->canonical_name);
+ else
+@@ -26417,6 +27147,8 @@ s_arm_cpu (int ignored ATTRIBUTE_UNUSED)
+ selected_cpu_name[i] = 0;
+ }
+ ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
++ if (dyn_mcpu_ext_opt)
++ ARM_MERGE_FEATURE_SETS (cpu_variant, cpu_variant, *dyn_mcpu_ext_opt);
+ *input_line_pointer = saved_char;
+ demand_empty_rest_of_line ();
+ return;
+@@ -26447,9 +27179,11 @@ s_arm_arch (int ignored ATTRIBUTE_UNUSED
+ if (streq (opt->name, name))
+ {
+ mcpu_cpu_opt = &opt->value;
+- selected_cpu = opt->value;
++ XDELETE (dyn_mcpu_ext_opt);
++ dyn_mcpu_ext_opt = NULL;
++ selected_cpu = *mcpu_cpu_opt;
+ strcpy (selected_cpu_name, opt->name);
+- ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
++ ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, *mfpu_opt);
+ *input_line_pointer = saved_char;
+ demand_empty_rest_of_line ();
+ return;
+@@ -26536,16 +27270,26 @@ s_arm_arch_extension (int ignored ATTRIB
+ break;
+ }
+
++ if (!dyn_mcpu_ext_opt)
++ {
++ dyn_mcpu_ext_opt = XNEW (arm_feature_set);
++ *dyn_mcpu_ext_opt = arm_arch_none;
++ }
+ if (adding_value)
+- ARM_MERGE_FEATURE_SETS (selected_cpu, selected_cpu,
++ ARM_MERGE_FEATURE_SETS (*dyn_mcpu_ext_opt, *dyn_mcpu_ext_opt,
+ opt->merge_value);
+ else
+- ARM_CLEAR_FEATURE (selected_cpu, selected_cpu, opt->clear_value);
++ ARM_CLEAR_FEATURE (*dyn_mcpu_ext_opt, *dyn_mcpu_ext_opt,
++ opt->clear_value);
+
+- mcpu_cpu_opt = &selected_cpu;
+- ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
++ ARM_MERGE_FEATURE_SETS (selected_cpu, *mcpu_cpu_opt, *dyn_mcpu_ext_opt);
++ ARM_MERGE_FEATURE_SETS (cpu_variant, selected_cpu, *mfpu_opt);
+ *input_line_pointer = saved_char;
+ demand_empty_rest_of_line ();
++ /* Allowing Thumb division instructions for ARMv7 in autodetection rely
++ on this return so that duplicate extensions (extensions with the
++ same name as a previous extension in the list) are not considered
++ for command-line parsing. */
+ return;
+ }
+
+@@ -26576,6 +27320,8 @@ s_arm_fpu (int ignored ATTRIBUTE_UNUSED)
+ {
+ mfpu_opt = &opt->value;
+ ARM_MERGE_FEATURE_SETS (cpu_variant, *mcpu_cpu_opt, *mfpu_opt);
++ if (dyn_mcpu_ext_opt)
++ ARM_MERGE_FEATURE_SETS (cpu_variant, cpu_variant, *dyn_mcpu_ext_opt);
+ *input_line_pointer = saved_char;
+ demand_empty_rest_of_line ();
+ return;
+diff -rup binutils.orig/gas/config/tc-arm.h binutils-2.27/gas/config/tc-arm.h
+--- binutils.orig/gas/config/tc-arm.h 2017-08-09 10:26:30.032741952 +0100
++++ binutils-2.27/gas/config/tc-arm.h 2017-08-09 11:17:35.442400257 +0100
+@@ -118,8 +118,8 @@ extern bfd_boolean tc_start_label_withou
+ extern void arm_md_end (void);
+ bfd_boolean arm_is_eabi (void);
+
+-#define md_post_relax_hook aeabi_set_public_attributes ()
+-extern void aeabi_set_public_attributes (void);
++#define md_post_relax_hook arm_md_post_relax ()
++extern void arm_md_post_relax (void);
+ #endif
+
+ /* NOTE: The fake label creation in stabs.c:s_stab_generic() has
+diff -rup binutils.orig/gas/doc/c-arm.texi binutils-2.27/gas/doc/c-arm.texi
+--- binutils.orig/gas/doc/c-arm.texi 2017-08-09 10:26:30.039741874 +0100
++++ binutils-2.27/gas/doc/c-arm.texi 2017-08-09 10:28:00.216732329 +0100
+@@ -172,6 +172,7 @@ been added, again in ascending alphabeti
+ The following extensions are currently supported:
+ @code{crc}
+ @code{crypto} (Cryptography Extensions for v8-A architecture, implies @code{fp+simd}),
++@code{dotprod} (Dot Product Extensions for v8.2-A architecture, implies @code{fp+simd}),
+ @code{fp} (Floating Point Extensions for v8-A architecture),
+ @code{idiv} (Integer Divide Extensions for v7-A and v7-R architectures),
+ @code{iwmmxt},
+@@ -185,7 +186,7 @@ architectures),
+ @code{simd} (Advanced SIMD Extensions for v8-A architecture, implies @code{fp}),
+ @code{virt} (Virtualization Extensions for v7-A architecture, implies
+ @code{idiv}),
+-@code{pan} (Priviliged Access Never Extensions for v8-A architecture),
++@code{pan} (Privileged Access Never Extensions for v8-A architecture),
+ @code{ras} (Reliability, Availability and Serviceability extensions
+ for v8-A architecture),
+ @code{rdma} (ARMv8.1 Advanced SIMD extensions for v8-A architecture, implies
+@@ -230,6 +231,8 @@ names are recognized:
+ @code{armv8-a},
+ @code{armv8.1-a},
+ @code{armv8.2-a},
++@code{armv8.3-a},
++@code{armv8-r},
+ @code{iwmmxt}
+ @code{iwmmxt2}
+ and
+@@ -281,7 +284,7 @@ The following format options are recogni
+ @code{arm1136jf-s},
+ @code{maverick},
+ @code{neon},
+-@code{neon-vfpv4},
++@code{neon-vfpv3},
+ @code{neon-fp-armv8},
+ @code{crypto-neon-fp-armv8},
+ @code{neon-fp-armv8.1}
+@@ -293,7 +296,7 @@ also affects the way in which the @code{
+ when assembling little-endian code.
+
+ The default is dependent on the processor selected. For Architecture 5 or
+-later, the default is to assembler for VFP instructions; for earlier
++later, the default is to assemble for VFP instructions; for earlier
+ architectures the default is to assemble for FPA instructions.
+
+ @cindex @code{-mthumb} command line option, ARM
+@@ -931,7 +934,7 @@ between Arm and Thumb instructions and s
+ interworking is not going to be performed. The presence of this
+ directive also implies @code{.thumb}
+
+-This directive is not neccessary when generating EABI objects. On these
++This directive is not necessary when generating EABI objects. On these
+ targets the encoding is implicit when generating Thumb code.
+
+ @cindex @code{.thumb_set} directive, ARM
+@@ -966,7 +969,7 @@ should only be done if it is really nece
+
+ @cindex @code{.unwind_raw} directive, ARM
+ @item .unwind_raw @var{offset}, @var{byte1}, @dots{}
+-Insert one of more arbitary unwind opcode bytes, which are known to adjust
++Insert one of more arbitrary unwind opcode bytes, which are known to adjust
+ the stack pointer by @var{offset} bytes.
+
+ For example @code{.unwind_raw 4, 0xb1, 0x01} is equivalent to
+diff -rup binutils.orig/gas/testsuite/gas/arm/archv8m-cmse-msr-base.d binutils-2.27/gas/testsuite/gas/arm/archv8m-cmse-msr-base.d
+--- binutils.orig/gas/testsuite/gas/arm/archv8m-cmse-msr-base.d 2017-08-09 10:26:30.056741684 +0100
++++ binutils-2.27/gas/testsuite/gas/arm/archv8m-cmse-msr-base.d 2017-08-09 11:51:59.357287965 +0100
+@@ -6,27 +6,71 @@
+ .*: +file format .*arm.*
+
+ Disassembly of section .text:
+-0+.* <[^>]*> f380 8808 msr MSP, r0
+-0+.* <[^>]*> f380 8808 msr MSP, r0
+-0+.* <[^>]*> f380 8888 msr MSP_NS, r0
+-0+.* <[^>]*> f380 8809 msr PSP, r0
+-0+.* <[^>]*> f380 8809 msr PSP, r0
+-0+.* <[^>]*> f380 8889 msr PSP_NS, r0
+-0+.* <[^>]*> f380 8808 msr MSP, r0
+-0+.* <[^>]*> f380 8808 msr MSP, r0
+-0+.* <[^>]*> f380 8888 msr MSP_NS, r0
+-0+.* <[^>]*> f380 8809 msr PSP, r0
+-0+.* <[^>]*> f380 8809 msr PSP, r0
+-0+.* <[^>]*> f380 8889 msr PSP_NS, r0
+-0+.* <[^>]*> f3ef 8008 mrs r0, MSP
+ 0+.* <[^>]*> f3ef 8008 mrs r0, MSP
+ 0+.* <[^>]*> f3ef 8088 mrs r0, MSP_NS
+-0+.* <[^>]*> f3ef 8009 mrs r0, PSP
+-0+.* <[^>]*> f3ef 8009 mrs r0, PSP
+-0+.* <[^>]*> f3ef 8089 mrs r0, PSP_NS
+-0+.* <[^>]*> f3ef 8008 mrs r0, MSP
+ 0+.* <[^>]*> f3ef 8008 mrs r0, MSP
+ 0+.* <[^>]*> f3ef 8088 mrs r0, MSP_NS
+-0+.* <[^>]*> f3ef 8009 mrs r0, PSP
+-0+.* <[^>]*> f3ef 8009 mrs r0, PSP
+-0+.* <[^>]*> f3ef 8089 mrs r0, PSP_NS
++0+.* <[^>]*> f3ef 8109 mrs r1, PSP
++0+.* <[^>]*> f3ef 8189 mrs r1, PSP_NS
++0+.* <[^>]*> f3ef 8109 mrs r1, PSP
++0+.* <[^>]*> f3ef 8189 mrs r1, PSP_NS
++0+.* <[^>]*> f3ef 820a mrs r2, MSPLIM
++0+.* <[^>]*> f3ef 828a mrs r2, MSPLIM_NS
++0+.* <[^>]*> f3ef 820a mrs r2, MSPLIM
++0+.* <[^>]*> f3ef 828a mrs r2, MSPLIM_NS
++0+.* <[^>]*> f3ef 830b mrs r3, PSPLIM
++0+.* <[^>]*> f3ef 838b mrs r3, PSPLIM_NS
++0+.* <[^>]*> f3ef 830b mrs r3, PSPLIM
++0+.* <[^>]*> f3ef 838b mrs r3, PSPLIM_NS
++0+.* <[^>]*> f3ef 8410 mrs r4, PRIMASK
++0+.* <[^>]*> f3ef 8490 mrs r4, PRIMASK_NS
++0+.* <[^>]*> f3ef 8410 mrs r4, PRIMASK
++0+.* <[^>]*> f3ef 8490 mrs r4, PRIMASK_NS
++0+.* <[^>]*> f3ef 8511 mrs r5, BASEPRI
++0+.* <[^>]*> f3ef 8591 mrs r5, BASEPRI_NS
++0+.* <[^>]*> f3ef 8511 mrs r5, BASEPRI
++0+.* <[^>]*> f3ef 8591 mrs r5, BASEPRI_NS
++0+.* <[^>]*> f3ef 8613 mrs r6, FAULTMASK
++0+.* <[^>]*> f3ef 8693 mrs r6, FAULTMASK_NS
++0+.* <[^>]*> f3ef 8613 mrs r6, FAULTMASK
++0+.* <[^>]*> f3ef 8693 mrs r6, FAULTMASK_NS
++0+.* <[^>]*> f3ef 8714 mrs r7, CONTROL
++0+.* <[^>]*> f3ef 8794 mrs r7, CONTROL_NS
++0+.* <[^>]*> f3ef 8714 mrs r7, CONTROL
++0+.* <[^>]*> f3ef 8794 mrs r7, CONTROL_NS
++0+.* <[^>]*> f3ef 8898 mrs r8, SP_NS
++0+.* <[^>]*> f3ef 8898 mrs r8, SP_NS
++0+.* <[^>]*> f380 8808 msr MSP, r0
++0+.* <[^>]*> f380 8888 msr MSP_NS, r0
++0+.* <[^>]*> f380 8808 msr MSP, r0
++0+.* <[^>]*> f380 8888 msr MSP_NS, r0
++0+.* <[^>]*> f381 8809 msr PSP, r1
++0+.* <[^>]*> f381 8889 msr PSP_NS, r1
++0+.* <[^>]*> f381 8809 msr PSP, r1
++0+.* <[^>]*> f381 8889 msr PSP_NS, r1
++0+.* <[^>]*> f382 880a msr MSPLIM, r2
++0+.* <[^>]*> f382 888a msr MSPLIM_NS, r2
++0+.* <[^>]*> f382 880a msr MSPLIM, r2
++0+.* <[^>]*> f382 888a msr MSPLIM_NS, r2
++0+.* <[^>]*> f383 880b msr PSPLIM, r3
++0+.* <[^>]*> f383 888b msr PSPLIM_NS, r3
++0+.* <[^>]*> f383 880b msr PSPLIM, r3
++0+.* <[^>]*> f383 888b msr PSPLIM_NS, r3
++0+.* <[^>]*> f384 8810 msr PRIMASK, r4
++0+.* <[^>]*> f384 8890 msr PRIMASK_NS, r4
++0+.* <[^>]*> f384 8810 msr PRIMASK, r4
++0+.* <[^>]*> f384 8890 msr PRIMASK_NS, r4
++0+.* <[^>]*> f385 8811 msr BASEPRI, r5
++0+.* <[^>]*> f385 8891 msr BASEPRI_NS, r5
++0+.* <[^>]*> f385 8811 msr BASEPRI, r5
++0+.* <[^>]*> f385 8891 msr BASEPRI_NS, r5
++0+.* <[^>]*> f386 8813 msr FAULTMASK, r6
++0+.* <[^>]*> f386 8893 msr FAULTMASK_NS, r6
++0+.* <[^>]*> f386 8813 msr FAULTMASK, r6
++0+.* <[^>]*> f386 8893 msr FAULTMASK_NS, r6
++0+.* <[^>]*> f387 8814 msr CONTROL, r7
++0+.* <[^>]*> f387 8894 msr CONTROL_NS, r7
++0+.* <[^>]*> f387 8814 msr CONTROL, r7
++0+.* <[^>]*> f387 8894 msr CONTROL_NS, r7
++0+.* <[^>]*> f388 8898 msr SP_NS, r8
++0+.* <[^>]*> f388 8898 msr SP_NS, r8
+diff -rup binutils.orig/gas/testsuite/gas/arm/archv8m-cmse-msr-main.d binutils-2.27/gas/testsuite/gas/arm/archv8m-cmse-msr-main.d
+--- binutils.orig/gas/testsuite/gas/arm/archv8m-cmse-msr-main.d 2017-08-09 10:26:30.056741684 +0100
++++ binutils-2.27/gas/testsuite/gas/arm/archv8m-cmse-msr-main.d 2017-08-09 11:52:33.776902849 +0100
+@@ -6,27 +6,71 @@
+ .*: +file format .*arm.*
+
+ Disassembly of section .text:
+-0+.* <[^>]*> f380 8808 msr MSP, r0
+-0+.* <[^>]*> f380 8808 msr MSP, r0
+-0+.* <[^>]*> f380 8888 msr MSP_NS, r0
+-0+.* <[^>]*> f380 8809 msr PSP, r0
+-0+.* <[^>]*> f380 8809 msr PSP, r0
+-0+.* <[^>]*> f380 8889 msr PSP_NS, r0
+-0+.* <[^>]*> f380 8808 msr MSP, r0
+-0+.* <[^>]*> f380 8808 msr MSP, r0
+-0+.* <[^>]*> f380 8888 msr MSP_NS, r0
+-0+.* <[^>]*> f380 8809 msr PSP, r0
+-0+.* <[^>]*> f380 8809 msr PSP, r0
+-0+.* <[^>]*> f380 8889 msr PSP_NS, r0
+-0+.* <[^>]*> f3ef 8008 mrs r0, MSP
+ 0+.* <[^>]*> f3ef 8008 mrs r0, MSP
+ 0+.* <[^>]*> f3ef 8088 mrs r0, MSP_NS
+-0+.* <[^>]*> f3ef 8009 mrs r0, PSP
+-0+.* <[^>]*> f3ef 8009 mrs r0, PSP
+-0+.* <[^>]*> f3ef 8089 mrs r0, PSP_NS
+-0+.* <[^>]*> f3ef 8008 mrs r0, MSP
+ 0+.* <[^>]*> f3ef 8008 mrs r0, MSP
+ 0+.* <[^>]*> f3ef 8088 mrs r0, MSP_NS
+-0+.* <[^>]*> f3ef 8009 mrs r0, PSP
+-0+.* <[^>]*> f3ef 8009 mrs r0, PSP
+-0+.* <[^>]*> f3ef 8089 mrs r0, PSP_NS
++0+.* <[^>]*> f3ef 8109 mrs r1, PSP
++0+.* <[^>]*> f3ef 8189 mrs r1, PSP_NS
++0+.* <[^>]*> f3ef 8109 mrs r1, PSP
++0+.* <[^>]*> f3ef 8189 mrs r1, PSP_NS
++0+.* <[^>]*> f3ef 820a mrs r2, MSPLIM
++0+.* <[^>]*> f3ef 828a mrs r2, MSPLIM_NS
++0+.* <[^>]*> f3ef 820a mrs r2, MSPLIM
++0+.* <[^>]*> f3ef 828a mrs r2, MSPLIM_NS
++0+.* <[^>]*> f3ef 830b mrs r3, PSPLIM
++0+.* <[^>]*> f3ef 838b mrs r3, PSPLIM_NS
++0+.* <[^>]*> f3ef 830b mrs r3, PSPLIM
++0+.* <[^>]*> f3ef 838b mrs r3, PSPLIM_NS
++0+.* <[^>]*> f3ef 8410 mrs r4, PRIMASK
++0+.* <[^>]*> f3ef 8490 mrs r4, PRIMASK_NS
++0+.* <[^>]*> f3ef 8410 mrs r4, PRIMASK
++0+.* <[^>]*> f3ef 8490 mrs r4, PRIMASK_NS
++0+.* <[^>]*> f3ef 8511 mrs r5, BASEPRI
++0+.* <[^>]*> f3ef 8591 mrs r5, BASEPRI_NS
++0+.* <[^>]*> f3ef 8511 mrs r5, BASEPRI
++0+.* <[^>]*> f3ef 8591 mrs r5, BASEPRI_NS
++0+.* <[^>]*> f3ef 8613 mrs r6, FAULTMASK
++0+.* <[^>]*> f3ef 8693 mrs r6, FAULTMASK_NS
++0+.* <[^>]*> f3ef 8613 mrs r6, FAULTMASK
++0+.* <[^>]*> f3ef 8693 mrs r6, FAULTMASK_NS
++0+.* <[^>]*> f3ef 8714 mrs r7, CONTROL
++0+.* <[^>]*> f3ef 8794 mrs r7, CONTROL_NS
++0+.* <[^>]*> f3ef 8714 mrs r7, CONTROL
++0+.* <[^>]*> f3ef 8794 mrs r7, CONTROL_NS
++0+.* <[^>]*> f3ef 8898 mrs r8, SP_NS
++0+.* <[^>]*> f3ef 8898 mrs r8, SP_NS
++0+.* <[^>]*> f380 8808 msr MSP, r0
++0+.* <[^>]*> f380 8888 msr MSP_NS, r0
++0+.* <[^>]*> f380 8808 msr MSP, r0
++0+.* <[^>]*> f380 8888 msr MSP_NS, r0
++0+.* <[^>]*> f381 8809 msr PSP, r1
++0+.* <[^>]*> f381 8889 msr PSP_NS, r1
++0+.* <[^>]*> f381 8809 msr PSP, r1
++0+.* <[^>]*> f381 8889 msr PSP_NS, r1
++0+.* <[^>]*> f382 880a msr MSPLIM, r2
++0+.* <[^>]*> f382 888a msr MSPLIM_NS, r2
++0+.* <[^>]*> f382 880a msr MSPLIM, r2
++0+.* <[^>]*> f382 888a msr MSPLIM_NS, r2
++0+.* <[^>]*> f383 880b msr PSPLIM, r3
++0+.* <[^>]*> f383 888b msr PSPLIM_NS, r3
++0+.* <[^>]*> f383 880b msr PSPLIM, r3
++0+.* <[^>]*> f383 888b msr PSPLIM_NS, r3
++0+.* <[^>]*> f384 8810 msr PRIMASK, r4
++0+.* <[^>]*> f384 8890 msr PRIMASK_NS, r4
++0+.* <[^>]*> f384 8810 msr PRIMASK, r4
++0+.* <[^>]*> f384 8890 msr PRIMASK_NS, r4
++0+.* <[^>]*> f385 8811 msr BASEPRI, r5
++0+.* <[^>]*> f385 8891 msr BASEPRI_NS, r5
++0+.* <[^>]*> f385 8811 msr BASEPRI, r5
++0+.* <[^>]*> f385 8891 msr BASEPRI_NS, r5
++0+.* <[^>]*> f386 8813 msr FAULTMASK, r6
++0+.* <[^>]*> f386 8893 msr FAULTMASK_NS, r6
++0+.* <[^>]*> f386 8813 msr FAULTMASK, r6
++0+.* <[^>]*> f386 8893 msr FAULTMASK_NS, r6
++0+.* <[^>]*> f387 8814 msr CONTROL, r7
++0+.* <[^>]*> f387 8894 msr CONTROL_NS, r7
++0+.* <[^>]*> f387 8814 msr CONTROL, r7
++0+.* <[^>]*> f387 8894 msr CONTROL_NS, r7
++0+.* <[^>]*> f388 8898 msr SP_NS, r8
++0+.* <[^>]*> f388 8898 msr SP_NS, r8
+diff -rup binutils.orig/gas/testsuite/gas/arm/archv8m-cmse-msr.s binutils-2.27/gas/testsuite/gas/arm/archv8m-cmse-msr.s
+--- binutils.orig/gas/testsuite/gas/arm/archv8m-cmse-msr.s 2017-08-09 10:26:30.056741684 +0100
++++ binutils-2.27/gas/testsuite/gas/arm/archv8m-cmse-msr.s 2017-08-09 11:50:44.728124484 +0100
+@@ -1,25 +1,109 @@
+ T:
+-msr MSP, r0
+-msr MSP_S, r0
+-msr MSP_NS, r0
+-msr PSP, r0
+-msr PSP_S, r0
+-msr PSP_NS, r0
+-msr msp, r0
+-msr msp_s, r0
+-msr msp_ns, r0
+-msr psp, r0
+-msr psp_s, r0
+-msr psp_ns, r0
++## MRS ##
++
++# MSP
+ mrs r0, MSP
+-mrs r0, MSP_S
+ mrs r0, MSP_NS
+-mrs r0, PSP
+-mrs r0, PSP_S
+-mrs r0, PSP_NS
+ mrs r0, msp
+-mrs r0, msp_s
+ mrs r0, msp_ns
+-mrs r0, psp
+-mrs r0, psp_s
+-mrs r0, psp_ns
++
++# PSP
++mrs r1, PSP
++mrs r1, PSP_NS
++mrs r1, psp
++mrs r1, psp_ns
++
++# MSPLIM
++mrs r2, MSPLIM
++mrs r2, MSPLIM_NS
++mrs r2, msplim
++mrs r2, msplim_ns
++
++# PSPLIM
++mrs r3, PSPLIM
++mrs r3, PSPLIM_NS
++mrs r3, psplim
++mrs r3, psplim_ns
++
++# PRIMASK
++mrs r4, PRIMASK
++mrs r4, PRIMASK_NS
++mrs r4, primask
++mrs r4, primask_ns
++
++# BASEPRI
++mrs r5, BASEPRI
++mrs r5, BASEPRI_NS
++mrs r5, basepri
++mrs r5, basepri_ns
++
++# FAULTMASK
++mrs r6, FAULTMASK
++mrs r6, FAULTMASK_NS
++mrs r6, faultmask
++mrs r6, faultmask_ns
++
++# CONTROL
++mrs r7, CONTROL
++mrs r7, CONTROL_NS
++mrs r7, control
++mrs r7, control_ns
++
++# SP_NS
++mrs r8, SP_NS
++mrs r8, sp_ns
++
++
++## MSR ##
++
++# MSP
++msr MSP, r0
++msr MSP_NS, r0
++msr msp, r0
++msr msp_ns, r0
++
++# PSP
++msr PSP, r1
++msr PSP_NS, r1
++msr psp, r1
++msr psp_ns, r1
++
++# MSPLIM
++msr MSPLIM, r2
++msr MSPLIM_NS, r2
++msr msplim, r2
++msr msplim_ns, r2
++
++# PSPLIM
++msr PSPLIM, r3
++msr PSPLIM_NS, r3
++msr psplim, r3
++msr psplim_ns, r3
++
++# PRIMASK
++msr PRIMASK, r4
++msr PRIMASK_NS, r4
++msr primask, r4
++msr primask_ns, r4
++
++# BASEPRI
++msr BASEPRI, r5
++msr BASEPRI_NS, r5
++msr basepri, r5
++msr basepri_ns, r5
++
++# FAULTMASK
++msr FAULTMASK, r6
++msr FAULTMASK_NS, r6
++msr faultmask, r6
++msr faultmask_ns, r6
++
++# CONTROL
++msr CONTROL, r7
++msr CONTROL_NS, r7
++msr control, r7
++msr control_ns, r7
++
++# SP_NS
++msr SP_NS, r8
++msr sp_ns, r8
+diff -rup binutils.orig/gas/testsuite/gas/arm/archv8m-main-dsp-4.d binutils-2.27/gas/testsuite/gas/arm/archv8m-main-dsp-4.d
+--- binutils.orig/gas/testsuite/gas/arm/archv8m-main-dsp-4.d 2017-08-09 10:26:30.056741684 +0100
++++ binutils-2.27/gas/testsuite/gas/arm/archv8m-main-dsp-4.d 2017-08-09 11:54:37.162524973 +0100
+@@ -6,27 +6,71 @@
+ .*: +file format .*arm.*
+
+ Disassembly of section .text:
+-0+.* <[^>]*> f380 8808 msr MSP, r0
+-0+.* <[^>]*> f380 8808 msr MSP, r0
+-0+.* <[^>]*> f380 8888 msr MSP_NS, r0
+-0+.* <[^>]*> f380 8809 msr PSP, r0
+-0+.* <[^>]*> f380 8809 msr PSP, r0
+-0+.* <[^>]*> f380 8889 msr PSP_NS, r0
+-0+.* <[^>]*> f380 8808 msr MSP, r0
+-0+.* <[^>]*> f380 8808 msr MSP, r0
+-0+.* <[^>]*> f380 8888 msr MSP_NS, r0
+-0+.* <[^>]*> f380 8809 msr PSP, r0
+-0+.* <[^>]*> f380 8809 msr PSP, r0
+-0+.* <[^>]*> f380 8889 msr PSP_NS, r0
+-0+.* <[^>]*> f3ef 8008 mrs r0, MSP
+ 0+.* <[^>]*> f3ef 8008 mrs r0, MSP
+ 0+.* <[^>]*> f3ef 8088 mrs r0, MSP_NS
+-0+.* <[^>]*> f3ef 8009 mrs r0, PSP
+-0+.* <[^>]*> f3ef 8009 mrs r0, PSP
+-0+.* <[^>]*> f3ef 8089 mrs r0, PSP_NS
+-0+.* <[^>]*> f3ef 8008 mrs r0, MSP
+ 0+.* <[^>]*> f3ef 8008 mrs r0, MSP
+ 0+.* <[^>]*> f3ef 8088 mrs r0, MSP_NS
+-0+.* <[^>]*> f3ef 8009 mrs r0, PSP
+-0+.* <[^>]*> f3ef 8009 mrs r0, PSP
+-0+.* <[^>]*> f3ef 8089 mrs r0, PSP_NS
++0+.* <[^>]*> f3ef 8109 mrs r1, PSP
++0+.* <[^>]*> f3ef 8189 mrs r1, PSP_NS
++0+.* <[^>]*> f3ef 8109 mrs r1, PSP
++0+.* <[^>]*> f3ef 8189 mrs r1, PSP_NS
++0+.* <[^>]*> f3ef 820a mrs r2, MSPLIM
++0+.* <[^>]*> f3ef 828a mrs r2, MSPLIM_NS
++0+.* <[^>]*> f3ef 820a mrs r2, MSPLIM
++0+.* <[^>]*> f3ef 828a mrs r2, MSPLIM_NS
++0+.* <[^>]*> f3ef 830b mrs r3, PSPLIM
++0+.* <[^>]*> f3ef 838b mrs r3, PSPLIM_NS
++0+.* <[^>]*> f3ef 830b mrs r3, PSPLIM
++0+.* <[^>]*> f3ef 838b mrs r3, PSPLIM_NS
++0+.* <[^>]*> f3ef 8410 mrs r4, PRIMASK
++0+.* <[^>]*> f3ef 8490 mrs r4, PRIMASK_NS
++0+.* <[^>]*> f3ef 8410 mrs r4, PRIMASK
++0+.* <[^>]*> f3ef 8490 mrs r4, PRIMASK_NS
++0+.* <[^>]*> f3ef 8511 mrs r5, BASEPRI
++0+.* <[^>]*> f3ef 8591 mrs r5, BASEPRI_NS
++0+.* <[^>]*> f3ef 8511 mrs r5, BASEPRI
++0+.* <[^>]*> f3ef 8591 mrs r5, BASEPRI_NS
++0+.* <[^>]*> f3ef 8613 mrs r6, FAULTMASK
++0+.* <[^>]*> f3ef 8693 mrs r6, FAULTMASK_NS
++0+.* <[^>]*> f3ef 8613 mrs r6, FAULTMASK
++0+.* <[^>]*> f3ef 8693 mrs r6, FAULTMASK_NS
++0+.* <[^>]*> f3ef 8714 mrs r7, CONTROL
++0+.* <[^>]*> f3ef 8794 mrs r7, CONTROL_NS
++0+.* <[^>]*> f3ef 8714 mrs r7, CONTROL
++0+.* <[^>]*> f3ef 8794 mrs r7, CONTROL_NS
++0+.* <[^>]*> f3ef 8898 mrs r8, SP_NS
++0+.* <[^>]*> f3ef 8898 mrs r8, SP_NS
++0+.* <[^>]*> f380 8808 msr MSP, r0
++0+.* <[^>]*> f380 8888 msr MSP_NS, r0
++0+.* <[^>]*> f380 8808 msr MSP, r0
++0+.* <[^>]*> f380 8888 msr MSP_NS, r0
++0+.* <[^>]*> f381 8809 msr PSP, r1
++0+.* <[^>]*> f381 8889 msr PSP_NS, r1
++0+.* <[^>]*> f381 8809 msr PSP, r1
++0+.* <[^>]*> f381 8889 msr PSP_NS, r1
++0+.* <[^>]*> f382 880a msr MSPLIM, r2
++0+.* <[^>]*> f382 888a msr MSPLIM_NS, r2
++0+.* <[^>]*> f382 880a msr MSPLIM, r2
++0+.* <[^>]*> f382 888a msr MSPLIM_NS, r2
++0+.* <[^>]*> f383 880b msr PSPLIM, r3
++0+.* <[^>]*> f383 888b msr PSPLIM_NS, r3
++0+.* <[^>]*> f383 880b msr PSPLIM, r3
++0+.* <[^>]*> f383 888b msr PSPLIM_NS, r3
++0+.* <[^>]*> f384 8810 msr PRIMASK, r4
++0+.* <[^>]*> f384 8890 msr PRIMASK_NS, r4
++0+.* <[^>]*> f384 8810 msr PRIMASK, r4
++0+.* <[^>]*> f384 8890 msr PRIMASK_NS, r4
++0+.* <[^>]*> f385 8811 msr BASEPRI, r5
++0+.* <[^>]*> f385 8891 msr BASEPRI_NS, r5
++0+.* <[^>]*> f385 8811 msr BASEPRI, r5
++0+.* <[^>]*> f385 8891 msr BASEPRI_NS, r5
++0+.* <[^>]*> f386 8813 msr FAULTMASK, r6
++0+.* <[^>]*> f386 8893 msr FAULTMASK_NS, r6
++0+.* <[^>]*> f386 8813 msr FAULTMASK, r6
++0+.* <[^>]*> f386 8893 msr FAULTMASK_NS, r6
++0+.* <[^>]*> f387 8814 msr CONTROL, r7
++0+.* <[^>]*> f387 8894 msr CONTROL_NS, r7
++0+.* <[^>]*> f387 8814 msr CONTROL, r7
++0+.* <[^>]*> f387 8894 msr CONTROL_NS, r7
++0+.* <[^>]*> f388 8898 msr SP_NS, r8
++0+.* <[^>]*> f388 8898 msr SP_NS, r8
+diff -rup binutils.orig/gas/testsuite/gas/arm/attr-march-armv1.d binutils-2.27/gas/testsuite/gas/arm/attr-march-armv1.d
+--- binutils.orig/gas/testsuite/gas/arm/attr-march-armv1.d 2017-08-09 10:26:30.058741661 +0100
++++ binutils-2.27/gas/testsuite/gas/arm/attr-march-armv1.d 2017-08-09 11:56:00.992588823 +0100
+@@ -8,5 +8,4 @@
+ Attribute Section: aeabi
+ File Attributes
+ Tag_CPU_name: "1"
+- Tag_CPU_arch: v4
+ Tag_ARM_ISA_use: Yes
+diff -rup binutils.orig/gas/testsuite/gas/arm/attr-march-armv2a.d binutils-2.27/gas/testsuite/gas/arm/attr-march-armv2a.d
+--- binutils.orig/gas/testsuite/gas/arm/attr-march-armv2a.d 2017-08-09 10:26:30.058741661 +0100
++++ binutils-2.27/gas/testsuite/gas/arm/attr-march-armv2a.d 2017-08-09 11:56:27.548292268 +0100
+@@ -8,5 +8,4 @@
+ Attribute Section: aeabi
+ File Attributes
+ Tag_CPU_name: "2A"
+- Tag_CPU_arch: v4
+ Tag_ARM_ISA_use: Yes
+diff -rup binutils.orig/gas/testsuite/gas/arm/attr-march-armv2.d binutils-2.27/gas/testsuite/gas/arm/attr-march-armv2.d
+--- binutils.orig/gas/testsuite/gas/arm/attr-march-armv2.d 2017-08-09 10:26:30.058741661 +0100
++++ binutils-2.27/gas/testsuite/gas/arm/attr-march-armv2.d 2017-08-09 11:56:09.713491434 +0100
+@@ -8,5 +8,4 @@
+ Attribute Section: aeabi
+ File Attributes
+ Tag_CPU_name: "2"
+- Tag_CPU_arch: v4
+ Tag_ARM_ISA_use: Yes
+diff -rup binutils.orig/gas/testsuite/gas/arm/attr-march-armv2s.d binutils-2.27/gas/testsuite/gas/arm/attr-march-armv2s.d
+--- binutils.orig/gas/testsuite/gas/arm/attr-march-armv2s.d 2017-08-09 10:26:30.058741661 +0100
++++ binutils-2.27/gas/testsuite/gas/arm/attr-march-armv2s.d 2017-08-09 11:56:35.794200184 +0100
+@@ -8,5 +8,4 @@
+ Attribute Section: aeabi
+ File Attributes
+ Tag_CPU_name: "2S"
+- Tag_CPU_arch: v4
+ Tag_ARM_ISA_use: Yes
+diff -rup binutils.orig/gas/testsuite/gas/arm/attr-march-armv3.d binutils-2.27/gas/testsuite/gas/arm/attr-march-armv3.d
+--- binutils.orig/gas/testsuite/gas/arm/attr-march-armv3.d 2017-08-09 10:26:30.058741661 +0100
++++ binutils-2.27/gas/testsuite/gas/arm/attr-march-armv3.d 2017-08-09 11:56:52.435014353 +0100
+@@ -8,5 +8,4 @@
+ Attribute Section: aeabi
+ File Attributes
+ Tag_CPU_name: "3"
+- Tag_CPU_arch: v4
+ Tag_ARM_ISA_use: Yes
+diff -rup binutils.orig/gas/testsuite/gas/arm/attr-march-armv3m.d binutils-2.27/gas/testsuite/gas/arm/attr-march-armv3m.d
+--- binutils.orig/gas/testsuite/gas/arm/attr-march-armv3m.d 2017-08-09 10:26:30.058741661 +0100
++++ binutils-2.27/gas/testsuite/gas/arm/attr-march-armv3m.d 2017-08-09 11:56:57.715955379 +0100
+@@ -8,5 +8,4 @@
+ Attribute Section: aeabi
+ File Attributes
+ Tag_CPU_name: "3M"
+- Tag_CPU_arch: v4
+ Tag_ARM_ISA_use: Yes
+diff -rup binutils.orig/gas/testsuite/gas/arm/ldr-bad.l binutils-2.27/gas/testsuite/gas/arm/ldr-bad.l
+--- binutils.orig/gas/testsuite/gas/arm/ldr-bad.l 2017-08-09 10:26:30.062741616 +0100
++++ binutils-2.27/gas/testsuite/gas/arm/ldr-bad.l 2017-08-09 11:59:45.777078600 +0100
+@@ -1,7 +1,7 @@
+ [^:]*: Assembler messages:
+ [^:]*:5: Warning: destination register same as write-back base
+-[^:]*:9: Error: ldr to register 15 must be 4-byte alligned -- `ldr r15,\[r15,#5\]'
+-[^:]*:12: Error: ldr to register 15 must be 4-byte alligned -- `ldr r15,.-0xab7'
++[^:]*:9: Error: ldr to register 15 must be 4-byte aligned -- `ldr r15,\[r15,#5\]'
++[^:]*:12: Error: ldr to register 15 must be 4-byte aligned -- `ldr r15,.-0xab7'
+ [^:]*:15: Warning: destination register same as write-back base
+ [^:]*:16: Error: cannot use register index with PC-relative addressing -- `ldr r2,\[r15,r2\]!'
+ [^:]*:19: Error: cannot use register index with PC-relative addressing -- `ldr r1,\[r1,r15\]'
+diff -rup binutils.orig/gas/testsuite/gas/arm/ldr-t-bad.l binutils-2.27/gas/testsuite/gas/arm/ldr-t-bad.l
+--- binutils.orig/gas/testsuite/gas/arm/ldr-t-bad.l 2017-08-09 10:26:30.062741616 +0100
++++ binutils-2.27/gas/testsuite/gas/arm/ldr-t-bad.l 2017-08-09 12:00:06.268849764 +0100
+@@ -1,9 +1,9 @@
+ [^:]*: Assembler messages:
+ [^:]*:8: Error: registers may not be the same -- `ldr r1,\[r1,#5\]!'
+-[^:]*:12: Error: ldr to register 15 must be 4-byte alligned -- `ldr r15,\[r15,#5\]'
++[^:]*:12: Error: ldr to register 15 must be 4-byte aligned -- `ldr r15,\[r15,#5\]'
+ [^:]*:16: Error: branch must be last instruction in IT block -- `ldrge r15,\[r15,#4\]'
+ [^:]*:25: Error: branch must be last instruction in IT block -- `ldrge r15,.0x4'
+-[^:]*:30: Error: ldr to register 15 must be 4-byte alligned -- `ldr r15,.-0xab7'
++[^:]*:30: Error: ldr to register 15 must be 4-byte aligned -- `ldr r15,.-0xab7'
+ [^:]*:36: Error: branch must be last instruction in IT block -- `ldrge r15,\[r15,r1\]'
+ [^:]*:41: Error: r13 not allowed here -- `ldr r1,\[r2,r13\]'
+ [^:]*:42: Error: r15 not allowed here -- `ldr r2,\[r2,r15\]'
+diff -rup binutils.orig/gas/testsuite/gas/arm/ld-sp-warn.l binutils-2.27/gas/testsuite/gas/arm/ld-sp-warn.l
+--- binutils.orig/gas/testsuite/gas/arm/ld-sp-warn.l 2017-08-09 10:26:30.062741616 +0100
++++ binutils-2.27/gas/testsuite/gas/arm/ld-sp-warn.l 2017-08-09 11:59:02.223564973 +0100
+@@ -2,4 +2,3 @@
+ [^:]*:3: Warning: This instruction may be unpredictable if executed on M-profile cores with interrupts enabled.
+ [^:]*:4: Warning: This instruction may be unpredictable if executed on M-profile cores with interrupts enabled.
+ [^:]*:7: Error: Thumb does not support register indexing with writeback -- `ldr r1,\[r0,r1\]!'
+-[^:]*:8: Error: r13 not allowed here -- `ldrsb sp,\[r2,#16\]!'
+diff -rup binutils.orig/gas/testsuite/gas/arm/strex-bad-t.d binutils-2.27/gas/testsuite/gas/arm/strex-bad-t.d
+--- binutils.orig/gas/testsuite/gas/arm/strex-bad-t.d 2017-08-09 10:26:30.066741571 +0100
++++ binutils-2.27/gas/testsuite/gas/arm/strex-bad-t.d 2017-08-09 12:01:22.679996462 +0100
+@@ -1,3 +1,4 @@
+ # name: Bad addressing modes STREXH/STREXB. - THUMB
++# as: -march=armv7-a
+ # error-output: strex-bad-t.l
+
+diff -rup binutils.orig/gas/testsuite/gas/arm/thumb2_ldr_immediate_highregs_armv6t2.d binutils-2.27/gas/testsuite/gas/arm/thumb2_ldr_immediate_highregs_armv6t2.d
+--- binutils.orig/gas/testsuite/gas/arm/thumb2_ldr_immediate_highregs_armv6t2.d 2017-08-09 10:26:30.067741560 +0100
++++ binutils-2.27/gas/testsuite/gas/arm/thumb2_ldr_immediate_highregs_armv6t2.d 2017-08-09 11:57:45.943416812 +0100
+@@ -6,19 +6,23 @@
+ .*: +file format .*arm.*
+
+ Disassembly of section \.text:
+-0[0-9a-f]+ <[^>]+> 2000[[:space:]]+movs[[:space:]]+r0, #0.*
+-0[0-9a-f]+ <[^>]+> 2108[[:space:]]+movs[[:space:]]+r1, #8.*
+-0[0-9a-f]+ <[^>]+> 2251[[:space:]]+movs[[:space:]]+r2, #81.*
+-0[0-9a-f]+ <[^>]+> 231f[[:space:]]+movs[[:space:]]+r3, #31.*
+-0[0-9a-f]+ <[^>]+> 242f[[:space:]]+movs[[:space:]]+r4, #47.*
+-0[0-9a-f]+ <[^>]+> 253f[[:space:]]+movs[[:space:]]+r5, #63.*
+-0[0-9a-f]+ <[^>]+> 2680[[:space:]]+movs[[:space:]]+r6, #128.*
+-0[0-9a-f]+ <[^>]+> 27ff[[:space:]]+movs[[:space:]]+r7, #255.*
++0[0-9a-f]+ <[^>]+> f04f 0000[[:space:]]+mov\.w[[:space:]]+r0, #0.*
++0[0-9a-f]+ <[^>]+> f04f 0108[[:space:]]+mov\.w[[:space:]]+r1, #8.*
++0[0-9a-f]+ <[^>]+> f04f 0251[[:space:]]+mov\.w[[:space:]]+r2, #81.*
++0[0-9a-f]+ <[^>]+> f04f 031f[[:space:]]+mov\.w[[:space:]]+r3, #31.*
++0[0-9a-f]+ <[^>]+> f04f 042f[[:space:]]+mov\.w[[:space:]]+r4, #47.*
++0[0-9a-f]+ <[^>]+> f04f 053f[[:space:]]+mov\.w[[:space:]]+r5, #63.*
++0[0-9a-f]+ <[^>]+> f04f 0680[[:space:]]+mov\.w[[:space:]]+r6, #128.*
++0[0-9a-f]+ <[^>]+> f04f 07ff[[:space:]]+mov\.w[[:space:]]+r7, #255.*
+ 0[0-9a-f]+ <[^>]+> f04f 0800[[:space:]]+mov\.w[[:space:]]+r8, #0.*
+ 0[0-9a-f]+ <[^>]+> f04f 0908[[:space:]]+mov\.w[[:space:]]+r9, #8.*
+ 0[0-9a-f]+ <[^>]+> f04f 0a51[[:space:]]+mov\.w[[:space:]]+sl, #81.*
+ 0[0-9a-f]+ <[^>]+> f04f 0b1f[[:space:]]+mov\.w[[:space:]]+fp, #31.*
+ 0[0-9a-f]+ <[^>]+> f04f 0c2f[[:space:]]+mov\.w[[:space:]]+ip, #47.*
+-0[0-9a-f]+ <[^>]+> f04f 0d3f[[:space:]]+mov\.w[[:space:]]+sp, #63.*
+ 0[0-9a-f]+ <[^>]+> f04f 0e80[[:space:]]+mov\.w[[:space:]]+lr, #128.*
+-0[0-9a-f]+ <[^>]+> f04f 0fff[[:space:]]+mov\.w[[:space:]]+pc, #255.*
++0[0-9a-f]+ <[^>]+> f64f 78ff[[:space:]]+movw[[:space:]]+r8, #65535.*
++0[0-9a-f]+ <[^>]+> f24f 09f0[[:space:]]+movw[[:space:]]+r9, #61680.*
++0[0-9a-f]+ <[^>]+> f8df d004[[:space:]]+ldr\.w[[:space:]]+sp, \[pc, #4\].*
++0[0-9a-f]+ <[^>]+> f8df f004[[:space:]]+ldr\.w[[:space:]]+pc, \[pc, #4\].*
++0[0-9a-f]+ <[^>]+> 0000003f[[:space:]]+.word[[:space:]]+0x0000003f.*
++0[0-9a-f]+ <[^>]+> 000000ff[[:space:]]+.word[[:space:]]+0x000000ff.*
+diff -rup binutils.orig/gas/testsuite/gas/arm/thumb2_ldr_immediate_highregs_armv6t2.s binutils-2.27/gas/testsuite/gas/arm/thumb2_ldr_immediate_highregs_armv6t2.s
+--- binutils.orig/gas/testsuite/gas/arm/thumb2_ldr_immediate_highregs_armv6t2.s 2017-08-09 10:26:30.067741560 +0100
++++ binutils-2.27/gas/testsuite/gas/arm/thumb2_ldr_immediate_highregs_armv6t2.s 2017-08-09 11:58:27.561952048 +0100
+@@ -2,8 +2,8 @@
+ .syntax unified
+ .thumb_func
+ thumb2_ldr:
+- # These can be encoded into movs since constant is small
+- # And register can be encoded in 3 bits
++ # These must be encoded into mov.w despite constant and register being
++ # small enough as ldr should not generate a flag-setting instruction.
+ ldr r0,=0x00
+ ldr r1,=0x08
+ ldr r2,=0x51
+@@ -12,13 +12,19 @@ thumb2_ldr:
+ ldr r5,=0x3F
+ ldr r6,=0x80
+ ldr r7,=0xFF
+- # These shall be encoded into mov.w
+- # Since register cannot be encoded in 3 bits
++ # These shall be encoded into mov.w since register cannot be encoded in
++ # 3 bits
+ ldr r8,=0x00
+ ldr r9,=0x08
+ ldr r10,=0x51
+ ldr r11,=0x1F
+ ldr r12,=0x2F
+- ldr r13,=0x3F
+ ldr r14,=0x80
++ # These shall be encoded into movw since immediate cannot be encoded
++ # with mov.w
++ ldr r8,=0xFFFF
++ ldr r9,=0xF0F0
++ # These should be encoded as ldr since mov immediate is unpredictable
++ # for sp and pc
++ ldr r13,=0x3F
+ ldr r15,=0xFF
+diff -rup binutils.orig/include/opcode/arm.h binutils-2.27/include/opcode/arm.h
+--- binutils.orig/include/opcode/arm.h 2017-08-09 10:26:30.209739969 +0100
++++ binutils-2.27/include/opcode/arm.h 2017-08-09 11:11:08.487736404 +0100
+@@ -64,6 +64,8 @@
+ #define ARM_EXT2_FP16_INST 0x00000020 /* ARM V8.2A FP16 instructions. */
+ #define ARM_EXT2_V8M_MAIN 0x00000040 /* ARMv8-M Mainline. */
+ #define ARM_EXT2_RAS 0x00000080 /* RAS extension. */
++#define ARM_EXT2_V8_3A 0x00000100 /* ARM V8.3A. */
++#define ARM_EXT2_V8A 0x00000200 /* ARMv8-A. */
+
+ /* Co-processor space extensions. */
+ #define ARM_CEXT_XSCALE 0x00000001 /* Allow MIA etc. */
+@@ -92,6 +94,7 @@
+ #define CRC_EXT_ARMV8 0x00004000 /* CRC32 for ARMv8. */
+ #define FPU_VFP_EXT_ARMV8xD 0x00002000 /* Single-precision FP for ARMv8. */
+ #define FPU_NEON_EXT_RDMA 0x00001000 /* v8.1 Adv.SIMD extensions. */
++#define FPU_NEON_EXT_DOTPROD 0x00000800 /* Dot Product extension. */
+
+ /* Architectures are the sum of the base and extensions. The ARM ARM (rev E)
+ defines the following: ARMv3, ARMv3M, ARMv4xM, ARMv4, ARMv4TxM, ARMv4T,
+@@ -105,12 +108,14 @@
+ #define ARM_AEXT_V3M (ARM_AEXT_V3 | ARM_EXT_V3M)
+ #define ARM_AEXT_V4xM (ARM_AEXT_V3 | ARM_EXT_V4)
+ #define ARM_AEXT_V4 (ARM_AEXT_V3M | ARM_EXT_V4)
+-#define ARM_AEXT_V4TxM (ARM_AEXT_V4xM | ARM_EXT_V4T)
+-#define ARM_AEXT_V4T (ARM_AEXT_V4 | ARM_EXT_V4T)
++#define ARM_AEXT_V4TxM (ARM_AEXT_V4xM | ARM_EXT_V4T | ARM_EXT_OS)
++#define ARM_AEXT_V4T (ARM_AEXT_V4 | ARM_EXT_V4T | ARM_EXT_OS)
+ #define ARM_AEXT_V5xM (ARM_AEXT_V4xM | ARM_EXT_V5)
+ #define ARM_AEXT_V5 (ARM_AEXT_V4 | ARM_EXT_V5)
+-#define ARM_AEXT_V5TxM (ARM_AEXT_V5xM | ARM_EXT_V4T | ARM_EXT_V5T)
+-#define ARM_AEXT_V5T (ARM_AEXT_V5 | ARM_EXT_V4T | ARM_EXT_V5T)
++#define ARM_AEXT_V5TxM (ARM_AEXT_V5xM | ARM_EXT_V4T | ARM_EXT_V5T \
++ | ARM_EXT_OS)
++#define ARM_AEXT_V5T (ARM_AEXT_V5 | ARM_EXT_V4T | ARM_EXT_V5T \
++ | ARM_EXT_OS)
+ #define ARM_AEXT_V5TExP (ARM_AEXT_V5T | ARM_EXT_V5ExP)
+ #define ARM_AEXT_V5TE (ARM_AEXT_V5TExP | ARM_EXT_V5E)
+ #define ARM_AEXT_V5TEJ (ARM_AEXT_V5TE | ARM_EXT_V5J)
+@@ -135,7 +140,7 @@
+ #define ARM_AEXT_V6M_ONLY \
+ ((ARM_EXT_BARRIER | ARM_EXT_V6M | ARM_EXT_THUMB_MSR) & ~(ARM_AEXT_NOTM))
+ #define ARM_AEXT_V6M \
+- ((ARM_AEXT_V6K | ARM_AEXT_V6M_ONLY) & ~(ARM_AEXT_NOTM))
++ ((ARM_AEXT_V6K | ARM_AEXT_V6M_ONLY) & ~(ARM_AEXT_NOTM | ARM_EXT_OS))
+ #define ARM_AEXT_V6SM (ARM_AEXT_V6M | ARM_EXT_OS)
+ #define ARM_AEXT_V7M \
+ ((ARM_AEXT_V7_ARM | ARM_EXT_V6M | ARM_EXT_V7M | ARM_EXT_DIV) \
+@@ -146,13 +151,19 @@
+ #define ARM_AEXT_V8A \
+ (ARM_AEXT_V7A | ARM_EXT_MP | ARM_EXT_SEC | ARM_EXT_DIV | ARM_EXT_ADIV \
+ | ARM_EXT_VIRT | ARM_EXT_V8)
+-#define ARM_AEXT2_V8A (ARM_EXT2_V6T2_V8M | ARM_EXT2_ATOMICS)
++#define ARM_AEXT2_V8AR (ARM_EXT2_V6T2_V8M | ARM_EXT2_ATOMICS)
++#define ARM_AEXT2_V8A (ARM_AEXT2_V8AR | ARM_EXT2_V8A)
+ #define ARM_AEXT2_V8_1A (ARM_AEXT2_V8A | ARM_EXT2_PAN)
+ #define ARM_AEXT2_V8_2A (ARM_AEXT2_V8_1A | ARM_EXT2_V8_2A | ARM_EXT2_RAS)
++#define ARM_AEXT2_V8_3A (ARM_AEXT2_V8_2A | ARM_EXT2_V8_3A)
+ #define ARM_AEXT_V8M_BASE (ARM_AEXT_V6SM | ARM_EXT_DIV)
+ #define ARM_AEXT_V8M_MAIN ARM_AEXT_V7M
++#define ARM_AEXT_V8M_MAIN_DSP ARM_AEXT_V7EM
+ #define ARM_AEXT2_V8M (ARM_EXT2_V8M | ARM_EXT2_ATOMICS | ARM_EXT2_V6T2_V8M)
+ #define ARM_AEXT2_V8M_MAIN (ARM_AEXT2_V8M | ARM_EXT2_V8M_MAIN)
++#define ARM_AEXT2_V8M_MAIN_DSP ARM_AEXT2_V8M_MAIN
++#define ARM_AEXT_V8R ARM_AEXT_V8A
++#define ARM_AEXT2_V8R ARM_AEXT2_V8AR
+
+ /* Processors with specific extensions in the co-processor space. */
+ #define ARM_ARCH_XSCALE ARM_FEATURE_LOW (ARM_AEXT_V5TE, ARM_CEXT_XSCALE)
+@@ -224,6 +235,8 @@
+ #define FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1 \
+ ARM_FEATURE_COPROC (FPU_CRYPTO_ARMV8 | FPU_NEON_ARMV8 | FPU_VFP_ARMV8 \
+ | FPU_NEON_EXT_RDMA)
++#define FPU_ARCH_DOTPROD_NEON_VFP_ARMV8 \
++ ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD | FPU_NEON_ARMV8 | FPU_VFP_ARMV8)
+
+
+ #define FPU_ARCH_ENDIAN_PURE ARM_FEATURE_COPROC (FPU_ENDIAN_PURE)
+@@ -263,18 +276,26 @@
+ #define ARM_ARCH_V7M ARM_FEATURE_CORE (ARM_AEXT_V7M, ARM_EXT2_V6T2_V8M)
+ #define ARM_ARCH_V7EM ARM_FEATURE_CORE (ARM_AEXT_V7EM, ARM_EXT2_V6T2_V8M)
+ #define ARM_ARCH_V8A ARM_FEATURE_CORE (ARM_AEXT_V8A, ARM_AEXT2_V8A)
++#define ARM_ARCH_V8A_CRC ARM_FEATURE (ARM_AEXT_V8A, ARM_AEXT2_V8A, \
++ CRC_EXT_ARMV8)
+ #define ARM_ARCH_V8_1A ARM_FEATURE (ARM_AEXT_V8A, ARM_AEXT2_V8_1A, \
+ CRC_EXT_ARMV8 | FPU_NEON_EXT_RDMA)
+ #define ARM_ARCH_V8_2A ARM_FEATURE (ARM_AEXT_V8A, ARM_AEXT2_V8_2A, \
+ CRC_EXT_ARMV8 | FPU_NEON_EXT_RDMA)
++#define ARM_ARCH_V8_3A ARM_FEATURE (ARM_AEXT_V8A, ARM_AEXT2_V8_3A, \
++ CRC_EXT_ARMV8 | FPU_NEON_EXT_RDMA)
+ #define ARM_ARCH_V8M_BASE ARM_FEATURE_CORE (ARM_AEXT_V8M_BASE, ARM_AEXT2_V8M)
+ #define ARM_ARCH_V8M_MAIN ARM_FEATURE_CORE (ARM_AEXT_V8M_MAIN, \
+ ARM_AEXT2_V8M_MAIN)
++#define ARM_ARCH_V8M_MAIN_DSP ARM_FEATURE_CORE (ARM_AEXT_V8M_MAIN_DSP, \
++ ARM_AEXT2_V8M_MAIN_DSP)
++#define ARM_ARCH_V8R ARM_FEATURE_CORE (ARM_AEXT_V8R, ARM_AEXT2_V8R)
+
+ /* Some useful combinations: */
+ #define ARM_ARCH_NONE ARM_FEATURE_LOW (0, 0)
+ #define FPU_NONE ARM_FEATURE_LOW (0, 0)
+ #define ARM_ANY ARM_FEATURE (-1, -1, 0) /* Any basic core. */
++#define FPU_ANY ARM_FEATURE_COPROC (-1) /* Any FPU. */
+ #define ARM_FEATURE_ALL ARM_FEATURE (-1, -1, -1)/* All CPU and FPU features. */
+ #define FPU_ANY_HARD ARM_FEATURE_COPROC (FPU_FPA | FPU_VFP_HARD | FPU_MAVERICK)
+ /* Extensions containing some Thumb-2 instructions. If any is present, Thumb
+diff -rup binutils.orig/opcodes/arm-dis.c binutils-2.27/opcodes/arm-dis.c
+--- binutils.orig/opcodes/arm-dis.c 2017-08-09 10:26:30.352738367 +0100
++++ binutils-2.27/opcodes/arm-dis.c 2017-08-09 11:44:50.913090391 +0100
+@@ -26,6 +26,7 @@
+ #include "opcode/arm.h"
+ #include "opintl.h"
+ #include "safe-ctype.h"
++#include "libiberty.h"
+ #include "floatformat.h"
+
+ /* FIXME: This shouldn't be done here. */
+@@ -41,10 +42,6 @@
+ #define strneq(a,b,n) (strncmp ((a), (b), (n)) == 0)
+ #endif
+
+-#ifndef NUM_ELEM
+-#define NUM_ELEM(a) (sizeof (a) / sizeof (a)[0])
+-#endif
+-
+ /* Cached mapping symbol state. */
+ enum map_type
+ {
+@@ -116,6 +113,7 @@ struct opcode16
+ %<bitfield>G print as an iWMMXt general purpose or control register
+ %<bitfield>D print as a NEON D register
+ %<bitfield>Q print as a NEON Q register
++ %<bitfield>V print as a NEON D or Q register
+ %<bitfield>E print a quarter-float immediate value
+
+ %y<code> print a single precision VFP reg.
+@@ -505,6 +503,8 @@ static const struct opcode32 coprocessor
+ 0x0ee60a10, 0x0fff0fff, "vmsr%c\tmvfr1, %12-15r"},
+ {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ 0x0ee70a10, 0x0fff0fff, "vmsr%c\tmvfr0, %12-15r"},
++ {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
++ 0x0ee50a10, 0x0fff0fff, "vmsr%c\tmvfr2, %12-15r"},
+ {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ 0x0ee80a10, 0x0fff0fff, "vmsr%c\tfpexc, %12-15r"},
+ {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+@@ -517,6 +517,8 @@ static const struct opcode32 coprocessor
+ 0x0ef1fa10, 0x0fffffff, "vmrs%c\tAPSR_nzcv, fpscr"},
+ {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ 0x0ef10a10, 0x0fff0fff, "vmrs%c\t%12-15r, fpscr"},
++ {ARM_FEATURE_COPROC (FPU_VFP_EXT_ARMV8),
++ 0x0ef50a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr2"},
+ {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+ 0x0ef60a10, 0x0fff0fff, "vmrs%c\t%12-15r, mvfr1"},
+ {ARM_FEATURE_COPROC (FPU_VFP_EXT_V1xD),
+@@ -882,6 +884,34 @@ static const struct opcode32 coprocessor
+ 0xfc400000, 0xfff00000,
+ "mcrr2%c\t%8-11d, %4-7d, %12-15R, %16-19R, cr%0-3d"},
+
++ /* ARMv8.3 AdvSIMD instructions in the space of coprocessor 8. */
++ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
++ 0xfc800800, 0xfeb00f10, "vcadd%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
++ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
++ 0xfc900800, 0xfeb00f10, "vcadd%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%24?29%24'70"},
++ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
++ 0xfc200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
++ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
++ 0xfd200800, 0xff300f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
++ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
++ 0xfc300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23'90"},
++ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
++ 0xfd300800, 0xff300f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5V, #%23?21%23?780"},
++ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
++ 0xfe000800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20'90"},
++ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
++ 0xfe200800, 0xffa00f10, "vcmla%c.f16\t%12-15,22V, %16-19,7V, %0-3D[%5?10], #%20?21%20?780"},
++ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
++ 0xfe800800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20'90"},
++ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
++ 0xfea00800, 0xffa00f10, "vcmla%c.f32\t%12-15,22V, %16-19,7V, %0-3,5D[0], #%20?21%20?780"},
++
++ /* Dot Product instructions in the space of coprocessor 13. */
++ {ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
++ 0xfc200d00, 0xffb00f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3,5V"},
++ {ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD),
++ 0xfe000d00, 0xff000f00, "v%4?usdot.%4?us8\t%12-15,22V, %16-19,7V, %0-3D[%5?10]"},
++
+ /* V5 coprocessor instructions. */
+ {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
+ 0xfc100000, 0xfe100000, "ldc2%22'l%c\t%8-11d, cr%12-15d, %A"},
+@@ -971,6 +1001,10 @@ static const struct opcode32 coprocessor
+ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST),
+ 0x0e300940, 0x0fb00f50, "vsub%c.f16\t%y1, %y2, %y0"},
+
++ /* ARMv8.3 javascript conversion instruction. */
++ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A),
++ 0x0eb90bc0, 0x0fbf0fd0, "vjcvt%c.s32.f64\t%y1, %z0"},
++
+ {ARM_FEATURE_CORE_LOW (0), 0, 0, 0}
+ };
+
+@@ -2286,8 +2320,6 @@ static const struct opcode32 arm_opcodes
+ 0x01300000, 0x0ff00010, "teq%p%c\t%16-19r, %o"},
+ {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
+ 0x01300010, 0x0ff00010, "teq%p%c\t%16-19R, %o"},
+- {ARM_FEATURE_CORE_LOW (ARM_EXT_V5),
+- 0x0130f000, 0x0ff0f010, "bx%c\t%0-3r"},
+
+ {ARM_FEATURE_CORE_LOW (ARM_EXT_V1),
+ 0x03400000, 0x0fe00000, "cmp%p%c\t%16-19r, %o"},
+@@ -3171,18 +3203,20 @@ arm_regname;
+
+ static const arm_regname regnames[] =
+ {
+- { "raw" , "Select raw register names",
++ { "reg-names-raw", N_("Select raw register names"),
+ { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"}},
+- { "gcc", "Select register names used by GCC",
++ { "reg-names-gcc", N_("Select register names used by GCC"),
+ { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "sl", "fp", "ip", "sp", "lr", "pc" }},
+- { "std", "Select register names used in ARM's ISA documentation",
++ { "reg-names-std", N_("Select register names used in ARM's ISA documentation"),
+ { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc" }},
+- { "apcs", "Select register names used in the APCS",
++ { "force-thumb", N_("Assume all insns are Thumb insns"), {NULL} },
++ { "no-force-thumb", N_("Examine preceding label to determine an insn's type"), {NULL} },
++ { "reg-names-apcs", N_("Select register names used in the APCS"),
+ { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "sl", "fp", "ip", "sp", "lr", "pc" }},
+- { "atpcs", "Select register names used in the ATPCS",
++ { "reg-names-atpcs", N_("Select register names used in the ATPCS"),
+ { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }},
+- { "special-atpcs", "Select special register names used in the ATPCS",
+- { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }},
++ { "reg-names-special-atpcs", N_("Select special register names used in the ATPCS"),
++ { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }}
+ };
+
+ static const char *const iwmmxt_wwnames[] =
+@@ -3208,7 +3242,7 @@ static const char *const iwmmxt_cregname
+ /* Default to GCC register name set. */
+ static unsigned int regname_selected = 1;
+
+-#define NUM_ARM_REGNAMES NUM_ELEM (regnames)
++#define NUM_ARM_REGNAMES ARRAY_SIZE (regnames)
+ #define arm_regnames regnames[regname_selected].reg_names
+
+ static bfd_boolean force_thumb = FALSE;
+@@ -3227,31 +3261,6 @@ static bfd_vma ifthen_address;
+
+
+ /* Functions. */
+-int
+-get_arm_regname_num_options (void)
+-{
+- return NUM_ARM_REGNAMES;
+-}
+-
+-int
+-set_arm_regname_option (int option)
+-{
+- int old = regname_selected;
+- regname_selected = option;
+- return old;
+-}
+-
+-int
+-get_arm_regnames (int option,
+- const char **setname,
+- const char **setdescription,
+- const char *const **register_names)
+-{
+- *setname = regnames[option].name;
+- *setdescription = regnames[option].description;
+- *register_names = regnames[option].reg_names;
+- return 16;
+-}
+
+ /* Decode a bitfield of the form matching regexp (N(-N)?,)*N(-N)?.
+ Returns pointer to following character of the format string and
+@@ -3669,10 +3678,15 @@ print_insn_coprocessor (bfd_vma pc,
+ }
+ func (stream, "%s", arm_regnames[value]);
+ break;
++ case 'V':
++ if (given & (1 << 6))
++ goto Q;
++ /* FALLTHROUGH */
+ case 'D':
+ func (stream, "d%ld", value);
+ break;
+ case 'Q':
++ Q:
+ if (value & 1)
+ func (stream, "<illegal reg q%ld.5>", value >> 1);
+ else
+@@ -4686,6 +4700,7 @@ print_insn_arm (bfd_vma pc, struct disas
+
+ case 'S':
+ allow_unpredictable = TRUE;
++ /* Fall through. */
+ case 's':
+ if ((given & 0x004f0000) == 0x004f0000)
+ {
+@@ -5427,22 +5442,31 @@ psr_name (int regno)
+ {
+ switch (regno)
+ {
+- case 0: return "APSR";
+- case 1: return "IAPSR";
+- case 2: return "EAPSR";
+- case 3: return "PSR";
+- case 5: return "IPSR";
+- case 6: return "EPSR";
+- case 7: return "IEPSR";
+- case 8: return "MSP";
+- case 9: return "PSP";
+- case 16: return "PRIMASK";
+- case 17: return "BASEPRI";
+- case 18: return "BASEPRI_MAX";
+- case 19: return "FAULTMASK";
+- case 20: return "CONTROL";
++ case 0x0: return "APSR";
++ case 0x1: return "IAPSR";
++ case 0x2: return "EAPSR";
++ case 0x3: return "PSR";
++ case 0x5: return "IPSR";
++ case 0x6: return "EPSR";
++ case 0x7: return "IEPSR";
++ case 0x8: return "MSP";
++ case 0x9: return "PSP";
++ case 0xa: return "MSPLIM";
++ case 0xb: return "PSPLIM";
++ case 0x10: return "PRIMASK";
++ case 0x11: return "BASEPRI";
++ case 0x12: return "BASEPRI_MAX";
++ case 0x13: return "FAULTMASK";
++ case 0x14: return "CONTROL";
+ case 0x88: return "MSP_NS";
+ case 0x89: return "PSP_NS";
++ case 0x8a: return "MSPLIM_NS";
++ case 0x8b: return "PSPLIM_NS";
++ case 0x90: return "PRIMASK_NS";
++ case 0x91: return "BASEPRI_NS";
++ case 0x93: return "FAULTMASK_NS";
++ case 0x94: return "CONTROL_NS";
++ case 0x98: return "SP_NS";
+ default: return "<unknown>";
+ }
+ }
+@@ -5717,7 +5741,7 @@ print_insn_thumb32 (bfd_vma pc, struct d
+ if (off || !U)
+ {
+ func (stream, ", #%c%u", U ? '+' : '-', off * 4);
+- value_in_comment = off * 4 * U ? 1 : -1;
++ value_in_comment = off * 4 * (U ? 1 : -1);
+ }
+ func (stream, "]");
+ if (W)
+@@ -5729,7 +5753,7 @@ print_insn_thumb32 (bfd_vma pc, struct d
+ if (W)
+ {
+ func (stream, "#%c%u", U ? '+' : '-', off * 4);
+- value_in_comment = off * 4 * U ? 1 : -1;
++ value_in_comment = off * 4 * (U ? 1 : -1);
+ }
+ else
+ {
+diff -rupN binutils.orig/gas/testsuite/gas/arm/armv8_3-a-fp-bad.d binutils-2.27/gas/testsuite/gas/arm/armv8_3-a-fp-bad.d
+--- binutils.orig/gas/testsuite/gas/arm/armv8_3-a-fp-bad.d 1970-01-01 01:00:00.000000000 +0100
++++ binutils-2.27/gas/testsuite/gas/arm/armv8_3-a-fp-bad.d 2017-08-09 12:10:22.428965485 +0100
+@@ -0,0 +1,2 @@
++#as: -march=armv8.3-a+fp
++#error-output: armv8_3-a-fp-bad.l
+diff -rupN binutils.orig/gas/testsuite/gas/arm/armv8_3-a-fp-bad.l binutils-2.27/gas/testsuite/gas/arm/armv8_3-a-fp-bad.l
+--- binutils.orig/gas/testsuite/gas/arm/armv8_3-a-fp-bad.l 1970-01-01 01:00:00.000000000 +0100
++++ binutils-2.27/gas/testsuite/gas/arm/armv8_3-a-fp-bad.l 2017-08-09 12:10:22.428965485 +0100
+@@ -0,0 +1,7 @@
++[^:]+: Assembler messages:
++[^:]+:3: Error: operand types can't be inferred -- `vjcvt s0,d1'
++[^:]+:4: Error: VFP single precision register expected -- `vjcvt\.s32\.f64 r0,d1'
++[^:]+:5: Error: VFP/Neon double precision register expected -- `vjcvt\.s32\.f64 s0,s1'
++[^:]+:6: Error: VFP/Neon double precision register expected -- `vjcvt\.s32\.f32 s0,s1'
++[^:]+:7: Error: bad type in Neon instruction -- `vjcvt\.s32\.f32 s0,d1'
++[^:]+:8: Error: bad type in Neon instruction -- `vjcvt\.f32\.f64 s0,d1'
+diff -rupN binutils.orig/gas/testsuite/gas/arm/armv8_3-a-fp-bad.s binutils-2.27/gas/testsuite/gas/arm/armv8_3-a-fp-bad.s
+--- binutils.orig/gas/testsuite/gas/arm/armv8_3-a-fp-bad.s 1970-01-01 01:00:00.000000000 +0100
++++ binutils-2.27/gas/testsuite/gas/arm/armv8_3-a-fp-bad.s 2017-08-09 12:10:22.428965485 +0100
+@@ -0,0 +1,8 @@
++ .text
++ .arm
++ vjcvt s0, d1
++ vjcvt.s32.f64 r0, d1
++ vjcvt.s32.f64 s0, s1
++ vjcvt.s32.f32 s0, s1
++ vjcvt.s32.f32 s0, d1
++ vjcvt.f32.f64 s0, d1
+diff -rupN binutils.orig/gas/testsuite/gas/arm/armv8_3-a-fp.d binutils-2.27/gas/testsuite/gas/arm/armv8_3-a-fp.d
+--- binutils.orig/gas/testsuite/gas/arm/armv8_3-a-fp.d 1970-01-01 01:00:00.000000000 +0100
++++ binutils-2.27/gas/testsuite/gas/arm/armv8_3-a-fp.d 2017-08-09 12:10:22.428965485 +0100
+@@ -0,0 +1,15 @@
++#as: -march=armv8.3-a+fp
++#objdump: -dr
++#skip: *-*-pe *-wince-* *-*-coff
++
++.*: +file format .*arm.*
++
++Disassembly of section .text:
++
++[0-9a-f]+ <.*>:
++ [0-9a-f]+: eef90bc7 vjcvt.s32.f64 s1, d7
++ [0-9a-f]+: eef90bc7 vjcvt.s32.f64 s1, d7
++
++[0-9a-f]+ <.*>:
++ [0-9a-f]+: eef9 0bc7 vjcvt.s32.f64 s1, d7
++
+diff -rupN binutils.orig/gas/testsuite/gas/arm/armv8_3-a-fp.s binutils-2.27/gas/testsuite/gas/arm/armv8_3-a-fp.s
+--- binutils.orig/gas/testsuite/gas/arm/armv8_3-a-fp.s 1970-01-01 01:00:00.000000000 +0100
++++ binutils-2.27/gas/testsuite/gas/arm/armv8_3-a-fp.s 2017-08-09 12:10:22.428965485 +0100
+@@ -0,0 +1,8 @@
++ .text
++A1:
++ .arm
++ vjcvt.s32.f64 s1, d7
++ vjcvtal.s32.f64 s1, d7
++T1:
++ .thumb
++ vjcvt.s32.f64 s1, d7
+diff -rupN binutils.orig/gas/testsuite/gas/arm/armv8_3-a-simd-bad.d binutils-2.27/gas/testsuite/gas/arm/armv8_3-a-simd-bad.d
+--- binutils.orig/gas/testsuite/gas/arm/armv8_3-a-simd-bad.d 1970-01-01 01:00:00.000000000 +0100
++++ binutils-2.27/gas/testsuite/gas/arm/armv8_3-a-simd-bad.d 2017-08-09 12:10:22.428965485 +0100
+@@ -0,0 +1,2 @@
++#as: -march=armv8.3-a+fp16+simd
++#error-output: armv8_3-a-simd-bad.l
+diff -rupN binutils.orig/gas/testsuite/gas/arm/armv8_3-a-simd-bad.l binutils-2.27/gas/testsuite/gas/arm/armv8_3-a-simd-bad.l
+--- binutils.orig/gas/testsuite/gas/arm/armv8_3-a-simd-bad.l 1970-01-01 01:00:00.000000000 +0100
++++ binutils-2.27/gas/testsuite/gas/arm/armv8_3-a-simd-bad.l 2017-08-09 12:10:22.428965485 +0100
+@@ -0,0 +1,39 @@
++[^:]+: Assembler messages:
++[^:]+:6: Error: operand types can't be inferred -- `vcadd d0,d1,d2,#90'
++[^:]+:7: Error: immediate out of range -- `vcadd\.f32 q0,q1,q2,#0'
++[^:]+:8: Error: immediate out of range -- `vcadd\.f32 q0,q1,q2,#180'
++[^:]+:9: Error: Neon double or quad precision register expected -- `vcadd\.f16 s0,s1,s2,#90'
++[^:]+:10: Error: bad type in Neon instruction -- `vcadd\.f64 d0,d1,d2,#90'
++[^:]+:11: Error: bad type in Neon instruction -- `vcadd\.f64 q0,q1,q2,#90'
++[^:]+:13: Error: operand types can't be inferred -- `vcmla d0,d1,d2,#90'
++[^:]+:14: Error: immediate out of range -- `vcmla\.f32 q0,q1,q2,#-90'
++[^:]+:15: Error: immediate out of range -- `vcmla\.f32 q0,q1,q2,#120'
++[^:]+:16: Error: immediate out of range -- `vcmla\.f32 q0,q1,q2,#360'
++[^:]+:17: Error: Neon double or quad precision register expected -- `vcmla\.f16 s0,s1,s2,#90'
++[^:]+:18: Error: bad type in Neon instruction -- `vcmla\.f64 d0,d1,d2,#90'
++[^:]+:19: Error: bad type in Neon instruction -- `vcmla\.f64 q0,q1,q2,#90'
++[^:]+:21: Error: only D registers may be indexed -- `vcmla\.f16 q0,q1,q2\[0\],#90'
++[^:]+:22: Error: only D registers may be indexed -- `vcmla\.f32 q0,q1,q2\[0\],#90'
++[^:]+:23: Error: scalar out of range -- `vcmla\.f16 d0,d1,d2\[2\],#90'
++[^:]+:24: Error: scalar out of range -- `vcmla\.f16 q0,q1,d2\[2\],#90'
++[^:]+:25: Error: scalar out of range -- `vcmla\.f16 q0,q1,d16\[1\],#90'
++[^:]+:26: Error: scalar out of range -- `vcmla\.f32 q0,q1,d2\[1\],#90'
++[^:]+:31: Error: operand types can't be inferred -- `vcadd d0,d1,d2,#90'
++[^:]+:32: Error: immediate out of range -- `vcadd\.f32 q0,q1,q2,#0'
++[^:]+:33: Error: immediate out of range -- `vcadd\.f32 q0,q1,q2,#180'
++[^:]+:34: Error: Neon double or quad precision register expected -- `vcadd\.f16 s0,s1,s2,#90'
++[^:]+:35: Error: bad type in Neon instruction -- `vcadd\.f64 d0,d1,d2,#90'
++[^:]+:36: Error: bad type in Neon instruction -- `vcadd\.f64 q0,q1,q2,#90'
++[^:]+:38: Error: operand types can't be inferred -- `vcmla d0,d1,d2,#90'
++[^:]+:39: Error: immediate out of range -- `vcmla\.f32 q0,q1,q2,#-90'
++[^:]+:40: Error: immediate out of range -- `vcmla\.f32 q0,q1,q2,#120'
++[^:]+:41: Error: immediate out of range -- `vcmla\.f32 q0,q1,q2,#360'
++[^:]+:42: Error: Neon double or quad precision register expected -- `vcmla\.f16 s0,s1,s2,#90'
++[^:]+:43: Error: bad type in Neon instruction -- `vcmla\.f64 d0,d1,d2,#90'
++[^:]+:44: Error: bad type in Neon instruction -- `vcmla\.f64 q0,q1,q2,#90'
++[^:]+:46: Error: only D registers may be indexed -- `vcmla\.f16 q0,q1,q2\[0\],#90'
++[^:]+:47: Error: only D registers may be indexed -- `vcmla\.f32 q0,q1,q2\[0\],#90'
++[^:]+:48: Error: scalar out of range -- `vcmla\.f16 d0,d1,d2\[2\],#90'
++[^:]+:49: Error: scalar out of range -- `vcmla\.f16 q0,q1,d2\[2\],#90'
++[^:]+:50: Error: scalar out of range -- `vcmla\.f16 q0,q1,d16\[1\],#90'
++[^:]+:51: Error: scalar out of range -- `vcmla\.f32 q0,q1,d2\[1\],#90'
+diff -rupN binutils.orig/gas/testsuite/gas/arm/armv8_3-a-simd-bad.s binutils-2.27/gas/testsuite/gas/arm/armv8_3-a-simd-bad.s
+--- binutils.orig/gas/testsuite/gas/arm/armv8_3-a-simd-bad.s 1970-01-01 01:00:00.000000000 +0100
++++ binutils-2.27/gas/testsuite/gas/arm/armv8_3-a-simd-bad.s 2017-08-09 12:10:22.428965485 +0100
+@@ -0,0 +1,51 @@
++ .text
++
++A1:
++ .arm
++
++ vcadd d0,d1,d2,#90
++ vcadd.f32 q0,q1,q2,#0
++ vcadd.f32 q0,q1,q2,#180
++ vcadd.f16 s0,s1,s2,#90
++ vcadd.f64 d0,d1,d2,#90
++ vcadd.f64 q0,q1,q2,#90
++
++ vcmla d0,d1,d2,#90
++ vcmla.f32 q0,q1,q2,#-90
++ vcmla.f32 q0,q1,q2,#120
++ vcmla.f32 q0,q1,q2,#360
++ vcmla.f16 s0,s1,s2,#90
++ vcmla.f64 d0,d1,d2,#90
++ vcmla.f64 q0,q1,q2,#90
++
++ vcmla.f16 q0,q1,q2[0],#90
++ vcmla.f32 q0,q1,q2[0],#90
++ vcmla.f16 d0,d1,d2[2],#90
++ vcmla.f16 q0,q1,d2[2],#90
++ vcmla.f16 q0,q1,d16[1],#90
++ vcmla.f32 q0,q1,d2[1],#90
++
++T1:
++ .thumb
++
++ vcadd d0,d1,d2,#90
++ vcadd.f32 q0,q1,q2,#0
++ vcadd.f32 q0,q1,q2,#180
++ vcadd.f16 s0,s1,s2,#90
++ vcadd.f64 d0,d1,d2,#90
++ vcadd.f64 q0,q1,q2,#90
++
++ vcmla d0,d1,d2,#90
++ vcmla.f32 q0,q1,q2,#-90
++ vcmla.f32 q0,q1,q2,#120
++ vcmla.f32 q0,q1,q2,#360
++ vcmla.f16 s0,s1,s2,#90
++ vcmla.f64 d0,d1,d2,#90
++ vcmla.f64 q0,q1,q2,#90
++
++ vcmla.f16 q0,q1,q2[0],#90
++ vcmla.f32 q0,q1,q2[0],#90
++ vcmla.f16 d0,d1,d2[2],#90
++ vcmla.f16 q0,q1,d2[2],#90
++ vcmla.f16 q0,q1,d16[1],#90
++ vcmla.f32 q0,q1,d2[1],#90
+diff -rupN binutils.orig/gas/testsuite/gas/arm/armv8_3-a-simd.d binutils-2.27/gas/testsuite/gas/arm/armv8_3-a-simd.d
+--- binutils.orig/gas/testsuite/gas/arm/armv8_3-a-simd.d 1970-01-01 01:00:00.000000000 +0100
++++ binutils-2.27/gas/testsuite/gas/arm/armv8_3-a-simd.d 2017-08-09 12:10:22.428965485 +0100
+@@ -0,0 +1,59 @@
++#as: -march=armv8.3-a+fp16+simd
++#objdump: -dr
++#skip: *-*-pe *-wince-* *-*-coff
++
++.*: +file format .*arm.*
++
++Disassembly of section .text:
++
++[0-9a-f]+ <.*>:
++ +[0-9a-f]+: fc942846 vcadd.f32 q1, q2, q3, #90
++ +[0-9a-f]+: fd942846 vcadd.f32 q1, q2, q3, #270
++ +[0-9a-f]+: fcc658a7 vcadd.f16 d21, d22, d23, #90
++ +[0-9a-f]+: fc842846 vcadd.f16 q1, q2, q3, #90
++ +[0-9a-f]+: fcd658a7 vcadd.f32 d21, d22, d23, #90
++ +[0-9a-f]+: fc342846 vcmla.f32 q1, q2, q3, #0
++ +[0-9a-f]+: fcb42846 vcmla.f32 q1, q2, q3, #90
++ +[0-9a-f]+: fd342846 vcmla.f32 q1, q2, q3, #180
++ +[0-9a-f]+: fdb42846 vcmla.f32 q1, q2, q3, #270
++ +[0-9a-f]+: fce658a7 vcmla.f16 d21, d22, d23, #90
++ +[0-9a-f]+: fca42846 vcmla.f16 q1, q2, q3, #90
++ +[0-9a-f]+: fcf658a7 vcmla.f32 d21, d22, d23, #90
++ +[0-9a-f]+: fe565883 vcmla.f16 d21, d22, d3\[0\], #90
++ +[0-9a-f]+: fe5658a3 vcmla.f16 d21, d22, d3\[1\], #90
++ +[0-9a-f]+: fe142843 vcmla.f16 q1, q2, d3\[0\], #90
++ +[0-9a-f]+: fe142863 vcmla.f16 q1, q2, d3\[1\], #90
++ +[0-9a-f]+: fed658a7 vcmla.f32 d21, d22, d23\[0\], #90
++ +[0-9a-f]+: fe942867 vcmla.f32 q1, q2, d23\[0\], #90
++ +[0-9a-f]+: fe042863 vcmla.f16 q1, q2, d3\[1\], #0
++ +[0-9a-f]+: fe242863 vcmla.f16 q1, q2, d3\[1\], #180
++ +[0-9a-f]+: fe342863 vcmla.f16 q1, q2, d3\[1\], #270
++ +[0-9a-f]+: fe842843 vcmla.f32 q1, q2, d3\[0\], #0
++ +[0-9a-f]+: fea42843 vcmla.f32 q1, q2, d3\[0\], #180
++ +[0-9a-f]+: feb42843 vcmla.f32 q1, q2, d3\[0\], #270
++
++[0-9a-f]+ <.*>:
++ +[0-9a-f]+: fc94 2846 vcadd.f32 q1, q2, q3, #90
++ +[0-9a-f]+: fd94 2846 vcadd.f32 q1, q2, q3, #270
++ +[0-9a-f]+: fcc6 58a7 vcadd.f16 d21, d22, d23, #90
++ +[0-9a-f]+: fc84 2846 vcadd.f16 q1, q2, q3, #90
++ +[0-9a-f]+: fcd6 58a7 vcadd.f32 d21, d22, d23, #90
++ +[0-9a-f]+: fc34 2846 vcmla.f32 q1, q2, q3, #0
++ +[0-9a-f]+: fcb4 2846 vcmla.f32 q1, q2, q3, #90
++ +[0-9a-f]+: fd34 2846 vcmla.f32 q1, q2, q3, #180
++ +[0-9a-f]+: fdb4 2846 vcmla.f32 q1, q2, q3, #270
++ +[0-9a-f]+: fce6 58a7 vcmla.f16 d21, d22, d23, #90
++ +[0-9a-f]+: fca4 2846 vcmla.f16 q1, q2, q3, #90
++ +[0-9a-f]+: fcf6 58a7 vcmla.f32 d21, d22, d23, #90
++ +[0-9a-f]+: fe56 5883 vcmla.f16 d21, d22, d3\[0\], #90
++ +[0-9a-f]+: fe56 58a3 vcmla.f16 d21, d22, d3\[1\], #90
++ +[0-9a-f]+: fe14 2843 vcmla.f16 q1, q2, d3\[0\], #90
++ +[0-9a-f]+: fe14 2863 vcmla.f16 q1, q2, d3\[1\], #90
++ +[0-9a-f]+: fed6 58a7 vcmla.f32 d21, d22, d23\[0\], #90
++ +[0-9a-f]+: fe94 2867 vcmla.f32 q1, q2, d23\[0\], #90
++ +[0-9a-f]+: fe04 2863 vcmla.f16 q1, q2, d3\[1\], #0
++ +[0-9a-f]+: fe24 2863 vcmla.f16 q1, q2, d3\[1\], #180
++ +[0-9a-f]+: fe34 2863 vcmla.f16 q1, q2, d3\[1\], #270
++ +[0-9a-f]+: fe84 2843 vcmla.f32 q1, q2, d3\[0\], #0
++ +[0-9a-f]+: fea4 2843 vcmla.f32 q1, q2, d3\[0\], #180
++ +[0-9a-f]+: feb4 2843 vcmla.f32 q1, q2, d3\[0\], #270
+diff -rupN binutils.orig/gas/testsuite/gas/arm/armv8_3-a-simd.s binutils-2.27/gas/testsuite/gas/arm/armv8_3-a-simd.s
+--- binutils.orig/gas/testsuite/gas/arm/armv8_3-a-simd.s 1970-01-01 01:00:00.000000000 +0100
++++ binutils-2.27/gas/testsuite/gas/arm/armv8_3-a-simd.s 2017-08-09 12:10:22.428965485 +0100
+@@ -0,0 +1,63 @@
++ .text
++
++A1:
++ .arm
++
++ vcadd.f32 q1,q2,q3,#90
++ vcadd.f32 q1,q2,q3,#270
++ vcadd.f16 d21,d22,d23,#90
++ vcadd.f16 q1,q2,q3,#90
++ vcadd.f32 d21,d22,d23,#90
++
++ vcmla.f32 q1,q2,q3,#0
++ vcmla.f32 q1,q2,q3,#90
++ vcmla.f32 q1,q2,q3,#180
++ vcmla.f32 q1,q2,q3,#270
++ vcmla.f16 d21,d22,d23,#90
++ vcmla.f16 q1,q2,q3,#90
++ vcmla.f32 d21,d22,d23,#90
++
++ vcmla.f16 d21,d22,d3[0],#90
++ vcmla.f16 d21,d22,d3[1],#90
++ vcmla.f16 q1,q2,d3[0],#90
++ vcmla.f16 q1,q2,d3[1],#90
++ vcmla.f32 d21,d22,d23[0],#90
++ vcmla.f32 q1,q2,d23[0],#90
++
++ vcmla.f16 q1,q2,d3[1],#0
++ vcmla.f16 q1,q2,d3[1],#180
++ vcmla.f16 q1,q2,d3[1],#270
++ vcmla.f32 q1,q2,d3[0],#0
++ vcmla.f32 q1,q2,d3[0],#180
++ vcmla.f32 q1,q2,d3[0],#270
++
++T1:
++ .thumb
++
++ vcadd.f32 q1,q2,q3,#90
++ vcadd.f32 q1,q2,q3,#270
++ vcadd.f16 d21,d22,d23,#90
++ vcadd.f16 q1,q2,q3,#90
++ vcadd.f32 d21,d22,d23,#90
++
++ vcmla.f32 q1,q2,q3,#0
++ vcmla.f32 q1,q2,q3,#90
++ vcmla.f32 q1,q2,q3,#180
++ vcmla.f32 q1,q2,q3,#270
++ vcmla.f16 d21,d22,d23,#90
++ vcmla.f16 q1,q2,q3,#90
++ vcmla.f32 d21,d22,d23,#90
++
++ vcmla.f16 d21,d22,d3[0],#90
++ vcmla.f16 d21,d22,d3[1],#90
++ vcmla.f16 q1,q2,d3[0],#90
++ vcmla.f16 q1,q2,d3[1],#90
++ vcmla.f32 d21,d22,d23[0],#90
++ vcmla.f32 q1,q2,d23[0],#90
++
++ vcmla.f16 q1,q2,d3[1],#0
++ vcmla.f16 q1,q2,d3[1],#180
++ vcmla.f16 q1,q2,d3[1],#270
++ vcmla.f32 q1,q2,d3[0],#0
++ vcmla.f32 q1,q2,d3[0],#180
++ vcmla.f32 q1,q2,d3[0],#270
diff --git a/SOURCES/binutils-2.27-DW_AT_export_symbols.patch b/SOURCES/binutils-2.27-DW_AT_export_symbols.patch
new file mode 100644
index 0000000..5994f60
--- /dev/null
+++ b/SOURCES/binutils-2.27-DW_AT_export_symbols.patch
@@ -0,0 +1,10 @@
+--- binutils.orig/include/dwarf2.def 2017-08-08 17:40:39.295382994 +0100
++++ binutils-2.27/include/dwarf2.def 2017-08-08 17:44:03.672045965 +0100
+@@ -310,6 +310,7 @@ DW_AT (DW_AT_enum_class, 0x6d)
+ DW_AT (DW_AT_linkage_name, 0x6e)
+ /* DWARF 5. */
+ DW_AT (DW_AT_noreturn, 0x87)
++DW_AT (DW_AT_export_symbols, 0x89)
+
+ DW_AT_DUP (DW_AT_lo_user, 0x2000) /* Implementation-defined range start. */
+ DW_AT_DUP (DW_AT_hi_user, 0x3fff) /* Implementation-defined range end. */
diff --git a/SOURCES/binutils-2.27-aarch64-copy-relocs.patch b/SOURCES/binutils-2.27-aarch64-copy-relocs.patch
new file mode 100644
index 0000000..b8102b2
--- /dev/null
+++ b/SOURCES/binutils-2.27-aarch64-copy-relocs.patch
@@ -0,0 +1,367 @@
+diff --git a/bfd/elfnn-aarch64.c b/bfd/elfnn-aarch64.c
+index 1edf2a0..e27f067 100644 (file)
+--- a/bfd/elfnn-aarch64.c
++++ b/bfd/elfnn-aarch64.c
+@@ -6869,6 +6889,31 @@ elfNN_aarch64_gc_sweep_hook (bfd *abfd,
+ return TRUE;
+ }
+
++/* Return true if we need copy relocation against EH. */
++
++static bfd_boolean
++need_copy_relocation_p (struct elf_aarch64_link_hash_entry *eh)
++{
++ struct elf_dyn_relocs *p;
++ asection *s;
++
++ for (p = eh->dyn_relocs; p != NULL; p = p->next)
++ {
++ /* If there is any pc-relative reference, we need to keep copy relocation
++ to avoid propagating the relocation into runtime that current glibc
++ does not support. */
++ if (p->pc_count)
++ return TRUE;
++
++ s = p->sec->output_section;
++ /* Need copy relocation if it's against read-only section. */
++ if (s != NULL && (s->flags & SEC_READONLY) != 0)
++ return TRUE;
++ }
++
++ return FALSE;
++}
++
+ /* Adjust a symbol defined by a dynamic object and referenced by a
+ regular object. The current definition is in some section of the
+ dynamic object, but we're not including those sections. We have to
+@@ -6942,6 +6987,19 @@ elfNN_aarch64_adjust_dynamic_symbol (struct bfd_link_info *info,
+ return TRUE;
+ }
+
++ if (ELIMINATE_COPY_RELOCS)
++ {
++ struct elf_aarch64_link_hash_entry *eh;
++ /* If we didn't find any dynamic relocs in read-only sections, then
++ we'll be keeping the dynamic relocs and avoiding the copy reloc. */
++ eh = (struct elf_aarch64_link_hash_entry *) h;
++ if (!need_copy_relocation_p (eh))
++ {
++ h->non_got_ref = 0;
++ return TRUE;
++ }
++ }
++
+ /* We must allocate the symbol in our .dynbss section, which will
+ become part of the .bss section of the executable. There will be
+ an entry for this symbol in the .dynsym section. The dynamic
+diff --git a/ld/testsuite/ld-aarch64/copy-reloc-2.d b/ld/testsuite/ld-aarch64/copy-reloc-2.d
+new file mode 100644 (file)
+index 0000000..87ddccd
+--- /dev/null
++++ b/ld/testsuite/ld-aarch64/copy-reloc-2.d
+@@ -0,0 +1,7 @@
++.*
++DYNAMIC RELOCATION RECORDS
++OFFSET.*TYPE.*VALUE.*
++.*R_AARCH64_COPY.*global_[abcd]
++.*R_AARCH64_COPY.*global_[abcd]
++.*R_AARCH64_COPY.*global_[abcd]
++.*R_AARCH64_COPY.*global_[abcd]
+diff --git a/ld/testsuite/ld-aarch64/copy-reloc-eliminate.d b/ld/testsuite/ld-aarch64/copy-reloc-eliminate.d
+new file mode 100644 (file)
+index 0000000..9657d65
+--- /dev/null
++++ b/ld/testsuite/ld-aarch64/copy-reloc-eliminate.d
+@@ -0,0 +1,4 @@
++.*
++DYNAMIC RELOCATION RECORDS
++OFFSET.*TYPE.*VALUE.*
++.*R_AARCH64_ABS64.*global_a
+diff --git a/ld/testsuite/ld-aarch64/copy-reloc-exe-2.s b/ld/testsuite/ld-aarch64/copy-reloc-exe-2.s
+new file mode 100644 (file)
+index 0000000..d83658c
+--- /dev/null
++++ b/ld/testsuite/ld-aarch64/copy-reloc-exe-2.s
+@@ -0,0 +1,32 @@
++ # expect copy relocation for all these scenarios.
++ .global p
++ .global q
++ .global r
++ .section .data.rel.ro,"aw",%progbits
++ .align 3
++ .type p, %object
++ .size p, 8
++p:
++ .xword global_a
++
++ .type q, %object
++ .size q, 8
++q:
++ .xword global_b
++
++ .type r, %object
++ .size r, 8
++r:
++ # Any pc-rel relocation as no dynamic linker support on AArch64.
++ .xword global_c - .
++
++ .text
++ .global main
++main:
++ # Symbols are referenced by any other relocation against read-only
++ # section.
++ movz x0, :abs_g0_nc:global_a
++ adrp x1, global_b
++ # pc-rel.
++ adrp x2, global_d
++ add x2, x2, #:lo12:global_c
+diff --git a/ld/testsuite/ld-aarch64/copy-reloc-exe-eliminate.s b/ld/testsuite/ld-aarch64/copy-reloc-exe-eliminate.s
+new file mode 100644 (file)
+index 0000000..33227aa
+--- /dev/null
++++ b/ld/testsuite/ld-aarch64/copy-reloc-exe-eliminate.s
+@@ -0,0 +1,7 @@
++ .global p
++ .section .data.rel.ro,"aw",%progbits
++ .align 3
++ .type p, %object
++ .size p, 8
++p:
++ .xword global_a
+--- binutils.orig/ld/testsuite/ld-aarch64/copy-reloc-so.s 2017-10-10 16:56:06.347550451 +0100
++++ binutils-2.27/ld/testsuite/ld-aarch64/copy-reloc-so.s 2017-10-10 16:56:25.926321182 +0100
+@@ -1,6 +1,25 @@
+ .global global_a
+ .type global_a, %object
+ .size global_a, 4
++
++ .global global_b
++ .type global_b, %object
++ .size global_b, 4
++
++ .global global_c
++ .type global_c, %object
++ .size global_c, 4
++
++ .global global_d
++ .type global_d, %object
++ .size global_d, 4
++
+ .data
+ global_a:
+ .word 0xcafedead
++global_b:
++ .word 0xcafecafe
++global_c:
++ .word 0xdeadcafe
++global_d:
++ .word 0xdeaddead
+--- binutils.orig/ld/testsuite/ld-aarch64/aarch64-elf.exp 2017-10-10 16:56:06.347550451 +0100
++++ binutils-2.27/ld/testsuite/ld-aarch64/aarch64-elf.exp 2017-10-10 16:58:19.629989701 +0100
+@@ -292,6 +292,10 @@ set aarch64elflinktests {
+ {} "copy-reloc-so.so"}
+ {"ld-aarch64/exe with copy relocation" "-e0 tmpdir/copy-reloc-so.so" "" ""
+ {copy-reloc-exe.s} {{objdump -R copy-reloc.d}} "copy-reloc"}
++ {"ld-aarch64/exe with copy relocation 2" "-e0 tmpdir/copy-reloc-so.so" "" ""
++ {copy-reloc-exe-2.s} {{objdump -R copy-reloc-2.d}} "copy-reloc-2"}
++ {"ld-aarch64/exe with copy relocation elimination" "-e0 tmpdir/copy-reloc-so.so" "" ""
++ {copy-reloc-exe-eliminate.s} {{objdump -R copy-reloc-eliminate.d}} "copy-reloc-elimination"}
+ }
+
+ run_ld_link_tests $aarch64elflinktests
+--- binutils.orig/bfd/elfnn-aarch64.c 2017-10-10 16:56:05.783557056 +0100
++++ binutils-2.27/bfd/elfnn-aarch64.c 2017-10-10 17:15:02.559298576 +0100
+@@ -246,7 +246,7 @@
+ || (R_TYPE) == BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC \
+ || (R_TYPE) == BFD_RELOC_AARCH64_TLSDESC_OFF_G1)
+
+-#define ELIMINATE_COPY_RELOCS 0
++#define ELIMINATE_COPY_RELOCS 1
+
+ /* Return size of a relocation entry. HTAB is the bfd's
+ elf_aarch64_link_hash_entry. */
+@@ -5154,12 +5154,25 @@ elfNN_aarch64_final_link_relocate (reloc
+ /* When generating a shared object or relocatable executable, these
+ relocations are copied into the output file to be resolved at
+ run time. */
+- if (((bfd_link_pic (info) == TRUE)
+- || globals->root.is_relocatable_executable)
+- && (input_section->flags & SEC_ALLOC)
+- && (h == NULL
+- || ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
+- || h->root.type != bfd_link_hash_undefweak))
++ if ((((bfd_link_pic (info) == TRUE)
++ || globals->root.is_relocatable_executable)
++ && (input_section->flags & SEC_ALLOC)
++ && (h == NULL
++ || ELF_ST_VISIBILITY (h->other) == STV_DEFAULT
++ || h->root.type != bfd_link_hash_undefweak))
++ /* Or we are creating an executable, we may need to keep relocations
++ for symbols satisfied by a dynamic library if we manage to avoid
++ copy relocs for the symbol. */
++ || (ELIMINATE_COPY_RELOCS
++ && !bfd_link_pic (info)
++ && h != NULL
++ && (input_section->flags & SEC_ALLOC)
++ && h->dynindx != -1
++ && !h->non_got_ref
++ && ((h->def_dynamic
++ && !h->def_regular)
++ || h->root.type == bfd_link_hash_undefweak
++ || h->root.type == bfd_link_hash_undefined)))
+ {
+ Elf_Internal_Rela outrel;
+ bfd_byte *loc;
+@@ -6777,15 +6790,22 @@ elfNN_aarch64_gc_sweep_hook (bfd *abfd,
+ h->plt.refcount -= 1;
+ break;
+
++ case BFD_RELOC_AARCH64_ADD_LO12:
+ case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL:
+ case BFD_RELOC_AARCH64_ADR_HI21_PCREL:
+ case BFD_RELOC_AARCH64_ADR_LO21_PCREL:
++ case BFD_RELOC_AARCH64_LDST128_LO12:
++ case BFD_RELOC_AARCH64_LDST16_LO12:
++ case BFD_RELOC_AARCH64_LDST32_LO12:
++ case BFD_RELOC_AARCH64_LDST64_LO12:
++ case BFD_RELOC_AARCH64_LDST8_LO12:
++ case BFD_RELOC_AARCH64_LD_LO19_PCREL:
+ case BFD_RELOC_AARCH64_MOVW_G0_NC:
+ case BFD_RELOC_AARCH64_MOVW_G1_NC:
+ case BFD_RELOC_AARCH64_MOVW_G2_NC:
+ case BFD_RELOC_AARCH64_MOVW_G3:
+ case BFD_RELOC_AARCH64_NN:
+- if (h != NULL && bfd_link_executable (info))
++ if (h != NULL && bfd_link_pic (info))
+ {
+ if (h->plt.refcount > 0)
+ h->plt.refcount -= 1;
+@@ -7158,6 +7178,41 @@ elfNN_aarch64_check_relocs (bfd *abfd, s
+
+ switch (bfd_r_type)
+ {
++ case BFD_RELOC_AARCH64_MOVW_G0_NC:
++ case BFD_RELOC_AARCH64_MOVW_G1_NC:
++ case BFD_RELOC_AARCH64_MOVW_G2_NC:
++ case BFD_RELOC_AARCH64_MOVW_G3:
++ if (bfd_link_pic (info))
++ {
++ int howto_index = bfd_r_type - BFD_RELOC_AARCH64_RELOC_START;
++ _bfd_error_handler
++ /* xgettext:c-format */
++ (_("%B: relocation %s against `%s' can not be used when making "
++ "a shared object; recompile with -fPIC"),
++ abfd, elfNN_aarch64_howto_table[howto_index].name,
++ (h) ? h->root.root.string : "a local symbol");
++ bfd_set_error (bfd_error_bad_value);
++ return FALSE;
++ }
++ /* Fall through. */
++
++ case BFD_RELOC_AARCH64_16_PCREL:
++ case BFD_RELOC_AARCH64_32_PCREL:
++ case BFD_RELOC_AARCH64_64_PCREL:
++ case BFD_RELOC_AARCH64_ADD_LO12:
++ case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL:
++ case BFD_RELOC_AARCH64_ADR_HI21_PCREL:
++ case BFD_RELOC_AARCH64_ADR_LO21_PCREL:
++ case BFD_RELOC_AARCH64_LDST128_LO12:
++ case BFD_RELOC_AARCH64_LDST16_LO12:
++ case BFD_RELOC_AARCH64_LDST32_LO12:
++ case BFD_RELOC_AARCH64_LDST64_LO12:
++ case BFD_RELOC_AARCH64_LDST8_LO12:
++ case BFD_RELOC_AARCH64_LD_LO19_PCREL:
++ if (h == NULL || bfd_link_pic (info))
++ break;
++ /* Fall through. */
++
+ case BFD_RELOC_AARCH64_NN:
+
+ /* We don't need to handle relocs into sections not going into
+@@ -7176,12 +7231,32 @@ elfNN_aarch64_check_relocs (bfd *abfd, s
+
+ /* No need to do anything if we're not creating a shared
+ object. */
+- if (! bfd_link_pic (info))
+- break;
++ if (!(bfd_link_pic (info)
++ /* If on the other hand, we are creating an executable, we
++ may need to keep relocations for symbols satisfied by a
++ dynamic library if we manage to avoid copy relocs for the
++ symbol.
++
++ NOTE: Currently, there is no support of copy relocs
++ elimination on pc-relative relocation types, because there is
++ no dynamic relocation support for them in glibc. We still
++ record the dynamic symbol reference for them. This is
++ because one symbol may be referenced by both absolute
++ relocation (for example, BFD_RELOC_AARCH64_NN) and
++ pc-relative relocation. We need full symbol reference
++ information to make correct decision later in
++ elfNN_aarch64_adjust_dynamic_symbol. */
++ || (ELIMINATE_COPY_RELOCS
++ && !bfd_link_pic (info)
++ && h != NULL
++ && (h->root.type == bfd_link_hash_defweak
++ || !h->def_regular))))
++ break;
+
+ {
+ struct elf_dyn_relocs *p;
+ struct elf_dyn_relocs **head;
++ int howto_index = bfd_r_type - BFD_RELOC_AARCH64_RELOC_START;
+
+ /* We must copy these reloc types into the output file.
+ Create a reloc section in dynobj and make room for
+@@ -7245,6 +7320,8 @@ elfNN_aarch64_check_relocs (bfd *abfd, s
+
+ p->count += 1;
+
++ if (elfNN_aarch64_howto_table[howto_index].pc_relative)
++ p->pc_count += 1;
+ }
+ break;
+
+@@ -7348,42 +7425,6 @@ elfNN_aarch64_check_relocs (bfd *abfd, s
+ break;
+ }
+
+- case BFD_RELOC_AARCH64_MOVW_G0_NC:
+- case BFD_RELOC_AARCH64_MOVW_G1_NC:
+- case BFD_RELOC_AARCH64_MOVW_G2_NC:
+- case BFD_RELOC_AARCH64_MOVW_G3:
+- if (bfd_link_pic (info))
+- {
+- int howto_index = bfd_r_type - BFD_RELOC_AARCH64_RELOC_START;
+- (*_bfd_error_handler)
+- (_("%B: relocation %s against `%s' can not be used when making "
+- "a shared object; recompile with -fPIC"),
+- abfd, elfNN_aarch64_howto_table[howto_index].name,
+- (h) ? h->root.root.string : "a local symbol");
+- bfd_set_error (bfd_error_bad_value);
+- return FALSE;
+- }
+-
+- case BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL:
+- case BFD_RELOC_AARCH64_ADR_HI21_PCREL:
+- case BFD_RELOC_AARCH64_ADR_LO21_PCREL:
+- if (h != NULL && bfd_link_executable (info))
+- {
+- /* If this reloc is in a read-only section, we might
+- need a copy reloc. We can't check reliably at this
+- stage whether the section is read-only, as input
+- sections have not yet been mapped to output sections.
+- Tentatively set the flag for now, and correct in
+- adjust_dynamic_symbol. */
+- h->non_got_ref = 1;
+- h->plt.refcount += 1;
+- h->pointer_equality_needed = 1;
+- }
+- /* FIXME:: RR need to handle these in shared libraries
+- and essentially bomb out as these being non-PIC
+- relocations in shared libraries. */
+- break;
+-
+ case BFD_RELOC_AARCH64_CALL26:
+ case BFD_RELOC_AARCH64_JUMP26:
+ /* If this is a local symbol then we resolve it
diff --git a/SOURCES/binutils-2.27-aarch64-ifunc.patch b/SOURCES/binutils-2.27-aarch64-ifunc.patch
new file mode 100644
index 0000000..89e6ea3
--- /dev/null
+++ b/SOURCES/binutils-2.27-aarch64-ifunc.patch
@@ -0,0 +1,25 @@
+diff -rup binutils.orig/bfd/elfnn-aarch64.c binutils-2.27/bfd/elfnn-aarch64.c
+--- binutils.orig/bfd/elfnn-aarch64.c 2017-02-21 10:45:19.311956006 +0000
++++ binutils-2.27/bfd/elfnn-aarch64.c 2017-02-21 11:55:07.517922655 +0000
+@@ -4947,6 +4947,7 @@ elfNN_aarch64_final_link_relocate (reloc
+ it here if it is defined in a non-shared object. */
+ if (h != NULL
+ && h->type == STT_GNU_IFUNC
++ && (input_section->flags & SEC_ALLOC)
+ && h->def_regular)
+ {
+ asection *plt;
+Only in binutils.orig/ld/testsuite/ld-ifunc: .#pr18808b.c
+Only in binutils.orig/ld/testsuite/ld-ifunc: #pr18808b.c#
+diff -rup binutils.orig/ld/testsuite/ld-ifunc/pr18808b.c binutils-2.27/ld/testsuite/ld-ifunc/pr18808b.c
+--- binutils.orig/ld/testsuite/ld-ifunc/pr18808b.c 2017-02-21 10:45:27.418826491 +0000
++++ binutils-2.27/ld/testsuite/ld-ifunc/pr18808b.c 2017-02-21 10:45:41.049608726 +0000
+@@ -6,7 +6,7 @@ static int foo_impl(int x)
+ return x;
+ }
+
+-int bar()
++void bar ()
+ {
+ int (*f)(int) = foo;
+
diff --git a/SOURCES/binutils-2.27-add-globalaudit-support.patch b/SOURCES/binutils-2.27-add-globalaudit-support.patch
new file mode 100644
index 0000000..3eb29b8
--- /dev/null
+++ b/SOURCES/binutils-2.27-add-globalaudit-support.patch
@@ -0,0 +1,67 @@
+diff --git a/ld/emultempl/elf32.em b/ld/emultempl/elf32.em
+index 9ac1840316..748f56b844 100644
+--- a/ld/emultempl/elf32.em
++++ b/ld/emultempl/elf32.em
+@@ -2676,6 +2676,10 @@ fragment <<EOF
+ link_info.noexecstack = TRUE;
+ link_info.execstack = FALSE;
+ }
++ else if (strcmp (optarg, "globalaudit") == 0)
++ {
++ link_info.flags_1 |= DF_1_GLOBAUDIT;
++ }
+ EOF
+
+ if test x"$GENERATE_SHLIB_SCRIPT" = xyes; then
+diff --git a/ld/ld.texinfo b/ld/ld.texinfo
+index ebe7e7b7bd..bbfa9fd4f4 100644
+--- a/ld/ld.texinfo
++++ b/ld/ld.texinfo
+@@ -1136,6 +1136,14 @@ This option is only meaningful when building a shared object. It makes
+ the symbols defined by this shared object available for symbol resolution
+ of subsequently loaded libraries.
+
++@item globalaudit
++This option is only meaningful when building a dynamic executable.
++This option marks the executable as requiring global auditing by
++setting the @code{DF_1_GLOBAUDIT} bit in the @code{DT_FLAGS_1} dynamic
++tag. Global auditing requires that any auditing library defined via
++the @option{--depaudit} or @option{-P} command line options be run for
++all dynamic objects loaded by the application.
++
+ @item initfirst
+ This option is only meaningful when building a shared object.
+ It marks the object so that its runtime initialization will occur
+diff --git a/ld/lexsup.c b/ld/lexsup.c
+index effa277b16..1adb302a14 100644
+--- a/ld/lexsup.c
++++ b/ld/lexsup.c
+@@ -1828,6 +1828,8 @@ elf_static_list_options (FILE *file)
+ -z execstack Mark executable as requiring executable stack\n"));
+ fprintf (file, _("\
+ -z noexecstack Mark executable as not requiring executable stack\n"));
++ fprintf (file, _("\
++ -z globalaudit Mark executable requiring global auditing\n"));
+ }
+
+ static void
+diff --git a/ld/testsuite/ld-elf/audit.exp b/ld/testsuite/ld-elf/audit.exp
+index 83ee35582e..b7af4b72cf 100644
+--- a/ld/testsuite/ld-elf/audit.exp
++++ b/ld/testsuite/ld-elf/audit.exp
+@@ -60,6 +60,9 @@ set build_tests {
+ {"Run with -lusesaudit -lusesaudit2"
+ "-Ltmpdir/ -lusesaudit -lusesaudit2" ""
+ {main.c} {{"readelf" {-d} "depaudit2.rd"}} "useslibusesaudit2.out"}
++ {"Link with -z globalaudit"
++ "-Wl,-Paudit.so -Wl,-z,globalaudit" ""
++ {main.c} {{"readelf" {-d} "globalaudit.rd"}} "globalaudit.out"}
+ }
+
+ run_cc_link_tests $build_tests
+--- /dev/null 2017-08-11 08:05:42.291658471 +0100
++++ ld/testsuite/ld-elf/globalaudit.rd 2017-08-11 15:32:41.009073026 +0100
+@@ -0,0 +1,3 @@
++#...
++.*\(FLAGS_1\).*Flags: GLOBAUDIT
++#pass
diff --git a/SOURCES/binutils-2.27-cve-bugs.patch b/SOURCES/binutils-2.27-cve-bugs.patch
new file mode 100644
index 0000000..f835e1e
--- /dev/null
+++ b/SOURCES/binutils-2.27-cve-bugs.patch
@@ -0,0 +1,2317 @@
+diff -rup binutils.orig/bfd/aoutx.h binutils-2.27/bfd/aoutx.h
+--- binutils.orig/bfd/aoutx.h 2017-03-24 13:50:55.358188013 +0000
++++ binutils-2.27/bfd/aoutx.h 2017-03-24 14:26:38.438542134 +0000
+@@ -2807,9 +2807,17 @@ NAME (aout, find_nearest_line) (bfd *abf
+ *filename_ptr = main_file_name;
+ else
+ {
+- sprintf (buf, "%s%s", directory_name, main_file_name);
+- *filename_ptr = buf;
+- buf += filelen + 1;
++ if (buf == NULL)
++ /* PR binutils/20891: In a corrupt input file both
++ main_file_name and directory_name can be empty... */
++ * filename_ptr = NULL;
++ else
++ {
++ snprintf (buf, filelen + 1, "%s%s", directory_name,
++ main_file_name);
++ *filename_ptr = buf;
++ buf += filelen + 1;
++ }
+ }
+ }
+
+@@ -2818,6 +2826,13 @@ NAME (aout, find_nearest_line) (bfd *abf
+ const char *function = func->name;
+ char *colon;
+
++ if (buf == NULL)
++ {
++ /* PR binutils/20892: In a corrupt input file func can be empty. */
++ * functionname_ptr = NULL;
++ return TRUE;
++ }
++
+ /* The caller expects a symbol name. We actually have a
+ function name, without the leading underscore. Put the
+ underscore back in, so that the caller gets a symbol name. */
+diff -rup binutils.orig/bfd/compress.c binutils-2.27/bfd/compress.c
+--- binutils.orig/bfd/compress.c 2017-03-24 13:50:55.362187961 +0000
++++ binutils-2.27/bfd/compress.c 2017-03-24 14:17:49.075366778 +0000
+@@ -292,7 +292,7 @@ bfd_get_full_section_contents (bfd *abfd
+ SHF_COMPRESSED section. */
+ compression_header_size = 12;
+ if (!decompress_contents (compressed_buffer + compression_header_size,
+- sec->compressed_size, p, sz))
++ sec->compressed_size - compression_header_size, p, sz))
+ {
+ bfd_set_error (bfd_error_bad_value);
+ if (p != *ptr)
+diff -rup binutils.orig/bfd/peicode.h binutils-2.27/bfd/peicode.h
+--- binutils.orig/bfd/peicode.h 2017-03-24 13:50:55.374187806 +0000
++++ binutils-2.27/bfd/peicode.h 2017-03-24 14:22:36.326663483 +0000
+@@ -1264,7 +1264,8 @@ pe_ILF_object_p (bfd * abfd)
+ }
+
+ symbol_name = (char *) ptr;
+- source_dll = symbol_name + strlen (symbol_name) + 1;
++ /* See PR 20905 for an example of where the strnlen is necessary. */
++ source_dll = symbol_name + strnlen (symbol_name, size - 1) + 1;
+
+ /* Verify that the strings are null terminated. */
+ if (ptr[size - 1] != 0
+diff -rup binutils.orig/binutils/dwarf.c binutils-2.27/binutils/dwarf.c
+--- binutils.orig/binutils/dwarf.c 2017-03-24 13:50:55.381187716 +0000
++++ binutils-2.27/binutils/dwarf.c 2017-03-24 13:58:05.061648769 +0000
+@@ -76,7 +76,6 @@ int dwarf_check = 0;
+ as a zero-terminated list of section indexes comprising one set of debug
+ sections from a .dwo file. */
+
+-static int cu_tu_indexes_read = 0;
+ static unsigned int *shndx_pool = NULL;
+ static unsigned int shndx_pool_size = 0;
+ static unsigned int shndx_pool_used = 0;
+@@ -99,7 +98,7 @@ static int tu_count = 0;
+ static struct cu_tu_set *cu_sets = NULL;
+ static struct cu_tu_set *tu_sets = NULL;
+
+-static void load_cu_tu_indexes (void *file);
++static bfd_boolean load_cu_tu_indexes (void *);
+
+ /* Values for do_debug_lines. */
+ #define FLAG_DEBUG_LINES_RAW 1
+@@ -2713,7 +2712,7 @@ load_debug_info (void * file)
+ return num_debug_info_entries;
+
+ /* If this is a DWARF package file, load the CU and TU indexes. */
+- load_cu_tu_indexes (file);
++ (void) load_cu_tu_indexes (file);
+
+ if (load_debug_section (info, file)
+ && process_debug_info (&debug_displays [info].section, file, abbrev, 1, 0))
+@@ -7302,21 +7301,27 @@ process_cu_tu_index (struct dwarf_sectio
+ section sets that we can use to associate a .debug_info.dwo section
+ with its associated .debug_abbrev.dwo section in a .dwp file. */
+
+-static void
++static bfd_boolean
+ load_cu_tu_indexes (void *file)
+ {
++ static int cu_tu_indexes_read = -1; /* Tri-state variable. */
++
+ /* If we have already loaded (or tried to load) the CU and TU indexes
+ then do not bother to repeat the task. */
+- if (cu_tu_indexes_read)
+- return;
+-
+- if (load_debug_section (dwp_cu_index, file))
+- process_cu_tu_index (&debug_displays [dwp_cu_index].section, 0);
++ if (cu_tu_indexes_read == -1)
++ {
++ cu_tu_indexes_read = TRUE;
++
++ if (load_debug_section (dwp_cu_index, file))
++ if (! process_cu_tu_index (&debug_displays [dwp_cu_index].section, 0))
++ cu_tu_indexes_read = FALSE;
+
+- if (load_debug_section (dwp_tu_index, file))
+- process_cu_tu_index (&debug_displays [dwp_tu_index].section, 0);
++ if (load_debug_section (dwp_tu_index, file))
++ if (! process_cu_tu_index (&debug_displays [dwp_tu_index].section, 0))
++ cu_tu_indexes_read = FALSE;
++ }
+
+- cu_tu_indexes_read = 1;
++ return (bfd_boolean) cu_tu_indexes_read;
+ }
+
+ /* Find the set of sections that includes section SHNDX. */
+@@ -7326,7 +7331,8 @@ find_cu_tu_set (void *file, unsigned int
+ {
+ unsigned int i;
+
+- load_cu_tu_indexes (file);
++ if (! load_cu_tu_indexes (file))
++ return NULL;
+
+ /* Find SHNDX in the shndx pool. */
+ for (i = 0; i < shndx_pool_used; i++)
+diff -rup binutils.orig/binutils/readelf.c binutils-2.27/binutils/readelf.c
+--- binutils.orig/binutils/readelf.c 2017-03-24 13:50:55.390187599 +0000
++++ binutils-2.27/binutils/readelf.c 2017-03-24 14:16:39.008271196 +0000
+@@ -674,8 +674,14 @@ find_section_in_set (const char * name,
+ if (set != NULL)
+ {
+ while ((i = *set++) > 0)
+- if (streq (SECTION_NAME (section_headers + i), name))
+- return section_headers + i;
++ {
++ /* See PR 21156 for a reproducer. */
++ if (i >= elf_header.e_shnum)
++ continue; /* FIXME: Should we issue an error message ? */
++
++ if (streq (SECTION_NAME (section_headers + i), name))
++ return section_headers + i;
++ }
+ }
+
+ return find_section (name);
+@@ -11342,16 +11348,32 @@ process_syminfo (FILE * file ATTRIBUTE_U
+ return 1;
+ }
+
++#define IN_RANGE(START,END,ADDR,OFF) \
++ (((ADDR) >= (START)) && ((ADDR) + (OFF) < (END)))
++
+ /* Check to see if the given reloc needs to be handled in a target specific
+ manner. If so then process the reloc and return TRUE otherwise return
+- FALSE. */
++ FALSE.
++
++ If called with reloc == NULL, then this is a signal that reloc processing
++ for the current section has finished, and any saved state should be
++ discarded. */
+
+ static bfd_boolean
+ target_specific_reloc_handling (Elf_Internal_Rela * reloc,
+ unsigned char * start,
+- Elf_Internal_Sym * symtab)
++ unsigned char * end,
++ Elf_Internal_Sym * symtab,
++ unsigned long num_syms)
+ {
+- unsigned int reloc_type = get_reloc_type (reloc->r_info);
++ unsigned int reloc_type = 0;
++ unsigned long sym_index = 0;
++
++ if (reloc)
++ {
++ reloc_type = get_reloc_type (reloc->r_info);
++ sym_index = get_reloc_symindex (reloc->r_info);
++ }
+
+ switch (elf_header.e_machine)
+ {
+@@ -11360,13 +11382,25 @@ target_specific_reloc_handling (Elf_Inte
+ {
+ static Elf_Internal_Sym * saved_sym = NULL;
+
++ if (reloc == NULL)
++ {
++ saved_sym = NULL;
++ return TRUE;
++ }
++
+ switch (reloc_type)
+ {
+ case 10: /* R_MSP430_SYM_DIFF */
+ if (uses_msp430x_relocs ())
+ break;
++ /* Fall through. */
+ case 21: /* R_MSP430X_SYM_DIFF */
+- saved_sym = symtab + get_reloc_symindex (reloc->r_info);
++ /* PR 21139. */
++ if (sym_index >= num_syms)
++ error (_("MSP430 SYM_DIFF reloc contains invalid symbol index %lu\n"),
++ sym_index);
++ else
++ saved_sym = symtab + sym_index;
+ return TRUE;
+
+ case 1: /* R_MSP430_32 or R_MSP430_ABS32 */
+@@ -11388,13 +11422,24 @@ target_specific_reloc_handling (Elf_Inte
+ handle_sym_diff:
+ if (saved_sym != NULL)
+ {
++ int reloc_size = reloc_type == 1 ? 4 : 2;
+ bfd_vma value;
+
+- value = reloc->r_addend
+- + (symtab[get_reloc_symindex (reloc->r_info)].st_value
+- - saved_sym->st_value);
++ if (sym_index >= num_syms)
++ error (_("MSP430 reloc contains invalid symbol index %lu\n"),
++ sym_index);
++ else
++ {
++ value = reloc->r_addend + (symtab[sym_index].st_value
++ - saved_sym->st_value);
+
+- byte_put (start + reloc->r_offset, value, reloc_type == 1 ? 4 : 2);
++ if (IN_RANGE (start, end, start + reloc->r_offset, reloc_size))
++ byte_put (start + reloc->r_offset, value, reloc_size);
++ else
++ /* PR 21137 */
++ error (_("MSP430 sym diff reloc contains invalid offset: 0x%lx\n"),
++ (long) reloc->r_offset);
++ }
+
+ saved_sym = NULL;
+ return TRUE;
+@@ -11414,24 +11459,46 @@ target_specific_reloc_handling (Elf_Inte
+ {
+ static Elf_Internal_Sym * saved_sym = NULL;
+
++ if (reloc == NULL)
++ {
++ saved_sym = NULL;
++ return TRUE;
++ }
++
+ switch (reloc_type)
+ {
+ case 34: /* R_MN10300_ALIGN */
+ return TRUE;
++
+ case 33: /* R_MN10300_SYM_DIFF */
+- saved_sym = symtab + get_reloc_symindex (reloc->r_info);
++ if (sym_index >= num_syms)
++ error (_("MN10300_SYM_DIFF reloc contains invalid symbol index %lu\n"),
++ sym_index);
++ else
++ saved_sym = symtab + sym_index;
+ return TRUE;
++
+ case 1: /* R_MN10300_32 */
+ case 2: /* R_MN10300_16 */
+ if (saved_sym != NULL)
+ {
++ int reloc_size = reloc_type == 1 ? 4 : 2;
+ bfd_vma value;
+
+- value = reloc->r_addend
+- + (symtab[get_reloc_symindex (reloc->r_info)].st_value
+- - saved_sym->st_value);
++ if (sym_index >= num_syms)
++ error (_("MN10300 reloc contains invalid symbol index %lu\n"),
++ sym_index);
++ else
++ {
++ value = reloc->r_addend + (symtab[sym_index].st_value
++ - saved_sym->st_value);
+
+- byte_put (start + reloc->r_offset, value, reloc_type == 1 ? 4 : 2);
++ if (IN_RANGE (start, end, start + reloc->r_offset, reloc_size))
++ byte_put (start + reloc->r_offset, value, reloc_size);
++ else
++ error (_("MN10300 sym diff reloc contains invalid offset: 0x%lx\n"),
++ (long) reloc->r_offset);
++ }
+
+ saved_sym = NULL;
+ return TRUE;
+@@ -11451,12 +11518,24 @@ target_specific_reloc_handling (Elf_Inte
+ static bfd_vma saved_sym2 = 0;
+ static bfd_vma value;
+
++ if (reloc == NULL)
++ {
++ saved_sym1 = saved_sym2 = 0;
++ return TRUE;
++ }
++
+ switch (reloc_type)
+ {
+ case 0x80: /* R_RL78_SYM. */
+ saved_sym1 = saved_sym2;
+- saved_sym2 = symtab[get_reloc_symindex (reloc->r_info)].st_value;
+- saved_sym2 += reloc->r_addend;
++ if (sym_index >= num_syms)
++ error (_("RL78_SYM reloc contains invalid symbol index %lu\n"),
++ sym_index);
++ else
++ {
++ saved_sym2 = symtab[sym_index].st_value;
++ saved_sym2 += reloc->r_addend;
++ }
+ return TRUE;
+
+ case 0x83: /* R_RL78_OPsub. */
+@@ -11466,12 +11545,20 @@ target_specific_reloc_handling (Elf_Inte
+ break;
+
+ case 0x41: /* R_RL78_ABS32. */
+- byte_put (start + reloc->r_offset, value, 4);
++ if (IN_RANGE (start, end, start + reloc->r_offset, 4))
++ byte_put (start + reloc->r_offset, value, 4);
++ else
++ error (_("RL78 sym diff reloc contains invalid offset: 0x%lx\n"),
++ (long) reloc->r_offset);
+ value = 0;
+ return TRUE;
+
+ case 0x43: /* R_RL78_ABS16. */
+- byte_put (start + reloc->r_offset, value, 2);
++ if (IN_RANGE (start, end, start + reloc->r_offset, 2))
++ byte_put (start + reloc->r_offset, value, 2);
++ else
++ error (_("RL78 sym diff reloc contains invalid offset: 0x%lx\n"),
++ (long) reloc->r_offset);
+ value = 0;
+ return TRUE;
+
+@@ -12078,7 +12165,7 @@ apply_relocations (void *
+
+ reloc_type = get_reloc_type (rp->r_info);
+
+- if (target_specific_reloc_handling (rp, start, symtab))
++ if (target_specific_reloc_handling (rp, start, end, symtab, num_syms))
+ continue;
+ else if (is_none_reloc (reloc_type))
+ continue;
+@@ -12174,6 +12261,9 @@ apply_relocations (void *
+ }
+
+ free (symtab);
++ /* Let the target specific reloc processing code know that
++ we have finished with these relocs. */
++ target_specific_reloc_handling (NULL, NULL, NULL, NULL, 0);
+
+ if (relocs_return)
+ {
+@@ -12471,10 +12561,18 @@ dump_section_as_bytes (Elf_Internal_Shdr
+ new_size -= 12;
+ }
+
+- if (uncompressed_size
+- && uncompress_section_contents (& start, uncompressed_size,
+- & new_size))
+- section_size = new_size;
++ if (uncompressed_size)
++ {
++ if (uncompress_section_contents (& start, uncompressed_size,
++ & new_size))
++ section_size = new_size;
++ else
++ {
++ error (_("Unable to decompress section %s\n"),
++ printable_section_name (section));
++ return;
++ }
++ }
+ }
+
+ if (relocate)
+diff -rup binutils.orig/binutils/stabs.c binutils-2.27/binutils/stabs.c
+--- binutils.orig/binutils/stabs.c 2017-03-24 13:50:55.386187651 +0000
++++ binutils-2.27/binutils/stabs.c 2017-03-24 14:14:20.823055085 +0000
+@@ -232,6 +232,10 @@ parse_number (const char **pp, bfd_boole
+
+ orig = *pp;
+
++ /* Stop early if we are passed an empty string. */
++ if (*orig == 0)
++ return (bfd_vma) 0;
++
+ errno = 0;
+ ul = strtoul (*pp, (char **) pp, 0);
+ if (ul + 1 != 0 || errno == 0)
+@@ -1975,9 +1979,17 @@ parse_stab_enum_type (void *dhandle, con
+ bfd_signed_vma val;
+
+ p = *pp;
+- while (*p != ':')
++ while (*p != ':' && *p != 0)
+ ++p;
+
++ if (*p == 0)
++ {
++ bad_stab (orig);
++ free (names);
++ free (values);
++ return DEBUG_TYPE_NULL;
++ }
++
+ name = savestring (*pp, p - *pp);
+
+ *pp = p + 1;
+diff -rup binutils.orig/gas/app.c binutils-2.27/gas/app.c
+--- binutils.orig/gas/app.c 2017-03-24 13:50:55.395187534 +0000
++++ binutils-2.27/gas/app.c 2017-03-24 13:52:02.141327121 +0000
+@@ -1187,7 +1187,7 @@ do_scrub_chars (size_t (*get) (char *, s
+ state = -2;
+ break;
+ }
+- else
++ else if (ch2 != EOF)
+ {
+ UNGET (ch2);
+ }
+diff -rup binutils.orig/ld/ldlex.c binutils-2.27/ld/ldlex.c
+--- binutils.orig/ld/ldlex.c 2017-03-24 13:50:55.613184724 +0000
++++ binutils-2.27/ld/ldlex.c 2017-03-24 14:20:47.319068827 +0000
+@@ -1,5 +1,5 @@
+
+-#line 3 "ldlex.c"
++#line 3 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.c"
+
+ #define YY_INT_ALIGNED short int
+
+@@ -7,8 +7,8 @@
+
+ #define FLEX_SCANNER
+ #define YY_FLEX_MAJOR_VERSION 2
+-#define YY_FLEX_MINOR_VERSION 5
+-#define YY_FLEX_SUBMINOR_VERSION 35
++#define YY_FLEX_MINOR_VERSION 6
++#define YY_FLEX_SUBMINOR_VERSION 0
+ #if YY_FLEX_SUBMINOR_VERSION > 0
+ #define FLEX_BETA
+ #endif
+@@ -46,7 +46,6 @@ typedef int16_t flex_int16_t;
+ typedef uint16_t flex_uint16_t;
+ typedef int32_t flex_int32_t;
+ typedef uint32_t flex_uint32_t;
+-typedef uint64_t flex_uint64_t;
+ #else
+ typedef signed char flex_int8_t;
+ typedef short int flex_int16_t;
+@@ -54,7 +53,6 @@ typedef int flex_int32_t;
+ typedef unsigned char flex_uint8_t;
+ typedef unsigned short int flex_uint16_t;
+ typedef unsigned int flex_uint32_t;
+-#endif /* ! C99 */
+
+ /* Limits of integral types. */
+ #ifndef INT8_MIN
+@@ -85,6 +83,8 @@ typedef unsigned int flex_uint32_t;
+ #define UINT32_MAX (4294967295U)
+ #endif
+
++#endif /* ! C99 */
++
+ #endif /* ! FLEXINT_H */
+
+ #ifdef __cplusplus
+@@ -141,7 +141,15 @@ typedef unsigned int flex_uint32_t;
+
+ /* Size of default input buffer. */
+ #ifndef YY_BUF_SIZE
++#ifdef __ia64__
++/* On IA-64, the buffer size is 16k, not 8k.
++ * Moreover, YY_BUF_SIZE is 2*YY_READ_BUF_SIZE in the general case.
++ * Ditto for the __ia64__ case accordingly.
++ */
++#define YY_BUF_SIZE 32768
++#else
+ #define YY_BUF_SIZE 16384
++#endif /* __ia64__ */
+ #endif
+
+ /* The state buf must be large enough to hold one state per character in the main buffer.
+@@ -167,13 +175,14 @@ extern FILE *yyin, *yyout;
+ #define EOB_ACT_LAST_MATCH 2
+
+ #define YY_LESS_LINENO(n)
++ #define YY_LINENO_REWIND_TO(ptr)
+
+ /* Return all but the first "n" matched characters back to the input stream. */
+ #define yyless(n) \
+ do \
+ { \
+ /* Undo effects of setting up yytext. */ \
+- int yyless_macro_arg = (n); \
++ yy_size_t yyless_macro_arg = (n); \
+ YY_LESS_LINENO(yyless_macro_arg);\
+ *yy_cp = (yy_hold_char); \
+ YY_RESTORE_YY_MORE_OFFSET \
+@@ -343,11 +352,17 @@ extern int yylineno;
+ int yylineno = 1;
+
+ extern char *yytext;
++#ifdef yytext_ptr
++#undef yytext_ptr
++#endif
+ #define yytext_ptr yytext
+
+ static yy_state_type yy_get_previous_state (void );
+ static yy_state_type yy_try_NUL_trans (yy_state_type current_state );
+ static int yy_get_next_buffer (void );
++#if defined(__GNUC__) && __GNUC__ >= 3
++__attribute__((__noreturn__))
++#endif
+ static void yy_fatal_error (yyconst char msg[] );
+
+ /* Done after the current pattern has been matched and before the
+@@ -355,7 +370,7 @@ static void yy_fatal_error (yyconst char
+ */
+ #define YY_DO_BEFORE_ACTION \
+ (yytext_ptr) = yy_bp; \
+- yyleng = (yy_size_t) (yy_cp - yy_bp); \
++ yyleng = (size_t) (yy_cp - yy_bp); \
+ (yy_hold_char) = *yy_cp; \
+ *yy_cp = '\0'; \
+ (yy_c_buf_p) = yy_cp;
+@@ -568,7 +583,7 @@ static yyconst flex_int16_t yy_accept[17
+ 174, 84, 84, 0
+ } ;
+
+-static yyconst flex_int32_t yy_ec[256] =
++static yyconst YY_CHAR yy_ec[256] =
+ { 0,
+ 1, 1, 1, 1, 1, 1, 1, 1, 2, 3,
+ 1, 1, 2, 1, 1, 1, 1, 1, 1, 1,
+@@ -600,7 +615,7 @@ static yyconst flex_int32_t yy_ec[256] =
+ 1, 1, 1, 1, 1
+ } ;
+
+-static yyconst flex_int32_t yy_meta[83] =
++static yyconst YY_CHAR yy_meta[83] =
+ { 0,
+ 1, 1, 2, 3, 1, 1, 4, 1, 1, 1,
+ 1, 3, 5, 6, 7, 8, 9, 10, 10, 10,
+@@ -613,7 +628,7 @@ static yyconst flex_int32_t yy_meta[83]
+ 1, 9
+ } ;
+
+-static yyconst flex_int16_t yy_base[1807] =
++static yyconst flex_uint16_t yy_base[1807] =
+ { 0,
+ 0, 0, 0, 0, 82, 163, 244, 0, 326, 0,
+ 408, 489, 570, 0, 112, 114, 652, 734, 816, 898,
+@@ -1019,7 +1034,7 @@ static yyconst flex_int16_t yy_def[1807]
+ 1774, 1774, 1774, 1774, 1774, 1774
+ } ;
+
+-static yyconst flex_int16_t yy_nxt[2940] =
++static yyconst flex_uint16_t yy_nxt[2940] =
+ { 0,
+ 23, 24, 25, 26, 27, 23, 28, 29, 30, 31,
+ 32, 33, 34, 35, 36, 37, 38, 39, 40, 40,
+@@ -1687,8 +1702,8 @@ int yy_flex_debug = 0;
+ #define YY_MORE_ADJ 0
+ #define YY_RESTORE_YY_MORE_OFFSET
+ char *yytext;
+-#line 1 "ldlex.l"
+-#line 4 "ldlex.l"
++#line 1 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
++#line 4 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+
+ /* Copyright (C) 1991-2016 Free Software Foundation, Inc.
+ Written by Steve Chamberlain of Cygnus Support.
+@@ -1788,7 +1803,7 @@ int yywrap (void) { return 1; }
+
+
+
+-#line 1792 "ldlex.c"
++#line 1807 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.c"
+
+ #define INITIAL 0
+ #define SCRIPT 1
+@@ -1830,11 +1845,11 @@ void yyset_extra (YY_EXTRA_TYPE user_def
+
+ FILE *yyget_in (void );
+
+-void yyset_in (FILE * in_str );
++void yyset_in (FILE * _in_str );
+
+ FILE *yyget_out (void );
+
+-void yyset_out (FILE * out_str );
++void yyset_out (FILE * _out_str );
+
+ yy_size_t yyget_leng (void );
+
+@@ -1842,7 +1857,7 @@ char *yyget_text (void );
+
+ int yyget_lineno (void );
+
+-void yyset_lineno (int line_number );
++void yyset_lineno (int _line_number );
+
+ /* Macros after this point can all be overridden by user definitions in
+ * section 1.
+@@ -1856,6 +1871,10 @@ extern int yywrap (void );
+ #endif
+ #endif
+
++#ifndef YY_NO_UNPUT
++
++#endif
++
+ #ifndef yytext_ptr
+ static void yy_flex_strncpy (char *,yyconst char *,int );
+ #endif
+@@ -1876,7 +1895,12 @@ static int input (void );
+
+ /* Amount of stuff to slurp up with each read. */
+ #ifndef YY_READ_BUF_SIZE
++#ifdef __ia64__
++/* On IA-64, the buffer size is 16k, not 8k */
++#define YY_READ_BUF_SIZE 16384
++#else
+ #define YY_READ_BUF_SIZE 8192
++#endif /* __ia64__ */
+ #endif
+
+ /* Copy whatever the last rule matched to the standard output. */
+@@ -1884,7 +1908,7 @@ static int input (void );
+ /* This used to be an fputs(), but since the string might contain NUL's,
+ * we now use fwrite().
+ */
+-#define ECHO fwrite( yytext, yyleng, 1, yyout )
++#define ECHO do { if (fwrite( yytext, yyleng, 1, yyout )) {} } while (0)
+ #endif
+
+ /* Gets input and stuffs it into "buf". number of characters read, or YY_NULL,
+@@ -1895,7 +1919,7 @@ static int input (void );
+ if ( YY_CURRENT_BUFFER_LVALUE->yy_is_interactive ) \
+ { \
+ int c = '*'; \
+- yy_size_t n; \
++ size_t n; \
+ for ( n = 0; n < max_size && \
+ (c = getc( yyin )) != EOF && c != '\n'; ++n ) \
+ buf[n] = (char) c; \
+@@ -1963,7 +1987,7 @@ extern int yylex (void);
+
+ /* Code executed at the end of each rule. */
+ #ifndef YY_BREAK
+-#define YY_BREAK break;
++#define YY_BREAK /*LINTED*/break;
+ #endif
+
+ #define YY_RULE_SETUP \
+@@ -1973,31 +1997,10 @@ extern int yylex (void);
+ */
+ YY_DECL
+ {
+- register yy_state_type yy_current_state;
+- register char *yy_cp, *yy_bp;
+- register int yy_act;
++ yy_state_type yy_current_state;
++ char *yy_cp, *yy_bp;
++ int yy_act;
+
+-#line 121 "ldlex.l"
+-
+-
+- if (parser_input != input_selected)
+- {
+- /* The first token of the input determines the initial parser state. */
+- input_type t = parser_input;
+- parser_input = input_selected;
+- switch (t)
+- {
+- case input_script: return INPUT_SCRIPT; break;
+- case input_mri_script: return INPUT_MRI_SCRIPT; break;
+- case input_version_script: return INPUT_VERSION_SCRIPT; break;
+- case input_dynamic_list: return INPUT_DYNAMIC_LIST; break;
+- case input_defsym: return INPUT_DEFSYM; break;
+- default: abort ();
+- }
+- }
+-
+-#line 2000 "ldlex.c"
+-
+ if ( !(yy_init) )
+ {
+ (yy_init) = 1;
+@@ -2024,7 +2027,29 @@ YY_DECL
+ yy_load_buffer_state( );
+ }
+
+- while ( 1 ) /* loops until end-of-file is reached */
++ {
++#line 121 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
++
++
++ if (parser_input != input_selected)
++ {
++ /* The first token of the input determines the initial parser state. */
++ input_type t = parser_input;
++ parser_input = input_selected;
++ switch (t)
++ {
++ case input_script: return INPUT_SCRIPT; break;
++ case input_mri_script: return INPUT_MRI_SCRIPT; break;
++ case input_version_script: return INPUT_VERSION_SCRIPT; break;
++ case input_dynamic_list: return INPUT_DYNAMIC_LIST; break;
++ case input_defsym: return INPUT_DEFSYM; break;
++ default: abort ();
++ }
++ }
++
++#line 2051 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.c"
++
++ while ( /*CONSTCOND*/1 ) /* loops until end-of-file is reached */
+ {
+ yy_cp = (yy_c_buf_p);
+
+@@ -2040,7 +2065,7 @@ YY_DECL
+ yy_match:
+ do
+ {
+- register YY_CHAR yy_c = yy_ec[YY_SC_TO_UI(*yy_cp)];
++ YY_CHAR yy_c = yy_ec[YY_SC_TO_UI(*yy_cp)] ;
+ if ( yy_accept[yy_current_state] )
+ {
+ (yy_last_accepting_state) = yy_current_state;
+@@ -2081,32 +2106,32 @@ do_action: /* This label is used only to
+
+ case 1:
+ YY_RULE_SETUP
+-#line 139 "ldlex.l"
++#line 139 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { comment (); }
+ YY_BREAK
+ case 2:
+ YY_RULE_SETUP
+-#line 142 "ldlex.l"
++#line 142 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN('-');}
+ YY_BREAK
+ case 3:
+ YY_RULE_SETUP
+-#line 143 "ldlex.l"
++#line 143 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN('+');}
+ YY_BREAK
+ case 4:
+ YY_RULE_SETUP
+-#line 144 "ldlex.l"
++#line 144 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { yylval.name = xstrdup (yytext); return NAME; }
+ YY_BREAK
+ case 5:
+ YY_RULE_SETUP
+-#line 145 "ldlex.l"
++#line 145 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN('='); }
+ YY_BREAK
+ case 6:
+ YY_RULE_SETUP
+-#line 147 "ldlex.l"
++#line 147 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ {
+ yylval.integer = bfd_scan_vma (yytext + 1, 0, 16);
+ yylval.bigint.str = NULL;
+@@ -2115,7 +2140,7 @@ YY_RULE_SETUP
+ YY_BREAK
+ case 7:
+ YY_RULE_SETUP
+-#line 153 "ldlex.l"
++#line 153 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ {
+ int ibase ;
+ switch (yytext[yyleng - 1]) {
+@@ -2144,7 +2169,7 @@ YY_RULE_SETUP
+ YY_BREAK
+ case 8:
+ YY_RULE_SETUP
+-#line 178 "ldlex.l"
++#line 178 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ {
+ char *s = yytext;
+ int ibase = 0;
+@@ -2177,829 +2202,829 @@ YY_RULE_SETUP
+ YY_BREAK
+ case 9:
+ YY_RULE_SETUP
+-#line 207 "ldlex.l"
++#line 207 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(']');}
+ YY_BREAK
+ case 10:
+ YY_RULE_SETUP
+-#line 208 "ldlex.l"
++#line 208 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN('[');}
+ YY_BREAK
+ case 11:
+ YY_RULE_SETUP
+-#line 209 "ldlex.l"
++#line 209 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(LSHIFTEQ);}
+ YY_BREAK
+ case 12:
+ YY_RULE_SETUP
+-#line 210 "ldlex.l"
++#line 210 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(RSHIFTEQ);}
+ YY_BREAK
+ case 13:
+ YY_RULE_SETUP
+-#line 211 "ldlex.l"
++#line 211 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(OROR);}
+ YY_BREAK
+ case 14:
+ YY_RULE_SETUP
+-#line 212 "ldlex.l"
++#line 212 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(EQ);}
+ YY_BREAK
+ case 15:
+ YY_RULE_SETUP
+-#line 213 "ldlex.l"
++#line 213 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(NE);}
+ YY_BREAK
+ case 16:
+ YY_RULE_SETUP
+-#line 214 "ldlex.l"
++#line 214 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(GE);}
+ YY_BREAK
+ case 17:
+ YY_RULE_SETUP
+-#line 215 "ldlex.l"
++#line 215 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(LE);}
+ YY_BREAK
+ case 18:
+ YY_RULE_SETUP
+-#line 216 "ldlex.l"
++#line 216 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(LSHIFT);}
+ YY_BREAK
+ case 19:
+ YY_RULE_SETUP
+-#line 217 "ldlex.l"
++#line 217 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(RSHIFT);}
+ YY_BREAK
+ case 20:
+ YY_RULE_SETUP
+-#line 218 "ldlex.l"
++#line 218 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(PLUSEQ);}
+ YY_BREAK
+ case 21:
+ YY_RULE_SETUP
+-#line 219 "ldlex.l"
++#line 219 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(MINUSEQ);}
+ YY_BREAK
+ case 22:
+ YY_RULE_SETUP
+-#line 220 "ldlex.l"
++#line 220 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(MULTEQ);}
+ YY_BREAK
+ case 23:
+ YY_RULE_SETUP
+-#line 221 "ldlex.l"
++#line 221 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(DIVEQ);}
+ YY_BREAK
+ case 24:
+ YY_RULE_SETUP
+-#line 222 "ldlex.l"
++#line 222 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(ANDEQ);}
+ YY_BREAK
+ case 25:
+ YY_RULE_SETUP
+-#line 223 "ldlex.l"
++#line 223 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(OREQ);}
+ YY_BREAK
+ case 26:
+ YY_RULE_SETUP
+-#line 224 "ldlex.l"
++#line 224 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(ANDAND);}
+ YY_BREAK
+ case 27:
+ YY_RULE_SETUP
+-#line 225 "ldlex.l"
++#line 225 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN('>');}
+ YY_BREAK
+ case 28:
+ YY_RULE_SETUP
+-#line 226 "ldlex.l"
++#line 226 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(',');}
+ YY_BREAK
+ case 29:
+ YY_RULE_SETUP
+-#line 227 "ldlex.l"
++#line 227 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN('&');}
+ YY_BREAK
+ case 30:
+ YY_RULE_SETUP
+-#line 228 "ldlex.l"
++#line 228 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN('|');}
+ YY_BREAK
+ case 31:
+ YY_RULE_SETUP
+-#line 229 "ldlex.l"
++#line 229 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN('~');}
+ YY_BREAK
+ case 32:
+ YY_RULE_SETUP
+-#line 230 "ldlex.l"
++#line 230 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN('!');}
+ YY_BREAK
+ case 33:
+ YY_RULE_SETUP
+-#line 231 "ldlex.l"
++#line 231 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN('?');}
+ YY_BREAK
+ case 34:
+ YY_RULE_SETUP
+-#line 232 "ldlex.l"
++#line 232 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN('*');}
+ YY_BREAK
+ case 35:
+ YY_RULE_SETUP
+-#line 233 "ldlex.l"
++#line 233 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN('+');}
+ YY_BREAK
+ case 36:
+ YY_RULE_SETUP
+-#line 234 "ldlex.l"
++#line 234 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN('-');}
+ YY_BREAK
+ case 37:
+ YY_RULE_SETUP
+-#line 235 "ldlex.l"
++#line 235 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN('/');}
+ YY_BREAK
+ case 38:
+ YY_RULE_SETUP
+-#line 236 "ldlex.l"
++#line 236 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN('%');}
+ YY_BREAK
+ case 39:
+ YY_RULE_SETUP
+-#line 237 "ldlex.l"
++#line 237 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN('<');}
+ YY_BREAK
+ case 40:
+ YY_RULE_SETUP
+-#line 238 "ldlex.l"
++#line 238 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN('=');}
+ YY_BREAK
+ case 41:
+ YY_RULE_SETUP
+-#line 239 "ldlex.l"
++#line 239 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN('}') ; }
+ YY_BREAK
+ case 42:
+ YY_RULE_SETUP
+-#line 240 "ldlex.l"
++#line 240 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN('{'); }
+ YY_BREAK
+ case 43:
+ YY_RULE_SETUP
+-#line 241 "ldlex.l"
++#line 241 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(')');}
+ YY_BREAK
+ case 44:
+ YY_RULE_SETUP
+-#line 242 "ldlex.l"
++#line 242 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN('(');}
+ YY_BREAK
+ case 45:
+ YY_RULE_SETUP
+-#line 243 "ldlex.l"
++#line 243 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(':'); }
+ YY_BREAK
+ case 46:
+ YY_RULE_SETUP
+-#line 244 "ldlex.l"
++#line 244 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(';');}
+ YY_BREAK
+ case 47:
+ YY_RULE_SETUP
+-#line 245 "ldlex.l"
++#line 245 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(MEMORY);}
+ YY_BREAK
+ case 48:
+ YY_RULE_SETUP
+-#line 246 "ldlex.l"
++#line 246 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(REGION_ALIAS);}
+ YY_BREAK
+ case 49:
+ YY_RULE_SETUP
+-#line 247 "ldlex.l"
++#line 247 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(LD_FEATURE);}
+ YY_BREAK
+ case 50:
+ YY_RULE_SETUP
+-#line 248 "ldlex.l"
++#line 248 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(ORIGIN);}
+ YY_BREAK
+ case 51:
+ YY_RULE_SETUP
+-#line 249 "ldlex.l"
++#line 249 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(VERSIONK);}
+ YY_BREAK
+ case 52:
+ YY_RULE_SETUP
+-#line 250 "ldlex.l"
++#line 250 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(BLOCK);}
+ YY_BREAK
+ case 53:
+ YY_RULE_SETUP
+-#line 251 "ldlex.l"
++#line 251 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(BIND);}
+ YY_BREAK
+ case 54:
+ YY_RULE_SETUP
+-#line 252 "ldlex.l"
++#line 252 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(LENGTH);}
+ YY_BREAK
+ case 55:
+ YY_RULE_SETUP
+-#line 253 "ldlex.l"
++#line 253 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(ALIGN_K);}
+ YY_BREAK
+ case 56:
+ YY_RULE_SETUP
+-#line 254 "ldlex.l"
++#line 254 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(DATA_SEGMENT_ALIGN);}
+ YY_BREAK
+ case 57:
+ YY_RULE_SETUP
+-#line 255 "ldlex.l"
++#line 255 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(DATA_SEGMENT_RELRO_END);}
+ YY_BREAK
+ case 58:
+ YY_RULE_SETUP
+-#line 256 "ldlex.l"
++#line 256 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(DATA_SEGMENT_END);}
+ YY_BREAK
+ case 59:
+ YY_RULE_SETUP
+-#line 257 "ldlex.l"
++#line 257 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(ADDR);}
+ YY_BREAK
+ case 60:
+ YY_RULE_SETUP
+-#line 258 "ldlex.l"
++#line 258 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(LOADADDR);}
+ YY_BREAK
+ case 61:
+ YY_RULE_SETUP
+-#line 259 "ldlex.l"
++#line 259 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(ALIGNOF); }
+ YY_BREAK
+ case 62:
+ YY_RULE_SETUP
+-#line 260 "ldlex.l"
++#line 260 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(MAX_K); }
+ YY_BREAK
+ case 63:
+ YY_RULE_SETUP
+-#line 261 "ldlex.l"
++#line 261 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(MIN_K); }
+ YY_BREAK
+ case 64:
+ YY_RULE_SETUP
+-#line 262 "ldlex.l"
++#line 262 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(LOG2CEIL); }
+ YY_BREAK
+ case 65:
+ YY_RULE_SETUP
+-#line 263 "ldlex.l"
++#line 263 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(ASSERT_K); }
+ YY_BREAK
+ case 66:
+ YY_RULE_SETUP
+-#line 264 "ldlex.l"
++#line 264 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(ENTRY);}
+ YY_BREAK
+ case 67:
+ YY_RULE_SETUP
+-#line 265 "ldlex.l"
++#line 265 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(EXTERN);}
+ YY_BREAK
+ case 68:
+ YY_RULE_SETUP
+-#line 266 "ldlex.l"
++#line 266 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(NEXT);}
+ YY_BREAK
+ case 69:
+ YY_RULE_SETUP
+-#line 267 "ldlex.l"
++#line 267 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(SIZEOF_HEADERS);}
+ YY_BREAK
+ case 70:
+ YY_RULE_SETUP
+-#line 268 "ldlex.l"
++#line 268 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(SIZEOF_HEADERS);}
+ YY_BREAK
+ case 71:
+ YY_RULE_SETUP
+-#line 269 "ldlex.l"
++#line 269 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(SEGMENT_START);}
+ YY_BREAK
+ case 72:
+ YY_RULE_SETUP
+-#line 270 "ldlex.l"
++#line 270 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(MAP);}
+ YY_BREAK
+ case 73:
+ YY_RULE_SETUP
+-#line 271 "ldlex.l"
++#line 271 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(SIZEOF);}
+ YY_BREAK
+ case 74:
+ YY_RULE_SETUP
+-#line 272 "ldlex.l"
++#line 272 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(TARGET_K);}
+ YY_BREAK
+ case 75:
+ YY_RULE_SETUP
+-#line 273 "ldlex.l"
++#line 273 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(SEARCH_DIR);}
+ YY_BREAK
+ case 76:
+ YY_RULE_SETUP
+-#line 274 "ldlex.l"
++#line 274 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(OUTPUT);}
+ YY_BREAK
+ case 77:
+ YY_RULE_SETUP
+-#line 275 "ldlex.l"
++#line 275 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(INPUT);}
+ YY_BREAK
+ case 78:
+ YY_RULE_SETUP
+-#line 276 "ldlex.l"
++#line 276 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(GROUP);}
+ YY_BREAK
+ case 79:
+ YY_RULE_SETUP
+-#line 277 "ldlex.l"
++#line 277 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(AS_NEEDED);}
+ YY_BREAK
+ case 80:
+ YY_RULE_SETUP
+-#line 278 "ldlex.l"
++#line 278 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(DEFINED);}
+ YY_BREAK
+ case 81:
+ YY_RULE_SETUP
+-#line 279 "ldlex.l"
++#line 279 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(CREATE_OBJECT_SYMBOLS);}
+ YY_BREAK
+ case 82:
+ YY_RULE_SETUP
+-#line 280 "ldlex.l"
++#line 280 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN( CONSTRUCTORS);}
+ YY_BREAK
+ case 83:
+ YY_RULE_SETUP
+-#line 281 "ldlex.l"
++#line 281 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(FORCE_COMMON_ALLOCATION);}
+ YY_BREAK
+ case 84:
+ YY_RULE_SETUP
+-#line 282 "ldlex.l"
++#line 282 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(INHIBIT_COMMON_ALLOCATION);}
+ YY_BREAK
+ case 85:
+ YY_RULE_SETUP
+-#line 283 "ldlex.l"
++#line 283 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(SECTIONS);}
+ YY_BREAK
+ case 86:
+ YY_RULE_SETUP
+-#line 284 "ldlex.l"
++#line 284 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(INSERT_K);}
+ YY_BREAK
+ case 87:
+ YY_RULE_SETUP
+-#line 285 "ldlex.l"
++#line 285 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(AFTER);}
+ YY_BREAK
+ case 88:
+ YY_RULE_SETUP
+-#line 286 "ldlex.l"
++#line 286 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(BEFORE);}
+ YY_BREAK
+ case 89:
+ YY_RULE_SETUP
+-#line 287 "ldlex.l"
++#line 287 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(FILL);}
+ YY_BREAK
+ case 90:
+ YY_RULE_SETUP
+-#line 288 "ldlex.l"
++#line 288 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(STARTUP);}
+ YY_BREAK
+ case 91:
+ YY_RULE_SETUP
+-#line 289 "ldlex.l"
++#line 289 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(OUTPUT_FORMAT);}
+ YY_BREAK
+ case 92:
+ YY_RULE_SETUP
+-#line 290 "ldlex.l"
++#line 290 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN( OUTPUT_ARCH);}
+ YY_BREAK
+ case 93:
+ YY_RULE_SETUP
+-#line 291 "ldlex.l"
++#line 291 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(HLL);}
+ YY_BREAK
+ case 94:
+ YY_RULE_SETUP
+-#line 292 "ldlex.l"
++#line 292 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(SYSLIB);}
+ YY_BREAK
+ case 95:
+ YY_RULE_SETUP
+-#line 293 "ldlex.l"
++#line 293 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(FLOAT);}
+ YY_BREAK
+ case 96:
+ YY_RULE_SETUP
+-#line 294 "ldlex.l"
++#line 294 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN( QUAD);}
+ YY_BREAK
+ case 97:
+ YY_RULE_SETUP
+-#line 295 "ldlex.l"
++#line 295 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN( SQUAD);}
+ YY_BREAK
+ case 98:
+ YY_RULE_SETUP
+-#line 296 "ldlex.l"
++#line 296 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN( LONG);}
+ YY_BREAK
+ case 99:
+ YY_RULE_SETUP
+-#line 297 "ldlex.l"
++#line 297 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN( SHORT);}
+ YY_BREAK
+ case 100:
+ YY_RULE_SETUP
+-#line 298 "ldlex.l"
++#line 298 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN( BYTE);}
+ YY_BREAK
+ case 101:
+ YY_RULE_SETUP
+-#line 299 "ldlex.l"
++#line 299 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(NOFLOAT);}
+ YY_BREAK
+ case 102:
+ YY_RULE_SETUP
+-#line 300 "ldlex.l"
++#line 300 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(NOCROSSREFS);}
+ YY_BREAK
+ case 103:
+ YY_RULE_SETUP
+-#line 301 "ldlex.l"
++#line 301 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(NOCROSSREFS_TO);}
+ YY_BREAK
+ case 104:
+ YY_RULE_SETUP
+-#line 302 "ldlex.l"
++#line 302 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(OVERLAY); }
+ YY_BREAK
+ case 105:
+ YY_RULE_SETUP
+-#line 303 "ldlex.l"
++#line 303 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(SORT_BY_NAME); }
+ YY_BREAK
+ case 106:
+ YY_RULE_SETUP
+-#line 304 "ldlex.l"
++#line 304 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(SORT_BY_ALIGNMENT); }
+ YY_BREAK
+ case 107:
+ YY_RULE_SETUP
+-#line 305 "ldlex.l"
++#line 305 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(SORT_BY_NAME); }
+ YY_BREAK
+ case 108:
+ YY_RULE_SETUP
+-#line 306 "ldlex.l"
++#line 306 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(SORT_BY_INIT_PRIORITY); }
+ YY_BREAK
+ case 109:
+ YY_RULE_SETUP
+-#line 307 "ldlex.l"
++#line 307 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(SORT_NONE); }
+ YY_BREAK
+ case 110:
+ YY_RULE_SETUP
+-#line 308 "ldlex.l"
++#line 308 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(NOLOAD);}
+ YY_BREAK
+ case 111:
+ YY_RULE_SETUP
+-#line 309 "ldlex.l"
++#line 309 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(DSECT);}
+ YY_BREAK
+ case 112:
+ YY_RULE_SETUP
+-#line 310 "ldlex.l"
++#line 310 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(COPY);}
+ YY_BREAK
+ case 113:
+ YY_RULE_SETUP
+-#line 311 "ldlex.l"
++#line 311 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(INFO);}
+ YY_BREAK
+ case 114:
+ YY_RULE_SETUP
+-#line 312 "ldlex.l"
++#line 312 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(OVERLAY);}
+ YY_BREAK
+ case 115:
+ YY_RULE_SETUP
+-#line 313 "ldlex.l"
++#line 313 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(ONLY_IF_RO); }
+ YY_BREAK
+ case 116:
+ YY_RULE_SETUP
+-#line 314 "ldlex.l"
++#line 314 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(ONLY_IF_RW); }
+ YY_BREAK
+ case 117:
+ YY_RULE_SETUP
+-#line 315 "ldlex.l"
++#line 315 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(SPECIAL); }
+ YY_BREAK
+ case 118:
+ YY_RULE_SETUP
+-#line 316 "ldlex.l"
++#line 316 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(ORIGIN);}
+ YY_BREAK
+ case 119:
+ YY_RULE_SETUP
+-#line 317 "ldlex.l"
++#line 317 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(ORIGIN);}
+ YY_BREAK
+ case 120:
+ YY_RULE_SETUP
+-#line 318 "ldlex.l"
++#line 318 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN( LENGTH);}
+ YY_BREAK
+ case 121:
+ YY_RULE_SETUP
+-#line 319 "ldlex.l"
++#line 319 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN( LENGTH);}
+ YY_BREAK
+ case 122:
+ YY_RULE_SETUP
+-#line 320 "ldlex.l"
++#line 320 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(INPUT_SECTION_FLAGS); }
+ YY_BREAK
+ case 123:
+ YY_RULE_SETUP
+-#line 321 "ldlex.l"
++#line 321 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(INCLUDE);}
+ YY_BREAK
+ case 124:
+ YY_RULE_SETUP
+-#line 322 "ldlex.l"
++#line 322 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN (PHDRS); }
+ YY_BREAK
+ case 125:
+ YY_RULE_SETUP
+-#line 323 "ldlex.l"
++#line 323 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(AT);}
+ YY_BREAK
+ case 126:
+ YY_RULE_SETUP
+-#line 324 "ldlex.l"
++#line 324 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(ALIGN_WITH_INPUT);}
+ YY_BREAK
+ case 127:
+ YY_RULE_SETUP
+-#line 325 "ldlex.l"
++#line 325 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(SUBALIGN);}
+ YY_BREAK
+ case 128:
+ YY_RULE_SETUP
+-#line 326 "ldlex.l"
++#line 326 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(HIDDEN); }
+ YY_BREAK
+ case 129:
+ YY_RULE_SETUP
+-#line 327 "ldlex.l"
++#line 327 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(PROVIDE); }
+ YY_BREAK
+ case 130:
+ YY_RULE_SETUP
+-#line 328 "ldlex.l"
++#line 328 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(PROVIDE_HIDDEN); }
+ YY_BREAK
+ case 131:
+ YY_RULE_SETUP
+-#line 329 "ldlex.l"
++#line 329 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(KEEP); }
+ YY_BREAK
+ case 132:
+ YY_RULE_SETUP
+-#line 330 "ldlex.l"
++#line 330 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(EXCLUDE_FILE); }
+ YY_BREAK
+ case 133:
+ YY_RULE_SETUP
+-#line 331 "ldlex.l"
++#line 331 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(CONSTANT);}
+ YY_BREAK
+ case 134:
+ /* rule 134 can match eol */
+ YY_RULE_SETUP
+-#line 332 "ldlex.l"
++#line 332 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { ++ lineno; }
+ YY_BREAK
+ case 135:
+ /* rule 135 can match eol */
+ YY_RULE_SETUP
+-#line 333 "ldlex.l"
++#line 333 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { ++ lineno; RTOKEN(NEWLINE); }
+ YY_BREAK
+ case 136:
+ YY_RULE_SETUP
+-#line 334 "ldlex.l"
++#line 334 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { /* Mri comment line */ }
+ YY_BREAK
+ case 137:
+ YY_RULE_SETUP
+-#line 335 "ldlex.l"
++#line 335 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { /* Mri comment line */ }
+ YY_BREAK
+ case 138:
+ YY_RULE_SETUP
+-#line 336 "ldlex.l"
++#line 336 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(ENDWORD); }
+ YY_BREAK
+ case 139:
+ YY_RULE_SETUP
+-#line 337 "ldlex.l"
++#line 337 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(ALIGNMOD);}
+ YY_BREAK
+ case 140:
+ YY_RULE_SETUP
+-#line 338 "ldlex.l"
++#line 338 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(ALIGN_K);}
+ YY_BREAK
+ case 141:
+ YY_RULE_SETUP
+-#line 339 "ldlex.l"
++#line 339 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(CHIP); }
+ YY_BREAK
+ case 142:
+ YY_RULE_SETUP
+-#line 340 "ldlex.l"
++#line 340 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(BASE); }
+ YY_BREAK
+ case 143:
+ YY_RULE_SETUP
+-#line 341 "ldlex.l"
++#line 341 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(ALIAS); }
+ YY_BREAK
+ case 144:
+ YY_RULE_SETUP
+-#line 342 "ldlex.l"
++#line 342 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(TRUNCATE); }
+ YY_BREAK
+ case 145:
+ YY_RULE_SETUP
+-#line 343 "ldlex.l"
++#line 343 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(LOAD); }
+ YY_BREAK
+ case 146:
+ YY_RULE_SETUP
+-#line 344 "ldlex.l"
++#line 344 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(PUBLIC); }
+ YY_BREAK
+ case 147:
+ YY_RULE_SETUP
+-#line 345 "ldlex.l"
++#line 345 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(ORDER); }
+ YY_BREAK
+ case 148:
+ YY_RULE_SETUP
+-#line 346 "ldlex.l"
++#line 346 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(NAMEWORD); }
+ YY_BREAK
+ case 149:
+ YY_RULE_SETUP
+-#line 347 "ldlex.l"
++#line 347 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(FORMAT); }
+ YY_BREAK
+ case 150:
+ YY_RULE_SETUP
+-#line 348 "ldlex.l"
++#line 348 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(CASE); }
+ YY_BREAK
+ case 151:
+ YY_RULE_SETUP
+-#line 349 "ldlex.l"
++#line 349 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(START); }
+ YY_BREAK
+ case 152:
+ YY_RULE_SETUP
+-#line 350 "ldlex.l"
++#line 350 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(LIST); /* LIST and ignore to end of line */ }
+ YY_BREAK
+ case 153:
+ YY_RULE_SETUP
+-#line 351 "ldlex.l"
++#line 351 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(SECT); }
+ YY_BREAK
+ case 154:
+ YY_RULE_SETUP
+-#line 352 "ldlex.l"
++#line 352 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(ABSOLUTE); }
+ YY_BREAK
+ case 155:
+ YY_RULE_SETUP
+-#line 353 "ldlex.l"
++#line 353 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(ENDWORD); }
+ YY_BREAK
+ case 156:
+ YY_RULE_SETUP
+-#line 354 "ldlex.l"
++#line 354 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(ALIGNMOD);}
+ YY_BREAK
+ case 157:
+ YY_RULE_SETUP
+-#line 355 "ldlex.l"
++#line 355 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(ALIGN_K);}
+ YY_BREAK
+ case 158:
+ YY_RULE_SETUP
+-#line 356 "ldlex.l"
++#line 356 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(CHIP); }
+ YY_BREAK
+ case 159:
+ YY_RULE_SETUP
+-#line 357 "ldlex.l"
++#line 357 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(BASE); }
+ YY_BREAK
+ case 160:
+ YY_RULE_SETUP
+-#line 358 "ldlex.l"
++#line 358 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(ALIAS); }
+ YY_BREAK
+ case 161:
+ YY_RULE_SETUP
+-#line 359 "ldlex.l"
++#line 359 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(TRUNCATE); }
+ YY_BREAK
+ case 162:
+ YY_RULE_SETUP
+-#line 360 "ldlex.l"
++#line 360 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(LOAD); }
+ YY_BREAK
+ case 163:
+ YY_RULE_SETUP
+-#line 361 "ldlex.l"
++#line 361 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(PUBLIC); }
+ YY_BREAK
+ case 164:
+ YY_RULE_SETUP
+-#line 362 "ldlex.l"
++#line 362 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(ORDER); }
+ YY_BREAK
+ case 165:
+ YY_RULE_SETUP
+-#line 363 "ldlex.l"
++#line 363 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(NAMEWORD); }
+ YY_BREAK
+ case 166:
+ YY_RULE_SETUP
+-#line 364 "ldlex.l"
++#line 364 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(FORMAT); }
+ YY_BREAK
+ case 167:
+ YY_RULE_SETUP
+-#line 365 "ldlex.l"
++#line 365 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(CASE); }
+ YY_BREAK
+ case 168:
+ YY_RULE_SETUP
+-#line 366 "ldlex.l"
++#line 366 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(EXTERN); }
+ YY_BREAK
+ case 169:
+ YY_RULE_SETUP
+-#line 367 "ldlex.l"
++#line 367 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(START); }
+ YY_BREAK
+ case 170:
+ YY_RULE_SETUP
+-#line 368 "ldlex.l"
++#line 368 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(LIST); /* LIST and ignore to end of line */ }
+ YY_BREAK
+ case 171:
+ YY_RULE_SETUP
+-#line 369 "ldlex.l"
++#line 369 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(SECT); }
+ YY_BREAK
+ case 172:
+ YY_RULE_SETUP
+-#line 370 "ldlex.l"
++#line 370 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(ABSOLUTE); }
+ YY_BREAK
+ case 173:
+ YY_RULE_SETUP
+-#line 372 "ldlex.l"
++#line 372 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ {
+ /* Filename without commas, needed to parse mri stuff */
+ yylval.name = xstrdup (yytext);
+@@ -3008,7 +3033,7 @@ YY_RULE_SETUP
+ YY_BREAK
+ case 174:
+ YY_RULE_SETUP
+-#line 379 "ldlex.l"
++#line 379 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ {
+ yylval.name = xstrdup (yytext);
+ return NAME;
+@@ -3016,7 +3041,7 @@ YY_RULE_SETUP
+ YY_BREAK
+ case 175:
+ YY_RULE_SETUP
+-#line 383 "ldlex.l"
++#line 383 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ {
+ /* Filename to be prefixed by --sysroot or when non-sysrooted, nothing. */
+ yylval.name = xstrdup (yytext);
+@@ -3025,7 +3050,7 @@ YY_RULE_SETUP
+ YY_BREAK
+ case 176:
+ YY_RULE_SETUP
+-#line 388 "ldlex.l"
++#line 388 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ {
+ yylval.name = xstrdup (yytext + 2);
+ return LNAME;
+@@ -3033,7 +3058,7 @@ YY_RULE_SETUP
+ YY_BREAK
+ case 177:
+ YY_RULE_SETUP
+-#line 392 "ldlex.l"
++#line 392 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ {
+ yylval.name = xstrdup (yytext);
+ return NAME;
+@@ -3041,7 +3066,7 @@ YY_RULE_SETUP
+ YY_BREAK
+ case 178:
+ YY_RULE_SETUP
+-#line 396 "ldlex.l"
++#line 396 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ {
+ yylval.name = xstrdup (yytext + 2);
+ return LNAME;
+@@ -3049,7 +3074,7 @@ YY_RULE_SETUP
+ YY_BREAK
+ case 179:
+ YY_RULE_SETUP
+-#line 400 "ldlex.l"
++#line 400 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ {
+ /* Annoyingly, this pattern can match comments, and we have
+ longest match issues to consider. So if the first two
+@@ -3070,66 +3095,72 @@ YY_RULE_SETUP
+ case 180:
+ /* rule 180 can match eol */
+ YY_RULE_SETUP
+-#line 417 "ldlex.l"
++#line 417 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ {
+ /* No matter the state, quotes
+- give what's inside */
++ give what's inside. */
++ bfd_size_type len;
+ yylval.name = xstrdup (yytext + 1);
+- yylval.name[yyleng - 2] = 0;
++ /* PR ld/20906. A corrupt input file
++ can contain bogus strings. */
++ len = strlen (yylval.name);
++ if (len > yyleng - 2)
++ len = yyleng - 2;
++ yylval.name[len] = 0;
+ return NAME;
+ }
+ YY_BREAK
+ case 181:
+ /* rule 181 can match eol */
+ YY_RULE_SETUP
+-#line 424 "ldlex.l"
++#line 430 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { lineno++;}
+ YY_BREAK
+ case 182:
+ YY_RULE_SETUP
+-#line 425 "ldlex.l"
++#line 431 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { }
+ YY_BREAK
+ case 183:
+ YY_RULE_SETUP
+-#line 427 "ldlex.l"
++#line 433 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { return *yytext; }
+ YY_BREAK
+ case 184:
+ YY_RULE_SETUP
+-#line 429 "ldlex.l"
++#line 435 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(GLOBAL); }
+ YY_BREAK
+ case 185:
+ YY_RULE_SETUP
+-#line 431 "ldlex.l"
++#line 437 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(LOCAL); }
+ YY_BREAK
+ case 186:
+ YY_RULE_SETUP
+-#line 433 "ldlex.l"
++#line 439 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { RTOKEN(EXTERN); }
+ YY_BREAK
+ case 187:
+ YY_RULE_SETUP
+-#line 435 "ldlex.l"
++#line 441 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { yylval.name = xstrdup (yytext);
+ return VERS_IDENTIFIER; }
+ YY_BREAK
+ case 188:
+ YY_RULE_SETUP
+-#line 438 "ldlex.l"
++#line 444 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { yylval.name = xstrdup (yytext);
+ return VERS_TAG; }
+ YY_BREAK
+ case 189:
+ YY_RULE_SETUP
+-#line 441 "ldlex.l"
++#line 447 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { BEGIN(VERS_SCRIPT); return *yytext; }
+ YY_BREAK
+ case 190:
+ YY_RULE_SETUP
+-#line 443 "ldlex.l"
++#line 449 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { BEGIN(VERS_NODE);
+ vers_node_nesting = 0;
+ return *yytext;
+@@ -3137,17 +3168,17 @@ YY_RULE_SETUP
+ YY_BREAK
+ case 191:
+ YY_RULE_SETUP
+-#line 447 "ldlex.l"
++#line 453 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { return *yytext; }
+ YY_BREAK
+ case 192:
+ YY_RULE_SETUP
+-#line 448 "ldlex.l"
++#line 454 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { vers_node_nesting++; return *yytext; }
+ YY_BREAK
+ case 193:
+ YY_RULE_SETUP
+-#line 449 "ldlex.l"
++#line 455 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { if (--vers_node_nesting < 0)
+ BEGIN(VERS_SCRIPT);
+ return *yytext;
+@@ -3156,17 +3187,17 @@ YY_RULE_SETUP
+ case 194:
+ /* rule 194 can match eol */
+ YY_RULE_SETUP
+-#line 454 "ldlex.l"
++#line 460 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { lineno++; }
+ YY_BREAK
+ case 195:
+ YY_RULE_SETUP
+-#line 456 "ldlex.l"
++#line 462 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { /* Eat up comments */ }
+ YY_BREAK
+ case 196:
+ YY_RULE_SETUP
+-#line 458 "ldlex.l"
++#line 464 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ { /* Eat up whitespace */ }
+ YY_BREAK
+ case YY_STATE_EOF(INITIAL):
+@@ -3179,7 +3210,7 @@ case YY_STATE_EOF(MRI):
+ case YY_STATE_EOF(VERS_START):
+ case YY_STATE_EOF(VERS_SCRIPT):
+ case YY_STATE_EOF(VERS_NODE):
+-#line 460 "ldlex.l"
++#line 466 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ {
+ include_stack_ptr--;
+ if (include_stack_ptr == 0)
+@@ -3195,20 +3226,20 @@ case YY_STATE_EOF(VERS_NODE):
+ YY_BREAK
+ case 197:
+ YY_RULE_SETUP
+-#line 473 "ldlex.l"
++#line 479 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ lex_warn_invalid (" in script", yytext);
+ YY_BREAK
+ case 198:
+ YY_RULE_SETUP
+-#line 474 "ldlex.l"
++#line 480 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ lex_warn_invalid (" in expression", yytext);
+ YY_BREAK
+ case 199:
+ YY_RULE_SETUP
+-#line 476 "ldlex.l"
++#line 482 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+ ECHO;
+ YY_BREAK
+-#line 3212 "ldlex.c"
++#line 3243 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.c"
+
+ case YY_END_OF_BUFFER:
+ {
+@@ -3337,6 +3368,7 @@ ECHO;
+ "fatal flex scanner internal error--no action found" );
+ } /* end of action switch */
+ } /* end of scanning one token */
++ } /* end of user's declarations */
+ } /* end of yylex */
+
+ /* yy_get_next_buffer - try to read in a new buffer
+@@ -3348,9 +3380,9 @@ ECHO;
+ */
+ static int yy_get_next_buffer (void)
+ {
+- register char *dest = YY_CURRENT_BUFFER_LVALUE->yy_ch_buf;
+- register char *source = (yytext_ptr);
+- register int number_to_move, i;
++ char *dest = YY_CURRENT_BUFFER_LVALUE->yy_ch_buf;
++ char *source = (yytext_ptr);
++ yy_size_t number_to_move, i;
+ int ret_val;
+
+ if ( (yy_c_buf_p) > &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[(yy_n_chars) + 1] )
+@@ -3379,7 +3411,7 @@ static int yy_get_next_buffer (void)
+ /* Try to read more data. */
+
+ /* First move last chars to start of buffer. */
+- number_to_move = (int) ((yy_c_buf_p) - (yytext_ptr)) - 1;
++ number_to_move = (yy_size_t) ((yy_c_buf_p) - (yytext_ptr)) - 1;
+
+ for ( i = 0; i < number_to_move; ++i )
+ *(dest++) = *(source++);
+@@ -3392,14 +3424,14 @@ static int yy_get_next_buffer (void)
+
+ else
+ {
+- yy_size_t num_to_read =
++ int num_to_read =
+ YY_CURRENT_BUFFER_LVALUE->yy_buf_size - number_to_move - 1;
+
+ while ( num_to_read <= 0 )
+ { /* Not enough room in the buffer - grow it. */
+
+ /* just a shorter name for the current buffer */
+- YY_BUFFER_STATE b = YY_CURRENT_BUFFER;
++ YY_BUFFER_STATE b = YY_CURRENT_BUFFER_LVALUE;
+
+ int yy_c_buf_p_offset =
+ (int) ((yy_c_buf_p) - b->yy_ch_buf);
+@@ -3482,14 +3514,14 @@ static int yy_get_next_buffer (void)
+
+ static yy_state_type yy_get_previous_state (void)
+ {
+- register yy_state_type yy_current_state;
+- register char *yy_cp;
++ yy_state_type yy_current_state;
++ char *yy_cp;
+
+ yy_current_state = (yy_start);
+
+ for ( yy_cp = (yytext_ptr) + YY_MORE_ADJ; yy_cp < (yy_c_buf_p); ++yy_cp )
+ {
+- register YY_CHAR yy_c = (*yy_cp ? yy_ec[YY_SC_TO_UI(*yy_cp)] : 1);
++ YY_CHAR yy_c = (*yy_cp ? yy_ec[YY_SC_TO_UI(*yy_cp)] : 1);
+ if ( yy_accept[yy_current_state] )
+ {
+ (yy_last_accepting_state) = yy_current_state;
+@@ -3514,10 +3546,10 @@ static int yy_get_next_buffer (void)
+ */
+ static yy_state_type yy_try_NUL_trans (yy_state_type yy_current_state )
+ {
+- register int yy_is_jam;
+- register char *yy_cp = (yy_c_buf_p);
++ int yy_is_jam;
++ char *yy_cp = (yy_c_buf_p);
+
+- register YY_CHAR yy_c = 1;
++ YY_CHAR yy_c = 1;
+ if ( yy_accept[yy_current_state] )
+ {
+ (yy_last_accepting_state) = yy_current_state;
+@@ -3532,9 +3564,13 @@ static int yy_get_next_buffer (void)
+ yy_current_state = yy_nxt[yy_base[yy_current_state] + (unsigned int) yy_c];
+ yy_is_jam = (yy_current_state == 1774);
+
+- return yy_is_jam ? 0 : yy_current_state;
++ return yy_is_jam ? 0 : yy_current_state;
+ }
+
++#ifndef YY_NO_UNPUT
++
++#endif
++
+ #ifndef YY_NO_INPUT
+ #ifdef __cplusplus
+ static int yyinput (void)
+@@ -3583,7 +3619,7 @@ static int yy_get_next_buffer (void)
+ case EOB_ACT_END_OF_FILE:
+ {
+ if ( yywrap( ) )
+- return 0;
++ return EOF;
+
+ if ( ! (yy_did_buffer_switch_on_eof) )
+ YY_NEW_FILE;
+@@ -3684,7 +3720,7 @@ static void yy_load_buffer_state (void)
+ if ( ! b )
+ YY_FATAL_ERROR( "out of dynamic memory in yy_create_buffer()" );
+
+- b->yy_buf_size = size;
++ b->yy_buf_size = (yy_size_t)size;
+
+ /* yy_ch_buf has to be 2 characters longer than the size given because
+ * we need to put in 2 end-of-buffer characters.
+@@ -3719,10 +3755,6 @@ static void yy_load_buffer_state (void)
+ yyfree((void *) b );
+ }
+
+-#ifndef __cplusplus
+-extern int isatty (int );
+-#endif /* __cplusplus */
+-
+ /* Initializes or reinitializes a buffer.
+ * This function is sometimes called more than once on the same buffer,
+ * such as during a yyrestart() or at EOF.
+@@ -3843,7 +3875,7 @@ static void yyensure_buffer_stack (void)
+ * scanner will even need a stack. We use 2 instead of 1 to avoid an
+ * immediate realloc on the next call.
+ */
+- num_to_alloc = 1;
++ num_to_alloc = 1; /* After all that talk, this was set to 1 anyways... */
+ (yy_buffer_stack) = (struct yy_buffer_state**)yyalloc
+ (num_to_alloc * sizeof(struct yy_buffer_state*)
+ );
+@@ -3860,7 +3892,7 @@ static void yyensure_buffer_stack (void)
+ if ((yy_buffer_stack_top) >= ((yy_buffer_stack_max)) - 1){
+
+ /* Increase the buffer to prepare for a possible push. */
+- int grow_size = 8 /* arbitrary grow size */;
++ yy_size_t grow_size = 8 /* arbitrary grow size */;
+
+ num_to_alloc = (yy_buffer_stack_max) + grow_size;
+ (yy_buffer_stack) = (struct yy_buffer_state**)yyrealloc
+@@ -3927,8 +3959,8 @@ YY_BUFFER_STATE yy_scan_string (yyconst
+
+ /** Setup the input buffer state to scan the given bytes. The next call to yylex() will
+ * scan from a @e copy of @a bytes.
+- * @param bytes the byte buffer to scan
+- * @param len the number of bytes in the buffer pointed to by @a bytes.
++ * @param yybytes the byte buffer to scan
++ * @param _yybytes_len the number of bytes in the buffer pointed to by @a bytes.
+ *
+ * @return the newly allocated buffer state object.
+ */
+@@ -3936,7 +3968,8 @@ YY_BUFFER_STATE yy_scan_bytes (yyconst
+ {
+ YY_BUFFER_STATE b;
+ char *buf;
+- yy_size_t n, i;
++ yy_size_t n;
++ yy_size_t i;
+
+ /* Get memory for full buffer, including space for trailing EOB's. */
+ n = _yybytes_len + 2;
+@@ -3967,7 +4000,7 @@ YY_BUFFER_STATE yy_scan_bytes (yyconst
+
+ static void yy_fatal_error (yyconst char* msg )
+ {
+- (void) fprintf( stderr, "%s\n", msg );
++ (void) fprintf( stderr, "%s\n", msg );
+ exit( YY_EXIT_FAILURE );
+ }
+
+@@ -3978,7 +4011,7 @@ static void yy_fatal_error (yyconst char
+ do \
+ { \
+ /* Undo effects of setting up yytext. */ \
+- int yyless_macro_arg = (n); \
++ yy_size_t yyless_macro_arg = (n); \
+ YY_LESS_LINENO(yyless_macro_arg);\
+ yytext[yyleng] = (yy_hold_char); \
+ (yy_c_buf_p) = yytext + yyless_macro_arg; \
+@@ -4033,29 +4066,29 @@ char *yyget_text (void)
+ }
+
+ /** Set the current line number.
+- * @param line_number
++ * @param _line_number line number
+ *
+ */
+-void yyset_lineno (int line_number )
++void yyset_lineno (int _line_number )
+ {
+
+- yylineno = line_number;
++ yylineno = _line_number;
+ }
+
+ /** Set the input stream. This does not discard the current
+ * input buffer.
+- * @param in_str A readable stream.
++ * @param _in_str A readable stream.
+ *
+ * @see yy_switch_to_buffer
+ */
+-void yyset_in (FILE * in_str )
++void yyset_in (FILE * _in_str )
+ {
+- yyin = in_str ;
++ yyin = _in_str ;
+ }
+
+-void yyset_out (FILE * out_str )
++void yyset_out (FILE * _out_str )
+ {
+- yyout = out_str ;
++ yyout = _out_str ;
+ }
+
+ int yyget_debug (void)
+@@ -4063,9 +4096,9 @@ int yyget_debug (void)
+ return yy_flex_debug;
+ }
+
+-void yyset_debug (int bdebug )
++void yyset_debug (int _bdebug )
+ {
+- yy_flex_debug = bdebug ;
++ yy_flex_debug = _bdebug ;
+ }
+
+ static int yy_init_globals (void)
+@@ -4125,7 +4158,8 @@ int yylex_destroy (void)
+ #ifndef yytext_ptr
+ static void yy_flex_strncpy (char* s1, yyconst char * s2, int n )
+ {
+- register int i;
++
++ int i;
+ for ( i = 0; i < n; ++i )
+ s1[i] = s2[i];
+ }
+@@ -4134,7 +4168,7 @@ static void yy_flex_strncpy (char* s1, y
+ #ifdef YY_NEED_STRLEN
+ static int yy_flex_strlen (yyconst char * s )
+ {
+- register int n;
++ int n;
+ for ( n = 0; s[n]; ++n )
+ ;
+
+@@ -4144,11 +4178,12 @@ static int yy_flex_strlen (yyconst char
+
+ void *yyalloc (yy_size_t size )
+ {
+- return (void *) malloc( size );
++ return (void *) malloc( size );
+ }
+
+ void *yyrealloc (void * ptr, yy_size_t size )
+ {
++
+ /* The cast to (char *) in the following accommodates both
+ * implementations that use char* generic pointers, and those
+ * that use void* generic pointers. It works with the latter
+@@ -4161,12 +4196,12 @@ void *yyrealloc (void * ptr, yy_size_t
+
+ void yyfree (void * ptr )
+ {
+- free( (char *) ptr ); /* see yyrealloc() for (char *) cast */
++ free( (char *) ptr ); /* see yyrealloc() for (char *) cast */
+ }
+
+ #define YYTABLES_NAME "yytables"
+
+-#line 476 "ldlex.l"
++#line 482 "/work/sources/rhel/binutils/rhel-7.4/binutils-2.27/ld/ldlex.l"
+
+
+
+diff -rup binutils.orig/ld/ldlex.l binutils-2.27/ld/ldlex.l
+--- binutils.orig/ld/ldlex.l 2017-03-24 13:50:55.613184724 +0000
++++ binutils-2.27/ld/ldlex.l 2017-03-24 14:20:35.039227142 +0000
+@@ -416,9 +416,15 @@ V_IDENTIFIER [*?.$_a-zA-Z\[\]\-\!\^\\]([
+
+ <EXPRESSION,BOTH,SCRIPT,VERS_NODE,INPUTLIST>"\""[^\"]*"\"" {
+ /* No matter the state, quotes
+- give what's inside */
++ give what's inside. */
++ bfd_size_type len;
+ yylval.name = xstrdup (yytext + 1);
+- yylval.name[yyleng - 2] = 0;
++ /* PR ld/20906. A corrupt input file
++ can contain bogus strings. */
++ len = strlen (yylval.name);
++ if (len > yyleng - 2)
++ len = yyleng - 2;
++ yylval.name[len] = 0;
+ return NAME;
+ }
+ <BOTH,SCRIPT,EXPRESSION>"\n" { lineno++;}
diff --git a/SOURCES/binutils-2.27-filename-in-error-messages.patch b/SOURCES/binutils-2.27-filename-in-error-messages.patch
new file mode 100644
index 0000000..19654c7
--- /dev/null
+++ b/SOURCES/binutils-2.27-filename-in-error-messages.patch
@@ -0,0 +1,84 @@
+--- binutils-2.27.orig/binutils/readelf.c 2017-01-16 11:51:05.043922264 +0000
++++ binutils-2.27/binutils/readelf.c 2017-01-16 12:01:34.389053872 +0000
+@@ -16733,39 +16733,49 @@ process_archive (char * file_name, FILE
+ static int
+ process_file (char * file_name)
+ {
++ char * name;
++ char * saved_program_name;
+ FILE * file;
+ struct stat statbuf;
+ char armag[SARMAG];
+- int ret;
++ int ret = 1;
++
++ /* Overload program_name to include file_name. Doing this means
++ that warning/error messages will positively identify the file
++ concerned even when multiple instances of readelf are running. */
++ name = xmalloc (strlen (program_name) + strlen (file_name) + 3);
++ sprintf (name, "%s: %s", program_name, file_name);
++ saved_program_name = program_name;
++ program_name = name;
+
+ if (stat (file_name, &statbuf) < 0)
+ {
+ if (errno == ENOENT)
+- error (_("'%s': No such file\n"), file_name);
++ error (_("No such file\n"));
+ else
+- error (_("Could not locate '%s'. System error message: %s\n"),
+- file_name, strerror (errno));
+- return 1;
++ error (_("Could not locate file. System error message: %s\n"),
++ strerror (errno));
++ goto done;
+ }
+
+ if (! S_ISREG (statbuf.st_mode))
+ {
+- error (_("'%s' is not an ordinary file\n"), file_name);
+- return 1;
++ error (_("Not an ordinary file\n"));
++ goto done;
+ }
+
+ file = fopen (file_name, "rb");
+ if (file == NULL)
+ {
+- error (_("Input file '%s' is not readable.\n"), file_name);
+- return 1;
++ error (_("Not readable\n"));
++ goto done;
+ }
+
+ if (fread (armag, SARMAG, 1, file) != 1)
+ {
+- error (_("%s: Failed to read file's magic number\n"), file_name);
++ error (_("Failed to read file's magic number\n"));
+ fclose (file);
+- return 1;
++ goto done;
+ }
+
+ current_file_size = (bfd_size_type) statbuf.st_size;
+@@ -16777,8 +16787,7 @@ process_file (char * file_name)
+ else
+ {
+ if (do_archive_index)
+- error (_("File %s is not an archive so its index cannot be displayed.\n"),
+- file_name);
++ error (_("Not an archive so its index cannot be displayed\n"));
+
+ rewind (file);
+ archive_file_size = archive_file_offset = 0;
+@@ -16787,7 +16796,10 @@ process_file (char * file_name)
+
+ fclose (file);
+
++ done:
+ current_file_size = 0;
++ free (program_name);
++ program_name = saved_program_name;
+ return ret;
+ }
+
diff --git a/SOURCES/binutils-2.27-gold.patch b/SOURCES/binutils-2.27-gold.patch
new file mode 100644
index 0000000..96fef02
--- /dev/null
+++ b/SOURCES/binutils-2.27-gold.patch
@@ -0,0 +1,1717 @@
+diff -rup ../binutils-2.27/gold/aarch64.cc gold/aarch64.cc
+--- ../binutils-2.27/gold/aarch64.cc 2016-09-26 11:22:18.728811436 +0100
++++ gold/aarch64.cc 2016-11-03 15:05:31.000000000 +0000
+@@ -6026,6 +6026,23 @@ Target_aarch64<size, big_endian>::Scan::
+ }
+ break;
+
++ case elfcpp::R_AARCH64_MOVW_UABS_G0: // 263
++ case elfcpp::R_AARCH64_MOVW_UABS_G0_NC: // 264
++ case elfcpp::R_AARCH64_MOVW_UABS_G1: // 265
++ case elfcpp::R_AARCH64_MOVW_UABS_G1_NC: // 266
++ case elfcpp::R_AARCH64_MOVW_UABS_G2: // 267
++ case elfcpp::R_AARCH64_MOVW_UABS_G2_NC: // 268
++ case elfcpp::R_AARCH64_MOVW_UABS_G3: // 269
++ case elfcpp::R_AARCH64_MOVW_SABS_G0: // 270
++ case elfcpp::R_AARCH64_MOVW_SABS_G1: // 271
++ case elfcpp::R_AARCH64_MOVW_SABS_G2: // 272
++ if (parameters->options().output_is_position_independent())
++ {
++ gold_error(_("%s: unsupported reloc %u in pos independent link."),
++ object->name().c_str(), r_type);
++ }
++ break;
++
+ case elfcpp::R_AARCH64_LD_PREL_LO19: // 273
+ case elfcpp::R_AARCH64_ADR_PREL_LO21: // 274
+ case elfcpp::R_AARCH64_ADR_PREL_PG_HI21: // 275
+@@ -6311,6 +6328,23 @@ Target_aarch64<size, big_endian>::Scan::
+ }
+ break;
+
++ case elfcpp::R_AARCH64_MOVW_UABS_G0: // 263
++ case elfcpp::R_AARCH64_MOVW_UABS_G0_NC: // 264
++ case elfcpp::R_AARCH64_MOVW_UABS_G1: // 265
++ case elfcpp::R_AARCH64_MOVW_UABS_G1_NC: // 266
++ case elfcpp::R_AARCH64_MOVW_UABS_G2: // 267
++ case elfcpp::R_AARCH64_MOVW_UABS_G2_NC: // 268
++ case elfcpp::R_AARCH64_MOVW_UABS_G3: // 269
++ case elfcpp::R_AARCH64_MOVW_SABS_G0: // 270
++ case elfcpp::R_AARCH64_MOVW_SABS_G1: // 271
++ case elfcpp::R_AARCH64_MOVW_SABS_G2: // 272
++ if (parameters->options().output_is_position_independent())
++ {
++ gold_error(_("%s: unsupported reloc %u in pos independent link."),
++ object->name().c_str(), r_type);
++ }
++ break;
++
+ case elfcpp::R_AARCH64_LD_PREL_LO19: // 273
+ case elfcpp::R_AARCH64_ADR_PREL_LO21: // 274
+ case elfcpp::R_AARCH64_ADR_PREL_PG_HI21: // 275
+@@ -6993,6 +7027,23 @@ Target_aarch64<size, big_endian>::Reloca
+ view, object, psymval, addend, address, reloc_property);
+ break;
+
++ case elfcpp::R_AARCH64_MOVW_UABS_G0:
++ case elfcpp::R_AARCH64_MOVW_UABS_G0_NC:
++ case elfcpp::R_AARCH64_MOVW_UABS_G1:
++ case elfcpp::R_AARCH64_MOVW_UABS_G1_NC:
++ case elfcpp::R_AARCH64_MOVW_UABS_G2:
++ case elfcpp::R_AARCH64_MOVW_UABS_G2_NC:
++ case elfcpp::R_AARCH64_MOVW_UABS_G3:
++ reloc_status = Reloc::template rela_general<32>(
++ view, object, psymval, addend, reloc_property);
++ break;
++ case elfcpp::R_AARCH64_MOVW_SABS_G0:
++ case elfcpp::R_AARCH64_MOVW_SABS_G1:
++ case elfcpp::R_AARCH64_MOVW_SABS_G2:
++ reloc_status = Reloc::movnz(view, psymval->value(object, addend),
++ reloc_property);
++ break;
++
+ case elfcpp::R_AARCH64_LD_PREL_LO19:
+ reloc_status = Reloc::template pcrela_general<32>(
+ view, object, psymval, addend, address, reloc_property);
+@@ -8075,7 +8126,7 @@ Target_aarch64<size, big_endian>::is_err
+ typename elfcpp::Swap<32,big_endian>::Valtype insn2)
+ {
+ uint32_t rt;
+- uint32_t rt2;
++ uint32_t rt2 = 0;
+ uint32_t rn;
+ uint32_t rm;
+ uint32_t ra;
+diff -rup ../binutils-2.27/gold/aarch64-reloc.def gold/aarch64-reloc.def
+--- ../binutils-2.27/gold/aarch64-reloc.def 2016-08-03 08:36:53.000000000 +0100
++++ gold/aarch64-reloc.def 2016-11-03 14:38:22.000000000 +0000
+@@ -43,6 +43,20 @@ ARD(PREL32 , STATI
+ ARD(PREL16 , STATIC , DATA , Y, -1, 15,16 , 0,0 , Symbol::RELATIVE_REF , DATA )
+ // Above is from Table 4-6, Data relocations, 257-262.
+
++ARD(MOVW_UABS_G0 , STATIC , AARCH64 , Y, 0, 0,16 , 0,15 , Symbol::ABSOLUTE_REF , MOVW )
++ARD(MOVW_UABS_G0_NC , STATIC , AARCH64 , Y, 0, 0,0 , 0,15 , Symbol::ABSOLUTE_REF , MOVW )
++ARD(MOVW_UABS_G1 , STATIC , AARCH64 , Y, 0, 0,32 , 16,31 , Symbol::ABSOLUTE_REF , MOVW )
++ARD(MOVW_UABS_G1_NC , STATIC , AARCH64 , Y, 0, 0,0 , 16,31 , Symbol::ABSOLUTE_REF , MOVW )
++ARD(MOVW_UABS_G2 , STATIC , AARCH64 , Y, 0, 0,48 , 32,47 , Symbol::ABSOLUTE_REF , MOVW )
++ARD(MOVW_UABS_G2_NC , STATIC , AARCH64 , Y, 0, 0,0 , 32,47 , Symbol::ABSOLUTE_REF , MOVW )
++ARD(MOVW_UABS_G3 , STATIC , AARCH64 , Y, 0, 0,0 , 48,63 , Symbol::ABSOLUTE_REF , MOVW )
++// Above is from Table 4-7, Group relocations to create a 16-, 32-, 48-, or 64-bit unsigned data value or address inline.
++
++ARD(MOVW_SABS_G0 , STATIC , AARCH64 , Y, 0, 16,16 , 0,15 , Symbol::ABSOLUTE_REF , MOVW )
++ARD(MOVW_SABS_G1 , STATIC , AARCH64 , Y, 0, 32,32 , 16,31 , Symbol::ABSOLUTE_REF , MOVW )
++ARD(MOVW_SABS_G2 , STATIC , AARCH64 , Y, 0, 48,48 , 32,47 , Symbol::ABSOLUTE_REF , MOVW )
++// Above is from Table 4-8, Group relocations to create a 16, 32, 48, or 64 bit signed data or offset value inline.
++
+ ARD(LD_PREL_LO19 , STATIC , AARCH64 , Y, -1, 20,20 , 2,20 , Symbol::RELATIVE_REF , LDST )
+ ARD(ADR_PREL_LO21 , STATIC , AARCH64 , Y, -1, 20,20 , 0,20 , Symbol::RELATIVE_REF , ADR )
+ ARD(ADR_PREL_PG_HI21 , STATIC , AARCH64 , Y, -1, 32,32 , 12,32 , Symbol::RELATIVE_REF , ADRP )
+diff -rup ../binutils-2.27/gold/aarch64-reloc-property.cc gold/aarch64-reloc-property.cc
+--- ../binutils-2.27/gold/aarch64-reloc-property.cc 2016-08-03 08:36:53.000000000 +0100
++++ gold/aarch64-reloc-property.cc 2016-11-03 15:05:32.000000000 +0000
+@@ -59,17 +59,51 @@ template<>
+ bool
+ rvalue_checkup<0, 0>(int64_t) { return true; }
+
++namespace
++{
++
+ template<int L, int U>
+-uint64_t
+-rvalue_bit_select(uint64_t x)
++class Rvalue_bit_select_impl
+ {
+- if (U == 63) return x >> L;
+- return (x & (((uint64_t)1 << (U+1)) - 1)) >> L;
+-}
++public:
++ static uint64_t
++ calc(uint64_t x)
++ {
++ return (x & ((1ULL << (U+1)) - 1)) >> L;
++ }
++};
++
++template<int L>
++class Rvalue_bit_select_impl<L, 63>
++{
++public:
++ static uint64_t
++ calc(uint64_t x)
++ {
++ return x >> L;
++ }
++};
+
++// By our convention, L=U=0 means that the whole value should be retrieved.
+ template<>
++class Rvalue_bit_select_impl<0, 0>
++{
++public:
++ static uint64_t
++ calc(uint64_t x)
++ {
++ return x;
++ }
++};
++
++} // End anonymous namespace.
++
++template<int L, int U>
+ uint64_t
+-rvalue_bit_select<0, 0>(uint64_t x) { return x; }
++rvalue_bit_select(uint64_t x)
++{
++ return Rvalue_bit_select_impl<L, U>::calc(x);
++}
+
+ AArch64_reloc_property::AArch64_reloc_property(
+ unsigned int code,
+diff -rup ../binutils-2.27/gold/arm.cc gold/arm.cc
+--- ../binutils-2.27/gold/arm.cc 2016-09-26 11:22:18.629810833 +0100
++++ gold/arm.cc 2016-11-03 15:05:33.000000000 +0000
+@@ -2128,8 +2128,36 @@ class Target_arm : public Sized_target<3
+ stub_tables_(), stub_factory_(Stub_factory::get_instance()),
+ should_force_pic_veneer_(false),
+ arm_input_section_map_(), attributes_section_data_(NULL),
+- fix_cortex_a8_(false), cortex_a8_relocs_info_()
+- { }
++ fix_cortex_a8_(false), cortex_a8_relocs_info_(),
++ target1_reloc_(elfcpp::R_ARM_ABS32),
++ // This can be any reloc type but usually is R_ARM_GOT_PREL.
++ target2_reloc_(elfcpp::R_ARM_GOT_PREL)
++ {
++ if (parameters->options().user_set_target1_rel())
++ {
++ // FIXME: This is not strictly compatible with ld, which allows both
++ // --target1-abs and --target-rel to be given.
++ if (parameters->options().user_set_target1_abs())
++ gold_error(_("Cannot use both --target1-abs and --target1-rel."));
++ else
++ this->target1_reloc_ = elfcpp::R_ARM_REL32;
++ }
++ // We don't need to handle --target1-abs because target1_reloc_ is set
++ // to elfcpp::R_ARM_ABS32 in the member initializer list.
++
++ if (parameters->options().user_set_target2())
++ {
++ const char* target2 = parameters->options().target2();
++ if (strcmp(target2, "rel") == 0)
++ this->target2_reloc_ = elfcpp::R_ARM_REL32;
++ else if (strcmp(target2, "abs") == 0)
++ this->target2_reloc_ = elfcpp::R_ARM_ABS32;
++ else if (strcmp(target2, "got-rel") == 0)
++ this->target2_reloc_ = elfcpp::R_ARM_GOT_PREL;
++ else
++ gold_unreachable();
++ }
++ }
+
+ // Whether we force PCI branch veneers.
+ bool
+@@ -2391,8 +2419,8 @@ class Target_arm : public Sized_target<3
+ rel_irelative_section(Layout*);
+
+ // Map platform-specific reloc types
+- static unsigned int
+- get_real_reloc_type(unsigned int r_type);
++ unsigned int
++ get_real_reloc_type(unsigned int r_type) const;
+
+ //
+ // Methods to support stub-generations.
+@@ -3002,6 +3030,11 @@ class Target_arm : public Sized_target<3
+ bool fix_cortex_a8_;
+ // Map addresses to relocs for Cortex-A8 erratum.
+ Cortex_a8_relocs_info cortex_a8_relocs_info_;
++ // What R_ARM_TARGET1 maps to. It can be R_ARM_REL32 or R_ARM_ABS32.
++ unsigned int target1_reloc_;
++ // What R_ARM_TARGET2 maps to. It should be one of R_ARM_REL32, R_ARM_ABS32
++ // and R_ARM_GOT_PREL.
++ unsigned int target2_reloc_;
+ };
+
+ template<bool big_endian>
+@@ -6639,6 +6672,80 @@ Arm_relobj<big_endian>::do_relocate_sect
+ section_address,
+ section_size);
+ }
++ // BE8 swapping
++ if (parameters->options().be8())
++ {
++ section_size_type span_start, span_end;
++ elfcpp::Shdr<32, big_endian>
++ shdr(pshdrs + i * elfcpp::Elf_sizes<32>::shdr_size);
++ Mapping_symbol_position section_start(i, 0);
++ typename Mapping_symbols_info::const_iterator p =
++ this->mapping_symbols_info_.lower_bound(section_start);
++ unsigned char* view = (*pviews)[i].view;
++ Arm_address view_address = (*pviews)[i].address;
++ section_size_type view_size = (*pviews)[i].view_size;
++ while (p != this->mapping_symbols_info_.end()
++ && p->first.first == i)
++ {
++ typename Mapping_symbols_info::const_iterator next =
++ this->mapping_symbols_info_.upper_bound(p->first);
++
++ // Only swap arm or thumb code.
++ if ((p->second == 'a') || (p->second == 't'))
++ {
++ Output_section* os = this->output_section(i);
++ gold_assert(os != NULL);
++ Arm_address section_address =
++ this->simple_input_section_output_address(i, os);
++ span_start = convert_to_section_size_type(p->first.second);
++ if (next != this->mapping_symbols_info_.end()
++ && next->first.first == i)
++ span_end =
++ convert_to_section_size_type(next->first.second);
++ else
++ span_end =
++ convert_to_section_size_type(shdr.get_sh_size());
++ unsigned char* section_view =
++ view + (section_address - view_address);
++ uint64_t section_size = this->section_size(i);
++
++ gold_assert(section_address >= view_address
++ && ((section_address + section_size)
++ <= (view_address + view_size)));
++
++ // Set Output view for swapping
++ unsigned char *oview = section_view + span_start;
++ unsigned int index = 0;
++ if (p->second == 'a')
++ {
++ while (index + 3 < (span_end - span_start))
++ {
++ typedef typename elfcpp::Swap<32, big_endian>
++ ::Valtype Valtype;
++ Valtype* wv =
++ reinterpret_cast<Valtype*>(oview+index);
++ uint32_t val = elfcpp::Swap<32, false>::readval(wv);
++ elfcpp::Swap<32, true>::writeval(wv, val);
++ index += 4;
++ }
++ }
++ else if (p->second == 't')
++ {
++ while (index + 1 < (span_end - span_start))
++ {
++ typedef typename elfcpp::Swap<16, big_endian>
++ ::Valtype Valtype;
++ Valtype* wv =
++ reinterpret_cast<Valtype*>(oview+index);
++ uint16_t val = elfcpp::Swap<16, false>::readval(wv);
++ elfcpp::Swap<16, true>::writeval(wv, val);
++ index += 2;
++ }
++ }
++ }
++ p = next;
++ }
++ }
+ }
+ }
+
+@@ -7785,7 +7892,18 @@ Output_data_plt_arm_standard<big_endian>
+ const size_t num_first_plt_words = (sizeof(first_plt_entry)
+ / sizeof(first_plt_entry[0]));
+ for (size_t i = 0; i < num_first_plt_words - 1; i++)
+- elfcpp::Swap<32, big_endian>::writeval(pov + i * 4, first_plt_entry[i]);
++ {
++ if (parameters->options().be8())
++ {
++ elfcpp::Swap<32, false>::writeval(pov + i * 4,
++ first_plt_entry[i]);
++ }
++ else
++ {
++ elfcpp::Swap<32, big_endian>::writeval(pov + i * 4,
++ first_plt_entry[i]);
++ }
++ }
+ // Last word in first PLT entry is &GOT[0] - .
+ elfcpp::Swap<32, big_endian>::writeval(pov + 16,
+ got_address - (plt_address + 16));
+@@ -7846,11 +7964,21 @@ Output_data_plt_arm_short<big_endian>::d
+ gold_error(_("PLT offset too large, try linking with --long-plt"));
+
+ uint32_t plt_insn0 = plt_entry[0] | ((offset >> 20) & 0xff);
+- elfcpp::Swap<32, big_endian>::writeval(pov, plt_insn0);
+ uint32_t plt_insn1 = plt_entry[1] | ((offset >> 12) & 0xff);
+- elfcpp::Swap<32, big_endian>::writeval(pov + 4, plt_insn1);
+ uint32_t plt_insn2 = plt_entry[2] | (offset & 0xfff);
+- elfcpp::Swap<32, big_endian>::writeval(pov + 8, plt_insn2);
++
++ if (parameters->options().be8())
++ {
++ elfcpp::Swap<32, false>::writeval(pov, plt_insn0);
++ elfcpp::Swap<32, false>::writeval(pov + 4, plt_insn1);
++ elfcpp::Swap<32, false>::writeval(pov + 8, plt_insn2);
++ }
++ else
++ {
++ elfcpp::Swap<32, big_endian>::writeval(pov, plt_insn0);
++ elfcpp::Swap<32, big_endian>::writeval(pov + 4, plt_insn1);
++ elfcpp::Swap<32, big_endian>::writeval(pov + 8, plt_insn2);
++ }
+ }
+
+ // This class generates long (16-byte) entries, for arbitrary displacements.
+@@ -7906,13 +8034,24 @@ Output_data_plt_arm_long<big_endian>::do
+ - (plt_address + plt_offset + 8));
+
+ uint32_t plt_insn0 = plt_entry[0] | (offset >> 28);
+- elfcpp::Swap<32, big_endian>::writeval(pov, plt_insn0);
+ uint32_t plt_insn1 = plt_entry[1] | ((offset >> 20) & 0xff);
+- elfcpp::Swap<32, big_endian>::writeval(pov + 4, plt_insn1);
+ uint32_t plt_insn2 = plt_entry[2] | ((offset >> 12) & 0xff);
+- elfcpp::Swap<32, big_endian>::writeval(pov + 8, plt_insn2);
+ uint32_t plt_insn3 = plt_entry[3] | (offset & 0xfff);
+- elfcpp::Swap<32, big_endian>::writeval(pov + 12, plt_insn3);
++
++ if (parameters->options().be8())
++ {
++ elfcpp::Swap<32, false>::writeval(pov, plt_insn0);
++ elfcpp::Swap<32, false>::writeval(pov + 4, plt_insn1);
++ elfcpp::Swap<32, false>::writeval(pov + 8, plt_insn2);
++ elfcpp::Swap<32, false>::writeval(pov + 12, plt_insn3);
++ }
++ else
++ {
++ elfcpp::Swap<32, big_endian>::writeval(pov, plt_insn0);
++ elfcpp::Swap<32, big_endian>::writeval(pov + 4, plt_insn1);
++ elfcpp::Swap<32, big_endian>::writeval(pov + 8, plt_insn2);
++ elfcpp::Swap<32, big_endian>::writeval(pov + 12, plt_insn3);
++ }
+ }
+
+ // Write out the PLT. This uses the hand-coded instructions above,
+@@ -8414,7 +8553,7 @@ Target_arm<big_endian>::Scan::local(Symb
+ if (is_discarded)
+ return;
+
+- r_type = get_real_reloc_type(r_type);
++ r_type = target->get_real_reloc_type(r_type);
+
+ // A local STT_GNU_IFUNC symbol may require a PLT entry.
+ bool is_ifunc = lsym.get_st_type() == elfcpp::STT_GNU_IFUNC;
+@@ -8820,7 +8959,7 @@ Target_arm<big_endian>::Scan::global(Sym
+ && this->reloc_needs_plt_for_ifunc(object, r_type))
+ target->make_plt_entry(symtab, layout, gsym);
+
+- r_type = get_real_reloc_type(r_type);
++ r_type = target->get_real_reloc_type(r_type);
+ switch (r_type)
+ {
+ case elfcpp::R_ARM_NONE:
+@@ -9446,7 +9585,7 @@ Target_arm<big_endian>::Relocate::reloca
+
+ const elfcpp::Rel<32, big_endian> rel(preloc);
+ unsigned int r_type = elfcpp::elf_r_type<32>(rel.get_r_info());
+- r_type = get_real_reloc_type(r_type);
++ r_type = target->get_real_reloc_type(r_type);
+ const Arm_reloc_property* reloc_property =
+ arm_reloc_property_table->get_implemented_static_reloc_property(r_type);
+ if (reloc_property == NULL)
+@@ -10156,7 +10295,9 @@ Target_arm<big_endian>::Classify_reloc::
+ unsigned int r_type,
+ Relobj* object)
+ {
+- r_type = get_real_reloc_type(r_type);
++ Target_arm<big_endian>* arm_target =
++ Target_arm<big_endian>::default_target();
++ r_type = arm_target->get_real_reloc_type(r_type);
+ const Arm_reloc_property* arp =
+ arm_reloc_property_table->get_implemented_static_reloc_property(r_type);
+ if (arp != NULL)
+@@ -10580,17 +10721,15 @@ Target_arm<big_endian>::do_dynsym_value(
+ //
+ template<bool big_endian>
+ unsigned int
+-Target_arm<big_endian>::get_real_reloc_type(unsigned int r_type)
++Target_arm<big_endian>::get_real_reloc_type(unsigned int r_type) const
+ {
+ switch (r_type)
+ {
+ case elfcpp::R_ARM_TARGET1:
+- // This is either R_ARM_ABS32 or R_ARM_REL32;
+- return elfcpp::R_ARM_ABS32;
++ return this->target1_reloc_;
+
+ case elfcpp::R_ARM_TARGET2:
+- // This can be any reloc type but usually is R_ARM_GOT_PREL
+- return elfcpp::R_ARM_GOT_PREL;
++ return this->target2_reloc_;
+
+ default:
+ return r_type;
+@@ -10683,7 +10822,14 @@ Target_arm<big_endian>::do_adjust_elf_he
+ e_ident[elfcpp::EI_OSABI] = 0;
+ e_ident[elfcpp::EI_ABIVERSION] = 0;
+
+- // FIXME: Do EF_ARM_BE8 adjustment.
++ // Do EF_ARM_BE8 adjustment.
++ if (parameters->options().be8() && !big_endian)
++ gold_error("BE8 images only valid in big-endian mode.");
++ if (parameters->options().be8())
++ {
++ flags |= elfcpp::EF_ARM_BE8;
++ this->set_processor_specific_flags(flags);
++ }
+
+ // If we're working in EABI_VER5, set the hard/soft float ABI flags
+ // as appropriate.
+diff -rup ../binutils-2.27/gold/configure gold/configure
+--- ../binutils-2.27/gold/configure 2016-09-26 11:22:19.027813254 +0100
++++ gold/configure 2016-11-03 14:38:22.000000000 +0000
+@@ -609,6 +609,7 @@ GOLD_LDFLAGS
+ WARN_CXXFLAGS
+ WARN_WRITE_STRINGS
+ NO_WERROR
++WARN_CFLAGS_FOR_BUILD
+ WARN_CFLAGS
+ IFUNC_STATIC_FALSE
+ IFUNC_STATIC_TRUE
+@@ -6723,8 +6724,12 @@ fi
+ # Set the 'development' global.
+ . $srcdir/../bfd/development.sh
+
++# Set acp_cpp_for_build variable
++ac_cpp_for_build="$CC_FOR_BUILD -E $CPPFLAGS_FOR_BUILD"
++
+ # Default set of GCC warnings to enable.
+ GCC_WARN_CFLAGS="-W -Wall -Wstrict-prototypes -Wmissing-prototypes"
++GCC_WARN_CFLAGS_FOR_BUILD="-W -Wall -Wstrict-prototypes -Wmissing-prototypes"
+
+ # Add -Wshadow if the compiler is a sufficiently recent version of GCC.
+ cat confdefs.h - <<_ACEOF >conftest.$ac_ext
+@@ -6769,6 +6774,36 @@ fi
+ rm -f conftest*
+
+
++# Verify CC_FOR_BUILD to be compatible with waring flags
++
++# Add -Wshadow if the compiler is a sufficiently recent version of GCC.
++cat confdefs.h - <<_ACEOF >conftest.$ac_ext
++/* end confdefs.h. */
++__GNUC__
++_ACEOF
++if (eval "$ac_cpp_for_build conftest.$ac_ext") 2>&5 |
++ $EGREP "^[0-3]$" >/dev/null 2>&1; then :
++
++else
++ GCC_WARN_CFLAGS_FOR_BUILD="$GCC_WARN_CFLAGS_FOR_BUILD -Wshadow"
++fi
++rm -f conftest*
++
++
++# Add -Wstack-usage if the compiler is a sufficiently recent version of GCC.
++cat confdefs.h - <<_ACEOF >conftest.$ac_ext
++/* end confdefs.h. */
++__GNUC__
++_ACEOF
++if (eval "$ac_cpp_for_build conftest.$ac_ext") 2>&5 |
++ $EGREP "^[0-4]$" >/dev/null 2>&1; then :
++
++else
++ GCC_WARN_CFLAGS_FOR_BUILD="$GCC_WARN_CFLAGS_FOR_BUILD -Wstack-usage=262144"
++fi
++rm -f conftest*
++
++
+ # Check whether --enable-werror was given.
+ if test "${enable_werror+set}" = set; then :
+ enableval=$enable_werror; case "${enableval}" in
+@@ -6784,6 +6819,7 @@ case "${host}" in
+ *-*-mingw32*)
+ if test "${GCC}" = yes -a -z "${ERROR_ON_WARNING}" ; then
+ GCC_WARN_CFLAGS="$GCC_WARN_CFLAGS -Wno-format"
++ GCC_WARN_CFLAGS_FOR_BUILD="$GCC_WARN_CFLAGS_FOR_BUILD -Wno-format"
+ fi
+ ;;
+ *) ;;
+@@ -6797,25 +6833,32 @@ fi
+ NO_WERROR=
+ if test "${ERROR_ON_WARNING}" = yes ; then
+ GCC_WARN_CFLAGS="$GCC_WARN_CFLAGS -Werror"
++ GCC_WARN_CFLAGS_FOR_BUILD="$GCC_WARN_CFLAGS_FOR_BUILD -Werror"
+ NO_WERROR="-Wno-error"
+ fi
+
+ if test "${GCC}" = yes ; then
+ WARN_CFLAGS="${GCC_WARN_CFLAGS}"
++ WARN_CFLAGS_FOR_BUILD="${GCC_WARN_CFLAGS_FOR_BUILD}"
+ fi
+
+ # Check whether --enable-build-warnings was given.
+ if test "${enable_build_warnings+set}" = set; then :
+ enableval=$enable_build_warnings; case "${enableval}" in
+- yes) WARN_CFLAGS="${GCC_WARN_CFLAGS}";;
++ yes) WARN_CFLAGS="${GCC_WARN_CFLAGS}"
++ WARN_CFLAGS_FOR_BUILD="${GCC_WARN_CFLAGS_FOR_BUILD}";;
+ no) if test "${GCC}" = yes ; then
+ WARN_CFLAGS="-w"
++ WARN_CFLAGS_FOR_BUILD="-w"
+ fi;;
+ ,*) t=`echo "${enableval}" | sed -e "s/,/ /g"`
+- WARN_CFLAGS="${GCC_WARN_CFLAGS} ${t}";;
++ WARN_CFLAGS="${GCC_WARN_CFLAGS} ${t}"
++ WARN_CFLAGS_FOR_BUILD="${GCC_WARN_CFLAGS_FOR_BUILD} ${t}";;
+ *,) t=`echo "${enableval}" | sed -e "s/,/ /g"`
+- WARN_CFLAGS="${t} ${GCC_WARN_CFLAGS}";;
+- *) WARN_CFLAGS=`echo "${enableval}" | sed -e "s/,/ /g"`;;
++ WARN_CFLAGS="${t} ${GCC_WARN_CFLAGS}"
++ WARN_CFLAGS_FOR_BUILD="${t} ${GCC_WARN_CFLAGS_FOR_BUILD}";;
++ *) WARN_CFLAGS=`echo "${enableval}" | sed -e "s/,/ /g"`
++ WARN_CFLAGS_FOR_BUILD=`echo "${enableval}" | sed -e "s/,/ /g"`;;
+ esac
+ fi
+
+diff -rup ../binutils-2.27/gold/debug.h gold/debug.h
+--- ../binutils-2.27/gold/debug.h 2016-08-03 08:36:53.000000000 +0100
++++ gold/debug.h 2016-11-03 15:05:05.000000000 +0000
+@@ -39,10 +39,11 @@ const int DEBUG_FILES = 0x4;
+ const int DEBUG_RELAXATION = 0x8;
+ const int DEBUG_INCREMENTAL = 0x10;
+ const int DEBUG_LOCATION = 0x20;
++const int DEBUG_TARGET = 0x40;
+
+ const int DEBUG_ALL = (DEBUG_TASK | DEBUG_SCRIPT | DEBUG_FILES
+ | DEBUG_RELAXATION | DEBUG_INCREMENTAL
+- | DEBUG_LOCATION);
++ | DEBUG_LOCATION | DEBUG_TARGET);
+
+ // Convert a debug string to the appropriate enum.
+ inline int
+@@ -57,6 +58,7 @@ debug_string_to_enum(const char* arg)
+ { "relaxation", DEBUG_RELAXATION },
+ { "incremental", DEBUG_INCREMENTAL },
+ { "location", DEBUG_LOCATION },
++ { "target", DEBUG_TARGET },
+ { "all", DEBUG_ALL }
+ };
+
+@@ -70,11 +72,11 @@ debug_string_to_enum(const char* arg)
+ // Print a debug message if TYPE is enabled. This is a macro so that
+ // we only evaluate the arguments if necessary.
+
+-#define gold_debug(TYPE, FORMAT, ...) \
++#define gold_debug(TYPE, ...) \
+ do \
+ { \
+ if (is_debugging_enabled(TYPE)) \
+- parameters->errors()->debug(FORMAT, __VA_ARGS__); \
++ parameters->errors()->debug(__VA_ARGS__); \
+ } \
+ while (0)
+
+diff -rup ../binutils-2.27/gold/i386.cc gold/i386.cc
+--- ../binutils-2.27/gold/i386.cc 2016-08-03 08:36:53.000000000 +0100
++++ gold/i386.cc 2016-11-03 15:05:40.000000000 +0000
+@@ -2794,8 +2794,11 @@ Target_i386::Relocate::relocate(const Re
+ && r_type != elfcpp::R_386_PC32)
+ || gsym == NULL
+ || strcmp(gsym->name(), "___tls_get_addr") != 0)
+- gold_error_at_location(relinfo, relnum, rel.get_r_offset(),
+- _("missing expected TLS relocation"));
++ {
++ gold_error_at_location(relinfo, relnum, rel.get_r_offset(),
++ _("missing expected TLS relocation"));
++ this->skip_call_tls_get_addr_ = false;
++ }
+ else
+ {
+ this->skip_call_tls_get_addr_ = false;
+diff -rup ../binutils-2.27/gold/icf.cc gold/icf.cc
+--- ../binutils-2.27/gold/icf.cc 2016-08-03 08:36:53.000000000 +0100
++++ gold/icf.cc 2016-11-03 15:05:40.000000000 +0000
+@@ -590,6 +590,7 @@ match_sections(unsigned int iteration_nu
+ std::vector<unsigned int>* num_tracked_relocs,
+ std::vector<unsigned int>* kept_section_id,
+ const std::vector<Section_id>& id_section,
++ const std::vector<uint64_t>& section_addraligns,
+ std::vector<bool>* is_secn_or_group_unique,
+ std::vector<std::string>* section_contents)
+ {
+@@ -630,13 +631,7 @@ match_sections(unsigned int iteration_nu
+ {
+ if ((*kept_section_id)[i] != i)
+ {
+- // This section is already folded into something. See
+- // if it should point to a different kept section.
+- unsigned int kept_section = (*kept_section_id)[i];
+- if (kept_section != (*kept_section_id)[kept_section])
+- {
+- (*kept_section_id)[i] = (*kept_section_id)[kept_section];
+- }
++ // This section is already folded into something.
+ continue;
+ }
+ this_secn_contents = get_section_contents(false, secn, i, NULL,
+@@ -671,7 +666,25 @@ match_sections(unsigned int iteration_nu
+ this_secn_contents.c_str(),
+ this_secn_contents.length()) != 0)
+ continue;
+- (*kept_section_id)[i] = kept_section;
++
++ // Check section alignment here.
++ // The section with the larger alignment requirement
++ // should be kept. We assume alignment can only be
++ // zero or postive integral powers of two.
++ uint64_t align_i = section_addraligns[i];
++ uint64_t align_kept = section_addraligns[kept_section];
++ if (align_i <= align_kept)
++ {
++ (*kept_section_id)[i] = kept_section;
++ }
++ else
++ {
++ (*kept_section_id)[kept_section] = i;
++ it->second = i;
++ full_section_contents[kept_section].swap(
++ full_section_contents[i]);
++ }
++
+ converged = false;
+ break;
+ }
+@@ -688,6 +701,26 @@ match_sections(unsigned int iteration_nu
+ (*is_secn_or_group_unique)[i] = true;
+ }
+
++ // If a section was folded into another section that was later folded
++ // again then the former has to be updated.
++ for (unsigned int i = 0; i < id_section.size(); i++)
++ {
++ // Find the end of the folding chain
++ unsigned int kept = i;
++ while ((*kept_section_id)[kept] != kept)
++ {
++ kept = (*kept_section_id)[kept];
++ }
++ // Update every element of the chain
++ unsigned int current = i;
++ while ((*kept_section_id)[current] != kept)
++ {
++ unsigned int next = (*kept_section_id)[current];
++ (*kept_section_id)[current] = kept;
++ current = next;
++ }
++ }
++
+ return converged;
+ }
+
+@@ -719,6 +752,7 @@ Icf::find_identical_sections(const Input
+ {
+ unsigned int section_num = 0;
+ std::vector<unsigned int> num_tracked_relocs;
++ std::vector<uint64_t> section_addraligns;
+ std::vector<bool> is_secn_or_group_unique;
+ std::vector<std::string> section_contents;
+ const Target& target = parameters->target();
+@@ -759,6 +793,7 @@ Icf::find_identical_sections(const Input
+ this->section_id_[Section_id(*p, i)] = section_num;
+ this->kept_section_id_.push_back(section_num);
+ num_tracked_relocs.push_back(0);
++ section_addraligns.push_back((*p)->section_addralign(i));
+ is_secn_or_group_unique.push_back(false);
+ section_contents.push_back("");
+ section_num++;
+@@ -779,8 +814,8 @@ Icf::find_identical_sections(const Input
+ num_iterations++;
+ converged = match_sections(num_iterations, symtab,
+ &num_tracked_relocs, &this->kept_section_id_,
+- this->id_section_, &is_secn_or_group_unique,
+- §ion_contents);
++ this->id_section_, section_addraligns,
++ &is_secn_or_group_unique, §ion_contents);
+ }
+
+ if (parameters->options().print_icf_sections())
+diff -rup ../binutils-2.27/gold/layout.cc gold/layout.cc
+--- ../binutils-2.27/gold/layout.cc 2016-08-03 08:36:53.000000000 +0100
++++ gold/layout.cc 2016-11-03 15:05:42.000000000 +0000
+@@ -2135,7 +2135,7 @@ void
+ Layout::create_notes()
+ {
+ this->create_gold_note();
+- this->create_executable_stack_info();
++ this->create_stack_segment();
+ this->create_build_id();
+ }
+
+@@ -2785,7 +2785,7 @@ Layout::finalize(const Input_objects* in
+ if (load_seg != NULL)
+ ehdr_start->set_output_segment(load_seg, Symbol::SEGMENT_START);
+ else
+- ehdr_start->set_undefined();
++ ehdr_start->set_undefined();
+ }
+
+ // Set the file offsets of all the non-data sections we've seen so
+@@ -2985,25 +2985,29 @@ Layout::create_gold_note()
+ // executable. Otherwise, if at least one input file a
+ // .note.GNU-stack section, and some input file has no .note.GNU-stack
+ // section, we use the target default for whether the stack should be
+-// executable. Otherwise, we don't generate a stack note. When
+-// generating a object file, we create a .note.GNU-stack section with
+-// the appropriate marking. When generating an executable or shared
+-// library, we create a PT_GNU_STACK segment.
++// executable. If -z stack-size was used to set a p_memsz value for
++// PT_GNU_STACK, we generate the segment regardless. Otherwise, we
++// don't generate a stack note. When generating a object file, we
++// create a .note.GNU-stack section with the appropriate marking.
++// When generating an executable or shared library, we create a
++// PT_GNU_STACK segment.
+
+ void
+-Layout::create_executable_stack_info()
++Layout::create_stack_segment()
+ {
+ bool is_stack_executable;
+ if (parameters->options().is_execstack_set())
+ {
+ is_stack_executable = parameters->options().is_stack_executable();
+ if (!is_stack_executable
+- && this->input_requires_executable_stack_
+- && parameters->options().warn_execstack())
++ && this->input_requires_executable_stack_
++ && parameters->options().warn_execstack())
+ gold_warning(_("one or more inputs require executable stack, "
+- "but -z noexecstack was given"));
++ "but -z noexecstack was given"));
+ }
+- else if (!this->input_with_gnu_stack_note_)
++ else if (!this->input_with_gnu_stack_note_
++ && (!parameters->options().user_set_stack_size()
++ || parameters->options().relocatable()))
+ return;
+ else
+ {
+@@ -3032,7 +3036,12 @@ Layout::create_executable_stack_info()
+ int flags = elfcpp::PF_R | elfcpp::PF_W;
+ if (is_stack_executable)
+ flags |= elfcpp::PF_X;
+- this->make_output_segment(elfcpp::PT_GNU_STACK, flags);
++ Output_segment* seg =
++ this->make_output_segment(elfcpp::PT_GNU_STACK, flags);
++ seg->set_size(parameters->options().stack_size());
++ // BFD lets targets override this default alignment, but the only
++ // targets that do so are ones that Gold does not support so far.
++ seg->set_minimum_p_align(16);
+ }
+ }
+
+@@ -3718,7 +3727,9 @@ Layout::set_segment_offsets(const Target
+ p != this->segment_list_.end();
+ ++p)
+ {
+- if ((*p)->type() != elfcpp::PT_LOAD)
++ // PT_GNU_STACK was set up correctly when it was created.
++ if ((*p)->type() != elfcpp::PT_LOAD
++ && (*p)->type() != elfcpp::PT_GNU_STACK)
+ (*p)->set_offset((*p)->type() == elfcpp::PT_GNU_RELRO
+ ? increase_relro
+ : 0);
+diff -rup ../binutils-2.27/gold/layout.h gold/layout.h
+--- ../binutils-2.27/gold/layout.h 2016-08-03 08:36:53.000000000 +0100
++++ gold/layout.h 2016-11-03 15:05:12.000000000 +0000
+@@ -1037,9 +1037,9 @@ class Layout
+ void
+ create_gold_note();
+
+- // Record whether the stack must be executable.
++ // Record whether the stack must be executable, and a user-supplied size.
+ void
+- create_executable_stack_info();
++ create_stack_segment();
+
+ // Create a build ID note if needed.
+ void
+diff -rup ../binutils-2.27/gold/Makefile.in gold/Makefile.in
+--- ../binutils-2.27/gold/Makefile.in 2016-08-03 08:36:53.000000000 +0100
++++ gold/Makefile.in 2016-11-03 14:38:22.000000000 +0000
+@@ -87,8 +87,8 @@ subdir = .
+ DIST_COMMON = NEWS README ChangeLog $(srcdir)/Makefile.in \
+ $(srcdir)/Makefile.am $(top_srcdir)/configure \
+ $(am__configure_deps) $(srcdir)/config.in \
+- $(srcdir)/../mkinstalldirs $(top_srcdir)/po/Make-in \
+- ftruncate.c pread.c mremap.c ffsll.c yyscript.h yyscript.c \
++ $(srcdir)/../mkinstalldirs $(top_srcdir)/po/Make-in ffsll.c \
++ mremap.c ftruncate.c pread.c yyscript.h yyscript.c \
+ $(srcdir)/../depcomp $(srcdir)/../ylwrap
+ ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
+ am__aclocal_m4_deps = $(top_srcdir)/../config/depstand.m4 \
+@@ -409,6 +409,7 @@ TARGETOBJS = @TARGETOBJS@
+ USE_NLS = @USE_NLS@
+ VERSION = @VERSION@
+ WARN_CFLAGS = @WARN_CFLAGS@
++WARN_CFLAGS_FOR_BUILD = @WARN_CFLAGS_FOR_BUILD@
+ WARN_CXXFLAGS = @WARN_CXXFLAGS@
+ WARN_WRITE_STRINGS = @WARN_WRITE_STRINGS@
+ XGETTEXT = @XGETTEXT@
+diff -rup ../binutils-2.27/gold/options.h gold/options.h
+--- ../binutils-2.27/gold/options.h 2016-08-03 08:36:53.000000000 +0100
++++ gold/options.h 2016-11-03 15:05:13.000000000 +0000
+@@ -647,7 +647,7 @@ class General_options
+ DEFINE_bool(apply_dynamic_relocs, options::TWO_DASHES, '\0', true,
+ N_("Apply link-time values for dynamic relocations (default)"),
+ N_("(aarch64 only) Do not apply link-time values "
+- "for dynamic relocations"));
++ "for dynamic relocations"));
+
+ DEFINE_bool(as_needed, options::TWO_DASHES, '\0', false,
+ N_("Only set DT_NEEDED for shared libraries if used"),
+@@ -674,6 +674,9 @@ class General_options
+ DEFINE_bool_alias(dn, Bdynamic, options::ONE_DASH, '\0',
+ N_("alias for -Bstatic"), NULL, true);
+
++ DEFINE_bool(be8,options::TWO_DASHES, '\0', false,
++ N_("Output BE8 format image"), NULL);
++
+ DEFINE_bool(Bgroup, options::ONE_DASH, '\0', false,
+ N_("Use group name lookup rules for shared library"), NULL);
+
+@@ -1152,6 +1155,17 @@ class General_options
+ DEFINE_string(sysroot, options::TWO_DASHES, '\0', "",
+ N_("Set target system root directory"), N_("DIR"));
+
++ DEFINE_bool(target1_rel, options::TWO_DASHES, '\0', false,
++ N_("(ARM only) Force R_ARM_TARGET1 type to R_ARM_REL32"),
++ NULL);
++ DEFINE_bool(target1_abs, options::TWO_DASHES, '\0', false,
++ N_("(ARM only) Force R_ARM_TARGET1 type to R_ARM_ABS32"),
++ NULL);
++ DEFINE_enum(target2, options::TWO_DASHES, '\0', NULL,
++ N_("(ARM only) Set R_ARM_TARGET2 relocation type"),
++ N_("[rel, abs, got-rel"),
++ {"rel", "abs", "got-rel"});
++
+ DEFINE_bool(trace, options::TWO_DASHES, 't', false,
+ N_("Print the name of each input file"), NULL);
+
+@@ -1293,7 +1307,7 @@ class General_options
+ N_("Mark output as requiring executable stack"), NULL);
+ DEFINE_bool(global, options::DASH_Z, '\0', false,
+ N_("Make symbols in DSO available for subsequently loaded "
+- "objects"), NULL);
++ "objects"), NULL);
+ DEFINE_bool(initfirst, options::DASH_Z, '\0', false,
+ N_("Mark DSO to be initialized first at runtime"),
+ NULL);
+@@ -1339,6 +1353,8 @@ class General_options
+ DEFINE_bool(relro, options::DASH_Z, '\0', DEFAULT_LD_Z_RELRO,
+ N_("Where possible mark variables read-only after relocation"),
+ N_("Don't mark variables read-only after relocation"));
++ DEFINE_uint64(stack_size, options::DASH_Z, '\0', 0,
++ N_("Set PT_GNU_STACK segment p_memsz to SIZE"), N_("SIZE"));
+ DEFINE_bool(text, options::DASH_Z, '\0', false,
+ N_("Do not permit relocations in read-only segments"),
+ N_("Permit relocations in read-only segments (default)"));
+diff -rup ../binutils-2.27/gold/output.cc gold/output.cc
+--- ../binutils-2.27/gold/output.cc 2016-08-03 08:36:53.000000000 +0100
++++ gold/output.cc 2016-11-03 15:05:44.000000000 +0000
+@@ -4398,7 +4398,7 @@ Output_segment::set_section_addresses(co
+ this->offset_ = orig_off;
+
+ off_t off = 0;
+- uint64_t ret;
++ uint64_t ret = 0;
+ for (int i = 0; i < static_cast<int>(ORDER_MAX); ++i)
+ {
+ if (i == static_cast<int>(ORDER_RELRO_LAST))
+diff -rup ../binutils-2.27/gold/output.h gold/output.h
+--- ../binutils-2.27/gold/output.h 2016-08-03 08:36:53.000000000 +0100
++++ gold/output.h 2016-11-03 15:05:14.000000000 +0000
+@@ -2499,7 +2499,7 @@ class Output_data_got : public Output_da
+ // entry.
+ bool
+ add_local(Relobj* object, unsigned int sym_index, unsigned int got_type,
+- uint64_t addend);
++ uint64_t addend);
+
+ // Like add_local, but use the PLT offset of the local symbol if it
+ // has one.
+@@ -2643,7 +2643,7 @@ class Output_data_got : public Output_da
+
+ // Create a local symbol entry plus addend.
+ Got_entry(Relobj* object, unsigned int local_sym_index,
+- bool use_plt_or_tls_offset, uint64_t addend)
++ bool use_plt_or_tls_offset, uint64_t addend)
+ : local_sym_index_(local_sym_index),
+ use_plt_or_tls_offset_(use_plt_or_tls_offset), addend_(addend)
+ {
+@@ -4796,6 +4796,13 @@ class Output_segment
+ this->min_p_align_ = align;
+ }
+
++ // Set the memory size of this segment.
++ void
++ set_size(uint64_t size)
++ {
++ this->memsz_ = size;
++ }
++
+ // Set the offset of this segment based on the section. This should
+ // only be called for a non-PT_LOAD segment.
+ void
+diff -rup ../binutils-2.27/gold/powerpc.cc gold/powerpc.cc
+--- ../binutils-2.27/gold/powerpc.cc 2016-09-26 11:22:18.717811369 +0100
++++ gold/powerpc.cc 2016-11-03 15:05:45.000000000 +0000
+@@ -2439,9 +2439,8 @@ class Stub_control
+ // the stubbed branches.
+ Stub_control(int32_t size, bool no_size_errors)
+ : state_(NO_GROUP), stub_group_size_(abs(size)),
+- stub14_group_size_(abs(size) >> 10),
+ stubs_always_before_branch_(size < 0),
+- suppress_size_errors_(no_size_errors),
++ suppress_size_errors_(no_size_errors), group_size_(0),
+ group_end_addr_(0), owner_(NULL), output_section_(NULL)
+ {
+ }
+@@ -2479,24 +2478,28 @@ class Stub_control
+
+ State state_;
+ uint32_t stub_group_size_;
+- uint32_t stub14_group_size_;
+ bool stubs_always_before_branch_;
+ bool suppress_size_errors_;
++ // Current max size of group. Starts at stub_group_size_ but is
++ // reduced to stub_group_size_/1024 on seeing a section with
++ // external conditional branches.
++ uint32_t group_size_;
+ uint64_t group_end_addr_;
++ // owner_ and output_section_ specify the section to which stubs are
++ // attached. The stubs are placed at the end of this section.
+ const Output_section::Input_section* owner_;
+ Output_section* output_section_;
+ };
+
+ // Return true iff input section can be handled by current stub
+-// group.
++// group. Sections are presented to this function in reverse order,
++// so the first section is the tail of the group.
+
+ bool
+ Stub_control::can_add_to_stub_group(Output_section* o,
+ const Output_section::Input_section* i,
+ bool has14)
+ {
+- uint32_t group_size
+- = has14 ? this->stub14_group_size_ : this->stub_group_size_;
+ bool whole_sec = o->order() == ORDER_INIT || o->order() == ORDER_FINI;
+ uint64_t this_size;
+ uint64_t start_addr = o->address();
+@@ -2510,46 +2513,90 @@ Stub_control::can_add_to_stub_group(Outp
+ start_addr += i->relobj()->output_section_offset(i->shndx());
+ this_size = i->data_size();
+ }
+- uint64_t end_addr = start_addr + this_size;
+- bool toobig = this_size > group_size;
+
+- if (toobig && !this->suppress_size_errors_)
++ uint32_t group_size = this->stub_group_size_;
++ if (has14)
++ this->group_size_ = group_size = group_size >> 10;
++
++ if (this_size > group_size && !this->suppress_size_errors_)
+ gold_warning(_("%s:%s exceeds group size"),
+ i->relobj()->name().c_str(),
+ i->relobj()->section_name(i->shndx()).c_str());
+
+- if (this->state_ != HAS_STUB_SECTION
+- && (!whole_sec || this->output_section_ != o)
+- && (this->state_ == NO_GROUP
+- || this->group_end_addr_ - end_addr < group_size))
+- {
+- this->owner_ = i;
+- this->output_section_ = o;
+- }
+-
+- if (this->state_ == NO_GROUP)
+- {
+- this->state_ = FINDING_STUB_SECTION;
+- this->group_end_addr_ = end_addr;
+- }
+- else if (this->group_end_addr_ - start_addr < group_size)
+- ;
+- // Adding this section would make the group larger than GROUP_SIZE.
+- else if (this->state_ == FINDING_STUB_SECTION
+- && !this->stubs_always_before_branch_
+- && !toobig)
+- {
+- // But wait, there's more! Input sections up to GROUP_SIZE
+- // bytes before the stub table can be handled by it too.
+- this->state_ = HAS_STUB_SECTION;
+- this->group_end_addr_ = end_addr;
++ gold_debug(DEBUG_TARGET, "maybe add%s %s:%s size=%#llx total=%#llx",
++ has14 ? " 14bit" : "",
++ i->relobj()->name().c_str(),
++ i->relobj()->section_name(i->shndx()).c_str(),
++ (long long) this_size,
++ (long long) this->group_end_addr_ - start_addr);
++
++ uint64_t end_addr = start_addr + this_size;
++ if (this->state_ == HAS_STUB_SECTION)
++ {
++ // Can we add this section, which is before the stubs, to the
++ // group?
++ if (this->group_end_addr_ - start_addr <= this->group_size_)
++ return true;
+ }
+ else
+ {
+- this->state_ = NO_GROUP;
+- return false;
++ // Stubs are added at the end of "owner_".
++ // The current section can always be the stub owner, except when
++ // whole_sec is true and the current section isn't the last of
++ // the pasted sections. (This restriction for the whole_sec
++ // case is just to simplify the corner case mentioned in
++ // group_sections.)
++ // Note that "owner_" itself is not necessarily part of the
++ // group of sections served by these stubs!
++ if (!whole_sec || this->output_section_ != o)
++ {
++ this->owner_ = i;
++ this->output_section_ = o;
++ }
++
++ if (this->state_ == FINDING_STUB_SECTION)
++ {
++ if (this->group_end_addr_ - start_addr <= this->group_size_)
++ return true;
++ // The group after the stubs has reached maximum size.
++ // Now see about adding sections before the stubs to the
++ // group. If the current section has a 14-bit branch and
++ // the group after the stubs exceeds group_size_ (because
++ // they didn't have 14-bit branches), don't add sections
++ // before the stubs: The size of stubs for such a large
++ // group may exceed the reach of a 14-bit branch.
++ if (!this->stubs_always_before_branch_
++ && this_size <= this->group_size_
++ && this->group_end_addr_ - end_addr <= this->group_size_)
++ {
++ gold_debug(DEBUG_TARGET, "adding before stubs");
++ this->state_ = HAS_STUB_SECTION;
++ this->group_end_addr_ = end_addr;
++ return true;
++ }
++ }
++ else if (this->state_ == NO_GROUP)
++ {
++ // Only here on very first use of Stub_control
++ this->state_ = FINDING_STUB_SECTION;
++ this->group_size_ = group_size;
++ this->group_end_addr_ = end_addr;
++ return true;
++ }
++ else
++ gold_unreachable();
+ }
+- return true;
++
++ gold_debug(DEBUG_TARGET, "nope, didn't fit\n");
++
++ // The section fails to fit in the current group. Set up a few
++ // things for the next group. owner_ and output_section_ will be
++ // set later after we've retrieved those values for the current
++ // group.
++ this->state_ = FINDING_STUB_SECTION;
++ this->group_size_ = group_size;
++ this->group_end_addr_ = end_addr;
++ return false;
+ }
+
+ // Look over all the input sections, deciding where to place stubs.
+@@ -2887,7 +2934,7 @@ Target_powerpc<size, big_endian>::do_rel
+ }
+ this->stub_tables_.clear();
+ this->stub_group_size_ = this->stub_group_size_ / 4 * 3;
+- gold_info(_("%s: stub group size is too large; retrying with %d"),
++ gold_info(_("%s: stub group size is too large; retrying with %#x"),
+ program_name, this->stub_group_size_);
+ this->group_sections(layout, task, true);
+ }
+@@ -2982,7 +3029,13 @@ Target_powerpc<size, big_endian>::do_rel
+ Stub_table<size, big_endian>* stub_table
+ = static_cast<Stub_table<size, big_endian>*>(
+ i->relaxed_input_section());
+- off += stub_table->set_address_and_size(os, off);
++ Address stub_table_size = stub_table->set_address_and_size(os, off);
++ off += stub_table_size;
++ // After a few iterations, set current stub table size
++ // as min size threshold, so later stub tables can only
++ // grow in size.
++ if (pass >= 4)
++ stub_table->set_min_size_threshold(stub_table_size);
+ }
+ else
+ off += i->data_size();
+@@ -3634,8 +3687,8 @@ class Stub_table : public Output_relaxed
+ targ_(targ), plt_call_stubs_(), long_branch_stubs_(),
+ orig_data_size_(owner->current_data_size()),
+ plt_size_(0), last_plt_size_(0),
+- branch_size_(0), last_branch_size_(0), eh_frame_added_(false),
+- need_save_res_(false)
++ branch_size_(0), last_branch_size_(0), min_size_threshold_(0),
++ eh_frame_added_(false), need_save_res_(false)
+ {
+ this->set_output_section(output_section);
+
+@@ -3726,6 +3779,11 @@ class Stub_table : public Output_relaxed
+ off = align_address(off, this->stub_align());
+ // Include original section size and alignment padding in size
+ my_size += off - start_off;
++ // Ensure new size is always larger than min size
++ // threshold. Alignment requirement is included in "my_size", so
++ // increase "my_size" does not invalidate alignment.
++ if (my_size < this->min_size_threshold_)
++ my_size = this->min_size_threshold_;
+ this->reset_address_and_file_offset();
+ this->set_current_data_size(my_size);
+ this->set_address_and_file_offset(os->address() + start_off,
+@@ -3751,6 +3809,9 @@ class Stub_table : public Output_relaxed
+ plt_size() const
+ { return this->plt_size_; }
+
++ void set_min_size_threshold(Address min_size)
++ { this->min_size_threshold_ = min_size; }
++
+ bool
+ size_update()
+ {
+@@ -4015,6 +4076,13 @@ class Stub_table : public Output_relaxed
+ section_size_type orig_data_size_;
+ // size of stubs
+ section_size_type plt_size_, last_plt_size_, branch_size_, last_branch_size_;
++ // Some rare cases cause (PR/20529) fluctuation in stub table
++ // size, which leads to an endless relax loop. This is to be fixed
++ // by, after the first few iterations, allowing only increase of
++ // stub table size. This variable sets the minimal possible size of
++ // a stub table, it is zero for the first few iterations, then
++ // increases monotonically.
++ Address min_size_threshold_;
+ // Whether .eh_frame info has been created for this stub section.
+ bool eh_frame_added_;
+ // Set if this stub group needs a copy of out-of-line register
+@@ -6024,7 +6092,7 @@ Target_powerpc<size, big_endian>::Scan::
+ ppc_object->set_opd_discard(reloc.get_r_offset());
+ break;
+ }
+- // Fall thru
++ // Fall through.
+ case elfcpp::R_PPC64_UADDR64:
+ case elfcpp::R_POWERPC_ADDR32:
+ case elfcpp::R_POWERPC_UADDR32:
+@@ -6131,7 +6199,7 @@ Target_powerpc<size, big_endian>::Scan::
+ || gsym->is_preemptible())))
+ target->make_plt_entry(symtab, layout, gsym);
+ }
+- // Fall thru
++ // Fall through.
+
+ case elfcpp::R_PPC64_REL64:
+ case elfcpp::R_POWERPC_REL32:
+@@ -7521,6 +7589,7 @@ Target_powerpc<size, big_endian>::Reloca
+ if (size != 64)
+ // R_PPC_TLSGD, R_PPC_TLSLD, R_PPC_EMB_RELST_LO, R_PPC_EMB_RELST_HI
+ break;
++ // Fall through.
+ case elfcpp::R_POWERPC_TPREL16:
+ case elfcpp::R_POWERPC_TPREL16_LO:
+ case elfcpp::R_POWERPC_TPREL16_HI:
+@@ -7544,6 +7613,7 @@ Target_powerpc<size, big_endian>::Reloca
+ // R_PPC_EMB_NADDR32, R_PPC_EMB_NADDR16, R_PPC_EMB_NADDR16_LO
+ // R_PPC_EMB_NADDR16_HI, R_PPC_EMB_NADDR16_HA, R_PPC_EMB_SDAI16
+ break;
++ // Fall through.
+ case elfcpp::R_POWERPC_DTPREL16:
+ case elfcpp::R_POWERPC_DTPREL16_LO:
+ case elfcpp::R_POWERPC_DTPREL16_HI:
+@@ -7572,6 +7642,7 @@ Target_powerpc<size, big_endian>::Reloca
+ case elfcpp::R_POWERPC_ADDR14_BRTAKEN:
+ case elfcpp::R_POWERPC_REL14_BRTAKEN:
+ branch_bit = 1 << 21;
++ // Fall through.
+ case elfcpp::R_POWERPC_ADDR14_BRNTAKEN:
+ case elfcpp::R_POWERPC_REL14_BRNTAKEN:
+ {
+@@ -7936,6 +8007,7 @@ Target_powerpc<size, big_endian>::Reloca
+ maybe_dq_reloc = true;
+ break;
+ }
++ // Fall through.
+ case elfcpp::R_POWERPC_ADDR16:
+ case elfcpp::R_POWERPC_REL16:
+ case elfcpp::R_PPC64_TOC16:
+@@ -7970,6 +8042,7 @@ Target_powerpc<size, big_endian>::Reloca
+ if (size == 32)
+ // R_PPC_EMB_MRKREF, R_PPC_EMB_RELST_LO, R_PPC_EMB_RELST_HA
+ goto unsupp;
++ // Fall through.
+ case elfcpp::R_POWERPC_ADDR16_HI:
+ case elfcpp::R_POWERPC_REL16_HI:
+ case elfcpp::R_PPC64_TOC16_HI:
+@@ -7990,6 +8063,7 @@ Target_powerpc<size, big_endian>::Reloca
+ if (size == 32)
+ // R_PPC_EMB_RELSEC16, R_PPC_EMB_RELST_HI, R_PPC_EMB_BIT_FLD
+ goto unsupp;
++ // Fall through.
+ case elfcpp::R_POWERPC_ADDR16_HA:
+ case elfcpp::R_POWERPC_REL16_HA:
+ case elfcpp::R_PPC64_TOC16_HA:
+@@ -8012,6 +8086,7 @@ Target_powerpc<size, big_endian>::Reloca
+ if (size == 32)
+ // R_PPC_EMB_NADDR16_LO
+ goto unsupp;
++ // Fall through.
+ case elfcpp::R_PPC64_ADDR16_HIGHER:
+ case elfcpp::R_PPC64_TPREL16_HIGHER:
+ Reloc::addr16_hi2(view, value);
+@@ -8021,6 +8096,7 @@ Target_powerpc<size, big_endian>::Reloca
+ if (size == 32)
+ // R_PPC_EMB_NADDR16_HI
+ goto unsupp;
++ // Fall through.
+ case elfcpp::R_PPC64_ADDR16_HIGHERA:
+ case elfcpp::R_PPC64_TPREL16_HIGHERA:
+ Reloc::addr16_ha2(view, value);
+@@ -8030,6 +8106,7 @@ Target_powerpc<size, big_endian>::Reloca
+ if (size == 32)
+ // R_PPC_EMB_NADDR16_HA
+ goto unsupp;
++ // Fall through.
+ case elfcpp::R_PPC64_ADDR16_HIGHEST:
+ case elfcpp::R_PPC64_TPREL16_HIGHEST:
+ Reloc::addr16_hi3(view, value);
+@@ -8039,6 +8116,7 @@ Target_powerpc<size, big_endian>::Reloca
+ if (size == 32)
+ // R_PPC_EMB_SDAI16
+ goto unsupp;
++ // Fall through.
+ case elfcpp::R_PPC64_ADDR16_HIGHESTA:
+ case elfcpp::R_PPC64_TPREL16_HIGHESTA:
+ Reloc::addr16_ha3(view, value);
+@@ -8049,11 +8127,13 @@ Target_powerpc<size, big_endian>::Reloca
+ if (size == 32)
+ // R_PPC_EMB_NADDR32, R_PPC_EMB_NADDR16
+ goto unsupp;
++ // Fall through.
+ case elfcpp::R_PPC64_TPREL16_DS:
+ case elfcpp::R_PPC64_TPREL16_LO_DS:
+ if (size == 32)
+ // R_PPC_TLSGD, R_PPC_TLSLD
+ break;
++ // Fall through.
+ case elfcpp::R_PPC64_ADDR16_DS:
+ case elfcpp::R_PPC64_ADDR16_LO_DS:
+ case elfcpp::R_PPC64_TOC16_DS:
+diff -rup ../binutils-2.27/gold/resolve.cc gold/resolve.cc
+--- ../binutils-2.27/gold/resolve.cc 2016-08-03 08:36:53.000000000 +0100
++++ gold/resolve.cc 2016-11-03 15:05:47.000000000 +0000
+@@ -193,6 +193,7 @@ symbol_to_bits(elfcpp::STB binding, bool
+ // table.
+ gold_error(_("invalid STB_LOCAL symbol in external symbols"));
+ bits = global_flag;
++ break;
+
+ default:
+ // Any target which wants to handle STB_LOOS, etc., needs to
+diff -rup ../binutils-2.27/gold/script.cc gold/script.cc
+--- ../binutils-2.27/gold/script.cc 2016-08-03 08:36:53.000000000 +0100
++++ gold/script.cc 2016-11-03 15:05:47.000000000 +0000
+@@ -1755,6 +1755,7 @@ script_keyword_parsecodes[] =
+ { "FLOAT", FLOAT },
+ { "FORCE_COMMON_ALLOCATION", FORCE_COMMON_ALLOCATION },
+ { "GROUP", GROUP },
++ { "HIDDEN", HIDDEN },
+ { "HLL", HLL },
+ { "INCLUDE", INCLUDE },
+ { "INFO", INFO },
+diff -rup ../binutils-2.27/gold/script-sections.cc gold/script-sections.cc
+--- ../binutils-2.27/gold/script-sections.cc 2016-08-03 08:36:53.000000000 +0100
++++ gold/script-sections.cc 2016-11-03 15:05:48.000000000 +0000
+@@ -1503,7 +1503,7 @@ class Input_section_info
+ private:
+ // Input section, can be a relaxed section.
+ Output_section::Input_section input_section_;
+- // Name of the section.
++ // Name of the section.
+ std::string section_name_;
+ // Section size.
+ uint64_t size_;
+@@ -1545,7 +1545,7 @@ Input_section_sorter::get_init_priority(
+ // GCC uses the following section names for the init_priority
+ // attribute with numerical values 101 and 65535 inclusive. A
+ // lower value means a higher priority.
+- //
++ //
+ // 1: .init_array.NNNN/.fini_array.NNNN: Where NNNN is the
+ // decimal numerical value of the init_priority attribute.
+ // The order of execution in .init_array is forward and
+@@ -1666,7 +1666,7 @@ Output_section_element_input::set_sectio
+ while (p != input_sections->end())
+ {
+ Relobj* relobj = p->relobj();
+- unsigned int shndx = p->shndx();
++ unsigned int shndx = p->shndx();
+ Input_section_info isi(*p);
+
+ // Calling section_name and section_addralign is not very
+@@ -1758,7 +1758,7 @@ Output_section_element_input::set_sectio
+
+ uint64_t this_subalign = sis.addralign();
+ if (!sis.is_input_section())
+- sis.output_section_data()->finalize_data_size();
++ sis.output_section_data()->finalize_data_size();
+ uint64_t data_size = sis.data_size();
+ if (this_subalign < subalign)
+ {
+@@ -2029,7 +2029,7 @@ class Output_section_definition : public
+ void
+ set_section_vma(Expression* address)
+ { this->address_ = address; }
+-
++
+ void
+ set_section_lma(Expression* address)
+ { this->load_address_ = address; }
+@@ -2037,7 +2037,7 @@ class Output_section_definition : public
+ const std::string&
+ get_section_name() const
+ { return this->name_; }
+-
++
+ private:
+ static const char*
+ script_section_type_name(Script_section_type);
+@@ -2402,9 +2402,9 @@ Output_section_definition::set_section_a
+ uint64_t old_load_address = *load_address;
+
+ // If input section sorting is requested via --section-ordering-file or
+- // linker plugins, then do it here. This is important because we want
++ // linker plugins, then do it here. This is important because we want
+ // any sorting specified in the linker scripts, which will be done after
+- // this, to take precedence. The final order of input sections is then
++ // this, to take precedence. The final order of input sections is then
+ // guaranteed to be according to the linker script specification.
+ if (this->output_section_ != NULL
+ && this->output_section_->input_section_order_specified())
+@@ -2495,7 +2495,7 @@ Output_section_definition::set_section_a
+ // The LMA address was explicitly set to the given region.
+ laddr = lma_region->get_current_address()->eval(symtab, layout,
+ false);
+- else
++ else
+ {
+ // We are not going to use the discovered lma_region, so
+ // make sure that we do not update it in the code below.
+@@ -2987,9 +2987,9 @@ Orphan_output_section::set_section_addre
+ address = align_address(address, this->os_->addralign());
+
+ // If input section sorting is requested via --section-ordering-file or
+- // linker plugins, then do it here. This is important because we want
++ // linker plugins, then do it here. This is important because we want
+ // any sorting specified in the linker scripts, which will be done after
+- // this, to take precedence. The final order of input sections is then
++ // this, to take precedence. The final order of input sections is then
+ // guaranteed to be according to the linker script specification.
+ if (this->os_ != NULL
+ && this->os_->input_section_order_specified())
+@@ -3023,7 +3023,7 @@ Orphan_output_section::set_section_addre
+ {
+ uint64_t addralign = p->addralign();
+ if (!p->is_input_section())
+- p->output_section_data()->finalize_data_size();
++ p->output_section_data()->finalize_data_size();
+ uint64_t size = p->data_size();
+ address = align_address(address, addralign);
+ this->os_->add_script_input_section(*p);
+@@ -3605,7 +3605,7 @@ Output_segment*
+ Script_sections::set_section_addresses(Symbol_table* symtab, Layout* layout)
+ {
+ gold_assert(this->saw_sections_clause_);
+-
++
+ // Implement ONLY_IF_RO/ONLY_IF_RW constraints. These are a pain
+ // for our representation.
+ for (Sections_elements::iterator p = this->sections_elements_->begin();
+@@ -3674,7 +3674,7 @@ Script_sections::set_section_addresses(S
+ Output_section* os = (*p)->get_output_section();
+
+ // Handle -Ttext, -Tdata and -Tbss options. We do this by looking for
+- // the special sections by names and doing dot assignments.
++ // the special sections by names and doing dot assignments.
+ if (use_tsection_options
+ && os != NULL
+ && (os->flags() & elfcpp::SHF_ALLOC) != 0)
+@@ -3703,7 +3703,7 @@ Script_sections::set_section_addresses(S
+
+ (*p)->set_section_addresses(symtab, layout, &dot_value, &dot_alignment,
+ &load_address);
+- }
++ }
+
+ if (this->phdrs_elements_ != NULL)
+ {
+@@ -3890,7 +3890,7 @@ Script_sections::create_segments(Layout*
+ layout->get_allocated_sections(§ions);
+
+ // Sort the sections by address.
+- std::stable_sort(sections.begin(), sections.end(),
++ std::stable_sort(sections.begin(), sections.end(),
+ Sort_output_sections(this->sections_elements_));
+
+ this->create_note_and_tls_segments(layout, §ions);
+@@ -4217,7 +4217,7 @@ Script_sections::attach_sections_using_p
+ // Output sections in the script which do not list segments are
+ // attached to the same set of segments as the immediately preceding
+ // output section.
+-
++
+ String_list* phdr_names = NULL;
+ bool load_segments_only = false;
+ for (Sections_elements::const_iterator p = this->sections_elements_->begin();
+@@ -4262,7 +4262,7 @@ Script_sections::attach_sections_using_p
+ // filtering.
+ if (old_phdr_names != phdr_names)
+ load_segments_only = false;
+-
++
+ // If this is an orphan section--one that was not explicitly
+ // mentioned in the linker script--then it should not inherit
+ // any segment type other than PT_LOAD. Otherwise, e.g., the
+@@ -4459,6 +4459,7 @@ Script_sections::release_segments()
+ ++p)
+ (*p)->release_segment();
+ }
++ this->segments_created_ = false;
+ }
+
+ // Print the SECTIONS clause to F for debugging.
+diff -rup ../binutils-2.27/gold/sparc.cc gold/sparc.cc
+--- ../binutils-2.27/gold/sparc.cc 2016-08-03 08:36:53.000000000 +0100
++++ gold/sparc.cc 2016-11-03 15:05:48.000000000 +0000
+@@ -2150,6 +2150,7 @@ Target_sparc<size, big_endian>::Scan::ch
+ case elfcpp::R_SPARC_RELATIVE:
+ case elfcpp::R_SPARC_IRELATIVE:
+ case elfcpp::R_SPARC_COPY:
++ case elfcpp::R_SPARC_32:
+ case elfcpp::R_SPARC_64:
+ case elfcpp::R_SPARC_GLOB_DAT:
+ case elfcpp::R_SPARC_JMP_SLOT:
+@@ -2304,7 +2305,7 @@ Target_sparc<size, big_endian>::Scan::lo
+ reloc.get_r_addend(), is_ifunc);
+ break;
+ }
+- /* Fall through. */
++ // Fall through.
+
+ case elfcpp::R_SPARC_HIX22:
+ case elfcpp::R_SPARC_LOX10:
+@@ -2814,6 +2815,7 @@ Target_sparc<size, big_endian>::Scan::gl
+ // and code transform the GOT load into an addition.
+ break;
+ }
++ // Fall through.
+ case elfcpp::R_SPARC_GOT10:
+ case elfcpp::R_SPARC_GOT13:
+ case elfcpp::R_SPARC_GOT22:
+@@ -3353,6 +3355,7 @@ Target_sparc<size, big_endian>::Relocate
+ gdop_valid = true;
+ break;
+ }
++ // Fall through.
+ case elfcpp::R_SPARC_GOT10:
+ case elfcpp::R_SPARC_GOT13:
+ case elfcpp::R_SPARC_GOT22:
+@@ -3468,6 +3471,13 @@ Target_sparc<size, big_endian>::Relocate
+ Reloc::lo10(view, object, psymval, addend);
+ break;
+
++ case elfcpp::R_SPARC_GOTDATA_OP_LOX10:
++ if (gdop_valid)
++ {
++ Reloc::gdop_lox10(view, got_offset);
++ break;
++ }
++ // Fall through.
+ case elfcpp::R_SPARC_GOT10:
+ Reloc::lo10(view, got_offset, addend);
+ break;
+@@ -3486,13 +3496,6 @@ Target_sparc<size, big_endian>::Relocate
+ }
+ break;
+
+- case elfcpp::R_SPARC_GOTDATA_OP_LOX10:
+- if (gdop_valid)
+- {
+- Reloc::gdop_lox10(view, got_offset);
+- break;
+- }
+- /* Fall through. */
+ case elfcpp::R_SPARC_GOT13:
+ Reloc::rela32_13(view, got_offset, addend);
+ break;
+@@ -3503,7 +3506,7 @@ Target_sparc<size, big_endian>::Relocate
+ Reloc::gdop_hix22(view, got_offset);
+ break;
+ }
+- /* Fall through. */
++ // Fall through.
+ case elfcpp::R_SPARC_GOT22:
+ Reloc::hi22(view, got_offset, addend);
+ break;
+diff -rup ../binutils-2.27/gold/symtab.cc gold/symtab.cc
+--- ../binutils-2.27/gold/symtab.cc 2016-08-03 08:36:53.000000000 +0100
++++ gold/symtab.cc 2016-11-03 15:05:49.000000000 +0000
+@@ -882,6 +882,7 @@ Symbol_table::define_default_version(Siz
+ ;
+ else if (pdef->second->is_from_dynobj()
+ && sym->is_from_dynobj()
++ && pdef->second->is_defined()
+ && pdef->second->object() != sym->object())
+ ;
+ else
+@@ -1325,6 +1326,9 @@ Symbol_table::add_from_relobj(
+ res = this->add_from_object(relobj, name, name_key, ver, ver_key,
+ is_default_version, *psym, st_shndx,
+ is_ordinary, orig_st_shndx);
++
++ if (res == NULL)
++ continue;
+
+ if (is_forced_local)
+ this->force_local(res);
+@@ -1406,6 +1410,9 @@ Symbol_table::add_from_pluginobj(
+ is_default_version, *sym, st_shndx,
+ is_ordinary, st_shndx);
+
++ if (res == NULL)
++ return NULL;
++
+ if (is_forced_local)
+ this->force_local(res);
+
+@@ -1602,6 +1609,9 @@ Symbol_table::add_from_dynobj(
+ }
+ }
+
++ if (res == NULL)
++ continue;
++
+ // Note that it is possible that RES was overridden by an
+ // earlier object, in which case it can't be aliased here.
+ if (st_shndx != elfcpp::SHN_UNDEF
+@@ -1640,7 +1650,6 @@ Symbol_table::add_from_incrobj(
+
+ Stringpool::Key ver_key = 0;
+ bool is_default_version = false;
+- bool is_forced_local = false;
+
+ Stringpool::Key name_key;
+ name = this->namepool_.add(name, true, &name_key);
+@@ -1650,9 +1659,6 @@ Symbol_table::add_from_incrobj(
+ is_default_version, *sym, st_shndx,
+ is_ordinary, st_shndx);
+
+- if (is_forced_local)
+- this->force_local(res);
+-
+ return res;
+ }
+
+diff -rup ../binutils-2.27/gold/tilegx.cc gold/tilegx.cc
+--- ../binutils-2.27/gold/tilegx.cc 2016-08-03 08:36:53.000000000 +0100
++++ gold/tilegx.cc 2016-11-03 15:05:50.000000000 +0000
+@@ -4428,6 +4428,7 @@ Target_tilegx<size, big_endian>::Relocat
+ psymval = &symval;
+ always_apply_relocation = true;
+ addend = 0;
++ // Fall through.
+
+ // when under PIC mode, these relocations are deferred to rtld
+ case elfcpp::R_TILEGX_IMM16_X0_HW0:
+@@ -4618,6 +4619,7 @@ Target_tilegx<size, big_endian>::Relocat
+ got_type = GOT_TYPE_TLS_OFFSET;
+ have_got_offset = true;
+ }
++ // Fall through.
+ do_update_value:
+ if (have_got_offset) {
+ if (gsym != NULL) {
+@@ -4647,10 +4649,8 @@ Target_tilegx<size, big_endian>::Relocat
+ } // else if (opt_t == tls::TLSOPT_TO_LE)
+ // both GD/IE are turned into LE, which
+ // is absolute relocation.
+- //
+- // | go through
+- // |
+- // V
++ // Fall through.
++
+ // LE
+ //
+ // tp
+diff -rup ../binutils-2.27/gold/x86_64.cc gold/x86_64.cc
+--- ../binutils-2.27/gold/x86_64.cc 2016-08-03 08:36:53.000000000 +0100
++++ gold/x86_64.cc 2016-11-03 15:05:52.000000000 +0000
+@@ -2361,7 +2361,7 @@ Target_x86_64<size>::Scan::check_non_pic
+ && !gsym->is_undefined()
+ && !gsym->is_preemptible()))
+ return;
+- /* Fall through. */
++ // Fall through.
+ case elfcpp::R_X86_64_32:
+ // R_X86_64_32 is OK for x32.
+ if (size == 32 && r_type == elfcpp::R_X86_64_32)
+@@ -3505,6 +3505,7 @@ Target_x86_64<size>::Relocate::relocate(
+ if (this->skip_call_tls_get_addr_)
+ {
+ if ((r_type != elfcpp::R_X86_64_PLT32
++ && r_type != elfcpp::R_X86_64_GOTPCREL
+ && r_type != elfcpp::R_X86_64_GOTPCRELX
+ && r_type != elfcpp::R_X86_64_PLT32_BND
+ && r_type != elfcpp::R_X86_64_PC32_BND
+@@ -3514,6 +3515,7 @@ Target_x86_64<size>::Relocate::relocate(
+ {
+ gold_error_at_location(relinfo, relnum, rela.get_r_offset(),
+ _("missing expected TLS relocation"));
++ this->skip_call_tls_get_addr_ = false;
+ }
+ else
+ {
+diff -rup ../binutils-2.27/gold/yyscript.y gold/yyscript.y
+--- ../binutils-2.27/gold/yyscript.y 2016-08-03 08:36:53.000000000 +0100
++++ gold/yyscript.y 2016-11-03 15:05:59.000000000 +0000
+@@ -137,6 +137,7 @@
+ %token FORCE_COMMON_ALLOCATION
+ %token GLOBAL /* global */
+ %token GROUP
++%token HIDDEN
+ %token HLL
+ %token INCLUDE
+ %token INHIBIT_COMMON_ALLOCATION
+@@ -864,6 +865,8 @@ assignment:
+ Expression_ptr e = script_exp_binary_bitwise_or(s, $3);
+ script_set_symbol(closure, $1.value, $1.length, e, 0, 0);
+ }
++ | HIDDEN '(' string '=' parse_exp ')'
++ { script_set_symbol(closure, $3.value, $3.length, $5, 0, 1); }
+ | PROVIDE '(' string '=' parse_exp ')'
+ { script_set_symbol(closure, $3.value, $3.length, $5, 1, 0); }
+ | PROVIDE_HIDDEN '(' string '=' parse_exp ')'
+diff -rup binutils.orig/gold/testsuite/pr18689.sh binutils-2.27/gold/testsuite/pr18689.sh
+--- binutils.orig/gold/testsuite/pr18689.sh 2017-01-17 10:17:46.062813402 +0000
++++ gold/testsuite/pr18689.sh 2017-01-17 10:30:51.583556117 +0000
+@@ -23,6 +23,6 @@
+
+ set -e
+
+-egrep -q "..debug_mac[ro|info][ ]+*" pr18689.stdout
++egrep -q "..debug_str[ ]+*" pr18689.stdout
+
+ exit 0
diff --git a/SOURCES/binutils-2.27-local-dynsym-count.patch b/SOURCES/binutils-2.27-local-dynsym-count.patch
new file mode 100644
index 0000000..7b27255
--- /dev/null
+++ b/SOURCES/binutils-2.27-local-dynsym-count.patch
@@ -0,0 +1,271 @@
+diff -rup binutils-2.27.orig/bfd/ChangeLog binutils-2.27/bfd/ChangeLog
+--- binutils-2.27.orig/bfd/ChangeLog 2016-08-12 17:14:07.621773233 +0100
++++ binutils-2.27/bfd/ChangeLog 2016-08-12 17:17:32.408119156 +0100
+@@ -1,3 +1,9 @@
++2016-08-12 Alan Modra <amodra@gmail.com>
++
++ * elf-bfd.h (struct elf_link_hash_table): Add local_dynsymcount.
++ * elflink.c (_bfd_elf_link_renumber_dynsyms): Set local_dynsymcount.
++ (bfd_elf_final_link): Set .dynsym sh_info from local_dynsymcount.
++
+ 2016-08-03 Tristan Gingold <gingold@adacore.com>
+
+ * version.m4: Bump version to 2.27
+Only in binutils-2.27/bfd: ChangeLog.orig
+Only in binutils-2.27/bfd: ChangeLog.rej
+diff -rup binutils-2.27.orig/bfd/elf-bfd.h binutils-2.27/bfd/elf-bfd.h
+--- binutils-2.27.orig/bfd/elf-bfd.h 2016-08-12 17:14:07.630773290 +0100
++++ binutils-2.27/bfd/elf-bfd.h 2016-08-12 17:16:08.519549845 +0100
+@@ -524,6 +524,7 @@ struct elf_link_hash_table
+ /* The number of symbols found in the link which is intended for the
+ mandatory DT_SYMTAB tag (.dynsym section) in .dynamic section. */
+ bfd_size_type dynsymcount;
++ bfd_size_type local_dynsymcount;
+
+ /* The string table of dynamic symbols, which becomes the .dynstr
+ section. */
+diff -rup binutils-2.27.orig/bfd/elflink.c binutils-2.27/bfd/elflink.c
+--- binutils-2.27.orig/bfd/elflink.c 2016-08-12 17:14:07.637773334 +0100
++++ binutils-2.27/bfd/elflink.c 2016-08-12 17:16:08.521549858 +0100
+@@ -903,6 +903,7 @@ _bfd_elf_link_renumber_dynsyms (bfd *out
+ for (p = elf_hash_table (info)->dynlocal; p ; p = p->next)
+ p->dynindx = ++dynsymcount;
+ }
++ elf_hash_table (info)->local_dynsymcount = dynsymcount;
+
+ elf_link_hash_traverse (elf_hash_table (info),
+ elf_link_renumber_hash_table_dynsyms,
+@@ -11678,7 +11679,10 @@ bfd_elf_final_link (bfd *abfd, struct bf
+ {
+ Elf_Internal_Sym sym;
+ bfd_byte *dynsym = elf_hash_table (info)->dynsym->contents;
+- long last_local = 0;
++
++ o = elf_hash_table (info)->dynsym->output_section;
++ elf_section_data (o)->this_hdr.sh_info
++ = elf_hash_table (info)->local_dynsymcount + 1;
+
+ /* Write out the section symbols for the output sections. */
+ if (bfd_link_pic (info)
+@@ -11708,8 +11712,6 @@ bfd_elf_final_link (bfd *abfd, struct bf
+ return FALSE;
+ sym.st_value = s->vma;
+ dest = dynsym + dynindx * bed->s->sizeof_sym;
+- if (last_local < dynindx)
+- last_local = dynindx;
+ bed->s->swap_symbol_out (abfd, &sym, dest, 0);
+ }
+ }
+@@ -11742,16 +11744,10 @@ bfd_elf_final_link (bfd *abfd, struct bf
+ + e->isym.st_value);
+ }
+
+- if (last_local < e->dynindx)
+- last_local = e->dynindx;
+-
+ dest = dynsym + e->dynindx * bed->s->sizeof_sym;
+ bed->s->swap_symbol_out (abfd, &sym, dest, 0);
+ }
+ }
+-
+- elf_section_data (elf_hash_table (info)->dynsym->output_section)->this_hdr.sh_info =
+- last_local + 1;
+ }
+
+ /* We get the global symbols from the hash table. */
+Only in binutils-2.27/bfd: elflink.c.orig
+diff -rup binutils-2.27.orig/ld/ChangeLog binutils-2.27/ld/ChangeLog
+--- binutils-2.27.orig/ld/ChangeLog 2016-08-12 17:14:08.064776041 +0100
++++ binutils-2.27/ld/ChangeLog 2016-08-12 17:17:00.166900351 +0100
+@@ -1,3 +1,19 @@
++2016-08-12 Alan Modra <amodra@gmail.com>
++
++ * testsuite/ld-tic6x/shlib-1.rd: Correct expected .dynsym sh_info.
++ * testsuite/ld-tic6x/shlib-1b.rd: Likewise.
++ * testsuite/ld-tic6x/shlib-1r.rd: Likewise.
++ * testsuite/ld-tic6x/shlib-1rb.rd: Likewise.
++ * testsuite/ld-tic6x/shlib-app-1.rd: Likewise.
++ * testsuite/ld-tic6x/shlib-app-1b.rd: Likewise.
++ * testsuite/ld-tic6x/shlib-app-1r.rd: Likewise.
++ * testsuite/ld-tic6x/shlib-app-1rb.rd: Likewise.
++ * testsuite/ld-tic6x/shlib-noindex.rd: Likewise.
++ * testsuite/ld-tic6x/static-app-1.rd: Likewise.
++ * testsuite/ld-tic6x/static-app-1b.rd: Likewise.
++ * testsuite/ld-tic6x/static-app-1r.rd: Likewise.
++ * testsuite/ld-tic6x/static-app-1rb.rd: Likewise.
++
+ 2016-08-03 Tristan Gingold <gingold@adacore.com>
+
+ * configure: Regenerate.
+Only in binutils-2.27/ld: ChangeLog.orig
+Only in binutils-2.27/ld: ChangeLog.rej
+diff -rup binutils-2.27.orig/ld/testsuite/ld-tic6x/shlib-1b.rd binutils-2.27/ld/testsuite/ld-tic6x/shlib-1b.rd
+--- binutils-2.27.orig/ld/testsuite/ld-tic6x/shlib-1b.rd 2016-08-12 17:14:08.200776903 +0100
++++ binutils-2.27/ld/testsuite/ld-tic6x/shlib-1b.rd 2016-08-12 17:16:08.522549865 +0100
+@@ -4,7 +4,7 @@ Section Headers:
+ \[Nr\] Name Type Addr Off Size ES Flg Lk Inf Al
+ \[ 0\] NULL 00000000 000000 000000 00 0 0 0
+ \[ 1\] \.hash HASH 00008000 001000 000048 04 A 2 0 4
+- \[ 2\] \.dynsym DYNSYM 00008048 001048 0000d0 10 A 3 6 4
++ \[ 2\] \.dynsym DYNSYM 00008048 001048 0000d0 10 A 3 7 4
+ \[ 3\] \.dynstr STRTAB 00008118 001118 000025 00 A 0 0 1
+ \[ 4\] \.rela\.got RELA 00008140 001140 000024 0c AI 2 10 4
+ \[ 5\] \.rela\.neardata RELA 00008164 001164 000018 0c AI 2 11 4
+diff -rup binutils-2.27.orig/ld/testsuite/ld-tic6x/shlib-1rb.rd binutils-2.27/ld/testsuite/ld-tic6x/shlib-1rb.rd
+--- binutils-2.27.orig/ld/testsuite/ld-tic6x/shlib-1rb.rd 2016-08-12 17:14:08.200776903 +0100
++++ binutils-2.27/ld/testsuite/ld-tic6x/shlib-1rb.rd 2016-08-12 17:16:08.522549865 +0100
+@@ -4,7 +4,7 @@ Section Headers:
+ \[Nr\] Name Type Addr Off Size ES Flg Lk Inf Al
+ \[ 0\] NULL 00000000 000000 000000 00 0 0 0
+ \[ 1\] \.hash HASH 00008000 001000 000048 04 A 2 0 4
+- \[ 2\] \.dynsym DYNSYM 00008048 001048 0000d0 10 A 3 6 4
++ \[ 2\] \.dynsym DYNSYM 00008048 001048 0000d0 10 A 3 7 4
+ \[ 3\] \.dynstr STRTAB 00008118 001118 000025 00 A 0 0 1
+ \[ 4\] \.rela\.got RELA 00008140 001140 000024 0c AI 2 10 4
+ \[ 5\] \.rela\.neardata RELA 00008164 001164 000018 0c AI 2 11 4
+diff -rup binutils-2.27.orig/ld/testsuite/ld-tic6x/shlib-1.rd binutils-2.27/ld/testsuite/ld-tic6x/shlib-1.rd
+--- binutils-2.27.orig/ld/testsuite/ld-tic6x/shlib-1.rd 2016-08-12 17:14:08.200776903 +0100
++++ binutils-2.27/ld/testsuite/ld-tic6x/shlib-1.rd 2016-08-12 17:16:08.522549865 +0100
+@@ -4,7 +4,7 @@ Section Headers:
+ \[Nr\] Name Type Addr Off Size ES Flg Lk Inf Al
+ \[ 0\] NULL 00000000 000000 000000 00 0 0 0
+ \[ 1\] \.hash HASH 00008000 001000 000048 04 A 2 0 4
+- \[ 2\] \.dynsym DYNSYM 00008048 001048 0000d0 10 A 3 6 4
++ \[ 2\] \.dynsym DYNSYM 00008048 001048 0000d0 10 A 3 7 4
+ \[ 3\] \.dynstr STRTAB 00008118 001118 000025 00 A 0 0 1
+ \[ 4\] \.rela\.got RELA 00008140 001140 000024 0c AI 2 10 4
+ \[ 5\] \.rela\.neardata RELA 00008164 001164 000018 0c AI 2 11 4
+diff -rup binutils-2.27.orig/ld/testsuite/ld-tic6x/shlib-1r.rd binutils-2.27/ld/testsuite/ld-tic6x/shlib-1r.rd
+--- binutils-2.27.orig/ld/testsuite/ld-tic6x/shlib-1r.rd 2016-08-12 17:14:08.200776903 +0100
++++ binutils-2.27/ld/testsuite/ld-tic6x/shlib-1r.rd 2016-08-12 17:16:08.522549865 +0100
+@@ -4,7 +4,7 @@ Section Headers:
+ \[Nr\] Name Type Addr Off Size ES Flg Lk Inf Al
+ \[ 0\] NULL 00000000 000000 000000 00 0 0 0
+ \[ 1\] \.hash HASH 00008000 001000 000048 04 A 2 0 4
+- \[ 2\] \.dynsym DYNSYM 00008048 001048 0000d0 10 A 3 6 4
++ \[ 2\] \.dynsym DYNSYM 00008048 001048 0000d0 10 A 3 7 4
+ \[ 3\] \.dynstr STRTAB 00008118 001118 000025 00 A 0 0 1
+ \[ 4\] \.rela\.got RELA 00008140 001140 000024 0c AI 2 10 4
+ \[ 5\] \.rela\.neardata RELA 00008164 001164 000018 0c AI 2 11 4
+diff -rup binutils-2.27.orig/ld/testsuite/ld-tic6x/shlib-app-1b.rd binutils-2.27/ld/testsuite/ld-tic6x/shlib-app-1b.rd
+--- binutils-2.27.orig/ld/testsuite/ld-tic6x/shlib-app-1b.rd 2016-08-12 17:14:08.200776903 +0100
++++ binutils-2.27/ld/testsuite/ld-tic6x/shlib-app-1b.rd 2016-08-12 17:16:08.522549865 +0100
+@@ -4,7 +4,7 @@ Section Headers:
+ \[Nr\] Name Type Addr Off Size ES Flg Lk Inf Al
+ \[ 0\] NULL 00000000 000000 000000 00 0 0 0
+ \[ 1\] \.hash HASH 00008000 001000 000044 04 A 2 0 4
+- \[ 2\] \.dynsym DYNSYM 00008044 001044 0000c0 10 A 3 6 4
++ \[ 2\] \.dynsym DYNSYM 00008044 001044 0000c0 10 A 3 7 4
+ \[ 3\] \.dynstr STRTAB 00008104 001104 000036 00 A 0 0 1
+ \[ 4\] \.rela\.got RELA 0000813c 00113c 000018 0c AI 2 11 4
+ \[ 5\] \.rela\.neardata RELA 00008154 001154 000018 0c AI 2 12 4
+diff -rup binutils-2.27.orig/ld/testsuite/ld-tic6x/shlib-app-1rb.rd binutils-2.27/ld/testsuite/ld-tic6x/shlib-app-1rb.rd
+--- binutils-2.27.orig/ld/testsuite/ld-tic6x/shlib-app-1rb.rd 2016-08-12 17:14:08.201776909 +0100
++++ binutils-2.27/ld/testsuite/ld-tic6x/shlib-app-1rb.rd 2016-08-12 17:16:08.522549865 +0100
+@@ -4,7 +4,7 @@ Section Headers:
+ \[Nr\] Name Type Addr Off Size ES Flg Lk Inf Al
+ \[ 0\] NULL 00000000 000000 000000 00 0 0 0
+ \[ 1\] \.hash HASH 00008000 001000 00003c 04 A 2 0 4
+- \[ 2\] \.dynsym DYNSYM 0000803c 00103c 0000a0 10 A 3 6 4
++ \[ 2\] \.dynsym DYNSYM 0000803c 00103c 0000a0 10 A 3 7 4
+ \[ 3\] \.dynstr STRTAB 000080dc 0010dc 000031 00 A 0 0 1
+ \[ 4\] \.rela\.got RELA 00008110 001110 000018 0c AI 2 10 4
+ \[ 5\] \.rela\.bss RELA 00008128 001128 00000c 0c AI 2 12 4
+diff -rup binutils-2.27.orig/ld/testsuite/ld-tic6x/shlib-app-1.rd binutils-2.27/ld/testsuite/ld-tic6x/shlib-app-1.rd
+--- binutils-2.27.orig/ld/testsuite/ld-tic6x/shlib-app-1.rd 2016-08-12 17:14:08.200776903 +0100
++++ binutils-2.27/ld/testsuite/ld-tic6x/shlib-app-1.rd 2016-08-12 17:16:08.522549865 +0100
+@@ -4,7 +4,7 @@ Section Headers:
+ \[Nr\] Name Type Addr Off Size ES Flg Lk Inf Al
+ \[ 0\] NULL 00000000 000000 000000 00 0 0 0
+ \[ 1\] \.hash HASH 00008000 001000 000044 04 A 2 0 4
+- \[ 2\] \.dynsym DYNSYM 00008044 001044 0000c0 10 A 3 6 4
++ \[ 2\] \.dynsym DYNSYM 00008044 001044 0000c0 10 A 3 7 4
+ \[ 3\] \.dynstr STRTAB 00008104 001104 000035 00 A 0 0 1
+ \[ 4\] \.rela\.got RELA 0000813c 00113c 000018 0c AI 2 11 4
+ \[ 5\] \.rela\.neardata RELA 00008154 001154 000018 0c AI 2 12 4
+diff -rup binutils-2.27.orig/ld/testsuite/ld-tic6x/shlib-app-1r.rd binutils-2.27/ld/testsuite/ld-tic6x/shlib-app-1r.rd
+--- binutils-2.27.orig/ld/testsuite/ld-tic6x/shlib-app-1r.rd 2016-08-12 17:14:08.200776903 +0100
++++ binutils-2.27/ld/testsuite/ld-tic6x/shlib-app-1r.rd 2016-08-12 17:16:08.522549865 +0100
+@@ -4,7 +4,7 @@ Section Headers:
+ \[Nr\] Name Type Addr Off Size ES Flg Lk Inf Al
+ \[ 0\] NULL 00000000 000000 000000 00 0 0 0
+ \[ 1\] \.hash HASH 00008000 001000 00003c 04 A 2 0 4
+- \[ 2\] \.dynsym DYNSYM 0000803c 00103c 0000a0 10 A 3 6 4
++ \[ 2\] \.dynsym DYNSYM 0000803c 00103c 0000a0 10 A 3 7 4
+ \[ 3\] \.dynstr STRTAB 000080dc 0010dc 000030 00 A 0 0 1
+ \[ 4\] \.rela\.got RELA 0000810c 00110c 000018 0c AI 2 10 4
+ \[ 5\] \.rela\.bss RELA 00008124 001124 00000c 0c AI 2 12 4
+diff -rup binutils-2.27.orig/ld/testsuite/ld-tic6x/shlib-noindex.rd binutils-2.27/ld/testsuite/ld-tic6x/shlib-noindex.rd
+--- binutils-2.27.orig/ld/testsuite/ld-tic6x/shlib-noindex.rd 2016-08-12 17:14:08.201776909 +0100
++++ binutils-2.27/ld/testsuite/ld-tic6x/shlib-noindex.rd 2016-08-12 17:16:08.522549865 +0100
+@@ -4,7 +4,7 @@ Section Headers:
+ \[Nr\] Name Type Addr Off Size ES Flg Lk Inf Al
+ \[ 0\] NULL 00000000 000000 000000 00 0 0 0
+ \[ 1\] \.hash HASH 00008000 001000 000048 04 A 2 0 4
+- \[ 2\] \.dynsym DYNSYM 00008048 001048 0000d0 10 A 3 6 4
++ \[ 2\] \.dynsym DYNSYM 00008048 001048 0000d0 10 A 3 7 4
+ \[ 3\] \.dynstr STRTAB 00008118 001118 000025 00 A 0 0 1
+ \[ 4\] \.rela\.text RELA 00008140 001140 00000c 0c AI 2 10 4
+ \[ 5\] \.rela\.got RELA 0000814c 00114c 000024 0c AI 2 11 4
+diff -rup binutils-2.27.orig/ld/testsuite/ld-tic6x/static-app-1b.rd binutils-2.27/ld/testsuite/ld-tic6x/static-app-1b.rd
+--- binutils-2.27.orig/ld/testsuite/ld-tic6x/static-app-1b.rd 2016-08-12 17:14:08.201776909 +0100
++++ binutils-2.27/ld/testsuite/ld-tic6x/static-app-1b.rd 2016-08-12 17:16:08.522549865 +0100
+@@ -4,7 +4,7 @@ Section Headers:
+ \[Nr\] Name Type Addr Off Size ES Flg Lk Inf Al
+ \[ 0\] NULL 00000000 000000 000000 00 0 0 0
+ \[ 1\] \.hash HASH 00008000 001000 00003c 04 A 2 0 4
+- \[ 2\] \.dynsym DYNSYM 0000803c 00103c 0000a0 10 A 3 5 4
++ \[ 2\] \.dynsym DYNSYM 0000803c 00103c 0000a0 10 A 3 7 4
+ \[ 3\] \.dynstr STRTAB 000080dc 0010dc 00001d 00 A 0 0 1
+ \[ 4\] \.rela\.got RELA 000080fc 0010fc 000024 0c AI 2 8 4
+ \[ 5\] \.rela\.neardata RELA 00008120 001120 000030 0c AI 2 9 4
+diff -rup binutils-2.27.orig/ld/testsuite/ld-tic6x/static-app-1rb.rd binutils-2.27/ld/testsuite/ld-tic6x/static-app-1rb.rd
+--- binutils-2.27.orig/ld/testsuite/ld-tic6x/static-app-1rb.rd 2016-08-12 17:14:08.201776909 +0100
++++ binutils-2.27/ld/testsuite/ld-tic6x/static-app-1rb.rd 2016-08-12 17:16:08.523549872 +0100
+@@ -4,7 +4,7 @@ Section Headers:
+ \[Nr\] Name Type Addr Off Size ES Flg Lk Inf Al
+ \[ 0\] NULL 00000000 000000 000000 00 0 0 0
+ \[ 1\] \.hash HASH 00008000 001000 00003c 04 A 2 0 4
+- \[ 2\] \.dynsym DYNSYM 0000803c 00103c 0000a0 10 A 3 5 4
++ \[ 2\] \.dynsym DYNSYM 0000803c 00103c 0000a0 10 A 3 7 4
+ \[ 3\] \.dynstr STRTAB 000080dc 0010dc 00001d 00 A 0 0 1
+ \[ 4\] \.rela\.got RELA 000080fc 0010fc 000024 0c AI 2 8 4
+ \[ 5\] \.rela\.neardata RELA 00008120 001120 000018 0c AI 2 9 4
+diff -rup binutils-2.27.orig/ld/testsuite/ld-tic6x/static-app-1.rd binutils-2.27/ld/testsuite/ld-tic6x/static-app-1.rd
+--- binutils-2.27.orig/ld/testsuite/ld-tic6x/static-app-1.rd 2016-08-12 17:14:08.201776909 +0100
++++ binutils-2.27/ld/testsuite/ld-tic6x/static-app-1.rd 2016-08-12 17:16:08.522549865 +0100
+@@ -4,7 +4,7 @@ Section Headers:
+ \[Nr\] Name Type Addr Off Size ES Flg Lk Inf Al
+ \[ 0\] NULL 00000000 000000 000000 00 0 0 0
+ \[ 1\] \.hash HASH 00008000 001000 00003c 04 A 2 0 4
+- \[ 2\] \.dynsym DYNSYM 0000803c 00103c 0000a0 10 A 3 5 4
++ \[ 2\] \.dynsym DYNSYM 0000803c 00103c 0000a0 10 A 3 7 4
+ \[ 3\] \.dynstr STRTAB 000080dc 0010dc 00001d 00 A 0 0 1
+ \[ 4\] \.rela\.got RELA 000080fc 0010fc 000024 0c AI 2 8 4
+ \[ 5\] \.rela\.neardata RELA 00008120 001120 000030 0c AI 2 9 4
+diff -rup binutils-2.27.orig/ld/testsuite/ld-tic6x/static-app-1r.rd binutils-2.27/ld/testsuite/ld-tic6x/static-app-1r.rd
+--- binutils-2.27.orig/ld/testsuite/ld-tic6x/static-app-1r.rd 2016-08-12 17:14:08.201776909 +0100
++++ binutils-2.27/ld/testsuite/ld-tic6x/static-app-1r.rd 2016-08-12 17:16:08.523549872 +0100
+@@ -4,7 +4,7 @@ Section Headers:
+ \[Nr\] Name Type Addr Off Size ES Flg Lk Inf Al
+ \[ 0\] NULL 00000000 000000 000000 00 0 0 0
+ \[ 1\] \.hash HASH 00008000 001000 00003c 04 A 2 0 4
+- \[ 2\] \.dynsym DYNSYM 0000803c 00103c 0000a0 10 A 3 5 4
++ \[ 2\] \.dynsym DYNSYM 0000803c 00103c 0000a0 10 A 3 7 4
+ \[ 3\] \.dynstr STRTAB 000080dc 0010dc 00001d 00 A 0 0 1
+ \[ 4\] \.rela\.got RELA 000080fc 0010fc 000024 0c AI 2 8 4
+ \[ 5\] \.rela\.neardata RELA 00008120 001120 000018 0c AI 2 9 4
+--- binutils-2.27.orig/binutils/readelf.c 2016-08-12 17:14:07.717773841 +0100
++++ binutils-2.27/binutils/readelf.c 2016-08-12 17:24:25.007897415 +0100
+@@ -11110,6 +11110,11 @@ process_symbol_table (FILE * file)
+ }
+
+ putchar ('\n');
++
++ if (ELF_ST_BIND (psym->st_info) == STB_LOCAL
++ && si >= section->sh_info)
++ warn (_("local symbol %u found at index >= %s's sh_info value of %u\n"),
++ si, printable_section_name (section), section->sh_info);
+ }
+
+ free (symtab);
diff --git a/SOURCES/binutils-2.27-monotonic-section-offsets.patch b/SOURCES/binutils-2.27-monotonic-section-offsets.patch
new file mode 100644
index 0000000..932df8b
--- /dev/null
+++ b/SOURCES/binutils-2.27-monotonic-section-offsets.patch
@@ -0,0 +1,2097 @@
+diff --git a/bfd/elf.c b/bfd/elf.c
+index 274cd53..c3630d2 100644
+--- a/bfd/elf.c
++++ b/bfd/elf.c
+@@ -3093,7 +3093,7 @@ elf_fake_sections (bfd *abfd, asection *asect, void *fsarg)
+ compressed. */
+ asect->flags |= SEC_ELF_COMPRESS;
+
+- /* If this section will be compressed, delay adding setion
++ /* If this section will be compressed, delay adding section
+ name to section name section after it is compressed in
+ _bfd_elf_assign_file_positions_for_non_load. */
+ delay_st_name_p = TRUE;
+@@ -3595,10 +3595,6 @@ assign_section_numbers (bfd *abfd, struct bfd_link_info *link_info)
+ d->rela.idx = 0;
+ }
+
+- elf_shstrtab_sec (abfd) = section_number++;
+- _bfd_elf_strtab_addref (elf_shstrtab (abfd), t->shstrtab_hdr.sh_name);
+- elf_elfheader (abfd)->e_shstrndx = elf_shstrtab_sec (abfd);
+-
+ need_symtab = (bfd_get_symcount (abfd) > 0
+ || (link_info == NULL
+ && ((abfd->flags & (EXEC_P | DYNAMIC | HAS_RELOC))
+@@ -3626,6 +3622,10 @@ assign_section_numbers (bfd *abfd, struct bfd_link_info *link_info)
+ _bfd_elf_strtab_addref (elf_shstrtab (abfd), t->strtab_hdr.sh_name);
+ }
+
++ elf_shstrtab_sec (abfd) = section_number++;
++ _bfd_elf_strtab_addref (elf_shstrtab (abfd), t->shstrtab_hdr.sh_name);
++ elf_elfheader (abfd)->e_shstrndx = elf_shstrtab_sec (abfd);
++
+ if (section_number >= SHN_LORESERVE)
+ {
+ _bfd_error_handler (_("%B: too many sections: %u"),
+@@ -6028,7 +6028,7 @@ _bfd_elf_assign_file_positions_for_non_load (bfd *abfd)
+ return FALSE;
+ name = new_name;
+ }
+- /* Add setion name to section name section. */
++ /* Add section name to section name section. */
+ if (shdrp->sh_name != (unsigned int) -1)
+ abort ();
+ shdrp->sh_name
+@@ -6036,7 +6036,7 @@ _bfd_elf_assign_file_positions_for_non_load (bfd *abfd)
+ name, FALSE);
+ d = elf_section_data (sec);
+
+- /* Add reloc setion name to section name section. */
++ /* Add reloc section name to section name section. */
+ if (d->rel.hdr
+ && !_bfd_elf_set_reloc_sh_name (abfd,
+ d->rel.hdr,
+diff --git a/binutils/testsuite/binutils-all/readelf.s b/binutils/testsuite/binutils-all/readelf.s
+index fd62fda..5aae0ce 100644
+--- a/binutils/testsuite/binutils-all/readelf.s
++++ b/binutils/testsuite/binutils-all/readelf.s
+@@ -14,8 +14,8 @@ Section Headers:
+ # MIPS targets put .reginfo, .mdebug, .MIPS.abiflags and .gnu.attributes here.
+ # v850 targets put .call_table_data and .call_table_text here.
+ #...
+- +\[ .\] .shstrtab +STRTAB +00000000 0+.* 0+.* 00 .* +0 +0 +.
+ +\[..\] .symtab +SYMTAB +00000000 0+.* 0+.* 10 +.. +.+ +4
+ +\[..\] .strtab +STRTAB +00000000 0+.* 0+.* 00 .* +0 +0 +1
++ +\[..\] .shstrtab +STRTAB +00000000 0+.* 0+.* 00 .* +0 +0 +.
+ Key to Flags:
+ #...
+diff --git a/binutils/testsuite/binutils-all/readelf.s-64 b/binutils/testsuite/binutils-all/readelf.s-64
+index d198300..622b314 100644
+--- a/binutils/testsuite/binutils-all/readelf.s-64
++++ b/binutils/testsuite/binutils-all/readelf.s-64
+@@ -13,12 +13,12 @@ Section Headers:
+ +000000000000000[48] +0000000000000000 +WA +0 +0 +.*
+ +\[ 4\] .bss +NOBITS +0000000000000000 +000000(4c|50|54|58)
+ +0000000000000000 +0000000000000000 +WA +0 +0 +.*
+- +\[ 5\] .shstrtab +STRTAB +0000000000000000 +[0-9a-f]+
+- +00000000000000.. +0000000000000000 .* +0 +0 +.*
+- +\[ 6\] .symtab +SYMTAB +0000000000000000 +0+.*
++ +\[ 5\] .symtab +SYMTAB +0000000000000000 +0+.*
+ # aarch64-elf targets have one more data symbol.
+- +0+.* +0000000000000018 +7 +(6|7) +8
+- +\[ 7\] .strtab +STRTAB +0000000000000000 +0+.*
++ +0+.* +0000000000000018 +6 +(6|7) +8
++ +\[ 6\] .strtab +STRTAB +0000000000000000 +0+.*
+ +0+.* +0000000000000000 .* +0 +0 +1
++ +\[ 7\] .shstrtab +STRTAB +0000000000000000 +[0-9a-f]+
++ +00000000000000.. +0000000000000000 .* +0 +0 +.*
+ Key to Flags:
+ #...
+diff --git a/gas/testsuite/gas/i386/ilp32/x86-64-unwind.d b/gas/testsuite/gas/i386/ilp32/x86-64-unwind.d
+index 5cea05e..5dc74d6 100644
+--- a/gas/testsuite/gas/i386/ilp32/x86-64-unwind.d
++++ b/gas/testsuite/gas/i386/ilp32/x86-64-unwind.d
+@@ -11,8 +11,8 @@ Section Headers:
+ \[ 2\] .data PROGBITS 00000000 000034 000000 00 WA 0 0 1
+ \[ 3\] .bss NOBITS 00000000 000034 000000 00 WA 0 0 1
+ \[ 4\] .eh_frame X86_64_UNWIND 00000000 000034 000008 00 A 0 0 1
+- \[ 5\] .shstrtab STRTAB 00000000 [0-9a-f]+ 000036 00 . 0 0 1
+- \[ 6\] .symtab SYMTAB 00000000 [0-9a-f]+ 000050 10 7 5 4
+- \[ 7\] .strtab STRTAB 00000000 [0-9a-f]+ 000001 00 . 0 0 1
++ \[ 5\] .symtab SYMTAB 00000000 [0-9a-f]+ 000050 10 6 5 4
++ \[ 6\] .strtab STRTAB 00000000 [0-9a-f]+ 000001 00 . 0 0 1
++ \[ 7\] .shstrtab STRTAB 00000000 [0-9a-f]+ 000036 00 . 0 0 1
+ Key to Flags:
+ #pass
+diff --git a/gas/testsuite/gas/i386/x86-64-unwind.d b/gas/testsuite/gas/i386/x86-64-unwind.d
+index 7a4c64c..89f1a65 100644
+--- a/gas/testsuite/gas/i386/x86-64-unwind.d
++++ b/gas/testsuite/gas/i386/x86-64-unwind.d
+@@ -16,11 +16,11 @@ Section Headers:
+ 0000000000000000 0000000000000000 WA 0 0 1
+ \[ 4\] \.eh_frame X86_64_UNWIND 0000000000000000 00000040
+ 0000000000000008 0000000000000000 A 0 0 1
+- \[ 5\] \.shstrtab STRTAB 0000000000000000 [0-9a-f]+
+- 0000000000000036 0000000000000000 . 0 0 1
+- \[ 6\] \.symtab SYMTAB 0000000000000000 [0-9a-f]+
+- 0000000000000078 0000000000000018 7 5 8
+- \[ 7\] \.strtab STRTAB 0000000000000000 [0-9a-f]+
++ \[ 5\] \.symtab SYMTAB 0000000000000000 [0-9a-f]+
++ 0000000000000078 0000000000000018 6 5 8
++ \[ 6\] \.strtab STRTAB 0000000000000000 [0-9a-f]+
+ 0000000000000001 0000000000000000 . 0 0 1
++ \[ 7\] \.shstrtab STRTAB 0000000000000000 [0-9a-f]+
++ 0000000000000036 0000000000000000 . 0 0 1
+ Key to Flags:
+ #...
+diff --git a/gas/testsuite/gas/ia64/alias-ilp32.d b/gas/testsuite/gas/ia64/alias-ilp32.d
+index d882b3c..df05d36 100644
+--- a/gas/testsuite/gas/ia64/alias-ilp32.d
++++ b/gas/testsuite/gas/ia64/alias-ilp32.d
+@@ -12,9 +12,9 @@ Section Headers:
+ +\[ 2\] .data +PROGBITS +00000000 000040 000000 00 +WA +0 +0 +1
+ +\[ 3\] .bss +NOBITS +00000000 000040 000000 00 +WA +0 +0 +1
+ +\[ 4\] 1234 +PROGBITS +00000000 000040 000005 00 +WA +0 +0 +1
+- +\[ 5\] .shstrtab +STRTAB +00000000 [0-9a-f]+ 000031 00 +0 +0 +1
+- +\[ 6\] .symtab +SYMTAB +00000000 [0-9a-f]+ 000060 10 +7 +6 +4
+- +\[ 7\] .strtab +STRTAB +00000000 [0-9a-f]+ 000006 00 +0 +0 +1
++ +\[ 5\] .symtab +SYMTAB +00000000 [0-9a-f]+ 000060 10 +6 +6 +4
++ +\[ 6\] .strtab +STRTAB +00000000 [0-9a-f]+ 000006 00 +0 +0 +1
++ +\[ 7\] .shstrtab +STRTAB +00000000 [0-9a-f]+ 000031 00 +0 +0 +1
+ Key to Flags:
+ #...
+
+diff --git a/gas/testsuite/gas/ia64/alias.d b/gas/testsuite/gas/ia64/alias.d
+index 398bff4..23b9330 100644
+--- a/gas/testsuite/gas/ia64/alias.d
++++ b/gas/testsuite/gas/ia64/alias.d
+@@ -16,12 +16,12 @@ Section Headers:
+ +0000000000000000 +0000000000000000 +WA +0 +0 +1
+ +\[ 4\] 1234 +PROGBITS +0000000000000000 +00000040
+ +0000000000000005 +0000000000000000 +WA +0 +0 +1
+- +\[ 5\] \.shstrtab +STRTAB +0000000000000000 +[0-9a-f]+
+- +0000000000000031 +0000000000000000 +0 +0 +1
+- +\[ 6\] \.symtab +SYMTAB +0000000000000000 .*
+- +0000000000000090 +0000000000000018 +7 +6 +8
+- +\[ 7\] \.strtab +STRTAB +0000000000000000 .*
++ +\[ 5\] \.symtab +SYMTAB +0000000000000000 .*
++ +0000000000000090 +0000000000000018 +6 +6 +8
++ +\[ 6\] \.strtab +STRTAB +0000000000000000 .*
+ +0000000000000006 +0000000000000000 +0 +0 +1
++ +\[ 7\] \.shstrtab +STRTAB +0000000000000000 +[0-9a-f]+
++ +0000000000000031 +0000000000000000 +0 +0 +1
+ Key to Flags:
+ #...
+
+diff --git a/gas/testsuite/gas/ia64/group-1.d b/gas/testsuite/gas/ia64/group-1.d
+index b4eab14..b90bd88 100644
+--- a/gas/testsuite/gas/ia64/group-1.d
++++ b/gas/testsuite/gas/ia64/group-1.d
+@@ -18,12 +18,12 @@ Section Headers:
+ 0000000000000000 0000000000000000 WA 0 0 1
+ \[ 5\] \.text PROGBITS 0000000000000000 00000050
+ 0000000000000010 0000000000000000 AXG 0 0 16
+- \[ 6\] \.shstrtab STRTAB 0000000000000000 [0-9a-f]+
+- 0000000000000033 0000000000000000 0 0 1
+- \[ 7\] \.symtab SYMTAB 0000000000000000 .*
+- 00000000000000c0 0000000000000018 8 8 8
+- \[ 8\] \.strtab STRTAB 0000000000000000 .*
++ \[ 6\] \.symtab SYMTAB 0000000000000000 .*
++ 00000000000000c0 0000000000000018 7 8 8
++ \[ 7\] \.strtab STRTAB 0000000000000000 .*
+ 000000000000000[7c] 0000000000000000 0 0 1
++ \[ 8\] \.shstrtab STRTAB 0000000000000000 [0-9a-f]+
++ 0000000000000033 0000000000000000 0 0 1
+ Key to Flags:
+ #...
+
+diff --git a/gas/testsuite/gas/ia64/group-2.d b/gas/testsuite/gas/ia64/group-2.d
+index 7370367..cc8413f 100644
+--- a/gas/testsuite/gas/ia64/group-2.d
++++ b/gas/testsuite/gas/ia64/group-2.d
+@@ -25,12 +25,12 @@ Section Headers:
+ 0000000000000018 0000000000000000 ALG 5 5 8
+ \[ 8\] \.rela\.gnu\.linkonc RELA 0000000000000000 .*
+ 0000000000000048 0000000000000018 I 10 7 8
+- \[ 9\] \.shstrtab STRTAB 0000000000000000 [0-9a-f]+
+- 0000000000000081 0000000000000000 0 0 1
+- \[10\] \.symtab SYMTAB 0000000000000000 .*
+- 00000000000000d8 0000000000000018 11 9 8
+- \[11\] \.strtab STRTAB 0000000000000000 .*
++ \[ 9\] \.symtab SYMTAB 0000000000000000 .*
++ 00000000000000d8 0000000000000018 10 9 8
++ \[10\] \.strtab STRTAB 0000000000000000 .*
+ 0000000000000005 0000000000000000 0 0 1
++ \[11\] \.shstrtab STRTAB 0000000000000000 [0-9a-f]+
++ 0000000000000081 0000000000000000 0 0 1
+ Key to Flags:
+ #...
+
+diff --git a/gas/testsuite/gas/ia64/secname-ilp32.d b/gas/testsuite/gas/ia64/secname-ilp32.d
+index 4146307..0b8a771 100644
+--- a/gas/testsuite/gas/ia64/secname-ilp32.d
++++ b/gas/testsuite/gas/ia64/secname-ilp32.d
+@@ -12,8 +12,8 @@ Section Headers:
+ \[ 2\] .data PROGBITS 00000000 000040 000000 00 WA 0 0 1
+ \[ 3\] .bss NOBITS 00000000 000040 000000 00 WA 0 0 1
+ \[ 4\] .foo PROGBITS 00000000 000040 000008 00 WA 0 0 8
+- \[ 5\] .shstrtab STRTAB 00000000 [0-9a-f]+ 000031 00 0 0 1
+- \[ 6\] .symtab SYMTAB 00000000 [0-9a-f]+ 000050 10 7 5 4
+- \[ 7\] .strtab STRTAB 00000000 [0-9a-f]+ 000001 00 0 0 1
++ \[ 5\] .symtab SYMTAB 00000000 [0-9a-f]+ 000050 10 6 5 4
++ \[ 6\] .strtab STRTAB 00000000 [0-9a-f]+ 000001 00 0 0 1
++ \[ 7\] .shstrtab STRTAB 00000000 [0-9a-f]+ 000031 00 0 0 1
+ Key to Flags:
+ #...
+diff --git a/gas/testsuite/gas/ia64/secname.d b/gas/testsuite/gas/ia64/secname.d
+index 79f1e33..9d02e1a 100644
+--- a/gas/testsuite/gas/ia64/secname.d
++++ b/gas/testsuite/gas/ia64/secname.d
+@@ -16,11 +16,11 @@ Section Headers:
+ 0000000000000000 0000000000000000 WA 0 0 1
+ \[ 4\] \.foo PROGBITS 0000000000000000 00000040
+ 0000000000000008 0000000000000000 WA 0 0 8
+- \[ 5\] \.shstrtab STRTAB 0000000000000000 [0-9a-f]+
+- 0000000000000031 0000000000000000 0 0 1
+- \[ 6\] \.symtab SYMTAB 0000000000000000 .*
+- 0000000000000078 0000000000000018 7 5 8
+- \[ 7\] \.strtab STRTAB 0000000000000000 .*
++ \[ 5\] \.symtab SYMTAB 0000000000000000 .*
++ 0000000000000078 0000000000000018 6 5 8
++ \[ 6\] \.strtab STRTAB 0000000000000000 .*
+ 0000000000000001 0000000000000000 0 0 1
++ \[ 7\] \.shstrtab STRTAB 0000000000000000 [0-9a-f]+
++ 0000000000000031 0000000000000000 0 0 1
+ Key to Flags:
+ #...
+diff --git a/gas/testsuite/gas/ia64/unwind-ilp32.d b/gas/testsuite/gas/ia64/unwind-ilp32.d
+index cd25b0d..e96f89b 100644
+--- a/gas/testsuite/gas/ia64/unwind-ilp32.d
++++ b/gas/testsuite/gas/ia64/unwind-ilp32.d
+@@ -13,8 +13,8 @@ Section Headers:
+ \[ 3\] .bss NOBITS 00000000 000040 000000 00 WA 0 0 1
+ \[ 4\] .IA_64.unwind_inf PROGBITS 00000000 000040 000008 00 A 0 0 8
+ \[ 5\] .IA_64.unwind IA_64_UNWIND 00000000 000048 000008 00 AL 1 1 8
+- \[ 6\] .shstrtab STRTAB 00000000 [0-9a-f]+ 00004d 00 0 0 1
+- \[ 7\] .symtab SYMTAB 00000000 [0-9a-f]+ 000060 10 8 6 4
+- \[ 8\] .strtab STRTAB 00000000 [0-9a-f]+ 000001 00 0 0 1
++ \[ 6\] .symtab SYMTAB 00000000 [0-9a-f]+ 000060 10 7 6 4
++ \[ 7\] .strtab STRTAB 00000000 [0-9a-f]+ 000001 00 0 0 1
++ \[ 8\] .shstrtab STRTAB 00000000 [0-9a-f]+ 00004d 00 0 0 1
+ Key to Flags:
+ #...
+diff --git a/gas/testsuite/gas/ia64/unwind.d b/gas/testsuite/gas/ia64/unwind.d
+index ce71a7a..bdb7af8 100644
+--- a/gas/testsuite/gas/ia64/unwind.d
++++ b/gas/testsuite/gas/ia64/unwind.d
+@@ -18,11 +18,11 @@ Section Headers:
+ 0000000000000008 0000000000000000 A 0 0 8
+ \[ 5\] \.IA_64\.unwind IA_64_UNWIND 0000000000000000 00000048
+ 0000000000000008 0000000000000000 AL 1 1 8
+- \[ 6\] \.shstrtab STRTAB 0000000000000000 [0-9a-f]+
+- 000000000000004d 0000000000000000 0 0 1
+- \[ 7\] \.symtab SYMTAB 0000000000000000 .*
+- 0000000000000090 0000000000000018 8 6 8
+- \[ 8\] \.strtab STRTAB 0000000000000000 .*
++ \[ 6\] \.symtab SYMTAB 0000000000000000 .*
++ 0000000000000090 0000000000000018 7 6 8
++ \[ 7\] \.strtab STRTAB 0000000000000000 .*
+ 0000000000000001 0000000000000000 0 0 1
++ \[ 8\] \.shstrtab STRTAB 0000000000000000 [0-9a-f]+
++ 000000000000004d 0000000000000000 0 0 1
+ Key to Flags:
+ #...
+diff --git a/gas/testsuite/gas/ia64/xdata-ilp32.d b/gas/testsuite/gas/ia64/xdata-ilp32.d
+index 8c0bb30..e5dd507 100644
+--- a/gas/testsuite/gas/ia64/xdata-ilp32.d
++++ b/gas/testsuite/gas/ia64/xdata-ilp32.d
+@@ -23,7 +23,7 @@ Section Headers:
+ \[13\] \.xreal\[4\] PROGBITS 00000000 [[:xdigit:]]+ 000020 00 A 0 0 16
+ \[14\] \.xstr<1> PROGBITS 00000000 [[:xdigit:]]+ 000003 00 A 0 0 1
+ \[15\] \.xstr\{2\} PROGBITS 00000000 [[:xdigit:]]+ 000004 00 A 0 0 1
+- \[16\] .shstrtab STRTAB 00000000 [[:xdigit:]]+ [[:xdigit:]]+ 00 0 0 1
+- \[17\] .symtab SYMTAB 00000000 [[:xdigit:]]+ [[:xdigit:]]+ 10 18 15 4
+- \[18\] .strtab STRTAB 00000000 [[:xdigit:]]+ [[:xdigit:]]+ 00 0 0 1
++ \[16\] .symtab SYMTAB 00000000 [[:xdigit:]]+ [[:xdigit:]]+ 10 17 15 4
++ \[17\] .strtab STRTAB 00000000 [[:xdigit:]]+ [[:xdigit:]]+ 00 0 0 1
++ \[18\] .shstrtab STRTAB 00000000 [[:xdigit:]]+ [[:xdigit:]]+ 00 0 0 1
+ #pass
+diff --git a/gas/testsuite/gas/ia64/xdata.d b/gas/testsuite/gas/ia64/xdata.d
+index dc23b78..eb12819 100644
+--- a/gas/testsuite/gas/ia64/xdata.d
++++ b/gas/testsuite/gas/ia64/xdata.d
+@@ -38,10 +38,10 @@ Section Headers:
+ 0000000000000003 0000000000000000 A 0 0 1
+ \[15\] \.xstr\{2\} PROGBITS 0000000000000000 [[:xdigit:]]+
+ 0000000000000004 0000000000000000 A 0 0 1
+- \[16\] \.shstrtab STRTAB 0000000000000000 [[:xdigit:]]+
++ \[16\] \.symtab SYMTAB 0000000000000000 [[:xdigit:]]+
++ [[:xdigit:]]+ 0000000000000018 17 15 8
++ \[17\] \.strtab STRTAB 0000000000000000 [[:xdigit:]]+
+ [[:xdigit:]]+ 0000000000000000 0 0 1
+- \[17\] \.symtab SYMTAB 0000000000000000 [[:xdigit:]]+
+- [[:xdigit:]]+ 0000000000000018 18 15 8
+- \[18\] \.strtab STRTAB 0000000000000000 [[:xdigit:]]+
++ \[18\] \.shstrtab STRTAB 0000000000000000 [[:xdigit:]]+
+ [[:xdigit:]]+ 0000000000000000 0 0 1
+ #pass
+diff --git a/gas/testsuite/gas/mmix/bspec-1.d b/gas/testsuite/gas/mmix/bspec-1.d
+index a18d242..4bbda8d 100644
+--- a/gas/testsuite/gas/mmix/bspec-1.d
++++ b/gas/testsuite/gas/mmix/bspec-1.d
+@@ -4,7 +4,7 @@ There are 9 section headers, starting at offset .*:
+ +\[ 4\] \.MMIX\.spec_data\.2 +PROGBITS +0+ +0+44
+ +0+4 +0+ +0 +0 +4
+ +\[ 5\] \.rela\.MMIX\.spec_d +RELA +0+ +.*
+- +0+18 +0+18 +I +7 +4 +8
++ +0+18 +0+18 +I +6 +4 +8
+ #...
+ Relocation section '\.rela\.MMIX\.spec_data\.2' at offset 0x[0-9a-f]+ contains 1 entries:
+ .*
+diff --git a/gas/testsuite/gas/mmix/bspec-2.d b/gas/testsuite/gas/mmix/bspec-2.d
+index a9ce03d..ab3afd3 100644
+--- a/gas/testsuite/gas/mmix/bspec-2.d
++++ b/gas/testsuite/gas/mmix/bspec-2.d
+@@ -4,11 +4,11 @@ There are 11 section headers, starting at offset .*:
+ \[ 4\] \.MMIX\.spec_data\.2 PROGBITS 0+ 0+48
+ 0+10 0+ 0 0 8
+ \[ 5\] \.rela\.MMIX\.spec_d RELA 0+ .*
+- +0+30 0+18 +I +9 +4 +8
++ +0+30 0+18 +I +8 +4 +8
+ \[ 6\] \.MMIX\.spec_data\.3 PROGBITS 0+ 0+58
+ 0+8 0+ 0 0 8
+ \[ 7\] \.rela\.MMIX\.spec_d RELA 0+ .*
+- +0+18 +0+18 +I +9 +6 +8
++ +0+18 +0+18 +I +8 +6 +8
+ #...
+ Relocation section '\.rela\.MMIX\.spec_data\.2' at offset .* contains 2 entries:
+ .*
+diff --git a/gas/testsuite/gas/mmix/byte-1.d b/gas/testsuite/gas/mmix/byte-1.d
+index b6c2768..a77eb08 100644
+--- a/gas/testsuite/gas/mmix/byte-1.d
++++ b/gas/testsuite/gas/mmix/byte-1.d
+@@ -12,12 +12,12 @@ Section Headers:
+ +0000000000000000 +0000000000000000 +WA +0 +0 +1
+ +\[ 3\] \.bss +NOBITS +0000000000000000 +00000056
+ +0000000000000000 +0000000000000000 +WA +0 +0 +1
+- +\[ 4\] \.shstrtab +STRTAB +0000000000000000 +[0-9a-f]+
+- +000000000000002c +0000000000000000 +0 +0 +1
+- +\[ 5\] \.symtab +SYMTAB +0000000000000000 .*
+- +00000000000000c0 +0000000000000018 +6 +7 +8
+- +\[ 6\] \.strtab +STRTAB +0000000000000000 .*
++ +\[ 4\] \.symtab +SYMTAB +0000000000000000 .*
++ +00000000000000c0 +0000000000000018 +5 +7 +8
++ +\[ 5\] \.strtab +STRTAB +0000000000000000 .*
+ +0000000000000018 +0000000000000000 +0 +0 +1
++ +\[ 6\] \.shstrtab +STRTAB +0000000000000000 +[0-9a-f]+
++ +000000000000002c +0000000000000000 +0 +0 +1
+ Key to Flags:
+ #...
+
+diff --git a/gas/testsuite/gas/mmix/loc-1.d b/gas/testsuite/gas/mmix/loc-1.d
+index e45b1d5..e46247d 100644
+--- a/gas/testsuite/gas/mmix/loc-1.d
++++ b/gas/testsuite/gas/mmix/loc-1.d
+@@ -13,12 +13,12 @@ Section Headers:
+ +0000000000000004 +0000000000000000 +WA +0 +0 +4
+ +\[ 3\] \.bss +NOBITS +0000000000000000 +00000064
+ +0000000000000000 +0000000000000000 +WA +0 +0 +1
+- +\[ 4\] \.shstrtab +STRTAB +0000000000000000 +[0-9a-f]+
+- +000000000000002c +0000000000000000 +0 +0 +1
+- +\[ 5\] \.symtab +SYMTAB +0000000000000000 .*
+- +00000000000000c0 +0000000000000018 +6 +6 +8
+- +\[ 6\] \.strtab +STRTAB +0000000000000000 .*
++ +\[ 4\] \.symtab +SYMTAB +0000000000000000 .*
++ +00000000000000c0 +0000000000000018 +5 +6 +8
++ +\[ 5\] \.strtab +STRTAB +0000000000000000 .*
+ +000000000000002a +0000000000000000 +0 +0 +1
++ +\[ 6\] \.shstrtab +STRTAB +0000000000000000 +[0-9a-f]+
++ +000000000000002c +0000000000000000 +0 +0 +1
+ Key to Flags:
+ #...
+
+diff --git a/gas/testsuite/gas/mmix/loc-2.d b/gas/testsuite/gas/mmix/loc-2.d
+index b92cabb..8d7ec8b 100644
+--- a/gas/testsuite/gas/mmix/loc-2.d
++++ b/gas/testsuite/gas/mmix/loc-2.d
+@@ -13,12 +13,12 @@ Section Headers:
+ +0000000000000000 +0000000000000000 +WA +0 +0 +1
+ +\[ 3\] \.bss +NOBITS +0000000000000000 +00000048
+ +0000000000000000 +0000000000000000 +WA +0 +0 +1
+- +\[ 4\] \.shstrtab +STRTAB +0000000000000000 +[0-9a-f]+
+- +000000000000002c +0000000000000000 +0 +0 +1
+- +\[ 5\] \.symtab +SYMTAB +0000000000000000 .*
+- +0000000000000090 +0000000000000018 +6 +4 +8
+- +\[ 6\] \.strtab +STRTAB +0000000000000000 .*
++ +\[ 4\] \.symtab +SYMTAB +0000000000000000 .*
++ +0000000000000090 +0000000000000018 +5 +4 +8
++ +\[ 5\] \.strtab +STRTAB +0000000000000000 .*
+ +000000000000001a +0000000000000000 +0 +0 +1
++ +\[ 6\] \.shstrtab +STRTAB +0000000000000000 +[0-9a-f]+
++ +000000000000002c +0000000000000000 +0 +0 +1
+ Key to Flags:
+ #...
+
+diff --git a/gas/testsuite/gas/mmix/loc-3.d b/gas/testsuite/gas/mmix/loc-3.d
+index 2c477db..14a68fa 100644
+--- a/gas/testsuite/gas/mmix/loc-3.d
++++ b/gas/testsuite/gas/mmix/loc-3.d
+@@ -12,12 +12,12 @@ Section Headers:
+ +0000000000000008 +0000000000000000 +WA +0 +0 +4
+ +\[ 3\] \.bss +NOBITS +0000000000000000 +00000054
+ +0000000000000000 +0000000000000000 +WA +0 +0 +1
+- +\[ 4\] \.shstrtab +STRTAB +0000000000000000 +[0-9a-f]+
+- +000000000000002c +0000000000000000 +0 +0 +1
+- +\[ 5\] \.symtab +SYMTAB +0000000000000000 .*
+- +00000000000000c0 +0000000000000018 +6 +5 +8
+- +\[ 6\] \.strtab +STRTAB +0000000000000000 .*
++ +\[ 4\] \.symtab +SYMTAB +0000000000000000 .*
++ +00000000000000c0 +0000000000000018 +5 +5 +8
++ +\[ 5\] \.strtab +STRTAB +0000000000000000 .*
+ +000000000000002e +0000000000000000 +0 +0 +1
++ +\[ 6\] \.shstrtab +STRTAB +0000000000000000 +[0-9a-f]+
++ +000000000000002c +0000000000000000 +0 +0 +1
+ Key to Flags:
+ #...
+
+diff --git a/gas/testsuite/gas/mmix/loc-4.d b/gas/testsuite/gas/mmix/loc-4.d
+index 1efc084..935cc18 100644
+--- a/gas/testsuite/gas/mmix/loc-4.d
++++ b/gas/testsuite/gas/mmix/loc-4.d
+@@ -12,12 +12,12 @@ Section Headers:
+ +0000000000000004 +0000000000000000 +WA +0 +0 +4
+ +\[ 3\] \.bss +NOBITS +0000000000000000 +0000005c
+ +0000000000000000 +0000000000000000 +WA +0 +0 +1
+- +\[ 4\] \.shstrtab +STRTAB +0000000000000000 +[0-9a-f]+
+- +000000000000002c +0000000000000000 +0 +0 +1
+- +\[ 5\] \.symtab +SYMTAB +0000000000000000 .*
+- +00000000000000c0 +0000000000000018 +6 +5 +8
+- +\[ 6\] \.strtab +STRTAB +0000000000000000 .*
++ +\[ 4\] \.symtab +SYMTAB +0000000000000000 .*
++ +00000000000000c0 +0000000000000018 +5 +5 +8
++ +\[ 5\] \.strtab +STRTAB +0000000000000000 .*
+ +000000000000003b +0000000000000000 +0 +0 +1
++ +\[ 6\] \.shstrtab +STRTAB +0000000000000000 +[0-9a-f]+
++ +000000000000002c +0000000000000000 +0 +0 +1
+ Key to Flags:
+ #...
+
+diff --git a/gas/testsuite/gas/mmix/loc-5.d b/gas/testsuite/gas/mmix/loc-5.d
+index fa80a86..a8e7545 100644
+--- a/gas/testsuite/gas/mmix/loc-5.d
++++ b/gas/testsuite/gas/mmix/loc-5.d
+@@ -12,12 +12,12 @@ Section Headers:
+ +0+24 +0+ +WA +0 +0 +4
+ +\[ 3\] \.bss +NOBITS +0+ +0+6c
+ +0+ +0+ +WA +0 +0 +1
+- +\[ 4\] \.shstrtab +STRTAB +0+ +[0-9a-f]+
+- +0+2c +0+ +0 +0 +1
+- +\[ 5\] \.symtab +SYMTAB +0+ .*
+- +0+c0 +0+18 +6 +6 +8
+- +\[ 6\] \.strtab +STRTAB +0+ .*
++ +\[ 4\] \.symtab +SYMTAB +0+ .*
++ +0+c0 +0+18 +5 +6 +8
++ +\[ 5\] \.strtab +STRTAB +0+ .*
+ +0+27 +0+ +0 +0 +1
++ +\[ 6\] \.shstrtab +STRTAB +0+ +[0-9a-f]+
++ +0+2c +0+ +0 +0 +1
+ Key to Flags:
+ #...
+
+diff --git a/gas/testsuite/gas/tic6x/scomm-directive-4.d b/gas/testsuite/gas/tic6x/scomm-directive-4.d
+index 7822e8f..219673d 100644
+--- a/gas/testsuite/gas/tic6x/scomm-directive-4.d
++++ b/gas/testsuite/gas/tic6x/scomm-directive-4.d
+@@ -12,9 +12,9 @@ Section Headers:
+ \[ 2\] \.data PROGBITS 00000000 000034 000000 00 WA 0 0 1
+ \[ 3\] \.bss NOBITS 00000000 000034 000000 00 WA 0 0 1
+ \[ 4\] \.c6xabi\.attribute C6000_ATTRIBUTE 00000000 000034 000013 00 0 0 1
+- \[ 5\] \.shstrtab STRTAB 00000000 [0-9a-f]+ 00003f 00 0 0 1
+- \[ 6\] \.symtab SYMTAB 00000000 [0-9a-f]+ 0000d0 10 7 5 4
+- \[ 7\] \.strtab STRTAB 00000000 [0-9a-f]+ 00001d 00 0 0 1
++ \[ 5\] \.symtab SYMTAB 00000000 [0-9a-f]+ 0000d0 10 6 5 4
++ \[ 6\] \.strtab STRTAB 00000000 [0-9a-f]+ 00001d 00 0 0 1
++ \[ 7\] \.shstrtab STRTAB 00000000 [0-9a-f]+ 00003f 00 0 0 1
+ Key to Flags:
+ #...
+
+diff --git a/ld/testsuite/ld-alpha/tlsbin.rd b/ld/testsuite/ld-alpha/tlsbin.rd
+index 2184e5e..21fb11a 100644
+--- a/ld/testsuite/ld-alpha/tlsbin.rd
++++ b/ld/testsuite/ld-alpha/tlsbin.rd
+@@ -24,9 +24,9 @@ Section Headers:
+ +\[[ 0-9]+\] .tbss +NOBITS +[0-9a-f]+ [0-9a-f]+ [0-9a-f]+ 00 WAT +0 +0 +1
+ +\[[ 0-9]+\] .dynamic +DYNAMIC +[0-9a-f]+ [0-9a-f]+ [0-9a-f]+ 10 +WA +4 +0 +8
+ +\[[ 0-9]+\] .got +PROGBITS +[0-9a-f]+ [0-9a-f]+ [0-9a-f]+ 00 +WA +0 +0 +8
+- +\[[ 0-9]+\] .shstrtab +.*
+ +\[[ 0-9]+\] .symtab +.*
+ +\[[ 0-9]+\] .strtab +.*
++ +\[[ 0-9]+\] .shstrtab +.*
+ #...
+
+ Elf file type is EXEC \(Executable file\)
+diff --git a/ld/testsuite/ld-alpha/tlsbinr.rd b/ld/testsuite/ld-alpha/tlsbinr.rd
+index 0329ba9..8b7b76a 100644
+--- a/ld/testsuite/ld-alpha/tlsbinr.rd
++++ b/ld/testsuite/ld-alpha/tlsbinr.rd
+@@ -24,9 +24,9 @@ Section Headers:
+ +\[[ 0-9]+\] \.tbss +NOBITS +[0-9a-f]+ [0-9a-f]+ [0-9a-f]+ 0+ WAT +0 +0 +1
+ +\[[ 0-9]+\] \.dynamic +DYNAMIC +[0-9a-f]+ [0-9a-f]+ [0-9a-f]+ 10 +WA +4 +0 +8
+ +\[[ 0-9]+\] \.got +PROGBITS +[0-9a-f]+ [0-9a-f]+ [0-9a-f]+ 0+ +WA +0 +0 +8
+- +\[[ 0-9]+\] \.shstrtab +.*
+ +\[[ 0-9]+\] \.symtab +.*
+ +\[[ 0-9]+\] \.strtab +.*
++ +\[[ 0-9]+\] \.shstrtab +.*
+ #...
+
+ Elf file type is EXEC \(Executable file\)
+diff --git a/ld/testsuite/ld-alpha/tlspic.rd b/ld/testsuite/ld-alpha/tlspic.rd
+index 7a97847..f1fb974 100644
+--- a/ld/testsuite/ld-alpha/tlspic.rd
++++ b/ld/testsuite/ld-alpha/tlspic.rd
+@@ -23,9 +23,9 @@ Section Headers:
+ +\[[ 0-9]+\] .tbss +NOBITS +[0-9a-f]+ [0-9a-f]+ [0-9a-f]+ 0+ WAT +0 +0 +1
+ +\[[ 0-9]+\] .dynamic +DYNAMIC +[0-9a-f]+ [0-9a-f]+ [0-9a-f]+ 10 +WA +3 +0 +8
+ +\[[ 0-9]+\] .got +PROGBITS +[0-9a-f]+ [0-9a-f]+ [0-9a-f]+ 0+ +WA +0 +0 +8
+- +\[[ 0-9]+\] .shstrtab +.*
+ +\[[ 0-9]+\] .symtab +.*
+ +\[[ 0-9]+\] .strtab +.*
++ +\[[ 0-9]+\] .shstrtab +.*
+ #...
+
+ Elf file type is DYN \(Shared object file\)
+diff --git a/ld/testsuite/ld-cris/libdso-2.d b/ld/testsuite/ld-cris/libdso-2.d
+index 3b4777a..aa4a7c8 100644
+--- a/ld/testsuite/ld-cris/libdso-2.d
++++ b/ld/testsuite/ld-cris/libdso-2.d
+@@ -21,9 +21,9 @@ There are 13 section headers.*
+ +\[ 7\] \.text +PROGBITS .*
+ +\[ 8\] \.dynamic +DYNAMIC +.*
+ +\[ 9\] \.got +PROGBITS .*
+- +\[10\] \.shstrtab +STRTAB +.*
+- +\[11\] \.symtab +SYMTAB +.*
+- +\[12\] \.strtab +STRTAB +.*
++ +\[10\] \.symtab +SYMTAB +.*
++ +\[11\] \.strtab +STRTAB +.*
++ +\[12\] \.shstrtab +STRTAB +.*
+ #...
+ Relocation section '\.rela\.dyn' at offset 0x[0-9a-f]+ contains 1 entries:
+ #...
+diff --git a/ld/testsuite/ld-i386/nogot1.d b/ld/testsuite/ld-i386/nogot1.d
+index a6c8832..018c24d 100644
+--- a/ld/testsuite/ld-i386/nogot1.d
++++ b/ld/testsuite/ld-i386/nogot1.d
+@@ -4,5 +4,6 @@
+
+ #...
+ [ ]*\[.*\][ ]+\.dynamic[ ]+DYNAMIC.*
++#...
+ [ ]*\[.*\][ ]+.*STRTAB.*
+ #pass
+diff --git a/ld/testsuite/ld-i386/pr12718.d b/ld/testsuite/ld-i386/pr12718.d
+index 87905c3..ec51540 100644
+--- a/ld/testsuite/ld-i386/pr12718.d
++++ b/ld/testsuite/ld-i386/pr12718.d
+@@ -9,8 +9,8 @@ Section Headers:
+ +\[Nr\] Name +Type +Addr +Off +Size +ES +Flg +Lk +Inf +Al
+ +\[ 0\] +NULL +0+ +0+ +0+ +0+ +0 +0 +0
+ +\[ 1\] +.text +PROGBITS +[0-9a-f]+ +[0-9a-f]+ +000006 00 +AX +0 +0 +1
+- +\[ 2\] +.shstrtab +STRTAB +0+ +[0-9a-f]+ +[0-9a-f]+ +0+ +0 +0 +1
+- +\[ 3\] +.symtab +SYMTAB +0+ +[0-9a-f]+ +[0-9a-f]+ 10 +4 +[0-9] +4
+- +\[ 4\] +.strtab +STRTAB +0+ +[0-9a-f]+ +[0-9a-f]+ 00 +0 +0 +1
++ +\[ 2\] +.symtab +SYMTAB +0+ +[0-9a-f]+ +[0-9a-f]+ 10 +3 +[0-9] +4
++ +\[ 3\] +.strtab +STRTAB +0+ +[0-9a-f]+ +[0-9a-f]+ 00 +0 +0 +1
++ +\[ 4\] +.shstrtab +STRTAB +0+ +[0-9a-f]+ +[0-9a-f]+ +0+ +0 +0 +1
+ Key to Flags:
+ #pass
+diff --git a/ld/testsuite/ld-i386/pr12921.d b/ld/testsuite/ld-i386/pr12921.d
+index c72b04c..e49079b 100644
+--- a/ld/testsuite/ld-i386/pr12921.d
++++ b/ld/testsuite/ld-i386/pr12921.d
+@@ -11,8 +11,8 @@ Section Headers:
+ +\[ 1\] .text +PROGBITS +[0-9a-f]+ +[0-9a-f]+ +0+1 00 +AX +0 +0 +4096
+ +\[ 2\] .data +PROGBITS +[0-9a-f]+ +[0-9a-f]+000 +0+20 +00 +WA +0 +0 +4096
+ +\[ 3\] .bss +NOBITS +[0-9a-f]+ +[0-9a-f]+020 +0+10000 +00 +WA +0 +0 +4096
+- +\[ 4\] .shstrtab +STRTAB +0+ +[0-9a-f]+ +0+2c +00 +0 +0 +1
+- +\[ 5\] .symtab +SYMTAB +0+ +[0-9a-f]+ +[0-9a-f]+ +10 +6 +[0-9] +4
+- +\[ 6\] .strtab +STRTAB +0+ +[0-9a-f]+ +[0-9a-f]+ +00 +0 +0 +1
++ +\[ 4\] .symtab +SYMTAB +0+ +[0-9a-f]+ +[0-9a-f]+ +10 +5 +[0-9] +4
++ +\[ 5\] .strtab +STRTAB +0+ +[0-9a-f]+ +[0-9a-f]+ +00 +0 +0 +1
++ +\[ 6\] .shstrtab +STRTAB +0+ +[0-9a-f]+ +0+2c +00 +0 +0 +1
+ Key to Flags:
+ #pass
+diff --git a/ld/testsuite/ld-i386/tlsbin-nacl.rd b/ld/testsuite/ld-i386/tlsbin-nacl.rd
+index 1e1cf7c..89a0673 100644
+--- a/ld/testsuite/ld-i386/tlsbin-nacl.rd
++++ b/ld/testsuite/ld-i386/tlsbin-nacl.rd
+@@ -23,9 +23,9 @@ Section Headers:
+ +\[[ 0-9]+\] \.dynamic +DYNAMIC +0*10031060 .*
+ +\[[ 0-9]+\] \.got +PROGBITS +0*10031100 .*
+ +\[[ 0-9]+\] \.got\.plt +PROGBITS +0*10031124 .*
+- +\[[ 0-9]+\] \.shstrtab +.*
+ +\[[ 0-9]+\] \.symtab +.*
+ +\[[ 0-9]+\] \.strtab +.*
++ +\[[ 0-9]+\] \.shstrtab +.*
+ Key to Flags:
+ #...
+
+diff --git a/ld/testsuite/ld-i386/tlsbin.rd b/ld/testsuite/ld-i386/tlsbin.rd
+index 12b3e81..23fffd1 100644
+--- a/ld/testsuite/ld-i386/tlsbin.rd
++++ b/ld/testsuite/ld-i386/tlsbin.rd
+@@ -23,9 +23,9 @@ Section Headers:
+ +\[[ 0-9]+\] \.dynamic +DYNAMIC +0+804a060 .*
+ +\[[ 0-9]+\] \.got +PROGBITS +0+804a100 .*
+ +\[[ 0-9]+\] \.got\.plt +PROGBITS +0+804a124 .*
+- +\[[ 0-9]+\] \.shstrtab +.*
+ +\[[ 0-9]+\] \.symtab +.*
+ +\[[ 0-9]+\] \.strtab +.*
++ +\[[ 0-9]+\] \.shstrtab +.*
+ Key to Flags:
+ #...
+
+diff --git a/ld/testsuite/ld-i386/tlsbin2-nacl.rd b/ld/testsuite/ld-i386/tlsbin2-nacl.rd
+index b23bfe0..0011716 100644
+--- a/ld/testsuite/ld-i386/tlsbin2-nacl.rd
++++ b/ld/testsuite/ld-i386/tlsbin2-nacl.rd
+@@ -21,9 +21,9 @@ Section Headers:
+ +\[[ 0-9]+\] \.dynamic +DYNAMIC +0*10031060 .*
+ +\[[ 0-9]+\] \.got +PROGBITS +0*100310e0 .*
+ +\[[ 0-9]+\] \.got\.plt +PROGBITS +0*10031108 .*
+- +\[[ 0-9]+\] \.shstrtab +.*
+ +\[[ 0-9]+\] \.symtab +.*
+ +\[[ 0-9]+\] \.strtab +.*
++ +\[[ 0-9]+\] \.shstrtab +.*
+ Key to Flags:
+ #...
+
+diff --git a/ld/testsuite/ld-i386/tlsbin2.rd b/ld/testsuite/ld-i386/tlsbin2.rd
+index 05d4ddb..e34d167 100644
+--- a/ld/testsuite/ld-i386/tlsbin2.rd
++++ b/ld/testsuite/ld-i386/tlsbin2.rd
+@@ -21,9 +21,9 @@ Section Headers:
+ +\[[ 0-9]+\] \.dynamic +DYNAMIC +0+804a060 .*
+ +\[[ 0-9]+\] \.got +PROGBITS +0+804a0e0 .*
+ +\[[ 0-9]+\] \.got\.plt +PROGBITS +0+804a108 .*
+- +\[[ 0-9]+\] \.shstrtab +.*
+ +\[[ 0-9]+\] \.symtab +.*
+ +\[[ 0-9]+\] \.strtab +.*
++ +\[[ 0-9]+\] \.shstrtab +.*
+ Key to Flags:
+ #...
+
+diff --git a/ld/testsuite/ld-i386/tlsbindesc-nacl.rd b/ld/testsuite/ld-i386/tlsbindesc-nacl.rd
+index 51cffc0..39c60a5 100644
+--- a/ld/testsuite/ld-i386/tlsbindesc-nacl.rd
++++ b/ld/testsuite/ld-i386/tlsbindesc-nacl.rd
+@@ -21,9 +21,9 @@ Section Headers:
+ +\[[ 0-9]+\] \.dynamic +DYNAMIC +0*10031060 .*
+ +\[[ 0-9]+\] \.got +PROGBITS +0*100310e0 .*
+ +\[[ 0-9]+\] \.got\.plt +PROGBITS +0*10031104 .*
+- +\[[ 0-9]+\] \.shstrtab +.*
+ +\[[ 0-9]+\] \.symtab +.*
+ +\[[ 0-9]+\] \.strtab +.*
++ +\[[ 0-9]+\] \.shstrtab +.*
+ Key to Flags:
+ #...
+
+diff --git a/ld/testsuite/ld-i386/tlsbindesc.rd b/ld/testsuite/ld-i386/tlsbindesc.rd
+index 7f7194c..7cc85f1 100644
+--- a/ld/testsuite/ld-i386/tlsbindesc.rd
++++ b/ld/testsuite/ld-i386/tlsbindesc.rd
+@@ -21,9 +21,9 @@ Section Headers:
+ +\[[ 0-9]+\] \.dynamic +DYNAMIC +0+804a060 .*
+ +\[[ 0-9]+\] \.got +PROGBITS +0+804a0e0 .*
+ +\[[ 0-9]+\] \.got\.plt +PROGBITS +0+804a104 .*
+- +\[[ 0-9]+\] \.shstrtab +.*
+ +\[[ 0-9]+\] \.symtab +.*
+ +\[[ 0-9]+\] \.strtab +.*
++ +\[[ 0-9]+\] \.shstrtab +.*
+ Key to Flags:
+ #...
+
+diff --git a/ld/testsuite/ld-i386/tlsdesc-nacl.rd b/ld/testsuite/ld-i386/tlsdesc-nacl.rd
+index b28744f..20c8ea2 100644
+--- a/ld/testsuite/ld-i386/tlsdesc-nacl.rd
++++ b/ld/testsuite/ld-i386/tlsdesc-nacl.rd
+@@ -21,9 +21,9 @@ Section Headers:
+ +\[[ 0-9]+\] \.dynamic +.*
+ +\[[ 0-9]+\] \.got +.*
+ +\[[ 0-9]+\] \.got.plt +.*
+- +\[[ 0-9]+\] \.shstrtab +.*
+ +\[[ 0-9]+\] \.symtab +.*
+ +\[[ 0-9]+\] \.strtab +.*
++ +\[[ 0-9]+\] \.shstrtab +.*
+ Key to Flags:
+ #...
+
+diff --git a/ld/testsuite/ld-i386/tlsdesc.rd b/ld/testsuite/ld-i386/tlsdesc.rd
+index 68695ff..3486847 100644
+--- a/ld/testsuite/ld-i386/tlsdesc.rd
++++ b/ld/testsuite/ld-i386/tlsdesc.rd
+@@ -21,9 +21,9 @@ Section Headers:
+ +\[[ 0-9]+\] \.dynamic +.*
+ +\[[ 0-9]+\] \.got +.*
+ +\[[ 0-9]+\] \.got.plt +.*
+- +\[[ 0-9]+\] \.shstrtab +.*
+ +\[[ 0-9]+\] \.symtab +.*
+ +\[[ 0-9]+\] \.strtab +.*
++ +\[[ 0-9]+\] \.shstrtab +.*
+ Key to Flags:
+ #...
+
+diff --git a/ld/testsuite/ld-i386/tlsgdesc-nacl.rd b/ld/testsuite/ld-i386/tlsgdesc-nacl.rd
+index ba5fa62..407bf2c 100644
+--- a/ld/testsuite/ld-i386/tlsgdesc-nacl.rd
++++ b/ld/testsuite/ld-i386/tlsgdesc-nacl.rd
+@@ -19,9 +19,9 @@ Section Headers:
+ +\[[ 0-9]+\] \.dynamic +.*
+ +\[[ 0-9]+\] \.got +.*
+ +\[[ 0-9]+\] \.got.plt +.*
+- +\[[ 0-9]+\] \.shstrtab +.*
+ +\[[ 0-9]+\] \.symtab +.*
+ +\[[ 0-9]+\] \.strtab +.*
++ +\[[ 0-9]+\] \.shstrtab +.*
+ Key to Flags:
+ #...
+
+diff --git a/ld/testsuite/ld-i386/tlsgdesc.rd b/ld/testsuite/ld-i386/tlsgdesc.rd
+index 929ffa2..269cede 100644
+--- a/ld/testsuite/ld-i386/tlsgdesc.rd
++++ b/ld/testsuite/ld-i386/tlsgdesc.rd
+@@ -19,9 +19,9 @@ Section Headers:
+ +\[[ 0-9]+\] \.dynamic +.*
+ +\[[ 0-9]+\] \.got +.*
+ +\[[ 0-9]+\] \.got.plt +.*
+- +\[[ 0-9]+\] \.shstrtab +.*
+ +\[[ 0-9]+\] \.symtab +.*
+ +\[[ 0-9]+\] \.strtab +.*
++ +\[[ 0-9]+\] \.shstrtab +.*
+ Key to Flags:
+ #...
+
+diff --git a/ld/testsuite/ld-i386/tlsnopic-nacl.rd b/ld/testsuite/ld-i386/tlsnopic-nacl.rd
+index b14164a..15e7eea 100644
+--- a/ld/testsuite/ld-i386/tlsnopic-nacl.rd
++++ b/ld/testsuite/ld-i386/tlsnopic-nacl.rd
+@@ -19,9 +19,9 @@ Section Headers:
+ +\[[ 0-9]+\] \.dynamic +DYNAMIC +0*10010284 .*
+ +\[[ 0-9]+\] \.got +PROGBITS +0*10010304 .*
+ +\[[ 0-9]+\] \.got.plt +PROGBITS +0*1001031c .*
+- +\[[ 0-9]+\] \.shstrtab +.*
+ +\[[ 0-9]+\] \.symtab +.*
+ +\[[ 0-9]+\] \.strtab +.*
++ +\[[ 0-9]+\] \.shstrtab +.*
+ Key to Flags:
+ #...
+
+diff --git a/ld/testsuite/ld-i386/tlsnopic.rd b/ld/testsuite/ld-i386/tlsnopic.rd
+index b754158..b60fb1d 100644
+--- a/ld/testsuite/ld-i386/tlsnopic.rd
++++ b/ld/testsuite/ld-i386/tlsnopic.rd
+@@ -19,9 +19,9 @@ Section Headers:
+ +\[[ 0-9]+\] \.dynamic +DYNAMIC +0+20f4 .*
+ +\[[ 0-9]+\] \.got +PROGBITS +0+2174 .*
+ +\[[ 0-9]+\] \.got.plt +PROGBITS +0+218c .*
+- +\[[ 0-9]+\] \.shstrtab +.*
+ +\[[ 0-9]+\] \.symtab +.*
+ +\[[ 0-9]+\] \.strtab +.*
++ +\[[ 0-9]+\] \.shstrtab +.*
+ Key to Flags:
+ #...
+
+diff --git a/ld/testsuite/ld-i386/tlspic-nacl.rd b/ld/testsuite/ld-i386/tlspic-nacl.rd
+index b7d3e35..9645e35 100644
+--- a/ld/testsuite/ld-i386/tlspic-nacl.rd
++++ b/ld/testsuite/ld-i386/tlspic-nacl.rd
+@@ -22,9 +22,9 @@ Section Headers:
+ +\[[ 0-9]+\] \.dynamic +.*
+ +\[[ 0-9]+\] \.got +.*
+ +\[[ 0-9]+\] \.got.plt +.*
+- +\[[ 0-9]+\] \.shstrtab +.*
+ +\[[ 0-9]+\] \.symtab +.*
+ +\[[ 0-9]+\] \.strtab +.*
++ +\[[ 0-9]+\] \.shstrtab +.*
+ Key to Flags:
+ #...
+
+diff --git a/ld/testsuite/ld-i386/tlspic.rd b/ld/testsuite/ld-i386/tlspic.rd
+index f693760..6b915e5 100644
+--- a/ld/testsuite/ld-i386/tlspic.rd
++++ b/ld/testsuite/ld-i386/tlspic.rd
+@@ -22,9 +22,9 @@ Section Headers:
+ +\[[ 0-9]+\] \.dynamic +.*
+ +\[[ 0-9]+\] \.got +.*
+ +\[[ 0-9]+\] \.got.plt +.*
+- +\[[ 0-9]+\] \.shstrtab +.*
+ +\[[ 0-9]+\] \.symtab +.*
+ +\[[ 0-9]+\] \.strtab +.*
++ +\[[ 0-9]+\] \.shstrtab +.*
+ Key to Flags:
+ #...
+
+diff --git a/ld/testsuite/ld-i386/tlspic2-nacl.rd b/ld/testsuite/ld-i386/tlspic2-nacl.rd
+index 560e840..5fb6ba6 100644
+--- a/ld/testsuite/ld-i386/tlspic2-nacl.rd
++++ b/ld/testsuite/ld-i386/tlspic2-nacl.rd
+@@ -20,9 +20,9 @@ Section Headers:
+ +\[[ 0-9]+\] \.dynamic +.*
+ +\[[ 0-9]+\] \.got +.*
+ +\[[ 0-9]+\] \.got.plt +.*
+- +\[[ 0-9]+\] \.shstrtab +.*
+ +\[[ 0-9]+\] \.symtab +.*
+ +\[[ 0-9]+\] \.strtab +.*
++ +\[[ 0-9]+\] \.shstrtab +.*
+ Key to Flags:
+ #...
+
+diff --git a/ld/testsuite/ld-i386/tlspic2.rd b/ld/testsuite/ld-i386/tlspic2.rd
+index a135547..ab00063 100644
+--- a/ld/testsuite/ld-i386/tlspic2.rd
++++ b/ld/testsuite/ld-i386/tlspic2.rd
+@@ -20,9 +20,9 @@ Section Headers:
+ +\[[ 0-9]+\] \.dynamic +.*
+ +\[[ 0-9]+\] \.got +.*
+ +\[[ 0-9]+\] \.got.plt +.*
+- +\[[ 0-9]+\] \.shstrtab +.*
+ +\[[ 0-9]+\] \.symtab +.*
+ +\[[ 0-9]+\] \.strtab +.*
++ +\[[ 0-9]+\] \.shstrtab +.*
+ Key to Flags:
+ #...
+
+diff --git a/ld/testsuite/ld-ia64/tlsbin.rd b/ld/testsuite/ld-ia64/tlsbin.rd
+index ab2dacd..08c6a59 100644
+--- a/ld/testsuite/ld-ia64/tlsbin.rd
++++ b/ld/testsuite/ld-ia64/tlsbin.rd
+@@ -25,9 +25,9 @@ Section Headers:
+ +\[[ 0-9]+\] .dynamic +DYNAMIC +60+1[0-9a-f]+ 0+1[0-9a-f]+ 0+150 10 +WA +4 +0 +8
+ +\[[ 0-9]+\] .got +PROGBITS +60+1318 0+1318 0+48 00 WAp +0 +0 +8
+ +\[[ 0-9]+\] .IA_64.pltoff +.*
+- +\[[ 0-9]+\] .shstrtab +.*
+ +\[[ 0-9]+\] .symtab +.*
+ +\[[ 0-9]+\] .strtab +.*
++ +\[[ 0-9]+\] .shstrtab +.*
+ #...
+
+ Elf file type is EXEC \(Executable file\)
+diff --git a/ld/testsuite/ld-ia64/tlspic.rd b/ld/testsuite/ld-ia64/tlspic.rd
+index 9666f86..cfcf8ed 100644
+--- a/ld/testsuite/ld-ia64/tlspic.rd
++++ b/ld/testsuite/ld-ia64/tlspic.rd
+@@ -24,9 +24,9 @@ Section Headers:
+ +\[[ 0-9]+\] .dynamic +DYNAMIC +0+11[0-9a-f]+ 0+1[0-9a-f]+ 0+140 10 +WA +3 +0 +8
+ +\[[ 0-9]+\] .got +PROGBITS +0+112d8 0+12d8 0+50 00 WAp +0 +0 +8
+ +\[[ 0-9]+\] .IA_64.pltoff +.*
+- +\[[ 0-9]+\] .shstrtab +.*
+ +\[[ 0-9]+\] .symtab +.*
+ +\[[ 0-9]+\] .strtab +.*
++ +\[[ 0-9]+\] .shstrtab +.*
+ Key to Flags:
+ #...
+
+diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-10.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-10.d
+index e3a1c9c..8827e41 100644
+--- a/ld/testsuite/ld-mips-elf/attr-gnu-4-10.d
++++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-10.d
+@@ -22,7 +22,7 @@ ELF Header:
+ Number of program headers: 0
+ Size of section headers: 40 \(bytes\)
+ Number of section headers: 11
+- Section header string table index: 8
++ Section header string table index: 10
+
+ Attribute Section: gnu
+ File Attributes
+diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-50.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-50.d
+index 5dc46d3..1fcab63 100644
+--- a/ld/testsuite/ld-mips-elf/attr-gnu-4-50.d
++++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-50.d
+@@ -22,7 +22,7 @@ ELF Header:
+ Number of program headers: 0
+ Size of section headers: 40 \(bytes\)
+ Number of section headers: 11
+- Section header string table index: 8
++ Section header string table index: 10
+ Attribute Section: gnu
+ File Attributes
+ Tag_GNU_MIPS_ABI_FP: Hard float \(32-bit CPU, Any FPU\)
+diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-60.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-60.d
+index ea80c18..48a9839 100644
+--- a/ld/testsuite/ld-mips-elf/attr-gnu-4-60.d
++++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-60.d
+@@ -22,7 +22,7 @@ ELF Header:
+ Number of program headers: 0
+ Size of section headers: 40 \(bytes\)
+ Number of section headers: 11
+- Section header string table index: 8
++ Section header string table index: 10
+ Attribute Section: gnu
+ File Attributes
+ Tag_GNU_MIPS_ABI_FP: Hard float \(32-bit CPU, 64-bit FPU\)
+diff --git a/ld/testsuite/ld-mips-elf/attr-gnu-4-70.d b/ld/testsuite/ld-mips-elf/attr-gnu-4-70.d
+index edbd61f..ca17421 100644
+--- a/ld/testsuite/ld-mips-elf/attr-gnu-4-70.d
++++ b/ld/testsuite/ld-mips-elf/attr-gnu-4-70.d
+@@ -22,7 +22,7 @@ ELF Header:
+ Number of program headers: 0
+ Size of section headers: 40 \(bytes\)
+ Number of section headers: 11
+- Section header string table index: 8
++ Section header string table index: 10
+ Attribute Section: gnu
+ File Attributes
+ Tag_GNU_MIPS_ABI_FP: Hard float compat \(32-bit CPU, 64-bit FPU\)
+diff --git a/ld/testsuite/ld-mmix/bspec1.d b/ld/testsuite/ld-mmix/bspec1.d
+index 6440bbe..3d07d2d 100644
+--- a/ld/testsuite/ld-mmix/bspec1.d
++++ b/ld/testsuite/ld-mmix/bspec1.d
+@@ -14,12 +14,12 @@ Section Headers:
+ +0+4 +0+ +AX +0 +0 +4
+ +\[ 2\] \.MMIX\.spec_data\.2 PROGBITS +0+ +0+7c
+ +0+4 +0+ +0 +0 +4
+- +\[ 3\] \.shstrtab +STRTAB +0+ +[0-9a-f]+
+- +0+33 +0+ +0 +0 +1
+- +\[ 4\] \.symtab +SYMTAB +0+ .*
+- +0+d8 +0+18 +5 +3 +8
+- +\[ 5\] \.strtab +STRTAB +0+ .*
++ +\[ 3\] \.symtab +SYMTAB +0+ .*
++ +0+d8 +0+18 +4 +3 +8
++ +\[ 4\] \.strtab +STRTAB +0+ .*
+ +0+26 +0+ +0 +0 +1
++ +\[ 5\] \.shstrtab +STRTAB +0+ +[0-9a-f]+
++ +0+33 +0+ +0 +0 +1
+ Key to Flags:
+ #...
+
+diff --git a/ld/testsuite/ld-mmix/bspec2.d b/ld/testsuite/ld-mmix/bspec2.d
+index e881b08..b18fe47 100644
+--- a/ld/testsuite/ld-mmix/bspec2.d
++++ b/ld/testsuite/ld-mmix/bspec2.d
+@@ -19,12 +19,12 @@ Section Headers:
+ +0+8 +0+ +0 +0 +4
+ +\[ 3\] \.MMIX\.spec_data\.3 PROGBITS +0+ +0+84
+ +0+4 +0+ +0 +0 +4
+- +\[ 4\] \.shstrtab +STRTAB +0+ +[0-9a-f]+
+- +0+45 +0+ +0 +0 +1
+- +\[ 5\] \.symtab +SYMTAB +0+ .*
+- +0+108 +0+18 +6 +4 +8
+- +\[ 6\] \.strtab +STRTAB +0+ .*
++ +\[ 4\] \.symtab +SYMTAB +0+ .*
++ +0+108 +0+18 +5 +4 +8
++ +\[ 5\] \.strtab +STRTAB +0+ .*
+ +0+2b +0+ +0 +0 +1
++ +\[ 6\] \.shstrtab +STRTAB +0+ +[0-9a-f]+
++ +0+45 +0+ +0 +0 +1
+ Key to Flags:
+ #...
+
+diff --git a/ld/testsuite/ld-mmix/local1.d b/ld/testsuite/ld-mmix/local1.d
+index 478d17b..41a67c2 100644
+--- a/ld/testsuite/ld-mmix/local1.d
++++ b/ld/testsuite/ld-mmix/local1.d
+@@ -21,12 +21,12 @@ Section Headers:
+ +0+8 +0+ +AX +0 +0 +4
+ +\[ 2\] \.MMIX\.reg_content PROGBITS +0+7e8 +0+80
+ +0+10 +0+ +W +0 +0 +1
+- +\[ 3\] \.shstrtab +STRTAB +0+ +[0-9a-f]+
+- +0+34 +0+ +0 +0 +1
+- +\[ 4\] \.symtab +SYMTAB +0+ +[0-9a-f]+
+- +[0-9a-f]+ +0+18 +5 +[0-9] +8
+- +\[ 5\] \.strtab +STRTAB +0+ +[0-9a-f]+
++ +\[ 3\] \.symtab +SYMTAB +0+ +[0-9a-f]+
++ +[0-9a-f]+ +0+18 +4 +[0-9] +8
++ +\[ 4\] \.strtab +STRTAB +0+ +[0-9a-f]+
+ +[0-9a-f]+ +0+ +0 +0 +1
++ +\[ 5\] \.shstrtab +STRTAB +0+ +[0-9a-f]+
++ +0+34 +0+ +0 +0 +1
+ Key to Flags:
+ #...
+
+diff --git a/ld/testsuite/ld-mmix/local3.d b/ld/testsuite/ld-mmix/local3.d
+index 9b9001a..74840d3 100644
+--- a/ld/testsuite/ld-mmix/local3.d
++++ b/ld/testsuite/ld-mmix/local3.d
+@@ -19,12 +19,12 @@ Section Headers:
+ +0+8 +0+ +AX +0 +0 +4
+ +\[ 2\] \.MMIX\.reg_content PROGBITS +0+7e8 +0+80
+ +0+10 +0+ +W +0 +0 +1
+- +\[ 3\] \.shstrtab +STRTAB +0+ +[0-9a-f]+
+- +0+34 +0+ +0 +0 +1
+- +\[ 4\] \.symtab +SYMTAB +0+ +[0-9a-f]+
+- +[0-9a-f]+ +0+18 +5 +[0-9] +8
+- +\[ 5\] \.strtab +STRTAB +0+ +[0-9a-f]+
++ +\[ 3\] \.symtab +SYMTAB +0+ +[0-9a-f]+
++ +[0-9a-f]+ +0+18 +4 +[0-9] +8
++ +\[ 4\] \.strtab +STRTAB +0+ +[0-9a-f]+
+ +[0-9a-f]+ +0+ +0 +0 +1
++ +\[ 5\] \.shstrtab +STRTAB +0+ +[0-9a-f]+
++ +0+34 +0+ +0 +0 +1
+ Key to Flags:
+ #...
+
+diff --git a/ld/testsuite/ld-mmix/local5.d b/ld/testsuite/ld-mmix/local5.d
+index 93bacd3..ae81364 100644
+--- a/ld/testsuite/ld-mmix/local5.d
++++ b/ld/testsuite/ld-mmix/local5.d
+@@ -20,12 +20,12 @@ Section Headers:
+ +0+c +0+ +AX +0 +0 +4
+ +\[ 2\] \.MMIX\.reg_content PROGBITS +0+7e8 +0+84
+ +0+10 +0+ +W +0 +0 +1
+- +\[ 3\] \.shstrtab +STRTAB +0+ +[0-9a-f]+
+- +0+34 +0+ +0 +0 +1
+- +\[ 4\] \.symtab +SYMTAB +0+ +[0-9a-f]+
+- +[0-9a-f]+ +0+18 +5 +[0-9] +8
+- +\[ 5\] \.strtab +STRTAB +0+ +[0-9a-f]+
++ +\[ 3\] \.symtab +SYMTAB +0+ +[0-9a-f]+
++ +[0-9a-f]+ +0+18 +4 +[0-9] +8
++ +\[ 4\] \.strtab +STRTAB +0+ +[0-9a-f]+
+ +[0-9a-f]+ +0+ +0 +0 +1
++ +\[ 5\] \.shstrtab +STRTAB +0+ +[0-9a-f]+
++ +0+34 +0+ +0 +0 +1
+ Key to Flags:
+ #...
+
+diff --git a/ld/testsuite/ld-mmix/local7.d b/ld/testsuite/ld-mmix/local7.d
+index 1495bf1..6d80cc9 100644
+--- a/ld/testsuite/ld-mmix/local7.d
++++ b/ld/testsuite/ld-mmix/local7.d
+@@ -21,12 +21,12 @@ Section Headers:
+ +0+c +0+ +AX +0 +0 +4
+ +\[ 2\] \.MMIX\.reg_content PROGBITS +0+7e8 +0+84
+ +0+10 +0+ +W +0 +0 +1
+- +\[ 3\] \.shstrtab +STRTAB +0+ +[0-9a-f]+
+- +0+34 +0+ +0 +0 +1
+- +\[ 4\] \.symtab +SYMTAB +0+ +[0-9a-f]+
+- +[0-9a-f]+ +0+18 +5 +[0-9] +8
+- +\[ 5\] \.strtab +STRTAB +0+ +[0-9a-f]+
++ +\[ 3\] \.symtab +SYMTAB +0+ +[0-9a-f]+
++ +[0-9a-f]+ +0+18 +4 +[0-9] +8
++ +\[ 4\] \.strtab +STRTAB +0+ +[0-9a-f]+
+ +[0-9a-f]+ +0+ +0 +0 +1
++ +\[ 5\] \.shstrtab +STRTAB +0+ +[0-9a-f]+
++ +0+34 +0+ +0 +0 +1
+ Key to Flags:
+ #...
+
+diff --git a/ld/testsuite/ld-mmix/undef-3.d b/ld/testsuite/ld-mmix/undef-3.d
+index 94eeeaa..6afb52b 100644
+--- a/ld/testsuite/ld-mmix/undef-3.d
++++ b/ld/testsuite/ld-mmix/undef-3.d
+@@ -11,11 +11,11 @@ Section Headers:
+ +0+ +0+ +0 +0 +0
+ +\[ 1\] \.text +PROGBITS +0+ +0+78
+ +0+4 +0+ +AX +0 +0 +4
+- +\[ 2\] \.shstrtab +STRTAB +0+ +[0-9a-f]+
++ +\[ 2\] \.symtab +SYMTAB +0+ .*
++ +0+a8 +0+18 +3 +2 +8
++ +\[ 3\] \.strtab +STRTAB +0+ .*
+ +0+21 +0+ +0 +0 +1
+- +\[ 3\] \.symtab +SYMTAB +0+ .*
+- +0+a8 +0+18 +4 +2 +8
+- +\[ 4\] \.strtab +STRTAB +0+ .*
++ +\[ 4\] \.shstrtab +STRTAB +0+ +[0-9a-f]+
+ +0+21 +0+ +0 +0 +1
+ Key to Flags:
+ #...
+diff --git a/ld/testsuite/ld-powerpc/tlsexe.r b/ld/testsuite/ld-powerpc/tlsexe.r
+index db72ad7..11da4a8 100644
+--- a/ld/testsuite/ld-powerpc/tlsexe.r
++++ b/ld/testsuite/ld-powerpc/tlsexe.r
+@@ -23,9 +23,9 @@ Section Headers:
+ +\[[ 0-9]+\] \.opd .*
+ +\[[ 0-9]+\] \.got +PROGBITS .* 0+30 08 +WA +0 +0 +256
+ +\[[ 0-9]+\] \.plt +.*
+- +\[[ 0-9]+\] \.shstrtab +.*
+ +\[[ 0-9]+\] \.symtab +.*
+ +\[[ 0-9]+\] \.strtab +.*
++ +\[[ 0-9]+\] \.shstrtab +.*
+ #...
+
+ Elf file type is EXEC \(Executable file\)
+diff --git a/ld/testsuite/ld-powerpc/tlsexetoc.r b/ld/testsuite/ld-powerpc/tlsexetoc.r
+index 56716bb..5c4a490 100644
+--- a/ld/testsuite/ld-powerpc/tlsexetoc.r
++++ b/ld/testsuite/ld-powerpc/tlsexetoc.r
+@@ -23,9 +23,9 @@ Section Headers:
+ +\[[ 0-9]+\] \.opd .*
+ +\[[ 0-9]+\] \.got +PROGBITS .* 0+58 08 +WA +0 +0 +256
+ +\[[ 0-9]+\] \.plt +.*
+- +\[[ 0-9]+\] \.shstrtab +.*
+ +\[[ 0-9]+\] \.symtab +.*
+ +\[[ 0-9]+\] \.strtab +.*
++ +\[[ 0-9]+\] \.shstrtab +.*
+ #...
+
+ Elf file type is EXEC \(Executable file\)
+diff --git a/ld/testsuite/ld-powerpc/tlsso.r b/ld/testsuite/ld-powerpc/tlsso.r
+index fd3002b..4ba6173 100644
+--- a/ld/testsuite/ld-powerpc/tlsso.r
++++ b/ld/testsuite/ld-powerpc/tlsso.r
+@@ -21,9 +21,9 @@ Section Headers:
+ +\[[ 0-9]+\] \.opd .*
+ +\[[ 0-9]+\] \.got .*
+ +\[[ 0-9]+\] \.plt .*
+- +\[[ 0-9]+\] \.shstrtab .*
+ +\[[ 0-9]+\] \.symtab .*
+ +\[[ 0-9]+\] \.strtab .*
++ +\[[ 0-9]+\] \.shstrtab .*
+ #...
+
+ Elf file type is DYN \(Shared object file\)
+diff --git a/ld/testsuite/ld-s390/tlsbin.rd b/ld/testsuite/ld-s390/tlsbin.rd
+index 32c883a..b45fc29 100644
+--- a/ld/testsuite/ld-s390/tlsbin.rd
++++ b/ld/testsuite/ld-s390/tlsbin.rd
+@@ -22,9 +22,9 @@ Section Headers:
+ +\[[ 0-9]+\] .tbss +NOBITS .* 0+40 00 WAT +0 +0 +1
+ +\[[ 0-9]+\] .dynamic +DYNAMIC .*
+ +\[[ 0-9]+\] .got +PROGBITS .*
+- +\[[ 0-9]+\] .shstrtab .*
+ +\[[ 0-9]+\] .symtab .*
+ +\[[ 0-9]+\] .strtab .*
++ +\[[ 0-9]+\] .shstrtab .*
+ Key to Flags:
+ #...
+
+diff --git a/ld/testsuite/ld-s390/tlsbin_64.rd b/ld/testsuite/ld-s390/tlsbin_64.rd
+index 38d5789..f7caa16 100644
+--- a/ld/testsuite/ld-s390/tlsbin_64.rd
++++ b/ld/testsuite/ld-s390/tlsbin_64.rd
+@@ -22,9 +22,9 @@ Section Headers:
+ +\[[ 0-9]+\] .tbss +NOBITS .* 0+40 00 WAT +0 +0 +1
+ +\[[ 0-9]+\] .dynamic +DYNAMIC .*
+ +\[[ 0-9]+\] .got +PROGBITS .*
+- +\[[ 0-9]+\] .shstrtab .*
+ +\[[ 0-9]+\] .symtab .*
+ +\[[ 0-9]+\] .strtab .*
++ +\[[ 0-9]+\] .shstrtab .*
+ Key to Flags:
+ #...
+
+diff --git a/ld/testsuite/ld-s390/tlspic.rd b/ld/testsuite/ld-s390/tlspic.rd
+index 07d29c2..5159863 100644
+--- a/ld/testsuite/ld-s390/tlspic.rd
++++ b/ld/testsuite/ld-s390/tlspic.rd
+@@ -21,9 +21,9 @@ Section Headers:
+ +\[[ 0-9]+\] .tbss +NOBITS .* 0+20 00 WAT +0 +0 +1
+ +\[[ 0-9]+\] .dynamic +DYNAMIC .*
+ +\[[ 0-9]+\] .got +PROGBITS .*
+- +\[[ 0-9]+\] .shstrtab .*
+ +\[[ 0-9]+\] .symtab .*
+ +\[[ 0-9]+\] .strtab .*
++ +\[[ 0-9]+\] .shstrtab .*
+ Key to Flags:
+ #...
+
+diff --git a/ld/testsuite/ld-s390/tlspic_64.rd b/ld/testsuite/ld-s390/tlspic_64.rd
+index 6197f8a..7f8dc1b 100644
+--- a/ld/testsuite/ld-s390/tlspic_64.rd
++++ b/ld/testsuite/ld-s390/tlspic_64.rd
+@@ -21,9 +21,9 @@ Section Headers:
+ +\[[ 0-9]+\] .tbss +NOBITS .* 0+20 00 WAT +0 +0 +1
+ +\[[ 0-9]+\] .dynamic +DYNAMIC .*
+ +\[[ 0-9]+\] .got +PROGBITS .*
+- +\[[ 0-9]+\] .shstrtab .*
+ +\[[ 0-9]+\] .symtab .*
+ +\[[ 0-9]+\] .strtab .*
++ +\[[ 0-9]+\] .shstrtab .*
+ Key to Flags:
+ #...
+
+diff --git a/ld/testsuite/ld-sh/sh64/crange1.rd b/ld/testsuite/ld-sh/sh64/crange1.rd
+index e22d502..83c1e9b 100644
+--- a/ld/testsuite/ld-sh/sh64/crange1.rd
++++ b/ld/testsuite/ld-sh/sh64/crange1.rd
+@@ -7,9 +7,9 @@ Section Headers:
+ +\[ 2\] \.text +PROGBITS +00001004 000084 000018 00 AXp +0 +0 +4
+ +\[ 3\] \.stack +PROGBITS +00080000 000100 000004 00 +WA +0 +0 +1
+ +\[ 4\] \.cranges +LOUSER\+1 +00000000 000104 00001e 00 +W +0 +0 +1
+- +\[ 5\] \.shstrtab +STRTAB +.*
+- +\[ 6\] \.symtab +SYMTAB +.*
+- +\[ 7\] \.strtab +STRTAB +.*
++ +\[ 5\] \.symtab +SYMTAB +.*
++ +\[ 6\] \.strtab +STRTAB +.*
++ +\[ 7\] \.shstrtab +STRTAB +.*
+ Key to Flags:
+ #...
+
+diff --git a/ld/testsuite/ld-sh/sh64/crange2.rd b/ld/testsuite/ld-sh/sh64/crange2.rd
+index 5074087..e7416e1 100644
+--- a/ld/testsuite/ld-sh/sh64/crange2.rd
++++ b/ld/testsuite/ld-sh/sh64/crange2.rd
+@@ -7,9 +7,9 @@ Section Headers:
+ +\[ 2\] \.text +PROGBITS +00001004 000084 00005c 00 AXp +0 +0 +4
+ +\[ 3\] \.stack +PROGBITS +00080000 000100 000004 00 +WA +0 +0 +1
+ +\[ 4\] \.cranges +LOUSER\+1 +00000000 000104 000046 00 +W +0 +0 +1
+- +\[ 5\] \.shstrtab +STRTAB +.*
+- +\[ 6\] \.symtab +SYMTAB +.*
+- +\[ 7\] \.strtab +STRTAB +.*
++ +\[ 5\] \.symtab +SYMTAB +.*
++ +\[ 6\] \.strtab +STRTAB +.*
++ +\[ 7\] \.shstrtab +STRTAB +.*
+ Key to Flags:
+ #...
+
+diff --git a/ld/testsuite/ld-sh/sh64/crange3-cmpct.rd b/ld/testsuite/ld-sh/sh64/crange3-cmpct.rd
+index d4f090e..9f5f595 100644
+--- a/ld/testsuite/ld-sh/sh64/crange3-cmpct.rd
++++ b/ld/testsuite/ld-sh/sh64/crange3-cmpct.rd
+@@ -17,7 +17,7 @@ ELF Header:
+ +Number of program headers: +2
+ +Size of section headers: +40 \(bytes\)
+ +Number of section headers: +8
+- +Section header string table index: 5
++ +Section header string table index: 7
+
+ Section Headers:
+ +\[Nr\] Name +Type +Addr +Off +Size +ES Flg Lk Inf Al
+@@ -26,9 +26,9 @@ Section Headers:
+ +\[ 2\] \.text +PROGBITS +00001004 000084 0000d8 00 AXp +0 +0 +4
+ +\[ 3\] \.stack +PROGBITS +00080000 000180 000004 00 +WA +0 +0 +1
+ +\[ 4\] \.cranges +LOUSER\+1 +00000000 000184 00003c 00 +W +0 +0 +1
+- +\[ 5\] \.shstrtab +STRTAB +.*
+- +\[ 6\] \.symtab +SYMTAB +.*
+- +\[ 7\] \.strtab +STRTAB +.*
++ +\[ 5\] \.symtab +SYMTAB +.*
++ +\[ 6\] \.strtab +STRTAB +.*
++ +\[ 7\] \.shstrtab +STRTAB +.*
+ Key to Flags:
+ #...
+
+diff --git a/ld/testsuite/ld-sh/sh64/crange3-media.rd b/ld/testsuite/ld-sh/sh64/crange3-media.rd
+index 5a856d4..926925c 100644
+--- a/ld/testsuite/ld-sh/sh64/crange3-media.rd
++++ b/ld/testsuite/ld-sh/sh64/crange3-media.rd
+@@ -17,7 +17,7 @@ ELF Header:
+ +Number of program headers: +2
+ +Size of section headers: +40 \(bytes\)
+ +Number of section headers: +8
+- +Section header string table index: 5
++ +Section header string table index: 7
+
+ Section Headers:
+ +\[Nr\] Name +Type +Addr +Off +Size +ES Flg Lk Inf Al
+@@ -26,9 +26,9 @@ Section Headers:
+ +\[ 2\] \.text +PROGBITS +00001004 000084 0000d8 00 AXp +0 +0 +4
+ +\[ 3\] \.stack +PROGBITS +00080000 000180 000004 00 +WA +0 +0 +1
+ +\[ 4\] \.cranges +LOUSER\+1 +00000000 000184 00003c 00 +W +0 +0 +1
+- +\[ 5\] \.shstrtab +STRTAB +.*
+- +\[ 6\] \.symtab +SYMTAB +.*
+- +\[ 7\] \.strtab +STRTAB +.*
++ +\[ 5\] \.symtab +SYMTAB +.*
++ +\[ 6\] \.strtab +STRTAB +.*
++ +\[ 7\] \.shstrtab +STRTAB +.*
+ Key to Flags:
+ #...
+
+diff --git a/ld/testsuite/ld-sh/sh64/crange3.rd b/ld/testsuite/ld-sh/sh64/crange3.rd
+index b495861..8870e0b 100644
+--- a/ld/testsuite/ld-sh/sh64/crange3.rd
++++ b/ld/testsuite/ld-sh/sh64/crange3.rd
+@@ -7,9 +7,9 @@ Section Headers:
+ +\[ 2\] \.text +PROGBITS +00001004 000084 0000d8 00 AXp +0 +0 +4
+ +\[ 3\] \.stack +PROGBITS +00080000 000180 000004 00 +WA +0 +0 +1
+ +\[ 4\] \.cranges +LOUSER\+1 +00000000 000184 00003c 00 +W +0 +0 +1
+- +\[ 5\] \.shstrtab +STRTAB +.*
+- +\[ 6\] \.symtab +SYMTAB +.*
+- +\[ 7\] \.strtab +STRTAB +.*
++ +\[ 5\] \.symtab +SYMTAB +.*
++ +\[ 6\] \.strtab +STRTAB +.*
++ +\[ 7\] \.shstrtab +STRTAB +.*
+ Key to Flags:
+ #...
+
+diff --git a/ld/testsuite/ld-sh/sh64/crangerel1.rd b/ld/testsuite/ld-sh/sh64/crangerel1.rd
+index 90d71c5..3443f2a 100644
+--- a/ld/testsuite/ld-sh/sh64/crangerel1.rd
++++ b/ld/testsuite/ld-sh/sh64/crangerel1.rd
+@@ -10,9 +10,9 @@ Section Headers:
+ +\[ 5\] \.stack +PROGBITS +00000000 00004c 000004 00 +WA +0 +0 +1
+ +\[ 6\] \.cranges +PROGBITS +00000000 000050 00001e 00 +W +0 +0 +1
+ +\[ 7\] \.rela\.cranges +RELA +00000000 [0-9a-f]+ 000024 0c +I +9 +6 +4
+- +\[ 8\] \.shstrtab +STRTAB +00000000 [0-9a-f]+ 00004d 00 +0 +0 +1
+- +\[ 9\] \.symtab +SYMTAB .*
+- +\[10\] \.strtab +STRTAB .*
++ +\[ 8\] \.symtab +SYMTAB .*
++ +\[ 9\] \.strtab +STRTAB .*
++ +\[10\] \.shstrtab +STRTAB +00000000 [0-9a-f]+ 00004d 00 +0 +0 +1
+ Key to Flags:
+ #...
+
+diff --git a/ld/testsuite/ld-sh/sh64/crangerel2.rd b/ld/testsuite/ld-sh/sh64/crangerel2.rd
+index 2daede7..a1674b5 100644
+--- a/ld/testsuite/ld-sh/sh64/crangerel2.rd
++++ b/ld/testsuite/ld-sh/sh64/crangerel2.rd
+@@ -10,9 +10,9 @@ Section Headers:
+ +\[ 5\] \.stack +PROGBITS +00000000 000090 000004 00 +WA +0 +0 +1
+ +\[ 6\] \.cranges +PROGBITS +00000000 000094 000046 00 +W +0 +0 +1
+ +\[ 7\] \.rela\.cranges +RELA +00000000 [0-9a-f]+ 000054 0c +I +9 +6 +4
+- +\[ 8\] \.shstrtab +STRTAB +00000000 [0-9a-f]+ 00004d 00 +0 +0 +1
+- +\[ 9\] \.symtab +SYMTAB +00000000 [0-9a-f]+ [0-9a-f]+ 10 +10 +[0-9]+ +4
+- +\[10\] \.strtab +STRTAB +00000000 [0-9a-f]+ [0-9a-f]+ 00 +0 +0 +1
++ +\[ 8\] \.symtab +SYMTAB +00000000 [0-9a-f]+ [0-9a-f]+ 10 +8 +[0-9]+ +4
++ +\[ 9\] \.strtab +STRTAB +00000000 [0-9a-f]+ [0-9a-f]+ 00 +0 +0 +1
++ +\[10\] \.shstrtab +STRTAB +00000000 [0-9a-f]+ 00004d 00 +0 +0 +1
+ Key to Flags:
+ #...
+
+diff --git a/ld/testsuite/ld-sh/tlsbin-2.d b/ld/testsuite/ld-sh/tlsbin-2.d
+index 167270f..6958e45 100644
+--- a/ld/testsuite/ld-sh/tlsbin-2.d
++++ b/ld/testsuite/ld-sh/tlsbin-2.d
+@@ -23,9 +23,9 @@ Section Headers:
+ #...
+ +\[[0-9a-f]+\] \.got +PROGBITS .*
+ #...
+- +\[[0-9a-f]+\] \.shstrtab .*
+ +\[[0-9a-f]+\] \.symtab .*
+ +\[[0-9a-f]+\] \.strtab .*
++ +\[[0-9a-f]+\] \.shstrtab .*
+ Key to Flags:
+ #...
+
+diff --git a/ld/testsuite/ld-sh/tlspic-2.d b/ld/testsuite/ld-sh/tlspic-2.d
+index 0b47878..42baf1d 100644
+--- a/ld/testsuite/ld-sh/tlspic-2.d
++++ b/ld/testsuite/ld-sh/tlspic-2.d
+@@ -22,9 +22,9 @@ Section Headers:
+ #...
+ +\[[0-9a-f]+\] \.got +PROGBITS .*
+ #...
+- +\[[0-9a-f]+\] \.shstrtab .*
+ +\[[0-9a-f]+\] \.symtab .*
+ +\[[0-9a-f]+\] \.strtab .*
++ +\[[0-9a-f]+\] \.shstrtab .*
+ Key to Flags:
+ #...
+
+diff --git a/ld/testsuite/ld-sparc/gotop32.rd b/ld/testsuite/ld-sparc/gotop32.rd
+index 3b5b942..1813719 100644
+--- a/ld/testsuite/ld-sparc/gotop32.rd
++++ b/ld/testsuite/ld-sparc/gotop32.rd
+@@ -17,9 +17,9 @@ Section Headers:
+ +\[[ 0-9]+\] .dynamic +DYNAMIC +0+12000 0+2000 0+70 08 +WA +3 +0 +4
+ +\[[ 0-9]+\] .got +PROGBITS +0+12070 0+2070 0+8 04 +WA +0 +0 +4
+ +\[[ 0-9]+\] .data +PROGBITS +0+13000 0+3000 0+8 00 +WA +0 +0 4096
+- +\[[ 0-9]+\] .shstrtab +.*
+ +\[[ 0-9]+\] .symtab +.*
+ +\[[ 0-9]+\] .strtab +.*
++ +\[[ 0-9]+\] .shstrtab +.*
+ #...
+
+ Elf file type is DYN \(Shared object file\)
+diff --git a/ld/testsuite/ld-sparc/gotop64.rd b/ld/testsuite/ld-sparc/gotop64.rd
+index 2d3ffec..578fb2b 100644
+--- a/ld/testsuite/ld-sparc/gotop64.rd
++++ b/ld/testsuite/ld-sparc/gotop64.rd
+@@ -17,9 +17,9 @@ Section Headers:
+ +\[[ 0-9]+\] .dynamic +DYNAMIC +0+102000 0+2000 0+e0 10 +WA +3 +0 +8
+ +\[[ 0-9]+\] .got +PROGBITS +0+1020e0 0+20e0 0+10 08 +WA +0 +0 +8
+ +\[[ 0-9]+\] .data +PROGBITS +0+103000 0+3000 0+8 00 +WA +0 +0 4096
+- +\[[ 0-9]+\] .shstrtab +.*
+ +\[[ 0-9]+\] .symtab +.*
+ +\[[ 0-9]+\] .strtab +.*
++ +\[[ 0-9]+\] .shstrtab +.*
+ #...
+
+ Elf file type is DYN \(Shared object file\)
+diff --git a/ld/testsuite/ld-sparc/tlssunbin32.rd b/ld/testsuite/ld-sparc/tlssunbin32.rd
+index 7212732..3de615f 100644
+--- a/ld/testsuite/ld-sparc/tlssunbin32.rd
++++ b/ld/testsuite/ld-sparc/tlssunbin32.rd
+@@ -19,9 +19,9 @@ Section Headers:
+ +\[[ 0-9]+\] .tbss +NOBITS +0+231f4 0+31f4 0+40 00 WAT +0 +0 +4
+ +\[[ 0-9]+\] .dynamic +DYNAMIC +0+231f4 0+31f4 0+80 08 +WA +4 +0 +4
+ +\[[ 0-9]+\] .got +PROGBITS +0+23274 0+3274 0+14 04 +WA +0 +0 +4
+- +\[[ 0-9]+\] .shstrtab +.*
+ +\[[ 0-9]+\] .symtab +.*
+ +\[[ 0-9]+\] .strtab +.*
++ +\[[ 0-9]+\] .shstrtab +.*
+ #...
+
+ Elf file type is EXEC \(Executable file\)
+diff --git a/ld/testsuite/ld-sparc/tlssunbin64.rd b/ld/testsuite/ld-sparc/tlssunbin64.rd
+index 5480dab..2297d2e 100644
+--- a/ld/testsuite/ld-sparc/tlssunbin64.rd
++++ b/ld/testsuite/ld-sparc/tlssunbin64.rd
+@@ -19,9 +19,9 @@ Section Headers:
+ +\[[ 0-9]+\] .tbss +NOBITS +0+202204 0+2204 0+40 00 WAT +0 +0 +4
+ +\[[ 0-9]+\] .dynamic +DYNAMIC +0+202208 0+2208 0+100 10 +WA +4 +0 +8
+ +\[[ 0-9]+\] .got +PROGBITS +0+202308 0+2308 0+28 08 +WA +0 +0 +8
+- +\[[ 0-9]+\] .shstrtab +.*
+ +\[[ 0-9]+\] .symtab +.*
+ +\[[ 0-9]+\] .strtab +.*
++ +\[[ 0-9]+\] .shstrtab +.*
+ #...
+
+ Elf file type is EXEC \(Executable file\)
+diff --git a/ld/testsuite/ld-sparc/tlssunnopic32.rd b/ld/testsuite/ld-sparc/tlssunnopic32.rd
+index 21d07c0..bfb7cb8 100644
+--- a/ld/testsuite/ld-sparc/tlssunnopic32.rd
++++ b/ld/testsuite/ld-sparc/tlssunnopic32.rd
+@@ -18,9 +18,9 @@ Section Headers:
+ +\[[ 0-9]+\] .tbss +NOBITS +0+12000 0+2000 0+24 0+ WAT +0 +0 +4
+ +\[[ 0-9]+\] .dynamic +DYNAMIC +0+12000 0+2000 0+80 08 +WA +3 +0 +4
+ +\[[ 0-9]+\] .got +PROGBITS +0+12080 0+2080 0+1c 04 +WA +0 +0 +4
+- +\[[ 0-9]+\] .shstrtab +.*
+ +\[[ 0-9]+\] .symtab +.*
+ +\[[ 0-9]+\] .strtab +.*
++ +\[[ 0-9]+\] .shstrtab +.*
+ #...
+ Elf file type is DYN \(Shared object file\)
+ Entry point 0x1000
+diff --git a/ld/testsuite/ld-sparc/tlssunnopic64.rd b/ld/testsuite/ld-sparc/tlssunnopic64.rd
+index 6825aa9..88fe05f 100644
+--- a/ld/testsuite/ld-sparc/tlssunnopic64.rd
++++ b/ld/testsuite/ld-sparc/tlssunnopic64.rd
+@@ -18,9 +18,9 @@ Section Headers:
+ +\[[ 0-9]+\] .tbss +NOBITS +0+102000 0+2000 0+24 0+ WAT +0 +0 +4
+ +\[[ 0-9]+\] .dynamic +DYNAMIC +0+102000 0+2000 0+100 10 +WA +3 +0 +8
+ +\[[ 0-9]+\] .got +PROGBITS +0+102100 0+2100 0+38 08 +WA +0 +0 +8
+- +\[[ 0-9]+\] .shstrtab +.*
+ +\[[ 0-9]+\] .symtab +.*
+ +\[[ 0-9]+\] .strtab +.*
++ +\[[ 0-9]+\] .shstrtab +.*
+ #...
+ Elf file type is DYN \(Shared object file\)
+ Entry point 0x1000
+diff --git a/ld/testsuite/ld-sparc/tlssunpic32.rd b/ld/testsuite/ld-sparc/tlssunpic32.rd
+index 4d96736..519b5df 100644
+--- a/ld/testsuite/ld-sparc/tlssunpic32.rd
++++ b/ld/testsuite/ld-sparc/tlssunpic32.rd
+@@ -21,9 +21,9 @@ Section Headers:
+ +\[[ 0-9]+\] .dynamic +DYNAMIC +0+12060 0+2060 0+98 08 +WA +3 +0 +4
+ +\[[ 0-9]+\] .got +PROGBITS +0+120f8 0+20f8 0+4c 04 +WA +0 +0 +4
+ +\[[ 0-9]+\] .plt +.*
+- +\[[ 0-9]+\] .shstrtab +.*
+ +\[[ 0-9]+\] .symtab +.*
+ +\[[ 0-9]+\] .strtab +.*
++ +\[[ 0-9]+\] .shstrtab +.*
+ #...
+
+ Elf file type is DYN \(Shared object file\)
+diff --git a/ld/testsuite/ld-sparc/tlssunpic64.rd b/ld/testsuite/ld-sparc/tlssunpic64.rd
+index 6f91fee..fa00bbf 100644
+--- a/ld/testsuite/ld-sparc/tlssunpic64.rd
++++ b/ld/testsuite/ld-sparc/tlssunpic64.rd
+@@ -21,9 +21,9 @@ Section Headers:
+ +\[[ 0-9]+\] .dynamic +DYNAMIC +0+102060 0+2060 0+130 10 +WA +3 +0 +8
+ +\[[ 0-9]+\] .got +PROGBITS +0+102190 0+2190 0+98 08 +WA +0 +0 +8
+ +\[[ 0-9]+\] .plt +.*
+- +\[[ 0-9]+\] .shstrtab +.*
+ +\[[ 0-9]+\] .symtab +.*
+ +\[[ 0-9]+\] .strtab +.*
++ +\[[ 0-9]+\] .shstrtab +.*
+ #...
+
+ Elf file type is DYN \(Shared object file\)
+diff --git a/ld/testsuite/ld-tic6x/common.d b/ld/testsuite/ld-tic6x/common.d
+index 30521fc..f2a7b1b 100644
+--- a/ld/testsuite/ld-tic6x/common.d
++++ b/ld/testsuite/ld-tic6x/common.d
+@@ -11,9 +11,9 @@ Section Headers:
+ \[ 0\] NULL 00000000 000000 000000 00 0 0 0
+ \[ 1\] \.far NOBITS 00000080 000080 000008 00 WA 0 0 4
+ \[ 2\] \.bss NOBITS 00000100 000080 000004 00 WA 0 0 4
+- \[ 3\] \.shstrtab STRTAB 00000000 [0-9a-f]+ 000025 00 0 0 1
+- \[ 4\] \.symtab SYMTAB 00000000 [0-9a-f]+ 000050 10 5 3 4
+- \[ 5\] \.strtab STRTAB 00000000 [0-9a-f]+ 000005 00 0 0 1
++ \[ 3\] \.symtab SYMTAB 00000000 [0-9a-f]+ 000050 10 4 3 4
++ \[ 4\] \.strtab STRTAB 00000000 [0-9a-f]+ 000005 00 0 0 1
++ \[ 5\] \.shstrtab STRTAB 00000000 [0-9a-f]+ 000025 00 0 0 1
+ Key to Flags:
+ #...
+
+diff --git a/ld/testsuite/ld-tic6x/shlib-1.rd b/ld/testsuite/ld-tic6x/shlib-1.rd
+index a07ddca..77ec3d7 100644
+--- a/ld/testsuite/ld-tic6x/shlib-1.rd
++++ b/ld/testsuite/ld-tic6x/shlib-1.rd
+@@ -16,9 +16,9 @@ Section Headers:
+ \[11\] \.neardata PROGBITS 10000128 002128 000008 00 WA 0 0 4
+ \[12\] \.bss NOBITS 10000130 002130 000004 00 WA 0 0 4
+ \[13\] \.c6xabi\.attributes C6000_ATTRIBUTES 00000000 002130 000019 00 0 0 1
+- \[14\] \.shstrtab STRTAB 00000000 [0-9a-f]+ 00007b 00 0 0 1
+- \[15\] \.symtab SYMTAB 00000000 [0-9a-f]+ [0-9a-f]+ 10 16 [0-9]+ 4
+- \[16\] \.strtab STRTAB 00000000 [0-9a-f]+ [0-9a-f]+ 00 0 0 1
++ \[14\] \.symtab SYMTAB 00000000 [0-9a-f]+ [0-9a-f]+ 10 15 [0-9]+ 4
++ \[15\] \.strtab STRTAB 00000000 [0-9a-f]+ [0-9a-f]+ 00 0 0 1
++ \[16\] \.shstrtab STRTAB 00000000 [0-9a-f]+ 00007b 00 0 0 1
+ Key to Flags:
+ #...
+
+diff --git a/ld/testsuite/ld-tic6x/shlib-1b.rd b/ld/testsuite/ld-tic6x/shlib-1b.rd
+index a07ddca..77ec3d7 100644
+--- a/ld/testsuite/ld-tic6x/shlib-1b.rd
++++ b/ld/testsuite/ld-tic6x/shlib-1b.rd
+@@ -16,9 +16,9 @@ Section Headers:
+ \[11\] \.neardata PROGBITS 10000128 002128 000008 00 WA 0 0 4
+ \[12\] \.bss NOBITS 10000130 002130 000004 00 WA 0 0 4
+ \[13\] \.c6xabi\.attributes C6000_ATTRIBUTES 00000000 002130 000019 00 0 0 1
+- \[14\] \.shstrtab STRTAB 00000000 [0-9a-f]+ 00007b 00 0 0 1
+- \[15\] \.symtab SYMTAB 00000000 [0-9a-f]+ [0-9a-f]+ 10 16 [0-9]+ 4
+- \[16\] \.strtab STRTAB 00000000 [0-9a-f]+ [0-9a-f]+ 00 0 0 1
++ \[14\] \.symtab SYMTAB 00000000 [0-9a-f]+ [0-9a-f]+ 10 15 [0-9]+ 4
++ \[15\] \.strtab STRTAB 00000000 [0-9a-f]+ [0-9a-f]+ 00 0 0 1
++ \[16\] \.shstrtab STRTAB 00000000 [0-9a-f]+ 00007b 00 0 0 1
+ Key to Flags:
+ #...
+
+diff --git a/ld/testsuite/ld-tic6x/shlib-1r.rd b/ld/testsuite/ld-tic6x/shlib-1r.rd
+index a07ddca..77ec3d7 100644
+--- a/ld/testsuite/ld-tic6x/shlib-1r.rd
++++ b/ld/testsuite/ld-tic6x/shlib-1r.rd
+@@ -16,9 +16,9 @@ Section Headers:
+ \[11\] \.neardata PROGBITS 10000128 002128 000008 00 WA 0 0 4
+ \[12\] \.bss NOBITS 10000130 002130 000004 00 WA 0 0 4
+ \[13\] \.c6xabi\.attributes C6000_ATTRIBUTES 00000000 002130 000019 00 0 0 1
+- \[14\] \.shstrtab STRTAB 00000000 [0-9a-f]+ 00007b 00 0 0 1
+- \[15\] \.symtab SYMTAB 00000000 [0-9a-f]+ [0-9a-f]+ 10 16 [0-9]+ 4
+- \[16\] \.strtab STRTAB 00000000 [0-9a-f]+ [0-9a-f]+ 00 0 0 1
++ \[14\] \.symtab SYMTAB 00000000 [0-9a-f]+ [0-9a-f]+ 10 15 [0-9]+ 4
++ \[15\] \.strtab STRTAB 00000000 [0-9a-f]+ [0-9a-f]+ 00 0 0 1
++ \[16\] \.shstrtab STRTAB 00000000 [0-9a-f]+ 00007b 00 0 0 1
+ Key to Flags:
+ #...
+
+diff --git a/ld/testsuite/ld-tic6x/shlib-1rb.rd b/ld/testsuite/ld-tic6x/shlib-1rb.rd
+index a07ddca..77ec3d7 100644
+--- a/ld/testsuite/ld-tic6x/shlib-1rb.rd
++++ b/ld/testsuite/ld-tic6x/shlib-1rb.rd
+@@ -16,9 +16,9 @@ Section Headers:
+ \[11\] \.neardata PROGBITS 10000128 002128 000008 00 WA 0 0 4
+ \[12\] \.bss NOBITS 10000130 002130 000004 00 WA 0 0 4
+ \[13\] \.c6xabi\.attributes C6000_ATTRIBUTES 00000000 002130 000019 00 0 0 1
+- \[14\] \.shstrtab STRTAB 00000000 [0-9a-f]+ 00007b 00 0 0 1
+- \[15\] \.symtab SYMTAB 00000000 [0-9a-f]+ [0-9a-f]+ 10 16 [0-9]+ 4
+- \[16\] \.strtab STRTAB 00000000 [0-9a-f]+ [0-9a-f]+ 00 0 0 1
++ \[14\] \.symtab SYMTAB 00000000 [0-9a-f]+ [0-9a-f]+ 10 15 [0-9]+ 4
++ \[15\] \.strtab STRTAB 00000000 [0-9a-f]+ [0-9a-f]+ 00 0 0 1
++ \[16\] \.shstrtab STRTAB 00000000 [0-9a-f]+ 00007b 00 0 0 1
+ Key to Flags:
+ #...
+
+diff --git a/ld/testsuite/ld-tic6x/shlib-app-1.rd b/ld/testsuite/ld-tic6x/shlib-app-1.rd
+index f0e67c9..c3ddcd3 100644
+--- a/ld/testsuite/ld-tic6x/shlib-app-1.rd
++++ b/ld/testsuite/ld-tic6x/shlib-app-1.rd
+@@ -17,9 +17,9 @@ Section Headers:
+ \[12\] \.neardata PROGBITS 100000c0 0020c0 00000c 00 WA 0 0 4
+ \[13\] \.bss NOBITS 100000cc 0020cc 000004 00 WA 0 0 4
+ \[14\] \.c6xabi\.attributes C6000_ATTRIBUTES 00000000 0020cc 000019 00 0 0 1
+- \[15\] \.shstrtab STRTAB 00000000 [0-9a-f]+ 000080 00 0 0 1
+- \[16\] \.symtab SYMTAB 00000000 [0-9a-f]+ [0-9a-f]+ 10 17 [0-9]+ 4
+- \[17\] \.strtab STRTAB 00000000 [0-9a-f]+ [0-9a-f]+ 00 0 0 1
++ \[15\] \.symtab SYMTAB 00000000 [0-9a-f]+ [0-9a-f]+ 10 16 [0-9]+ 4
++ \[16\] \.strtab STRTAB 00000000 [0-9a-f]+ [0-9a-f]+ 00 0 0 1
++ \[17\] \.shstrtab STRTAB 00000000 [0-9a-f]+ 000080 00 0 0 1
+ Key to Flags:
+ #...
+
+diff --git a/ld/testsuite/ld-tic6x/shlib-app-1b.rd b/ld/testsuite/ld-tic6x/shlib-app-1b.rd
+index 19a7371..2f9d0f6 100644
+--- a/ld/testsuite/ld-tic6x/shlib-app-1b.rd
++++ b/ld/testsuite/ld-tic6x/shlib-app-1b.rd
+@@ -17,9 +17,9 @@ Section Headers:
+ \[12\] \.neardata PROGBITS 100000c0 0020c0 00000c 00 WA 0 0 4
+ \[13\] \.bss NOBITS 100000cc 0020cc 000004 00 WA 0 0 4
+ \[14\] \.c6xabi\.attributes C6000_ATTRIBUTES 00000000 0020cc 000019 00 0 0 1
+- \[15\] \.shstrtab STRTAB 00000000 [0-9a-f]+ 000080 00 0 0 1
+- \[16\] \.symtab SYMTAB 00000000 [0-9a-f]+ [0-9a-f]+ 10 17 [0-9]+ 4
+- \[17\] \.strtab STRTAB 00000000 [0-9a-f]+ [0-9a-f]+ 00 0 0 1
++ \[15\] \.symtab SYMTAB 00000000 [0-9a-f]+ [0-9a-f]+ 10 16 [0-9]+ 4
++ \[16\] \.strtab STRTAB 00000000 [0-9a-f]+ [0-9a-f]+ 00 0 0 1
++ \[17\] \.shstrtab STRTAB 00000000 [0-9a-f]+ 000080 00 0 0 1
+ Key to Flags:
+ #...
+
+diff --git a/ld/testsuite/ld-tic6x/shlib-app-1r.rd b/ld/testsuite/ld-tic6x/shlib-app-1r.rd
+index f4fcf6b..2cf8c58 100644
+--- a/ld/testsuite/ld-tic6x/shlib-app-1r.rd
++++ b/ld/testsuite/ld-tic6x/shlib-app-1r.rd
+@@ -16,9 +16,9 @@ Section Headers:
+ \[11\] \.neardata PROGBITS 100000c0 0020c0 000004 00 WA 0 0 4
+ \[12\] \.bss NOBITS 100000c4 0020c4 000004 00 WA 0 0 4
+ \[13\] \.c6xabi\.attributes C6000_ATTRIBUTES 00000000 0020c4 000019 00 0 0 1
+- \[14\] \.shstrtab STRTAB 00000000 [0-9a-f]+ 00007b 00 0 0 1
+- \[15\] \.symtab SYMTAB 00000000 [0-9a-f]+ [0-9a-f]+ 10 16 [0-9]+ 4
+- \[16\] \.strtab STRTAB 00000000 [0-9a-f]+ [0-9a-f]+ 00 0 0 1
++ \[14\] \.symtab SYMTAB 00000000 [0-9a-f]+ [0-9a-f]+ 10 15 [0-9]+ 4
++ \[15\] \.strtab STRTAB 00000000 [0-9a-f]+ [0-9a-f]+ 00 0 0 1
++ \[16\] \.shstrtab STRTAB 00000000 [0-9a-f]+ 00007b 00 0 0 1
+ Key to Flags:
+ #...
+
+diff --git a/ld/testsuite/ld-tic6x/shlib-app-1rb.rd b/ld/testsuite/ld-tic6x/shlib-app-1rb.rd
+index 3b7b6a9..3cb0256 100644
+--- a/ld/testsuite/ld-tic6x/shlib-app-1rb.rd
++++ b/ld/testsuite/ld-tic6x/shlib-app-1rb.rd
+@@ -16,9 +16,9 @@ Section Headers:
+ \[11\] \.neardata PROGBITS 100000c0 0020c0 000004 00 WA 0 0 4
+ \[12\] \.bss NOBITS 100000c4 0020c4 000004 00 WA 0 0 4
+ \[13\] \.c6xabi\.attributes C6000_ATTRIBUTES 00000000 0020c4 000019 00 0 0 1
+- \[14\] \.shstrtab STRTAB 00000000 [0-9a-f]+ 00007b 00 0 0 1
+- \[15\] \.symtab SYMTAB 00000000 [0-9a-f]+ [0-9a-f]+ 10 16 [0-9]+ 4
+- \[16\] \.strtab STRTAB 00000000 [0-9a-f]+ [0-9a-f]+ 00 0 0 1
++ \[14\] \.symtab SYMTAB 00000000 [0-9a-f]+ [0-9a-f]+ 10 15 [0-9]+ 4
++ \[15\] \.strtab STRTAB 00000000 [0-9a-f]+ [0-9a-f]+ 00 0 0 1
++ \[16\] \.shstrtab STRTAB 00000000 [0-9a-f]+ 00007b 00 0 0 1
+ Key to Flags:
+ #...
+
+diff --git a/ld/testsuite/ld-tic6x/shlib-noindex.rd b/ld/testsuite/ld-tic6x/shlib-noindex.rd
+index fa03130..0a29c63 100644
+--- a/ld/testsuite/ld-tic6x/shlib-noindex.rd
++++ b/ld/testsuite/ld-tic6x/shlib-noindex.rd
+@@ -17,9 +17,9 @@ Section Headers:
+ \[12\] \.neardata PROGBITS 10000128 002128 000008 00 WA 0 0 4
+ \[13\] \.bss NOBITS 10000130 002130 000004 00 WA 0 0 4
+ \[14\] \.c6xabi\.attributes C6000_ATTRIBUTES 00000000 002130 000019 00 0 0 1
+- \[15\] \.shstrtab STRTAB 00000000 [0-9a-f]+ 000080 00 0 0 1
+- \[16\] \.symtab SYMTAB 00000000 [0-9a-f]+ [0-9a-f]+ 10 17 [0-9]+ 4
+- \[17\] \.strtab STRTAB 00000000 [0-9a-f]+ [0-9a-f]+ 00 0 0 1
++ \[15\] \.symtab SYMTAB 00000000 [0-9a-f]+ [0-9a-f]+ 10 16 [0-9]+ 4
++ \[16\] \.strtab STRTAB 00000000 [0-9a-f]+ [0-9a-f]+ 00 0 0 1
++ \[17\] \.shstrtab STRTAB 00000000 [0-9a-f]+ 000080 00 0 0 1
+ Key to Flags:
+ #...
+
+diff --git a/ld/testsuite/ld-tic6x/static-app-1.rd b/ld/testsuite/ld-tic6x/static-app-1.rd
+index c1bfc2f..27d2d23 100644
+--- a/ld/testsuite/ld-tic6x/static-app-1.rd
++++ b/ld/testsuite/ld-tic6x/static-app-1.rd
+@@ -14,9 +14,9 @@ Section Headers:
+ \[ 9\] \.neardata PROGBITS 100000e0 0020e0 000014 00 WA 0 0 4
+ \[10\] \.bss NOBITS 100000f4 0020f4 000004 00 WA 0 0 4
+ \[11\] \.c6xabi\.attributes C6000_ATTRIBUTES 00000000 0020f4 000019 00 0 0 1
+- \[12\] \.shstrtab STRTAB 00000000 [0-9a-f]+ 000071 00 0 0 1
+- \[13\] \.symtab SYMTAB 00000000 [0-9a-f]+ [0-9a-f]+ 10 14 [0-9]+ 4
+- \[14\] \.strtab STRTAB 00000000 [0-9a-f]+ [0-9a-f]+ 00 0 0 1
++ \[12\] \.symtab SYMTAB 00000000 [0-9a-f]+ [0-9a-f]+ 10 13 [0-9]+ 4
++ \[13\] \.strtab STRTAB 00000000 [0-9a-f]+ [0-9a-f]+ 00 0 0 1
++ \[14\] \.shstrtab STRTAB 00000000 [0-9a-f]+ 000071 00 0 0 1
+ Key to Flags:
+ #...
+
+diff --git a/ld/testsuite/ld-tic6x/static-app-1b.rd b/ld/testsuite/ld-tic6x/static-app-1b.rd
+index c1bfc2f..27d2d23 100644
+--- a/ld/testsuite/ld-tic6x/static-app-1b.rd
++++ b/ld/testsuite/ld-tic6x/static-app-1b.rd
+@@ -14,9 +14,9 @@ Section Headers:
+ \[ 9\] \.neardata PROGBITS 100000e0 0020e0 000014 00 WA 0 0 4
+ \[10\] \.bss NOBITS 100000f4 0020f4 000004 00 WA 0 0 4
+ \[11\] \.c6xabi\.attributes C6000_ATTRIBUTES 00000000 0020f4 000019 00 0 0 1
+- \[12\] \.shstrtab STRTAB 00000000 [0-9a-f]+ 000071 00 0 0 1
+- \[13\] \.symtab SYMTAB 00000000 [0-9a-f]+ [0-9a-f]+ 10 14 [0-9]+ 4
+- \[14\] \.strtab STRTAB 00000000 [0-9a-f]+ [0-9a-f]+ 00 0 0 1
++ \[12\] \.symtab SYMTAB 00000000 [0-9a-f]+ [0-9a-f]+ 10 13 [0-9]+ 4
++ \[13\] \.strtab STRTAB 00000000 [0-9a-f]+ [0-9a-f]+ 00 0 0 1
++ \[14\] \.shstrtab STRTAB 00000000 [0-9a-f]+ 000071 00 0 0 1
+ Key to Flags:
+ #...
+
+diff --git a/ld/testsuite/ld-tic6x/static-app-1r.rd b/ld/testsuite/ld-tic6x/static-app-1r.rd
+index af8341e..9f3ed9b 100644
+--- a/ld/testsuite/ld-tic6x/static-app-1r.rd
++++ b/ld/testsuite/ld-tic6x/static-app-1r.rd
+@@ -14,9 +14,9 @@ Section Headers:
+ \[ 9\] \.neardata PROGBITS 100000e0 0020e0 00000c 00 WA 0 0 4
+ \[10\] \.bss NOBITS 100000ec 0020ec 000004 00 WA 0 0 4
+ \[11\] \.c6xabi\.attributes C6000_ATTRIBUTES 00000000 0020ec 000019 00 0 0 1
+- \[12\] \.shstrtab STRTAB 00000000 [0-9a-f]+ 000071 00 0 0 1
+- \[13\] \.symtab SYMTAB 00000000 [0-9a-f]+ [0-9a-f]+ 10 14 [0-9]+ 4
+- \[14\] \.strtab STRTAB 00000000 [0-9a-f]+ [0-9a-f]+ 00 0 0 1
++ \[12\] \.symtab SYMTAB 00000000 [0-9a-f]+ [0-9a-f]+ 10 13 [0-9]+ 4
++ \[13\] \.strtab STRTAB 00000000 [0-9a-f]+ [0-9a-f]+ 00 0 0 1
++ \[14\] \.shstrtab STRTAB 00000000 [0-9a-f]+ 000071 00 0 0 1
+ Key to Flags:
+ #...
+
+diff --git a/ld/testsuite/ld-tic6x/static-app-1rb.rd b/ld/testsuite/ld-tic6x/static-app-1rb.rd
+index af8341e..9f3ed9b 100644
+--- a/ld/testsuite/ld-tic6x/static-app-1rb.rd
++++ b/ld/testsuite/ld-tic6x/static-app-1rb.rd
+@@ -14,9 +14,9 @@ Section Headers:
+ \[ 9\] \.neardata PROGBITS 100000e0 0020e0 00000c 00 WA 0 0 4
+ \[10\] \.bss NOBITS 100000ec 0020ec 000004 00 WA 0 0 4
+ \[11\] \.c6xabi\.attributes C6000_ATTRIBUTES 00000000 0020ec 000019 00 0 0 1
+- \[12\] \.shstrtab STRTAB 00000000 [0-9a-f]+ 000071 00 0 0 1
+- \[13\] \.symtab SYMTAB 00000000 [0-9a-f]+ [0-9a-f]+ 10 14 [0-9]+ 4
+- \[14\] \.strtab STRTAB 00000000 [0-9a-f]+ [0-9a-f]+ 00 0 0 1
++ \[12\] \.symtab SYMTAB 00000000 [0-9a-f]+ [0-9a-f]+ 10 13 [0-9]+ 4
++ \[13\] \.strtab STRTAB 00000000 [0-9a-f]+ [0-9a-f]+ 00 0 0 1
++ \[14\] \.shstrtab STRTAB 00000000 [0-9a-f]+ 000071 00 0 0 1
+ Key to Flags:
+ #...
+
+diff --git a/ld/testsuite/ld-x86-64/ilp32-4-nacl.d b/ld/testsuite/ld-x86-64/ilp32-4-nacl.d
+index 296c406..f560ae3 100644
+--- a/ld/testsuite/ld-x86-64/ilp32-4-nacl.d
++++ b/ld/testsuite/ld-x86-64/ilp32-4-nacl.d
+@@ -14,9 +14,9 @@ Section Headers:
+ +\[ 3\] \.dynsym +DYNSYM +100000dc +0+dc +0+50 +10 +A +4 +1 +4
+ +\[ 4\] \.dynstr +STRTAB +1000012c +0+12c +0+19 +00 +A +0 +0 +1
+ +\[ 5\] \.dynamic +DYNAMIC +10010148 +0+148 +0+58 +08 +WA +4 +0 +4
+- +\[ 6\] \.shstrtab +STRTAB +0+ +[0-9a-f]+ +0+40 +00 +0 +0 +1
+- +\[ 7\] \.symtab +SYMTAB +0+0 +[0-9a-f]+ +[0-9a-f]+ +10 +8 +[0-9] +4
+- +\[ 8\] \.strtab +STRTAB +0+ +[0-9a-f]+ +[0-9a-f]+ +00 +0 +0 +1
++ +\[ 6\] \.symtab +SYMTAB +0+0 +[0-9a-f]+ +[0-9a-f]+ +10 +7 +[0-9] +4
++ +\[ 7\] \.strtab +STRTAB +0+ +[0-9a-f]+ +[0-9a-f]+ +00 +0 +0 +1
++ +\[ 8\] \.shstrtab +STRTAB +0+ +[0-9a-f]+ +0+40 +00 +0 +0 +1
+ Key to Flags:
+ #...
+
+diff --git a/ld/testsuite/ld-x86-64/ilp32-4.d b/ld/testsuite/ld-x86-64/ilp32-4.d
+index 7f1391f..658ad49 100644
+--- a/ld/testsuite/ld-x86-64/ilp32-4.d
++++ b/ld/testsuite/ld-x86-64/ilp32-4.d
+@@ -13,9 +13,9 @@ Section Headers:
+ \[ 3\] .dynstr STRTAB 0000010c 00010c 000019 00 A 0 0 1
+ \[ 4\] .text PROGBITS 00000125 000125 000001 00 AX 0 0 1
+ \[ 5\] .dynamic DYNAMIC 00200128 000128 000058 08 WA 3 0 4
+- \[ 6\] .shstrtab STRTAB 00000000 [0-9a-f]+ 000040 00 0 0 1
+- \[ 7\] .symtab SYMTAB 00000000 [0-9a-f]+ [0-9a-f]+ 10 8 [0-9] 4
+- \[ 8\] .strtab STRTAB 00000000 [0-9a-f]+ [0-9a-f]+ 00 0 0 1
++ \[ 6\] .symtab SYMTAB 00000000 [0-9a-f]+ [0-9a-f]+ 10 7 [0-9] 4
++ \[ 7\] .strtab STRTAB 00000000 [0-9a-f]+ [0-9a-f]+ 00 0 0 1
++ \[ 8\] .shstrtab STRTAB 00000000 [0-9a-f]+ 000040 00 0 0 1
+ Key to Flags:
+ #...
+
+diff --git a/ld/testsuite/ld-x86-64/nogot1.d b/ld/testsuite/ld-x86-64/nogot1.d
+index f6c4cf1..823a28a 100644
+--- a/ld/testsuite/ld-x86-64/nogot1.d
++++ b/ld/testsuite/ld-x86-64/nogot1.d
+@@ -4,5 +4,6 @@
+
+ #...
+ [ ]*\[.*\][ ]+\.dynamic[ ]+DYNAMIC.*
++#...
+ [ ]*\[.*\][ ]+.*STRTAB.*
+ #pass
+diff --git a/ld/testsuite/ld-x86-64/pr12718.d b/ld/testsuite/ld-x86-64/pr12718.d
+index 4b81d71..07d1732 100644
+--- a/ld/testsuite/ld-x86-64/pr12718.d
++++ b/ld/testsuite/ld-x86-64/pr12718.d
+@@ -9,8 +9,8 @@ Section Headers:
+ +\[Nr\] Name +Type +Address +Off +Size +ES +Flg +Lk +Inf +Al
+ +\[ 0\] +NULL +0+ +0+ +0+ +0+ +0 +0 +0
+ +\[ 1\] +.text +PROGBITS +[0-9a-f]+ +[0-9a-f]+ +000006 00 +AX +0 +0 +1
+- +\[ 2\] +.shstrtab +STRTAB +0+ +[0-9a-f]+ +[0-9a-f]+ +0+ +0 +0 +1
+- +\[ 3\] +.symtab +SYMTAB +0+ +[0-9a-f]+ +[0-9a-f]+ 18 +4 +[0-9] +8
+- +\[ 4\] +.strtab +STRTAB +0+ +[0-9a-f]+ +[0-9a-f]+ 00 +0 +0 +1
++ +\[ 2\] +.symtab +SYMTAB +0+ +[0-9a-f]+ +[0-9a-f]+ 18 +3 +[0-9] +8
++ +\[ 3\] +.strtab +STRTAB +0+ +[0-9a-f]+ +[0-9a-f]+ 00 +0 +0 +1
++ +\[ 4\] +.shstrtab +STRTAB +0+ +[0-9a-f]+ +[0-9a-f]+ +0+ +0 +0 +1
+ Key to Flags:
+ #pass
+diff --git a/ld/testsuite/ld-x86-64/pr12921.d b/ld/testsuite/ld-x86-64/pr12921.d
+index 8d09616..6fe6abe 100644
+--- a/ld/testsuite/ld-x86-64/pr12921.d
++++ b/ld/testsuite/ld-x86-64/pr12921.d
+@@ -11,8 +11,8 @@ Section Headers:
+ +\[ 1\] .text +PROGBITS +[0-9a-f]+ +[0-9a-f]+ +0+1 00 +AX +0 +0 +4096
+ +\[ 2\] .data +PROGBITS +[0-9a-f]+ +[0-9a-f]+000 +0+28 +00 +WA +0 +0 +4096
+ +\[ 3\] .bss +NOBITS +[0-9a-f]+ +[0-9a-f]+028 +0+10000 +00 +WA +0 +0 +4096
+- +\[ 4\] .shstrtab +STRTAB +0+ +[0-9a-f]+ +0+2c +00 +0 +0 +1
+- +\[ 5\] .symtab +SYMTAB +0+ +[0-9a-f]+ +[0-9a-f]+ +18 +6 +[0-9] +8
+- +\[ 6\] .strtab +STRTAB +0+ +[0-9a-f]+ +[0-9a-f]+ +00 +0 +0 +1
++ +\[ 4\] .symtab +SYMTAB +0+ +[0-9a-f]+ +[0-9a-f]+ +18 +5 +[0-9] +8
++ +\[ 5\] .strtab +STRTAB +0+ +[0-9a-f]+ +[0-9a-f]+ +00 +0 +0 +1
++ +\[ 6\] .shstrtab +STRTAB +0+ +[0-9a-f]+ +0+2c +00 +0 +0 +1
+ Key to Flags:
+ #pass
+diff --git a/ld/testsuite/ld-x86-64/split-by-file-nacl.rd b/ld/testsuite/ld-x86-64/split-by-file-nacl.rd
+index d11988a..4e3e74a 100644
+--- a/ld/testsuite/ld-x86-64/split-by-file-nacl.rd
++++ b/ld/testsuite/ld-x86-64/split-by-file-nacl.rd
+@@ -8,8 +8,8 @@ Section Headers:
+ \[ 3\] .data PROGBITS 0000000000000000 000043 000000 00 WA 0 0 1
+ \[ 4\] .bss NOBITS 0000000000000000 000043 000000 00 WA 0 0 1
+ \[ 5\] .foo.0 PROGBITS 0000000000000003 000043 000003 00 AXl 0 0 1
+- \[ 6\] .shstrtab STRTAB 0000000000000000 [0-9a-f]+ 000038 00 0 0 1
+- \[ 7\] .symtab SYMTAB 0000000000000000 [0-9a-f]+ [0-9a-f]+ 18 8 [0-9] 8
+- \[ 8\] .strtab STRTAB 0000000000000000 [0-9a-f]+ [0-9a-f]+ 00 0 0 1
++ \[ 6\] .symtab SYMTAB 0000000000000000 [0-9a-f]+ [0-9a-f]+ 18 7 [0-9] 8
++ \[ 7\] .strtab STRTAB 0000000000000000 [0-9a-f]+ [0-9a-f]+ 00 0 0 1
++ \[ 8\] .shstrtab STRTAB 0000000000000000 [0-9a-f]+ 000038 00 0 0 1
+ Key to Flags:
+ #pass
+diff --git a/ld/testsuite/ld-x86-64/split-by-file.rd b/ld/testsuite/ld-x86-64/split-by-file.rd
+index d11988a..4e3e74a 100644
+--- a/ld/testsuite/ld-x86-64/split-by-file.rd
++++ b/ld/testsuite/ld-x86-64/split-by-file.rd
+@@ -8,8 +8,8 @@ Section Headers:
+ \[ 3\] .data PROGBITS 0000000000000000 000043 000000 00 WA 0 0 1
+ \[ 4\] .bss NOBITS 0000000000000000 000043 000000 00 WA 0 0 1
+ \[ 5\] .foo.0 PROGBITS 0000000000000003 000043 000003 00 AXl 0 0 1
+- \[ 6\] .shstrtab STRTAB 0000000000000000 [0-9a-f]+ 000038 00 0 0 1
+- \[ 7\] .symtab SYMTAB 0000000000000000 [0-9a-f]+ [0-9a-f]+ 18 8 [0-9] 8
+- \[ 8\] .strtab STRTAB 0000000000000000 [0-9a-f]+ [0-9a-f]+ 00 0 0 1
++ \[ 6\] .symtab SYMTAB 0000000000000000 [0-9a-f]+ [0-9a-f]+ 18 7 [0-9] 8
++ \[ 7\] .strtab STRTAB 0000000000000000 [0-9a-f]+ [0-9a-f]+ 00 0 0 1
++ \[ 8\] .shstrtab STRTAB 0000000000000000 [0-9a-f]+ 000038 00 0 0 1
+ Key to Flags:
+ #pass
+diff --git a/ld/testsuite/ld-x86-64/tlsbin-nacl.rd b/ld/testsuite/ld-x86-64/tlsbin-nacl.rd
+index 5de5e1a..4284644 100644
+--- a/ld/testsuite/ld-x86-64/tlsbin-nacl.rd
++++ b/ld/testsuite/ld-x86-64/tlsbin-nacl.rd
+@@ -23,9 +23,9 @@ Section Headers:
+ +\[[ 0-9]+\] .dynamic +DYNAMIC +0+10030410 [0-9a-f]+ 0+140 10 +WA +6 +0 +8
+ +\[[ 0-9]+\] .got +PROGBITS +0+10030550 [0-9a-f]+ 0+20 08 +WA +0 +0 +8
+ +\[[ 0-9]+\] .got.plt +PROGBITS +0+10030570 [0-9a-f]+ 0+20 08 +WA +0 +0 +8
+- +\[[ 0-9]+\] .shstrtab +.*
+ +\[[ 0-9]+\] .symtab +.*
+ +\[[ 0-9]+\] .strtab +.*
++ +\[[ 0-9]+\] .shstrtab +.*
+ Key to Flags:
+ #...
+
+diff --git a/ld/testsuite/ld-x86-64/tlsbin.rd b/ld/testsuite/ld-x86-64/tlsbin.rd
+index 6f73b98..a34775d 100644
+--- a/ld/testsuite/ld-x86-64/tlsbin.rd
++++ b/ld/testsuite/ld-x86-64/tlsbin.rd
+@@ -23,9 +23,9 @@ Section Headers:
+ +\[[ 0-9]+\] .dynamic +DYNAMIC +0+601298 0+1298 0+140 10 +WA +4 +0 +8
+ +\[[ 0-9]+\] .got +PROGBITS +0+6013d8 0+13d8 0+20 08 +WA +0 +0 +8
+ +\[[ 0-9]+\] .got.plt +PROGBITS +0+6013f8 0+13f8 0+20 08 +WA +0 +0 +8
+- +\[[ 0-9]+\] .shstrtab +.*
+ +\[[ 0-9]+\] .symtab +.*
+ +\[[ 0-9]+\] .strtab +.*
++ +\[[ 0-9]+\] .shstrtab +.*
+ Key to Flags:
+ #...
+
+diff --git a/ld/testsuite/ld-x86-64/tlsbin2-nacl.rd b/ld/testsuite/ld-x86-64/tlsbin2-nacl.rd
+index 110927b..1f5b782 100644
+--- a/ld/testsuite/ld-x86-64/tlsbin2-nacl.rd
++++ b/ld/testsuite/ld-x86-64/tlsbin2-nacl.rd
+@@ -21,9 +21,9 @@ Section Headers:
+ +\[[ 0-9]+\] .dynamic +DYNAMIC +0+10030410 [0-9a-f]+ 0+100 10 +WA +5 +0 +8
+ +\[[ 0-9]+\] .got +PROGBITS +0+10030510 [0-9a-f]+ 0+28 08 +WA +0 +0 +8
+ +\[[ 0-9]+\] .got.plt +PROGBITS +0+10030538 [0-9a-f]+ 0+18 08 +WA +0 +0 +8
+- +\[[ 0-9]+\] .shstrtab +.*
+ +\[[ 0-9]+\] .symtab +.*
+ +\[[ 0-9]+\] .strtab +.*
++ +\[[ 0-9]+\] .shstrtab +.*
+ Key to Flags:
+ #...
+
+diff --git a/ld/testsuite/ld-x86-64/tlsbin2.rd b/ld/testsuite/ld-x86-64/tlsbin2.rd
+index b283648..5fb1599 100644
+--- a/ld/testsuite/ld-x86-64/tlsbin2.rd
++++ b/ld/testsuite/ld-x86-64/tlsbin2.rd
+@@ -21,9 +21,9 @@ Section Headers:
+ +\[[ 0-9]+\] .dynamic +DYNAMIC +0+601298 0+1298 0+100 10 +WA +4 +0 +8
+ +\[[ 0-9]+\] .got +PROGBITS +0+601398 0+1398 0+28 08 +WA +0 +0 +8
+ +\[[ 0-9]+\] .got.plt +PROGBITS +0+6013c0 0+13c0 0+18 08 +WA +0 +0 +8
+- +\[[ 0-9]+\] .shstrtab +.*
+ +\[[ 0-9]+\] .symtab +.*
+ +\[[ 0-9]+\] .strtab +.*
++ +\[[ 0-9]+\] .shstrtab +.*
+ Key to Flags:
+ #...
+
+diff --git a/ld/testsuite/ld-x86-64/tlsbindesc-nacl.rd b/ld/testsuite/ld-x86-64/tlsbindesc-nacl.rd
+index 39a5abe..2c046f4 100644
+--- a/ld/testsuite/ld-x86-64/tlsbindesc-nacl.rd
++++ b/ld/testsuite/ld-x86-64/tlsbindesc-nacl.rd
+@@ -21,9 +21,9 @@ Section Headers:
+ +\[[ 0-9]+\] .dynamic +DYNAMIC +0+100303d0 0+3d0 0+100 10 +WA +5 +0 +8
+ +\[[ 0-9]+\] .got +PROGBITS +0+100304d0 0+4d0 0+20 08 +WA +0 +0 +8
+ +\[[ 0-9]+\] .got.plt +PROGBITS +0+100304f0 0+4f0 0+18 08 +WA +0 +0 +8
+- +\[[ 0-9]+\] .shstrtab +.*
+ +\[[ 0-9]+\] .symtab +.*
+ +\[[ 0-9]+\] .strtab +.*
++ +\[[ 0-9]+\] .shstrtab +.*
+ Key to Flags:
+ #...
+
+diff --git a/ld/testsuite/ld-x86-64/tlsbindesc.rd b/ld/testsuite/ld-x86-64/tlsbindesc.rd
+index 8c9a342..c94014a 100644
+--- a/ld/testsuite/ld-x86-64/tlsbindesc.rd
++++ b/ld/testsuite/ld-x86-64/tlsbindesc.rd
+@@ -21,9 +21,9 @@ Section Headers:
+ +\[[ 0-9]+\] .dynamic +DYNAMIC +0+601260 0+1260 0+100 10 +WA +4 +0 +8
+ +\[[ 0-9]+\] .got +PROGBITS +0+601360 0+1360 0+20 08 +WA +0 +0 +8
+ +\[[ 0-9]+\] .got.plt +PROGBITS +0+601380 0+1380 0+18 08 +WA +0 +0 +8
+- +\[[ 0-9]+\] .shstrtab +.*
+ +\[[ 0-9]+\] .symtab +.*
+ +\[[ 0-9]+\] .strtab +.*
++ +\[[ 0-9]+\] .shstrtab +.*
+ Key to Flags:
+ #...
+
+diff --git a/ld/testsuite/ld-x86-64/tlsdesc-nacl.rd b/ld/testsuite/ld-x86-64/tlsdesc-nacl.rd
+index db196a5..7c9d77a 100644
+--- a/ld/testsuite/ld-x86-64/tlsdesc-nacl.rd
++++ b/ld/testsuite/ld-x86-64/tlsdesc-nacl.rd
+@@ -22,9 +22,9 @@ Section Headers:
+ +\[[ 0-9]+\] .dynamic +DYNAMIC +0+100104b0 [0-9a-f]+ 0+150 10 +WA +5 +0 +8
+ +\[[ 0-9]+\] .got +PROGBITS +0+10010600 [0-9a-f]+ 0+48 08 +WA +0 +0 +8
+ +\[[ 0-9]+\] .got.plt +PROGBITS +0+10010648 [0-9a-f]+ 0+68 08 +WA +0 +0 +8
+- +\[[ 0-9]+\] .shstrtab +.*
+ +\[[ 0-9]+\] .symtab +.*
+ +\[[ 0-9]+\] .strtab +.*
++ +\[[ 0-9]+\] .shstrtab +.*
+ Key to Flags:
+ #...
+
+diff --git a/ld/testsuite/ld-x86-64/tlsdesc.rd b/ld/testsuite/ld-x86-64/tlsdesc.rd
+index 6a636a0..18060c0 100644
+--- a/ld/testsuite/ld-x86-64/tlsdesc.rd
++++ b/ld/testsuite/ld-x86-64/tlsdesc.rd
+@@ -22,9 +22,9 @@ Section Headers:
+ +\[[ 0-9]+\] .dynamic +DYNAMIC +0+2011b8 0+11b8 0+150 10 +WA +3 +0 +8
+ +\[[ 0-9]+\] .got +PROGBITS +0+201308 0+1308 0+48 08 +WA +0 +0 +8
+ +\[[ 0-9]+\] .got.plt +PROGBITS +0+201350 0+1350 0+68 08 +WA +0 +0 +8
+- +\[[ 0-9]+\] .shstrtab +.*
+ +\[[ 0-9]+\] .symtab +.*
+ +\[[ 0-9]+\] .strtab +.*
++ +\[[ 0-9]+\] .shstrtab +.*
+ Key to Flags:
+ #...
+
+diff --git a/ld/testsuite/ld-x86-64/tlsgdesc-nacl.rd b/ld/testsuite/ld-x86-64/tlsgdesc-nacl.rd
+index 8614af5..934ba03 100644
+--- a/ld/testsuite/ld-x86-64/tlsgdesc-nacl.rd
++++ b/ld/testsuite/ld-x86-64/tlsgdesc-nacl.rd
+@@ -19,9 +19,9 @@ Section Headers:
+ +\[[ 0-9]+\] \.dynamic +.*
+ +\[[ 0-9]+\] \.got +.*
+ +\[[ 0-9]+\] \.got.plt +.*
+- +\[[ 0-9]+\] \.shstrtab +.*
+ +\[[ 0-9]+\] \.symtab +.*
+ +\[[ 0-9]+\] \.strtab +.*
++ +\[[ 0-9]+\] \.shstrtab +.*
+ Key to Flags:
+ #...
+
+diff --git a/ld/testsuite/ld-x86-64/tlsgdesc.rd b/ld/testsuite/ld-x86-64/tlsgdesc.rd
+index 5d845c7..729d12e6 100644
+--- a/ld/testsuite/ld-x86-64/tlsgdesc.rd
++++ b/ld/testsuite/ld-x86-64/tlsgdesc.rd
+@@ -19,9 +19,9 @@ Section Headers:
+ +\[[ 0-9]+\] \.dynamic +.*
+ +\[[ 0-9]+\] \.got +.*
+ +\[[ 0-9]+\] \.got.plt +.*
+- +\[[ 0-9]+\] \.shstrtab +.*
+ +\[[ 0-9]+\] \.symtab +.*
+ +\[[ 0-9]+\] \.strtab +.*
++ +\[[ 0-9]+\] \.shstrtab +.*
+ Key to Flags:
+ #...
+
+diff --git a/ld/testsuite/ld-x86-64/tlspic-nacl.rd b/ld/testsuite/ld-x86-64/tlspic-nacl.rd
+index f98e39b..740e399 100644
+--- a/ld/testsuite/ld-x86-64/tlspic-nacl.rd
++++ b/ld/testsuite/ld-x86-64/tlspic-nacl.rd
+@@ -22,9 +22,9 @@ Section Headers:
+ +\[[ 0-9]+\] .dynamic +DYNAMIC +0+10010510 [0-9a-f]+ 0+130 10 +WA +5 +0 +8
+ +\[[ 0-9]+\] .got +PROGBITS +0+10010640 [0-9a-f]+ 0+90 08 +WA +0 +0 +8
+ +\[[ 0-9]+\] .got.plt +PROGBITS +0+100106d0 [0-9a-f]+ 0+20 08 +WA +0 +0 +8
+- +\[[ 0-9]+\] .shstrtab +.*
+ +\[[ 0-9]+\] .symtab +.*
+ +\[[ 0-9]+\] .strtab +.*
++ +\[[ 0-9]+\] .shstrtab +.*
+ Key to Flags:
+ #...
+
+diff --git a/ld/testsuite/ld-x86-64/tlspic.rd b/ld/testsuite/ld-x86-64/tlspic.rd
+index 589666b..3f5d544 100644
+--- a/ld/testsuite/ld-x86-64/tlspic.rd
++++ b/ld/testsuite/ld-x86-64/tlspic.rd
+@@ -22,9 +22,9 @@ Section Headers:
+ +\[[ 0-9]+\] .dynamic +DYNAMIC +0+201380 0+1380 0+130 10 +WA +3 +0 +8
+ +\[[ 0-9]+\] .got +PROGBITS +0+2014b0 0+14b0 0+90 08 +WA +0 +0 +8
+ +\[[ 0-9]+\] .got.plt +PROGBITS +0+201540 0+1540 0+20 08 +WA +0 +0 +8
+- +\[[ 0-9]+\] .shstrtab +.*
+ +\[[ 0-9]+\] .symtab +.*
+ +\[[ 0-9]+\] .strtab +.*
++ +\[[ 0-9]+\] .shstrtab +.*
+ Key to Flags:
+ #...
+
+diff --git a/ld/testsuite/ld-x86-64/tlspic2-nacl.rd b/ld/testsuite/ld-x86-64/tlspic2-nacl.rd
+index 1919b3f..cbc0a75 100644
+--- a/ld/testsuite/ld-x86-64/tlspic2-nacl.rd
++++ b/ld/testsuite/ld-x86-64/tlspic2-nacl.rd
+@@ -22,9 +22,9 @@ Section Headers:
+ +\[[ 0-9]+\] .dynamic +DYNAMIC +0+10010528 [0-9a-f]+ 0+130 10 +WA +5 +0 +8
+ +\[[ 0-9]+\] .got +PROGBITS +0+10010658 [0-9a-f]+ 0+98 08 +WA +0 +0 +8
+ +\[[ 0-9]+\] .got.plt +PROGBITS +0+100106f0 [0-9a-f]+ 0+20 08 +WA +0 +0 +8
+- +\[[ 0-9]+\] .shstrtab +.*
+ +\[[ 0-9]+\] .symtab +.*
+ +\[[ 0-9]+\] .strtab +.*
++ +\[[ 0-9]+\] .shstrtab +.*
+ Key to Flags:
+ #...
+
+diff --git a/ld/testsuite/ld-x86-64/tlspic2.rd b/ld/testsuite/ld-x86-64/tlspic2.rd
+index 3c7b8c1..684ae21 100644
+--- a/ld/testsuite/ld-x86-64/tlspic2.rd
++++ b/ld/testsuite/ld-x86-64/tlspic2.rd
+@@ -22,9 +22,9 @@ Section Headers:
+ +\[[ 0-9]+\] .dynamic +DYNAMIC +0+201380 0+1380 0+100 10 +WA +3 +0 +8
+ +\[[ 0-9]+\] .got +PROGBITS +0+201480 0+1480 0+98 08 +WA +0 +0 +8
+ +\[[ 0-9]+\] .got.plt +PROGBITS +0+201518 0+1518 0+18 08 +WA +0 +0 +8
+- +\[[ 0-9]+\] .shstrtab +.*
+ +\[[ 0-9]+\] .symtab +.*
+ +\[[ 0-9]+\] .strtab +.*
++ +\[[ 0-9]+\] .shstrtab +.*
+ Key to Flags:
+ #...
+
+diff --git a/ld/testsuite/ld-xtensa/tlsbin.rd b/ld/testsuite/ld-xtensa/tlsbin.rd
+index 2361139..dcd2b04 100644
+--- a/ld/testsuite/ld-xtensa/tlsbin.rd
++++ b/ld/testsuite/ld-xtensa/tlsbin.rd
+@@ -22,9 +22,9 @@ Section Headers:
+ +\[[ 0-9]+\] .xtensa.info +NOTE +0+ .*
+ +\[[ 0-9]+\] .xt.lit +PROGBITS +0+ .*
+ +\[[ 0-9]+\] .xt.prop +PROGBITS +0+ .*
+- +\[[ 0-9]+\] .shstrtab +.*
+ +\[[ 0-9]+\] .symtab +.*
+ +\[[ 0-9]+\] .strtab +.*
++ +\[[ 0-9]+\] .shstrtab +.*
+ Key to Flags:
+ #...
+
+diff --git a/ld/testsuite/ld-xtensa/tlspic.rd b/ld/testsuite/ld-xtensa/tlspic.rd
+index 379334c..b6f7067 100644
+--- a/ld/testsuite/ld-xtensa/tlspic.rd
++++ b/ld/testsuite/ld-xtensa/tlspic.rd
+@@ -23,9 +23,9 @@ Section Headers:
+ +\[[ 0-9]+\] .xtensa.info +NOTE +0+ .*
+ +\[[ 0-9]+\] .xt.lit +PROGBITS +0+ .*
+ +\[[ 0-9]+\] .xt.prop +PROGBITS +0+ .*
+- +\[[ 0-9]+\] .shstrtab +.*
+ +\[[ 0-9]+\] .symtab +.*
+ +\[[ 0-9]+\] .strtab +.*
++ +\[[ 0-9]+\] .shstrtab +.*
+ Key to Flags:
+ #...
+
+diff -rup binutils-2.27.orig/ld/testsuite/ld-powerpc/tlsexe32.r binutils-2.27/ld/testsuite/ld-powerpc/tlsexe32.r
+--- binutils-2.27.orig/ld/testsuite/ld-powerpc/tlsexe32.r 2017-01-17 09:30:06.631463387 +0000
++++ binutils-2.27/ld/testsuite/ld-powerpc/tlsexe32.r 2017-01-17 09:30:34.074140629 +0000
+@@ -23,9 +23,9 @@ Section Headers:
+ +\[[ 0-9]+\] \.got +PROGBITS +[0-9a-f]+ [0-9a-f]+ 000018 04 +WA +0 +0 +4
+ +\[[ 0-9]+\] \.plt +PROGBITS +[0-9a-f]+ [0-9a-f]+ 000004 00 +WA +0 +0 +4
+ #...
+- +\[[ 0-9]+\] \.shstrtab +STRTAB +.*
+ +\[[ 0-9]+\] \.symtab +SYMTAB +.*
+ +\[[ 0-9]+\] \.strtab +STRTAB +.*
++ +\[[ 0-9]+\] \.shstrtab +STRTAB +.*
+ #...
+
+ Elf file type is EXEC \(Executable file\)
+diff -rup binutils-2.27.orig/ld/testsuite/ld-powerpc/tlsso32.r binutils-2.27/ld/testsuite/ld-powerpc/tlsso32.r
+--- binutils-2.27.orig/ld/testsuite/ld-powerpc/tlsso32.r 2017-01-17 09:30:06.632463375 +0000
++++ binutils-2.27/ld/testsuite/ld-powerpc/tlsso32.r 2017-01-17 09:30:18.506323674 +0000
+@@ -21,9 +21,9 @@ Section Headers:
+ +\[[ 0-9]+\] \.got +PROGBITS .* 0+30 04 +WA +0 +0 +4
+ +\[[ 0-9]+\] \.plt +PROGBITS .* 0+4 00 +WA +0 +0 +4
+ #...
+- +\[[ 0-9]+\] \.shstrtab +.*
+ +\[[ 0-9]+\] \.symtab +.*
+ +\[[ 0-9]+\] \.strtab +.*
++ +\[[ 0-9]+\] \.shstrtab +.*
+ #...
+
+ Elf file type is DYN \(Shared object file\)
+diff -rup binutils-2.27.orig/ld/testsuite/ld-powerpc/tlstocso.r binutils-2.27/ld/testsuite/ld-powerpc/tlstocso.r
+--- binutils-2.27.orig/ld/testsuite/ld-powerpc/tlstocso.r 2017-01-17 09:30:06.631463387 +0000
++++ binutils-2.27/ld/testsuite/ld-powerpc/tlstocso.r 2017-01-17 09:32:37.080695394 +0000
+@@ -21,9 +21,9 @@ Section Headers:
+ +\[[ 0-9]+\] \.opd .*
+ +\[[ 0-9]+\] \.got .*
+ +\[[ 0-9]+\] \.plt .*
+- +\[[ 0-9]+\] \.shstrtab .*
+ +\[[ 0-9]+\] \.symtab .*
+ +\[[ 0-9]+\] \.strtab .*
++ +\[[ 0-9]+\] \.shstrtab .*
+ #...
+
+ Elf file type is DYN \(Shared object file\)
diff --git a/SOURCES/binutils-2.27-objdump-improvements.patch b/SOURCES/binutils-2.27-objdump-improvements.patch
new file mode 100644
index 0000000..ee2418a
--- /dev/null
+++ b/SOURCES/binutils-2.27-objdump-improvements.patch
@@ -0,0 +1,4350 @@
+--- binutils-2.27.orig/binutils/objdump.c 2016-11-08 15:39:41.094551341 +0000
++++ binutils-2.27/binutils/objdump.c 2016-11-08 16:04:52.433507357 +0000
+@@ -620,6 +620,18 @@ slurp_dynamic_symtab (bfd *abfd)
+ return sy;
+ }
+
++/* Some symbol names are significant and should be kept in the
++ table of sorted symbol names, even if they are marked as
++ debugging/section symbols. */
++
++static bfd_boolean
++is_significant_symbol_name (const char * name)
++{
++ return strcmp (name, ".plt") == 0
++ || strcmp (name, ".got") == 0
++ || strcmp (name, ".plt.got") == 0;
++}
++
+ /* Filter out (in place) symbols that are useless for disassembly.
+ COUNT is the number of elements in SYMBOLS.
+ Return the number of useful symbols. */
+@@ -635,7 +647,8 @@ remove_useless_symbols (asymbol **symbol
+
+ if (sym->name == NULL || sym->name[0] == '\0')
+ continue;
+- if (sym->flags & (BSF_DEBUGGING | BSF_SECTION_SYM))
++ if ((sym->flags & (BSF_DEBUGGING | BSF_SECTION_SYM))
++ && ! is_significant_symbol_name (sym->name))
+ continue;
+ if (bfd_is_und_section (sym->section)
+ || bfd_is_com_section (sym->section))
+@@ -903,11 +916,13 @@ find_symbol_for_address (bfd_vma vma,
+
+ /* The symbol we want is now in min, the low end of the range we
+ were searching. If there are several symbols with the same
+- value, we want the first one. */
++ value, we want the first (non-section/non-debugging) one. */
+ thisplace = min;
+ while (thisplace > 0
+ && (bfd_asymbol_value (sorted_syms[thisplace])
+- == bfd_asymbol_value (sorted_syms[thisplace - 1])))
++ == bfd_asymbol_value (sorted_syms[thisplace - 1]))
++ && ((sorted_syms[thisplace - 1]->flags
++ & (BSF_SECTION_SYM | BSF_DEBUGGING)) == 0))
+ --thisplace;
+
+ /* Prefer a symbol in the current section if we have multple symbols
+@@ -993,6 +1008,41 @@ find_symbol_for_address (bfd_vma vma,
+ return NULL;
+ }
+
++ /* If we have not found an exact match for the specified address
++ and we have dynamic relocations available, then we can produce
++ a better result by matching a relocation to the address and
++ using the symbol associated with that relocation. */
++ if (!want_section
++ && aux->dynrelbuf != NULL
++ && sorted_syms[thisplace]->value != vma
++ /* If we have matched a synthetic symbol, then stick with that. */
++ && (sorted_syms[thisplace]->flags & BSF_SYNTHETIC) == 0)
++ {
++ arelent ** rel_pp;
++ long rel_count;
++
++ for (rel_count = aux->dynrelcount, rel_pp = aux->dynrelbuf;
++ rel_count--;)
++ {
++ arelent * rel = rel_pp[rel_count];
++
++ if (rel->address == vma
++ && rel->sym_ptr_ptr != NULL
++ /* Absolute relocations do not provide a more helpful symbolic address. */
++ && ! bfd_is_abs_section ((* rel->sym_ptr_ptr)->section))
++ {
++ if (place != NULL)
++ * place = thisplace;
++ return * rel->sym_ptr_ptr;
++ }
++
++ /* We are scanning backwards, so if we go below the target address
++ we have failed. */
++ if (rel_pp[rel_count]->address < vma)
++ break;
++ }
++ }
++
+ if (place != NULL)
+ *place = thisplace;
+
+@@ -1031,7 +1081,19 @@ objdump_print_addr_with_sym (bfd *abfd,
+ {
+ (*inf->fprintf_func) (inf->stream, " <");
+ objdump_print_symname (abfd, inf, sym);
+- if (bfd_asymbol_value (sym) > vma)
++
++ if (bfd_asymbol_value (sym) == vma)
++ ;
++ /* Undefined symbols in an executables and dynamic objects do not have
++ a value associated with them, so it does not make sense to display
++ an offset relative to them. Normally we would not be provided with
++ this kind of symbol, but the target backend might choose to do so,
++ and the code in find_symbol_for_address might return an as yet
++ unresolved symbol associated with a dynamic reloc. */
++ else if ((bfd_get_file_flags (abfd) & (EXEC_P | DYNAMIC))
++ && bfd_is_und_section (sym->section))
++ ;
++ else if (bfd_asymbol_value (sym) > vma)
+ {
+ (*inf->fprintf_func) (inf->stream, "-0x");
+ objdump_print_value (bfd_asymbol_value (sym) - vma, inf, TRUE);
+@@ -1996,7 +2058,7 @@ disassemble_section (bfd *abfd, asection
+
+ /* Decide which set of relocs to use. Load them if necessary. */
+ paux = (struct objdump_disasm_info *) pinfo->application_data;
+- if (paux->dynrelbuf)
++ if (paux->dynrelbuf && dump_dynamic_reloc_info)
+ {
+ rel_pp = paux->dynrelbuf;
+ rel_count = paux->dynrelcount;
+@@ -2273,13 +2335,11 @@ disassemble_data (bfd *abfd)
+ /* Allow the target to customize the info structure. */
+ disassemble_init_for_target (& disasm_info);
+
+- /* Pre-load the dynamic relocs if we are going
+- to be dumping them along with the disassembly. */
+- if (dump_dynamic_reloc_info)
++ /* Pre-load the dynamic relocs as we may need them during the disassembly. */
+ {
+ long relsize = bfd_get_dynamic_reloc_upper_bound (abfd);
+
+- if (relsize < 0)
++ if (relsize < 0 && dump_dynamic_reloc_info)
+ bfd_fatal (bfd_get_filename (abfd));
+
+ if (relsize > 0)
+--- binutils-2.27/gas/testsuite/gas/arm/tls.d 2015-11-13 08:27:41.000000000 +0000
++++ /work/sources/binutils/current/gas/testsuite/gas/arm/tls.d 2016-10-11 12:14:08.383657767 +0100
+@@ -15,7 +15,7 @@ Disassembly of section .text:
+ 0: e1a00000 nop ; .*
+ 0: R_ARM_TLS_DESCSEQ af
+ 4: e59f0014 ldr r0, \[pc, #20\] ; 20 .*
+- 8: fa000000 blx 8 <ae\+.*>
++ 8: fa000000 blx 8 <ae.*>
+ 8: R_ARM_TLS_CALL ae
+ c: e1a00000 nop ; .*
+ 0+10 <.arm_pool>:
+@@ -34,7 +34,7 @@ Disassembly of section .text:
+ 26: 46c0 nop ; .*
+ 26: R_ARM_THM_TLS_DESCSEQ tf
+ 28: 4805 ldr r0, \[pc, #20\] ; \(40 .*\)
+- 2a: f000 e800 blx 4 <te\+0x4>
++ 2a: f000 e800 blx 4 <te.*>
+ 2a: R_ARM_THM_TLS_CALL te
+ 2e: 46c0 nop ; .*
+ 30: 00000002 .word 0x00000002
+diff --git a/ld/testsuite/ld-aarch64/emit-relocs-515-be.d b/ld/testsuite/ld-aarch64/emit-relocs-515-be.d
+index 0bd39e3..82d5bd6 100644
+--- a/ld/testsuite/ld-aarch64/emit-relocs-515-be.d
++++ b/ld/testsuite/ld-aarch64/emit-relocs-515-be.d
+@@ -12,7 +12,7 @@ Disassembly of section .text:
+ 10008: 8b020021 add x1, x1, x2
+ 1000c: d2a00000 movz x0, #0x0, lsl #16
+ 10010: 8b000020 add x0, x1, x0
+- 10014: 9400000c bl 10044 \<test\+0x44\>
++ 10014: 9400000c bl 10044 \<.*\>
+ 10018: d503201f nop
+ 1001c: 00000000 .word 0x00000000
+ 10020: 0000ffe4 .word 0x0000ffe4
+diff --git a/ld/testsuite/ld-aarch64/emit-relocs-515.d b/ld/testsuite/ld-aarch64/emit-relocs-515.d
+index 67f436b..9d84bf1 100644
+--- a/ld/testsuite/ld-aarch64/emit-relocs-515.d
++++ b/ld/testsuite/ld-aarch64/emit-relocs-515.d
+@@ -12,7 +12,7 @@ Disassembly of section .text:
+ 10008: 8b020021 add x1, x1, x2
+ 1000c: d2a00000 movz x0, #0x0, lsl #16
+ 10010: 8b000020 add x0, x1, x0
+- 10014: 9400000c bl 10044 \<test\+0x44\>
++ 10014: 9400000c bl 10044 \<.*\>
+ 10018: d503201f nop
+ 1001c: 0000ffe4 .word 0x0000ffe4
+ 10020: 00000000 .word 0x00000000
+diff --git a/ld/testsuite/ld-aarch64/emit-relocs-516-be.d b/ld/testsuite/ld-aarch64/emit-relocs-516-be.d
+index e3b528d..23332b0 100644
+--- a/ld/testsuite/ld-aarch64/emit-relocs-516-be.d
++++ b/ld/testsuite/ld-aarch64/emit-relocs-516-be.d
+@@ -13,7 +13,7 @@ Disassembly of section .text:
+ 1000c: f2800100 movk x0, #0x8
+ 10010: f2800300 movk x0, #0x18
+ 10014: 8b000020 add x0, x1, x0
+- 10018: 9400000c bl 10048 \<test\+0x48\>
++ 10018: 9400000c bl 10048 \<.*\>
+ 1001c: d503201f nop
+ 10020: 00000000 .word 0x00000000
+ 10024: 0000ffe0 .word 0x0000ffe0
+diff --git a/ld/testsuite/ld-aarch64/emit-relocs-516.d b/ld/testsuite/ld-aarch64/emit-relocs-516.d
+index 2ace032..e2ad1d6 100644
+--- a/ld/testsuite/ld-aarch64/emit-relocs-516.d
++++ b/ld/testsuite/ld-aarch64/emit-relocs-516.d
+@@ -13,7 +13,7 @@ Disassembly of section .text:
+ 1000c: f2800100 movk x0, #0x8
+ 10010: f2800300 movk x0, #0x18
+ 10014: 8b000020 add x0, x1, x0
+- 10018: 9400000c bl 10048 \<test\+0x48\>
++ 10018: 9400000c bl 10048 \<.*\>
+ 1001c: d503201f nop
+ 10020: 0000ffe0 .word 0x0000ffe0
+ 10024: 00000000 .word 0x00000000
+diff --git a/ld/testsuite/ld-aarch64/gc-plt-relocs.d b/ld/testsuite/ld-aarch64/gc-plt-relocs.d
+index 086968c..d9f9413 100644
+--- a/ld/testsuite/ld-aarch64/gc-plt-relocs.d
++++ b/ld/testsuite/ld-aarch64/gc-plt-relocs.d
+@@ -20,7 +20,7 @@ DYNAMIC SYMBOL TABLE:
+ Disassembly of section .text:
+
+ 0+8000 \<_start\>:
+- 8000: 9400000c bl 8030 \<foo\+0x24\>
++ 8000: 9400000c bl 8030 \<.*>
+
+ 0+8004 \<hidfn\>:
+ 8004: 8a000000 and x0, x0, x0
+diff --git a/ld/testsuite/ld-aarch64/tls-tiny-desc.d b/ld/testsuite/ld-aarch64/tls-tiny-desc.d
+index 7b88786..c17c448 100644
+--- a/ld/testsuite/ld-aarch64/tls-tiny-desc.d
++++ b/ld/testsuite/ld-aarch64/tls-tiny-desc.d
+@@ -6,8 +6,8 @@
+ Disassembly of section .text:
+
+ 0000000000010000 \<test\>:
+- +10000: 58080141 ldr x1, 20028 \<_GLOBAL_OFFSET_TABLE_\+0x28\>
+- +10004: 10080120 adr x0, 20028 \<_GLOBAL_OFFSET_TABLE_\+0x28\>
++ +10000: 58080141 ldr x1, 20028 \<var>
++ +10004: 10080120 adr x0, 20028 \<var>
+ +10008: d63f0020 blr x1
+
+ Disassembly of section .plt:
+diff --git a/ld/testsuite/ld-aarch64/tls-tiny-gd.d b/ld/testsuite/ld-aarch64/tls-tiny-gd.d
+index 2f55f7b..9133492 100644
+--- a/ld/testsuite/ld-aarch64/tls-tiny-gd.d
++++ b/ld/testsuite/ld-aarch64/tls-tiny-gd.d
+@@ -6,8 +6,8 @@
+ Disassembly of section .text:
+
+ 0000000000010000 \<test\>:
+- +10000: 10080040 adr x0, 20008 \<_GLOBAL_OFFSET_TABLE_\+0x8\>
+- +10004: 9400000a bl 1002c \<test\+0x2c\>
++ +10000: 10080040 adr x0, 20008 \<var>
++ +10004: 9400000a bl 1002c \<.*>
+ +10008: d503201f nop
+
+ Disassembly of section .plt:
+diff --git a/ld/testsuite/ld-aarch64/tls-tiny-ie.d b/ld/testsuite/ld-aarch64/tls-tiny-ie.d
+index 02aff35..849e73d 100644
+--- a/ld/testsuite/ld-aarch64/tls-tiny-ie.d
++++ b/ld/testsuite/ld-aarch64/tls-tiny-ie.d
+@@ -3,6 +3,6 @@
+ #objdump: -dr
+ #...
+ +10000: d53bd042 mrs x2, tpidr_el0
+- +10004: 58080020 ldr x0, 20008 <_GLOBAL_OFFSET_TABLE_\+0x8>
++ +10004: 58080020 ldr x0, 20008 <.*>
+ +10008: 8b000040 add x0, x2, x0
+ +1000c: b9400000 ldr w0, \[x0\]
+diff --git a/ld/testsuite/ld-arm/arm-app-abs32.d b/ld/testsuite/ld-arm/arm-app-abs32.d
+index 13221f0..d888929 100644
+--- a/ld/testsuite/ld-arm/arm-app-abs32.d
++++ b/ld/testsuite/ld-arm/arm-app-abs32.d
+@@ -6,9 +6,9 @@ start address .*
+
+ Disassembly of section .plt:
+
+-.* <lib_func1@plt-0x14>:
++.* <.plt>:
+ +.*: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\)
+- +.*: e59fe004 ldr lr, \[pc, #4\] ; .* <lib_func1@plt-0x4>
++ +.*: e59fe004 ldr lr, \[pc, #4\] ; .* <.*>
+ +.*: e08fe00e add lr, pc, lr
+ +.*: e5bef008 ldr pc, \[lr, #8\]!
+ +.*: .* .*
+diff --git a/ld/testsuite/ld-arm/arm-app.d b/ld/testsuite/ld-arm/arm-app.d
+index 98fc899..dd4cf81 100644
+--- a/ld/testsuite/ld-arm/arm-app.d
++++ b/ld/testsuite/ld-arm/arm-app.d
+@@ -6,9 +6,9 @@ start address 0x.*
+
+ Disassembly of section .plt:
+
+-.* <lib_func1@plt-0x14>:
++.* <.plt>:
+ .*: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\)
+- .*: e59fe004 ldr lr, \[pc, #4\] ; .* <lib_func1@plt-0x4>
++ .*: e59fe004 ldr lr, \[pc, #4\] ; .* <.*>
+ .*: e08fe00e add lr, pc, lr
+ .*: e5bef008 ldr pc, \[lr, #8\]!
+ .*: .*
+diff --git a/ld/testsuite/ld-arm/arm-lib-plt32.d b/ld/testsuite/ld-arm/arm-lib-plt32.d
+index ecc2cf2..2eaf89a 100644
+--- a/ld/testsuite/ld-arm/arm-lib-plt32.d
++++ b/ld/testsuite/ld-arm/arm-lib-plt32.d
+@@ -6,9 +6,9 @@ start address 0x.*
+
+ Disassembly of section .plt:
+
+-.* <app_func2@plt-0x14>:
++.* <.plt>:
+ .*: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\)
+- .*: e59fe004 ldr lr, \[pc, #4\] ; .* <app_func2@plt-0x4>
++ .*: e59fe004 ldr lr, \[pc, #4\] ; .* <.*>
+ .*: e08fe00e add lr, pc, lr
+ .*: e5bef008 ldr pc, \[lr, #8\]!
+ .*: .*
+diff --git a/ld/testsuite/ld-arm/arm-lib.d b/ld/testsuite/ld-arm/arm-lib.d
+index 0e2a7aa..ac439ea 100644
+--- a/ld/testsuite/ld-arm/arm-lib.d
++++ b/ld/testsuite/ld-arm/arm-lib.d
+@@ -6,9 +6,9 @@ start address 0x.*
+
+ Disassembly of section .plt:
+
+-.* <app_func2@plt-0x14>:
++.* <.plt>:
+ .*: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\)
+- .*: e59fe004 ldr lr, \[pc, #4\] ; .* <app_func2@plt-0x4>
++ .*: e59fe004 ldr lr, \[pc, #4\] ; .* <.*>
+ .*: e08fe00e add lr, pc, lr
+ .*: e5bef008 ldr pc, \[lr, #8\]!
+ .*: .*
+diff --git a/ld/testsuite/ld-arm/armthumb-lib.d b/ld/testsuite/ld-arm/armthumb-lib.d
+index 9a5dea8..4f43b8e 100644
+--- a/ld/testsuite/ld-arm/armthumb-lib.d
++++ b/ld/testsuite/ld-arm/armthumb-lib.d
+@@ -6,9 +6,9 @@ start address 0x.*
+
+ Disassembly of section .plt:
+
+-.* <app_func2@plt-0x14>:
++.* <.plt>:
+ .*: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\)
+- .*: e59fe004 ldr lr, \[pc, #4\] ; .* <app_func2@plt-0x4>
++ .*: e59fe004 ldr lr, \[pc, #4\] ; .* <.*>
+ .*: e08fe00e add lr, pc, lr
+ .*: e5bef008 ldr pc, \[lr, #8\]!
+ .*: .*
+diff --git a/ld/testsuite/ld-arm/cortex-a8-fix-b-plt.d b/ld/testsuite/ld-arm/cortex-a8-fix-b-plt.d
+index 0f40861..bbf6839 100644
+--- a/ld/testsuite/ld-arm/cortex-a8-fix-b-plt.d
++++ b/ld/testsuite/ld-arm/cortex-a8-fix-b-plt.d
+@@ -4,9 +4,9 @@
+
+ Disassembly of section \.plt:
+
+-00008000 <bar@plt-0x14>:
++00008000 <.*>:
+ 8000: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\)
+- 8004: e59fe004 ldr lr, \[pc, #4\] ; 8010 <bar@plt-0x4>
++ 8004: e59fe004 ldr lr, \[pc, #4\] ; 8010 <.*>
+ 8008: e08fe00e add lr, pc, lr
+ 800c: e5bef008 ldr pc, \[lr, #8\]!
+ 8010: 00000ffc \.word 0x00000ffc
+diff --git a/ld/testsuite/ld-arm/cortex-a8-fix-bcc-plt.d b/ld/testsuite/ld-arm/cortex-a8-fix-bcc-plt.d
+index b6e6fff..079c928 100644
+--- a/ld/testsuite/ld-arm/cortex-a8-fix-bcc-plt.d
++++ b/ld/testsuite/ld-arm/cortex-a8-fix-bcc-plt.d
+@@ -4,9 +4,9 @@
+
+ Disassembly of section \.plt:
+
+-00008000 <bar@plt-0x14>:
++00008000 <.plt>:
+ 8000: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\)
+- 8004: e59fe004 ldr lr, \[pc, #4\] ; 8010 <bar@plt-0x4>
++ 8004: e59fe004 ldr lr, \[pc, #4\] ; 8010 <.*>
+ 8008: e08fe00e add lr, pc, lr
+ 800c: e5bef008 ldr pc, \[lr, #8\]!
+ 8010: 00001004 \.word 0x00001004
+diff --git a/ld/testsuite/ld-arm/cortex-a8-fix-bl-plt.d b/ld/testsuite/ld-arm/cortex-a8-fix-bl-plt.d
+index baad3d0..e4e6760 100644
+--- a/ld/testsuite/ld-arm/cortex-a8-fix-bl-plt.d
++++ b/ld/testsuite/ld-arm/cortex-a8-fix-bl-plt.d
+@@ -4,9 +4,9 @@
+
+ Disassembly of section \.plt:
+
+-00008000 <bar@plt-0x14>:
++00008000 <.plt>:
+ 8000: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\)
+- 8004: e59fe004 ldr lr, \[pc, #4\] ; 8010 <bar@plt-0x4>
++ 8004: e59fe004 ldr lr, \[pc, #4\] ; 8010 <.*>
+ 8008: e08fe00e add lr, pc, lr
+ 800c: e5bef008 ldr pc, \[lr, #8\]!
+ 8010: 00000ffc \.word 0x00000ffc
+diff --git a/ld/testsuite/ld-arm/cortex-a8-fix-bl-rel-plt.d b/ld/testsuite/ld-arm/cortex-a8-fix-bl-rel-plt.d
+index c504f79..4a5be27 100644
+--- a/ld/testsuite/ld-arm/cortex-a8-fix-bl-rel-plt.d
++++ b/ld/testsuite/ld-arm/cortex-a8-fix-bl-rel-plt.d
+@@ -4,9 +4,9 @@
+
+ Disassembly of section \.plt:
+
+-00008e00 <targetfn@plt-0x14>:
++00008e00 <.plt>:
+ 8e00: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\)
+- 8e04: e59fe004 ldr lr, \[pc, #4\] ; 8e10 <targetfn@plt-0x4>
++ 8e04: e59fe004 ldr lr, \[pc, #4\] ; 8e10 <.*>
+ 8e08: e08fe00e add lr, pc, lr
+ 8e0c: e5bef008 ldr pc, \[lr, #8\]!
+ 8e10: 0001027c \.word 0x0001027c
+diff --git a/ld/testsuite/ld-arm/cortex-a8-fix-blx-plt.d b/ld/testsuite/ld-arm/cortex-a8-fix-blx-plt.d
+index baad3d0..e4e6760 100644
+--- a/ld/testsuite/ld-arm/cortex-a8-fix-blx-plt.d
++++ b/ld/testsuite/ld-arm/cortex-a8-fix-blx-plt.d
+@@ -4,9 +4,9 @@
+
+ Disassembly of section \.plt:
+
+-00008000 <bar@plt-0x14>:
++00008000 <.plt>:
+ 8000: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\)
+- 8004: e59fe004 ldr lr, \[pc, #4\] ; 8010 <bar@plt-0x4>
++ 8004: e59fe004 ldr lr, \[pc, #4\] ; 8010 <.*>
+ 8008: e08fe00e add lr, pc, lr
+ 800c: e5bef008 ldr pc, \[lr, #8\]!
+ 8010: 00000ffc \.word 0x00000ffc
+diff --git a/ld/testsuite/ld-arm/farcall-mixed-app-v5.d b/ld/testsuite/ld-arm/farcall-mixed-app-v5.d
+index ea0e823..b570bad 100644
+--- a/ld/testsuite/ld-arm/farcall-mixed-app-v5.d
++++ b/ld/testsuite/ld-arm/farcall-mixed-app-v5.d
+@@ -6,9 +6,9 @@ start address 0x.*
+
+ Disassembly of section .plt:
+
+-.* <lib_func2@plt-0x14>:
++.* <.plt>:
+ .*: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\)
+- .*: e59fe004 ldr lr, \[pc, #4\] ; .* <lib_func2@plt-0x4>
++ .*: e59fe004 ldr lr, \[pc, #4\] ; .* <.*>
+ .*: e08fe00e add lr, pc, lr
+ .*: e5bef008 ldr pc, \[lr, #8\]!
+ .*: .*
+diff --git a/ld/testsuite/ld-arm/farcall-mixed-app.d b/ld/testsuite/ld-arm/farcall-mixed-app.d
+index 86127ef..9fa97dc 100644
+--- a/ld/testsuite/ld-arm/farcall-mixed-app.d
++++ b/ld/testsuite/ld-arm/farcall-mixed-app.d
+@@ -6,9 +6,9 @@ start address 0x.*
+
+ Disassembly of section .plt:
+
+-.* <lib_func2@plt-0x14>:
++.* <.plt>:
+ .*: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\)
+- .*: e59fe004 ldr lr, \[pc, #4\] ; .* <lib_func2@plt-0x4>
++ .*: e59fe004 ldr lr, \[pc, #4\] ; .* <.*>
+ .*: e08fe00e add lr, pc, lr
+ .*: e5bef008 ldr pc, \[lr, #8\]!
+ .*: .*
+diff --git a/ld/testsuite/ld-arm/farcall-mixed-lib-v4t.d b/ld/testsuite/ld-arm/farcall-mixed-lib-v4t.d
+index e2dbc1b..fa52ad1 100644
+--- a/ld/testsuite/ld-arm/farcall-mixed-lib-v4t.d
++++ b/ld/testsuite/ld-arm/farcall-mixed-lib-v4t.d
+@@ -5,9 +5,9 @@ start address 0x.*
+
+ Disassembly of section .plt:
+
+-.* <app_func@plt-0x14>:
++.* <.plt>:
+ .*: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\)
+- .*: e59fe004 ldr lr, \[pc, #4\] ; .* <app_func@plt-0x4>
++ .*: e59fe004 ldr lr, \[pc, #4\] ; .* <.*>
+ .*: e08fe00e add lr, pc, lr
+ .*: e5bef008 ldr pc, \[lr, #8\]!
+ .*: .* .word .*
+diff --git a/ld/testsuite/ld-arm/farcall-mixed-lib.d b/ld/testsuite/ld-arm/farcall-mixed-lib.d
+index b736983..ad7352b 100644
+--- a/ld/testsuite/ld-arm/farcall-mixed-lib.d
++++ b/ld/testsuite/ld-arm/farcall-mixed-lib.d
+@@ -5,9 +5,9 @@ start address 0x.*
+
+ Disassembly of section .plt:
+
+-.* <app_func@plt-0x14>:
++.* <.plt>:
+ .*: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\)
+- .*: e59fe004 ldr lr, \[pc, #4\] ; .* <app_func@plt-0x4>
++ .*: e59fe004 ldr lr, \[pc, #4\] ; .* <.*>
+ .*: e08fe00e add lr, pc, lr
+ .*: e5bef008 ldr pc, \[lr, #8\]!
+ .*: .*
+diff --git a/ld/testsuite/ld-arm/ifunc-10.dd b/ld/testsuite/ld-arm/ifunc-10.dd
+index d96c086..05e4be5 100644
+--- a/ld/testsuite/ld-arm/ifunc-10.dd
++++ b/ld/testsuite/ld-arm/ifunc-10.dd
+@@ -4,9 +4,9 @@
+
+ Disassembly of section \.plt:
+
+-00009000 <atf2@plt-0x14>:
++00009000 <.plt>:
+ 9000: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\)
+- 9004: e59fe004 ldr lr, \[pc, #4\] ; 9010 <atf2@plt-0x4>
++ 9004: e59fe004 ldr lr, \[pc, #4\] ; 9010 <.*>
+ 9008: e08fe00e add lr, pc, lr
+ 900c: e5bef008 ldr pc, \[lr, #8\]!
+ #------------------------------------------------------------------------------
+diff --git a/ld/testsuite/ld-arm/ifunc-14.dd b/ld/testsuite/ld-arm/ifunc-14.dd
+index cbad1c8..281373c 100644
+--- a/ld/testsuite/ld-arm/ifunc-14.dd
++++ b/ld/testsuite/ld-arm/ifunc-14.dd
+@@ -4,9 +4,9 @@
+
+ Disassembly of section \.plt:
+
+-00009000 <f2t@plt-0x14>:
++00009000 <.plt>:
+ 9000: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\)
+- 9004: e59fe004 ldr lr, \[pc, #4\] ; 9010 <__irel_end\+0xff0>
++ 9004: e59fe004 ldr lr, \[pc, #4\] ; 9010 <.*>
+ 9008: e08fe00e add lr, pc, lr
+ 900c: e5bef008 ldr pc, \[lr, #8\]!
+ #------------------------------------------------------------------------------
+diff --git a/ld/testsuite/ld-arm/ifunc-15.dd b/ld/testsuite/ld-arm/ifunc-15.dd
+index f23e8e8..d3fbf9d 100644
+--- a/ld/testsuite/ld-arm/ifunc-15.dd
++++ b/ld/testsuite/ld-arm/ifunc-15.dd
+@@ -4,9 +4,9 @@
+
+ Disassembly of section \.plt:
+
+-00009000 <f2t@plt-0x14>:
++00009000 <.plt>:
+ 9000: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\)
+- 9004: e59fe004 ldr lr, \[pc, #4\] ; 9010 <__irel_end\+0xff0>
++ 9004: e59fe004 ldr lr, \[pc, #4\] ; 9010 <.*>
+ 9008: e08fe00e add lr, pc, lr
+ 900c: e5bef008 ldr pc, \[lr, #8\]!
+ #------------------------------------------------------------------------------
+diff --git a/ld/testsuite/ld-arm/ifunc-3.dd b/ld/testsuite/ld-arm/ifunc-3.dd
+index b267bf1..2297e5a 100644
+--- a/ld/testsuite/ld-arm/ifunc-3.dd
++++ b/ld/testsuite/ld-arm/ifunc-3.dd
+@@ -4,9 +4,9 @@
+
+ Disassembly of section \.plt:
+
+-00009000 <f2@plt-0x14>:
++00009000 <.plt>:
+ 9000: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\)
+- 9004: e59fe004 ldr lr, \[pc, #4\] ; 9010 <f2@plt-0x4>
++ 9004: e59fe004 ldr lr, \[pc, #4\] ; 9010 <.*>
+ 9008: e08fe00e add lr, pc, lr
+ 900c: e5bef008 ldr pc, \[lr, #8\]!
+ #------------------------------------------------------------------------------
+diff --git a/ld/testsuite/ld-arm/ifunc-4.dd b/ld/testsuite/ld-arm/ifunc-4.dd
+index 6ce996b..647a340 100644
+--- a/ld/testsuite/ld-arm/ifunc-4.dd
++++ b/ld/testsuite/ld-arm/ifunc-4.dd
+@@ -4,9 +4,9 @@
+
+ Disassembly of section \.plt:
+
+-00009000 <atf2@plt-0x14>:
++00009000 <.plt>:
+ 9000: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\)
+- 9004: e59fe004 ldr lr, \[pc, #4\] ; 9010 <atf2@plt-0x4>
++ 9004: e59fe004 ldr lr, \[pc, #4\] ; 9010 <.*>
+ 9008: e08fe00e add lr, pc, lr
+ 900c: e5bef008 ldr pc, \[lr, #8\]!
+ #------------------------------------------------------------------------------
+diff --git a/ld/testsuite/ld-arm/ifunc-9.dd b/ld/testsuite/ld-arm/ifunc-9.dd
+index af7ec4b..cc4afa8 100644
+--- a/ld/testsuite/ld-arm/ifunc-9.dd
++++ b/ld/testsuite/ld-arm/ifunc-9.dd
+@@ -4,9 +4,9 @@
+
+ Disassembly of section \.plt:
+
+-00009000 <f2@plt-0x14>:
++00009000 <.plt>:
+ 9000: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\)
+- 9004: e59fe004 ldr lr, \[pc, #4\] ; 9010 <f2@plt-0x4>
++ 9004: e59fe004 ldr lr, \[pc, #4\] ; 9010 <.*>
+ 9008: e08fe00e add lr, pc, lr
+ 900c: e5bef008 ldr pc, \[lr, #8\]!
+ #------------------------------------------------------------------------------
+diff --git a/ld/testsuite/ld-arm/long-plt-format.d b/ld/testsuite/ld-arm/long-plt-format.d
+index b0a1abc..b14d9b5 100644
+--- a/ld/testsuite/ld-arm/long-plt-format.d
++++ b/ld/testsuite/ld-arm/long-plt-format.d
+@@ -3,7 +3,7 @@
+
+ Disassembly of section .plt:
+
+-.* <foo@plt-0x14>:
++.* <.plt>:
+ .*: .*
+ .*: .*
+ .*: .*
+diff --git a/ld/testsuite/ld-arm/mixed-app-v5.d b/ld/testsuite/ld-arm/mixed-app-v5.d
+index 0ad39e6..9c734a9 100644
+--- a/ld/testsuite/ld-arm/mixed-app-v5.d
++++ b/ld/testsuite/ld-arm/mixed-app-v5.d
+@@ -6,9 +6,9 @@ start address 0x.*
+
+ Disassembly of section .plt:
+
+-.* <lib_func2@plt-0x14>:
++.* <.plt>:
+ .*: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\)
+- .*: e59fe004 ldr lr, \[pc, #4\] ; .* <lib_func2@plt-0x4>
++ .*: e59fe004 ldr lr, \[pc, #4\] ; .* <.*>
+ .*: e08fe00e add lr, pc, lr
+ .*: e5bef008 ldr pc, \[lr, #8\]!
+ .*: .*
+diff --git a/ld/testsuite/ld-arm/mixed-app.d b/ld/testsuite/ld-arm/mixed-app.d
+index 6083161..4bcbdad 100644
+--- a/ld/testsuite/ld-arm/mixed-app.d
++++ b/ld/testsuite/ld-arm/mixed-app.d
+@@ -6,9 +6,9 @@ start address 0x.*
+
+ Disassembly of section .plt:
+
+-.* <lib_func2@plt-0x14>:
++.* <.plt>:
+ .*: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\)
+- .*: e59fe004 ldr lr, \[pc, #4\] ; .* <lib_func2@plt-0x4>
++ .*: e59fe004 ldr lr, \[pc, #4\] ; .* <.*>
+ .*: e08fe00e add lr, pc, lr
+ .*: e5bef008 ldr pc, \[lr, #8\]!
+ .*: .*
+diff --git a/ld/testsuite/ld-arm/mixed-lib.d b/ld/testsuite/ld-arm/mixed-lib.d
+index 271692c..a4bb26b 100644
+--- a/ld/testsuite/ld-arm/mixed-lib.d
++++ b/ld/testsuite/ld-arm/mixed-lib.d
+@@ -6,9 +6,9 @@ start address 0x.*
+
+ Disassembly of section .plt:
+
+-.* <app_func2@plt-0x14>:
++.* <.plt>:
+ .*: e52de004 push {lr} ; \(str lr, \[sp, #-4\]!\)
+- .*: e59fe004 ldr lr, \[pc, #4\] ; .* <app_func2@plt-0x4>
++ .*: e59fe004 ldr lr, \[pc, #4\] ; .* <.*>
+ .*: e08fe00e add lr, pc, lr
+ .*: e5bef008 ldr pc, \[lr, #8\]!
+ .*: .*
+diff --git a/ld/testsuite/ld-arm/tls-lib-loc.d b/ld/testsuite/ld-arm/tls-lib-loc.d
+index 27789b4..2e641b3 100644
+--- a/ld/testsuite/ld-arm/tls-lib-loc.d
++++ b/ld/testsuite/ld-arm/tls-lib-loc.d
+@@ -28,6 +28,6 @@ Disassembly of section .text:
+
+ [0-9a-f]+ <foo>:
+ [0-9a-f]+: e59f0004 ldr r0, \[pc, #4\] ; 818c .*
+- [0-9a-f]+: fafffff2 blx 8154 <.*\+0x8154>
++ [0-9a-f]+: fafffff2 blx 8154 <.*>
+ [0-9a-f]+: e1a00000 nop ; .*
+ 818c: 000080a0 .word 0x000080a0
+diff --git a/ld/testsuite/ld-cris/dso-pltdis1.d b/ld/testsuite/ld-cris/dso-pltdis1.d
+index 4bc3c70..e2c0f93 100644
+--- a/ld/testsuite/ld-cris/dso-pltdis1.d
++++ b/ld/testsuite/ld-cris/dso-pltdis1.d
+@@ -20,7 +20,7 @@
+
+ Disassembly of section \.plt:
+
+-0+1b4 <(dsofn4@plt-0x1a|dsofn@plt-0x34)>:
++0+1b4 <.*>:
+ 1b4: 84e2 subq 4,\$sp
+ 1b6: 0401 addoq 4,\$r0,\$acr
+ 1b8: 7e7a move \$mof,\[\$sp\]
+@@ -45,7 +45,7 @@ Disassembly of section \.plt:
+ 1f0: bf09 jump \$acr
+ 1f2: b005 nop
+ 1f4: 3f7e .... .... move .*,\$mof
+- 1fa: bf0e baff ffff ba 1b4 <(dsofn4@plt-0x1a|dsofn@plt-0x34)>
++ 1fa: bf0e baff ffff ba 1b4 <.*>
+ 200: b005 nop
+
+ Disassembly of section \.text:
+@@ -57,5 +57,5 @@ Disassembly of section \.text:
+ 0+20a <dsofn4>:
+ 20a: 7f0d ae20 0000 lapc 22b8 <_GLOBAL_OFFSET_TABLE_>,\$r0
+ 210: 5f0d 1400 addo\.w 0x14,\$r0,\$acr
+- 214: bfbe baff ffff bsr 1ce <(dsofn4@plt|dsofn@plt-0x1a)>
++ 214: bfbe baff ffff bsr 1ce <.*>
+ #pass
+diff --git a/ld/testsuite/ld-cris/dso-pltdis2.d b/ld/testsuite/ld-cris/dso-pltdis2.d
+index 5348a8a..24da97a 100644
+--- a/ld/testsuite/ld-cris/dso-pltdis2.d
++++ b/ld/testsuite/ld-cris/dso-pltdis2.d
+@@ -12,7 +12,7 @@
+
+ Disassembly of section \.plt:
+
+-0+1b4 <(dsofn4@plt-0x1a|dsofn@plt-0x34)>:
++0+1b4 <.*>:
+
+ 1b4: 84e2 subq 4,\$sp
+ 1b6: 0401 addoq 4,\$r0,\$acr
+@@ -44,7 +44,7 @@ Disassembly of section \.plt:
+ Disassembly of section \.text:
+ #...
+ 0+202 <dsofn3>:
+- 202: bfbe e6ff ffff bsr 1e8 <(dsofn@plt|dsofn4@plt\+0x1a)>
++ 202: bfbe e6ff ffff bsr 1e8 <.*>
+ 208: b005 nop
+
+ 0+20a <dsofn4>:
+diff --git a/ld/testsuite/ld-cris/dso12-pltdis.d b/ld/testsuite/ld-cris/dso12-pltdis.d
+index 71a1748..187730b 100644
+--- a/ld/testsuite/ld-cris/dso12-pltdis.d
++++ b/ld/testsuite/ld-cris/dso12-pltdis.d
+@@ -11,7 +11,7 @@
+
+ Disassembly of section \.plt:
+
+-0+1e4 <dsofn4@plt-0x1a>:
++0+1e4 <.plt>:
+
+ 1e4: 84e2 subq 4,\$sp
+ 1e6: 0401 addoq 4,\$r0,\$acr
+@@ -24,21 +24,21 @@ Disassembly of section \.plt:
+ \.\.\.
+
+ 0+1fe <dsofn4@plt>:
+- 1fe: 6f0d 0c00 0000 addo\.d c <dsofn4@plt-0x1f2>,\$r0,\$acr
++ 1fe: 6f0d 0c00 0000 addo\.d c <.*>,\$r0,\$acr
+ 204: 6ffa move\.d \[\$acr\],\$acr
+ 206: bf09 jump \$acr
+ 208: b005 nop
+- 20a: 3f7e 0000 0000 move 0 <dsofn4@plt-0x1fe>,\$mof
+- 210: bf0e d4ff ffff ba 1e4 <dsofn4@plt-0x1a>
++ 20a: 3f7e 0000 0000 move 0 <.*>,\$mof
++ 210: bf0e d4ff ffff ba 1e4 <.*>
+ 216: b005 nop
+
+ 0+218 <dsofn@plt>:
+- 218: 6f0d 1000 0000 addo\.d 10 <dsofn4@plt-0x1ee>,\$r0,\$acr
++ 218: 6f0d 1000 0000 addo\.d 10 <.*>,\$r0,\$acr
+ 21e: 6ffa move\.d \[\$acr\],\$acr
+ 220: bf09 jump \$acr
+ 222: b005 nop
+- 224: 3f7e 0c00 0000 move c <dsofn4@plt-0x1f2>,\$mof
+- 22a: bf0e baff ffff ba 1e4 <dsofn4@plt-0x1a>
++ 224: 3f7e 0c00 0000 move c <.*>,\$mof
++ 22a: bf0e baff ffff ba 1e4 <.*>
+ 230: b005 nop
+
+ Disassembly of section \.text:
+diff --git a/ld/testsuite/ld-elf/symbolic-func.r b/ld/testsuite/ld-elf/symbolic-func.r
+index 3d31f8f..448b01a 100644
+--- a/ld/testsuite/ld-elf/symbolic-func.r
++++ b/ld/testsuite/ld-elf/symbolic-func.r
+@@ -14,5 +14,5 @@
+
+ Relocation section.*
+ *Offset.*
+-0*[1-9a-f][0-9a-f]* +[^ ]+ +[^ ]+ +([0-9a-f]+( +\.text( \+ [0-9a-f]+)?)?)?
++0*[1-9a-f][0-9a-f]* +[^ ]+ +[^ ]+ +([0-9a-f]+( +(\.text|fun)( \+ [0-9a-f]+)?)?)?
+ #pass
+diff --git a/ld/testsuite/ld-frv/fdpic-pie-1.d b/ld/testsuite/ld-frv/fdpic-pie-1.d
+index 0e37324..5369d07 100644
+--- a/ld/testsuite/ld-frv/fdpic-pie-1.d
++++ b/ld/testsuite/ld-frv/fdpic-pie-1.d
+@@ -42,7 +42,7 @@ Disassembly of section \.data:
+ [0-9a-f ]+: R_FRV_32 \.text
+ Disassembly of section \.got:
+
+-[0-9a-f ]+<_GLOBAL_OFFSET_TABLE_-0x8>:
++[0-9a-f ]+<.got>:
+ [0-9a-f ]+: 00 00 00 04 add\.p gr0,gr4,gr0
+ [0-9a-f ]+: R_FRV_FUNCDESC_VALUE \.text
+ [0-9a-f ]+: 00 00 00 02 add\.p gr0,fp,gr0
+diff --git a/ld/testsuite/ld-frv/fdpic-pie-2.d b/ld/testsuite/ld-frv/fdpic-pie-2.d
+index 3583a3b..40c1532 100644
+--- a/ld/testsuite/ld-frv/fdpic-pie-2.d
++++ b/ld/testsuite/ld-frv/fdpic-pie-2.d
+@@ -42,7 +42,7 @@ Disassembly of section \.dat[0-9a-f ]+:
+ [0-9a-f ]+: R_FRV_32 \.text
+ Disassembly of section \.got:
+
+-[0-9a-f ]+<_GLOBAL_OFFSET_TABLE_-0x18>:
++[0-9a-f ]+<.got>:
+ [0-9a-f ]+: 00 00 00 04 add\.p gr0,gr4,gr0
+ [0-9a-f ]+: R_FRV_FUNCDESC_VALUE \.text
+ [0-9a-f ]+: 00 00 00 02 add\.p gr0,fp,gr0
+diff --git a/ld/testsuite/ld-frv/fdpic-pie-6.d b/ld/testsuite/ld-frv/fdpic-pie-6.d
+index c59b304..743166e 100644
+--- a/ld/testsuite/ld-frv/fdpic-pie-6.d
++++ b/ld/testsuite/ld-frv/fdpic-pie-6.d
+@@ -9,11 +9,11 @@ Disassembly of section \.plt:
+
+ [0-9a-f ]+<\.plt>:
+ [0-9a-f ]+: 00 00 00 08 add\.p gr0,gr8,gr0
+-[0-9a-f ]+: c0 1a 00 06 bra [0-9a-f]+ <F6-0x10>
++[0-9a-f ]+: c0 1a 00 06 bra [0-9a-f]+ <.*>
+ [0-9a-f ]+: 00 00 00 00 add\.p gr0,gr0,gr0
+-[0-9a-f ]+: c0 1a 00 04 bra [0-9a-f]+ <F6-0x10>
++[0-9a-f ]+: c0 1a 00 04 bra [0-9a-f]+ <.*>
+ [0-9a-f ]+: 00 00 00 10 add\.p gr0,gr16,gr0
+-[0-9a-f ]+: c0 1a 00 02 bra [0-9a-f]+ <F6-0x10>
++[0-9a-f ]+: c0 1a 00 02 bra [0-9a-f]+ <.*>
+ [0-9a-f ]+: 00 00 00 18 add\.p gr0,gr24,gr0
+ [0-9a-f ]+: 88 08 f1 40 ldd @\(gr15,gr0\),gr4
+ [0-9a-f ]+: 80 30 40 00 jmpl @\(gr4,gr0\)
+@@ -22,7 +22,7 @@ Disassembly of section \.plt:
+ Disassembly of section \.text:
+
+ [0-9a-f ]+<F6>:
+-[0-9a-f ]+: fe 3f ff fe call [0-9a-f]+ <F6-0x8>
++[0-9a-f ]+: fe 3f ff fe call [0-9a-f]+ <.*>
+ [0-9a-f ]+: 80 40 f0 0c addi gr15,12,gr0
+ [0-9a-f ]+: 80 fc 00 24 setlos 0x24,gr0
+ [0-9a-f ]+: 80 f4 00 20 setlo 0x20,gr0
+@@ -48,7 +48,7 @@ Disassembly of section \.dat[0-9a-f ]+:
+ [0-9a-f ]+: R_FRV_32 WFb
+ Disassembly of section \.got:
+
+-[0-9a-f ]+<_GLOBAL_OFFSET_TABLE_-0x20>:
++[0-9a-f ]+<.got>:
+ [0-9a-f ]+: 00 00 03 b0 .*
+ [0-9a-f ]+: R_FRV_FUNCDESC_VALUE WF9
+ [0-9a-f ]+: 00 00 00 02 .*
+diff --git a/ld/testsuite/ld-frv/fdpic-pie-7.d b/ld/testsuite/ld-frv/fdpic-pie-7.d
+index 7ebd0b7..7eceec2 100644
+--- a/ld/testsuite/ld-frv/fdpic-pie-7.d
++++ b/ld/testsuite/ld-frv/fdpic-pie-7.d
+@@ -42,7 +42,7 @@ Disassembly of section \.dat[0-9a-f ]+:
+ [0-9a-f ]+: R_FRV_32 \.text
+ Disassembly of section \.got:
+
+-[0-9a-f ]+<_GLOBAL_OFFSET_TABLE_-0x8>:
++[0-9a-f ]+<.got>:
+ [0-9a-f ]+: 00 00 00 08 add\.p gr0,gr8,gr0
+ [0-9a-f ]+: R_FRV_FUNCDESC_VALUE \.text
+ [0-9a-f ]+: 00 00 00 02 add\.p gr0,fp,gr0
+diff --git a/ld/testsuite/ld-frv/fdpic-pie-8.d b/ld/testsuite/ld-frv/fdpic-pie-8.d
+index 0de4a81..8f7c344 100644
+--- a/ld/testsuite/ld-frv/fdpic-pie-8.d
++++ b/ld/testsuite/ld-frv/fdpic-pie-8.d
+@@ -42,7 +42,7 @@ Disassembly of section \.dat[0-9a-f ]+:
+ [0-9a-f ]+: R_FRV_32 \.text
+ Disassembly of section \.got:
+
+-[0-9a-f ]+<_GLOBAL_OFFSET_TABLE_-0x18>:
++[0-9a-f ]+<.got>:
+ [0-9a-f ]+: 00 00 00 08 add\.p gr0,gr8,gr0
+ [0-9a-f ]+: R_FRV_FUNCDESC_VALUE \.text
+ [0-9a-f ]+: 00 00 00 02 add\.p gr0,fp,gr0
+diff --git a/ld/testsuite/ld-frv/fdpic-shared-1.d b/ld/testsuite/ld-frv/fdpic-shared-1.d
+index 7f88e18..4968deb 100644
+--- a/ld/testsuite/ld-frv/fdpic-shared-1.d
++++ b/ld/testsuite/ld-frv/fdpic-shared-1.d
+@@ -42,7 +42,7 @@ Disassembly of section \.dat[0-9a-f ]+:
+ [0-9a-f ]+: R_FRV_32 \.text
+ Disassembly of section \.got:
+
+-[0-9a-f ]+<_GLOBAL_OFFSET_TABLE_-0x8>:
++[0-9a-f ]+<.got>:
+ [0-9a-f ]+: 00 00 00 04 add\.p gr0,gr4,gr0
+ [0-9a-f ]+: R_FRV_FUNCDESC_VALUE \.text
+ [0-9a-f ]+: 00 00 00 00 add\.p gr0,gr0,gr0
+diff --git a/ld/testsuite/ld-frv/fdpic-shared-2.d b/ld/testsuite/ld-frv/fdpic-shared-2.d
+index cb4b68d..13e140a 100644
+--- a/ld/testsuite/ld-frv/fdpic-shared-2.d
++++ b/ld/testsuite/ld-frv/fdpic-shared-2.d
+@@ -9,11 +9,11 @@ Disassembly of section \.plt:
+
+ [0-9a-f ]+ <\.plt>:
+ [0-9a-f ]+: 00 00 00 00 add\.p gr0,gr0,gr0
+-[0-9a-f ]+: c0 1a 00 06 bra [0-9a-f]+ <F2-0x10>
++[0-9a-f ]+: c0 1a 00 06 bra [0-9a-f]+ <.*>
+ [0-9a-f ]+: 00 00 00 10 add\.p gr0,gr16,gr0
+-[0-9a-f ]+: c0 1a 00 04 bra [0-9a-f]+ <F2-0x10>
++[0-9a-f ]+: c0 1a 00 04 bra [0-9a-f]+ <.*>
+ [0-9a-f ]+: 00 00 00 18 add\.p gr0,gr24,gr0
+-[0-9a-f ]+: c0 1a 00 02 bra [0-9a-f]+ <F2-0x10>
++[0-9a-f ]+: c0 1a 00 02 bra [0-9a-f]+ <.*>
+ [0-9a-f ]+: 00 00 00 08 add\.p gr0,gr8,gr0
+ [0-9a-f ]+: 88 08 f1 40 ldd @\(gr15,gr0\),gr4
+ [0-9a-f ]+: 80 30 40 00 jmpl @\(gr4,gr0\)
+@@ -22,7 +22,7 @@ Disassembly of section \.plt:
+ Disassembly of section \.text:
+
+ [0-9a-f ]+<F2>:
+-[0-9a-f ]+: fe 3f ff fe call [0-9a-f]+ <F2-0x8>
++[0-9a-f ]+: fe 3f ff fe call [0-9a-f]+ <.*>
+
+ [0-9a-f ]+<GF0>:
+ [0-9a-f ]+: 80 40 f0 10 addi gr15,16,gr0
+@@ -55,7 +55,7 @@ Disassembly of section \.dat[0-9a-f ]+:
+ [0-9a-f ]+: R_FRV_32 GFb
+ [0-9A-F ]+isassembly of section \.got:
+
+-[0-9a-f ]+<_GLOBAL_OFFSET_TABLE_-0x20>:
++[0-9a-f ]+<.got>:
+ [0-9a-f ]+: 00 00 04 a4 .*
+ [0-9a-f ]+: R_FRV_FUNCDESC_VALUE GF9
+ [0-9a-f ]+: 00 00 00 00 .*
+diff --git a/ld/testsuite/ld-frv/fdpic-shared-3.d b/ld/testsuite/ld-frv/fdpic-shared-3.d
+index fceb16a..fc59185 100644
+--- a/ld/testsuite/ld-frv/fdpic-shared-3.d
++++ b/ld/testsuite/ld-frv/fdpic-shared-3.d
+@@ -42,7 +42,7 @@ Disassembly of section \.dat[0-9a-f ]+:
+ [0-9a-f ]+: R_FRV_32 \.text
+ Disassembly of section \.got:
+
+-[0-9a-f ]+<_GLOBAL_OFFSET_TABLE_-0x38>:
++[0-9a-f ]+<.got>:
+ [0-9a-f ]+: 00 00 00 04 add\.p gr0,gr4,gr0
+ [0-9a-f ]+: R_FRV_FUNCDESC_VALUE \.text
+ [0-9a-f ]+: 00 00 00 00 add\.p gr0,gr0,gr0
+diff --git a/ld/testsuite/ld-frv/fdpic-shared-4.d b/ld/testsuite/ld-frv/fdpic-shared-4.d
+index 4045562..298ae28 100644
+--- a/ld/testsuite/ld-frv/fdpic-shared-4.d
++++ b/ld/testsuite/ld-frv/fdpic-shared-4.d
+@@ -42,7 +42,7 @@ Disassembly of section \.dat[0-9a-f ]+:
+ [0-9a-f ]+: R_FRV_32 \.text
+ Disassembly of section \.got:
+
+-[0-9a-f ]+<_GLOBAL_OFFSET_TABLE_-0x18>:
++[0-9a-f ]+<.got>:
+ [0-9a-f ]+: 00 00 00 04 add\.p gr0,gr4,gr0
+ [0-9a-f ]+: R_FRV_FUNCDESC_VALUE \.text
+ [0-9a-f ]+: 00 00 00 00 add\.p gr0,gr0,gr0
+diff --git a/ld/testsuite/ld-frv/fdpic-shared-5.d b/ld/testsuite/ld-frv/fdpic-shared-5.d
+index 009c62c..dbfd143 100644
+--- a/ld/testsuite/ld-frv/fdpic-shared-5.d
++++ b/ld/testsuite/ld-frv/fdpic-shared-5.d
+@@ -9,11 +9,11 @@ Disassembly of section \.plt:
+
+ [0-9a-f ]+<\.plt>:
+ [0-9a-f ]+: 00 00 00 10 add\.p gr0,gr16,gr0
+-[0-9a-f ]+: c0 1a 00 06 bra [0-9a-f]+ <F5-0x10>
++[0-9a-f ]+: c0 1a 00 06 bra [0-9a-f]+ <.*>
+ [0-9a-f ]+: 00 00 00 08 add\.p gr0,gr8,gr0
+-[0-9a-f ]+: c0 1a 00 04 bra [0-9a-f]+ <F5-0x10>
++[0-9a-f ]+: c0 1a 00 04 bra [0-9a-f]+ <.*>
+ [0-9a-f ]+: 00 00 00 00 add\.p gr0,gr0,gr0
+-[0-9a-f ]+: c0 1a 00 02 bra [0-9a-f]+ <F5-0x10>
++[0-9a-f ]+: c0 1a 00 02 bra [0-9a-f]+ <.*>
+ [0-9a-f ]+: 00 00 00 18 add\.p gr0,gr24,gr0
+ [0-9a-f ]+: 88 08 f1 40 ldd @\(gr15,gr0\),gr4
+ [0-9a-f ]+: 80 30 40 00 jmpl @\(gr4,gr0\)
+@@ -22,7 +22,7 @@ Disassembly of section \.plt:
+ Disassembly of section \.text:
+
+ [0-9a-f ]+<F5>:
+-[0-9a-f ]+: fe 3f ff fe call [0-9a-f]+ <F5-0x8>
++[0-9a-f ]+: fe 3f ff fe call [0-9a-f]+ <.*>
+ [0-9a-f ]+: 80 40 f0 0c addi gr15,12,gr0
+ [0-9a-f ]+: 80 fc 00 24 setlos 0x24,gr0
+ [0-9a-f ]+: 80 f4 00 20 setlo 0x20,gr0
+@@ -48,7 +48,7 @@ Disassembly of section \.dat[0-9a-f ]+:
+ [0-9a-f ]+: R_FRV_32 UFb
+ Disassembly of section \.got:
+
+-[0-9a-f ]+<_GLOBAL_OFFSET_TABLE_-0x20>:
++[0-9a-f ]+<.got>:
+ [0-9a-f ]+: 00 00 04 7c .*
+ [0-9a-f ]+: R_FRV_FUNCDESC_VALUE UF9
+ [0-9a-f ]+: 00 00 00 00 .*
+diff --git a/ld/testsuite/ld-frv/fdpic-shared-6.d b/ld/testsuite/ld-frv/fdpic-shared-6.d
+index 06a335f..2191af8 100644
+--- a/ld/testsuite/ld-frv/fdpic-shared-6.d
++++ b/ld/testsuite/ld-frv/fdpic-shared-6.d
+@@ -9,11 +9,11 @@ Disassembly of section \.plt:
+
+ [0-9a-f ]+<\.plt>:
+ [0-9a-f ]+: 00 00 00 08 add\.p gr0,gr8,gr0
+-[0-9a-f ]+: c0 1a 00 06 bra [0-9a-f]+ <F6-0x10>
++[0-9a-f ]+: c0 1a 00 06 bra [0-9a-f]+ <.*>
+ [0-9a-f ]+: 00 00 00 00 add\.p gr0,gr0,gr0
+-[0-9a-f ]+: c0 1a 00 04 bra [0-9a-f]+ <F6-0x10>
++[0-9a-f ]+: c0 1a 00 04 bra [0-9a-f]+ <.*>
+ [0-9a-f ]+: 00 00 00 10 add\.p gr0,gr16,gr0
+-[0-9a-f ]+: c0 1a 00 02 bra [0-9a-f]+ <F6-0x10>
++[0-9a-f ]+: c0 1a 00 02 bra [0-9a-f]+ <.*>
+ [0-9a-f ]+: 00 00 00 18 add\.p gr0,gr24,gr0
+ [0-9a-f ]+: 88 08 f1 40 ldd @\(gr15,gr0\),gr4
+ [0-9a-f ]+: 80 30 40 00 jmpl @\(gr4,gr0\)
+@@ -22,7 +22,7 @@ Disassembly of section \.plt:
+ Disassembly of section \.text:
+
+ [0-9a-f ]+<F6>:
+-[0-9a-f ]+: fe 3f ff fe call [0-9a-f]+ <F6-0x8>
++[0-9a-f ]+: fe 3f ff fe call [0-9a-f]+ <.*>
+ [0-9a-f ]+: 80 40 f0 0c addi gr15,12,gr0
+ [0-9a-f ]+: 80 fc 00 24 setlos 0x24,gr0
+ [0-9a-f ]+: 80 f4 00 20 setlo 0x20,gr0
+@@ -48,7 +48,7 @@ Disassembly of section \.dat[0-9a-f ]+:
+ [0-9a-f ]+: R_FRV_32 WFb
+ Disassembly of section \.got:
+
+-[0-9a-f ]+<_GLOBAL_OFFSET_TABLE_-0x20>:
++[0-9a-f ]+<.got>:
+ [0-9a-f ]+: 00 00 03 60 .*
+ [0-9a-f ]+: R_FRV_FUNCDESC_VALUE WF9
+ [0-9a-f ]+: 00 00 00 00 .*
+diff --git a/ld/testsuite/ld-frv/fdpic-shared-7.d b/ld/testsuite/ld-frv/fdpic-shared-7.d
+index 2004a84..071dd8f 100644
+--- a/ld/testsuite/ld-frv/fdpic-shared-7.d
++++ b/ld/testsuite/ld-frv/fdpic-shared-7.d
+@@ -42,7 +42,7 @@ Disassembly of section \.dat[0-9a-f ]+:
+ [0-9a-f ]+: R_FRV_32 \.text
+ Disassembly of section \.got:
+
+-[0-9a-f ]+<_GLOBAL_OFFSET_TABLE_-0x8>:
++[0-9a-f ]+<.got>:
+ [0-9a-f ]+: 00 00 00 08 add\.p gr0,gr8,gr0
+ [0-9a-f ]+: R_FRV_FUNCDESC_VALUE \.text
+ [0-9a-f ]+: 00 00 00 00 add\.p gr0,gr0,gr0
+diff --git a/ld/testsuite/ld-frv/fdpic-shared-8.d b/ld/testsuite/ld-frv/fdpic-shared-8.d
+index 543d313..e50e7b9 100644
+--- a/ld/testsuite/ld-frv/fdpic-shared-8.d
++++ b/ld/testsuite/ld-frv/fdpic-shared-8.d
+@@ -42,7 +42,7 @@ Disassembly of section \.text:
+ [0-9a-f ]+: R_FRV_32 \.text
+ Disassembly of section \.got:
+
+-[0-9a-f ]+<_GLOBAL_OFFSET_TABLE_-0x38>:
++[0-9a-f ]+<.got>:
+ [0-9a-f ]+: 00 00 00 08 add\.p gr0,gr8,gr0
+ [0-9a-f ]+: R_FRV_FUNCDESC_VALUE \.text
+ [0-9a-f ]+: 00 00 00 00 add\.p gr0,gr0,gr0
+diff --git a/ld/testsuite/ld-frv/fdpic-shared-local-2.d b/ld/testsuite/ld-frv/fdpic-shared-local-2.d
+index 51ca126..0074172 100644
+--- a/ld/testsuite/ld-frv/fdpic-shared-local-2.d
++++ b/ld/testsuite/ld-frv/fdpic-shared-local-2.d
+@@ -42,7 +42,7 @@ Disassembly of section \.dat[0-9a-f ]+:
+ [0-9a-f ]+: R_FRV_32 \.text
+ Disassembly of section \.got:
+
+-[0-9a-f ]+<_GLOBAL_OFFSET_TABLE_-0x38>:
++[0-9a-f ]+<.got>:
+ [0-9a-f ]+: 00 00 00 04 add\.p gr0,gr4,gr0
+ [0-9a-f ]+: R_FRV_FUNCDESC_VALUE \.text
+ [0-9a-f ]+: 00 00 00 00 add\.p gr0,gr0,gr0
+diff --git a/ld/testsuite/ld-frv/fdpic-shared-local-8.d b/ld/testsuite/ld-frv/fdpic-shared-local-8.d
+index 8d2c67e..7d238e9 100644
+--- a/ld/testsuite/ld-frv/fdpic-shared-local-8.d
++++ b/ld/testsuite/ld-frv/fdpic-shared-local-8.d
+@@ -42,7 +42,7 @@ Disassembly of section \.dat[0-9a-f ]+:
+ [0-9a-f ]+: R_FRV_32 \.text
+ Disassembly of section \.got:
+
+-[0-9a-f ]+<_GLOBAL_OFFSET_TABLE_-0x38>:
++[0-9a-f ]+<.got>:
+ [0-9a-f ]+: 00 00 00 08 add\.p gr0,gr8,gr0
+ [0-9a-f ]+: R_FRV_FUNCDESC_VALUE \.text
+ [0-9a-f ]+: 00 00 00 00 add\.p gr0,gr0,gr0
+diff --git a/ld/testsuite/ld-frv/fdpic-static-1.d b/ld/testsuite/ld-frv/fdpic-static-1.d
+index 1c4dce1..9bab5d7 100644
+--- a/ld/testsuite/ld-frv/fdpic-static-1.d
++++ b/ld/testsuite/ld-frv/fdpic-static-1.d
+@@ -51,7 +51,7 @@ Disassembly of section \.dat[0-9a-f ]+:
+ [0-9a-f ]+: 00 01 00 98 addx\.p gr16,gr24,gr0,icc0
+ Disassembly of section \.got:
+
+-[0-9a-f ]+<_GLOBAL_OFFSET_TABLE_-0x8>:
++[0-9a-f ]+<.got>:
+ [0-9a-f ]+: 00 01 00 98 addx\.p gr16,gr24,gr0,icc0
+ [0-9a-f ]+: 00 01 41 18 sub\.p gr20,gr24,gr0
+
+diff --git a/ld/testsuite/ld-frv/fdpic-static-2.d b/ld/testsuite/ld-frv/fdpic-static-2.d
+index d2b794f..e388e2c 100644
+--- a/ld/testsuite/ld-frv/fdpic-static-2.d
++++ b/ld/testsuite/ld-frv/fdpic-static-2.d
+@@ -67,7 +67,7 @@ Disassembly of section \.dat[0-9a-f ]+:
+ [0-9a-f ]+: 00 01 00 98 addx\.p gr16,gr24,gr0,icc0
+ Disassembly of section \.got:
+
+-[0-9a-f ]+<_GLOBAL_OFFSET_TABLE_-0x38>:
++[0-9a-f ]+<.got>:
+ [0-9a-f ]+: 00 01 00 98 addx\.p gr16,gr24,gr0,icc0
+ [0-9a-f ]+: 00 01 41 88 subx\.p gr20,gr8,gr0,icc0
+ [0-9a-f ]+: 00 01 00 98 addx\.p gr16,gr24,gr0,icc0
+diff --git a/ld/testsuite/ld-frv/fdpic-static-6.d b/ld/testsuite/ld-frv/fdpic-static-6.d
+index 491b7c7..1c197a2 100644
+--- a/ld/testsuite/ld-frv/fdpic-static-6.d
++++ b/ld/testsuite/ld-frv/fdpic-static-6.d
+@@ -36,7 +36,7 @@ Disassembly of section \.dat[0-9a-f ]+:
+ \.\.\.
+ Disassembly of section \.got:
+
+-[0-9a-f ]+<_GLOBAL_OFFSET_TABLE_-0x38>:
++[0-9a-f ]+<.got>:
+ \.\.\.
+
+ [0-9a-f ]+<_GLOBAL_OFFSET_TABLE_>:
+diff --git a/ld/testsuite/ld-frv/fdpic-static-7.d b/ld/testsuite/ld-frv/fdpic-static-7.d
+index 6f8313c..77899f6 100644
+--- a/ld/testsuite/ld-frv/fdpic-static-7.d
++++ b/ld/testsuite/ld-frv/fdpic-static-7.d
+@@ -51,7 +51,7 @@ Disassembly of section \.dat[0-9a-f ]+:
+ [0-9a-f ]+: 00 01 00 9c addx\.p gr16,gr28,gr0,icc0
+ Disassembly of section \.got:
+
+-[0-9a-f ]+<_GLOBAL_OFFSET_TABLE_-0x8>:
++[0-9a-f ]+<.got>:
+ [0-9a-f ]+: 00 01 00 9c addx\.p gr16,gr28,gr0,icc0
+ [0-9a-f ]+: 00 01 41 18 sub\.p gr20,gr24,gr0
+
+diff --git a/ld/testsuite/ld-frv/fdpic-static-8.d b/ld/testsuite/ld-frv/fdpic-static-8.d
+index c0cc732..03e795e 100644
+--- a/ld/testsuite/ld-frv/fdpic-static-8.d
++++ b/ld/testsuite/ld-frv/fdpic-static-8.d
+@@ -67,7 +67,7 @@ Disassembly of section \.dat[0-9a-f ]+:
+ [0-9a-f ]+: 00 01 00 9c addx\.p gr16,gr28,gr0,icc0
+ Disassembly of section \.got:
+
+-[0-9a-f ]+<_GLOBAL_OFFSET_TABLE_-0x38>:
++[0-9a-f ]+<.got>:
+ [0-9a-f ]+: 00 01 00 9c addx\.p gr16,gr28,gr0,icc0
+ [0-9a-f ]+: 00 01 41 88 subx\.p gr20,gr8,gr0,icc0
+ [0-9a-f ]+: 00 01 00 9c addx\.p gr16,gr28,gr0,icc0
+diff --git a/ld/testsuite/ld-frv/tls-dynamic-2.d b/ld/testsuite/ld-frv/tls-dynamic-2.d
+index 07bf332..d943e86 100644
+--- a/ld/testsuite/ld-frv/tls-dynamic-2.d
++++ b/ld/testsuite/ld-frv/tls-dynamic-2.d
+@@ -155,7 +155,7 @@ Disassembly of section \.text:
+ [0-9a-f ]+: 80 88 00 00 nop
+ Disassembly of section \.got:
+
+-[0-9a-f ]+<(__data_start|_GLOBAL_OFFSET_TABLE_-0x60)>:
++[0-9a-f ]+<.*>:
+ [0-9a-f ]+: 00 01 02 c0 .*
+ [0-9a-f ]+: 00 00 08 21 .*
+ [0-9a-f ]+: 00 01 02 c0 .*
+diff --git a/ld/testsuite/ld-frv/tls-initial-shared-2.d b/ld/testsuite/ld-frv/tls-initial-shared-2.d
+index e4ea6a1..7f73c27 100644
+--- a/ld/testsuite/ld-frv/tls-initial-shared-2.d
++++ b/ld/testsuite/ld-frv/tls-initial-shared-2.d
+@@ -149,7 +149,7 @@ Disassembly of section \.text:
+ [0-9a-f ]+: 92 c8 f0 5c ldi @\(gr15,92\),gr9
+ Disassembly of section \.got:
+
+-[0-9a-f ]+<(__data_start|_GLOBAL_OFFSET_TABLE_-0x20)>:
++[0-9a-f ]+<.*>:
+ [0-9a-f ]+: 00 00 00 00 add\.p gr0,gr0,gr0
+ [0-9a-f ]+: R_FRV_TLSDESC_VALUE \.tbss
+ [0-9a-f ]+: 00 00 10 11 add\.p sp,gr17,gr0
+diff --git a/ld/testsuite/ld-frv/tls-relax-shared-2.d b/ld/testsuite/ld-frv/tls-relax-shared-2.d
+index c07bb35..7519247 100644
+--- a/ld/testsuite/ld-frv/tls-relax-shared-2.d
++++ b/ld/testsuite/ld-frv/tls-relax-shared-2.d
+@@ -151,7 +151,7 @@ Disassembly of section \.text:
+ [0-9a-f ]+: 82 30 80 00 calll @\(gr8,gr0\)
+ Disassembly of section \.got:
+
+-[0-9a-f ]+<(__data_start|_GLOBAL_OFFSET_TABLE_-0x60)>:
++[0-9a-f ]+<.*>:
+ [0-9a-f ]+: 00 00 00 00 add\.p gr0,gr0,gr0
+ [0-9a-f ]+: R_FRV_TLSDESC_VALUE \.tbss
+ [0-9a-f ]+: 00 00 17 f3 \*unknown\*
+diff --git a/ld/testsuite/ld-frv/tls-shared-2.d b/ld/testsuite/ld-frv/tls-shared-2.d
+index bd92cdb..1e6b533 100644
+--- a/ld/testsuite/ld-frv/tls-shared-2.d
++++ b/ld/testsuite/ld-frv/tls-shared-2.d
+@@ -151,7 +151,7 @@ Disassembly of section \.text:
+ [0-9a-f ]+: 82 30 80 00 calll @\(gr8,gr0\)
+ Disassembly of section \.got:
+
+-[0-9a-f ]+<(__data_start|_GLOBAL_OFFSET_TABLE_-0x60)>:
++[0-9a-f ]+<.*>:
+ [0-9a-f ]+: 00 00 00 00 add\.p gr0,gr0,gr0
+ [0-9a-f ]+: R_FRV_TLSDESC_VALUE \.tbss
+ [0-9a-f ]+: 00 00 17 f3 \*unknown\*
+diff --git a/ld/testsuite/ld-i386/plt-nacl.pd b/ld/testsuite/ld-i386/plt-nacl.pd
+index 0f8e114..d95e888e 100644
+--- a/ld/testsuite/ld-i386/plt-nacl.pd
++++ b/ld/testsuite/ld-i386/plt-nacl.pd
+@@ -8,7 +8,7 @@
+
+ Disassembly of section .plt:
+
+-[0-9a-f]+ <fn1@plt-0x40>:
++[0-9a-f]+ <.plt>:
+ +[0-9a-f]+: ff 35 ([0-9a-f]{2} ){4} * pushl 0x[0-9a-f]+
+ +[0-9a-f]+: 8b 0d ([0-9a-f]{2} ){4} * mov 0x[0-9a-f]+,%ecx
+ +[0-9a-f]+: 83 e1 e0 and \$0xffffffe0,%ecx
+@@ -87,7 +87,7 @@ Disassembly of section .plt:
+ +[0-9a-f]+: 90 nop
+ +[0-9a-f]+: 90 nop
+ +[0-9a-f]+: 68 00 00 00 00 push \$0x0
+- +[0-9a-f]+: e9 ([0-9a-f]{2} ){4} * jmp [0-9a-f]+ <fn1@plt-0x40>
++ +[0-9a-f]+: e9 ([0-9a-f]{2} ){4} * jmp [0-9a-f]+ <.plt>
+ +[0-9a-f]+: 90 nop
+ +[0-9a-f]+: 90 nop
+ +[0-9a-f]+: 90 nop
+@@ -137,7 +137,7 @@ Disassembly of section .plt:
+ +[0-9a-f]+: 90 nop
+ +[0-9a-f]+: 90 nop
+ +[0-9a-f]+: 68 08 00 00 00 push \$0x8
+- +[0-9a-f]+: e9 ([0-9a-f]{2} ){4} * jmp [0-9a-f]+ <fn1@plt-0x40>
++ +[0-9a-f]+: e9 ([0-9a-f]{2} ){4} * jmp [0-9a-f]+ <.plt>
+ +[0-9a-f]+: 90 nop
+ +[0-9a-f]+: 90 nop
+ +[0-9a-f]+: 90 nop
+diff --git a/ld/testsuite/ld-i386/plt-pic-nacl.pd b/ld/testsuite/ld-i386/plt-pic-nacl.pd
+index 77e8a2a..03aa007 100644
+--- a/ld/testsuite/ld-i386/plt-pic-nacl.pd
++++ b/ld/testsuite/ld-i386/plt-pic-nacl.pd
+@@ -8,7 +8,7 @@
+
+ Disassembly of section .plt:
+
+-[0-9a-f]+ <fn1@plt-0x40>:
++[0-9a-f]+ <.plt>:
+ +[0-9a-f]+: ff 73 04 pushl 0x4\(%ebx\)
+ +[0-9a-f]+: 8b 4b 08 mov 0x8\(%ebx\),%ecx
+ +[0-9a-f]+: 83 e1 e0 and \$0xffffffe0,%ecx
+@@ -93,7 +93,7 @@ Disassembly of section .plt:
+ +[0-9a-f]+: 90 nop
+ +[0-9a-f]+: 90 nop
+ +[0-9a-f]+: 68 00 00 00 00 push \$0x0
+- +[0-9a-f]+: e9 ([0-9a-f]{2} ){4} * jmp [0-9a-f]+ <fn1@plt-0x40>
++ +[0-9a-f]+: e9 ([0-9a-f]{2} ){4} * jmp [0-9a-f]+ <.plt>
+ +[0-9a-f]+: 90 nop
+ +[0-9a-f]+: 90 nop
+ +[0-9a-f]+: 90 nop
+@@ -143,7 +143,7 @@ Disassembly of section .plt:
+ +[0-9a-f]+: 90 nop
+ +[0-9a-f]+: 90 nop
+ +[0-9a-f]+: 68 08 00 00 00 push \$0x8
+- +[0-9a-f]+: e9 ([0-9a-f]{2} ){4} * jmp [0-9a-f]+ <fn1@plt-0x40>
++ +[0-9a-f]+: e9 ([0-9a-f]{2} ){4} * jmp [0-9a-f]+ <.plt>
+ +[0-9a-f]+: 90 nop
+ +[0-9a-f]+: 90 nop
+ +[0-9a-f]+: 90 nop
+diff --git a/ld/testsuite/ld-i386/plt-pic.pd b/ld/testsuite/ld-i386/plt-pic.pd
+index 5fe2930..4122c46 100644
+--- a/ld/testsuite/ld-i386/plt-pic.pd
++++ b/ld/testsuite/ld-i386/plt-pic.pd
+@@ -8,7 +8,7 @@
+
+ Disassembly of section .plt:
+
+-[0-9a-f]+ <fn1@plt-0x10>:
++[0-9a-f]+ <.plt>:
+ +[0-9a-f]+: ff b3 04 00 00 00 pushl 0x4\(%ebx\)
+ +[0-9a-f]+: ff a3 08 00 00 00 jmp \*0x8\(%ebx\)
+ #...
+@@ -16,9 +16,9 @@ Disassembly of section .plt:
+ [0-9a-f]+ <fn1@plt>:
+ +[0-9a-f]+: ff a3 ([0-9a-f]{2} ){4} * jmp \*0x[0-9a-f]+\(%ebx\)
+ +[0-9a-f]+: 68 00 00 00 00 push \$0x0
+- +[0-9a-f]+: e9 ([0-9a-f]{2} ){4} * jmp [0-9a-f]+ <fn1@plt-0x10>
++ +[0-9a-f]+: e9 ([0-9a-f]{2} ){4} * jmp [0-9a-f]+ <.plt>
+
+ [0-9a-f]+ <fn2@plt>:
+ +[0-9a-f]+: ff a3 ([0-9a-f]{2} ){4} * jmp \*0x[0-9a-f]+\(%ebx\)
+ +[0-9a-f]+: 68 08 00 00 00 push \$0x8
+- +[0-9a-f]+: e9 ([0-9a-f]{2} ){4} * jmp [0-9a-f]+ <fn1@plt-0x10>
++ +[0-9a-f]+: e9 ([0-9a-f]{2} ){4} * jmp [0-9a-f]+ <.plt>
+diff --git a/ld/testsuite/ld-i386/plt.pd b/ld/testsuite/ld-i386/plt.pd
+index 1b1f57d..a6e6d35 100644
+--- a/ld/testsuite/ld-i386/plt.pd
++++ b/ld/testsuite/ld-i386/plt.pd
+@@ -8,7 +8,7 @@
+
+ Disassembly of section .plt:
+
+-[0-9a-f]+ <fn1@plt-0x10>:
++[0-9a-f]+ <.plt>:
+ +[0-9a-f]+: ff 35 ([0-9a-f]{2} ){4} * pushl 0x[0-9a-f]+
+ +[0-9a-f]+: ff 25 ([0-9a-f]{2} ){4} * jmp \*0x[0-9a-f]+
+ #...
+@@ -16,9 +16,9 @@ Disassembly of section .plt:
+ [0-9a-f]+ <fn1@plt>:
+ +[0-9a-f]+: ff 25 ([0-9a-f]{2} ){4} * jmp \*0x[0-9a-f]+
+ +[0-9a-f]+: 68 00 00 00 00 push \$0x0
+- +[0-9a-f]+: e9 ([0-9a-f]{2} ){4} * jmp [0-9a-f]+ <fn1@plt-0x10>
++ +[0-9a-f]+: e9 ([0-9a-f]{2} ){4} * jmp [0-9a-f]+ <.plt>
+
+ [0-9a-f]+ <fn2@plt>:
+ +[0-9a-f]+: ff 25 ([0-9a-f]{2} ){4} * jmp \*0x[0-9a-f]+
+ +[0-9a-f]+: 68 08 00 00 00 push \$0x8
+- +[0-9a-f]+: e9 ([0-9a-f]{2} ){4} * jmp [0-9a-f]+ <fn1@plt-0x10>
++ +[0-9a-f]+: e9 ([0-9a-f]{2} ){4} * jmp [0-9a-f]+ <.plt>
+diff --git a/ld/testsuite/ld-i386/pr19636-1d-nacl.d b/ld/testsuite/ld-i386/pr19636-1d-nacl.d
+index fef5eea..489eab6 100644
+--- a/ld/testsuite/ld-i386/pr19636-1d-nacl.d
++++ b/ld/testsuite/ld-i386/pr19636-1d-nacl.d
+@@ -121,4 +121,4 @@ Disassembly of section .text:
+ 0+80 <_start>:
+ [ ]*[a-f0-9]+: 3b 80 f8 ff ff ff cmp -0x8\(%eax\),%eax
+ [ ]*[a-f0-9]+: ff a0 fc ff ff ff jmp \*-0x4\(%eax\)
+-[ ]*[a-f0-9]+: e8 af ff ff ff call 40 <_start-0x40>
++[ ]*[a-f0-9]+: e8 af ff ff ff call 40 <.*>
+diff --git a/ld/testsuite/ld-i386/pr19636-1d.d b/ld/testsuite/ld-i386/pr19636-1d.d
+index 16e316c..ac86786 100644
+--- a/ld/testsuite/ld-i386/pr19636-1d.d
++++ b/ld/testsuite/ld-i386/pr19636-1d.d
+@@ -23,4 +23,4 @@ Disassembly of section .text:
+ 0+e0 <_start>:
+ [ ]*[a-f0-9]+: 3b 80 f8 ff ff ff cmp -0x8\(%eax\),%eax
+ [ ]*[a-f0-9]+: ff a0 fc ff ff ff jmp \*-0x4\(%eax\)
+-[ ]*[a-f0-9]+: e8 df ff ff ff call d0 <_start-0x10>
++[ ]*[a-f0-9]+: e8 df ff ff ff call d0 <.*>
+diff --git a/ld/testsuite/ld-i386/pr19636-2c-nacl.d b/ld/testsuite/ld-i386/pr19636-2c-nacl.d
+index 7543e0e..7a6cce1 100644
+--- a/ld/testsuite/ld-i386/pr19636-2c-nacl.d
++++ b/ld/testsuite/ld-i386/pr19636-2c-nacl.d
+@@ -121,6 +121,6 @@ Disassembly of section .text:
+ 0+80 <_start>:
+ [ ]*[a-f0-9]+: 3b 80 fc ff ff ff cmp -0x4\(%eax\),%eax
+ [ ]*[a-f0-9]+: ff a0 fc ff ff ff jmp \*-0x4\(%eax\)
+-[ ]*[a-f0-9]+: e8 af ff ff ff call 40 <_start-0x40>
++[ ]*[a-f0-9]+: e8 af ff ff ff call 40 <.*>
+ [ ]*[a-f0-9]+: 3d 00 00 00 00 cmp \$0x0,%eax
+-[ ]*[a-f0-9]+: e8 fc ff ff ff call 97 <_start\+0x17>
++[ ]*[a-f0-9]+: e8 fc ff ff ff call 97 <.*>
+diff --git a/ld/testsuite/ld-i386/pr19636-2c.d b/ld/testsuite/ld-i386/pr19636-2c.d
+index 98b53aa..08db119 100644
+--- a/ld/testsuite/ld-i386/pr19636-2c.d
++++ b/ld/testsuite/ld-i386/pr19636-2c.d
+@@ -23,6 +23,6 @@ Disassembly of section .text:
+ 0+150 <_start>:
+ [ ]*[a-f0-9]+: 3b 80 fc ff ff ff cmp -0x4\(%eax\),%eax
+ [ ]*[a-f0-9]+: ff a0 fc ff ff ff jmp \*-0x4\(%eax\)
+-[ ]*[a-f0-9]+: e8 df ff ff ff call 140 <_start-0x10>
++[ ]*[a-f0-9]+: e8 df ff ff ff call 140 <.*>
+ [ ]*[a-f0-9]+: 3d 00 00 00 00 cmp \$0x0,%eax
+-[ ]*[a-f0-9]+: e8 fc ff ff ff call 167 <_start\+0x17>
++[ ]*[a-f0-9]+: e8 fc ff ff ff call 167 <.*>
+diff --git a/ld/testsuite/ld-ifunc/ifunc-21-x86-64.d b/ld/testsuite/ld-ifunc/ifunc-21-x86-64.d
+index 4e3582d..fd42acc 100644
+--- a/ld/testsuite/ld-ifunc/ifunc-21-x86-64.d
++++ b/ld/testsuite/ld-ifunc/ifunc-21-x86-64.d
+@@ -9,11 +9,11 @@
+ Disassembly of section .text:
+
+ 0+4000c8 <__start>:
+- +[a-f0-9]+: ff 15 2a 00 20 00 callq \*0x20002a\(%rip\) # 6000f8 <bar\+0x200007>
+- +[a-f0-9]+: ff 25 24 00 20 00 jmpq \*0x200024\(%rip\) # 6000f8 <bar\+0x200007>
+- +[a-f0-9]+: 48 03 05 1d 00 20 00 add 0x20001d\(%rip\),%rax # 6000f8 <bar\+0x200007>
+- +[a-f0-9]+: 48 8b 05 16 00 20 00 mov 0x200016\(%rip\),%rax # 6000f8 <bar\+0x200007>
+- +[a-f0-9]+: 48 85 05 0f 00 20 00 test %rax,0x20000f\(%rip\) # 6000f8 <bar\+0x200007>
++ +[a-f0-9]+: ff 15 2a 00 20 00 callq \*0x20002a\(%rip\) # 6000f8 <.got>
++ +[a-f0-9]+: ff 25 24 00 20 00 jmpq \*0x200024\(%rip\) # 6000f8 <.got>
++ +[a-f0-9]+: 48 03 05 1d 00 20 00 add 0x20001d\(%rip\),%rax # 6000f8 <.got>
++ +[a-f0-9]+: 48 8b 05 16 00 20 00 mov 0x200016\(%rip\),%rax # 6000f8 <.got>
++ +[a-f0-9]+: 48 85 05 0f 00 20 00 test %rax,0x20000f\(%rip\) # 6000f8 <.got>
+ +[a-f0-9]+: 48 c7 c0 f1 00 40 00 mov \$0x4000f1,%rax
+
+ 0+4000f0 <foo>:
+diff --git a/ld/testsuite/ld-ifunc/ifunc-22-x86-64.d b/ld/testsuite/ld-ifunc/ifunc-22-x86-64.d
+index 4e3582d..fd42acc 100644
+--- a/ld/testsuite/ld-ifunc/ifunc-22-x86-64.d
++++ b/ld/testsuite/ld-ifunc/ifunc-22-x86-64.d
+@@ -9,11 +9,11 @@
+ Disassembly of section .text:
+
+ 0+4000c8 <__start>:
+- +[a-f0-9]+: ff 15 2a 00 20 00 callq \*0x20002a\(%rip\) # 6000f8 <bar\+0x200007>
+- +[a-f0-9]+: ff 25 24 00 20 00 jmpq \*0x200024\(%rip\) # 6000f8 <bar\+0x200007>
+- +[a-f0-9]+: 48 03 05 1d 00 20 00 add 0x20001d\(%rip\),%rax # 6000f8 <bar\+0x200007>
+- +[a-f0-9]+: 48 8b 05 16 00 20 00 mov 0x200016\(%rip\),%rax # 6000f8 <bar\+0x200007>
+- +[a-f0-9]+: 48 85 05 0f 00 20 00 test %rax,0x20000f\(%rip\) # 6000f8 <bar\+0x200007>
++ +[a-f0-9]+: ff 15 2a 00 20 00 callq \*0x20002a\(%rip\) # 6000f8 <.got>
++ +[a-f0-9]+: ff 25 24 00 20 00 jmpq \*0x200024\(%rip\) # 6000f8 <.got>
++ +[a-f0-9]+: 48 03 05 1d 00 20 00 add 0x20001d\(%rip\),%rax # 6000f8 <.got>
++ +[a-f0-9]+: 48 8b 05 16 00 20 00 mov 0x200016\(%rip\),%rax # 6000f8 <.got>
++ +[a-f0-9]+: 48 85 05 0f 00 20 00 test %rax,0x20000f\(%rip\) # 6000f8 <.got>
+ +[a-f0-9]+: 48 c7 c0 f1 00 40 00 mov \$0x4000f1,%rax
+
+ 0+4000f0 <foo>:
+diff --git a/ld/testsuite/ld-ifunc/pr17154-i386.d b/ld/testsuite/ld-ifunc/pr17154-i386.d
+index e526223..16fcd4e 100644
+--- a/ld/testsuite/ld-ifunc/pr17154-i386.d
++++ b/ld/testsuite/ld-ifunc/pr17154-i386.d
+@@ -5,7 +5,7 @@
+ #target: x86_64-*-* i?86-*-*
+
+ #...
+-0+1d0 <\*ABS\*@plt-0x10>:
++0+1d0 <.*>:
+ [ ]*[a-f0-9]+: ff b3 04 00 00 00 pushl 0x4\(%ebx\)
+ [ ]*[a-f0-9]+: ff a3 08 00 00 00 jmp \*0x8\(%ebx\)
+ [ ]*[a-f0-9]+: 00 00 add %al,\(%eax\)
+@@ -14,22 +14,22 @@
+ 0+1e0 <\*ABS\*@plt>:
+ [ ]*[a-f0-9]+: ff a3 0c 00 00 00 jmp \*0xc\(%ebx\)
+ [ ]*[a-f0-9]+: 68 18 00 00 00 push \$0x18
+-[ ]*[a-f0-9]+: e9 e0 ff ff ff jmp 1d0 <\*ABS\*@plt-0x10>
++[ ]*[a-f0-9]+: e9 e0 ff ff ff jmp 1d0 <.*>
+
+ 0+1f0 <func1@plt>:
+ [ ]*[a-f0-9]+: ff a3 10 00 00 00 jmp \*0x10\(%ebx\)
+ [ ]*[a-f0-9]+: 68 00 00 00 00 push \$0x0
+-[ ]*[a-f0-9]+: e9 d0 ff ff ff jmp 1d0 <\*ABS\*@plt-0x10>
++[ ]*[a-f0-9]+: e9 d0 ff ff ff jmp 1d0 <.*>
+
+ 0+200 <func2@plt>:
+ [ ]*[a-f0-9]+: ff a3 14 00 00 00 jmp \*0x14\(%ebx\)
+ [ ]*[a-f0-9]+: 68 08 00 00 00 push \$0x8
+-[ ]*[a-f0-9]+: e9 c0 ff ff ff jmp 1d0 <\*ABS\*@plt-0x10>
++[ ]*[a-f0-9]+: e9 c0 ff ff ff jmp 1d0 <.*>
+
+ 0+210 <\*ABS\*@plt>:
+ [ ]*[a-f0-9]+: ff a3 18 00 00 00 jmp \*0x18\(%ebx\)
+ [ ]*[a-f0-9]+: 68 10 00 00 00 push \$0x10
+-[ ]*[a-f0-9]+: e9 b0 ff ff ff jmp 1d0 <\*ABS\*@plt-0x10>
++[ ]*[a-f0-9]+: e9 b0 ff ff ff jmp 1d0 <.*>
+
+ Disassembly of section .text:
+
+diff --git a/ld/testsuite/ld-ifunc/pr17154-x86-64.d b/ld/testsuite/ld-ifunc/pr17154-x86-64.d
+index 9d2a688..1cdcf50 100644
+--- a/ld/testsuite/ld-ifunc/pr17154-x86-64.d
++++ b/ld/testsuite/ld-ifunc/pr17154-x86-64.d
+@@ -5,30 +5,30 @@
+ #target: x86_64-*-*
+
+ #...
+-0+2b0 <\*ABS\*\+0x30a@plt-0x10>:
+-[ ]*[a-f0-9]+: ff 35 5a 01 20 00 pushq 0x20015a\(%rip\) # 200410 <_GLOBAL_OFFSET_TABLE_\+0x8>
+-[ ]*[a-f0-9]+: ff 25 5c 01 20 00 jmpq \*0x20015c\(%rip\) # 200418 <_GLOBAL_OFFSET_TABLE_\+0x10>
++0+2b0 <.*>:
++[ ]*[a-f0-9]+: ff 35 5a 01 20 00 pushq 0x20015a\(%rip\) # 200410 <.*>
++[ ]*[a-f0-9]+: ff 25 5c 01 20 00 jmpq \*0x20015c\(%rip\) # 200418 <.*>
+ [ ]*[a-f0-9]+: 0f 1f 40 00 nopl 0x0\(%rax\)
+
+ 0+2c0 <\*ABS\*\+0x30a@plt>:
+-[ ]*[a-f0-9]+: ff 25 5a 01 20 00 jmpq \*0x20015a\(%rip\) # 200420 <_GLOBAL_OFFSET_TABLE_\+0x18>
++[ ]*[a-f0-9]+: ff 25 5a 01 20 00 jmpq \*0x20015a\(%rip\) # 200420 <.*>
+ [ ]*[a-f0-9]+: 68 03 00 00 00 pushq \$0x3
+-[ ]*[a-f0-9]+: e9 e0 ff ff ff jmpq 2b0 <\*ABS\*\+0x30a@plt-0x10>
++[ ]*[a-f0-9]+: e9 e0 ff ff ff jmpq 2b0 <.*>
+
+ 0+2d0 <func1@plt>:
+-[ ]*[a-f0-9]+: ff 25 52 01 20 00 jmpq \*0x200152\(%rip\) # 200428 <_GLOBAL_OFFSET_TABLE_\+0x20>
++[ ]*[a-f0-9]+: ff 25 52 01 20 00 jmpq \*0x200152\(%rip\) # 200428 <.*>
+ [ ]*[a-f0-9]+: 68 00 00 00 00 pushq \$0x0
+-[ ]*[a-f0-9]+: e9 d0 ff ff ff jmpq 2b0 <\*ABS\*\+0x30a@plt-0x10>
++[ ]*[a-f0-9]+: e9 d0 ff ff ff jmpq 2b0 <.*>
+
+ 0+2e0 <func2@plt>:
+-[ ]*[a-f0-9]+: ff 25 4a 01 20 00 jmpq \*0x20014a\(%rip\) # 200430 <_GLOBAL_OFFSET_TABLE_\+0x28>
++[ ]*[a-f0-9]+: ff 25 4a 01 20 00 jmpq \*0x20014a\(%rip\) # 200430 <.*>
+ [ ]*[a-f0-9]+: 68 01 00 00 00 pushq \$0x1
+-[ ]*[a-f0-9]+: e9 c0 ff ff ff jmpq 2b0 <\*ABS\*\+0x30a@plt-0x10>
++[ ]*[a-f0-9]+: e9 c0 ff ff ff jmpq 2b0 <.*>
+
+ 0+2f0 <\*ABS\*\+0x300@plt>:
+-[ ]*[a-f0-9]+: ff 25 42 01 20 00 jmpq \*0x200142\(%rip\) # 200438 <_GLOBAL_OFFSET_TABLE_\+0x30>
++[ ]*[a-f0-9]+: ff 25 42 01 20 00 jmpq \*0x200142\(%rip\) # 200438 <.*>
+ [ ]*[a-f0-9]+: 68 02 00 00 00 pushq \$0x2
+-[ ]*[a-f0-9]+: e9 b0 ff ff ff jmpq 2b0 <\*ABS\*\+0x30a@plt-0x10>
++[ ]*[a-f0-9]+: e9 b0 ff ff ff jmpq 2b0 <.*>
+
+ Disassembly of section .text:
+
+diff --git a/ld/testsuite/ld-m68k/plt1-68020.d b/ld/testsuite/ld-m68k/plt1-68020.d
+index 54463b9..ed3e1c1 100644
+--- a/ld/testsuite/ld-m68k/plt1-68020.d
++++ b/ld/testsuite/ld-m68k/plt1-68020.d
+@@ -3,7 +3,7 @@
+
+ Disassembly of section \.plt:
+
+-00020800 <f.@plt-0x14>:
++00020800 <.plt>:
+ 20800: 2f3b 0170 0000 movel %pc@\(30404 <_GLOBAL_OFFSET_TABLE_\+0x4>\),%sp@-
+ 20806: fc02
+ 20808: 4efb 0171 0000 jmp %pc@\(30408 <_GLOBAL_OFFSET_TABLE_\+0x8>\)@\(0*\)
+@@ -11,22 +11,22 @@ Disassembly of section \.plt:
+ 20810: 0000 0000 orib #0,%d0
+
+ 00020814 <f.@plt>:
+- 20814: 4efb 0171 0000 jmp %pc@\(3040c <_GLOBAL_OFFSET_TABLE_\+0xc>\)@\(0*\)
++ 20814: 4efb 0171 0000 jmp %pc@\(3040c <f3>\)@\(0*\)
+ 2081a: fbf6
+ 2081c: 2f3c 0000 0000 movel #0,%sp@-
+- 20822: 60ff ffff ffdc bral 20800 <f.@plt-0x14>
++ 20822: 60ff ffff ffdc bral 20800 <.plt>
+
+ 00020828 <f.@plt>:
+- 20828: 4efb 0171 0000 jmp %pc@\(30410 <_GLOBAL_OFFSET_TABLE_\+0x10>\)@\(0*\)
++ 20828: 4efb 0171 0000 jmp %pc@\(30410 <f2>\)@\(0*\)
+ 2082e: fbe6
+ 20830: 2f3c 0000 000c movel #12,%sp@-
+- 20836: 60ff ffff ffc8 bral 20800 <f.@plt-0x14>
++ 20836: 60ff ffff ffc8 bral 20800 <.plt>
+
+ 0002083c <f.@plt>:
+- 2083c: 4efb 0171 0000 jmp %pc@\(30414 <_GLOBAL_OFFSET_TABLE_\+0x14>\)@\(0*\)
++ 2083c: 4efb 0171 0000 jmp %pc@\(30414 <f1>\)@\(0*\)
+ 20842: fbd6
+ 20844: 2f3c 0000 0018 movel #24,%sp@-
+- 2084a: 60ff ffff ffb4 bral 20800 <f.@plt-0x14>
++ 2084a: 60ff ffff ffb4 bral 20800 <.plt>
+ Disassembly of section \.text:
+
+ 00020c00 <.*>:
+diff --git a/ld/testsuite/ld-m68k/plt1-cpu32.d b/ld/testsuite/ld-m68k/plt1-cpu32.d
+index a497740..e303cd1 100644
+--- a/ld/testsuite/ld-m68k/plt1-cpu32.d
++++ b/ld/testsuite/ld-m68k/plt1-cpu32.d
+@@ -3,7 +3,7 @@
+
+ Disassembly of section \.plt:
+
+-00020800 <f.@plt-0x18>:
++00020800 <.plt>:
+ 20800: 2f3b 0170 0000 movel %pc@\(30404 <_GLOBAL_OFFSET_TABLE_\+0x4>\),%sp@-
+ 20806: fc02
+ 20808: 227b 0170 0000 moveal %pc@\(30408 <_GLOBAL_OFFSET_TABLE_\+0x8>\),%a1
+@@ -13,27 +13,27 @@ Disassembly of section \.plt:
+ \.\.\.
+
+ 00020818 <f.@plt>:
+- 20818: 227b 0170 0000 moveal %pc@\(3040c <_GLOBAL_OFFSET_TABLE_\+0xc>\),%a1
++ 20818: 227b 0170 0000 moveal %pc@\(3040c <f3>\),%a1
+ 2081e: fbf2
+ 20820: 4ed1 jmp %a1@
+ 20822: 2f3c 0000 0000 movel #0,%sp@-
+- 20828: 60ff ffff ffd6 bral 20800 <f.@plt-0x18>
++ 20828: 60ff ffff ffd6 bral 20800 <.plt>
+ \.\.\.
+
+ 00020830 <f.@plt>:
+- 20830: 227b 0170 0000 moveal %pc@\(30410 <_GLOBAL_OFFSET_TABLE_\+0x10>\),%a1
++ 20830: 227b 0170 0000 moveal %pc@\(30410 <f2>\),%a1
+ 20836: fbde
+ 20838: 4ed1 jmp %a1@
+ 2083a: 2f3c 0000 000c movel #12,%sp@-
+- 20840: 60ff ffff ffbe bral 20800 <f.@plt-0x18>
++ 20840: 60ff ffff ffbe bral 20800 <.plt>
+ \.\.\.
+
+ 00020848 <f.@plt>:
+- 20848: 227b 0170 0000 moveal %pc@\(30414 <_GLOBAL_OFFSET_TABLE_\+0x14>\),%a1
++ 20848: 227b 0170 0000 moveal %pc@\(30414 <f1>\),%a1
+ 2084e: fbca
+ 20850: 4ed1 jmp %a1@
+ 20852: 2f3c 0000 0018 movel #24,%sp@-
+- 20858: 60ff ffff ffa6 bral 20800 <f.@plt-0x18>
++ 20858: 60ff ffff ffa6 bral 20800 <.plt>
+ \.\.\.
+ Disassembly of section \.text:
+
+diff --git a/ld/testsuite/ld-m68k/plt1-isab.d b/ld/testsuite/ld-m68k/plt1-isab.d
+index a9aeacb..00e88b7 100644
+--- a/ld/testsuite/ld-m68k/plt1-isab.d
++++ b/ld/testsuite/ld-m68k/plt1-isab.d
+@@ -3,23 +3,23 @@
+
+ Disassembly of section \.plt:
+
+-00020800 <f.@plt-0x18>:
++00020800 <.plt>:
+ # _GLOBAL_OFFSET_TABLE_ + 4 == 0x30404 == 0x20802 + 0xfc02
+ 20800: 203c 0000 fc02 movel #64514,%d0
+- 20806: 2f3b 08fa movel %pc@\(20802 <f.@plt-0x16>,%d0:l\),%sp@-
++ 20806: 2f3b 08fa movel %pc@\(20802 <.*>,%d0:l\),%sp@-
+ # _GLOBAL_OFFSET_TABLE_ + 8 == 0x30408 == 0x2080c + 0xfbfc
+ 2080a: 203c 0000 fbfc movel #64508,%d0
+- 20810: 207b 08fa moveal %pc@\(2080c <f.@plt-0xc>,%d0:l\),%a0
++ 20810: 207b 08fa moveal %pc@\(2080c <.*>,%d0:l\),%a0
+ 20814: 4ed0 jmp %a0@
+ 20816: 4e71 nop
+
+ 00020818 <f.@plt>:
+ # _GLOBAL_OFFSET_TABLE_ + 12 == 0x3040c == 0x2081a + 0xfbf2
+ 20818: 203c 0000 fbf2 movel #64498,%d0
+- 2081e: 207b 08fa moveal %pc@\(2081a <f.@plt\+0x2>,%d0:l\),%a0
++ 2081e: 207b 08fa moveal %pc@\(2081a <.*>,%d0:l\),%a0
+ 20822: 4ed0 jmp %a0@
+ 20824: 2f3c 0000 0000 movel #0,%sp@-
+- 2082a: 60ff ffff ffd4 bral 20800 <f.@plt-0x18>
++ 2082a: 60ff ffff ffd4 bral 20800 <.plt>
+
+ 00020830 <f.@plt>:
+ # _GLOBAL_OFFSET_TABLE_ + 16 == 0x30410 == 0x20832 + 0xfbde
+@@ -27,7 +27,7 @@ Disassembly of section \.plt:
+ 20836: 207b 08fa moveal %pc@\(20832 <f.@plt\+0x2>,%d0:l\),%a0
+ 2083a: 4ed0 jmp %a0@
+ 2083c: 2f3c 0000 000c movel #12,%sp@-
+- 20842: 60ff ffff ffbc bral 20800 <f.@plt-0x18>
++ 20842: 60ff ffff ffbc bral 20800 <.*>
+
+ 00020848 <f.@plt>:
+ # _GLOBAL_OFFSET_TABLE_ + 20 == 0x30414 == 0x2084a + 0xfbca
+@@ -35,7 +35,7 @@ Disassembly of section \.plt:
+ 2084e: 207b 08fa moveal %pc@\(2084a <f.@plt\+0x2>,%d0:l\),%a0
+ 20852: 4ed0 jmp %a0@
+ 20854: 2f3c 0000 0018 movel #24,%sp@-
+- 2085a: 60ff ffff ffa4 bral 20800 <f.@plt-0x18>
++ 2085a: 60ff ffff ffa4 bral 20800 <.*>
+ Disassembly of section \.text:
+
+ 00020c00 <.*>:
+diff --git a/ld/testsuite/ld-m68k/plt1-isac.d b/ld/testsuite/ld-m68k/plt1-isac.d
+index ae299ce..d3d775e 100644
+--- a/ld/testsuite/ld-m68k/plt1-isac.d
++++ b/ld/testsuite/ld-m68k/plt1-isac.d
+@@ -3,13 +3,13 @@
+
+ Disassembly of section \.plt:
+
+-00020800 <f.@plt-0x18>:
++00020800 <.plt>:
+ # _GLOBAL_OFFSET_TABLE_ + 4 == 0x30404 == 0x20802 + 0xfc02
+ 20800: 203c 0000 fc02 movel #64514,%d0
+- 20806: 2ebb 08fa movel %pc@\(20802 <f.@plt-0x16>,%d0:l\),%sp@
++ 20806: 2ebb 08fa movel %pc@\(20802 <.*>,%d0:l\),%sp@
+ # _GLOBAL_OFFSET_TABLE_ + 8 == 0x30408 == 0x2080c + 0xfbfc
+ 2080a: 203c 0000 fbfc movel #64508,%d0
+- 20810: 207b 08fa moveal %pc@\(2080c <f.@plt-0xc>,%d0:l\),%a0
++ 20810: 207b 08fa moveal %pc@\(2080c <.*>,%d0:l\),%a0
+ 20814: 4ed0 jmp %a0@
+ 20816: 4e71 nop
+
+@@ -19,7 +19,7 @@ Disassembly of section \.plt:
+ 2081e: 207b 08fa moveal %pc@\(2081a <f.@plt\+0x2>,%d0:l\),%a0
+ 20822: 4ed0 jmp %a0@
+ 20824: 2f3c 0000 0000 movel #0,%sp@-
+- 2082a: 61ff ffff ffd4 bsrl 20800 <f.@plt-0x18>
++ 2082a: 61ff ffff ffd4 bsrl 20800 <.plt>
+
+ 00020830 <f.@plt>:
+ # _GLOBAL_OFFSET_TABLE_ + 16 == 0x30410 == 0x20832 + 0xfbde
+@@ -27,7 +27,7 @@ Disassembly of section \.plt:
+ 20836: 207b 08fa moveal %pc@\(20832 <f.@plt\+0x2>,%d0:l\),%a0
+ 2083a: 4ed0 jmp %a0@
+ 2083c: 2f3c 0000 000c movel #12,%sp@-
+- 20842: 61ff ffff ffbc bsrl 20800 <f.@plt-0x18>
++ 20842: 61ff ffff ffbc bsrl 20800 <.plt>
+
+ 00020848 <f.@plt>:
+ # _GLOBAL_OFFSET_TABLE_ + 20 == 0x30414 == 0x2084a + 0xfbca
+@@ -35,7 +35,7 @@ Disassembly of section \.plt:
+ 2084e: 207b 08fa moveal %pc@\(2084a <f.@plt\+0x2>,%d0:l\),%a0
+ 20852: 4ed0 jmp %a0@
+ 20854: 2f3c 0000 0018 movel #24,%sp@-
+- 2085a: 61ff ffff ffa4 bsrl 20800 <f.@plt-0x18>
++ 2085a: 61ff ffff ffa4 bsrl 20800 <.plt>
+ Disassembly of section \.text:
+
+ 00020c00 <.*>:
+diff --git a/ld/testsuite/ld-metag/shared.d b/ld/testsuite/ld-metag/shared.d
+index 7662dbc..94e48c0 100644
+--- a/ld/testsuite/ld-metag/shared.d
++++ b/ld/testsuite/ld-metag/shared.d
+@@ -17,7 +17,7 @@ Disassembly of section .plt:
+ .*: 82120780 ADD A0.2,A0.2,#0x40f0
+ .*: c600806a GETD PC,\[A0.2\]
+ .*: 03000004 MOV D1Re0,#0
+- .*: a0fffee0 B 184 <app_func2@plt-0x14>
++ .*: a0fffee0 B 184 <.*>
+ Disassembly of section .text:
+
+ .* <lib_func1>:
+diff --git a/ld/testsuite/ld-metag/stub_pic_app.d b/ld/testsuite/ld-metag/stub_pic_app.d
+index 7a763b9..a6cf3d4 100644
+--- a/ld/testsuite/ld-metag/stub_pic_app.d
++++ b/ld/testsuite/ld-metag/stub_pic_app.d
+@@ -16,7 +16,7 @@ Disassembly of section .plt:
+ .*: 821496e0 ADD A0.2,A0.2,#0x92dc
+ .*: c600806a GETD PC,\[A0.2\]
+ .*: 03000004 MOV D1Re0,#0
+-.*: a0fffee0 B .* <_lib_func@plt-0x14>
++.*: a0fffee0 B .* <.*>
+ Disassembly of section .text:
+ .* <__start-0x10>:
+ .*: 82188105 MOVT A0.3,#0x1020
+diff --git a/ld/testsuite/ld-metag/stub_pic_shared.d b/ld/testsuite/ld-metag/stub_pic_shared.d
+index 41129c3..c422b09 100644
+--- a/ld/testsuite/ld-metag/stub_pic_shared.d
++++ b/ld/testsuite/ld-metag/stub_pic_shared.d
+@@ -16,7 +16,7 @@ Disassembly of section .plt:
+ .*: 82120580 ADD A0.2,A0.2,#0x40b0
+ .*: c600806a GETD PC,\[A0.2\]
+ .*: 03000004 MOV D1Re0,#0
+- .*: a0fffee0 B .* <_far2@plt-0x14>
++ .*: a0fffee0 B .* <.*>
+ Disassembly of section .text:
+ .* <__start-0xc>:
+ .*: 82980101 ADDT A0.3,CPC0,#0x20
+diff --git a/ld/testsuite/ld-metag/stub_shared.d b/ld/testsuite/ld-metag/stub_shared.d
+index e937f1e..dbcd4b9 100644
+--- a/ld/testsuite/ld-metag/stub_shared.d
++++ b/ld/testsuite/ld-metag/stub_shared.d
+@@ -17,7 +17,7 @@ Disassembly of section .plt:
+ .*: 82120620 ADD A0.2,A0.2,#0x40c4
+ .*: c600806a GETD PC,\[A0.2\]
+ .*: 03000004 MOV D1Re0,#0
+- .*: a0fffee0 B .* <_far2@plt-0x14>
++ .*: a0fffee0 B .* <.*>
+ Disassembly of section .text:
+
+ .* <_lib_func>:
+diff --git a/ld/testsuite/ld-s390/tlsbin_64.dd b/ld/testsuite/ld-s390/tlsbin_64.dd
+index eac7f41..fe11a23 100644
+--- a/ld/testsuite/ld-s390/tlsbin_64.dd
++++ b/ld/testsuite/ld-s390/tlsbin_64.dd
+@@ -129,7 +129,7 @@ Disassembly of section .text:
+ +[0-9a-f]+: eb 43 00 00 00 0d sllg %r4,%r3,0
+ +[0-9a-f]+: 41 54 90 00 la %r5,0\(%r4,%r9\)
+ # IE against global var with larl got access
+- +[0-9a-f]+: c0 30 [0-9a-f ]+ larl %r3,[0-9a-f]+ <_GLOBAL_OFFSET_TABLE_\+0x28>
++ +[0-9a-f]+: c0 30 [0-9a-f ]+ larl %r3,[0-9a-f]+ <.*>
+ +[0-9a-f]+: e3 33 c0 00 00 04 lg %r3,0\(%r3,%r12\)
+ +[0-9a-f]+: 41 33 90 00 la %r3,0\(%r3,%r9\)
+ # IE against global var defined in exec with larl got access
+diff --git a/ld/testsuite/ld-s390/tlspic_64.dd b/ld/testsuite/ld-s390/tlspic_64.dd
+index 274cd16..86fdbbd 100644
+--- a/ld/testsuite/ld-s390/tlspic_64.dd
++++ b/ld/testsuite/ld-s390/tlspic_64.dd
+@@ -160,7 +160,7 @@ Disassembly of section .text:
+ +[0-9a-f]+: e3 43 c0 00 00 04 lg %r4,0\(%r3,%r12\)
+ +[0-9a-f]+: 41 54 90 00 la %r5,0\(%r4,%r9\)
+ # IE against global var with larl got access
+- +[0-9a-f]+: c0 30 [0-9a-f ]+ larl %r3,[0-9a-f]+ <\_GLOBAL\_OFFSET\_TABLE\_\+0x68>
++ +[0-9a-f]+: c0 30 [0-9a-f ]+ larl %r3,[0-9a-f]+ <.*>
+ +[0-9a-f]+: e3 33 c0 00 00 04 lg %r3,0\(%r3,%r12\)
+ +[0-9a-f]+: 41 33 90 00 la %r3,0\(%r3,%r9\)
+ # IE against local var with larl got access
+diff --git a/ld/testsuite/ld-tic6x/shlib-1.dd b/ld/testsuite/ld-tic6x/shlib-1.dd
+index d33887e..a00c136 100644
+--- a/ld/testsuite/ld-tic6x/shlib-1.dd
++++ b/ld/testsuite/ld-tic6x/shlib-1.dd
+@@ -4,7 +4,7 @@ tmpdir/libtest\.so: file format elf32-tic6x-le
+
+ Disassembly of section \.plt:
+
+-10000020 <sub0@plt-0x18>:
++10000020 <.plt>:
+ 10000020:[ \t]*0100036e[ \t]*ldw \.D2T2 \*\+b14\(12\),b2
+ 10000024:[ \t]*0080046e[ \t]*ldw \.D2T2 \*\+b14\(16\),b1
+ 10000028:[ \t]*00004000[ \t]*nop 3
+diff --git a/ld/testsuite/ld-tic6x/shlib-1b.dd b/ld/testsuite/ld-tic6x/shlib-1b.dd
+index 658da73..fa597d6 100644
+--- a/ld/testsuite/ld-tic6x/shlib-1b.dd
++++ b/ld/testsuite/ld-tic6x/shlib-1b.dd
+@@ -4,7 +4,7 @@ tmpdir/libtestb\.so: file format elf32-tic6x-be
+
+ Disassembly of section \.plt:
+
+-10000020 <sub0@plt-0x18>:
++10000020 <.plt>:
+ 10000020:[ \t]*0100036e[ \t]*ldw \.D2T2 \*\+b14\(12\),b2
+ 10000024:[ \t]*0080046e[ \t]*ldw \.D2T2 \*\+b14\(16\),b1
+ 10000028:[ \t]*00004000[ \t]*nop 3
+diff --git a/ld/testsuite/ld-tic6x/shlib-1rb.dd b/ld/testsuite/ld-tic6x/shlib-1rb.dd
+index ee1a607..6b3a2c2 100644
+--- a/ld/testsuite/ld-tic6x/shlib-1rb.dd
++++ b/ld/testsuite/ld-tic6x/shlib-1rb.dd
+@@ -4,7 +4,7 @@ tmpdir/libtestrb\.so: file format elf32-tic6x-be
+
+ Disassembly of section \.plt:
+
+-10000020 <sub0@plt-0x18>:
++10000020 <.plt>:
+ 10000020:[ \t]*0100036e[ \t]*ldw \.D2T2 \*\+b14\(12\),b2
+ 10000024:[ \t]*0080046e[ \t]*ldw \.D2T2 \*\+b14\(16\),b1
+ 10000028:[ \t]*00004000[ \t]*nop 3
+diff --git a/ld/testsuite/ld-tic6x/shlib-app-1.dd b/ld/testsuite/ld-tic6x/shlib-app-1.dd
+index 411d47f..9e437bb 100644
+--- a/ld/testsuite/ld-tic6x/shlib-app-1.dd
++++ b/ld/testsuite/ld-tic6x/shlib-app-1.dd
+@@ -4,7 +4,7 @@ tmpdir/shlib-dynapp-1: file format elf32-tic6x-le
+
+ Disassembly of section \.plt:
+
+-10000020 <sub0@plt-0x18>:
++10000020 <.plt>:
+ 10000020:[ \t]*0100036e[ \t]*ldw \.D2T2 \*\+b14\(12\),b2
+ 10000024:[ \t]*0080046e[ \t]*ldw \.D2T2 \*\+b14\(16\),b1
+ 10000028:[ \t]*00004000[ \t]*nop 3
+diff --git a/ld/testsuite/ld-tic6x/shlib-app-1b.dd b/ld/testsuite/ld-tic6x/shlib-app-1b.dd
+index 5312ff8..b7cb86b 100644
+--- a/ld/testsuite/ld-tic6x/shlib-app-1b.dd
++++ b/ld/testsuite/ld-tic6x/shlib-app-1b.dd
+@@ -4,7 +4,7 @@ tmpdir/shlib-dynapp-1b: file format elf32-tic6x-be
+
+ Disassembly of section \.plt:
+
+-10000020 <sub0@plt-0x18>:
++10000020 <.plt>:
+ 10000020:[ \t]*0100036e[ \t]*ldw \.D2T2 \*\+b14\(12\),b2
+ 10000024:[ \t]*0080046e[ \t]*ldw \.D2T2 \*\+b14\(16\),b1
+ 10000028:[ \t]*00004000[ \t]*nop 3
+diff --git a/ld/testsuite/ld-tic6x/shlib-app-1r.dd b/ld/testsuite/ld-tic6x/shlib-app-1r.dd
+index 3e68bf2..6d7cd09 100644
+--- a/ld/testsuite/ld-tic6x/shlib-app-1r.dd
++++ b/ld/testsuite/ld-tic6x/shlib-app-1r.dd
+@@ -4,7 +4,7 @@ tmpdir/shlib-dynapp-1r: file format elf32-tic6x-le
+
+ Disassembly of section \.plt:
+
+-10000020 <sub0@plt-0x18>:
++10000020 <.plt>:
+ 10000020:[ \t]*0100036e[ \t]*ldw \.D2T2 \*\+b14\(12\),b2
+ 10000024:[ \t]*0080046e[ \t]*ldw \.D2T2 \*\+b14\(16\),b1
+ 10000028:[ \t]*00004000[ \t]*nop 3
+diff --git a/ld/testsuite/ld-tic6x/shlib-app-1rb.dd b/ld/testsuite/ld-tic6x/shlib-app-1rb.dd
+index ad1f28e..57809ab 100644
+--- a/ld/testsuite/ld-tic6x/shlib-app-1rb.dd
++++ b/ld/testsuite/ld-tic6x/shlib-app-1rb.dd
+@@ -4,7 +4,7 @@ tmpdir/shlib-dynapp-1rb: file format elf32-tic6x-be
+
+ Disassembly of section \.plt:
+
+-10000020 <sub0@plt-0x18>:
++10000020 <.plt>:
+ 10000020:[ \t]*0100036e[ \t]*ldw \.D2T2 \*\+b14\(12\),b2
+ 10000024:[ \t]*0080046e[ \t]*ldw \.D2T2 \*\+b14\(16\),b1
+ 10000028:[ \t]*00004000[ \t]*nop 3
+diff --git a/ld/testsuite/ld-tic6x/shlib-noindex.dd b/ld/testsuite/ld-tic6x/shlib-noindex.dd
+index bfdf499..fd37bac 100644
+--- a/ld/testsuite/ld-tic6x/shlib-noindex.dd
++++ b/ld/testsuite/ld-tic6x/shlib-noindex.dd
+@@ -4,7 +4,7 @@ tmpdir/libtestn\.so: file format elf32-tic6x-le
+
+ Disassembly of section \.plt:
+
+-10000020 <sub0@plt-0x18>:
++10000020 <.plt>:
+ 10000020: 0100036e ldw \.D2T2 \*\+b14\(12\),b2
+ 10000024: 0080046e ldw \.D2T2 \*\+b14\(16\),b1
+ 10000028: 00004000 nop 3
+diff --git a/ld/testsuite/ld-vax-elf/export-class-data.dd b/ld/testsuite/ld-vax-elf/export-class-data.dd
+index c2be30c..7d152c8 100644
+--- a/ld/testsuite/ld-vax-elf/export-class-data.dd
++++ b/ld/testsuite/ld-vax-elf/export-class-data.dd
+@@ -5,7 +5,7 @@ Disassembly of section \.text:
+
+ 12340000 <foo>:
+ 12340000: 00 00 \.word 0x0000 # Entry mask: < >
+-12340002: 9e ff 2c 00 movab \*12340034 <_GLOBAL_OFFSET_TABLE_\+0x10>,r0
++12340002: 9e ff 2c 00 movab \*12340034 <.*>,r0
+ 12340006: 00 00 50
+ 12340009: 9e ef 0c 00 movab 1234001b <hidden_foo>,r0
+ 1234000d: 00 00 50
+diff --git a/ld/testsuite/ld-vax-elf/plt-local-lib.dd b/ld/testsuite/ld-vax-elf/plt-local-lib.dd
+index 95e8176..3c1268c 100644
+--- a/ld/testsuite/ld-vax-elf/plt-local-lib.dd
++++ b/ld/testsuite/ld-vax-elf/plt-local-lib.dd
+@@ -2,7 +2,7 @@
+
+ Disassembly of section \.plt:
+
+-00001000 <foo_local@plt-0xc>:
++00001000 <.plt>:
+ 1000: dd ef 76 20 pushl 307c <_GLOBAL_OFFSET_TABLE_\+0x4>
+ 1004: 00 00
+ 1006: 17 ff 74 20 jmp \*3080 <_GLOBAL_OFFSET_TABLE_\+0x8>
+@@ -10,25 +10,25 @@ Disassembly of section \.plt:
+
+ 0000100c <foo_local@plt>:
+ 100c: fc 0f \.word 0x0ffc # Entry mask: < r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 >
+- 100e: 16 ef ec ff jsb 1000 <foo_local@plt-0xc>
++ 100e: 16 ef ec ff jsb 1000 <.plt>
+ 1012: ff ff
+ 1014: 00 00 00 00 \.long 0x00000000
+
+ 00001018 <foo_extern@plt>:
+ 1018: fc 0f \.word 0x0ffc # Entry mask: < r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 >
+- 101a: 16 ef e0 ff jsb 1000 <foo_local@plt-0xc>
++ 101a: 16 ef e0 ff jsb 1000 <.plt>
+ 101e: ff ff
+ 1020: 0c 00 00 00 \.long 0x0000000c
+
+ 00001024 <foo_rehidden@plt>:
+ 1024: fc 0f \.word 0x0ffc # Entry mask: < r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 >
+- 1026: 16 ef d4 ff jsb 1000 <foo_local@plt-0xc>
++ 1026: 16 ef d4 ff jsb 1000 <.plt>
+ 102a: ff ff
+ 102c: 18 00 00 00 \.long 0x00000018
+
+ 00001030 <foo_global@plt>:
+ 1030: fc 0f \.word 0x0ffc # Entry mask: < r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 >
+- 1032: 16 ef c8 ff jsb 1000 <foo_local@plt-0xc>
++ 1032: 16 ef c8 ff jsb 1000 <.plt>
+ 1036: ff ff
+ 1038: 24 00 00 00 \.long 0x00000024
+
+@@ -36,56 +36,56 @@ Disassembly of section \.text:
+
+ 00002000 <foo_extern>:
+ 2000: 00 00 \.word 0x0000 # Entry mask: < >
+- 2002: fb 00 ff 7f calls \$0x0,\*3088 <_GLOBAL_OFFSET_TABLE_\+0x10>
++ 2002: fb 00 ff 7f calls \$0x0,\*3088 <.*>
+ 2006: 10 00 00
+- 2009: fb 00 ff 80 calls \$0x0,\*3090 <_GLOBAL_OFFSET_TABLE_\+0x18>
++ 2009: fb 00 ff 80 calls \$0x0,\*3090 <.*>
+ 200d: 10 00 00
+- 2010: fb 00 ff 6d calls \$0x0,\*3084 <_GLOBAL_OFFSET_TABLE_\+0xc>
++ 2010: fb 00 ff 6d calls \$0x0,\*3084 <.*>
+ 2014: 10 00 00
+ 2017: fb 00 ef 2e calls \$0x0,204c <foo_hidden>
+ 201b: 00 00 00
+- 201e: fb 00 ff 67 calls \$0x0,\*308c <_GLOBAL_OFFSET_TABLE_\+0x14>
++ 201e: fb 00 ff 67 calls \$0x0,\*308c <.*>
+ 2022: 10 00 00
+ 2025: 04 ret
+
+ 00002026 <foo_local>:
+ 2026: 00 00 \.word 0x0000 # Entry mask: < >
+- 2028: fb 00 ff 59 calls \$0x0,\*3088 <_GLOBAL_OFFSET_TABLE_\+0x10>
++ 2028: fb 00 ff 59 calls \$0x0,\*3088 <.*>
+ 202c: 10 00 00
+- 202f: fb 00 ff 5a calls \$0x0,\*3090 <_GLOBAL_OFFSET_TABLE_\+0x18>
++ 202f: fb 00 ff 5a calls \$0x0,\*3090 <.*>
+ 2033: 10 00 00
+- 2036: fb 00 ff 47 calls \$0x0,\*3084 <_GLOBAL_OFFSET_TABLE_\+0xc>
++ 2036: fb 00 ff 47 calls \$0x0,\*3084 <.*>
+ 203a: 10 00 00
+ 203d: fb 00 ef 08 calls \$0x0,204c <foo_hidden>
+ 2041: 00 00 00
+- 2044: fb 00 ff 41 calls \$0x0,\*308c <_GLOBAL_OFFSET_TABLE_\+0x14>
++ 2044: fb 00 ff 41 calls \$0x0,\*308c <.*>
+ 2048: 10 00 00
+ 204b: 04 ret
+
+ 0000204c <foo_hidden>:
+ 204c: 00 00 \.word 0x0000 # Entry mask: < >
+- 204e: fb 00 ff 33 calls \$0x0,\*3088 <_GLOBAL_OFFSET_TABLE_\+0x10>
++ 204e: fb 00 ff 33 calls \$0x0,\*3088 <.*>
+ 2052: 10 00 00
+- 2055: fb 00 ff 34 calls \$0x0,\*3090 <_GLOBAL_OFFSET_TABLE_\+0x18>
++ 2055: fb 00 ff 34 calls \$0x0,\*3090 <.*>
+ 2059: 10 00 00
+- 205c: fb 00 ff 21 calls \$0x0,\*3084 <_GLOBAL_OFFSET_TABLE_\+0xc>
++ 205c: fb 00 ff 21 calls \$0x0,\*3084 <.*>
+ 2060: 10 00 00
+ 2063: fb 00 ef e2 calls \$0x0,204c <foo_hidden>
+ 2067: ff ff ff
+- 206a: fb 00 ff 1b calls \$0x0,\*308c <_GLOBAL_OFFSET_TABLE_\+0x14>
++ 206a: fb 00 ff 1b calls \$0x0,\*308c <.*>
+ 206e: 10 00 00
+ 2071: 04 ret
+
+ 00002072 <foo_rehidden>:
+ 2072: 00 00 \.word 0x0000 # Entry mask: < >
+- 2074: fb 00 ff 0d calls \$0x0,\*3088 <_GLOBAL_OFFSET_TABLE_\+0x10>
++ 2074: fb 00 ff 0d calls \$0x0,\*3088 <.*>
+ 2078: 10 00 00
+- 207b: fb 00 ff 0e calls \$0x0,\*3090 <_GLOBAL_OFFSET_TABLE_\+0x18>
++ 207b: fb 00 ff 0e calls \$0x0,\*3090 <.*>
+ 207f: 10 00 00
+- 2082: fb 00 ff fb calls \$0x0,\*3084 <_GLOBAL_OFFSET_TABLE_\+0xc>
++ 2082: fb 00 ff fb calls \$0x0,\*3084 <.*>
+ 2086: 0f 00 00
+ 2089: fb 00 ef bc calls \$0x0,204c <foo_hidden>
+ 208d: ff ff ff
+- 2090: fb 00 ff f5 calls \$0x0,\*308c <_GLOBAL_OFFSET_TABLE_\+0x14>
++ 2090: fb 00 ff f5 calls \$0x0,\*308c <.*>
+ 2094: 0f 00 00
+ 2097: 04 ret
+diff --git a/ld/testsuite/ld-vax-elf/plt-local.dd b/ld/testsuite/ld-vax-elf/plt-local.dd
+index 84eca55..94fbadd 100644
+--- a/ld/testsuite/ld-vax-elf/plt-local.dd
++++ b/ld/testsuite/ld-vax-elf/plt-local.dd
+@@ -2,7 +2,7 @@
+
+ Disassembly of section \.plt:
+
+-00001000 <foo_extern@plt-0xc>:
++00001000 <.plt>:
+ 1000: dd ef 86 20 pushl 308c <_GLOBAL_OFFSET_TABLE_\+0x4>
+ 1004: 00 00
+ 1006: 17 ff 84 20 jmp \*3090 <_GLOBAL_OFFSET_TABLE_\+0x8>
+@@ -10,7 +10,7 @@ Disassembly of section \.plt:
+
+ 0000100c <foo_extern@plt>:
+ 100c: fc 0f \.word 0x0ffc # Entry mask: < r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 >
+- 100e: 16 ef ec ff jsb 1000 <foo_extern@plt-0xc>
++ 100e: 16 ef ec ff jsb 1000 <.plt>
+ 1012: ff ff
+ 1014: 00 00 00 00 \.long 0x00000000
+
+@@ -18,7 +18,7 @@ Disassembly of section \.text:
+
+ 00002000 <foo_hidden>:
+ 2000: 00 00 \.word 0x0000 # Entry mask: < >
+- 2002: fb 00 ff 8b calls \$0x0,\*3094 <_GLOBAL_OFFSET_TABLE_\+0xc>
++ 2002: fb 00 ff 8b calls \$0x0,\*3094 <foo_extern>
+ 2006: 10 00 00
+ 2009: fb 00 ef 3c calls \$0x0,204c <foo_global>
+ 200d: 00 00 00
+@@ -32,7 +32,7 @@ Disassembly of section \.text:
+
+ 00002026 <foo_rehidden>:
+ 2026: 00 00 \.word 0x0000 # Entry mask: < >
+- 2028: fb 00 ff 65 calls \$0x0,\*3094 <_GLOBAL_OFFSET_TABLE_\+0xc>
++ 2028: fb 00 ff 65 calls \$0x0,\*3094 <foo_extern>
+ 202c: 10 00 00
+ 202f: fb 00 ef 16 calls \$0x0,204c <foo_global>
+ 2033: 00 00 00
+@@ -46,7 +46,7 @@ Disassembly of section \.text:
+
+ 0000204c <foo_global>:
+ 204c: 00 00 \.word 0x0000 # Entry mask: < >
+- 204e: fb 00 ff 3f calls \$0x0,\*3094 <_GLOBAL_OFFSET_TABLE_\+0xc>
++ 204e: fb 00 ff 3f calls \$0x0,\*3094 <foo_extern>
+ 2052: 10 00 00
+ 2055: fb 00 ef f0 calls \$0x0,204c <foo_global>
+ 2059: ff ff ff
+@@ -60,7 +60,7 @@ Disassembly of section \.text:
+
+ 00002072 <foo_local>:
+ 2072: 00 00 \.word 0x0000 # Entry mask: < >
+- 2074: fb 00 ff 19 calls \$0x0,\*3094 <_GLOBAL_OFFSET_TABLE_\+0xc>
++ 2074: fb 00 ff 19 calls \$0x0,\*3094 <foo_extern>
+ 2078: 10 00 00
+ 207b: fb 00 ef ca calls \$0x0,204c <foo_global>
+ 207f: ff ff ff
+diff --git a/ld/testsuite/ld-x86-64/bnd-ifunc-2.d b/ld/testsuite/ld-x86-64/bnd-ifunc-2.d
+index 61750c9..306a17d 100644
+--- a/ld/testsuite/ld-x86-64/bnd-ifunc-2.d
++++ b/ld/testsuite/ld-x86-64/bnd-ifunc-2.d
+@@ -8,16 +8,16 @@
+ [ ]*[a-f0-9]+: f2 ff 25 7b 01 20 00 bnd jmpq \*0x20017b\(%rip\) # 200438 <_GLOBAL_OFFSET_TABLE_\+0x10>
+ [ ]*[a-f0-9]+: 0f 1f 00 nopl \(%rax\)
+ [ ]*[a-f0-9]+: 68 03 00 00 00 pushq \$0x3
+-[ ]*[a-f0-9]+: f2 e9 e5 ff ff ff bnd jmpq 2b0 <\*ABS\*\+0x32c@plt-0x50>
++[ ]*[a-f0-9]+: f2 e9 e5 ff ff ff bnd jmpq 2b0 <.*>
+ [ ]*[a-f0-9]+: 0f 1f 44 00 00 nopl 0x0\(%rax,%rax,1\)
+ [ ]*[a-f0-9]+: 68 00 00 00 00 pushq \$0x0
+-[ ]*[a-f0-9]+: f2 e9 d5 ff ff ff bnd jmpq 2b0 <\*ABS\*\+0x32c@plt-0x50>
++[ ]*[a-f0-9]+: f2 e9 d5 ff ff ff bnd jmpq 2b0 <.*>
+ [ ]*[a-f0-9]+: 0f 1f 44 00 00 nopl 0x0\(%rax,%rax,1\)
+ [ ]*[a-f0-9]+: 68 01 00 00 00 pushq \$0x1
+-[ ]*[a-f0-9]+: f2 e9 c5 ff ff ff bnd jmpq 2b0 <\*ABS\*\+0x32c@plt-0x50>
++[ ]*[a-f0-9]+: f2 e9 c5 ff ff ff bnd jmpq 2b0 <.*>
+ [ ]*[a-f0-9]+: 0f 1f 44 00 00 nopl 0x0\(%rax,%rax,1\)
+ [ ]*[a-f0-9]+: 68 02 00 00 00 pushq \$0x2
+-[ ]*[a-f0-9]+: f2 e9 b5 ff ff ff bnd jmpq 2b0 <\*ABS\*\+0x32c@plt-0x50>
++[ ]*[a-f0-9]+: f2 e9 b5 ff ff ff bnd jmpq 2b0 <.*>
+ [ ]*[a-f0-9]+: 0f 1f 44 00 00 nopl 0x0\(%rax,%rax,1\)
+
+ Disassembly of section .plt.bnd:
+@@ -27,11 +27,11 @@ Disassembly of section .plt.bnd:
+ [ ]*[a-f0-9]+: 90 nop
+
+ 0+308 <func1@plt>:
+-[ ]*[a-f0-9]+: f2 ff 25 39 01 20 00 bnd jmpq \*0x200139\(%rip\) # 200448 <_GLOBAL_OFFSET_TABLE_\+0x20>
++[ ]*[a-f0-9]+: f2 ff 25 39 01 20 00 bnd jmpq \*0x200139\(%rip\) # 200448 <func1>
+ [ ]*[a-f0-9]+: 90 nop
+
+ 0+310 <func2@plt>:
+-[ ]*[a-f0-9]+: f2 ff 25 39 01 20 00 bnd jmpq \*0x200139\(%rip\) # 200450 <_GLOBAL_OFFSET_TABLE_\+0x28>
++[ ]*[a-f0-9]+: f2 ff 25 39 01 20 00 bnd jmpq \*0x200139\(%rip\) # 200450 <func2>
+ [ ]*[a-f0-9]+: 90 nop
+
+ 0+318 <\*ABS\*\+0x320@plt>:
+diff --git a/ld/testsuite/ld-x86-64/bnd-plt-1.d b/ld/testsuite/ld-x86-64/bnd-plt-1.d
+index 1c1f2d3..6bd50b2 100644
+--- a/ld/testsuite/ld-x86-64/bnd-plt-1.d
++++ b/ld/testsuite/ld-x86-64/bnd-plt-1.d
+@@ -13,34 +13,34 @@ Disassembly of section .plt:
+ [ ]*[a-f0-9]+: f2 ff 25 83 01 20 00 bnd jmpq \*0x200183\(%rip\) # 200420 <_GLOBAL_OFFSET_TABLE_\+0x10>
+ [ ]*[a-f0-9]+: 0f 1f 00 nopl \(%rax\)
+ [ ]*[a-f0-9]+: 68 00 00 00 00 pushq \$0x0
+-[ ]*[a-f0-9]+: f2 e9 e5 ff ff ff bnd jmpq 290 <foo2@plt-0x50>
++[ ]*[a-f0-9]+: f2 e9 e5 ff ff ff bnd jmpq 290 <.*>
+ [ ]*[a-f0-9]+: 0f 1f 44 00 00 nopl 0x0\(%rax,%rax,1\)
+ [ ]*[a-f0-9]+: 68 01 00 00 00 pushq \$0x1
+-[ ]*[a-f0-9]+: f2 e9 d5 ff ff ff bnd jmpq 290 <foo2@plt-0x50>
++[ ]*[a-f0-9]+: f2 e9 d5 ff ff ff bnd jmpq 290 <.*>
+ [ ]*[a-f0-9]+: 0f 1f 44 00 00 nopl 0x0\(%rax,%rax,1\)
+ [ ]*[a-f0-9]+: 68 02 00 00 00 pushq \$0x2
+-[ ]*[a-f0-9]+: f2 e9 c5 ff ff ff bnd jmpq 290 <foo2@plt-0x50>
++[ ]*[a-f0-9]+: f2 e9 c5 ff ff ff bnd jmpq 290 <.*>
+ [ ]*[a-f0-9]+: 0f 1f 44 00 00 nopl 0x0\(%rax,%rax,1\)
+ [ ]*[a-f0-9]+: 68 03 00 00 00 pushq \$0x3
+-[ ]*[a-f0-9]+: f2 e9 b5 ff ff ff bnd jmpq 290 <foo2@plt-0x50>
++[ ]*[a-f0-9]+: f2 e9 b5 ff ff ff bnd jmpq 290 <.*>
+ [ ]*[a-f0-9]+: 0f 1f 44 00 00 nopl 0x0\(%rax,%rax,1\)
+
+ Disassembly of section .plt.bnd:
+
+ 0+2e0 <foo2@plt>:
+-[ ]*[a-f0-9]+: f2 ff 25 41 01 20 00 bnd jmpq \*0x200141\(%rip\) # 200428 <_GLOBAL_OFFSET_TABLE_\+0x18>
++[ ]*[a-f0-9]+: f2 ff 25 41 01 20 00 bnd jmpq \*0x200141\(%rip\) # 200428 <foo2>
+ [ ]*[a-f0-9]+: 90 nop
+
+ 0+2e8 <foo3@plt>:
+-[ ]*[a-f0-9]+: f2 ff 25 41 01 20 00 bnd jmpq \*0x200141\(%rip\) # 200430 <_GLOBAL_OFFSET_TABLE_\+0x20>
++[ ]*[a-f0-9]+: f2 ff 25 41 01 20 00 bnd jmpq \*0x200141\(%rip\) # 200430 <foo3>
+ [ ]*[a-f0-9]+: 90 nop
+
+ 0+2f0 <foo1@plt>:
+-[ ]*[a-f0-9]+: f2 ff 25 41 01 20 00 bnd jmpq \*0x200141\(%rip\) # 200438 <_GLOBAL_OFFSET_TABLE_\+0x28>
++[ ]*[a-f0-9]+: f2 ff 25 41 01 20 00 bnd jmpq \*0x200141\(%rip\) # 200438 <foo1>
+ [ ]*[a-f0-9]+: 90 nop
+
+ 0+2f8 <foo4@plt>:
+-[ ]*[a-f0-9]+: f2 ff 25 41 01 20 00 bnd jmpq \*0x200141\(%rip\) # 200440 <_GLOBAL_OFFSET_TABLE_\+0x30>
++[ ]*[a-f0-9]+: f2 ff 25 41 01 20 00 bnd jmpq \*0x200141\(%rip\) # 200440 <foo4>
+ [ ]*[a-f0-9]+: 90 nop
+
+ Disassembly of section .text:
+diff --git a/ld/testsuite/ld-x86-64/gotpcrel1.dd b/ld/testsuite/ld-x86-64/gotpcrel1.dd
+index 46321db..58450bd 100644
+--- a/ld/testsuite/ld-x86-64/gotpcrel1.dd
++++ b/ld/testsuite/ld-x86-64/gotpcrel1.dd
+@@ -2,13 +2,13 @@
+ [a-f0-9]+ <main>:
+ [ ]*[a-f0-9]+: 48 83 ec 08 sub \$0x8,%rsp
+ [ ]*[a-f0-9]+: [ a-f0-9]+ addr32 callq [a-f0-9]+ <foo>
+-[ ]*[a-f0-9]+: [ a-f0-9]+ callq \*0x[a-f0-9]+\(%rip\) # [a-f0-9]+ <_DYNAMIC\+0x[a-f0-9]+>
+-[ ]*[a-f0-9]+: [ a-f0-9]+ callq \*0x[a-f0-9]+\(%rip\) # [a-f0-9]+ <_DYNAMIC\+0x[a-f0-9]+>
++[ ]*[a-f0-9]+: [ a-f0-9]+ callq \*0x[a-f0-9]+\(%rip\) # [a-f0-9]+ <.*>
++[ ]*[a-f0-9]+: [ a-f0-9]+ callq \*0x[a-f0-9]+\(%rip\) # [a-f0-9]+ <.*>
+ [ ]*[a-f0-9]+: [ a-f0-9]+ (rex mov|mov ) \$0x[a-f0-9]+,%(r|e)ax
+ [ ]*[a-f0-9]+: ff d0 callq \*%rax
+-[ ]*[a-f0-9]+: [ a-f0-9]+ mov 0x[a-f0-9]+\(%rip\),%rcx # [a-f0-9]+ <_DYNAMIC\+0x[a-f0-9]+>
++[ ]*[a-f0-9]+: [ a-f0-9]+ mov 0x[a-f0-9]+\(%rip\),%rcx # [a-f0-9]+ <.*>
+ [ ]*[a-f0-9]+: ff d1 callq \*%rcx
+-[ ]*[a-f0-9]+: [ a-f0-9]+ mov 0x[a-f0-9]+\(%rip\),%rdx # [a-f0-9]+ <_DYNAMIC\+0x[a-f0-9]+>
++[ ]*[a-f0-9]+: [ a-f0-9]+ mov 0x[a-f0-9]+\(%rip\),%rdx # [a-f0-9]+ <.*>
+ [ ]*[a-f0-9]+: ff d2 callq \*%rdx
+ [ ]*[a-f0-9]+: 31 ff xor %edi,%edi
+ [ ]*[a-f0-9]+: 48 83 c4 08 add \$0x8,%rsp
+diff --git a/ld/testsuite/ld-x86-64/libno-plt-1b.dd b/ld/testsuite/ld-x86-64/libno-plt-1b.dd
+index 2892ce4..93d8a7b 100644
+--- a/ld/testsuite/ld-x86-64/libno-plt-1b.dd
++++ b/ld/testsuite/ld-x86-64/libno-plt-1b.dd
+@@ -7,9 +7,9 @@ Disassembly of section .text:
+
+ #...
+ [0-9a-f]+ <get_func>:
+- +[a-f0-9]+: 48 8b 05 ([0-9a-f]{2} ){4}[ ]+mov 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <_DYNAMIC\+0x[0-9a-f]+>
++ +[a-f0-9]+: 48 8b 05 ([0-9a-f]{2} ){4}[ ]+mov 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <.*>
+ +[a-f0-9]+: c3 retq
+ #...
+ [0-9a-f]+ <call_func>:
+- +[a-f0-9]+: ff 25 ([0-9a-f]{2} ){4}[ ]+jmpq \*0x[0-9a-f]+\(%rip\) +# [0-9a-f]+ <_DYNAMIC\+0x[0-9a-f]+>
++ +[a-f0-9]+: ff 25 ([0-9a-f]{2} ){4}[ ]+jmpq \*0x[0-9a-f]+\(%rip\) +# [0-9a-f]+ <.*>
+ #pass
+diff --git a/ld/testsuite/ld-x86-64/load1c-nacl.d b/ld/testsuite/ld-x86-64/load1c-nacl.d
+index be90480..57bc2c2 100644
+--- a/ld/testsuite/ld-x86-64/load1c-nacl.d
++++ b/ld/testsuite/ld-x86-64/load1c-nacl.d
+@@ -9,40 +9,40 @@
+ Disassembly of section .text:
+
+ 0+ <_start>:
+-[ ]*[a-f0-9]+: 13 05 0a 03 01 10 adc 0x1001030a\(%rip\),%eax # 10010310 <_DYNAMIC\+0xe0>
+-[ ]*[a-f0-9]+: 03 1d 04 03 01 10 add 0x10010304\(%rip\),%ebx # 10010310 <_DYNAMIC\+0xe0>
+-[ ]*[a-f0-9]+: 23 0d fe 02 01 10 and 0x100102fe\(%rip\),%ecx # 10010310 <_DYNAMIC\+0xe0>
+-[ ]*[a-f0-9]+: 3b 15 f8 02 01 10 cmp 0x100102f8\(%rip\),%edx # 10010310 <_DYNAMIC\+0xe0>
+-[ ]*[a-f0-9]+: 0b 35 f2 02 01 10 or 0x100102f2\(%rip\),%esi # 10010310 <_DYNAMIC\+0xe0>
+-[ ]*[a-f0-9]+: 1b 3d ec 02 01 10 sbb 0x100102ec\(%rip\),%edi # 10010310 <_DYNAMIC\+0xe0>
+-[ ]*[a-f0-9]+: 2b 2d e6 02 01 10 sub 0x100102e6\(%rip\),%ebp # 10010310 <_DYNAMIC\+0xe0>
+-[ ]*[a-f0-9]+: 44 33 05 df 02 01 10 xor 0x100102df\(%rip\),%r8d # 10010310 <_DYNAMIC\+0xe0>
+-[ ]*[a-f0-9]+: 44 85 3d d8 02 01 10 test %r15d,0x100102d8\(%rip\) # 10010310 <_DYNAMIC\+0xe0>
+-[ ]*[a-f0-9]+: 48 13 05 d1 02 01 10 adc 0x100102d1\(%rip\),%rax # 10010310 <_DYNAMIC\+0xe0>
+-[ ]*[a-f0-9]+: 48 03 1d ca 02 01 10 add 0x100102ca\(%rip\),%rbx # 10010310 <_DYNAMIC\+0xe0>
+-[ ]*[a-f0-9]+: 48 23 0d c3 02 01 10 and 0x100102c3\(%rip\),%rcx # 10010310 <_DYNAMIC\+0xe0>
+-[ ]*[a-f0-9]+: 48 3b 15 bc 02 01 10 cmp 0x100102bc\(%rip\),%rdx # 10010310 <_DYNAMIC\+0xe0>
+-[ ]*[a-f0-9]+: 48 0b 3d b5 02 01 10 or 0x100102b5\(%rip\),%rdi # 10010310 <_DYNAMIC\+0xe0>
+-[ ]*[a-f0-9]+: 48 1b 35 ae 02 01 10 sbb 0x100102ae\(%rip\),%rsi # 10010310 <_DYNAMIC\+0xe0>
+-[ ]*[a-f0-9]+: 48 2b 2d a7 02 01 10 sub 0x100102a7\(%rip\),%rbp # 10010310 <_DYNAMIC\+0xe0>
+-[ ]*[a-f0-9]+: 4c 33 05 a0 02 01 10 xor 0x100102a0\(%rip\),%r8 # 10010310 <_DYNAMIC\+0xe0>
+-[ ]*[a-f0-9]+: 4c 85 3d 99 02 01 10 test %r15,0x10010299\(%rip\) # 10010310 <_DYNAMIC\+0xe0>
+-[ ]*[a-f0-9]+: 13 05 9b 02 01 10 adc 0x1001029b\(%rip\),%eax # 10010318 <_DYNAMIC\+0xe8>
+-[ ]*[a-f0-9]+: 03 1d 95 02 01 10 add 0x10010295\(%rip\),%ebx # 10010318 <_DYNAMIC\+0xe8>
+-[ ]*[a-f0-9]+: 23 0d 8f 02 01 10 and 0x1001028f\(%rip\),%ecx # 10010318 <_DYNAMIC\+0xe8>
+-[ ]*[a-f0-9]+: 3b 15 89 02 01 10 cmp 0x10010289\(%rip\),%edx # 10010318 <_DYNAMIC\+0xe8>
+-[ ]*[a-f0-9]+: 0b 35 83 02 01 10 or 0x10010283\(%rip\),%esi # 10010318 <_DYNAMIC\+0xe8>
+-[ ]*[a-f0-9]+: 1b 3d 7d 02 01 10 sbb 0x1001027d\(%rip\),%edi # 10010318 <_DYNAMIC\+0xe8>
+-[ ]*[a-f0-9]+: 2b 2d 77 02 01 10 sub 0x10010277\(%rip\),%ebp # 10010318 <_DYNAMIC\+0xe8>
+-[ ]*[a-f0-9]+: 44 33 05 70 02 01 10 xor 0x10010270\(%rip\),%r8d # 10010318 <_DYNAMIC\+0xe8>
+-[ ]*[a-f0-9]+: 44 85 3d 69 02 01 10 test %r15d,0x10010269\(%rip\) # 10010318 <_DYNAMIC\+0xe8>
+-[ ]*[a-f0-9]+: 48 13 05 62 02 01 10 adc 0x10010262\(%rip\),%rax # 10010318 <_DYNAMIC\+0xe8>
+-[ ]*[a-f0-9]+: 48 03 1d 5b 02 01 10 add 0x1001025b\(%rip\),%rbx # 10010318 <_DYNAMIC\+0xe8>
+-[ ]*[a-f0-9]+: 48 23 0d 54 02 01 10 and 0x10010254\(%rip\),%rcx # 10010318 <_DYNAMIC\+0xe8>
+-[ ]*[a-f0-9]+: 48 3b 15 4d 02 01 10 cmp 0x1001024d\(%rip\),%rdx # 10010318 <_DYNAMIC\+0xe8>
+-[ ]*[a-f0-9]+: 48 0b 3d 46 02 01 10 or 0x10010246\(%rip\),%rdi # 10010318 <_DYNAMIC\+0xe8>
+-[ ]*[a-f0-9]+: 48 1b 35 3f 02 01 10 sbb 0x1001023f\(%rip\),%rsi # 10010318 <_DYNAMIC\+0xe8>
+-[ ]*[a-f0-9]+: 48 2b 2d 38 02 01 10 sub 0x10010238\(%rip\),%rbp # 10010318 <_DYNAMIC\+0xe8>
+-[ ]*[a-f0-9]+: 4c 33 05 31 02 01 10 xor 0x10010231\(%rip\),%r8 # 10010318 <_DYNAMIC\+0xe8>
+-[ ]*[a-f0-9]+: 4c 85 3d 2a 02 01 10 test %r15,0x1001022a\(%rip\) # 10010318 <_DYNAMIC\+0xe8>
++[ ]*[a-f0-9]+: 13 05 0a 03 01 10 adc 0x1001030a\(%rip\),%eax # 10010310 <.*>
++[ ]*[a-f0-9]+: 03 1d 04 03 01 10 add 0x10010304\(%rip\),%ebx # 10010310 <.*>
++[ ]*[a-f0-9]+: 23 0d fe 02 01 10 and 0x100102fe\(%rip\),%ecx # 10010310 <.*>
++[ ]*[a-f0-9]+: 3b 15 f8 02 01 10 cmp 0x100102f8\(%rip\),%edx # 10010310 <.*>
++[ ]*[a-f0-9]+: 0b 35 f2 02 01 10 or 0x100102f2\(%rip\),%esi # 10010310 <.*>
++[ ]*[a-f0-9]+: 1b 3d ec 02 01 10 sbb 0x100102ec\(%rip\),%edi # 10010310 <.*>
++[ ]*[a-f0-9]+: 2b 2d e6 02 01 10 sub 0x100102e6\(%rip\),%ebp # 10010310 <.*>
++[ ]*[a-f0-9]+: 44 33 05 df 02 01 10 xor 0x100102df\(%rip\),%r8d # 10010310 <.*>
++[ ]*[a-f0-9]+: 44 85 3d d8 02 01 10 test %r15d,0x100102d8\(%rip\) # 10010310 <.*>
++[ ]*[a-f0-9]+: 48 13 05 d1 02 01 10 adc 0x100102d1\(%rip\),%rax # 10010310 <.*>
++[ ]*[a-f0-9]+: 48 03 1d ca 02 01 10 add 0x100102ca\(%rip\),%rbx # 10010310 <.*>
++[ ]*[a-f0-9]+: 48 23 0d c3 02 01 10 and 0x100102c3\(%rip\),%rcx # 10010310 <.*>
++[ ]*[a-f0-9]+: 48 3b 15 bc 02 01 10 cmp 0x100102bc\(%rip\),%rdx # 10010310 <.*>
++[ ]*[a-f0-9]+: 48 0b 3d b5 02 01 10 or 0x100102b5\(%rip\),%rdi # 10010310 <.*>
++[ ]*[a-f0-9]+: 48 1b 35 ae 02 01 10 sbb 0x100102ae\(%rip\),%rsi # 10010310 <.*>
++[ ]*[a-f0-9]+: 48 2b 2d a7 02 01 10 sub 0x100102a7\(%rip\),%rbp # 10010310 <.*>
++[ ]*[a-f0-9]+: 4c 33 05 a0 02 01 10 xor 0x100102a0\(%rip\),%r8 # 10010310 <.*>
++[ ]*[a-f0-9]+: 4c 85 3d 99 02 01 10 test %r15,0x10010299\(%rip\) # 10010310 <.*>
++[ ]*[a-f0-9]+: 13 05 9b 02 01 10 adc 0x1001029b\(%rip\),%eax # 10010318 <.*>
++[ ]*[a-f0-9]+: 03 1d 95 02 01 10 add 0x10010295\(%rip\),%ebx # 10010318 <.*>
++[ ]*[a-f0-9]+: 23 0d 8f 02 01 10 and 0x1001028f\(%rip\),%ecx # 10010318 <.*>
++[ ]*[a-f0-9]+: 3b 15 89 02 01 10 cmp 0x10010289\(%rip\),%edx # 10010318 <.*>
++[ ]*[a-f0-9]+: 0b 35 83 02 01 10 or 0x10010283\(%rip\),%esi # 10010318 <.*>
++[ ]*[a-f0-9]+: 1b 3d 7d 02 01 10 sbb 0x1001027d\(%rip\),%edi # 10010318 <.*>
++[ ]*[a-f0-9]+: 2b 2d 77 02 01 10 sub 0x10010277\(%rip\),%ebp # 10010318 <.*>
++[ ]*[a-f0-9]+: 44 33 05 70 02 01 10 xor 0x10010270\(%rip\),%r8d # 10010318 <.*>
++[ ]*[a-f0-9]+: 44 85 3d 69 02 01 10 test %r15d,0x10010269\(%rip\) # 10010318 <.*>
++[ ]*[a-f0-9]+: 48 13 05 62 02 01 10 adc 0x10010262\(%rip\),%rax # 10010318 <.*>
++[ ]*[a-f0-9]+: 48 03 1d 5b 02 01 10 add 0x1001025b\(%rip\),%rbx # 10010318 <.*>
++[ ]*[a-f0-9]+: 48 23 0d 54 02 01 10 and 0x10010254\(%rip\),%rcx # 10010318 <.*>
++[ ]*[a-f0-9]+: 48 3b 15 4d 02 01 10 cmp 0x1001024d\(%rip\),%rdx # 10010318 <.*>
++[ ]*[a-f0-9]+: 48 0b 3d 46 02 01 10 or 0x10010246\(%rip\),%rdi # 10010318 <.*>
++[ ]*[a-f0-9]+: 48 1b 35 3f 02 01 10 sbb 0x1001023f\(%rip\),%rsi # 10010318 <.*>
++[ ]*[a-f0-9]+: 48 2b 2d 38 02 01 10 sub 0x10010238\(%rip\),%rbp # 10010318 <.*>
++[ ]*[a-f0-9]+: 4c 33 05 31 02 01 10 xor 0x10010231\(%rip\),%r8 # 10010318 <.*>
++[ ]*[a-f0-9]+: 4c 85 3d 2a 02 01 10 test %r15,0x1001022a\(%rip\) # 10010318 <.*>
+ #pass
+diff --git a/ld/testsuite/ld-x86-64/load1c.d b/ld/testsuite/ld-x86-64/load1c.d
+index d4bf277..a4f7d8a 100644
+--- a/ld/testsuite/ld-x86-64/load1c.d
++++ b/ld/testsuite/ld-x86-64/load1c.d
+@@ -9,40 +9,40 @@
+ Disassembly of section .text:
+
+ [a-f0-9]+ <_start>:
+-[ ]*[a-f0-9]+: 13 05 ca 01 20 00 adc 0x2001ca\(%rip\),%eax # 2003c8 <_DYNAMIC\+0xe0>
+-[ ]*[a-f0-9]+: 03 1d c4 01 20 00 add 0x2001c4\(%rip\),%ebx # 2003c8 <_DYNAMIC\+0xe0>
+-[ ]*[a-f0-9]+: 23 0d be 01 20 00 and 0x2001be\(%rip\),%ecx # 2003c8 <_DYNAMIC\+0xe0>
+-[ ]*[a-f0-9]+: 3b 15 b8 01 20 00 cmp 0x2001b8\(%rip\),%edx # 2003c8 <_DYNAMIC\+0xe0>
+-[ ]*[a-f0-9]+: 0b 35 b2 01 20 00 or 0x2001b2\(%rip\),%esi # 2003c8 <_DYNAMIC\+0xe0>
+-[ ]*[a-f0-9]+: 1b 3d ac 01 20 00 sbb 0x2001ac\(%rip\),%edi # 2003c8 <_DYNAMIC\+0xe0>
+-[ ]*[a-f0-9]+: 2b 2d a6 01 20 00 sub 0x2001a6\(%rip\),%ebp # 2003c8 <_DYNAMIC\+0xe0>
+-[ ]*[a-f0-9]+: 44 33 05 9f 01 20 00 xor 0x20019f\(%rip\),%r8d # 2003c8 <_DYNAMIC\+0xe0>
+-[ ]*[a-f0-9]+: 44 85 3d 98 01 20 00 test %r15d,0x200198\(%rip\) # 2003c8 <_DYNAMIC\+0xe0>
+-[ ]*[a-f0-9]+: 48 13 05 91 01 20 00 adc 0x200191\(%rip\),%rax # 2003c8 <_DYNAMIC\+0xe0>
+-[ ]*[a-f0-9]+: 48 03 1d 8a 01 20 00 add 0x20018a\(%rip\),%rbx # 2003c8 <_DYNAMIC\+0xe0>
+-[ ]*[a-f0-9]+: 48 23 0d 83 01 20 00 and 0x200183\(%rip\),%rcx # 2003c8 <_DYNAMIC\+0xe0>
+-[ ]*[a-f0-9]+: 48 3b 15 7c 01 20 00 cmp 0x20017c\(%rip\),%rdx # 2003c8 <_DYNAMIC\+0xe0>
+-[ ]*[a-f0-9]+: 48 0b 3d 75 01 20 00 or 0x200175\(%rip\),%rdi # 2003c8 <_DYNAMIC\+0xe0>
+-[ ]*[a-f0-9]+: 48 1b 35 6e 01 20 00 sbb 0x20016e\(%rip\),%rsi # 2003c8 <_DYNAMIC\+0xe0>
+-[ ]*[a-f0-9]+: 48 2b 2d 67 01 20 00 sub 0x200167\(%rip\),%rbp # 2003c8 <_DYNAMIC\+0xe0>
+-[ ]*[a-f0-9]+: 4c 33 05 60 01 20 00 xor 0x200160\(%rip\),%r8 # 2003c8 <_DYNAMIC\+0xe0>
+-[ ]*[a-f0-9]+: 4c 85 3d 59 01 20 00 test %r15,0x200159\(%rip\) # 2003c8 <_DYNAMIC\+0xe0>
+-[ ]*[a-f0-9]+: 13 05 5b 01 20 00 adc 0x20015b\(%rip\),%eax # 2003d0 <_DYNAMIC\+0xe8>
+-[ ]*[a-f0-9]+: 03 1d 55 01 20 00 add 0x200155\(%rip\),%ebx # 2003d0 <_DYNAMIC\+0xe8>
+-[ ]*[a-f0-9]+: 23 0d 4f 01 20 00 and 0x20014f\(%rip\),%ecx # 2003d0 <_DYNAMIC\+0xe8>
+-[ ]*[a-f0-9]+: 3b 15 49 01 20 00 cmp 0x200149\(%rip\),%edx # 2003d0 <_DYNAMIC\+0xe8>
+-[ ]*[a-f0-9]+: 0b 35 43 01 20 00 or 0x200143\(%rip\),%esi # 2003d0 <_DYNAMIC\+0xe8>
+-[ ]*[a-f0-9]+: 1b 3d 3d 01 20 00 sbb 0x20013d\(%rip\),%edi # 2003d0 <_DYNAMIC\+0xe8>
+-[ ]*[a-f0-9]+: 2b 2d 37 01 20 00 sub 0x200137\(%rip\),%ebp # 2003d0 <_DYNAMIC\+0xe8>
+-[ ]*[a-f0-9]+: 44 33 05 30 01 20 00 xor 0x200130\(%rip\),%r8d # 2003d0 <_DYNAMIC\+0xe8>
+-[ ]*[a-f0-9]+: 44 85 3d 29 01 20 00 test %r15d,0x200129\(%rip\) # 2003d0 <_DYNAMIC\+0xe8>
+-[ ]*[a-f0-9]+: 48 13 05 22 01 20 00 adc 0x200122\(%rip\),%rax # 2003d0 <_DYNAMIC\+0xe8>
+-[ ]*[a-f0-9]+: 48 03 1d 1b 01 20 00 add 0x20011b\(%rip\),%rbx # 2003d0 <_DYNAMIC\+0xe8>
+-[ ]*[a-f0-9]+: 48 23 0d 14 01 20 00 and 0x200114\(%rip\),%rcx # 2003d0 <_DYNAMIC\+0xe8>
+-[ ]*[a-f0-9]+: 48 3b 15 0d 01 20 00 cmp 0x20010d\(%rip\),%rdx # 2003d0 <_DYNAMIC\+0xe8>
+-[ ]*[a-f0-9]+: 48 0b 3d 06 01 20 00 or 0x200106\(%rip\),%rdi # 2003d0 <_DYNAMIC\+0xe8>
+-[ ]*[a-f0-9]+: 48 1b 35 ff 00 20 00 sbb 0x2000ff\(%rip\),%rsi # 2003d0 <_DYNAMIC\+0xe8>
+-[ ]*[a-f0-9]+: 48 2b 2d f8 00 20 00 sub 0x2000f8\(%rip\),%rbp # 2003d0 <_DYNAMIC\+0xe8>
+-[ ]*[a-f0-9]+: 4c 33 05 f1 00 20 00 xor 0x2000f1\(%rip\),%r8 # 2003d0 <_DYNAMIC\+0xe8>
+-[ ]*[a-f0-9]+: 4c 85 3d ea 00 20 00 test %r15,0x2000ea\(%rip\) # 2003d0 <_DYNAMIC\+0xe8>
++[ ]*[a-f0-9]+: 13 05 ca 01 20 00 adc 0x2001ca\(%rip\),%eax # 2003c8 <.*>
++[ ]*[a-f0-9]+: 03 1d c4 01 20 00 add 0x2001c4\(%rip\),%ebx # 2003c8 <.*>
++[ ]*[a-f0-9]+: 23 0d be 01 20 00 and 0x2001be\(%rip\),%ecx # 2003c8 <.*>
++[ ]*[a-f0-9]+: 3b 15 b8 01 20 00 cmp 0x2001b8\(%rip\),%edx # 2003c8 <.*>
++[ ]*[a-f0-9]+: 0b 35 b2 01 20 00 or 0x2001b2\(%rip\),%esi # 2003c8 <.*>
++[ ]*[a-f0-9]+: 1b 3d ac 01 20 00 sbb 0x2001ac\(%rip\),%edi # 2003c8 <.*>
++[ ]*[a-f0-9]+: 2b 2d a6 01 20 00 sub 0x2001a6\(%rip\),%ebp # 2003c8 <.*>
++[ ]*[a-f0-9]+: 44 33 05 9f 01 20 00 xor 0x20019f\(%rip\),%r8d # 2003c8 <.*>
++[ ]*[a-f0-9]+: 44 85 3d 98 01 20 00 test %r15d,0x200198\(%rip\) # 2003c8 <.*>
++[ ]*[a-f0-9]+: 48 13 05 91 01 20 00 adc 0x200191\(%rip\),%rax # 2003c8 <.*>
++[ ]*[a-f0-9]+: 48 03 1d 8a 01 20 00 add 0x20018a\(%rip\),%rbx # 2003c8 <.*>
++[ ]*[a-f0-9]+: 48 23 0d 83 01 20 00 and 0x200183\(%rip\),%rcx # 2003c8 <.*>
++[ ]*[a-f0-9]+: 48 3b 15 7c 01 20 00 cmp 0x20017c\(%rip\),%rdx # 2003c8 <.*>
++[ ]*[a-f0-9]+: 48 0b 3d 75 01 20 00 or 0x200175\(%rip\),%rdi # 2003c8 <.*>
++[ ]*[a-f0-9]+: 48 1b 35 6e 01 20 00 sbb 0x20016e\(%rip\),%rsi # 2003c8 <.*>
++[ ]*[a-f0-9]+: 48 2b 2d 67 01 20 00 sub 0x200167\(%rip\),%rbp # 2003c8 <.*>
++[ ]*[a-f0-9]+: 4c 33 05 60 01 20 00 xor 0x200160\(%rip\),%r8 # 2003c8 <.*>
++[ ]*[a-f0-9]+: 4c 85 3d 59 01 20 00 test %r15,0x200159\(%rip\) # 2003c8 <.*>
++[ ]*[a-f0-9]+: 13 05 5b 01 20 00 adc 0x20015b\(%rip\),%eax # 2003d0 <.*>
++[ ]*[a-f0-9]+: 03 1d 55 01 20 00 add 0x200155\(%rip\),%ebx # 2003d0 <.*>
++[ ]*[a-f0-9]+: 23 0d 4f 01 20 00 and 0x20014f\(%rip\),%ecx # 2003d0 <.*>
++[ ]*[a-f0-9]+: 3b 15 49 01 20 00 cmp 0x200149\(%rip\),%edx # 2003d0 <.*>
++[ ]*[a-f0-9]+: 0b 35 43 01 20 00 or 0x200143\(%rip\),%esi # 2003d0 <.*>
++[ ]*[a-f0-9]+: 1b 3d 3d 01 20 00 sbb 0x20013d\(%rip\),%edi # 2003d0 <.*>
++[ ]*[a-f0-9]+: 2b 2d 37 01 20 00 sub 0x200137\(%rip\),%ebp # 2003d0 <.*>
++[ ]*[a-f0-9]+: 44 33 05 30 01 20 00 xor 0x200130\(%rip\),%r8d # 2003d0 <.*>
++[ ]*[a-f0-9]+: 44 85 3d 29 01 20 00 test %r15d,0x200129\(%rip\) # 2003d0 <.*>
++[ ]*[a-f0-9]+: 48 13 05 22 01 20 00 adc 0x200122\(%rip\),%rax # 2003d0 <.*>
++[ ]*[a-f0-9]+: 48 03 1d 1b 01 20 00 add 0x20011b\(%rip\),%rbx # 2003d0 <.*>
++[ ]*[a-f0-9]+: 48 23 0d 14 01 20 00 and 0x200114\(%rip\),%rcx # 2003d0 <.*>
++[ ]*[a-f0-9]+: 48 3b 15 0d 01 20 00 cmp 0x20010d\(%rip\),%rdx # 2003d0 <.*>
++[ ]*[a-f0-9]+: 48 0b 3d 06 01 20 00 or 0x200106\(%rip\),%rdi # 2003d0 <.*>
++[ ]*[a-f0-9]+: 48 1b 35 ff 00 20 00 sbb 0x2000ff\(%rip\),%rsi # 2003d0 <.*>
++[ ]*[a-f0-9]+: 48 2b 2d f8 00 20 00 sub 0x2000f8\(%rip\),%rbp # 2003d0 <.*>
++[ ]*[a-f0-9]+: 4c 33 05 f1 00 20 00 xor 0x2000f1\(%rip\),%r8 # 2003d0 <.*>
++[ ]*[a-f0-9]+: 4c 85 3d ea 00 20 00 test %r15,0x2000ea\(%rip\) # 2003d0 <.*>
+ #pass
+diff --git a/ld/testsuite/ld-x86-64/load1d-nacl.d b/ld/testsuite/ld-x86-64/load1d-nacl.d
+index 3e9b144..b741917 100644
+--- a/ld/testsuite/ld-x86-64/load1d-nacl.d
++++ b/ld/testsuite/ld-x86-64/load1d-nacl.d
+@@ -9,40 +9,40 @@
+ Disassembly of section .text:
+
+ 0+ <_start>:
+-[ ]*[a-f0-9]+: 13 05 e2 01 01 10 adc 0x100101e2\(%rip\),%eax # 100101e8 <_DYNAMIC\+0x70>
+-[ ]*[a-f0-9]+: 03 1d dc 01 01 10 add 0x100101dc\(%rip\),%ebx # 100101e8 <_DYNAMIC\+0x70>
+-[ ]*[a-f0-9]+: 23 0d d6 01 01 10 and 0x100101d6\(%rip\),%ecx # 100101e8 <_DYNAMIC\+0x70>
+-[ ]*[a-f0-9]+: 3b 15 d0 01 01 10 cmp 0x100101d0\(%rip\),%edx # 100101e8 <_DYNAMIC\+0x70>
+-[ ]*[a-f0-9]+: 0b 35 ca 01 01 10 or 0x100101ca\(%rip\),%esi # 100101e8 <_DYNAMIC\+0x70>
+-[ ]*[a-f0-9]+: 1b 3d c4 01 01 10 sbb 0x100101c4\(%rip\),%edi # 100101e8 <_DYNAMIC\+0x70>
+-[ ]*[a-f0-9]+: 2b 2d be 01 01 10 sub 0x100101be\(%rip\),%ebp # 100101e8 <_DYNAMIC\+0x70>
+-[ ]*[a-f0-9]+: 44 33 05 b7 01 01 10 xor 0x100101b7\(%rip\),%r8d # 100101e8 <_DYNAMIC\+0x70>
+-[ ]*[a-f0-9]+: 44 85 3d b0 01 01 10 test %r15d,0x100101b0\(%rip\) # 100101e8 <_DYNAMIC\+0x70>
+-[ ]*[a-f0-9]+: 48 13 05 a9 01 01 10 adc 0x100101a9\(%rip\),%rax # 100101e8 <_DYNAMIC\+0x70>
+-[ ]*[a-f0-9]+: 48 03 1d a2 01 01 10 add 0x100101a2\(%rip\),%rbx # 100101e8 <_DYNAMIC\+0x70>
+-[ ]*[a-f0-9]+: 48 23 0d 9b 01 01 10 and 0x1001019b\(%rip\),%rcx # 100101e8 <_DYNAMIC\+0x70>
+-[ ]*[a-f0-9]+: 48 3b 15 94 01 01 10 cmp 0x10010194\(%rip\),%rdx # 100101e8 <_DYNAMIC\+0x70>
+-[ ]*[a-f0-9]+: 48 0b 3d 8d 01 01 10 or 0x1001018d\(%rip\),%rdi # 100101e8 <_DYNAMIC\+0x70>
+-[ ]*[a-f0-9]+: 48 1b 35 86 01 01 10 sbb 0x10010186\(%rip\),%rsi # 100101e8 <_DYNAMIC\+0x70>
+-[ ]*[a-f0-9]+: 48 2b 2d 7f 01 01 10 sub 0x1001017f\(%rip\),%rbp # 100101e8 <_DYNAMIC\+0x70>
+-[ ]*[a-f0-9]+: 4c 33 05 78 01 01 10 xor 0x10010178\(%rip\),%r8 # 100101e8 <_DYNAMIC\+0x70>
+-[ ]*[a-f0-9]+: 4c 85 3d 71 01 01 10 test %r15,0x10010171\(%rip\) # 100101e8 <_DYNAMIC\+0x70>
+-[ ]*[a-f0-9]+: 13 05 73 01 01 10 adc 0x10010173\(%rip\),%eax # 100101f0 <_DYNAMIC\+0x78>
+-[ ]*[a-f0-9]+: 03 1d 6d 01 01 10 add 0x1001016d\(%rip\),%ebx # 100101f0 <_DYNAMIC\+0x78>
+-[ ]*[a-f0-9]+: 23 0d 67 01 01 10 and 0x10010167\(%rip\),%ecx # 100101f0 <_DYNAMIC\+0x78>
+-[ ]*[a-f0-9]+: 3b 15 61 01 01 10 cmp 0x10010161\(%rip\),%edx # 100101f0 <_DYNAMIC\+0x78>
+-[ ]*[a-f0-9]+: 0b 35 5b 01 01 10 or 0x1001015b\(%rip\),%esi # 100101f0 <_DYNAMIC\+0x78>
+-[ ]*[a-f0-9]+: 1b 3d 55 01 01 10 sbb 0x10010155\(%rip\),%edi # 100101f0 <_DYNAMIC\+0x78>
+-[ ]*[a-f0-9]+: 2b 2d 4f 01 01 10 sub 0x1001014f\(%rip\),%ebp # 100101f0 <_DYNAMIC\+0x78>
+-[ ]*[a-f0-9]+: 44 33 05 48 01 01 10 xor 0x10010148\(%rip\),%r8d # 100101f0 <_DYNAMIC\+0x78>
+-[ ]*[a-f0-9]+: 44 85 3d 41 01 01 10 test %r15d,0x10010141\(%rip\) # 100101f0 <_DYNAMIC\+0x78>
+-[ ]*[a-f0-9]+: 48 13 05 3a 01 01 10 adc 0x1001013a\(%rip\),%rax # 100101f0 <_DYNAMIC\+0x78>
+-[ ]*[a-f0-9]+: 48 03 1d 33 01 01 10 add 0x10010133\(%rip\),%rbx # 100101f0 <_DYNAMIC\+0x78>
+-[ ]*[a-f0-9]+: 48 23 0d 2c 01 01 10 and 0x1001012c\(%rip\),%rcx # 100101f0 <_DYNAMIC\+0x78>
+-[ ]*[a-f0-9]+: 48 3b 15 25 01 01 10 cmp 0x10010125\(%rip\),%rdx # 100101f0 <_DYNAMIC\+0x78>
+-[ ]*[a-f0-9]+: 48 0b 3d 1e 01 01 10 or 0x1001011e\(%rip\),%rdi # 100101f0 <_DYNAMIC\+0x78>
+-[ ]*[a-f0-9]+: 48 1b 35 17 01 01 10 sbb 0x10010117\(%rip\),%rsi # 100101f0 <_DYNAMIC\+0x78>
+-[ ]*[a-f0-9]+: 48 2b 2d 10 01 01 10 sub 0x10010110\(%rip\),%rbp # 100101f0 <_DYNAMIC\+0x78>
+-[ ]*[a-f0-9]+: 4c 33 05 09 01 01 10 xor 0x10010109\(%rip\),%r8 # 100101f0 <_DYNAMIC\+0x78>
+-[ ]*[a-f0-9]+: 4c 85 3d 02 01 01 10 test %r15,0x10010102\(%rip\) # 100101f0 <_DYNAMIC\+0x78>
++[ ]*[a-f0-9]+: 13 05 e2 01 01 10 adc 0x100101e2\(%rip\),%eax # 100101e8 <.*>
++[ ]*[a-f0-9]+: 03 1d dc 01 01 10 add 0x100101dc\(%rip\),%ebx # 100101e8 <.*>
++[ ]*[a-f0-9]+: 23 0d d6 01 01 10 and 0x100101d6\(%rip\),%ecx # 100101e8 <.*>
++[ ]*[a-f0-9]+: 3b 15 d0 01 01 10 cmp 0x100101d0\(%rip\),%edx # 100101e8 <.*>
++[ ]*[a-f0-9]+: 0b 35 ca 01 01 10 or 0x100101ca\(%rip\),%esi # 100101e8 <.*>
++[ ]*[a-f0-9]+: 1b 3d c4 01 01 10 sbb 0x100101c4\(%rip\),%edi # 100101e8 <.*>
++[ ]*[a-f0-9]+: 2b 2d be 01 01 10 sub 0x100101be\(%rip\),%ebp # 100101e8 <.*>
++[ ]*[a-f0-9]+: 44 33 05 b7 01 01 10 xor 0x100101b7\(%rip\),%r8d # 100101e8 <.*>
++[ ]*[a-f0-9]+: 44 85 3d b0 01 01 10 test %r15d,0x100101b0\(%rip\) # 100101e8 <.*>
++[ ]*[a-f0-9]+: 48 13 05 a9 01 01 10 adc 0x100101a9\(%rip\),%rax # 100101e8 <.*>
++[ ]*[a-f0-9]+: 48 03 1d a2 01 01 10 add 0x100101a2\(%rip\),%rbx # 100101e8 <.*>
++[ ]*[a-f0-9]+: 48 23 0d 9b 01 01 10 and 0x1001019b\(%rip\),%rcx # 100101e8 <.*>
++[ ]*[a-f0-9]+: 48 3b 15 94 01 01 10 cmp 0x10010194\(%rip\),%rdx # 100101e8 <.*>
++[ ]*[a-f0-9]+: 48 0b 3d 8d 01 01 10 or 0x1001018d\(%rip\),%rdi # 100101e8 <.*>
++[ ]*[a-f0-9]+: 48 1b 35 86 01 01 10 sbb 0x10010186\(%rip\),%rsi # 100101e8 <.*>
++[ ]*[a-f0-9]+: 48 2b 2d 7f 01 01 10 sub 0x1001017f\(%rip\),%rbp # 100101e8 <.*>
++[ ]*[a-f0-9]+: 4c 33 05 78 01 01 10 xor 0x10010178\(%rip\),%r8 # 100101e8 <.*>
++[ ]*[a-f0-9]+: 4c 85 3d 71 01 01 10 test %r15,0x10010171\(%rip\) # 100101e8 <.*>
++[ ]*[a-f0-9]+: 13 05 73 01 01 10 adc 0x10010173\(%rip\),%eax # 100101f0 <.*>
++[ ]*[a-f0-9]+: 03 1d 6d 01 01 10 add 0x1001016d\(%rip\),%ebx # 100101f0 <.*>
++[ ]*[a-f0-9]+: 23 0d 67 01 01 10 and 0x10010167\(%rip\),%ecx # 100101f0 <.*>
++[ ]*[a-f0-9]+: 3b 15 61 01 01 10 cmp 0x10010161\(%rip\),%edx # 100101f0 <.*>
++[ ]*[a-f0-9]+: 0b 35 5b 01 01 10 or 0x1001015b\(%rip\),%esi # 100101f0 <.*>
++[ ]*[a-f0-9]+: 1b 3d 55 01 01 10 sbb 0x10010155\(%rip\),%edi # 100101f0 <.*>
++[ ]*[a-f0-9]+: 2b 2d 4f 01 01 10 sub 0x1001014f\(%rip\),%ebp # 100101f0 <.*>
++[ ]*[a-f0-9]+: 44 33 05 48 01 01 10 xor 0x10010148\(%rip\),%r8d # 100101f0 <.*>
++[ ]*[a-f0-9]+: 44 85 3d 41 01 01 10 test %r15d,0x10010141\(%rip\) # 100101f0 <.*>
++[ ]*[a-f0-9]+: 48 13 05 3a 01 01 10 adc 0x1001013a\(%rip\),%rax # 100101f0 <.*>
++[ ]*[a-f0-9]+: 48 03 1d 33 01 01 10 add 0x10010133\(%rip\),%rbx # 100101f0 <.*>
++[ ]*[a-f0-9]+: 48 23 0d 2c 01 01 10 and 0x1001012c\(%rip\),%rcx # 100101f0 <.*>
++[ ]*[a-f0-9]+: 48 3b 15 25 01 01 10 cmp 0x10010125\(%rip\),%rdx # 100101f0 <.*>
++[ ]*[a-f0-9]+: 48 0b 3d 1e 01 01 10 or 0x1001011e\(%rip\),%rdi # 100101f0 <.*>
++[ ]*[a-f0-9]+: 48 1b 35 17 01 01 10 sbb 0x10010117\(%rip\),%rsi # 100101f0 <.*>
++[ ]*[a-f0-9]+: 48 2b 2d 10 01 01 10 sub 0x10010110\(%rip\),%rbp # 100101f0 <.*>
++[ ]*[a-f0-9]+: 4c 33 05 09 01 01 10 xor 0x10010109\(%rip\),%r8 # 100101f0 <.*>
++[ ]*[a-f0-9]+: 4c 85 3d 02 01 01 10 test %r15,0x10010102\(%rip\) # 100101f0 <.*>
+ #pass
+diff --git a/ld/testsuite/ld-x86-64/load1d.d b/ld/testsuite/ld-x86-64/load1d.d
+index 2987048..ee1e3f0 100644
+--- a/ld/testsuite/ld-x86-64/load1d.d
++++ b/ld/testsuite/ld-x86-64/load1d.d
+@@ -9,40 +9,40 @@
+ Disassembly of section .text:
+
+ 0+[a-f0-9]+ <_start>:
+-[ ]*[a-f0-9]+: 13 05 5a 01 20 00 adc 0x20015a\(%rip\),%eax # 2002b8 <_DYNAMIC\+0x70>
+-[ ]*[a-f0-9]+: 03 1d 54 01 20 00 add 0x200154\(%rip\),%ebx # 2002b8 <_DYNAMIC\+0x70>
+-[ ]*[a-f0-9]+: 23 0d 4e 01 20 00 and 0x20014e\(%rip\),%ecx # 2002b8 <_DYNAMIC\+0x70>
+-[ ]*[a-f0-9]+: 3b 15 48 01 20 00 cmp 0x200148\(%rip\),%edx # 2002b8 <_DYNAMIC\+0x70>
+-[ ]*[a-f0-9]+: 0b 35 42 01 20 00 or 0x200142\(%rip\),%esi # 2002b8 <_DYNAMIC\+0x70>
+-[ ]*[a-f0-9]+: 1b 3d 3c 01 20 00 sbb 0x20013c\(%rip\),%edi # 2002b8 <_DYNAMIC\+0x70>
+-[ ]*[a-f0-9]+: 2b 2d 36 01 20 00 sub 0x200136\(%rip\),%ebp # 2002b8 <_DYNAMIC\+0x70>
+-[ ]*[a-f0-9]+: 44 33 05 2f 01 20 00 xor 0x20012f\(%rip\),%r8d # 2002b8 <_DYNAMIC\+0x70>
+-[ ]*[a-f0-9]+: 44 85 3d 28 01 20 00 test %r15d,0x200128\(%rip\) # 2002b8 <_DYNAMIC\+0x70>
+-[ ]*[a-f0-9]+: 48 13 05 21 01 20 00 adc 0x200121\(%rip\),%rax # 2002b8 <_DYNAMIC\+0x70>
+-[ ]*[a-f0-9]+: 48 03 1d 1a 01 20 00 add 0x20011a\(%rip\),%rbx # 2002b8 <_DYNAMIC\+0x70>
+-[ ]*[a-f0-9]+: 48 23 0d 13 01 20 00 and 0x200113\(%rip\),%rcx # 2002b8 <_DYNAMIC\+0x70>
+-[ ]*[a-f0-9]+: 48 3b 15 0c 01 20 00 cmp 0x20010c\(%rip\),%rdx # 2002b8 <_DYNAMIC\+0x70>
+-[ ]*[a-f0-9]+: 48 0b 3d 05 01 20 00 or 0x200105\(%rip\),%rdi # 2002b8 <_DYNAMIC\+0x70>
+-[ ]*[a-f0-9]+: 48 1b 35 fe 00 20 00 sbb 0x2000fe\(%rip\),%rsi # 2002b8 <_DYNAMIC\+0x70>
+-[ ]*[a-f0-9]+: 48 2b 2d f7 00 20 00 sub 0x2000f7\(%rip\),%rbp # 2002b8 <_DYNAMIC\+0x70>
+-[ ]*[a-f0-9]+: 4c 33 05 f0 00 20 00 xor 0x2000f0\(%rip\),%r8 # 2002b8 <_DYNAMIC\+0x70>
+-[ ]*[a-f0-9]+: 4c 85 3d e9 00 20 00 test %r15,0x2000e9\(%rip\) # 2002b8 <_DYNAMIC\+0x70>
+-[ ]*[a-f0-9]+: 13 05 eb 00 20 00 adc 0x2000eb\(%rip\),%eax # 2002c0 <_DYNAMIC\+0x78>
+-[ ]*[a-f0-9]+: 03 1d e5 00 20 00 add 0x2000e5\(%rip\),%ebx # 2002c0 <_DYNAMIC\+0x78>
+-[ ]*[a-f0-9]+: 23 0d df 00 20 00 and 0x2000df\(%rip\),%ecx # 2002c0 <_DYNAMIC\+0x78>
+-[ ]*[a-f0-9]+: 3b 15 d9 00 20 00 cmp 0x2000d9\(%rip\),%edx # 2002c0 <_DYNAMIC\+0x78>
+-[ ]*[a-f0-9]+: 0b 35 d3 00 20 00 or 0x2000d3\(%rip\),%esi # 2002c0 <_DYNAMIC\+0x78>
+-[ ]*[a-f0-9]+: 1b 3d cd 00 20 00 sbb 0x2000cd\(%rip\),%edi # 2002c0 <_DYNAMIC\+0x78>
+-[ ]*[a-f0-9]+: 2b 2d c7 00 20 00 sub 0x2000c7\(%rip\),%ebp # 2002c0 <_DYNAMIC\+0x78>
+-[ ]*[a-f0-9]+: 44 33 05 c0 00 20 00 xor 0x2000c0\(%rip\),%r8d # 2002c0 <_DYNAMIC\+0x78>
+-[ ]*[a-f0-9]+: 44 85 3d b9 00 20 00 test %r15d,0x2000b9\(%rip\) # 2002c0 <_DYNAMIC\+0x78>
+-[ ]*[a-f0-9]+: 48 13 05 b2 00 20 00 adc 0x2000b2\(%rip\),%rax # 2002c0 <_DYNAMIC\+0x78>
+-[ ]*[a-f0-9]+: 48 03 1d ab 00 20 00 add 0x2000ab\(%rip\),%rbx # 2002c0 <_DYNAMIC\+0x78>
+-[ ]*[a-f0-9]+: 48 23 0d a4 00 20 00 and 0x2000a4\(%rip\),%rcx # 2002c0 <_DYNAMIC\+0x78>
+-[ ]*[a-f0-9]+: 48 3b 15 9d 00 20 00 cmp 0x20009d\(%rip\),%rdx # 2002c0 <_DYNAMIC\+0x78>
+-[ ]*[a-f0-9]+: 48 0b 3d 96 00 20 00 or 0x200096\(%rip\),%rdi # 2002c0 <_DYNAMIC\+0x78>
+-[ ]*[a-f0-9]+: 48 1b 35 8f 00 20 00 sbb 0x20008f\(%rip\),%rsi # 2002c0 <_DYNAMIC\+0x78>
+-[ ]*[a-f0-9]+: 48 2b 2d 88 00 20 00 sub 0x200088\(%rip\),%rbp # 2002c0 <_DYNAMIC\+0x78>
+-[ ]*[a-f0-9]+: 4c 33 05 81 00 20 00 xor 0x200081\(%rip\),%r8 # 2002c0 <_DYNAMIC\+0x78>
+-[ ]*[a-f0-9]+: 4c 85 3d 7a 00 20 00 test %r15,0x20007a\(%rip\) # 2002c0 <_DYNAMIC\+0x78>
++[ ]*[a-f0-9]+: 13 05 5a 01 20 00 adc 0x20015a\(%rip\),%eax # 2002b8 <.*>
++[ ]*[a-f0-9]+: 03 1d 54 01 20 00 add 0x200154\(%rip\),%ebx # 2002b8 <.*>
++[ ]*[a-f0-9]+: 23 0d 4e 01 20 00 and 0x20014e\(%rip\),%ecx # 2002b8 <.*>
++[ ]*[a-f0-9]+: 3b 15 48 01 20 00 cmp 0x200148\(%rip\),%edx # 2002b8 <.*>
++[ ]*[a-f0-9]+: 0b 35 42 01 20 00 or 0x200142\(%rip\),%esi # 2002b8 <.*>
++[ ]*[a-f0-9]+: 1b 3d 3c 01 20 00 sbb 0x20013c\(%rip\),%edi # 2002b8 <.*>
++[ ]*[a-f0-9]+: 2b 2d 36 01 20 00 sub 0x200136\(%rip\),%ebp # 2002b8 <.*>
++[ ]*[a-f0-9]+: 44 33 05 2f 01 20 00 xor 0x20012f\(%rip\),%r8d # 2002b8 <.*>
++[ ]*[a-f0-9]+: 44 85 3d 28 01 20 00 test %r15d,0x200128\(%rip\) # 2002b8 <.*>
++[ ]*[a-f0-9]+: 48 13 05 21 01 20 00 adc 0x200121\(%rip\),%rax # 2002b8 <.*>
++[ ]*[a-f0-9]+: 48 03 1d 1a 01 20 00 add 0x20011a\(%rip\),%rbx # 2002b8 <.*>
++[ ]*[a-f0-9]+: 48 23 0d 13 01 20 00 and 0x200113\(%rip\),%rcx # 2002b8 <.*>
++[ ]*[a-f0-9]+: 48 3b 15 0c 01 20 00 cmp 0x20010c\(%rip\),%rdx # 2002b8 <.*>
++[ ]*[a-f0-9]+: 48 0b 3d 05 01 20 00 or 0x200105\(%rip\),%rdi # 2002b8 <.*>
++[ ]*[a-f0-9]+: 48 1b 35 fe 00 20 00 sbb 0x2000fe\(%rip\),%rsi # 2002b8 <.*>
++[ ]*[a-f0-9]+: 48 2b 2d f7 00 20 00 sub 0x2000f7\(%rip\),%rbp # 2002b8 <.*>
++[ ]*[a-f0-9]+: 4c 33 05 f0 00 20 00 xor 0x2000f0\(%rip\),%r8 # 2002b8 <.*>
++[ ]*[a-f0-9]+: 4c 85 3d e9 00 20 00 test %r15,0x2000e9\(%rip\) # 2002b8 <.*>
++[ ]*[a-f0-9]+: 13 05 eb 00 20 00 adc 0x2000eb\(%rip\),%eax # 2002c0 <.*>
++[ ]*[a-f0-9]+: 03 1d e5 00 20 00 add 0x2000e5\(%rip\),%ebx # 2002c0 <.*>
++[ ]*[a-f0-9]+: 23 0d df 00 20 00 and 0x2000df\(%rip\),%ecx # 2002c0 <.*>
++[ ]*[a-f0-9]+: 3b 15 d9 00 20 00 cmp 0x2000d9\(%rip\),%edx # 2002c0 <.*>
++[ ]*[a-f0-9]+: 0b 35 d3 00 20 00 or 0x2000d3\(%rip\),%esi # 2002c0 <.*>
++[ ]*[a-f0-9]+: 1b 3d cd 00 20 00 sbb 0x2000cd\(%rip\),%edi # 2002c0 <.*>
++[ ]*[a-f0-9]+: 2b 2d c7 00 20 00 sub 0x2000c7\(%rip\),%ebp # 2002c0 <.*>
++[ ]*[a-f0-9]+: 44 33 05 c0 00 20 00 xor 0x2000c0\(%rip\),%r8d # 2002c0 <.*>
++[ ]*[a-f0-9]+: 44 85 3d b9 00 20 00 test %r15d,0x2000b9\(%rip\) # 2002c0 <.*>
++[ ]*[a-f0-9]+: 48 13 05 b2 00 20 00 adc 0x2000b2\(%rip\),%rax # 2002c0 <.*>
++[ ]*[a-f0-9]+: 48 03 1d ab 00 20 00 add 0x2000ab\(%rip\),%rbx # 2002c0 <.*>
++[ ]*[a-f0-9]+: 48 23 0d a4 00 20 00 and 0x2000a4\(%rip\),%rcx # 2002c0 <.*>
++[ ]*[a-f0-9]+: 48 3b 15 9d 00 20 00 cmp 0x20009d\(%rip\),%rdx # 2002c0 <.*>
++[ ]*[a-f0-9]+: 48 0b 3d 96 00 20 00 or 0x200096\(%rip\),%rdi # 2002c0 <.*>
++[ ]*[a-f0-9]+: 48 1b 35 8f 00 20 00 sbb 0x20008f\(%rip\),%rsi # 2002c0 <.*>
++[ ]*[a-f0-9]+: 48 2b 2d 88 00 20 00 sub 0x200088\(%rip\),%rbp # 2002c0 <.*>
++[ ]*[a-f0-9]+: 4c 33 05 81 00 20 00 xor 0x200081\(%rip\),%r8 # 2002c0 <.*>
++[ ]*[a-f0-9]+: 4c 85 3d 7a 00 20 00 test %r15,0x20007a\(%rip\) # 2002c0 <.*>
+ #pass
+diff --git a/ld/testsuite/ld-x86-64/mov1a.d b/ld/testsuite/ld-x86-64/mov1a.d
+index 4ac6d7e..4c26d6f 100644
+--- a/ld/testsuite/ld-x86-64/mov1a.d
++++ b/ld/testsuite/ld-x86-64/mov1a.d
+@@ -9,7 +9,7 @@
+ Disassembly of section .text:
+
+ #...
+-[ ]*[a-f0-9]+: 48 8b 05 ([0-9a-f]{2} ){4} * mov 0x[a-f0-9]+\(%rip\),%rax # [a-f0-9]+ <_DYNAMIC\+0x[a-f0-9]+>
+-[ ]*[a-f0-9]+: 48 8b 05 ([0-9a-f]{2} ){4} * mov 0x[a-f0-9]+\(%rip\),%rax # [a-f0-9]+ <_DYNAMIC\+0x[a-f0-9]+>
+-[ ]*[a-f0-9]+: 48 8b 05 ([0-9a-f]{2} ){4} * mov 0x[a-f0-9]+\(%rip\),%rax # [a-f0-9]+ <_DYNAMIC\+0x[a-f0-9]+>
++[ ]*[a-f0-9]+: 48 8b 05 ([0-9a-f]{2} ){4} * mov 0x[a-f0-9]+\(%rip\),%rax # [a-f0-9]+ <.*>
++[ ]*[a-f0-9]+: 48 8b 05 ([0-9a-f]{2} ){4} * mov 0x[a-f0-9]+\(%rip\),%rax # [a-f0-9]+ <.*>
++[ ]*[a-f0-9]+: 48 8b 05 ([0-9a-f]{2} ){4} * mov 0x[a-f0-9]+\(%rip\),%rax # [a-f0-9]+ <.*>
+ #pass
+diff --git a/ld/testsuite/ld-x86-64/mov1b.d b/ld/testsuite/ld-x86-64/mov1b.d
+index 7421853..51a9190 100644
+--- a/ld/testsuite/ld-x86-64/mov1b.d
++++ b/ld/testsuite/ld-x86-64/mov1b.d
+@@ -9,7 +9,7 @@
+ Disassembly of section .text:
+
+ #...
+-[ ]*[a-f0-9]+: 48 8b 05 ([0-9a-f]{2} ){4} * mov 0x[a-f0-9]+\(%rip\),%rax # [a-f0-9]+ <_DYNAMIC\+0x[a-f0-9]+>
++[ ]*[a-f0-9]+: 48 8b 05 ([0-9a-f]{2} ){4} * mov 0x[a-f0-9]+\(%rip\),%rax # [a-f0-9]+ <.*>
+ [ ]*[a-f0-9]+: 48 c7 c0 00 00 00 00 * mov \$0x0,%rax
+ [ ]*[a-f0-9]+: 48 c7 c0 00 00 00 00 * mov \$0x0,%rax
+ #pass
+diff --git a/ld/testsuite/ld-x86-64/mov1c.d b/ld/testsuite/ld-x86-64/mov1c.d
+index bb7bab1..be3337a 100644
+--- a/ld/testsuite/ld-x86-64/mov1c.d
++++ b/ld/testsuite/ld-x86-64/mov1c.d
+@@ -9,7 +9,7 @@
+ Disassembly of section .text:
+
+ #...
+-[ ]*[a-f0-9]+: 48 8b 05 ([0-9a-f]{2} ){4} * mov 0x[a-f0-9]+\(%rip\),%rax # [a-f0-9]+ <_DYNAMIC\+0x[a-f0-9]+>
+-[ ]*[a-f0-9]+: 48 8b 05 ([0-9a-f]{2} ){4} * mov 0x[a-f0-9]+\(%rip\),%rax # [a-f0-9]+ <_DYNAMIC\+0x[a-f0-9]+>
+-[ ]*[a-f0-9]+: 48 8b 05 ([0-9a-f]{2} ){4} * mov 0x[a-f0-9]+\(%rip\),%rax # [a-f0-9]+ <_DYNAMIC\+0x[a-f0-9]+>
++[ ]*[a-f0-9]+: 48 8b 05 ([0-9a-f]{2} ){4} * mov 0x[a-f0-9]+\(%rip\),%rax # [a-f0-9]+ <.*>
++[ ]*[a-f0-9]+: 48 8b 05 ([0-9a-f]{2} ){4} * mov 0x[a-f0-9]+\(%rip\),%rax # [a-f0-9]+ <.*>
++[ ]*[a-f0-9]+: 48 8b 05 ([0-9a-f]{2} ){4} * mov 0x[a-f0-9]+\(%rip\),%rax # [a-f0-9]+ <.*>
+ #pass
+diff --git a/ld/testsuite/ld-x86-64/mov1d.d b/ld/testsuite/ld-x86-64/mov1d.d
+index 7cdab0c..720b150 100644
+--- a/ld/testsuite/ld-x86-64/mov1d.d
++++ b/ld/testsuite/ld-x86-64/mov1d.d
+@@ -9,7 +9,7 @@
+ Disassembly of section .text:
+
+ #...
+-[ ]*[a-f0-9]+: 48 8b 05 ([0-9a-f]{2} ){4} * mov 0x[a-f0-9]+\(%rip\),%rax # [a-f0-9]+ <_DYNAMIC\+0x[a-f0-9]+>
++[ ]*[a-f0-9]+: 48 8b 05 ([0-9a-f]{2} ){4} * mov 0x[a-f0-9]+\(%rip\),%rax # [a-f0-9]+ <.*>
+ [ ]*[a-f0-9]+: 40 c7 c0 00 00 00 00 * rex mov \$0x0,%eax
+ [ ]*[a-f0-9]+: 40 c7 c0 00 00 00 00 * rex mov \$0x0,%eax
+ #pass
+diff --git a/ld/testsuite/ld-x86-64/mov2a.d b/ld/testsuite/ld-x86-64/mov2a.d
+index aaf5707..09f8790 100644
+--- a/ld/testsuite/ld-x86-64/mov2a.d
++++ b/ld/testsuite/ld-x86-64/mov2a.d
+@@ -9,7 +9,7 @@
+ Disassembly of section .text:
+
+ #...
+-[ ]*[a-f0-9]+: 48 8b 05 ([0-9a-f]{2} ){4} * mov 0x[a-f0-9]+\(%rip\),%rax # [a-f0-9]+ <_DYNAMIC\+0x[a-f0-9]+>
+-[ ]*[a-f0-9]+: 48 8b 05 ([0-9a-f]{2} ){4} * mov 0x[a-f0-9]+\(%rip\),%rax # [a-f0-9]+ <_DYNAMIC\+0x[a-f0-9]+>
+-[ ]*[a-f0-9]+: 48 8b 05 ([0-9a-f]{2} ){4} * mov 0x[a-f0-9]+\(%rip\),%rax # [a-f0-9]+ <_DYNAMIC\+0x[a-f0-9]+>
++[ ]*[a-f0-9]+: 48 8b 05 ([0-9a-f]{2} ){4} * mov 0x[a-f0-9]+\(%rip\),%rax # [a-f0-9]+ <.*>
++[ ]*[a-f0-9]+: 48 8b 05 ([0-9a-f]{2} ){4} * mov 0x[a-f0-9]+\(%rip\),%rax # [a-f0-9]+ <.*>
++[ ]*[a-f0-9]+: 48 8b 05 ([0-9a-f]{2} ){4} * mov 0x[a-f0-9]+\(%rip\),%rax # [a-f0-9]+ <.*>
+ #pass
+diff --git a/ld/testsuite/ld-x86-64/mov2b.d b/ld/testsuite/ld-x86-64/mov2b.d
+index ee1b308..41d4b95 100644
+--- a/ld/testsuite/ld-x86-64/mov2b.d
++++ b/ld/testsuite/ld-x86-64/mov2b.d
+@@ -9,7 +9,7 @@
+ Disassembly of section .text:
+
+ #...
+-[ ]*[a-f0-9]+: 48 8b 05 ([0-9a-f]{2} ){4} * mov 0x[a-f0-9]+\(%rip\),%rax # [a-f0-9]+ <_DYNAMIC\+0x[a-f0-9]+>
+-[ ]*[a-f0-9]+: 48 8b 05 ([0-9a-f]{2} ){4} * mov 0x[a-f0-9]+\(%rip\),%rax # [a-f0-9]+ <_DYNAMIC\+0x[a-f0-9]+>
+-[ ]*[a-f0-9]+: 48 8b 05 ([0-9a-f]{2} ){4} * mov 0x[a-f0-9]+\(%rip\),%rax # [a-f0-9]+ <_DYNAMIC\+0x[a-f0-9]+>
++[ ]*[a-f0-9]+: 48 8b 05 ([0-9a-f]{2} ){4} * mov 0x[a-f0-9]+\(%rip\),%rax # [a-f0-9]+ <.*>
++[ ]*[a-f0-9]+: 48 8b 05 ([0-9a-f]{2} ){4} * mov 0x[a-f0-9]+\(%rip\),%rax # [a-f0-9]+ <.*>
++[ ]*[a-f0-9]+: 48 8b 05 ([0-9a-f]{2} ){4} * mov 0x[a-f0-9]+\(%rip\),%rax # [a-f0-9]+ <.*>
+ #pass
+diff --git a/ld/testsuite/ld-x86-64/mov2c.d b/ld/testsuite/ld-x86-64/mov2c.d
+index 8991121..766584c 100644
+--- a/ld/testsuite/ld-x86-64/mov2c.d
++++ b/ld/testsuite/ld-x86-64/mov2c.d
+@@ -9,7 +9,7 @@
+ Disassembly of section .text:
+
+ #...
+-[ ]*[a-f0-9]+: 48 8b 05 ([0-9a-f]{2} ){4} * mov 0x[a-f0-9]+\(%rip\),%rax # [a-f0-9]+ <_DYNAMIC\+0x[a-f0-9]+>
+-[ ]*[a-f0-9]+: 48 8b 05 ([0-9a-f]{2} ){4} * mov 0x[a-f0-9]+\(%rip\),%rax # [a-f0-9]+ <_DYNAMIC\+0x[a-f0-9]+>
+-[ ]*[a-f0-9]+: 48 8b 05 ([0-9a-f]{2} ){4} * mov 0x[a-f0-9]+\(%rip\),%rax # [a-f0-9]+ <_DYNAMIC\+0x[a-f0-9]+>
++[ ]*[a-f0-9]+: 48 8b 05 ([0-9a-f]{2} ){4} * mov 0x[a-f0-9]+\(%rip\),%rax # [a-f0-9]+ <.*>
++[ ]*[a-f0-9]+: 48 8b 05 ([0-9a-f]{2} ){4} * mov 0x[a-f0-9]+\(%rip\),%rax # [a-f0-9]+ <.*>
++[ ]*[a-f0-9]+: 48 8b 05 ([0-9a-f]{2} ){4} * mov 0x[a-f0-9]+\(%rip\),%rax # [a-f0-9]+ <.*>
+ #pass
+diff --git a/ld/testsuite/ld-x86-64/mov2d.d b/ld/testsuite/ld-x86-64/mov2d.d
+index 744028e..6b93947 100644
+--- a/ld/testsuite/ld-x86-64/mov2d.d
++++ b/ld/testsuite/ld-x86-64/mov2d.d
+@@ -9,7 +9,7 @@
+ Disassembly of section .text:
+
+ #...
+-[ ]*[a-f0-9]+: 48 8b 05 ([0-9a-f]{2} ){4} * mov 0x[a-f0-9]+\(%rip\),%rax # [a-f0-9]+ <_DYNAMIC\+0x[a-f0-9]+>
+-[ ]*[a-f0-9]+: 48 8b 05 ([0-9a-f]{2} ){4} * mov 0x[a-f0-9]+\(%rip\),%rax # [a-f0-9]+ <_DYNAMIC\+0x[a-f0-9]+>
+-[ ]*[a-f0-9]+: 48 8b 05 ([0-9a-f]{2} ){4} * mov 0x[a-f0-9]+\(%rip\),%rax # [a-f0-9]+ <_DYNAMIC\+0x[a-f0-9]+>
++[ ]*[a-f0-9]+: 48 8b 05 ([0-9a-f]{2} ){4} * mov 0x[a-f0-9]+\(%rip\),%rax # [a-f0-9]+ <.*>
++[ ]*[a-f0-9]+: 48 8b 05 ([0-9a-f]{2} ){4} * mov 0x[a-f0-9]+\(%rip\),%rax # [a-f0-9]+ <.*>
++[ ]*[a-f0-9]+: 48 8b 05 ([0-9a-f]{2} ){4} * mov 0x[a-f0-9]+\(%rip\),%rax # [a-f0-9]+ <.*>
+ #pass
+diff --git a/ld/testsuite/ld-x86-64/mpx3.dd b/ld/testsuite/ld-x86-64/mpx3.dd
+index eb529f4..d5d8049 100644
+--- a/ld/testsuite/ld-x86-64/mpx3.dd
++++ b/ld/testsuite/ld-x86-64/mpx3.dd
+@@ -8,13 +8,13 @@ Disassembly of section .plt:
+ [ ]*[a-f0-9]+: f2 ff ([0-9a-f]{2} ){5} bnd jmpq \*0x[a-f0-9]+\(%rip\) # [a-f0-9]+ <_GLOBAL_OFFSET_TABLE_\+0x10>
+ [ ]*[a-f0-9]+: 0f 1f 00 nopl \(%rax\)
+ [ ]*[a-f0-9]+: 68 00 00 00 00 pushq \$0x0
+-[ ]*[a-f0-9]+: f2 e9 ([0-9a-f]{2} ){4} bnd jmpq [a-f0-9]+ <call1@plt-0x20>
++[ ]*[a-f0-9]+: f2 e9 ([0-9a-f]{2} ){4} bnd jmpq [a-f0-9]+ <.plt>
+ [ ]*[a-f0-9]+: 0f 1f 44 00 00 nopl 0x0\(%rax,%rax,1\)
+
+ Disassembly of section .plt.bnd:
+
+ 0+[a-f0-9]+ <call1@plt>:
+-[ ]*[a-f0-9]+: f2 ff ([0-9a-f]{2} ){5} bnd jmpq \*0x[a-f0-9]+\(%rip\) # [a-f0-9]+ <_GLOBAL_OFFSET_TABLE_\+0x18>
++[ ]*[a-f0-9]+: f2 ff ([0-9a-f]{2} ){5} bnd jmpq \*0x[a-f0-9]+\(%rip\) # [a-f0-9]+ <call1>
+ [ ]*[a-f0-9]+: 90 nop
+
+ Disassembly of section .text:
+@@ -22,7 +22,7 @@ Disassembly of section .text:
+ 0+[a-f0-9]+ <_start>:
+ [ ]*[a-f0-9]+: bf ([0-9a-f]{2} ){4} mov \$0x[a-f0-9]+,%edi
+ [ ]*[a-f0-9]+: f2 ff d7 bnd callq \*%rdi
+-[ ]*[a-f0-9]+: 48 8b ([0-9a-f]{2} ){5} mov 0x[a-f0-9]+\(%rip\),%rdi # [a-f0-9]+ <func>
++[ ]*[a-f0-9]+: 48 8b ([0-9a-f]{2} ){5} mov 0x[a-f0-9]+\(%rip\),%rdi # [a-f0-9]+ <call2>
+ [ ]*[a-f0-9]+: f2 ff d7 bnd callq \*%rdi
+ [ ]*[a-f0-9]+: c3 retq
+ #pass
+diff --git a/ld/testsuite/ld-x86-64/mpx4.dd b/ld/testsuite/ld-x86-64/mpx4.dd
+index 0cf0f75..1bcb13b 100644
+--- a/ld/testsuite/ld-x86-64/mpx4.dd
++++ b/ld/testsuite/ld-x86-64/mpx4.dd
+@@ -8,13 +8,13 @@ Disassembly of section .plt:
+ [ ]*[a-f0-9]+: f2 ff 25 43 01 20 00 bnd jmpq \*0x200143\(%rip\) # 6003b0 <_GLOBAL_OFFSET_TABLE_\+0x10>
+ [ ]*[a-f0-9]+: 0f 1f 00 nopl \(%rax\)
+ [ ]*[a-f0-9]+: 68 00 00 00 00 pushq \$0x0
+-[ ]*[a-f0-9]+: f2 e9 e5 ff ff ff bnd jmpq 400260 <call1@plt-0x20>
++[ ]*[a-f0-9]+: f2 e9 e5 ff ff ff bnd jmpq 400260 <.plt>
+ [ ]*[a-f0-9]+: 0f 1f 44 00 00 nopl 0x0\(%rax,%rax,1\)
+
+ Disassembly of section .plt.bnd:
+
+ 0+400280 <call1@plt>:
+-[ ]*[a-f0-9]+: f2 ff 25 31 01 20 00 bnd jmpq \*0x200131\(%rip\) # 6003b8 <_GLOBAL_OFFSET_TABLE_\+0x18>
++[ ]*[a-f0-9]+: f2 ff 25 31 01 20 00 bnd jmpq \*0x200131\(%rip\) # 6003b8 <call1>
+ [ ]*[a-f0-9]+: 90 nop
+
+ Disassembly of section .text:
+diff --git a/ld/testsuite/ld-x86-64/no-plt-1a.dd b/ld/testsuite/ld-x86-64/no-plt-1a.dd
+index 7c2f5b2..a8445c7 100644
+--- a/ld/testsuite/ld-x86-64/no-plt-1a.dd
++++ b/ld/testsuite/ld-x86-64/no-plt-1a.dd
+@@ -21,8 +21,8 @@ Disassembly of section .text:
+ +[a-f0-9]+: 75 11 jne [0-9a-f]+ <check\+0x[0-9a-f]+>
+ +[a-f0-9]+: 48 8d 3d ([0-9a-f]{2} ){4}[ ]+lea 0x[a-f0-9]+\(%rip\),%rdi +# [a-f0-9]+.*
+ +[a-f0-9]+: 48 83 c4 08 add \$0x8,%rsp
+- +[a-f0-9]+: ff 25 ([0-9a-f]{2} ){4}[ ]+jmpq \*0x[0-9a-f]+\(%rip\) +# [0-9a-f]+ <_DYNAMIC\+0x[0-9a-f]+>
+- +[a-f0-9]+: ff 15 ([0-9a-f]{2} ){4}[ ]+callq \*0x[0-9a-f]+\(%rip\) +# [0-9a-f]+ <_DYNAMIC\+0x[0-9a-f]+>
++ +[a-f0-9]+: ff 25 ([0-9a-f]{2} ){4}[ ]+jmpq \*0x[0-9a-f]+\(%rip\) +# [0-9a-f]+ <.*>
++ +[a-f0-9]+: ff 15 ([0-9a-f]{2} ){4}[ ]+callq \*0x[0-9a-f]+\(%rip\) +# [0-9a-f]+ <.*>
+ #...
+ [0-9a-f]+ <get_func>:
+ +[a-f0-9]+: 4(0|8) c7 c0 ([0-9a-f]{2} ){4}[ ]+(rex |)mov +\$0x[0-9a-f]+,%(e|r)ax
+diff --git a/ld/testsuite/ld-x86-64/no-plt-1b.dd b/ld/testsuite/ld-x86-64/no-plt-1b.dd
+index 13d24b8..c21e912 100644
+--- a/ld/testsuite/ld-x86-64/no-plt-1b.dd
++++ b/ld/testsuite/ld-x86-64/no-plt-1b.dd
+@@ -8,19 +8,19 @@ Disassembly of section .text:
+ #...
+ [0-9a-f]+ <check>:
+ +[a-f0-9]+: 48 83 ec 08 sub \$0x8,%rsp
+- +[a-f0-9]+: ff 15 ([0-9a-f]{2} ){4}[ ]+callq \*0x[0-9a-f]+\(%rip\) +# [0-9a-f]+ <_DYNAMIC\+0x[0-9a-f]+>
+- +[a-f0-9]+: 48 3b 05 ([0-9a-f]{2} ){4}[ ]+cmp 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <_DYNAMIC\+0x[0-9a-f]+>
++ +[a-f0-9]+: ff 15 ([0-9a-f]{2} ){4}[ ]+callq \*0x[0-9a-f]+\(%rip\) +# [0-9a-f]+ <.*>
++ +[a-f0-9]+: 48 3b 05 ([0-9a-f]{2} ){4}[ ]+cmp 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <.*>
+ +[a-f0-9]+: 75 34 jne [0-9a-f]+ <check\+0x[0-9a-f]+>
+ +[a-f0-9]+: 4(0|8) 39 05 ([0-9a-f]{2} ){4}[ ]+(rex |)cmp +%(e|r)ax,0x[0-9a-f]+\(%rip\) +# [a-f0-9]+ <.*>
+ +[a-f0-9]+: 75 2b jne [0-9a-f]+ <check\+0x[0-9a-f]+>
+- +[a-f0-9]+: ff 15 ([0-9a-f]{2} ){4}[ ]+callq \*0x[0-9a-f]+\(%rip\) +# [0-9a-f]+ <_DYNAMIC\+0x[0-9a-f]+>
++ +[a-f0-9]+: ff 15 ([0-9a-f]{2} ){4}[ ]+callq \*0x[0-9a-f]+\(%rip\) +# [0-9a-f]+ <.*>
+ +[a-f0-9]+: 3d 78 56 34 12 cmp \$0x12345678,%eax
+ +[a-f0-9]+: 75 1e jne [0-9a-f]+ <check\+0x[0-9a-f]+>
+- +[a-f0-9]+: ff 15 ([0-9a-f]{2} ){4}[ ]+callq \*0x[0-9a-f]+\(%rip\) +# [0-9a-f]+ <_DYNAMIC\+0x[0-9a-f]+>
++ +[a-f0-9]+: ff 15 ([0-9a-f]{2} ){4}[ ]+callq \*0x[0-9a-f]+\(%rip\) +# [0-9a-f]+ <.*>
+ +[a-f0-9]+: 3d 78 56 34 12 cmp \$0x12345678,%eax
+ +[a-f0-9]+: 75 11 jne [0-9a-f]+ <check\+0x[0-9a-f]+>
+ +[a-f0-9]+: 48 8d 3d ([0-9a-f]{2} ){4}[ ]+lea 0x[a-f0-9]+\(%rip\),%rdi +# [a-f0-9]+.*
+ +[a-f0-9]+: 48 83 c4 08 add \$0x8,%rsp
+- +[a-f0-9]+: ff 25 ([0-9a-f]{2} ){4}[ ]+jmpq \*0x[0-9a-f]+\(%rip\) +# [0-9a-f]+ <_DYNAMIC\+0x[0-9a-f]+>
+- +[a-f0-9]+: ff 15 ([0-9a-f]{2} ){4}[ ]+callq \*0x[0-9a-f]+\(%rip\) +# [0-9a-f]+ <_DYNAMIC\+0x[0-9a-f]+>
++ +[a-f0-9]+: ff 25 ([0-9a-f]{2} ){4}[ ]+jmpq \*0x[0-9a-f]+\(%rip\) +# [0-9a-f]+ <.*>
++ +[a-f0-9]+: ff 15 ([0-9a-f]{2} ){4}[ ]+callq \*0x[0-9a-f]+\(%rip\) +# [0-9a-f]+ <.*>
+ #pass
+diff --git a/ld/testsuite/ld-x86-64/no-plt-1c.dd b/ld/testsuite/ld-x86-64/no-plt-1c.dd
+index 75287c9..b41246b 100644
+--- a/ld/testsuite/ld-x86-64/no-plt-1c.dd
++++ b/ld/testsuite/ld-x86-64/no-plt-1c.dd
+@@ -8,7 +8,7 @@ Disassembly of section .text:
+ #...
+ [0-9a-f]+ <check>:
+ +[a-f0-9]+: 48 83 ec 08 sub \$0x8,%rsp
+- +[a-f0-9]+: ff 15 ([0-9a-f]{2} ){4}[ ]+callq \*0x[0-9a-f]+\(%rip\) +# [0-9a-f]+ <_DYNAMIC\+0x[0-9a-f]+>
++ +[a-f0-9]+: ff 15 ([0-9a-f]{2} ){4}[ ]+callq \*0x[0-9a-f]+\(%rip\) +# [0-9a-f]+ <.*>
+ +[a-f0-9]+: 48 81 f8 ([0-9a-f]{2} ){4}[ ]+cmp \$0x[0-9a-f]+,%rax
+ +[a-f0-9]+: 75 34 jne [0-9a-f]+ <check\+0x[0-9a-f]+>
+ +[a-f0-9]+: 4(0|8) 39 05 ([0-9a-f]{2} ){4}[ ]+(rex |)cmp +%(e|r)ax,0x[0-9a-f]+\(%rip\) +# [a-f0-9]+ <.*>
+@@ -16,11 +16,11 @@ Disassembly of section .text:
+ +[a-f0-9]+: 67 e8 ([0-9a-f]{2} ){4}[ ]+addr32 callq [0-9a-f]+ <func>
+ +[a-f0-9]+: 3d 78 56 34 12 cmp \$0x12345678,%eax
+ +[a-f0-9]+: 75 1e jne [0-9a-f]+ <check\+0x[0-9a-f]+>
+- +[a-f0-9]+: ff 15 ([0-9a-f]{2} ){4}[ ]+callq \*0x[0-9a-f]+\(%rip\) +# [0-9a-f]+ <_DYNAMIC\+0x[0-9a-f]+>
++ +[a-f0-9]+: ff 15 ([0-9a-f]{2} ){4}[ ]+callq \*0x[0-9a-f]+\(%rip\) +# [0-9a-f]+ <.*>
+ +[a-f0-9]+: 3d 78 56 34 12 cmp \$0x12345678,%eax
+ +[a-f0-9]+: 75 11 jne [0-9a-f]+ <check\+0x[0-9a-f]+>
+ +[a-f0-9]+: 48 8d 3d ([0-9a-f]{2} ){4}[ ]+lea 0x[a-f0-9]+\(%rip\),%rdi +# [a-f0-9]+.*
+ +[a-f0-9]+: 48 83 c4 08 add \$0x8,%rsp
+- +[a-f0-9]+: ff 25 ([0-9a-f]{2} ){4}[ ]+jmpq \*0x[0-9a-f]+\(%rip\) +# [0-9a-f]+ <_DYNAMIC\+0x[0-9a-f]+>
+- +[a-f0-9]+: ff 15 ([0-9a-f]{2} ){4}[ ]+callq \*0x[0-9a-f]+\(%rip\) +# [0-9a-f]+ <_DYNAMIC\+0x[0-9a-f]+>
++ +[a-f0-9]+: ff 25 ([0-9a-f]{2} ){4}[ ]+jmpq \*0x[0-9a-f]+\(%rip\) +# [0-9a-f]+ <.*>
++ +[a-f0-9]+: ff 15 ([0-9a-f]{2} ){4}[ ]+callq \*0x[0-9a-f]+\(%rip\) +# [0-9a-f]+ <.*>
+ #pass
+diff --git a/ld/testsuite/ld-x86-64/no-plt-1e.dd b/ld/testsuite/ld-x86-64/no-plt-1e.dd
+index 0126abe..f3b07ab 100644
+--- a/ld/testsuite/ld-x86-64/no-plt-1e.dd
++++ b/ld/testsuite/ld-x86-64/no-plt-1e.dd
+@@ -9,7 +9,7 @@ Disassembly of section .text:
+ [0-9a-f]+ <check>:
+ +[a-f0-9]+: 48 83 ec 08 sub \$0x8,%rsp
+ +[a-f0-9]+: 67 e8 ([0-9a-f]{2} ){4}[ ]+addr32 callq [0-9a-f]+ <get_func>
+- +[a-f0-9]+: 48 3b 05 ([0-9a-f]{2} ){4}[ ]+cmp 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <_DYNAMIC\+0x[0-9a-f]+>
++ +[a-f0-9]+: 48 3b 05 ([0-9a-f]{2} ){4}[ ]+cmp 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <.*>
+ +[a-f0-9]+: 75 34 jne [0-9a-f]+ <check\+0x[0-9a-f]+>
+ +[a-f0-9]+: 4(0|8) 39 05 ([0-9a-f]{2} ){4}[ ]+(rex |)cmp +%(e|r)ax,0x[0-9a-f]+\(%rip\) +# [a-f0-9]+ <func_p>
+ +[a-f0-9]+: 75 2b jne [0-9a-f]+ <check\+0x[0-9a-f]+>
+@@ -21,8 +21,8 @@ Disassembly of section .text:
+ +[a-f0-9]+: 75 11 jne [0-9a-f]+ <check\+0x[0-9a-f]+>
+ +[a-f0-9]+: 48 8d 3d ([0-9a-f]{2} ){4}[ ]+lea 0x[a-f0-9]+\(%rip\),%rdi +# [a-f0-9]+.*
+ +[a-f0-9]+: 48 83 c4 08 add \$0x8,%rsp
+- +[a-f0-9]+: ff 25 ([0-9a-f]{2} ){4}[ ]+jmpq \*0x[0-9a-f]+\(%rip\) +# [0-9a-f]+ <_DYNAMIC\+0x[0-9a-f]+>
+- +[a-f0-9]+: ff 15 ([0-9a-f]{2} ){4}[ ]+callq \*0x[0-9a-f]+\(%rip\) +# [0-9a-f]+ <_DYNAMIC\+0x[0-9a-f]+>
++ +[a-f0-9]+: ff 25 ([0-9a-f]{2} ){4}[ ]+jmpq \*0x[0-9a-f]+\(%rip\) +# [0-9a-f]+ <.*>
++ +[a-f0-9]+: ff 15 ([0-9a-f]{2} ){4}[ ]+callq \*0x[0-9a-f]+\(%rip\) +# [0-9a-f]+ <.*>
+ #...
+ [0-9a-f]+ <get_func>:
+ +[a-f0-9]+: 48 8d 05 ([0-9a-f]{2} ){4}[ ]+lea -0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <func>
+diff --git a/ld/testsuite/ld-x86-64/no-plt-1f.dd b/ld/testsuite/ld-x86-64/no-plt-1f.dd
+index 13d24b8..c21e912 100644
+--- a/ld/testsuite/ld-x86-64/no-plt-1f.dd
++++ b/ld/testsuite/ld-x86-64/no-plt-1f.dd
+@@ -8,19 +8,19 @@ Disassembly of section .text:
+ #...
+ [0-9a-f]+ <check>:
+ +[a-f0-9]+: 48 83 ec 08 sub \$0x8,%rsp
+- +[a-f0-9]+: ff 15 ([0-9a-f]{2} ){4}[ ]+callq \*0x[0-9a-f]+\(%rip\) +# [0-9a-f]+ <_DYNAMIC\+0x[0-9a-f]+>
+- +[a-f0-9]+: 48 3b 05 ([0-9a-f]{2} ){4}[ ]+cmp 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <_DYNAMIC\+0x[0-9a-f]+>
++ +[a-f0-9]+: ff 15 ([0-9a-f]{2} ){4}[ ]+callq \*0x[0-9a-f]+\(%rip\) +# [0-9a-f]+ <.*>
++ +[a-f0-9]+: 48 3b 05 ([0-9a-f]{2} ){4}[ ]+cmp 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <.*>
+ +[a-f0-9]+: 75 34 jne [0-9a-f]+ <check\+0x[0-9a-f]+>
+ +[a-f0-9]+: 4(0|8) 39 05 ([0-9a-f]{2} ){4}[ ]+(rex |)cmp +%(e|r)ax,0x[0-9a-f]+\(%rip\) +# [a-f0-9]+ <.*>
+ +[a-f0-9]+: 75 2b jne [0-9a-f]+ <check\+0x[0-9a-f]+>
+- +[a-f0-9]+: ff 15 ([0-9a-f]{2} ){4}[ ]+callq \*0x[0-9a-f]+\(%rip\) +# [0-9a-f]+ <_DYNAMIC\+0x[0-9a-f]+>
++ +[a-f0-9]+: ff 15 ([0-9a-f]{2} ){4}[ ]+callq \*0x[0-9a-f]+\(%rip\) +# [0-9a-f]+ <.*>
+ +[a-f0-9]+: 3d 78 56 34 12 cmp \$0x12345678,%eax
+ +[a-f0-9]+: 75 1e jne [0-9a-f]+ <check\+0x[0-9a-f]+>
+- +[a-f0-9]+: ff 15 ([0-9a-f]{2} ){4}[ ]+callq \*0x[0-9a-f]+\(%rip\) +# [0-9a-f]+ <_DYNAMIC\+0x[0-9a-f]+>
++ +[a-f0-9]+: ff 15 ([0-9a-f]{2} ){4}[ ]+callq \*0x[0-9a-f]+\(%rip\) +# [0-9a-f]+ <.*>
+ +[a-f0-9]+: 3d 78 56 34 12 cmp \$0x12345678,%eax
+ +[a-f0-9]+: 75 11 jne [0-9a-f]+ <check\+0x[0-9a-f]+>
+ +[a-f0-9]+: 48 8d 3d ([0-9a-f]{2} ){4}[ ]+lea 0x[a-f0-9]+\(%rip\),%rdi +# [a-f0-9]+.*
+ +[a-f0-9]+: 48 83 c4 08 add \$0x8,%rsp
+- +[a-f0-9]+: ff 25 ([0-9a-f]{2} ){4}[ ]+jmpq \*0x[0-9a-f]+\(%rip\) +# [0-9a-f]+ <_DYNAMIC\+0x[0-9a-f]+>
+- +[a-f0-9]+: ff 15 ([0-9a-f]{2} ){4}[ ]+callq \*0x[0-9a-f]+\(%rip\) +# [0-9a-f]+ <_DYNAMIC\+0x[0-9a-f]+>
++ +[a-f0-9]+: ff 25 ([0-9a-f]{2} ){4}[ ]+jmpq \*0x[0-9a-f]+\(%rip\) +# [0-9a-f]+ <.*>
++ +[a-f0-9]+: ff 15 ([0-9a-f]{2} ){4}[ ]+callq \*0x[0-9a-f]+\(%rip\) +# [0-9a-f]+ <.*>
+ #pass
+diff --git a/ld/testsuite/ld-x86-64/no-plt-1g.dd b/ld/testsuite/ld-x86-64/no-plt-1g.dd
+index 5a3dd17..ca4eb59 100644
+--- a/ld/testsuite/ld-x86-64/no-plt-1g.dd
++++ b/ld/testsuite/ld-x86-64/no-plt-1g.dd
+@@ -8,19 +8,19 @@ Disassembly of section .text:
+ #...
+ [0-9a-f]+ <check>:
+ +[a-f0-9]+: 48 83 ec 08 sub \$0x8,%rsp
+- +[a-f0-9]+: ff 15 ([0-9a-f]{2} ){4}[ ]+callq \*0x[0-9a-f]+\(%rip\) +# [0-9a-f]+ <_DYNAMIC\+0x[0-9a-f]+>
+- +[a-f0-9]+: 48 3b 05 ([0-9a-f]{2} ){4}[ ]+cmp 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <_DYNAMIC\+0x[0-9a-f]+>
++ +[a-f0-9]+: ff 15 ([0-9a-f]{2} ){4}[ ]+callq \*0x[0-9a-f]+\(%rip\) +# [0-9a-f]+ <.*>
++ +[a-f0-9]+: 48 3b 05 ([0-9a-f]{2} ){4}[ ]+cmp 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <.*>
+ +[a-f0-9]+: 75 34 jne [0-9a-f]+ <check\+0x[0-9a-f]+>
+ +[a-f0-9]+: 4(0|8) 39 05 ([0-9a-f]{2} ){4}[ ]+(rex |)cmp +%(e|r)ax,0x[0-9a-f]+\(%rip\) +# [a-f0-9]+ <.*>
+ +[a-f0-9]+: 75 2b jne [0-9a-f]+ <check\+0x[0-9a-f]+>
+ +[a-f0-9]+: 67 e8 ([0-9a-f]{2} ){4}[ ]+addr32 callq [0-9a-f]+ <func>
+ +[a-f0-9]+: 3d 78 56 34 12 cmp \$0x12345678,%eax
+ +[a-f0-9]+: 75 1e jne [0-9a-f]+ <check\+0x[0-9a-f]+>
+- +[a-f0-9]+: ff 15 ([0-9a-f]{2} ){4}[ ]+callq \*0x[0-9a-f]+\(%rip\) +# [0-9a-f]+ <_DYNAMIC\+0x[0-9a-f]+>
++ +[a-f0-9]+: ff 15 ([0-9a-f]{2} ){4}[ ]+callq \*0x[0-9a-f]+\(%rip\) +# [0-9a-f]+ <.*>
+ +[a-f0-9]+: 3d 78 56 34 12 cmp \$0x12345678,%eax
+ +[a-f0-9]+: 75 11 jne [0-9a-f]+ <check\+0x[0-9a-f]+>
+ +[a-f0-9]+: 48 8d 3d ([0-9a-f]{2} ){4}[ ]+lea 0x[a-f0-9]+\(%rip\),%rdi +# [a-f0-9]+.*
+ +[a-f0-9]+: 48 83 c4 08 add \$0x8,%rsp
+- +[a-f0-9]+: ff 25 ([0-9a-f]{2} ){4}[ ]+jmpq \*0x[0-9a-f]+\(%rip\) +# [0-9a-f]+ <_DYNAMIC\+0x[0-9a-f]+>
+- +[a-f0-9]+: ff 15 ([0-9a-f]{2} ){4}[ ]+callq \*0x[0-9a-f]+\(%rip\) +# [0-9a-f]+ <_DYNAMIC\+0x[0-9a-f]+>
++ +[a-f0-9]+: ff 25 ([0-9a-f]{2} ){4}[ ]+jmpq \*0x[0-9a-f]+\(%rip\) +# [0-9a-f]+ <.*>
++ +[a-f0-9]+: ff 15 ([0-9a-f]{2} ){4}[ ]+callq \*0x[0-9a-f]+\(%rip\) +# [0-9a-f]+ <.*>
+ #pass
+diff --git a/ld/testsuite/ld-x86-64/plt-main-bnd.dd b/ld/testsuite/ld-x86-64/plt-main-bnd.dd
+index 8598e30..91fc945 100644
+--- a/ld/testsuite/ld-x86-64/plt-main-bnd.dd
++++ b/ld/testsuite/ld-x86-64/plt-main-bnd.dd
+@@ -2,6 +2,6 @@
+ Disassembly of section .plt.got:
+
+ [a-f0-9]+ <.plt.got>:
+-[ ]*[a-f0-9]+: f2 ff 25 .. .. 20 00 bnd jmpq \*0x20....\(%rip\) # ...... <_DYNAMIC\+0x...>
++[ ]*[a-f0-9]+: f2 ff 25 .. .. 20 00 bnd jmpq \*0x20....\(%rip\) # ...... <.*>
+ [ ]*[a-f0-9]+: 90 nop
+ #pass
+diff --git a/ld/testsuite/ld-x86-64/plt-nacl.pd b/ld/testsuite/ld-x86-64/plt-nacl.pd
+index b17bf71..e0ff471 100644
+--- a/ld/testsuite/ld-x86-64/plt-nacl.pd
++++ b/ld/testsuite/ld-x86-64/plt-nacl.pd
+@@ -8,7 +8,7 @@
+
+ Disassembly of section .plt:
+
+-[0-9a-f]+ <fn1@plt-0x40>:
++[0-9a-f]+ <.plt>:
+ +[0-9a-f]+: ff 35 ([0-9a-f]{2} ){4} * pushq 0x[0-9a-f]+\(%rip\) +# [0-9a-f]+ <_GLOBAL_OFFSET_TABLE_\+0x8>
+ +[0-9a-f]+: 4c 8b 1d ([0-9a-f]{2} ){4} * mov 0x[0-9a-f]+\(%rip\),%r11 +# [0-9a-f]+ <_GLOBAL_OFFSET_TABLE_\+0x10>
+ +[0-9a-f]+: 41 83 e3 e0 and \$0xffffffe0,%r11d
+@@ -33,7 +33,7 @@ Disassembly of section .plt:
+ +[0-9a-f]+: 0f 1f 84 00 00 00 00 *
+ +[0-9a-f]+: 00 *
+ +[0-9a-f]+: 68 00 00 00 00 pushq \$0x0
+- +[0-9a-f]+: e9 ([0-9a-f]{2} ){4} * jmpq [0-9a-f]+ <fn1@plt-0x40>
++ +[0-9a-f]+: e9 ([0-9a-f]{2} ){4} * jmpq [0-9a-f]+ <.plt>
+ +[0-9a-f]+: 66 66 66 66 66 66 2e data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\)
+ +[0-9a-f]+: 0f 1f 84 00 00 00 00 *
+ +[0-9a-f]+: 00 *
+@@ -48,7 +48,7 @@ Disassembly of section .plt:
+ +[0-9a-f]+: 0f 1f 84 00 00 00 00 *
+ +[0-9a-f]+: 00 *
+ +[0-9a-f]+: 68 01 00 00 00 pushq \$0x1
+- +[0-9a-f]+: e9 ([0-9a-f]{2} ){4} * jmpq [0-9a-f]+ <fn1@plt-0x40>
++ +[0-9a-f]+: e9 ([0-9a-f]{2} ){4} * jmpq [0-9a-f]+ <.plt>
+ +[0-9a-f]+: 66 66 66 66 66 66 2e data16 data16 data16 data16 data16 nopw %cs:0x0\(%rax,%rax,1\)
+ +[0-9a-f]+: 0f 1f 84 00 00 00 00 *
+ +[0-9a-f]+: 00 *
+diff --git a/ld/testsuite/ld-x86-64/plt.pd b/ld/testsuite/ld-x86-64/plt.pd
+index b11cc22..b303d36 100644
+--- a/ld/testsuite/ld-x86-64/plt.pd
++++ b/ld/testsuite/ld-x86-64/plt.pd
+@@ -8,17 +8,17 @@
+
+ Disassembly of section .plt:
+
+-[0-9a-f]+ <fn1@plt-0x10>:
++[0-9a-f]+ <.plt>:
+ +[0-9a-f]+: ff 35 ([0-9a-f]{2} ){4} * pushq 0x[0-9a-f]+\(%rip\) +# [0-9a-f]+ <_GLOBAL_OFFSET_TABLE_\+0x8>
+ +[0-9a-f]+: ff 25 ([0-9a-f]{2} ){4} * jmpq \*0x[0-9a-f]+\(%rip\) +# [0-9a-f]+ <_GLOBAL_OFFSET_TABLE_\+0x10>
+ +[0-9a-f]+: 0f 1f 40 00 nopl 0x0\(%rax\)
+
+ [0-9a-f]+ <fn1@plt>:
+- +[0-9a-f]+: ff 25 ([0-9a-f]{2} ){4} * jmpq \*0x[0-9a-f]+\(%rip\) +# [0-9a-f]+ <_GLOBAL_OFFSET_TABLE_\+0x18>
++ +[0-9a-f]+: ff 25 ([0-9a-f]{2} ){4} * jmpq \*0x[0-9a-f]+\(%rip\) +# [0-9a-f]+ <fn1>
+ +[0-9a-f]+: 68 00 00 00 00 pushq \$0x0
+- +[0-9a-f]+: e9 ([0-9a-f]{2} ){4} * jmpq [0-9a-f]+ <fn1@plt-0x10>
++ +[0-9a-f]+: e9 ([0-9a-f]{2} ){4} * jmpq [0-9a-f]+ <.plt>
+
+ [0-9a-f]+ <fn2@plt>:
+- +[0-9a-f]+: ff 25 ([0-9a-f]{2} ){4} * jmpq \*0x[0-9a-f]+\(%rip\) +# [0-9a-f]+ <_GLOBAL_OFFSET_TABLE_\+0x20>
++ +[0-9a-f]+: ff 25 ([0-9a-f]{2} ){4} * jmpq \*0x[0-9a-f]+\(%rip\) +# [0-9a-f]+ <fn2>
+ +[0-9a-f]+: 68 01 00 00 00 pushq \$0x1
+- +[0-9a-f]+: e9 ([0-9a-f]{2} ){4} * jmpq [0-9a-f]+ <fn1@plt-0x10>
++ +[0-9a-f]+: e9 ([0-9a-f]{2} ){4} * jmpq [0-9a-f]+ <.plt>
+diff --git a/ld/testsuite/ld-x86-64/pr18591.d b/ld/testsuite/ld-x86-64/pr18591.d
+index d5c2150..af930f6 100644
+--- a/ld/testsuite/ld-x86-64/pr18591.d
++++ b/ld/testsuite/ld-x86-64/pr18591.d
+@@ -8,5 +8,5 @@
+ Disassembly of section .text:
+
+ [a-f0-9]+ <bar>:
+-[ ]*[a-f0-9]+: 48 8b 05 ([0-9a-f]{2} ){4} mov 0x[a-f0-9]+\(%rip\),%rax # [a-f0-9]+ <_DYNAMIC\+0x[a-f0-9]+>
++[ ]*[a-f0-9]+: 48 8b 05 ([0-9a-f]{2} ){4} mov 0x[a-f0-9]+\(%rip\),%rax # [a-f0-9]+ <.*>
+ #pass
+diff --git a/ld/testsuite/ld-x86-64/pr19609-1c.d b/ld/testsuite/ld-x86-64/pr19609-1c.d
+index 3b1e98d..32bf67a 100644
+--- a/ld/testsuite/ld-x86-64/pr19609-1c.d
++++ b/ld/testsuite/ld-x86-64/pr19609-1c.d
+@@ -9,15 +9,15 @@
+ Disassembly of section .text:
+
+ [a-f0-9]+ <_start>:
+-[ ]*[a-f0-9]+: 48 3b 05 ([0-9a-f]{2} ){4} * cmp 0x[a-f0-9]+\(%rip\),%rax # [a-f0-9]+ <_DYNAMIC\+0x[a-f0-9]+>
+-[ ]*[a-f0-9]+: 3b 0d ([0-9a-f]{2} ){4} * cmp 0x[a-f0-9]+\(%rip\),%ecx # [a-f0-9]+ <_DYNAMIC\+0x[a-f0-9]+>
+-[ ]*[a-f0-9]+: 4c 3b 1d ([0-9a-f]{2} ){4} * cmp 0x[a-f0-9]+\(%rip\),%r11 # [a-f0-9]+ <_DYNAMIC\+0x[a-f0-9]+>
+-[ ]*[a-f0-9]+: 44 3b 25 ([0-9a-f]{2} ){4} * cmp 0x[a-f0-9]+\(%rip\),%r12d # [a-f0-9]+ <_DYNAMIC\+0x[a-f0-9]+>
+-[ ]*[a-f0-9]+: 48 8b 05 ([0-9a-f]{2} ){4} * mov 0x[a-f0-9]+\(%rip\),%rax # [a-f0-9]+ <_DYNAMIC\+0x[a-f0-9]+>
+-[ ]*[a-f0-9]+: 8b 0d ([0-9a-f]{2} ){4} * mov 0x[a-f0-9]+\(%rip\),%ecx # [a-f0-9]+ <_DYNAMIC\+0x[a-f0-9]+>
+-[ ]*[a-f0-9]+: 4c 8b 1d ([0-9a-f]{2} ){4} * mov 0x[a-f0-9]+\(%rip\),%r11 # [a-f0-9]+ <_DYNAMIC\+0x[a-f0-9]+>
+-[ ]*[a-f0-9]+: 44 8b 25 ([0-9a-f]{2} ){4} * mov 0x[a-f0-9]+\(%rip\),%r12d # [a-f0-9]+ <_DYNAMIC\+0x[a-f0-9]+>
+-[ ]*[a-f0-9]+: 48 85 05 ([0-9a-f]{2} ){4} * test %rax,0x[a-f0-9]+\(%rip\) # [a-f0-9]+ <_DYNAMIC\+0x[a-f0-9]+>
+-[ ]*[a-f0-9]+: 85 0d ([0-9a-f]{2} ){4} * test %ecx,0x[a-f0-9]+\(%rip\) # [a-f0-9]+ <_DYNAMIC\+0x[a-f0-9]+>
+-[ ]*[a-f0-9]+: 4c 85 1d ([0-9a-f]{2} ){4} * test %r11,0x[a-f0-9]+\(%rip\) # [a-f0-9]+ <_DYNAMIC\+0x[a-f0-9]+>
+-[ ]*[a-f0-9]+: 44 85 25 ([0-9a-f]{2} ){4} * test %r12d,0x[a-f0-9]+\(%rip\) # [a-f0-9]+ <_DYNAMIC\+0x[a-f0-9]+>
++[ ]*[a-f0-9]+: 48 3b 05 ([0-9a-f]{2} ){4} * cmp 0x[a-f0-9]+\(%rip\),%rax # [a-f0-9]+ <.*>
++[ ]*[a-f0-9]+: 3b 0d ([0-9a-f]{2} ){4} * cmp 0x[a-f0-9]+\(%rip\),%ecx # [a-f0-9]+ <.*>
++[ ]*[a-f0-9]+: 4c 3b 1d ([0-9a-f]{2} ){4} * cmp 0x[a-f0-9]+\(%rip\),%r11 # [a-f0-9]+ <.*>
++[ ]*[a-f0-9]+: 44 3b 25 ([0-9a-f]{2} ){4} * cmp 0x[a-f0-9]+\(%rip\),%r12d # [a-f0-9]+ <.*>
++[ ]*[a-f0-9]+: 48 8b 05 ([0-9a-f]{2} ){4} * mov 0x[a-f0-9]+\(%rip\),%rax # [a-f0-9]+ <.*>
++[ ]*[a-f0-9]+: 8b 0d ([0-9a-f]{2} ){4} * mov 0x[a-f0-9]+\(%rip\),%ecx # [a-f0-9]+ <.*>
++[ ]*[a-f0-9]+: 4c 8b 1d ([0-9a-f]{2} ){4} * mov 0x[a-f0-9]+\(%rip\),%r11 # [a-f0-9]+ <.*>
++[ ]*[a-f0-9]+: 44 8b 25 ([0-9a-f]{2} ){4} * mov 0x[a-f0-9]+\(%rip\),%r12d # [a-f0-9]+ <.*>
++[ ]*[a-f0-9]+: 48 85 05 ([0-9a-f]{2} ){4} * test %rax,0x[a-f0-9]+\(%rip\) # [a-f0-9]+ <.*>
++[ ]*[a-f0-9]+: 85 0d ([0-9a-f]{2} ){4} * test %ecx,0x[a-f0-9]+\(%rip\) # [a-f0-9]+ <.*>
++[ ]*[a-f0-9]+: 4c 85 1d ([0-9a-f]{2} ){4} * test %r11,0x[a-f0-9]+\(%rip\) # [a-f0-9]+ <.*>
++[ ]*[a-f0-9]+: 44 85 25 ([0-9a-f]{2} ){4} * test %r12d,0x[a-f0-9]+\(%rip\) # [a-f0-9]+ <.*>
+diff --git a/ld/testsuite/ld-x86-64/pr19609-1e.d b/ld/testsuite/ld-x86-64/pr19609-1e.d
+index dac5fef..4edc56e 100644
+--- a/ld/testsuite/ld-x86-64/pr19609-1e.d
++++ b/ld/testsuite/ld-x86-64/pr19609-1e.d
+@@ -9,15 +9,15 @@
+ Disassembly of section .text:
+
+ [a-f0-9]+ <_start>:
+-[ ]*[a-f0-9]+: 48 3b 05 ([0-9a-f]{2} ){4} * cmp 0x[a-f0-9]+\(%rip\),%rax # [a-f0-9]+ <_DYNAMIC\+0x[a-f0-9]+>
+-[ ]*[a-f0-9]+: 3b 0d ([0-9a-f]{2} ){4} * cmp 0x[a-f0-9]+\(%rip\),%ecx # [a-f0-9]+ <_DYNAMIC\+0x[a-f0-9]+>
+-[ ]*[a-f0-9]+: 4c 3b 1d ([0-9a-f]{2} ){4} * cmp 0x[a-f0-9]+\(%rip\),%r11 # [a-f0-9]+ <_DYNAMIC\+0x[a-f0-9]+>
+-[ ]*[a-f0-9]+: 44 3b 25 ([0-9a-f]{2} ){4} * cmp 0x[a-f0-9]+\(%rip\),%r12d # [a-f0-9]+ <_DYNAMIC\+0x[a-f0-9]+>
+-[ ]*[a-f0-9]+: 48 8b 05 ([0-9a-f]{2} ){4} * mov 0x[a-f0-9]+\(%rip\),%rax # [a-f0-9]+ <_DYNAMIC\+0x[a-f0-9]+>
+-[ ]*[a-f0-9]+: 8b 0d ([0-9a-f]{2} ){4} * mov 0x[a-f0-9]+\(%rip\),%ecx # [a-f0-9]+ <_DYNAMIC\+0x[a-f0-9]+>
+-[ ]*[a-f0-9]+: 4c 8b 1d ([0-9a-f]{2} ){4} * mov 0x[a-f0-9]+\(%rip\),%r11 # [a-f0-9]+ <_DYNAMIC\+0x[a-f0-9]+>
+-[ ]*[a-f0-9]+: 44 8b 25 ([0-9a-f]{2} ){4} * mov 0x[a-f0-9]+\(%rip\),%r12d # [a-f0-9]+ <_DYNAMIC\+0x[a-f0-9]+>
+-[ ]*[a-f0-9]+: 48 85 05 ([0-9a-f]{2} ){4} * test %rax,0x[a-f0-9]+\(%rip\) # [a-f0-9]+ <_DYNAMIC\+0x[a-f0-9]+>
+-[ ]*[a-f0-9]+: 85 0d ([0-9a-f]{2} ){4} * test %ecx,0x[a-f0-9]+\(%rip\) # [a-f0-9]+ <_DYNAMIC\+0x[a-f0-9]+>
+-[ ]*[a-f0-9]+: 4c 85 1d ([0-9a-f]{2} ){4} * test %r11,0x[a-f0-9]+\(%rip\) # [a-f0-9]+ <_DYNAMIC\+0x[a-f0-9]+>
+-[ ]*[a-f0-9]+: 44 85 25 ([0-9a-f]{2} ){4} * test %r12d,0x[a-f0-9]+\(%rip\) # [a-f0-9]+ <_DYNAMIC\+0x[a-f0-9]+>
++[ ]*[a-f0-9]+: 48 3b 05 ([0-9a-f]{2} ){4} * cmp 0x[a-f0-9]+\(%rip\),%rax # [a-f0-9]+ <.*>
++[ ]*[a-f0-9]+: 3b 0d ([0-9a-f]{2} ){4} * cmp 0x[a-f0-9]+\(%rip\),%ecx # [a-f0-9]+ <.*>
++[ ]*[a-f0-9]+: 4c 3b 1d ([0-9a-f]{2} ){4} * cmp 0x[a-f0-9]+\(%rip\),%r11 # [a-f0-9]+ <.*>
++[ ]*[a-f0-9]+: 44 3b 25 ([0-9a-f]{2} ){4} * cmp 0x[a-f0-9]+\(%rip\),%r12d # [a-f0-9]+ <.*>
++[ ]*[a-f0-9]+: 48 8b 05 ([0-9a-f]{2} ){4} * mov 0x[a-f0-9]+\(%rip\),%rax # [a-f0-9]+ <.*>
++[ ]*[a-f0-9]+: 8b 0d ([0-9a-f]{2} ){4} * mov 0x[a-f0-9]+\(%rip\),%ecx # [a-f0-9]+ <.*>
++[ ]*[a-f0-9]+: 4c 8b 1d ([0-9a-f]{2} ){4} * mov 0x[a-f0-9]+\(%rip\),%r11 # [a-f0-9]+ <.*>
++[ ]*[a-f0-9]+: 44 8b 25 ([0-9a-f]{2} ){4} * mov 0x[a-f0-9]+\(%rip\),%r12d # [a-f0-9]+ <.*>
++[ ]*[a-f0-9]+: 48 85 05 ([0-9a-f]{2} ){4} * test %rax,0x[a-f0-9]+\(%rip\) # [a-f0-9]+ <.*>
++[ ]*[a-f0-9]+: 85 0d ([0-9a-f]{2} ){4} * test %ecx,0x[a-f0-9]+\(%rip\) # [a-f0-9]+ <.*>
++[ ]*[a-f0-9]+: 4c 85 1d ([0-9a-f]{2} ){4} * test %r11,0x[a-f0-9]+\(%rip\) # [a-f0-9]+ <.*>
++[ ]*[a-f0-9]+: 44 85 25 ([0-9a-f]{2} ){4} * test %r12d,0x[a-f0-9]+\(%rip\) # [a-f0-9]+ <.*>
+diff --git a/ld/testsuite/ld-x86-64/pr19609-1j.d b/ld/testsuite/ld-x86-64/pr19609-1j.d
+index 4a36a70..c8b940a 100644
+--- a/ld/testsuite/ld-x86-64/pr19609-1j.d
++++ b/ld/testsuite/ld-x86-64/pr19609-1j.d
+@@ -9,15 +9,15 @@
+ Disassembly of section .text:
+
+ [a-f0-9]+ <_start>:
+-[ ]*[a-f0-9]+: 48 3b 05 ([0-9a-f]{2} ){4} * cmp 0x[a-f0-9]+\(%rip\),%rax # [a-f0-9]+ <_DYNAMIC\+0x[a-f0-9]+>
+-[ ]*[a-f0-9]+: 3b 0d ([0-9a-f]{2} ){4} * cmp 0x[a-f0-9]+\(%rip\),%ecx # [a-f0-9]+ <_DYNAMIC\+0x[a-f0-9]+>
+-[ ]*[a-f0-9]+: 4c 3b 1d ([0-9a-f]{2} ){4} * cmp 0x[a-f0-9]+\(%rip\),%r11 # [a-f0-9]+ <_DYNAMIC\+0x[a-f0-9]+>
+-[ ]*[a-f0-9]+: 44 3b 25 ([0-9a-f]{2} ){4} * cmp 0x[a-f0-9]+\(%rip\),%r12d # [a-f0-9]+ <_DYNAMIC\+0x[a-f0-9]+>
+-[ ]*[a-f0-9]+: 48 8b 05 ([0-9a-f]{2} ){4} * mov 0x[a-f0-9]+\(%rip\),%rax # [a-f0-9]+ <_DYNAMIC\+0x[a-f0-9]+>
+-[ ]*[a-f0-9]+: 8b 0d ([0-9a-f]{2} ){4} * mov 0x[a-f0-9]+\(%rip\),%ecx # [a-f0-9]+ <_DYNAMIC\+0x[a-f0-9]+>
+-[ ]*[a-f0-9]+: 4c 8b 1d ([0-9a-f]{2} ){4} * mov 0x[a-f0-9]+\(%rip\),%r11 # [a-f0-9]+ <_DYNAMIC\+0x[a-f0-9]+>
+-[ ]*[a-f0-9]+: 44 8b 25 ([0-9a-f]{2} ){4} * mov 0x[a-f0-9]+\(%rip\),%r12d # [a-f0-9]+ <_DYNAMIC\+0x[a-f0-9]+>
+-[ ]*[a-f0-9]+: 48 85 05 ([0-9a-f]{2} ){4} * test %rax,0x[a-f0-9]+\(%rip\) # [a-f0-9]+ <_DYNAMIC\+0x[a-f0-9]+>
+-[ ]*[a-f0-9]+: 85 0d ([0-9a-f]{2} ){4} * test %ecx,0x[a-f0-9]+\(%rip\) # [a-f0-9]+ <_DYNAMIC\+0x[a-f0-9]+>
+-[ ]*[a-f0-9]+: 4c 85 1d ([0-9a-f]{2} ){4} * test %r11,0x[a-f0-9]+\(%rip\) # [a-f0-9]+ <_DYNAMIC\+0x[a-f0-9]+>
+-[ ]*[a-f0-9]+: 44 85 25 ([0-9a-f]{2} ){4} * test %r12d,0x[a-f0-9]+\(%rip\) # [a-f0-9]+ <_DYNAMIC\+0x[a-f0-9]+>
++[ ]*[a-f0-9]+: 48 3b 05 ([0-9a-f]{2} ){4} * cmp 0x[a-f0-9]+\(%rip\),%rax # [a-f0-9]+ <.*>
++[ ]*[a-f0-9]+: 3b 0d ([0-9a-f]{2} ){4} * cmp 0x[a-f0-9]+\(%rip\),%ecx # [a-f0-9]+ <.*>
++[ ]*[a-f0-9]+: 4c 3b 1d ([0-9a-f]{2} ){4} * cmp 0x[a-f0-9]+\(%rip\),%r11 # [a-f0-9]+ <.*>
++[ ]*[a-f0-9]+: 44 3b 25 ([0-9a-f]{2} ){4} * cmp 0x[a-f0-9]+\(%rip\),%r12d # [a-f0-9]+ <.*>
++[ ]*[a-f0-9]+: 48 8b 05 ([0-9a-f]{2} ){4} * mov 0x[a-f0-9]+\(%rip\),%rax # [a-f0-9]+ <.*>
++[ ]*[a-f0-9]+: 8b 0d ([0-9a-f]{2} ){4} * mov 0x[a-f0-9]+\(%rip\),%ecx # [a-f0-9]+ <.*>
++[ ]*[a-f0-9]+: 4c 8b 1d ([0-9a-f]{2} ){4} * mov 0x[a-f0-9]+\(%rip\),%r11 # [a-f0-9]+ <.*>
++[ ]*[a-f0-9]+: 44 8b 25 ([0-9a-f]{2} ){4} * mov 0x[a-f0-9]+\(%rip\),%r12d # [a-f0-9]+ <.*>
++[ ]*[a-f0-9]+: 48 85 05 ([0-9a-f]{2} ){4} * test %rax,0x[a-f0-9]+\(%rip\) # [a-f0-9]+ <.*>
++[ ]*[a-f0-9]+: 85 0d ([0-9a-f]{2} ){4} * test %ecx,0x[a-f0-9]+\(%rip\) # [a-f0-9]+ <.*>
++[ ]*[a-f0-9]+: 4c 85 1d ([0-9a-f]{2} ){4} * test %r11,0x[a-f0-9]+\(%rip\) # [a-f0-9]+ <.*>
++[ ]*[a-f0-9]+: 44 85 25 ([0-9a-f]{2} ){4} * test %r12d,0x[a-f0-9]+\(%rip\) # [a-f0-9]+ <.*>
+diff --git a/ld/testsuite/ld-x86-64/pr19609-1l.d b/ld/testsuite/ld-x86-64/pr19609-1l.d
+index aedf5d8..5559399 100644
+--- a/ld/testsuite/ld-x86-64/pr19609-1l.d
++++ b/ld/testsuite/ld-x86-64/pr19609-1l.d
+@@ -9,15 +9,15 @@
+ Disassembly of section .text:
+
+ [a-f0-9]+ <_start>:
+-[ ]*[a-f0-9]+: 48 3b 05 ([0-9a-f]{2} ){4} * cmp 0x[a-f0-9]+\(%rip\),%rax # [a-f0-9]+ <_start\+0x[a-f0-9]+>
+-[ ]*[a-f0-9]+: 3b 0d ([0-9a-f]{2} ){4} * cmp 0x[a-f0-9]+\(%rip\),%ecx # [a-f0-9]+ <_start\+0x[a-f0-9]+>
+-[ ]*[a-f0-9]+: 4c 3b 1d ([0-9a-f]{2} ){4} * cmp 0x[a-f0-9]+\(%rip\),%r11 # [a-f0-9]+ <_start\+0x[a-f0-9]+>
+-[ ]*[a-f0-9]+: 44 3b 25 ([0-9a-f]{2} ){4} * cmp 0x[a-f0-9]+\(%rip\),%r12d # [a-f0-9]+ <_start\+0x[a-f0-9]+>
++[ ]*[a-f0-9]+: 48 3b 05 ([0-9a-f]{2} ){4} * cmp 0x[a-f0-9]+\(%rip\),%rax # [a-f0-9]+ <.*>
++[ ]*[a-f0-9]+: 3b 0d ([0-9a-f]{2} ){4} * cmp 0x[a-f0-9]+\(%rip\),%ecx # [a-f0-9]+ <.*>
++[ ]*[a-f0-9]+: 4c 3b 1d ([0-9a-f]{2} ){4} * cmp 0x[a-f0-9]+\(%rip\),%r11 # [a-f0-9]+ <.*>
++[ ]*[a-f0-9]+: 44 3b 25 ([0-9a-f]{2} ){4} * cmp 0x[a-f0-9]+\(%rip\),%r12d # [a-f0-9]+ <.*>
+ [ ]*[a-f0-9]+: 48 8d 05 ([0-9a-f]{2} ){4} * lea -0x[a-f0-9]+\(%rip\),%rax # 0 <_start-0x[a-f0-9]+>
+ [ ]*[a-f0-9]+: 8d 0d ([0-9a-f]{2} ){4} * lea -0x[a-f0-9]+\(%rip\),%ecx # 0 <_start-0x[a-f0-9]+>
+ [ ]*[a-f0-9]+: 4c 8d 1d ([0-9a-f]{2} ){4} * lea -0x[a-f0-9]+\(%rip\),%r11 # 0 <_start-0x[a-f0-9]+>
+ [ ]*[a-f0-9]+: 44 8d 25 ([0-9a-f]{2} ){4} * lea -0x[a-f0-9]+\(%rip\),%r12d # 0 <_start-0x[a-f0-9]+>
+-[ ]*[a-f0-9]+: 48 85 05 ([0-9a-f]{2} ){4} * test %rax,0x[a-f0-9]+\(%rip\) # [a-f0-9]+ <_start\+0x[a-f0-9]+>
+-[ ]*[a-f0-9]+: 85 0d ([0-9a-f]{2} ){4} * test %ecx,0x[a-f0-9]+\(%rip\) # [a-f0-9]+ <_start\+0x[a-f0-9]+>
+-[ ]*[a-f0-9]+: 4c 85 1d ([0-9a-f]{2} ){4} * test %r11,0x[a-f0-9]+\(%rip\) # [a-f0-9]+ <_start\+0x[a-f0-9]+>
+-[ ]*[a-f0-9]+: 44 85 25 ([0-9a-f]{2} ){4} * test %r12d,0x[a-f0-9]+\(%rip\) # [a-f0-9]+ <_start\+0x[a-f0-9]+>
++[ ]*[a-f0-9]+: 48 85 05 ([0-9a-f]{2} ){4} * test %rax,0x[a-f0-9]+\(%rip\) # [a-f0-9]+ <.*>
++[ ]*[a-f0-9]+: 85 0d ([0-9a-f]{2} ){4} * test %ecx,0x[a-f0-9]+\(%rip\) # [a-f0-9]+ <.*>
++[ ]*[a-f0-9]+: 4c 85 1d ([0-9a-f]{2} ){4} * test %r11,0x[a-f0-9]+\(%rip\) # [a-f0-9]+ <.*>
++[ ]*[a-f0-9]+: 44 85 25 ([0-9a-f]{2} ){4} * test %r12d,0x[a-f0-9]+\(%rip\) # [a-f0-9]+ <.*>
+diff --git a/ld/testsuite/ld-x86-64/pr19609-1m.d b/ld/testsuite/ld-x86-64/pr19609-1m.d
+index 8e80cbb..c6831d8 100644
+--- a/ld/testsuite/ld-x86-64/pr19609-1m.d
++++ b/ld/testsuite/ld-x86-64/pr19609-1m.d
+@@ -9,15 +9,15 @@
+ Disassembly of section .text:
+
+ [a-f0-9]+ <_start>:
+-[ ]*[a-f0-9]+: 48 3b 05 ([0-9a-f]{2} ){4} * cmp 0x[a-f0-9]+\(%rip\),%rax # [a-f0-9]+ <_DYNAMIC\+0x[a-f0-9]+>
+-[ ]*[a-f0-9]+: 3b 0d ([0-9a-f]{2} ){4} * cmp 0x[a-f0-9]+\(%rip\),%ecx # [a-f0-9]+ <_DYNAMIC\+0x[a-f0-9]+>
+-[ ]*[a-f0-9]+: 4c 3b 1d ([0-9a-f]{2} ){4} * cmp 0x[a-f0-9]+\(%rip\),%r11 # [a-f0-9]+ <_DYNAMIC\+0x[a-f0-9]+>
+-[ ]*[a-f0-9]+: 44 3b 25 ([0-9a-f]{2} ){4} * cmp 0x[a-f0-9]+\(%rip\),%r12d # [a-f0-9]+ <_DYNAMIC\+0x[a-f0-9]+>
+-[ ]*[a-f0-9]+: 48 8b 05 ([0-9a-f]{2} ){4} * mov 0x[a-f0-9]+\(%rip\),%rax # [a-f0-9]+ <_DYNAMIC\+0x[a-f0-9]+>
+-[ ]*[a-f0-9]+: 8b 0d ([0-9a-f]{2} ){4} * mov 0x[a-f0-9]+\(%rip\),%ecx # [a-f0-9]+ <_DYNAMIC\+0x[a-f0-9]+>
+-[ ]*[a-f0-9]+: 4c 8b 1d ([0-9a-f]{2} ){4} * mov 0x[a-f0-9]+\(%rip\),%r11 # [a-f0-9]+ <_DYNAMIC\+0x[a-f0-9]+>
+-[ ]*[a-f0-9]+: 44 8b 25 ([0-9a-f]{2} ){4} * mov 0x[a-f0-9]+\(%rip\),%r12d # [a-f0-9]+ <_DYNAMIC\+0x[a-f0-9]+>
+-[ ]*[a-f0-9]+: 48 85 05 ([0-9a-f]{2} ){4} * test %rax,0x[a-f0-9]+\(%rip\) # [a-f0-9]+ <_DYNAMIC\+0x[a-f0-9]+>
+-[ ]*[a-f0-9]+: 85 0d ([0-9a-f]{2} ){4} * test %ecx,0x[a-f0-9]+\(%rip\) # [a-f0-9]+ <_DYNAMIC\+0x[a-f0-9]+>
+-[ ]*[a-f0-9]+: 4c 85 1d ([0-9a-f]{2} ){4} * test %r11,0x[a-f0-9]+\(%rip\) # [a-f0-9]+ <_DYNAMIC\+0x[a-f0-9]+>
+-[ ]*[a-f0-9]+: 44 85 25 ([0-9a-f]{2} ){4} * test %r12d,0x[a-f0-9]+\(%rip\) # [a-f0-9]+ <_DYNAMIC\+0x[a-f0-9]+>
++[ ]*[a-f0-9]+: 48 3b 05 ([0-9a-f]{2} ){4} * cmp 0x[a-f0-9]+\(%rip\),%rax # [a-f0-9]+ <.*>
++[ ]*[a-f0-9]+: 3b 0d ([0-9a-f]{2} ){4} * cmp 0x[a-f0-9]+\(%rip\),%ecx # [a-f0-9]+ <.*>
++[ ]*[a-f0-9]+: 4c 3b 1d ([0-9a-f]{2} ){4} * cmp 0x[a-f0-9]+\(%rip\),%r11 # [a-f0-9]+ <.*>
++[ ]*[a-f0-9]+: 44 3b 25 ([0-9a-f]{2} ){4} * cmp 0x[a-f0-9]+\(%rip\),%r12d # [a-f0-9]+ <.*>
++[ ]*[a-f0-9]+: 48 8b 05 ([0-9a-f]{2} ){4} * mov 0x[a-f0-9]+\(%rip\),%rax # [a-f0-9]+ <.*>
++[ ]*[a-f0-9]+: 8b 0d ([0-9a-f]{2} ){4} * mov 0x[a-f0-9]+\(%rip\),%ecx # [a-f0-9]+ <.*>
++[ ]*[a-f0-9]+: 4c 8b 1d ([0-9a-f]{2} ){4} * mov 0x[a-f0-9]+\(%rip\),%r11 # [a-f0-9]+ <.*>
++[ ]*[a-f0-9]+: 44 8b 25 ([0-9a-f]{2} ){4} * mov 0x[a-f0-9]+\(%rip\),%r12d # [a-f0-9]+ <.*>
++[ ]*[a-f0-9]+: 48 85 05 ([0-9a-f]{2} ){4} * test %rax,0x[a-f0-9]+\(%rip\) # [a-f0-9]+ <.*>
++[ ]*[a-f0-9]+: 85 0d ([0-9a-f]{2} ){4} * test %ecx,0x[a-f0-9]+\(%rip\) # [a-f0-9]+ <.*>
++[ ]*[a-f0-9]+: 4c 85 1d ([0-9a-f]{2} ){4} * test %r11,0x[a-f0-9]+\(%rip\) # [a-f0-9]+ <.*>
++[ ]*[a-f0-9]+: 44 85 25 ([0-9a-f]{2} ){4} * test %r12d,0x[a-f0-9]+\(%rip\) # [a-f0-9]+ <.*>
+diff --git a/ld/testsuite/ld-x86-64/pr19609-5b.d b/ld/testsuite/ld-x86-64/pr19609-5b.d
+index 4183d56..257fa63 100644
+--- a/ld/testsuite/ld-x86-64/pr19609-5b.d
++++ b/ld/testsuite/ld-x86-64/pr19609-5b.d
+@@ -9,4 +9,4 @@
+ Disassembly of section .text:
+
+ [a-f0-9]+ <_start>:
+-[ ]+[a-f0-9]+: ff 15 ([0-9a-f]{2} ){4} * callq \*0x[a-f0-9]+\(%rip\) # [a-f0-9]+ <_DYNAMIC\+0x[a-f0-9]+>
++[ ]+[a-f0-9]+: ff 15 ([0-9a-f]{2} ){4} * callq \*0x[a-f0-9]+\(%rip\) # [a-f0-9]+ <.*>
+diff --git a/ld/testsuite/ld-x86-64/pr19609-5c.d b/ld/testsuite/ld-x86-64/pr19609-5c.d
+index 4eaeb2b..1de68b4 100644
+--- a/ld/testsuite/ld-x86-64/pr19609-5c.d
++++ b/ld/testsuite/ld-x86-64/pr19609-5c.d
+@@ -9,4 +9,4 @@
+ Disassembly of section .text:
+
+ [a-f0-9]+ <_start>:
+-[ ]+[a-f0-9]+: ff 15 ([0-9a-f]{2} ){4} * callq \*0x[a-f0-9]+\(%rip\) # [a-f0-9]+ <_DYNAMIC\+0x[a-f0-9]+>
++[ ]+[a-f0-9]+: ff 15 ([0-9a-f]{2} ){4} * callq \*0x[a-f0-9]+\(%rip\) # [a-f0-9]+ <bar>
+diff --git a/ld/testsuite/ld-x86-64/pr19609-5e.d b/ld/testsuite/ld-x86-64/pr19609-5e.d
+index b6b6c65..90bdb3d 100644
+--- a/ld/testsuite/ld-x86-64/pr19609-5e.d
++++ b/ld/testsuite/ld-x86-64/pr19609-5e.d
+@@ -9,4 +9,4 @@
+ Disassembly of section .text:
+
+ [a-f0-9]+ <_start>:
+-[ ]+[a-f0-9]+: ff 15 ([0-9a-f]{2} ){4} * callq \*-?0x[a-f0-9]+\(%rip\) # [a-f0-9]+ <[0-9a-zA-Z_]+[\+\-]+0x[a-f0-9]+>
++[ ]+[a-f0-9]+: ff 15 ([0-9a-f]{2} ){4} * callq \*-?0x[a-f0-9]+\(%rip\) # [a-f0-9]+ <.*>
+diff --git a/ld/testsuite/ld-x86-64/pr19609-6b.d b/ld/testsuite/ld-x86-64/pr19609-6b.d
+index 64e1f5b..810023b 100644
+--- a/ld/testsuite/ld-x86-64/pr19609-6b.d
++++ b/ld/testsuite/ld-x86-64/pr19609-6b.d
+@@ -9,5 +9,5 @@
+ Disassembly of section .text:
+
+ [a-f0-9]+ <_start>:
+-[ ]*[a-f0-9]+: 48 8b 05 ([0-9a-f]{2} ){4} * mov 0x[a-f0-9]+\(%rip\),%rax # [a-f0-9]+ <_start\+0x[a-f0-9]+>
++[ ]*[a-f0-9]+: 48 8b 05 ([0-9a-f]{2} ){4} * mov 0x[a-f0-9]+\(%rip\),%rax # [a-f0-9]+ <.got>
+ #pass
+diff --git a/ld/testsuite/ld-x86-64/pr19609-7b.d b/ld/testsuite/ld-x86-64/pr19609-7b.d
+index 2e8fd35..898a5df 100644
+--- a/ld/testsuite/ld-x86-64/pr19609-7b.d
++++ b/ld/testsuite/ld-x86-64/pr19609-7b.d
+@@ -9,5 +9,5 @@
+ Disassembly of section .text:
+
+ [a-f0-9]+ <_start>:
+-[ ]*[a-f0-9]+: ff 15 ([0-9a-f]{2} ){4} * callq \*-?0x[a-f0-9]+\(%rip\) # [a-f0-9]+ <.*0x[a-f0-9]+>
++[ ]*[a-f0-9]+: ff 15 ([0-9a-f]{2} ){4} * callq \*-?0x[a-f0-9]+\(%rip\) # [a-f0-9]+ <.got>
+ #pass
+diff --git a/ld/testsuite/ld-x86-64/pr19609-7d.d b/ld/testsuite/ld-x86-64/pr19609-7d.d
+index ba28828..476cafa 100644
+--- a/ld/testsuite/ld-x86-64/pr19609-7d.d
++++ b/ld/testsuite/ld-x86-64/pr19609-7d.d
+@@ -9,5 +9,5 @@
+ Disassembly of section .text:
+
+ [a-f0-9]+ <_start>:
+-[ ]*[a-f0-9]+: ff 15 ([0-9a-f]{2} ){4} * callq \*-?0x[a-f0-9]+\(%rip\) # [a-f0-9]+ <.*0x[a-f0-9]+>
++[ ]*[a-f0-9]+: ff 15 ([0-9a-f]{2} ){4} * callq \*-?0x[a-f0-9]+\(%rip\) # [a-f0-9]+ <.got>
+ #pass
+diff --git a/ld/testsuite/ld-x86-64/pr19636-2d.d b/ld/testsuite/ld-x86-64/pr19636-2d.d
+index ff25ec1..4f5c1f0 100644
+--- a/ld/testsuite/ld-x86-64/pr19636-2d.d
++++ b/ld/testsuite/ld-x86-64/pr19636-2d.d
+@@ -20,6 +20,6 @@ Disassembly of section .plt:
+ Disassembly of section .text:
+
+ 0+140 <_start>:
+-[ ]*[a-f0-9]+: 48 3b 05 f1 00 20 00 cmp 0x2000f1\(%rip\),%rax # 200238 <_DYNAMIC\+0xe0>
+-[ ]*[a-f0-9]+: ff 25 f3 00 20 00 jmpq \*0x2000f3\(%rip\) # 200240 <_DYNAMIC\+0xe8>
+-[ ]*[a-f0-9]+: e8 de ff ff ff callq 130 <_start-0x10>
++[ ]*[a-f0-9]+: 48 3b 05 f1 00 20 00 cmp 0x2000f1\(%rip\),%rax # 200238 <.*>
++[ ]*[a-f0-9]+: ff 25 f3 00 20 00 jmpq \*0x2000f3\(%rip\) # 200240 <.*>
++[ ]*[a-f0-9]+: e8 de ff ff ff callq 130 <.*>
+diff --git a/ld/testsuite/ld-x86-64/pr20093-1.d b/ld/testsuite/ld-x86-64/pr20093-1.d
+index de81443..90bb3ab 100644
+--- a/ld/testsuite/ld-x86-64/pr20093-1.d
++++ b/ld/testsuite/ld-x86-64/pr20093-1.d
+@@ -8,4 +8,4 @@
+ Disassembly of section .text:
+
+ [a-f0-9]+ <_start>:
+-[ ]*[a-f0-9]+: 48 8b 05 ([0-9a-f]{2} ){4} * mov 0x[a-f0-9]+\(%rip\),%rax # [a-f0-9]+ <_DYNAMIC\+0x[a-f0-9]+>
++[ ]*[a-f0-9]+: 48 8b 05 ([0-9a-f]{2} ){4} * mov 0x[a-f0-9]+\(%rip\),%rax # [a-f0-9]+ <.*>
+diff --git a/ld/testsuite/ld-x86-64/pr20093-2.d b/ld/testsuite/ld-x86-64/pr20093-2.d
+index de81443..90bb3ab 100644
+--- a/ld/testsuite/ld-x86-64/pr20093-2.d
++++ b/ld/testsuite/ld-x86-64/pr20093-2.d
+@@ -8,4 +8,4 @@
+ Disassembly of section .text:
+
+ [a-f0-9]+ <_start>:
+-[ ]*[a-f0-9]+: 48 8b 05 ([0-9a-f]{2} ){4} * mov 0x[a-f0-9]+\(%rip\),%rax # [a-f0-9]+ <_DYNAMIC\+0x[a-f0-9]+>
++[ ]*[a-f0-9]+: 48 8b 05 ([0-9a-f]{2} ){4} * mov 0x[a-f0-9]+\(%rip\),%rax # [a-f0-9]+ <.*>
+diff --git a/ld/testsuite/ld-x86-64/pr20253-1b.d b/ld/testsuite/ld-x86-64/pr20253-1b.d
+index 247e042..d68dd46 100644
+--- a/ld/testsuite/ld-x86-64/pr20253-1b.d
++++ b/ld/testsuite/ld-x86-64/pr20253-1b.d
+@@ -16,10 +16,10 @@ Disassembly of section .text:
+ +[a-f0-9]+: c3 retq
+
+ 0+4000e2 <_start>:
+- +[a-f0-9]+: ff 15 28 00 20 00 callq \*0x200028\(%rip\) # 600110 <_start\+0x20002e>
+- +[a-f0-9]+: ff 25 2a 00 20 00 jmpq \*0x20002a\(%rip\) # 600118 <_start\+0x200036>
+- +[a-f0-9]+: 48 c7 05 1f 00 20 00 00 00 00 00 movq \$0x0,0x20001f\(%rip\) # 600118 <_start\+0x200036>
+- +[a-f0-9]+: 48 83 3d 0f 00 20 00 00 cmpq \$0x0,0x20000f\(%rip\) # 600110 <_start\+0x20002e>
+- +[a-f0-9]+: 48 3b 0d 08 00 20 00 cmp 0x200008\(%rip\),%rcx # 600110 <_start\+0x20002e>
+- +[a-f0-9]+: 48 3b 0d 09 00 20 00 cmp 0x200009\(%rip\),%rcx # 600118 <_start\+0x200036>
++ +[a-f0-9]+: ff 15 28 00 20 00 callq \*0x200028\(%rip\) # 600110 <.*>
++ +[a-f0-9]+: ff 25 2a 00 20 00 jmpq \*0x20002a\(%rip\) # 600118 <.*>
++ +[a-f0-9]+: 48 c7 05 1f 00 20 00 00 00 00 00 movq \$0x0,0x20001f\(%rip\) # 600118 <.*>
++ +[a-f0-9]+: 48 83 3d 0f 00 20 00 00 cmpq \$0x0,0x20000f\(%rip\) # 600110 <.*>
++ +[a-f0-9]+: 48 3b 0d 08 00 20 00 cmp 0x200008\(%rip\),%rcx # 600110 <.*>
++ +[a-f0-9]+: 48 3b 0d 09 00 20 00 cmp 0x200009\(%rip\),%rcx # 600118 <.*>
+ #pass
+diff --git a/ld/testsuite/ld-x86-64/pr20253-1d.d b/ld/testsuite/ld-x86-64/pr20253-1d.d
+index 35c04f8..6953c79 100644
+--- a/ld/testsuite/ld-x86-64/pr20253-1d.d
++++ b/ld/testsuite/ld-x86-64/pr20253-1d.d
+@@ -16,10 +16,10 @@ Disassembly of section .text:
+ +[a-f0-9]+: c3 retq
+
+ 0+1ca <_start>:
+- +[a-f0-9]+: ff 15 28 01 20 00 callq \*0x200128\(%rip\) # 2002f8 <_DYNAMIC\+0x100>
+- +[a-f0-9]+: ff 25 2a 01 20 00 jmpq \*0x20012a\(%rip\) # 200300 <_DYNAMIC\+0x108>
+- +[a-f0-9]+: 48 c7 05 1f 01 20 00 00 00 00 00 movq \$0x0,0x20011f\(%rip\) # 200300 <_DYNAMIC\+0x108>
+- +[a-f0-9]+: 48 83 3d 0f 01 20 00 00 cmpq \$0x0,0x20010f\(%rip\) # 2002f8 <_DYNAMIC\+0x100>
+- +[a-f0-9]+: 48 3b 0d 08 01 20 00 cmp 0x200108\(%rip\),%rcx # 2002f8 <_DYNAMIC\+0x100>
+- +[a-f0-9]+: 48 3b 0d 09 01 20 00 cmp 0x200109\(%rip\),%rcx # 200300 <_DYNAMIC\+0x108>
++ +[a-f0-9]+: ff 15 28 01 20 00 callq \*0x200128\(%rip\) # 2002f8 <.got>
++ +[a-f0-9]+: ff 25 2a 01 20 00 jmpq \*0x20012a\(%rip\) # 200300 <.got\+0x8>
++ +[a-f0-9]+: 48 c7 05 1f 01 20 00 00 00 00 00 movq \$0x0,0x20011f\(%rip\) # 200300 <.got\+0x8>
++ +[a-f0-9]+: 48 83 3d 0f 01 20 00 00 cmpq \$0x0,0x20010f\(%rip\) # 2002f8 <.got>
++ +[a-f0-9]+: 48 3b 0d 08 01 20 00 cmp 0x200108\(%rip\),%rcx # 2002f8 <.got>
++ +[a-f0-9]+: 48 3b 0d 09 01 20 00 cmp 0x200109\(%rip\),%rcx # 200300 <.got\+0x8>
+ #pass
+diff --git a/ld/testsuite/ld-x86-64/pr20253-1f.d b/ld/testsuite/ld-x86-64/pr20253-1f.d
+index d84b60e..9319350 100644
+--- a/ld/testsuite/ld-x86-64/pr20253-1f.d
++++ b/ld/testsuite/ld-x86-64/pr20253-1f.d
+@@ -16,10 +16,10 @@ Disassembly of section .text:
+ +[a-f0-9]+: c3 retq
+
+ 0+1fa <_start>:
+- +[a-f0-9]+: ff 15 08 01 20 00 callq \*0x200108\(%rip\) # 200308 <_DYNAMIC\+0xe0>
+- +[a-f0-9]+: ff 25 0a 01 20 00 jmpq \*0x20010a\(%rip\) # 200310 <_DYNAMIC\+0xe8>
+- +[a-f0-9]+: 48 c7 05 ff 00 20 00 00 00 00 00 movq \$0x0,0x2000ff\(%rip\) # 200310 <_DYNAMIC\+0xe8>
+- +[a-f0-9]+: 48 83 3d ef 00 20 00 00 cmpq \$0x0,0x2000ef\(%rip\) # 200308 <_DYNAMIC\+0xe0>
+- +[a-f0-9]+: 48 3b 0d e8 00 20 00 cmp 0x2000e8\(%rip\),%rcx # 200308 <_DYNAMIC\+0xe0>
+- +[a-f0-9]+: 48 3b 0d e9 00 20 00 cmp 0x2000e9\(%rip\),%rcx # 200310 <_DYNAMIC\+0xe8>
++ +[a-f0-9]+: ff 15 08 01 20 00 callq \*0x200108\(%rip\) # 200308 <.*>
++ +[a-f0-9]+: ff 25 0a 01 20 00 jmpq \*0x20010a\(%rip\) # 200310 <.*>
++ +[a-f0-9]+: 48 c7 05 ff 00 20 00 00 00 00 00 movq \$0x0,0x2000ff\(%rip\) # 200310 <.*>
++ +[a-f0-9]+: 48 83 3d ef 00 20 00 00 cmpq \$0x0,0x2000ef\(%rip\) # 200308 <.*>
++ +[a-f0-9]+: 48 3b 0d e8 00 20 00 cmp 0x2000e8\(%rip\),%rcx # 200308 <.*>
++ +[a-f0-9]+: 48 3b 0d e9 00 20 00 cmp 0x2000e9\(%rip\),%rcx # 200310 <.*>
+ #pass
+diff --git a/ld/testsuite/ld-x86-64/pr20253-1h.d b/ld/testsuite/ld-x86-64/pr20253-1h.d
+index 77ff100..14a8f1b 100644
+--- a/ld/testsuite/ld-x86-64/pr20253-1h.d
++++ b/ld/testsuite/ld-x86-64/pr20253-1h.d
+@@ -16,10 +16,10 @@ Disassembly of section .text:
+ +[a-f0-9]+: c3 retq
+
+ 0+40008e <_start>:
+- +[a-f0-9]+: ff 15 28 00 20 00 callq \*0x200028\(%rip\) # 6000bc <_start\+0x20002e>
+- +[a-f0-9]+: ff 25 2a 00 20 00 jmpq \*0x20002a\(%rip\) # 6000c4 <_start\+0x200036>
+- +[a-f0-9]+: 48 c7 05 1f 00 20 00 00 00 00 00 movq \$0x0,0x20001f\(%rip\) # 6000c4 <_start\+0x200036>
+- +[a-f0-9]+: 48 83 3d 0f 00 20 00 00 cmpq \$0x0,0x20000f\(%rip\) # 6000bc <_start\+0x20002e>
+- +[a-f0-9]+: 48 3b 0d 08 00 20 00 cmp 0x200008\(%rip\),%rcx # 6000bc <_start\+0x20002e>
+- +[a-f0-9]+: 48 3b 0d 09 00 20 00 cmp 0x200009\(%rip\),%rcx # 6000c4 <_start\+0x200036>
++ +[a-f0-9]+: ff 15 28 00 20 00 callq \*0x200028\(%rip\) # 6000bc <.*>
++ +[a-f0-9]+: ff 25 2a 00 20 00 jmpq \*0x20002a\(%rip\) # 6000c4 <.*>
++ +[a-f0-9]+: 48 c7 05 1f 00 20 00 00 00 00 00 movq \$0x0,0x20001f\(%rip\) # 6000c4 <.*>
++ +[a-f0-9]+: 48 83 3d 0f 00 20 00 00 cmpq \$0x0,0x20000f\(%rip\) # 6000bc <.*>
++ +[a-f0-9]+: 48 3b 0d 08 00 20 00 cmp 0x200008\(%rip\),%rcx # 6000bc <.*>
++ +[a-f0-9]+: 48 3b 0d 09 00 20 00 cmp 0x200009\(%rip\),%rcx # 6000c4 <.*>
+ #pass
+diff --git a/ld/testsuite/ld-x86-64/pr20253-1j.d b/ld/testsuite/ld-x86-64/pr20253-1j.d
+index 6f5d666..5662e0c 100644
+--- a/ld/testsuite/ld-x86-64/pr20253-1j.d
++++ b/ld/testsuite/ld-x86-64/pr20253-1j.d
+@@ -16,10 +16,10 @@ Disassembly of section .text:
+ +[a-f0-9]+: c3 retq
+
+ 0+122 <_start>:
+- +[a-f0-9]+: ff 15 a8 00 20 00 callq \*0x2000a8\(%rip\) # 2001d0 <_DYNAMIC\+0x80>
+- +[a-f0-9]+: ff 25 aa 00 20 00 jmpq \*0x2000aa\(%rip\) # 2001d8 <_DYNAMIC\+0x88>
+- +[a-f0-9]+: 48 c7 05 9f 00 20 00 00 00 00 00 movq \$0x0,0x20009f\(%rip\) # 2001d8 <_DYNAMIC\+0x88>
+- +[a-f0-9]+: 48 83 3d 8f 00 20 00 00 cmpq \$0x0,0x20008f\(%rip\) # 2001d0 <_DYNAMIC\+0x80>
+- +[a-f0-9]+: 48 3b 0d 88 00 20 00 cmp 0x200088\(%rip\),%rcx # 2001d0 <_DYNAMIC\+0x80>
+- +[a-f0-9]+: 48 3b 0d 89 00 20 00 cmp 0x200089\(%rip\),%rcx # 2001d8 <_DYNAMIC\+0x88>
++ +[a-f0-9]+: ff 15 a8 00 20 00 callq \*0x2000a8\(%rip\) # 2001d0 <.*>
++ +[a-f0-9]+: ff 25 aa 00 20 00 jmpq \*0x2000aa\(%rip\) # 2001d8 <.*>
++ +[a-f0-9]+: 48 c7 05 9f 00 20 00 00 00 00 00 movq \$0x0,0x20009f\(%rip\) # 2001d8 <.*>
++ +[a-f0-9]+: 48 83 3d 8f 00 20 00 00 cmpq \$0x0,0x20008f\(%rip\) # 2001d0 <.*>
++ +[a-f0-9]+: 48 3b 0d 88 00 20 00 cmp 0x200088\(%rip\),%rcx # 2001d0 <.*>
++ +[a-f0-9]+: 48 3b 0d 89 00 20 00 cmp 0x200089\(%rip\),%rcx # 2001d8 <.*>
+ #pass
+diff --git a/ld/testsuite/ld-x86-64/pr20253-1l.d b/ld/testsuite/ld-x86-64/pr20253-1l.d
+index 0276558..83a61db 100644
+--- a/ld/testsuite/ld-x86-64/pr20253-1l.d
++++ b/ld/testsuite/ld-x86-64/pr20253-1l.d
+@@ -16,10 +16,10 @@ Disassembly of section .text:
+ +[a-f0-9]+: c3 retq
+
+ 0+15a <_start>:
+- +[a-f0-9]+: ff 15 98 00 20 00 callq \*0x200098\(%rip\) # 2001f8 <_DYNAMIC\+0x70>
+- +[a-f0-9]+: ff 25 9a 00 20 00 jmpq \*0x20009a\(%rip\) # 200200 <_DYNAMIC\+0x78>
+- +[a-f0-9]+: 48 c7 05 8f 00 20 00 00 00 00 00 movq \$0x0,0x20008f\(%rip\) # 200200 <_DYNAMIC\+0x78>
+- +[a-f0-9]+: 48 83 3d 7f 00 20 00 00 cmpq \$0x0,0x20007f\(%rip\) # 2001f8 <_DYNAMIC\+0x70>
+- +[a-f0-9]+: 48 3b 0d 78 00 20 00 cmp 0x200078\(%rip\),%rcx # 2001f8 <_DYNAMIC\+0x70>
+- +[a-f0-9]+: 48 3b 0d 79 00 20 00 cmp 0x200079\(%rip\),%rcx # 200200 <_DYNAMIC\+0x78>
++ +[a-f0-9]+: ff 15 98 00 20 00 callq \*0x200098\(%rip\) # 2001f8 <.*>
++ +[a-f0-9]+: ff 25 9a 00 20 00 jmpq \*0x20009a\(%rip\) # 200200 <.*>
++ +[a-f0-9]+: 48 c7 05 8f 00 20 00 00 00 00 00 movq \$0x0,0x20008f\(%rip\) # 200200 <.*>
++ +[a-f0-9]+: 48 83 3d 7f 00 20 00 00 cmpq \$0x0,0x20007f\(%rip\) # 2001f8 <.*>
++ +[a-f0-9]+: 48 3b 0d 78 00 20 00 cmp 0x200078\(%rip\),%rcx # 2001f8 <.*>
++ +[a-f0-9]+: 48 3b 0d 79 00 20 00 cmp 0x200079\(%rip\),%rcx # 200200 <.*>
+ #pass
+diff --git a/ld/testsuite/ld-x86-64/protected3.d b/ld/testsuite/ld-x86-64/protected3.d
+index d8f09da..0c60167 100644
+--- a/ld/testsuite/ld-x86-64/protected3.d
++++ b/ld/testsuite/ld-x86-64/protected3.d
+@@ -8,7 +8,7 @@
+ Disassembly of section .text:
+
+ 0+[a-f0-9]+ <bar>:
+-[ ]*[a-f0-9]+: 48 8b 05 ([0-9a-f]{2} ){4} * mov 0x[a-f0-9]+\(%rip\),%rax # [a-f0-9]+ <_DYNAMIC\+0x[a-f0-9]+>
++[ ]*[a-f0-9]+: 48 8b 05 ([0-9a-f]{2} ){4} * mov 0x[a-f0-9]+\(%rip\),%rax # [a-f0-9]+ <.*>
+ [ ]*[a-f0-9]+: 8b 00 mov \(%rax\),%eax
+ [ ]*[a-f0-9]+: c3 retq *
+ #pass
+diff --git a/ld/testsuite/ld-x86-64/tlsbin.dd b/ld/testsuite/ld-x86-64/tlsbin.dd
+index c89e7ee..6bc7ca2 100644
+--- a/ld/testsuite/ld-x86-64/tlsbin.dd
++++ b/ld/testsuite/ld-x86-64/tlsbin.dd
+@@ -24,7 +24,7 @@ Disassembly of section .text:
+ # GD -> IE because variable is not defined in executable
+ +[0-9a-f]+: 64 48 8b 04 25 00 00[ ]+mov %fs:0x0,%rax
+ +[0-9a-f]+: 00 00 *
+- +[0-9a-f]+: 48 03 05 ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <_DYNAMIC\+0x158>
++ +[0-9a-f]+: 48 03 05 ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <.*>
+ # -> R_X86_64_TPOFF64 sG1
+ +[0-9a-f]+: 90[ ]+nop *
+ +[0-9a-f]+: 90[ ]+nop *
+@@ -34,7 +34,7 @@ Disassembly of section .text:
+ # the variable is referenced through IE too
+ +[0-9a-f]+: 64 48 8b 04 25 00 00[ ]+mov %fs:0x0,%rax
+ +[0-9a-f]+: 00 00 *
+- +[0-9a-f]+: 48 03 05 ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <_DYNAMIC\+0x148>
++ +[0-9a-f]+: 48 03 05 ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <.*>
+ # -> R_X86_64_TPOFF64 sG2
+ +[0-9a-f]+: 90[ ]+nop *
+ +[0-9a-f]+: 90[ ]+nop *
+@@ -102,7 +102,7 @@ Disassembly of section .text:
+ +[0-9a-f]+: 00 00 *
+ +[0-9a-f]+: 90[ ]+nop *
+ +[0-9a-f]+: 90[ ]+nop *
+- +[0-9a-f]+: 4c 03 0d ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%r9 +# [0-9a-f]+ <_DYNAMIC\+0x148>
++ +[0-9a-f]+: 4c 03 0d ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%r9 +# [0-9a-f]+ <.*>
+ # -> R_X86_64_TPOFF64 sG2
+ +[0-9a-f]+: 90[ ]+nop *
+ +[0-9a-f]+: 90[ ]+nop *
+@@ -143,7 +143,7 @@ Disassembly of section .text:
+ +[0-9a-f]+: 90[ ]+nop *
+ # Direct access through %fs
+ # IE against global var
+- +[0-9a-f]+: 48 8b 0d ([0-9a-f]{2} ){4}[ ]+mov 0x[0-9a-f]+\(%rip\),%rcx +# [0-9a-f]+ <_DYNAMIC\+0x140>
++ +[0-9a-f]+: 48 8b 0d ([0-9a-f]{2} ){4}[ ]+mov 0x[0-9a-f]+\(%rip\),%rcx +# [0-9a-f]+ <.*>
+ # -> R_X86_64_TPOFF64 sG5
+ +[0-9a-f]+: 90[ ]+nop *
+ +[0-9a-f]+: 90[ ]+nop *
+@@ -183,7 +183,7 @@ Disassembly of section .text:
+ +[0-9a-f]+: 00 00 *
+ +[0-9a-f]+: 90[ ]+nop *
+ +[0-9a-f]+: 90[ ]+nop *
+- +[0-9a-f]+: 4c 03 1d ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%r11 +# [0-9a-f]+ <_DYNAMIC\+0x150>
++ +[0-9a-f]+: 4c 03 1d ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%r11 +# [0-9a-f]+ <.*>
+ # -> R_X86_64_TPOFF64 sG6
+ +[0-9a-f]+: 90[ ]+nop *
+ +[0-9a-f]+: 90[ ]+nop *
+diff --git a/ld/testsuite/ld-x86-64/tlsbin2.dd b/ld/testsuite/ld-x86-64/tlsbin2.dd
+index a73fcef..0010d38 100644
+--- a/ld/testsuite/ld-x86-64/tlsbin2.dd
++++ b/ld/testsuite/ld-x86-64/tlsbin2.dd
+@@ -24,7 +24,7 @@ Disassembly of section .text:
+ # GD -> IE because variable is not defined in executable
+ +[0-9a-f]+: 64 48 8b 04 25 00 00[ ]+mov %fs:0x0,%rax
+ +[0-9a-f]+: 00 00 *
+- +[0-9a-f]+: 48 03 05 ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <_DYNAMIC\+0x[0-9a-f]+>
++ +[0-9a-f]+: 48 03 05 ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <.*>
+ # -> R_X86_64_TPOFF64 sG1
+ +[0-9a-f]+: 90[ ]+nop *
+ +[0-9a-f]+: 90[ ]+nop *
+@@ -34,7 +34,7 @@ Disassembly of section .text:
+ # the variable is referenced through IE too
+ +[0-9a-f]+: 64 48 8b 04 25 00 00[ ]+mov %fs:0x0,%rax
+ +[0-9a-f]+: 00 00 *
+- +[0-9a-f]+: 48 03 05 ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <_DYNAMIC\+0x108>
++ +[0-9a-f]+: 48 03 05 ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <.*>
+ # -> R_X86_64_TPOFF64 sG2
+ +[0-9a-f]+: 90[ ]+nop *
+ +[0-9a-f]+: 90[ ]+nop *
+@@ -102,7 +102,7 @@ Disassembly of section .text:
+ +[0-9a-f]+: 00 00 *
+ +[0-9a-f]+: 90[ ]+nop *
+ +[0-9a-f]+: 90[ ]+nop *
+- +[0-9a-f]+: 4c 03 0d ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%r9 +# [0-9a-f]+ <_DYNAMIC\+0x108>
++ +[0-9a-f]+: 4c 03 0d ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%r9 +# [0-9a-f]+ <.*>
+ # -> R_X86_64_TPOFF64 sG2
+ +[0-9a-f]+: 90[ ]+nop *
+ +[0-9a-f]+: 90[ ]+nop *
+@@ -143,7 +143,7 @@ Disassembly of section .text:
+ +[0-9a-f]+: 90[ ]+nop *
+ # Direct access through %fs
+ # IE against global var
+- +[0-9a-f]+: 48 8b 0d ([0-9a-f]{2} ){4}[ ]+mov 0x[0-9a-f]+\(%rip\),%rcx +# [0-9a-f]+ <_DYNAMIC\+0x100>
++ +[0-9a-f]+: 48 8b 0d ([0-9a-f]{2} ){4}[ ]+mov 0x[0-9a-f]+\(%rip\),%rcx +# [0-9a-f]+ <.*>
+ # -> R_X86_64_TPOFF64 sG5
+ +[0-9a-f]+: 90[ ]+nop *
+ +[0-9a-f]+: 90[ ]+nop *
+@@ -183,7 +183,7 @@ Disassembly of section .text:
+ +[0-9a-f]+: 00 00 *
+ +[0-9a-f]+: 90[ ]+nop *
+ +[0-9a-f]+: 90[ ]+nop *
+- +[0-9a-f]+: 4c 03 1d ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%r11 +# [0-9a-f]+ <_DYNAMIC\+0x118>
++ +[0-9a-f]+: 4c 03 1d ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%r11 +# [0-9a-f]+ <.*>
+ # -> R_X86_64_TPOFF64 sG6
+ +[0-9a-f]+: 90[ ]+nop *
+ +[0-9a-f]+: 90[ ]+nop *
+diff --git a/ld/testsuite/ld-x86-64/tlsbindesc.dd b/ld/testsuite/ld-x86-64/tlsbindesc.dd
+index f77ebf2..50dc6d1 100644
+--- a/ld/testsuite/ld-x86-64/tlsbindesc.dd
++++ b/ld/testsuite/ld-x86-64/tlsbindesc.dd
+@@ -22,7 +22,7 @@ Disassembly of section .text:
+ +[0-9a-f]+: 55[ ]+push %rbp
+ +[0-9a-f]+: 48 89 e5[ ]+mov %rsp,%rbp
+ # GD -> IE because variable is not defined in executable
+- +[0-9a-f]+: 48 8b 05 ([0-9a-f]{2} ){4}[ ]+mov 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <_DYNAMIC\+0x118>
++ +[0-9a-f]+: 48 8b 05 ([0-9a-f]{2} ){4}[ ]+mov 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <.*>
+ # -> R_X86_64_TPOFF64 sG1
+ +[0-9a-f]+: 66 90[ ]+xchg %ax,%ax
+ +[0-9a-f]+: 90[ ]+nop *
+@@ -31,7 +31,7 @@ Disassembly of section .text:
+ +[0-9a-f]+: 90[ ]+nop *
+ # GD -> IE because variable is not defined in executable where
+ # the variable is referenced through IE too
+- +[0-9a-f]+: 48 8b 05 ([0-9a-f]{2} ){4}[ ]+mov 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <_DYNAMIC\+0x108>
++ +[0-9a-f]+: 48 8b 05 ([0-9a-f]{2} ){4}[ ]+mov 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <.*>
+ # -> R_X86_64_TPOFF64 sG2
+ +[0-9a-f]+: 66 90[ ]+xchg %ax,%ax
+ +[0-9a-f]+: 90[ ]+nop *
+@@ -93,7 +93,7 @@ Disassembly of section .text:
+ +[0-9a-f]+: 00 00 *
+ +[0-9a-f]+: 90[ ]+nop *
+ +[0-9a-f]+: 90[ ]+nop *
+- +[0-9a-f]+: 4c 03 0d ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%r9 +# [0-9a-f]+ <_DYNAMIC\+0x108>
++ +[0-9a-f]+: 4c 03 0d ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%r9 +# [0-9a-f]+ <.*>
+ # -> R_X86_64_TPOFF64 sG2
+ +[0-9a-f]+: 90[ ]+nop *
+ +[0-9a-f]+: 90[ ]+nop *
+@@ -134,7 +134,7 @@ Disassembly of section .text:
+ +[0-9a-f]+: 90[ ]+nop *
+ # Direct access through %fs
+ # IE against global var
+- +[0-9a-f]+: 48 8b 0d ([0-9a-f]{2} ){4}[ ]+mov 0x[0-9a-f]+\(%rip\),%rcx +# [0-9a-f]+ <_DYNAMIC\+0x100>
++ +[0-9a-f]+: 48 8b 0d ([0-9a-f]{2} ){4}[ ]+mov 0x[0-9a-f]+\(%rip\),%rcx +# [0-9a-f]+ <.*>
+ # -> R_X86_64_TPOFF64 sG5
+ +[0-9a-f]+: 90[ ]+nop *
+ +[0-9a-f]+: 90[ ]+nop *
+@@ -174,7 +174,7 @@ Disassembly of section .text:
+ +[0-9a-f]+: 00 00 *
+ +[0-9a-f]+: 90[ ]+nop *
+ +[0-9a-f]+: 90[ ]+nop *
+- +[0-9a-f]+: 4c 03 1d ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%r11 +# [0-9a-f]+ <_DYNAMIC\+0x110>
++ +[0-9a-f]+: 4c 03 1d ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%r11 +# [0-9a-f]+ <.*>
+ # -> R_X86_64_TPOFF64 sG6
+ +[0-9a-f]+: 90[ ]+nop *
+ +[0-9a-f]+: 90[ ]+nop *
+diff --git a/ld/testsuite/ld-x86-64/tlsdesc-nacl.pd b/ld/testsuite/ld-x86-64/tlsdesc-nacl.pd
+index eff90a8..f744f0e 100644
+--- a/ld/testsuite/ld-x86-64/tlsdesc-nacl.pd
++++ b/ld/testsuite/ld-x86-64/tlsdesc-nacl.pd
+@@ -25,7 +25,7 @@ Disassembly of section .plt:
+ +[0-9a-f]+: 00 *
+ +[0-9a-f]+: 66 90 xchg %ax,%ax
+ +[0-9a-f]+: ff 35 .. .. .. .. pushq 0x[0-9a-f]+\(%rip\) +# [0-9a-f]+ <_GLOBAL_OFFSET_TABLE_\+0x8>
+- +[0-9a-f]+: 4c 8b 1d .. .. .. .. mov 0x[0-9a-f]+\(%rip\),%r11 +# [0-9a-f]+ <_DYNAMIC\+0x190>
++ +[0-9a-f]+: 4c 8b 1d .. .. .. .. mov 0x[0-9a-f]+\(%rip\),%r11 +# [0-9a-f]+ <.*>
+ +[0-9a-f]+: 41 83 e3 e0 and \$0xffffffe0,%r11d
+ +[0-9a-f]+: 4d 01 fb add %r15,%r11
+ +[0-9a-f]+: 41 ff e3 jmpq \*%r11
+diff --git a/ld/testsuite/ld-x86-64/tlsdesc.dd b/ld/testsuite/ld-x86-64/tlsdesc.dd
+index a6f22b6..c9b1cf8 100644
+--- a/ld/testsuite/ld-x86-64/tlsdesc.dd
++++ b/ld/testsuite/ld-x86-64/tlsdesc.dd
+@@ -17,7 +17,7 @@ Disassembly of section .text:
+ +[0-9a-f]+: 90[ ]+nop *
+ +[0-9a-f]+: 90[ ]+nop *
+ # GD
+- +[0-9a-f]+: 48 8d 05 ([0-9a-f]{2} ){4}[ ]+lea 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <_GLOBAL_OFFSET_TABLE_\+0x48>
++ +[0-9a-f]+: 48 8d 05 ([0-9a-f]{2} ){4}[ ]+lea 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <.*>
+ # -> R_X86_64_TLSDESC sg1
+ +[0-9a-f]+: ff 10[ ]+callq \*\(%rax\)
+ +[0-9a-f]+: 90[ ]+nop *
+@@ -25,7 +25,7 @@ Disassembly of section .text:
+ +[0-9a-f]+: 90[ ]+nop *
+ +[0-9a-f]+: 90[ ]+nop *
+ # GD -> IE because variable is referenced through IE too
+- +[0-9a-f]+: 48 8b 05 ([0-9a-f]{2} ){4}[ ]+mov 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <_DYNAMIC\+0x180>
++ +[0-9a-f]+: 48 8b 05 ([0-9a-f]{2} ){4}[ ]+mov 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <.*>
+ # -> R_X86_64_TPOFF64 sg2
+ +[0-9a-f]+: 66 90[ ]+xchg %ax,%ax
+ +[0-9a-f]+: 90[ ]+nop *
+@@ -41,7 +41,7 @@ Disassembly of section .text:
+ +[0-9a-f]+: 90[ ]+nop *
+ +[0-9a-f]+: 90[ ]+nop *
+ # GD -> IE against local variable referenced through IE too
+- +[0-9a-f]+: 48 8b 05 ([0-9a-f]{2} ){4}[ ]+mov 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <_DYNAMIC\+0x150>
++ +[0-9a-f]+: 48 8b 05 ([0-9a-f]{2} ){4}[ ]+mov 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <.*>
+ # -> R_X86_64_TPOFF64 *ABS*+0x24
+ +[0-9a-f]+: 66 90[ ]+xchg %ax,%ax
+ +[0-9a-f]+: 90[ ]+nop *
+@@ -57,7 +57,7 @@ Disassembly of section .text:
+ +[0-9a-f]+: 90[ ]+nop *
+ +[0-9a-f]+: 90[ ]+nop *
+ # GD -> IE against hidden and local variable referenced through IE too
+- +[0-9a-f]+: 48 8b 05 ([0-9a-f]{2} ){4}[ ]+mov 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <_DYNAMIC\+0x188>
++ +[0-9a-f]+: 48 8b 05 ([0-9a-f]{2} ){4}[ ]+mov 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <.*>
+ # -> R_X86_64_TPOFF64 *ABS*+0x44
+ +[0-9a-f]+: 66 90[ ]+xchg %ax,%ax
+ +[0-9a-f]+: 90[ ]+nop *
+@@ -73,7 +73,7 @@ Disassembly of section .text:
+ +[0-9a-f]+: 90[ ]+nop *
+ +[0-9a-f]+: 90[ ]+nop *
+ # GD -> IE against hidden but not local variable referenced through IE too
+- +[0-9a-f]+: 48 8b 05 ([0-9a-f]{2} ){4}[ ]+mov 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <_DYNAMIC\+0x160>
++ +[0-9a-f]+: 48 8b 05 ([0-9a-f]{2} ){4}[ ]+mov 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <.*>
+ # -> R_X86_64_TPOFF64 *ABS*+0x64
+ +[0-9a-f]+: 66 90[ ]+xchg %ax,%ax
+ +[0-9a-f]+: 90[ ]+nop *
+@@ -115,7 +115,7 @@ Disassembly of section .text:
+ +[0-9a-f]+: 00 00 *
+ +[0-9a-f]+: 90[ ]+nop *
+ +[0-9a-f]+: 90[ ]+nop *
+- +[0-9a-f]+: 48 03 0d ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%rcx +# [0-9a-f]+ <_DYNAMIC\+0x180>
++ +[0-9a-f]+: 48 03 0d ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%rcx +# [0-9a-f]+ <.*>
+ # -> R_X86_64_TPOFF64 sg2
+ +[0-9a-f]+: 90[ ]+nop *
+ +[0-9a-f]+: 90[ ]+nop *
+@@ -126,7 +126,7 @@ Disassembly of section .text:
+ +[0-9a-f]+: 00 00 *
+ +[0-9a-f]+: 90[ ]+nop *
+ +[0-9a-f]+: 90[ ]+nop *
+- +[0-9a-f]+: 4c 03 35 ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%r14 +# [0-9a-f]+ <_DYNAMIC\+0x150>
++ +[0-9a-f]+: 4c 03 35 ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%r14 +# [0-9a-f]+ <.*>
+ # -> R_X86_64_TPOFF64 *ABS*+0x24
+ +[0-9a-f]+: 90[ ]+nop *
+ +[0-9a-f]+: 90[ ]+nop *
+@@ -137,7 +137,7 @@ Disassembly of section .text:
+ +[0-9a-f]+: 00 00 *
+ +[0-9a-f]+: 90[ ]+nop *
+ +[0-9a-f]+: 90[ ]+nop *
+- +[0-9a-f]+: 48 03 0d ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%rcx +# [0-9a-f]+ <_DYNAMIC\+0x188>
++ +[0-9a-f]+: 48 03 0d ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%rcx +# [0-9a-f]+ <.*>
+ # -> R_X86_64_TPOFF64 *ABS*+0x44
+ +[0-9a-f]+: 90[ ]+nop *
+ +[0-9a-f]+: 90[ ]+nop *
+@@ -148,7 +148,7 @@ Disassembly of section .text:
+ +[0-9a-f]+: 00 00 *
+ +[0-9a-f]+: 90[ ]+nop *
+ +[0-9a-f]+: 90[ ]+nop *
+- +[0-9a-f]+: 48 03 0d ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%rcx +# [0-9a-f]+ <_DYNAMIC\+0x160>
++ +[0-9a-f]+: 48 03 0d ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%rcx +# [0-9a-f]+ <.*>
+ # -> R_X86_64_TPOFF64 *ABS*+0x64
+ +[0-9a-f]+: 90[ ]+nop *
+ +[0-9a-f]+: 90[ ]+nop *
+@@ -156,7 +156,7 @@ Disassembly of section .text:
+ +[0-9a-f]+: 90[ ]+nop *
+ # Direct access through %fs
+ # IE against global var
+- +[0-9a-f]+: 48 8b 0d ([0-9a-f]{2} ){4}[ ]+mov 0x[0-9a-f]+\(%rip\),%rcx +# [0-9a-f]+ <_DYNAMIC\+0x168>
++ +[0-9a-f]+: 48 8b 0d ([0-9a-f]{2} ){4}[ ]+mov 0x[0-9a-f]+\(%rip\),%rcx +# [0-9a-f]+ <.*>
+ # -> R_X86_64_TPOFF64 sg5
+ +[0-9a-f]+: 90[ ]+nop *
+ +[0-9a-f]+: 90[ ]+nop *
+@@ -166,7 +166,7 @@ Disassembly of section .text:
+ +[0-9a-f]+: 90[ ]+nop *
+ +[0-9a-f]+: 90[ ]+nop *
+ # IE against local var
+- +[0-9a-f]+: 4c 8b 15 ([0-9a-f]{2} ){4}[ ]+mov 0x[0-9a-f]+\(%rip\),%r10 +# [0-9a-f]+ <_DYNAMIC\+0x158>
++ +[0-9a-f]+: 4c 8b 15 ([0-9a-f]{2} ){4}[ ]+mov 0x[0-9a-f]+\(%rip\),%r10 +# [0-9a-f]+ <.*>
+ # -> R_X86_64_TPOFF64 *ABS*+0x30
+ +[0-9a-f]+: 90[ ]+nop *
+ +[0-9a-f]+: 90[ ]+nop *
+@@ -176,7 +176,7 @@ Disassembly of section .text:
+ +[0-9a-f]+: 90[ ]+nop *
+ +[0-9a-f]+: 90[ ]+nop *
+ # IE against hidden and local var
+- +[0-9a-f]+: 48 8b 15 ([0-9a-f]{2} ){4}[ ]+mov 0x[0-9a-f]+\(%rip\),%rdx +# [0-9a-f]+ <_DYNAMIC\+0x170>
++ +[0-9a-f]+: 48 8b 15 ([0-9a-f]{2} ){4}[ ]+mov 0x[0-9a-f]+\(%rip\),%rdx +# [0-9a-f]+ <.*>
+ # -> R_X86_64_TPOFF64 *ABS*+0x50
+ +[0-9a-f]+: 90[ ]+nop *
+ +[0-9a-f]+: 90[ ]+nop *
+@@ -186,7 +186,7 @@ Disassembly of section .text:
+ +[0-9a-f]+: 90[ ]+nop *
+ +[0-9a-f]+: 90[ ]+nop *
+ # IE against hidden but not local var
+- +[0-9a-f]+: 48 8b 0d ([0-9a-f]{2} ){4}[ ]+mov 0x[0-9a-f]+\(%rip\),%rcx +# [0-9a-f]+ <_DYNAMIC\+0x178>
++ +[0-9a-f]+: 48 8b 0d ([0-9a-f]{2} ){4}[ ]+mov 0x[0-9a-f]+\(%rip\),%rcx +# [0-9a-f]+ <.*>
+ # -> R_X86_64_TPOFF64 *ABS*+0x70
+ +[0-9a-f]+: 90[ ]+nop *
+ +[0-9a-f]+: 90[ ]+nop *
+diff --git a/ld/testsuite/ld-x86-64/tlsdesc.pd b/ld/testsuite/ld-x86-64/tlsdesc.pd
+index c24403c..0fa36f3 100644
+--- a/ld/testsuite/ld-x86-64/tlsdesc.pd
++++ b/ld/testsuite/ld-x86-64/tlsdesc.pd
+@@ -14,6 +14,6 @@ Disassembly of section .plt:
+ [0-9a-f]+: ff 25 .. .. 20 00 jmpq \*.*\(%rip\) # 201360 <_GLOBAL_OFFSET_TABLE_\+0x10>
+ [0-9a-f]+: 0f 1f 40 00 nopl 0x0\(%rax\)
+ [0-9a-f]+: ff 35 .. .. 20 00 pushq .*\(%rip\) # 201358 <_GLOBAL_OFFSET_TABLE_\+0x8>
+- [0-9a-f]+: ff 25 .. .. 20 00 jmpq \*.*\(%rip\) # 201348 <_DYNAMIC\+0x190>
++ [0-9a-f]+: ff 25 .. .. 20 00 jmpq \*.*\(%rip\) # 201348 <.*>
+ [0-9a-f]+: 0f 1f 40 00 nopl 0x0\(%rax\)
+
+diff --git a/ld/testsuite/ld-x86-64/tlsgd10.dd b/ld/testsuite/ld-x86-64/tlsgd10.dd
+index 448015e..6c3ca5c 100644
+--- a/ld/testsuite/ld-x86-64/tlsgd10.dd
++++ b/ld/testsuite/ld-x86-64/tlsgd10.dd
+@@ -15,7 +15,7 @@ Disassembly of section .text:
+ [ ]*[a-f0-9]+: 4c 8d 3d eb ff ff ff lea -0x15\(%rip\),%r15 # [0-9a-f]+ <_start>
+ [ ]*[a-f0-9]+: 4d 01 df add %r11,%r15
+ [ ]*[a-f0-9]+: 64 48 8b 04 25 00 00 00 00 mov %fs:0x0,%rax
+-[ ]*[a-f0-9]+: 48 03 05 ([0-9a-f]{2} ){4} add 0x[0-9a-f]+\(%rip\),%rax # [0-9a-f]+ <_DYNAMIC\+0x140>
++[ ]*[a-f0-9]+: 48 03 05 ([0-9a-f]{2} ){4} add 0x[0-9a-f]+\(%rip\),%rax # [0-9a-f]+ <.*>
+ [ ]*[a-f0-9]+: 66 0f 1f 44 00 00 nopw 0x0\(%rax,%rax,1\)
+ [ ]*[a-f0-9]+: 41 5f pop %r15
+ [ ]*[a-f0-9]+: 41 5f pop %r15
+diff --git a/ld/testsuite/ld-x86-64/tlsgd5.dd b/ld/testsuite/ld-x86-64/tlsgd5.dd
+index 54cf357..c2e2621 100644
+--- a/ld/testsuite/ld-x86-64/tlsgd5.dd
++++ b/ld/testsuite/ld-x86-64/tlsgd5.dd
+@@ -10,5 +10,5 @@ Disassembly of section .text:
+
+ [a-f0-9]+ <_start>:
+ [ ]*[a-f0-9]+: 64 48 8b 04 25 00 00 00 00 mov %fs:0x0,%rax
+-[ ]*[a-f0-9]+: 48 03 05 ([0-9a-f]{2} ){4} * add 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <_DYNAMIC\+0x[a-f0-9]+>
++[ ]*[a-f0-9]+: 48 03 05 ([0-9a-f]{2} ){4} * add 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <.*>
+ #pass
+diff --git a/ld/testsuite/ld-x86-64/tlsgd6.dd b/ld/testsuite/ld-x86-64/tlsgd6.dd
+index 2cbfda6..08e3b99 100644
+--- a/ld/testsuite/ld-x86-64/tlsgd6.dd
++++ b/ld/testsuite/ld-x86-64/tlsgd6.dd
+@@ -10,5 +10,5 @@ Disassembly of section .text:
+
+ [a-f0-9]+ <_start>:
+ [ ]*[a-f0-9]+: 64 8b 04 25 00 00 00 00 mov %fs:0x0,%eax
+-[ ]*[a-f0-9]+: 48 03 05 ([0-9a-f]{2} ){4} * add 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <_DYNAMIC\+0x[a-f0-9]+>
++[ ]*[a-f0-9]+: 48 03 05 ([0-9a-f]{2} ){4} * add 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <foo>
+ #pass
+diff --git a/ld/testsuite/ld-x86-64/tlsgd8.dd b/ld/testsuite/ld-x86-64/tlsgd8.dd
+index 1055052..2bb1132 100644
+--- a/ld/testsuite/ld-x86-64/tlsgd8.dd
++++ b/ld/testsuite/ld-x86-64/tlsgd8.dd
+@@ -15,7 +15,7 @@ Disassembly of section .text:
+ [ ]*[a-f0-9]+: 48 8d 1d ed ff ff ff lea -0x13\(%rip\),%rbx # [0-9a-f]+ <_start>
+ [ ]*[a-f0-9]+: 4c 01 db add %r11,%rbx
+ [ ]*[a-f0-9]+: 64 48 8b 04 25 00 00 00 00 mov %fs:0x0,%rax
+-[ ]*[a-f0-9]+: 48 03 05 ([0-9a-f]{2} ){4} add 0x[0-9a-f]+\(%rip\),%rax # [0-9a-f]+ <_DYNAMIC\+0x140>
++[ ]*[a-f0-9]+: 48 03 05 ([0-9a-f]{2} ){4} add 0x[0-9a-f]+\(%rip\),%rax # [0-9a-f]+ <foo>
+ [ ]*[a-f0-9]+: 66 0f 1f 44 00 00 nopw 0x0\(%rax,%rax,1\)
+ [ ]*[a-f0-9]+: 5b pop %rbx
+ [ ]*[a-f0-9]+: 5b pop %rbx
+diff --git a/ld/testsuite/ld-x86-64/tlsgdesc.dd b/ld/testsuite/ld-x86-64/tlsgdesc.dd
+index a983a75..d0a274b 100644
+--- a/ld/testsuite/ld-x86-64/tlsgdesc.dd
++++ b/ld/testsuite/ld-x86-64/tlsgdesc.dd
+@@ -20,7 +20,7 @@ Disassembly of section .text:
+ +[0-9a-f]+: 00 00 *
+ +[0-9a-f]+: 90[ ]+nop *
+ +[0-9a-f]+: 90[ ]+nop *
+- +[0-9a-f]+: 48 03 0d ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%rcx +# [0-9a-f]+ <_DYNAMIC\+0x150>
++ +[0-9a-f]+: 48 03 0d ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%rcx +# [0-9a-f]+ <.*>
+ # -> R_X86_64_TPOFF64 sG3
+ +[0-9a-f]+: 90[ ]+nop *
+ +[0-9a-f]+: 90[ ]+nop *
+@@ -31,14 +31,14 @@ Disassembly of section .text:
+ +[0-9a-f]+: 00 00 *
+ +[0-9a-f]+: 90[ ]+nop *
+ +[0-9a-f]+: 90[ ]+nop *
+- +[0-9a-f]+: 48 03 0d ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%rcx +# [0-9a-f]+ <_DYNAMIC\+0x170>
++ +[0-9a-f]+: 48 03 0d ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%rcx +# [0-9a-f]+ <.*>
+ # -> R_X86_64_TPOFF64 sG4
+ +[0-9a-f]+: 90[ ]+nop *
+ +[0-9a-f]+: 90[ ]+nop *
+ +[0-9a-f]+: 90[ ]+nop *
+ +[0-9a-f]+: 90[ ]+nop *
+ # GD, gd first
+- +[0-9a-f]+: 66 48 8d 3d ([0-9a-f]{2} ){3}[ ]+data16 lea 0x[0-9a-f]+\(%rip\),%rdi +# [0-9a-f]+ <_DYNAMIC\+0x180>
++ +[0-9a-f]+: 66 48 8d 3d ([0-9a-f]{2} ){3}[ ]+data16 lea 0x[0-9a-f]+\(%rip\),%rdi +# [0-9a-f]+ <.*>
+ +[0-9a-f]+: [0-9a-f]{2} *
+ # -> R_X86_64_DTPMOD64 sG1
+ +[0-9a-f]+: 66 66 48 e8 ([0-9a-f]{2} ){3}[ ]+data16 data16 rex.W callq [0-9a-f]+ <__tls_get_addr@plt>
+@@ -48,7 +48,7 @@ Disassembly of section .text:
+ +[0-9a-f]+: 90[ ]+nop *
+ +[0-9a-f]+: 90[ ]+nop *
+ +[0-9a-f]+: 90[ ]+nop *
+- +[0-9a-f]+: 48 8d 05 ([0-9a-f]{2} ){4}[ ]+lea 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <_GLOBAL_OFFSET_TABLE_\+0x30>
++ +[0-9a-f]+: 48 8d 05 ([0-9a-f]{2} ){4}[ ]+lea 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <.*>
+ # -> R_X86_64_TLSDESC sG1
+ +[0-9a-f]+: ff 10[ ]+callq \*\(%rax\)
+ +[0-9a-f]+: 90[ ]+nop *
+@@ -56,14 +56,14 @@ Disassembly of section .text:
+ +[0-9a-f]+: 90[ ]+nop *
+ +[0-9a-f]+: 90[ ]+nop *
+ # GD, desc first
+- +[0-9a-f]+: 48 8d 05 ([0-9a-f]{2} ){4}[ ]+lea 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <_GLOBAL_OFFSET_TABLE_\+0x20>
++ +[0-9a-f]+: 48 8d 05 ([0-9a-f]{2} ){4}[ ]+lea 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <.*>
+ # -> R_X86_64_TLSDESC sG2
+ +[0-9a-f]+: ff 10[ ]+callq \*\(%rax\)
+ +[0-9a-f]+: 90[ ]+nop *
+ +[0-9a-f]+: 90[ ]+nop *
+ +[0-9a-f]+: 90[ ]+nop *
+ +[0-9a-f]+: 90[ ]+nop *
+- +[0-9a-f]+: 66 48 8d 3d ([0-9a-f]{2} ){3}[ ]+data16 lea 0x[0-9a-f]+\(%rip\),%rdi +# [0-9a-f]+ <_DYNAMIC\+0x160>
++ +[0-9a-f]+: 66 48 8d 3d ([0-9a-f]{2} ){3}[ ]+data16 lea 0x[0-9a-f]+\(%rip\),%rdi +# [0-9a-f]+ <.*>
+ +[0-9a-f]+: [0-9a-f]{2} *
+ # -> R_X86_64_DTPMOD64 sG2
+ +[0-9a-f]+: 66 66 48 e8 ([0-9a-f]{2} ){3}[ ]+data16 data16 rex.W callq [0-9a-f]+ <__tls_get_addr@plt>
+@@ -76,13 +76,13 @@ Disassembly of section .text:
+ # GD -> IE, gd first, after IE use
+ +[0-9a-f]+: 64 48 8b 04 25 00 00[ ]+mov %fs:0x0,%rax
+ +[0-9a-f]+: 00 00 *
+- +[0-9a-f]+: 48 03 05 ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <_DYNAMIC\+0x150>
++ +[0-9a-f]+: 48 03 05 ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <.*>
+ # -> R_X86_64_TPOFF64 sG3
+ +[0-9a-f]+: 90[ ]+nop *
+ +[0-9a-f]+: 90[ ]+nop *
+ +[0-9a-f]+: 90[ ]+nop *
+ +[0-9a-f]+: 90[ ]+nop *
+- +[0-9a-f]+: 48 8b 05 ([0-9a-f]{2} ){4}[ ]+mov 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <_DYNAMIC\+0x150>
++ +[0-9a-f]+: 48 8b 05 ([0-9a-f]{2} ){4}[ ]+mov 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <.*>
+ # -> R_X86_64_TPOFF64 sG3
+ +[0-9a-f]+: 66 90[ ]+xchg %ax,%ax
+ +[0-9a-f]+: 90[ ]+nop *
+@@ -90,7 +90,7 @@ Disassembly of section .text:
+ +[0-9a-f]+: 90[ ]+nop *
+ +[0-9a-f]+: 90[ ]+nop *
+ # GD -> IE, desc first, after IE use
+- +[0-9a-f]+: 48 8b 05 ([0-9a-f]{2} ){4}[ ]+mov 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <_DYNAMIC\+0x170>
++ +[0-9a-f]+: 48 8b 05 ([0-9a-f]{2} ){4}[ ]+mov 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <.*>
+ # -> R_X86_64_TPOFF64 sG4
+ +[0-9a-f]+: 66 90[ ]+xchg %ax,%ax
+ +[0-9a-f]+: 90[ ]+nop *
+@@ -99,7 +99,7 @@ Disassembly of section .text:
+ +[0-9a-f]+: 90[ ]+nop *
+ +[0-9a-f]+: 64 48 8b 04 25 00 00[ ]+mov %fs:0x0,%rax
+ +[0-9a-f]+: 00 00 *
+- +[0-9a-f]+: 48 03 05 ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <_DYNAMIC\+0x170>
++ +[0-9a-f]+: 48 03 05 ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <.*>
+ # -> R_X86_64_TPOFF64 sG4
+ +[0-9a-f]+: 90[ ]+nop *
+ +[0-9a-f]+: 90[ ]+nop *
+@@ -108,13 +108,13 @@ Disassembly of section .text:
+ # GD -> IE, gd first, before IE use
+ +[0-9a-f]+: 64 48 8b 04 25 00 00[ ]+mov %fs:0x0,%rax
+ +[0-9a-f]+: 00 00 *
+- +[0-9a-f]+: 48 03 05 ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <_DYNAMIC\+0x158>
++ +[0-9a-f]+: 48 03 05 ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <.*>
+ # -> R_X86_64_TPOFF64 sG5
+ +[0-9a-f]+: 90[ ]+nop *
+ +[0-9a-f]+: 90[ ]+nop *
+ +[0-9a-f]+: 90[ ]+nop *
+ +[0-9a-f]+: 90[ ]+nop *
+- +[0-9a-f]+: 48 8b 05 ([0-9a-f]{2} ){4}[ ]+mov 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <_DYNAMIC\+0x158>
++ +[0-9a-f]+: 48 8b 05 ([0-9a-f]{2} ){4}[ ]+mov 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <.*>
+ # -> R_X86_64_TPOFF64 sG5
+ +[0-9a-f]+: 66 90[ ]+xchg %ax,%ax
+ +[0-9a-f]+: 90[ ]+nop *
+@@ -122,7 +122,7 @@ Disassembly of section .text:
+ +[0-9a-f]+: 90[ ]+nop *
+ +[0-9a-f]+: 90[ ]+nop *
+ # GD -> IE, desc first, before IE use
+- +[0-9a-f]+: 48 8b 05 ([0-9a-f]{2} ){4}[ ]+mov 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <_DYNAMIC\+0x178>
++ +[0-9a-f]+: 48 8b 05 ([0-9a-f]{2} ){4}[ ]+mov 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <.*>
+ # -> R_X86_64_TPOFF64 sG6
+ +[0-9a-f]+: 66 90[ ]+xchg %ax,%ax
+ +[0-9a-f]+: 90[ ]+nop *
+@@ -131,7 +131,7 @@ Disassembly of section .text:
+ +[0-9a-f]+: 90[ ]+nop *
+ +[0-9a-f]+: 64 48 8b 04 25 00 00[ ]+mov %fs:0x0,%rax
+ +[0-9a-f]+: 00 00 *
+- +[0-9a-f]+: 48 03 05 ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <_DYNAMIC\+0x178>
++ +[0-9a-f]+: 48 03 05 ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <.*>
+ # -> R_X86_64_TPOFF64 sG6
+ +[0-9a-f]+: 90[ ]+nop *
+ +[0-9a-f]+: 90[ ]+nop *
+@@ -142,7 +142,7 @@ Disassembly of section .text:
+ +[0-9a-f]+: 00 00 *
+ +[0-9a-f]+: 90[ ]+nop *
+ +[0-9a-f]+: 90[ ]+nop *
+- +[0-9a-f]+: 48 03 0d ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%rcx +# [0-9a-f]+ <_DYNAMIC\+0x158>
++ +[0-9a-f]+: 48 03 0d ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%rcx +# [0-9a-f]+ <.*>
+ # -> R_X86_64_TPOFF64 sG5
+ +[0-9a-f]+: 90[ ]+nop *
+ +[0-9a-f]+: 90[ ]+nop *
+@@ -153,7 +153,7 @@ Disassembly of section .text:
+ +[0-9a-f]+: 00 00 *
+ +[0-9a-f]+: 90[ ]+nop *
+ +[0-9a-f]+: 90[ ]+nop *
+- +[0-9a-f]+: 48 03 0d ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%rcx +# [0-9a-f]+ <_DYNAMIC\+0x178>
++ +[0-9a-f]+: 48 03 0d ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%rcx +# [0-9a-f]+ <.*>
+ # -> R_X86_64_TPOFF64 sG6
+ +[0-9a-f]+: 90[ ]+nop *
+ +[0-9a-f]+: 90[ ]+nop *
+diff --git a/ld/testsuite/ld-x86-64/tlspic.dd b/ld/testsuite/ld-x86-64/tlspic.dd
+index bf3ba69..88026c1 100644
+--- a/ld/testsuite/ld-x86-64/tlspic.dd
++++ b/ld/testsuite/ld-x86-64/tlspic.dd
+@@ -17,7 +17,7 @@ Disassembly of section .text:
+ +1006: 90[ ]+nop *
+ +1007: 90[ ]+nop *
+ # GD
+- +1008: 66 48 8d 3d ([0-9a-f]{2} ){3}[ ]+data16 lea 0x[0-9a-f]+\(%rip\),%rdi +# [0-9a-f]+ <_DYNAMIC\+0x180>
++ +1008: 66 48 8d 3d ([0-9a-f]{2} ){3}[ ]+data16 lea 0x[0-9a-f]+\(%rip\),%rdi +# [0-9a-f]+ <.*>
+ +100f: [0-9a-f ]+
+ # -> R_X86_64_DTPMOD64 sg1
+ +1010: 66 66 48 e8 [0-9a-f ]+data16 data16 rex.W callq [0-9a-f]+ <.*>
+@@ -30,14 +30,14 @@ Disassembly of section .text:
+ # GD -> IE because variable is referenced through IE too
+ +101c: 64 48 8b 04 25 00 00[ ]+mov %fs:0x0,%rax
+ +1023: 00 00 *
+- +1025: 48 03 05 ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <_DYNAMIC\+0x1a0>
++ +1025: 48 03 05 ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <.*>
+ # -> R_X86_64_TPOFF64 sg2
+ +102c: 90[ ]+nop *
+ +102d: 90[ ]+nop *
+ +102e: 90[ ]+nop *
+ +102f: 90[ ]+nop *
+ # GD against local variable
+- +1030: 66 48 8d 3d ([0-9a-f]{2} ){3}[ ]+data16 lea 0x[0-9a-f]+\(%rip\),%rdi +# [0-9a-f]+ <_DYNAMIC\+0x130>
++ +1030: 66 48 8d 3d ([0-9a-f]{2} ){3}[ ]+data16 lea 0x[0-9a-f]+\(%rip\),%rdi +# [0-9a-f]+ <.*>
+ +1037: [0-9a-f ]+
+ # -> R_X86_64_DTPMOD64 [0 0x2000000000000000]
+ +1038: 66 66 48 e8 [0-9a-f ]+data16 data16 rex.W callq [0-9a-f]+ <.*>
+@@ -50,14 +50,14 @@ Disassembly of section .text:
+ # GD -> IE against local variable referenced through IE too
+ +1044: 64 48 8b 04 25 00 00[ ]+mov %fs:0x0,%rax
+ +104b: 00 00 *
+- +104d: 48 03 05 ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <_DYNAMIC\+0x140>
++ +104d: 48 03 05 ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <.*>
+ # -> R_X86_64_TPOFF64 *ABS*+0x24
+ +1054: 90[ ]+nop *
+ +1055: 90[ ]+nop *
+ +1056: 90[ ]+nop *
+ +1057: 90[ ]+nop *
+ # GD against hidden and local variable
+- +1058: 66 48 8d 3d ([0-9a-f]{2} ){3}[ ]+data16 lea 0x[0-9a-f]+\(%rip\),%rdi +# [0-9a-f]+ <_DYNAMIC\+0x1a8>
++ +1058: 66 48 8d 3d ([0-9a-f]{2} ){3}[ ]+data16 lea 0x[0-9a-f]+\(%rip\),%rdi +# [0-9a-f]+ <.*>
+ +105f: [0-9a-f ]+
+ # -> R_X86_64_DTPMOD64 [0 0x4000000000000000]
+ +1060: 66 66 48 e8 [0-9a-f ]+data16 data16 rex.W callq [0-9a-f]+ <.*>
+@@ -70,14 +70,14 @@ Disassembly of section .text:
+ # GD -> IE against hidden and local variable referenced through IE too
+ +106c: 64 48 8b 04 25 00 00[ ]+mov %fs:0x0,%rax
+ +1073: 00 00 *
+- +1075: 48 03 05 ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <_DYNAMIC\+0x1b8>
++ +1075: 48 03 05 ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <.*>
+ # -> R_X86_64_TPOFF64 *ABS*+0x44
+ +107c: 90[ ]+nop *
+ +107d: 90[ ]+nop *
+ +107e: 90[ ]+nop *
+ +107f: 90[ ]+nop *
+ # GD against hidden but not local variable
+- +1080: 66 48 8d 3d ([0-9a-f]{2} ){3}[ ]+data16 lea 0x[0-9a-f]+\(%rip\),%rdi +# [0-9a-f]+ <_DYNAMIC\+0x160>
++ +1080: 66 48 8d 3d ([0-9a-f]{2} ){3}[ ]+data16 lea 0x[0-9a-f]+\(%rip\),%rdi +# [0-9a-f]+ <.*>
+ +1087: [0-9a-f ]+
+ # -> R_X86_64_DTPMOD64 [0 0x6000000000000000]
+ +1088: 66 66 48 e8 [0-9a-f ]+data16 data16 rex.W callq [0-9a-f]+ <.*>
+@@ -90,14 +90,14 @@ Disassembly of section .text:
+ # GD -> IE against hidden but not local variable referenced through IE too
+ +1094: 64 48 8b 04 25 00 00[ ]+mov %fs:0x0,%rax
+ +109b: 00 00 *
+- +109d: 48 03 05 ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <_DYNAMIC\+0x170>
++ +109d: 48 03 05 ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <.*>
+ # -> R_X86_64_TPOFF64 *ABS*+0x64
+ +10a4: 90[ ]+nop *
+ +10a5: 90[ ]+nop *
+ +10a6: 90[ ]+nop *
+ +10a7: 90[ ]+nop *
+ # LD
+- +10a8: 48 8d 3d ([0-9a-f]{2} ){4}[ ]+lea 0x[0-9a-f]+\(%rip\),%rdi +# [0-9a-f]+ <_DYNAMIC\+0x150>
++ +10a8: 48 8d 3d ([0-9a-f]{2} ){4}[ ]+lea 0x[0-9a-f]+\(%rip\),%rdi +# [0-9a-f]+ <.*>
+ # -> R_X86_64_DTPMOD64 [0 0x000000000000000]
+ +10af: e8 [0-9a-f ]+callq [0-9a-f]+ <.*>
+ # -> R_X86_64_JUMP_SLOT __tls_get_addr
+@@ -112,7 +112,7 @@ Disassembly of section .text:
+ +10c8: 90[ ]+nop *
+ +10c9: 90[ ]+nop *
+ # LD against hidden and local variables
+- +10ca: 48 8d 3d ([0-9a-f]{2} ){4}[ ]+lea 0x[0-9a-f]+\(%rip\),%rdi +# [0-9a-f]+ <_DYNAMIC\+0x150>
++ +10ca: 48 8d 3d ([0-9a-f]{2} ){4}[ ]+lea 0x[0-9a-f]+\(%rip\),%rdi +# [0-9a-f]+ <.*>
+ # -> R_X86_64_DTPMOD64 [0 0x000000000000000]
+ +10d1: e8 [0-9a-f ]+callq [0-9a-f]+ <.*>
+ # -> R_X86_64_JUMP_SLOT __tls_get_addr
+@@ -127,7 +127,7 @@ Disassembly of section .text:
+ +10ea: 90[ ]+nop *
+ +10eb: 90[ ]+nop *
+ # LD against hidden but not local variables
+- +10ec: 48 8d 3d ([0-9a-f]{2} ){4}[ ]+lea 0x[0-9a-f]+\(%rip\),%rdi +# [0-9a-f]+ <_DYNAMIC\+0x150>
++ +10ec: 48 8d 3d ([0-9a-f]{2} ){4}[ ]+lea 0x[0-9a-f]+\(%rip\),%rdi +# [0-9a-f]+ <.*>
+ # -> R_X86_64_DTPMOD64 [0 0x000000000000000]
+ +10f3: e8 [0-9a-f ]+callq [0-9a-f]+ <.*>
+ # -> R_X86_64_JUMP_SLOT __tls_get_addr
+@@ -144,7 +144,7 @@ Disassembly of section .text:
+ +1113: 00 00 *
+ +1115: 90[ ]+nop *
+ +1116: 90[ ]+nop *
+- +1117: 48 03 0d ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%rcx +# [0-9a-f]+ <_DYNAMIC\+0x1a0>
++ +1117: 48 03 0d ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%rcx +# [0-9a-f]+ <.*>
+ # -> R_X86_64_TPOFF64 sg2
+ +111e: 90[ ]+nop *
+ +111f: 90[ ]+nop *
+@@ -155,7 +155,7 @@ Disassembly of section .text:
+ +1129: 00 00 *
+ +112b: 90[ ]+nop *
+ +112c: 90[ ]+nop *
+- +112d: 4c 03 35 ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%r14 +# [0-9a-f]+ <_DYNAMIC\+0x140>
++ +112d: 4c 03 35 ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%r14 +# [0-9a-f]+ <.*>
+ # -> R_X86_64_TPOFF64 *ABS*+0x24
+ +1134: 90[ ]+nop *
+ +1135: 90[ ]+nop *
+@@ -166,7 +166,7 @@ Disassembly of section .text:
+ +113f: 00 00 *
+ +1141: 90[ ]+nop *
+ +1142: 90[ ]+nop *
+- +1143: 48 03 0d ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%rcx +# [0-9a-f]+ <_DYNAMIC\+0x1b8>
++ +1143: 48 03 0d ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%rcx +# [0-9a-f]+ <.*>
+ # -> R_X86_64_TPOFF64 *ABS*+0x44
+ +114a: 90[ ]+nop *
+ +114b: 90[ ]+nop *
+@@ -177,7 +177,7 @@ Disassembly of section .text:
+ +1155: 00 00 *
+ +1157: 90[ ]+nop *
+ +1158: 90[ ]+nop *
+- +1159: 48 03 0d ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%rcx +# [0-9a-f]+ <_DYNAMIC\+0x170>
++ +1159: 48 03 0d ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%rcx +# [0-9a-f]+ <.*>
+ # -> R_X86_64_TPOFF64 *ABS*+0x64
+ +1160: 90[ ]+nop *
+ +1161: 90[ ]+nop *
+@@ -185,7 +185,7 @@ Disassembly of section .text:
+ +1163: 90[ ]+nop *
+ # Direct access through %fs
+ # IE against global var
+- +1164: 48 8b 0d ([0-9a-f]{2} ){4}[ ]+mov 0x[0-9a-f]+\(%rip\),%rcx +# [0-9a-f]+ <_DYNAMIC\+0x178>
++ +1164: 48 8b 0d ([0-9a-f]{2} ){4}[ ]+mov 0x[0-9a-f]+\(%rip\),%rcx +# [0-9a-f]+ <.*>
+ # -> R_X86_64_TPOFF64 sg5
+ +116b: 90[ ]+nop *
+ +116c: 90[ ]+nop *
+@@ -195,7 +195,7 @@ Disassembly of section .text:
+ +1173: 90[ ]+nop *
+ +1174: 90[ ]+nop *
+ # IE against local var
+- +1175: 4c 8b 15 ([0-9a-f]{2} ){4}[ ]+mov 0x[0-9a-f]+\(%rip\),%r10 +# [0-9a-f]+ <_DYNAMIC\+0x148>
++ +1175: 4c 8b 15 ([0-9a-f]{2} ){4}[ ]+mov 0x[0-9a-f]+\(%rip\),%r10 +# [0-9a-f]+ <.*>
+ # -> R_X86_64_TPOFF64 *ABS*+0x30
+ +117c: 90[ ]+nop *
+ +117d: 90[ ]+nop *
+@@ -205,7 +205,7 @@ Disassembly of section .text:
+ +1184: 90[ ]+nop *
+ +1185: 90[ ]+nop *
+ # IE against hidden and local var
+- +1186: 48 8b 15 ([0-9a-f]{2} ){4}[ ]+mov 0x[0-9a-f]+\(%rip\),%rdx +# [0-9a-f]+ <_DYNAMIC\+0x190>
++ +1186: 48 8b 15 ([0-9a-f]{2} ){4}[ ]+mov 0x[0-9a-f]+\(%rip\),%rdx +# [0-9a-f]+ <.*>
+ # -> R_X86_64_TPOFF64 *ABS*+0x50
+ +118d: 90[ ]+nop *
+ +118e: 90[ ]+nop *
+@@ -215,7 +215,7 @@ Disassembly of section .text:
+ +1195: 90[ ]+nop *
+ +1196: 90[ ]+nop *
+ # IE against hidden but not local var
+- +1197: 48 8b 0d ([0-9a-f]{2} ){4}[ ]+mov 0x[0-9a-f]+\(%rip\),%rcx +# [0-9a-f]+ <_DYNAMIC\+0x198>
++ +1197: 48 8b 0d ([0-9a-f]{2} ){4}[ ]+mov 0x[0-9a-f]+\(%rip\),%rcx +# [0-9a-f]+ <.*>
+ # -> R_X86_64_TPOFF64 *ABS*+0x70
+ +119e: 90[ ]+nop *
+ +119f: 90[ ]+nop *
+@@ -237,7 +237,7 @@ Disassembly of section .text:
+ # -mcmodel=large sequences
+ #
+ # -mcmodel=large GD
+- +11c2: 48 8d 3d ([0-9a-f]{2} ){4}[ ]+lea 0x[0-9a-f]+\(%rip\),%rdi +# [0-9a-f]+ <_DYNAMIC\+0x180>
++ +11c2: 48 8d 3d ([0-9a-f]{2} ){4}[ ]+lea 0x[0-9a-f]+\(%rip\),%rdi +# [0-9a-f]+ <.*>
+ # -> R_X86_64_DTPMOD64 sg1
+ +11c9: 48 b8 ([0-9a-f]{2} ){5}[ ]+movabs \$0x[0-9a-f]+,%rax
+ # -> R_X86_64_JUMP_SLOT __tls_get_addr
+@@ -252,7 +252,7 @@ Disassembly of section .text:
+ # -> R_X86_64_TPOFF64 sg2
+ +11dc: 64 48 8b 04 25 00 00[ ]+mov %fs:0x0,%rax
+ +11e3: 00 00
+- +11e5: 48 03 05 ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <_DYNAMIC\+0x1a0>
++ +11e5: 48 03 05 ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <.*>
+ # -> R_X86_64_TPOFF64 sg2
+ +11ec: 66 0f 1f 44 00 00[ ]+nopw 0x0\(%rax,%rax,1\)
+ +11f2: 90[ ]+nop *
+@@ -260,7 +260,7 @@ Disassembly of section .text:
+ +11f4: 90[ ]+nop *
+ +11f5: 90[ ]+nop *
+ # -mcmodel=large GD against local variable
+- +11f6: 48 8d 3d ([0-9a-f]{2} ){4}[ ]+lea 0x[0-9a-f]+\(%rip\),%rdi +# [0-9a-f]+ <_DYNAMIC\+0x130>
++ +11f6: 48 8d 3d ([0-9a-f]{2} ){4}[ ]+lea 0x[0-9a-f]+\(%rip\),%rdi +# [0-9a-f]+ <.*>
+ # -> R_X86_64_DTPMOD64 [0 0x2000000000000000]
+ +11fd: 48 b8 ([0-9a-f]{2} ){5}[ ]+movabs \$0x[0-9a-f]+,%rax
+ # -> R_X86_64_JUMP_SLOT __tls_get_addr
+@@ -274,7 +274,7 @@ Disassembly of section .text:
+ # -mcmodel=large GD -> IE against local variable referenced through IE too
+ +1210: 64 48 8b 04 25 00 00[ ]+mov %fs:0x0,%rax
+ +1217: 00 00
+- +1219: 48 03 05 ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <_DYNAMIC\+0x140>
++ +1219: 48 03 05 ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <.*>
+ # -> R_X86_64_TPOFF64 *ABS*+0x24
+ +1220: 66 0f 1f 44 00 00[ ]+nopw 0x0\(%rax,%rax,1\)
+ +1226: 90[ ]+nop *
+@@ -282,7 +282,7 @@ Disassembly of section .text:
+ +1228: 90[ ]+nop *
+ +1229: 90[ ]+nop *
+ # -mcmodel=large GD against hidden and local variable
+- +122a: 48 8d 3d ([0-9a-f]{2} ){4}[ ]+lea 0x[0-9a-f]+\(%rip\),%rdi +# [0-9a-f]+ <_DYNAMIC\+0x1a8>
++ +122a: 48 8d 3d ([0-9a-f]{2} ){4}[ ]+lea 0x[0-9a-f]+\(%rip\),%rdi +# [0-9a-f]+ <.*>
+ # -> R_X86_64_DTPMOD64 [0 0x4000000000000000]
+ +1231: 48 b8 ([0-9a-f]{2} ){5}[ ]+movabs \$0x[0-9a-f]+,%rax
+ # -> R_X86_64_JUMP_SLOT __tls_get_addr
+@@ -296,7 +296,7 @@ Disassembly of section .text:
+ # -mcmodel=large GD -> IE against hidden and local variable referenced through IE too
+ +1244: 64 48 8b 04 25 00 00[ ]+mov %fs:0x0,%rax
+ +124b: 00 00
+- +124d: 48 03 05 ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <_DYNAMIC\+0x1b8>
++ +124d: 48 03 05 ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <.*>
+ # -> R_X86_64_TPOFF64 *ABS*+0x44
+ +1254: 66 0f 1f 44 00 00[ ]+nopw 0x0\(%rax,%rax,1\)
+ +125a: 90[ ]+nop *
+@@ -304,7 +304,7 @@ Disassembly of section .text:
+ +125c: 90[ ]+nop *
+ +125d: 90[ ]+nop *
+ # -mcmodel=large GD against hidden but not local variable
+- +125e: 48 8d 3d ([0-9a-f]{2} ){4}[ ]+lea 0x[0-9a-f]+\(%rip\),%rdi +# [0-9a-f]+ <_DYNAMIC\+0x160>
++ +125e: 48 8d 3d ([0-9a-f]{2} ){4}[ ]+lea 0x[0-9a-f]+\(%rip\),%rdi +# [0-9a-f]+ <.*>
+ # -> R_X86_64_DTPMOD64 [0 0x6000000000000000]
+ +1265: 48 b8 ([0-9a-f]{2} ){5}[ ]+movabs \$0x[0-9a-f]+,%rax
+ # -> R_X86_64_JUMP_SLOT __tls_get_addr
+@@ -318,7 +318,7 @@ Disassembly of section .text:
+ # -mcmodel=large GD -> IE against hidden but not local variable referenced through IE too
+ +1278: 64 48 8b 04 25 00 00[ ]+mov %fs:0x0,%rax
+ +127f: 00 00
+- +1281: 48 03 05 ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <_DYNAMIC\+0x170>
++ +1281: 48 03 05 ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <.*>
+ # -> R_X86_64_TPOFF64 *ABS*+0x64
+ +1288: 66 0f 1f 44 00 00[ ]+nopw 0x0\(%rax,%rax,1\)
+ +128e: 90[ ]+nop *
+@@ -326,7 +326,7 @@ Disassembly of section .text:
+ +1290: 90[ ]+nop *
+ +1291: 90[ ]+nop *
+ # -mcmodel=large LD
+- +1292: 48 8d 3d ([0-9a-f]{2} ){4}[ ]+lea 0x[0-9a-f]+\(%rip\),%rdi +# [0-9a-f]+ <_DYNAMIC\+0x150>
++ +1292: 48 8d 3d ([0-9a-f]{2} ){4}[ ]+lea 0x[0-9a-f]+\(%rip\),%rdi +# [0-9a-f]+ <.*>
+ # -> R_X86_64_DTPMOD64 [0 0x000000000000000]
+ +1299: 48 b8 ([0-9a-f]{2} ){5}[ ]+movabs \$0x[0-9a-f]+,%rax
+ # -> R_X86_64_JUMP_SLOT __tls_get_addr
+@@ -344,7 +344,7 @@ Disassembly of section .text:
+ +12bc: 90[ ]+nop *
+ +12bd: 90[ ]+nop *
+ # -mcmodel=large LD against hidden and local variables
+- +12be: 48 8d 3d ([0-9a-f]{2} ){4}[ ]+lea 0x[0-9a-f]+\(%rip\),%rdi +# [0-9a-f]+ <_DYNAMIC\+0x150>
++ +12be: 48 8d 3d ([0-9a-f]{2} ){4}[ ]+lea 0x[0-9a-f]+\(%rip\),%rdi +# [0-9a-f]+ <.*>
+ # -> R_X86_64_DTPMOD64 [0 0x000000000000000]
+ +12c5: 48 b8 ([0-9a-f]{2} ){5}[ ]+movabs \$0x[0-9a-f]+,%rax
+ # -> R_X86_64_JUMP_SLOT __tls_get_addr
+@@ -362,7 +362,7 @@ Disassembly of section .text:
+ +12e8: 90[ ]+nop *
+ +12e9: 90[ ]+nop *
+ # -mcmodel=large LD against hidden but not local variables
+- +12ea: 48 8d 3d ([0-9a-f]{2} ){4}[ ]+lea 0x[0-9a-f]+\(%rip\),%rdi +# [0-9a-f]+ <_DYNAMIC\+0x150>
++ +12ea: 48 8d 3d ([0-9a-f]{2} ){4}[ ]+lea 0x[0-9a-f]+\(%rip\),%rdi +# [0-9a-f]+ <.*>
+ # -> R_X86_64_DTPMOD64 [0 0x000000000000000]
+ +12f1: 48 b8 ([0-9a-f]{2} ){5}[ ]+movabs \$0x[0-9a-f]+,%rax
+ # -> R_X86_64_JUMP_SLOT __tls_get_addr
+diff --git a/ld/testsuite/ld-x86-64/tlspic2.dd b/ld/testsuite/ld-x86-64/tlspic2.dd
+index 18358f1..596fcb4 100644
+--- a/ld/testsuite/ld-x86-64/tlspic2.dd
++++ b/ld/testsuite/ld-x86-64/tlspic2.dd
+@@ -17,10 +17,10 @@ Disassembly of section .text:
+ +1006: 90[ ]+nop *
+ +1007: 90[ ]+nop *
+ # GD
+- +1008: 66 48 8d 3d ([0-9a-f]{2} ){3}[ ]+data16 lea 0x[0-9a-f]+\(%rip\),%rdi +# [0-9a-f]+ <_DYNAMIC\+0x[0-9a-f]+>
++ +1008: 66 48 8d 3d ([0-9a-f]{2} ){3}[ ]+data16 lea 0x[0-9a-f]+\(%rip\),%rdi +# [0-9a-f]+ <.*>
+ +100f: [0-9a-f ]+
+ # -> R_X86_64_DTPMOD64 sg1
+- +1010: 66 48 ff [0-9a-f ]+data16 rex\.W callq \*0x[0-9a-f]+\(%rip\) +# [0-9a-f]+ <_DYNAMIC\+0x[0-9a-f]+>
++ +1010: 66 48 ff [0-9a-f ]+data16 rex\.W callq \*0x[0-9a-f]+\(%rip\) +# [0-9a-f]+ <.*>
+ # -> R_X86_64_GLOB_DAT __tls_get_addr
+ +1017: [0-9a-f ]+
+ +1018: 90[ ]+nop *
+@@ -30,17 +30,17 @@ Disassembly of section .text:
+ # GD -> IE because variable is referenced through IE too
+ +101c: 64 48 8b 04 25 00 00[ ]+mov %fs:0x0,%rax
+ +1023: 00 00 *
+- +1025: 48 03 05 ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <_DYNAMIC\+0x[0-9a-f]+>
++ +1025: 48 03 05 ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <.*>
+ # -> R_X86_64_TPOFF64 sg2
+ +102c: 90[ ]+nop *
+ +102d: 90[ ]+nop *
+ +102e: 90[ ]+nop *
+ +102f: 90[ ]+nop *
+ # GD against local variable
+- +1030: 66 48 8d 3d ([0-9a-f]{2} ){3}[ ]+data16 lea 0x[0-9a-f]+\(%rip\),%rdi +# [0-9a-f]+ <_DYNAMIC\+0x[0-9a-f]+>
++ +1030: 66 48 8d 3d ([0-9a-f]{2} ){3}[ ]+data16 lea 0x[0-9a-f]+\(%rip\),%rdi +# [0-9a-f]+ <.*>
+ +1037: [0-9a-f ]+
+ # -> R_X86_64_DTPMOD64 [0 0x2000000000000000]
+- +1038: 66 48 ff [0-9a-f ]+data16 rex\.W callq \*0x[0-9a-f]+\(%rip\) +# [0-9a-f]+ <_DYNAMIC\+0x[0-9a-f]+>
++ +1038: 66 48 ff [0-9a-f ]+data16 rex\.W callq \*0x[0-9a-f]+\(%rip\) +# [0-9a-f]+ <.*>
+ # -> R_X86_64_GLOB_DAT __tls_get_addr
+ +103f: [0-9a-f ]+
+ +1040: 90[ ]+nop *
+@@ -50,17 +50,17 @@ Disassembly of section .text:
+ # GD -> IE against local variable referenced through IE too
+ +1044: 64 48 8b 04 25 00 00[ ]+mov %fs:0x0,%rax
+ +104b: 00 00 *
+- +104d: 48 03 05 ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <_DYNAMIC\+0x[0-9a-f]+>
++ +104d: 48 03 05 ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <.*>
+ # -> R_X86_64_TPOFF64 *ABS*+0x24
+ +1054: 90[ ]+nop *
+ +1055: 90[ ]+nop *
+ +1056: 90[ ]+nop *
+ +1057: 90[ ]+nop *
+ # GD against hidden and local variable
+- +1058: 66 48 8d 3d ([0-9a-f]{2} ){3}[ ]+data16 lea 0x[0-9a-f]+\(%rip\),%rdi +# [0-9a-f]+ <_DYNAMIC\+0x[0-9a-f]+>
++ +1058: 66 48 8d 3d ([0-9a-f]{2} ){3}[ ]+data16 lea 0x[0-9a-f]+\(%rip\),%rdi +# [0-9a-f]+ <.*>
+ +105f: [0-9a-f ]+
+ # -> R_X86_64_DTPMOD64 [0 0x4000000000000000]
+- +1060: 66 48 ff [0-9a-f ]+data16 rex\.W callq \*0x[0-9a-f]+\(%rip\) +# [0-9a-f]+ <_DYNAMIC\+0x[0-9a-f]+>
++ +1060: 66 48 ff [0-9a-f ]+data16 rex\.W callq \*0x[0-9a-f]+\(%rip\) +# [0-9a-f]+ <.*>
+ # -> R_X86_64_GLOB_DAT __tls_get_addr
+ +1067: [0-9a-f ]+
+ +1068: 90[ ]+nop *
+@@ -70,17 +70,17 @@ Disassembly of section .text:
+ # GD -> IE against hidden and local variable referenced through IE too
+ +106c: 64 48 8b 04 25 00 00[ ]+mov %fs:0x0,%rax
+ +1073: 00 00 *
+- +1075: 48 03 05 ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <_DYNAMIC\+0x[0-9a-f]+>
++ +1075: 48 03 05 ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <.*>
+ # -> R_X86_64_TPOFF64 *ABS*+0x44
+ +107c: 90[ ]+nop *
+ +107d: 90[ ]+nop *
+ +107e: 90[ ]+nop *
+ +107f: 90[ ]+nop *
+ # GD against hidden but not local variable
+- +1080: 66 48 8d 3d ([0-9a-f]{2} ){3}[ ]+data16 lea 0x[0-9a-f]+\(%rip\),%rdi +# [0-9a-f]+ <_DYNAMIC\+0x[0-9a-f]+>
++ +1080: 66 48 8d 3d ([0-9a-f]{2} ){3}[ ]+data16 lea 0x[0-9a-f]+\(%rip\),%rdi +# [0-9a-f]+ <.*>
+ +1087: [0-9a-f ]+
+ # -> R_X86_64_DTPMOD64 [0 0x6000000000000000]
+- +1088: 66 48 ff [0-9a-f ]+data16 rex\.W callq \*0x[0-9a-f]+\(%rip\) +# [0-9a-f]+ <_DYNAMIC\+0x[0-9a-f]+>
++ +1088: 66 48 ff [0-9a-f ]+data16 rex\.W callq \*0x[0-9a-f]+\(%rip\) +# [0-9a-f]+ <.*>
+ # -> R_X86_64_GLOB_DAT __tls_get_addr
+ +108f: [0-9a-f ]+
+ +1090: 90[ ]+nop *
+@@ -90,16 +90,16 @@ Disassembly of section .text:
+ # GD -> IE against hidden but not local variable referenced through IE too
+ +1094: 64 48 8b 04 25 00 00[ ]+mov %fs:0x0,%rax
+ +109b: 00 00 *
+- +109d: 48 03 05 ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <_DYNAMIC\+0x[0-9a-f]+>
++ +109d: 48 03 05 ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <.*>
+ # -> R_X86_64_TPOFF64 *ABS*+0x64
+ +10a4: 90[ ]+nop *
+ +10a5: 90[ ]+nop *
+ +10a6: 90[ ]+nop *
+ +10a7: 90[ ]+nop *
+ # LD
+- +10a8: 48 8d 3d ([0-9a-f]{2} ){4}[ ]+lea 0x[0-9a-f]+\(%rip\),%rdi +# [0-9a-f]+ <_DYNAMIC\+0x[0-9a-f]+>
++ +10a8: 48 8d 3d ([0-9a-f]{2} ){4}[ ]+lea 0x[0-9a-f]+\(%rip\),%rdi +# [0-9a-f]+ <.*>
+ # -> R_X86_64_DTPMOD64 [0 0x000000000000000]
+- +10af: ff [0-9a-f ]+callq[ ]+\*0x[0-9a-f]+\(%rip\) +# [0-9a-f]+ <_DYNAMIC\+0x[0-9a-f]+>
++ +10af: ff [0-9a-f ]+callq[ ]+\*0x[0-9a-f]+\(%rip\) +# [0-9a-f]+ <.*>
+ # -> R_X86_64_GLOB_DAT __tls_get_addr
+ +10b5: 90[ ]+nop *
+ +10b6: 48 8d 90 20 00 00 00[ ]+lea 0x20\(%rax\),%rdx
+@@ -111,9 +111,9 @@ Disassembly of section .text:
+ +10c8: 90[ ]+nop *
+ +10c9: 90[ ]+nop *
+ # LD against hidden and local variables
+- +10ca: 48 8d 3d ([0-9a-f]{2} ){4}[ ]+lea 0x[0-9a-f]+\(%rip\),%rdi +# [0-9a-f]+ <_DYNAMIC\+0x[0-9a-f]+>
++ +10ca: 48 8d 3d ([0-9a-f]{2} ){4}[ ]+lea 0x[0-9a-f]+\(%rip\),%rdi +# [0-9a-f]+ <.*>
+ # -> R_X86_64_DTPMOD64 [0 0x000000000000000]
+- +10d1: ff [0-9a-f ]+callq[ ]+\*0x[0-9a-f]+\(%rip\) +# [0-9a-f]+ <_DYNAMIC\+0x[0-9a-f]+>
++ +10d1: ff [0-9a-f ]+callq[ ]+\*0x[0-9a-f]+\(%rip\) +# [0-9a-f]+ <.*>
+ # -> R_X86_64_GLOB_DAT __tls_get_addr
+ +10d7: 90[ ]+nop *
+ +10d8: 48 8d 90 40 00 00 00[ ]+lea 0x40\(%rax\),%rdx
+@@ -125,9 +125,9 @@ Disassembly of section .text:
+ +10ea: 90[ ]+nop *
+ +10eb: 90[ ]+nop *
+ # LD against hidden but not local variables
+- +10ec: 48 8d 3d ([0-9a-f]{2} ){4}[ ]+lea 0x[0-9a-f]+\(%rip\),%rdi +# [0-9a-f]+ <_DYNAMIC\+0x[0-9a-f]+>
++ +10ec: 48 8d 3d ([0-9a-f]{2} ){4}[ ]+lea 0x[0-9a-f]+\(%rip\),%rdi +# [0-9a-f]+ <.*>
+ # -> R_X86_64_DTPMOD64 [0 0x000000000000000]
+- +10f3: ff [0-9a-f ]+callq[ ]+\*0x[0-9a-f]+\(%rip\) +# [0-9a-f]+ <_DYNAMIC\+0x[0-9a-f]+>
++ +10f3: ff [0-9a-f ]+callq[ ]+\*0x[0-9a-f]+\(%rip\) +# [0-9a-f]+ <.*>
+ # -> R_X86_64_GLOB_DAT __tls_get_addr
+ +10f9: 90[ ]+nop *
+ +10fa: 4c 8d a0 60 00 00 00[ ]+lea 0x60\(%rax\),%r12
+@@ -141,7 +141,7 @@ Disassembly of section .text:
+ +1113: 00 00 *
+ +1115: 90[ ]+nop *
+ +1116: 90[ ]+nop *
+- +1117: 48 03 0d ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%rcx +# [0-9a-f]+ <_DYNAMIC\+0x[0-9a-f]+>
++ +1117: 48 03 0d ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%rcx +# [0-9a-f]+ <.*>
+ # -> R_X86_64_TPOFF64 sg2
+ +111e: 90[ ]+nop *
+ +111f: 90[ ]+nop *
+@@ -152,7 +152,7 @@ Disassembly of section .text:
+ +1129: 00 00 *
+ +112b: 90[ ]+nop *
+ +112c: 90[ ]+nop *
+- +112d: 4c 03 35 ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%r14 +# [0-9a-f]+ <_DYNAMIC\+0x[0-9a-f]+>
++ +112d: 4c 03 35 ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%r14 +# [0-9a-f]+ <.*>
+ # -> R_X86_64_TPOFF64 *ABS*+0x24
+ +1134: 90[ ]+nop *
+ +1135: 90[ ]+nop *
+@@ -163,7 +163,7 @@ Disassembly of section .text:
+ +113f: 00 00 *
+ +1141: 90[ ]+nop *
+ +1142: 90[ ]+nop *
+- +1143: 48 03 0d ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%rcx +# [0-9a-f]+ <_DYNAMIC\+0x[0-9a-f]+>
++ +1143: 48 03 0d ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%rcx +# [0-9a-f]+ <.*>
+ # -> R_X86_64_TPOFF64 *ABS*+0x44
+ +114a: 90[ ]+nop *
+ +114b: 90[ ]+nop *
+@@ -174,7 +174,7 @@ Disassembly of section .text:
+ +1155: 00 00 *
+ +1157: 90[ ]+nop *
+ +1158: 90[ ]+nop *
+- +1159: 48 03 0d ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%rcx +# [0-9a-f]+ <_DYNAMIC\+0x[0-9a-f]+>
++ +1159: 48 03 0d ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%rcx +# [0-9a-f]+ <.*>
+ # -> R_X86_64_TPOFF64 *ABS*+0x64
+ +1160: 90[ ]+nop *
+ +1161: 90[ ]+nop *
+@@ -182,7 +182,7 @@ Disassembly of section .text:
+ +1163: 90[ ]+nop *
+ # Direct access through %fs
+ # IE against global var
+- +1164: 48 8b 0d ([0-9a-f]{2} ){4}[ ]+mov 0x[0-9a-f]+\(%rip\),%rcx +# [0-9a-f]+ <_DYNAMIC\+0x[0-9a-f]+>
++ +1164: 48 8b 0d ([0-9a-f]{2} ){4}[ ]+mov 0x[0-9a-f]+\(%rip\),%rcx +# [0-9a-f]+ <.*>
+ # -> R_X86_64_TPOFF64 sg5
+ +116b: 90[ ]+nop *
+ +116c: 90[ ]+nop *
+@@ -192,7 +192,7 @@ Disassembly of section .text:
+ +1173: 90[ ]+nop *
+ +1174: 90[ ]+nop *
+ # IE against local var
+- +1175: 4c 8b 15 ([0-9a-f]{2} ){4}[ ]+mov 0x[0-9a-f]+\(%rip\),%r10 +# [0-9a-f]+ <_DYNAMIC\+0x[0-9a-f]+>
++ +1175: 4c 8b 15 ([0-9a-f]{2} ){4}[ ]+mov 0x[0-9a-f]+\(%rip\),%r10 +# [0-9a-f]+ <.*>
+ # -> R_X86_64_TPOFF64 *ABS*+0x30
+ +117c: 90[ ]+nop *
+ +117d: 90[ ]+nop *
+@@ -202,7 +202,7 @@ Disassembly of section .text:
+ +1184: 90[ ]+nop *
+ +1185: 90[ ]+nop *
+ # IE against hidden and local var
+- +1186: 48 8b 15 ([0-9a-f]{2} ){4}[ ]+mov 0x[0-9a-f]+\(%rip\),%rdx +# [0-9a-f]+ <_DYNAMIC\+0x[0-9a-f]+>
++ +1186: 48 8b 15 ([0-9a-f]{2} ){4}[ ]+mov 0x[0-9a-f]+\(%rip\),%rdx +# [0-9a-f]+ <.*>
+ # -> R_X86_64_TPOFF64 *ABS*+0x50
+ +118d: 90[ ]+nop *
+ +118e: 90[ ]+nop *
+@@ -212,7 +212,7 @@ Disassembly of section .text:
+ +1195: 90[ ]+nop *
+ +1196: 90[ ]+nop *
+ # IE against hidden but not local var
+- +1197: 48 8b 0d ([0-9a-f]{2} ){4}[ ]+mov 0x[0-9a-f]+\(%rip\),%rcx +# [0-9a-f]+ <_DYNAMIC\+0x[0-9a-f]+>
++ +1197: 48 8b 0d ([0-9a-f]{2} ){4}[ ]+mov 0x[0-9a-f]+\(%rip\),%rcx +# [0-9a-f]+ <.*>
+ # -> R_X86_64_TPOFF64 *ABS*+0x70
+ +119e: 90[ ]+nop *
+ +119f: 90[ ]+nop *
+@@ -232,7 +232,7 @@ Disassembly of section .text:
+ # -mcmodel=large sequences
+ #
+ # -mcmodel=large GD
+- +11c2: 48 8d 3d ([0-9a-f]{2} ){4}[ ]+lea 0x[0-9a-f]+\(%rip\),%rdi +# [0-9a-f]+ <_DYNAMIC\+0x[0-9a-f]+>
++ +11c2: 48 8d 3d ([0-9a-f]{2} ){4}[ ]+lea 0x[0-9a-f]+\(%rip\),%rdi +# [0-9a-f]+ <.*>
+ # -> R_X86_64_DTPMOD64 sg1
+ +11c9: 48 b8 ([0-9a-f]{2} ){5}[ ]+movabs \$0x[0-9a-f]+,%rax
+ # -> R_X86_64_GLOB_DAT __tls_get_addr
+@@ -247,7 +247,7 @@ Disassembly of section .text:
+ # -> R_X86_64_TPOFF64 sg2
+ +11dc: 64 48 8b 04 25 00 00[ ]+mov %fs:0x0,%rax
+ +11e3: 00 00
+- +11e5: 48 03 05 ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <_DYNAMIC\+0x[0-9a-f]+>
++ +11e5: 48 03 05 ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <.*>
+ # -> R_X86_64_TPOFF64 sg2
+ +11ec: 66 0f 1f 44 00 00[ ]+nopw 0x0\(%rax,%rax,1\)
+ +11f2: 90[ ]+nop *
+@@ -255,7 +255,7 @@ Disassembly of section .text:
+ +11f4: 90[ ]+nop *
+ +11f5: 90[ ]+nop *
+ # -mcmodel=large GD against local variable
+- +11f6: 48 8d 3d ([0-9a-f]{2} ){4}[ ]+lea 0x[0-9a-f]+\(%rip\),%rdi +# [0-9a-f]+ <_DYNAMIC\+0x[0-9a-f]+>
++ +11f6: 48 8d 3d ([0-9a-f]{2} ){4}[ ]+lea 0x[0-9a-f]+\(%rip\),%rdi +# [0-9a-f]+ <.*>
+ # -> R_X86_64_DTPMOD64 [0 0x2000000000000000]
+ +11fd: 48 b8 ([0-9a-f]{2} ){5}[ ]+movabs \$0x[0-9a-f]+,%rax
+ # -> R_X86_64_GLOB_DAT __tls_get_addr
+@@ -269,7 +269,7 @@ Disassembly of section .text:
+ # -mcmodel=large GD -> IE against local variable referenced through IE too
+ +1210: 64 48 8b 04 25 00 00[ ]+mov %fs:0x0,%rax
+ +1217: 00 00
+- +1219: 48 03 05 ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <_DYNAMIC\+0x[0-9a-f]+>
++ +1219: 48 03 05 ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <.*>
+ # -> R_X86_64_TPOFF64 *ABS*+0x24
+ +1220: 66 0f 1f 44 00 00[ ]+nopw 0x0\(%rax,%rax,1\)
+ +1226: 90[ ]+nop *
+@@ -277,7 +277,7 @@ Disassembly of section .text:
+ +1228: 90[ ]+nop *
+ +1229: 90[ ]+nop *
+ # -mcmodel=large GD against hidden and local variable
+- +122a: 48 8d 3d ([0-9a-f]{2} ){4}[ ]+lea 0x[0-9a-f]+\(%rip\),%rdi +# [0-9a-f]+ <_DYNAMIC\+0x[0-9a-f]+>
++ +122a: 48 8d 3d ([0-9a-f]{2} ){4}[ ]+lea 0x[0-9a-f]+\(%rip\),%rdi +# [0-9a-f]+ <.*>
+ # -> R_X86_64_DTPMOD64 [0 0x4000000000000000]
+ +1231: 48 b8 ([0-9a-f]{2} ){5}[ ]+movabs \$0x[0-9a-f]+,%rax
+ # -> R_X86_64_GLOB_DAT __tls_get_addr
+@@ -291,7 +291,7 @@ Disassembly of section .text:
+ # -mcmodel=large GD -> IE against hidden and local variable referenced through IE too
+ +1244: 64 48 8b 04 25 00 00[ ]+mov %fs:0x0,%rax
+ +124b: 00 00
+- +124d: 48 03 05 ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <_DYNAMIC\+0x[0-9a-f]+>
++ +124d: 48 03 05 ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <.*>
+ # -> R_X86_64_TPOFF64 *ABS*+0x44
+ +1254: 66 0f 1f 44 00 00[ ]+nopw 0x0\(%rax,%rax,1\)
+ +125a: 90[ ]+nop *
+@@ -299,7 +299,7 @@ Disassembly of section .text:
+ +125c: 90[ ]+nop *
+ +125d: 90[ ]+nop *
+ # -mcmodel=large GD against hidden but not local variable
+- +125e: 48 8d 3d ([0-9a-f]{2} ){4}[ ]+lea 0x[0-9a-f]+\(%rip\),%rdi +# [0-9a-f]+ <_DYNAMIC\+0x[0-9a-f]+>
++ +125e: 48 8d 3d ([0-9a-f]{2} ){4}[ ]+lea 0x[0-9a-f]+\(%rip\),%rdi +# [0-9a-f]+ <.*>
+ # -> R_X86_64_DTPMOD64 [0 0x6000000000000000]
+ +1265: 48 b8 ([0-9a-f]{2} ){5}[ ]+movabs \$0x[0-9a-f]+,%rax
+ # -> R_X86_64_GLOB_DAT __tls_get_addr
+@@ -313,7 +313,7 @@ Disassembly of section .text:
+ # -mcmodel=large GD -> IE against hidden but not local variable referenced through IE too
+ +1278: 64 48 8b 04 25 00 00[ ]+mov %fs:0x0,%rax
+ +127f: 00 00
+- +1281: 48 03 05 ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <_DYNAMIC\+0x[0-9a-f]+>
++ +1281: 48 03 05 ([0-9a-f]{2} ){4}[ ]+add 0x[0-9a-f]+\(%rip\),%rax +# [0-9a-f]+ <.*>
+ # -> R_X86_64_TPOFF64 *ABS*+0x64
+ +1288: 66 0f 1f 44 00 00[ ]+nopw 0x0\(%rax,%rax,1\)
+ +128e: 90[ ]+nop *
+@@ -321,7 +321,7 @@ Disassembly of section .text:
+ +1290: 90[ ]+nop *
+ +1291: 90[ ]+nop *
+ # -mcmodel=large LD
+- +1292: 48 8d 3d ([0-9a-f]{2} ){4}[ ]+lea 0x[0-9a-f]+\(%rip\),%rdi +# [0-9a-f]+ <_DYNAMIC\+0x[0-9a-f]+>
++ +1292: 48 8d 3d ([0-9a-f]{2} ){4}[ ]+lea 0x[0-9a-f]+\(%rip\),%rdi +# [0-9a-f]+ <.*>
+ # -> R_X86_64_DTPMOD64 [0 0x000000000000000]
+ +1299: 48 b8 ([0-9a-f]{2} ){5}[ ]+movabs \$0x[0-9a-f]+,%rax
+ # -> R_X86_64_GLOB_DAT __tls_get_addr
+@@ -339,7 +339,7 @@ Disassembly of section .text:
+ +12bc: 90[ ]+nop *
+ +12bd: 90[ ]+nop *
+ # -mcmodel=large LD against hidden and local variables
+- +12be: 48 8d 3d ([0-9a-f]{2} ){4}[ ]+lea 0x[0-9a-f]+\(%rip\),%rdi +# [0-9a-f]+ <_DYNAMIC\+0x[0-9a-f]+>
++ +12be: 48 8d 3d ([0-9a-f]{2} ){4}[ ]+lea 0x[0-9a-f]+\(%rip\),%rdi +# [0-9a-f]+ <.*>
+ # -> R_X86_64_DTPMOD64 [0 0x000000000000000]
+ +12c5: 48 b8 ([0-9a-f]{2} ){5}[ ]+movabs \$0x[0-9a-f]+,%rax
+ # -> R_X86_64_GLOB_DAT __tls_get_addr
+@@ -357,7 +357,7 @@ Disassembly of section .text:
+ +12e8: 90[ ]+nop *
+ +12e9: 90[ ]+nop *
+ # -mcmodel=large LD against hidden but not local variables
+- +12ea: 48 8d 3d ([0-9a-f]{2} ){4}[ ]+lea 0x[0-9a-f]+\(%rip\),%rdi +# [0-9a-f]+ <_DYNAMIC\+0x[0-9a-f]+>
++ +12ea: 48 8d 3d ([0-9a-f]{2} ){4}[ ]+lea 0x[0-9a-f]+\(%rip\),%rdi +# [0-9a-f]+ <.*>
+ # -> R_X86_64_DTPMOD64 [0 0x000000000000000]
+ +12f1: 48 b8 ([0-9a-f]{2} ){5}[ ]+movabs \$0x[0-9a-f]+,%rax
+ # -> R_X86_64_GLOB_DAT __tls_get_addr
+--- binutils-2.27.orig/ld/testsuite/ld-aarch64/farcall-bl-plt.d 2016-11-08 15:39:42.082556640 +0000
++++ binutils-2.27/ld/testsuite/ld-aarch64/farcall-bl-plt.d 2016-11-08 16:56:38.410233674 +0000
+@@ -7,7 +7,7 @@
+
+ Disassembly of section .plt:
+
+-.* <foo@plt.*>:
++.* <.plt>:
+ .*: a9bf7bf0 stp x16, x30, \[sp,#-16\]!
+ .*: .* adrp x16, .* <__foo_veneer\+.*>
+ .*: .* ldr x17, \[x16,#.*\]
+@@ -32,7 +32,7 @@ Disassembly of section .text:
+ .*: .* b .* <__foo_veneer\+.*>
+
+ .* <__foo_veneer>:
+-.*: .* adrp x16, 0 <foo@plt.*>
++.*: .* adrp x16, 0 <.*>
+ .*: .* add x16, x16, #.*
+ .*: d61f0200 br x16
+ ...
+--- binutils-2.27.orig/ld/testsuite/ld-aarch64/farcall-b-plt.d 2016-11-08 15:39:42.082556640 +0000
++++ binutils-2.27/ld/testsuite/ld-aarch64/farcall-b-plt.d 2016-11-08 16:59:06.733057238 +0000
+@@ -7,7 +7,7 @@
+
+ Disassembly of section .plt:
+
+-.* <foo@plt.*>:
++.* <.plt>:
+ .*: a9bf7bf0 stp x16, x30, \[sp,#-16\]!
+ .*: .* adrp x16, .* <__foo_veneer\+.*>
+ .*: .* ldr x17, \[x16,#.*\]
+@@ -32,7 +32,7 @@ Disassembly of section .text:
+ .*: .* b .* <__foo_veneer\+.*>
+
+ .* <__foo_veneer>:
+-.*: .* adrp x16, 0 <foo@plt.*>
++.*: .* adrp x16, 0 <.*>
+ .*: .* add x16, x16, #.*
+ .*: d61f0200 br x16
+ ...
+--- binutils-2.27.orig/ld/testsuite/ld-aarch64/tls-desc-ie.d 2016-11-08 15:39:42.091556688 +0000
++++ binutils-2.27/ld/testsuite/ld-aarch64/tls-desc-ie.d 2016-11-08 17:00:23.757503387 +0000
+@@ -4,7 +4,7 @@
+ #...
+ +10000: 90000080 adrp x0, 20000 <_GLOBAL_OFFSET_TABLE_>
+ +10004: 91004000 add x0, x0, #0x10
+- +10008: 94000016 bl 10060 <v1\+0x10060>
++ +10008: 94000016 bl 10060 <.*>
+ +1000c: d503201f nop
+ +10010: 90000080 adrp x0, 20000 <_GLOBAL_OFFSET_TABLE_>
+ +10014: f9400400 ldr x0, \[x0,#8\]
diff --git a/SOURCES/binutils-2.27-power9.2.patch b/SOURCES/binutils-2.27-power9.2.patch
new file mode 100644
index 0000000..5bc33c5
--- /dev/null
+++ b/SOURCES/binutils-2.27-power9.2.patch
@@ -0,0 +1,606 @@
+diff -rup binutils.orig/gas/config/tc-ppc.c binutils-2.27/gas/config/tc-ppc.c
+--- binutils.orig/gas/config/tc-ppc.c 2017-01-17 10:34:39.694867665 +0000
++++ binutils-2.27/gas/config/tc-ppc.c 2017-01-17 10:49:40.367225030 +0000
+@@ -2671,7 +2671,8 @@ md_assemble (char *str)
+ const struct powerpc_operand *operand;
+
+ operand = &powerpc_operands[*opindex_ptr];
+- if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0)
++ if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0
++ && !((operand->flags & PPC_OPERAND_OPTIONAL32) != 0 && ppc_obj64))
+ {
+ unsigned int opcount;
+ unsigned int num_operands_expected;
+@@ -2741,6 +2742,7 @@ md_assemble (char *str)
+ /* If this is an optional operand, and we are skipping it, just
+ insert a zero. */
+ if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0
++ && !((operand->flags & PPC_OPERAND_OPTIONAL32) != 0 && ppc_obj64)
+ && skip_optional)
+ {
+ long val = ppc_optional_operand_value (operand);
+@@ -2942,7 +2944,7 @@ md_assemble (char *str)
+ }
+ break;
+ }
+- /* Fall thru */
++ /* Fallthru */
+
+ case BFD_RELOC_PPC64_ADDR16_HIGH:
+ ex.X_add_number = PPC_HI (ex.X_add_number);
+@@ -2964,7 +2966,7 @@ md_assemble (char *str)
+ }
+ break;
+ }
+- /* Fall thru */
++ /* Fallthru */
+
+ case BFD_RELOC_PPC64_ADDR16_HIGHA:
+ ex.X_add_number = PPC_HA (ex.X_add_number);
+@@ -3087,14 +3089,14 @@ md_assemble (char *str)
+ {
+ int tmp_insn = insn & opcode->mask;
+
+- int use_d_reloc = (tmp_insn == E_OR2I_INSN
++ int use_a_reloc = (tmp_insn == E_OR2I_INSN
+ || tmp_insn == E_AND2I_DOT_INSN
+ || tmp_insn == E_OR2IS_INSN
+ || tmp_insn == E_LIS_INSN
+ || tmp_insn == E_AND2IS_DOT_INSN);
+
+
+- int use_a_reloc = (tmp_insn == E_ADD2I_DOT_INSN
++ int use_d_reloc = (tmp_insn == E_ADD2I_DOT_INSN
+ || tmp_insn == E_ADD2IS_INSN
+ || tmp_insn == E_CMP16I_INSN
+ || tmp_insn == E_MULL2I_INSN
+@@ -3377,13 +3379,17 @@ md_assemble (char *str)
+ however it'll remain clear for dual-mode instructions on
+ dual-mode and, more importantly, standard-mode processors. */
+ if ((ppc_cpu & opcode->flags) == PPC_OPCODE_VLE)
+- ppc_apuinfo_section_add (PPC_APUINFO_VLE, 1);
++ {
++ ppc_apuinfo_section_add (PPC_APUINFO_VLE, 1);
++ if (elf_section_data (now_seg) != NULL)
++ elf_section_data (now_seg)->this_hdr.sh_flags |= SHF_PPC_VLE;
++ }
+ }
+ #endif
+
+ /* Write out the instruction. */
+ /* Differentiate between two and four byte insns. */
+- if (ppc_mach () == bfd_mach_ppc_vle)
++ if ((ppc_cpu & PPC_OPCODE_VLE) != 0)
+ {
+ if (PPC_OP_SE_VLE (insn))
+ insn_length = 2;
+@@ -3400,7 +3406,7 @@ md_assemble (char *str)
+ f = frag_more (insn_length);
+ if (frag_now->has_code && frag_now->insn_addr != addr_mod)
+ {
+- if (ppc_mach() == bfd_mach_ppc_vle)
++ if ((ppc_cpu & PPC_OPCODE_VLE) != 0)
+ as_bad (_("instruction address is not a multiple of 2"));
+ else
+ as_bad (_("instruction address is not a multiple of 4"));
+@@ -6346,7 +6352,7 @@ ppc_frag_check (struct frag *fragP)
+ if (!fragP->has_code)
+ return;
+
+- if (ppc_mach() == bfd_mach_ppc_vle)
++ if ((ppc_cpu & PPC_OPCODE_VLE) != 0)
+ {
+ if (((fragP->fr_address + fragP->insn_addr) & 1) != 0)
+ as_bad (_("instruction address is not a multiple of 2"));
+@@ -6367,7 +6373,7 @@ ppc_handle_align (struct frag *fragP)
+ valueT count = (fragP->fr_next->fr_address
+ - (fragP->fr_address + fragP->fr_fix));
+
+- if (ppc_mach() == bfd_mach_ppc_vle && count != 0 && (count & 1) == 0)
++ if ((ppc_cpu & PPC_OPCODE_VLE) != 0 && count != 0 && (count & 1) == 0)
+ {
+ char *dest = fragP->fr_literal + fragP->fr_fix;
+
+@@ -6565,7 +6571,7 @@ md_apply_fix (fixS *fixP, valueT *valP,
+ }
+ break;
+ }
+- /* Fall thru */
++ /* Fallthru */
+
+ case BFD_RELOC_PPC_VLE_HI16A:
+ case BFD_RELOC_PPC_VLE_HI16D:
+@@ -6588,7 +6594,7 @@ md_apply_fix (fixS *fixP, valueT *valP,
+ }
+ break;
+ }
+- /* Fall thru */
++ /* Fallthru */
+
+ case BFD_RELOC_PPC_VLE_HA16A:
+ case BFD_RELOC_PPC_VLE_HA16D:
+@@ -6730,7 +6736,7 @@ md_apply_fix (fixS *fixP, valueT *valP,
+ case BFD_RELOC_PPC_VLE_SDAREL_HA16A:
+ case BFD_RELOC_PPC_VLE_SDAREL_HA16D:
+ gas_assert (fixP->fx_addsy != NULL);
+- /* Fall thru */
++ /* Fallthru */
+
+ case BFD_RELOC_PPC_TLS:
+ case BFD_RELOC_PPC_TLSGD:
+@@ -6854,7 +6860,7 @@ md_apply_fix (fixS *fixP, valueT *valP,
+ && !S_IS_DEFINED (fixP->fx_addsy)
+ && !S_IS_WEAK (fixP->fx_addsy))
+ S_SET_WEAK (fixP->fx_addsy);
+- /* Fall thru */
++ /* Fallthru */
+
+ case BFD_RELOC_VTABLE_ENTRY:
+ fixP->fx_done = 0;
+diff -rup binutils.orig/gas/testsuite/gas/ppc/power9.d binutils-2.27/gas/testsuite/gas/ppc/power9.d
+--- binutils.orig/gas/testsuite/gas/ppc/power9.d 2017-01-17 10:34:39.823866144 +0000
++++ binutils-2.27/gas/testsuite/gas/ppc/power9.d 2017-01-17 10:55:45.214908333 +0000
+@@ -274,8 +274,8 @@ Disassembly of section \.text:
+ .*: (f3 89 ef 6f|6f ef 89 f3) xvxsigsp vs60,vs61
+ .*: (7c 06 39 c0|c0 39 06 7c) cmpeqb cr0,r6,r7
+ .*: (7f 86 39 c0|c0 39 86 7f) cmpeqb cr7,r6,r7
+-.*: (7c 08 49 80|80 49 08 7c) cmprb cr0,r8,r9
+-.*: (7f 88 49 80|80 49 88 7f) cmprb cr7,r8,r9
++.*: (7c 08 49 80|80 49 08 7c) cmprb cr0,0,r8,r9
++.*: (7f 88 49 80|80 49 88 7f) cmprb cr7,0,r8,r9
+ .*: (7c 28 49 80|80 49 28 7c) cmprb cr0,1,r8,r9
+ .*: (7f a8 49 80|80 49 a8 7f) cmprb cr7,1,r8,r9
+ .*: (7d e0 01 00|00 01 e0 7d) setb r15,cr0
+diff -rup binutils.orig/gas/testsuite/gas/ppc/vle-reloc.d binutils-2.27/gas/testsuite/gas/ppc/vle-reloc.d
+--- binutils.orig/gas/testsuite/gas/ppc/vle-reloc.d 2017-01-17 10:34:39.822866157 +0000
++++ binutils-2.27/gas/testsuite/gas/ppc/vle-reloc.d 2017-01-17 10:53:43.744345513 +0000
+@@ -25,148 +25,148 @@ Disassembly of section \.text:
+ 14: R_PPC_VLE_REL15 sub5
+
+ 18: 70 20 c0 00 e_or2i r1,0
+- 18: R_PPC_VLE_LO16D low
++ 18: R_PPC_VLE_LO16A low
+ 1c: 70 40 c0 00 e_or2i r2,0
+- 1c: R_PPC_VLE_HI16D high
++ 1c: R_PPC_VLE_HI16A high
+ 20: 70 60 c0 00 e_or2i r3,0
+- 20: R_PPC_VLE_HA16D high_adjust
++ 20: R_PPC_VLE_HA16A high_adjust
+ 24: 70 80 c0 00 e_or2i r4,0
+- 24: R_PPC_VLE_SDAREL_LO16D low_sdarel
++ 24: R_PPC_VLE_SDAREL_LO16A low_sdarel
+ 28: 70 a0 c0 00 e_or2i r5,0
+- 28: R_PPC_VLE_SDAREL_HI16D high_sdarel
++ 28: R_PPC_VLE_SDAREL_HI16A high_sdarel
+ 2c: 70 40 c0 00 e_or2i r2,0
+- 2c: R_PPC_VLE_SDAREL_HA16D high_adjust_sdarel
++ 2c: R_PPC_VLE_SDAREL_HA16A high_adjust_sdarel
+ 30: 70 20 c8 00 e_and2i. r1,0
+- 30: R_PPC_VLE_LO16D low
++ 30: R_PPC_VLE_LO16A low
+ 34: 70 40 c8 00 e_and2i. r2,0
+- 34: R_PPC_VLE_HI16D high
++ 34: R_PPC_VLE_HI16A high
+ 38: 70 60 c8 00 e_and2i. r3,0
+- 38: R_PPC_VLE_HA16D high_adjust
++ 38: R_PPC_VLE_HA16A high_adjust
+ 3c: 70 80 c8 00 e_and2i. r4,0
+- 3c: R_PPC_VLE_SDAREL_LO16D low_sdarel
++ 3c: R_PPC_VLE_SDAREL_LO16A low_sdarel
+ 40: 70 a0 c8 00 e_and2i. r5,0
+- 40: R_PPC_VLE_SDAREL_HI16D high_sdarel
++ 40: R_PPC_VLE_SDAREL_HI16A high_sdarel
+ 44: 70 40 c8 00 e_and2i. r2,0
+- 44: R_PPC_VLE_SDAREL_HA16D high_adjust_sdarel
++ 44: R_PPC_VLE_SDAREL_HA16A high_adjust_sdarel
+ 48: 70 40 c8 00 e_and2i. r2,0
+- 48: R_PPC_VLE_SDAREL_HA16D high_adjust_sdarel
++ 48: R_PPC_VLE_SDAREL_HA16A high_adjust_sdarel
+ 4c: 70 20 d0 00 e_or2is r1,0
+- 4c: R_PPC_VLE_LO16D low
++ 4c: R_PPC_VLE_LO16A low
+ 50: 70 40 d0 00 e_or2is r2,0
+- 50: R_PPC_VLE_HI16D high
++ 50: R_PPC_VLE_HI16A high
+ 54: 70 60 d0 00 e_or2is r3,0
+- 54: R_PPC_VLE_HA16D high_adjust
++ 54: R_PPC_VLE_HA16A high_adjust
+ 58: 70 80 d0 00 e_or2is r4,0
+- 58: R_PPC_VLE_SDAREL_LO16D low_sdarel
++ 58: R_PPC_VLE_SDAREL_LO16A low_sdarel
+ 5c: 70 a0 d0 00 e_or2is r5,0
+- 5c: R_PPC_VLE_SDAREL_HI16D high_sdarel
++ 5c: R_PPC_VLE_SDAREL_HI16A high_sdarel
+ 60: 70 40 d0 00 e_or2is r2,0
+- 60: R_PPC_VLE_SDAREL_HA16D high_adjust_sdarel
++ 60: R_PPC_VLE_SDAREL_HA16A high_adjust_sdarel
+ 64: 70 20 e0 00 e_lis r1,0
+- 64: R_PPC_VLE_LO16D low
++ 64: R_PPC_VLE_LO16A low
+ 68: 70 40 e0 00 e_lis r2,0
+- 68: R_PPC_VLE_HI16D high
++ 68: R_PPC_VLE_HI16A high
+ 6c: 70 60 e0 00 e_lis r3,0
+- 6c: R_PPC_VLE_HA16D high_adjust
++ 6c: R_PPC_VLE_HA16A high_adjust
+ 70: 70 80 e0 00 e_lis r4,0
+- 70: R_PPC_VLE_SDAREL_LO16D low_sdarel
++ 70: R_PPC_VLE_SDAREL_LO16A low_sdarel
+ 74: 70 a0 e0 00 e_lis r5,0
+- 74: R_PPC_VLE_SDAREL_HI16D high_sdarel
++ 74: R_PPC_VLE_SDAREL_HI16A high_sdarel
+ 78: 70 40 e0 00 e_lis r2,0
+- 78: R_PPC_VLE_SDAREL_HA16D high_adjust_sdarel
++ 78: R_PPC_VLE_SDAREL_HA16A high_adjust_sdarel
+ 7c: 70 20 e8 00 e_and2is. r1,0
+- 7c: R_PPC_VLE_LO16D low
++ 7c: R_PPC_VLE_LO16A low
+ 80: 70 40 e8 00 e_and2is. r2,0
+- 80: R_PPC_VLE_HI16D high
++ 80: R_PPC_VLE_HI16A high
+ 84: 70 60 e8 00 e_and2is. r3,0
+- 84: R_PPC_VLE_HA16D high_adjust
++ 84: R_PPC_VLE_HA16A high_adjust
+ 88: 70 80 e8 00 e_and2is. r4,0
+- 88: R_PPC_VLE_SDAREL_LO16D low_sdarel
++ 88: R_PPC_VLE_SDAREL_LO16A low_sdarel
+ 8c: 70 a0 e8 00 e_and2is. r5,0
+- 8c: R_PPC_VLE_SDAREL_HI16D high_sdarel
++ 8c: R_PPC_VLE_SDAREL_HI16A high_sdarel
+ 90: 70 40 e8 00 e_and2is. r2,0
+- 90: R_PPC_VLE_SDAREL_HA16D high_adjust_sdarel
++ 90: R_PPC_VLE_SDAREL_HA16A high_adjust_sdarel
+ 94: 70 01 98 00 e_cmp16i r1,0
+- 94: R_PPC_VLE_LO16A low
++ 94: R_PPC_VLE_LO16D low
+ 98: 70 02 98 00 e_cmp16i r2,0
+- 98: R_PPC_VLE_HI16A high
++ 98: R_PPC_VLE_HI16D high
+ 9c: 70 03 98 00 e_cmp16i r3,0
+- 9c: R_PPC_VLE_HA16A high_adjust
++ 9c: R_PPC_VLE_HA16D high_adjust
+ a0: 70 04 98 00 e_cmp16i r4,0
+- a0: R_PPC_VLE_SDAREL_LO16A low_sdarel
++ a0: R_PPC_VLE_SDAREL_LO16D low_sdarel
+ a4: 70 05 98 00 e_cmp16i r5,0
+- a4: R_PPC_VLE_SDAREL_HI16A high_sdarel
++ a4: R_PPC_VLE_SDAREL_HI16D high_sdarel
+ a8: 70 02 98 00 e_cmp16i r2,0
+- a8: R_PPC_VLE_SDAREL_HA16A high_adjust_sdarel
++ a8: R_PPC_VLE_SDAREL_HA16D high_adjust_sdarel
+ ac: 70 01 a8 00 e_cmpl16i r1,0
+- ac: R_PPC_VLE_LO16A low
++ ac: R_PPC_VLE_LO16D low
+ b0: 70 02 a8 00 e_cmpl16i r2,0
+- b0: R_PPC_VLE_HI16A high
++ b0: R_PPC_VLE_HI16D high
+ b4: 70 03 a8 00 e_cmpl16i r3,0
+- b4: R_PPC_VLE_HA16A high_adjust
++ b4: R_PPC_VLE_HA16D high_adjust
+ b8: 70 04 a8 00 e_cmpl16i r4,0
+- b8: R_PPC_VLE_SDAREL_LO16A low_sdarel
++ b8: R_PPC_VLE_SDAREL_LO16D low_sdarel
+ bc: 70 05 a8 00 e_cmpl16i r5,0
+- bc: R_PPC_VLE_SDAREL_HI16A high_sdarel
++ bc: R_PPC_VLE_SDAREL_HI16D high_sdarel
+ c0: 70 02 a8 00 e_cmpl16i r2,0
+- c0: R_PPC_VLE_SDAREL_HA16A high_adjust_sdarel
++ c0: R_PPC_VLE_SDAREL_HA16D high_adjust_sdarel
+ c4: 70 01 b0 00 e_cmph16i r1,0
+- c4: R_PPC_VLE_LO16A low
++ c4: R_PPC_VLE_LO16D low
+ c8: 70 02 b0 00 e_cmph16i r2,0
+- c8: R_PPC_VLE_HI16A high
++ c8: R_PPC_VLE_HI16D high
+ cc: 70 03 b0 00 e_cmph16i r3,0
+- cc: R_PPC_VLE_HA16A high_adjust
++ cc: R_PPC_VLE_HA16D high_adjust
+ d0: 70 04 b0 00 e_cmph16i r4,0
+- d0: R_PPC_VLE_SDAREL_LO16A low_sdarel
++ d0: R_PPC_VLE_SDAREL_LO16D low_sdarel
+ d4: 70 05 b0 00 e_cmph16i r5,0
+- d4: R_PPC_VLE_SDAREL_HI16A high_sdarel
++ d4: R_PPC_VLE_SDAREL_HI16D high_sdarel
+ d8: 70 02 b0 00 e_cmph16i r2,0
+- d8: R_PPC_VLE_SDAREL_HA16A high_adjust_sdarel
++ d8: R_PPC_VLE_SDAREL_HA16D high_adjust_sdarel
+ dc: 70 01 b8 00 e_cmphl16i r1,0
+- dc: R_PPC_VLE_LO16A low
++ dc: R_PPC_VLE_LO16D low
+ e0: 70 02 b8 00 e_cmphl16i r2,0
+- e0: R_PPC_VLE_HI16A high
++ e0: R_PPC_VLE_HI16D high
+ e4: 70 03 b8 00 e_cmphl16i r3,0
+- e4: R_PPC_VLE_HA16A high_adjust
++ e4: R_PPC_VLE_HA16D high_adjust
+ e8: 70 04 b8 00 e_cmphl16i r4,0
+- e8: R_PPC_VLE_SDAREL_LO16A low_sdarel
++ e8: R_PPC_VLE_SDAREL_LO16D low_sdarel
+ ec: 70 05 b8 00 e_cmphl16i r5,0
+- ec: R_PPC_VLE_SDAREL_HI16A high_sdarel
++ ec: R_PPC_VLE_SDAREL_HI16D high_sdarel
+ f0: 70 02 b8 00 e_cmphl16i r2,0
+- f0: R_PPC_VLE_SDAREL_HA16A high_adjust_sdarel
++ f0: R_PPC_VLE_SDAREL_HA16D high_adjust_sdarel
+ f4: 70 01 88 00 e_add2i. r1,0
+- f4: R_PPC_VLE_LO16A low
++ f4: R_PPC_VLE_LO16D low
+ f8: 70 02 88 00 e_add2i. r2,0
+- f8: R_PPC_VLE_HI16A high
++ f8: R_PPC_VLE_HI16D high
+ fc: 70 03 88 00 e_add2i. r3,0
+- fc: R_PPC_VLE_HA16A high_adjust
++ fc: R_PPC_VLE_HA16D high_adjust
+ 100: 70 04 88 00 e_add2i. r4,0
+- 100: R_PPC_VLE_SDAREL_LO16A low_sdarel
++ 100: R_PPC_VLE_SDAREL_LO16D low_sdarel
+ 104: 70 05 88 00 e_add2i. r5,0
+- 104: R_PPC_VLE_SDAREL_HI16A high_sdarel
++ 104: R_PPC_VLE_SDAREL_HI16D high_sdarel
+ 108: 70 02 88 00 e_add2i. r2,0
+- 108: R_PPC_VLE_SDAREL_HA16A high_adjust_sdarel
++ 108: R_PPC_VLE_SDAREL_HA16D high_adjust_sdarel
+ 10c: 70 01 90 00 e_add2is r1,0
+- 10c: R_PPC_VLE_LO16A low
++ 10c: R_PPC_VLE_LO16D low
+ 110: 70 02 90 00 e_add2is r2,0
+- 110: R_PPC_VLE_HI16A high
++ 110: R_PPC_VLE_HI16D high
+ 114: 70 03 90 00 e_add2is r3,0
+- 114: R_PPC_VLE_HA16A high_adjust
++ 114: R_PPC_VLE_HA16D high_adjust
+ 118: 70 04 90 00 e_add2is r4,0
+- 118: R_PPC_VLE_SDAREL_LO16A low_sdarel
++ 118: R_PPC_VLE_SDAREL_LO16D low_sdarel
+ 11c: 70 05 90 00 e_add2is r5,0
+- 11c: R_PPC_VLE_SDAREL_HI16A high_sdarel
++ 11c: R_PPC_VLE_SDAREL_HI16D high_sdarel
+ 120: 70 02 90 00 e_add2is r2,0
+- 120: R_PPC_VLE_SDAREL_HA16A high_adjust_sdarel
++ 120: R_PPC_VLE_SDAREL_HA16D high_adjust_sdarel
+ 124: 70 01 a0 00 e_mull2i r1,0
+- 124: R_PPC_VLE_LO16A low
++ 124: R_PPC_VLE_LO16D low
+ 128: 70 02 a0 00 e_mull2i r2,0
+- 128: R_PPC_VLE_HI16A high
++ 128: R_PPC_VLE_HI16D high
+ 12c: 70 03 a0 00 e_mull2i r3,0
+- 12c: R_PPC_VLE_HA16A high_adjust
++ 12c: R_PPC_VLE_HA16D high_adjust
+ 130: 70 04 a0 00 e_mull2i r4,0
+- 130: R_PPC_VLE_SDAREL_LO16A low_sdarel
++ 130: R_PPC_VLE_SDAREL_LO16D low_sdarel
+ 134: 70 05 a0 00 e_mull2i r5,0
+- 134: R_PPC_VLE_SDAREL_HI16A high_sdarel
++ 134: R_PPC_VLE_SDAREL_HI16D high_sdarel
+ 138: 70 02 a0 00 e_mull2i r2,0
+- 138: R_PPC_VLE_SDAREL_HA16A high_adjust_sdarel
++ 138: R_PPC_VLE_SDAREL_HA16D high_adjust_sdarel
+diff -rup binutils.orig/include/opcode/ppc.h binutils-2.27/include/opcode/ppc.h
+--- binutils.orig/include/opcode/ppc.h 2017-01-17 10:34:39.864865661 +0000
++++ binutils-2.27/include/opcode/ppc.h 2017-01-17 10:49:40.367225030 +0000
+@@ -407,6 +407,10 @@ extern const unsigned int num_powerpc_op
+ is omitted, then the value it should use for the operand is stored
+ in the SHIFT field of the immediatly following operand field. */
+ #define PPC_OPERAND_OPTIONAL_VALUE (0x400000)
++
++/* This flag is only used with PPC_OPERAND_OPTIONAL. The operand is
++ only optional when generating 32-bit code. */
++#define PPC_OPERAND_OPTIONAL32 (0x800000)
+
+ /* The POWER and PowerPC assemblers use a few macros. We keep them
+ with the operands table for simplicity. The macro table is an
+@@ -444,6 +448,23 @@ ppc_optional_operand_value (const struct
+ return 0;
+ }
+
++/* PowerPC VLE insns. */
++/* Form I16L, uses 16A relocs. */
++#define E_OR2I_INSN 0x7000C000
++#define E_AND2I_DOT_INSN 0x7000C800
++#define E_OR2IS_INSN 0x7000D000
++#define E_LIS_INSN 0x7000E000
++#define E_AND2IS_DOT_INSN 0x7000E800
++
++/* Form I16A, uses 16D relocs. */
++#define E_ADD2I_DOT_INSN 0x70008800
++#define E_ADD2IS_INSN 0x70009000
++#define E_CMP16I_INSN 0x70009800
++#define E_MULL2I_INSN 0x7000A000
++#define E_CMPL16I_INSN 0x7000A800
++#define E_CMPH16I_INSN 0x7000B000
++#define E_CMPHL16I_INSN 0x7000B800
++
+ #ifdef __cplusplus
+ }
+ #endif
+diff -rup binutils.orig/opcodes/ppc-dis.c binutils-2.27/opcodes/ppc-dis.c
+--- binutils.orig/opcodes/ppc-dis.c 2017-01-17 10:34:40.064863304 +0000
++++ binutils-2.27/opcodes/ppc-dis.c 2017-01-17 10:49:40.391224746 +0000
+@@ -236,7 +236,7 @@ get_powerpc_dialect (struct disassemble_
+
+ /* Disassemble according to the section headers flags for VLE-mode. */
+ if (dialect & PPC_OPCODE_VLE
+- && info->section->owner != NULL
++ && info->section != NULL && info->section->owner != NULL
+ && bfd_get_flavour (info->section->owner) == bfd_target_elf_flavour
+ && elf_object_id (info->section->owner) == PPC32_ELF_DATA
+ && (elf_section_flags (info->section) & SHF_PPC_VLE) != 0)
+diff -rup binutils.orig/opcodes/ppc-opc.c binutils-2.27/opcodes/ppc-opc.c
+--- binutils.orig/opcodes/ppc-opc.c 2017-01-17 10:34:40.064863304 +0000
++++ binutils-2.27/opcodes/ppc-opc.c 2017-01-17 10:49:40.393224722 +0000
+@@ -62,10 +62,6 @@ static unsigned long insert_dxdn (unsign
+ static long extract_dxdn (unsigned long, ppc_cpu_t, int *);
+ static unsigned long insert_fxm (unsigned long, long, ppc_cpu_t, const char **);
+ static long extract_fxm (unsigned long, ppc_cpu_t, int *);
+-static unsigned long insert_l0 (unsigned long, long, ppc_cpu_t, const char **);
+-static long extract_l0 (unsigned long, ppc_cpu_t, int *);
+-static unsigned long insert_l1 (unsigned long, long, ppc_cpu_t, const char **);
+-static long extract_l1 (unsigned long, ppc_cpu_t, int *);
+ static unsigned long insert_li20 (unsigned long, long, ppc_cpu_t, const char **);
+ static long extract_li20 (unsigned long, ppc_cpu_t, int *);
+ static unsigned long insert_ls (unsigned long, long, ppc_cpu_t, const char **);
+@@ -429,20 +425,24 @@ const struct powerpc_operand powerpc_ope
+
+ /* The L field in a D or X form instruction. */
+ #define L IMM20 + 1
++ { 0x1, 21, NULL, NULL, 0 },
++
++ /* The optional L field in tlbie and tlbiel instructions. */
++#define LOPT L + 1
+ /* The R field in a HTM X form instruction. */
+-#define HTM_R L
++#define HTM_R LOPT
+ { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
+
+- /* The L field in an X form instruction which must be zero. */
+-#define L0 L + 1
+- { 0x1, 21, insert_l0, extract_l0, PPC_OPERAND_OPTIONAL },
+-
+- /* The L field in an X form instruction which must be one. */
+-#define L1 L0 + 1
+- { 0x1, 21, insert_l1, extract_l1, 0 },
++ /* The optional (for 32-bit) L field in cmp[l][i] instructions. */
++#define L32OPT LOPT + 1
++ { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL32 },
++
++ /* The L field in dcbf instruction. */
++#define L2OPT L32OPT + 1
++ { 0x3, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
+
+ /* The LEV field in a POWER SVC form instruction. */
+-#define SVC_LEV L1 + 1
++#define SVC_LEV L2OPT + 1
+ { 0x7f, 5, NULL, NULL, 0 },
+
+ /* The LEV field in an SC form instruction. */
+@@ -688,6 +688,8 @@ const struct powerpc_operand powerpc_ope
+ #define STRM SR + 1
+ /* The T field in a tlbilx form instruction. */
+ #define T STRM
++ /* The L field in wclr instructions. */
++#define L2 STRM
+ { 0x3, 21, NULL, NULL, 0 },
+
+ /* The ESYNC field in an X (sync) form instruction. */
+@@ -1483,58 +1485,6 @@ extract_fxm (unsigned long insn,
+ return mask;
+ }
+
+-/* The L field in an X form instruction which must have the value zero. */
+-
+-static unsigned long
+-insert_l0 (unsigned long insn,
+- long value,
+- ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+- const char **errmsg)
+-{
+- if (value != 0)
+- *errmsg = _("invalid operand constant");
+- return insn & ~(0x1 << 21);
+-}
+-
+-static long
+-extract_l0 (unsigned long insn,
+- ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+- int *invalid)
+-{
+- long value;
+-
+- value = (insn >> 21) & 0x1;
+- if (value != 0)
+- *invalid = 1;
+- return value;
+-}
+-
+-/* The L field in an X form instruction which must have the value one. */
+-
+-static unsigned long
+-insert_l1 (unsigned long insn,
+- long value,
+- ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+- const char **errmsg)
+-{
+- if (value != 1)
+- *errmsg = _("invalid operand constant");
+- return insn | (0x1 << 21);
+-}
+-
+-static long
+-extract_l1 (unsigned long insn,
+- ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+- int *invalid)
+-{
+- long value;
+-
+- value = (insn >> 21) & 0x1;
+- if (value != 1)
+- *invalid = 1;
+- return value;
+-}
+-
+ static unsigned long
+ insert_li20 (unsigned long insn,
+ long value,
+@@ -3890,12 +3840,12 @@ const struct powerpc_opcode powerpc_opco
+
+ {"cmplwi", OPL(10,0), OPL_MASK, PPCCOM, PPCVLE, {OBF, RA, UISIGNOPT}},
+ {"cmpldi", OPL(10,1), OPL_MASK, PPC64, PPCVLE, {OBF, RA, UISIGNOPT}},
+-{"cmpli", OP(10), OP_MASK, PPC, PPCVLE, {BF, L, RA, UISIGNOPT}},
++{"cmpli", OP(10), OP_MASK, PPC, PPCVLE, {BF, L32OPT, RA, UISIGNOPT}},
+ {"cmpli", OP(10), OP_MASK, PWRCOM, PPC|PPCVLE, {BF, RA, UISIGNOPT}},
+
+ {"cmpwi", OPL(11,0), OPL_MASK, PPCCOM, PPCVLE, {OBF, RA, SI}},
+ {"cmpdi", OPL(11,1), OPL_MASK, PPC64, PPCVLE, {OBF, RA, SI}},
+-{"cmpi", OP(11), OP_MASK, PPC, PPCVLE, {BF, L, RA, SI}},
++{"cmpi", OP(11), OP_MASK, PPC, PPCVLE, {BF, L32OPT, RA, SI}},
+ {"cmpi", OP(11), OP_MASK, PWRCOM, PPC|PPCVLE, {BF, RA, SI}},
+
+ {"addic", OP(12), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}},
+@@ -4713,7 +4663,7 @@ const struct powerpc_opcode powerpc_opco
+
+ {"cmpw", XOPL(31,0,0), XCMPL_MASK, PPCCOM, 0, {OBF, RA, RB}},
+ {"cmpd", XOPL(31,0,1), XCMPL_MASK, PPC64, 0, {OBF, RA, RB}},
+-{"cmp", X(31,0), XCMP_MASK, PPC, 0, {BF, L, RA, RB}},
++{"cmp", X(31,0), XCMP_MASK, PPC, 0, {BF, L32OPT, RA, RB}},
+ {"cmp", X(31,0), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}},
+
+ {"twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, 0, {RA, RB}},
+@@ -4821,7 +4771,7 @@ const struct powerpc_opcode powerpc_opco
+
+ {"cmplw", XOPL(31,32,0), XCMPL_MASK, PPCCOM, 0, {OBF, RA, RB}},
+ {"cmpld", XOPL(31,32,1), XCMPL_MASK, PPC64, 0, {OBF, RA, RB}},
+-{"cmpl", X(31,32), XCMP_MASK, PPC, 0, {BF, L, RA, RB}},
++{"cmpl", X(31,32), XCMP_MASK, PPC, 0, {BF, L32OPT, RA, RB}},
+ {"cmpl", X(31,32), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}},
+
+ {"lvsr", X(31,38), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
+@@ -4907,7 +4857,7 @@ const struct powerpc_opcode powerpc_opco
+ {"ldarx", X(31,84), XEH_MASK, PPC64, 0, {RT, RA0, RB, EH}},
+
+ {"dcbfl", XOPL(31,86,1), XRT_MASK, POWER5, PPC476, {RA0, RB}},
+-{"dcbf", X(31,86), XLRT_MASK, PPC, 0, {RA0, RB, L}},
++{"dcbf", X(31,86), XLRT_MASK, PPC, 0, {RA0, RB, L2OPT}},
+
+ {"lbzx", X(31,87), X_MASK, COM, 0, {RT, RA0, RB}},
+
+@@ -5149,7 +5099,7 @@ const struct powerpc_opcode powerpc_opco
+ {"ehpriv", X(31,270), 0xffffffff, E500MC|PPCA2, 0, {0}},
+
+ {"tlbiel", X(31,274), X_MASK|1<<20,POWER9, PPC476, {RB, RSO, RIC, PRS, X_R}},
+-{"tlbiel", X(31,274), XRTLRA_MASK, POWER4, POWER9|PPC476, {RB, L}},
++{"tlbiel", X(31,274), XRTLRA_MASK, POWER4, POWER9|PPC476, {RB, LOPT}},
+
+ {"mfapidi", X(31,275), X_MASK, BOOKE, E500|TITAN, {RT, RA}},
+
+@@ -6233,8 +6183,8 @@ const struct powerpc_opcode powerpc_opco
+ {"stvfrxl", X(31,933), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
+
+ {"wclrone", XOPL2(31,934,2),XRT_MASK, PPCA2, 0, {RA0, RB}},
+-{"wclrall", X(31,934), XRARB_MASK, PPCA2, 0, {L}},
+-{"wclr", X(31,934), X_MASK, PPCA2, 0, {L, RA0, RB}},
++{"wclrall", X(31,934), XRARB_MASK, PPCA2, 0, {L2}},
++{"wclr", X(31,934), X_MASK, PPCA2, 0, {L2, RA0, RB}},
+
+ {"stvrxl", X(31,935), X_MASK, CELL, 0, {VS, RA0, RB}},
+
diff --git a/SOURCES/binutils-2.27-power9.3.patch b/SOURCES/binutils-2.27-power9.3.patch
new file mode 100644
index 0000000..8c6ad4f
--- /dev/null
+++ b/SOURCES/binutils-2.27-power9.3.patch
@@ -0,0 +1,87 @@
+diff -rup binutils.orig/gas/testsuite/gas/ppc/power9.d binutils-2.27/gas/testsuite/gas/ppc/power9.d
+--- binutils.orig/gas/testsuite/gas/ppc/power9.d 2017-09-13 09:46:21.695333611 +0100
++++ binutils-2.27/gas/testsuite/gas/ppc/power9.d 2017-09-13 09:53:46.594277167 +0100
+@@ -312,8 +312,9 @@ Disassembly of section \.text:
+ .*: (f1 31 9d 6f|6f 9d 31 f1) xscvdphp vs41,vs51
+ .*: (f1 58 a7 6f|6f a7 58 f1) xvcvhpsp vs42,vs52
+ .*: (f1 79 af 6f|6f af 79 f1) xvcvsphp vs43,vs53
+-.*: (4c 60 00 04|04 00 60 4c) addpcis r3,0
+-.*: (4c 60 00 04|04 00 60 4c) addpcis r3,0
++.*: (4c 60 00 04|04 00 60 4c) lnia r3
++.*: (4c 60 00 04|04 00 60 4c) lnia r3
++.*: (4c 60 00 04|04 00 60 4c) lnia r3
+ .*: (4c 80 00 05|05 00 80 4c) addpcis r4,1
+ .*: (4c 80 00 05|05 00 80 4c) addpcis r4,1
+ .*: (4c bf ff c4|c4 ff bf 4c) addpcis r5,-2
+@@ -391,4 +392,7 @@ Disassembly of section \.text:
+ .*: (ff d7 04 8e|8e 04 d7 ff) mffscrni f30,0
+ .*: (ff d7 1c 8e|8e 1c d7 ff) mffscrni f30,3
+ .*: (ff f8 04 8e|8e 04 f8 ff) mffsl f31
++.*: (01 00 00 44|44 00 00 01) scv 0
++.*: (e1 0f 00 44|44 00 0f e1) scv 127
++.*: (a4 00 00 4c|4c 00 00 a4) rfscv
+ #pass
+diff -rup binutils.orig/gas/testsuite/gas/ppc/power9.s binutils-2.27/gas/testsuite/gas/ppc/power9.s
+--- binutils.orig/gas/testsuite/gas/ppc/power9.s 2017-09-13 09:46:21.694333623 +0100
++++ binutils-2.27/gas/testsuite/gas/ppc/power9.s 2017-09-13 09:54:01.747104949 +0100
+@@ -303,6 +303,7 @@ power9:
+ xscvdphp 41,51
+ xvcvhpsp 42,52
+ xvcvsphp 43,53
++ lnia 3
+ addpcis 3,0
+ subpcis 3,0
+ addpcis 4,1
+@@ -382,3 +383,6 @@ power9:
+ mffscrni 30,0
+ mffscrni 30,3
+ mffsl 31
++ scv 0
++ scv 127
++ rfscv
+diff -rup binutils.orig/opcodes/ppc-opc.c binutils-2.27/opcodes/ppc-opc.c
+--- binutils.orig/opcodes/ppc-opc.c 2017-09-13 09:46:21.874331577 +0100
++++ binutils-2.27/opcodes/ppc-opc.c 2017-09-13 09:55:18.745229836 +0100
+@@ -441,7 +441,7 @@ const struct powerpc_operand powerpc_ope
+ #define L2OPT L32OPT + 1
+ { 0x3, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
+
+- /* The LEV field in a POWER SVC form instruction. */
++ /* The LEV field in a POWER SVC / POWER9 SCV form instruction. */
+ #define SVC_LEV L2OPT + 1
+ { 0x7f, 5, NULL, NULL, 0 },
+
+@@ -2447,6 +2447,9 @@ extract_vleil (unsigned long insn,
+ #define DX(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
+ #define DX_MASK DX (0x3f, 0x1f)
+
++/* An DX form instruction with the D bits specified. */
++#define NODX_MASK (DX_MASK | 0x1fffc1)
++
+ /* An EVSEL form instruction. */
+ #define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
+ #define EVSEL_MASK EVSEL(0x3f, 0xff)
+@@ -4145,6 +4148,7 @@ const struct powerpc_opcode powerpc_opco
+ {"bcla", B(16,1,1), B_MASK, COM, PPCVLE, {BO, BI, BDA}},
+
+ {"svc", SC(17,0,0), SC_MASK, POWER, PPCVLE, {SVC_LEV, FL1, FL2}},
++{"scv", SC(17,0,1), SC_MASK, POWER9, PPCVLE, {SVC_LEV}},
+ {"svcl", SC(17,0,1), SC_MASK, POWER, PPCVLE, {SVC_LEV, FL1, FL2}},
+ {"sc", SC(17,1,0), SC_MASK, PPC, PPCVLE, {LEV}},
+ {"svca", SC(17,1,0), SC_MASK, PWRCOM, PPCVLE, {SV}},
+@@ -4157,6 +4161,7 @@ const struct powerpc_opcode powerpc_opco
+
+ {"mcrf", XL(19,0), XLBB_MASK|(3<<21)|(3<<16), COM, PPCVLE, {BF, BFA}},
+
++{"lnia", DX(19,2), NODX_MASK, POWER9, PPCVLE, {RT}},
+ {"addpcis", DX(19,2), DX_MASK, POWER9, PPCVLE, {RT, DXD}},
+ {"subpcis", DX(19,2), DX_MASK, POWER9, PPCVLE, {RT, NDXD}},
+
+@@ -4394,6 +4399,7 @@ const struct powerpc_opcode powerpc_opco
+ {"rfi", XL(19,50), 0xffffffff, COM, PPCVLE, {0}},
+ {"rfci", XL(19,51), 0xffffffff, PPC403|BOOKE|PPCE300|PPCA2|PPC476, PPCVLE, {0}},
+
++{"rfscv", XL(19,82), 0xffffffff, POWER9, PPCVLE, {0}},
+ {"rfsvc", XL(19,82), 0xffffffff, POWER, PPCVLE, {0}},
+
+ {"rfgi", XL(19,102), 0xffffffff, E500MC|PPCA2, PPCVLE, {0}},
diff --git a/SOURCES/binutils-2.27-power9.patch b/SOURCES/binutils-2.27-power9.patch
new file mode 100644
index 0000000..e632e80
--- /dev/null
+++ b/SOURCES/binutils-2.27-power9.patch
@@ -0,0 +1,452 @@
+diff -rup binutils-2.27.orig/bfd/elf32-ppc.c binutils-2.27/bfd/elf32-ppc.c
+--- binutils-2.27.orig/bfd/elf32-ppc.c 2016-09-28 08:49:28.280430815 +0100
++++ binutils-2.27/bfd/elf32-ppc.c 2016-09-28 08:53:48.133843615 +0100
+@@ -3946,7 +3946,8 @@ is_branch_reloc (enum elf_ppc_reloc_type
+ || r_type == R_PPC_ADDR24
+ || r_type == R_PPC_ADDR14
+ || r_type == R_PPC_ADDR14_BRTAKEN
+- || r_type == R_PPC_ADDR14_BRNTAKEN);
++ || r_type == R_PPC_ADDR14_BRNTAKEN
++ || r_type == R_PPC_VLE_REL24);
+ }
+
+ static void
+@@ -4897,6 +4898,7 @@ ppc_elf_vle_split16 (bfd *output_bfd, bf
+ insn = bfd_get_32 (output_bfd, loc);
+ top5 = value & 0xf800;
+ top5 = top5 << (split16_format == split16a_type ? 9 : 5);
++ insn &= (split16_format == split16a_type ? ~0x1f007ff : ~0x1f07ff);
+ insn |= top5;
+ insn |= value & 0x7ff;
+ bfd_put_32 (output_bfd, insn, loc);
+diff -rup binutils-2.27.orig/gas/testsuite/gas/ppc/power9.d binutils-2.27/gas/testsuite/gas/ppc/power9.d
+--- binutils-2.27.orig/gas/testsuite/gas/ppc/power9.d 2016-09-28 08:49:28.783433550 +0100
++++ binutils-2.27/gas/testsuite/gas/ppc/power9.d 2016-09-28 08:53:47.423839755 +0100
+@@ -280,14 +280,6 @@ Disassembly of section \.text:
+ .*: (7f a8 49 80|80 49 a8 7f) cmprb cr7,1,r8,r9
+ .*: (7d e0 01 00|00 01 e0 7d) setb r15,cr0
+ .*: (7d fc 01 00|00 01 fc 7d) setb r15,cr7
+-.*: (7e 00 01 01|01 01 00 7e) setbool r16,lt
+-.*: (7e 01 01 01|01 01 01 7e) setbool r16,gt
+-.*: (7e 02 01 01|01 01 02 7e) setbool r16,eq
+-.*: (7e 03 01 01|01 01 03 7e) setbool r16,so
+-.*: (7e 1c 01 01|01 01 1c 7e) setbool r16,4\*cr7\+lt
+-.*: (7e 1d 01 01|01 01 1d 7e) setbool r16,4\*cr7\+gt
+-.*: (7e 1e 01 01|01 01 1e 7e) setbool r16,4\*cr7\+eq
+-.*: (7e 1f 01 01|01 01 1f 7e) setbool r16,4\*cr7\+so
+ .*: (7f 40 52 1a|1a 52 40 7f) lxvl vs26,0,r10
+ .*: (7f 14 52 1b|1b 52 14 7f) lxvl vs56,r20,r10
+ .*: (7f 60 5b 1a|1a 5b 60 7f) stxvl vs27,0,r11
+@@ -331,6 +323,7 @@ Disassembly of section \.text:
+ .*: (4c e0 80 04|04 80 e0 4c) addpcis r7,-32768
+ .*: (4c e0 80 04|04 80 e0 4c) addpcis r7,-32768
+ .*: (7c 00 02 a4|a4 02 00 7c) slbsync
++.*: (7d 40 06 a4|a4 06 40 7d) slbiag r10
+ .*: (7d 40 5b a4|a4 5b 40 7d) slbieg r10,r11
+ .*: (7c 60 27 26|26 27 60 7c) slbmfee r3,r4
+ .*: (7c 60 27 26|26 27 60 7c) slbmfee r3,r4
+@@ -344,14 +337,9 @@ Disassembly of section \.text:
+ .*: (7c 00 1a 24|24 1a 00 7c) tlbiel r3
+ .*: (7c 00 1a 24|24 1a 00 7c) tlbiel r3
+ .*: (7c 8f 1a 24|24 1a 8f 7c) tlbiel r3,r4,3,1,1
+-.*: (7c 0c 6e 0c|0c 6e 0c 7c) copy r12,r13
+-.*: (7c 2c 6e 0c|0c 6e 2c 7c) copy_first r12,r13
+-.*: (7c 2c 6e 0c|0c 6e 2c 7c) copy_first r12,r13
+-.*: (7c 0a 5f 0c|0c 5f 0a 7c) paste r10,r11
+-.*: (7c 0a 5f 0c|0c 5f 0a 7c) paste r10,r11
+-.*: (7c 2a 5f 0d|0d 5f 2a 7c) paste_last r10,r11
+-.*: (7c 2a 5f 0d|0d 5f 2a 7c) paste_last r10,r11
+-.*: (7c 00 06 8c|8c 06 00 7c) cp_abort
++.*: (7c 2c 6e 0c|0c 6e 2c 7c) copy r12,r13
++.*: (7c 2a 5f 0d|0d 5f 2a 7c) paste\. r10,r11
++.*: (7c 00 06 8c|8c 06 00 7c) cpabort
+ .*: (7c 00 04 ac|ac 04 00 7c) hwsync
+ .*: (7c 00 04 ac|ac 04 00 7c) hwsync
+ .*: (7c 00 04 ac|ac 04 00 7c) hwsync
+@@ -359,8 +347,6 @@ Disassembly of section \.text:
+ .*: (7c 20 04 ac|ac 04 20 7c) lwsync
+ .*: (7c 40 04 ac|ac 04 40 7c) ptesync
+ .*: (7c 40 04 ac|ac 04 40 7c) ptesync
+-.*: (7c 07 04 ac|ac 04 07 7c) sync 0,7
+-.*: (7c 28 04 ac|ac 04 28 7c) sync 1,8
+ .*: (7e 80 04 cc|cc 04 80 7e) ldat r20,0,0
+ .*: (7e 8a e4 cc|cc e4 8a 7e) ldat r20,r10,28
+ .*: (7e a0 04 8c|8c 04 a0 7e) lwat r21,0,0
+@@ -373,8 +359,6 @@ Disassembly of section \.text:
+ .*: (7c 00 f6 e4|e4 f6 00 7c) rmieg r30
+ .*: (7d 40 7a 6a|6a 7a 40 7d) ldmx r10,0,r15
+ .*: (7d 43 7a 6a|6a 7a 43 7d) ldmx r10,r3,r15
+-.*: (7d 60 83 6a|6a 83 60 7d) lwzmx r11,0,r16
+-.*: (7d 63 83 6a|6a 83 63 7d) lwzmx r11,r3,r16
+ .*: (4c 00 02 e4|e4 02 00 4c) stop
+ .*: (7c 00 00 3c|3c 00 00 7c) wait
+ .*: (7c 00 00 3c|3c 00 00 7c) wait
+@@ -397,9 +381,6 @@ Disassembly of section \.text:
+ .*: (7d 6c 69 54|54 69 6c 7d) addex r11,r12,r13,0
+ .*: (7d 6c 6b 54|54 6b 6c 7d) addex r11,r12,r13,1
+ .*: (7d 6c 6d 54|54 6d 6c 7d) addex r11,r12,r13,2
+-.*: (7e b6 b9 55|55 b9 b6 7e) addex\. r21,r22,r23,0
+-.*: (7e b6 bb 55|55 bb b6 7e) addex\. r21,r22,r23,1
+-.*: (7e b6 bd 55|55 bd b6 7e) addex\. r21,r22,r23,2
+ .*: (ff 20 04 8e|8e 04 20 ff) mffs f25
+ .*: (ff 20 04 8f|8f 04 20 ff) mffs\. f25
+ .*: (ff 41 04 8e|8e 04 41 ff) mffsce f26
+@@ -410,12 +391,4 @@ Disassembly of section \.text:
+ .*: (ff d7 04 8e|8e 04 d7 ff) mffscrni f30,0
+ .*: (ff d7 1c 8e|8e 1c d7 ff) mffscrni f30,3
+ .*: (ff f8 04 8e|8e 04 f8 ff) mffsl f31
+-.*: (7e 8a 01 76|76 01 8a 7e) brd r10,r20
+-.*: (7e ab 01 b6|b6 01 ab 7e) brh r11,r21
+-.*: (7e cc 01 36|36 01 cc 7e) brw r12,r22
+-.*: (11 6a 63 77|77 63 6a 11) nandxor r10,r11,r12,r13
+-.*: (12 b4 b5 f6|f6 b5 b4 12) xor3 r20,r21,r22,r23
+-.*: (11 6a 60 34|34 60 6a 11) rldixor r10,r11,0,r12
+-.*: (11 6a 66 f4|f4 66 6a 11) rldixor r10,r11,27,r12
+-.*: (11 6a 67 f5|f5 67 6a 11) rldixor r10,r11,63,r12
+ #pass
+diff -rup binutils-2.27.orig/gas/testsuite/gas/ppc/power9.s binutils-2.27/gas/testsuite/gas/ppc/power9.s
+--- binutils-2.27.orig/gas/testsuite/gas/ppc/power9.s 2016-09-28 08:49:28.783433550 +0100
++++ binutils-2.27/gas/testsuite/gas/ppc/power9.s 2016-09-28 08:53:47.424839761 +0100
+@@ -271,14 +271,6 @@ power9:
+ cmprb 7,1,8,9
+ setb 15,0
+ setb 15,7
+- setbool 16,0
+- setbool 16,1
+- setbool 16,2
+- setbool 16,3
+- setbool 16,28
+- setbool 16,29
+- setbool 16,30
+- setbool 16,31
+ lxvl 26,0,10
+ lxvl 56,20,10
+ stxvl 27,0,11
+@@ -322,6 +314,7 @@ power9:
+ addpcis 7,-0x8000
+ subpcis 7,0x8000
+ slbsync
++ slbiag 10
+ slbieg 10,11
+ slbmfee 3,4
+ slbmfee 3,4,0
+@@ -335,23 +328,16 @@ power9:
+ tlbiel 3
+ tlbiel 3,0,0,0,0
+ tlbiel 3,4,3,1,1
+- copy 12,13,0
+- copy_first 12,13
+- copy 12,13,1
+- paste 10,11,0
+- paste 10,11
+- paste. 10,11,1
+- paste_last 10,11
+- cp_abort
++ copy 12,13
++ paste. 10,11
++ cpabort
+ hwsync
+ sync
+- sync 0,0x0
++ sync 0
+ lwsync
+- sync 1,0x0
++ sync 1
+ ptesync
+- sync 2,0x0
+- sync 0,0x7
+- sync 1,0x8
++ sync 2
+ ldat 20,0,0x0
+ ldat 20,10,0x1c
+ lwat 21,0,0x0
+@@ -364,8 +350,6 @@ power9:
+ rmieg 30
+ ldmx 10,0,15
+ ldmx 10,3,15
+- lwzmx 11,0,16
+- lwzmx 11,3,16
+ stop
+ wait
+ wait 0
+@@ -388,9 +372,6 @@ power9:
+ addex 11,12,13,0
+ addex 11,12,13,1
+ addex 11,12,13,2
+- addex. 21,22,23,0
+- addex. 21,22,23,1
+- addex. 21,22,23,2
+ mffs 25
+ mffs. 25
+ mffsce 26
+@@ -401,11 +382,3 @@ power9:
+ mffscrni 30,0
+ mffscrni 30,3
+ mffsl 31
+- brd 10,20
+- brh 11,21
+- brw 12,22
+- nandxor 10,11,12,13
+- xor3 20,21,22,23
+- rldixor 10,11,0,12
+- rldixor 10,11,27,12
+- rldixor 10,11,63,12
+diff -rup binutils-2.27.orig/include/opcode/ppc.h binutils-2.27/include/opcode/ppc.h
+--- binutils-2.27.orig/include/opcode/ppc.h 2016-09-28 08:49:28.845433887 +0100
++++ binutils-2.27/include/opcode/ppc.h 2016-09-28 08:53:48.132843610 +0100
+@@ -214,6 +214,9 @@ extern const int vle_num_opcodes;
+ /* Opcode is supported by Vector-Scalar (VSX) Unit from ISA 2.08. */
+ #define PPC_OPCODE_VSX3 0x40000000000ull
+
++/* Opcode is supported by e200z4. */
++#define PPC_OPCODE_E200Z4 0x80000000000ull
++
+ /* A macro to extract the major opcode from an instruction. */
+ #define PPC_OP(i) (((i) >> 26) & 0x3f)
+
+diff -rup binutils-2.27.orig/opcodes/ppc-dis.c binutils-2.27/opcodes/ppc-dis.c
+--- binutils-2.27.orig/opcodes/ppc-dis.c 2016-09-28 08:49:29.236436013 +0100
++++ binutils-2.27/opcodes/ppc-dis.c 2016-09-28 08:58:35.525406139 +0100
+@@ -105,6 +105,11 @@ struct ppc_mopt ppc_opts[] = {
+ 0 },
+ { "com", PPC_OPCODE_COMMON,
+ 0 },
++ { "e200z4", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE| PPC_OPCODE_SPE
++ | PPC_OPCODE_ISEL | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK
++ | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK | PPC_OPCODE_RFMCI
++ | PPC_OPCODE_E500 | PPC_OPCODE_E200Z4),
++ PPC_OPCODE_VLE },
+ { "e300", PPC_OPCODE_PPC | PPC_OPCODE_E300,
+ 0 },
+ { "e500", (PPC_OPCODE_PPC | PPC_OPCODE_BOOKE | PPC_OPCODE_SPE
+diff -rup binutils-2.27.orig/opcodes/ppc-opc.c binutils-2.27/opcodes/ppc-opc.c
+--- binutils-2.27.orig/opcodes/ppc-opc.c 2016-09-28 08:49:29.236436013 +0100
++++ binutils-2.27/opcodes/ppc-opc.c 2016-09-28 08:58:16.374302016 +0100
+@@ -2374,6 +2374,12 @@ extract_vleil (unsigned long insn,
+ #define OPVUP(x,vup) (OP (x) | ((((unsigned long)(vup)) & 0xff) << 8))
+ #define OPVUP_MASK OPVUP (0x3f, 0xff)
+
++/* The main opcode combined with an update code and the RT fields specified in
++ D form instruction. Used for VLE volatile context save/restore
++ instructions. */
++#define OPVUPRT(x,vup,rt) (OPVUP (x, vup) | ((((unsigned long)(rt)) & 0x1f) << 21))
++#define OPVUPRT_MASK OPVUPRT (0x3f, 0xff, 0x1f)
++
+ /* An A form instruction. */
+ #define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
+ #define A_MASK A (0x3f, 0x1f, 1)
+@@ -3055,6 +3061,7 @@ extract_vleil (unsigned long insn,
+ #define E6500 PPC_OPCODE_E6500
+ #define PPCVLE PPC_OPCODE_VLE
+ #define PPCHTM PPC_OPCODE_HTM
++#define E200Z4 PPC_OPCODE_E200Z4
+ /* The list of embedded processors that use the embedded operand ordering
+ for the 3 operand dcbt and dcbtst instructions. */
+ #define DCBT_EO (PPC_OPCODE_E500 | PPC_OPCODE_E500MC | PPC_OPCODE_476 \
+@@ -3161,7 +3168,6 @@ const struct powerpc_opcode powerpc_opco
+ {"machhwu.", XO (4, 12,0,1), XO_MASK, MULHW, 0, {RT, RA, RB}},
+ {"ps_muls1", A (4, 13,0), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
+ {"ps_muls1.", A (4, 13,1), AFRB_MASK, PPCPS, 0, {FRT, FRA, FRC}},
+-{"rldixor", VXASH(4,26), VXASH_MASK, POWER9, 0, {RA, RS, SH6, RB}},
+ {"ps_madds0", A (4, 14,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
+ {"ps_madds0.", A (4, 14,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
+ {"ps_madds1", A (4, 15,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
+@@ -3203,8 +3209,6 @@ const struct powerpc_opcode powerpc_opco
+ {"ps_msub.", A (4, 28,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
+ {"ps_madd", A (4, 29,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
+ {"ps_madd.", A (4, 29,1), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
+-{"xor3", VXA(4, 54), VXA_MASK, POWER9, 0, {RA, RS, RB, RC}},
+-{"nandxor", VXA(4, 55), VXA_MASK, POWER9, 0, {RA, RS, RB, RC}},
+ {"vpermr", VXA(4, 59), VXA_MASK, PPCVEC3, 0, {VD, VA, VB, VC}},
+ {"ps_nmsub", A (4, 30,0), A_MASK, PPCPS, 0, {FRT, FRA, FRC, FRB}},
+ {"vaddeuqm", VXA(4, 60), VXA_MASK, PPCVEC2, 0, {VD, VA, VB, VC}},
+@@ -4943,8 +4947,7 @@ const struct powerpc_opcode powerpc_opco
+
+ {"dcbfep", XRT(31,127,0), XRT_MASK, E500MC|PPCA2, 0, {RA0, RB}},
+
+-{"setb", VX(31,256), VXVB_MASK|(3<<16), POWER9, 0, {RT, BFA}},
+-{"setbool", VX(31,257), VXVB_MASK, POWER9, 0, {RT, BA}},
++{"setb", X(31,128), XRB_MASK|(3<<16), POWER9, 0, {RT, BFA}},
+
+ {"wrtee", X(31,131), XRARB_MASK, PPC403|BOOKE|PPCA2|PPC476, 0, {RS}},
+
+@@ -4994,8 +4997,6 @@ const struct powerpc_opcode powerpc_opco
+
+ {"prtyw", X(31,154), XRB_MASK, POWER6|PPCA2|PPC476, 0, {RA, RS}},
+
+-{"brw", X(31,155), XRB_MASK, POWER9, 0, {RA, RS}},
+-
+ {"stdepx", X(31,157), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
+
+ {"stwepx", X(31,159), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
+@@ -5008,7 +5009,6 @@ const struct powerpc_opcode powerpc_opco
+ {"sthfcmx", APU(31,167,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
+
+ {"addex", ZRC(31,170,0), Z2_MASK, POWER9, 0, {RT, RA, RB, CY}},
+-{"addex.", ZRC(31,170,1), Z2_MASK, POWER9, 0, {RT, RA, RB, CY}},
+
+ {"msgclrp", XRTRA(31,174,0,0), XRTRA_MASK, POWER8, 0, {RB}},
+ {"dcbtlse", X(31,174), X_MASK, PPCCHLK, E500MC, {CT, RA0, RB}},
+@@ -5033,8 +5033,6 @@ const struct powerpc_opcode powerpc_opco
+
+ {"prtyd", X(31,186), XRB_MASK, POWER6|PPCA2, 0, {RA, RS}},
+
+-{"brd", X(31,187), XRB_MASK, POWER9, 0, {RA, RS}},
+-
+ {"cmprb", X(31,192), XCMP_MASK, POWER9, 0, {BF, L, RA, RB}},
+
+ {"icblq.", XRC(31,198,1), X_MASK, E6500, 0, {CT, RA0, RB}},
+@@ -5073,8 +5071,6 @@ const struct powerpc_opcode powerpc_opco
+ {"sleq", XRC(31,217,0), X_MASK, M601, 0, {RA, RS, RB}},
+ {"sleq.", XRC(31,217,1), X_MASK, M601, 0, {RA, RS, RB}},
+
+-{"brh", X(31,219), XRB_MASK, POWER9, 0, {RA, RS}},
+-
+ {"stbepx", X(31,223), X_MASK, E500MC|PPCA2, 0, {RS, RA0, RB}},
+
+ {"cmpeqb", X(31,224), XCMPL_MASK, POWER9, 0, {BF, RA, RB}},
+@@ -5541,8 +5537,6 @@ const struct powerpc_opcode powerpc_opco
+
+ {"mtvsrdd", X(31,435), XX1_MASK, PPCVSX3, 0, {XT6, RA0, RB}},
+
+-{"lwzmx", X(31,437), X_MASK, POWER9, 0, {RT, RA0, RB}},
+-
+ {"ecowx", X(31,438), X_MASK, PPC, E500|TITAN, {RT, RA0, RB}},
+
+ {"sthux", X(31,439), X_MASK, COM, 0, {RS, RAS, RB}},
+@@ -5815,6 +5809,7 @@ const struct powerpc_opcode powerpc_opco
+
+ {"mcrxr", X(31,512), XBFRARB_MASK, COM, POWER7, {BF}},
+
++{"lbdcbx", X(31,514), X_MASK, E200Z4, 0, {RT, RA, RB}},
+ {"lbdx", X(31,515), X_MASK, E500MC, 0, {RT, RA, RB}},
+
+ {"bblels", X(31,518), X_MASK, PPCBRLK, 0, {0}},
+@@ -5865,6 +5860,7 @@ const struct powerpc_opcode powerpc_opco
+ {"maskir", XRC(31,541,0), X_MASK, M601, 0, {RA, RS, RB}},
+ {"maskir.", XRC(31,541,1), X_MASK, M601, 0, {RA, RS, RB}},
+
++{"lhdcbx", X(31,546), X_MASK, E200Z4, 0, {RT, RA, RB}},
+ {"lhdx", X(31,547), X_MASK, E500MC, 0, {RT, RA, RB}},
+
+ {"lvtrx", X(31,549), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
+@@ -5888,6 +5884,7 @@ const struct powerpc_opcode powerpc_opco
+
+ {"mcrxrx", X(31,576), XBFRARB_MASK, POWER9, 0, {BF}},
+
++{"lwdcbx", X(31,578), X_MASK, E200Z4, 0, {RT, RA, RB}},
+ {"lwdx", X(31,579), X_MASK, E500MC, 0, {RT, RA, RB}},
+
+ {"lvtlx", X(31,581), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
+@@ -5906,8 +5903,8 @@ const struct powerpc_opcode powerpc_opco
+ {"hwsync", XSYNC(31,598,0), 0xffffffff, POWER4, BOOKE|PPC476, {0}},
+ {"lwsync", XSYNC(31,598,1), 0xffffffff, PPC, E500, {0}},
+ {"ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, 0, {0}},
+-{"sync", X(31,598), XSYNCLE_MASK, POWER9|E6500, 0, {LS, ESYNC}},
+-{"sync", X(31,598), XSYNC_MASK, PPCCOM, BOOKE|PPC476|POWER9, {LS}},
++{"sync", X(31,598), XSYNCLE_MASK, E6500, 0, {LS, ESYNC}},
++{"sync", X(31,598), XSYNC_MASK, PPCCOM, BOOKE|PPC476, {LS}},
+ {"msync", X(31,598), 0xffffffff, BOOKE|PPCA2|PPC476, 0, {0}},
+ {"sync", X(31,598), 0xffffffff, BOOKE|PPC476, E6500, {0}},
+ {"lwsync", X(31,598), 0xffffffff, E500, 0, {0}},
+@@ -5938,6 +5935,7 @@ const struct powerpc_opcode powerpc_opco
+
+ {"lfdux", X(31,631), X_MASK, COM, PPCEFS, {FRT, RAS, RB}},
+
++{"stbdcbx", X(31,642), X_MASK, E200Z4, 0, {RS, RA, RB}},
+ {"stbdx", X(31,643), X_MASK, E500MC, 0, {RS, RA, RB}},
+
+ {"stvlx", X(31,647), X_MASK, CELL, 0, {VS, RA0, RB}},
+@@ -5975,6 +5973,7 @@ const struct powerpc_opcode powerpc_opco
+ {"sre", XRC(31,665,0), X_MASK, M601, 0, {RA, RS, RB}},
+ {"sre.", XRC(31,665,1), X_MASK, M601, 0, {RA, RS, RB}},
+
++{"sthdcbx", X(31,674), X_MASK, E200Z4, 0, {RS, RA, RB}},
+ {"sthdx", X(31,675), X_MASK, E500MC, 0, {RS, RA, RB}},
+
+ {"stvfrx", X(31,677), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
+@@ -5992,6 +5991,7 @@ const struct powerpc_opcode powerpc_opco
+ {"sriq", XRC(31,696,0), X_MASK, M601, 0, {RA, RS, SH}},
+ {"sriq.", XRC(31,696,1), X_MASK, M601, 0, {RA, RS, SH}},
+
++{"stwdcbx", X(31,706), X_MASK, E200Z4, 0, {RS, RA, RB}},
+ {"stwdx", X(31,707), X_MASK, E500MC, 0, {RS, RA, RB}},
+
+ {"stvflx", X(31,709), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
+@@ -6072,8 +6072,7 @@ const struct powerpc_opcode powerpc_opco
+
+ {"lvsm", X(31,773), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
+
+-{"copy_first", XOPL(31,774,1), XRT_MASK, POWER9, 0, {RA0, RB}},
+-{"copy", X(31,774), XLRT_MASK, POWER9, 0, {RA0, RB, L}},
++{"copy", XOPL(31,774,1), XRT_MASK, POWER9, 0, {RA0, RB}},
+
+ {"stvepxl", X(31,775), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
+ {"lvlxl", X(31,775), X_MASK, CELL, 0, {VD, RA0, RB}},
+@@ -6143,7 +6142,7 @@ const struct powerpc_opcode powerpc_opco
+
+ {"lvtlxl", X(31,837), X_MASK, PPCVEC2, 0, {VD, RA0, RB}},
+
+-{"cp_abort", X(31,838), XRTRARB_MASK,POWER9, 0, {0}},
++{"cpabort", X(31,838), XRTRARB_MASK,POWER9, 0, {0}},
+
+ {"divo", XO(31,331,1,0), XO_MASK, M601, 0, {RT, RA, RB}},
+ {"divo.", XO(31,331,1,1), XO_MASK, M601, 0, {RT, RA, RB}},
+@@ -6155,6 +6154,7 @@ const struct powerpc_opcode powerpc_opco
+
+ {"tlbsrx.", XRC(31,850,1), XRT_MASK, PPCA2, 0, {RA0, RB}},
+
++{"slbiag", X(31,850), XRARB_MASK, POWER9, 0, {RS}},
+ {"slbmfev", X(31,851), XRLA_MASK, POWER9, 0, {RT, RB, A_L}},
+ {"slbmfev", X(31,851), XRA_MASK, PPC64, POWER9, {RT, RB}},
+
+@@ -6190,9 +6190,7 @@ const struct powerpc_opcode powerpc_opco
+ {"extswsli", XS(31,445,0), XS_MASK, POWER9, 0, {RA, RS, SH6}},
+ {"extswsli.", XS(31,445,1), XS_MASK, POWER9, 0, {RA, RS, SH6}},
+
+-{"paste", XRC(31,902,0), XLRT_MASK, POWER9, 0, {RA0, RB, L0}},
+-{"paste_last", XRCL(31,902,1,1),XRT_MASK, POWER9, 0, {RA0, RB}},
+-{"paste.", XRC(31,902,1), XLRT_MASK, POWER9, 0, {RA0, RB, L1}},
++{"paste.", XRCL(31,902,1,1),XRT_MASK, POWER9, 0, {RA0, RB}},
+
+ {"stvlxl", X(31,903), X_MASK, CELL, 0, {VS, RA0, RB}},
+ {"stdfcmux", APU(31,903,0), APU_MASK, PPC405, 0, {FCRT, RA, RB}},
+@@ -7070,7 +7068,9 @@ const struct powerpc_opcode vle_opcodes[
+ {"se_cmphl", SE_RR(3,3), SE_RR_MASK, PPCVLE, 0, {RX, RY}},
+
+ {"e_cmpi", SCI8BF(6,0,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}},
++{"e_cmpwi", SCI8BF(6,0,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}},
+ {"e_cmpli", SCI8BF(6,1,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}},
++{"e_cmplwi", SCI8BF(6,1,21), SCI8BF_MASK, PPCVLE, 0, {CRD32, RA, SCLSCI8}},
+ {"e_addi", SCI8(6,16), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
+ {"e_subi", SCI8(6,16), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8N}},
+ {"e_addi.", SCI8(6,17), SCI8_MASK, PPCVLE, 0, {RT, RA, SCLSCI8}},
+@@ -7097,6 +7097,16 @@ const struct powerpc_opcode vle_opcodes[
+ {"e_sthu", OPVUP(6,5), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
+ {"e_stwu", OPVUP(6,6), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
+ {"e_stmw", OPVUP(6,9), OPVUP_MASK, PPCVLE, 0, {RT, D8, RA0}},
++{"e_ldmvgprw", OPVUPRT(6,16,0),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
++{"e_stmvgprw", OPVUPRT(6,17,0),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
++{"e_ldmvsprw", OPVUPRT(6,16,1),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
++{"e_stmvsprw", OPVUPRT(6,17,1),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
++{"e_ldmvsrrw", OPVUPRT(6,16,4),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
++{"e_stmvsrrw", OPVUPRT(6,17,4),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
++{"e_ldmvcsrrw", OPVUPRT(6,16,5),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
++{"e_stmvcsrrw", OPVUPRT(6,17,5),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
++{"e_ldmvdsrrw", OPVUPRT(6,16,6),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
++{"e_stmvdsrrw", OPVUPRT(6,17,6),OPVUPRT_MASK, PPCVLE, 0, {D8, RA0}},
+ {"e_add16i", OP(7), OP_MASK, PPCVLE, 0, {RT, RA, SI}},
+ {"e_la", OP(7), OP_MASK, PPCVLE, 0, {RT, D, RA0}},
+ {"e_sub16i", OP(7), OP_MASK, PPCVLE, 0, {RT, RA, NSI}},
+@@ -7144,10 +7154,8 @@ const struct powerpc_opcode vle_opcodes[
+ {"e_cmphl16i", IA16(28,23), IA16_MASK, PPCVLE, 0, {RA, VLEUIMM}},
+ {"e_cmph16i", IA16(28,22), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}},
+ {"e_cmpl16i", I16A(28,21), I16A_MASK, PPCVLE, 0, {RA, VLEUIMM}},
+-{"e_cmplwi", I16A(28,21), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
+ {"e_mull2i", I16A(28,20), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
+ {"e_cmp16i", IA16(28,19), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}},
+-{"e_cmpwi", IA16(28,19), IA16_MASK, PPCVLE, 0, {RA, VLESIMM}},
+ {"e_sub2is", I16A(28,18), I16A_MASK, PPCVLE, 0, {RA, VLENSIMM}},
+ {"e_add2is", I16A(28,18), I16A_MASK, PPCVLE, 0, {RA, VLESIMM}},
+ {"e_sub2i.", I16A(28,17), I16A_MASK, PPCVLE, 0, {RA, VLENSIMM}},
+
diff --git a/SOURCES/binutils-2.27-ppc-stubs.patch b/SOURCES/binutils-2.27-ppc-stubs.patch
new file mode 100644
index 0000000..76bd5ed
--- /dev/null
+++ b/SOURCES/binutils-2.27-ppc-stubs.patch
@@ -0,0 +1,14 @@
+--- binutils.orig/bfd/elf64-ppc.c 2017-03-08 13:43:51.185482217 +0000
++++ binutils-2.27/bfd/elf64-ppc.c 2017-03-08 13:44:28.403034088 +0000
+@@ -12514,7 +12514,10 @@ ppc64_elf_size_stubs (struct bfd_link_in
+ stub_sec = stub_sec->next)
+ if ((stub_sec->flags & SEC_LINKER_CREATED) == 0)
+ {
+- stub_sec->rawsize = stub_sec->size;
++ if (htab->stub_iteration <= STUB_SHRINK_ITER
++ || stub_sec->rawsize < stub_sec->size)
++ /* Past STUB_SHRINK_ITER, rawsize is the max size seen. */
++ stub_sec->rawsize = stub_sec->size;
+ stub_sec->size = 0;
+ stub_sec->reloc_count = 0;
+ stub_sec->flags &= ~SEC_RELOC;
diff --git a/SOURCES/binutils-2.27-ppc64-discarded-plt-sections.patch b/SOURCES/binutils-2.27-ppc64-discarded-plt-sections.patch
new file mode 100644
index 0000000..dc40f0e
--- /dev/null
+++ b/SOURCES/binutils-2.27-ppc64-discarded-plt-sections.patch
@@ -0,0 +1,79 @@
+diff -rup binutils.orig/bfd/elf64-ppc.c binutils-2.27/bfd/elf64-ppc.c
+--- binutils.orig/bfd/elf64-ppc.c 2017-11-16 10:35:34.873666405 +0000
++++ binutils-2.27/bfd/elf64-ppc.c 2017-11-16 10:39:54.037530964 +0000
+@@ -10105,6 +10105,10 @@ ppc64_elf_size_dynamic_sections (bfd *ou
+ continue;
+ }
+
++ if (bfd_is_abs_section (s->output_section))
++ _bfd_error_handler (_("warning: discarding dynamic section %s"),
++ s->name);
++
+ if ((s->flags & SEC_HAS_CONTENTS) == 0)
+ continue;
+
+@@ -10875,7 +10879,7 @@ ppc_build_one_stub (struct bfd_hash_entr
+ + htab->brlt->output_section->vma);
+
+ off = (dest
+- - elf_gp (htab->brlt->output_section->owner)
++ - elf_gp (info->output_bfd)
+ - htab->sec_info[stub_entry->group->link_sec->id].toc_off);
+
+ if (off + 0x80008000 > 0xffffffff || (off & 7) != 0)
+@@ -11025,7 +11029,7 @@ ppc_build_one_stub (struct bfd_hash_entr
+ }
+
+ off = (dest
+- - elf_gp (plt->output_section->owner)
++ - elf_gp (info->output_bfd)
+ - htab->sec_info[stub_entry->group->link_sec->id].toc_off);
+
+ if (off + 0x80008000 > 0xffffffff || (off & 7) != 0)
+@@ -11172,7 +11176,7 @@ ppc_size_one_stub (struct bfd_hash_entry
+ plt = htab->elf.iplt;
+ off += (plt->output_offset
+ + plt->output_section->vma
+- - elf_gp (plt->output_section->owner)
++ - elf_gp (info->output_bfd)
+ - htab->sec_info[stub_entry->group->link_sec->id].toc_off);
+
+ size = plt_stub_size (htab, stub_entry, off);
+@@ -11266,7 +11270,7 @@ ppc_size_one_stub (struct bfd_hash_entry
+ off = (br_entry->offset
+ + htab->brlt->output_offset
+ + htab->brlt->output_section->vma
+- - elf_gp (htab->brlt->output_section->owner)
++ - elf_gp (info->output_bfd)
+ - htab->sec_info[stub_entry->group->link_sec->id].toc_off);
+
+ if (info->emitrelocations)
+@@ -11386,7 +11390,7 @@ ppc64_elf_next_toc_section (struct bfd_l
+ output toc base plus 0x8000. Making the input elf_gp an
+ offset allows us to move the toc as a whole without
+ recalculating input elf_gp. */
+- off = htab->toc_curr - elf_gp (isec->output_section->owner);
++ off = htab->toc_curr - elf_gp (info->output_bfd);
+ off += TOC_BASE_OFF;
+
+ /* Die if someone uses a linker script that doesn't keep input
+@@ -11415,7 +11419,7 @@ ppc64_elf_next_toc_section (struct bfd_l
+ }
+ addr = (htab->toc_first_sec->output_offset
+ + htab->toc_first_sec->output_section->vma);
+- off = addr - elf_gp (isec->output_section->owner) + TOC_BASE_OFF;
++ off = addr - elf_gp (info->output_bfd) + TOC_BASE_OFF;
+ elf_gp (isec->owner) = off;
+
+ return TRUE;
+diff -rup binutils.orig/ld/testsuite/ld-elf/note-3.t binutils-2.27/ld/testsuite/ld-elf/note-3.t
+--- binutils.orig/ld/testsuite/ld-elf/note-3.t 2017-11-16 10:35:35.670656893 +0000
++++ binutils-2.27/ld/testsuite/ld-elf/note-3.t 2017-11-16 10:59:06.352286215 +0000
+@@ -17,6 +17,7 @@ SECTIONS
+
+ .dynstr : { *(.dynstr) }
+ .dynsym : { *(.dynsym) }
++ .got : { *(.got .toc) *(.igot) }
+ .got.plt : { *(.got.plt) *(.igot.plt) }
+ /DISCARD/ : { *(*) }
+ }
diff --git a/SOURCES/binutils-2.27-remove-dwarf2-minmax.patch b/SOURCES/binutils-2.27-remove-dwarf2-minmax.patch
new file mode 100644
index 0000000..c65dbe2
--- /dev/null
+++ b/SOURCES/binutils-2.27-remove-dwarf2-minmax.patch
@@ -0,0 +1,41 @@
+--- binutils.orig/bfd/dwarf2.c 2017-08-08 17:40:39.084385407 +0100
++++ binutils-2.27/bfd/dwarf2.c 2017-08-08 17:41:34.237754733 +0100
+@@ -215,9 +215,6 @@ struct comp_unit
+ /* Linked list of the low and high address ranges contained in this
+ compilation unit as specified in the compilation unit header. */
+ struct arange arange;
+- /* A single arange containing the lowest and highest
+- addresses covered by the compilation unit. */
+- struct arange minmax;
+
+ /* The DW_AT_name attribute (for error messages). */
+ char *name;
+@@ -1540,16 +1537,11 @@ arange_add (struct comp_unit *unit, stru
+ /* If the first arange is empty, use it. */
+ if (first_arange->high == 0)
+ {
+- unit->minmax.low = first_arange->low = low_pc;
+- unit->minmax.high = first_arange->high = high_pc;
++ first_arange->low = low_pc;
++ first_arange->high = high_pc;
+ return TRUE;
+ }
+
+- if (unit->minmax.low > low_pc)
+- unit->minmax.low = low_pc;
+- if (unit->minmax.high < high_pc)
+- unit->minmax.high = high_pc;
+-
+ /* Next see if we can cheaply extend an existing range. */
+ arange = first_arange;
+ do
+@@ -3151,9 +3143,6 @@ comp_unit_contains_address (struct comp_
+ if (unit->error)
+ return FALSE;
+
+- if (unit->minmax.high < addr || unit->minmax.low > addr)
+- return FALSE;
+-
+ /* We know that the address *might* be contained within this comp
+ unit, but we cannot be sure until we check the specific ranges. */
+ arange = &unit->arange;
diff --git a/SOURCES/binutils-2.27-remove-pr19784-test.patch b/SOURCES/binutils-2.27-remove-pr19784-test.patch
new file mode 100644
index 0000000..06afe28
--- /dev/null
+++ b/SOURCES/binutils-2.27-remove-pr19784-test.patch
@@ -0,0 +1,24 @@
+diff -rup binutils.orig/ld/testsuite/ld-ifunc/ifunc.exp binutils-2.27/ld/testsuite/ld-ifunc/ifunc.exp
+--- binutils.orig/ld/testsuite/ld-ifunc/ifunc.exp 2017-02-21 16:23:38.051305028 +0000
++++ binutils-2.27/ld/testsuite/ld-ifunc/ifunc.exp 2017-02-21 16:59:09.769220809 +0000
+@@ -563,20 +563,4 @@ run_ld_link_exec_tests [] [list \
+ "pr18841c" \
+ "pr18841.out" \
+ ] \
+- [list \
+- "Run pr19784a" \
+- "tmpdir/pr19784a.o tmpdir/libpr19784a.so" \
+- "" \
+- { dummy.c } \
+- "pr19784a" \
+- "pass.out" \
+- ] \
+- [list \
+- "Run pr19784b" \
+- "--as-needed tmpdir/pr19784a.o tmpdir/libpr19784b.so" \
+- "" \
+- { dummy.c } \
+- "pr19784b" \
+- "pass.out" \
+- ] \
+ ]
diff --git a/SOURCES/binutils-2.27-revert-PLT-elision.patch b/SOURCES/binutils-2.27-revert-PLT-elision.patch
new file mode 100644
index 0000000..3eb828f
--- /dev/null
+++ b/SOURCES/binutils-2.27-revert-PLT-elision.patch
@@ -0,0 +1,76 @@
+diff -rup binutils.orig/bfd/elf32-i386.c binutils-2.27/bfd/elf32-i386.c
+--- binutils.orig/bfd/elf32-i386.c 2017-05-17 11:22:32.393303573 +0100
++++ binutils-2.27/bfd/elf32-i386.c 2017-05-17 11:25:33.097138811 +0100
+@@ -2322,8 +2322,7 @@ do_size:
+ if (use_plt_got
+ && h != NULL
+ && h->plt.refcount > 0
+- && (((info->flags & DF_BIND_NOW) && !h->pointer_equality_needed)
+- || h->got.refcount > 0)
++ && h->got.refcount > 0
+ && htab->plt_got == NULL)
+ {
+ /* Create the GOT procedure linkage table. */
+@@ -2672,16 +2671,6 @@ elf_i386_allocate_dynrelocs (struct elf_
+ if PLT is used. */
+ eh->func_pointer_refcount = 0;
+
+- if ((info->flags & DF_BIND_NOW) && !h->pointer_equality_needed)
+- {
+- /* Don't use the regular PLT for DF_BIND_NOW. */
+- h->plt.offset = (bfd_vma) -1;
+-
+- /* Use the GOT PLT. */
+- h->got.refcount = 1;
+- eh->plt_got.refcount = 1;
+- }
+-
+ use_plt_got = eh->plt_got.refcount > 0;
+
+ /* Make sure this symbol is output as a dynamic symbol.
+diff -rup binutils.orig/bfd/elf64-x86-64.c binutils-2.27/bfd/elf64-x86-64.c
+--- binutils.orig/bfd/elf64-x86-64.c 2017-05-17 11:22:32.396303537 +0100
++++ binutils-2.27/bfd/elf64-x86-64.c 2017-05-17 11:26:00.250813521 +0100
+@@ -2722,8 +2722,7 @@ do_size:
+ if (use_plt_got
+ && h != NULL
+ && h->plt.refcount > 0
+- && (((info->flags & DF_BIND_NOW) && !h->pointer_equality_needed)
+- || h->got.refcount > 0)
++ && h->got.refcount > 0
+ && htab->plt_got == NULL)
+ {
+ /* Create the GOT procedure linkage table. */
+@@ -3094,16 +3093,6 @@ elf_x86_64_allocate_dynrelocs (struct el
+ if PLT is used. */
+ eh->func_pointer_refcount = 0;
+
+- if ((info->flags & DF_BIND_NOW) && !h->pointer_equality_needed)
+- {
+- /* Don't use the regular PLT for DF_BIND_NOW. */
+- h->plt.offset = (bfd_vma) -1;
+-
+- /* Use the GOT PLT. */
+- h->got.refcount = 1;
+- eh->plt_got.refcount = 1;
+- }
+-
+ use_plt_got = eh->plt_got.refcount > 0;
+
+ /* Make sure this symbol is output as a dynamic symbol.
+diff -rup binutils.orig/ld/testsuite/ld-i386/pr17689now.rd binutils-2.27/ld/testsuite/ld-i386/pr17689now.rd
+--- binutils.orig/ld/testsuite/ld-i386/pr17689now.rd 2017-05-17 11:22:32.677300171 +0100
++++ binutils-2.27/ld/testsuite/ld-i386/pr17689now.rd 2017-05-17 11:39:36.097021963 +0100
+@@ -1,4 +1,3 @@
+-#failif
+ #...
+ [0-9a-f ]+R_386_JUMP_SLOT +0+.*
+ #...
+diff -rup binutils.orig/ld/testsuite/ld-x86-64/pr17689now.rd binutils-2.27/ld/testsuite/ld-x86-64/pr17689now.rd
+--- binutils.orig/ld/testsuite/ld-x86-64/pr17689now.rd 2017-05-17 11:22:32.734299489 +0100
++++ binutils-2.27/ld/testsuite/ld-x86-64/pr17689now.rd 2017-05-17 11:39:53.071818174 +0100
+@@ -1,4 +1,3 @@
+-#failif
+ #...
+ [0-9a-f ]+R_X86_64_JUMP_SLOT +0+ +.*
+ #...
diff --git a/SOURCES/binutils-2.27-s390-pgste-marker.patch b/SOURCES/binutils-2.27-s390-pgste-marker.patch
new file mode 100644
index 0000000..e864c39
--- /dev/null
+++ b/SOURCES/binutils-2.27-s390-pgste-marker.patch
@@ -0,0 +1,354 @@
+diff -rup binutils.orig/bfd/elf64-s390.c binutils-2.27/bfd/elf64-s390.c
+--- binutils.orig/bfd/elf64-s390.c 2017-08-29 13:09:44.135143399 +0100
++++ binutils-2.27/bfd/elf64-s390.c 2017-08-29 13:10:37.272554164 +0100
+@@ -25,6 +25,7 @@
+ #include "libbfd.h"
+ #include "elf-bfd.h"
+ #include "elf/s390.h"
++#include "elf-s390.h"
+
+ /* In case we're on a 32-bit machine, construct a 64-bit "-1" value
+ from smaller values. Start with zero, widen, *then* decrement. */
+@@ -660,6 +661,9 @@ struct elf_s390_link_hash_table
+
+ /* Small local sym cache. */
+ struct sym_cache sym_cache;
++
++ /* Options passed from the linker. */
++ struct s390_elf_params *params;
+ };
+
+ /* Get the s390 ELF linker hash table from a link_info structure. */
+@@ -3883,6 +3887,70 @@ elf64_s390_merge_private_bfd_data (bfd *
+ return TRUE;
+ }
+
++/* We may add a PT_S390_PGSTE program header. */
++
++static int
++elf_s390_additional_program_headers (bfd *abfd ATTRIBUTE_UNUSED,
++ struct bfd_link_info *info)
++{
++ struct elf_s390_link_hash_table *htab;
++
++ htab = elf_s390_hash_table (info);
++ return htab->params->pgste;
++}
++
++
++/* Add the PT_S390_PGSTE program header. */
++
++static bfd_boolean
++elf_s390_modify_segment_map (bfd *abfd ATTRIBUTE_UNUSED,
++ struct bfd_link_info *info)
++{
++ struct elf_s390_link_hash_table *htab;
++ struct elf_segment_map *m, *pm = NULL;
++
++ htab = elf_s390_hash_table (info);
++ if (!htab->params->pgste)
++ return TRUE;
++
++ /* If there is already a PT_S390_PGSTE header, avoid adding
++ another. */
++ m = elf_seg_map (abfd);
++ while (m && m->p_type != PT_S390_PGSTE)
++ {
++ pm = m;
++ m = m->next;
++ }
++
++ if (m)
++ return TRUE;
++
++ m = (struct elf_segment_map *)
++ bfd_zalloc (abfd, sizeof (struct elf_segment_map));
++ if (m == NULL)
++ return FALSE;
++ m->p_type = PT_S390_PGSTE;
++ m->count = 0;
++ m->next = NULL;
++ if (pm)
++ pm->next = m;
++
++ return TRUE;
++}
++
++bfd_boolean
++bfd_elf_s390_set_options (struct bfd_link_info *info,
++ struct s390_elf_params *params)
++{
++ struct elf_s390_link_hash_table *htab;
++
++ htab = elf_s390_hash_table (info);
++ htab->params = params;
++
++ return TRUE;
++}
++
++
+ /* Why was the hash table entry size definition changed from
+ ARCH_SIZE/8 to 4? This breaks the 64 bit dynamic linker and
+ this is the only reason for the s390_elf64_size_info structure. */
+@@ -3959,6 +4027,8 @@ const struct elf_size_info s390_elf64_si
+ #define elf_backend_plt_sym_val elf_s390_plt_sym_val
+ #define elf_backend_add_symbol_hook elf_s390_add_symbol_hook
+ #define elf_backend_sort_relocs_p elf_s390_elf_sort_relocs_p
++#define elf_backend_additional_program_headers elf_s390_additional_program_headers
++#define elf_backend_modify_segment_map elf_s390_modify_segment_map
+
+ #define bfd_elf64_mkobject elf_s390_mkobject
+ #define elf_backend_object_p elf_s390_object_p
+diff -rup binutils.orig/binutils/readelf.c binutils-2.27/binutils/readelf.c
+--- binutils.orig/binutils/readelf.c 2017-08-29 13:09:44.138143366 +0100
++++ binutils-2.27/binutils/readelf.c 2017-08-29 13:09:53.384040839 +0100
+@@ -3610,6 +3610,16 @@ get_arm_segment_type (unsigned long type
+ }
+
+ static const char *
++get_s390_segment_type (unsigned long type)
++{
++ switch (type)
++ {
++ case PT_S390_PGSTE: return "S390_PGSTE";
++ default: return NULL;
++ }
++}
++
++static const char *
+ get_mips_segment_type (unsigned long type)
+ {
+ switch (type)
+@@ -3755,6 +3765,10 @@ get_segment_type (unsigned long p_type)
+ case EM_TI_C6000:
+ result = get_tic6x_segment_type (p_type);
+ break;
++ case EM_S390:
++ case EM_S390_OLD:
++ result = get_s390_segment_type (p_type);
++ break;
+ default:
+ result = NULL;
+ break;
+diff -rup binutils.orig/elfcpp/elfcpp.h binutils-2.27/elfcpp/elfcpp.h
+--- binutils.orig/elfcpp/elfcpp.h 2017-08-29 13:09:44.182142878 +0100
++++ binutils-2.27/elfcpp/elfcpp.h 2017-08-29 13:09:53.385040828 +0100
+@@ -514,7 +514,9 @@ enum PT
+ // Platform architecture compatibility information
+ PT_AARCH64_ARCHEXT = 0x70000000,
+ // Exception unwind tables
+- PT_AARCH64_UNWIND = 0x70000001
++ PT_AARCH64_UNWIND = 0x70000001,
++ // 4k page table size
++ PT_S390_PGSTE = 0x70000000,
+ };
+
+ // The valid bit flags found in the Phdr p_flags field.
+diff -rup binutils.orig/include/elf/s390.h binutils-2.27/include/elf/s390.h
+--- binutils.orig/include/elf/s390.h 2017-08-29 13:09:44.434140083 +0100
++++ binutils-2.27/include/elf/s390.h 2017-08-29 13:09:53.385040828 +0100
+@@ -37,6 +37,9 @@
+
+ #define EF_S390_HIGH_GPRS 0x00000001
+
++/* Request 4k page table size. */
++#define PT_S390_PGSTE (PT_LOPROC + 0)
++
+ /* Relocation types. */
+
+ START_RELOC_NUMBERS (elf_s390_reloc_type)
+diff -rup binutils.orig/ld/emulparams/elf64_s390.sh binutils-2.27/ld/emulparams/elf64_s390.sh
+--- binutils.orig/ld/emulparams/elf64_s390.sh 2017-08-29 13:09:44.441140006 +0100
++++ binutils-2.27/ld/emulparams/elf64_s390.sh 2017-08-29 13:09:53.385040828 +0100
+@@ -12,6 +12,7 @@ TEMPLATE_NAME=elf32
+ GENERATE_SHLIB_SCRIPT=yes
+ GENERATE_PIE_SCRIPT=yes
+ NO_SMALL_DATA=yes
++EXTRA_EM_FILE=s390
+ IREL_IN_PLT=
+
+ # Treat a host that matches the target with the possible exception of "x"
+diff -rup binutils.orig/ld/gen-doc.texi binutils-2.27/ld/gen-doc.texi
+--- binutils.orig/ld/gen-doc.texi 2017-08-29 13:09:44.445139961 +0100
++++ binutils-2.27/ld/gen-doc.texi 2017-08-29 13:09:53.385040828 +0100
+@@ -21,6 +21,7 @@
+ @set POWERPC
+ @set POWERPC64
+ @set Renesas
++@set S/390
+ @set SPU
+ @set TICOFF
+ @set WIN32
+diff -rup binutils.orig/ld/ld.texinfo binutils-2.27/ld/ld.texinfo
+--- binutils.orig/ld/ld.texinfo 2017-08-29 13:09:44.445139961 +0100
++++ binutils-2.27/ld/ld.texinfo 2017-08-29 13:09:53.385040828 +0100
+@@ -34,6 +34,7 @@
+ @set POWERPC
+ @set POWERPC64
+ @set Renesas
++@set S/390
+ @set SPU
+ @set TICOFF
+ @set WIN32
+@@ -158,6 +159,9 @@ in the section entitled ``GNU Free Docum
+ @ifset POWERPC64
+ * PowerPC64 ELF64:: ld and PowerPC64 64-bit ELF Support
+ @end ifset
++@ifset S/390
++* S/390 ELF:: ld and S/390 ELF Support
++@end ifset
+ @ifset SPU
+ * SPU ELF:: ld and SPU ELF Support
+ @end ifset
+@@ -6380,6 +6384,9 @@ functionality are not listed.
+ @ifset POWERPC64
+ * PowerPC64 ELF64:: @command{ld} and PowerPC64 64-bit ELF Support
+ @end ifset
++@ifset S/390
++* S/390 ELF:: @command{ld} and S/390 ELF Support
++@end ifset
+ @ifset SPU
+ * SPU ELF:: @command{ld} and SPU ELF Support
+ @end ifset
+@@ -7373,6 +7380,30 @@ default behaviour.
+ @end table
+
+ @ifclear GENERIC
++@lowersections
++@end ifclear
++@end ifset
++
++@ifset S/390
++@ifclear GENERIC
++@raisesections
++@end ifclear
++
++@node S/390 ELF
++@section @command{ld} and S/390 ELF Support
++
++@cindex S/390 ELF options
++@table @option
++
++@cindex S/390
++@kindex --s390-pgste
++@item --s390-pgste
++This option marks the result file with a @code{PT_S390_PGSTE}
++segment. The Linux kernel is supposed to allocate 4k page tables for
++binaries marked that way.
++@end table
++
++@ifclear GENERIC
+ @lowersections
+ @end ifclear
+ @end ifset
+diff -rup binutils.orig/ld/Makefile.in binutils-2.27/ld/Makefile.in
+--- binutils.orig/ld/Makefile.in 2017-08-29 13:09:44.446139950 +0100
++++ binutils-2.27/ld/Makefile.in 2017-08-29 13:09:53.385040828 +0100
+@@ -3490,6 +3490,7 @@ eelf64_ia64_vms.c: $(srcdir)/emulparams/
+ $(srcdir)/scripttempl/ia64vms.sc ${GEN_DEPENDS}
+
+ eelf64_s390.c: $(srcdir)/emulparams/elf64_s390.sh \
++ $(srcdir)/emultempl/s390.em \
+ $(ELF_DEPS) $(srcdir)/scripttempl/elf.sc ${GEN_DEPENDS}
+
+ eelf64_sparc.c: $(srcdir)/emulparams/elf64_sparc.sh \
+
+--- /dev/null 2017-08-29 08:03:33.387685165 +0100
++++ binutils-2.27/bfd/elf-s390.h 2017-08-29 13:19:31.705627899 +0100
+@@ -0,0 +1,29 @@
++/* S/390-specific support for ELF.
++ Copyright (C) 2017 Free Software Foundation, Inc.
++
++ This file is part of BFD, the Binary File Descriptor library.
++
++ This program is free software; you can redistribute it and/or modify
++ it under the terms of the GNU General Public License as published by
++ the Free Software Foundation; either version 3 of the License, or
++ (at your option) any later version.
++
++ This program is distributed in the hope that it will be useful,
++ but WITHOUT ANY WARRANTY; without even the implied warranty of
++ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ GNU General Public License for more details.
++
++ You should have received a copy of the GNU General Public License
++ along with this program; if not, write to the Free Software
++ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
++ MA 02110-1301, USA. */
++
++/* Used to pass info between ld and bfd. */
++struct s390_elf_params
++{
++ /* Tell the kernel to allocate 4k page tables. */
++ int pgste;
++};
++
++bfd_boolean bfd_elf_s390_set_options (struct bfd_link_info *info,
++ struct s390_elf_params *params);
+--- /dev/null 2017-08-29 08:03:33.387685165 +0100
++++ binutils-2.27/ld/emultempl/s390.em 2017-08-29 13:26:01.797302217 +0100
+@@ -0,0 +1,64 @@
++# This shell script emits a C file. -*- C -*-
++# Copyright (C) 2017 Free Software Foundation, Inc.
++#
++# This file is part of the GNU Binutils.
++#
++# This program is free software; you can redistribute it and/or modify
++# it under the terms of the GNU General Public License as published by
++# the Free Software Foundation; either version 3 of the license, or
++# (at your option) any later version.
++#
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with this program; see the file COPYING3. If not,
++# see <http://www.gnu.org/licenses/>.
++#
++
++# This file is sourced from elf-generic.em, and defines S/390
++# specific routines.
++#
++fragment <<EOF
++
++#include "ldctor.h"
++#include "elf-s390.h"
++
++static struct s390_elf_params params = { 0 };
++
++/* This is a convenient point to tell BFD about target specific flags.
++ After the output has been created, but before inputs are read. */
++static void
++s390_elf_create_output_section_statements (void)
++{
++ if (!bfd_elf_s390_set_options (&link_info, ¶ms))
++ einfo ("%F%P: can not init BFD: %E\n");
++}
++
++EOF
++
++# Define some shell vars to insert bits of code into the standard elf
++# parse_args and list_options functions.
++#
++PARSE_AND_LIST_PROLOGUE='
++#define OPTION_PGSTE 301
++'
++
++PARSE_AND_LIST_LONGOPTS='
++ { "s390-pgste", no_argument, NULL, OPTION_PGSTE},
++'
++
++PARSE_AND_LIST_OPTIONS='
++ fprintf (file, _(" --s390-pgste Tell the kernel to "
++ "allocate 4k page tables\n"));
++'
++
++PARSE_AND_LIST_ARGS_CASES='
++ case OPTION_PGSTE:
++ params.pgste = 1;
++ break;
++'
++
++LDEMUL_CREATE_OUTPUT_SECTION_STATEMENTS=s390_elf_create_output_section_statements
diff --git a/SOURCES/binutils-2.27-s390-plt.patch b/SOURCES/binutils-2.27-s390-plt.patch
new file mode 100644
index 0000000..5e9a866
--- /dev/null
+++ b/SOURCES/binutils-2.27-s390-plt.patch
@@ -0,0 +1,44 @@
+diff -rup binutils.orig/bfd/elf32-s390.c binutils-2.27/bfd/elf32-s390.c
+--- binutils.orig/bfd/elf32-s390.c 2017-05-12 13:00:01.697650210 +0100
++++ binutils-2.27/bfd/elf32-s390.c 2017-05-12 13:01:05.223988744 +0100
+@@ -2809,7 +2809,7 @@ elf_s390_relocate_section (bfd *output_b
+ && s390_is_ifunc_symbol_p (h)
+ && h->def_regular)
+ {
+- if (!bfd_link_pic (info) || !h->non_got_ref)
++ if (!bfd_link_pic (info))
+ {
+ /* For a non-shared object STT_GNU_IFUNC symbol must
+ go through PLT. */
+diff -rup binutils.orig/bfd/elf64-s390.c binutils-2.27/bfd/elf64-s390.c
+--- binutils.orig/bfd/elf64-s390.c 2017-05-12 13:00:01.699650190 +0100
++++ binutils-2.27/bfd/elf64-s390.c 2017-05-12 13:01:31.017720167 +0100
+@@ -2768,10 +2768,11 @@ elf_s390_relocate_section (bfd *output_b
+ && s390_is_ifunc_symbol_p (h)
+ && h->def_regular)
+ {
+- if (!bfd_link_pic (info) || !h->non_got_ref)
++ if (!bfd_link_pic (info))
+ {
+- /* For a non-shared object STT_GNU_IFUNC symbol must
+- go through PLT. */
++ /* For a non-shared object the symbol will not
++ change. Hence we can write the address of the
++ target IPLT slot now. */
+ relocation = (htab->elf.iplt->output_section->vma
+ + htab->elf.iplt->output_offset
+ + h ->plt.offset);
+diff -rup binutils.orig/bfd/elf-s390-common.c binutils-2.27/bfd/elf-s390-common.c
+--- binutils.orig/bfd/elf-s390-common.c 2017-05-12 13:00:01.695650231 +0100
++++ binutils-2.27/bfd/elf-s390-common.c 2017-05-12 13:01:54.347477247 +0100
+@@ -161,9 +161,7 @@ keep:
+ h->type = STT_FUNC;
+ }
+
+- /* We need dynamic relocation for STT_GNU_IFUNC symbol only when
+- there is a non-GOT reference in a shared object. */
+- if (!bfd_link_pic (info) || !h->non_got_ref)
++ if (!bfd_link_pic (info))
+ *head = NULL;
+
+ /* Finally, allocate space. */
diff --git a/SOURCES/binutils-2.27-s390-pr19719.patch b/SOURCES/binutils-2.27-s390-pr19719.patch
new file mode 100644
index 0000000..4feacac
--- /dev/null
+++ b/SOURCES/binutils-2.27-s390-pr19719.patch
@@ -0,0 +1,10 @@
+diff -rup binutils.orig/ld/testsuite/ld-elf/shared.exp binutils-2.27/ld/testsuite/ld-elf/shared.exp
+--- binutils.orig/ld/testsuite/ld-elf/shared.exp 2017-02-21 15:00:21.788036974 +0000
++++ binutils-2.27/ld/testsuite/ld-elf/shared.exp 2017-02-21 16:18:12.497641235 +0000
+@@ -665,5 +665,5 @@ proc mix_pic_and_non_pic {xfails cflags
+ }
+ }
+
+-mix_pic_and_non_pic [list "arm*-*-*" "aarch64*-*-*"] "" "" "pr19719"
++mix_pic_and_non_pic [list "arm*-*-*" "aarch64*-*-*" "s390*-*-*"] "" "" "pr19719"
+ mix_pic_and_non_pic [] "-fPIE" "-pie" "pr19719pie"
diff --git a/SOURCES/binutils-2.27-s390x-arch12.patch b/SOURCES/binutils-2.27-s390x-arch12.patch
new file mode 100644
index 0000000..2293c10
--- /dev/null
+++ b/SOURCES/binutils-2.27-s390x-arch12.patch
@@ -0,0 +1,1064 @@
+diff -rup binutils.orig/gas/config/tc-s390.c binutils-2.27/gas/config/tc-s390.c
+--- binutils.orig/gas/config/tc-s390.c 2017-03-24 14:50:52.004815587 +0000
++++ binutils-2.27/gas/config/tc-s390.c 2017-03-24 14:55:19.129377655 +0000
+@@ -282,7 +282,8 @@ s390_parse_cpu (const char * arg
+ { STRING_COMMA_LEN ("z10"), 0 },
+ { STRING_COMMA_LEN ("z196"), 0 },
+ { STRING_COMMA_LEN ("zEC12"), S390_INSTR_FLAG_HTM },
+- { STRING_COMMA_LEN ("z13"), S390_INSTR_FLAG_HTM | S390_INSTR_FLAG_VX }
++ { STRING_COMMA_LEN ("z13"), S390_INSTR_FLAG_HTM | S390_INSTR_FLAG_VX },
++ { STRING_COMMA_LEN ("arch12"), S390_INSTR_FLAG_HTM | S390_INSTR_FLAG_VX | S390_INSTR_FLAG_VX2 }
+ };
+ static struct
+ {
+@@ -294,7 +295,9 @@ s390_parse_cpu (const char * arg
+ { "htm", S390_INSTR_FLAG_HTM, TRUE },
+ { "nohtm", S390_INSTR_FLAG_HTM, FALSE },
+ { "vx", S390_INSTR_FLAG_VX, TRUE },
+- { "novx", S390_INSTR_FLAG_VX, FALSE }
++ { "novx", S390_INSTR_FLAG_VX, FALSE },
++ { "vx2", S390_INSTR_FLAG_VX2, TRUE },
++ { "novx2", S390_INSTR_FLAG_VX2, FALSE }
+ };
+ unsigned int icpu;
+ char *ilp_bak;
+diff -rup binutils.orig/gas/doc/as.texinfo binutils-2.27/gas/doc/as.texinfo
+--- binutils.orig/gas/doc/as.texinfo 2017-03-24 14:50:52.037815161 +0000
++++ binutils-2.27/gas/doc/as.texinfo 2017-03-24 14:56:29.325474523 +0000
+@@ -1656,7 +1656,7 @@ Architecture (esa) or the z/Architecture
+ @item -march=@var{processor}
+ Specify which s390 processor variant is the target, @samp{g6}, @samp{g6},
+ @samp{z900}, @samp{z990}, @samp{z9-109}, @samp{z9-ec}, @samp{z10},
+-@samp{z196}, @samp{zEC12}, or @samp{z13}.
++@samp{z196}, @samp{zEC12}, or @samp{z13} (or @samp{arch11}), or @samp{arch12}.
+ @item -mregnames
+ @itemx -mno-regnames
+ Allow or disallow symbolic names for registers.
+diff -rup binutils.orig/gas/doc/c-s390.texi binutils-2.27/gas/doc/c-s390.texi
+--- binutils.orig/gas/doc/c-s390.texi 2017-03-24 14:50:52.053814956 +0000
++++ binutils-2.27/gas/doc/c-s390.texi 2017-03-24 14:57:53.010397844 +0000
+@@ -14,9 +14,11 @@
+ @cindex s390 support
+
+ The s390 version of @code{@value{AS}} supports two architectures modes
+-and seven chip levels. The architecture modes are the Enterprise System
++and eleven chip levels. The architecture modes are the Enterprise System
+ Architecture (ESA) and the newer z/Architecture mode. The chip levels
+-are g5, g6, z900, z990, z9-109, z9-ec, z10, z196, zEC12, and z13.
++are g5 (or arch3), g6, z900 (or arch5), z990 (or arch6), z9-109, z9-ec
++(or arch7), z10 (or arch8), z196 (or arch9), zEC12 (or arch10), z13
++(or arch11), and arch12.
+
+ @menu
+ * s390 Options:: Command-line Options.
+diff -rup binutils.orig/gas/testsuite/gas/s390/s390.exp binutils-2.27/gas/testsuite/gas/s390/s390.exp
+--- binutils.orig/gas/testsuite/gas/s390/s390.exp 2017-03-24 14:50:54.051789225 +0000
++++ binutils-2.27/gas/testsuite/gas/s390/s390.exp 2017-03-24 14:54:05.065330554 +0000
+@@ -28,6 +28,7 @@ if [expr [istarget "s390-*-*"] || [ista
+ run_dump_test "zarch-z196" "{as -m64} {as -march=z196}"
+ run_dump_test "zarch-zEC12" "{as -m64} {as -march=zEC12}"
+ run_dump_test "zarch-z13" "{as -m64} {as -march=z13}"
++ run_dump_test "zarch-arch12" "{as -m64} {as -march=arch12}"
+ run_dump_test "zarch-reloc" "{as -m64}"
+ run_dump_test "zarch-operands" "{as -m64} {as -march=z9-109}"
+ run_dump_test "zarch-machine" "{as -m64} {as -march=z900}"
+diff --git a/gas/testsuite/gas/s390/zarch-arch12.d b/gas/testsuite/gas/s390/zarch-arch12.d
+new file mode 100644
+index 0000000..bc2ce18
+--- /dev/null
++++ b/gas/testsuite/gas/s390/zarch-arch12.d
+@@ -0,0 +1,200 @@
++#name: s390x opcode
++#objdump: -dr
++
++.*: +file format .*
++
++Disassembly of section .text:
++
++.* <foo>:
++.*: e7 f1 40 00 06 85 [ ]*vbperm %v15,%v17,%v20
++.*: e7 f6 9f a0 60 04 [ ]*vllezlf %v15,4000\(%r6,%r9\)
++.*: e7 f1 4d c0 87 b8 [ ]*vmsl %v15,%v17,%v20,%v24,13,12
++.*: e7 f1 43 d0 87 b8 [ ]*vmslg %v15,%v17,%v20,%v24,13
++.*: e7 f1 40 00 06 6c [ ]*vnx %v15,%v17,%v20
++.*: e7 f1 40 00 06 6e [ ]*vnn %v15,%v17,%v20
++.*: e7 f1 40 00 06 6f [ ]*voc %v15,%v17,%v20
++.*: e7 f1 00 00 04 50 [ ]*vpopctb %v15,%v17
++.*: e7 f1 00 00 14 50 [ ]*vpopcth %v15,%v17
++.*: e7 f1 00 00 24 50 [ ]*vpopctf %v15,%v17
++.*: e7 f1 00 00 34 50 [ ]*vpopctg %v15,%v17
++.*: e7 f1 40 00 26 e3 [ ]*vfasb %v15,%v17,%v20
++.*: e7 f1 40 08 26 e3 [ ]*wfasb %v15,%v17,%v20
++.*: e7 f1 40 08 46 e3 [ ]*wfaxb %v15,%v17,%v20
++.*: e7 f1 00 00 24 cb [ ]*wfcsb %v15,%v17
++.*: e7 f1 00 00 44 cb [ ]*wfcxb %v15,%v17
++.*: e7 f1 00 00 24 ca [ ]*wfksb %v15,%v17
++.*: e7 f1 00 00 44 ca [ ]*wfkxb %v15,%v17
++.*: e7 f1 40 00 26 e8 [ ]*vfcesb %v15,%v17,%v20
++.*: e7 f1 40 10 26 e8 [ ]*vfcesbs %v15,%v17,%v20
++.*: e7 f1 40 08 26 e8 [ ]*wfcesb %v15,%v17,%v20
++.*: e7 f1 40 18 26 e8 [ ]*wfcesbs %v15,%v17,%v20
++.*: e7 f1 40 08 46 e8 [ ]*wfcexb %v15,%v17,%v20
++.*: e7 f1 40 18 46 e8 [ ]*wfcexbs %v15,%v17,%v20
++.*: e7 f1 40 04 26 e8 [ ]*vfkesb %v15,%v17,%v20
++.*: e7 f1 40 14 26 e8 [ ]*vfkesbs %v15,%v17,%v20
++.*: e7 f1 40 0c 26 e8 [ ]*wfkesb %v15,%v17,%v20
++.*: e7 f1 40 1c 26 e8 [ ]*wfkesbs %v15,%v17,%v20
++.*: e7 f1 40 04 36 e8 [ ]*vfkedb %v15,%v17,%v20
++.*: e7 f1 40 14 36 e8 [ ]*vfkedbs %v15,%v17,%v20
++.*: e7 f1 40 0c 36 e8 [ ]*wfkedb %v15,%v17,%v20
++.*: e7 f1 40 1c 36 e8 [ ]*wfkedbs %v15,%v17,%v20
++.*: e7 f1 40 0c 46 e8 [ ]*wfkexb %v15,%v17,%v20
++.*: e7 f1 40 1c 46 e8 [ ]*wfkexbs %v15,%v17,%v20
++.*: e7 f1 40 00 26 eb [ ]*vfchsb %v15,%v17,%v20
++.*: e7 f1 40 10 26 eb [ ]*vfchsbs %v15,%v17,%v20
++.*: e7 f1 40 08 26 eb [ ]*wfchsb %v15,%v17,%v20
++.*: e7 f1 40 18 26 eb [ ]*wfchsbs %v15,%v17,%v20
++.*: e7 f1 40 08 46 eb [ ]*wfchxb %v15,%v17,%v20
++.*: e7 f1 40 18 46 eb [ ]*wfchxbs %v15,%v17,%v20
++.*: e7 f1 40 04 26 eb [ ]*vfkhsb %v15,%v17,%v20
++.*: e7 f1 40 14 26 eb [ ]*vfkhsbs %v15,%v17,%v20
++.*: e7 f1 40 0c 26 eb [ ]*wfkhsb %v15,%v17,%v20
++.*: e7 f1 40 1c 26 eb [ ]*wfkhsbs %v15,%v17,%v20
++.*: e7 f1 40 04 36 eb [ ]*vfkhdb %v15,%v17,%v20
++.*: e7 f1 40 14 36 eb [ ]*vfkhdbs %v15,%v17,%v20
++.*: e7 f1 40 0c 36 eb [ ]*wfkhdb %v15,%v17,%v20
++.*: e7 f1 40 1c 36 eb [ ]*wfkhdbs %v15,%v17,%v20
++.*: e7 f1 40 0c 46 eb [ ]*wfkhxb %v15,%v17,%v20
++.*: e7 f1 40 1c 46 eb [ ]*wfkhxbs %v15,%v17,%v20
++.*: e7 f1 40 00 26 ea [ ]*vfchesb %v15,%v17,%v20
++.*: e7 f1 40 10 26 ea [ ]*vfchesbs %v15,%v17,%v20
++.*: e7 f1 40 08 26 ea [ ]*wfchesb %v15,%v17,%v20
++.*: e7 f1 40 18 26 ea [ ]*wfchesbs %v15,%v17,%v20
++.*: e7 f1 40 08 46 ea [ ]*wfchexb %v15,%v17,%v20
++.*: e7 f1 40 18 46 ea [ ]*wfchexbs %v15,%v17,%v20
++.*: e7 f1 40 04 26 ea [ ]*vfkhesb %v15,%v17,%v20
++.*: e7 f1 40 14 26 ea [ ]*vfkhesbs %v15,%v17,%v20
++.*: e7 f1 40 0c 26 ea [ ]*wfkhesb %v15,%v17,%v20
++.*: e7 f1 40 1c 26 ea [ ]*wfkhesbs %v15,%v17,%v20
++.*: e7 f1 40 04 36 ea [ ]*vfkhedb %v15,%v17,%v20
++.*: e7 f1 40 14 36 ea [ ]*vfkhedbs %v15,%v17,%v20
++.*: e7 f1 40 0c 36 ea [ ]*wfkhedb %v15,%v17,%v20
++.*: e7 f1 40 1c 36 ea [ ]*wfkhedbs %v15,%v17,%v20
++.*: e7 f1 40 0c 46 ea [ ]*wfkhexb %v15,%v17,%v20
++.*: e7 f1 40 1c 46 ea [ ]*wfkhexbs %v15,%v17,%v20
++.*: e7 f1 40 00 26 e5 [ ]*vfdsb %v15,%v17,%v20
++.*: e7 f1 40 08 26 e5 [ ]*wfdsb %v15,%v17,%v20
++.*: e7 f1 40 08 46 e5 [ ]*wfdxb %v15,%v17,%v20
++.*: e7 f1 00 cd 24 c7 [ ]*wfisb %v15,%v17,5,12
++.*: e7 f1 00 cd 24 c7 [ ]*wfisb %v15,%v17,5,12
++.*: e7 f1 00 cd 44 c7 [ ]*wfixb %v15,%v17,5,12
++.*: e7 f1 00 0c d4 c4 [ ]*vfll %v15,%v17,13,12
++.*: e7 f1 00 00 24 c4 [ ]*vflls %v15,%v17
++.*: e7 f1 00 08 24 c4 [ ]*wflls %v15,%v17
++.*: e7 f1 00 08 34 c4 [ ]*wflld %v15,%v17
++.*: e7 f1 00 bc d4 c5 [ ]*vflr %v15,%v17,13,12,11
++.*: e7 f1 00 cd 34 c5 [ ]*wflrd %v15,%v17,5,12
++.*: e7 f1 00 cd 34 c5 [ ]*wflrd %v15,%v17,5,12
++.*: e7 f1 00 cd 44 c5 [ ]*wflrx %v15,%v17,5,12
++.*: e7 f1 40 bc d6 ef [ ]*vfmax %v15,%v17,%v20,13,12,11
++.*: e7 f1 40 d0 26 ef [ ]*vfmaxsb %v15,%v17,%v20,13
++.*: e7 f1 40 d0 36 ef [ ]*vfmaxdb %v15,%v17,%v20,13
++.*: e7 f1 40 d8 26 ef [ ]*wfmaxsb %v15,%v17,%v20,13
++.*: e7 f1 40 d8 36 ef [ ]*wfmaxdb %v15,%v17,%v20,13
++.*: e7 f1 40 d8 46 ef [ ]*wfmaxxb %v15,%v17,%v20,13
++.*: e7 f1 40 bc d6 ee [ ]*vfmin %v15,%v17,%v20,13,12,11
++.*: e7 f1 40 d0 26 ee [ ]*vfminsb %v15,%v17,%v20,13
++.*: e7 f1 40 d0 36 ee [ ]*vfmindb %v15,%v17,%v20,13
++.*: e7 f1 40 d8 26 ee [ ]*wfminsb %v15,%v17,%v20,13
++.*: e7 f1 40 d8 36 ee [ ]*wfmindb %v15,%v17,%v20,13
++.*: e7 f1 40 d8 46 ee [ ]*wfminxb %v15,%v17,%v20,13
++.*: e7 f1 40 00 26 e7 [ ]*vfmsb %v15,%v17,%v20
++.*: e7 f1 40 08 26 e7 [ ]*wfmsb %v15,%v17,%v20
++.*: e7 f1 40 08 46 e7 [ ]*wfmxb %v15,%v17,%v20
++.*: e7 f1 42 00 87 8f [ ]*vfmasb %v15,%v17,%v20,%v24
++.*: e7 f1 42 08 87 8f [ ]*wfmasb %v15,%v17,%v20,%v24
++.*: e7 f1 44 08 87 8f [ ]*wfmaxb %v15,%v17,%v20,%v24
++.*: e7 f1 42 00 87 8e [ ]*vfmssb %v15,%v17,%v20,%v24
++.*: e7 f1 42 08 87 8e [ ]*wfmssb %v15,%v17,%v20,%v24
++.*: e7 f1 44 08 87 8e [ ]*wfmsxb %v15,%v17,%v20,%v24
++.*: e7 f1 4c 0d 87 9f [ ]*vfnma %v15,%v17,%v20,%v24,13,12
++.*: e7 f1 42 00 87 9f [ ]*vfnmasb %v15,%v17,%v20,%v24
++.*: e7 f1 42 08 87 9f [ ]*wfnmasb %v15,%v17,%v20,%v24
++.*: e7 f1 43 00 87 9f [ ]*vfnmadb %v15,%v17,%v20,%v24
++.*: e7 f1 43 08 87 9f [ ]*wfnmadb %v15,%v17,%v20,%v24
++.*: e7 f1 44 08 87 9f [ ]*wfnmaxb %v15,%v17,%v20,%v24
++.*: e7 f1 4c 0d 87 9e [ ]*vfnms %v15,%v17,%v20,%v24,13,12
++.*: e7 f1 42 00 87 9e [ ]*vfnmssb %v15,%v17,%v20,%v24
++.*: e7 f1 42 08 87 9e [ ]*wfnmssb %v15,%v17,%v20,%v24
++.*: e7 f1 43 00 87 9e [ ]*vfnmsdb %v15,%v17,%v20,%v24
++.*: e7 f1 43 08 87 9e [ ]*wfnmsdb %v15,%v17,%v20,%v24
++.*: e7 f1 44 08 87 9e [ ]*wfnmsxb %v15,%v17,%v20,%v24
++.*: e7 f1 00 d0 24 cc [ ]*vfpsosb %v15,%v17,13
++.*: e7 f1 00 d8 24 cc [ ]*wfpsosb %v15,%v17,13
++.*: e7 f1 00 00 24 cc [ ]*vflcsb %v15,%v17
++.*: e7 f1 00 08 24 cc [ ]*wflcsb %v15,%v17
++.*: e7 f1 00 10 24 cc [ ]*vflnsb %v15,%v17
++.*: e7 f1 00 18 24 cc [ ]*wflnsb %v15,%v17
++.*: e7 f1 00 20 24 cc [ ]*vflpsb %v15,%v17
++.*: e7 f1 00 28 24 cc [ ]*wflpsb %v15,%v17
++.*: e7 f1 00 d8 44 cc [ ]*wfpsoxb %v15,%v17,13
++.*: e7 f1 00 08 44 cc [ ]*wflcxb %v15,%v17
++.*: e7 f1 00 18 44 cc [ ]*wflnxb %v15,%v17
++.*: e7 f1 00 28 44 cc [ ]*wflpxb %v15,%v17
++.*: e7 f1 00 00 24 ce [ ]*vfsqsb %v15,%v17
++.*: e7 f1 00 08 24 ce [ ]*wfsqsb %v15,%v17
++.*: e7 f1 00 08 44 ce [ ]*wfsqxb %v15,%v17
++.*: e7 f1 40 00 26 e2 [ ]*vfssb %v15,%v17,%v20
++.*: e7 f1 40 08 26 e2 [ ]*wfssb %v15,%v17,%v20
++.*: e7 f1 40 08 46 e2 [ ]*wfsxb %v15,%v17,%v20
++.*: e7 f1 ff d0 24 4a [ ]*vftcisb %v15,%v17,4093
++.*: e7 f1 ff d8 24 4a [ ]*wftcisb %v15,%v17,4093
++.*: e7 f1 ff d8 44 4a [ ]*wftcixb %v15,%v17,4093
++.*: e3 69 b8 f0 fd 38 [ ]*agh %r6,-10000\(%r9,%r11\)
++.*: e3 d6 98 f0 fd 47 [ ]*binh -10000\(%r6,%r9\)
++.*: e3 f6 98 f0 fd 47 [ ]*bi -10000\(%r6,%r9\)
++.*: e3 16 98 f0 fd 47 [ ]*bio -10000\(%r6,%r9\)
++.*: e3 26 98 f0 fd 47 [ ]*bih -10000\(%r6,%r9\)
++.*: e3 26 98 f0 fd 47 [ ]*bih -10000\(%r6,%r9\)
++.*: e3 36 98 f0 fd 47 [ ]*binle -10000\(%r6,%r9\)
++.*: e3 46 98 f0 fd 47 [ ]*bil -10000\(%r6,%r9\)
++.*: e3 46 98 f0 fd 47 [ ]*bil -10000\(%r6,%r9\)
++.*: e3 56 98 f0 fd 47 [ ]*binhe -10000\(%r6,%r9\)
++.*: e3 66 98 f0 fd 47 [ ]*bilh -10000\(%r6,%r9\)
++.*: e3 76 98 f0 fd 47 [ ]*bine -10000\(%r6,%r9\)
++.*: e3 76 98 f0 fd 47 [ ]*bine -10000\(%r6,%r9\)
++.*: e3 86 98 f0 fd 47 [ ]*bie -10000\(%r6,%r9\)
++.*: e3 86 98 f0 fd 47 [ ]*bie -10000\(%r6,%r9\)
++.*: e3 96 98 f0 fd 47 [ ]*binlh -10000\(%r6,%r9\)
++.*: e3 a6 98 f0 fd 47 [ ]*bihe -10000\(%r6,%r9\)
++.*: e3 b6 98 f0 fd 47 [ ]*binl -10000\(%r6,%r9\)
++.*: e3 b6 98 f0 fd 47 [ ]*binl -10000\(%r6,%r9\)
++.*: e3 c6 98 f0 fd 47 [ ]*bile -10000\(%r6,%r9\)
++.*: e3 d6 98 f0 fd 47 [ ]*binh -10000\(%r6,%r9\)
++.*: e3 d6 98 f0 fd 47 [ ]*binh -10000\(%r6,%r9\)
++.*: e3 e6 98 f0 fd 47 [ ]*bino -10000\(%r6,%r9\)
++.*: b9 ec b0 69 [ ]*mgrk %r6,%r9,%r11
++.*: e3 69 b8 f0 fd 84 [ ]*mg %r6,-10000\(%r9,%r11\)
++.*: e3 69 b8 f0 fd 3c [ ]*mgh %r6,-10000\(%r9,%r11\)
++.*: b9 fd b0 69 [ ]*msrkc %r6,%r9,%r11
++.*: b9 ed b0 69 [ ]*msgrkc %r6,%r9,%r11
++.*: e3 69 b8 f0 fd 53 [ ]*msc %r6,-10000\(%r9,%r11\)
++.*: e3 69 b8 f0 fd 83 [ ]*msgc %r6,-10000\(%r9,%r11\)
++.*: e3 69 b8 f0 fd 39 [ ]*sgh %r6,-10000\(%r9,%r11\)
++.*: e6 06 9f a0 f0 37 [ ]*vlrlr %v15,%r6,4000\(%r9\)
++.*: e6 fd 6f a0 f0 35 [ ]*vlrl %v15,4000\(%r6\),253
++.*: e6 06 9f a0 f0 3f [ ]*vstrlr %v15,%r6,4000\(%r9\)
++.*: e6 fd 6f a0 f0 3d [ ]*vstrl %v15,4000\(%r6\),253
++.*: e6 f1 40 cf d6 71 [ ]*vap %v15,%v17,%v20,253,12
++.*: e6 0f 10 d0 02 77 [ ]*vcp %v15,%v17,13
++.*: e6 6f 00 d0 00 50 [ ]*vcvb %r6,%v15,13
++.*: e6 6f 00 d0 00 52 [ ]*vcvbg %r6,%v15,13
++.*: e6 f6 00 cf d0 58 [ ]*vcvd %v15,%r6,253,12
++.*: e6 f6 00 cf d0 5a [ ]*vcvdg %v15,%r6,253,12
++.*: e6 f1 40 cf d6 7a [ ]*vdp %v15,%v17,%v20,253,12
++.*: e6 f0 ff fd c0 49 [ ]*vlip %v15,65533,12
++.*: e6 f1 40 cf d6 78 [ ]*vmp %v15,%v17,%v20,253,12
++.*: e6 f1 40 cf d6 79 [ ]*vmsp %v15,%v17,%v20,253,12
++.*: e6 fd 6f a0 f0 34 [ ]*vpkz %v15,4000\(%r6\),253
++.*: e6 f1 fc bf d4 5b [ ]*vpsop %v15,%v17,253,252,11
++.*: e6 f1 40 cf d6 7b [ ]*vrp %v15,%v17,%v20,253,12
++.*: e6 f1 40 cf d6 7e [ ]*vsdp %v15,%v17,%v20,253,12
++.*: e6 f1 fc bf d4 59 [ ]*vsrp %v15,%v17,253,252,11
++.*: e6 f1 40 cf d6 73 [ ]*vsp %v15,%v17,%v20,253,12
++.*: e6 0f 00 00 00 5f [ ]*vtp %v15
++.*: e6 fd 6f a0 f0 3c [ ]*vupkz %v15,4000\(%r6\),253
++.*: e3 69 b8 f0 fd 4c [ ]*lgg %r6,-10000\(%r9,%r11\)
++.*: e3 69 b8 f0 fd 48 [ ]*llgfsg %r6,-10000\(%r9,%r11\)
++.*: e3 69 b8 f0 fd 4d [ ]*lgsc %r6,-10000\(%r9,%r11\)
++.*: e3 69 b8 f0 fd 49 [ ]*stgsc %r6,-10000\(%r9,%r11\)
++.*: b9 29 90 6b [ ]*kma %r6,%r9,%r11
+diff --git a/gas/testsuite/gas/s390/zarch-arch12.s b/gas/testsuite/gas/s390/zarch-arch12.s
+new file mode 100644
+index 0000000..6ebd2fd
+--- /dev/null
++++ b/gas/testsuite/gas/s390/zarch-arch12.s
+@@ -0,0 +1,194 @@
++.text
++foo:
++ vbperm %v15,%v17,%v20
++ vllezlf %v15,4000(%r6,%r9)
++ vmsl %v15,%v17,%v20,%v24,13,12
++ vmslg %v15,%v17,%v20,%v24,13
++ vnx %v15,%v17,%v20
++ vnn %v15,%v17,%v20
++ voc %v15,%v17,%v20
++ vpopctb %v15,%v17
++ vpopcth %v15,%v17
++ vpopctf %v15,%v17
++ vpopctg %v15,%v17
++ vfasb %v15,%v17,%v20
++ wfasb %v15,%v17,%v20
++ wfaxb %v15,%v17,%v20
++ wfcsb %v15,%v17
++ wfcxb %v15,%v17
++ wfksb %v15,%v17
++ wfkxb %v15,%v17
++ vfcesb %v15,%v17,%v20
++ vfcesbs %v15,%v17,%v20
++ wfcesb %v15,%v17,%v20
++ wfcesbs %v15,%v17,%v20
++ wfcexb %v15,%v17,%v20
++ wfcexbs %v15,%v17,%v20
++ vfkesb %v15,%v17,%v20
++ vfkesbs %v15,%v17,%v20
++ wfkesb %v15,%v17,%v20
++ wfkesbs %v15,%v17,%v20
++ vfkedb %v15,%v17,%v20
++ vfkedbs %v15,%v17,%v20
++ wfkedb %v15,%v17,%v20
++ wfkedbs %v15,%v17,%v20
++ wfkexb %v15,%v17,%v20
++ wfkexbs %v15,%v17,%v20
++ vfchsb %v15,%v17,%v20
++ vfchsbs %v15,%v17,%v20
++ wfchsb %v15,%v17,%v20
++ wfchsbs %v15,%v17,%v20
++ wfchxb %v15,%v17,%v20
++ wfchxbs %v15,%v17,%v20
++ vfkhsb %v15,%v17,%v20
++ vfkhsbs %v15,%v17,%v20
++ wfkhsb %v15,%v17,%v20
++ wfkhsbs %v15,%v17,%v20
++ vfkhdb %v15,%v17,%v20
++ vfkhdbs %v15,%v17,%v20
++ wfkhdb %v15,%v17,%v20
++ wfkhdbs %v15,%v17,%v20
++ wfkhxb %v15,%v17,%v20
++ wfkhxbs %v15,%v17,%v20
++ vfchesb %v15,%v17,%v20
++ vfchesbs %v15,%v17,%v20
++ wfchesb %v15,%v17,%v20
++ wfchesbs %v15,%v17,%v20
++ wfchexb %v15,%v17,%v20
++ wfchexbs %v15,%v17,%v20
++ vfkhesb %v15,%v17,%v20
++ vfkhesbs %v15,%v17,%v20
++ wfkhesb %v15,%v17,%v20
++ wfkhesbs %v15,%v17,%v20
++ vfkhedb %v15,%v17,%v20
++ vfkhedbs %v15,%v17,%v20
++ wfkhedb %v15,%v17,%v20
++ wfkhedbs %v15,%v17,%v20
++ wfkhexb %v15,%v17,%v20
++ wfkhexbs %v15,%v17,%v20
++ vfdsb %v15,%v17,%v20
++ wfdsb %v15,%v17,%v20
++ wfdxb %v15,%v17,%v20
++ vfisb %v15,%v17,13,12
++ wfisb %v15,%v17,13,12
++ wfixb %v15,%v17,13,12
++ vfll %v15,%v17,13,12
++ vflls %v15,%v17
++ wflls %v15,%v17
++ wflld %v15,%v17
++ vflr %v15,%v17,13,12,11
++ vflrd %v15,%v17,13,12
++ wflrd %v15,%v17,13,12
++ wflrx %v15,%v17,13,12
++ vfmax %v15,%v17,%v20,13,12,11
++ vfmaxsb %v15,%v17,%v20,13
++ vfmaxdb %v15,%v17,%v20,13
++ wfmaxsb %v15,%v17,%v20,13
++ wfmaxdb %v15,%v17,%v20,13
++ wfmaxxb %v15,%v17,%v20,13
++ vfmin %v15,%v17,%v20,13,12,11
++ vfminsb %v15,%v17,%v20,13
++ vfmindb %v15,%v17,%v20,13
++ wfminsb %v15,%v17,%v20,13
++ wfmindb %v15,%v17,%v20,13
++ wfminxb %v15,%v17,%v20,13
++ vfmsb %v15,%v17,%v20
++ wfmsb %v15,%v17,%v20
++ wfmxb %v15,%v17,%v20
++ vfmasb %v15,%v17,%v20,%v24
++ wfmasb %v15,%v17,%v20,%v24
++ wfmaxb %v15,%v17,%v20,%v24
++ vfmssb %v15,%v17,%v20,%v24
++ wfmssb %v15,%v17,%v20,%v24
++ wfmsxb %v15,%v17,%v20,%v24
++ vfnma %v15,%v17,%v20,%v24,13,12
++ vfnmasb %v15,%v17,%v20,%v24
++ wfnmasb %v15,%v17,%v20,%v24
++ vfnmadb %v15,%v17,%v20,%v24
++ wfnmadb %v15,%v17,%v20,%v24
++ wfnmaxb %v15,%v17,%v20,%v24
++ vfnms %v15,%v17,%v20,%v24,13,12
++ vfnmssb %v15,%v17,%v20,%v24
++ wfnmssb %v15,%v17,%v20,%v24
++ vfnmsdb %v15,%v17,%v20,%v24
++ wfnmsdb %v15,%v17,%v20,%v24
++ wfnmsxb %v15,%v17,%v20,%v24
++ vfpsosb %v15,%v17,13
++ wfpsosb %v15,%v17,13
++ vflcsb %v15,%v17
++ wflcsb %v15,%v17
++ vflnsb %v15,%v17
++ wflnsb %v15,%v17
++ vflpsb %v15,%v17
++ wflpsb %v15,%v17
++ wfpsoxb %v15,%v17,13
++ wflcxb %v15,%v17
++ wflnxb %v15,%v17
++ wflpxb %v15,%v17
++ vfsqsb %v15,%v17
++ wfsqsb %v15,%v17
++ wfsqxb %v15,%v17
++ vfssb %v15,%v17,%v20
++ wfssb %v15,%v17,%v20
++ wfsxb %v15,%v17,%v20
++ vftcisb %v15,%v17,4093
++ wftcisb %v15,%v17,4093
++ wftcixb %v15,%v17,4093
++ agh %r6,-10000(%r9,%r11)
++ bic 13,-10000(%r6,%r9)
++ bi -10000(%r6,%r9)
++ bio -10000(%r6,%r9)
++ bih -10000(%r6,%r9)
++ bip -10000(%r6,%r9)
++ binle -10000(%r6,%r9)
++ bil -10000(%r6,%r9)
++ bim -10000(%r6,%r9)
++ binhe -10000(%r6,%r9)
++ bilh -10000(%r6,%r9)
++ bine -10000(%r6,%r9)
++ binz -10000(%r6,%r9)
++ bie -10000(%r6,%r9)
++ biz -10000(%r6,%r9)
++ binlh -10000(%r6,%r9)
++ bihe -10000(%r6,%r9)
++ binl -10000(%r6,%r9)
++ binm -10000(%r6,%r9)
++ bile -10000(%r6,%r9)
++ binh -10000(%r6,%r9)
++ binp -10000(%r6,%r9)
++ bino -10000(%r6,%r9)
++ mgrk %r6,%r9,%r11
++ mg %r6,-10000(%r9,%r11)
++ mgh %r6,-10000(%r9,%r11)
++ msrkc %r6,%r9,%r11
++ msgrkc %r6,%r9,%r11
++ msc %r6,-10000(%r9,%r11)
++ msgc %r6,-10000(%r9,%r11)
++ sgh %r6,-10000(%r9,%r11)
++ vlrlr %v15,%r6,4000(%r9)
++ vlrl %v15,4000(%r6),253
++ vstrlr %v15,%r6,4000(%r9)
++ vstrl %v15,4000(%r6),253
++ vap %v15,%v17,%v20,253,12
++ vcp %v15,%v17,13
++ vcvb %r6,%v15,13
++ vcvbg %r6,%v15,13
++ vcvd %v15,%r6,253,12
++ vcvdg %v15,%r6,253,12
++ vdp %v15,%v17,%v20,253,12
++ vlip %v15,65533,12
++ vmp %v15,%v17,%v20,253,12
++ vmsp %v15,%v17,%v20,253,12
++ vpkz %v15,4000(%r6),253
++ vpsop %v15,%v17,253,252,11
++ vrp %v15,%v17,%v20,253,12
++ vsdp %v15,%v17,%v20,253,12
++ vsrp %v15,%v17,253,252,11
++ vsp %v15,%v17,%v20,253,12
++ vtp %v15
++ vupkz %v15,4000(%r6),253
++ lgg %r6,-10000(%r9,%r11)
++ llgfsg %r6,-10000(%r9,%r11)
++ lgsc %r6,-10000(%r9,%r11)
++ stgsc %r6,-10000(%r9,%r11)
++ kma %r6,%r9,%r11
+diff -rup binutils.orig/gas/testsuite/gas/s390/zarch-z13.d binutils-2.27/gas/testsuite/gas/s390/zarch-z13.d
+--- binutils.orig/gas/testsuite/gas/s390/zarch-z13.d 2017-03-24 14:50:54.052789212 +0000
++++ binutils-2.27/gas/testsuite/gas/s390/zarch-z13.d 2017-03-24 14:54:05.065330554 +0000
+@@ -513,12 +513,12 @@ Disassembly of section .text:
+ .*: e7 f1 00 bc d4 c7 [ ]*vfi %v15,%v17,13,12,11
+ .*: e7 f1 00 cd 34 c7 [ ]*wfidb %v15,%v17,5,12
+ .*: e7 f1 00 cd 34 c7 [ ]*wfidb %v15,%v17,5,12
+-.*: e7 f1 00 0c d4 c4 [ ]*vlde %v15,%v17,13,12
+-.*: e7 f1 00 00 24 c4 [ ]*vldeb %v15,%v17
+-.*: e7 f1 00 08 24 c4 [ ]*wldeb %v15,%v17
+-.*: e7 f1 00 bc d4 c5 [ ]*vled %v15,%v17,13,12,11
+-.*: e7 f1 00 cd 34 c5 [ ]*wledb %v15,%v17,5,12
+-.*: e7 f1 00 cd 34 c5 [ ]*wledb %v15,%v17,5,12
++.*: e7 f1 00 0c d4 c4 [ ]*vfll %v15,%v17,13,12
++.*: e7 f1 00 00 24 c4 [ ]*vflls %v15,%v17
++.*: e7 f1 00 08 24 c4 [ ]*wflls %v15,%v17
++.*: e7 f1 00 bc d4 c5 [ ]*vflr %v15,%v17,13,12,11
++.*: e7 f1 00 cd 34 c5 [ ]*wflrd %v15,%v17,5,12
++.*: e7 f1 00 cd 34 c5 [ ]*wflrd %v15,%v17,5,12
+ .*: e7 f1 40 0c d6 e7 [ ]*vfm %v15,%v17,%v20,13,12
+ .*: e7 f1 40 00 36 e7 [ ]*vfmdb %v15,%v17,%v20
+ .*: e7 f1 40 08 36 e7 [ ]*wfmdb %v15,%v17,%v20
+diff -rup binutils.orig/include/opcode/s390.h binutils-2.27/include/opcode/s390.h
+--- binutils.orig/include/opcode/s390.h 2017-03-24 14:51:01.896688195 +0000
++++ binutils-2.27/include/opcode/s390.h 2017-03-24 14:54:05.065330554 +0000
+@@ -42,14 +42,17 @@ enum s390_opcode_cpu_val
+ S390_OPCODE_Z196,
+ S390_OPCODE_ZEC12,
+ S390_OPCODE_Z13,
++ S390_OPCODE_ARCH12,
+ S390_OPCODE_MAXCPU
+ };
+
+ /* Instruction specific flags. */
+ #define S390_INSTR_FLAG_OPTPARM 0x1
++
+ #define S390_INSTR_FLAG_HTM 0x2
+ #define S390_INSTR_FLAG_VX 0x4
+-#define S390_INSTR_FLAG_FACILITY_MASK 0x6
++#define S390_INSTR_FLAG_VX2 0x8
++#define S390_INSTR_FLAG_FACILITY_MASK 0xe
+
+ /* The opcode table is an array of struct s390_opcode. */
+
+diff -rup binutils.orig/opcodes/s390-mkopc.c binutils-2.27/opcodes/s390-mkopc.c
+--- binutils.orig/opcodes/s390-mkopc.c 2017-03-24 14:50:54.849778948 +0000
++++ binutils-2.27/opcodes/s390-mkopc.c 2017-03-24 14:54:05.065330554 +0000
+@@ -366,6 +366,8 @@ main (void)
+ min_cpu = S390_OPCODE_ZEC12;
+ else if (strcmp (cpu_string, "z13") == 0)
+ min_cpu = S390_OPCODE_Z13;
++ else if (strcmp (cpu_string, "arch12") == 0)
++ min_cpu = S390_OPCODE_ARCH12;
+ else {
+ fprintf (stderr, "Couldn't parse cpu string %s\n", cpu_string);
+ exit (1);
+@@ -409,6 +411,10 @@ main (void)
+ && (str[2] == 0 || str[2] == ',')) {
+ flag_bits |= S390_INSTR_FLAG_VX;
+ str += 2;
++ } else if (strncmp (str, "vx2", 3) == 0
++ && (str[3] == 0 || str[3] == ',')) {
++ flag_bits |= S390_INSTR_FLAG_VX2;
++ str += 3;
+ } else {
+ fprintf (stderr, "Couldn't parse flags string %s\n",
+ flags_string);
+diff -rup binutils.orig/opcodes/s390-opc.c binutils-2.27/opcodes/s390-opc.c
+--- binutils.orig/opcodes/s390-opc.c 2017-03-24 14:50:54.850778935 +0000
++++ binutils-2.27/opcodes/s390-opc.c 2017-03-24 14:54:05.065330554 +0000
+@@ -220,28 +220,30 @@ const struct s390_operand s390_operands[
+ { 8, 16, 0 },
+ #define U8_24 69 /* 8 bit unsigned value starting at 24 */
+ { 8, 24, 0 },
+-#define U8_32 70 /* 8 bit unsigned value starting at 32 */
++#define U8_28 70 /* 8 bit unsigned value starting at 28 */
++ { 8, 28, 0 },
++#define U8_32 71 /* 8 bit unsigned value starting at 32 */
+ { 8, 32, 0 },
+-#define U12_16 71 /* 12 bit unsigned value starting at 16 */
++#define U12_16 72 /* 12 bit unsigned value starting at 16 */
+ { 12, 16, 0 },
+-#define U16_16 72 /* 16 bit unsigned value starting at 16 */
++#define U16_16 73 /* 16 bit unsigned value starting at 16 */
+ { 16, 16, 0 },
+-#define U16_32 73 /* 16 bit unsigned value starting at 32 */
++#define U16_32 74 /* 16 bit unsigned value starting at 32 */
+ { 16, 32, 0 },
+-#define U32_16 74 /* 32 bit unsigned value starting at 16 */
++#define U32_16 75 /* 32 bit unsigned value starting at 16 */
+ { 32, 16, 0 },
+
+ /* PC-relative address operands. */
+
+-#define J12_12 75 /* 12 bit PC relative offset at 12 */
++#define J12_12 76 /* 12 bit PC relative offset at 12 */
+ { 12, 12, S390_OPERAND_PCREL },
+-#define J16_16 76 /* 16 bit PC relative offset at 16 */
++#define J16_16 77 /* 16 bit PC relative offset at 16 */
+ { 16, 16, S390_OPERAND_PCREL },
+-#define J16_32 77 /* 16 bit PC relative offset at 32 */
++#define J16_32 78 /* 16 bit PC relative offset at 32 */
+ { 16, 32, S390_OPERAND_PCREL },
+-#define J24_24 78 /* 24 bit PC relative offset at 24 */
++#define J24_24 79 /* 24 bit PC relative offset at 24 */
+ { 24, 24, S390_OPERAND_PCREL },
+-#define J32_16 79 /* 32 bit PC relative offset at 16 */
++#define J32_16 80 /* 32 bit PC relative offset at 16 */
+ { 32, 16, S390_OPERAND_PCREL },
+
+ };
+@@ -425,6 +427,7 @@ const struct s390_operand s390_operands[
+ #define INSTR_RXY_RERRD 6, { RE_8,D20_20,X_12,B_16,0,0 } /* e.g. dsg */
+ #define INSTR_RXY_FRRD 6, { F_8,D20_20,X_12,B_16,0,0 } /* e.g. ley */
+ #define INSTR_RXY_URRD 6, { U4_8,D20_20,X_12,B_16,0,0 } /* e.g. pfd */
++#define INSTR_RXY_0RRD 6, { D20_20,X_12,B_16,0,0 } /* e.g. bic */
+ #define INSTR_RX_0RRD 4, { D_20,X_12,B_16,0,0,0 } /* e.g. be */
+ #define INSTR_RX_FRRD 4, { F_8,D_20,X_12,B_16,0,0 } /* e.g. ae */
+ #define INSTR_RX_FERRD 4, { FE_8,D_20,X_12,B_16,0,0 } /* e.g. mxd */
+@@ -454,23 +457,29 @@ const struct s390_operand s390_operands[
+ #define INSTR_VRI_V 6, { V_8,0,0,0,0,0 } /* e.g. vzero */
+ #define INSTR_VRI_V0UUU 6, { V_8,U8_16,U8_24,U4_32,0,0 } /* e.g. vgm */
+ #define INSTR_VRI_V0UU 6, { V_8,U8_16,U8_24,0,0,0 } /* e.g. vgmb */
++#define INSTR_VRI_V0UU2 6, { V_8,U16_16,U4_32,0,0,0 } /* e.g. vlip */
+ #define INSTR_VRI_VVUU 6, { V_8,V_12,U16_16,U4_32,0,0 } /* e.g. vrep */
+ #define INSTR_VRI_VVU 6, { V_8,V_12,U16_16,0,0,0 } /* e.g. vrepb */
+ #define INSTR_VRI_VVU2 6, { V_8,V_12,U12_16,0,0,0 } /* e.g. vftcidb */
+ #define INSTR_VRI_V0IU 6, { V_8,I16_16,U4_32,0,0,0 } /* e.g. vrepi */
+ #define INSTR_VRI_V0I 6, { V_8,I16_16,0,0,0,0 } /* e.g. vrepib */
+ #define INSTR_VRI_VVV0UU 6, { V_8,V_12,V_16,U8_24,U4_32,0 } /* e.g. verim */
++#define INSTR_VRI_VVV0UU2 6, { V_8,V_12,V_16,U8_28,U4_24,0 } /* e.g. vap */
+ #define INSTR_VRI_VVV0U 6, { V_8,V_12,V_16,U8_24,0,0 } /* e.g. verimb*/
+ #define INSTR_VRI_VVUUU 6, { V_8,V_12,U12_16,U4_32,U4_28,0 } /* e.g. vftci */
++#define INSTR_VRI_VVUUU2 6, { V_8,V_12,U8_28,U8_16,U4_24,0 } /* e.g. vpsop */
++#define INSTR_VRI_VR0UU 6, { V_8,R_12,U8_28,U4_24,0,0 } /* e.g. vcvd */
+ #define INSTR_VRX_VRRD 6, { V_8,D_20,X_12,B_16,0,0 } /* e.g. vl */
+ #define INSTR_VRX_VV 6, { V_8,V_12,0,0,0,0 } /* e.g. vlr */
+-#define INSTR_VRX_VRRDU 6, { V_8,D_20,X_12,B_16,U4_32,0 } /* e.g. vlrp */
++#define INSTR_VRX_VRRDU 6, { V_8,D_20,X_12,B_16,U4_32,0 } /* e.g. vlrep */
+ #define INSTR_VRS_RVRDU 6, { R_8,V_12,D_20,B_16,U4_32,0 } /* e.g. vlgv */
+ #define INSTR_VRS_RVRD 6, { R_8,V_12,D_20,B_16,0,0 } /* e.g. vlgvb */
+ #define INSTR_VRS_VVRDU 6, { V_8,V_12,D_20,B_16,U4_32,0 } /* e.g. verll */
+ #define INSTR_VRS_VVRD 6, { V_8,V_12,D_20,B_16,0,0 } /* e.g. vlm */
+ #define INSTR_VRS_VRRDU 6, { V_8,R_12,D_20,B_16,U4_32,0 } /* e.g. vlvg */
+ #define INSTR_VRS_VRRD 6, { V_8,R_12,D_20,B_16,0,0 } /* e.g. vlvgb */
++#define INSTR_VRS_RRDV 6, { V_32,R_12,D_20,B_16,0,0 } /* e.g. vlrlr */
++#define INSTR_VRR_0V 6, { V_12,0,0,0,0,0 } /* e.g. vtp */
+ #define INSTR_VRR_VRR 6, { V_8,R_12,R_16,0,0,0 } /* e.g. vlvgp */
+ #define INSTR_VRR_VVV0U 6, { V_8,V_12,V_16,U4_32,0,0 } /* e.g. vmrh */
+ #define INSTR_VRR_VVV0U0 6, { V_8,V_12,V_16,U4_24,0,0 } /* e.g. vfaeb */
+@@ -499,6 +508,9 @@ const struct s390_operand s390_operands[
+ #define INSTR_VRR_VV0UUU 6, { V_8,V_12,U4_32,U4_28,U4_24,0 } /* e.g. vcdg */
+ #define INSTR_VRR_VVVU0UV 6, { V_8,V_12,V_16,V_32,U4_28,U4_20 } /* e.g. vfma */
+ #define INSTR_VRR_VV0U0U 6, { V_8,V_12,U4_32,U4_24,0,0 } /* e.g. vistr */
++#define INSTR_VRR_0VV0U 6, { V_12,V_16,U4_24,0,0,0 } /* e.g. vcp */
++#define INSTR_VRR_RV0U 6, { R_8,V_12,U4_24,0,0,0 } /* e.g. vcvb */
++#define INSTR_VSI_URDV 6, { V_32,D_20,B_16,U8_8,0,0 } /* e.g. vlrl */
+
+ #define MASK_E { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 }
+ #define MASK_IE_UU { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 }
+@@ -631,6 +643,7 @@ const struct s390_operand s390_operands[
+ #define MASK_RXY_RERRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
+ #define MASK_RXY_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
+ #define MASK_RXY_URRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
++#define MASK_RXY_0RRD { 0xff, 0xf0, 0x00, 0x00, 0x00, 0xff }
+ #define MASK_RX_0RRD { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 }
+ #define MASK_RX_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
+ #define MASK_RX_FERRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 }
+@@ -660,14 +673,18 @@ const struct s390_operand s390_operands[
+ #define MASK_VRI_V { 0xff, 0x0f, 0xff, 0xff, 0xf0, 0xff }
+ #define MASK_VRI_V0UUU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0xff }
+ #define MASK_VRI_V0UU { 0xff, 0x0f, 0x00, 0x00, 0xf0, 0xff }
++#define MASK_VRI_V0UU2 { 0xff, 0x0f, 0x00, 0x00, 0x00, 0xff }
+ #define MASK_VRI_VVUU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
+ #define MASK_VRI_VVU { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff }
+ #define MASK_VRI_VVU2 { 0xff, 0x00, 0x00, 0x0f, 0xf0, 0xff }
+ #define MASK_VRI_V0IU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0xff }
+ #define MASK_VRI_V0I { 0xff, 0x0f, 0x00, 0x00, 0xf0, 0xff }
+ #define MASK_VRI_VVV0UU { 0xff, 0x00, 0x0f, 0x00, 0x00, 0xff }
++#define MASK_VRI_VVV0UU2 { 0xff, 0x00, 0x0f, 0x00, 0x00, 0xff }
+ #define MASK_VRI_VVV0U { 0xff, 0x00, 0x0f, 0x00, 0xf0, 0xff }
+ #define MASK_VRI_VVUUU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
++#define MASK_VRI_VVUUU2 { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
++#define MASK_VRI_VR0UU { 0xff, 0x00, 0xff, 0x00, 0x00, 0xff }
+ #define MASK_VRX_VRRD { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff }
+ #define MASK_VRX_VV { 0xff, 0x00, 0xff, 0xff, 0xf0, 0xff }
+ #define MASK_VRX_VRRDU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
+@@ -677,6 +694,8 @@ const struct s390_operand s390_operands[
+ #define MASK_VRS_VVRD { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff }
+ #define MASK_VRS_VRRDU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
+ #define MASK_VRS_VRRD { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff }
++#define MASK_VRS_RRDV { 0xff, 0xf0, 0x00, 0x00, 0x00, 0xff }
++#define MASK_VRR_0V { 0xff, 0xf0, 0xff, 0xff, 0xf0, 0xff }
+ #define MASK_VRR_VRR { 0xff, 0x00, 0x0f, 0xff, 0xf0, 0xff }
+ #define MASK_VRR_VVV0U { 0xff, 0x00, 0x0f, 0xff, 0x00, 0xff }
+ #define MASK_VRR_VVV0U0 { 0xff, 0x00, 0x0f, 0x0f, 0xf0, 0xff }
+@@ -705,36 +724,46 @@ const struct s390_operand s390_operands[
+ #define MASK_VRR_VV0UUU { 0xff, 0x00, 0xff, 0x00, 0x00, 0xff }
+ #define MASK_VRR_VVVU0UV { 0xff, 0x00, 0x00, 0xf0, 0x00, 0xff }
+ #define MASK_VRR_VV0U0U { 0xff, 0x00, 0xff, 0x0f, 0x00, 0xff }
++#define MASK_VRR_0VV0U { 0xff, 0xf0, 0x0f, 0x0f, 0xf0, 0xff }
++#define MASK_VRR_RV0U { 0xff, 0x00, 0xff, 0x0f, 0xf0, 0xff }
++#define MASK_VSI_URDV { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff }
++
+
+ /* The opcode formats table (blueprints for .insn pseudo mnemonic). */
+
+ const struct s390_opcode s390_opformats[] =
+ {
+- { "e", OP8(0x00LL), MASK_E, INSTR_E, 3, 0 ,0 },
+- { "ri", OP8(0x00LL), MASK_RI_RI, INSTR_RI_RI, 3, 0 ,0 },
+- { "rie", OP8(0x00LL), MASK_RIE_RRP, INSTR_RIE_RRP, 3, 0 ,0 },
+- { "ril", OP8(0x00LL), MASK_RIL_RP, INSTR_RIL_RP, 3, 0 ,0 },
+- { "rilu", OP8(0x00LL), MASK_RIL_RU, INSTR_RIL_RU, 3, 0 ,0 },
+- { "ris", OP8(0x00LL), MASK_RIS_RURDI, INSTR_RIS_RURDI,3, 6 ,0 },
+- { "rr", OP8(0x00LL), MASK_RR_RR, INSTR_RR_RR, 3, 0 ,0 },
+- { "rre", OP8(0x00LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0 ,0 },
+- { "rrf", OP8(0x00LL), MASK_RRF_RURR, INSTR_RRF_RURR, 3, 0 ,0 },
+- { "rrs", OP8(0x00LL), MASK_RRS_RRRDU, INSTR_RRS_RRRDU,3, 6 ,0 },
+- { "rs", OP8(0x00LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0 ,0 },
+- { "rse", OP8(0x00LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 3, 0 ,0 },
+- { "rsi", OP8(0x00LL), MASK_RSI_RRP, INSTR_RSI_RRP, 3, 0 ,0 },
+- { "rsy", OP8(0x00LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 3, 3 ,0 },
+- { "rx", OP8(0x00LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0 ,0 },
+- { "rxe", OP8(0x00LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 0 ,0 },
+- { "rxf", OP8(0x00LL), MASK_RXF_RRRDR, INSTR_RXF_RRRDR,3, 0 ,0 },
+- { "rxy", OP8(0x00LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3 ,0 },
+- { "s", OP8(0x00LL), MASK_S_RD, INSTR_S_RD, 3, 0 ,0 },
+- { "si", OP8(0x00LL), MASK_SI_URD, INSTR_SI_URD, 3, 0 ,0 },
+- { "siy", OP8(0x00LL), MASK_SIY_URD, INSTR_SIY_URD, 3, 3 ,0 },
+- { "sil", OP8(0x00LL), MASK_SIL_RDI, INSTR_SIL_RDI, 3, 6 ,0 },
+- { "ss", OP8(0x00LL), MASK_SS_RRRDRD, INSTR_SS_RRRDRD,3, 0 ,0 },
+- { "sse", OP8(0x00LL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 3, 0 ,0 },
+- { "ssf", OP8(0x00LL), MASK_SSF_RRDRD, INSTR_SSF_RRDRD,3, 0 ,0 },
++ { "e", OP8(0x00LL), MASK_E, INSTR_E, 3, 0 ,0 },
++ { "ri", OP8(0x00LL), MASK_RI_RI, INSTR_RI_RI, 3, 0 ,0 },
++ { "rie", OP8(0x00LL), MASK_RIE_RRP, INSTR_RIE_RRP, 3, 0 ,0 },
++ { "ril", OP8(0x00LL), MASK_RIL_RP, INSTR_RIL_RP, 3, 0 ,0 },
++ { "rilu", OP8(0x00LL), MASK_RIL_RU, INSTR_RIL_RU, 3, 0 ,0 },
++ { "ris", OP8(0x00LL), MASK_RIS_RURDI, INSTR_RIS_RURDI, 3, 6 ,0 },
++ { "rr", OP8(0x00LL), MASK_RR_RR, INSTR_RR_RR, 3, 0 ,0 },
++ { "rre", OP8(0x00LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0 ,0 },
++ { "rrf", OP8(0x00LL), MASK_RRF_RURR, INSTR_RRF_RURR, 3, 0 ,0 },
++ { "rrs", OP8(0x00LL), MASK_RRS_RRRDU, INSTR_RRS_RRRDU, 3, 6 ,0 },
++ { "rs", OP8(0x00LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0 ,0 },
++ { "rse", OP8(0x00LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 3, 0 ,0 },
++ { "rsi", OP8(0x00LL), MASK_RSI_RRP, INSTR_RSI_RRP, 3, 0 ,0 },
++ { "rsy", OP8(0x00LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 3, 3 ,0 },
++ { "rx", OP8(0x00LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0 ,0 },
++ { "rxe", OP8(0x00LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 0 ,0 },
++ { "rxf", OP8(0x00LL), MASK_RXF_RRRDR, INSTR_RXF_RRRDR, 3, 0 ,0 },
++ { "rxy", OP8(0x00LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3 ,0 },
++ { "s", OP8(0x00LL), MASK_S_RD, INSTR_S_RD, 3, 0 ,0 },
++ { "si", OP8(0x00LL), MASK_SI_URD, INSTR_SI_URD, 3, 0 ,0 },
++ { "siy", OP8(0x00LL), MASK_SIY_URD, INSTR_SIY_URD, 3, 3 ,0 },
++ { "sil", OP8(0x00LL), MASK_SIL_RDI, INSTR_SIL_RDI, 3, 6 ,0 },
++ { "ss", OP8(0x00LL), MASK_SS_RRRDRD, INSTR_SS_RRRDRD, 3, 0 ,0 },
++ { "sse", OP8(0x00LL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 3, 0 ,0 },
++ { "ssf", OP8(0x00LL), MASK_SSF_RRDRD, INSTR_SSF_RRDRD, 3, 0 ,0 },
++ { "vrv", OP8(0x00LL), MASK_VRV_VVXRDU, INSTR_VRV_VVXRDU, 3, 9 ,0 },
++ { "vri", OP8(0x00LL), MASK_VRI_VVUUU, INSTR_VRI_VVUUU, 3, 9 ,0 },
++ { "vrx", OP8(0x00LL), MASK_VRX_VRRDU, INSTR_VRX_VRRDU, 3, 9 ,0 },
++ { "vrs", OP8(0x00LL), MASK_VRS_RVRDU, INSTR_VRS_RVRDU, 3, 9 ,0 },
++ { "vrr", OP8(0x00LL), MASK_VRR_VVV0UUU, INSTR_VRR_VVV0UUU, 3, 9 ,0 },
++ { "vsi", OP8(0x00LL), MASK_VSI_URDV, INSTR_VSI_URDV, 3, 10 ,0 },
+ };
+
+ const int s390_num_opformats =
+diff -rup binutils.orig/opcodes/s390-opc.txt binutils-2.27/opcodes/s390-opc.txt
+--- binutils.orig/opcodes/s390-opc.txt 2017-03-24 14:50:54.851778922 +0000
++++ binutils-2.27/opcodes/s390-opc.txt 2017-03-24 14:54:05.066330541 +0000
+@@ -630,7 +630,7 @@ eb0000000051 tmy SIY_URD "test under mas
+ # 'old' instructions extended to long displacement
+ # these instructions are entered into the opcode table twice.
+ e30000000003 lrag RXY_RRRD "load real address with long offset 64" z990 zarch
+-e30000000004 lg RXY_RRRD " load 64" z990 zarch
++e30000000004 lg RXY_RRRD "load 64" z990 zarch
+ e30000000008 ag RXY_RRRD "add with long offset 64" z990 zarch
+ e30000000009 sg RXY_RRRD "subtract with long offset 64" z990 zarch
+ e3000000000a alg RXY_RRRD "add logical with long offset 64" z990 zarch
+@@ -1584,27 +1584,27 @@ e7000230008a vstrczfs VRR_VVVU0VB3 "vect
+
+ # Chapter 24
+ e700000000e3 vfa VRR_VVV0UU "vector fp add" z13 zarch vx
+-e700000030e3 vfadb VRR_VVV "vector fp add" z13 zarch vx
+-e700000830e3 wfadb VRR_VVV "vector fp add" z13 zarch vx
++e700000030e3 vfadb VRR_VVV "vector fp add long" z13 zarch vx
++e700000830e3 wfadb VRR_VVV "vector fp add long" z13 zarch vx
+ e700000000cb wfc VRR_VV0UU2 "vector fp compare scalar" z13 zarch vx
+-e700000030cb wfcdb VRR_VV "vector fp compare scalar" z13 zarch vx
++e700000030cb wfcdb VRR_VV "vector fp compare scalar long" z13 zarch vx
+ e700000000ca wfk VRR_VV0UU2 "vector fp compare and signal scalar" z13 zarch vx
+-e700000030ca wfkdb VRR_VV "vector fp compare and signal scalar" z13 zarch vx
++e700000030ca wfkdb VRR_VV "vector fp compare and signal scalar long" z13 zarch vx
+ e700000000e8 vfce VRR_VVV0UUU "vector fp compare equal" z13 zarch vx
+-e700000030e8 vfcedb VRR_VVV "vector fp compare equal" z13 zarch vx
+-e700001030e8 vfcedbs VRR_VVV "vector fp compare equal" z13 zarch vx
+-e700000830e8 wfcedb VRR_VVV "vector fp compare equal" z13 zarch vx
+-e700001830e8 wfcedbs VRR_VVV "vector fp compare equal" z13 zarch vx
++e700000030e8 vfcedb VRR_VVV "vector fp compare equal long" z13 zarch vx
++e700001030e8 vfcedbs VRR_VVV "vector fp compare equal long" z13 zarch vx
++e700000830e8 wfcedb VRR_VVV "vector fp compare equal long" z13 zarch vx
++e700001830e8 wfcedbs VRR_VVV "vector fp compare equal long" z13 zarch vx
+ e700000000eb vfch VRR_VVV0UUU "vector fp compare high" z13 zarch vx
+-e700000030eb vfchdb VRR_VVV "vector fp compare high" z13 zarch vx
+-e700001030eb vfchdbs VRR_VVV "vector fp compare high" z13 zarch vx
+-e700000830eb wfchdb VRR_VVV "vector fp compare high" z13 zarch vx
+-e700001830eb wfchdbs VRR_VVV "vector fp compare high" z13 zarch vx
++e700000030eb vfchdb VRR_VVV "vector fp compare high long" z13 zarch vx
++e700001030eb vfchdbs VRR_VVV "vector fp compare high long" z13 zarch vx
++e700000830eb wfchdb VRR_VVV "vector fp compare high long" z13 zarch vx
++e700001830eb wfchdbs VRR_VVV "vector fp compare high long" z13 zarch vx
+ e700000000ea vfche VRR_VVV0UUU "vector fp compare high or equal" z13 zarch vx
+-e700000030ea vfchedb VRR_VVV "vector fp compare high or equal" z13 zarch vx
+-e700001030ea vfchedbs VRR_VVV "vector fp compare high or equal" z13 zarch vx
+-e700000830ea wfchedb VRR_VVV "vector fp compare high or equal" z13 zarch vx
+-e700001830ea wfchedbs VRR_VVV "vector fp compare high or equal" z13 zarch vx
++e700000030ea vfchedb VRR_VVV "vector fp compare high or equal long" z13 zarch vx
++e700001030ea vfchedbs VRR_VVV "vector fp compare high or equal long" z13 zarch vx
++e700000830ea wfchedb VRR_VVV "vector fp compare high or equal long" z13 zarch vx
++e700001830ea wfchedbs VRR_VVV "vector fp compare high or equal long" z13 zarch vx
+ e700000000c3 vcdg VRR_VV0UUU "vector fp convert from fixed 64 bit" z13 zarch vx
+ e700000030c3 vcdgb VRR_VV0UU "vector fp convert from fixed 64 bit" z13 zarch vx
+ e700000830c3 wcdgb VRR_VV0UU8 "vector fp convert from fixed 64 bit" z13 zarch vx
+@@ -1618,41 +1618,41 @@ e700000000c0 vclgd VRR_VV0UUU "vector fp
+ e700000030c0 vclgdb VRR_VV0UU "vector fp convert to logical 64 bit" z13 zarch vx
+ e700000830c0 wclgdb VRR_VV0UU8 "vector fp convert to logical 64 bit" z13 zarch vx
+ e700000000e5 vfd VRR_VVV0UU "vector fp divide" z13 zarch vx
+-e700000030e5 vfddb VRR_VVV "vector fp divide" z13 zarch vx
+-e700000830e5 wfddb VRR_VVV "vector fp divide" z13 zarch vx
++e700000030e5 vfddb VRR_VVV "vector fp divide long" z13 zarch vx
++e700000830e5 wfddb VRR_VVV "vector fp divide long" z13 zarch vx
+ e700000000c7 vfi VRR_VV0UUU "vector load fp integer" z13 zarch vx
+-e700000030c7 vfidb VRR_VV0UU "vector load fp integer" z13 zarch vx
+-e700000830c7 wfidb VRR_VV0UU8 "vector load fp integer" z13 zarch vx
++e700000030c7 vfidb VRR_VV0UU "vector load fp integer long" z13 zarch vx
++e700000830c7 wfidb VRR_VV0UU8 "vector load fp integer long" z13 zarch vx
+ e700000000c4 vlde VRR_VV0UU2 "vector fp load lengthened" z13 zarch vx
+-e700000020c4 vldeb VRR_VV "vector fp load lengthened" z13 zarch vx
+-e700000820c4 wldeb VRR_VV "vector fp load lengthened" z13 zarch vx
++e700000020c4 vldeb VRR_VV "vector fp load lengthened short to long" z13 zarch vx
++e700000820c4 wldeb VRR_VV "vector fp load lengthened short to long" z13 zarch vx
+ e700000000c5 vled VRR_VV0UUU "vector fp load rounded" z13 zarch vx
+-e700000030c5 vledb VRR_VV0UU "vector fp load rounded" z13 zarch vx
+-e700000830c5 wledb VRR_VV0UU8 "vector fp load rounded" z13 zarch vx
++e700000030c5 vledb VRR_VV0UU "vector fp load rounded long to short" z13 zarch vx
++e700000830c5 wledb VRR_VV0UU8 "vector fp load rounded long to short" z13 zarch vx
+ e700000000e7 vfm VRR_VVV0UU "vector fp multiply" z13 zarch vx
+-e700000030e7 vfmdb VRR_VVV "vector fp multiply" z13 zarch vx
+-e700000830e7 wfmdb VRR_VVV "vector fp multiply" z13 zarch vx
++e700000030e7 vfmdb VRR_VVV "vector fp multiply long" z13 zarch vx
++e700000830e7 wfmdb VRR_VVV "vector fp multiply long" z13 zarch vx
+ e7000000008f vfma VRR_VVVU0UV "vector fp multiply and add" z13 zarch vx
+-e7000300008f vfmadb VRR_VVVV "vector fp multiply and add" z13 zarch vx
+-e7000308008f wfmadb VRR_VVVV "vector fp multiply and add" z13 zarch vx
++e7000300008f vfmadb VRR_VVVV "vector fp multiply and add long" z13 zarch vx
++e7000308008f wfmadb VRR_VVVV "vector fp multiply and add long" z13 zarch vx
+ e7000000008e vfms VRR_VVVU0UV "vector fp multiply and subtract" z13 zarch vx
+-e7000300008e vfmsdb VRR_VVVV "vector fp multiply and subtract" z13 zarch vx
+-e7000308008e wfmsdb VRR_VVVV "vector fp multiply and subtract" z13 zarch vx
++e7000300008e vfmsdb VRR_VVVV "vector fp multiply and subtract long" z13 zarch vx
++e7000308008e wfmsdb VRR_VVVV "vector fp multiply and subtract long" z13 zarch vx
+ e700000000cc vfpso VRR_VV0UUU "vector fp perform sign operation" z13 zarch vx
+-e700000030cc vfpsodb VRR_VV0U2 "vector fp perform sign operation" z13 zarch vx
+-e700000830cc wfpsodb VRR_VV0U2 "vector fp perform sign operation" z13 zarch vx
+-e700000030cc vflcdb VRR_VV "vector fp perform sign operation" z13 zarch vx
+-e700000830cc wflcdb VRR_VV "vector fp perform sign operation" z13 zarch vx
+-e700001030cc vflndb VRR_VV "vector fp perform sign operation" z13 zarch vx
+-e700001830cc wflndb VRR_VV "vector fp perform sign operation" z13 zarch vx
+-e700002030cc vflpdb VRR_VV "vector fp perform sign operation" z13 zarch vx
+-e700002830cc wflpdb VRR_VV "vector fp perform sign operation" z13 zarch vx
++e700000030cc vfpsodb VRR_VV0U2 "vector fp perform sign operation long" z13 zarch vx
++e700000830cc wfpsodb VRR_VV0U2 "vector fp perform sign operation long" z13 zarch vx
++e700000030cc vflcdb VRR_VV "vector fp perform sign operation long" z13 zarch vx
++e700000830cc wflcdb VRR_VV "vector fp perform sign operation long" z13 zarch vx
++e700001030cc vflndb VRR_VV "vector fp perform sign operation long" z13 zarch vx
++e700001830cc wflndb VRR_VV "vector fp perform sign operation long" z13 zarch vx
++e700002030cc vflpdb VRR_VV "vector fp perform sign operation long" z13 zarch vx
++e700002830cc wflpdb VRR_VV "vector fp perform sign operation long" z13 zarch vx
+ e700000000ce vfsq VRR_VV0UU2 "vector fp square root" z13 zarch vx
+-e700000030ce vfsqdb VRR_VV "vector fp square root" z13 zarch vx
+-e700000830ce wfsqdb VRR_VV "vector fp square root" z13 zarch vx
++e700000030ce vfsqdb VRR_VV "vector fp square root long" z13 zarch vx
++e700000830ce wfsqdb VRR_VV "vector fp square root long" z13 zarch vx
+ e700000000e2 vfs VRR_VVV0UU "vector fp subtract" z13 zarch vx
+-e700000030e2 vfsdb VRR_VVV "vector fp subtract" z13 zarch vx
+-e700000830e2 wfsdb VRR_VVV "vector fp subtract" z13 zarch vx
++e700000030e2 vfsdb VRR_VVV "vector fp subtract long" z13 zarch vx
++e700000830e2 wfsdb VRR_VVV "vector fp subtract long" z13 zarch vx
+ e7000000004a vftci VRI_VVUUU "vector fp test data class immediate" z13 zarch vx
+ e7000000304a vftcidb VRI_VVU2 "vector fp test data class immediate" z13 zarch vx
+ e7000008304a wftcidb VRI_VVU2 "vector fp test data class immediate" z13 zarch vx
+@@ -1679,3 +1679,200 @@ e3000000003a llzrgf RXY_RRRD "load logic
+ e3000000003b lzrf RXY_RRRD "load and zero rightmost byte 32->32" z13 zarch
+ e3000000002a lzrg RXY_RRRD "load and zero rightmost byte 64->64" z13 zarch
+ b93c ppno RRE_RR "perform pseudorandom number operation" z13 zarch
++
++# arch12 instructions
++
++# Vector Enhancements Facility 1
++
++e70000000085 vbperm VRR_VVV "vector bit permute" arch12 zarch
++e70000006004 vllezlf VRX_VRRD "vector load logical word element and zero - left aligned" arch12 zarch vx2
++e700000000b8 vmsl VRR_VVVUU0V "vector multiply sum logical" arch12 zarch vx2
++e700030000b8 vmslg VRR_VVVU0VB "vector multiply sum logical double word" arch12 zarch vx2
++e7000000006c vnx VRR_VVV "vector not exclusive or" arch12 zarch vx2
++e7000000006e vnn VRR_VVV "vector nand" arch12 zarch
++e7000000006f voc VRR_VVV "vector or with complement" arch12 zarch vx2
++e70000000050 vpopctb VRR_VV "vector population count byte" arch12 zarch vx2
++e70000001050 vpopcth VRR_VV "vector population count halfword" arch12 zarch vx2
++e70000002050 vpopctf VRR_VV "vector population count word" arch12 zarch vx2
++e70000003050 vpopctg VRR_VV "vector population count double word" arch12 zarch vx2
++e700000020e3 vfasb VRR_VVV "vector fp add short" arch12 zarch vx2
++e700000820e3 wfasb VRR_VVV "scalar vector fp add scalar short" arch12 zarch vx2
++e700000840e3 wfaxb VRR_VVV "scalar vector fp add scalar extended" arch12 zarch vx2
++e700000020cb wfcsb VRR_VV "scalar vector fp compare scalar short" arch12 zarch vx2
++e700000040cb wfcxb VRR_VV "scalar vector fp compare scalar extended" arch12 zarch vx2
++e700000020ca wfksb VRR_VV "scalar vector fp compare and signal scalar short" arch12 zarch vx2
++e700000040ca wfkxb VRR_VV "scalar vector fp compare and signal scalar extended" arch12 zarch vx2
++
++e700000020e8 vfcesb VRR_VVV "vector fp compare equal short" arch12 zarch vx2
++e700001020e8 vfcesbs VRR_VVV "vector fp compare equal short" arch12 zarch vx2
++e700000820e8 wfcesb VRR_VVV "scalar vector fp compare equal scalar short" arch12 zarch vx2
++e700001820e8 wfcesbs VRR_VVV "scalar fp compare equal scalar short" arch12 zarch vx2
++e700000840e8 wfcexb VRR_VVV "scalar vector fp compare equal scalar extended" arch12 zarch vx2
++e700001840e8 wfcexbs VRR_VVV "scalar vector fp compare equal scalar extended" arch12 zarch vx2
++
++e700000420e8 vfkesb VRR_VVV "vector fp compare and signal equal short" arch12 zarch vx2
++e700001420e8 vfkesbs VRR_VVV "vector fp compare and signal equal short" arch12 zarch vx2
++e700000c20e8 wfkesb VRR_VVV "scalar vector fp compare and signal equal scalar short" arch12 zarch vx2
++e700001c20e8 wfkesbs VRR_VVV "scalar fp compare and signal equal scalar short" arch12 zarch vx2
++e700000430e8 vfkedb VRR_VVV "vector fp compare and signal equal long" arch12 zarch vx
++e700001430e8 vfkedbs VRR_VVV "vector fp compare and signal equal long" arch12 zarch vx
++e700000c30e8 wfkedb VRR_VVV "vector fp compare and signal equal long" arch12 zarch vx
++e700001c30e8 wfkedbs VRR_VVV "vector fp compare and signal equal long" arch12 zarch vx
++e700000c40e8 wfkexb VRR_VVV "scalar vector fp compare and signal equal scalar extended" arch12 zarch vx2
++e700001c40e8 wfkexbs VRR_VVV "scalar vector fp compare and signal equal scalar extended" arch12 zarch vx2
++
++e700000020eb vfchsb VRR_VVV "vector fp compare high short" arch12 zarch vx2
++e700001020eb vfchsbs VRR_VVV "vector fp compare high short" arch12 zarch vx2
++e700000820eb wfchsb VRR_VVV "scalar vector fp compare high scalar short" arch12 zarch vx2
++e700001820eb wfchsbs VRR_VVV "scalar vector fp compare high scalar short" arch12 zarch vx2
++e700000840eb wfchxb VRR_VVV "scalar vector fp compare high scalar extended" arch12 zarch vx2
++e700001840eb wfchxbs VRR_VVV "scalar vector fp compare high scalar extended" arch12 zarch vx2
++
++e700000420eb vfkhsb VRR_VVV "vector fp compare and signal high short" arch12 zarch vx2
++e700001420eb vfkhsbs VRR_VVV "vector fp compare and signal high short" arch12 zarch vx2
++e700000c20eb wfkhsb VRR_VVV "scalar vector fp compare and signal high scalar short" arch12 zarch vx2
++e700001c20eb wfkhsbs VRR_VVV "scalar vector fp compare and signal high scalar short" arch12 zarch vx2
++e700000430eb vfkhdb VRR_VVV "vector fp compare and signal high long" arch12 zarch vx
++e700001430eb vfkhdbs VRR_VVV "vector fp compare and signal high long" arch12 zarch vx
++e700000c30eb wfkhdb VRR_VVV "vector fp compare and signal high long" arch12 zarch vx
++e700001c30eb wfkhdbs VRR_VVV "vector fp compare and signal high long" arch12 zarch vx
++e700000c40eb wfkhxb VRR_VVV "scalar vector fp compare and signal high scalar extended" arch12 zarch vx2
++e700001c40eb wfkhxbs VRR_VVV "scalar vector fp compare and signal high scalar extended" arch12 zarch vx2
++
++e700000020ea vfchesb VRR_VVV "vector fp compare high or equal short" arch12 zarch vx2
++e700001020ea vfchesbs VRR_VVV "vector fp compare high or equal short" arch12 zarch vx2
++e700000820ea wfchesb VRR_VVV "scalar vector fp compare high or equal scalar short" arch12 zarch vx2
++e700001820ea wfchesbs VRR_VVV "scalar vector fp compare high or equal scalar short" arch12 zarch vx2
++e700000840ea wfchexb VRR_VVV "scalar vector fp compare high or equal scalar extended" arch12 zarch vx2
++e700001840ea wfchexbs VRR_VVV "scalar vector fp compare high or equal scalar extended" arch12 zarch vx2
++
++e700000420ea vfkhesb VRR_VVV "vector fp compare and signal high or equal short" arch12 zarch vx2
++e700001420ea vfkhesbs VRR_VVV "vector fp compare and signal high or equal short" arch12 zarch vx2
++e700000c20ea wfkhesb VRR_VVV "scalar vector fp compare and signal high or equal scalar short" arch12 zarch vx2
++e700001c20ea wfkhesbs VRR_VVV "scalar vector fp compare and signal high or equal scalar short" arch12 zarch vx2
++e700000430ea vfkhedb VRR_VVV "vector fp compare and signal high or equal long" arch12 zarch vx
++e700001430ea vfkhedbs VRR_VVV "vector fp compare and signal high or equal long" arch12 zarch vx
++e700000c30ea wfkhedb VRR_VVV "vector fp compare and signal high or equal long" arch12 zarch vx
++e700001c30ea wfkhedbs VRR_VVV "vector fp compare and signal high or equal long" arch12 zarch vx
++e700000c40ea wfkhexb VRR_VVV "scalar vector fp compare and signal high or equal scalar extended" arch12 zarch vx2
++e700001c40ea wfkhexbs VRR_VVV "scalar vector fp compare and signal high or equal scalar extended" arch12 zarch vx2
++
++e700000020e5 vfdsb VRR_VVV "vector fp divide short" arch12 zarch vx2
++e700000820e5 wfdsb VRR_VVV "scalar vector fp divide scalar short" arch12 zarch vx2
++e700000840e5 wfdxb VRR_VVV "scalar vector fp divide scalar extended" arch12 zarch vx2
++e700000020c7 vfisb VRR_VV0UU "vector load fp integer short" arch12 zarch vx2
++e700000820c7 wfisb VRR_VV0UU8 "scalar vector load fp integer scalar short" arch12 zarch vx2
++e700000840c7 wfixb VRR_VV0UU8 "scalar vector load fp integer scalar extended" arch12 zarch vx2
++e700000000c4 vfll VRR_VV0UU2 "vector fp load lengthened" arch12 zarch vx2
++e700000020c4 vflls VRR_VV "vector fp load lengthened" arch12 zarch vx2
++e700000820c4 wflls VRR_VV "scalar vector fp load lengthened short" arch12 zarch vx2
++e700000830c4 wflld VRR_VV "scalar vector fp load lengthened long" arch12 zarch vx2
++e700000000c5 vflr VRR_VV0UUU "vector fp load rounded" arch12 zarch vx2
++e700000030c5 vflrd VRR_VV0UU "vector fp load rounded long" arch12 zarch vx2
++e700000830c5 wflrd VRR_VV0UU8 "scalar vector fp load rounded long" arch12 zarch vx2
++e700000840c5 wflrx VRR_VV0UU8 "scalar vector fp load rounded extended" arch12 zarch vx2
++e700000000ef vfmax VRR_VVV0UUU "vector fp maximum" arch12 zarch vx2
++e700000020ef vfmaxsb VRR_VVV0U0 "vector fp maximum short" arch12 zarch vx2
++e700000030ef vfmaxdb VRR_VVV0U0 "vector fp maximum long" arch12 zarch vx2
++e700000820ef wfmaxsb VRR_VVV0U0 "scalar fp maximum scalar short" arch12 zarch vx2
++e700000830ef wfmaxdb VRR_VVV0U0 "scalar fp maximum scalar long" arch12 zarch vx2
++e700000840ef wfmaxxb VRR_VVV0U0 "scalar fp maximum scalar extended" arch12 zarch vx2
++e700000000ee vfmin VRR_VVV0UUU "vector fp minimum" arch12 zarch vx2
++e700000020ee vfminsb VRR_VVV0U0 "vector fp minimum short" arch12 zarch vx2
++e700000030ee vfmindb VRR_VVV0U0 "vector fp minimum long" arch12 zarch vx2
++e700000820ee wfminsb VRR_VVV0U0 "scalar fp minimum scalar short" arch12 zarch vx2
++e700000830ee wfmindb VRR_VVV0U0 "scalar fp minimum scalar long" arch12 zarch vx2
++e700000840ee wfminxb VRR_VVV0U0 "scalar fp minimum scalar extended" arch12 zarch vx2
++e700000020e7 vfmsb VRR_VVV "vector fp multiply short" arch12 zarch vx2
++e700000820e7 wfmsb VRR_VVV "scalar vector fp multiply scalar short" arch12 zarch vx2
++e700000840e7 wfmxb VRR_VVV "scalar vector fp multiply scalar extended" arch12 zarch vx2
++e7000200008f vfmasb VRR_VVVV "vector fp multiply and add short" arch12 zarch vx2
++e7000208008f wfmasb VRR_VVVV "scalar vector fp multiply and add scalar short" arch12 zarch vx2
++e7000408008f wfmaxb VRR_VVVV "scalar vector fp multiply and add scalar extended" arch12 zarch vx2
++e7000200008e vfmssb VRR_VVVV "vector fp multiply and subtract short" arch12 zarch vx2
++e7000208008e wfmssb VRR_VVVV "scalar vector fp multiply and subtract scalar short" arch12 zarch vx2
++e7000408008e wfmsxb VRR_VVVV "scalar vector fp multiply and subtract scalar extended" arch12 zarch vx2
++e7000000009f vfnma VRR_VVVU0UV "vector fp negative multiply and add" arch12 zarch vx2
++e7000200009f vfnmasb VRR_VVVV "vector fp negative multiply and add short" arch12 zarch vx2
++e7000208009f wfnmasb VRR_VVVV "scalar vector fp negative multiply and add scalar short" arch12 zarch vx2
++e7000300009f vfnmadb VRR_VVVV "vector fp negative multiply and add long" arch12 zarch vx2
++e7000308009f wfnmadb VRR_VVVV "scalar vector fp negative multiply and add scalar long" arch12 zarch vx2
++e7000408009f wfnmaxb VRR_VVVV "scalar vector fp negative multiply and add scalar extended" arch12 zarch vx2
++e7000000009e vfnms VRR_VVVU0UV "vector fp negative multiply and subtract" arch12 zarch vx2
++e7000200009e vfnmssb VRR_VVVV "vector fp negative multiply and subtract short" arch12 zarch vx2
++e7000208009e wfnmssb VRR_VVVV "scalar vector fp negative multiply and subtract scalar short" arch12 zarch vx2
++e7000300009e vfnmsdb VRR_VVVV "vector fp negative multiply and subtract long" arch12 zarch vx2
++e7000308009e wfnmsdb VRR_VVVV "scalar vector fp negative multiply and subtract scalar long" arch12 zarch vx2
++e7000408009e wfnmsxb VRR_VVVV "scalar vector fp negative multiply and subtract scalar extended" arch12 zarch vx2
++e700000020cc vfpsosb VRR_VV0U2 "vector fp perform sign operation short" arch12 zarch vx2
++e700000820cc wfpsosb VRR_VV0U2 "scalar vector fp perform sign operation scalar short" arch12 zarch vx2
++e700000020cc vflcsb VRR_VV "vector fp perform sign operation short" arch12 zarch vx2
++e700000820cc wflcsb VRR_VV "scalar vector fp perform sign operation scalar short" arch12 zarch vx2
++e700001020cc vflnsb VRR_VV "vector fp perform sign operation short" arch12 zarch vx2
++e700001820cc wflnsb VRR_VV "scalar vector fp perform sign operation scalar short" arch12 zarch vx2
++e700002020cc vflpsb VRR_VV "vector fp perform sign operation short" arch12 zarch vx2
++e700002820cc wflpsb VRR_VV "scalar vector fp perform sign operation scalar short" arch12 zarch vx2
++e700000840cc wfpsoxb VRR_VV0U2 "scalar vector fp perform sign operation scalar extended" arch12 zarch vx2
++e700000840cc wflcxb VRR_VV "scalar vector fp perform sign operation scalar extended" arch12 zarch vx2
++e700001840cc wflnxb VRR_VV "scalar vector fp perform sign operation scalar extended" arch12 zarch vx2
++e700002840cc wflpxb VRR_VV "scalar vector fp perform sign operation scalar extended" arch12 zarch vx2
++e700000020ce vfsqsb VRR_VV "vector fp square root short" arch12 zarch vx2
++e700000820ce wfsqsb VRR_VV "scalar vector fp square root scalar short" arch12 zarch vx2
++e700000840ce wfsqxb VRR_VV "scalar vector fp square root scalar extended" arch12 zarch vx2
++e700000020e2 vfssb VRR_VVV "vector fp subtract short" arch12 zarch vx2
++e700000820e2 wfssb VRR_VVV "scalar vector fp subtract scalar short" arch12 zarch vx2
++e700000840e2 wfsxb VRR_VVV "scalar vector fp subtract scalar extended" arch12 zarch vx2
++e7000000204a vftcisb VRI_VVU2 "vector fp test data class immediate short" arch12 zarch vx2
++e7000008204a wftcisb VRI_VVU2 "scalar vector fp test data class immediate scalar short" arch12 zarch vx2
++e7000008404a wftcixb VRI_VVU2 "scalar vector fp test data class immediate scalar extended" arch12 zarch vx2
++
++# Miscellaneous Instruction Extensions Facility 2
++
++e30000000038 agh RXY_RRRD "add halfword to 64 bit value" arch12 zarch
++e30000000047 bic RXY_URRD "branch indirect on condition" arch12 zarch
++e3f000000047 bi RXY_0RRD "unconditional indirect branch" arch12 zarch
++e30000000047 bi*8 RXY_0RRD "branch indirect on condition" arch12 zarch
++b9ec mgrk RRF_R0RR2 "multiply 64x64reg -> 128" arch12 zarch
++e30000000084 mg RXY_RRRD "multiply 64x64mem -> 128" arch12 zarch
++e3000000003c mgh RXY_RRRD "multiply halfword 64x16mem -> 64" arch12 zarch
++b9fd msrkc RRF_R0RR2 "multiply single 32x32 -> 32" arch12 zarch
++b9ed msgrkc RRF_R0RR2 "multiply single 64x64 -> 64" arch12 zarch
++e30000000053 msc RXY_RRRD "multiply single 32x32mem -> 32" arch12 zarch
++e30000000083 msgc RXY_RRRD "multiply single 64x64mem -> 64" arch12 zarch
++e30000000039 sgh RXY_RRRD "subtract halfword from 64 bit value" arch12 zarch
++
++# Vector packed decimal facility
++
++e60000000037 vlrlr VRS_RRDV "vector load rightmost with length" arch12 zarch vx2
++e60000000035 vlrl VSI_URDV "vector load rightmost with immediate length" arch12 zarch vx2
++e6000000003f vstrlr VRS_RRDV "vector store rightmost with length" arch12 zarch vx2
++e6000000003d vstrl VSI_URDV "vector store rightmost with immediate length" arch12 zarch vx2
++e60000000071 vap VRI_VVV0UU2 "vector add decimal" arch12 zarch vx2
++e60000000077 vcp VRR_0VV0U "vector compare decimal" arch12 zarch vx2
++e60000000050 vcvb VRR_RV0U "vector convert to binary 32 bit" arch12 zarch vx2
++e60000000052 vcvbg VRR_RV0U "vector convert to binary 64 bit" arch12 zarch vx2
++e60000000058 vcvd VRI_VR0UU "vector convert to decimal 32 bit" arch12 zarch vx2
++e6000000005a vcvdg VRI_VR0UU "vector convert to decimal 64 bit" arch12 zarch vx2
++e6000000007a vdp VRI_VVV0UU2 "vector divide decimal" arch12 zarch vx2
++e60000000049 vlip VRI_V0UU2 "vector load immediate decimal" arch12 zarch vx2
++e60000000078 vmp VRI_VVV0UU2 "vector multiply decimal" arch12 zarch vx2
++e60000000079 vmsp VRI_VVV0UU2 "vector multiply and shift decimal" arch12 zarch vx2
++e60000000034 vpkz VSI_URDV "vector pack zoned" arch12 zarch vx2
++e6000000005b vpsop VRI_VVUUU2 "vector perform sign operation decimal" arch12 zarch vx2
++e6000000007b vrp VRI_VVV0UU2 "vector remainder decimal" arch12 zarch vx2
++e6000000007e vsdp VRI_VVV0UU2 "vector shift and divide decimal" arch12 zarch vx2
++e60000000059 vsrp VRI_VVUUU2 "vector shift and round decimal" arch12 zarch vx2
++e60000000073 vsp VRI_VVV0UU2 "vector subtract decimal" arch12 zarch vx2
++e6000000005f vtp VRR_0V "vector test decimal" arch12 zarch vx2
++e6000000003c vupkz VSI_URDV "vector unpack zoned" arch12 zarch vx2
++
++# Guarded storage facility
++
++e3000000004c lgg RXY_RRRD "load guarded 64 bit" arch12 zarch
++e30000000048 llgfsg RXY_RRRD "load logical and shift guarded 64 bit" arch12 zarch
++e3000000004d lgsc RXY_RRRD "load guarded storage controls" arch12 zarch
++e30000000049 stgsc RXY_RRRD "store guarded storage controls" arch12 zarch
++
++# Message-Security-Assist Extension 8
++
++b929 kma RRF_R0RR "cipher message with galois counter mode" arch12 zarch
+
diff --git a/SOURCES/binutils-2.27-s390x-check-for-NULL-pointers.patch b/SOURCES/binutils-2.27-s390x-check-for-NULL-pointers.patch
new file mode 100644
index 0000000..bcc7d22
--- /dev/null
+++ b/SOURCES/binutils-2.27-s390x-check-for-NULL-pointers.patch
@@ -0,0 +1,43 @@
+--- binutils.orig/bfd/elf64-s390.c 2017-09-06 09:03:23.142216202 +0100
++++ binutils-2.27/bfd/elf64-s390.c 2017-09-06 09:11:05.209080947 +0100
+@@ -3895,8 +3895,13 @@ elf_s390_additional_program_headers (bfd
+ {
+ struct elf_s390_link_hash_table *htab;
+
+- htab = elf_s390_hash_table (info);
+- return htab->params->pgste;
++ if (info)
++ {
++ htab = elf_s390_hash_table (info);
++ if (htab)
++ return htab->params->pgste;
++ }
++ return 0;
+ }
+
+
+@@ -3909,6 +3914,9 @@ elf_s390_modify_segment_map (bfd *abfd A
+ struct elf_s390_link_hash_table *htab;
+ struct elf_segment_map *m, *pm = NULL;
+
++ if (!abfd || !info)
++ return TRUE;
++
+ htab = elf_s390_hash_table (info);
+ if (!htab->params->pgste)
+ return TRUE;
+@@ -3944,8 +3952,12 @@ bfd_elf_s390_set_options (struct bfd_lin
+ {
+ struct elf_s390_link_hash_table *htab;
+
+- htab = elf_s390_hash_table (info);
+- htab->params = params;
++ if (info)
++ {
++ htab = elf_s390_hash_table (info);
++ if (htab)
++ htab->params = params;
++ }
+
+ return TRUE;
+ }
diff --git a/SOURCES/binutils-2.27-s390x-complain-missing-fPIC.patch b/SOURCES/binutils-2.27-s390x-complain-missing-fPIC.patch
new file mode 100644
index 0000000..373391b
--- /dev/null
+++ b/SOURCES/binutils-2.27-s390x-complain-missing-fPIC.patch
@@ -0,0 +1,22 @@
+--- binutils.orig/bfd/elf64-s390.c 2017-08-11 11:09:23.264667227 +0000
++++ binutils-2.27/bfd/elf64-s390.c 2017-08-11 11:15:07.510029088 +0000
+@@ -2745,6 +2745,19 @@ elf_s390_relocate_section (bfd *output_b
+ case R_390_PC32:
+ case R_390_PC32DBL:
+ case R_390_PC64:
++ if (h != NULL
++ && bfd_link_pie (info)
++ && !h->def_regular)
++ {
++ _bfd_error_handler (_("%B: `%s' non-PLT reloc for symbol defined "
++ "in shared library and accessed "
++ "from executable "
++ "(rebuild file with -fPIC ?)"),
++ input_bfd, h->root.root.string);
++ bfd_set_error (bfd_error_bad_value);
++ return FALSE;
++ }
++
+ /* The target of these relocs are instruction operands
+ residing in read-only sections. We cannot emit a runtime
+ reloc for it. */
diff --git a/SOURCES/binutils-2.27-skip-ld-aarch64-ifunc-exec-tests.patch b/SOURCES/binutils-2.27-skip-ld-aarch64-ifunc-exec-tests.patch
new file mode 100644
index 0000000..dfa6ee1
--- /dev/null
+++ b/SOURCES/binutils-2.27-skip-ld-aarch64-ifunc-exec-tests.patch
@@ -0,0 +1,18 @@
+Only in binutils.orig/ld/testsuite/ld-ifunc: .#ifunc.exp
+diff -rup binutils.orig/ld/testsuite/ld-ifunc/ifunc.exp binutils-2.27/ld/testsuite/ld-ifunc/ifunc.exp
+--- binutils.orig/ld/testsuite/ld-ifunc/ifunc.exp 2017-02-21 15:00:21.802036746 +0000
++++ binutils-2.27/ld/testsuite/ld-ifunc/ifunc.exp 2017-02-21 15:06:32.730980432 +0000
+@@ -531,6 +531,13 @@ run_cc_link_tests [list \
+ ] \
+ ]
+
++# IFUNC support for AArch64 is still experimental, and in particular
++# function resolution is not yet stable. So skip these tests for now.
++# NC Feb 2017.
++if {[istarget "aarch64-*-*"]} {
++ return
++}
++
+ run_ld_link_exec_tests [] [list \
+ [list \
+ "Run pr18808" \
diff --git a/SOURCES/binutils-2.27-skip-rp14918-test-for-arm.patch b/SOURCES/binutils-2.27-skip-rp14918-test-for-arm.patch
new file mode 100644
index 0000000..6c62b50
--- /dev/null
+++ b/SOURCES/binutils-2.27-skip-rp14918-test-for-arm.patch
@@ -0,0 +1,26 @@
+--- binutils-2.27.orig/ld/testsuite/ld-plugin/lto.exp 2016-09-20 14:11:51.866711051 +0100
++++ binutils-2.27/ld/testsuite/ld-plugin/lto.exp 2016-09-20 14:18:28.528223979 +0100
+@@ -287,11 +287,21 @@ set lto_link_elf_tests [list \
+ {dummy.c} {} "pr16746a.exe"] \
+ [list "PR ld/16746 (2)" \
+ "-O2 -flto -fuse-linker-plugin tmpdir/pr16746c.o tmpdir/pr16746a.o" "-O2 -flto" \
+- {dummy.c} {} "pr16746b.exe"] \
++ {dummy.c} {} "pr16746b.exe"] \
++]
++
++# PR 14918 checks that libgcc is not spuriously included in a shared link of
++# an empty program. The ARM crt1.o startup code however calls __libc_csu_init
++# in /usr/lib/libc_nonshared.a(elf-init.oS). This in turn needs
++# __aeabi_unwind_cpp_pr0@@GCC_3.5 which is provided by libgcc_s.so.1, so the
++# test fails. Hence this code to skip the test.
++if { ! [istarget "arm*-*-*"] } {
++ set lto_link_elf_tests [concat $lto_link_elf_tests [list \
+ [list "PR ld/14918" \
+ "-flto" "-flto" \
+ {pr14918.c} {{"readelf" {-d --wide} "pr14918.d"}} "pr14918.exe" "c"] \
+-]
++ ]]
++}
+
+ # Check final symbols in executables.
+ set lto_link_symbol_tests [list \
diff --git a/SOURCES/binutils-2.27-suppress-R_X86_64_GOTPCRELX.patch b/SOURCES/binutils-2.27-suppress-R_X86_64_GOTPCRELX.patch
new file mode 100644
index 0000000..39bb368
--- /dev/null
+++ b/SOURCES/binutils-2.27-suppress-R_X86_64_GOTPCRELX.patch
@@ -0,0 +1,1561 @@
+--- binutils.orig/gas/config/tc-i386.c 2017-10-25 12:52:19.977290474 +0100
++++ binutils-2.27/gas/config/tc-i386.c 2017-10-25 15:09:15.572415126 +0100
+@@ -10655,14 +10655,7 @@ i386_validate_fix (fixS *fixp)
+ {
+ if (!object_64bit)
+ abort ();
+-#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
+- if (fixp->fx_tcbit2)
+- fixp->fx_r_type = (fixp->fx_tcbit
+- ? BFD_RELOC_X86_64_REX_GOTPCRELX
+- : BFD_RELOC_X86_64_GOTPCRELX);
+- else
+-#endif
+- fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
++ fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
+ }
+ else
+ {
+@@ -10674,14 +10667,6 @@ i386_validate_fix (fixS *fixp)
+ fixp->fx_subsy = 0;
+ }
+ }
+-#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
+- else if (!object_64bit)
+- {
+- if (fixp->fx_r_type == BFD_RELOC_386_GOT32
+- && fixp->fx_tcbit2)
+- fixp->fx_r_type = BFD_RELOC_386_GOT32X;
+- }
+-#endif
+ }
+
+ arelent *
+diff -rup binutils.orig/gas/testsuite/gas/i386/got.d binutils-2.27/gas/testsuite/gas/i386/got.d
+--- binutils.orig/gas/testsuite/gas/i386/got.d 2017-10-25 12:52:20.045289685 +0100
++++ binutils-2.27/gas/testsuite/gas/i386/got.d 2017-10-25 15:19:02.458621604 +0100
+@@ -8,23 +8,23 @@ Disassembly of section .text:
+
+ 0+ <_start>:
+ [ ]*[a-f0-9]+: b8 00 00 00 00 mov \$0x0,%eax 1: R_386_GOT32 foo
+-[ ]*[a-f0-9]+: 8b 05 00 00 00 00 mov 0x0,%eax 7: R_386_GOT32X foo
+-[ ]*[a-f0-9]+: 8b 80 00 00 00 00 mov 0x0\(%eax\),%eax d: R_386_GOT32X foo
++[ ]*[a-f0-9]+: 8b 05 00 00 00 00 mov 0x0,%eax 7: R_386_GOT32 foo
++[ ]*[a-f0-9]+: 8b 80 00 00 00 00 mov 0x0\(%eax\),%eax d: R_386_GOT32 foo
+ [ ]*[a-f0-9]+: 05 00 00 00 00 add \$0x0,%eax 12: R_386_GOT32 foo
+-[ ]*[a-f0-9]+: 03 05 00 00 00 00 add 0x0,%eax 18: R_386_GOT32X foo
+-[ ]*[a-f0-9]+: 03 80 00 00 00 00 add 0x0\(%eax\),%eax 1e: R_386_GOT32X foo
+-[ ]*[a-f0-9]+: ff 15 00 00 00 00 call \*0x0 24: R_386_GOT32X foo
+-[ ]*[a-f0-9]+: ff 90 00 00 00 00 call \*0x0\(%eax\) 2a: R_386_GOT32X foo
+-[ ]*[a-f0-9]+: ff 25 00 00 00 00 jmp \*0x0 30: R_386_GOT32X foo
+-[ ]*[a-f0-9]+: ff a0 00 00 00 00 jmp \*0x0\(%eax\) 36: R_386_GOT32X foo
++[ ]*[a-f0-9]+: 03 05 00 00 00 00 add 0x0,%eax 18: R_386_GOT32 foo
++[ ]*[a-f0-9]+: 03 80 00 00 00 00 add 0x0\(%eax\),%eax 1e: R_386_GOT32 foo
++[ ]*[a-f0-9]+: ff 15 00 00 00 00 call \*0x0 24: R_386_GOT32 foo
++[ ]*[a-f0-9]+: ff 90 00 00 00 00 call \*0x0\(%eax\) 2a: R_386_GOT32 foo
++[ ]*[a-f0-9]+: ff 25 00 00 00 00 jmp \*0x0 30: R_386_GOT32 foo
++[ ]*[a-f0-9]+: ff a0 00 00 00 00 jmp \*0x0\(%eax\) 36: R_386_GOT32 foo
+ [ ]*[a-f0-9]+: b8 00 00 00 00 mov \$0x0,%eax 3b: R_386_GOT32 foo
+-[ ]*[a-f0-9]+: 8b 05 00 00 00 00 mov 0x0,%eax 41: R_386_GOT32X foo
+-[ ]*[a-f0-9]+: 8b 80 00 00 00 00 mov 0x0\(%eax\),%eax 47: R_386_GOT32X foo
++[ ]*[a-f0-9]+: 8b 05 00 00 00 00 mov 0x0,%eax 41: R_386_GOT32 foo
++[ ]*[a-f0-9]+: 8b 80 00 00 00 00 mov 0x0\(%eax\),%eax 47: R_386_GOT32 foo
+ [ ]*[a-f0-9]+: 05 00 00 00 00 add \$0x0,%eax 4c: R_386_GOT32 foo
+-[ ]*[a-f0-9]+: 03 05 00 00 00 00 add 0x0,%eax 52: R_386_GOT32X foo
+-[ ]*[a-f0-9]+: 03 80 00 00 00 00 add 0x0\(%eax\),%eax 58: R_386_GOT32X foo
+-[ ]*[a-f0-9]+: ff 90 00 00 00 00 call \*0x0\(%eax\) 5e: R_386_GOT32X foo
+-[ ]*[a-f0-9]+: ff 15 00 00 00 00 call \*0x0 64: R_386_GOT32X foo
+-[ ]*[a-f0-9]+: ff a0 00 00 00 00 jmp \*0x0\(%eax\) 6a: R_386_GOT32X foo
+-[ ]*[a-f0-9]+: ff 25 00 00 00 00 jmp \*0x0 70: R_386_GOT32X foo
++[ ]*[a-f0-9]+: 03 05 00 00 00 00 add 0x0,%eax 52: R_386_GOT32 foo
++[ ]*[a-f0-9]+: 03 80 00 00 00 00 add 0x0\(%eax\),%eax 58: R_386_GOT32 foo
++[ ]*[a-f0-9]+: ff 90 00 00 00 00 call \*0x0\(%eax\) 5e: R_386_GOT32 foo
++[ ]*[a-f0-9]+: ff 15 00 00 00 00 call \*0x0 64: R_386_GOT32 foo
++[ ]*[a-f0-9]+: ff a0 00 00 00 00 jmp \*0x0\(%eax\) 6a: R_386_GOT32 foo
++[ ]*[a-f0-9]+: ff 25 00 00 00 00 jmp \*0x0 70: R_386_GOT32 foo
+ #pass
+diff -rup binutils.orig/gas/testsuite/gas/i386/got-no-relax.d binutils-2.27/gas/testsuite/gas/i386/got-no-relax.d
+--- binutils.orig/gas/testsuite/gas/i386/got-no-relax.d 2017-10-25 12:52:20.045289685 +0100
++++ binutils-2.27/gas/testsuite/gas/i386/got-no-relax.d 2017-10-25 15:18:30.398991961 +0100
+@@ -9,23 +9,23 @@ Disassembly of section .text:
+
+ 0+ <_start>:
+ [ ]*[a-f0-9]+: b8 00 00 00 00 mov \$0x0,%eax 1: R_386_GOT32 foo
+-[ ]*[a-f0-9]+: 8b 05 00 00 00 00 mov 0x0,%eax 7: R_386_GOT32X foo
++[ ]*[a-f0-9]+: 8b 05 00 00 00 00 mov 0x0,%eax 7: R_386_GOT32 foo
+ [ ]*[a-f0-9]+: 8b 80 00 00 00 00 mov 0x0\(%eax\),%eax d: R_386_GOT32 foo
+ [ ]*[a-f0-9]+: 05 00 00 00 00 add \$0x0,%eax 12: R_386_GOT32 foo
+-[ ]*[a-f0-9]+: 03 05 00 00 00 00 add 0x0,%eax 18: R_386_GOT32X foo
++[ ]*[a-f0-9]+: 03 05 00 00 00 00 add 0x0,%eax 18: R_386_GOT32 foo
+ [ ]*[a-f0-9]+: 03 80 00 00 00 00 add 0x0\(%eax\),%eax 1e: R_386_GOT32 foo
+-[ ]*[a-f0-9]+: ff 15 00 00 00 00 call \*0x0 24: R_386_GOT32X foo
++[ ]*[a-f0-9]+: ff 15 00 00 00 00 call \*0x0 24: R_386_GOT32 foo
+ [ ]*[a-f0-9]+: ff 90 00 00 00 00 call \*0x0\(%eax\) 2a: R_386_GOT32 foo
+-[ ]*[a-f0-9]+: ff 25 00 00 00 00 jmp \*0x0 30: R_386_GOT32X foo
++[ ]*[a-f0-9]+: ff 25 00 00 00 00 jmp \*0x0 30: R_386_GOT32 foo
+ [ ]*[a-f0-9]+: ff a0 00 00 00 00 jmp \*0x0\(%eax\) 36: R_386_GOT32 foo
+ [ ]*[a-f0-9]+: b8 00 00 00 00 mov \$0x0,%eax 3b: R_386_GOT32 foo
+-[ ]*[a-f0-9]+: 8b 05 00 00 00 00 mov 0x0,%eax 41: R_386_GOT32X foo
++[ ]*[a-f0-9]+: 8b 05 00 00 00 00 mov 0x0,%eax 41: R_386_GOT32 foo
+ [ ]*[a-f0-9]+: 8b 80 00 00 00 00 mov 0x0\(%eax\),%eax 47: R_386_GOT32 foo
+ [ ]*[a-f0-9]+: 05 00 00 00 00 add \$0x0,%eax 4c: R_386_GOT32 foo
+-[ ]*[a-f0-9]+: 03 05 00 00 00 00 add 0x0,%eax 52: R_386_GOT32X foo
++[ ]*[a-f0-9]+: 03 05 00 00 00 00 add 0x0,%eax 52: R_386_GOT32 foo
+ [ ]*[a-f0-9]+: 03 80 00 00 00 00 add 0x0\(%eax\),%eax 58: R_386_GOT32 foo
+ [ ]*[a-f0-9]+: ff 90 00 00 00 00 call \*0x0\(%eax\) 5e: R_386_GOT32 foo
+-[ ]*[a-f0-9]+: ff 15 00 00 00 00 call \*0x0 64: R_386_GOT32X foo
++[ ]*[a-f0-9]+: ff 15 00 00 00 00 call \*0x0 64: R_386_GOT32 foo
+ [ ]*[a-f0-9]+: ff a0 00 00 00 00 jmp \*0x0\(%eax\) 6a: R_386_GOT32 foo
+-[ ]*[a-f0-9]+: ff 25 00 00 00 00 jmp \*0x0 70: R_386_GOT32X foo
++[ ]*[a-f0-9]+: ff 25 00 00 00 00 jmp \*0x0 70: R_386_GOT32 foo
+ #pass
+diff -rup binutils.orig/gas/testsuite/gas/i386/ilp32/x86-64-gotpcrel.d binutils-2.27/gas/testsuite/gas/i386/ilp32/x86-64-gotpcrel.d
+--- binutils.orig/gas/testsuite/gas/i386/ilp32/x86-64-gotpcrel.d 2017-10-25 12:52:20.047289662 +0100
++++ binutils-2.27/gas/testsuite/gas/i386/ilp32/x86-64-gotpcrel.d 2017-10-25 15:12:35.549099037 +0100
+@@ -2,6 +2,8 @@
+ #as: --x32 -mrelax-relocations=yes
+ #objdump: -dwr
+ #name: x86-64 (ILP32) gotpcrel
++#skip: *-*-*
++# SKIPed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed.
+
+ .*: +file format .*
+
+diff -rup binutils.orig/gas/testsuite/gas/i386/ilp32/x86-64-localpic.d binutils-2.27/gas/testsuite/gas/i386/ilp32/x86-64-localpic.d
+--- binutils.orig/gas/testsuite/gas/i386/ilp32/x86-64-localpic.d 2017-10-25 12:52:20.047289662 +0100
++++ binutils-2.27/gas/testsuite/gas/i386/ilp32/x86-64-localpic.d 2017-10-25 15:12:35.549099037 +0100
+@@ -2,6 +2,8 @@
+ #as: --x32 -mrelax-relocations=yes
+ #readelf: -rsW
+ #name: x86-64 (ILP32) local PIC
++#skip: *-*-*
++# SKIPed because generation of the R_X86_64_REX_GOTPCRELX reloc is currently suppressed.
+
+ Relocation section '.rela.text' at offset 0x[0-9a-f]+ contains 1 entries:
+ +Offset +Info +Type +Sym. Value +Symbol's Name \+ Addend
+diff -rup binutils.orig/gas/testsuite/gas/i386/localpic.d binutils-2.27/gas/testsuite/gas/i386/localpic.d
+--- binutils.orig/gas/testsuite/gas/i386/localpic.d 2017-10-25 12:52:20.049289639 +0100
++++ binutils-2.27/gas/testsuite/gas/i386/localpic.d 2017-10-25 15:18:13.799183724 +0100
+@@ -4,7 +4,7 @@
+
+ Relocation section '.rel.text' at offset 0x[0-9a-f]+ contains 1 entries:
+ Offset Info Type Sym.Value Sym. Name
+-[0-9a-f]+ +[0-9a-f]+ R_386_GOT32X +[0-9a-f]+ +foo
++[0-9a-f]+ +[0-9a-f]+ R_386_GOT32 +[0-9a-f]+ +foo
+ #...
+ +[0-9]+: +[0-9a-f]+ +[0-9a-f]+ +NOTYPE +LOCAL +DEFAULT +[0-9]+ +foo
+ #pass
+diff -rup binutils.orig/gas/testsuite/gas/i386/mixed-mode-reloc32.d binutils-2.27/gas/testsuite/gas/i386/mixed-mode-reloc32.d
+--- binutils.orig/gas/testsuite/gas/i386/mixed-mode-reloc32.d 2017-10-25 12:52:20.050289627 +0100
++++ binutils-2.27/gas/testsuite/gas/i386/mixed-mode-reloc32.d 2017-10-25 15:18:02.186317878 +0100
+@@ -7,9 +7,9 @@
+
+ RELOCATION RECORDS FOR \[.text\]:
+ OFFSET[ ]+TYPE[ ]+VALUE[ ]*
+-[0-9a-f]+[ ]+R_386_GOT32X[ ]+xtrn[ ]*
++[0-9a-f]+[ ]+R_386_GOT32[ ]+xtrn[ ]*
+ [0-9a-f]+[ ]+R_386_PLT32[ ]+xtrn[ ]*
+-[0-9a-f]+[ ]+R_386_GOT32X[ ]+xtrn[ ]*
++[0-9a-f]+[ ]+R_386_GOT32[ ]+xtrn[ ]*
+ [0-9a-f]+[ ]+R_386_PLT32[ ]+xtrn[ ]*
+-[0-9a-f]+[ ]+R_386_GOT32X[ ]+xtrn[ ]*
++[0-9a-f]+[ ]+R_386_GOT32[ ]+xtrn[ ]*
+ [0-9a-f]+[ ]+R_386_PLT32[ ]+xtrn[ ]*
+diff -rup binutils.orig/gas/testsuite/gas/i386/reloc32.d binutils-2.27/gas/testsuite/gas/i386/reloc32.d
+--- binutils.orig/gas/testsuite/gas/i386/reloc32.d 2017-10-25 12:52:20.052289604 +0100
++++ binutils-2.27/gas/testsuite/gas/i386/reloc32.d 2017-10-25 15:16:06.161659763 +0100
+@@ -19,7 +19,7 @@ Disassembly of section \.text:
+ .*[ ]+R_386_PC32[ ]+xtrn
+ .*[ ]+R_386_PC8[ ]+xtrn
+ .*[ ]+R_386_GOT32[ ]+xtrn
+-.*[ ]+R_386_GOT32X[ ]+xtrn
++.*[ ]+R_386_GOT32[ ]+xtrn
+ .*[ ]+R_386_GOTOFF[ ]+xtrn
+ .*[ ]+R_386_GOTOFF[ ]+xtrn
+ .*[ ]+R_386_GOTPC[ ]+_GLOBAL_OFFSET_TABLE_
+diff -rup binutils.orig/gas/testsuite/gas/i386/x86-64-gotpcrel.d binutils-2.27/gas/testsuite/gas/i386/x86-64-gotpcrel.d
+--- binutils.orig/gas/testsuite/gas/i386/x86-64-gotpcrel.d 2017-10-25 12:52:20.063289476 +0100
++++ binutils-2.27/gas/testsuite/gas/i386/x86-64-gotpcrel.d 2017-10-25 15:12:35.549099037 +0100
+@@ -1,5 +1,7 @@
+ #as: -mrelax-relocations=yes
+ #objdump: -dwr
++#skip: *-*-*
++# SKIPed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed.
+
+ .*: +file format .*
+
+diff -rup binutils.orig/gas/testsuite/gas/i386/x86-64-localpic.d binutils-2.27/gas/testsuite/gas/i386/x86-64-localpic.d
+--- binutils.orig/gas/testsuite/gas/i386/x86-64-localpic.d 2017-10-25 12:52:20.064289465 +0100
++++ binutils-2.27/gas/testsuite/gas/i386/x86-64-localpic.d 2017-10-25 15:12:35.549099037 +0100
+@@ -1,6 +1,8 @@
+ #as: -mrelax-relocations=yes
+ #readelf: -rsW
+ #name: x86-64 local PIC
++#skip: *-*-*
++# SKIPed because generation of the R_X86_64_REX_GOTPCRELX reloc is currently suppressed.
+
+ Relocation section '.rela.text' at offset 0x[0-9a-f]+ contains 1 entries:
+ +Offset +Info +Type +Symbol's Value +Symbol's Name \+ Addend
+diff -rup binutils.orig/ld/testsuite/ld-cdtest/cdtest-foo.cc binutils-2.27/ld/testsuite/ld-cdtest/cdtest-foo.cc
+--- binutils.orig/ld/testsuite/ld-cdtest/cdtest-foo.cc 2017-10-25 12:52:20.549283841 +0100
++++ binutils-2.27/ld/testsuite/ld-cdtest/cdtest-foo.cc 2017-10-25 15:12:35.549099037 +0100
+@@ -8,7 +8,7 @@
+ #if (__GNUG__ == 2)
+ typedef __SIZE_TYPE__ size_t;
+ #else
+-typedef unsigned int size_t;
++typedef unsigned long size_t;
+ #endif
+
+ extern "C" {
+diff -rup binutils.orig/ld/testsuite/ld-elf/shared.exp binutils-2.27/ld/testsuite/ld-elf/shared.exp
+--- binutils.orig/ld/testsuite/ld-elf/shared.exp 2017-10-25 12:52:20.578283504 +0100
++++ binutils-2.27/ld/testsuite/ld-elf/shared.exp 2017-10-25 15:45:58.374968233 +0100
+@@ -483,10 +483,10 @@ set build_cxx_tests {
+ "-shared -Wl,--dynamic-list-cpp-typeinfo" "-fPIC"
+ {dl3.cc} {} "libdl3c.so" "c++"}
+ {"Build libdnew1a.so with --Bsymbolic-functions --dynamic-list-cpp-new"
+- "-shared -Wl,-Bsymbolic-functions,--dynamic-list-cpp-new" "-fPIC"
++ "-shared -Wl,-Bsymbolic-functions,--dynamic-list-cpp-new" "-fPIC -ansi"
+ {del.cc new.cc} {} "libnew1a.so" "c++"}
+ {"Build libdnew1b.so with --dynamic-list-data --dynamic-list-cpp-new"
+- "-shared -Wl,--dynamic-list-data,--dynamic-list-cpp-new" "-fPIC"
++ "-shared -Wl,--dynamic-list-data,--dynamic-list-cpp-new" "-fPIC -ansi"
+ {del.cc new.cc} {} "libnew1b.so" "c++"}
+ }
+
+@@ -503,10 +503,10 @@ set run_cxx_tests {
+ {dl3main.cc} "dl3c" "dl3a.out" "" "c++"}
+ {"Run with libnew1a.so"
+ "tmpdir/libnew1a.so" ""
+- {dl5.cc} "dl5a" "dl5.out" "" "c++"}
++ {dl5.cc} "dl5a" "dl5.out" "-ansi" "c++"}
+ {"Run with libnew1b.so"
+ "tmpdir/libnew1b.so" ""
+- {dl5.cc} "dl5b" "dl5.out" "" "c++"}
++ {dl5.cc} "dl5b" "dl5.out" "-ansi" "c++"}
+ }
+
+ run_cc_link_tests $build_cxx_tests
+diff -rup binutils.orig/ld/testsuite/ld-i386/branch1.d binutils-2.27/ld/testsuite/ld-i386/branch1.d
+--- binutils.orig/ld/testsuite/ld-i386/branch1.d 2017-10-25 12:52:20.657282588 +0100
++++ binutils-2.27/ld/testsuite/ld-i386/branch1.d 2017-10-25 15:26:26.015497567 +0100
+@@ -1,6 +1,8 @@
+ #as: --32 -mrelax-relocations=yes
+ #ld: -melf_i386
+ #objdump: -dw
++#xfail: *-*-*
++# XFAILed because generation of the R_386_GOT32X relocs is currently suppressed.
+
+ .*: +file format .*
+
+diff -rup binutils.orig/ld/testsuite/ld-i386/call1.d binutils-2.27/ld/testsuite/ld-i386/call1.d
+--- binutils.orig/ld/testsuite/ld-i386/call1.d 2017-10-25 12:52:20.658282576 +0100
++++ binutils-2.27/ld/testsuite/ld-i386/call1.d 2017-10-25 15:26:33.407412174 +0100
+@@ -1,3 +1,5 @@
+ #as: --32 -mrelax-relocations=yes
+ #ld: -shared -melf_i386
+ #error: direct GOT relocation R_386_GOT32X against `foo' without base register can not be used when making a shared object
++#xfail: *-*-*
++# XFAILed because generation of the R_386_GOT32X relocs is currently suppressed.
+diff -rup binutils.orig/ld/testsuite/ld-i386/call2.d binutils-2.27/ld/testsuite/ld-i386/call2.d
+--- binutils.orig/ld/testsuite/ld-i386/call2.d 2017-10-25 12:52:20.658282576 +0100
++++ binutils-2.27/ld/testsuite/ld-i386/call2.d 2017-10-25 15:26:43.024301080 +0100
+@@ -1,3 +1,5 @@
+ #as: --32 -mrelax-relocations=yes
+ #ld: -shared -melf_i386
+ #error: direct GOT relocation R_386_GOT32X against `foo' without base register can not be used when making a shared object
++#xfail: *-*-*
++# XFAILed because generation of the R_386_GOT32X relocs is currently suppressed.
+diff -rup binutils.orig/ld/testsuite/ld-i386/call3a.d binutils-2.27/ld/testsuite/ld-i386/call3a.d
+--- binutils.orig/ld/testsuite/ld-i386/call3a.d 2017-10-25 12:52:20.658282576 +0100
++++ binutils-2.27/ld/testsuite/ld-i386/call3a.d 2017-10-25 15:29:17.042521838 +0100
+@@ -2,6 +2,8 @@
+ #as: --32 -mrelax-relocations=yes
+ #ld: -melf_i386
+ #objdump: -dw
++#xfail: *-*-*
++# XFAILed because generation of the R_386_GOT32X relocs is currently suppressed.
+
+ .*: +file format .*
+
+diff -rup binutils.orig/ld/testsuite/ld-i386/call3b.d binutils-2.27/ld/testsuite/ld-i386/call3b.d
+--- binutils.orig/ld/testsuite/ld-i386/call3b.d 2017-10-25 12:52:20.658282576 +0100
++++ binutils-2.27/ld/testsuite/ld-i386/call3b.d 2017-10-25 15:29:21.756467382 +0100
+@@ -2,6 +2,8 @@
+ #as: --32 -mrelax-relocations=yes
+ #ld: -melf_i386 -z call-nop=prefix-addr
+ #objdump: -dw
++#xfail: *-*-*
++# XFAILed because generation of the R_386_GOT32X relocs is currently suppressed.
+
+ .*: +file format .*
+
+diff -rup binutils.orig/ld/testsuite/ld-i386/call3c.d binutils-2.27/ld/testsuite/ld-i386/call3c.d
+--- binutils.orig/ld/testsuite/ld-i386/call3c.d 2017-10-25 12:52:20.658282576 +0100
++++ binutils-2.27/ld/testsuite/ld-i386/call3c.d 2017-10-25 15:29:26.457413076 +0100
+@@ -2,6 +2,8 @@
+ #as: --32 -mrelax-relocations=yes
+ #ld: -melf_i386 -z call-nop=prefix-nop
+ #objdump: -dw
++#xfail: *-*-*
++# XFAILed because generation of the R_386_GOT32X relocs is currently suppressed.
+
+ .*: +file format .*
+
+diff -rup binutils.orig/ld/testsuite/ld-i386/call3d.d binutils-2.27/ld/testsuite/ld-i386/call3d.d
+--- binutils.orig/ld/testsuite/ld-i386/call3d.d 2017-10-25 12:52:20.658282576 +0100
++++ binutils-2.27/ld/testsuite/ld-i386/call3d.d 2017-10-25 15:29:30.925361461 +0100
+@@ -2,6 +2,8 @@
+ #as: --32 -mrelax-relocations=yes
+ #ld: -melf_i386 -z call-nop=suffix-nop
+ #objdump: -dw
++#xfail: *-*-*
++# XFAILed because generation of the R_386_GOT32X relocs is currently suppressed.
+
+ .*: +file format .*
+
+diff -rup binutils.orig/ld/testsuite/ld-i386/call3e.d binutils-2.27/ld/testsuite/ld-i386/call3e.d
+--- binutils.orig/ld/testsuite/ld-i386/call3e.d 2017-10-25 12:52:20.658282576 +0100
++++ binutils-2.27/ld/testsuite/ld-i386/call3e.d 2017-10-25 15:29:38.894269403 +0100
+@@ -2,6 +2,8 @@
+ #as: --32 -mrelax-relocations=yes
+ #ld: -melf_i386 -z call-nop=prefix-0x67
+ #objdump: -dw
++#xfail: *-*-*
++# XFAILed because generation of the R_386_GOT32X relocs is currently suppressed.
+
+ .*: +file format .*
+
+diff -rup binutils.orig/ld/testsuite/ld-i386/call3f.d binutils-2.27/ld/testsuite/ld-i386/call3f.d
+--- binutils.orig/ld/testsuite/ld-i386/call3f.d 2017-10-25 12:52:20.658282576 +0100
++++ binutils-2.27/ld/testsuite/ld-i386/call3f.d 2017-10-25 15:29:47.134174215 +0100
+@@ -2,6 +2,8 @@
+ #as: --32 -mrelax-relocations=yes
+ #ld: -melf_i386 -z call-nop=prefix-0x90
+ #objdump: -dw
++#xfail: *-*-*
++# XFAILed because generation of the R_386_GOT32X relocs is currently suppressed.
+
+ .*: +file format .*
+
+diff -rup binutils.orig/ld/testsuite/ld-i386/call3g.d binutils-2.27/ld/testsuite/ld-i386/call3g.d
+--- binutils.orig/ld/testsuite/ld-i386/call3g.d 2017-10-25 12:52:20.658282576 +0100
++++ binutils-2.27/ld/testsuite/ld-i386/call3g.d 2017-10-25 15:29:52.341114063 +0100
+@@ -2,6 +2,8 @@
+ #as: --32 -mrelax-relocations=yes
+ #ld: -melf_i386 -z call-nop=suffix-0x90
+ #objdump: -dw
++#xfail: *-*-*
++# XFAILed because generation of the R_386_GOT32X relocs is currently suppressed.
+
+ .*: +file format .*
+
+diff -rup binutils.orig/ld/testsuite/ld-i386/call3h.d binutils-2.27/ld/testsuite/ld-i386/call3h.d
+--- binutils.orig/ld/testsuite/ld-i386/call3h.d 2017-10-25 12:52:20.658282576 +0100
++++ binutils-2.27/ld/testsuite/ld-i386/call3h.d 2017-10-25 15:29:57.237057504 +0100
+@@ -2,6 +2,8 @@
+ #as: --32 -mrelax-relocations=yes
+ #ld: -melf_i386 -z call-nop=suffix-144
+ #objdump: -dw
++#xfail: *-*-*
++# XFAILed because generation of the R_386_GOT32X relocs is currently suppressed.
+
+ .*: +file format .*
+
+diff -rup binutils.orig/ld/testsuite/ld-i386/i386.exp binutils-2.27/ld/testsuite/ld-i386/i386.exp
+--- binutils.orig/ld/testsuite/ld-i386/i386.exp 2017-10-25 12:52:20.661282542 +0100
++++ binutils-2.27/ld/testsuite/ld-i386/i386.exp 2017-10-25 15:42:06.083647050 +0100
+@@ -133,13 +133,6 @@ set i386tests {
+ {{readelf -Ssrl tlspic.rd} {objdump -drj.text tlspic.dd}
+ {objdump -sj.got tlspic.sd} {objdump -sj.tdata tlspic.td}}
+ "libtlspic.so"}
+- {"TLS -fpic -shared transitions without PLT"
+- "-shared -melf_i386 --no-ld-generated-unwind-info" ""
+- "-mrelax-relocations=yes --32"
+- {tlspic3.s tlspic2.s}
+- {{readelf -Ssrl tlspic2.rd} {objdump -drj.text tlspic2.dd}
+- {objdump -sj.got tlspic2.sd} {objdump -sj.tdata tlspic2.td}}
+- "libtlspic2.so"}
+ {"TLS descriptor -fpic -shared transitions"
+ "-shared -melf_i386 --no-ld-generated-unwind-info" ""
+ "--32" {tlsdesc.s tlspic2.s}
+@@ -154,13 +147,6 @@ set i386tests {
+ {{readelf -Ssrl tlsbin.rd} {objdump -drj.text tlsbin.dd}
+ {objdump -sj.got tlsbin.sd} {objdump -sj.tdata tlsbin.td}}
+ "tlsbin"}
+- {"TLS -fpic and -fno-pic exec transitions without PLT"
+- "-melf_i386 tmpdir/libtlslib.so --no-ld-generated-unwind-info" ""
+- "-mrelax-relocations=yes --32"
+- {tlsbinpic2.s tlsbin.s}
+- {{readelf -Ssrl tlsbin2.rd} {objdump -drj.text tlsbin2.dd}
+- {objdump -sj.got tlsbin2.sd} {objdump -sj.tdata tlsbin2.td}}
+- "tlsbin2"}
+ {"TLS descriptor -fpic and -fno-pic exec transitions"
+ "-melf_i386 tmpdir/libtlslib.so --no-ld-generated-unwind-info" ""
+ "--32" {tlsbindesc.s tlsbin.s}
+@@ -191,17 +177,9 @@ set i386tests {
+ {"TLS GD->LE transition" "-melf_i386" ""
+ "--32" {tlsgd1.s}
+ {{objdump -dwr tlsgd1.dd}} "tlsgd1"}
+- {"TLS GD->LE transition without PLT" "-melf_i386" ""
+- "-mrelax-relocations=yes --32"
+- {tlsgd3.s}
+- {{objdump -dwr tlsgd3.dd}} "tlsgd3"}
+ {"TLS LD->LE transition" "-melf_i386" ""
+ "--32" {tlsld1.s}
+ {{objdump -dwr tlsld1.dd}} "tlsld1"}
+- {"TLS LD->LE transition without PLT" "-melf_i386" ""
+- "-mrelax-relocations=yes --32"
+- {tlsld2.s}
+- {{objdump -dwr tlsld2.dd}} "tlsld2"}
+ {"TLS IE->LE transition" "-melf_i386" ""
+ "--32" {tlsie1.s}
+ {{objdump -dwr tlsie1.dd}} "tlsie1"}
+diff -rup binutils.orig/ld/testsuite/ld-i386/jmp1.d binutils-2.27/ld/testsuite/ld-i386/jmp1.d
+--- binutils.orig/ld/testsuite/ld-i386/jmp1.d 2017-10-25 12:52:20.661282542 +0100
++++ binutils-2.27/ld/testsuite/ld-i386/jmp1.d 2017-10-25 15:30:06.805946963 +0100
+@@ -1,3 +1,5 @@
+ #as: --32 -mrelax-relocations=yes
+ #ld: -shared -melf_i386
+ #error: direct GOT relocation R_386_GOT32X against `foo' without base register can not be used when making a shared object
++#xfail: *-*-*
++# XFAILed because generation of the R_386_GOT32X relocs is currently suppressed.
+diff -rup binutils.orig/ld/testsuite/ld-i386/jmp2.d binutils-2.27/ld/testsuite/ld-i386/jmp2.d
+--- binutils.orig/ld/testsuite/ld-i386/jmp2.d 2017-10-25 12:52:20.662282530 +0100
++++ binutils-2.27/ld/testsuite/ld-i386/jmp2.d 2017-10-25 15:30:14.181861755 +0100
+@@ -1,3 +1,5 @@
+ #as: --32 -mrelax-relocations=yes
+ #ld: -shared -melf_i386
+ #error: direct GOT relocation R_386_GOT32X against `foo' without base register can not be used when making a shared object
++#xfail: *-*-*
++# XFAILed because generation of the R_386_GOT32X relocs is currently suppressed.
+diff -rup binutils.orig/ld/testsuite/ld-i386/lea1a.d binutils-2.27/ld/testsuite/ld-i386/lea1a.d
+--- binutils.orig/ld/testsuite/ld-i386/lea1a.d 2017-10-25 12:52:20.662282530 +0100
++++ binutils-2.27/ld/testsuite/ld-i386/lea1a.d 2017-10-25 15:25:33.592103171 +0100
+@@ -2,6 +2,8 @@
+ #as: --32 -mrelax-relocations=yes
+ #ld: -Bsymbolic -shared -melf_i386
+ #objdump: -dw
++#xfail: *-*-*
++# XFAILed because generation of the R_386_GOT32X relocs is currently suppressed.
+
+ .*: +file format .*
+
+diff -rup binutils.orig/ld/testsuite/ld-i386/lea1b.d binutils-2.27/ld/testsuite/ld-i386/lea1b.d
+--- binutils.orig/ld/testsuite/ld-i386/lea1b.d 2017-10-25 12:52:20.662282530 +0100
++++ binutils-2.27/ld/testsuite/ld-i386/lea1b.d 2017-10-25 15:25:39.289037359 +0100
+@@ -2,6 +2,8 @@
+ #as: --32 -mrelax-relocations=yes
+ #ld: -pie -melf_i386
+ #objdump: -dw
++#xfail: *-*-*
++# XFAILed because generation of the R_386_GOT32X relocs is currently suppressed.
+
+ .*: +file format .*
+
+diff -rup binutils.orig/ld/testsuite/ld-i386/lea1c.d binutils-2.27/ld/testsuite/ld-i386/lea1c.d
+--- binutils.orig/ld/testsuite/ld-i386/lea1c.d 2017-10-25 12:52:20.662282530 +0100
++++ binutils-2.27/ld/testsuite/ld-i386/lea1c.d 2017-10-25 15:25:46.777950846 +0100
+@@ -2,6 +2,8 @@
+ #as: --32 -mrelax-relocations=yes
+ #ld: -melf_i386
+ #objdump: -dw
++#xfail: *-*-*
++# XFAILed because generation of the R_386_GOT32X relocs is currently suppressed.
+
+ .*: +file format .*
+
+diff -rup binutils.orig/ld/testsuite/ld-i386/lea1d.d binutils-2.27/ld/testsuite/ld-i386/lea1d.d
+--- binutils.orig/ld/testsuite/ld-i386/lea1d.d 2017-10-25 12:52:20.662282530 +0100
++++ binutils-2.27/ld/testsuite/ld-i386/lea1d.d 2017-10-25 15:25:55.802846589 +0100
+@@ -2,6 +2,8 @@
+ #as: --32 -mrelax-relocations=yes
+ #ld: -Bsymbolic -shared -melf_i386
+ #readelf: -Sw
++#xfail: *-*-*
++# XFAILed because generation of the R_386_GOT32X relocs is currently suppressed.
+
+ #failif
+ #...
+diff -rup binutils.orig/ld/testsuite/ld-i386/lea1e.d binutils-2.27/ld/testsuite/ld-i386/lea1e.d
+--- binutils.orig/ld/testsuite/ld-i386/lea1e.d 2017-10-25 12:52:20.662282530 +0100
++++ binutils-2.27/ld/testsuite/ld-i386/lea1e.d 2017-10-25 15:26:03.115762109 +0100
+@@ -2,6 +2,8 @@
+ #as: --32 -mrelax-relocations=yes
+ #ld: -pie -melf_i386
+ #readelf: -Sw
++#xfail: *-*-*
++# XFAILed because generation of the R_386_GOT32X relocs is currently suppressed.
+
+ #failif
+ #...
+diff -rup binutils.orig/ld/testsuite/ld-i386/lea1f.d binutils-2.27/ld/testsuite/ld-i386/lea1f.d
+--- binutils.orig/ld/testsuite/ld-i386/lea1f.d 2017-10-25 12:52:20.662282530 +0100
++++ binutils-2.27/ld/testsuite/ld-i386/lea1f.d 2017-10-25 15:26:09.485688523 +0100
+@@ -2,6 +2,8 @@
+ #as: --32 -mrelax-relocations=yes
+ #ld: -melf_i386
+ #readelf: -Sw
++#xfail: *-*-*
++# XFAILed because generation of the R_386_GOT32X relocs is currently suppressed.
+
+ #failif
+ #...
+diff -rup binutils.orig/ld/testsuite/ld-i386/load1.d binutils-2.27/ld/testsuite/ld-i386/load1.d
+--- binutils.orig/ld/testsuite/ld-i386/load1.d 2017-10-25 12:52:20.662282530 +0100
++++ binutils-2.27/ld/testsuite/ld-i386/load1.d 2017-10-25 15:30:23.543753605 +0100
+@@ -2,6 +2,8 @@
+ #ld: -melf_i386
+ #objdump: -dw --sym
+ #notarget: i?86-*-nacl* x86_64-*-nacl*
++#xfail: *-*-*
++# XFAILed because generation of the R_386_GOT32X relocs is currently suppressed.
+
+ .*: +file format .*
+
+diff -rup binutils.orig/ld/testsuite/ld-i386/load2.d binutils-2.27/ld/testsuite/ld-i386/load2.d
+--- binutils.orig/ld/testsuite/ld-i386/load2.d 2017-10-25 12:52:20.662282530 +0100
++++ binutils-2.27/ld/testsuite/ld-i386/load2.d 2017-10-25 15:31:10.090215894 +0100
+@@ -1,3 +1,3 @@
+ #as: --32 -mrelax-relocations=yes
+ #ld: -melf_i386 -shared
+-#error: direct GOT relocation R_386_GOT32X against `foo' without base register can not be used when making a shared object
++#error: direct GOT relocation R_386_GOT32 against `foo' without base register can not be used when making a shared object
+diff -rup binutils.orig/ld/testsuite/ld-i386/load3.d binutils-2.27/ld/testsuite/ld-i386/load3.d
+--- binutils.orig/ld/testsuite/ld-i386/load3.d 2017-10-25 12:52:20.663282518 +0100
++++ binutils-2.27/ld/testsuite/ld-i386/load3.d 2017-10-25 15:31:24.220052664 +0100
+@@ -1,3 +1,3 @@
+ #as: --32 -mrelax-relocations=yes
+ #ld: -melf_i386 -shared
+-#error: direct GOT relocation R_386_GOT32X against `foo' without base register can not be used when making a shared object
++#error: direct GOT relocation R_386_GOT32 against `foo' without base register can not be used when making a shared object
+diff -rup binutils.orig/ld/testsuite/ld-i386/load4a.d binutils-2.27/ld/testsuite/ld-i386/load4a.d
+--- binutils.orig/ld/testsuite/ld-i386/load4a.d 2017-10-25 12:52:20.663282518 +0100
++++ binutils-2.27/ld/testsuite/ld-i386/load4a.d 2017-10-25 15:31:33.802941960 +0100
+@@ -1,4 +1,4 @@
+ #source: load4.s
+ #as: --32 -mrelax-relocations=yes
+ #ld: -Bsymbolic -shared -melf_i386
+-#error: direct GOT relocation R_386_GOT32X against `foo' without base register can not be used when making a shared object
++#error: direct GOT relocation R_386_GOT32 against `foo' without base register can not be used when making a shared object
+diff -rup binutils.orig/ld/testsuite/ld-i386/load4b.d binutils-2.27/ld/testsuite/ld-i386/load4b.d
+--- binutils.orig/ld/testsuite/ld-i386/load4b.d 2017-10-25 12:52:20.663282518 +0100
++++ binutils-2.27/ld/testsuite/ld-i386/load4b.d 2017-10-25 15:31:50.701746743 +0100
+@@ -2,6 +2,8 @@
+ #as: --32
+ #ld: -melf_i386
+ #objdump: -dw
++#xfail: *-*-*
++# XFAILed because generation of the R_386_GOT32X relocs is currently suppressed.
+
+ .*: +file format .*
+
+diff -rup binutils.orig/ld/testsuite/ld-i386/load5a.d binutils-2.27/ld/testsuite/ld-i386/load5a.d
+--- binutils.orig/ld/testsuite/ld-i386/load5a.d 2017-10-25 12:52:20.663282518 +0100
++++ binutils-2.27/ld/testsuite/ld-i386/load5a.d 2017-10-25 15:31:59.182648770 +0100
+@@ -1,4 +1,4 @@
+ #source: load5.s
+ #as: --32 -mrelax-relocations=yes
+ #ld: -Bsymbolic -shared -melf_i386
+-#error: direct GOT relocation R_386_GOT32X against `foo' without base register can not be used when making a shared object
++#error: direct GOT relocation R_386_GOT32 against `foo' without base register can not be used when making a shared object
+diff -rup binutils.orig/ld/testsuite/ld-i386/load5b.d binutils-2.27/ld/testsuite/ld-i386/load5b.d
+--- binutils.orig/ld/testsuite/ld-i386/load5b.d 2017-10-25 12:52:20.663282518 +0100
++++ binutils-2.27/ld/testsuite/ld-i386/load5b.d 2017-10-25 15:32:05.614574468 +0100
+@@ -2,6 +2,8 @@
+ #as: --32
+ #ld: -melf_i386
+ #objdump: -dw
++#xfail: *-*-*
++# XFAILed because generation of the R_386_GOT32X relocs is currently suppressed.
+
+ .*: +file format .*
+
+diff -rup binutils.orig/ld/testsuite/ld-i386/load7.d binutils-2.27/ld/testsuite/ld-i386/load7.d
+--- binutils.orig/ld/testsuite/ld-i386/load7.d 2017-10-25 12:52:20.663282518 +0100
++++ binutils-2.27/ld/testsuite/ld-i386/load7.d 2017-10-25 15:32:15.231463372 +0100
+@@ -1,6 +1,8 @@
+ #as: --32 -mrelax-relocations=yes
+ #ld: -shared -melf_i386 --version-script load7.map
+ #objdump: -dw
++#xfail: *-*-*
++# XFAILed because generation of the R_386_GOT32X relocs is currently suppressed.
+
+ .*: +file format .*
+
+diff -rup binutils.orig/ld/testsuite/ld-i386/mov1b.d binutils-2.27/ld/testsuite/ld-i386/mov1b.d
+--- binutils.orig/ld/testsuite/ld-i386/mov1b.d 2017-10-25 12:52:20.664282507 +0100
++++ binutils-2.27/ld/testsuite/ld-i386/mov1b.d 2017-10-25 15:26:17.582594986 +0100
+@@ -2,6 +2,8 @@
+ #as: --32 -mrelax-relocations=yes
+ #ld: -pie -melf_i386 --no-dynamic-linker
+ #objdump: -dw
++#xfail: *-*-*
++# XFAILed because generation of the R_386_GOT32X relocs is currently suppressed.
+
+ .*: +file format .*
+
+diff -rup binutils.orig/ld/testsuite/ld-i386/pr19175.d binutils-2.27/ld/testsuite/ld-i386/pr19175.d
+--- binutils.orig/ld/testsuite/ld-i386/pr19175.d 2017-10-25 12:52:20.671282426 +0100
++++ binutils-2.27/ld/testsuite/ld-i386/pr19175.d 2017-10-25 15:34:05.638187937 +0100
+@@ -2,6 +2,8 @@
+ #as: --32 -mrelax-relocations=yes
+ #ld: -Bsymbolic -shared -melf_i386 -T pr19175.t
+ #objdump: -dw
++#xfail: *-*-*
++# XFAILed because generation of the R_386_GOT32X relocs is currently suppressed.
+
+ .*: +file format .*
+
+diff -rup binutils.orig/ld/testsuite/ld-i386/pr19609-1a.d binutils-2.27/ld/testsuite/ld-i386/pr19609-1a.d
+--- binutils.orig/ld/testsuite/ld-i386/pr19609-1a.d 2017-10-25 12:52:20.672282414 +0100
++++ binutils-2.27/ld/testsuite/ld-i386/pr19609-1a.d 2017-10-25 15:34:17.143055031 +0100
+@@ -2,6 +2,8 @@
+ #as: --32 -mrelax-relocations=yes
+ #ld: -melf_i386
+ #objdump: -dw
++#xfail: *-*-*
++# XFAILed because generation of the R_386_GOT32X relocs is currently suppressed.
+
+ .*: +file format .*
+
+diff -rup binutils.orig/ld/testsuite/ld-i386/pr19609-1b.d binutils-2.27/ld/testsuite/ld-i386/pr19609-1b.d
+--- binutils.orig/ld/testsuite/ld-i386/pr19609-1b.d 2017-10-25 12:52:20.672282414 +0100
++++ binutils-2.27/ld/testsuite/ld-i386/pr19609-1b.d 2017-10-25 15:34:25.735955848 +0100
+@@ -2,6 +2,8 @@
+ #as: --32 -mrelax-relocations=yes
+ #ld: -pie -melf_i386 --no-dynamic-linker
+ #objdump: -dw
++#xfail: *-*-*
++# XFAILed because generation of the R_386_GOT32X relocs is currently suppressed.
+
+ .*: +file format .*
+
+diff -rup binutils.orig/ld/testsuite/ld-i386/pr19609-1d.d binutils-2.27/ld/testsuite/ld-i386/pr19609-1d.d
+--- binutils.orig/ld/testsuite/ld-i386/pr19609-1d.d 2017-10-25 12:52:20.673282403 +0100
++++ binutils-2.27/ld/testsuite/ld-i386/pr19609-1d.d 2017-10-25 15:35:05.258500067 +0100
+@@ -2,6 +2,8 @@
+ #as: --32 -mrelax-relocations=yes
+ #ld: -E -melf_i386 --no-dynamic-linker
+ #objdump: -dw
++#xfail: *-*-*
++# XFAILed because generation of the R_386_GOT32X relocs is currently suppressed.
+
+ .*: +file format .*
+
+diff -rup binutils.orig/ld/testsuite/ld-i386/pr19609-1f.d binutils-2.27/ld/testsuite/ld-i386/pr19609-1f.d
+--- binutils.orig/ld/testsuite/ld-i386/pr19609-1f.d 2017-10-25 12:52:20.673282403 +0100
++++ binutils-2.27/ld/testsuite/ld-i386/pr19609-1f.d 2017-10-25 15:35:18.620345975 +0100
+@@ -2,6 +2,8 @@
+ #as: --32 -mrelax-relocations=yes
+ #ld: -pie --dynamic-list-data -melf_i386 --no-dynamic-linker
+ #objdump: -dw
++#xfail: *-*-*
++# XFAILed because generation of the R_386_GOT32X relocs is currently suppressed.
+
+ .*: +file format .*
+
+diff -rup binutils.orig/ld/testsuite/ld-i386/pr19609-1g.d binutils-2.27/ld/testsuite/ld-i386/pr19609-1g.d
+--- binutils.orig/ld/testsuite/ld-i386/pr19609-1g.d 2017-10-25 12:52:20.673282403 +0100
++++ binutils-2.27/ld/testsuite/ld-i386/pr19609-1g.d 2017-10-25 15:35:26.379256499 +0100
+@@ -2,6 +2,8 @@
+ #as: --32 -mrelax-relocations=yes
+ #ld: -pie -E -melf_i386 --no-dynamic-linker
+ #objdump: -dw
++#xfail: *-*-*
++# XFAILed because generation of the R_386_GOT32X relocs is currently suppressed.
+
+ .*: +file format .*
+
+diff -rup binutils.orig/ld/testsuite/ld-i386/pr19609-1h.d binutils-2.27/ld/testsuite/ld-i386/pr19609-1h.d
+--- binutils.orig/ld/testsuite/ld-i386/pr19609-1h.d 2017-10-25 12:52:20.673282403 +0100
++++ binutils-2.27/ld/testsuite/ld-i386/pr19609-1h.d 2017-10-25 15:35:33.308176593 +0100
+@@ -2,6 +2,8 @@
+ #as: --32 -mrelax-relocations=yes
+ #ld: -pie -E -Bsymbolic-functions -melf_i386 --no-dynamic-linker
+ #objdump: -dw
++#xfail: *-*-*
++# XFAILed because generation of the R_386_GOT32X relocs is currently suppressed.
+
+ .*: +file format .*
+
+diff -rup binutils.orig/ld/testsuite/ld-i386/pr19609-2a.d binutils-2.27/ld/testsuite/ld-i386/pr19609-2a.d
+--- binutils.orig/ld/testsuite/ld-i386/pr19609-2a.d 2017-10-25 12:52:20.673282403 +0100
++++ binutils-2.27/ld/testsuite/ld-i386/pr19609-2a.d 2017-10-25 15:35:46.253027313 +0100
+@@ -2,6 +2,8 @@
+ #as: --32 -mrelax-relocations=yes
+ #ld: -melf_i386
+ #objdump: -dw
++#xfail: *-*-*
++# XFAILed because generation of the R_386_GOT32X relocs is currently suppressed.
+
+ .*: +file format .*
+
+diff -rup binutils.orig/ld/testsuite/ld-i386/pr20244-2d.d binutils-2.27/ld/testsuite/ld-i386/pr20244-2d.d
+--- binutils.orig/ld/testsuite/ld-i386/pr20244-2d.d 2017-10-25 12:52:20.677282356 +0100
++++ binutils-2.27/ld/testsuite/ld-i386/pr20244-2d.d 2017-10-25 15:38:34.521086821 +0100
+@@ -1,4 +1,4 @@
+ #source: pr20244-2.s
+ #as: --32
+ #ld: -pie -m elf_i386
+-#error: direct GOT relocation R_386_GOT32X against `foo' without base register can not be used when making a shared object
++#error: direct GOT relocation R_386_GOT32 against `foo' without base register can not be used when making a shared object
+diff -rup binutils.orig/ld/testsuite/ld-i386/pr20253-4b.d binutils-2.27/ld/testsuite/ld-i386/pr20253-4b.d
+--- binutils.orig/ld/testsuite/ld-i386/pr20253-4b.d 2017-10-25 12:52:20.678282345 +0100
++++ binutils-2.27/ld/testsuite/ld-i386/pr20253-4b.d 2017-10-25 15:36:45.185347695 +0100
+@@ -2,6 +2,8 @@
+ #as: --32 -mrelax-relocations=yes
+ #ld: -pie -melf_i386
+ #readelf: -r --wide
++#xfail: *-*-*
++# XFAILed because generation of the R_386_GOT32X relocs is currently suppressed.
+
+ Relocation section '.rel.dyn' at offset 0x[0-9a-f]+ contains 1 entries:
+ +Offset +Info +Type +Sym.* Value +Symbol's Name
+diff -rup binutils.orig/ld/testsuite/ld-i386/tlspie3a.d binutils-2.27/ld/testsuite/ld-i386/tlspie3a.d
+--- binutils.orig/ld/testsuite/ld-i386/tlspie3a.d 2017-10-25 12:52:20.682282298 +0100
++++ binutils-2.27/ld/testsuite/ld-i386/tlspie3a.d 2017-10-25 15:25:02.726459735 +0100
+@@ -2,5 +2,7 @@
+ #as: --32 -mrelax-relocations=yes
+ #ld: -melf_i386 -pie
+ #readelf: -r
++#xfail: *-*-*
++# XFAILed because generation of the R_386_GOT32X relocs is currently suppressed.
+
+ There are no relocations in this file.
+diff -rup binutils.orig/ld/testsuite/ld-i386/tlspie3b.d binutils-2.27/ld/testsuite/ld-i386/tlspie3b.d
+--- binutils.orig/ld/testsuite/ld-i386/tlspie3b.d 2017-10-25 12:52:20.682282298 +0100
++++ binutils-2.27/ld/testsuite/ld-i386/tlspie3b.d 2017-10-25 15:25:10.854365839 +0100
+@@ -2,6 +2,8 @@
+ #as: --32 -mrelax-relocations=yes
+ #ld: -melf_i386 -pie
+ #objdump: -dwr
++#xfail: *-*-*
++# XFAILed because generation of the R_386_GOT32X relocs is currently suppressed.
+
+ .*: +file format .*
+
+diff -rup binutils.orig/ld/testsuite/ld-i386/tlspie3c.d binutils-2.27/ld/testsuite/ld-i386/tlspie3c.d
+--- binutils.orig/ld/testsuite/ld-i386/tlspie3c.d 2017-10-25 12:52:20.682282298 +0100
++++ binutils-2.27/ld/testsuite/ld-i386/tlspie3c.d 2017-10-25 15:25:21.319244949 +0100
+@@ -2,6 +2,8 @@
+ #as: --32 -mrelax-relocations=yes
+ #ld: -melf_i386 -pie -z call-nop=suffix-nop
+ #objdump: -dwr
++#xfail: *-*-*
++# XFAILed because generation of the R_386_GOT32X relocs is currently suppressed.
+
+ .*: +file format .*
+
+diff -rup binutils.orig/ld/testsuite/ld-ifunc/ifunc-13-i386.d binutils-2.27/ld/testsuite/ld-ifunc/ifunc-13-i386.d
+--- binutils.orig/ld/testsuite/ld-ifunc/ifunc-13-i386.d 2017-10-25 12:52:20.686282252 +0100
++++ binutils-2.27/ld/testsuite/ld-ifunc/ifunc-13-i386.d 2017-10-25 15:22:29.230232946 +0100
+@@ -4,6 +4,8 @@
+ #as: --32 -mrelax-relocations=yes
+ #readelf: -r --wide
+ #target: x86_64-*-* i?86-*-*
++#xfail: *-*-*
++# XFAILed because generation of the R_386_GOT32X relocs is currently suppressed.
+
+ Relocation section '.rel.ifunc' at offset 0x[0-9a-f]+ contains 1 entries:
+ [ ]+Offset[ ]+Info[ ]+Type[ ]+.*
+diff -rup binutils.orig/ld/testsuite/ld-ifunc/ifunc-21-i386.d binutils-2.27/ld/testsuite/ld-ifunc/ifunc-21-i386.d
+--- binutils.orig/ld/testsuite/ld-ifunc/ifunc-21-i386.d 2017-10-25 12:52:20.688282229 +0100
++++ binutils-2.27/ld/testsuite/ld-ifunc/ifunc-21-i386.d 2017-10-25 15:23:08.637777705 +0100
+@@ -2,6 +2,8 @@
+ #as: --32 -mrelax-relocations=yes
+ #objdump: -dw
+ #target: x86_64-*-* i?86-*-*
++#xfail: *-*-*
++# XFAILed because generation of the R_386_GOT32X relocs is currently suppressed.
+
+ .*: +file format .*
+
+diff -rup binutils.orig/ld/testsuite/ld-ifunc/ifunc-21-x86-64.d binutils-2.27/ld/testsuite/ld-ifunc/ifunc-21-x86-64.d
+--- binutils.orig/ld/testsuite/ld-ifunc/ifunc-21-x86-64.d 2017-10-25 12:52:20.690282205 +0100
++++ binutils-2.27/ld/testsuite/ld-ifunc/ifunc-21-x86-64.d 2017-10-25 15:12:35.549099037 +0100
+@@ -2,6 +2,8 @@
+ #ld: -melf_x86_64
+ #objdump: -dw
+ #target: x86_64-*-*
++#xfail: *-*-*
++# XFAILed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed.
+
+ .*: +file format .*
+
+diff -rup binutils.orig/ld/testsuite/ld-ifunc/ifunc-22-i386.d binutils-2.27/ld/testsuite/ld-ifunc/ifunc-22-i386.d
+--- binutils.orig/ld/testsuite/ld-ifunc/ifunc-22-i386.d 2017-10-25 12:52:20.688282229 +0100
++++ binutils-2.27/ld/testsuite/ld-ifunc/ifunc-22-i386.d 2017-10-25 15:23:00.698869415 +0100
+@@ -2,6 +2,8 @@
+ #as: --32 -mrelax-relocations=yes
+ #objdump: -dw
+ #target: x86_64-*-* i?86-*-*
++#xfail: *-*-*
++# XFAILed because generation of the R_386_GOT32X relocs is currently suppressed.
+
+ .*: +file format .*
+
+diff -rup binutils.orig/ld/testsuite/ld-ifunc/ifunc-22-x86-64.d binutils-2.27/ld/testsuite/ld-ifunc/ifunc-22-x86-64.d
+--- binutils.orig/ld/testsuite/ld-ifunc/ifunc-22-x86-64.d 2017-10-25 12:52:20.690282205 +0100
++++ binutils-2.27/ld/testsuite/ld-ifunc/ifunc-22-x86-64.d 2017-10-25 15:12:35.549099037 +0100
+@@ -2,6 +2,8 @@
+ #ld: -melf_x86_64
+ #objdump: -dw
+ #target: x86_64-*-*
++#xfail: *-*-*
++# XFAILed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed.
+
+ .*: +file format .*
+
+diff -rup binutils.orig/ld/testsuite/ld-ifunc/ifunc-5r-local-x86-64.d binutils-2.27/ld/testsuite/ld-ifunc/ifunc-5r-local-x86-64.d
+--- binutils.orig/ld/testsuite/ld-ifunc/ifunc-5r-local-x86-64.d 2017-10-25 12:52:20.689282217 +0100
++++ binutils-2.27/ld/testsuite/ld-ifunc/ifunc-5r-local-x86-64.d 2017-10-25 15:12:35.549099037 +0100
+@@ -3,6 +3,8 @@
+ #ld: -r -melf_x86_64
+ #readelf: -r --wide
+ #target: x86_64-*-*
++#xfail: *-*-*
++# XFAILed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed.
+
+ Relocation section '.rela.text' at .*
+ [ ]+Offset[ ]+Info[ ]+Type[ ]+.*
+diff -rup binutils.orig/ld/testsuite/ld-selective/selective.exp binutils-2.27/ld/testsuite/ld-selective/selective.exp
+--- binutils.orig/ld/testsuite/ld-selective/selective.exp 2017-10-25 12:52:20.872280095 +0100
++++ binutils-2.27/ld/testsuite/ld-selective/selective.exp 2017-10-25 15:21:30.397912586 +0100
+@@ -102,7 +102,7 @@ foreach testitem $seltests {
+ # the functionality we try to test for cannot be expected to work.
+ set version [remote_exec host "$CXX -dumpversion"]
+ set version [lindex $version 1]
+- if [regexp "^(\[1-9\]\[0-9\]+|\[4-9\]|3.(\[1-9\]\[0-9\]+|\[4-9\]))\\." $version] {
++ if [regexp "^(\[1-9\]\[0-9\]+|\[4-9\]|3.(\[1-9\]\[0-9\]+|\[4-9\]))" $version] {
+ set testflags "$cflags $cxxflags"
+ setup_xfail {*-*-*}
+ } else {
+diff -rup binutils.orig/ld/testsuite/ld-x86-64/call1a.d binutils-2.27/ld/testsuite/ld-x86-64/call1a.d
+--- binutils.orig/ld/testsuite/ld-x86-64/call1a.d 2017-10-25 12:52:21.010278494 +0100
++++ binutils-2.27/ld/testsuite/ld-x86-64/call1a.d 2017-10-25 15:12:35.550099025 +0100
+@@ -2,6 +2,8 @@
+ #as: --64 -mrelax-relocations=yes
+ #ld: -melf_x86_64
+ #objdump: -dw
++#xfail: *-*-*
++# XFAILed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed.
+
+ .*: +file format .*
+
+diff -rup binutils.orig/ld/testsuite/ld-x86-64/call1b.d binutils-2.27/ld/testsuite/ld-x86-64/call1b.d
+--- binutils.orig/ld/testsuite/ld-x86-64/call1b.d 2017-10-25 12:52:21.010278494 +0100
++++ binutils-2.27/ld/testsuite/ld-x86-64/call1b.d 2017-10-25 15:12:35.550099025 +0100
+@@ -2,6 +2,8 @@
+ #as: --64 -mrelax-relocations=yes
+ #ld: -melf_x86_64 -z call-nop=prefix-addr
+ #objdump: -dw
++#xfail: *-*-*
++# XFAILed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed.
+
+ .*: +file format .*
+
+diff -rup binutils.orig/ld/testsuite/ld-x86-64/call1c.d binutils-2.27/ld/testsuite/ld-x86-64/call1c.d
+--- binutils.orig/ld/testsuite/ld-x86-64/call1c.d 2017-10-25 12:52:21.010278494 +0100
++++ binutils-2.27/ld/testsuite/ld-x86-64/call1c.d 2017-10-25 15:12:35.550099025 +0100
+@@ -2,6 +2,8 @@
+ #as: --64 -mrelax-relocations=yes
+ #ld: -melf_x86_64 -z call-nop=prefix-nop
+ #objdump: -dw
++#xfail: *-*-*
++# XFAILed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed.
+
+ .*: +file format .*
+
+diff -rup binutils.orig/ld/testsuite/ld-x86-64/call1d.d binutils-2.27/ld/testsuite/ld-x86-64/call1d.d
+--- binutils.orig/ld/testsuite/ld-x86-64/call1d.d 2017-10-25 12:52:21.011278483 +0100
++++ binutils-2.27/ld/testsuite/ld-x86-64/call1d.d 2017-10-25 15:12:35.550099025 +0100
+@@ -2,6 +2,8 @@
+ #as: --64 -mrelax-relocations=yes
+ #ld: -melf_x86_64 -z call-nop=suffix-nop
+ #objdump: -dw
++#xfail: *-*-*
++# XFAILed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed.
+
+ .*: +file format .*
+
+diff -rup binutils.orig/ld/testsuite/ld-x86-64/call1e.d binutils-2.27/ld/testsuite/ld-x86-64/call1e.d
+--- binutils.orig/ld/testsuite/ld-x86-64/call1e.d 2017-10-25 12:52:21.011278483 +0100
++++ binutils-2.27/ld/testsuite/ld-x86-64/call1e.d 2017-10-25 15:12:35.550099025 +0100
+@@ -2,6 +2,8 @@
+ #as: --64 -mrelax-relocations=yes
+ #ld: -melf_x86_64 -z call-nop=prefix-0x67
+ #objdump: -dw
++#xfail: *-*-*
++# XFAILed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed.
+
+ .*: +file format .*
+
+diff -rup binutils.orig/ld/testsuite/ld-x86-64/call1f.d binutils-2.27/ld/testsuite/ld-x86-64/call1f.d
+--- binutils.orig/ld/testsuite/ld-x86-64/call1f.d 2017-10-25 12:52:21.011278483 +0100
++++ binutils-2.27/ld/testsuite/ld-x86-64/call1f.d 2017-10-25 15:12:35.550099025 +0100
+@@ -2,6 +2,8 @@
+ #as: --64 -mrelax-relocations=yes
+ #ld: -melf_x86_64 -z call-nop=prefix-0x90
+ #objdump: -dw
++#xfail: *-*-*
++# XFAILed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed.
+
+ .*: +file format .*
+
+diff -rup binutils.orig/ld/testsuite/ld-x86-64/call1g.d binutils-2.27/ld/testsuite/ld-x86-64/call1g.d
+--- binutils.orig/ld/testsuite/ld-x86-64/call1g.d 2017-10-25 12:52:21.011278483 +0100
++++ binutils-2.27/ld/testsuite/ld-x86-64/call1g.d 2017-10-25 15:12:35.550099025 +0100
+@@ -2,6 +2,8 @@
+ #as: --64 -mrelax-relocations=yes
+ #ld: -melf_x86_64 -z call-nop=suffix-0x90
+ #objdump: -dw
++#xfail: *-*-*
++# XFAILed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed.
+
+ .*: +file format .*
+
+diff -rup binutils.orig/ld/testsuite/ld-x86-64/call1h.d binutils-2.27/ld/testsuite/ld-x86-64/call1h.d
+--- binutils.orig/ld/testsuite/ld-x86-64/call1h.d 2017-10-25 12:52:21.011278483 +0100
++++ binutils-2.27/ld/testsuite/ld-x86-64/call1h.d 2017-10-25 15:12:35.550099025 +0100
+@@ -2,6 +2,8 @@
+ #as: --64 -mrelax-relocations=yes
+ #ld: -melf_x86_64 -z call-nop=suffix-144
+ #objdump: -dw
++#xfail: *-*-*
++# XFAILed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed.
+
+ .*: +file format .*
+
+diff -rup binutils.orig/ld/testsuite/ld-x86-64/call1i.d binutils-2.27/ld/testsuite/ld-x86-64/call1i.d
+--- binutils.orig/ld/testsuite/ld-x86-64/call1i.d 2017-10-25 12:52:21.011278483 +0100
++++ binutils-2.27/ld/testsuite/ld-x86-64/call1i.d 2017-10-25 15:12:35.550099025 +0100
+@@ -2,6 +2,8 @@
+ #as: --x32 -mrelax-relocations=yes
+ #ld: -melf32_x86_64 -z call-nop=suffix-0x90
+ #objdump: -dw
++#xfail: *-*-*
++# XFAILed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed.
+
+ .*: +file format .*
+
+diff -rup binutils.orig/ld/testsuite/ld-x86-64/lea1c.d binutils-2.27/ld/testsuite/ld-x86-64/lea1c.d
+--- binutils.orig/ld/testsuite/ld-x86-64/lea1c.d 2017-10-25 12:52:21.015278436 +0100
++++ binutils-2.27/ld/testsuite/ld-x86-64/lea1c.d 2017-10-25 15:12:35.550099025 +0100
+@@ -2,6 +2,8 @@
+ #as: --64 -mrelax-relocations=yes
+ #ld: -melf_x86_64
+ #objdump: -dw
++#xfail: *-*-*
++# XFAILed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed.
+
+ .*: +file format .*
+
+diff -rup binutils.orig/ld/testsuite/ld-x86-64/lea1f.d binutils-2.27/ld/testsuite/ld-x86-64/lea1f.d
+--- binutils.orig/ld/testsuite/ld-x86-64/lea1f.d 2017-10-25 12:52:21.016278425 +0100
++++ binutils-2.27/ld/testsuite/ld-x86-64/lea1f.d 2017-10-25 15:12:35.550099025 +0100
+@@ -2,6 +2,8 @@
+ #as: --x32 -mrelax-relocations=yes
+ #ld: -melf32_x86_64
+ #objdump: -dw
++#xfail: *-*-*
++# XFAILed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed.
+
+ .*: +file format .*
+
+diff -rup binutils.orig/ld/testsuite/ld-x86-64/load1a.d binutils-2.27/ld/testsuite/ld-x86-64/load1a.d
+--- binutils.orig/ld/testsuite/ld-x86-64/load1a.d 2017-10-25 12:52:21.016278425 +0100
++++ binutils-2.27/ld/testsuite/ld-x86-64/load1a.d 2017-10-25 15:12:35.550099025 +0100
+@@ -3,6 +3,8 @@
+ #ld: -melf_x86_64
+ #objdump: -dw --sym
+ #notarget: x86_64-*-nacl*
++#xfail: *-*-*
++# XFAILed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed.
+
+ .*: +file format .*
+
+diff -rup binutils.orig/ld/testsuite/ld-x86-64/load1b.d binutils-2.27/ld/testsuite/ld-x86-64/load1b.d
+--- binutils.orig/ld/testsuite/ld-x86-64/load1b.d 2017-10-25 12:52:21.017278414 +0100
++++ binutils-2.27/ld/testsuite/ld-x86-64/load1b.d 2017-10-25 15:12:35.550099025 +0100
+@@ -3,6 +3,8 @@
+ #ld: -melf32_x86_64
+ #objdump: -dw --sym
+ #notarget: x86_64-*-nacl*
++#xfail: *-*-*
++# XFAILed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed.
+
+ .*: +file format .*
+
+diff -rup binutils.orig/ld/testsuite/ld-x86-64/mov1b.d binutils-2.27/ld/testsuite/ld-x86-64/mov1b.d
+--- binutils.orig/ld/testsuite/ld-x86-64/mov1b.d 2017-10-25 12:52:21.041278135 +0100
++++ binutils-2.27/ld/testsuite/ld-x86-64/mov1b.d 2017-10-25 15:12:35.550099025 +0100
+@@ -2,6 +2,8 @@
+ #as: --64 -mrelax-relocations=yes
+ #ld: -pie -melf_x86_64 --no-dynamic-linker
+ #objdump: -dw
++#xfail: *-*-*
++# XFAILed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed.
+
+ .*: +file format .*
+
+diff -rup binutils.orig/ld/testsuite/ld-x86-64/mov1d.d binutils-2.27/ld/testsuite/ld-x86-64/mov1d.d
+--- binutils.orig/ld/testsuite/ld-x86-64/mov1d.d 2017-10-25 12:52:21.041278135 +0100
++++ binutils-2.27/ld/testsuite/ld-x86-64/mov1d.d 2017-10-25 15:12:35.551099013 +0100
+@@ -2,6 +2,8 @@
+ #as: --x32 -mrelax-relocations=yes
+ #ld: -pie -melf32_x86_64 --no-dynamic-linker
+ #objdump: -dw
++#xfail: *-*-*
++# XFAILed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed.
+
+ .*: +file format .*
+
+diff -rup binutils.orig/ld/testsuite/ld-x86-64/no-plt.exp binutils-2.27/ld/testsuite/ld-x86-64/no-plt.exp
+--- binutils.orig/ld/testsuite/ld-x86-64/no-plt.exp 2017-10-25 12:52:21.020278378 +0100
++++ binutils-2.27/ld/testsuite/ld-x86-64/no-plt.exp 2017-10-25 15:12:35.551099013 +0100
+@@ -70,15 +70,6 @@ run_cc_link_tests [list \
+ "libno-plt-1b.so" \
+ ] \
+ [list \
+- "No PLT (dynamic 1a)" \
+- "tmpdir/no-plt-check1.o tmpdir/no-plt-main1.o \
+- tmpdir/no-plt-func1.o tmpdir/no-plt-extern1.o" \
+- "" \
+- {dummy.s} \
+- {{readelf -Wr no-plt-1a.rd} {objdump -dwrj.text no-plt-1a.dd}} \
+- "no-plt-1a" \
+- ] \
+- [list \
+ "No PLT (dynamic 1b)" \
+ "tmpdir/no-plt-check1.o tmpdir/no-plt-main1.o \
+ tmpdir/libno-plt-1a.so tmpdir/libno-plt-1b.so" \
+@@ -88,33 +79,6 @@ run_cc_link_tests [list \
+ "no-plt-1b" \
+ ] \
+ [list \
+- "No PLT (dynamic 1c)" \
+- "tmpdir/no-plt-check1.o tmpdir/no-plt-main1.o \
+- tmpdir/no-plt-func1.o tmpdir/libno-plt-1b.so" \
+- "" \
+- {dummy.s} \
+- {{readelf -Wr no-plt-1c.rd} {objdump -dwrj.text no-plt-1c.dd}} \
+- "no-plt-1c" \
+- ] \
+- [list \
+- "No PLT (static 1d)" \
+- "-static tmpdir/no-plt-check1.o tmpdir/no-plt-main1.o \
+- tmpdir/no-plt-func1.o tmpdir/no-plt-extern1.o" \
+- "" \
+- {dummy.s} \
+- {{readelf -Wr no-plt-1d.rd} {objdump -dwrj.text no-plt-1d.dd}} \
+- "no-plt-1d" \
+- ] \
+- [list \
+- "No PLT (PIE 1e)" \
+- "-pie tmpdir/no-plt-check1.o tmpdir/no-plt-main1.o \
+- tmpdir/no-plt-func1.o tmpdir/no-plt-extern1.o" \
+- "" \
+- {dummy.s} \
+- {{readelf -Wr no-plt-1e.rd} {objdump -dwrj.text no-plt-1e.dd}} \
+- "no-plt-1e" \
+- ] \
+- [list \
+ "No PLT (PIE 1f)" \
+ "-pie tmpdir/no-plt-check1.o tmpdir/no-plt-main1.o \
+ tmpdir/libno-plt-1a.so tmpdir/libno-plt-1b.so" \
+@@ -123,15 +87,6 @@ run_cc_link_tests [list \
+ {{readelf -Wr no-plt-1f.rd} {objdump -dwrj.text no-plt-1f.dd}} \
+ "no-plt-1f" \
+ ] \
+- [list \
+- "No PLT (PIE 1g)" \
+- "-pie tmpdir/no-plt-check1.o tmpdir/no-plt-main1.o \
+- tmpdir/no-plt-func1.o tmpdir/libno-plt-1b.so" \
+- "" \
+- { dummy.s } \
+- {{readelf -Wr no-plt-1g.rd} {objdump -dwrj.text no-plt-1g.dd}} \
+- "no-plt-1g" \
+- ] \
+ ]
+
+ run_ld_link_exec_tests [] [list \
+diff -rup binutils.orig/ld/testsuite/ld-x86-64/pr19609-1a.d binutils-2.27/ld/testsuite/ld-x86-64/pr19609-1a.d
+--- binutils.orig/ld/testsuite/ld-x86-64/pr19609-1a.d 2017-10-25 12:52:21.029278274 +0100
++++ binutils-2.27/ld/testsuite/ld-x86-64/pr19609-1a.d 2017-10-25 15:12:35.551099013 +0100
+@@ -2,6 +2,8 @@
+ #as: --64 -mrelax-relocations=yes
+ #ld: -melf_x86_64 --no-relax
+ #objdump: -dw
++#xfail: *-*-*
++# XFAILed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed.
+
+ .*: +file format .*
+
+diff -rup binutils.orig/ld/testsuite/ld-x86-64/pr19609-1b.d binutils-2.27/ld/testsuite/ld-x86-64/pr19609-1b.d
+--- binutils.orig/ld/testsuite/ld-x86-64/pr19609-1b.d 2017-10-25 12:52:21.029278274 +0100
++++ binutils-2.27/ld/testsuite/ld-x86-64/pr19609-1b.d 2017-10-25 15:12:35.551099013 +0100
+@@ -2,6 +2,8 @@
+ #as: --64 -mrelax-relocations=yes
+ #ld: -pie -melf_x86_64 --no-dynamic-linker
+ #objdump: -dw
++#xfail: *-*-*
++# XFAILed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed.
+
+ .*: +file format .*
+
+diff -rup binutils.orig/ld/testsuite/ld-x86-64/pr19609-1d.d binutils-2.27/ld/testsuite/ld-x86-64/pr19609-1d.d
+--- binutils.orig/ld/testsuite/ld-x86-64/pr19609-1d.d 2017-10-25 12:52:21.029278274 +0100
++++ binutils-2.27/ld/testsuite/ld-x86-64/pr19609-1d.d 2017-10-25 15:12:35.551099013 +0100
+@@ -2,6 +2,8 @@
+ #as: --64 -mrelax-relocations=yes
+ #ld: -E -melf_x86_64 --no-dynamic-linker
+ #objdump: -dw
++#xfail: *-*-*
++# XFAILed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed.
+
+ .*: +file format .*
+
+diff -rup binutils.orig/ld/testsuite/ld-x86-64/pr19609-1f.d binutils-2.27/ld/testsuite/ld-x86-64/pr19609-1f.d
+--- binutils.orig/ld/testsuite/ld-x86-64/pr19609-1f.d 2017-10-25 12:52:21.029278274 +0100
++++ binutils-2.27/ld/testsuite/ld-x86-64/pr19609-1f.d 2017-10-25 15:12:35.551099013 +0100
+@@ -2,6 +2,8 @@
+ #as: --64 -mrelax-relocations=yes
+ #ld: -pie --dynamic-list-data -melf_x86_64 --no-dynamic-linker
+ #objdump: -dw
++#xfail: *-*-*
++# XFAILed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed.
+
+ .*: +file format .*
+
+diff -rup binutils.orig/ld/testsuite/ld-x86-64/pr19609-1g.d binutils-2.27/ld/testsuite/ld-x86-64/pr19609-1g.d
+--- binutils.orig/ld/testsuite/ld-x86-64/pr19609-1g.d 2017-10-25 12:52:21.029278274 +0100
++++ binutils-2.27/ld/testsuite/ld-x86-64/pr19609-1g.d 2017-10-25 15:12:35.551099013 +0100
+@@ -2,6 +2,8 @@
+ #as: --64 -mrelax-relocations=yes
+ #ld: -pie -E -melf_x86_64 --no-dynamic-linker
+ #objdump: -dw
++#xfail: *-*-*
++# XFAILed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed.
+
+ .*: +file format .*
+
+diff -rup binutils.orig/ld/testsuite/ld-x86-64/pr19609-1h.d binutils-2.27/ld/testsuite/ld-x86-64/pr19609-1h.d
+--- binutils.orig/ld/testsuite/ld-x86-64/pr19609-1h.d 2017-10-25 12:52:21.029278274 +0100
++++ binutils-2.27/ld/testsuite/ld-x86-64/pr19609-1h.d 2017-10-25 15:12:35.551099013 +0100
+@@ -2,6 +2,8 @@
+ #as: --x32 -mrelax-relocations=yes
+ #ld: -melf32_x86_64 --no-relax
+ #objdump: -dw
++#xfail: *-*-*
++# XFAILed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed.
+
+ .*: +file format .*
+
+diff -rup binutils.orig/ld/testsuite/ld-x86-64/pr19609-1i.d binutils-2.27/ld/testsuite/ld-x86-64/pr19609-1i.d
+--- binutils.orig/ld/testsuite/ld-x86-64/pr19609-1i.d 2017-10-25 12:52:21.029278274 +0100
++++ binutils-2.27/ld/testsuite/ld-x86-64/pr19609-1i.d 2017-10-25 15:12:35.551099013 +0100
+@@ -2,6 +2,8 @@
+ #as: --x32 -mrelax-relocations=yes
+ #ld: -pie -melf32_x86_64 --no-dynamic-linker
+ #objdump: -dw
++#xfail: *-*-*
++# XFAILed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed.
+
+ .*: +file format .*
+
+diff -rup binutils.orig/ld/testsuite/ld-x86-64/pr19609-1k.d binutils-2.27/ld/testsuite/ld-x86-64/pr19609-1k.d
+--- binutils.orig/ld/testsuite/ld-x86-64/pr19609-1k.d 2017-10-25 12:52:21.029278274 +0100
++++ binutils-2.27/ld/testsuite/ld-x86-64/pr19609-1k.d 2017-10-25 15:12:35.551099013 +0100
+@@ -2,6 +2,8 @@
+ #as: --64 -mrelax-relocations=yes
+ #ld: -pie -E -Bsymbolic-functions -melf_x86_64 --no-dynamic-linker
+ #objdump: -dw
++#xfail: *-*-*
++# XFAILed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed.
+
+ .*: +file format .*
+
+diff -rup binutils.orig/ld/testsuite/ld-x86-64/pr19609-2a.d binutils-2.27/ld/testsuite/ld-x86-64/pr19609-2a.d
+--- binutils.orig/ld/testsuite/ld-x86-64/pr19609-2a.d 2017-10-25 12:52:21.029278274 +0100
++++ binutils-2.27/ld/testsuite/ld-x86-64/pr19609-2a.d 2017-10-25 15:12:35.551099013 +0100
+@@ -2,3 +2,5 @@
+ #as: --64 -mrelax-relocations=yes
+ #ld: -melf_x86_64 -Ttext=0x70000000 -Tdata=0xa0000000
+ #error: .*relocation truncated to fit: R_X86_64_32S .*
++#xfail: *-*-*
++# XFAILed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed.
+diff -rup binutils.orig/ld/testsuite/ld-x86-64/pr19609-2b.d binutils-2.27/ld/testsuite/ld-x86-64/pr19609-2b.d
+--- binutils.orig/ld/testsuite/ld-x86-64/pr19609-2b.d 2017-10-25 12:52:21.029278274 +0100
++++ binutils-2.27/ld/testsuite/ld-x86-64/pr19609-2b.d 2017-10-25 15:12:35.551099013 +0100
+@@ -2,3 +2,5 @@
+ #as: --x32 -mrelax-relocations=yes
+ #ld: -melf32_x86_64 -Ttext=0x70000000 -Tdata=0xa0000000
+ #error: .*relocation truncated to fit: R_X86_64_32S .*
++#xfail: *-*-*
++# XFAILed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed.
+diff -rup binutils.orig/ld/testsuite/ld-x86-64/pr19609-3a.d binutils-2.27/ld/testsuite/ld-x86-64/pr19609-3a.d
+--- binutils.orig/ld/testsuite/ld-x86-64/pr19609-3a.d 2017-10-25 12:52:21.030278263 +0100
++++ binutils-2.27/ld/testsuite/ld-x86-64/pr19609-3a.d 2017-10-25 15:12:35.551099013 +0100
+@@ -2,6 +2,8 @@
+ #as: --64 -mrelax-relocations=yes
+ #ld: -melf_x86_64 -Ttext=0x70000000 -Tdata=0xa0000000
+ #objdump: -dw
++#xfail: *-*-*
++# XFAILed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed.
+
+ .*: +file format .*
+
+diff -rup binutils.orig/ld/testsuite/ld-x86-64/pr19609-3b.d binutils-2.27/ld/testsuite/ld-x86-64/pr19609-3b.d
+--- binutils.orig/ld/testsuite/ld-x86-64/pr19609-3b.d 2017-10-25 12:52:21.030278263 +0100
++++ binutils-2.27/ld/testsuite/ld-x86-64/pr19609-3b.d 2017-10-25 15:12:35.552099002 +0100
+@@ -2,6 +2,8 @@
+ #as: --x32 -mrelax-relocations=yes
+ #ld: -melf32_x86_64 -Ttext=0x70000000 -Tdata=0xa0000000
+ #objdump: -dw
++#xfail: *-*-*
++# XFAILed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed.
+
+ .*: +file format .*
+
+diff -rup binutils.orig/ld/testsuite/ld-x86-64/pr19609-4a.d binutils-2.27/ld/testsuite/ld-x86-64/pr19609-4a.d
+--- binutils.orig/ld/testsuite/ld-x86-64/pr19609-4a.d 2017-10-25 12:52:21.030278263 +0100
++++ binutils-2.27/ld/testsuite/ld-x86-64/pr19609-4a.d 2017-10-25 15:12:35.552099002 +0100
+@@ -3,3 +3,5 @@
+ #ld: -melf_x86_64 -Ttext=0x70000000 -Tdata=0xa0000000
+ #error: .*relocation truncated to fit: R_X86_64_32S .*
+ #error: .*relocation truncated to fit: R_X86_64_32S .*
++#xfail: *-*-*
++# XFAILed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed.
+diff -rup binutils.orig/ld/testsuite/ld-x86-64/pr19609-4b.d binutils-2.27/ld/testsuite/ld-x86-64/pr19609-4b.d
+--- binutils.orig/ld/testsuite/ld-x86-64/pr19609-4b.d 2017-10-25 12:52:21.030278263 +0100
++++ binutils-2.27/ld/testsuite/ld-x86-64/pr19609-4b.d 2017-10-25 15:12:35.552099002 +0100
+@@ -2,6 +2,8 @@
+ #as: --x32 -mrelax-relocations=yes
+ #ld: -melf32_x86_64 -Ttext=0x70000000 -Tdata=0xa0000000
+ #objdump: -dw
++#xfail: *-*-*
++# XFAILed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed.
+
+ .*: +file format .*
+
+diff -rup binutils.orig/ld/testsuite/ld-x86-64/pr19609-4c.d binutils-2.27/ld/testsuite/ld-x86-64/pr19609-4c.d
+--- binutils.orig/ld/testsuite/ld-x86-64/pr19609-4c.d 2017-10-25 12:52:21.030278263 +0100
++++ binutils-2.27/ld/testsuite/ld-x86-64/pr19609-4c.d 2017-10-25 15:12:35.552099002 +0100
+@@ -3,3 +3,5 @@
+ #ld: -melf_x86_64 -Ttext=0x70000000 -Tdata=0xa0000000
+ #error: .*relocation truncated to fit: R_X86_64_32S .*
+ #error: .*relocation truncated to fit: R_X86_64_32S .*
++#xfail: *-*-*
++# XFAILed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed.
+diff -rup binutils.orig/ld/testsuite/ld-x86-64/pr19609-4d.d binutils-2.27/ld/testsuite/ld-x86-64/pr19609-4d.d
+--- binutils.orig/ld/testsuite/ld-x86-64/pr19609-4d.d 2017-10-25 12:52:21.030278263 +0100
++++ binutils-2.27/ld/testsuite/ld-x86-64/pr19609-4d.d 2017-10-25 15:12:35.552099002 +0100
+@@ -2,6 +2,8 @@
+ #as: --x32 -mrelax-relocations=yes
+ #ld: -melf32_x86_64 -Ttext=0x70000000 -Tdata=0xa0000000
+ #objdump: -dw
++#xfail: *-*-*
++# XFAILed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed.
+
+ .*: +file format .*
+
+diff -rup binutils.orig/ld/testsuite/ld-x86-64/pr19609-5a.d binutils-2.27/ld/testsuite/ld-x86-64/pr19609-5a.d
+--- binutils.orig/ld/testsuite/ld-x86-64/pr19609-5a.d 2017-10-25 12:52:21.030278263 +0100
++++ binutils-2.27/ld/testsuite/ld-x86-64/pr19609-5a.d 2017-10-25 15:12:35.552099002 +0100
+@@ -2,6 +2,8 @@
+ #as: --64 -mrelax-relocations=yes
+ #ld: -melf_x86_64
+ #objdump: -dw
++#xfail: *-*-*
++# XFAILed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed.
+
+ .*: +file format .*
+
+diff -rup binutils.orig/ld/testsuite/ld-x86-64/pr19609-5d.d binutils-2.27/ld/testsuite/ld-x86-64/pr19609-5d.d
+--- binutils.orig/ld/testsuite/ld-x86-64/pr19609-5d.d 2017-10-25 12:52:21.030278263 +0100
++++ binutils-2.27/ld/testsuite/ld-x86-64/pr19609-5d.d 2017-10-25 15:12:35.552099002 +0100
+@@ -2,3 +2,5 @@
+ #as: --64 -mrelax-relocations=yes
+ #ld: -melf_x86_64 -Ttext=0x80000000
+ #error: .*relocation truncated to fit: R_X86_64_PC32 .*
++#xfail: *-*-*
++# XFAILed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed.
+diff -rup binutils.orig/ld/testsuite/ld-x86-64/pr19609-6a.d binutils-2.27/ld/testsuite/ld-x86-64/pr19609-6a.d
+--- binutils.orig/ld/testsuite/ld-x86-64/pr19609-6a.d 2017-10-25 12:52:21.031278251 +0100
++++ binutils-2.27/ld/testsuite/ld-x86-64/pr19609-6a.d 2017-10-25 15:12:35.552099002 +0100
+@@ -2,3 +2,5 @@
+ #as: --64 -mrelax-relocations=yes
+ #ld: -melf_x86_64 --defsym foobar=0x80000000
+ #error: .*relocation truncated to fit: R_X86_64_32S .*
++#xfail: *-*-*
++# XFAILed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed.
+diff -rup binutils.orig/ld/testsuite/ld-x86-64/pr19609-6c.d binutils-2.27/ld/testsuite/ld-x86-64/pr19609-6c.d
+--- binutils.orig/ld/testsuite/ld-x86-64/pr19609-6c.d 2017-10-25 12:52:21.031278251 +0100
++++ binutils-2.27/ld/testsuite/ld-x86-64/pr19609-6c.d 2017-10-25 15:12:35.552099002 +0100
+@@ -2,6 +2,8 @@
+ #as: --64 -mrelax-relocations=yes
+ #ld: -melf_x86_64 --defsym foobar=0x70000000
+ #objdump: -dw
++#xfail: *-*-*
++# XFAILed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed.
+
+ .*: +file format .*
+
+diff -rup binutils.orig/ld/testsuite/ld-x86-64/pr19609-6d.d binutils-2.27/ld/testsuite/ld-x86-64/pr19609-6d.d
+--- binutils.orig/ld/testsuite/ld-x86-64/pr19609-6d.d 2017-10-25 12:52:21.031278251 +0100
++++ binutils-2.27/ld/testsuite/ld-x86-64/pr19609-6d.d 2017-10-25 15:12:35.552099002 +0100
+@@ -2,6 +2,8 @@
+ #as: --x32 -mrelax-relocations=yes
+ #ld: -melf32_x86_64 --defsym foobar=0x80000000
+ #objdump: -dw
++#xfail: *-*-*
++# XFAILed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed.
+
+ .*: +file format .*
+
+diff -rup binutils.orig/ld/testsuite/ld-x86-64/pr19609-7a.d binutils-2.27/ld/testsuite/ld-x86-64/pr19609-7a.d
+--- binutils.orig/ld/testsuite/ld-x86-64/pr19609-7a.d 2017-10-25 12:52:21.031278251 +0100
++++ binutils-2.27/ld/testsuite/ld-x86-64/pr19609-7a.d 2017-10-25 15:12:35.552099002 +0100
+@@ -2,3 +2,5 @@
+ #as: --64 -mrelax-relocations=yes
+ #ld: -melf_x86_64 -Ttext=0x80000000
+ #error: .*relocation truncated to fit: R_X86_64_PC32 .*
++#xfail: *-*-*
++# XFAILed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed.
+diff -rup binutils.orig/ld/testsuite/ld-x86-64/pr19609-7c.d binutils-2.27/ld/testsuite/ld-x86-64/pr19609-7c.d
+--- binutils.orig/ld/testsuite/ld-x86-64/pr19609-7c.d 2017-10-25 12:52:21.031278251 +0100
++++ binutils-2.27/ld/testsuite/ld-x86-64/pr19609-7c.d 2017-10-25 15:12:35.552099002 +0100
+@@ -2,3 +2,5 @@
+ #as: --x32 -mrelax-relocations=yes
+ #ld: -melf32_x86_64 -Ttext=0x80000000
+ #error: .*relocation truncated to fit: R_X86_64_PC32 .*
++#xfail: *-*-*
++# XFAILed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed.
+diff -rup binutils.orig/ld/testsuite/ld-x86-64/tls.exp binutils-2.27/ld/testsuite/ld-x86-64/tls.exp
+--- binutils.orig/ld/testsuite/ld-x86-64/tls.exp 2017-10-25 12:52:21.036278193 +0100
++++ binutils-2.27/ld/testsuite/ld-x86-64/tls.exp 2017-10-25 15:12:35.552099002 +0100
+@@ -69,42 +69,6 @@ run_cc_link_tests [list \
+
+ run_ld_link_exec_tests [] [list \
+ [list \
+- "TLS GD/LD -> LE transition without PLT (dynamic)" \
+- "tmpdir/tls-def1.o tmpdir/tls-main1.o tmpdir/tls-gd1.o \
+- tmpdir/tls-ld1.o" \
+- "" \
+- { dummy.s } \
+- "tls-1a" \
+- "pass.out" \
+- ] \
+- [list \
+- "TLS GD/LD -> LE transition without PLT (PIE)" \
+- "-pie tmpdir/tls-def1.o tmpdir/tls-main1.o tmpdir/tls-gd1.o \
+- tmpdir/tls-ld1.o" \
+- "" \
+- { dummy.s } \
+- "tls-1b" \
+- "pass.out" \
+- ] \
+- [list \
+- "TLS GD/LD -> LE transition without PLT (static)" \
+- "-static tmpdir/tls-def1.o tmpdir/tls-main1.o tmpdir/tls-gd1.o \
+- tmpdir/tls-ld1.o" \
+- "" \
+- { dummy.s } \
+- "tls-1c" \
+- "pass.out" \
+- ] \
+- [list \
+- "TLS GD/LD -> IE transition without PLT" \
+- "tmpdir/tls-main1.o tmpdir/tls-gd1.o tmpdir/tls-ld1.o \
+- tmpdir/libtls-1a.so -R tmpdir" \
+- "" \
+- { dummy.s } \
+- "tls-1d" \
+- "pass.out" \
+- ] \
+- [list \
+ "TLS without PLT (1)" \
+ "tmpdir/tls-main1.o \
+ tmpdir/libtls-1a.so tmpdir/libtls-1b.so -R tmpdir" \
+diff -rup binutils.orig/ld/testsuite/ld-x86-64/tlspie2a.d binutils-2.27/ld/testsuite/ld-x86-64/tlspie2a.d
+--- binutils.orig/ld/testsuite/ld-x86-64/tlspie2a.d 2017-10-25 12:52:21.039278158 +0100
++++ binutils-2.27/ld/testsuite/ld-x86-64/tlspie2a.d 2017-10-25 15:12:35.552099002 +0100
+@@ -2,5 +2,7 @@
+ #as: --64 -mrelax-relocations=yes
+ #ld: -melf_x86_64 -pie
+ #readelf: -r
++#xfail: *-*-*
++# XFAILed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed.
+
+ There are no relocations in this file.
+diff -rup binutils.orig/ld/testsuite/ld-x86-64/tlspie2b.d binutils-2.27/ld/testsuite/ld-x86-64/tlspie2b.d
+--- binutils.orig/ld/testsuite/ld-x86-64/tlspie2b.d 2017-10-25 12:52:21.039278158 +0100
++++ binutils-2.27/ld/testsuite/ld-x86-64/tlspie2b.d 2017-10-25 15:12:35.552099002 +0100
+@@ -2,6 +2,8 @@
+ #as: --64 -mrelax-relocations=yes
+ #ld: -melf_x86_64 -pie
+ #objdump: -dwr
++#xfail: *-*-*
++# XFAILed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed.
+
+ .*: +file format .*
+
+diff -rup binutils.orig/ld/testsuite/ld-x86-64/tlspie2c.d binutils-2.27/ld/testsuite/ld-x86-64/tlspie2c.d
+--- binutils.orig/ld/testsuite/ld-x86-64/tlspie2c.d 2017-10-25 12:52:21.039278158 +0100
++++ binutils-2.27/ld/testsuite/ld-x86-64/tlspie2c.d 2017-10-25 15:12:35.553098990 +0100
+@@ -2,6 +2,8 @@
+ #as: --64 -mrelax-relocations=yes
+ #ld: -melf_x86_64 -pie -z call-nop=suffix-nop
+ #objdump: -dwr
++#xfail: *-*-*
++# XFAILed because generation of the R_X86_64_REX_GOTPCRELX and R_X86_64_GOTPCRELX relocs is currently suppressed.
+
+ .*: +file format .*
+
+diff -rup binutils.orig/ld/testsuite/ld-x86-64/x86-64.exp binutils-2.27/ld/testsuite/ld-x86-64/x86-64.exp
+--- binutils.orig/ld/testsuite/ld-x86-64/x86-64.exp 2017-10-25 12:52:21.040278147 +0100
++++ binutils-2.27/ld/testsuite/ld-x86-64/x86-64.exp 2017-10-25 15:12:35.553098990 +0100
+@@ -55,13 +55,6 @@ set x86_64tests {
+ {{readelf -WSsrl tlspic.rd} {objdump -drj.text\ -Mintel64 tlspic.dd}
+ {objdump -sj.got tlspic.sd} {objdump -sj.tdata tlspic.td}}
+ "libtlspic.so"}
+- {"TLS -fpic -shared transitions with r15 as GOT base"
+- "-shared -melf_x86_64 --no-ld-generated-unwind-info" ""
+- "--64 -mrelax-relocations=yes"
+- {tlspic3.s tlspic2.s}
+- {{readelf -WSsrl tlspic2.rd} {objdump -drj.text\ -Mintel64 tlspic2.dd}
+- {objdump -sj.got tlspic2.sd} {objdump -sj.tdata tlspic2.td}}
+- "libtlspic2.so"}
+ {"TLS descriptor -fpic -shared transitions"
+ "-shared -melf_x86_64 --no-ld-generated-unwind-info" ""
+ "--64" {tlsdesc.s tlspic2.s}
+@@ -76,12 +69,6 @@ set x86_64tests {
+ {{readelf -WSsrl tlsbin.rd} {objdump -drj.text tlsbin.dd}
+ {objdump -sj.got tlsbin.sd} {objdump -sj.tdata tlsbin.td}}
+ "tlsbin"}
+- {"TLS -fpic and -fno-pic exec transitions without PLT"
+- "-melf_x86_64 tmpdir/libtlslib.so --no-ld-generated-unwind-info" ""
+- "-mrelax-relocations=yes --64" {tlsbinpic2.s tlsbin.s}
+- {{readelf -WSsrl tlsbin2.rd} {objdump -drj.text tlsbin2.dd}
+- {objdump -sj.got tlsbin2.sd} {objdump -sj.tdata tlsbin2.td}}
+- "tlsbin2"}
+ {"TLS descriptor -fpic and -fno-pic exec transitions"
+ "-melf_x86_64 tmpdir/libtlslib.so --no-ld-generated-unwind-info" ""
+ "--64" {tlsbindesc.s tlsbin.s}
+@@ -128,19 +115,11 @@ set x86_64tests {
+ {"TLS GD->IE transition" "-melf_x86_64 tmpdir/libtlsgd5.so" ""
+ "--64" {tlsgd5a.s}
+ {{objdump -dwr tlsgd5.dd}} "tlsgd5a"}
+- {"TLS GD->IE transition without PLT"
+- "-melf_x86_64 tmpdir/libtlsgd5.so" ""
+- "-mrelax-relocations=yes --64" {tlsgd5c.s}
+- {{objdump -dwr tlsgd5.dd}} "tlsgd5b"}
+ {"Helper TLS X32 GD->IE transition DSO" "-shared -melf32_x86_64" ""
+ "--x32" {tlsgd6b.s} {} "libtlsgd6.so"}
+ {"TLS X32 GD->IE transition" "-melf32_x86_64 tmpdir/libtlsgd6.so" ""
+ "--x32" {tlsgd6a.s}
+ {{objdump -dwr tlsgd6.dd}} "tlsgd6a"}
+- {"TLS X32 GD->IE transition without PLT"
+- "-melf32_x86_64 tmpdir/libtlsgd6.so" ""
+- "-mrelax-relocations=yes --x32" {tlsgd6c.s}
+- {{objdump -dwr tlsgd6.dd}} "tlsgd6b"}
+ {"TLS X32 LD->LE transition" "-melf32_x86_64" ""
+ "--x32" {tlsld2.s}
+ {{objdump -dwr tlsld2.dd}} "tlsld2"}
+@@ -154,15 +133,6 @@ set x86_64tests {
+ "-melf_x86_64" ""
+ "--64" {tlsld4.s}
+ {{objdump -dwr tlsld4.dd}} "tlsld4"}
+- {"TLS LD->LE transition without PLT"
+- "-melf_x86_64" ""
+- "--64 -mrelax-relocations=yes"
+- {tlsld5.s}
+- {{objdump -dwr tlsld5.dd}} "tlsld5"}
+- {"TLS X32 LD->LE transition without PLT" "-melf32_x86_64" ""
+- "--x32 -mrelax-relocations=yes"
+- {tlsld6.s}
+- {{objdump -dwr tlsld6.dd}} "tlsld6"}
+ {"TLS -mcmodel=large GD->IE transition" "-melf_x86_64 tmpdir/libtlsgd5.so" ""
+ "--64" {tlsgd8.s}
+ {{objdump -dwrj.text tlsgd8.dd}} "tlsgd8"}
+@@ -620,7 +590,7 @@ if { [isnative] && [which $CC] != 0 } {
+ "" \
+ "-fPIC -Wa,-mrelax-relocations=yes" \
+ { plt-main1.c } \
+- {{readelf {-Wr} plt-main1.rd}} \
++ {} \
+ "libplt-main1.a" \
+ ] \
+ [list \
+@@ -644,7 +614,7 @@ if { [isnative] && [which $CC] != 0 } {
+ "" \
+ "-fPIC -Wa,-mrelax-relocations=yes $PLT_CFLAGS" \
+ { plt-main4.c } \
+- {{readelf {-Wr} plt-main4.rd}} \
++ {} \
+ "libplt-main4.a" \
+ ] \
+ [list \
+@@ -799,14 +769,6 @@ if { [isnative] && [which $CC] != 0 } {
+ { gotpcrel1a.S gotpcrel1b.c gotpcrel1c.c } \
+ ] \
+ [list \
+- "Build gotpcrel1" \
+- "-Wl,--as-needed tmpdir/gotpcrel1a.o tmpdir/gotpcrel1b.o tmpdir/gotpcrel1c.o tmpdir/gotpcrel1d.so" \
+- { dummy.s } \
+- "" \
+- {{objdump {-dw} gotpcrel1.dd}} \
+- "gotpcrel1" \
+- ] \
+- [list \
+ "Build pr19319.so" \
+ "-shared" \
+ "" \
+--- binutils.orig/ld/testsuite/ld-x86-64/x86-64.exp 2019-04-15 13:13:09.203928459 +0100
++++ binutils-2.27/ld/testsuite/ld-x86-64/x86-64.exp 2019-04-15 13:15:31.960858042 +0100
+@@ -623,7 +623,7 @@ if { [isnative] && [which $CC] != 0 } {
+ tmpdir/plt-main4.o tmpdir/libplt-lib.so" \
+ "" \
+ { plt-main5.c } \
+- {{readelf {-Wr} plt-main.rd}} \
++ {} \
+ "plt-main" \
+ ] \
+ [list \
+@@ -632,7 +632,7 @@ if { [isnative] && [which $CC] != 0 } {
+ tmpdir/plt-main4.o tmpdir/libplt-lib.so -pie" \
+ "-fPIC" \
+ { plt-main5.c } \
+- {{readelf {-Wr} plt-main.rd}} \
++ {} \
+ "plt-main" \
+ ] \
+ [list \
+@@ -866,7 +866,7 @@ if { [isnative] && [which $CC] != 0 } {
+ tmpdir/plt-main4.o tmpdir/libplt-lib.so -z bndplt" \
+ "" \
+ { plt-main5.c } \
+- {{objdump {-drw} plt-main-bnd.dd}} \
++ {} \
+ "plt-main-bnd" \
+ ] \
+ [list \
+@@ -875,7 +875,7 @@ if { [isnative] && [which $CC] != 0 } {
+ tmpdir/plt-main4.o tmpdir/libplt-lib.so -z bndplt -pie" \
+ "-fPIC" \
+ { plt-main5.c } \
+- {{objdump {-drw} plt-main-bnd.dd}} \
++ {} \
+ "plt-main-pie-bnd" \
+ ] \
+ ]
+@@ -916,5 +916,5 @@ if { ![istarget "x86_64-*-linux*"]} {
+
+ # Linux only tests
+ run_dump_test "pr17618"
+-run_dump_test "pltgot-1"
+-run_dump_test "pltgot-2"
++# run_dump_test "pltgot-1"
++# run_dump_test "pltgot-2"
diff --git a/SOURCES/binutils-CVE-2018-1000876.patch b/SOURCES/binutils-CVE-2018-1000876.patch
new file mode 100644
index 0000000..caf1f63
--- /dev/null
+++ b/SOURCES/binutils-CVE-2018-1000876.patch
@@ -0,0 +1,151 @@
+diff -rup binutils.orig/bfd/aoutx.h binutils-2.27/bfd/aoutx.h
+--- binutils.orig/bfd/aoutx.h 2019-01-14 16:10:59.344958851 +0000
++++ binutils-2.27/bfd/aoutx.h 2019-01-14 16:11:46.893598783 +0000
+@@ -118,6 +118,7 @@ DESCRIPTION
+ #define KEEPIT udata.i
+
+ #include "sysdep.h"
++#include <limits.h>
+ #include "bfd.h"
+ #include "safe-ctype.h"
+ #include "bfdlink.h"
+@@ -2465,6 +2466,8 @@ NAME (aout, canonicalize_reloc) (bfd *ab
+ long
+ NAME (aout, get_reloc_upper_bound) (bfd *abfd, sec_ptr asect)
+ {
++ bfd_size_type count;
++
+ if (bfd_get_format (abfd) != bfd_object)
+ {
+ bfd_set_error (bfd_error_invalid_operation);
+@@ -2472,26 +2475,25 @@ NAME (aout, get_reloc_upper_bound) (bfd
+ }
+
+ if (asect->flags & SEC_CONSTRUCTOR)
+- return sizeof (arelent *) * (asect->reloc_count + 1);
+-
+- if (asect == obj_datasec (abfd))
+- return sizeof (arelent *)
+- * ((exec_hdr (abfd)->a_drsize / obj_reloc_entry_size (abfd))
+- + 1);
+-
+- if (asect == obj_textsec (abfd))
+- return sizeof (arelent *)
+- * ((exec_hdr (abfd)->a_trsize / obj_reloc_entry_size (abfd))
+- + 1);
+-
+- if (asect == obj_bsssec (abfd))
+- return sizeof (arelent *);
+-
+- if (asect == obj_bsssec (abfd))
+- return 0;
++ count = asect->reloc_count;
++ else if (asect == obj_datasec (abfd))
++ count = exec_hdr (abfd)->a_drsize / obj_reloc_entry_size (abfd);
++ else if (asect == obj_textsec (abfd))
++ count = exec_hdr (abfd)->a_trsize / obj_reloc_entry_size (abfd);
++ else if (asect == obj_bsssec (abfd))
++ count = 0;
++ else
++ {
++ bfd_set_error (bfd_error_invalid_operation);
++ return -1;
++ }
+
+- bfd_set_error (bfd_error_invalid_operation);
+- return -1;
++ if (count >= LONG_MAX / sizeof (arelent *))
++ {
++ bfd_set_error (bfd_error_file_too_big);
++ return -1;
++ }
++ return (count + 1) * sizeof (arelent *);
+ }
+
+ long
+diff -rup binutils.orig/bfd/elf.c binutils-2.27/bfd/elf.c
+--- binutils.orig/bfd/elf.c 2019-01-14 16:10:59.331958950 +0000
++++ binutils-2.27/bfd/elf.c 2019-01-14 16:11:52.525556135 +0000
+@@ -35,6 +35,7 @@ SECTION
+ /* For sparc64-cross-sparc32. */
+ #define _SYSCALL32
+ #include "sysdep.h"
++#include <limits.h>
+ #include "bfd.h"
+ #include "bfdlink.h"
+ #include "libbfd.h"
+@@ -7769,11 +7770,16 @@ Unable to find equivalent output section
+ long
+ _bfd_elf_get_symtab_upper_bound (bfd *abfd)
+ {
+- long symcount;
++ bfd_size_type symcount;
+ long symtab_size;
+ Elf_Internal_Shdr *hdr = &elf_tdata (abfd)->symtab_hdr;
+
+ symcount = hdr->sh_size / get_elf_backend_data (abfd)->s->sizeof_sym;
++ if (symcount >= LONG_MAX / sizeof (asymbol *))
++ {
++ bfd_set_error (bfd_error_file_too_big);
++ return -1;
++ }
+ symtab_size = (symcount + 1) * (sizeof (asymbol *));
+ if (symcount > 0)
+ symtab_size -= sizeof (asymbol *);
+@@ -7784,7 +7790,7 @@ _bfd_elf_get_symtab_upper_bound (bfd *ab
+ long
+ _bfd_elf_get_dynamic_symtab_upper_bound (bfd *abfd)
+ {
+- long symcount;
++ bfd_size_type symcount;
+ long symtab_size;
+ Elf_Internal_Shdr *hdr = &elf_tdata (abfd)->dynsymtab_hdr;
+
+@@ -7795,6 +7801,11 @@ _bfd_elf_get_dynamic_symtab_upper_bound
+ }
+
+ symcount = hdr->sh_size / get_elf_backend_data (abfd)->s->sizeof_sym;
++ if (symcount >= LONG_MAX / sizeof (asymbol *))
++ {
++ bfd_set_error (bfd_error_file_too_big);
++ return -1;
++ }
+ symtab_size = (symcount + 1) * (sizeof (asymbol *));
+ if (symcount > 0)
+ symtab_size -= sizeof (asymbol *);
+@@ -7864,7 +7875,7 @@ _bfd_elf_canonicalize_dynamic_symtab (bf
+ long
+ _bfd_elf_get_dynamic_reloc_upper_bound (bfd *abfd)
+ {
+- long ret;
++ bfd_size_type count;
+ asection *s;
+
+ if (elf_dynsymtab (abfd) == 0)
+@@ -7873,15 +7884,20 @@ _bfd_elf_get_dynamic_reloc_upper_bound (
+ return -1;
+ }
+
+- ret = sizeof (arelent *);
++ count = 1;
+ for (s = abfd->sections; s != NULL; s = s->next)
+ if (elf_section_data (s)->this_hdr.sh_link == elf_dynsymtab (abfd)
+ && (elf_section_data (s)->this_hdr.sh_type == SHT_REL
+ || elf_section_data (s)->this_hdr.sh_type == SHT_RELA))
+- ret += ((s->size / elf_section_data (s)->this_hdr.sh_entsize)
+- * sizeof (arelent *));
+-
+- return ret;
++ {
++ count += s->size / elf_section_data (s)->this_hdr.sh_entsize;
++ if (count > LONG_MAX / sizeof (arelent *))
++ {
++ bfd_set_error (bfd_error_file_too_big);
++ return -1;
++ }
++ }
++ return count * sizeof (arelent *);
+ }
+
+ /* Canonicalize the dynamic relocation entries. Note that we return the
+
diff --git a/SOURCES/binutils-CVE-2018-10372.patch b/SOURCES/binutils-CVE-2018-10372.patch
new file mode 100644
index 0000000..073a407
--- /dev/null
+++ b/SOURCES/binutils-CVE-2018-10372.patch
@@ -0,0 +1,22 @@
+--- binutils.orig/binutils/dwarf.c 2018-05-01 11:42:02.656431736 +0100
++++ binutils-2.30/binutils/dwarf.c 2018-05-01 11:43:24.210383020 +0100
+@@ -9244,7 +9244,18 @@ process_cu_tu_index (struct dwarf_sectio
+ }
+
+ if (!do_display)
+- memcpy (&this_set[row - 1].signature, ph, sizeof (uint64_t));
++ {
++ size_t num_copy = sizeof (uint64_t);
++
++ /* PR 23064: Beware of buffer overflow. */
++ if (ph + num_copy < limit)
++ memcpy (&this_set[row - 1].signature, ph, num_copy);
++ else
++ {
++ warn (_("Signature (%p) extends beyond end of space in section\n"), ph);
++ return 0;
++ }
++ }
+
+ prow = poffsets + (row - 1) * ncols * 4;
+ /* PR 17531: file: b8ce60a8. */
diff --git a/SOURCES/binutils-CVE-2018-10373.patch b/SOURCES/binutils-CVE-2018-10373.patch
new file mode 100644
index 0000000..239f257
--- /dev/null
+++ b/SOURCES/binutils-CVE-2018-10373.patch
@@ -0,0 +1,11 @@
+--- binutils.orig/bfd/dwarf2.c 2018-05-17 11:46:03.916280930 +0100
++++ binutils-2.27/bfd/dwarf2.c 2018-05-17 12:11:45.193856898 +0100
+@@ -1471,7 +1471,7 @@ concat_filename (struct line_info_table
+ {
+ char *filename;
+
+- if (file - 1 >= table->num_files)
++ if (table == NULL || file - 1 >= table->num_files)
+ {
+ /* FILE == 0 means unknown. */
+ if (file)
diff --git a/SOURCES/binutils-CVE-2018-10534.patch b/SOURCES/binutils-CVE-2018-10534.patch
new file mode 100644
index 0000000..4a1fc8a
--- /dev/null
+++ b/SOURCES/binutils-CVE-2018-10534.patch
@@ -0,0 +1,18 @@
+--- binutils.orig/bfd/peXXigen.c 2018-05-17 11:46:03.979280220 +0100
++++ binutils-2.27/bfd/peXXigen.c 2018-05-17 12:56:36.402304487 +0100
+@@ -2964,6 +2964,15 @@ _bfd_XX_bfd_copy_private_bfd_data_common
+ bfd_get_section_size (section) - (addr - section->vma));
+ return FALSE;
+ }
++ /* PR 23110. */
++ else if (ope->pe_opthdr.DataDirectory[PE_DEBUG_DATA].Size < 0)
++ {
++ /* xgettext:c-format */
++ _bfd_error_handler
++ (_("%pB: Data Directory size (%#lx) is negative"),
++ obfd, ope->pe_opthdr.DataDirectory[PE_DEBUG_DATA].Size);
++ return FALSE;
++ }
+
+ for (i = 0; i < ope->pe_opthdr.DataDirectory[PE_DEBUG_DATA].Size
+ / sizeof (struct external_IMAGE_DEBUG_DIRECTORY); i++)
diff --git a/SOURCES/binutils-CVE-2018-10535.patch b/SOURCES/binutils-CVE-2018-10535.patch
new file mode 100644
index 0000000..212d53c
--- /dev/null
+++ b/SOURCES/binutils-CVE-2018-10535.patch
@@ -0,0 +1,28 @@
+--- binutils.orig/bfd/elf.c 2018-05-17 11:46:03.983280175 +0100
++++ binutils-2.27/bfd/elf.c 2018-05-17 11:48:01.560955253 +0100
+@@ -3878,16 +3878,23 @@ ignore_section_sym (bfd *abfd, asymbol *
+ {
+ elf_symbol_type *type_ptr;
+
++ if (sym == NULL)
++ return FALSE;
++
+ if ((sym->flags & BSF_SECTION_SYM) == 0)
+ return FALSE;
+
++ if (sym->section == NULL)
++ return TRUE;
++
+ type_ptr = elf_symbol_from (abfd, sym);
+ return ((type_ptr != NULL
+ && type_ptr->internal_elf_sym.st_shndx != 0
+ && bfd_is_abs_section (sym->section))
+ || !(sym->section->owner == abfd
+- || (sym->section->output_section->owner == abfd
+- && sym->section->output_offset == 0)
++ || (sym->section->output_section != NULL
++ && sym->section->output_section->owner == abfd
++ && sym->section->output_offset == 0)
+ || bfd_is_abs_section (sym->section)));
+ }
+
diff --git a/SOURCES/binutils-CVE-2018-7208.patch b/SOURCES/binutils-CVE-2018-7208.patch
new file mode 100644
index 0000000..98f0a6b
--- /dev/null
+++ b/SOURCES/binutils-CVE-2018-7208.patch
@@ -0,0 +1,12 @@
+--- binutils.orig/bfd/coffgen.c 2018-05-15 17:25:27.653131326 +0100
++++ binutils-2.27/bfd/coffgen.c 2018-05-15 17:41:49.604116561 +0100
+@@ -1552,7 +1552,8 @@ coff_pointerize_aux (bfd *abfd,
+ }
+ /* A negative tagndx is meaningless, but the SCO 3.2v4 cc can
+ generate one, so we must be careful to ignore it. */
+- if (auxent->u.auxent.x_sym.x_tagndx.l > 0)
++ if ((unsigned long) auxent->u.auxent.x_sym.x_tagndx.l
++ < obj_raw_syment_count (abfd))
+ {
+ auxent->u.auxent.x_sym.x_tagndx.p =
+ table_base + auxent->u.auxent.x_sym.x_tagndx.l;
diff --git a/SOURCES/binutils-CVE-2018-7568.patch b/SOURCES/binutils-CVE-2018-7568.patch
new file mode 100644
index 0000000..481ea14
--- /dev/null
+++ b/SOURCES/binutils-CVE-2018-7568.patch
@@ -0,0 +1,80 @@
+--- binutils.orig/bfd/dwarf1.c 2018-05-15 17:25:27.656131299 +0100
++++ binutils-2.27/bfd/dwarf1.c 2018-05-15 17:29:04.176057372 +0100
+@@ -208,6 +208,7 @@ parse_die (bfd * abfd,
+ /* Then the attributes. */
+ while (xptr < (this_die + aDieInfo->length))
+ {
++ unsigned int block_len;
+ unsigned short attr;
+
+ /* Parse the attribute based on its form. This section
+@@ -223,12 +224,15 @@ parse_die (bfd * abfd,
+ break;
+ case FORM_DATA4:
+ case FORM_REF:
+- if (attr == AT_sibling)
+- aDieInfo->sibling = bfd_get_32 (abfd, (bfd_byte *) xptr);
+- else if (attr == AT_stmt_list)
++ if (xptr + 4 <= aDiePtrEnd)
+ {
+- aDieInfo->stmt_list_offset = bfd_get_32 (abfd, (bfd_byte *) xptr);
+- aDieInfo->has_stmt_list = 1;
++ if (attr == AT_sibling)
++ aDieInfo->sibling = bfd_get_32 (abfd, xptr);
++ else if (attr == AT_stmt_list)
++ {
++ aDieInfo->stmt_list_offset = bfd_get_32 (abfd, xptr);
++ aDieInfo->has_stmt_list = 1;
++ }
+ }
+ xptr += 4;
+ break;
+@@ -236,22 +240,41 @@ parse_die (bfd * abfd,
+ xptr += 8;
+ break;
+ case FORM_ADDR:
+- if (attr == AT_low_pc)
+- aDieInfo->low_pc = bfd_get_32 (abfd, (bfd_byte *) xptr);
+- else if (attr == AT_high_pc)
+- aDieInfo->high_pc = bfd_get_32 (abfd, (bfd_byte *) xptr);
++ if (xptr + 4 <= aDiePtrEnd)
++ {
++ if (attr == AT_low_pc)
++ aDieInfo->low_pc = bfd_get_32 (abfd, xptr);
++ else if (attr == AT_high_pc)
++ aDieInfo->high_pc = bfd_get_32 (abfd, xptr);
++ }
+ xptr += 4;
+ break;
+ case FORM_BLOCK2:
+- xptr += 2 + bfd_get_16 (abfd, (bfd_byte *) xptr);
++ if (xptr + 2 <= aDiePtrEnd)
++ {
++ block_len = bfd_get_16 (abfd, xptr);
++ if (xptr + block_len > aDiePtrEnd
++ || xptr + block_len < xptr)
++ return FALSE;
++ xptr += block_len;
++ }
++ xptr += 2;
+ break;
+ case FORM_BLOCK4:
+- xptr += 4 + bfd_get_32 (abfd, (bfd_byte *) xptr);
++ if (xptr + 4 <= aDiePtrEnd)
++ {
++ block_len = bfd_get_32 (abfd, xptr);
++ if (xptr + block_len > aDiePtrEnd
++ || xptr + block_len < xptr)
++ return FALSE;
++ xptr += block_len;
++ }
++ xptr += 4;
+ break;
+ case FORM_STRING:
+ if (attr == AT_name)
+ aDieInfo->name = (char *) xptr;
+- xptr += strlen ((char *) xptr) + 1;
++ xptr += strnlen ((char *) xptr, aDiePtrEnd - xptr) + 1;
+ break;
+ }
+ }
diff --git a/SOURCES/binutils-CVE-2018-7569.patch b/SOURCES/binutils-CVE-2018-7569.patch
new file mode 100644
index 0000000..3141bd9
--- /dev/null
+++ b/SOURCES/binutils-CVE-2018-7569.patch
@@ -0,0 +1,74 @@
+--- binutils.orig/bfd/dwarf2.c 2018-05-15 17:25:27.661131255 +0100
++++ binutils-2.27/bfd/dwarf2.c 2018-05-15 17:38:16.900598281 +0100
+@@ -606,14 +606,24 @@ read_8_bytes (bfd *abfd, bfd_byte *buf,
+ }
+
+ static bfd_byte *
+-read_n_bytes (bfd *abfd ATTRIBUTE_UNUSED,
+- bfd_byte *buf,
+- bfd_byte *end,
+- unsigned int size ATTRIBUTE_UNUSED)
++read_n_bytes (bfd_byte * buf,
++ bfd_byte * end,
++ struct dwarf_block * block)
+ {
+- if (buf + size > end)
+- return NULL;
+- return buf;
++ unsigned int size = block->size;
++ bfd_byte * block_end = buf + size;
++
++ if (block_end > end || block_end < buf)
++ {
++ block->data = NULL;
++ block->size = 0;
++ return end;
++ }
++ else
++ {
++ block->data = buf;
++ return block_end;
++ }
+ }
+
+ /* Scans a NUL terminated string starting at BUF, returning a pointer to it.
+@@ -1053,8 +1063,7 @@ read_attribute_value (struct attribute *
+ return NULL;
+ blk->size = read_2_bytes (abfd, info_ptr, info_ptr_end);
+ info_ptr += 2;
+- blk->data = read_n_bytes (abfd, info_ptr, info_ptr_end, blk->size);
+- info_ptr += blk->size;
++ info_ptr = read_n_bytes (info_ptr, info_ptr_end, blk);
+ attr->u.blk = blk;
+ break;
+ case DW_FORM_block4:
+@@ -1064,8 +1073,7 @@ read_attribute_value (struct attribute *
+ return NULL;
+ blk->size = read_4_bytes (abfd, info_ptr, info_ptr_end);
+ info_ptr += 4;
+- blk->data = read_n_bytes (abfd, info_ptr, info_ptr_end, blk->size);
+- info_ptr += blk->size;
++ info_ptr = read_n_bytes (info_ptr, info_ptr_end, blk);
+ attr->u.blk = blk;
+ break;
+ case DW_FORM_data2:
+@@ -1100,8 +1108,7 @@ read_attribute_value (struct attribute *
+ return NULL;
+ blk->size = safe_read_leb128 (abfd, info_ptr, &bytes_read, FALSE, info_ptr_end);
+ info_ptr += bytes_read;
+- blk->data = read_n_bytes (abfd, info_ptr, info_ptr_end, blk->size);
+- info_ptr += blk->size;
++ info_ptr = read_n_bytes (info_ptr, info_ptr_end, blk);
+ attr->u.blk = blk;
+ break;
+ case DW_FORM_block1:
+@@ -1111,8 +1118,7 @@ read_attribute_value (struct attribute *
+ return NULL;
+ blk->size = read_1_byte (abfd, info_ptr, info_ptr_end);
+ info_ptr += 1;
+- blk->data = read_n_bytes (abfd, info_ptr, info_ptr_end, blk->size);
+- info_ptr += blk->size;
++ info_ptr = read_n_bytes (info_ptr, info_ptr_end, blk);
+ attr->u.blk = blk;
+ break;
+ case DW_FORM_data1:
diff --git a/SOURCES/binutils-CVE-2018-7642.patch b/SOURCES/binutils-CVE-2018-7642.patch
new file mode 100644
index 0000000..dd690ec
--- /dev/null
+++ b/SOURCES/binutils-CVE-2018-7642.patch
@@ -0,0 +1,32 @@
+--- binutils.orig/bfd/aoutx.h 2018-05-29 17:35:09.220062492 +0100
++++ binutils-2.27/bfd/aoutx.h 2018-05-29 17:37:09.131765293 +0100
+@@ -1713,7 +1713,13 @@ NAME (aout, translate_symbol_table) (bfd
+ else if (x < strsize)
+ in->symbol.name = str + x;
+ else
+- return FALSE;
++ {
++ _bfd_error_handler
++ (_("%B: invalid string offset %lx >= %lx"),
++ abfd, (long) x, (long) strsize);
++ bfd_set_error (bfd_error_bad_value);
++ return FALSE;
++ }
+
+ in->symbol.value = GET_SWORD (abfd, ext->e_value);
+ in->desc = H_GET_16 (abfd, ext->e_desc);
+@@ -2261,10 +2267,12 @@ NAME (aout, swap_std_reloc_in) (bfd *abf
+ if (r_baserel)
+ r_extern = 1;
+
+- if (r_extern && r_index > symcount)
++ if (r_extern && r_index >= symcount)
+ {
+ /* We could arrange to return an error, but it might be useful
+- to see the file even if it is bad. */
++ to see the file even if it is bad. FIXME: Of course this
++ means that objdump -r *doesn't* see the actual reloc, and
++ objcopy silently writes a different reloc. */
+ r_extern = 0;
+ r_index = N_ABS;
+ }
diff --git a/SOURCES/binutils-CVE-2018-7643.patch b/SOURCES/binutils-CVE-2018-7643.patch
new file mode 100644
index 0000000..7a4ed19
--- /dev/null
+++ b/SOURCES/binutils-CVE-2018-7643.patch
@@ -0,0 +1,17 @@
+diff -rup binutils.orig/binutils/dwarf.c binutils-2.27/binutils/dwarf.c
+--- binutils.orig/binutils/dwarf.c 2018-05-30 09:57:23.401080405 +0100
++++ binutils-2.27/binutils/dwarf.c 2018-05-30 09:57:33.578971357 +0100
+@@ -5195,6 +5195,13 @@ display_debug_ranges (struct dwarf_secti
+ continue;
+ }
+
++ if (next < section_begin || next >= finish)
++ {
++ warn (_("Corrupt offset (%#8.8lx) in range entry %u\n"),
++ (unsigned long) offset, i);
++ continue;
++ }
++
+ if (dwarf_check != 0 && i > 0)
+ {
+ if (start < next)
diff --git a/SOURCES/binutils-CVE-2018-8945.patch b/SOURCES/binutils-CVE-2018-8945.patch
new file mode 100644
index 0000000..de25cba
--- /dev/null
+++ b/SOURCES/binutils-CVE-2018-8945.patch
@@ -0,0 +1,30 @@
+diff -rup binutils.orig/bfd/elf-attrs.c binutils-2.27/bfd/elf-attrs.c
+--- binutils.orig/bfd/elf-attrs.c 2018-05-30 09:57:23.385080577 +0100
++++ binutils-2.27/bfd/elf-attrs.c 2018-05-30 10:01:03.528712202 +0100
+@@ -438,6 +438,15 @@ _bfd_elf_parse_attributes (bfd *abfd, El
+ /* PR 17512: file: 2844a11d. */
+ if (hdr->sh_size == 0)
+ return;
++ if (hdr->sh_size > bfd_get_size (abfd))
++ {
++ /* xgettext:c-format */
++ _bfd_error_handler (_("%B: error: attribute section '%A' too big: %#llx"),
++ abfd, hdr->bfd_section, (long long) hdr->sh_size);
++ bfd_set_error (bfd_error_invalid_operation);
++ return;
++ }
++
+ contents = (bfd_byte *) bfd_malloc (hdr->sh_size);
+ if (!contents)
+ return;
+diff -rup binutils.orig/bfd/elf.c binutils-2.27/bfd/elf.c
+--- binutils.orig/bfd/elf.c 2018-05-30 09:57:23.382080610 +0100
++++ binutils-2.27/bfd/elf.c 2018-05-30 10:01:52.766182199 +0100
+@@ -297,6 +297,7 @@ bfd_elf_get_str_section (bfd *abfd, unsi
+ /* Allocate and clear an extra byte at the end, to prevent crashes
+ in case the string table is not terminated. */
+ if (shstrtabsize + 1 <= 1
++ || shstrtabsize > bfd_get_size (abfd)
+ || bfd_seek (abfd, offset, SEEK_SET) != 0
+ || (shstrtab = (bfd_byte *) bfd_alloc (abfd, shstrtabsize + 1)) == NULL)
+ shstrtab = NULL;
diff --git a/SOURCES/binutils-SUPPRESS-PPC-TLBIE-CHECK.patch b/SOURCES/binutils-SUPPRESS-PPC-TLBIE-CHECK.patch
new file mode 100644
index 0000000..449f681
--- /dev/null
+++ b/SOURCES/binutils-SUPPRESS-PPC-TLBIE-CHECK.patch
@@ -0,0 +1,141 @@
+--- binutils-2.25.1/gas/testsuite/gas/ppc/power7.s 2015-07-21 09:20:58.000000000 +0100
++++ binutils-2.25.1.new/gas/testsuite/gas/ppc/power7.s 2016-03-01 14:08:17.020136029 +0000
+@@ -98,4 +98,4 @@ power7:
+ mfppr32 11
+ mtppr 12
+ mtppr32 13
+- tlbie 10,11
++ tlbie 10
+--- binutils-2.25.1/gas/testsuite/gas/ppc/power7.d 2015-07-21 09:20:58.000000000 +0100
++++ binutils-2.25.1.new/gas/testsuite/gas/ppc/power7.d 2016-03-01 14:08:17.020136029 +0000
+@@ -107,5 +107,5 @@ Disassembly of section \.text:
+ .*: (7d 62 e2 a6|a6 e2 62 7d) mfppr32 r11
+ .*: (7d 80 e3 a6|a6 e3 80 7d) mtppr r12
+ .*: (7d a2 e3 a6|a6 e3 a2 7d) mtppr32 r13
+-.*: (7d 60 52 64|64 52 60 7d) tlbie r10,r11
++.*: (7c 00 52 64|64 52 00 7c) tlbie r10
+ #pass
+--- binutils.orig/opcodes/ppc-opc.c 2017-01-17 09:44:23.341397357 +0000
++++ binutils-2.27/opcodes/ppc-opc.c 2017-01-17 09:45:24.000684653 +0000
+@@ -5182,8 +5182,7 @@ const struct powerpc_opcode powerpc_opco
+ {"mfbhrbe", X(31,302), X_MASK, POWER8, 0, {RT, BHRBE}},
+
+ {"tlbie", X(31,306), X_MASK|1<<20,POWER9, TITAN, {RB, RS, RIC, PRS, X_R}},
+-{"tlbie", X(31,306), XRA_MASK, POWER7, POWER9|TITAN, {RB, RS}},
+-{"tlbie", X(31,306), XRTLRA_MASK, PPC, E500|POWER7|TITAN, {RB, L}},
++{"tlbie", X(31,306), XRTLRA_MASK, PPC, POWER9|TITAN, {RB, L}},
+ {"tlbi", X(31,306), XRT_MASK, POWER, 0, {RA0, RB}},
+
+ {"mfvsrld", X(31,307), XX1RB_MASK, PPCVSX3, 0, {RA, XS6}},
+--- binutils.orig/gas/testsuite/gas/ppc/e500-ill.s 2017-01-17 10:34:39.821866168 +0000
++++ binutils-2.27/gas/testsuite/gas/ppc/e500-ill.s 2017-01-17 10:56:56.766061777 +0000
+@@ -7,4 +7,4 @@ start:
+ mfdcr 5, 234
+ mtdcr 432, 8
+ tlbia
+- tlbie 3
++
+--- binutils.orig/gas/testsuite/gas/ppc/e500-ill.l 2017-01-17 10:34:39.821866168 +0000
++++ binutils-2.27/gas/testsuite/gas/ppc/e500-ill.l 2017-01-17 10:57:09.021915557 +0000
+@@ -5,4 +5,3 @@
+ .*: Error: unrecognized opcode: `mfdcr'
+ .*: Error: unrecognized opcode: `mtdcr'
+ .*: Error: unrecognized opcode: `tlbia'
+-.*: Error: unrecognized opcode: `tlbie'
+--- binutils.orig/gas/testsuite/gas/ppc/power6.s 2017-01-17 10:34:39.822866157 +0000
++++ binutils-2.27/gas/testsuite/gas/ppc/power6.s 2017-01-17 10:58:38.316849143 +0000
+@@ -69,6 +69,5 @@ start:
+ slbia
+ slbia 0
+ slbia 7
+- tlbie 10
+ tlbie 10,0
+ tlbie 10,1
+--- binutils.orig/gas/testsuite/gas/ppc/power6.d 2017-01-17 10:34:39.822866157 +0000
++++ binutils-2.27/gas/testsuite/gas/ppc/power6.d 2017-01-17 10:59:24.780294250 +0000
+@@ -74,7 +74,6 @@ Disassembly of section \.text:
+ .*: (7c 00 03 e4|e4 03 00 7c) slbia
+ .*: (7c 00 03 e4|e4 03 00 7c) slbia
+ .*: (7c e0 03 e4|e4 03 e0 7c) slbia 7
+-.*: (7c 00 52 64|64 52 00 7c) tlbie r10
+-.*: (7c 00 52 64|64 52 00 7c) tlbie r10
++.*: (7c 00 52 64|64 52 00 7c) tlbie r10,0
+ .*: (7c 20 52 64|64 52 20 7c) tlbie r10,1
+ #pass
+--- binutils.orig/gas/testsuite/gas/ppc/power7.s 2017-01-17 10:34:39.823866144 +0000
++++ binutils-2.27/gas/testsuite/gas/ppc/power7.s 2017-01-17 11:00:19.835636746 +0000
+@@ -98,4 +98,4 @@ power7:
+ mfppr32 11
+ mtppr 12
+ mtppr32 13
+- tlbie 10
++
+--- binutils.orig/gas/testsuite/gas/ppc/power7.d 2017-01-17 10:34:39.822866157 +0000
++++ binutils-2.27/gas/testsuite/gas/ppc/power7.d 2017-01-17 11:00:27.995539295 +0000
+@@ -107,5 +107,4 @@ Disassembly of section \.text:
+ .*: (7d 62 e2 a6|a6 e2 62 7d) mfppr32 r11
+ .*: (7d 80 e3 a6|a6 e3 80 7d) mtppr r12
+ .*: (7d a2 e3 a6|a6 e3 a2 7d) mtppr32 r13
+-.*: (7c 00 52 64|64 52 00 7c) tlbie r10
+ #pass
+diff -rup binutils.orig/gas/config/tc-ppc.c binutils-2.27/gas/config/tc-ppc.c
+--- binutils.orig/gas/config/tc-ppc.c 2017-02-02 12:21:55.246930313 +0000
++++ binutils-2.27/gas/config/tc-ppc.c 2017-02-02 12:29:13.568862941 +0000
+@@ -2672,7 +2672,7 @@ md_assemble (char *str)
+
+ operand = &powerpc_operands[*opindex_ptr];
+ if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0
+- && !((operand->flags & PPC_OPERAND_OPTIONAL32) != 0 && ppc_obj64))
++ || (operand->flags & PPC_OPERAND_OPTIONAL32))
+ {
+ unsigned int opcount;
+ unsigned int num_operands_expected;
+@@ -2741,8 +2741,8 @@ md_assemble (char *str)
+
+ /* If this is an optional operand, and we are skipping it, just
+ insert a zero. */
+- if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0
+- && !((operand->flags & PPC_OPERAND_OPTIONAL32) != 0 && ppc_obj64)
++ if (((operand->flags & PPC_OPERAND_OPTIONAL) != 0
++ || (operand->flags & PPC_OPERAND_OPTIONAL32) != 0)
+ && skip_optional)
+ {
+ long val = ppc_optional_operand_value (operand);
+diff -rup binutils-2.27.orig/gas/testsuite/gas/ppc/power6.d binutils-2.27/gas/testsuite/gas/ppc/power6.d
+--- binutils-2.27.orig/gas/testsuite/gas/ppc/power6.d 2017-02-14 10:17:21.352033787 +0000
++++ binutils-2.27/gas/testsuite/gas/ppc/power6.d 2017-02-14 11:54:36.643091777 +0000
+@@ -74,6 +74,6 @@ Disassembly of section \.text:
+ .*: (7c 00 03 e4|e4 03 00 7c) slbia
+ .*: (7c 00 03 e4|e4 03 00 7c) slbia
+ .*: (7c e0 03 e4|e4 03 e0 7c) slbia 7
+-.*: (7c 00 52 64|64 52 00 7c) tlbie r10,0
++.*: (7c 00 52 64|64 52 00 7c) tlbie r10
+ .*: (7c 20 52 64|64 52 20 7c) tlbie r10,1
+ #pass
+diff -rup binutils-2.27.orig/opcodes/ppc-opc.c binutils-2.27/opcodes/ppc-opc.c
+--- binutils-2.27.orig/opcodes/ppc-opc.c 2017-02-14 10:17:22.281021961 +0000
++++ binutils-2.27/opcodes/ppc-opc.c 2017-02-14 11:58:50.035840144 +0000
+@@ -576,9 +576,12 @@ const struct powerpc_operand powerpc_ope
+ #define RD RS
+ { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR },
+
++#define RSLL RS + 1
++ { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL32 },
++
+ /* The RS and RT fields of the DS form stq and DQ form lq instructions,
+ which have special value restrictions. */
+-#define RSQ RS + 1
++#define RSQ RSLL + 1
+ #define RTQ RSQ
+ { 0x1e, 21, NULL, NULL, PPC_OPERAND_GPR },
+
+@@ -5132,7 +5135,8 @@ const struct powerpc_opcode powerpc_opco
+ {"mfbhrbe", X(31,302), X_MASK, POWER8, 0, {RT, BHRBE}},
+
+ {"tlbie", X(31,306), X_MASK|1<<20,POWER9, TITAN, {RB, RS, RIC, PRS, X_R}},
+-{"tlbie", X(31,306), XRTLRA_MASK, PPC, POWER9|TITAN, {RB, L}},
++{"tlbie", X(31,306), XRA_MASK, POWER7, POWER9|TITAN, {RB, RSLL}},
++{"tlbie", X(31,306), XRTLRA_MASK, PPC, E500|POWER7|TITAN, {RB, LOPT}},
+ {"tlbi", X(31,306), XRT_MASK, POWER, 0, {RA0, RB}},
+
+ {"mfvsrld", X(31,307), XX1RB_MASK, PPCVSX3, 0, {RA, XS6}},
diff --git a/SOURCES/binutils-attach-to-group.patch b/SOURCES/binutils-attach-to-group.patch
new file mode 100644
index 0000000..9883f68
--- /dev/null
+++ b/SOURCES/binutils-attach-to-group.patch
@@ -0,0 +1,67 @@
+diff -rup binutils.orig/gas/config/obj-elf.c binutils-2.27/gas/config/obj-elf.c
+--- binutils.orig/gas/config/obj-elf.c 2019-01-08 13:52:32.758716536 +0000
++++ binutils-2.27/gas/config/obj-elf.c 2019-01-08 15:05:34.705763638 +0000
+@@ -78,9 +78,11 @@ static void obj_elf_gnu_attribute (int);
+ static void obj_elf_tls_common (int);
+ static void obj_elf_lcomm (int);
+ static void obj_elf_struct (int);
++static void obj_elf_attach_to_group (int);
+
+ static const pseudo_typeS elf_pseudo_table[] =
+ {
++ {"attach_to_group", obj_elf_attach_to_group, 0},
+ {"comm", obj_elf_common, 0},
+ {"common", obj_elf_common, 1},
+ {"ident", obj_elf_ident, 0},
+@@ -980,6 +982,27 @@ obj_elf_section_name (void)
+ return name;
+ }
+
++static void
++obj_elf_attach_to_group (int dummy ATTRIBUTE_UNUSED)
++{
++ const char * gname = obj_elf_section_name ();
++
++ if (gname == NULL)
++ {
++ as_warn ("group name not parseable");
++ return;
++ }
++
++ if (elf_group_name (now_seg))
++ {
++ as_warn ("already has a group");
++ return;
++ }
++
++ elf_group_name (now_seg) = xstrdup (gname);
++ elf_section_flags (now_seg) |= SHF_GROUP;
++}
++
+ void
+ obj_elf_section (int push)
+ {
+diff -rup binutils.orig/gas/doc/as.texinfo binutils-2.27/gas/doc/as.texinfo
+--- binutils.orig/gas/doc/as.texinfo 2019-01-08 13:52:32.766716472 +0000
++++ binutils-2.27/gas/doc/as.texinfo 2019-01-08 15:05:34.707763621 +0000
+@@ -4312,6 +4312,7 @@ Some machine configurations provide addi
+ * Altmacro:: @code{.altmacro}
+ * Ascii:: @code{.ascii "@var{string}"}@dots{}
+ * Asciz:: @code{.asciz "@var{string}"}@dots{}
++* Attach_to_group:: @code{.attach_to_group @var{name}}
+ * Balign:: @code{.balign @var{abs-expr} , @var{abs-expr}}
+ * Bundle directives:: @code{.bundle_align_mode @var{abs-expr}}, etc
+ * Byte:: @code{.byte @var{expressions}}
+@@ -4603,6 +4604,12 @@ trailing zero byte) into consecutive add
+ @code{.asciz} is just like @code{.ascii}, but each string is followed by
+ a zero byte. The ``z'' in @samp{.asciz} stands for ``zero''.
+
++@node Attach_to_group
++@section @code{.attach_to_group @var{name}}
++Attaches the current section to the named group. This is like declaring
++the section with the @code{G} attribute, but can be done after the section
++has been created.
++
+ @node Balign
+ @section @code{.balign[wl] @var{abs-expr}, @var{abs-expr}, @var{abs-expr}}
+
diff --git a/SOURCES/binutils-coverty-fixes.patch b/SOURCES/binutils-coverty-fixes.patch
new file mode 100644
index 0000000..52791b0
--- /dev/null
+++ b/SOURCES/binutils-coverty-fixes.patch
@@ -0,0 +1,104 @@
+--- binutils.orig/gold/aarch64.cc 2017-01-18 16:05:12.747684566 +0000
++++ binutils-2.27/gold/aarch64.cc 2017-01-18 16:05:23.128501011 +0000
+@@ -784,8 +784,14 @@ Stub_template_repertoire<big_endian>::St
+ 0x14000000, /* b <label> */
+ };
+
+- // ST_E_835769 has the same stub template as ST_E_843419.
+- const static Insntype* ST_E_835769_INSNS = ST_E_843419_INSNS;
++ // ST_E_835769 has the same stub template as ST_E_843419
++ // but we reproduce the array here so that the sizeof
++ // expressions in install_insn_template will work.
++ const static Insntype ST_E_835769_INSNS[] =
++ {
++ 0x00000000, /* Placeholder for erratum insn. */
++ 0x14000000, /* b <label> */
++ };
+
+ #define install_insn_template(T) \
+ const static Stub_template<big_endian> template_##T = { \
+--- binutils.orig/gas/config/tc-i386.c 2017-01-18 16:05:12.533688350 +0000
++++ binutils-2.27/gas/config/tc-i386.c 2017-01-18 16:11:29.828016979 +0000
+@@ -4120,13 +4120,13 @@ parse_operands (char *l, const char *mne
+ { /* Yes, we've read in another operand. */
+ unsigned int operand_ok;
+ this_operand = i.operands++;
+- i.types[this_operand].bitfield.unspecified = 1;
+ if (i.operands > MAX_OPERANDS)
+ {
+ as_bad (_("spurious operands; (%d operands/instruction max)"),
+ MAX_OPERANDS);
+ return NULL;
+ }
++ i.types[this_operand].bitfield.unspecified = 1;
+ /* Now parse operand adding info to 'i' as we go along. */
+ END_STRING_AND_SAVE (l);
+
+diff -rup binutils.orig/ld/testplug2.c binutils-2.27/ld/testplug2.c
+--- binutils.orig/ld/testplug2.c 2017-01-18 16:05:12.777684035 +0000
++++ binutils-2.27/ld/testplug2.c 2017-01-18 16:18:39.437420563 +0000
+@@ -242,10 +242,11 @@ parse_symdefstr (const char *str, struct
+ sym->version = NULL;
+ if (colon5 && colon5[1])
+ {
+- sym->comdat_key = malloc (strlen (colon5 + 1) + 1);
++ ++colon5;
++ sym->comdat_key = malloc (strlen (colon5) + 1);
+ if (!sym->comdat_key)
+ return LDPS_ERR;
+- strcpy (sym->comdat_key, colon5 + 1);
++ strcpy (sym->comdat_key, colon5);
+ }
+ else
+ sym->comdat_key = 0;
+diff -rup binutils.orig/ld/testplug3.c binutils-2.27/ld/testplug3.c
+--- binutils.orig/ld/testplug3.c 2017-01-18 16:05:12.777684035 +0000
++++ binutils-2.27/ld/testplug3.c 2017-01-18 16:17:48.878314557 +0000
+@@ -241,10 +241,11 @@ parse_symdefstr (const char *str, struct
+ sym->version = NULL;
+ if (colon5 && colon5[1])
+ {
+- sym->comdat_key = malloc (strlen (colon5 + 1) + 1);
++ ++colon5;
++ sym->comdat_key = malloc (strlen (colon5) + 1);
+ if (!sym->comdat_key)
+ return LDPS_ERR;
+- strcpy (sym->comdat_key, colon5 + 1);
++ strcpy (sym->comdat_key, colon5);
+ }
+ else
+ sym->comdat_key = 0;
+diff -rup binutils.orig/ld/testplug4.c binutils-2.27/ld/testplug4.c
+--- binutils.orig/ld/testplug4.c 2017-01-18 16:05:12.777684035 +0000
++++ binutils-2.27/ld/testplug4.c 2017-01-18 16:16:34.751625275 +0000
+@@ -242,10 +242,11 @@ parse_symdefstr (const char *str, struct
+ sym->version = NULL;
+ if (colon5 && colon5[1])
+ {
+- sym->comdat_key = malloc (strlen (colon5 + 1) + 1);
++ ++colon5;
++ sym->comdat_key = malloc (strlen (colon5) + 1);
+ if (!sym->comdat_key)
+ return LDPS_ERR;
+- strcpy (sym->comdat_key, colon5 + 1);
++ strcpy (sym->comdat_key, colon5);
+ }
+ else
+ sym->comdat_key = 0;
+diff -rup binutils.orig/ld/testplug.c binutils-2.27/ld/testplug.c
+--- binutils.orig/ld/testplug.c 2017-01-18 16:05:12.777684035 +0000
++++ binutils-2.27/ld/testplug.c 2017-01-18 16:19:22.460659820 +0000
+@@ -238,10 +238,11 @@ parse_symdefstr (const char *str, struct
+ sym->version = NULL;
+ if (colon5 && colon5[1])
+ {
+- sym->comdat_key = malloc (strlen (colon5 + 1) + 1);
++ ++colon5;
++ sym->comdat_key = malloc (strlen (colon5) + 1);
+ if (!sym->comdat_key)
+ return LDPS_ERR;
+- strcpy (sym->comdat_key, colon5 + 1);
++ strcpy (sym->comdat_key, colon5);
+ }
+ else
+ sym->comdat_key = 0;
diff --git a/SOURCES/binutils-libiberty-demangler.patch b/SOURCES/binutils-libiberty-demangler.patch
new file mode 100644
index 0000000..883dff5
--- /dev/null
+++ b/SOURCES/binutils-libiberty-demangler.patch
@@ -0,0 +1,257 @@
+diff -rup binutils.orig/include/demangle.h binutils-2.27/include/demangle.h
+--- binutils.orig/include/demangle.h 2019-01-08 13:52:32.990714670 +0000
++++ binutils-2.27/include/demangle.h 2019-01-08 13:58:42.269743403 +0000
+@@ -64,9 +64,20 @@ extern "C" {
+ #define DMGL_GNAT (1 << 15)
+ #define DMGL_DLANG (1 << 16)
+
++/* Disable a limit on the depth of recursion in mangled strings.
++ Note if this limit is disabled then stack exhaustion is possible when
++ demangling pathologically complicated strings. Bug reports about stack
++ exhaustion when the option is enabled will be rejected. */
++#define DMGL_NO_RECURSE_LIMIT (1 << 17)
++
+ /* If none of these are set, use 'current_demangling_style' as the default. */
+ #define DMGL_STYLE_MASK (DMGL_AUTO|DMGL_GNU|DMGL_LUCID|DMGL_ARM|DMGL_HP|DMGL_EDG|DMGL_GNU_V3|DMGL_JAVA|DMGL_GNAT|DMGL_DLANG)
+
++/* If DMGL_NO_RECURSE_LIMIT is not enabled, then this is the value used as
++ the maximum depth of recursion allowed. It should be enough for any
++ real-world mangled name. */
++#define DEMANGLE_RECURSION_LIMIT 2048
++
+ /* Enumeration of possible demangling styles.
+
+ Lucid and ARM styles are still kept logically distinct, even though
+Only in binutils-2.27/include: demangle.h.orig
+Only in binutils-2.27/include: #demangle.h.rej#
+Only in binutils-2.27/include: .#demangle.h.rej
+Only in binutils-2.27/include: demangle.h.rej
+diff -rup binutils.orig/libiberty/cp-demangle.c binutils-2.27/libiberty/cp-demangle.c
+--- binutils.orig/libiberty/cp-demangle.c 2019-01-08 13:52:33.161713294 +0000
++++ binutils-2.27/libiberty/cp-demangle.c 2019-01-08 13:53:30.002255949 +0000
+@@ -2725,21 +2725,35 @@ d_ref_qualifier (struct d_info *di, stru
+ static struct demangle_component *
+ d_function_type (struct d_info *di)
+ {
+- struct demangle_component *ret;
++ struct demangle_component *ret = NULL;
+
+- if (! d_check_char (di, 'F'))
+- return NULL;
+- if (d_peek_char (di) == 'Y')
++ if ((di->options & DMGL_NO_RECURSE_LIMIT) == 0)
+ {
+- /* Function has C linkage. We don't print this information.
+- FIXME: We should print it in verbose mode. */
+- d_advance (di, 1);
++ if (di->recursion_level > DEMANGLE_RECURSION_LIMIT)
++ /* FIXME: There ought to be a way to report
++ that the recursion limit has been reached. */
++ return NULL;
++
++ di->recursion_level ++;
+ }
+- ret = d_bare_function_type (di, 1);
+- ret = d_ref_qualifier (di, ret);
+
+- if (! d_check_char (di, 'E'))
+- return NULL;
++ if (d_check_char (di, 'F'))
++ {
++ if (d_peek_char (di) == 'Y')
++ {
++ /* Function has C linkage. We don't print this information.
++ FIXME: We should print it in verbose mode. */
++ d_advance (di, 1);
++ }
++ ret = d_bare_function_type (di, 1);
++ ret = d_ref_qualifier (di, ret);
++
++ if (! d_check_char (di, 'E'))
++ ret = NULL;
++ }
++
++ if ((di->options & DMGL_NO_RECURSE_LIMIT) == 0)
++ di->recursion_level --;
+ return ret;
+ }
+
+@@ -5898,6 +5912,7 @@ cplus_demangle_init_info (const char *ma
+ di->expansion = 0;
+ di->is_expression = 0;
+ di->is_conversion = 0;
++ di->recursion_level = 0;
+ }
+
+ /* Internal implementation for the demangler. If MANGLED is a g++ v3 ABI
+@@ -5937,6 +5952,20 @@ d_demangle_callback (const char *mangled
+
+ cplus_demangle_init_info (mangled, options, strlen (mangled), &di);
+
++ /* PR 87675 - Check for a mangled string that is so long
++ that we do not have enough stack space to demangle it. */
++ if (((options & DMGL_NO_RECURSE_LIMIT) == 0)
++ /* This check is a bit arbitrary, since what we really want to do is to
++ compare the sizes of the di.comps and di.subs arrays against the
++ amount of stack space remaining. But there is no portable way to do
++ this, so instead we use the recursion limit as a guide to the maximum
++ size of the arrays. */
++ && (unsigned long) di.num_comps > DEMANGLE_RECURSION_LIMIT)
++ {
++ /* FIXME: We need a way to indicate that a stack limit has been reached. */
++ return 0;
++ }
++
+ {
+ #ifdef CP_DYNAMIC_ARRAYS
+ __extension__ struct demangle_component comps[di.num_comps];
+Only in binutils-2.27/libiberty: cp-demangle.c.orig
+diff -rup binutils.orig/libiberty/cp-demangle.h binutils-2.27/libiberty/cp-demangle.h
+--- binutils.orig/libiberty/cp-demangle.h 2019-01-08 13:52:33.161713294 +0000
++++ binutils-2.27/libiberty/cp-demangle.h 2019-01-08 13:53:30.003255941 +0000
+@@ -127,6 +127,9 @@ struct d_info
+ /* Non-zero if we are parsing the type operand of a conversion
+ operator, but not when in an expression. */
+ int is_conversion;
++ /* If DMGL_NO_RECURSE_LIMIT is not active then this is set to
++ the current recursion level. */
++ unsigned int recursion_level;
+ };
+
+ /* To avoid running past the ending '\0', don't:
+Only in binutils-2.27/libiberty: cp-demangle.h.orig
+diff -rup binutils.orig/libiberty/cplus-dem.c binutils-2.27/libiberty/cplus-dem.c
+--- binutils.orig/libiberty/cplus-dem.c 2019-01-08 13:52:33.161713294 +0000
++++ binutils-2.27/libiberty/cplus-dem.c 2019-01-08 14:10:00.057340821 +0000
+@@ -137,6 +137,7 @@ struct work_stuff
+ string* previous_argument; /* The last function argument demangled. */
+ int nrepeats; /* The number of times to repeat the previous
+ argument. */
++ unsigned int recursion_level;
+ };
+
+ #define PRINT_ANSI_QUALIFIERS (work -> options & DMGL_ANSI)
+@@ -1237,11 +1238,15 @@ squangle_mop_up (struct work_stuff *work
+ {
+ free ((char *) work -> btypevec);
+ work->btypevec = NULL;
++ work->bsize = 0;
++ work->numb = 0;
+ }
+ if (work -> ktypevec != NULL)
+ {
+ free ((char *) work -> ktypevec);
+ work->ktypevec = NULL;
++ work->ksize = 0;
++ work->numk = 0;
+ }
+ }
+
+@@ -1275,8 +1280,15 @@ work_stuff_copy_to_from (struct work_stu
+
+ for (i = 0; i < from->numk; i++)
+ {
+- int len = strlen (from->ktypevec[i]) + 1;
++ int len;
+
++ if (from->ktypevec[i] == NULL)
++ {
++ to->ktypevec[i] = NULL;
++ continue;
++ }
++
++ len = strlen (from->ktypevec[i]) + 1;
+ to->ktypevec[i] = XNEWVEC (char, len);
+ memcpy (to->ktypevec[i], from->ktypevec[i], len);
+ }
+@@ -1286,8 +1298,15 @@ work_stuff_copy_to_from (struct work_stu
+
+ for (i = 0; i < from->numb; i++)
+ {
+- int len = strlen (from->btypevec[i]) + 1;
++ int len;
+
++ if (from->btypevec[i] == NULL)
++ {
++ to->btypevec[i] = NULL;
++ continue;
++ }
++
++ len = strlen (from->btypevec[i]) + 1;
+ to->btypevec[i] = XNEWVEC (char , len);
+ memcpy (to->btypevec[i], from->btypevec[i], len);
+ }
+@@ -1335,6 +1354,7 @@ delete_non_B_K_work_stuff (struct work_s
+
+ free ((char*) work->tmpl_argvec);
+ work->tmpl_argvec = NULL;
++ work->ntmpl_args = 0;
+ }
+ if (work->previous_argument)
+ {
+@@ -3347,6 +3367,20 @@ demangle_qualified (struct work_stuff *w
+ success = 0;
+ }
+
++ if ((work->options & DMGL_NO_RECURSE_LIMIT) == 0)
++ {
++ /* PR 87241: Catch malicious input that will try to trick this code into
++ allocating a ridiculous amount of memory via the remember_Ktype()
++ function.
++ The choice of DEMANGLE_RECURSION_LIMIT is somewhat arbitrary. Possibly
++ a better solution would be to track how much memory remember_Ktype
++ allocates and abort when some upper limit is reached. */
++ if (qualifiers > DEMANGLE_RECURSION_LIMIT)
++ /* FIXME: We ought to have some way to tell the user that
++ this limit has been reached. */
++ success = 0;
++ }
++
+ if (!success)
+ return success;
+
+@@ -4335,6 +4369,7 @@ remember_Btype (struct work_stuff *work,
+ }
+
+ /* Lose all the info related to B and K type codes. */
++
+ static void
+ forget_B_and_K_types (struct work_stuff *work)
+ {
+@@ -4360,6 +4395,7 @@ forget_B_and_K_types (struct work_stuff
+ }
+ }
+ }
++
+ /* Forget the remembered types, but not the type vector itself. */
+
+ static void
+@@ -4551,6 +4587,16 @@ demangle_nested_args (struct work_stuff
+ int result;
+ int saved_nrepeats;
+
++ if ((work->options & DMGL_NO_RECURSE_LIMIT) == 0)
++ {
++ if (work->recursion_level > DEMANGLE_RECURSION_LIMIT)
++ /* FIXME: There ought to be a way to report
++ that the recursion limit has been reached. */
++ return 0;
++
++ work->recursion_level ++;
++ }
++
+ /* The G++ name-mangling algorithm does not remember types on nested
+ argument lists, unless -fsquangling is used, and in that case the
+ type vector updated by remember_type is not used. So, we turn
+@@ -4577,6 +4623,9 @@ demangle_nested_args (struct work_stuff
+ --work->forgetting_types;
+ work->nrepeats = saved_nrepeats;
+
++ if ((work->options & DMGL_NO_RECURSE_LIMIT) == 0)
++ --work->recursion_level;
++
+ return result;
+ }
+
+Only in binutils-2.27/libiberty: cplus-dem.c.orig
+Only in binutils-2.27/libiberty: cplus-dem.c.rej
diff --git a/SOURCES/binutils-multiple-relocs-for-same-section.patch b/SOURCES/binutils-multiple-relocs-for-same-section.patch
new file mode 100644
index 0000000..165c743
--- /dev/null
+++ b/SOURCES/binutils-multiple-relocs-for-same-section.patch
@@ -0,0 +1,23 @@
+--- binutils.orig/bfd/elf.c 2019-09-10 10:57:33.391081672 +0100
++++ binutils-2.27/bfd/elf.c 2019-09-10 10:59:55.355010766 +0100
+@@ -2324,9 +2324,18 @@ bfd_section_from_shdr (bfd *abfd, unsign
+ else
+ p_hdr = &esdt->rel.hdr;
+
+- /* PR 17512: file: 0b4f81b7. */
++ /* PR 17512: file: 0b4f81b7.
++ Also see PR 24456, for a file which deliberately has two reloc
++ sections. */
+ if (*p_hdr != NULL)
+- goto fail;
++ {
++ _bfd_error_handler
++ /* xgettext:c-format */
++ (_("%B: warning: multiple relocation sections for section %A \
++found - ignoring all but the first"),
++ abfd, target_sect);
++ goto success;
++ }
+ hdr2 = (Elf_Internal_Shdr *) bfd_alloc (abfd, sizeof (*hdr2));
+ if (hdr2 == NULL)
+ goto fail;
diff --git a/SOURCES/binutils-rh1203449.patch b/SOURCES/binutils-rh1203449.patch
new file mode 100644
index 0000000..009cefd
--- /dev/null
+++ b/SOURCES/binutils-rh1203449.patch
@@ -0,0 +1,20 @@
+--- ld/emultempl/armelf.em~ 2015-03-18 17:32:36.436208938 -0400
++++ ld/emultempl/armelf.em 2015-03-18 17:32:54.455591126 -0400
+@@ -53,6 +53,7 @@
+ input_flags.dynamic = ${DYNAMIC_LINK-TRUE};
+ config.has_shared = `if test -n "$GENERATE_SHLIB_SCRIPT" ; then echo TRUE ; else echo FALSE ; fi`;
+ config.separate_code = `if test "x${SEPARATE_CODE}" = xyes ; then echo TRUE ; else echo FALSE ; fi`;
++ link_info.relro = TRUE;
+ }
+
+ static void
+--- ld/emultempl/aarch64elf.em~ 2015-03-18 17:32:08.347172011 -0400
++++ ld/emultempl/aarch64elf.em 2015-03-18 17:32:30.866399906 -0400
+@@ -40,6 +40,7 @@
+ input_flags.dynamic = ${DYNAMIC_LINK-TRUE};
+ config.has_shared = `if test -n "$GENERATE_SHLIB_SCRIPT" ; then echo TRUE ; else echo FALSE ; fi`;
+ config.separate_code = `if test "x${SEPARATE_CODE}" = xyes ; then echo TRUE ; else echo FALSE ; fi`;
++ link_info.relro = TRUE;
+ }
+
+ static void
diff --git a/SOURCES/binutils-rh1300603.patch b/SOURCES/binutils-rh1300603.patch
new file mode 100644
index 0000000..2df8c35
--- /dev/null
+++ b/SOURCES/binutils-rh1300603.patch
@@ -0,0 +1,20 @@
+diff -rup binutils-2.27.orig/bfd/elf-eh-frame.c binutils-2.27/bfd/elf-eh-frame.c
+--- binutils-2.27.orig/bfd/elf-eh-frame.c 2017-01-16 17:27:46.411632857 +0000
++++ binutils-2.27/bfd/elf-eh-frame.c 2017-01-16 17:30:03.663437755 +0000
+@@ -2296,7 +2296,15 @@ write_dwarf_eh_frame_hdr (bfd *abfd, str
+ != sec->output_section->vma + val))
+ overflow = TRUE;
+ bfd_put_32 (abfd, val, contents + EH_FRAME_HDR_SIZE + i * 8 + 8);
+- if (i != 0
++ if (i > 0
++ && hdr_info->u.dwarf.array[i].initial_loc
++ == hdr_info->u.dwarf.array[i - 1].initial_loc
++ && hdr_info->u.dwarf.array[i].range
++ == hdr_info->u.dwarf.array[i - 1].range)
++ /* Duplicate FDE entry. We should probably discard it
++ but for now just ignore it. */
++ ;
++ else if (i != 0
+ && (hdr_info->u.dwarf.array[i].initial_loc
+ < (hdr_info->u.dwarf.array[i - 1].initial_loc
+ + hdr_info->u.dwarf.array[i - 1].range)))
diff --git a/SOURCES/binutils-rh1312876.patch b/SOURCES/binutils-rh1312876.patch
new file mode 100644
index 0000000..2ef6cb5
--- /dev/null
+++ b/SOURCES/binutils-rh1312876.patch
@@ -0,0 +1,139 @@
+--- binutils-2.25.1.new/ld/testsuite/ld-powerpc/tlsso32.r 2016-03-01 14:08:17.249137110 +0000
++++ binutils-2.25.1/ld/testsuite/ld-powerpc/tlsso32.r 2016-03-01 15:10:02.847812018 +0000
+@@ -20,6 +20,7 @@ Section Headers:
+ +\[[ 0-9]+\] \.dynamic +DYNAMIC .* 08 +WA +3 +0 +4
+ +\[[ 0-9]+\] \.got +PROGBITS .* 0+30 04 +WA +0 +0 +4
+ +\[[ 0-9]+\] \.plt +PROGBITS .* 0+4 00 +WA +0 +0 +4
++#...
+ +\[[ 0-9]+\] \.shstrtab +.*
+ +\[[ 0-9]+\] \.symtab +.*
+ +\[[ 0-9]+\] \.strtab +.*
+@@ -80,12 +81,12 @@ Symbol table '\.dynsym' contains [0-9]+
+ .* TLS +GLOBAL +DEFAULT +8 le1
+ .* TLS +GLOBAL +DEFAULT +UND ld
+ .* NOTYPE +GLOBAL +DEFAULT +6 _start
+-.* NOTYPE +GLOBAL +DEFAULT +11 __end
++.* NOTYPE +GLOBAL +DEFAULT +.. __end
+ .* TLS +GLOBAL +DEFAULT +8 ld2
+ .* TLS +GLOBAL +DEFAULT +8 ld1
+-.* NOTYPE +GLOBAL +DEFAULT +11 __bss_start
+-.* NOTYPE +GLOBAL +DEFAULT +11 _edata
+-.* NOTYPE +GLOBAL +DEFAULT +11 _end
++.* NOTYPE +GLOBAL +DEFAULT +.. __bss_start
++.* NOTYPE +GLOBAL +DEFAULT +.. _edata
++.* NOTYPE +GLOBAL +DEFAULT +.. _end
+ .* TLS +GLOBAL +DEFAULT +8 gd0
+ .* TLS +GLOBAL +DEFAULT +8 ie0
+
+@@ -103,32 +104,4 @@ Symbol table '\.symtab' contains [0-9]+
+ .* SECTION +LOCAL +DEFAULT +9
+ .* SECTION +LOCAL +DEFAULT +10
+ .* SECTION +LOCAL +DEFAULT +11
+-.* FILE +LOCAL +DEFAULT +ABS .*
+-.* TLS +LOCAL +DEFAULT +7 gd4
+-.* TLS +LOCAL +DEFAULT +7 ld4
+-.* TLS +LOCAL +DEFAULT +7 ld5
+-.* TLS +LOCAL +DEFAULT +7 ld6
+-.* TLS +LOCAL +DEFAULT +7 ie4
+-.* TLS +LOCAL +DEFAULT +7 le4
+-.* TLS +LOCAL +DEFAULT +7 le5
+-.* FILE +LOCAL +DEFAULT +ABS .*
+-.* OBJECT +LOCAL +DEFAULT +9 _DYNAMIC
+-.* NOTYPE +LOCAL +DEFAULT +6 0+8000\.got2\.plt_pic32\.__tls_get_addr
+-.* NOTYPE +LOCAL +DEFAULT +6 __glink_PLTresolve
+-.* NOTYPE +LOCAL +DEFAULT +6 __glink
+-.* OBJECT +LOCAL +DEFAULT +10 _GLOBAL_OFFSET_TABLE_
+-.* TLS +GLOBAL +DEFAULT +UND gd
+-.* TLS +GLOBAL +DEFAULT +8 le0
+-.* NOTYPE +GLOBAL +DEFAULT +UND __tls_get_addr
+-.* TLS +GLOBAL +DEFAULT +8 ld0
+-.* TLS +GLOBAL +DEFAULT +8 le1
+-.* TLS +GLOBAL +DEFAULT +UND ld
+-.* NOTYPE +GLOBAL +DEFAULT +6 _start
+-.* NOTYPE +GLOBAL +DEFAULT +11 __end
+-.* TLS +GLOBAL +DEFAULT +8 ld2
+-.* TLS +GLOBAL +DEFAULT +8 ld1
+-.* NOTYPE +GLOBAL +DEFAULT +11 __bss_start
+-.* NOTYPE +GLOBAL +DEFAULT +11 _edata
+-.* NOTYPE +GLOBAL +DEFAULT +11 _end
+-.* TLS +GLOBAL +DEFAULT +8 gd0
+-.* TLS +GLOBAL +DEFAULT +8 ie0
++#pass
+--- binutils-2.25.1.new/ld/testsuite/ld-powerpc/tlsexe32.r 2016-03-01 14:08:17.248137105 +0000
++++ binutils-2.25.1/ld/testsuite/ld-powerpc/tlsexe32.r 2016-03-01 15:08:57.693493230 +0000
+@@ -22,6 +22,7 @@ Section Headers:
+ +\[[ 0-9]+\] \.dynamic +DYNAMIC +[0-9a-f]+ [0-9a-f]+ [0-9a-f]+ 08 +WA +4 +0 +4
+ +\[[ 0-9]+\] \.got +PROGBITS +[0-9a-f]+ [0-9a-f]+ 000018 04 +WA +0 +0 +4
+ +\[[ 0-9]+\] \.plt +PROGBITS +[0-9a-f]+ [0-9a-f]+ 000004 00 +WA +0 +0 +4
++#...
+ +\[[ 0-9]+\] \.shstrtab +STRTAB +.*
+ +\[[ 0-9]+\] \.symtab +SYMTAB +.*
+ +\[[ 0-9]+\] \.strtab +STRTAB +.*
+@@ -64,11 +65,11 @@ Symbol table '\.dynsym' contains [0-9]+
+ .* NOTYPE +LOCAL +DEFAULT +UND
+ .* TLS +GLOBAL +DEFAULT +UND gd
+ .* TLS +GLOBAL +DEFAULT +UND ld
+-.* NOTYPE +GLOBAL +DEFAULT +12 __end
+-.* NOTYPE +GLOBAL +DEFAULT +12 __bss_start
++.* NOTYPE +GLOBAL +DEFAULT +.. __end
++.* NOTYPE +GLOBAL +DEFAULT +.. __bss_start
+ .* FUNC +GLOBAL +DEFAULT +UND __tls_get_addr_opt
+-.* NOTYPE +GLOBAL +DEFAULT +12 _edata
+-.* NOTYPE +GLOBAL +DEFAULT +12 _end
++.* NOTYPE +GLOBAL +DEFAULT +.. _edata
++.* NOTYPE +GLOBAL +DEFAULT +.. _end
+
+ Symbol table '\.symtab' contains [0-9]+ entries:
+ +Num: +Value +Size +Type +Bind +Vis +Ndx +Name
+@@ -85,29 +86,5 @@ Symbol table '\.symtab' contains [0-9]+
+ .* SECTION +LOCAL +DEFAULT +10
+ .* SECTION +LOCAL +DEFAULT +11
+ .* SECTION +LOCAL +DEFAULT +12
+-.* FILE +LOCAL +DEFAULT +ABS .*
+-.* TLS +LOCAL +DEFAULT +8 gd4
+-.* TLS +LOCAL +DEFAULT +8 ld4
+-.* TLS +LOCAL +DEFAULT +8 ld5
+-.* TLS +LOCAL +DEFAULT +8 ld6
+-.* TLS +LOCAL +DEFAULT +8 ie4
+-.* TLS +LOCAL +DEFAULT +8 le4
+-.* TLS +LOCAL +DEFAULT +8 le5
+-.* FILE +LOCAL +DEFAULT +ABS .*
+-.* OBJECT +LOCAL +DEFAULT +10 _DYNAMIC
+-.* OBJECT +LOCAL +DEFAULT +11 _GLOBAL_OFFSET_TABLE_
+-.* TLS +GLOBAL +DEFAULT +UND gd
+-.* TLS +GLOBAL +DEFAULT +9 le0
+-.* TLS +GLOBAL +DEFAULT +9 ld0
+-.* TLS +GLOBAL +DEFAULT +9 le1
+-.* TLS +GLOBAL +DEFAULT +UND ld
+-.* NOTYPE +GLOBAL +DEFAULT +7 _start
+-.* NOTYPE +GLOBAL +DEFAULT +12 __end
+-.* TLS +GLOBAL +DEFAULT +9 ld2
+-.* TLS +GLOBAL +DEFAULT +9 ld1
+-.* NOTYPE +GLOBAL +DEFAULT +12 __bss_start
+-.* FUNC +GLOBAL +DEFAULT +UND __tls_get_addr_opt
+-.* NOTYPE +GLOBAL +DEFAULT +12 _edata
+-.* NOTYPE +GLOBAL +DEFAULT +12 _end
+-.* TLS +GLOBAL +DEFAULT +9 gd0
+-.* TLS +GLOBAL +DEFAULT +9 ie0
++#pass
++
+diff -rup binutils-2.27.orig/ld/testsuite/ld-powerpc/powerpc.exp binutils-2.27/ld/testsuite/ld-powerpc/powerpc.exp
+--- binutils-2.27.orig/ld/testsuite/ld-powerpc/powerpc.exp 2017-01-16 17:27:46.697628285 +0000
++++ binutils-2.27/ld/testsuite/ld-powerpc/powerpc.exp 2017-01-16 17:34:34.684104074 +0000
+@@ -102,13 +102,13 @@ set ppcelftests {
+ {{objdump -hw reloc.d}} "reloc.so"}
+ {"APUinfo section processing" "-melf32ppc" ""
+ "-a32 -me500" {apuinfo1.s apuinfo-nul.s apuinfo2.s}
+- {{readelf -x2 apuinfo.rd}} "apuinfo"}
++ {{readelf -x.PPC.EMB.apuinfo apuinfo.rd}} "apuinfo"}
+ {"APUinfo VLE section processing" "-melf32ppc" ""
+ "-a32 -me500 -mvle" {apuinfo1.s apuinfo-vle.s apuinfo-vle2.s}
+- {{readelf -x2 apuinfo-vle.rd}} "apuinfo-vle"}
++ {{readelf -x.PPC.EMB.apuinfo apuinfo-vle.rd}} "apuinfo-vle"}
+ {"APUinfo NULL section processing" "-melf32ppc" ""
+ "-a32 -me500" {apuinfo-nul1.s apuinfo-nul.s}
+- {{readelf -x2 apuinfo-nul.rd}} "apuinfo"}
++ {{readelf -x.PPC.EMB.apuinfo apuinfo-nul.rd}} "apuinfo"}
+ {"TLS32 static exec" "-melf32ppc" "" "-a32" {tls32.s tlslib32.s}
+ {{objdump -dr tls32.d} {objdump -sj.got tls32.g}
+ {objdump -sj.tdata tls32.t}}
diff --git a/SOURCES/binutils-strip-fix.patch b/SOURCES/binutils-strip-fix.patch
new file mode 100644
index 0000000..f6737b5
--- /dev/null
+++ b/SOURCES/binutils-strip-fix.patch
@@ -0,0 +1,23 @@
+--- b/bfd/elf.c 2018-10-31 12:25:51.693217184 +0530
++++ a/bfd/elf.c 2018-10-31 12:27:54.243952676 +0530
+@@ -1249,13 +1249,19 @@
+ Elf_Internal_Shdr ** oheaders = elf_elfsections (obfd);
+ unsigned int i;
+
+- if (section_match (oheaders[hint], iheader))
++ BFD_ASSERT (iheader != NULL);
++
++ /* See PR 20922 for a reproducer of the NULL test. */
++ if (oheaders[hint] != NULL
++ && section_match (oheaders[hint], iheader))
+ return hint;
+
+ for (i = 1; i < elf_numsections (obfd); i++)
+ {
+ Elf_Internal_Shdr * oheader = oheaders[i];
+
++ if (oheader == NULL)
++ continue;
+ if (section_match (oheader, iheader))
+ /* FIXME: Do we care if there is a potential for
+ multiple matches ? */
diff --git a/SOURCES/binutils-strip-unknown-relocs.patch b/SOURCES/binutils-strip-unknown-relocs.patch
new file mode 100644
index 0000000..73f6912
--- /dev/null
+++ b/SOURCES/binutils-strip-unknown-relocs.patch
@@ -0,0 +1,544 @@
+diff -rup binutils.orig/bfd/elf32-i386.c binutils-2.30/bfd/elf32-i386.c
+--- binutils.orig/bfd/elf32-i386.c 2018-02-27 17:25:53.961140597 +0000
++++ binutils-2.30/bfd/elf32-i386.c 2018-02-27 17:27:14.115133477 +0000
+@@ -383,7 +383,7 @@ elf_i386_rtype_to_howto (bfd *abfd, unsi
+ {
+ (*_bfd_error_handler) (_("%B: invalid relocation type %d"),
+ abfd, (int) r_type);
+- indx = R_386_NONE;
++ return NULL;
+ }
+ /* PR 17512: file: 0f67f69d. */
+ if (elf_howto_table [indx].type != r_type)
+diff -rup binutils.orig/bfd/elf64-ppc.c binutils-2.30/bfd/elf64-ppc.c
+--- binutils.orig/bfd/elf64-ppc.c 2018-02-27 17:25:53.969140496 +0000
++++ binutils-2.30/bfd/elf64-ppc.c 2018-02-27 17:27:56.213604518 +0000
+@@ -2516,9 +2516,12 @@ ppc64_elf_info_to_howto (bfd *abfd, arel
+ {
+ (*_bfd_error_handler) (_("%B: invalid relocation type %d"),
+ abfd, (int) type);
+- type = R_PPC64_NONE;
++ cache_ptr->howto = NULL;
+ }
+- cache_ptr->howto = ppc64_elf_howto_table[type];
++ else
++ cache_ptr->howto = ppc64_elf_howto_table[type];
++ if (cache_ptr->howto == NULL || cache_ptr->howto->name == NULL)
++ _bfd_error_handler (_("%B: invalid relocation type %d"), abfd, type);
+ }
+
+ /* Handle the R_PPC64_ADDR16_HA and similar relocs. */
+diff -rup binutils.orig/bfd/elf64-s390.c binutils-2.30/bfd/elf64-s390.c
+--- binutils.orig/bfd/elf64-s390.c 2018-02-27 17:25:53.968140509 +0000
++++ binutils-2.30/bfd/elf64-s390.c 2018-02-27 17:28:24.632247443 +0000
+@@ -372,9 +372,10 @@ elf_s390_info_to_howto (bfd *abfd ATTRIB
+ {
+ (*_bfd_error_handler) (_("%B: invalid relocation type %d"),
+ abfd, (int) r_type);
+- r_type = R_390_NONE;
++ cache_ptr->howto = NULL;
+ }
+- cache_ptr->howto = &elf_howto_table[r_type];
++ else
++ cache_ptr->howto = &elf_howto_table[r_type];
+ }
+ }
+
+diff -rup binutils.orig/bfd/elf64-x86-64.c binutils-2.30/bfd/elf64-x86-64.c
+--- binutils.orig/bfd/elf64-x86-64.c 2018-02-27 17:25:53.964140559 +0000
++++ binutils-2.30/bfd/elf64-x86-64.c 2018-02-27 17:29:12.554645307 +0000
+@@ -284,7 +284,7 @@ elf_x86_64_rtype_to_howto (bfd *abfd, un
+ {
+ (*_bfd_error_handler) (_("%B: invalid relocation type %d"),
+ abfd, (int) r_type);
+- r_type = R_X86_64_NONE;
++ return NULL;
+ }
+ i = r_type;
+ }
+@@ -347,7 +347,6 @@ elf_x86_64_info_to_howto (bfd *abfd ATTR
+
+ r_type = ELF32_R_TYPE (dst->r_info);
+ cache_ptr->howto = elf_x86_64_rtype_to_howto (abfd, r_type);
+- BFD_ASSERT (r_type == cache_ptr->howto->type);
+ }
+
+ /* Support for core dump NOTE sections. */
+diff -rup binutils.orig/bfd/elfcode.h binutils-2.30/bfd/elfcode.h
+--- binutils.orig/bfd/elfcode.h 2018-02-27 17:25:53.964140559 +0000
++++ binutils-2.30/bfd/elfcode.h 2018-02-27 17:26:57.234345581 +0000
+@@ -1474,6 +1474,12 @@ elf_slurp_reloc_table_from_section (bfd
+ (*ebd->elf_info_to_howto) (abfd, relent, &rela);
+ else
+ (*ebd->elf_info_to_howto_rel) (abfd, relent, &rela);
++
++ if (relent->howto == NULL)
++ {
++ bfd_set_error (bfd_error_bad_value);
++ goto error_return;
++ }
+ }
+
+ if (allocated != NULL)
+diff -rup binutils.orig/binutils/objcopy.c binutils-2.30/binutils/objcopy.c
+--- binutils.orig/binutils/objcopy.c 2018-02-27 17:25:53.185150347 +0000
++++ binutils-2.30/binutils/objcopy.c 2018-02-27 17:30:05.806976202 +0000
+@@ -3022,10 +3022,19 @@ copy_object (bfd *ibfd, bfd *obfd, const
+ haven't been set yet. mark_symbols_used_in_relocations will
+ ignore input sections which have no corresponding output
+ section. */
++ bfd_set_error (bfd_error_no_error);
+ if (strip_symbols != STRIP_ALL)
+- bfd_map_over_sections (ibfd,
+- mark_symbols_used_in_relocations,
+- isympp);
++ {
++ bfd_map_over_sections (ibfd,
++ mark_symbols_used_in_relocations,
++ isympp);
++ if (bfd_get_error () != bfd_error_no_error)
++ {
++ status = 1;
++ return FALSE;
++ }
++ }
++
+ osympp = (asymbol **) xmalloc ((symcount + add_symbols + 1) * sizeof (asymbol *));
+ symcount = filter_symbols (ibfd, obfd, osympp, isympp, symcount);
+ }
+diff -rup binutils.orig/binutils/testsuite/binutils-all/objcopy.exp binutils-2.27/binutils/testsuite/binutils-all/objcopy.exp
+--- binutils.orig/binutils/testsuite/binutils-all/objcopy.exp 2018-04-11 12:34:04.671683298 +0100
++++ binutils-2.27/binutils/testsuite/binutils-all/objcopy.exp 2018-04-11 12:36:50.053734109 +0100
+@@ -1083,6 +1083,29 @@ if [is_elf_format] {
+ }
+ run_dump_test "strip-11" $extra_strip11
+
++ if { [istarget "mips64*-*-openbsd*"] } {
++ set reloc_format mips64
++ } elseif { [istarget "arm-*"] \
++ || [istarget "d10v-*"] \
++ || [istarget "dlx-*"] \
++ || [istarget "i*86-*"] \
++ || [istarget "i960-*"] \
++ || [istarget "m681*-*"] \
++ || [istarget "m68hc1*-*"] \
++ || ([istarget "mips*-*"] \
++ && ![istarget "mips64*-ps2-elf*"] \
++ && ![istarget "*-*-irix6*"] \
++ && ![istarget "mips64*-*-freebsd*"] \
++ && ![istarget "mips64*-*-kfreebsd*-gnu"] \
++ && ![istarget "mips64*-*-linux*"]) \
++ || [istarget "score*-*"] \
++ || [istarget "xgate-*"] } {
++ set reloc_format rel
++ } else {
++ set reloc_format rela
++ }
++ run_dump_test "strip-13" [list [list source strip-13${reloc_format}.s]]
++
+ if { [istarget "i*86-*"] || [istarget "x86_64-*-*"] } {
+ # Check to make sure we don't strip a symbol named in relocations.
+ set test "objcopy keeps symbols needed by relocs"
+diff -rup binutils.orig/binutils/testsuite/lib/utils-lib.exp binutils-2.27/binutils/testsuite/lib/utils-lib.exp
+--- binutils.orig/binutils/testsuite/lib/utils-lib.exp 2018-04-11 12:34:04.674683263 +0100
++++ binutils-2.27/binutils/testsuite/lib/utils-lib.exp 2018-04-11 12:54:56.097850613 +0100
+@@ -1,4 +1,4 @@
+-# Copyright (C) 1993-2016 Free Software Foundation, Inc.
++# Copyright (C) 1993-2018 Free Software Foundation, Inc.
+
+ # This program is free software; you can redistribute it and/or modify
+ # it under the terms of the GNU General Public License as published by
+@@ -51,12 +51,17 @@ proc binutil_version { prog } {
+ # default_binutils_run
+ # run a program, returning the output
+ # sets binutils_run_failed if the program does not exist
++# sets binutils_run_status to the exit status of the program
+ #
+ proc default_binutils_run { prog progargs } {
+ global binutils_run_failed
++ global binutils_run_status
+ global host_triplet
+
+ set binutils_run_failed 0
++ if [info exists binutils_run_status] {
++ unset binutils_run_status
++ }
+
+ if ![is_remote host] {
+ if {[which $prog] == 0} then {
+@@ -83,6 +88,7 @@ proc default_binutils_run { prog progarg
+ regsub -all "\\$" "$progargs" "\\$" progargs
+
+ set state [remote_exec host $prog $progargs]
++ set binutils_run_status [lindex $state 0]
+ set exec_output [prune_warnings [lindex $state 1]]
+ if {![string match "" $exec_output]} then {
+ send_log "$exec_output\n"
+@@ -127,7 +133,6 @@ proc default_binutils_assemble_flags { s
+ } else {
+ send_log "$exec_output\n"
+ verbose "$exec_output"
+- perror "$source: assembly failed"
+ return 0
+ }
+ }
+@@ -214,6 +219,11 @@ proc exe_ext {} {
+ # Assemble the file SOURCE.s. If omitted, this defaults to FILE.s.
+ # This is useful if several .d files want to share a .s file.
+ #
++# dump: DUMP
++# Match against DUMP.d. If omitted, this defaults to FILE.d. This
++# is useful if several .d files differ by options only. Options are
++# always read from FILE.d.
++#
+ # target: GLOBS...
+ # Run this test only on a specified list of targets. More precisely,
+ # each glob in the space-separated list is passed to "istarget"; if
+@@ -237,22 +247,22 @@ proc exe_ext {} {
+ #
+ # error: REGEX
+ # An error with message matching REGEX must be emitted for the test
+-# to pass. The PROG, objdump, nm and objcopy options have no
+-# meaning and need not supplied if this is present.
++# to pass. The DUMPPROG, addr2line, nm, objdump, readelf and size
++# options have no meaning and need not supplied if this is present.
++# Multiple "error" directives append to the expected error message.
++#
++# error_output: FILE
++# Means the same as 'error', except the regular expression lines
++# are contains in FILE.
+ #
+ # warning: REGEX
+-# Expect a gas warning matching REGEX. It is an error to issue
+-# both "error" and "warning".
+-#
+-# stderr: FILE
+-# FILE contains regexp lines to be matched against the diagnostic
+-# output of the assembler. This does not preclude the use of
+-# PROG, nm, objdump, or objcopy.
+-#
+-# error-output: FILE
+-# Means the same as 'stderr', but also indicates that the assembler
+-# is expected to exit unsuccessfully (therefore PROG, objdump, nm,
+-# and objcopy have no meaning and should not be supplied).
++# Expect a warning matching REGEX. It is an error to issue both
++# "error" and "warning". Multiple "warning" directives append to
++# the expected linker warning message.
++#
++# warning_output: FILE
++# Means the same as 'warning', except the regular expression
++# lines are contains in FILE.
+ #
+ # Each option may occur at most once.
+ #
+@@ -266,6 +276,7 @@ proc run_dump_test { name {extra_options
+ global OBJDUMP NM OBJCOPY READELF STRIP
+ global OBJDUMPFLAGS NMFLAGS OBJCOPYFLAGS READELFFLAGS STRIPFLAGS
+ global ELFEDIT ELFEDITFLAGS
++ global binutils_run_status
+ global host_triplet
+ global env
+ global copyfile
+@@ -299,6 +310,11 @@ proc run_dump_test { name {extra_options
+ set opts(PROG) {}
+ set opts(DUMPPROG) {}
+ set opts(source) {}
++ set opts(dump) {}
++ set opts(error) {}
++ set opts(warning) {}
++ set opts(error_output) {}
++ set opts(warning_output) {}
+ set opts(target) {}
+ set opts(not-target) {}
+ set opts(skip) {}
+@@ -317,12 +333,18 @@ proc run_dump_test { name {extra_options
+ # directory.
+ regsub -all "\\\$srcdir" "$opt_val" "$srcdir/$subdir" opt_val
+
+- if [string length $opts($opt_name)] {
+- perror "option $opt_name multiply set in $file.d"
+- unresolved $subdir/$name
+- return
++ switch -- $opt_name {
++ warning {}
++ error {}
++ default {
++ if [string length $opts($opt_name)] {
++ perror "option $opt_name multiply set in $file.d"
++ unresolved $subdir/$name
++ return
++ }
++ }
+ }
+- set opts($opt_name) $opt_val
++ append opts($opt_name) $opt_val
+ }
+
+ foreach i $extra_options {
+@@ -340,7 +362,8 @@ proc run_dump_test { name {extra_options
+
+ # add extra option to end of existing option, adding space
+ # if necessary.
+- if [string length $opts($opt_name)] {
++ if { ![regexp "warning|error" $opt_name]
++ && [string length $opts($opt_name)] } {
+ append opts($opt_name) " "
+ }
+ append opts($opt_name) $opt_val
+@@ -378,28 +401,35 @@ proc run_dump_test { name {extra_options
+ }
+
+ set dumpprogram ""
+- if { $opts(DUMPPROG) != "" } {
+- switch -- $opts(DUMPPROG) {
+- addr2line { set dumpprogram addr2line }
+- nm { set dumpprogram nm }
+- objdump { set dumpprogram objdump }
+- readelf { set dumpprogram readelf }
+- size { set dumpprogram size }
+- default {
+- perror "unrecognized dump program option $opts(DUMPPROG) in $file.d"
+- unresolved $testname
+- return }
+- }
+- } else {
+- # Guess which program to run, by seeing which option was specified.
+- foreach p {addr2line nm objdump readelf size} {
+- if {$opts($p) != ""} {
+- if {$dumpprogram != ""} {
+- perror "more than one possible dump program specified in $file.d"
++ # It's meaningless to require an output-testing method when we
++ # expect an error.
++ if { $opts(error) == "" && $opts(error_output) == "" } {
++ if { $opts(DUMPPROG) != "" } {
++ switch -- $opts(DUMPPROG) {
++ addr2line { set dumpprogram addr2line }
++ nm { set dumpprogram nm }
++ objdump { set dumpprogram objdump }
++ readelf { set dumpprogram readelf }
++ size { set dumpprogram size }
++ default {
++ perror "unrecognized dump program option $opts(DUMPPROG)\
++ in $file.d"
+ unresolved $testname
+ return
+- } else {
+- set dumpprogram $p
++ }
++ }
++ } else {
++ # Guess which program to run, by seeing which option was specified.
++ foreach p {addr2line nm objdump readelf size} {
++ if {$opts($p) != ""} {
++ if {$dumpprogram != ""} {
++ perror "more than one possible dump program specified\
++ in $file.d"
++ unresolved $testname
++ return
++ } else {
++ set dumpprogram $p
++ }
+ }
+ }
+ }
+@@ -456,6 +486,12 @@ proc run_dump_test { name {extra_options
+ set srcfile $srcdir/$subdir/$opts(source)
+ }
+
++ if { $opts(dump) == "" } {
++ set dumpfile ${file}.d
++ } else {
++ set dumpfile $srcdir/$subdir/$opts(dump)
++ }
++
+ if { $opts(as) == "binary" } {
+ while {[file type $srcfile] eq "link"} {
+ set newfile [file readlink $srcfile]
+@@ -464,7 +500,8 @@ proc run_dump_test { name {extra_options
+ }
+ set srcfile $newfile
+ }
+- file copy -force ${srcfile} $tempfile
++ # Make sure we copy the file if we are doing remote host testing.
++ remote_download host ${srcfile} $tempfile
+ } else {
+ set exec_output [binutils_assemble_flags ${srcfile} $tempfile $opts(as)]
+ if [string match "" $exec_output] then {
+@@ -475,16 +512,95 @@ proc run_dump_test { name {extra_options
+ }
+ }
+
++ if { (($opts(warning) != "") && ($opts(error) != "")) \
++ || (($opts(warning) != "") && ($opts(error_output) != "")) \
++ || (($opts(warning) != "") && ($opts(warning_output) != "")) \
++ || (($opts(error) != "") && ($opts(warning_output) != "")) \
++ || (($opts(error) != "") && ($opts(error_output) != "")) \
++ || (($opts(warning_output) != "") && ($opts(error_output) != "")) } {
++ perror "bad mix of warning, error, warning_output, and error_output\
++ test-directives"
++ unresolved $testname
++ return
++ }
++
++ set check_prog(source) ""
++ set check_prog(terminal) 0
++ if { $opts(error) != "" \
++ || $opts(warning) != "" \
++ || $opts(error_output) != "" \
++ || $opts(warning_output) != "" } {
++
++ if { $opts(error) != "" || $opts(error_output) != "" } {
++ set check_prog(terminal) 1
++ } else {
++ set check_prog(terminal) 0
++ }
++
++ if { $opts(error) != "" || $opts(warning) != "" } {
++ set check_prog(source) "regex"
++ if { $opts(error) != "" } {
++ set check_prog(regex) $opts(error)
++ } else {
++ set check_prog(regex) $opts(warning)
++ }
++ } else {
++ set check_prog(source) "file"
++ if { $opts(error_output) != "" } {
++ set check_prog(file) $opts(error_output)
++ } else {
++ set check_prog(file) $opts(warning_output)
++ }
++ }
++ }
++
+ set progopts1 $opts($program)
+ eval set progopts \$[string toupper $program]FLAGS
+ eval set binary \$[string toupper $program]
+
+ set exec_output [binutils_run $binary "$progopts $progopts1 $tempfile $destopt ${copyfile}.o"]
+- if ![string match "" $exec_output] {
+- send_log "$exec_output\n"
++ set cmdret 0
++ if [info exists binutils_run_status] {
++ set cmdret $binutils_run_status
++ }
++
++ regsub "\n$" $exec_output "" exec_output
++ if { $cmdret != 0 || $exec_output != "" || $check_prog(source) != "" } {
++ set exitstat "succeeded"
++ if { $cmdret != 0 } {
++ set exitstat "failed"
++ }
++
++ if { $check_prog(source) == "regex" } {
++ verbose -log "$exitstat with: <$exec_output>,\
++ expected: <$check_prog(regex)>"
++ } elseif { $check_prog(source) == "file" } {
++ verbose -log "$exitstat with: <$exec_output>,\
++ expected in file $check_prog(file)"
++ set_file_contents "tmpdir/prog.messages" "$exec_output"
++ } else {
++ verbose -log "$exitstat with: <$exec_output>, no expected output"
++ }
++ send_log -- "$exec_output\n"
+ verbose "$exec_output"
+- fail $testname
+- return
++
++ if { (($check_prog(source) == "") == ($exec_output == "")) \
++ && (($cmdret == 0) == ($check_prog(terminal) == 0)) \
++ && ((($check_prog(source) == "regex") \
++ && ($check_prog(regex) == "") == ($exec_output == "") \
++ && [regexp -- $check_prog(regex) $exec_output]) \
++ || (($check_prog(source) == "file") \
++ && (![regexp_diff "tmpdir/prog.messages" \
++ "$srcdir/$subdir/$check_prog(file)"]))) } {
++ # We have the expected output from prog.
++ if { $check_prog(terminal) || $program == "" } {
++ pass $testname
++ return
++ }
++ } else {
++ fail $testname
++ return
++ }
+ }
+
+ set progopts1 $opts($dumpprogram)
+@@ -534,7 +650,7 @@ proc run_dump_test { name {extra_options
+ }
+
+ verbose_eval {[file_contents "tmpdir/dump.out"]} 3
+- if { [regexp_diff "tmpdir/dump.out" "${file}.d"] } then {
++ if { [regexp_diff "tmpdir/dump.out" "${dumpfile}"] } then {
+ fail $testname
+ verbose "output is [file_contents "tmpdir/dump.out"]" 2
+ return
+--- /dev/null 2018-04-11 08:10:00.466225454 +0100
++++ binutils-2.27/binutils/testsuite/binutils-all/strip-13.d 2018-04-11 12:55:42.481306111 +0100
+@@ -0,0 +1,10 @@
++#PROG: strip
++#strip: -g
++#error: \A[^\n]*: invalid relocation type 143\n
++#error: [^\n]*: Bad value\Z
++#not-target: h8300-* ip2k-* m6811-* m68hc11-* rx-*
++# The H8300-*, IP2K and 68HC11 targets use 16-bit addressing, so `.dc.a'
++# does not work for manual relocation data construction.
++# The RX targets do not complain about unrecognised relocs, unless they
++# are actually used
++# (which is what should really happen with the other targets...)
+--- /dev/null 2018-04-11 08:10:00.466225454 +0100
++++ binutils-2.27/binutils/testsuite/binutils-all/strip-13mips64.s 2018-04-11 12:37:17.195412074 +0100
+@@ -0,0 +1,14 @@
++ .text
++foo:
++ .dc.l 0x12345678
++
++ .section .rela.text
++ .dc.a 0
++ .dc.l 0
++ .dc.b 0, 0, 0, 0x8f
++ .dc.a 0x0000008f
++
++ .dc.a 0
++ .dc.l 0
++ .dc.b 0, 0, 0, 0
++ .dc.a 0
+--- /dev/null 2018-04-11 08:10:00.466225454 +0100
++++ binutils-2.27/binutils/testsuite/binutils-all/strip-13rela.s 2018-04-11 12:37:17.195412074 +0100
+@@ -0,0 +1,12 @@
++ .text
++foo:
++ .dc.l 0x12345678
++
++ .section .rela.text
++ .dc.a 0
++ .dc.a 0x0000008f
++ .dc.a 0x0000008f
++
++ .dc.a 0
++ .dc.a 0
++ .dc.a 0
+--- /dev/null 2018-04-11 08:10:00.466225454 +0100
++++ binutils-2.27/binutils/testsuite/binutils-all/strip-13rel.s 2018-04-11 12:37:17.195412074 +0100
+@@ -0,0 +1,10 @@
++ .text
++foo:
++ .dc.l 0x12345678
++
++ .section .rel.text
++ .dc.a 0
++ .dc.a 0x0000008f
++
++ .dc.a 0
++ .dc.a 0
+--- binutils.orig/bfd/elfnn-aarch64.c 2018-04-11 12:34:04.649683557 +0100
++++ binutils-2.27/bfd/elfnn-aarch64.c 2018-04-11 13:33:08.539305994 +0100
+@@ -1977,6 +1977,8 @@ elfNN_aarch64_info_to_howto (bfd *abfd A
+
+ r_type = ELFNN_R_TYPE (elf_reloc->r_info);
+ bfd_reloc->howto = elfNN_aarch64_howto_from_type (r_type);
++ if (bfd_reloc->howto == NULL)
++ _bfd_error_handler (_("%B: invalid relocation type %d"), abfd, r_type);
+ }
+
+ static reloc_howto_type *
diff --git a/SOURCES/binutils-x86-lea-addressing.patch b/SOURCES/binutils-x86-lea-addressing.patch
new file mode 100644
index 0000000..6380545
--- /dev/null
+++ b/SOURCES/binutils-x86-lea-addressing.patch
@@ -0,0 +1,24 @@
+--- binutils.orig/bfd/elf32-i386.c 2018-05-02 15:59:44.716210095 +0100
++++ binutils-2.27/bfd/elf32-i386.c 2018-05-02 16:02:12.714435574 +0100
+@@ -3982,7 +3982,9 @@ elf_i386_relocate_section (bfd *output_b
+ - gotplt->output_section->vma
+ - gotplt->output_offset);
+
+- if ((*(contents + rel->r_offset - 1) & 0xc7) == 0x5)
++ if (rel->r_offset > 1
++ && (*(contents + rel->r_offset - 1) & 0xc7) == 0x5
++ && *(contents + rel->r_offset - 2) != 0x8d)
+ {
+ if (bfd_link_pic (info))
+ goto disallow_got32;
+@@ -4252,7 +4254,9 @@ r_386_got32:
+
+ relocation = (htab->elf.sgot->output_section->vma
+ + htab->elf.sgot->output_offset + off);
+- if ((*(contents + rel->r_offset - 1) & 0xc7) == 0x5)
++ if (rel->r_offset > 1
++ && (*(contents + rel->r_offset - 1) & 0xc7) == 0x5
++ && *(contents + rel->r_offset - 2) != 0x8d)
+ {
+ if (bfd_link_pic (info))
+ {
diff --git a/SOURCES/binutils-x86_64-disable-PLT-elision.patch b/SOURCES/binutils-x86_64-disable-PLT-elision.patch
new file mode 100644
index 0000000..070e7b7
--- /dev/null
+++ b/SOURCES/binutils-x86_64-disable-PLT-elision.patch
@@ -0,0 +1,20 @@
+diff -rup binutils.orig/bfd/elf64-x86-64.c binutils-2.27/bfd/elf64-x86-64.c
+--- binutils.orig/bfd/elf64-x86-64.c 2019-01-08 15:54:01.806611101 +0000
++++ binutils-2.27/bfd/elf64-x86-64.c 2019-01-08 15:55:30.790890607 +0000
+@@ -3032,7 +3032,7 @@ elf_x86_64_allocate_dynrelocs (struct el
+ resolved_to_zero = UNDEFINED_WEAK_RESOLVED_TO_ZERO (info,
+ eh->has_got_reloc,
+ eh);
+-
++#if 0
+ /* We can't use the GOT PLT if pointer equality is needed since
+ finish_dynamic_symbol won't clear symbol value and the dynamic
+ linker won't update the GOT slot. We will get into an infinite
+@@ -3050,6 +3050,7 @@ elf_x86_64_allocate_dynrelocs (struct el
+ /* Use the GOT PLT. */
+ eh->plt_got.refcount = 1;
+ }
++#endif
+
+ /* Clear the reference count of function pointer relocations if
+ symbol isn't a normal function. */
diff --git a/SOURCES/binutils-x86_64-do-not-convert-abs-relocs.patch b/SOURCES/binutils-x86_64-do-not-convert-abs-relocs.patch
new file mode 100644
index 0000000..f66fab7
--- /dev/null
+++ b/SOURCES/binutils-x86_64-do-not-convert-abs-relocs.patch
@@ -0,0 +1,12 @@
+--- binutils.orig/bfd/elf64-x86-64.c 2018-03-19 11:50:18.770407381 +0000
++++ binutils-2.27/bfd/elf64-x86-64.c 2018-03-19 12:01:12.177534677 +0000
+@@ -1931,6 +1931,9 @@ elf_x86_64_convert_load_reloc (bfd *abfd
+ {
+ bfd_signed_vma distance;
+
++ if (tsec->output_section == NULL)
++ return TRUE;
++
+ /* At this point, we don't know the load addresses of TSEC
+ section nor SEC section. We estimate the distrance between
+ SEC and TSEC. We store the estimated distances in the
diff --git a/SPECS/binutils.spec b/SPECS/binutils.spec
new file mode 100644
index 0000000..1c10a3e
--- /dev/null
+++ b/SPECS/binutils.spec
@@ -0,0 +1,2954 @@
+# rpmbuild parameters:
+# --define "binutils_target arm-linux-gnu" to create arm-linux-gnu-binutils.
+# --with=bootstrap: Build with minimal dependencies.
+# --with=debug: Build without optimizations and without splitting the debuginfo.
+# --without=docs: Skip building documentation.
+# --without=testsuite: Do not run the testsuite. Default is to run it.
+# --with=testsuite: Run the testsuite. Default when --with=debug is not to run it.
+
+%global _performance_build 1
+
+%if 0%{!?binutils_target:1}
+%define binutils_target %{_target_platform}
+%define isnative 1
+%define enable_shared 1
+%else
+%define cross %{binutils_target}-
+%define isnative 0
+%define enable_shared 0
+%endif
+
+# Provide a way to enable deterministic archives.
+# But do not do this by default.
+%define enable_deterministic_archives 0
+# Enable support for GCC LTO compilation.
+%define enable_lto 1
+# Disable the default generation of compressed debug sections.
+%define default_compress_debug 0
+# Default to read-only-relocations (relro) in shared binaries.
+%define default_relro 1
+
+# Default: Not bootstrapping.
+%bcond_with bootstrap
+# Default: Not debug
+%bcond_with debug
+# Default: Always build documentation.
+%bcond_without docs
+# Default: Always run the testsuite.
+%bcond_without testsuite
+
+%if %{with bootstrap}
+%undefine with_docs
+%undefine with_testsuite
+%endif
+
+%if %{with debug}
+%undefine with_testsuite
+%endif
+
+#---------------------------------------------------------------------------------
+
+Summary: A GNU collection of binary utilities
+Name: %{?cross}binutils%{?_with_debug:-debug}
+Version: 2.27
+# Note: The Release string *must* be different from that used by any of the
+# devtoolset binutils associated with this release. That is why ".base"
+# has been appended here. See BZ 1337617 for more details.
+Release: 42.base%{?dist}
+License: GPLv3+
+Group: Development/Tools
+URL: http://sources.redhat.com/binutils
+
+# Note - the Linux Kernel binutils releases are too unstable and contain
+# too many controversial patches so we stick with the official FSF version
+# instead.
+
+Source: http://ftp.gnu.org/gnu/binutils/binutils-%{version}.tar.bz2
+Source2: binutils-2.19.50.0.1-output-format.sed
+%if %{with docs}
+# Strictly speaking this next file is not part of the binutils distribution.
+# But the emacs info system expects it to be present on any system where
+# emacs is installed, and old binutils distributions used to include it by
+# mistake. Since there is no suitable 'documentation files' component to
+# current RHEL releases, it is included here, but to save time and complexity
+# it is stored as a pre-built, compressed, info file.
+# The upstream version of the original source file can be found here:
+# http://git.savannah.gnu.org/gitweb/?p=gnulib.git;a=blob_plain;f=doc/standards.texi;hb=HEAD
+# For more information see: https://bugzilla.redhat.com/show_bug.cgi?id=1467390
+Source3: standards.info.gz
+%endif
+
+#----------------------Patches----------------------------------------------------
+
+# Purpose: Use /lib64 and /usr/lib64 instead of /lib and /usr/lib in the
+# default library search path of 64-bit targets.
+# Lifetime: Permanent, but it should not be. This is a bug in the libtool
+# sources used in both binutils and gcc, (specifically the
+# libtool.m4 file). These are based on a version released in 2009
+# (2.2.6?) rather than the latest version. (Definitely fixed in
+# libtool version 2.4.6).
+Patch01: binutils-2.20.51.0.2-libtool-lib64.patch
+
+# Purpose: Prevents the generation of a spurious relocation in PPC64 PEI
+# executables.
+# Lifetime: Redundant - should be deleted.
+Patch02: binutils-2.20.51.0.10-ppc64-pie.patch
+
+# Purpose: Appends a RHEL or Fedora release string to the generic binutils
+# version string.
+# Lifetime: Permanent. This is a RHEL/Fedora specific patch.
+Patch03: binutils-2.25-version.patch
+
+# Purpose: Use the "unsigned long long" type for pointers on hosts where
+# long is a 32-bit type but pointers are a 64-bit type.
+# Lifetime: Redundant - should be deleted.
+Patch04: binutils-2.25-set-long-long.patch
+
+# Purpose: Prevent a seg-fault when attempting to pad a section with a NULL
+# padding pointer.
+# Lifetime: Fixed in 2.30.
+Patch05: binutils-2.20.51.0.10-sec-merge-emit.patch
+
+# Purpose: Exports the demangle.h header file (associated with the libiberty
+# sources) with the binutils-devel rpm.
+# Lifetime: Permanent. This is a RHEL/Fedora specific patch.
+Patch07: binutils-2.22.52.0.1-export-demangle.h.patch
+
+# Purpose: Disables the check in the BFD library's header file that config.h
+# has been included before the bfd.h header. See BZ #845084 for
+# more details.
+# Lifetime: Permanent - but it should not be. The bfd.h header defines
+# various types that are dependent upon configuration options, so
+# the order of inclusion is important.
+# FIXME: It would be better if the packages using the BFD header were
+# fixed so that they do include the header files in the correct
+# order. It may also be necessary to add a way for a package to
+# tell the bfd.h header that this check is not necessary.
+Patch08: binutils-2.22.52.0.4-no-config-h-check.patch
+
+# Purpose: Enables RELRO by default for AArch64 and ARM targets.
+# See BZ 1203449.
+# Lifetime: Fixed in FSF binutils 2.28.
+Patch09: binutils-rh1203449.patch
+
+# Purpose: Stops the linker from issuing a warning message when it
+# encounters an FDE entry that duplicates another FDE entry. These
+# can be generated by linker garbage collection eliminating a
+# section but not its FDE data. See BZ 1300603 for more details.
+# Lifetime: Permanent - for now. Ideally the linker should be improved so
+# that these duplicate entries are eliminated at an earlier stage
+# of the link process.
+Patch10: binutils-rh1300603.patch
+
+# Purpose: Fix linker testsuite failures for PPC64.
+# Lifetime: Redundant. These failures should be fixed in the upstream
+# sources now.
+# FIXME: Need to test that failures are fixed and then remove this patch.
+Patch11: binutils-rh1312876.patch
+
+# Purpose: Add /usr/lib/debug to the list of directories searched for
+# separate debug info files.
+# Lifetime: Fixed in 2.28.
+Patch12: binutils-2.23.52.0.1-find-separate-debug-file.patch
+
+# Purpose: Speed up combining source code listings with disassembly output.
+# Lifetime: Fixed in 2.28.
+Patch14: binutils-2.25.1-objdump-speedup.patch
+
+# Purpose: Fix computation of sh_info field for .dynsym sections
+# Lifetime: Fixed in 2.28.
+Patch15: binutils-2.27-local-dynsym-count.patch
+
+# Purpose: Ensure that sections are placed in a monotonically increasing
+# order of file offset.
+# Lifetime: Fixed in 2.28.
+Patch16: binutils-2.27-monotonic-section-offsets.patch
+
+# Purpose: Skip PR14918 linker test for ARM native targets.
+# Lifetime: Fixed in 2.30.
+Patch17: binutils-2.27-skip-rp14918-test-for-arm.patch
+
+# Purpose: Fixes compile time errors building GOLD for the AArch64 and ARM
+# targets.
+# Lifetime: Fixed in 2.28.
+Patch18: binutils-2.27-gold.patch
+
+# Purpose: Improve objdump's disassembly of dynamic executables.
+# Lifetime: Fixed in 2.28.
+# FIXME: Contains a bug. See entry for
+# binutils-2.27-remove-dwarf2-minmax.patch
+Patch19: binutils-2.27-objdump-improvements.patch
+
+# Purpose: Include the filename concerned in readelf error messages.
+# Lifetime: Permanent. This patch changes the format of readelf's output,
+# making it better (IMHO) but also potentially breaking tools that
+# depend upon readelf's current format. Hence it remains a local
+# patch.
+Patch20: binutils-2.27-filename-in-error-messages.patch
+
+# Purpose: Add support for the Power9 architecture.
+# Lifetime: Fixed in 2.28.
+Patch21: binutils-2.27-power9.patch
+
+# Purpose: And some Power9 bug fixes.
+# Lifetime: Fixed in 2.28.
+Patch22: binutils-2.27-power9.2.patch
+
+# Purpose: Fix up errors detected by Coverty.
+# Lifetime: Fixed in 2.29.
+Patch23: binutils-coverty-fixes.patch
+
+# Purpose: Do not create PLT entries for AARCH64 IFUNC symbols referenced in
+# debug sections.
+# Lifetime: Permanent.
+# FIXME: Find related bug. Decide on permanency.
+Patch24: binutils-2.27-aarch64-ifunc.patch
+
+# Purpose: Skip ifunc exec tests for AArch64.
+# Lifetime: Fixed in 2.28.
+Patch25: binutils-2.27-skip-ld-aarch64-ifunc-exec-tests.patch
+
+# Purpose: Expect linker test PR19719 to fail for the S390.
+# Lifetime: Permanent.
+# FIXME: Check to see if this test still fails, and delete patch when it
+# passes.
+Patch26: binutils-2.27-s390-pr19719.patch
+
+# Purpose: Delete linker tests for PR 19784.
+# Lifetime: Fixed in 2.28.
+Patch27: binutils-2.27-remove-pr19784-test.patch
+
+# Purpose: Fix computing stub sizes on PowerPC.
+# Lifetime: Fixed in 2.28.
+Patch28: binutils-2.27-ppc-stubs.patch
+
+# Purpose: Fix s390 PLT entry allocation.
+# Lifetime: Fixed in 2.29.
+Patch29: binutils-2.27-s390-plt.patch
+
+# Purpose: Revert H.J/s PLT elision patch.
+# Lifetime: Permanent.
+# FIXME: We should add a configure time option to enable/disable this
+# optimization.
+Patch30: binutils-2.27-revert-PLT-elision.patch
+
+# Purpose: Add support for new DWARF5 tag: DW_AT_export_symbols.
+# Lifetime: Fixed in 2.29.
+Patch31: binutils-2.27-DW_AT_export_symbols.patch
+
+# Purpose: Fixes a bug in binutils-2.25.1-objdump-speedup.patch that
+# prevents address to function name lookup from working properly
+# in some circumstances.
+# Lifetime: Retire when binutils-2.25.1-objdump-speedup.ptch is retired.
+# Ie when rebasing to 2.28.
+Patch32: binutils-2.27-remove-dwarf2-minmax.patch
+
+# Purpose: Add support for the arch12 s390x ISA extensions.
+# Lifetime: Fixed in 2.28.
+Patch33: binutils-2.27-s390x-arch12.patch
+
+# Purpose: Fix various minor CVE bugs.
+# Lifetime: Fixed in 2.28.
+Patch34: binutils-2.27-cve-bugs.patch
+
+# Purpose: Add support for ARMv8.2a and ARMv8.3 ISA extensions.
+# Lifetime: Fixewd in 2.29.
+Patch35: binutils-2.27-ARMv8.2.patch
+
+# Purpose: Fix generation of COPY relocs on AArch64.
+# Lifetime: Fixed in 2.29.
+Patch36: binutils-2.27-aarch64-copy-relocs.patch
+
+# Purpose: Generate an error when attempting to link non-PIC s390 objects in
+# PIE mode.
+# Lifetime: Fixed in 2.28.
+Patch37: binutils-2.27-s390x-complain-missing-fPIC.patch
+
+# Purpose: Add support for creating an PT_S390_PGSTE segment in s390
+# binaries.
+# Lifetime: Fixed in 2.29.
+Patch38: binutils-2.27-s390-pgste-marker.patch
+
+# Purpose: Fix seg-faults when stripping s390x binaries.
+# Lifetime: Fixed in 2.29.
+Patch39: binutils-2.27-s390x-check-for-NULL-pointers.patch
+
+# Purpose: Add support for the LNIA, SCV and RFSCV instructions in Power9
+# Lifetime: Fixed in 2.28.
+Patch40: binutils-2.27-power9.3.patch
+
+# Purpose: Fix a seg-fault in the PowerPC linker when discarding .plt
+# sections when -pie is used and undefined weak symbols are
+# present. See PR 22431.
+# Lifetime: Fixed in 2.30.
+Patch41: binutils-2.27-ppc64-discarded-plt-sections.patch
+
+# Purpose: Fix a seg-fault in the x86_64 linker when attempting to convert
+# relocations against the absolute section.
+# Lifetime: Fixed in 2.30.
+Patch42: binutils-x86_64-do-not-convert-abs-relocs.patch
+
+# Purpose: Add support for a "-z globalaudit" linker command line option.
+# Lifetime: Fixed in 2.30.
+Patch43: binutils-2.27-add-globalaudit-support.patch
+
+# Purpose: Stop strip from replacing unknown relocs with null relocs. Make
+# it return an error status and not strip the file instead.
+# Lifetime: Fixed in 2.31.
+Patch44: binutils-strip-unknown-relocs.patch
+
+# Purpose: Allow "lea foo@GOT, %reg" in PIC mode on the x86.
+# Lifetime: Fixed in 2.28
+Patch45: binutils-x86-lea-addressing.patch
+
+# Purpose: Fix seg-fault parsing corrupt DWARF1 debug information.
+# Lifetime: Fixed in 2.31
+Patch46: binutils-CVE-2018-7568.patch
+
+# Purpose: Fix seg-fault parsing corrupt DWARF debug information.
+# Lifetime: Fixed in 2.31
+Patch47: binutils-CVE-2018-7569.patch
+
+# Purpose: Fix seg-fault parsing corrupt COFF files.
+# Lifetime: Fixed in 2.31
+Patch48: binutils-CVE-2018-7208.patch
+
+# Purpose: Fix seg-fault parsing corrupt ELF files.
+# Lifetime: Fixed in 2.31
+Patch49: binutils-CVE-2018-10535.patch
+
+# Purpose: Fix seg-fault parsing corrupt DWARF debug information.
+# Lifetime: Fixed in 2.31
+Patch50: binutils-CVE-2018-10373.patch
+
+# Purpose: Fix seg-fault parsing corrupt DWARF debug information.
+# Lifetime: Fixed in 2.31
+Patch51: binutils-CVE-2018-10372.patch
+
+# Purpose: Fix seg-fault parsing a corrupt PE format file.
+# Lifetime: Fixed in 2.31
+Patch52: binutils-CVE-2018-10534.patch
+
+# Purpose: Fix seg-fault parsing a corrupt AOUT format file.
+# Lifetime: Fixed in 2.31
+Patch53: binutils-CVE-2018-7642.patch
+
+# Purpose: Fix seg-fault parsing corrupt DWARF debug information.
+# Lifetime: Fixed in 2.31
+Patch54: binutils-CVE-2018-7643.patch
+
+# Purpose: Fix seg-fault parsing corrupt ELF files.
+# Lifetime: Fixed in 2.31
+Patch55: binutils-CVE-2018-8945.patch
+
+# Purpose: Stop strip from crashing whilst removing .comment sections.
+# Lifetime: Fixed in 2.31
+Patch56: binutils-strip-fix.patch
+
+# Purpose: Prevent resource exhaustion attacks on the libiberty name
+# demangling code.
+# Lifetime: Fixed in 2.32
+Patch57: binutils-libiberty-demangler.patch
+
+# Purpose: Add the .attach-to-group pseudo-op to the assembler.
+# Lifetime: Permanent.
+Patch58: binutils-attach-to-group.patch
+
+# Purpose: Stop the x86_64 linker from optimizing PLT entries.
+# Lifetime: Permanent.
+Patch59: binutils-x86_64-disable-PLT-elision.patch
+
+# Purpose: Fix a possible memory corruption due to an integer overflow
+# when running the binutils as 32-bit binaries.
+# Lifetime: Fixed in 2.32
+Patch60: binutils-CVE-2018-1000876.patch
+
+# Purpose: Stop the BFD library from complaining about files with multiple
+# relocations against the same section. Allows examination of
+# special kernel modules.
+# Lifetime: Fixed in 2.33
+Patch61: binutils-multiple-relocs-for-same-section.patch
+
+
+# Purpose: A *temporary* patch to disable the generation of
+# R_X86_64_GOTPCRELX and R_X86_64_REX_GETPCRELX relocations by the
+# x86_64 assembler and the generations of the R_386_GOT32X
+# relocation by the x86 assembler. This is because these
+# relocations are unknown to the 2.25 version of the linker, and so
+# static libraries and object files built with the 2.27 assembler
+# (and without this patch) are incompatible. Unfortunately we need
+# to maintain backwards compatibility to the 2.25 linker for the
+# RHEL 7 product. See BZ 1506004 for more defails.
+# Lifetime: Keep in RHEL 7, discard for RHEL 8.
+Patch998: binutils-2.27-suppress-R_X86_64_GOTPCRELX.patch
+
+# Purpose: A *temporary* patch to disable checking for valid PowerPC64 TLBIE
+# instructions. This allows the PPC kernel to be built. See:
+# https://sourceware.org/ml/binutils/2015-05/msg00133.html
+# Lifetime: Delete in NEXT release.
+Patch999: binutils-SUPPRESS-PPC-TLBIE-CHECK.patch
+
+#---------------------------------------------------------------------------------
+
+Provides: bundled(libiberty)
+
+%define gold_arches %ix86 x86_64 %arm aarch64 %{power64} s390x
+
+%if %{with bootstrap}
+%define build_gold no
+%else
+%ifarch %gold_arches
+%define build_gold both
+%else
+%define build_gold no
+%endif
+%endif
+
+%if %{with debug}
+# Define this if you want to skip the strip step and preserve debug info.
+# Useful for testing.
+%define __debug_install_post : > %{_builddir}/%{?buildsubdir}/debugfiles.list
+%define debug_package %{nil}
+%endif
+
+Buildroot: %(mktemp -ud %{_tmppath}/%{name}-%{version}-%{release}-XXXXXX)
+
+BuildRequires: gcc
+
+# Gold needs bison in order to build gold/yyscript.c.
+# Bison needs m4.
+%if "%{build_gold}" == "both"
+BuildRequires: bison, m4, gcc-c++
+%endif
+
+%if %{without bootstrap}
+BuildRequires: gettext, flex, zlib-devel
+%endif
+
+%if %{with docs}
+BuildRequires: texinfo >= 4.0
+# BZ 920545: We need pod2man in order to build the manual pages.
+BuildRequires: /usr/bin/pod2man
+Requires(post): /sbin/install-info
+Requires(preun): /sbin/install-info
+%endif
+
+# Required for: ld-bootstrap/bootstrap.exp bootstrap with --static
+# It should not be required for: ld-elf/elf.exp static {preinit,init,fini} array
+%if %{with testsuite}
+# relro_test.sh uses dc which is part of the bc rpm, hence its inclusion here.
+BuildRequires: dejagnu, zlib-static, glibc-static, sharutils, bc
+%if "%{build_gold}" == "both"
+# The GOLD testsuite needs a static libc++
+BuildRequires: libstdc++-static
+%endif
+%endif
+
+Conflicts: gcc-c++ < 4.0.0
+
+# The higher of these two numbers determines the default ld.
+%{!?ld_bfd_priority: %global ld_bfd_priority 50}
+%{!?ld_gold_priority:%global ld_gold_priority 30}
+
+%if "%{build_gold}" == "both"
+Requires(post): coreutils
+Requires(post): %{_sbindir}/alternatives
+Requires(preun): %{_sbindir}/alternatives
+%endif
+
+# On ARM EABI systems, we do want -gnueabi to be part of the
+# target triple.
+%ifnarch %{arm}
+%define _gnu %{nil}
+%endif
+
+#---------------------------------------------------------------------------------
+
+%description
+Binutils is a collection of binary utilities, including ar (for
+creating, modifying and extracting from archives), as (a family of GNU
+assemblers), gprof (for displaying call graph profile data), ld (the
+GNU linker), nm (for listing symbols from object files), objcopy (for
+copying and translating object files), objdump (for displaying
+information from object files), ranlib (for generating an index for
+the contents of an archive), readelf (for displaying detailed
+information about binary files), size (for listing the section sizes
+of an object or archive file), strings (for listing printable strings
+from files), strip (for discarding symbols), and addr2line (for
+converting addresses to file and line).
+
+#---------------------------------------------------------------------------------
+
+%package devel
+Summary: BFD and opcodes static and dynamic libraries and header files
+Group: System Environment/Libraries
+Provides: binutils-static = %{version}-%{release}
+%if %{with docs}
+Requires(post): /sbin/install-info
+Requires(preun): /sbin/install-info
+%endif
+Requires: zlib-devel
+Requires: binutils = %{version}-%{release}
+Requires: coreutils
+
+%description devel
+This package contains BFD and opcodes static and dynamic libraries.
+
+The dynamic libraries are in this package, rather than a seperate
+base package because they are actually linker scripts that force
+the use of the static libraries. This is because the API of the
+BFD library is too unstable to be used dynamically.
+
+The static libraries are here because they are now needed by the
+dynamic libraries.
+
+Developers starting new projects are strongly encouraged to consider
+using libelf instead of BFD.
+
+#---------------------------------------------------------------------------------
+
+%prep
+%setup -q -n binutils-%{version}
+%patch01 -p0
+%patch02 -p0
+%patch03 -p1
+%patch04 -p1
+%patch05 -p1
+%patch07 -p1
+%patch08 -p0
+%patch09 -p0
+%patch10 -p1
+%patch11 -p1
+%patch12 -p1
+
+%patch14 -p1
+%patch15 -p1
+%patch16 -p1
+%patch17 -p1
+%patch18 -p0
+%patch19 -p1
+%patch20 -p1
+%patch21 -p1
+%patch22 -p1
+%patch23 -p1
+%patch24 -p1
+%patch25 -p1
+%patch26 -p1
+%patch27 -p1
+%patch28 -p1
+%patch29 -p1
+%patch30 -p1
+%patch31 -p1
+%patch32 -p1
+%patch33 -p1
+%patch34 -p1
+%patch35 -p1
+%patch36 -p1
+%patch37 -p1
+%patch38 -p1
+%patch39 -p1
+%patch40 -p1
+%patch41 -p1
+%patch42 -p1
+%patch43 -p1
+%patch44 -p1
+%patch45 -p1
+%patch46 -p1
+%patch47 -p1
+%patch48 -p1
+%patch49 -p1
+%patch50 -p1
+%patch51 -p1
+%patch52 -p1
+%patch53 -p1
+%patch54 -p1
+%patch55 -p1
+%patch56 -p1
+%patch57 -p1
+%patch58 -p1
+%patch59 -p1
+%patch60 -p1
+%patch61 -p1
+
+# TEMPORARY patches.
+%patch998 -p1
+%patch999 -p1
+
+# We cannot run autotools as there is an exact requirement of autoconf-2.59.
+
+# On ppc64 and aarch64, we might use 64KiB pages
+sed -i -e '/#define.*ELF_COMMONPAGESIZE/s/0x1000$/0x10000/' bfd/elf*ppc.c
+sed -i -e '/#define.*ELF_COMMONPAGESIZE/s/0x1000$/0x10000/' bfd/elf*aarch64.c
+sed -i -e '/common_pagesize/s/4 /64 /' gold/powerpc.cc
+sed -i -e '/pagesize/s/0x1000,/0x10000,/' gold/aarch64.cc
+# LTP sucks
+perl -pi -e 's/i\[3-7\]86/i[34567]86/g' */conf*
+sed -i -e 's/%''{release}/%{release}/g' bfd/Makefile{.am,.in}
+sed -i -e '/^libopcodes_la_\(DEPENDENCIES\|LIBADD\)/s,$, ../bfd/libbfd.la,' opcodes/Makefile.{am,in}
+# Build libbfd.so and libopcodes.so with -Bsymbolic-functions if possible.
+if gcc %{optflags} -v --help 2>&1 | grep -q -- -Bsymbolic-functions; then
+sed -i -e 's/^libbfd_la_LDFLAGS = /&-Wl,-Bsymbolic-functions /' bfd/Makefile.{am,in}
+sed -i -e 's/^libopcodes_la_LDFLAGS = /&-Wl,-Bsymbolic-functions /' opcodes/Makefile.{am,in}
+fi
+# $PACKAGE is used for the gettext catalog name.
+sed -i -e 's/^ PACKAGE=/ PACKAGE=%{?cross}/' */configure
+# Undo the name change to run the testsuite.
+for tool in binutils gas ld
+do
+ sed -i -e "2aDEJATOOL = $tool" $tool/Makefile.am
+ sed -i -e "s/^DEJATOOL = .*/DEJATOOL = $tool/" $tool/Makefile.in
+done
+touch */configure
+# Touch the .info files so that they are newer then the .texi files and
+# hence do not need to be rebuilt. This eliminates the need for makeinfo.
+# The -print is there just to confirm that the command is working.
+%if %{without docs}
+ find . -name *.info -print -exec touch {} \;
+%endif
+
+%ifarch %{power64} ppc64le
+%define _target_platform %{_arch}-%{_vendor}-%{_host_os}
+%endif
+
+#---------------------------------------------------------------------------------
+
+%build
+echo target is %{binutils_target}
+export CFLAGS="$RPM_OPT_FLAGS"
+
+CARGS=
+
+case %{binutils_target} in i?86*|sparc*|ppc*|s390*|sh*|arm*|aarch64*)
+ CARGS="$CARGS --enable-64-bit-bfd"
+ ;;
+esac
+
+case %{binutils_target} in ia64*)
+ CARGS="$CARGS --enable-targets=i386-linux"
+ ;;
+esac
+
+case %{binutils_target} in ppc*|ppc64*)
+ CARGS="$CARGS --enable-targets=spu"
+ ;;
+esac
+
+case %{binutils_target} in ppc64-*)
+ CARGS="$CARGS --enable-targets=powerpc64le-linux"
+ ;;
+esac
+
+case %{binutils_target} in ppc64le*)
+ CARGS="$CARGS --enable-targets=powerpc-linux"
+ ;;
+esac
+
+%if %{default_relro}
+ CARGS="$CARGS --enable-relro=yes"
+%else
+ CARGS="$CARGS --enable-relro=no"
+%endif
+
+%if 0%{?_with_debug:1}
+CFLAGS="$CFLAGS -O0 -ggdb2 -Wno-error -D_FORTIFY_SOURCE=0"
+%define enable_shared 0
+%endif
+
+# We could optimize the cross builds size by --enable-shared but the produced
+# binaries may be less convenient in the embedded environment.
+%configure \
+ --quiet \
+ --build=%{_target_platform} --host=%{_target_platform} \
+ --target=%{binutils_target} \
+%ifarch %gold_arches
+%if "%{build_gold}" == "both"
+ --enable-gold=default --enable-ld \
+%else
+ --enable-gold \
+%endif
+%endif
+%if %{isnative}
+ --with-sysroot=/ \
+%else
+ --enable-targets=%{_host} \
+ --with-sysroot=%{_prefix}/%{binutils_target}/sys-root \
+ --program-prefix=%{cross} \
+%endif
+%if %{enable_shared}
+ --enable-shared \
+%else
+ --disable-shared \
+%endif
+%if %{enable_deterministic_archives}
+ --enable-deterministic-archives \
+%else
+ --enable-deterministic-archives=no \
+%endif
+%if %{enable_lto}
+ --enable-lto \
+%endif
+%if %{default_compress_debug}
+ --enable-compressed-debug-sections=all \
+%else
+ --enable-compressed-debug-sections=none \
+%endif
+ $CARGS \
+ --enable-plugins \
+ --with-bugurl=http://bugzilla.redhat.com/bugzilla/
+
+%if %{with docs}
+make %{_smp_mflags} tooldir=%{_prefix} all
+make %{_smp_mflags} tooldir=%{_prefix} info
+%else
+make %{_smp_mflags} tooldir=%{_prefix} MAKEINFO=true all
+%endif
+
+# Do not use %%check as it is run after %%install where libbfd.so is rebuild
+# with -fvisibility=hidden no longer being usable in its shared form.
+%if %{without testsuite}
+echo ====================TESTSUITE DISABLED=========================
+%else
+make -k check < /dev/null || :
+echo ====================TESTING=========================
+cat {gas/testsuite/gas,ld/ld,binutils/binutils}.sum
+echo ====================TESTING END=====================
+for file in {gas/testsuite/gas,ld/ld,binutils/binutils}.{sum,log}
+do
+ ln $file binutils-%{_target_platform}-$(basename $file) || :
+done
+tar cjf binutils-%{_target_platform}.tar.bz2 binutils-%{_target_platform}-*.{sum,log}
+uuencode binutils-%{_target_platform}.tar.bz2 binutils-%{_target_platform}.tar.bz2
+rm -f binutils-%{_target_platform}.tar.bz2 binutils-%{_target_platform}-*.{sum,log}
+%endif
+
+#---------------------------------------------------------------------------------
+
+%install
+rm -rf %{buildroot}
+%if %{with docs}
+make install DESTDIR=%{buildroot}
+%else
+make install DESTDIR=%{buildroot} MAKEINFO=true
+%endif
+
+%if %{isnative}
+%if %{with docs}
+make prefix=%{buildroot}%{_prefix} infodir=%{buildroot}%{_infodir} install-info
+cp %{SOURCE3} %{buildroot}%{_infodir}
+%endif
+
+# Rebuild libiberty.a with -fPIC.
+# Future: Remove it together with its header file, projects should bundle it.
+make -C libiberty clean
+make CFLAGS="-g -fPIC $RPM_OPT_FLAGS" -C libiberty
+
+# Rebuild libbfd.a with -fPIC.
+# Without the hidden visibility the 3rd party shared libraries would export
+# the bfd non-stable ABI.
+make -C bfd clean
+make CFLAGS="-g -fPIC $RPM_OPT_FLAGS -fvisibility=hidden" -C bfd
+
+# Rebuild libopcodes.a with -fPIC.
+make -C opcodes clean
+make CFLAGS="-g -fPIC $RPM_OPT_FLAGS" -C opcodes
+
+install -m 644 bfd/libbfd.a %{buildroot}%{_libdir}
+install -m 644 libiberty/libiberty.a %{buildroot}%{_libdir}
+install -m 644 include/libiberty.h %{buildroot}%{_prefix}/include
+install -m 644 opcodes/libopcodes.a %{buildroot}%{_libdir}
+# Remove Windows/Novell only man pages
+rm -f %{buildroot}%{_mandir}/man1/{dlltool,nlmconv,windres,windmc}*
+%if %{without docs}
+rm -f %{buildroot}%{_mandir}/man1/{addr2line,ar,as,c++filt,elfedit,gprof,ld,nm,objcopy,objdump,ranlib,readelf,size,strings,strip}*
+rm -f %{buildroot}%{_infodir}/{as,bfd,binutils,gprof,ld}*
+%endif
+
+%if %{enable_shared}
+chmod +x %{buildroot}%{_libdir}/lib*.so*
+%endif # isnative
+
+# Prevent programs from linking against libbfd and libopcodes
+# dynamically, as they are change far too often.
+rm -f %{buildroot}%{_libdir}/lib{bfd,opcodes}.so
+
+# Remove libtool files, which reference the .so libs
+rm -f %{buildroot}%{_libdir}/lib{bfd,opcodes}.la
+
+# Sanity check --enable-64-bit-bfd really works.
+grep '^#define BFD_ARCH_SIZE 64$' %{buildroot}%{_prefix}/include/bfd.h
+# Fix multilib conflicts of generated values by __WORDSIZE-based expressions.
+%ifarch %{ix86} x86_64 ppc %{power64} s390 s390x sh3 sh4 sparc sparc64 arm
+sed -i -e '/^#include "ansidecl.h"/{p;s~^.*$~#include <bits/wordsize.h>~;}' \
+ -e 's/^#define BFD_DEFAULT_TARGET_SIZE \(32\|64\) *$/#define BFD_DEFAULT_TARGET_SIZE __WORDSIZE/' \
+ -e 's/^#define BFD_HOST_64BIT_LONG [01] *$/#define BFD_HOST_64BIT_LONG (__WORDSIZE == 64)/' \
+ -e 's/^#define BFD_HOST_64_BIT \(long \)\?long *$/#if __WORDSIZE == 32\
+#define BFD_HOST_64_BIT long long\
+#else\
+#define BFD_HOST_64_BIT long\
+#endif/' \
+ -e 's/^#define BFD_HOST_U_64_BIT unsigned \(long \)\?long *$/#define BFD_HOST_U_64_BIT unsigned BFD_HOST_64_BIT/' \
+ %{buildroot}%{_prefix}/include/bfd.h
+%endif
+touch -r bfd/bfd-in2.h %{buildroot}%{_prefix}/include/bfd.h
+
+# Generate .so linker scripts for dependencies; imported from glibc/Makerules:
+
+# This fragment of linker script gives the OUTPUT_FORMAT statement
+# for the configuration we are building.
+OUTPUT_FORMAT="\
+/* Ensure this .so library will not be used by a link for a different format
+ on a multi-architecture system. */
+$(gcc $CFLAGS $LDFLAGS -shared -x c /dev/null -o /dev/null -Wl,--verbose -v 2>&1 | sed -n -f "%{SOURCE2}")"
+
+tee %{buildroot}%{_libdir}/libbfd.so <<EOH
+/* GNU ld script */
+
+$OUTPUT_FORMAT
+
+/* The libz dependency is unexpected by legacy build scripts. */
+/* The libdl dependency is for plugin support. (BZ 889134) */
+INPUT ( %{_libdir}/libbfd.a -liberty -lz -ldl )
+EOH
+
+tee %{buildroot}%{_libdir}/libopcodes.so <<EOH
+/* GNU ld script */
+
+$OUTPUT_FORMAT
+
+INPUT ( %{_libdir}/libopcodes.a -lbfd )
+EOH
+
+%else # !isnative
+# For cross-binutils we drop the documentation.
+rm -rf %{buildroot}%{_infodir}
+# We keep these as one can have native + cross binutils of different versions.
+#rm -rf {buildroot}{_prefix}/share/locale
+#rm -rf {buildroot}{_mandir}
+rm -rf %{buildroot}%{_libdir}/libiberty.a
+%endif # !isnative
+
+# This one comes from gcc
+rm -f %{buildroot}%{_infodir}/dir
+rm -rf %{buildroot}%{_prefix}/%{binutils_target}
+
+%find_lang %{?cross}binutils
+%find_lang %{?cross}opcodes
+%find_lang %{?cross}bfd
+%find_lang %{?cross}gas
+%find_lang %{?cross}gprof
+cat %{?cross}opcodes.lang >> %{?cross}binutils.lang
+cat %{?cross}bfd.lang >> %{?cross}binutils.lang
+cat %{?cross}gas.lang >> %{?cross}binutils.lang
+cat %{?cross}gprof.lang >> %{?cross}binutils.lang
+
+if [ -x ld/ld-new ]; then
+ %find_lang %{?cross}ld
+ cat %{?cross}ld.lang >> %{?cross}binutils.lang
+fi
+if [ -x gold/ld-new ]; then
+ %find_lang %{?cross}gold
+ cat %{?cross}gold.lang >> %{?cross}binutils.lang
+fi
+
+#---------------------------------------------------------------------------------
+
+%clean
+rm -rf %{buildroot}
+
+#---------------------------------------------------------------------------------
+
+%post
+%if "%{build_gold}" == "both"
+%__rm -f %{_bindir}/%{?cross}ld
+%{_sbindir}/alternatives --install %{_bindir}/%{?cross}ld %{?cross}ld \
+ %{_bindir}/%{?cross}ld.bfd %{ld_bfd_priority}
+%{_sbindir}/alternatives --install %{_bindir}/%{?cross}ld %{?cross}ld \
+ %{_bindir}/%{?cross}ld.gold %{ld_gold_priority}
+%{_sbindir}/alternatives --auto %{?cross}ld
+%endif # both ld.gold and ld.bfd
+
+%if %{isnative}
+/sbin/ldconfig
+
+%if %{with docs}
+ /sbin/install-info --info-dir=%{_infodir} %{_infodir}/as.info.gz
+ /sbin/install-info --info-dir=%{_infodir} %{_infodir}/binutils.info.gz
+ /sbin/install-info --info-dir=%{_infodir} %{_infodir}/gprof.info.gz
+ /sbin/install-info --info-dir=%{_infodir} %{_infodir}/ld.info.gz
+ /sbin/install-info --info-dir=%{_infodir} %{_infodir}/standards.info.gz
+%endif # with docs
+%endif # isnative
+
+exit 0
+
+#---------------------------------------------------------------------------------
+
+%preun
+%if "%{build_gold}" == "both"
+if [ $1 = 0 ]; then
+ %{_sbindir}/alternatives --remove %{?cross}ld %{_bindir}/%{?cross}ld.bfd
+ %{_sbindir}/alternatives --remove %{?cross}ld %{_bindir}/%{?cross}ld.gold
+fi
+%endif # both ld.gold and ld.bfd
+
+%if %{isnative}
+if [ $1 = 0 ]; then
+ if [ -e %{_infodir}/binutils.info.gz ]
+ then
+ /sbin/install-info --delete --info-dir=%{_infodir} %{_infodir}/as.info.gz
+ /sbin/install-info --delete --info-dir=%{_infodir} %{_infodir}/binutils.info.gz
+ /sbin/install-info --delete --info-dir=%{_infodir} %{_infodir}/gprof.info.gz
+ /sbin/install-info --delete --info-dir=%{_infodir} %{_infodir}/ld.info.gz
+ fi
+ if [ -e %{_infodir}/standards.info.gz ]
+ then
+ /sbin/install-info --delete --info-dir=%{_infodir} %{_infodir}/standards.info.gz
+ fi
+fi
+%endif # isnative
+
+exit 0
+
+#---------------------------------------------------------------------------------
+
+%if %{isnative}
+%postun
+/sbin/ldconfig
+
+ if [ -e %{_infodir}/binutils.info.gz ]
+ then
+ /sbin/install-info --delete --info-dir=%{_infodir} %{_infodir}/as.info.gz
+ /sbin/install-info --delete --info-dir=%{_infodir} %{_infodir}/binutils.info.gz
+ /sbin/install-info --delete --info-dir=%{_infodir} %{_infodir}/gprof.info.gz
+ /sbin/install-info --delete --info-dir=%{_infodir} %{_infodir}/ld.info.gz
+ fi
+ if [ -e %{_infodir}/standards.info.gz ]
+ then
+ /sbin/install-info --delete --info-dir=%{_infodir} %{_infodir}/standards.info.gz
+ fi
+%endif # isnative
+
+#---------------------------------------------------------------------------------
+
+%files -f %{?cross}binutils.lang
+%defattr(-,root,root,-)
+%license COPYING COPYING3 COPYING3.LIB COPYING.LIB
+%doc README
+%{_bindir}/%{?cross}[!l]*
+
+%if "%{build_gold}" == "both"
+%{_bindir}/%{?cross}ld.*
+%ghost %{_bindir}/%{?cross}ld
+%else
+%{_bindir}/%{?cross}ld*
+%endif # both ld.gold and ld.bfd
+
+%if %{with docs}
+%{_mandir}/man1/*
+%{_infodir}/as.info.gz
+%{_infodir}/binutils.info.gz
+%{_infodir}/gprof.info.gz
+%{_infodir}/ld.info.gz
+%{_infodir}/standards.info.gz
+%endif # with docs
+
+%if %{enable_shared}
+%{_libdir}/lib*.so
+%exclude %{_libdir}/libbfd.so
+%exclude %{_libdir}/libopcodes.so
+%endif # enable_shared
+
+%if %{isnative}
+
+%if %{with docs}
+%{_infodir}/[^b]*info*
+%{_infodir}/binutils*info*
+%endif
+
+%files devel
+%defattr(-,root,root,-)
+%{_prefix}/include/*
+%{_libdir}/lib*.a
+%{_libdir}/libbfd.so
+%{_libdir}/libopcodes.so
+
+%if %{with docs}
+%{_infodir}/bfd*info*
+%endif # with docs
+
+%endif # isnative
+
+#---------------------------------------------------------------------------------
+%changelog
+* Tue Sep 10 2019 Nick Clifton <nickc@redhat.com> 2.27-42.base
+- Stop the BFD library from complaining about sections with multiple sets of relocations. (#1749085)
+
+* Mon Apr 15 2019 Nick Clifton <nickc@redhat.com> 2.27-41.base
+- Fix up some linker tests that fail because of the R_x86_64_GOTPCRELX patch. (#1699745)
+
+* Mon Jan 28 2019 Nick Clifton <nickc@redhat.com> 2.27-40.base
+- Enable gold for PowerPC and s390x. (#1670014)
+
+* Mon Jan 14 2019 Nick Clifton <nickc@redhat.com> 2.27-39.base
+- Fix a potential illegal memory access triggered by an integer overflow. (#1665884)
+
+* Tue Jan 08 2019 Nick Clifton <nickc@redhat.com> 2.27-38.base
+- Disable optimizations of x06_64 PLT entries. (#1624779)
+
+* Tue Jan 08 2019 Nick Clifton <nickc@redhat.com> 2.27-37.base
+- Add the .attach-to-group pseudo-op to the assembler. (#1652587)
+
+* Tue Jan 08 2019 Nick Clifton <nickc@redhat.com> 2.27-36.base
+- Prevent resource exhaustion attacks on libiberty's name demangling code. (#1598561)
+
+* Tue Jan 08 2019 Nick Clifton <nickc@redhat.com> 2.27-35.base
+- Stop strip crashing when removing .comment sections. (#1644632)
+
+* Wed May 30 2018 Nick Clifton <nickc@redhat.com> 2.27-34.base
+- Fix seg-fault parsing corrupt AOUT format files. (#1579799)
+- Fix seg-fault parsing corrupt DWARF2 debug information. (#1579802)
+- Fix seg-fault parsing corrupt ELF format files. (#1579801)
+
+* Thu May 17 2018 Nick Clifton <nickc@redhat.com> 2.27-33.base
+- Fix seg-fault parsing ELF files. (#1578979)
+- Fix seg-fault parsing DWARF-2 information. (#1579065)
+- Fix seg-fault parsing DWARF-2 information. (#1579051)
+- Fix seg-fault parsing a PE format file. (#1579019)
+
+* Wed May 16 2018 Nick Clifton <nickc@redhat.com> 2.27-32.base
+- Fix seg-fault parsing DWARF-1 information. (#1569580)
+- Fix seg-fault parsing DWARF-2 information. (#1569891)
+- Fix seg-fault parsing COFF files. (#1571917)
+
+* Wed May 02 2018 Nick Clifton <nickc@redhat.com> 2.27-31.base
+- Allow "lea foo@GOT, %reg" in PIC mode on the x86. (#1573872)
+
+* Fri Apr 20 2018 Nick Clifton <nickc@redhat.com> 2.27-30.base
+- Version bump in order to allow a rebuild, in order to work around a transient problem with the compose database.
+
+* Wed Apr 11 2018 Nick Clifton <nickc@redhat.com> 2.27-29.base
+- Add support for the GLOBALAUDIT dynamic linker tag.
+ (#1439351)
+
+* Wed Apr 11 2018 Nick Clifton <nickc@redhat.com> 2.27-28.base
+- Stop the x86_64 linker from crashing when asked to convert a reloc against the ABS section.
+ (#1557346)
+- Stop strip from replacing unknown relocs with null relocs.
+ (#1545386)
+
+* Thu Jan 11 2018 Nick Clifton <nickc@redhat.com> 2.27-27.base
+- Do enable relro by default for the PowerPC64 architecture.
+ (#1523946)
+
+* Thu Jan 04 2018 Nick Clifton <nickc@redhat.com> 2.27-26.base
+- Fix thinko in post-uninstall section.
+ (#1520899)
+
+* Tue Jan 02 2018 Nick Clifton <nickc@redhat.com> 2.27-25.base
+- Remove man and info files not needed when building without documentation.
+ (#1530339)
+
+* Tue Jan 02 2018 Nick Clifton <nickc@redhat.com> 2.27-24.base
+- Check for the existance of standards.info.gz before attempting to uninstall it.
+ (#1520899)
+
+* Tue Dec 19 2017 Nick Clifton <nickc@redhat.com> 2.27-23.base
+- Do not complain if the standards.info.gz file does not exist when uninstalling.
+ (#1520899)
+
+* Mon Dec 11 2017 Nick Clifton <nickc@redhat.com> 2.27-22.base
+- Do not enable relro by default for the PowerPC64 architecture.
+ (#1523946)
+
+* Thu Nov 16 2017 Nick Clifton <nickc@redhat.com> 2.27-21.base
+- Prevent the PowerPC64 linker from triggering a seg-fault when discarding dynamic sections.
+ (#1513014)
+
+* Thu Nov 02 2017 Nick Clifton <nickc@redhat.com> 2.27-20.base
+- Bump NVR so that the binutils rpms will be rebuilt, since they also have files that contain the offending relocs.
+ (#1508954)
+
+* Wed Oct 25 2017 Nick Clifton <nickc@redhat.com> 2.27-19.base
+- Suppress the generation of R_X86_64_GOTPCRELX, R_X86_64_REX_GETPCRELX and R_386_GOT32X relocations.
+ (#1506004)
+
+* Tue Oct 10 2017 Nick Clifton <nickc@redhat.com> 2.27-18.base
+- Update AArch64 copy reloc patch.
+ (#1430743)
+
+* Mon Sep 18 2017 Nick Clifton <nickc@redhat.com> 2.27-17.base
+- Add LNIA, SCV and RFSCV instructions from Power9.
+ (#1356856)
+
+* Wed Sep 06 2017 Nick Clifton <nickc@redhat.com> 2.27-16.base
+- Fix seg-fault when stripping s390x binaries.
+ (#14888890)
+
+* Wed Aug 30 2017 Nick Clifton <nickc@redhat.com> 2.27-15.base
+- Add support for creating a PT_S390_PGSTE segment in s390 binaries.
+ (#1485398)
+
+* Wed Aug 30 2017 Nick Clifton <nickc@redhat.com> 2.27-14.base
+- Add standards.info file to documentation distributed with the binutils package.
+ (#1467390)
+
+* Fri Aug 11 2017 Nick Clifton <nickc@redhat.com> 2.27-12.base
+- Generate an error when attempting to link non-PIC s390 objects in PIE mode.
+ (#1406430)
+
+* Fri Aug 11 2017 Nick Clifton <nickc@redhat.com> 2.27-11.base
+- Fix generation of dynamic COPY relocs for the AArch64.
+ (#1452170)
+
+* Wed Aug 09 2017 Nick Clifton <nickc@redhat.com> 2.27-10.base
+- Rebase to binutils 2.27
++ Retire: binutils-2.20.51.0.2-ia64-lib64.patch
++ Retire: binutils-2.20.51.0.10-copy-osabi.patch
++ Retire: binutils-rh1260158.patch
++ Retire: binutils-rh1300734.patch
++ Retire: binutils-2.25.1-aarch64-overflow-warnings.patch
++ Retire: binutils-2.25-aarch64-pr18668.patch
++ Retire: binutils-2.25.1-aarch64-pagesize.patch
++ Retire: binutils-rh1304451.patch
++ Retire: binutils-2.25.1-x86-Zepplin.patch
++ Retire: binutils-2.25.1-power9.patch
++ Retire: binutils-2.25.1-x86-mwaitx.patch
++ Retire: binutils-rh1162655.patch
++ Retire: binutils-2.25.1-aarch64-arch-extension.patch
++ Retire: binutils-2.25.1-s390-z13.patch
++ Retire: binutils-2.25.1-gold-resolving-to-hidden-symbols.patch
+- Sync with Pegas 1.1 binutils.
+- Import patch to add support for DWARF5 tags.
+ (#1472955)
+- Import patch to fix converting addresses into function names.
+ (#1465318)(#1452170)
+- Add support for ARMv8.2 ISA extensions.
+ (#1385959)
+
+* Tue Jul 25 2017 Nick Clifton <nickc@redhat.com> 2.25.1-33.base
+- Add support for new tags defined by version 5 of the DWARF standard.
+ (#1472955)
+
+* Tue Jul 25 2017 Nick Clifton <nickc@redhat.com> 2.25.1-32.base
+- Remove the minmax part of the objdump speedup patch.
+ (#1465318)
+
+* Tue May 09 2017 Nick Clifton <nickc@redhat.com> 2.25.1-31.base
+- Fix generation of PLT entries for s390 binaries.
+ (#1440168)
+
+* Thu May 04 2017 Nick Clifton <nickc@redhat.com> 2.25.1-28-base
+- Disable fix for 1406430. It breaks building real s390 executables.
+ (#1447209)
+ (#1406430)
+
+* Thu Apr 27 2017 Nick Clifton <nickc@redhat.com> 2.25.1-27-base
+- Fix infnite loop in linker when counting PowerPC stubs.
+ (#1406498)
+
+* Mon Jan 16 2017 Nick Clifton <nickc@redhat.com> 2.25.1-26-base
+- Speed up displaying disassembly when mixed with source code.
+ (#1311352)
+
+* Mon Jan 16 2017 Nick Clifton <nickc@redhat.com> 2.25.1-25-base
+- Fix GOLD so that it will not warn about references to hidden symbols in shared objects.
+ (#1326710)
+
+* Fri Jan 06 2017 Nick Clifton <nickc@redhat.com> 2.25.1-24-base
+- Fix thinko in previous patch.
+ (#1406430)
+
+* Fri Jan 06 2017 Nick Clifton <nickc@redhat.com> 2.25.1-23-base
+- Add code to detect attempts to link PIE and non-PIE S390 binaries.
+ (#1406430)
+
+* Mon Aug 08 2016 Nick Clifton <nickc@redhat.com> 2.25.1-22-base
+- Fix date format bug in changelog which was preventing package build.
+
+* Mon Aug 08 2016 Nick Clifton <nickc@redhat.com> 2.25.1-21-base
+- Add support for Z13 extensions to IBMs s390 architecture.
+ (#1364516)
+
+* Fri Jun 24 2016 Nick Clifton <nickc@redhat.com> 2.25.1-20-base
+- Import new PPC ISA 3.0 patch from FSF binutils.
+ (#1341730)
+
+* Mon Jun 13 2016 Nick Clifton <nickc@redhat.com> 2.25.1-19-base
+- Add support for the .arch_extension pseudo-op to the AArch64 port of GAS.
+ (#1276755)
+
+* Mon Jun 13 2016 Nick Clifton <nickc@redhat.com> 2.25.1-18-base
+- Update patch to fix AArch64 stub generation.
+ (#1243559)
+
+* Thu Jun 02 2016 Nick Clifton <nickc@redhat.com> 2.25.1-17-base
+- Close memory leak in "ar" archiver program.
+ (#1162655)
+- Retire the copy-osabi patch.
+ (#1252066)
+
+* Thu Jun 02 2016 Nick Clifton <nickc@redhat.com> 2.25.1-16-base
+- Version bump to allow adding 1300543 to the errata.
+ (#1300543)
+
+* Wed Jun 01 2016 Nick Clifton <nickc@redhat.com> 2.25.1-15-base
+- Extend Power9 patch to add new ISA 3.0 instructions.
+ (#1341730)
+
+* Wed May 25 2016 Nick Clifton <nickc@redhat.com> 2.25.1-14-base
+- Extend Release string to include ".base" thus ensuring that it
+ will not collide with a DTS release which might otherwise have
+ the same name.
+ (#1337617)
+
+* Mon May 23 2016 Nick Clifton <nickc@redhat.com> 2.25.1-13
+- Add support for Zeppelin x86 extensions.
+- Add support for the AMD MWAITX extension.
+- Add support for the PowerPC Power9 architecture.
+- Remove spurious binutils document references.
+ (#1335313)
+ (#1335684)
+ (#1333305)
+
+* Wed Apr 13 2016 Nick Clifton <nickc@redhat.com> 2.25.1-10
+- Allow the BFD library to locate debug info files below the /usr/lib/debug directory.
+ (#1311352)
+
+* Mon Apr 11 2016 Nick Clifton <nickc@redhat.com> 2.25.1-9
+- Housekeeping: Delete unused patches. Renumber existing patches.
+
+* Tue Mar 01 2016 Nick Clifton <nickc@redhat.com> 2.25.1-8
+- Fix PowerPC gas and ld testsuite failures.
+ (#1312876)
+
+* Tue Feb 23 2016 Nick Clifton <nickc@redhat.com> 2.25.1-7
+- Extend fix for AArch64 call veneers.
+ (#1243559)
+
+* Wed Feb 17 2016 Nick Clifton <nickc@redhat.com> 2.25.1-6
+- Add support for Intel Memory Protection Key instructions.
+ (#1304451)
+
+* Mon Feb 08 2016 Nick Clifton <nickc@redhat.com> 2.25.1-4
+- Improve warning message for overflowing AArch64 relocs.
+- Import patch to fix PR18668.
+- Ignore warning messages about duplicate FDE entries
+ (#1300543)
+ (#1300603)
+ (#1285614)
+ (#1243559)
+
+* Fri Jan 29 2016 Nick Clifton <nickc@redhat.com> 2.25.1-3
+- Experimental rebase on FSF 2.25.1 sources.
+ (#1341730)
+- Retire: patch11, patch12, patch13, patch14, patch15,
+ patch16, patch17, patch18, patch19, patch20, patch21,
+ patch22, patch23, patch24, patch25, patch26, patch27,
+ patch28, patch29, patch30, patch32, patch100, patch101,
+ patch102, patch110, patch111, patch112, patch113, patch114,
+ patch115, patch116, patch117, patch118, patch119, patch120,
+ patch121, patch201, patch202, patch203, patch204, patch205,
+ patch206, patch207, patch208, patch209, patch210, patch211,
+ patch212, patch300, patch301, patch302, patch303, patch304,
+ patch305, patch306, patch307, patch308, patch309, patch400,
+ patch401, patch402, patch403, patch404, patch405, patch406,
+ patch407, patch501
+- Add patch to suppress checking of PPC64 TLBIE instruction. [TEMPORARY]
+- Add fix for FSF PR 18879
+- Add fix for s390x linker testsuite failure.
+ (#1276755)
+ (#1260158)
+ (#1300734)
+ (#1288068)
+
+* Thu Jan 14 2016 Nick Clifton <nickc@redhat.com> 2.23.52.0.1-56
+- Remove __PPC__ checks from BFD library.
+ (#1261016)
+
+* Tue Oct 13 2015 Nick Clifton <nickc@redhat.com> 2.23.52.0.1-55
+- Add missing delta to patch that fixes parsing corrupted archives.
+ (#1162666)
+
+* Wed Jul 29 2015 Nick Clifton <nickc@redhat.com> 2.23.52.0.1-54
+- Import patch for PR 18270: Create AArch64 GOT entries for local symbols.
+ (#1238783)
+
+* Tue Jul 28 2015 Jeff Law <law@redhat.com> - 2.23.52.0.1-51
+- Fix incorrectly generated binaries and DSOs on PPC platforms.
+ (#1247126)
+
+* Mon Jun 29 2015 Nick Clifton <nickc@redhat.com> - 2.23.52.0.1-50
+- Fix memory corruption parsing corrupt archives.
+ (#1162666)
+
+* Mon Jun 29 2015 Nick Clifton <nickc@redhat.com> - 2.23.52.0.1-49
+- Fix directory traversal vulnerability.
+ (#1162655)
+
+* Mon Jun 29 2015 Nick Clifton <nickc@redhat.com> - 2.23.52.0.1-48
+- Fix stack overflow in SREC parser.
+ (#1162621)
+
+* Mon Jun 29 2015 Nick Clifton <nickc@redhat.com> - 2.23.52.0.1-47
+- Fix stack overflow whilst parsing a corrupt iHex file.
+ (#1162607)
+
+* Mon Jun 29 2015 Nick Clifton <nickc@redhat.com> - 2.23.52.0.1-46
+- Fix out of bounds memory accesses when parsing corrupt PE binaries.
+ (#1162594, #1162570)
+
+* Mon Jun 29 2015 Nick Clifton <nickc@redhat.com> - 2.23.52.0.1-45
+- Change strings program to default to -a. Fix problems parsing
+ files containg corrupt ELF group sections. (#1157276)
+
+* Tue Jun 23 2015 Jeff Law <law@redhat.com> - 2.23.52.0.1-44
+- Avoid reading beyond function boundary when disassembling.
+ (#1060282)
+
+- For binary ouput, we don't have an ELF bfd output so can't access
+ elf_elfheader. (#1226864)
+
+* Thu May 28 2015 Jeff Law <law@redhat.com> - 2.23.52.0.1-43
+- Do not discard stap probe note sections on aarch64 (#1225091)
+
+* Tue May 26 2015 Jeff Law <law@redhat.com> - 2.23.52.0.1-42
+- Clamp maxpagesize at 1 (rather than 0) to avoid segfaults
+ in the linker when passed a bogus max-page-size argument.
+ (#1203449)
+
+* Thu May 21 2015 Martin Sebor <msebor@redhat.com> - 2.23.52.0.1-41
+- Fixup bfd elf_link_add_object_symbols for ppc64 to prevent subsequent
+ uninitialized accesses elsewhere. (#1172766)
+
+* Thu May 7 2015 Jeff Law <law@redhat.com> - 2.23.52.0.1-40
+- Minor testsuite adjustments for PPC changes in -38/-39.
+ (#1183838)
+ Fix md_assemble for PPC to handle arithmetic involving the TOC
+ better. (#1183838)
+
+* Wed May 6 2015 Martin Sebor <msebor@redhat.com> - 2.23.52.0.1-39
+- Fix ppc64: segv in libbfd (#1172766).
+
+* Wed May 6 2015 Martin Sebor <msebor@redhat.com> - 2.23.52.0.1-38
+- Unconditionally apply ppc64le patches (#1183838).
+
+* Mon May 4 2015 Jeff Law <law@redhat.com> - 2.23.52.0.1-37
+- Andreas's backport of z13 and dependent fixes for s390,
+ including tesetcase fix from Apr 27, 2015.' (#1182153)
+
+* Tue Apr 7 2015 Jeff Law <law@redhat.com> - 2.23.52.0.1-35
+- Fixup testsuite for AArch64 (#1182111)
+- Add support for @localentry for LE PPC64 (#1194164)
+
+* Tue Mar 31 2015 Jeff Law <law@redhat.com> - 2.23.52.0.1-34
+- Do not install windmc(1) man page (#850832)
+
+* Fri Mar 27 2015 Jeff Law <law@redhat.com> - 2.23.52.0.1-33
+- Do not replace R_390_TLS_LE{32,64} with R_390_TLS_TPOFF for PIE
+ (#872148)
+- Enable relro by default for arm and aarch64 (#1203449)
+- Backport 3 RELRO improvements for ppc64/ppc64le from upstream
+ (#1175624)
+
+* Wed Mar 11 2015 Jeff Law <law@redhat.com> - 2.23.52.0.1-31
+- Backport upstream RELRO fixes. (#1200138)
+
+* Thu Jan 15 2015 Jeff Law <law@redhat.com> - 2.23.52.0.1-30
+- Fix syntax for multiple --enable-targets configure option.
+ (#1133147)
+
+* Thu Jan 8 2015 Jeff Law <law@redhat.com> - 2.23.52.0.1-29
+- Add support for crc instructions on aarch64 (#1179810)
+
+* Mon Jan 5 2015 Jeff Law <law@redhat.com> - 2.23.52.0.1-28
+- Bring back spu target for ppc64le which was accidentally lost
+ (#1133147)
+
+* Tue Dec 16 2014 Richard Henderson <rth@redhat.com> - 2.23.52.0.1-27
+- (Re-)Set ELF_COMMONPAGESIZE to 64k for ppc64le.
+ (#1174826)
+
+* Thu Sep 11 2014 Patsy Franklin <pfrankli@redhat.com> - 2.23.52.0.1-26
+- Enable Intel AVX-512VL, AVX-512BW, AVX-512DQ and SGX support.
+ (#1140375)
+
+* Wed Aug 27 2014 Jeff Law <law@redhat.com> - 2.23.52.0.1-25.9
+ Revert this change (handled elsewhere):
+- Additional patch from Alan to fix problems with ld --defsym.
+ (#1132732)
+
+* Mon Aug 25 2014 Jeff Law <law@redhat.com> - 2.23.52.0.1-23.9
+- Include powerpc-linux as a BFD target when building for ppc64le.
+ (#1133147).
+
+* Fri Aug 22 2014 Patsy Franklin <pfrankli@redhat.com> - 2.23.52.0.1-22.9
+- Reduce the size of aarch64 .debug_line; fix cfi encoding of fp registers;
+ add register names to dumping of aarch64 cfi data. Patch provided by rth.
+ Resolves: #1132641
+
+* Fri Aug 22 2014 Patsy Franklin <pfrankli@redhat.com> - 2.23.52.0.1-21.9
+- This fixes a problem seen on powerpc64le ELFv2 when creating a
+ function symbol alias with ld --defsym. st_other needs to be copied
+ from the source symbol to the alias in order to set up the local entry
+ offset for the alias.
+
+* Mon Aug 18 2014 Patsy Franklin <pfrankli@redhat.com> - 2.23.52.0.1-20.9
+- Correct handling of strong followed by weak def merging of st_other
+ Resolves: #1130479
+
+* Wed Aug 13 2014 Jeff Law <law@redhat.com> - 2.23.52.0.1-19.9
+- Add missing PPC opcodes
+ Resolves: #1090618
+
+* Mon Aug 11 2014 Jeff Law <law@redhat.com> - 2.23.52.0.1-18.9
+- Do not overwrite valid SONAME with empty string. (#1128279)
+ Resolves: #1128280
+
+* Mon Aug 4 2014 Aldy Hernandez <aldyh@redhat.com> - 2.23.52.0.1-17.9
+- Initial support for ppc64le.
+ Fix for bz#1125478
+
+* Thu Jun 26 2014 Richard Henderson <rth@redhat.com> - 2.23.52.0.1-16.9
+- Backport fix for movi.
+
+* Tue Jun 24 2014 Richard Henderson <rth@redhat.com> - 2.23.52.0.1-16.8
+- Backport support for IFUNCs.
+
+* Sat Jun 14 2014 Mark Salter <msalter@redhat.com> - 2.23.52.0.1-16.7
+- Backport support for full range of CRn in AArch64 system registers.
+ Fix for bz#1109497
+
+* Fri May 16 2014 Kyle McMartin <kyle@redhat.com> - 2.23.52.0.1-16.6
+- AArch64: Backport two patches from upstream fixing GOT handling.
+
+* Thu May 15 2014 Brendan Conoboy <blc@redhat.com> - 2.23.52.0.1-16.5
+- Rebuild for BZ#1098169
+
+* Fri May 09 2014 Kyle McMartin <kyle@redhat.com> - 2.23.52.0.1-16.4
+- AArch64: Backport two fixes from upstream and add a draft patch to
+ set DF_STATIC_TLS when emitting IE relocs. Also increase
+ ELF_COMMONPAGESIZE to 64K to match the kernel.
+
+* Wed Apr 16 2014 Richard Henderson <rth@redhat.com> - 2.23.52.0.1-16.3
+- Backport tls-relax-gdesc-ie fix
+
+* Thu Mar 13 2014 Richard Henderson <rth@redhat.com> - 2.23.52.0.1-16.2
+- Fix for rh1075827
+
+* Wed Feb 19 2014 Nick Clifton <nickc@redhat.com> - 2.23.52.0.1-16.1
+- Fix for rh1066712
+
+* Fri Jan 24 2014 Daniel Mach <dmach@redhat.com> - 2.23.52.0.1-16
+- Mass rebuild 2014-01-24
+
+* Mon Jan 13 2014 Jeff Law <law@redhat.com> - 2.23.52.0.1-15
+- Set _performance_build to get -O3 builds (#1051060).
+
+* Mon Jan 6 2014 Jeff Law <law@redhat.com> - 2.23.52.0.1-14
+- Fix two may-be-uninitialized issues exposed by changes in
+ compiler flags used to build binutils (#1048848).
+
+* Fri Dec 27 2013 Daniel Mach <dmach@redhat.com> - 2.23.52.0.1-13
+- Mass rebuild 2013-12-27
+
+* Thu Aug 29 2013 Jakub Jelinek <jakub@redhat.com> - 2.23.52.0.1-12
+- Add Intel AVX3, MPX and SHA support.
+- Add support for x86-64 -mcmodel=large -fpic TLS transitions. (#994244)
+
+* Fri Jul 5 2013 Jeff Law <law@redhat.com> - 2.23.52.0.1-11
+- Add support for TDB notes section (#805115)
+- Fix length operands for cdzt, cxzt czdt and czxt (#805115)
+
+* Wed Jul 3 2013 Jeff Law <law@redhat.com> - 2.23.52.0.1-10
+- Add libstdc++-static as a build requirement when running
+ the testsuite.
+- Add remaining power8 support (#731883)
+
+* Tue Jun 04 2013 Nick Clifton <nickc@redhat.com> - 2.23.52.0.1-9
+- Add support for the alternative debuging files generated by the DWZ program. (#965255)
+
+* Wed Apr 17 2013 Nick Clifton <nickc@redhat.com> - 2.23.52.0.1-8
+- Import patch for FSF mainline PR 15371 to fix ifunc references in shared libraries. (#927818)
+
+* Tue Apr 09 2013 Nick Clifton <nickc@redhat.com> - 2.23.52.0.1-7
+- Fix library search paths for 64-bit aarch64 linux targets. (#950098)
+
+* Wed Mar 13 2013 Nick Clifton <nickc@redhat.com> - 2.23.52.0.1-6
+- Add explicit requirement of /usr/bin/pod2man. (#920545)
+
+* Fri Mar 08 2013 Nick Clifton <nickc@redhat.com> - 2.23.52.0.1-5
+- Reverts patch for PR15149 - prevents report weak DT_NEEDED symbols. (#918003)
+
+* Wed Mar 06 2013 Nick Clifton <nickc@redhat.com> - 2.23.52.0.1-4
+- Enable building of GOLD for the ARM. (#908966)
+
+* Mon Mar 04 2013 Nick Clifton <nickc@redhat.com> - 2.23.52.0.1-3
+- Fix errors reported by version 5.0 of texinfo.
+
+* Fri Mar 01 2013 Nick Clifton <nickc@redhat.com> - 2.23.52.0.1-2
+- Fix the creation of index tables in 64-bit thin archives. (#915411)
+
+* Thu Feb 28 2013 Nick Clifton <nickc@redhat.com> - 2.23.52.0.1-1
+- Rebase on 2.23.51.0.1 release. (#916516)
+
+* Fri Feb 08 2013 Nick Clifton <nickc@redhat.com> - 2.23.51.0.9-2
+- Enable 64-bit BFD for aarch64. (#908904)
+
+* Mon Feb 04 2013 Nick Clifton <nickc@redhat.com> - 2.23.51.0.9-1
+- Rebase on 2.23.51.0.9 release. (#907089)
+- Retire binutils-2.23.51.0.8-arm-whitespace.patch.
+
+* Mon Jan 21 2013 Nick Clifton <nickc@redhat.com> - 2.23.51.0.8-4
+- Allow more whitespace in ARM instructions. (#892261)
+
+* Tue Jan 15 2013 Patsy Franklin <pfrankli@redhat.com> - 2.23.51.0.8-3
+- Add bc to BuildRequires when running the testsuite. (#895321)
+
+* Wed Jan 02 2013 Nick Clifton <nickc@redhat.com> - 2.23.51.0.8-2
+- Add runtime link with libdl. (#889134)
+
+* Wed Jan 02 2013 Nick Clifton <nickc@redhat.com> - 2.23.51.0.8-1
+- Rebase on 2.23.51.0.8 release. (#890382)
+
+* Fri Dec 21 2012 Nick Clifton <nickc@redhat.com> - 2.23.51.0.7-1
+- Rebase on 2.23.51.0.7 release. (#889432)
+
+* Tue Nov 27 2012 Nick Clifton <nickc@redhat.com> - 2.23.51.0.6-1
+- Rebase on 2.23.51.0.6 release. (#880508)
+
+* Tue Nov 13 2012 Nick Clifton <nickc@redhat.com> - 2.23.51.0.5-1
+- Rebase on 2.23.51.0.5 release. (#876141)
+- Retire binutils-2.23.51.0.3-arm-ldralt.patch
+
+* Tue Oct 23 2012 Nick Clifton <nickc@redhat.com> - 2.23.51.0.3-3
+- Rename ARM LDRALT instruction to LDALT. (#869025) PR/14575
+
+* Mon Oct 15 2012 Jon Ciesla <limburgher@gmail.com> - 2.23.51.0.3-2
+- Provides: bundled(libiberty)
+
+* Tue Oct 02 2012 Nick Clifton <nickc@redhat.com> - 2.23.51.0.3-1
+- Rebase on 2.23.51.0.3 release. (#858560)
+
+* Tue Sep 11 2012 Nick Clifton <nickc@redhat.com> - 2.23.51.0.2-1
+- Rebase on 2.23.51.0.2 release. (#856119)
+- Retire binutils-2.23.51.0.1-gold-keep.patch and binutils-rh805974.patch.
+
+* Tue Sep 4 2012 Jeff Law <law@redhat.com> 2.23.51.0.1-4
+- Correctly handle PLTOFF relocs for s390 IFUNCs.
+
+* Tue Aug 14 2012 Karsten Hopp <karsten@redhat.com> 2.23.51.0.1-3
+- apply F17 commit cd2fda5 to honour {powerpc64} macro (#834651)
+
+* Tue Aug 14 2012 Nick Clifton <nickc@redhat.com> - 2.23.51.0.1-2
+- Make GOLD honour KEEP directives in linker scripts (#8333355)
+
+* Wed Aug 08 2012 Nick Clifton <nickc@redhat.com> - 2.23.51.0.1-1
+- Rebase on 2.23.51.0.1 release. (#846433)
+- Retire binutils-2.22.52.0.4-dwz.patch, binutils-2.22.52.0.4-ar-4Gb.patch, binutils-2.22.52.0.4-arm-plt-refcount.patch, binutils-2.22.52.0.4-s390-64bit-archive.patch.
+
+* Thu Aug 02 2012 Nick Clifton <nickc@redhat.com> - 2.22.52.0.4-8
+- Make the binutils-devel package depend upon the binutils package. (#845082)
+
+* Thu Aug 02 2012 Nick Clifton <nickc@redhat.com> - 2.22.52.0.4-7
+- Disable checks that config.h is included before system headers. (#845084)
+
+* Tue Jul 17 2012 Nick Clifton <nickc@redhat.com> - 2.22.52.0.4-6
+- Use 64bit indicies in archives for s390 binaries. (#835957)
+
+* Thu Jul 05 2012 Nick Clifton <nickc@redhat.com> - 2.22.52.0.4-5
+- Catch attempts to create a broken symbol index with archives > 4Gb in size. (#835957)
+
+* Fri Jun 29 2012 Nick Clifton <nickc@redhat.com> - 2.22.52.0.4-4
+- Import fix for ld/14189. (#829311)
+
+* Fri Jun 29 2012 Nick Clifton <nickc@redhat.com> - 2.22.52.0.4-3
+- Fix handling of archives > 4Gb in size by importing patch for PR binutils/14302. (#835957)
+
+* Tue Jun 19 2012 Jakub Jelinek <jakub@redhat.com> - 2.22.52.0.4-2
+- Add minimal dwz -m support.
+
+* Wed Jun 06 2012 Nick Clifton <nickc@redhat.com> - 2.22.52.0.4-1
+- Rebase on 2.22.52.0.4 release. (#829027)
+
+* Tue May 08 2012 Nick Clifton <nickc@redhat.com> - 2.22.52.0.3-1
+- Rebase on 2.22.52.0.3 release. (#819823)
+
+* Mon Apr 30 2012 Nick Clifton <nickc@redhat.com> - 2.22.52.0.2-1
+- Rebase on 2.22.52.0.2 release. (#816514)
+- Retire binutils-2.22.52.0.1-weakdef.patch, binutils-2.22.52.0.1-ld-13621.patch, binutils-rh797752.patch, binutils-2.22.52.0.1-x86_64-hidden-ifunc.patch, binutils-2.22.52.0.1-tsx.patch and binutils-2.22.52.0.1-hidden-ifunc.patch.
+- Update binutils-2.22.52.0.1-reloc-on-by-default.patch.
+
+* Fri Apr 27 2012 Nick Clifton <nickc@redhat.com> - 2.22.52.0.1-12
+- Include demangle.h in the devel rpm.
+
+* Tue Apr 03 2012 Nick Clifton <nickc@redhat.com> - 2.22.52.0.1-11
+- Enable -zrelro by default for RHEL 7+. (#807831)
+
+* Fri Mar 16 2012 Jakub Jelinek <jakub@redhat.com> - 2.22.52.0.1-10
+- Fix up handling of hidden ifunc relocs on i?86
+
+* Wed Mar 14 2012 Jeff Law <law@redhat.com> - 2.22.52.0.1-9
+- Fix c++filt docs (2nd instance) (#797752)
+
+* Wed Mar 07 2012 Jakub Jelinek <jakub@redhat.com> - 2.22.52.0.1-8
+- Fix up handling of hidden ifunc relocs on x86_64
+- Add Intel TSX support
+
+* Tue Mar 06 2012 Nick Clifton <nickc@redhat.com> - 2.22.52.0.1-7
+- Enable -zrelro by default. (#621983 #807831)
+
+* Mon Feb 27 2012 Jeff Law <law@redhat.com> - 2.22.52.0.1-6
+- Fix c++filt docs (#797752)
+
+* Wed Feb 15 2012 Mark Wielaard <mjw@redhat.com> - 2.22.52.0.1-5
+- Add upstream ld/13621 'dangling global hidden symbol in symtab' patch.
+
+* Wed Feb 08 2012 Adam Williamson <awilliam@redhat.com> - 2.22.52.0.1-4
+- Actually apply the patch
+
+* Wed Feb 08 2012 Adam Williamson <awilliam@redhat.com> - 2.22.52.0.1-3
+- Add upstream weakdef.patch to fix RH #788107
+
+* Wed Feb 01 2012 Nick Clifton <nickc@redhat.com> - 2.22.52.0.1-2
+- Drat - forgot to upload the new tarball. Now done.
+
+* Wed Feb 01 2012 Nick Clifton <nickc@redhat.com> - 2.22.52.0.1-1
+- Rebase on 2.22.52 release.
+- Remove build-id.patch and gold-casts.patch as they are included in the 2.22.52 sources.
+
+* Fri Jan 13 2012 Nick Clifton <nickc@redhat.com> - 2.22-4
+- Fix bug in GOLD sources parsing signed integers in command line options.
+
+* Fri Jan 13 2012 Nick Clifton <nickc@redhat.com> - 2.22-3
+- Add casts for building gold with 4.7 version of gcc.
+
+* Thu Jan 12 2012 Fedora Release Engineering <rel-eng@lists.fedoraproject.org> - 2.22-2
+- Rebuilt for https://fedoraproject.org/wiki/Fedora_17_Mass_Rebuild
+
+* Tue Nov 22 2011 Nick Clifton <nickc@redhat.com> - 2.22-1
+- Rebase on 2.22 release.
+
+* Fri Sep 30 2011 Ricky Zhou <ricky@fedoraproject.org> - 2.21.53.0.2-2
+- Rebuild libopcodes.a with -fPIC.
+
+* Tue Aug 09 2011 Nick Clifton <nickc@redhat.com> - 2.21.53.0.2-1
+- Rebase on 2.21.53.0.2 tarball. Delete unneeded patches. (BZ 728677)
+
+* Tue Aug 02 2011 Nick Clifton <nickc@redhat.com> - 2.21.53.0.1-3
+- Update libiberty demangling. (BZ 727453)
+
+* Wed Jul 27 2011 Nick Clifton <nickc@redhat.com> - 2.21.53.0.1-2
+- Import Jakub Jelinek's patch to add support for displaying the contents of .debug_macro sections.
+
+* Tue Jul 19 2011 Nick Clifton <nickc@redhat.com> - 2.21.53.0.1-1
+- Rebase on 2.21.53.0.1 tarball. Delete unneeded patches. (BZ 712668)
+
+* Fri Jun 24 2011 Nick Clifton <nickc@redhat.com> - 2.21.52.0.1-5
+- Import fix for PR ld/12921.
+
+* Fri Jun 24 2011 Nick Clifton <nickc@redhat.com> - 2.21.52.0.1-4
+- Run "alternatives --auto" to restore ld symbolic link if it was manually configured. (BZ 661247)
+
+* Thu Jun 16 2011 Nick Clifton <nickc@redhat.com> - 2.21.52.0.1-3
+- Fix seg-fault attempting to find a function name without a symbol table. (BZ 713471)
+
+* Fri Jun 10 2011 Nick Clifton <nickc@redhat.com> - 2.21.52.0.1-2
+- Import fix for PR ld/12851 (BZ 711268)
+
+* Thu Jun 09 2011 Nick Clifton <nickc@redhat.com> - 2.21.52.0.1-1
+- Rebase on 2.21.52.0.1 tarball. (BZ 712025)
+
+* Tue May 17 2011 Nick Clifton <nickc@redhat.com> - 2.21.51.0.9-1
+- Rebase on 2.21.51.0.9 tarball. (BZ 703105)
+
+* Mon May 2 2011 Peter Robinson <pbrobinson@gmail.com> - 2.21.51.0.8-3
+- Add ARM to BFD checks
+
+* Mon Apr 11 2011 Nick Clifton <nickc@redhat.com> - 2.21.51.0.8-2
+- Delete plugins patch - enable plugins via configure option.
+
+* Mon Apr 11 2011 Nick Clifton <nickc@redhat.com> - 2.21.51.0.8-1
+- Rebase on 2.21.51.0.8 tarball.
+
+* Thu Mar 17 2011 Nick Clifton <nickc@redhat.com> - 2.21.51.0.7-1
+- Rebase on 2.21.51.0.7 tarball.
+
+* Tue Mar 08 2011 Nick Clifton <nickc@redhat.com> - 2.21.51.0.6-2
+- Enable gold plugins. (BZ 682852)
+
+* Thu Feb 10 2011 Nick Clifton <nickc@redhat.com> - 2.21.51.0.6-1
+- Rebase on 2.21.51.0.6 tarball.
+
+* Mon Feb 07 2011 Fedora Release Engineering <rel-eng@lists.fedoraproject.org> - 2.21.51.0.5-4
+- Rebuilt for https://fedoraproject.org/wiki/Fedora_15_Mass_Rebuild
+
+* Fri Jan 28 2011 Jakub Jelinek <jakub@redhat.com> - 2.21.51.0.5-3
+- Readd --build-id fix patch. (PR ld/12451)
+
+* Thu Jan 6 2011 Dan Horák <dan[at]danny.cz> - 2.21.51.0.5-2
+- fix build on non-gold arches like s390(x) where both ld and ld.bfd is installed
+
+* Wed Jan 5 2011 Nick Clifton <nickc@redhat.com> - 2.21.51.0.5-1
+- Rebase on 2.21.51.0.5 tarball.
+- Delete redundant patches.
+- Fix gold+ld configure command line option.
+
+* Fri Nov 5 2010 Dan Horák <dan[at]danny.cz> - 2.20.51.0.12-2
+- "no" is not valid option for --enable-gold
+
+* Thu Oct 28 2010 Nick Clifton <nickc@redhat.com> - 2.20.51.0.12-1
+- Rebase on 2.20.51.0.12 tarball. (BZ 582160)
+
+* Fri Sep 10 2010 Nick Clifton <nickc@redhat.com> - 2.20.51.0.11-1
+- Rebase on 2.20.51.0.11 tarball. (BZ 631771)
+
+* Fri Aug 20 2010 Nick Clifton <nickc@redhat.com> - 2.20.51.0.10-3
+- Allow ^ and ! characters in linker script wildcard patterns. (BZ 621742)
+
+* Fri Aug 20 2010 Nick Clifton <nickc@redhat.com> - 2.20.51.0.10-2
+- Fix seg fault in sec_merge_emit(). (BZ 623687)
+
+* Tue Aug 10 2010 Nick Clifton <nickc@redhat.com> - 2.20.51.0.10-1
+- Rebase on 2.20.51.0.10 tarball.
+- Import GOLD sources from binutils mainline as of 10 Aug 2010.
+
+* Wed Jun 30 2010 Nick Clifton <nickc@redhat.com> - 2.20.51.0.7-5
+- Rename the binutils-static package to binutils-devel in line with the Fedora packaging guidelines.
+
+* Wed Jun 9 2010 Nick Clifton <nickc@redhat.com> - 2.20.51.0.7-4
+- Allow GOLD linker to parse "-l<name>" directives inside INPUT statements in linker scripts. (BZ 600553)
+
+* Tue May 4 2010 Nick Clifton <nickc@redhat.com> - 2.20.51.0.7-3
+- Allow unique symbols in archive maps.
+
+* Tue Apr 20 2010 Nick Clifton <nickc@redhat.com> - 2.20.51.0.7-2
+- Merge binutils-devel package into binutils-static package. (BZ 576300)
+
+* Thu Apr 8 2010 Nick Clifton <nickc@redhat.com> - 2.20.51.0.7-1
+- Rebase on 2.20.51.0.7 tarball.
+- Delete redundant patches:
+ binutils-2.20.51.0.2-add-needed.patch,
+ binutils-2.20.51.0.2-do-not-set-ifunc.patch,
+ binutils-2.20.51.0.2-enable-gold.patch,
+ binutils-2.20.51.0.2-gas-expr.patch,
+ binutils-2.20.51.0.2-ifunc-ld-s.patch,
+ binutils-2.20.51.0.2-lwp.patch,
+ binutils-2.20.51.0.2-ppc-hidden-plt-relocs.patch,
+ binutils-2.20.51.0.2-x86-hash-table.patch,
+- Do not allow unique symbols to be bound locally. (PR ld/11434)
+- Add support for DWARF4 debug information.
+
+* Thu Mar 4 2010 Nick Clifton <nickc@redhat.com> - 2.20.51.0.2-17
+- Do not set ELFOSABI_LINUX on binaries which just link to IFUNC using DSOs. (BZ 568941)
+
+* Tue Mar 2 2010 Nick Clifton <nickc@redhat.com> - 2.20.51.0.2-16
+- Copy the OSABI field in ELF headers, if set. (BZ 568921)
+
+* Fri Feb 12 2010 Nick Clifton <nickc@redhat.com> - 2.20.51.0.2-15
+- Create separate static and devel sub-packages. (BZ 556040)
+
+* Tue Feb 2 2010 Nick Clifton <nickc@redhat.com> - 2.20.51.0.2-14
+- Fix seg-fault when linking mixed x86 and x86_64 binaries. (BZ 487472)
+
+* Fri Jan 22 2010 Nick Clifton <nickc@redhat.com> - 2.20.51.0.2-13
+- Add a requirement for the coreutils. (BZ 557006)
+
+* Wed Jan 20 2010 Nick Clifton <nickc@redhat.com> - 2.20.51.0.2-12
+- Fix --no-copy-dt-needed so that it will not complain about weak references.
+
+* Fri Dec 18 2009 Nick Clifton <nickc@redhat.com> - 2.20.51.0.2-11
+- Add missing part of PR 11088 patch.
+
+* Thu Dec 17 2009 Nick Clifton <nickc@redhat.com> - 2.20.51.0.2-10
+- Apply patch for PR 11088. (BZ 544149)
+
+* Wed Dec 9 2009 Nick Clifton <nickc@redhat.com> - 2.20.51.0.2-9
+- Apply patch for PR 10856. (BZ 544358)
+
+* Tue Dec 1 2009 Roland McGrath <roland@redhat.com> - 2.20.51.0.2-8
+- Build gold only for x86 flavors until others are tested.
+
+* Tue Nov 24 2009 Roland McGrath <roland@redhat.com> - 2.20.51.0.2-7
+- Add support for building gold.
+
+* Mon Nov 9 2009 Jakub Jelinek <jakub@redhat.com> 2.20.51.0.2-5
+- Fix up --copy-dt-needed-entries default. (Nick Clifton)
+
+* Mon Nov 9 2009 Jakub Jelinek <jakub@redhat.com> 2.20.51.0.2-4
+- Fix ld -s with IRELATIVE relocations. (BZ 533321, PR ld/10911)
+- Add AMD Orochi LWP support, fix FMA4 support.
+
+* Thu Nov 05 2009 Nick CLifton <nickc@redhat.com> 2.20.51.0.2-3
+- Rename --add-needed to --copy-dt-needed-entries and improve error message about unresolved symbols in DT_NEEDED DSOs.
+
+* Tue Oct 27 2009 Jan Kratochvil <jan.kratochvil@redhat.com> 2.20.51.0.2-2
+- Fix rpm --excludedocs (BZ 515922).
+- Fix spurious scriplet errors by `exit 0'. (BZ 517979, Nick Clifton)
+
+* Mon Oct 12 2009 Nick Clifton <nickc@redhat.com> 2.20.51.0.2-1
+- Rebase on 2.20 tarball.
+- Remove redundant moxie patch.
+- Remove redundant unique is global patch.
+- Remove redundant cxxfilt java doc patch.
+
+* Tue Sep 29 2009 Jan Kratochvil <jan.kratochvil@redhat.com> 2.19.51.0.14-32
+- Remove spurious description of nonexistent --java switch for cxxfilt.
+
+* Thu Aug 6 2009 Jakub Jelinek <jakub@redhat.com> 2.19.51.0.14-31
+- Fix strip on objects with STB_GNU_UNIQUE symbols. (BZ 515700, PR binutils/10492)
+
+* Fri Jul 24 2009 Fedora Release Engineering <rel-eng@lists.fedoraproject.org> - 2.19.51.0.14-30
+- Rebuilt for https://fedoraproject.org/wiki/Fedora_12_Mass_Rebuild
+
+* Wed Jul 22 2009 Nick Clifton <nickc@redhat.com> 2.19.51.0.11-28
+- Rebase sources on 2.19.51.0.14 tarball. Gain fixes for PRs 10429 and 10433.
+
+* Wed Jul 22 2009 Nick Clifton <nickc@redhat.com> 2.19.51.0.11-28
+- Rebase sources on 2.19.51.0.13 tarball. Remove redundant orphan section placement patch. (BZ 512937)
+
+* Tue Jul 14 2009 Nick Clifton <nickc@redhat.com> 2.19.51.0.11-27
+- Add patch to allow moxie target to build, and hence --enable-targets=all to work.
+
+* Tue Jul 14 2009 Nick Clifton <nickc@redhat.com> 2.19.51.0.11-26
+- Import orphan section placement patch from mainline. (BZ 510384)
+
+* Tue Jul 14 2009 Nick Clifton <nickc@redhat.com> 2.19.51.0.11-25
+- Fix build-id patch to avoid memory corruption. (BZ 501582)
+
+* Sat Jul 11 2009 Jan Kratochvil <jan.kratochvil@redhat.com> 2.19.51.0.11-24
+- Provide uuencode output of the testsuite results.
+
+* Tue Jun 30 2009 Nick Clifton <nickc@redhat.com> 2.19.51.0.11-23
+- Rebase sources on the 2.19.51.0.11 tarball.
+
+* Mon Jun 22 2009 Nick Clifton <nickc@redhat.com> 2.19.51.0.10-22
+- Rebase sources on the 2.19.51.0.10 tarball.
+
+* Thu Jun 11 2009 Nick Clifton <nickc@redhat.com> 2.19.51.0.2-21
+- Do not attempt to set execute permission on non-regular files. (BZ 503426)
+
+* Tue Jun 9 2009 Jakub Jelinek <jakub@redhat.com> 2.19.51.0.2-20
+- Fix .cfi_* skip over >= 64KB of code. (PR gas/10255)
+
+* Wed May 27 2009 Nick Clifton <nickc@redhat.com> 2.19.51.0.2-19
+- Import fix for binutils PR #9938. (BZ 500295)
+
+* Wed Apr 15 2009 Nick Clifton <nickc@redhat.com> 2.19.51.0.2-18
+- Update IBM Power 7 support patch to fix tlbilx opcode. (BZ 494718)
+
+* Tue Mar 17 2009 Nick Clifton <nickc@redhat.com> 2.19.51.0.2-17
+- Add glibc-static to BuildRequires when running the testsuite.
+
+* Thu Mar 05 2009 Nick Clifton <nickc@redhat.com> 2.19.51.0.2-16
+- Add IBM Power7 support. (BZ 487887)
+
+* Mon Mar 02 2009 Nick Clifton <nickc@redhat.com> 2.19.51.0.2-15
+- Add IFUNC support. (BZ 465302)
+
+* Mon Feb 23 2009 Fedora Release Engineering <rel-eng@lists.fedoraproject.org> - 2.19.51.0.2-14
+- Rebuilt for https://fedoraproject.org/wiki/Fedora_11_Mass_Rebuild
+
+* Mon Feb 23 2009 Jan Kratochvil <jan.kratochvil@redhat.com> 2.19.50.0.2-13
+- Rediff the symbolic-envvar-revert patch to comply with rpm patch --fuzz=0.
+
+* Thu Feb 5 2009 Nick Clifton <nickc@redhat.com> 2.19.51.0.2-12
+- Rebase sources on 2.19.51.0.2 tarball. Remove linkonce-r-discard and
+ gcc-expect-table patches.
+
+* Mon Feb 2 2009 Jan Kratochvil <jan.kratochvil@redhat.com> 2.19.50.0.1-11
+- Fix .eh_frame_hdr build also for .gcc_except_table LSDA refs (BZ 461675).
+
+* Fri Jan 23 2009 Nick Clifton <nickc@redhat.com> 2.19.50.0.1-10
+- Only require dejagnu if the testsuites are going to be run. (BZ 481169)
+
+* Sat Nov 29 2008 Nick Clifton <nickc@redhat.com> 2.19.50.0.1-8
+- Add build-id patch to ensure that section contents are incorporated
+ into a build id. (BZ 472152)
+
+* Fri Nov 21 2008 Nick Clifton <nickc@redhat.com> 2.19.50.0.1
+- Rebase sources on 2.19.50.0.1 tarball. Update all patches, trimming
+ those that are no longer needed.
+
+* Thu Oct 30 2008 Jan Kratochvil <jan.kratochvil@redhat.com> 2.18.50.0.9-7
+- Fix %%{_prefix}/include/bfd.h on 32-bit hosts due the 64-bit BFD target
+ support from 2.18.50.0.8-2 (BZ 468495).
+
+* Thu Oct 30 2008 Jan Kratochvil <jan.kratochvil@redhat.com> 2.18.50.0.9-6
+- binutils-devel now requires zlib-devel (BZ 463101 comment 5).
+- Fix complains on .gnu.linkonce.r relocations to their discarded
+ .gnu.linkonce.t counterparts.
+
+* Mon Sep 22 2008 Jan Kratochvil <jan.kratochvil@redhat.com> 2.18.50.0.9-5
+- Remove %%makeinstall to comply with the spu-binutils review (BZ 452211).
+
+* Mon Sep 22 2008 Jan Kratochvil <jan.kratochvil@redhat.com> 2.18.50.0.9-4
+- Fix *.so scripts for multilib linking (BZ 463101, suggested by Jakub Jelinek).
+
+* Sun Sep 21 2008 Jan Kratochvil <jan.kratochvil@redhat.com> 2.18.50.0.9-3
+- Provide libbfd.so and libopcodes.so for automatic dependencies (BZ 463101).
+- Fix .eh_frame_hdr build on C++ files with discarded common groups (BZ 458950).
+- Provide --build and --host to fix `rpmbuild --target' biarch builds.
+- Include %%{binutils_target}- filename prefix for binaries for cross builds.
+- Fix multilib conflict on %%{_prefix}/include/bfd.h's BFD_HOST_64BIT_LONG_LONG.
+
+* Mon Sep 15 2008 Jan Kratochvil <jan.kratochvil@redhat.com> 2.18.50.0.9-2
+- Package review, analysed by Jon Ciesla and Patrice Dumas (BZ 225615).
+ - build back in the sourcedir without problems as gasp is no longer included.
+ - Fix the install-info requirement.
+ - Drop the needless gzipping of the info files.
+ - Provide Obsoletes versions.
+ - Use the %%configure macro.
+
+* Sat Aug 30 2008 Jan Kratochvil <jan.kratochvil@redhat.com> 2.18.50.0.9-1
+- Update to 2.18.50.0.9.
+ - Drop the ppc-only spu target pre-build stage (BZ 455242).
+ - Drop parsing elf64-i386 files for kdump PAE vmcore dumps (BZ 457189).
+- New .spec BuildRequires zlib-devel (/-static) for compressed sections.
+- Update .spec Buildroot to be more unique.
+
+* Fri Aug 1 2008 Jan Kratochvil <jan.kratochvil@redhat.com> 2.18.50.0.8-2
+- Fix parsing elf64-i386 files for kdump PAE vmcore dumps (BZ 457189).
+- Turn on 64-bit BFD support for i386, globally enable AC_SYS_LARGEFILE.
+- `--with debug' builds now with --disable-shared.
+- Removed a forgotten unused ld/eelf32_spu.c workaround from 2.18.50.0.8-1.
+
+* Thu Jul 31 2008 Jan Kratochvil <jan.kratochvil@redhat.com> 2.18.50.0.8-1
+- Update to 2.18.50.0.8.
+ - Drop the .clmul -> .pclmul renaming backport.
+- Add %%{binutils_target} macro to support building cross-binutils.
+ (David Woodhouse)
+- Support `--without testsuite' to suppress the testsuite run.
+- Support `--with debug' to build without optimizations.
+- Refresh the patchset with fuzz 0 (for new rpmbuild).
+- Enable the spu target on ppc/ppc64 (BZ 455242).
+
+* Wed Jul 16 2008 Jan Kratochvil <jan.kratochvil@redhat.com> 2.18.50.0.6-4
+- include the `dist' tag in the Release number
+- libbfd.a symbols visibility is now hidden (for #447426, suggested by Jakub)
+
+* Wed Jul 16 2008 Jan Kratochvil <jan.kratochvil@redhat.com> 2.18.50.0.6-3
+- rebuild libbfd.a with -fPIC for inclusion into shared libraries (#447426)
+
+* Tue Apr 8 2008 Jakub Jelinek <jakub@redhat.com> 2.18.50.0.6-2
+- backport .clmul -> .pclmul renaming
+
+* Fri Apr 4 2008 Jakub Jelinek <jakub@redhat.com> 2.18.50.0.6-1
+- update to 2.18.50.0.6
+ - Intel AES, CLMUL, AVX/FMA support
+
+* Mon Mar 3 2008 Jakub Jelinek <jakub@redhat.com> 2.18.50.0.4-2
+- revert aranges optimization (Alan Modra, BZ#5303, BZ#5755)
+- fix ld-shared testcase for GCC 4.3 (H.J. Lu)
+
+* Fri Feb 29 2008 Jakub Jelinek <jakub@redhat.com> 2.18.50.0.4-1
+- update to 2.18.50.0.4
+
+* Tue Feb 19 2008 Fedora Release Engineering <rel-eng@fedoraproject.org> 2.18.50.0.3-2
+- Autorebuild for GCC 4.3
+
+* Wed Dec 12 2007 Jakub Jelinek <jakub@redhat.com> 2.18.50.0.3-1
+- update to 2.18.50.0.3
+ - fix build with recent makeinfo (#415271)
+
+* Thu Aug 16 2007 Jakub Jelinek <jakub@redhat.com> 2.17.50.0.18-1
+- update to 2.17.50.0.18
+ - GPLv3+
+ - preserve .note.gnu.build-id in objcopy --only-keep-debug (#251935)
+ - fix sparc64/alpha broken by --build-id patch (#252936)
+- update License tag
+- fix ld crash with --build-id and non-ELF output format (Alan Modra, BZ#4923)
+
+* Tue Jul 31 2007 Jakub Jelinek <jakub@redhat.com> 2.17.50.0.17-7
+- fix ppc32 secure PLT detection (Alan Modra)
+
+* Wed Jul 25 2007 Jakub Jelinek <jakub@redhat.com> 2.17.50.0.17-6
+- rebuilt to make sure even libbfd.so and libopcodes.so aren't
+ broken by #249435
+
+* Tue Jul 24 2007 Jakub Jelinek <jakub@redhat.com> 2.17.50.0.17-5
+- add .note.gnu.build-id into default linker script (#249435)
+
+* Tue Jul 24 2007 Jakub Jelinek <jakub@redhat.com> 2.17.50.0.17-4
+- don't kill the %%{_gnu} part of target name on arm
+ (Lennert Buytenhek, #243516)
+- create just one PT_NOTE segment header for all consecutive SHT_NOTE
+ sections
+
+* Wed Jul 18 2007 Roland McGrath <roland@redhat.com> 2.17.50.0.17-3
+- fix for ld --build-id
+
+* Sun Jul 15 2007 Roland McGrath <roland@redhat.com> 2.17.50.0.17-2
+- ld --build-id support
+
+* Wed Jun 27 2007 Jakub Jelinek <jakub@redhat.com> 2.17.50.0.17-1
+- update to 2.17.50.0.17
+
+* Tue Jun 12 2007 Jakub Jelinek <jakub@redhat.com> 2.17.50.0.16-1
+- update to 2.17.50.0.16
+
+* Sat Apr 14 2007 Jakub Jelinek <jakub@redhat.com> 2.17.50.0.12-4
+- fix linking non-ELF input objects into ELF output (#235747)
+
+* Wed Mar 14 2007 Jakub Jelinek <jakub@redhat.com> 2.17.50.0.12-3
+- don't require matching ELF_OSABI for target vecs with ELFOSABI_NONE,
+ only prefer specific osabi target vecs over the generic ones
+ (H.J.Lu, #230964, BZ#3826)
+- build libbfd.so and libopcodes.so with -Bsymbolic-functions
+
+* Fri Mar 2 2007 Jakub Jelinek <jakub@redhat.com> 2.17.50.0.12-2
+- ignore install-info errors from scriptlets (#223678)
+
+* Thu Mar 1 2007 Jakub Jelinek <jakub@redhat.com> 2.17.50.0.12-1
+- update to 2.17.50.0.12
+- revert the misdesigned LD_SYMBOLIC{,_FUNCTIONS} env var support,
+ only support -Bsymbolic/-Bsymbolic-functions/--dynamic-list*
+
+* Mon Jan 8 2007 Jakub Jelinek <jakub@redhat.com> 2.17.50.0.9-1
+- update to 2.17.50.0.9
+- fix tekhex reader
+
+* Sat Dec 23 2006 Jakub Jelinek <jakub@redhat.com> 2.17.50.0.8-2
+- fix --as-needed on ppc64 (#219629)
+
+* Sun Dec 3 2006 Jakub Jelinek <jakub@redhat.com> 2.17.50.0.8-1
+- update to 2.17.50.0.8
+- initialize frch_cfi_data (BZ#3607)
+
+* Fri Dec 1 2006 Jakub Jelinek <jakub@redhat.com> 2.17.50.0.7-1
+- update to 2.17.50.0.7
+ - .cfi_personality and .cfi_lsda directives, per subsection .cfi_*
+ directives, better .eh_frame CIE merging
+
+* Thu Nov 9 2006 Jakub Jelinek <jakub@redhat.com> 2.17.50.0.6-3
+- fix popcnt instruction assembly and disassembly on amd64 (#214767)
+
+* Mon Oct 23 2006 Jakub Jelinek <jakub@redhat.com> 2.17.50.0.6-2
+- update to 2.17.50.0.6
+ - fix for section relative linker script defined symbols in
+ empty sections (#207598, BZ#3267)
+ - fix handling of DW_CFA_set_loc in .eh_frame optimizations
+ - fix R_PPC_{PLT,GOT{,_TLSGD,_TLSLD,_TPREL,_DTPREL}}16_HA relocation
+ handling with weak undefined symbols (Alan Modra, #211094)
+
+* Tue Sep 12 2006 Jakub Jelinek <jakub@redhat.com> 2.17.50.0.3-6
+- fix multilib conflict in %%{_prefix}/include/bfd.h
+
+* Tue Sep 12 2006 Jakub Jelinek <jakub@redhat.com> 2.17.50.0.3-5
+- fix efi-app-ia64 magic number (#206002, BZ#3171)
+
+* Tue Sep 5 2006 Jakub Jelinek <jakub@redhat.com> 2.17.50.0.3-4
+- link libopcodes*.so against libbfd*.so (#202327)
+- split *.a and header files into binutils-devel
+
+* Fri Aug 18 2006 Jakub Jelinek <jakub@redhat.com> 2.17.50.0.3-3
+- on ppc and ppc64 increase default -z commonpagesize to 64K (#203001)
+
+* Fri Jul 28 2006 Alexandre Oliva <aoliva@redhat.com> 2.17.50.0.3-2
+- do not infer x86 arch implicitly based on instruction in the input
+ (#200330)
+
+* Mon Jul 17 2006 Jakub Jelinek <jakub@redhat.com> 2.17.50.0.3-1
+- update to 2.17.50.0.3
+
+* Fri Jul 14 2006 Jakub Jelinek <jakub@redhat.com> 2.17.50.0.2-8
+- add support for new AMDFAM10 instructions (#198281, IT#97662)
+- add -march=/-mtune= gas support on x86/x86-64
+- x86/x86-64 nop insn improvements
+- fix DT_GNU_HASH shift count value computation
+
+* Tue Jul 11 2006 Jakub Jelinek <jakub@redhat.com> 2.17.50.0.2-7
+- add DT_GNU_HASH support (--hash-style=gnu and --hash-style=both
+ ld options)
+
+* Thu Jun 29 2006 Jakub Jelinek <jakub@redhat.com> 2.17.50.0.2-4
+- fix i?86 TLS GD->IE transition in executables (#196157, BZ#2513)
+
+* Mon Jun 19 2006 Jakub Jelinek <jakub@redhat.com> 2.17.50.0.2-3
+- fix two places in ld that misbehaved with MALLOC_PERTURB_=N
+- fix .tls_common handling in relocatable linking
+
+* Mon Jun 5 2006 Jakub Jelinek <jakub@redhat.com> 2.17.50.0.2-2
+- fix --as-needed (Alan Modra, #193689, BZ#2721)
+
+* Thu Jun 1 2006 Jakub Jelinek <jakub@redhat.com> 2.17.50.0.2-1
+- update to 2.17.50.0.2
+- update from CVS to 20060601
+- speed up the ELF linker by caching the result of kept section check
+ (H.J. Lu)
+
+* Tue May 9 2006 Jakub Jelinek <jakub@redhat.com> 2.17.50.0.1-1
+- update to 2.17.50.0.1
+
+* Fri Mar 31 2006 Jakub Jelinek <jakub@redhat.com> 2.16.91.0.6-6
+- fix ld error message formatting, so that collect2 parser can
+ parse it again for g++ -frepo (#187142)
+
+* Thu Mar 9 2006 Alexandre Oliva <aoliva@redhat.com> 2.16.91.0.6-4
+- fix relaxation of TLS GD to LE on PPC (#184590)
+
+* Fri Mar 3 2006 Jakub Jelinek <jakub@redhat.com> 2.16.91.0.6-3
+- support DW_CFA_val_{offset,offset_sf,expression} in readelf/objdump
+
+* Tue Feb 28 2006 Jakub Jelinek <jakub@redhat.com> 2.16.91.0.6-2
+- add MNI support on i?86/x86_64 (#183080)
+- support S signal frame augmentation flag in .eh_frame,
+ add .cfi_signal_frame support (#175951, PR other/26208, BZ#300)
+
+* Tue Feb 14 2006 Jakub Jelinek <jakub@redhat.com> 2.16.91.0.6-1
+- update to 2.16.91.0.6
+ - fix ppc64 --gc-sections
+ - disassembler fixes for x86_64 cr/debug regs
+ - fix linker search order for DT_NEEDED libs
+
+* Mon Jan 02 2006 Jakub Jelinek <jakub@redhat.com> 2.16.91.0.5-1
+- update to 2.16.91.0.5
+- don't error about .toc1 references to discarded sectiosn on ppc64
+ (#175944)
+
+* Wed Dec 14 2005 Jakub Jelinek <jakub@redhat.com> 2.16.91.0.3-2
+- put .gnu.linkonce.d.rel.ro.* sections into relro region
+
+* Fri Dec 09 2005 Jesse Keating <jkeating@redhat.com>
+- rebuilt
+
+* Fri Nov 11 2005 Jakub Jelinek <jakub@redhat.com> 2.16.91.0.3-1
+- update to 2.16.91.0.3
+- add .weakref support (Alexandre Oliva, #115157, #165728)
+
+* Thu Aug 18 2005 Jakub Jelinek <jakub@redhat.com> 2.16.91.0.2-4
+- install-info also configure.info
+- update standards.texi from gnulib (#165530)
+
+* Tue Aug 16 2005 Jakub Jelinek <jakub@redhat.com> 2.16.91.0.2-3
+- update to 20050816 CVS
+- better fix for ld-cdtest
+- fix symbol version script parsing
+
+* Fri Jul 29 2005 Jakub Jelinek <jakub@redhat.com> 2.16.91.0.2-2
+- don't complain about relocs to discarded sections in ppc32
+ .got2 sections (Alan Modra, PR target/17828)
+
+* Fri Jul 22 2005 Jakub Jelinek <jakub@redhat.com> 2.16.91.0.2-1
+- update to 2.16.91.0.2
+
+* Thu Jul 21 2005 Jakub Jelinek <jakub@redhat.com> 2.16.91.0.1-3
+- fix buffer overflow in readelf ia64 unwind printing code
+- use vsnprintf rather than vsprintf in gas diagnostics (Tavis Ormandy)
+- fix ld-cdtest when CFLAGS contains -fexceptions
+
+* Wed Jul 20 2005 Jakub Jelinek <jakub@redhat.com> 2.16.91.0.1-2
+- update to 20050720 CVS
+
+* Mon Jul 11 2005 Jakub Jelinek <jakub@redhat.com> 2.16.91.0.1-1
+- update to 2.16.91.0.1 plus 20050708 CVS
+
+* Wed Jun 15 2005 Jakub Jelinek <jakub@redhat.com> 2.16.90.0.3-1
+- update to 2.16.90.0.3
+- update to 20050615 CVS
+ - ppc32 secure PLT support (Alan Modra)
+- further bfd/readelf robustification
+
+* Sat Jun 11 2005 Jakub Jelinek <jakub@redhat.com> 2.15.94.0.2.2-4
+- further bfd robustification (CAN-2005-1704, #158680)
+
+* Fri Jun 10 2005 Jakub Jelinek <jakub@redhat.com> 2.15.94.0.2.2-3
+- further objdump and readelf robustification (CAN-2005-1704, #158680)
+
+* Wed May 25 2005 Jakub Jelinek <jakub@redhat.com> 2.15.94.0.2.2-2
+- bfd and readelf robustification (CAN-2005-1704, #158680)
+
+* Tue Mar 29 2005 Jakub Jelinek <jakub@redhat.com> 2.15.94.0.2.2-1
+- update to 2.15.94.0.2.2
+- speed up walk_wild_section (Robert O'Callahan)
+
+* Mon Mar 7 2005 Jakub Jelinek <jakub@redhat.com> 2.15.94.0.2-4
+- rebuilt with GCC 4
+
+* Mon Feb 28 2005 Jakub Jelinek <jakub@redhat.com> 2.15.94.0.2-3
+- fix buffer overflows in readelf (#149506)
+- move c++filt to binutils from gcc-c++, conflict with gcc-c++ < 4.0 (#86333)
+
+* Thu Feb 10 2005 Jakub Jelinek <jakub@redhat.com> 2.15.94.0.2-1
+- update to 2.15.94.0.2
+- fix .note.GNU-stack/PT_GNU_STACK computation in linker on ppc64 (#147296)
+- fix stripping of binaries/libraries that have empty sections right before
+ .dynamic section (with the same starting address; #144038)
+- handle AS_NEEDED (...) in linker script INPUT/GROUP
+
+* Tue Dec 14 2004 Jakub Jelinek <jakub@redhat.com> 2.15.92.0.2-11
+- fix a longstanding -z relro bug
+
+* Mon Dec 13 2004 Jakub Jelinek <jakub@redhat.com> 2.15.92.0.2-10
+- avoid unnecessary gap with -z relro showing on i686 libc.so
+- ppc64 --emit-relocs fix (Alan Modra)
+- don't crash if STT_SECTION symbol has incorrect st_shndx (e.g. SHN_ABS,
+ as created by nasm; #142181)
+- don't try to make absptr LSDAs relative if they don't have relocations
+ against them (Alan Modra, #141162)
+
+* Wed Oct 27 2004 Jakub Jelinek <jakub@redhat.com> 2.15.92.0.2-5.EL4
+- fix ar xo (#104344)
+
+* Wed Oct 20 2004 Jakub Jelinek <jakub@redhat.com> 2.15.92.0.2-5
+- fix --just-symbols on ppc64 (Alan Modra, #135498)
+
+* Fri Oct 15 2004 Jakub Jelinek <jakub@redhat.com> 2.15.92.0.2-4
+- fix code detecting matching linkonce and single member comdat
+ group sections (#133078)
+
+* Mon Oct 11 2004 Jakub Jelinek <jakub@redhat.com> 2.15.92.0.2-3
+- revert Sep 09 change to make ppc L second argument e.g. for tlbie
+ non-optional
+- fix stripping of prelinked binaries and libraries (#133734)
+- allow strings(1) on 32-bit arches to be used again with > 2GB
+ files (#133555)
+
+* Mon Oct 4 2004 Jakub Jelinek <jakub@redhat.com> 2.15.92.0.2-2
+- update to 2.15.92.0.2
+- change ld's ld.so.conf parser to match ldconfig's (#129340)
+
+* Mon Sep 20 2004 Jakub Jelinek <jakub@redhat.com> 2.15.91.0.2-9
+- avoid almost 1MB (sparse) gaps in the middle of -z relro
+ libraries on x86-64 (Andreas Schwab)
+- fix -z relro to make sure end of PT_GNU_RELRO segment is always
+ COMMONPAGESIZE aligned
+
+* Wed Aug 18 2004 Jakub Jelinek <jakub@redhat.com> 2.15.91.0.2-8
+- fix linker segfaults on input objects with SHF_LINK_ORDER with
+ incorrect sh_link (H.J.Lu, Nick Clifton, #130198, BZ #290)
+
+* Wed Aug 18 2004 Jakub Jelinek <jakub@redhat.com> 2.15.91.0.2-7
+- resolve all undefined ppc64 .* syms to the function bodies through
+ .opd, not just those used in brach instructions (Alan Modra)
+
+* Tue Aug 17 2004 Jakub Jelinek <jakub@redhat.com> 2.15.91.0.2-6
+- fix ppc64 ld --dotsyms (Alan Modra)
+
+* Tue Aug 17 2004 Jakub Jelinek <jakub@redhat.com> 2.15.91.0.2-5
+- various ppc64 make check fixes when using non-dot-syms gcc (Alan Modra)
+- fix --gc-sections
+- on ia64 create empty .gnu.linkonce.ia64unw*.* sections for
+ .gnu.linkonce.t.* function doesn't need unwind info
+
+* Mon Aug 16 2004 Jakub Jelinek <jakub@redhat.com> 2.15.91.0.2-4
+- kill ppc64 dot symbols (Alan Modra)
+- objdump -d support for objects without dot symbols
+- support for overlapping ppc64 .opd entries
+
+* Mon Aug 9 2004 Jakub Jelinek <jakub@redhat.com> 2.15.91.0.2-3
+- fix a newly introduced linker crash on x86-64
+
+* Sun Aug 8 2004 Alan Cox <alan@redhat.com> 2.15.91.0.2-2
+- BuildRequire bison and macroise buildroot - from Steve Grubb
+
+* Fri Jul 30 2004 Jakub Jelinek <jakub@redhat.com> 2.15.91.0.2-1
+- update to 2.15.91.0.2
+- BuildRequire flex (#117763)
+
+* Wed May 19 2004 Jakub Jelinek <jakub@redhat.com> 2.15.90.0.3-7
+- use lib64 instead of lib directories on ia64 if %%{_lib} is
+ set to lib64 by rpm
+
+* Sat May 15 2004 Jakub Jelinek <jakub@redhat.com> 2.15.90.0.3-6
+- fix a bug introduced in the ++/-- rejection patch
+ from 2.15.90.0.3 (Alan Modra)
+
+* Tue May 4 2004 Jakub Jelinek <jakub@redhat.com> 2.15.90.0.3-5
+- fix s390{,x} .{,b,p2}align handling
+- ppc/ppc64 testsuite fix
+
+* Mon May 3 2004 Jakub Jelinek <jakub@redhat.com> 2.15.90.0.3-4
+- -z relro ppc/ppc64/ia64 fixes
+- change x86-64 .plt symbol st_size handling to match ia32
+- prettify objdump -d output
+
+* Tue Apr 20 2004 Jakub Jelinek <jakub@redhat.com> 2.15.90.0.3-3
+- several SPARC fixes
+
+* Sun Apr 18 2004 Jakub Jelinek <jakub@redhat.com> 2.15.90.0.3-2
+- yet another fix for .tbss handling
+
+* Fri Apr 16 2004 Jakub Jelinek <jakub@redhat.com> 2.15.90.0.3-1
+- update to 2.15.90.0.3
+
+* Fri Mar 26 2004 Jakub Jelinek <jakub@redhat.com> 2.15.90.0.1.1-2
+- update to 20040326 CVS
+ - fix ppc64 weak .opd symbol handling (Alan Modra, #119086)
+- fix .tbss handling bug introduced
+
+* Fri Mar 26 2004 Jakub Jelinek <jakub@redhat.com> 2.15.90.0.1.1-1
+- update to 2.15.90.0.1.1
+
+* Sat Feb 21 2004 Jakub Jelinek <jakub@redhat.com> 2.14.90.0.8-8
+- with -z now without --enable-new-dtags create DT_BIND_NOW
+ dynamic entry in addition to DT_FLAGS_1 with DF_1_NOW bit set
+
+* Fri Feb 20 2004 Jakub Jelinek <jakub@redhat.com> 2.14.90.0.8-7
+- fix -pie on ppc32
+
+* Fri Feb 20 2004 Jakub Jelinek <jakub@redhat.com> 2.14.90.0.8-6
+- clear .plt sh_entsize on sparc32
+- put whole .got into relro area with -z now -z relro
+
+* Fri Feb 13 2004 Elliot Lee <sopwith@redhat.com>
+- rebuilt
+
+* Thu Jan 22 2004 Jakub Jelinek <jakub@redhat.com> 2.14.90.0.8-4
+- fix -pie on IA64
+
+* Mon Jan 19 2004 Jakub Jelinek <jakub@redhat.com> 2.14.90.0.8-3
+- fix testcases on s390 and s390x
+
+* Fri Jan 16 2004 Jakub Jelinek <jakub@redhat.com> 2.14.90.0.8-2
+- fix testcases on AMD64
+- fix .got's sh_entsize on IA32/AMD64
+- set COMMONPAGESIZE on s390/s390x
+- set COMMONPAGESIZE on ppc32 (Alan Modra)
+
+* Fri Jan 16 2004 Jakub Jelinek <jakub@redhat.com> 2.14.90.0.8-1
+- update to 2.14.90.0.8
+
+* Tue Jan 13 2004 Jakub Jelinek <jakub@redhat.com> 2.14.90.0.7-4
+- fix -z relro on 64-bit arches
+
+* Mon Jan 12 2004 Jakub Jelinek <jakub@redhat.com> 2.14.90.0.7-3
+- fix some bugs in -z relro support
+
+* Fri Jan 9 2004 Jakub Jelinek <jakub@redhat.com> 2.14.90.0.7-2
+- -z relro support, reordering of RW sections
+
+* Fri Jan 9 2004 Jakub Jelinek <jakub@redhat.com> 2.14.90.0.7-1
+- update to 2.14.90.0.7
+
+* Mon Nov 24 2003 Jakub Jelinek <jakub@redhat.com> 2.14.90.0.6-4
+- fix assembly parsing of foo=(.-bar)/4 (Alan Modra)
+- fix IA-64 assembly parsing of (p7) hint @pause
+
+* Tue Sep 30 2003 Jakub Jelinek <jakub@redhat.com> 2.14.90.0.6-3
+- don't abort on some linker warnings/errors on IA-64
+
+* Sat Sep 20 2003 Jakub Jelinek <jakub@redhat.com> 2.14.90.0.6-2
+- fix up merge2.s to use .p2align instead of .align
+
+* Sat Sep 20 2003 Jakub Jelinek <jakub@redhat.com> 2.14.90.0.6-1
+- update to 2.14.90.0.6
+- speed up string merging (Lars Knoll, Michael Matz, Alan Modra)
+- speed up IA-64 local symbol handling during linking
+
+* Fri Sep 5 2003 Jakub Jelinek <jakub@redhat.com> 2.14.90.0.5-7
+- avoid ld -s segfaults introduced in 2.14.90.0.5-5 (Dmitry V. Levin,
+ #103180)
+
+* Fri Aug 29 2003 Jakub Jelinek <jakub@redhat.com> 2.14.90.0.5-6
+- build old demangler into libiberty.a (#102268)
+- SPARC .cfi* support
+
+* Tue Aug 5 2003 Jakub Jelinek <jakub@redhat.com> 2.14.90.0.5-5
+- fix orphan section placement
+
+* Tue Jul 29 2003 Jakub Jelinek <jakub@redhat.com> 2.14.90.0.5-4
+- fix ppc64 elfvsb linker tests
+- some more 64-bit cleanliness fixes, give ppc64 fdesc symbols
+ type and size (Alan Modra)
+
+* Tue Jul 29 2003 Jakub Jelinek <jakub@redhat.com> 2.14.90.0.5-3
+- fix 64-bit unclean code in ppc-opc.c
+
+* Mon Jul 28 2003 Jakub Jelinek <jakub@redhat.com> 2.14.90.0.5-2
+- fix 64-bit unclean code in tc-ppc.c
+
+* Mon Jul 28 2003 Jakub Jelinek <jakub@redhat.com> 2.14.90.0.5-1
+- update to 2.14.90.0.5
+- fix ld -r on ppc64 (Alan Modra)
+
+* Fri Jul 18 2003 Jakub Jelinek <jakub@redhat.com> 2.14.90.0.4-23
+- rebuilt
+
+* Thu Jul 17 2003 Jakub Jelinek <jakub@redhat.com> 2.14.90.0.4-22
+- fix elfNN_ia64_dynamic_symbol_p (Richard Henderson, #86661)
+- don't access memory beyond what was allocated in readelf
+ (Richard Henderson)
+
+* Thu Jul 10 2003 Jakub Jelinek <jakub@redhat.com> 2.14.90.0.4-21
+- add .cfi_* support on ppc{,64} and s390{,x}
+
+* Tue Jul 8 2003 Jakub Jelinek <jakub@redhat.com> 2.14.90.0.4-20
+- remove lib{bfd,opcodes}.la (#98190)
+
+* Mon Jul 7 2003 Jakub Jelinek <jakub@redhat.com> 2.14.90.0.4-19
+- fix -pie support on amd64, s390, s390x and ppc64
+- issue relocation overflow errors for s390/s390x -fpic code when
+ accessing .got slots above 4096 bytes from .got start
+
+* Thu Jul 3 2003 Jakub Jelinek <jakub@redhat.com> 2.14.90.0.4-18
+- rebuilt
+
+* Thu Jul 3 2003 Jakub Jelinek <jakub@redhat.com> 2.14.90.0.4-17
+- fix ia64 -pie support
+- require no undefined non-weak symbols in PIEs like required for normal
+ binaries
+
+* Wed Jul 2 2003 Jakub Jelinek <jakub@redhat.com> 2.14.90.0.4-16
+- fix readelf -d on IA-64
+- build libiberty.a with -fPIC, so that it can be lined into shared
+ libraries
+
+* Wed Jun 25 2003 Jakub Jelinek <jakub@redhat.com> 2.14.90.0.4-15
+- rebuilt
+
+* Wed Jun 25 2003 Jakub Jelinek <jakub@redhat.com> 2.14.90.0.4-14
+- added support for Intel Prescott instructions
+- fix hint@pause for ia64
+- add workaround for LTP sillyness (#97934)
+
+* Wed Jun 18 2003 Jakub Jelinek <jakub@redhat.com> 2.14.90.0.4-13
+- update CFI stuff to 2003-06-18
+- make sure .eh_frame is aligned to 8 bytes on 64-bit arches,
+ remove padding within one .eh_frame section
+
+* Tue Jun 17 2003 Jakub Jelinek <jakub@redhat.com> 2.14.90.0.4-12
+- rebuilt
+
+* Tue Jun 17 2003 Jakub Jelinek <jakub@redhat.com> 2.14.90.0.4-11
+- one more fix for the same patch
+
+* Tue Jun 17 2003 Jakub Jelinek <jakub@redhat.com> 2.14.90.0.4-10
+- fix previous patch
+
+* Mon Jun 16 2003 Jakub Jelinek <jakub@redhat.com> 2.14.90.0.4-9
+- ensure R_PPC64_{RELATIVE,ADDR64} have *r_offset == r_addend
+ and the other relocs have *r_offset == 0
+
+* Tue Jun 10 2003 Jakub Jelinek <jakub@redhat.com> 2.14.90.0.4-8
+- remove some unnecessary provides in ppc64 linker script
+ which were causing e.g. empty .ctors/.dtors section creation
+
+* Fri Jun 6 2003 Jakub Jelinek <jakub@redhat.com> 2.14.90.0.4-7
+- some CFI updates/fixes
+- don't create dynamic relocations against symbols defined in PIE
+ exported from its .dynsym
+
+* Wed Jun 4 2003 Jakub Jelinek <jakub@redhat.com> 2.14.90.0.4-6
+- update gas to 20030604
+- PT_GNU_STACK support
+
+* Mon Jun 2 2003 Jakub Jelinek <jakub@redhat.com> 2.14.90.0.4-5
+- buildrequire gettext (#91838)
+
+* Sat May 31 2003 Jakub Jelinek <jakub@redhat.com> 2.14.90.0.4-4
+- fix shared libraries with >= 8192 .plt slots on ppc32
+
+* Thu May 29 2003 Jakub Jelinek <jakub@redhat.com> 2.14.90.0.4-3
+- rebuilt
+
+* Thu May 29 2003 Jakub Jelinek <jakub@redhat.com> 2.14.90.0.4-2
+- rename ld --dynamic option to --pic-executable or --pie
+- fix ld --help output
+- document --pie/--pic-executable in ld.info and ld.1
+
+* Wed May 28 2003 Jakub Jelinek <jakub@redhat.com> 2.14.90.0.4-1
+- update to 2.14.90.0.4-1
+- gas CFI updates (Richard Henderson)
+- dynamic executables (Ulrich Drepper)
+
+* Tue May 20 2003 Jakub Jelinek <jakub@redhat.com> 2.14.90.0.2-2
+- fix ELF visibility handling
+- tidy plt entries on IA-32, ppc and ppc64
+
+* Mon May 19 2003 Jakub Jelinek <jakub@redhat.com> 2.14.90.0.2-1
+- update to 2.14.90.0.2-1
+
+* Tue May 13 2003 Jakub Jelinek <jakub@redhat.com> 2.13.90.0.20-8
+- fix bfd_elf_hash on 64-bit arches (Andrew Haley)
+
+* Wed Apr 30 2003 Jakub Jelinek <jakub@redhat.com> 2.13.90.0.20-7
+- rebuilt
+
+* Mon Apr 14 2003 Jakub Jelinek <jakub@redhat.com> 2.13.90.0.20-6
+- optimize DW_CFA_advance_loc4 in gas even if there is 'z' augmentation
+ with size 0 in FDE
+
+* Fri Apr 11 2003 Jakub Jelinek <jakub@redhat.com> 2.13.90.0.20-5
+- fix SPARC build
+
+* Thu Apr 3 2003 Jakub Jelinek <jakub@redhat.com> 2.13.90.0.20-4
+- fix ppc32 plt reference counting
+- don't include %%{_prefix}/%%{_lib}/debug in the non-debuginfo package
+ (#87729)
+
+* Mon Mar 31 2003 Jakub Jelinek <jakub@redhat.com> 2.13.90.0.20-3
+- make elf64ppc target native extra on ppc and elf32ppc native extra
+ on ppc64.
+
+* Fri Mar 28 2003 Jakub Jelinek <jakub@redhat.com> 2.13.90.0.20-2
+- fix TLS on IA-64 with ld relaxation
+
+* Sat Mar 22 2003 Jakub Jelinek <jakub@redhat.com> 2.13.90.0.20-1
+- update to 2.13.90.0.20
+
+* Mon Feb 24 2003 Jakub Jelinek <jakub@redhat.com> 2.13.90.0.18-9
+- rebuilt
+
+* Mon Feb 24 2003 Jakub Jelinek <jakub@redhat.com> 2.13.90.0.18-8
+- don't strip binaries in %%install, so that there is non-empty
+ debuginfo
+
+* Mon Feb 24 2003 Jakub Jelinek <jakub@redhat.com> 2.13.90.0.18-7
+- don't optimize .eh_frame during ld -r
+
+* Thu Feb 13 2003 Jakub Jelinek <jakub@redhat.com> 2.13.90.0.18-6
+- don't clear elf_link_hash_flags in the .symver patch
+- only use TC_FORCE_RELOCATION in s390's TC_FORCE_RELOCATION_SUB_SAME
+ (Alan Modra)
+
+* Mon Feb 10 2003 Jakub Jelinek <jakub@redhat.com> 2.13.90.0.18-5
+- fix the previous .symver change
+- remove libbfd.so and libopcodes.so symlinks, so that other packages
+ link statically, not dynamically against libbfd and libopcodes
+ whose ABI is everything but stable
+
+* Mon Feb 10 2003 Jakub Jelinek <jakub@redhat.com> 2.13.90.0.18-4
+- do .symver x, x@FOO handling earlier
+- support .file and .loc on s390*
+
+* Mon Feb 10 2003 Jakub Jelinek <jakub@redhat.com> 2.13.90.0.18-3
+- handle .symver x, x@FOO in ld such that relocs against x become
+ dynamic relocations against x@FOO (#83325)
+- two PPC64 TLS patches (Alan Modra)
+
+* Sun Feb 09 2003 Jakub Jelinek <jakub@redhat.com> 2.13.90.0.18-2
+- fix SEARCH_DIR on x86_64/s390x
+- fix Alpha --relax
+- create DT_RELA{,SZ,ENT} on s390 even if there is just .rela.plt
+ and no .rela.dyn section
+- support IA-32 on IA-64 (#83752)
+- .eh_frame_hdr fix (Andreas Schwab)
+
+* Thu Feb 06 2003 Jakub Jelinek <jakub@redhat.com> 2.13.90.0.18-1
+- update to 2.13.90.0.18 + 20030121->20030206 CVS diff
+
+* Tue Feb 04 2003 Jakub Jelinek <jakub@redhat.com> 2.13.90.0.16-8
+- alpha TLS fixes
+- use .debug_line directory table to make the section tiny bit smaller
+- libtool fix from Jens Petersen
+
+* Sun Feb 02 2003 Jakub Jelinek <jakub@redhat.com> 2.13.90.0.16-7
+- sparc32 TLS
+
+* Fri Jan 24 2003 Jakub Jelinek <jakub@redhat.com> 2.13.90.0.16-6
+- s390{,x} TLS and two other mainframe patches
+
+* Fri Jan 17 2003 Jakub Jelinek <jakub@redhat.com> 2.13.90.0.16-5
+- fix IA-64 TLS IE in shared libs
+- .{preinit,init,fini}_array compat hack from Alexandre Oliva
+
+* Thu Jan 16 2003 Jakub Jelinek <jakub@redhat.com> 2.13.90.0.16-4
+- IA-64 TLS fixes
+- fix .plt sh_entsize on Alpha
+- build with %%_smp_mflags
+
+* Sat Nov 30 2002 Jakub Jelinek <jakub@redhat.com> 2.13.90.0.16-3
+- fix strip on TLS binaries and libraries
+
+* Fri Nov 29 2002 Jakub Jelinek <jakub@redhat.com> 2.13.90.0.16-2
+- fix IA-64 ld bootstrap
+
+* Thu Nov 28 2002 Jakub Jelinek <jakub@redhat.com> 2.13.90.0.16-1
+- update to 2.13.90.0.16
+- STT_TLS SHN_UNDEF fix
+
+* Wed Nov 27 2002 Jakub Jelinek <jakub@redhat.com> 2.13.90.0.10-4
+- pad .rodata.cstNN sections at the end if they aren't sized to multiple
+ of sh_entsize
+- temporary patch to make .eh_frame and .gcc_except_table sections
+ readonly if possible (should be removed when AUTO_PLACE is implemented)
+- fix .PPC.EMB.apuinfo section flags
+
+* Wed Oct 23 2002 Jakub Jelinek <jakub@redhat.com> 2.13.90.0.10-3
+- fix names and content of alpha non-alloced .rela.* sections (#76583)
+- delete unpackaged files from the buildroot
+
+* Tue Oct 15 2002 Jakub Jelinek <jakub@redhat.com> 2.13.90.0.10-2
+- enable s390x resp. s390 emulation in linker too
+
+* Mon Oct 14 2002 Jakub Jelinek <jakub@redhat.com> 2.13.90.0.10-1
+- update to 2.13.90.0.10
+- add a bi-arch patch for sparc/s390/x86_64
+- add --enable-64-bit-bfd on sparc, s390 and ppc
+
+* Thu Oct 10 2002 Jakub Jelinek <jakub@redhat.com> 2.13.90.0.4-3
+- fix combreloc testcase
+
+* Thu Oct 10 2002 Jakub Jelinek <jakub@redhat.com> 2.13.90.0.4-2
+- fix orphan .rel and .rela section placement with -z combreloc (Alan Modra)
+- skip incompatible linker scripts when searching for libraries
+
+* Tue Oct 1 2002 Jakub Jelinek <jakub@redhat.com> 2.13.90.0.4-1
+- update to 2.13.90.0.4
+- x86-64 TLS support
+- some IA-32 TLS fixes
+- some backported patches from trunk
+- include opcodes, ld, gas and bfd l10n too
+
+* Thu Sep 19 2002 Jakub Jelinek <jakub@redhat.com> 2.13.90.0.2-3
+- allow addends for IA-32 TLS @tpoff, @ntpoff and @dtpoff
+- clear memory at *r_offset of dynamic relocs on PPC
+- avoid ld crash if accessing non-local symbols through LE relocs
+- new IA-32 TLS relocs, bugfixes and testcases
+- use brl insn on IA-64 (Richard Henderson)
+- fix R_IA64_PCREL21{M,F} handling (Richard Henderson)
+- build in separate builddir, so that gasp tests don't fail
+- include localization
+
+* Thu Aug 8 2002 Jakub Jelinek <jakub@redhat.com> 2.13.90.0.2-2
+- fix R_386_TPOFF32 addends (#70824)
+
+* Sat Aug 3 2002 Jakub Jelinek <jakub@redhat.com> 2.13.90.0.2-1
+- update to 2.13.90.0.2
+ - fix ld TLS assertion failure (#70084)
+ - fix readelf --debug-dump= handling to match man page and --help
+ (#68997)
+- fix _GLOBAL_OFFSET_TABLE gas handling (#70241)
+
+* Wed Jul 24 2002 Jakub Jelinek <jakub@redhat.com> 2.12.90.0.15-1
+- update to 2.12.90.0.15
+- TLS .tbss fix
+- don't use rpm %%configure macro, it is broken too often (#69366)
+
+* Thu May 30 2002 Jakub Jelinek <jakub@redhat.com> 2.12.90.0.9-1
+- update to 2.12.90.0.9
+ - TLS support
+- remove gasp.info from %%post/%%preun (#65400)
+
+* Mon Apr 29 2002 Jakub Jelinek <jakub@redhat.com> 2.12.90.0.7-1
+- update to 2.12.90.0.7
+- run make check
+
+* Mon Apr 29 2002 Jakub Jelinek <jakub@redhat.com> 2.11.93.0.2-12
+- fix .hidden handling on SPARC (Richard Henderson)
+- don't crash when linking -shared non-pic code with SHF_MERGE
+- fix .eh_frame_hdr for DW_EH_PE_aligned
+- correctly adjust DW_EH_PE_pcrel encoded personalities in CIEs
+
+* Fri Apr 5 2002 Jakub Jelinek <jakub@redhat.com> 2.11.93.0.2-11
+- don't emit dynamic R_SPARC_DISP* relocs against STV_HIDDEN symbols
+ into shared libraries
+
+* Thu Mar 21 2002 Jakub Jelinek <jakub@redhat.com> 2.11.93.0.2-10
+- don't merge IA-64 unwind info sections together during ld -r
+
+* Mon Mar 11 2002 Jakub Jelinek <jakub@redhat.com> 2.11.93.0.2-9
+- fix DATA_SEGMENT_ALIGN on ia64/alpha/sparc/sparc64
+
+* Fri Mar 8 2002 Jakub Jelinek <jakub@redhat.com> 2.11.93.0.2-8
+- don't crash on SHN_UNDEF local dynsyms (Andrew MacLeod)
+
+* Thu Mar 7 2002 Jakub Jelinek <jakub@redhat.com> 2.11.93.0.2-7
+- fix bfd configury bug (Alan Modra)
+
+* Tue Mar 5 2002 Jakub Jelinek <jakub@redhat.com> 2.11.93.0.2-6
+- don't copy visibility when equating symbols
+- fix alpha .text/.data with .previous directive bug
+
+* Tue Mar 5 2002 Jakub Jelinek <jakub@redhat.com> 2.11.93.0.2-5
+- fix SHF_MERGE crash with --gc-sections (#60369)
+- C++ symbol versioning patch
+
+* Fri Feb 22 2002 Jakub Jelinek <jakub@redhat.com> 2.11.93.0.2-4
+- add DW_EH_PE_absptr -> DW_EH_PE_pcrel optimization for shared libs,
+ if DW_EH_PE_absptr cannot be converted that way, don't build the
+ .eh_frame_hdr search table
+
+* Fri Feb 15 2002 Jakub Jelinek <jakub@redhat.com> 2.11.93.0.2-3
+- fix ld -N broken by last patch
+
+* Tue Feb 12 2002 Jakub Jelinek <jakub@redhat.com> 2.11.93.0.2-2
+- trade one saved runtime page for data segment (=almost always not shared)
+ for up to one page of disk space where possible
+
+* Fri Feb 8 2002 Jakub Jelinek <jakub@redhat.com> 2.11.93.0.2-1
+- update to 2.11.93.0.2
+- use %%{ix86} instead of i386 for -z combreloc default (#59086)
+
+* Thu Jan 31 2002 Jakub Jelinek <jakub@redhat.com> 2.11.92.0.12-10
+- don't create SHN_UNDEF STB_WEAK symbols unless there are any relocations
+ against them
+
+* Wed Jan 30 2002 Bill Nottingham <notting@redhat.com> 2.11.92.0.12-9.1
+- rebuild (fix ia64 miscompilation)
+
+* Wed Jan 09 2002 Tim Powers <timp@redhat.com>
+- automated rebuild
+
+* Fri Dec 28 2001 Jakub Jelinek <jakub@redhat.com> 2.11.92.0.12-8
+- two further .eh_frame patch fixes
+
+* Wed Dec 19 2001 Jakub Jelinek <jakub@redhat.com> 2.11.92.0.12-7
+- as ld is currently not able to shrink input sections to zero size
+ during discard_info, build a fake minimal CIE in that case
+- update elf-strtab patch to what was commited
+
+* Mon Dec 17 2001 Jakub Jelinek <jakub@redhat.com> 2.11.92.0.12-6
+- one more .eh_frame patch fix
+- fix alpha .eh_frame handling
+- optimize elf-strtab finalize
+
+* Sat Dec 15 2001 Jakub Jelinek <jakub@redhat.com> 2.11.92.0.12-5
+- yet another fix for the .eh_frame patch
+
+* Fri Dec 14 2001 Jakub Jelinek <jakub@redhat.com> 2.11.92.0.12-4
+- Alan Modra's patch to avoid crash if there is no dynobj
+
+* Thu Dec 13 2001 Jakub Jelinek <jakub@redhat.com> 2.11.92.0.12-3
+- H.J.'s patch to avoid crash if input files are not ELF
+- don't crash if a SHF_MERGE for some reason could not be merged
+- fix objcopy/strip to preserve SHF_MERGE sh_entsize
+- optimize .eh_frame sections, add PT_GNU_EH_FRAME support
+- support anonymous version tags in version script
+
+* Tue Nov 27 2001 Jakub Jelinek <jakub@redhat.com> 2.11.92.0.12-2
+- fix IA-64 SHF_MERGE handling
+
+* Tue Nov 27 2001 Jakub Jelinek <jakub@redhat.com> 2.11.92.0.12-1
+- update to 2.11.92.0.12
+ - optimize .dynstr and .shstrtab sections (#55524)
+ - fix ld.1 glitch (#55459)
+- turn relocs against SHF_MERGE local symbols with zero addend
+ into STT_SECTION + addend
+- remove man pages for programs not included (nlmconv, windres, dlltool;
+ #55456, #55461)
+- add BuildRequires for texinfo
+
+* Thu Oct 25 2001 Jakub Jelinek <jakub@redhat.com> 2.11.92.0.7-2
+- duh, fix strings on bfd objects (#55084)
+
+* Sat Oct 20 2001 Jakub Jelinek <jakub@redhat.com> 2.11.92.0.7-1
+- update to 2.11.92.0.7
+- remove .rel{,a}.dyn from output if it is empty
+
+* Thu Oct 11 2001 Jakub Jelinek <jakub@redhat.com> 2.11.92.0.5-2
+- fix strings patch
+- use getc_unlocked in strings to speed it up by 50% on large files
+
+* Wed Oct 10 2001 Jakub Jelinek <jakub@redhat.com> 2.11.92.0.5-1
+- update to 2.11.92.0.5
+ - binutils localization (#45148)
+ - fix typo in REPORT_BUGS_TO (#54325)
+- support files bigger than 2GB in strings (#54406)
+
+* Wed Sep 26 2001 Jakub Jelinek <jakub@redhat.com> 2.11.90.0.8-12
+- on IA-64, don't mix R_IA64_IPLTLSB relocs with non-PLT relocs in
+ .rela.dyn section.
+
+* Tue Sep 25 2001 Jakub Jelinek <jakub@redhat.com> 2.11.90.0.8-11
+- add iplt support for IA-64 (Richard Henderson)
+- switch to new section flags for SHF_MERGE and SHF_STRINGS, put
+ in compatibility code
+- "s" section flag for small data sections on IA-64 and Alpha
+ (Richard Henderson)
+- fix sparc64 .plt[32768+] handling
+- don't emit .rela.stab on sparc
+
+* Mon Sep 10 2001 Jakub Jelinek <jakub@redhat.com> 2.11.90.0.8-10
+- fix SHF_MERGE on Sparc
+
+* Fri Aug 31 2001 Jakub Jelinek <jakub@redhat.com> 2.11.90.0.8-9
+- on Alpha, copy *r_offset to R_ALPHA_RELATIVE's r_addend
+
+* Thu Aug 30 2001 Jakub Jelinek <jakub@redhat.com> 2.11.90.0.8-8
+- on IA-64, put crtend{,S}.o's .IA_64.unwind section last in
+ .IA_64.unwind output section (for compatibility with 7.1 eh)
+
+* Fri Aug 24 2001 Jakub Jelinek <jakub@redhat.com> 2.11.90.0.8-7
+- put RELATIVE relocs first, not last
+- enable -z combreloc by default on IA-{32,64}, Alpha, Sparc*
+
+* Thu Aug 23 2001 Jakub Jelinek <jakub@redhat.com> 2.11.90.0.8-6
+- support for -z combreloc
+- remove .dynamic patch, -z combreloc patch does this better
+- set STT_FUNC default symbol sizes in .endp directive on IA-64
+
+* Mon Jul 16 2001 Jakub Jelinek <jakub@redhat.com> 2.11.90.0.8-5
+- fix last patch (H.J.Lu)
+
+* Fri Jul 13 2001 Jakub Jelinek <jakub@redhat.com> 2.11.90.0.8-4
+- fix placing of orphan sections
+
+* Sat Jun 23 2001 Jakub Jelinek <jakub@redhat.com>
+- fix SHF_MERGE support on Alpha
+
+* Fri Jun 8 2001 Jakub Jelinek <jakub@redhat.com>
+- 2.11.90.0.8
+ - some SHF_MERGE suport fixes
+- don't build with tooldir /usrusr instead of /usr (#40937)
+- reserve few .dynamic entries for prelinking
+
+* Mon Apr 16 2001 Jakub Jelinek <jakub@redhat.com>
+- 2.11.90.0.5
+ - SHF_MERGE support
+
+* Tue Apr 3 2001 Jakub Jelinek <jakub@redhat.com>
+- 2.11.90.0.4
+ - fix uleb128 support, so that CVS gcc bootstraps
+ - some ia64 fixes
+
+* Mon Mar 19 2001 Jakub Jelinek <jakub@redhat.com>
+- add -Bgroup support from Ulrich Drepper
+
+* Fri Mar 9 2001 Jakub Jelinek <jakub@redhat.com>
+- hack - add elf_i386_glibc21 emulation
+
+* Fri Feb 16 2001 Jakub Jelinek <jakub@redhat.com>
+- 2.10.91.0.2
+
+* Fri Feb 9 2001 Jakub Jelinek <jakub@redhat.com>
+- 2.10.1.0.7
+- remove ExcludeArch ia64
+- back out the -oformat, -omagic and -output change for now
+
+* Fri Dec 15 2000 Jakub Jelinek <jakub@redhat.com>
+- Prereq /sbin/install-info
+
+* Tue Nov 21 2000 Jakub Jelinek <jakub@redhat.com>
+- 2.10.1.0.2
+
+* Tue Nov 21 2000 Jakub Jelinek <jakub@redhat.com>
+- add one more alpha patch
+
+* Wed Nov 15 2000 Jakub Jelinek <jakub@redhat.com>
+- fix alpha visibility as problem
+- add support for Ultra-III
+
+* Fri Sep 15 2000 Jakub Jelinek <jakub@redhat.com>
+- and one more alpha patch
+
+* Fri Sep 15 2000 Jakub Jelinek <jakub@redhat.com>
+- two sparc patches
+
+* Mon Jul 24 2000 Jakub Jelinek <jakub@redhat.com>
+- 2.10.0.18
+
+* Mon Jul 10 2000 Jakub Jelinek <jakub@redhat.com>
+- 2.10.0.12
+
+* Mon Jun 26 2000 Jakub Jelinek <jakub@redhat.com>
+- 2.10.0.9
+
+* Thu Jun 15 2000 Jakub Jelinek <jakub@redhat.com>
+- fix ld -r
+
+* Mon Jun 5 2000 Jakub Jelinek <jakub@redhat.com>
+- 2.9.5.0.46
+- use _mandir/_infodir/_lib
+
+* Mon May 8 2000 Bernhard Rosenkraenzer <bero@redhat.com>
+- 2.9.5.0.41
+
+* Wed Apr 12 2000 Bernhard Rosenkraenzer <bero@redhat.com>
+- 2.9.5.0.34
+
+* Wed Mar 22 2000 Bernhard Rosenkraenzer <bero@redhat.com>
+- 2.9.5.0.31
+
+* Fri Feb 04 2000 Cristian Gafton <gafton@redhat.com>
+- man pages are compressed
+- apply kingdon's patch from #5031
+
+* Wed Jan 19 2000 Jeff Johnson <jbj@redhat.com>
+- Permit package to be built with a prefix other than /usr.
+
+* Thu Jan 13 2000 Cristian Gafton <gafton@redhat.com>
+- add pacth from hjl to fix the versioning problems in ld
+
+* Tue Jan 11 2000 Bernhard Rosenkraenzer <bero@redhat.com>
+- Add sparc patches from Jakub Jelinek <jakub@redhat.com>
+- Add URL:
+
+* Tue Dec 14 1999 Bernhard Rosenkraenzer <bero@redhat.com>
+- 2.9.5.0.22
+
+* Wed Nov 24 1999 Bernhard Rosenkraenzer <bero@redhat.com>
+- 2.9.5.0.19
+
+* Sun Oct 24 1999 Bernhard Rosenkraenzer <bero@redhat.com>
+- 2.9.5.0.16
+
+* Mon Sep 06 1999 Jakub Jelinek <jj@ultra.linux.cz>
+- make shared non-pic libraries work on sparc with glibc 2.1.
+
+* Fri Aug 27 1999 Jim Kingdon
+- No source/spec changes, just rebuilding with egcs-1.1.2-18 because
+ the older egcs was miscompling gprof.
+
+* Mon Apr 26 1999 Cristian Gafton <gafton@redhat.com>
+- back out very *stupid* sparc patch done by HJLu. People, keep out of
+ things you don't understand.
+- add alpha relax patch from rth
+
+* Mon Apr 05 1999 Cristian Gafton <gafton@redhat.com>
+- version 2.9.1.0.23
+- patch to make texinfo documentation compile
+- auto rebuild in the new build environment (release 2)
+
+* Tue Feb 23 1999 Cristian Gafton <gafton@redhat.com>
+- updated to 2.9.1.0.21
+- merged with UltraPenguin
+
+* Mon Jan 04 1999 Cristian Gafton <gafton@redhat.com>
+- added ARM patch from philb
+- version 2.9.1.0.19a
+- added a patch to allow arm* arch to be identified as an ARM
+
+* Thu Oct 01 1998 Cristian Gafton <gafton@redhat.com>
+- updated to 2.9.1.0.14.
+
+* Sat Sep 19 1998 Jeff Johnson <jbj@redhat.com>
+- updated to 2.9.1.0.13.
+
+* Wed Sep 09 1998 Cristian Gafton <gafton@redhat.com>
+- updated to 2.9.1.0.12
+
+* Thu Jul 2 1998 Jeff Johnson <jbj@redhat.com>
+- updated to 2.9.1.0.7.
+
+* Wed Jun 03 1998 Jeff Johnson <jbj@redhat.com>
+- updated to 2.9.1.0.6.
+
+* Tue Jun 02 1998 Erik Troan <ewt@redhat.com>
+- added patch from rth to get right offsets for sections in relocateable
+ objects on sparc32
+
+* Thu May 07 1998 Prospector System <bugs@redhat.com>
+- translations modified for de, fr, tr
+
+* Tue May 05 1998 Cristian Gafton <gafton@redhat.com>
+- version 2.9.1.0.4 is out; even more, it is public !
+
+* Tue May 05 1998 Jeff Johnson <jbj@redhat.com>
+- updated to 2.9.1.0.3.
+
+* Mon Apr 20 1998 Cristian Gafton <gafton@redhat.com>
+- updated to 2.9.0.3
+
+* Tue Apr 14 1998 Cristian Gafton <gafton@redhat.com>
+- upgraded to 2.9.0.2
+
+* Sun Apr 05 1998 Cristian Gafton <gafton@redhat.com>
+- updated to 2.8.1.0.29 (HJ warned me that this thing is a moving target...
+ :-)
+- "fixed" the damn make install command so that all tools get installed
+
+* Thu Apr 02 1998 Cristian Gafton <gafton@redhat.com>
+- upgraded again to 2.8.1.0.28 (at least on alpha now egcs will compile)
+- added info packages handling
+
+* Tue Mar 10 1998 Cristian Gafton <gafton@redhat.com>
+- upgraded to 2.8.1.0.23
+
+* Mon Mar 02 1998 Cristian Gafton <gafton@redhat.com>
+- updated to 2.8.1.0.15 (required to compile the newer glibc)
+- all patches are obsoleted now
+
+* Wed Oct 22 1997 Erik Troan <ewt@redhat.com>
+- added 2.8.1.0.1 patch from hj
+- added patch for alpha palcode form rth