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From d7dbef3c3149dfd404f5dc68f9337e1f9b5d3e8c Mon Sep 17 00:00:00 2001
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From: Mark Salter <msalter@redhat.com>
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Date: Sat, 14 Jun 2014 00:34:58 -0400
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Subject: [PATCH] gas: Backport support for full range of aarch64 sysregs
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gas/
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Backport from mainline:
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2013-02-27 Yufeng Zhang <yufeng.zhang@arm.com>
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* config/tc-aarch64.c (parse_sys_reg): Allow the full range of CRn
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for system registers.
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gas/testsuite/
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Backport from mainline:
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2013-02-27 Yufeng Zhang <yufeng.zhang@arm.com>
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* gas/aarch64/illegal.l: Delete the error message for
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msr S3_1_C13_C15_1,x7.
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* gas/aarch64/sysreg.s: Add new tests.
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* gas/aarch64/sysreg.d: Update.
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---
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gas/ChangeLog | 8 ++++++++
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gas/config/tc-aarch64.c | 10 +++++++---
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gas/testsuite/ChangeLog | 10 ++++++++++
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gas/testsuite/gas/aarch64/illegal.l | 1 -
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gas/testsuite/gas/aarch64/sysreg.d | 3 +++
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gas/testsuite/gas/aarch64/sysreg.s | 4 ++++
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6 files changed, 32 insertions(+), 4 deletions(-)
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diff --git a/gas/ChangeLog b/gas/ChangeLog
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index 0014922..e03e191 100644
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--- a/gas/ChangeLog
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+++ b/gas/ChangeLog
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@@ -1,3 +1,11 @@
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+2013-05-13 Yufeng Zhang <yufeng.zhang@arm.com>
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+
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+ Backport from mainline:
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+
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+ 2013-02-27 Yufeng Zhang <yufeng.zhang@arm.com>
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+ * config/tc-aarch64.c (parse_sys_reg): Allow the full range of CRn
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+ for system registers.
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+
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2013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com>
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* config/rl78-parse.y: Fix encoding of DIVWU insn.
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diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
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index 620ae8a..1e88891 100644
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--- a/gas/config/tc-aarch64.c
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+++ b/gas/config/tc-aarch64.c
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@@ -3288,10 +3288,14 @@ parse_sys_reg (char **str, struct hash_control *sys_regs, int imple_defined_p)
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unsigned int op0, op1, cn, cm, op2;
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if (sscanf (buf, "s%u_%u_c%u_c%u_%u", &op0, &op1, &cn, &cm, &op2) != 5)
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return PARSE_FAIL;
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- /* Register access is encoded as follows:
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+ /* The architecture specifies the encoding space for implementation
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+ defined registers as:
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op0 op1 CRn CRm op2
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- 11 xxx 1x11 xxxx xxx. */
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- if (op0 != 3 || op1 > 7 || (cn | 0x4) != 0xf || cm > 15 || op2 > 7)
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+ 11 xxx 1x11 xxxx xxx
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+ For convenience GAS accepts a wider encoding space, as follows:
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+ op0 op1 CRn CRm op2
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+ 11 xxx xxxx xxxx xxx */
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+ if (op0 != 3 || op1 > 7 || cn > 15 || cm > 15 || op2 > 7)
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return PARSE_FAIL;
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value = (op0 << 14) | (op1 << 11) | (cn << 7) | (cm << 3) | op2;
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}
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diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
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index 4508042..48574c4 100644
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--- a/gas/testsuite/ChangeLog
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+++ b/gas/testsuite/ChangeLog
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@@ -1,3 +1,13 @@
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+2013-05-13 Yufeng Zhang <yufeng.zhang@arm.com>
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+
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+ Backport from mainline:
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+
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+ 2013-02-27 Yufeng Zhang <yufeng.zhang@arm.com>
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+ * gas/aarch64/illegal.l: Delete the error message for
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+ msr S3_1_C13_C15_1,x7.
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+ * gas/aarch64/sysreg.s: Add new tests.
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+ * gas/aarch64/sysreg.d: Update.
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+
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2013-02-19 H.J. Lu <hongjiu.lu@intel.com>
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PR gas/15159
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diff --git a/gas/testsuite/gas/aarch64/illegal.l b/gas/testsuite/gas/aarch64/illegal.l
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index 6905866..5bc9c3c 100644
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--- a/gas/testsuite/gas/aarch64/illegal.l
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+++ b/gas/testsuite/gas/aarch64/illegal.l
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@@ -520,7 +520,6 @@
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[^:]*:496: Error: .*`str x1,page_table_count'
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[^:]*:498: Error: .*`prfm PLDL3KEEP,\[x9,x15,sxtx#2\]'
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[^:]*:500: Error: .*`mrs x5,S1_0_C13_C8_0'
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-[^:]*:501: Error: .*`msr S3_1_C13_C15_1,x7'
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[^:]*:502: Error: .*`msr S3_1_C11_C15_-1,x7'
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[^:]*:503: Error: .*`msr S3_1_11_15_1,x7'
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[^:]*:506: Error: .*`movi w1,#15'
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diff --git a/gas/testsuite/gas/aarch64/sysreg.d b/gas/testsuite/gas/aarch64/sysreg.d
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index b83b270..c7cf00e 100644
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--- a/gas/testsuite/gas/aarch64/sysreg.d
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+++ b/gas/testsuite/gas/aarch64/sysreg.d
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@@ -23,3 +23,6 @@ Disassembly of section \.text:
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3c: d5380260 mrs x0, id_isar3_el1
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40: d5380280 mrs x0, id_isar4_el1
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44: d53802a0 mrs x0, id_isar5_el1
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+ 48: d538cc00 mrs x0, s3_0_c12_c12_0
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+ 4c: d5384600 mrs x0, s3_0_c4_c6_0
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+ 50: d5184600 msr s3_0_c4_c6_0, x0
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diff --git a/gas/testsuite/gas/aarch64/sysreg.s b/gas/testsuite/gas/aarch64/sysreg.s
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index e6f770e..3287594 100644
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--- a/gas/testsuite/gas/aarch64/sysreg.s
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+++ b/gas/testsuite/gas/aarch64/sysreg.s
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@@ -22,3 +22,7 @@
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mrs x0, id_isar3_el1
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mrs x0, id_isar4_el1
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mrs x0, id_isar5_el1
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+
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+ mrs x0, s3_0_c12_c12_0
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+ mrs x0, s3_0_c4_c6_0
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+ msr s3_0_c4_c6_0, x0
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--
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1.9.0
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