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1a405f |
diff -rup binutils.orig/gas/testsuite/gas/ppc/power9.d binutils-2.27/gas/testsuite/gas/ppc/power9.d
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--- binutils.orig/gas/testsuite/gas/ppc/power9.d 2017-09-13 09:46:21.695333611 +0100
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+++ binutils-2.27/gas/testsuite/gas/ppc/power9.d 2017-09-13 09:53:46.594277167 +0100
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@@ -312,8 +312,9 @@ Disassembly of section \.text:
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.*: (f1 31 9d 6f|6f 9d 31 f1) xscvdphp vs41,vs51
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.*: (f1 58 a7 6f|6f a7 58 f1) xvcvhpsp vs42,vs52
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.*: (f1 79 af 6f|6f af 79 f1) xvcvsphp vs43,vs53
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-.*: (4c 60 00 04|04 00 60 4c) addpcis r3,0
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-.*: (4c 60 00 04|04 00 60 4c) addpcis r3,0
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+.*: (4c 60 00 04|04 00 60 4c) lnia r3
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+.*: (4c 60 00 04|04 00 60 4c) lnia r3
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+.*: (4c 60 00 04|04 00 60 4c) lnia r3
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.*: (4c 80 00 05|05 00 80 4c) addpcis r4,1
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.*: (4c 80 00 05|05 00 80 4c) addpcis r4,1
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.*: (4c bf ff c4|c4 ff bf 4c) addpcis r5,-2
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@@ -391,4 +392,7 @@ Disassembly of section \.text:
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.*: (ff d7 04 8e|8e 04 d7 ff) mffscrni f30,0
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.*: (ff d7 1c 8e|8e 1c d7 ff) mffscrni f30,3
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.*: (ff f8 04 8e|8e 04 f8 ff) mffsl f31
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+.*: (01 00 00 44|44 00 00 01) scv 0
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+.*: (e1 0f 00 44|44 00 0f e1) scv 127
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+.*: (a4 00 00 4c|4c 00 00 a4) rfscv
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#pass
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diff -rup binutils.orig/gas/testsuite/gas/ppc/power9.s binutils-2.27/gas/testsuite/gas/ppc/power9.s
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--- binutils.orig/gas/testsuite/gas/ppc/power9.s 2017-09-13 09:46:21.694333623 +0100
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+++ binutils-2.27/gas/testsuite/gas/ppc/power9.s 2017-09-13 09:54:01.747104949 +0100
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@@ -303,6 +303,7 @@ power9:
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xscvdphp 41,51
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xvcvhpsp 42,52
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xvcvsphp 43,53
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+ lnia 3
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addpcis 3,0
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subpcis 3,0
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addpcis 4,1
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@@ -382,3 +383,6 @@ power9:
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mffscrni 30,0
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mffscrni 30,3
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mffsl 31
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+ scv 0
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+ scv 127
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+ rfscv
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diff -rup binutils.orig/opcodes/ppc-opc.c binutils-2.27/opcodes/ppc-opc.c
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1a405f |
--- binutils.orig/opcodes/ppc-opc.c 2017-09-13 09:46:21.874331577 +0100
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+++ binutils-2.27/opcodes/ppc-opc.c 2017-09-13 09:55:18.745229836 +0100
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@@ -441,7 +441,7 @@ const struct powerpc_operand powerpc_ope
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#define L2OPT L32OPT + 1
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{ 0x3, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
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- /* The LEV field in a POWER SVC form instruction. */
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+ /* The LEV field in a POWER SVC / POWER9 SCV form instruction. */
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#define SVC_LEV L2OPT + 1
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{ 0x7f, 5, NULL, NULL, 0 },
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1a405f |
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1a405f |
@@ -2447,6 +2447,9 @@ extract_vleil (unsigned long insn,
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#define DX(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
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#define DX_MASK DX (0x3f, 0x1f)
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+/* An DX form instruction with the D bits specified. */
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+#define NODX_MASK (DX_MASK | 0x1fffc1)
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+
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1a405f |
/* An EVSEL form instruction. */
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#define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
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#define EVSEL_MASK EVSEL(0x3f, 0xff)
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1a405f |
@@ -4145,6 +4148,7 @@ const struct powerpc_opcode powerpc_opco
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{"bcla", B(16,1,1), B_MASK, COM, PPCVLE, {BO, BI, BDA}},
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1a405f |
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{"svc", SC(17,0,0), SC_MASK, POWER, PPCVLE, {SVC_LEV, FL1, FL2}},
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+{"scv", SC(17,0,1), SC_MASK, POWER9, PPCVLE, {SVC_LEV}},
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{"svcl", SC(17,0,1), SC_MASK, POWER, PPCVLE, {SVC_LEV, FL1, FL2}},
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{"sc", SC(17,1,0), SC_MASK, PPC, PPCVLE, {LEV}},
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1a405f |
{"svca", SC(17,1,0), SC_MASK, PWRCOM, PPCVLE, {SV}},
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1a405f |
@@ -4157,6 +4161,7 @@ const struct powerpc_opcode powerpc_opco
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1a405f |
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1a405f |
{"mcrf", XL(19,0), XLBB_MASK|(3<<21)|(3<<16), COM, PPCVLE, {BF, BFA}},
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1a405f |
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1a405f |
+{"lnia", DX(19,2), NODX_MASK, POWER9, PPCVLE, {RT}},
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{"addpcis", DX(19,2), DX_MASK, POWER9, PPCVLE, {RT, DXD}},
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1a405f |
{"subpcis", DX(19,2), DX_MASK, POWER9, PPCVLE, {RT, NDXD}},
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1a405f |
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1a405f |
@@ -4394,6 +4399,7 @@ const struct powerpc_opcode powerpc_opco
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1a405f |
{"rfi", XL(19,50), 0xffffffff, COM, PPCVLE, {0}},
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1a405f |
{"rfci", XL(19,51), 0xffffffff, PPC403|BOOKE|PPCE300|PPCA2|PPC476, PPCVLE, {0}},
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1a405f |
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1a405f |
+{"rfscv", XL(19,82), 0xffffffff, POWER9, PPCVLE, {0}},
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1a405f |
{"rfsvc", XL(19,82), 0xffffffff, POWER, PPCVLE, {0}},
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1a405f |
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1a405f |
{"rfgi", XL(19,102), 0xffffffff, E500MC|PPCA2, PPCVLE, {0}},
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