|
 |
be6651 |
diff -rup binutils.orig/gas/config/tc-ppc.c binutils-2.27/gas/config/tc-ppc.c
|
|
|
be6651 |
--- binutils.orig/gas/config/tc-ppc.c 2017-01-17 10:34:39.694867665 +0000
|
|
|
be6651 |
+++ binutils-2.27/gas/config/tc-ppc.c 2017-01-17 10:49:40.367225030 +0000
|
|
|
be6651 |
@@ -2671,7 +2671,8 @@ md_assemble (char *str)
|
|
|
be6651 |
const struct powerpc_operand *operand;
|
|
|
be6651 |
|
|
|
be6651 |
operand = &powerpc_operands[*opindex_ptr];
|
|
|
be6651 |
- if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0)
|
|
|
be6651 |
+ if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0
|
|
|
be6651 |
+ && !((operand->flags & PPC_OPERAND_OPTIONAL32) != 0 && ppc_obj64))
|
|
|
be6651 |
{
|
|
|
be6651 |
unsigned int opcount;
|
|
|
be6651 |
unsigned int num_operands_expected;
|
|
|
be6651 |
@@ -2741,6 +2742,7 @@ md_assemble (char *str)
|
|
|
be6651 |
/* If this is an optional operand, and we are skipping it, just
|
|
|
be6651 |
insert a zero. */
|
|
|
be6651 |
if ((operand->flags & PPC_OPERAND_OPTIONAL) != 0
|
|
|
be6651 |
+ && !((operand->flags & PPC_OPERAND_OPTIONAL32) != 0 && ppc_obj64)
|
|
|
be6651 |
&& skip_optional)
|
|
|
be6651 |
{
|
|
|
be6651 |
long val = ppc_optional_operand_value (operand);
|
|
|
be6651 |
@@ -2942,7 +2944,7 @@ md_assemble (char *str)
|
|
|
be6651 |
}
|
|
|
be6651 |
break;
|
|
|
be6651 |
}
|
|
|
be6651 |
- /* Fall thru */
|
|
|
be6651 |
+ /* Fallthru */
|
|
|
be6651 |
|
|
|
be6651 |
case BFD_RELOC_PPC64_ADDR16_HIGH:
|
|
|
be6651 |
ex.X_add_number = PPC_HI (ex.X_add_number);
|
|
|
be6651 |
@@ -2964,7 +2966,7 @@ md_assemble (char *str)
|
|
|
be6651 |
}
|
|
|
be6651 |
break;
|
|
|
be6651 |
}
|
|
|
be6651 |
- /* Fall thru */
|
|
|
be6651 |
+ /* Fallthru */
|
|
|
be6651 |
|
|
|
be6651 |
case BFD_RELOC_PPC64_ADDR16_HIGHA:
|
|
|
be6651 |
ex.X_add_number = PPC_HA (ex.X_add_number);
|
|
|
be6651 |
@@ -3087,14 +3089,14 @@ md_assemble (char *str)
|
|
|
be6651 |
{
|
|
|
be6651 |
int tmp_insn = insn & opcode->mask;
|
|
|
be6651 |
|
|
|
be6651 |
- int use_d_reloc = (tmp_insn == E_OR2I_INSN
|
|
|
be6651 |
+ int use_a_reloc = (tmp_insn == E_OR2I_INSN
|
|
|
be6651 |
|| tmp_insn == E_AND2I_DOT_INSN
|
|
|
be6651 |
|| tmp_insn == E_OR2IS_INSN
|
|
|
be6651 |
|| tmp_insn == E_LIS_INSN
|
|
|
be6651 |
|| tmp_insn == E_AND2IS_DOT_INSN);
|
|
|
be6651 |
|
|
|
be6651 |
|
|
|
be6651 |
- int use_a_reloc = (tmp_insn == E_ADD2I_DOT_INSN
|
|
|
be6651 |
+ int use_d_reloc = (tmp_insn == E_ADD2I_DOT_INSN
|
|
|
be6651 |
|| tmp_insn == E_ADD2IS_INSN
|
|
|
be6651 |
|| tmp_insn == E_CMP16I_INSN
|
|
|
be6651 |
|| tmp_insn == E_MULL2I_INSN
|
|
|
be6651 |
@@ -3377,13 +3379,17 @@ md_assemble (char *str)
|
|
|
be6651 |
however it'll remain clear for dual-mode instructions on
|
|
|
be6651 |
dual-mode and, more importantly, standard-mode processors. */
|
|
|
be6651 |
if ((ppc_cpu & opcode->flags) == PPC_OPCODE_VLE)
|
|
|
be6651 |
- ppc_apuinfo_section_add (PPC_APUINFO_VLE, 1);
|
|
|
be6651 |
+ {
|
|
|
be6651 |
+ ppc_apuinfo_section_add (PPC_APUINFO_VLE, 1);
|
|
|
be6651 |
+ if (elf_section_data (now_seg) != NULL)
|
|
|
be6651 |
+ elf_section_data (now_seg)->this_hdr.sh_flags |= SHF_PPC_VLE;
|
|
|
be6651 |
+ }
|
|
|
be6651 |
}
|
|
|
be6651 |
#endif
|
|
|
be6651 |
|
|
|
be6651 |
/* Write out the instruction. */
|
|
|
be6651 |
/* Differentiate between two and four byte insns. */
|
|
|
be6651 |
- if (ppc_mach () == bfd_mach_ppc_vle)
|
|
|
be6651 |
+ if ((ppc_cpu & PPC_OPCODE_VLE) != 0)
|
|
|
be6651 |
{
|
|
|
be6651 |
if (PPC_OP_SE_VLE (insn))
|
|
|
be6651 |
insn_length = 2;
|
|
|
be6651 |
@@ -3400,7 +3406,7 @@ md_assemble (char *str)
|
|
|
be6651 |
f = frag_more (insn_length);
|
|
|
be6651 |
if (frag_now->has_code && frag_now->insn_addr != addr_mod)
|
|
|
be6651 |
{
|
|
|
be6651 |
- if (ppc_mach() == bfd_mach_ppc_vle)
|
|
|
be6651 |
+ if ((ppc_cpu & PPC_OPCODE_VLE) != 0)
|
|
|
be6651 |
as_bad (_("instruction address is not a multiple of 2"));
|
|
|
be6651 |
else
|
|
|
be6651 |
as_bad (_("instruction address is not a multiple of 4"));
|
|
|
be6651 |
@@ -6346,7 +6352,7 @@ ppc_frag_check (struct frag *fragP)
|
|
|
be6651 |
if (!fragP->has_code)
|
|
|
be6651 |
return;
|
|
|
be6651 |
|
|
|
be6651 |
- if (ppc_mach() == bfd_mach_ppc_vle)
|
|
|
be6651 |
+ if ((ppc_cpu & PPC_OPCODE_VLE) != 0)
|
|
|
be6651 |
{
|
|
|
be6651 |
if (((fragP->fr_address + fragP->insn_addr) & 1) != 0)
|
|
|
be6651 |
as_bad (_("instruction address is not a multiple of 2"));
|
|
|
be6651 |
@@ -6367,7 +6373,7 @@ ppc_handle_align (struct frag *fragP)
|
|
|
be6651 |
valueT count = (fragP->fr_next->fr_address
|
|
|
be6651 |
- (fragP->fr_address + fragP->fr_fix));
|
|
|
be6651 |
|
|
|
be6651 |
- if (ppc_mach() == bfd_mach_ppc_vle && count != 0 && (count & 1) == 0)
|
|
|
be6651 |
+ if ((ppc_cpu & PPC_OPCODE_VLE) != 0 && count != 0 && (count & 1) == 0)
|
|
|
be6651 |
{
|
|
|
be6651 |
char *dest = fragP->fr_literal + fragP->fr_fix;
|
|
|
be6651 |
|
|
|
be6651 |
@@ -6565,7 +6571,7 @@ md_apply_fix (fixS *fixP, valueT *valP,
|
|
|
be6651 |
}
|
|
|
be6651 |
break;
|
|
|
be6651 |
}
|
|
|
be6651 |
- /* Fall thru */
|
|
|
be6651 |
+ /* Fallthru */
|
|
|
be6651 |
|
|
|
be6651 |
case BFD_RELOC_PPC_VLE_HI16A:
|
|
|
be6651 |
case BFD_RELOC_PPC_VLE_HI16D:
|
|
|
be6651 |
@@ -6588,7 +6594,7 @@ md_apply_fix (fixS *fixP, valueT *valP,
|
|
|
be6651 |
}
|
|
|
be6651 |
break;
|
|
|
be6651 |
}
|
|
|
be6651 |
- /* Fall thru */
|
|
|
be6651 |
+ /* Fallthru */
|
|
|
be6651 |
|
|
|
be6651 |
case BFD_RELOC_PPC_VLE_HA16A:
|
|
|
be6651 |
case BFD_RELOC_PPC_VLE_HA16D:
|
|
|
be6651 |
@@ -6730,7 +6736,7 @@ md_apply_fix (fixS *fixP, valueT *valP,
|
|
|
be6651 |
case BFD_RELOC_PPC_VLE_SDAREL_HA16A:
|
|
|
be6651 |
case BFD_RELOC_PPC_VLE_SDAREL_HA16D:
|
|
|
be6651 |
gas_assert (fixP->fx_addsy != NULL);
|
|
|
be6651 |
- /* Fall thru */
|
|
|
be6651 |
+ /* Fallthru */
|
|
|
be6651 |
|
|
|
be6651 |
case BFD_RELOC_PPC_TLS:
|
|
|
be6651 |
case BFD_RELOC_PPC_TLSGD:
|
|
|
be6651 |
@@ -6854,7 +6860,7 @@ md_apply_fix (fixS *fixP, valueT *valP,
|
|
|
be6651 |
&& !S_IS_DEFINED (fixP->fx_addsy)
|
|
|
be6651 |
&& !S_IS_WEAK (fixP->fx_addsy))
|
|
|
be6651 |
S_SET_WEAK (fixP->fx_addsy);
|
|
|
be6651 |
- /* Fall thru */
|
|
|
be6651 |
+ /* Fallthru */
|
|
|
be6651 |
|
|
|
be6651 |
case BFD_RELOC_VTABLE_ENTRY:
|
|
|
be6651 |
fixP->fx_done = 0;
|
|
|
be6651 |
diff -rup binutils.orig/gas/testsuite/gas/ppc/power9.d binutils-2.27/gas/testsuite/gas/ppc/power9.d
|
|
|
be6651 |
--- binutils.orig/gas/testsuite/gas/ppc/power9.d 2017-01-17 10:34:39.823866144 +0000
|
|
|
be6651 |
+++ binutils-2.27/gas/testsuite/gas/ppc/power9.d 2017-01-17 10:55:45.214908333 +0000
|
|
|
be6651 |
@@ -274,8 +274,8 @@ Disassembly of section \.text:
|
|
|
be6651 |
.*: (f3 89 ef 6f|6f ef 89 f3) xvxsigsp vs60,vs61
|
|
|
be6651 |
.*: (7c 06 39 c0|c0 39 06 7c) cmpeqb cr0,r6,r7
|
|
|
be6651 |
.*: (7f 86 39 c0|c0 39 86 7f) cmpeqb cr7,r6,r7
|
|
|
be6651 |
-.*: (7c 08 49 80|80 49 08 7c) cmprb cr0,r8,r9
|
|
|
be6651 |
-.*: (7f 88 49 80|80 49 88 7f) cmprb cr7,r8,r9
|
|
|
be6651 |
+.*: (7c 08 49 80|80 49 08 7c) cmprb cr0,0,r8,r9
|
|
|
be6651 |
+.*: (7f 88 49 80|80 49 88 7f) cmprb cr7,0,r8,r9
|
|
|
be6651 |
.*: (7c 28 49 80|80 49 28 7c) cmprb cr0,1,r8,r9
|
|
|
be6651 |
.*: (7f a8 49 80|80 49 a8 7f) cmprb cr7,1,r8,r9
|
|
|
be6651 |
.*: (7d e0 01 00|00 01 e0 7d) setb r15,cr0
|
|
|
be6651 |
diff -rup binutils.orig/gas/testsuite/gas/ppc/vle-reloc.d binutils-2.27/gas/testsuite/gas/ppc/vle-reloc.d
|
|
|
be6651 |
--- binutils.orig/gas/testsuite/gas/ppc/vle-reloc.d 2017-01-17 10:34:39.822866157 +0000
|
|
|
be6651 |
+++ binutils-2.27/gas/testsuite/gas/ppc/vle-reloc.d 2017-01-17 10:53:43.744345513 +0000
|
|
|
be6651 |
@@ -25,148 +25,148 @@ Disassembly of section \.text:
|
|
|
be6651 |
14: R_PPC_VLE_REL15 sub5
|
|
|
be6651 |
|
|
|
be6651 |
18: 70 20 c0 00 e_or2i r1,0
|
|
|
be6651 |
- 18: R_PPC_VLE_LO16D low
|
|
|
be6651 |
+ 18: R_PPC_VLE_LO16A low
|
|
|
be6651 |
1c: 70 40 c0 00 e_or2i r2,0
|
|
|
be6651 |
- 1c: R_PPC_VLE_HI16D high
|
|
|
be6651 |
+ 1c: R_PPC_VLE_HI16A high
|
|
|
be6651 |
20: 70 60 c0 00 e_or2i r3,0
|
|
|
be6651 |
- 20: R_PPC_VLE_HA16D high_adjust
|
|
|
be6651 |
+ 20: R_PPC_VLE_HA16A high_adjust
|
|
|
be6651 |
24: 70 80 c0 00 e_or2i r4,0
|
|
|
be6651 |
- 24: R_PPC_VLE_SDAREL_LO16D low_sdarel
|
|
|
be6651 |
+ 24: R_PPC_VLE_SDAREL_LO16A low_sdarel
|
|
|
be6651 |
28: 70 a0 c0 00 e_or2i r5,0
|
|
|
be6651 |
- 28: R_PPC_VLE_SDAREL_HI16D high_sdarel
|
|
|
be6651 |
+ 28: R_PPC_VLE_SDAREL_HI16A high_sdarel
|
|
|
be6651 |
2c: 70 40 c0 00 e_or2i r2,0
|
|
|
be6651 |
- 2c: R_PPC_VLE_SDAREL_HA16D high_adjust_sdarel
|
|
|
be6651 |
+ 2c: R_PPC_VLE_SDAREL_HA16A high_adjust_sdarel
|
|
|
be6651 |
30: 70 20 c8 00 e_and2i. r1,0
|
|
|
be6651 |
- 30: R_PPC_VLE_LO16D low
|
|
|
be6651 |
+ 30: R_PPC_VLE_LO16A low
|
|
|
be6651 |
34: 70 40 c8 00 e_and2i. r2,0
|
|
|
be6651 |
- 34: R_PPC_VLE_HI16D high
|
|
|
be6651 |
+ 34: R_PPC_VLE_HI16A high
|
|
|
be6651 |
38: 70 60 c8 00 e_and2i. r3,0
|
|
|
be6651 |
- 38: R_PPC_VLE_HA16D high_adjust
|
|
|
be6651 |
+ 38: R_PPC_VLE_HA16A high_adjust
|
|
|
be6651 |
3c: 70 80 c8 00 e_and2i. r4,0
|
|
|
be6651 |
- 3c: R_PPC_VLE_SDAREL_LO16D low_sdarel
|
|
|
be6651 |
+ 3c: R_PPC_VLE_SDAREL_LO16A low_sdarel
|
|
|
be6651 |
40: 70 a0 c8 00 e_and2i. r5,0
|
|
|
be6651 |
- 40: R_PPC_VLE_SDAREL_HI16D high_sdarel
|
|
|
be6651 |
+ 40: R_PPC_VLE_SDAREL_HI16A high_sdarel
|
|
|
be6651 |
44: 70 40 c8 00 e_and2i. r2,0
|
|
|
be6651 |
- 44: R_PPC_VLE_SDAREL_HA16D high_adjust_sdarel
|
|
|
be6651 |
+ 44: R_PPC_VLE_SDAREL_HA16A high_adjust_sdarel
|
|
|
be6651 |
48: 70 40 c8 00 e_and2i. r2,0
|
|
|
be6651 |
- 48: R_PPC_VLE_SDAREL_HA16D high_adjust_sdarel
|
|
|
be6651 |
+ 48: R_PPC_VLE_SDAREL_HA16A high_adjust_sdarel
|
|
|
be6651 |
4c: 70 20 d0 00 e_or2is r1,0
|
|
|
be6651 |
- 4c: R_PPC_VLE_LO16D low
|
|
|
be6651 |
+ 4c: R_PPC_VLE_LO16A low
|
|
|
be6651 |
50: 70 40 d0 00 e_or2is r2,0
|
|
|
be6651 |
- 50: R_PPC_VLE_HI16D high
|
|
|
be6651 |
+ 50: R_PPC_VLE_HI16A high
|
|
|
be6651 |
54: 70 60 d0 00 e_or2is r3,0
|
|
|
be6651 |
- 54: R_PPC_VLE_HA16D high_adjust
|
|
|
be6651 |
+ 54: R_PPC_VLE_HA16A high_adjust
|
|
|
be6651 |
58: 70 80 d0 00 e_or2is r4,0
|
|
|
be6651 |
- 58: R_PPC_VLE_SDAREL_LO16D low_sdarel
|
|
|
be6651 |
+ 58: R_PPC_VLE_SDAREL_LO16A low_sdarel
|
|
|
be6651 |
5c: 70 a0 d0 00 e_or2is r5,0
|
|
|
be6651 |
- 5c: R_PPC_VLE_SDAREL_HI16D high_sdarel
|
|
|
be6651 |
+ 5c: R_PPC_VLE_SDAREL_HI16A high_sdarel
|
|
|
be6651 |
60: 70 40 d0 00 e_or2is r2,0
|
|
|
be6651 |
- 60: R_PPC_VLE_SDAREL_HA16D high_adjust_sdarel
|
|
|
be6651 |
+ 60: R_PPC_VLE_SDAREL_HA16A high_adjust_sdarel
|
|
|
be6651 |
64: 70 20 e0 00 e_lis r1,0
|
|
|
be6651 |
- 64: R_PPC_VLE_LO16D low
|
|
|
be6651 |
+ 64: R_PPC_VLE_LO16A low
|
|
|
be6651 |
68: 70 40 e0 00 e_lis r2,0
|
|
|
be6651 |
- 68: R_PPC_VLE_HI16D high
|
|
|
be6651 |
+ 68: R_PPC_VLE_HI16A high
|
|
|
be6651 |
6c: 70 60 e0 00 e_lis r3,0
|
|
|
be6651 |
- 6c: R_PPC_VLE_HA16D high_adjust
|
|
|
be6651 |
+ 6c: R_PPC_VLE_HA16A high_adjust
|
|
|
be6651 |
70: 70 80 e0 00 e_lis r4,0
|
|
|
be6651 |
- 70: R_PPC_VLE_SDAREL_LO16D low_sdarel
|
|
|
be6651 |
+ 70: R_PPC_VLE_SDAREL_LO16A low_sdarel
|
|
|
be6651 |
74: 70 a0 e0 00 e_lis r5,0
|
|
|
be6651 |
- 74: R_PPC_VLE_SDAREL_HI16D high_sdarel
|
|
|
be6651 |
+ 74: R_PPC_VLE_SDAREL_HI16A high_sdarel
|
|
|
be6651 |
78: 70 40 e0 00 e_lis r2,0
|
|
|
be6651 |
- 78: R_PPC_VLE_SDAREL_HA16D high_adjust_sdarel
|
|
|
be6651 |
+ 78: R_PPC_VLE_SDAREL_HA16A high_adjust_sdarel
|
|
|
be6651 |
7c: 70 20 e8 00 e_and2is. r1,0
|
|
|
be6651 |
- 7c: R_PPC_VLE_LO16D low
|
|
|
be6651 |
+ 7c: R_PPC_VLE_LO16A low
|
|
|
be6651 |
80: 70 40 e8 00 e_and2is. r2,0
|
|
|
be6651 |
- 80: R_PPC_VLE_HI16D high
|
|
|
be6651 |
+ 80: R_PPC_VLE_HI16A high
|
|
|
be6651 |
84: 70 60 e8 00 e_and2is. r3,0
|
|
|
be6651 |
- 84: R_PPC_VLE_HA16D high_adjust
|
|
|
be6651 |
+ 84: R_PPC_VLE_HA16A high_adjust
|
|
|
be6651 |
88: 70 80 e8 00 e_and2is. r4,0
|
|
|
be6651 |
- 88: R_PPC_VLE_SDAREL_LO16D low_sdarel
|
|
|
be6651 |
+ 88: R_PPC_VLE_SDAREL_LO16A low_sdarel
|
|
|
be6651 |
8c: 70 a0 e8 00 e_and2is. r5,0
|
|
|
be6651 |
- 8c: R_PPC_VLE_SDAREL_HI16D high_sdarel
|
|
|
be6651 |
+ 8c: R_PPC_VLE_SDAREL_HI16A high_sdarel
|
|
|
be6651 |
90: 70 40 e8 00 e_and2is. r2,0
|
|
|
be6651 |
- 90: R_PPC_VLE_SDAREL_HA16D high_adjust_sdarel
|
|
|
be6651 |
+ 90: R_PPC_VLE_SDAREL_HA16A high_adjust_sdarel
|
|
|
be6651 |
94: 70 01 98 00 e_cmp16i r1,0
|
|
|
be6651 |
- 94: R_PPC_VLE_LO16A low
|
|
|
be6651 |
+ 94: R_PPC_VLE_LO16D low
|
|
|
be6651 |
98: 70 02 98 00 e_cmp16i r2,0
|
|
|
be6651 |
- 98: R_PPC_VLE_HI16A high
|
|
|
be6651 |
+ 98: R_PPC_VLE_HI16D high
|
|
|
be6651 |
9c: 70 03 98 00 e_cmp16i r3,0
|
|
|
be6651 |
- 9c: R_PPC_VLE_HA16A high_adjust
|
|
|
be6651 |
+ 9c: R_PPC_VLE_HA16D high_adjust
|
|
|
be6651 |
a0: 70 04 98 00 e_cmp16i r4,0
|
|
|
be6651 |
- a0: R_PPC_VLE_SDAREL_LO16A low_sdarel
|
|
|
be6651 |
+ a0: R_PPC_VLE_SDAREL_LO16D low_sdarel
|
|
|
be6651 |
a4: 70 05 98 00 e_cmp16i r5,0
|
|
|
be6651 |
- a4: R_PPC_VLE_SDAREL_HI16A high_sdarel
|
|
|
be6651 |
+ a4: R_PPC_VLE_SDAREL_HI16D high_sdarel
|
|
|
be6651 |
a8: 70 02 98 00 e_cmp16i r2,0
|
|
|
be6651 |
- a8: R_PPC_VLE_SDAREL_HA16A high_adjust_sdarel
|
|
|
be6651 |
+ a8: R_PPC_VLE_SDAREL_HA16D high_adjust_sdarel
|
|
|
be6651 |
ac: 70 01 a8 00 e_cmpl16i r1,0
|
|
|
be6651 |
- ac: R_PPC_VLE_LO16A low
|
|
|
be6651 |
+ ac: R_PPC_VLE_LO16D low
|
|
|
be6651 |
b0: 70 02 a8 00 e_cmpl16i r2,0
|
|
|
be6651 |
- b0: R_PPC_VLE_HI16A high
|
|
|
be6651 |
+ b0: R_PPC_VLE_HI16D high
|
|
|
be6651 |
b4: 70 03 a8 00 e_cmpl16i r3,0
|
|
|
be6651 |
- b4: R_PPC_VLE_HA16A high_adjust
|
|
|
be6651 |
+ b4: R_PPC_VLE_HA16D high_adjust
|
|
|
be6651 |
b8: 70 04 a8 00 e_cmpl16i r4,0
|
|
|
be6651 |
- b8: R_PPC_VLE_SDAREL_LO16A low_sdarel
|
|
|
be6651 |
+ b8: R_PPC_VLE_SDAREL_LO16D low_sdarel
|
|
|
be6651 |
bc: 70 05 a8 00 e_cmpl16i r5,0
|
|
|
be6651 |
- bc: R_PPC_VLE_SDAREL_HI16A high_sdarel
|
|
|
be6651 |
+ bc: R_PPC_VLE_SDAREL_HI16D high_sdarel
|
|
|
be6651 |
c0: 70 02 a8 00 e_cmpl16i r2,0
|
|
|
be6651 |
- c0: R_PPC_VLE_SDAREL_HA16A high_adjust_sdarel
|
|
|
be6651 |
+ c0: R_PPC_VLE_SDAREL_HA16D high_adjust_sdarel
|
|
|
be6651 |
c4: 70 01 b0 00 e_cmph16i r1,0
|
|
|
be6651 |
- c4: R_PPC_VLE_LO16A low
|
|
|
be6651 |
+ c4: R_PPC_VLE_LO16D low
|
|
|
be6651 |
c8: 70 02 b0 00 e_cmph16i r2,0
|
|
|
be6651 |
- c8: R_PPC_VLE_HI16A high
|
|
|
be6651 |
+ c8: R_PPC_VLE_HI16D high
|
|
|
be6651 |
cc: 70 03 b0 00 e_cmph16i r3,0
|
|
|
be6651 |
- cc: R_PPC_VLE_HA16A high_adjust
|
|
|
be6651 |
+ cc: R_PPC_VLE_HA16D high_adjust
|
|
|
be6651 |
d0: 70 04 b0 00 e_cmph16i r4,0
|
|
|
be6651 |
- d0: R_PPC_VLE_SDAREL_LO16A low_sdarel
|
|
|
be6651 |
+ d0: R_PPC_VLE_SDAREL_LO16D low_sdarel
|
|
|
be6651 |
d4: 70 05 b0 00 e_cmph16i r5,0
|
|
|
be6651 |
- d4: R_PPC_VLE_SDAREL_HI16A high_sdarel
|
|
|
be6651 |
+ d4: R_PPC_VLE_SDAREL_HI16D high_sdarel
|
|
|
be6651 |
d8: 70 02 b0 00 e_cmph16i r2,0
|
|
|
be6651 |
- d8: R_PPC_VLE_SDAREL_HA16A high_adjust_sdarel
|
|
|
be6651 |
+ d8: R_PPC_VLE_SDAREL_HA16D high_adjust_sdarel
|
|
|
be6651 |
dc: 70 01 b8 00 e_cmphl16i r1,0
|
|
|
be6651 |
- dc: R_PPC_VLE_LO16A low
|
|
|
be6651 |
+ dc: R_PPC_VLE_LO16D low
|
|
|
be6651 |
e0: 70 02 b8 00 e_cmphl16i r2,0
|
|
|
be6651 |
- e0: R_PPC_VLE_HI16A high
|
|
|
be6651 |
+ e0: R_PPC_VLE_HI16D high
|
|
|
be6651 |
e4: 70 03 b8 00 e_cmphl16i r3,0
|
|
|
be6651 |
- e4: R_PPC_VLE_HA16A high_adjust
|
|
|
be6651 |
+ e4: R_PPC_VLE_HA16D high_adjust
|
|
|
be6651 |
e8: 70 04 b8 00 e_cmphl16i r4,0
|
|
|
be6651 |
- e8: R_PPC_VLE_SDAREL_LO16A low_sdarel
|
|
|
be6651 |
+ e8: R_PPC_VLE_SDAREL_LO16D low_sdarel
|
|
|
be6651 |
ec: 70 05 b8 00 e_cmphl16i r5,0
|
|
|
be6651 |
- ec: R_PPC_VLE_SDAREL_HI16A high_sdarel
|
|
|
be6651 |
+ ec: R_PPC_VLE_SDAREL_HI16D high_sdarel
|
|
|
be6651 |
f0: 70 02 b8 00 e_cmphl16i r2,0
|
|
|
be6651 |
- f0: R_PPC_VLE_SDAREL_HA16A high_adjust_sdarel
|
|
|
be6651 |
+ f0: R_PPC_VLE_SDAREL_HA16D high_adjust_sdarel
|
|
|
be6651 |
f4: 70 01 88 00 e_add2i. r1,0
|
|
|
be6651 |
- f4: R_PPC_VLE_LO16A low
|
|
|
be6651 |
+ f4: R_PPC_VLE_LO16D low
|
|
|
be6651 |
f8: 70 02 88 00 e_add2i. r2,0
|
|
|
be6651 |
- f8: R_PPC_VLE_HI16A high
|
|
|
be6651 |
+ f8: R_PPC_VLE_HI16D high
|
|
|
be6651 |
fc: 70 03 88 00 e_add2i. r3,0
|
|
|
be6651 |
- fc: R_PPC_VLE_HA16A high_adjust
|
|
|
be6651 |
+ fc: R_PPC_VLE_HA16D high_adjust
|
|
|
be6651 |
100: 70 04 88 00 e_add2i. r4,0
|
|
|
be6651 |
- 100: R_PPC_VLE_SDAREL_LO16A low_sdarel
|
|
|
be6651 |
+ 100: R_PPC_VLE_SDAREL_LO16D low_sdarel
|
|
|
be6651 |
104: 70 05 88 00 e_add2i. r5,0
|
|
|
be6651 |
- 104: R_PPC_VLE_SDAREL_HI16A high_sdarel
|
|
|
be6651 |
+ 104: R_PPC_VLE_SDAREL_HI16D high_sdarel
|
|
|
be6651 |
108: 70 02 88 00 e_add2i. r2,0
|
|
|
be6651 |
- 108: R_PPC_VLE_SDAREL_HA16A high_adjust_sdarel
|
|
|
be6651 |
+ 108: R_PPC_VLE_SDAREL_HA16D high_adjust_sdarel
|
|
|
be6651 |
10c: 70 01 90 00 e_add2is r1,0
|
|
|
be6651 |
- 10c: R_PPC_VLE_LO16A low
|
|
|
be6651 |
+ 10c: R_PPC_VLE_LO16D low
|
|
|
be6651 |
110: 70 02 90 00 e_add2is r2,0
|
|
|
be6651 |
- 110: R_PPC_VLE_HI16A high
|
|
|
be6651 |
+ 110: R_PPC_VLE_HI16D high
|
|
|
be6651 |
114: 70 03 90 00 e_add2is r3,0
|
|
|
be6651 |
- 114: R_PPC_VLE_HA16A high_adjust
|
|
|
be6651 |
+ 114: R_PPC_VLE_HA16D high_adjust
|
|
|
be6651 |
118: 70 04 90 00 e_add2is r4,0
|
|
|
be6651 |
- 118: R_PPC_VLE_SDAREL_LO16A low_sdarel
|
|
|
be6651 |
+ 118: R_PPC_VLE_SDAREL_LO16D low_sdarel
|
|
|
be6651 |
11c: 70 05 90 00 e_add2is r5,0
|
|
|
be6651 |
- 11c: R_PPC_VLE_SDAREL_HI16A high_sdarel
|
|
|
be6651 |
+ 11c: R_PPC_VLE_SDAREL_HI16D high_sdarel
|
|
|
be6651 |
120: 70 02 90 00 e_add2is r2,0
|
|
|
be6651 |
- 120: R_PPC_VLE_SDAREL_HA16A high_adjust_sdarel
|
|
|
be6651 |
+ 120: R_PPC_VLE_SDAREL_HA16D high_adjust_sdarel
|
|
|
be6651 |
124: 70 01 a0 00 e_mull2i r1,0
|
|
|
be6651 |
- 124: R_PPC_VLE_LO16A low
|
|
|
be6651 |
+ 124: R_PPC_VLE_LO16D low
|
|
|
be6651 |
128: 70 02 a0 00 e_mull2i r2,0
|
|
|
be6651 |
- 128: R_PPC_VLE_HI16A high
|
|
|
be6651 |
+ 128: R_PPC_VLE_HI16D high
|
|
|
be6651 |
12c: 70 03 a0 00 e_mull2i r3,0
|
|
|
be6651 |
- 12c: R_PPC_VLE_HA16A high_adjust
|
|
|
be6651 |
+ 12c: R_PPC_VLE_HA16D high_adjust
|
|
|
be6651 |
130: 70 04 a0 00 e_mull2i r4,0
|
|
|
be6651 |
- 130: R_PPC_VLE_SDAREL_LO16A low_sdarel
|
|
|
be6651 |
+ 130: R_PPC_VLE_SDAREL_LO16D low_sdarel
|
|
|
be6651 |
134: 70 05 a0 00 e_mull2i r5,0
|
|
|
be6651 |
- 134: R_PPC_VLE_SDAREL_HI16A high_sdarel
|
|
|
be6651 |
+ 134: R_PPC_VLE_SDAREL_HI16D high_sdarel
|
|
|
be6651 |
138: 70 02 a0 00 e_mull2i r2,0
|
|
|
be6651 |
- 138: R_PPC_VLE_SDAREL_HA16A high_adjust_sdarel
|
|
|
be6651 |
+ 138: R_PPC_VLE_SDAREL_HA16D high_adjust_sdarel
|
|
|
be6651 |
diff -rup binutils.orig/include/opcode/ppc.h binutils-2.27/include/opcode/ppc.h
|
|
|
be6651 |
--- binutils.orig/include/opcode/ppc.h 2017-01-17 10:34:39.864865661 +0000
|
|
|
be6651 |
+++ binutils-2.27/include/opcode/ppc.h 2017-01-17 10:49:40.367225030 +0000
|
|
|
be6651 |
@@ -407,6 +407,10 @@ extern const unsigned int num_powerpc_op
|
|
|
be6651 |
is omitted, then the value it should use for the operand is stored
|
|
|
be6651 |
in the SHIFT field of the immediatly following operand field. */
|
|
|
be6651 |
#define PPC_OPERAND_OPTIONAL_VALUE (0x400000)
|
|
|
be6651 |
+
|
|
|
be6651 |
+/* This flag is only used with PPC_OPERAND_OPTIONAL. The operand is
|
|
|
be6651 |
+ only optional when generating 32-bit code. */
|
|
|
be6651 |
+#define PPC_OPERAND_OPTIONAL32 (0x800000)
|
|
|
be6651 |
|
|
|
be6651 |
/* The POWER and PowerPC assemblers use a few macros. We keep them
|
|
|
be6651 |
with the operands table for simplicity. The macro table is an
|
|
|
be6651 |
@@ -444,6 +448,23 @@ ppc_optional_operand_value (const struct
|
|
|
be6651 |
return 0;
|
|
|
be6651 |
}
|
|
|
be6651 |
|
|
|
be6651 |
+/* PowerPC VLE insns. */
|
|
|
be6651 |
+/* Form I16L, uses 16A relocs. */
|
|
|
be6651 |
+#define E_OR2I_INSN 0x7000C000
|
|
|
be6651 |
+#define E_AND2I_DOT_INSN 0x7000C800
|
|
|
be6651 |
+#define E_OR2IS_INSN 0x7000D000
|
|
|
be6651 |
+#define E_LIS_INSN 0x7000E000
|
|
|
be6651 |
+#define E_AND2IS_DOT_INSN 0x7000E800
|
|
|
be6651 |
+
|
|
|
be6651 |
+/* Form I16A, uses 16D relocs. */
|
|
|
be6651 |
+#define E_ADD2I_DOT_INSN 0x70008800
|
|
|
be6651 |
+#define E_ADD2IS_INSN 0x70009000
|
|
|
be6651 |
+#define E_CMP16I_INSN 0x70009800
|
|
|
be6651 |
+#define E_MULL2I_INSN 0x7000A000
|
|
|
be6651 |
+#define E_CMPL16I_INSN 0x7000A800
|
|
|
be6651 |
+#define E_CMPH16I_INSN 0x7000B000
|
|
|
be6651 |
+#define E_CMPHL16I_INSN 0x7000B800
|
|
|
be6651 |
+
|
|
|
be6651 |
#ifdef __cplusplus
|
|
|
be6651 |
}
|
|
|
be6651 |
#endif
|
|
|
be6651 |
diff -rup binutils.orig/opcodes/ppc-dis.c binutils-2.27/opcodes/ppc-dis.c
|
|
|
be6651 |
--- binutils.orig/opcodes/ppc-dis.c 2017-01-17 10:34:40.064863304 +0000
|
|
|
be6651 |
+++ binutils-2.27/opcodes/ppc-dis.c 2017-01-17 10:49:40.391224746 +0000
|
|
|
be6651 |
@@ -236,7 +236,7 @@ get_powerpc_dialect (struct disassemble_
|
|
|
be6651 |
|
|
|
be6651 |
/* Disassemble according to the section headers flags for VLE-mode. */
|
|
|
be6651 |
if (dialect & PPC_OPCODE_VLE
|
|
|
be6651 |
- && info->section->owner != NULL
|
|
|
be6651 |
+ && info->section != NULL && info->section->owner != NULL
|
|
|
be6651 |
&& bfd_get_flavour (info->section->owner) == bfd_target_elf_flavour
|
|
|
be6651 |
&& elf_object_id (info->section->owner) == PPC32_ELF_DATA
|
|
|
be6651 |
&& (elf_section_flags (info->section) & SHF_PPC_VLE) != 0)
|
|
|
be6651 |
diff -rup binutils.orig/opcodes/ppc-opc.c binutils-2.27/opcodes/ppc-opc.c
|
|
|
be6651 |
--- binutils.orig/opcodes/ppc-opc.c 2017-01-17 10:34:40.064863304 +0000
|
|
|
be6651 |
+++ binutils-2.27/opcodes/ppc-opc.c 2017-01-17 10:49:40.393224722 +0000
|
|
|
be6651 |
@@ -62,10 +62,6 @@ static unsigned long insert_dxdn (unsign
|
|
|
be6651 |
static long extract_dxdn (unsigned long, ppc_cpu_t, int *);
|
|
|
be6651 |
static unsigned long insert_fxm (unsigned long, long, ppc_cpu_t, const char **);
|
|
|
be6651 |
static long extract_fxm (unsigned long, ppc_cpu_t, int *);
|
|
|
be6651 |
-static unsigned long insert_l0 (unsigned long, long, ppc_cpu_t, const char **);
|
|
|
be6651 |
-static long extract_l0 (unsigned long, ppc_cpu_t, int *);
|
|
|
be6651 |
-static unsigned long insert_l1 (unsigned long, long, ppc_cpu_t, const char **);
|
|
|
be6651 |
-static long extract_l1 (unsigned long, ppc_cpu_t, int *);
|
|
|
be6651 |
static unsigned long insert_li20 (unsigned long, long, ppc_cpu_t, const char **);
|
|
|
be6651 |
static long extract_li20 (unsigned long, ppc_cpu_t, int *);
|
|
|
be6651 |
static unsigned long insert_ls (unsigned long, long, ppc_cpu_t, const char **);
|
|
|
be6651 |
@@ -429,20 +425,24 @@ const struct powerpc_operand powerpc_ope
|
|
|
be6651 |
|
|
|
be6651 |
/* The L field in a D or X form instruction. */
|
|
|
be6651 |
#define L IMM20 + 1
|
|
|
be6651 |
+ { 0x1, 21, NULL, NULL, 0 },
|
|
|
be6651 |
+
|
|
|
be6651 |
+ /* The optional L field in tlbie and tlbiel instructions. */
|
|
|
be6651 |
+#define LOPT L + 1
|
|
|
be6651 |
/* The R field in a HTM X form instruction. */
|
|
|
be6651 |
-#define HTM_R L
|
|
|
be6651 |
+#define HTM_R LOPT
|
|
|
be6651 |
{ 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
|
|
|
be6651 |
|
|
|
be6651 |
- /* The L field in an X form instruction which must be zero. */
|
|
|
be6651 |
-#define L0 L + 1
|
|
|
be6651 |
- { 0x1, 21, insert_l0, extract_l0, PPC_OPERAND_OPTIONAL },
|
|
|
be6651 |
-
|
|
|
be6651 |
- /* The L field in an X form instruction which must be one. */
|
|
|
be6651 |
-#define L1 L0 + 1
|
|
|
be6651 |
- { 0x1, 21, insert_l1, extract_l1, 0 },
|
|
|
be6651 |
+ /* The optional (for 32-bit) L field in cmp[l][i] instructions. */
|
|
|
be6651 |
+#define L32OPT LOPT + 1
|
|
|
be6651 |
+ { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_OPTIONAL32 },
|
|
|
be6651 |
+
|
|
|
be6651 |
+ /* The L field in dcbf instruction. */
|
|
|
be6651 |
+#define L2OPT L32OPT + 1
|
|
|
be6651 |
+ { 0x3, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },
|
|
|
be6651 |
|
|
|
be6651 |
/* The LEV field in a POWER SVC form instruction. */
|
|
|
be6651 |
-#define SVC_LEV L1 + 1
|
|
|
be6651 |
+#define SVC_LEV L2OPT + 1
|
|
|
be6651 |
{ 0x7f, 5, NULL, NULL, 0 },
|
|
|
be6651 |
|
|
|
be6651 |
/* The LEV field in an SC form instruction. */
|
|
|
be6651 |
@@ -688,6 +688,8 @@ const struct powerpc_operand powerpc_ope
|
|
|
be6651 |
#define STRM SR + 1
|
|
|
be6651 |
/* The T field in a tlbilx form instruction. */
|
|
|
be6651 |
#define T STRM
|
|
|
be6651 |
+ /* The L field in wclr instructions. */
|
|
|
be6651 |
+#define L2 STRM
|
|
|
be6651 |
{ 0x3, 21, NULL, NULL, 0 },
|
|
|
be6651 |
|
|
|
be6651 |
/* The ESYNC field in an X (sync) form instruction. */
|
|
|
be6651 |
@@ -1483,58 +1485,6 @@ extract_fxm (unsigned long insn,
|
|
|
be6651 |
return mask;
|
|
|
be6651 |
}
|
|
|
be6651 |
|
|
|
be6651 |
-/* The L field in an X form instruction which must have the value zero. */
|
|
|
be6651 |
-
|
|
|
be6651 |
-static unsigned long
|
|
|
be6651 |
-insert_l0 (unsigned long insn,
|
|
|
be6651 |
- long value,
|
|
|
be6651 |
- ppc_cpu_t dialect ATTRIBUTE_UNUSED,
|
|
|
be6651 |
- const char **errmsg)
|
|
|
be6651 |
-{
|
|
|
be6651 |
- if (value != 0)
|
|
|
be6651 |
- *errmsg = _("invalid operand constant");
|
|
|
be6651 |
- return insn & ~(0x1 << 21);
|
|
|
be6651 |
-}
|
|
|
be6651 |
-
|
|
|
be6651 |
-static long
|
|
|
be6651 |
-extract_l0 (unsigned long insn,
|
|
|
be6651 |
- ppc_cpu_t dialect ATTRIBUTE_UNUSED,
|
|
|
be6651 |
- int *invalid)
|
|
|
be6651 |
-{
|
|
|
be6651 |
- long value;
|
|
|
be6651 |
-
|
|
|
be6651 |
- value = (insn >> 21) & 0x1;
|
|
|
be6651 |
- if (value != 0)
|
|
|
be6651 |
- *invalid = 1;
|
|
|
be6651 |
- return value;
|
|
|
be6651 |
-}
|
|
|
be6651 |
-
|
|
|
be6651 |
-/* The L field in an X form instruction which must have the value one. */
|
|
|
be6651 |
-
|
|
|
be6651 |
-static unsigned long
|
|
|
be6651 |
-insert_l1 (unsigned long insn,
|
|
|
be6651 |
- long value,
|
|
|
be6651 |
- ppc_cpu_t dialect ATTRIBUTE_UNUSED,
|
|
|
be6651 |
- const char **errmsg)
|
|
|
be6651 |
-{
|
|
|
be6651 |
- if (value != 1)
|
|
|
be6651 |
- *errmsg = _("invalid operand constant");
|
|
|
be6651 |
- return insn | (0x1 << 21);
|
|
|
be6651 |
-}
|
|
|
be6651 |
-
|
|
|
be6651 |
-static long
|
|
|
be6651 |
-extract_l1 (unsigned long insn,
|
|
|
be6651 |
- ppc_cpu_t dialect ATTRIBUTE_UNUSED,
|
|
|
be6651 |
- int *invalid)
|
|
|
be6651 |
-{
|
|
|
be6651 |
- long value;
|
|
|
be6651 |
-
|
|
|
be6651 |
- value = (insn >> 21) & 0x1;
|
|
|
be6651 |
- if (value != 1)
|
|
|
be6651 |
- *invalid = 1;
|
|
|
be6651 |
- return value;
|
|
|
be6651 |
-}
|
|
|
be6651 |
-
|
|
|
be6651 |
static unsigned long
|
|
|
be6651 |
insert_li20 (unsigned long insn,
|
|
|
be6651 |
long value,
|
|
|
be6651 |
@@ -3890,12 +3840,12 @@ const struct powerpc_opcode powerpc_opco
|
|
|
be6651 |
|
|
|
be6651 |
{"cmplwi", OPL(10,0), OPL_MASK, PPCCOM, PPCVLE, {OBF, RA, UISIGNOPT}},
|
|
|
be6651 |
{"cmpldi", OPL(10,1), OPL_MASK, PPC64, PPCVLE, {OBF, RA, UISIGNOPT}},
|
|
|
be6651 |
-{"cmpli", OP(10), OP_MASK, PPC, PPCVLE, {BF, L, RA, UISIGNOPT}},
|
|
|
be6651 |
+{"cmpli", OP(10), OP_MASK, PPC, PPCVLE, {BF, L32OPT, RA, UISIGNOPT}},
|
|
|
be6651 |
{"cmpli", OP(10), OP_MASK, PWRCOM, PPC|PPCVLE, {BF, RA, UISIGNOPT}},
|
|
|
be6651 |
|
|
|
be6651 |
{"cmpwi", OPL(11,0), OPL_MASK, PPCCOM, PPCVLE, {OBF, RA, SI}},
|
|
|
be6651 |
{"cmpdi", OPL(11,1), OPL_MASK, PPC64, PPCVLE, {OBF, RA, SI}},
|
|
|
be6651 |
-{"cmpi", OP(11), OP_MASK, PPC, PPCVLE, {BF, L, RA, SI}},
|
|
|
be6651 |
+{"cmpi", OP(11), OP_MASK, PPC, PPCVLE, {BF, L32OPT, RA, SI}},
|
|
|
be6651 |
{"cmpi", OP(11), OP_MASK, PWRCOM, PPC|PPCVLE, {BF, RA, SI}},
|
|
|
be6651 |
|
|
|
be6651 |
{"addic", OP(12), OP_MASK, PPCCOM, PPCVLE, {RT, RA, SI}},
|
|
|
be6651 |
@@ -4713,7 +4663,7 @@ const struct powerpc_opcode powerpc_opco
|
|
|
be6651 |
|
|
|
be6651 |
{"cmpw", XOPL(31,0,0), XCMPL_MASK, PPCCOM, 0, {OBF, RA, RB}},
|
|
|
be6651 |
{"cmpd", XOPL(31,0,1), XCMPL_MASK, PPC64, 0, {OBF, RA, RB}},
|
|
|
be6651 |
-{"cmp", X(31,0), XCMP_MASK, PPC, 0, {BF, L, RA, RB}},
|
|
|
be6651 |
+{"cmp", X(31,0), XCMP_MASK, PPC, 0, {BF, L32OPT, RA, RB}},
|
|
|
be6651 |
{"cmp", X(31,0), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}},
|
|
|
be6651 |
|
|
|
be6651 |
{"twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, 0, {RA, RB}},
|
|
|
be6651 |
@@ -4821,7 +4771,7 @@ const struct powerpc_opcode powerpc_opco
|
|
|
be6651 |
|
|
|
be6651 |
{"cmplw", XOPL(31,32,0), XCMPL_MASK, PPCCOM, 0, {OBF, RA, RB}},
|
|
|
be6651 |
{"cmpld", XOPL(31,32,1), XCMPL_MASK, PPC64, 0, {OBF, RA, RB}},
|
|
|
be6651 |
-{"cmpl", X(31,32), XCMP_MASK, PPC, 0, {BF, L, RA, RB}},
|
|
|
be6651 |
+{"cmpl", X(31,32), XCMP_MASK, PPC, 0, {BF, L32OPT, RA, RB}},
|
|
|
be6651 |
{"cmpl", X(31,32), XCMPL_MASK, PWRCOM, PPC, {BF, RA, RB}},
|
|
|
be6651 |
|
|
|
be6651 |
{"lvsr", X(31,38), X_MASK, PPCVEC, 0, {VD, RA0, RB}},
|
|
|
be6651 |
@@ -4907,7 +4857,7 @@ const struct powerpc_opcode powerpc_opco
|
|
|
be6651 |
{"ldarx", X(31,84), XEH_MASK, PPC64, 0, {RT, RA0, RB, EH}},
|
|
|
be6651 |
|
|
|
be6651 |
{"dcbfl", XOPL(31,86,1), XRT_MASK, POWER5, PPC476, {RA0, RB}},
|
|
|
be6651 |
-{"dcbf", X(31,86), XLRT_MASK, PPC, 0, {RA0, RB, L}},
|
|
|
be6651 |
+{"dcbf", X(31,86), XLRT_MASK, PPC, 0, {RA0, RB, L2OPT}},
|
|
|
be6651 |
|
|
|
be6651 |
{"lbzx", X(31,87), X_MASK, COM, 0, {RT, RA0, RB}},
|
|
|
be6651 |
|
|
|
be6651 |
@@ -5149,7 +5099,7 @@ const struct powerpc_opcode powerpc_opco
|
|
|
be6651 |
{"ehpriv", X(31,270), 0xffffffff, E500MC|PPCA2, 0, {0}},
|
|
|
be6651 |
|
|
|
be6651 |
{"tlbiel", X(31,274), X_MASK|1<<20,POWER9, PPC476, {RB, RSO, RIC, PRS, X_R}},
|
|
|
be6651 |
-{"tlbiel", X(31,274), XRTLRA_MASK, POWER4, POWER9|PPC476, {RB, L}},
|
|
|
be6651 |
+{"tlbiel", X(31,274), XRTLRA_MASK, POWER4, POWER9|PPC476, {RB, LOPT}},
|
|
|
be6651 |
|
|
|
be6651 |
{"mfapidi", X(31,275), X_MASK, BOOKE, E500|TITAN, {RT, RA}},
|
|
|
be6651 |
|
|
|
be6651 |
@@ -6233,8 +6183,8 @@ const struct powerpc_opcode powerpc_opco
|
|
|
be6651 |
{"stvfrxl", X(31,933), X_MASK, PPCVEC2, 0, {VS, RA0, RB}},
|
|
|
be6651 |
|
|
|
be6651 |
{"wclrone", XOPL2(31,934,2),XRT_MASK, PPCA2, 0, {RA0, RB}},
|
|
|
be6651 |
-{"wclrall", X(31,934), XRARB_MASK, PPCA2, 0, {L}},
|
|
|
be6651 |
-{"wclr", X(31,934), X_MASK, PPCA2, 0, {L, RA0, RB}},
|
|
|
be6651 |
+{"wclrall", X(31,934), XRARB_MASK, PPCA2, 0, {L2}},
|
|
|
be6651 |
+{"wclr", X(31,934), X_MASK, PPCA2, 0, {L2, RA0, RB}},
|
|
|
be6651 |
|
|
|
be6651 |
{"stvrxl", X(31,935), X_MASK, CELL, 0, {VS, RA0, RB}},
|
|
|
be6651 |
|