diff -rup binutils.orig/gas/config/tc-arm.c binutils-2.27/gas/config/tc-arm.c

--- binutils.orig/gas/config/tc-arm.c	2017-08-09 10:26:30.032741952 +0100

+++ binutils-2.27/gas/config/tc-arm.c	2017-08-09 11:17:17.747598541 +0100

@@ -147,8 +147,10 @@ static const arm_feature_set *legacy_cpu

 static const arm_feature_set *legacy_fpu = NULL;

 static const arm_feature_set *mcpu_cpu_opt = NULL;

+static arm_feature_set *dyn_mcpu_ext_opt = NULL;

 static const arm_feature_set *mcpu_fpu_opt = NULL;

 static const arm_feature_set *march_cpu_opt = NULL;

+static arm_feature_set *dyn_march_ext_opt = NULL;

 static const arm_feature_set *march_fpu_opt = NULL;

 static const arm_feature_set *mfpu_opt = NULL;

 static const arm_feature_set *object_arch = NULL;

@@ -187,7 +189,6 @@ static const arm_feature_set arm_ext_v5j

 static const arm_feature_set arm_ext_v6 = ARM_FEATURE_CORE_LOW (ARM_EXT_V6);

 static const arm_feature_set arm_ext_v6k = ARM_FEATURE_CORE_LOW (ARM_EXT_V6K);

 static const arm_feature_set arm_ext_v6t2 = ARM_FEATURE_CORE_LOW (ARM_EXT_V6T2);

-static const arm_feature_set arm_ext_v6m = ARM_FEATURE_CORE_LOW (ARM_EXT_V6M);

 static const arm_feature_set arm_ext_v6_notm =

   ARM_FEATURE_CORE_LOW (ARM_EXT_V6_NOTM);

 static const arm_feature_set arm_ext_v6_dsp =

@@ -201,11 +202,11 @@ static const arm_feature_set arm_ext_v7

 static const arm_feature_set arm_ext_v7a = ARM_FEATURE_CORE_LOW (ARM_EXT_V7A);

 static const arm_feature_set arm_ext_v7r = ARM_FEATURE_CORE_LOW (ARM_EXT_V7R);

 #ifdef OBJ_ELF

-static const arm_feature_set arm_ext_v7m = ARM_FEATURE_CORE_LOW (ARM_EXT_V7M);

+static const arm_feature_set ATTRIBUTE_UNUSED arm_ext_v7m = ARM_FEATURE_CORE_LOW (ARM_EXT_V7M);

 #endif

 static const arm_feature_set arm_ext_v8 = ARM_FEATURE_CORE_LOW (ARM_EXT_V8);

 static const arm_feature_set arm_ext_m =

-  ARM_FEATURE_CORE (ARM_EXT_V6M | ARM_EXT_OS | ARM_EXT_V7M,

+  ARM_FEATURE_CORE (ARM_EXT_V6M | ARM_EXT_V7M,

 		    ARM_EXT2_V8M | ARM_EXT2_V8M_MAIN);

 static const arm_feature_set arm_ext_mp = ARM_FEATURE_CORE_LOW (ARM_EXT_MP);

 static const arm_feature_set arm_ext_sec = ARM_FEATURE_CORE_LOW (ARM_EXT_SEC);

@@ -234,14 +235,16 @@ static const arm_feature_set arm_ext_ras

 /* FP16 instructions.  */

 static const arm_feature_set arm_ext_fp16 =

   ARM_FEATURE_CORE_HIGH (ARM_EXT2_FP16_INST);

+static const arm_feature_set arm_ext_v8_3 =

+  ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_3A);

 static const arm_feature_set arm_arch_any = ARM_ANY;

+#ifdef OBJ_ELF

+static const arm_feature_set fpu_any = FPU_ANY;

+#endif

 static const arm_feature_set arm_arch_full ATTRIBUTE_UNUSED = ARM_FEATURE (-1, -1, -1);

 static const arm_feature_set arm_arch_t2 = ARM_ARCH_THUMB2;

 static const arm_feature_set arm_arch_none = ARM_ARCH_NONE;

-#ifdef OBJ_ELF

-static const arm_feature_set arm_arch_v6m_only = ARM_ARCH_V6M_ONLY;

-#endif

 static const arm_feature_set arm_cext_iwmmxt2 =

   ARM_FEATURE_COPROC (ARM_CEXT_IWMMXT2);

@@ -291,6 +294,8 @@ static const arm_feature_set crc_ext_arm

   ARM_FEATURE_COPROC (CRC_EXT_ARMV8);

 static const arm_feature_set fpu_neon_ext_v8_1 =

   ARM_FEATURE_COPROC (FPU_NEON_EXT_RDMA);

+static const arm_feature_set fpu_neon_ext_dotprod =

+  ARM_FEATURE_COPROC (FPU_NEON_EXT_DOTPROD);

 static int mfloat_abi_opt = -1;

 /* Record user cpu selection for object attributes.  */

@@ -685,9 +690,11 @@ struct asm_opcode

 #define T2_SUBS_PC_LR	0xf3de8f00

 #define DATA_OP_SHIFT	21

+#define SBIT_SHIFT	20

 #define T2_OPCODE_MASK	0xfe1fffff

 #define T2_DATA_OP_SHIFT 21

+#define T2_SBIT_SHIFT	 20

 #define A_COND_MASK         0xf0000000

 #define A_PUSH_POP_OP_MASK  0x0fff0000

@@ -1276,6 +1283,7 @@ arm_reg_alt_syntax (char **ccp, char *st

 	if (*ccp != start && processor <= 15)

 	  return processor;

       }

+      /* Fall through.  */

     case REG_TYPE_MMXWC:

       /* WC includes WCG.  ??? I'm not sure this is true for all

@@ -2705,7 +2713,7 @@ mapping_state (enum mstate state)

 	Some Thumb instructions are alignment-sensitive modulo 4 bytes,

 	but themselves require 2-byte alignment; this applies to some

-	PC- relative forms.  However, these cases will invovle implicit

+	PC- relative forms.  However, these cases will involve implicit

 	literal pool generation or an explicit .align >=2, both of

 	which will cause the section to me marked with sufficient

 	alignment.  Thus, we don't handle those cases here.  */

@@ -3042,7 +3050,7 @@ s_ccs_ref (int unused ATTRIBUTE_UNUSED)

 }

 /*  If name is not NULL, then it is used for marking the beginning of a

-    function, wherease if it is NULL then it means the function end.  */

+    function, whereas if it is NULL then it means the function end.  */

 static void

 asmfunc_debug (const char * name)

 {

@@ -3375,7 +3383,7 @@ tc_start_label_without_colon (void)

 }

 /* Can't use symbol_new here, so have to create a symbol and then at

-   a later date assign it a value. Thats what these functions do.  */

+   a later date assign it a value. That's what these functions do.  */

 static void

 symbol_locate (symbolS *    symbolP,

@@ -4964,9 +4972,13 @@ parse_ifimm_zero (char **in)

   int error_code;

   if (!is_immediate_prefix (**in))

-    return FALSE;

-

-  ++*in;

+    {

+      /* In unified syntax, all prefixes are optional.  */

+      if (!unified_syntax)

+	return FALSE;

+    }

+  else

+    ++*in;

   /* Accept #0x0 as a synonym for #0.  */

   if (strncmp (*in, "0x", 2) == 0)

@@ -6530,6 +6542,8 @@ enum operand_parse_code

   OP_EXPi,	/* same, with optional immediate prefix */

   OP_EXPr,	/* same, with optional relocation suffix */

   OP_HALF,	/* 0 .. 65535 or low/high reloc.  */

+  OP_IROT1,	/* VCADD rotate immediate: 90, 270.  */

+  OP_IROT2,	/* VCMLA rotate immediate: 0, 90, 180, 270.  */

   OP_CPSF,	/* CPS flags */

   OP_ENDI,	/* Endianness specifier */

@@ -6541,7 +6555,7 @@ enum operand_parse_code

   OP_APSR_RR,   /* ARM register or "APSR_nzcv".  */

   OP_RRnpc_I0,	/* ARM register or literal 0 */

-  OP_RR_EXr,	/* ARM register or expression with opt. reloc suff. */

+  OP_RR_EXr,	/* ARM register or expression with opt. reloc stuff. */

   OP_RR_EXi,	/* ARM register or expression with imm prefix */

   OP_RF_IF,	/* FPA register or immediate */

   OP_RIWR_RIWC, /* iWMMXt R or C reg */

@@ -7178,8 +7192,14 @@ parse_operands (char *str, const unsigne

 	    {

 	      if (inst.operands[i].reg == REG_PC)

 		inst.error = BAD_PC;

-	      else if (inst.operands[i].reg == REG_SP)

-		inst.error = BAD_SP;

+	      else if (inst.operands[i].reg == REG_SP

+		       /* The restriction on Rd/Rt/Rt2 on Thumb mode has been

+			  relaxed since ARMv8-A.  */

+		       && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))

+		{

+		  gas_assert (thumb);

+		  inst.error = BAD_SP;

+		}

 	    }

 	  break;

@@ -7277,14 +7297,23 @@ parse_operands (char *str, const unsigne

 /* Reject "bad registers" for Thumb-2 instructions.  Many Thumb-2

    instructions are unpredictable if these registers are used.  This

-   is the BadReg predicate in ARM's Thumb-2 documentation.  */

-#define reject_bad_reg(reg)				\

-  do							\

-   if (reg == REG_SP || reg == REG_PC)			\

-     {							\

-       inst.error = (reg == REG_SP) ? BAD_SP : BAD_PC;	\

-       return;						\

-     }							\

+   is the BadReg predicate in ARM's Thumb-2 documentation.

+

+   Before ARMv8-A, REG_PC and REG_SP were not allowed in quite a few

+   places, while the restriction on REG_SP was relaxed since ARMv8-A.  */

+#define reject_bad_reg(reg)					\

+  do								\

+   if (reg == REG_PC)						\

+     {								\

+       inst.error = BAD_PC;					\

+       return;							\

+     }								\

+   else if (reg == REG_SP					\

+	    && !ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))	\

+     {								\

+       inst.error = BAD_SP;					\

+       return;							\

+     }								\

   while (0)

 /* If REG is R13 (the stack pointer), warn that its use is

@@ -7303,7 +7332,7 @@ parse_operands (char *str, const unsigne

    The only binary encoding difference is the Coprocessor number.  Coprocessor

    9 is used for half-precision calculations or conversions.  The format of the

-   instruction is the same as the equivalent Coprocessor 10 instuction that

+   instruction is the same as the equivalent Coprocessor 10 instruction that

    exists for Single-Precision operation.  */

 static void

@@ -7426,6 +7455,24 @@ encode_arm_vfp_reg (int reg, enum vfp_re

 static void

 encode_arm_shift (int i)

 {

+  /* Register-shifted register.  */

+  if (inst.operands[i].immisreg)

+    {

+      int op_index;

+      for (op_index = 0; op_index <= i; ++op_index)

+	{

+	  /* Check the operand only when it's presented.  In pre-UAL syntax,

+	     if the destination register is the same as the first operand, two

+	     register form of the instruction can be used.  */

+	  if (inst.operands[op_index].present && inst.operands[op_index].isreg

+	      && inst.operands[op_index].reg == REG_PC)

+	    as_warn (UNPRED_REG ("r15"));

+	}

+

+      if (inst.operands[i].imm == REG_PC)

+	as_warn (UNPRED_REG ("r15"));

+    }

+

   if (inst.operands[i].shift_kind == SHIFT_RRX)

     inst.instruction |= SHIFT_ROR << 5;

   else

@@ -7930,17 +7977,13 @@ move_or_literal_pool (int i, enum lit_ty

 	{

 	  if (thumb_p)

 	    {

-	      /* This can be encoded only for a low register.  */

-	      if ((v & ~0xFF) == 0 && (inst.operands[i].reg < 8))

-		{

-		  /* This can be done with a mov(1) instruction.  */

-		  inst.instruction = T_OPCODE_MOV_I8 | (inst.operands[i].reg << 8);

-		  inst.instruction |= v;

-		  return TRUE;

-		}

+	      /* LDR should not use lead in a flag-setting instruction being

+		 chosen so we do not check whether movs can be used.  */

-	      if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2)

+	      if ((ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2)

 		  || ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6t2_v8m))

+		  && inst.operands[i].reg != 13

+		  && inst.operands[i].reg != 15)

 		{

 		  /* Check if on thumb2 it can be done with a mov.w, mvn or

 		     movw instruction.  */

@@ -8326,6 +8369,12 @@ do_adr (void)

   inst.reloc.type = BFD_RELOC_ARM_IMMEDIATE;

   inst.reloc.pc_rel = 1;

   inst.reloc.exp.X_add_number -= 8;

+

+  if (inst.reloc.exp.X_op == O_symbol

+      && inst.reloc.exp.X_add_symbol != NULL

+      && S_IS_DEFINED (inst.reloc.exp.X_add_symbol)

+      && THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol))

+    inst.reloc.exp.X_add_number += 1;  

 }

 /* This is a pseudo-op of the form "adrl rd, label" to be converted

@@ -8344,6 +8393,12 @@ do_adrl (void)

   inst.reloc.pc_rel	       = 1;

   inst.size		       = INSN_SIZE * 2;

   inst.reloc.exp.X_add_number -= 8;

+

+  if (inst.reloc.exp.X_op == O_symbol

+      && inst.reloc.exp.X_add_symbol != NULL

+      && S_IS_DEFINED (inst.reloc.exp.X_add_symbol)

+      && THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol))

+    inst.reloc.exp.X_add_number += 1;  

 }

 static void

@@ -8622,7 +8677,7 @@ do_co_reg (void)

 	  || inst.instruction == 0xfe000010)

 	/* MCR, MCR2  */

 	reject_bad_reg (Rd);

-      else

+      else if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))

 	/* MRC, MRC2  */

 	constraint (Rd == REG_SP, BAD_SP);

     }

@@ -8691,6 +8746,14 @@ do_co_reg2c (void)

       constraint (Rn == REG_PC, BAD_PC);

     }

+  /* Only check the MRRC{2} variants.  */

+  if ((inst.instruction & 0x0FF00000) == 0x0C500000)

+    {

+       /* If Rd == Rn, error that the operation is

+	  unpredictable (example MRRC p3,#1,r1,r1,c4).  */

+       constraint (Rd == Rn, BAD_OVERLAP);

+    }

+

   inst.instruction |= inst.operands[0].reg << 8;

   inst.instruction |= inst.operands[1].imm << 4;

   inst.instruction |= Rd << 12;

@@ -8916,7 +8979,7 @@ check_ldr_r15_aligned (void)

 	      && (inst.operands[0].reg == REG_PC

 	      && inst.operands[1].reg == REG_PC

 	      && (inst.reloc.exp.X_add_number & 0x3)),

-	      _("ldr to register 15 must be 4-byte alligned"));

+	      _("ldr to register 15 must be 4-byte aligned"));

 }

 static void

@@ -9025,9 +9088,9 @@ do_mov16 (void)

   top = (inst.instruction & 0x00400000) != 0;

   constraint (top && inst.reloc.type == BFD_RELOC_ARM_MOVW,

-	      _(":lower16: not allowed this instruction"));

+	      _(":lower16: not allowed in this instruction"));

   constraint (!top && inst.reloc.type == BFD_RELOC_ARM_MOVT,

-	      _(":upper16: not allowed instruction"));

+	      _(":upper16: not allowed in this instruction"));

   inst.instruction |= inst.operands[0].reg << 12;

   if (inst.reloc.type == BFD_RELOC_UNUSED)

     {

@@ -9079,6 +9142,11 @@ do_vmrs (void)

       return;

     }

+  /* MVFR2 is only valid at ARMv8-A.  */

+  if (inst.operands[1].reg == 5)

+    constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),

+		_(BAD_FPU));

+

   /* APSR_ sets isvec. All other refs to PC are illegal.  */

   if (!inst.operands[0].isvec && Rt == REG_PC)

     {

@@ -9105,6 +9173,11 @@ do_vmsr (void)

       return;

     }

+  /* MVFR2 is only valid for ARMv8-A.  */

+  if (inst.operands[0].reg == 5)

+    constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),

+		_(BAD_FPU));

+

   /* If we get through parsing the register name, we just insert the number

      generated into the instruction without further validation.  */

   inst.instruction |= (inst.operands[0].reg << 16);

@@ -10453,7 +10526,7 @@ do_t_add_sub_w (void)

 }

 /* Parse an add or subtract instruction.  We get here with inst.instruction

-   equalling any of THUMB_OPCODE_add, adds, sub, or subs.  */

+   equaling any of THUMB_OPCODE_add, adds, sub, or subs.  */

 static void

 do_t_add_sub (void)

@@ -10484,7 +10557,8 @@ do_t_add_sub (void)

 	{

 	  int add;

-	  constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);

+	  if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))

+	    constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);

 	  add = (inst.instruction == T_MNEM_add

 		 || inst.instruction == T_MNEM_adds);

@@ -10608,7 +10682,8 @@ do_t_add_sub (void)

 	    }

 	  constraint (Rd == REG_PC, BAD_PC);

-	  constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);

+	  if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))

+	    constraint (Rd == REG_SP && Rs != REG_SP, BAD_SP);

 	  constraint (Rs == REG_PC, BAD_PC);

 	  reject_bad_reg (Rn);

@@ -10701,9 +10776,14 @@ do_t_adr (void)

       inst.reloc.type = BFD_RELOC_ARM_THUMB_ADD;

       inst.reloc.exp.X_add_number -= 4; /* PC relative adjust.  */

       inst.reloc.pc_rel = 1;

-

       inst.instruction |= Rd << 4;

     }

+

+  if (inst.reloc.exp.X_op == O_symbol

+      && inst.reloc.exp.X_add_symbol != NULL

+      && S_IS_DEFINED (inst.reloc.exp.X_add_symbol)

+      && THUMB_IS_FUNC (inst.reloc.exp.X_add_symbol))

+    inst.reloc.exp.X_add_number += 1;

 }

 /* Arithmetic instructions for which there is just one 16-bit

@@ -11856,7 +11936,8 @@ do_t_mov_cmp (void)

 		  /* This is mov.w.  */

 		  constraint (Rn == REG_PC, BAD_PC);

 		  constraint (Rm == REG_PC, BAD_PC);

-		  constraint (Rn == REG_SP && Rm == REG_SP, BAD_SP);

+		  if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))

+		    constraint (Rn == REG_SP && Rm == REG_SP, BAD_SP);

 		}

 	    }

 	  else

@@ -12082,12 +12163,12 @@ do_t_mov16 (void)

   top = (inst.instruction & 0x00800000) != 0;

   if (inst.reloc.type == BFD_RELOC_ARM_MOVW)

     {

-      constraint (top, _(":lower16: not allowed this instruction"));

+      constraint (top, _(":lower16: not allowed in this instruction"));

       inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVW;

     }

   else if (inst.reloc.type == BFD_RELOC_ARM_MOVT)

     {

-      constraint (!top, _(":upper16: not allowed this instruction"));

+      constraint (!top, _(":upper16: not allowed in this instruction"));

       inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVT;

     }

@@ -13049,17 +13130,6 @@ do_t_sxth (void)

 static void

 do_t_swi (void)

 {

-  /* We have to do the following check manually as ARM_EXT_OS only applies

-     to ARM_EXT_V6M.  */

-  if (ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v6m))

-    {

-      if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_os)

-	  /* This only applies to the v6m howver, not later architectures.  */

-	  && ! ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v7))

-	as_bad (_("SVC is not permitted on this architecture"));

-      ARM_MERGE_FEATURE_SETS (thumb_arch_used, thumb_arch_used, arm_ext_os);

-    }

-

   inst.reloc.type = BFD_RELOC_ARM_SWI;

 }

@@ -13077,7 +13147,8 @@ do_t_tb (void)

   Rn = inst.operands[0].reg;

   Rm = inst.operands[0].imm;

-  constraint (Rn == REG_SP, BAD_SP);

+  if (!ARM_CPU_HAS_FEATURE (cpu_variant, arm_ext_v8))

+    constraint (Rn == REG_SP, BAD_SP);

   reject_bad_reg (Rm);

   constraint (!half && inst.operands[0].shifted,

@@ -13317,6 +13388,8 @@ NEON_ENC_TAB

   X(3, (D, Q, S), MIXED),		\

   X(4, (D, D, D, I), DOUBLE),		\

   X(4, (Q, Q, Q, I), QUAD),		\

+  X(4, (D, D, S, I), DOUBLE),		\

+  X(4, (Q, Q, S, I), QUAD),		\

   X(2, (F, F), SINGLE),			\

   X(3, (F, F, F), SINGLE),		\

   X(2, (F, I), SINGLE),			\

@@ -14390,6 +14463,11 @@ static void

 do_vfp_nsyn_push (void)

 {

   nsyn_insert_sp ();

+

+  constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16,

+	      _("register list must contain at least 1 and at most 16 "

+		"registers"));

+

   if (inst.operands[1].issingle)

     do_vfp_nsyn_opcode ("fstmdbs");

   else

@@ -14400,6 +14478,11 @@ static void

 do_vfp_nsyn_pop (void)

 {

   nsyn_insert_sp ();

+

+  constraint (inst.operands[1].imm < 1 || inst.operands[1].imm > 16,

+	      _("register list must contain at least 1 and at most 16 "

+		"registers"));

+

   if (inst.operands[1].issingle)

     do_vfp_nsyn_opcode ("fldmias");

   else

@@ -14952,7 +15035,14 @@ do_neon_ceq (void)

    scalars, which are encoded in 5 bits, M : Rm.

    For 16-bit scalars, the register is encoded in Rm[2:0] and the index in

    M:Rm[3], and for 32-bit scalars, the register is encoded in Rm[3:0] and the

-   index in M.  */

+   index in M.

+

+   Dot Product instructions are similar to multiply instructions except elsize

+   should always be 32.

+

+   This function translates SCALAR, which is GAS's internal encoding of indexed

+   scalar register, to raw encoding.  There is also register and index range

+   check based on ELSIZE.  */

 static unsigned

 neon_scalar_for_mul (unsigned scalar, unsigned elsize)

@@ -17220,6 +17310,153 @@ do_vrintm (void)

   do_vrint_1 (neon_cvt_mode_m);

 }

+static unsigned

+neon_scalar_for_vcmla (unsigned opnd, unsigned elsize)

+{

+  unsigned regno = NEON_SCALAR_REG (opnd);

+  unsigned elno = NEON_SCALAR_INDEX (opnd);

+

+  if (elsize == 16 && elno < 2 && regno < 16)

+    return regno | (elno << 4);

+  else if (elsize == 32 && elno == 0)

+    return regno;

+

+  first_error (_("scalar out of range"));

+  return 0;

+}

+

+static void

+do_vcmla (void)

+{

+  constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_armv8),

+	      _(BAD_FPU));

+  constraint (inst.reloc.exp.X_op != O_constant, _("expression too complex"));

+  unsigned rot = inst.reloc.exp.X_add_number;

+  constraint (rot != 0 && rot != 90 && rot != 180 && rot != 270,

+	      _("immediate out of range"));

+  rot /= 90;

+  if (inst.operands[2].isscalar)

+    {

+      enum neon_shape rs = neon_select_shape (NS_DDSI, NS_QQSI, NS_NULL);

+      unsigned size = neon_check_type (3, rs, N_EQK, N_EQK,

+				       N_KEY | N_F16 | N_F32).size;

+      unsigned m = neon_scalar_for_vcmla (inst.operands[2].reg, size);

+      inst.is_neon = 1;

+      inst.instruction = 0xfe000800;

+      inst.instruction |= LOW4 (inst.operands[0].reg) << 12;

+      inst.instruction |= HI1 (inst.operands[0].reg) << 22;

+      inst.instruction |= LOW4 (inst.operands[1].reg) << 16;

+      inst.instruction |= HI1 (inst.operands[1].reg) << 7;

+      inst.instruction |= LOW4 (m);

+      inst.instruction |= HI1 (m) << 5;

+      inst.instruction |= neon_quad (rs) << 6;

+      inst.instruction |= rot << 20;

+      inst.instruction |= (size == 32) << 23;

+    }

+  else

+    {

+      enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL);

+      unsigned size = neon_check_type (3, rs, N_EQK, N_EQK,

+				       N_KEY | N_F16 | N_F32).size;

+      neon_three_same (neon_quad (rs), 0, -1);

+      inst.instruction &= 0x00ffffff; /* Undo neon_dp_fixup.  */

+      inst.instruction |= 0xfc200800;

+      inst.instruction |= rot << 23;

+      inst.instruction |= (size == 32) << 20;

+    }

+}

+

+static void

+do_vcadd (void)

+{

+  constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_armv8),

+	      _(BAD_FPU));

+  constraint (inst.reloc.exp.X_op != O_constant, _("expression too complex"));

+  unsigned rot = inst.reloc.exp.X_add_number;

+  constraint (rot != 90 && rot != 270, _("immediate out of range"));

+  enum neon_shape rs = neon_select_shape (NS_DDDI, NS_QQQI, NS_NULL);

+  unsigned size = neon_check_type (3, rs, N_EQK, N_EQK,

+				   N_KEY | N_F16 | N_F32).size;

+  neon_three_same (neon_quad (rs), 0, -1);

+  inst.instruction &= 0x00ffffff; /* Undo neon_dp_fixup.  */

+  inst.instruction |= 0xfc800800;

+  inst.instruction |= (rot == 270) << 24;

+  inst.instruction |= (size == 32) << 20;

+}

+

+/* Dot Product instructions encoding support.  */

+

+static void

+do_neon_dotproduct (int unsigned_p)

+{

+  enum neon_shape rs;

+  unsigned scalar_oprd2 = 0;

+  int high8;

+

+  if (inst.cond != COND_ALWAYS)

+    as_warn (_("Dot Product instructions cannot be conditional,  the behaviour "

+	       "is UNPREDICTABLE"));

+

+  constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_armv8),

+	      _(BAD_FPU));

+

+  /* Dot Product instructions are in three-same D/Q register format or the third

+     operand can be a scalar index register.  */

+  if (inst.operands[2].isscalar)

+    {

+      scalar_oprd2 = neon_scalar_for_mul (inst.operands[2].reg, 32);

+      high8 = 0xfe000000;

+      rs = neon_select_shape (NS_DDS, NS_QQS, NS_NULL);

+    }

+  else

+    {

+      high8 = 0xfc000000;

+      rs = neon_select_shape (NS_DDD, NS_QQQ, NS_NULL);

+    }

+

+  if (unsigned_p)

+    neon_check_type (3, rs, N_EQK, N_EQK, N_KEY | N_U8);

+  else

+    neon_check_type (3, rs, N_EQK, N_EQK, N_KEY | N_S8);

+

+  /* The "U" bit in traditional Three Same encoding is fixed to 0 for Dot

+     Product instruction, so we pass 0 as the "ubit" parameter.  And the

+     "Size" field are fixed to 0x2, so we pass 32 as the "size" parameter.  */

+  neon_three_same (neon_quad (rs), 0, 32);

+

+  /* Undo neon_dp_fixup.  Dot Product instructions are using a slightly

+     different NEON three-same encoding.  */

+  inst.instruction &= 0x00ffffff;

+  inst.instruction |= high8;

+  /* Encode 'U' bit which indicates signedness.  */

+  inst.instruction |= (unsigned_p ? 1 : 0) << 4;

+  /* Re-encode operand2 if it's indexed scalar operand.  What has been encoded

+     from inst.operand[2].reg in neon_three_same is GAS's internal encoding, not

+     the instruction encoding.  */

+  if (inst.operands[2].isscalar)

+    {

+      inst.instruction &= 0xffffffd0;

+      inst.instruction |= LOW4 (scalar_oprd2);

+      inst.instruction |= HI1 (scalar_oprd2) << 5;

+    }

+}

+

+/* Dot Product instructions for signed integer.  */

+

+static void

+do_neon_dotproduct_s (void)

+{

+  return do_neon_dotproduct (0);

+}

+

+/* Dot Product instructions for unsigned integer.  */

+

+static void

+do_neon_dotproduct_u (void)

+{

+  return do_neon_dotproduct (1);

+}

+

 /* Crypto v1 instructions.  */

 static void

 do_crypto_2op_1 (unsigned elttype, int op)

@@ -17401,6 +17638,16 @@ do_crc32cw (void)

   do_crc32_1 (1, 2);

 }

+static void

+do_vjcvt (void)

+{

+  constraint (!ARM_CPU_HAS_FEATURE (cpu_variant, fpu_vfp_ext_armv8),

+	      _(BAD_FPU));

+  neon_check_type (2, NS_FD, N_S32, N_F64);

+  do_vfp_sp_dp_cvt ();

+  do_vfp_cond_or_thumb ();

+}

+

 /* Overall per-instruction processing.	*/

@@ -17755,7 +18002,7 @@ opcode_lookup (char **str)

 	case OT_odd_infix_unc:

 	  if (!unified_syntax)

 	    return 0;

-	  /* else fall through */

+	  /* Fall through.  */

 	case OT_csuffix:

 	case OT_csuffixF:

@@ -17878,7 +18125,7 @@ now_it_add_mask (int cond)

      set_it_insn_type_last ()           ditto

      in_it_block ()                     ditto

      it_fsm_post_encode ()              from md_assemble ()

-     force_automatic_it_block_close ()  from label habdling functions

+     force_automatic_it_block_close ()  from label handling functions

    Rationale:

      1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),

@@ -17911,7 +18158,7 @@ now_it_add_mask (int cond)

 	for covering other cases.

 	Calling handle_it_state () may not transition the IT block state to

-	OUTSIDE_IT_BLOCK immediatelly, since the (current) state could be

+	OUTSIDE_IT_BLOCK immediately, since the (current) state could be

 	still queried. Instead, if the FSM determines that the state should

 	be transitioned to OUTSIDE_IT_BLOCK, a flag is marked to be closed

 	after the tencode () function: that's what it_fsm_post_encode () does.

@@ -18002,7 +18249,7 @@ handle_it_state (void)

       switch (inst.it_insn_type)

 	{

 	case OUTSIDE_IT_INSN:

-	  /* The closure of the block shall happen immediatelly,

+	  /* The closure of the block shall happen immediately,

 	     so any in_it_block () call reports the block as closed.  */

 	  force_automatic_it_block_close ();

 	  break;

@@ -18236,6 +18483,13 @@ t32_insn_ok (arm_feature_set arch, const

       && opcode->tencode == do_t_branch)

     return TRUE;

+  /* MOV accepts T1/T3 encodings under Baseline, T3 encoding is 32bit.  */

+  if (ARM_CPU_HAS_FEATURE (arch, arm_ext_v8m)

+      && opcode->tencode == do_t_mov_cmp

+      /* Make sure CMP instruction is not affected.  */

+      && opcode->aencode == do_mov)

+    return TRUE;

+

   /* Wide instruction variants of all instructions with narrow *and* wide

      variants become available with ARMv6t2.  Other opcodes are either

      narrow-only or wide-only and are thus available if OPCODE is valid.  */

@@ -18296,7 +18550,10 @@ md_assemble (char *str)

 	  || (thumb_mode == 1

 	      && !ARM_CPU_HAS_FEATURE (variant, *opcode->tvariant)))