|
|
f55871 |
diff -cp ../binutils-2.23.52.0.1.orig/gas/doc/c-arc.texi gas/doc/c-arc.texi
|
|
|
f55871 |
*** ../binutils-2.23.52.0.1.orig/gas/doc/c-arc.texi 2013-03-04 08:25:32.051931944 +0000
|
|
|
f55871 |
--- gas/doc/c-arc.texi 2013-03-04 08:26:19.234930452 +0000
|
|
|
f55871 |
*************** The extension instructions are not macro
|
|
|
f55871 |
*** 220,226 ****
|
|
|
f55871 |
encodings for use of these instructions according to the specification
|
|
|
f55871 |
by the user. The parameters are:
|
|
|
f55871 |
|
|
|
f55871 |
! @table @bullet
|
|
|
f55871 |
@item @var{name}
|
|
|
f55871 |
Name of the extension instruction
|
|
|
f55871 |
|
|
|
f55871 |
--- 220,226 ----
|
|
|
f55871 |
encodings for use of these instructions according to the specification
|
|
|
f55871 |
by the user. The parameters are:
|
|
|
f55871 |
|
|
|
f55871 |
! @table @code
|
|
|
f55871 |
@item @var{name}
|
|
|
f55871 |
Name of the extension instruction
|
|
|
f55871 |
|
|
|
f55871 |
diff -cp ../binutils-2.23.52.0.1.orig/gas/doc/c-arm.texi gas/doc/c-arm.texi
|
|
|
f55871 |
*** ../binutils-2.23.52.0.1.orig/gas/doc/c-arm.texi 2013-03-04 08:25:32.039931945 +0000
|
|
|
f55871 |
--- gas/doc/c-arm.texi 2013-03-04 08:27:37.462927978 +0000
|
|
|
f55871 |
*************** ARM and THUMB instructions had their own
|
|
|
f55871 |
*** 390,418 ****
|
|
|
f55871 |
@code{unified} syntax, which can be selected via the @code{.syntax}
|
|
|
f55871 |
directive, and has the following main features:
|
|
|
f55871 |
|
|
|
f55871 |
! @table @bullet
|
|
|
f55871 |
! @item
|
|
|
f55871 |
Immediate operands do not require a @code{#} prefix.
|
|
|
f55871 |
|
|
|
f55871 |
! @item
|
|
|
f55871 |
The @code{IT} instruction may appear, and if it does it is validated
|
|
|
f55871 |
against subsequent conditional affixes. In ARM mode it does not
|
|
|
f55871 |
generate machine code, in THUMB mode it does.
|
|
|
f55871 |
|
|
|
f55871 |
! @item
|
|
|
f55871 |
For ARM instructions the conditional affixes always appear at the end
|
|
|
f55871 |
of the instruction. For THUMB instructions conditional affixes can be
|
|
|
f55871 |
used, but only inside the scope of an @code{IT} instruction.
|
|
|
f55871 |
|
|
|
f55871 |
! @item
|
|
|
f55871 |
All of the instructions new to the V6T2 architecture (and later) are
|
|
|
f55871 |
available. (Only a few such instructions can be written in the
|
|
|
f55871 |
@code{divided} syntax).
|
|
|
f55871 |
|
|
|
f55871 |
! @item
|
|
|
f55871 |
The @code{.N} and @code{.W} suffixes are recognized and honored.
|
|
|
f55871 |
|
|
|
f55871 |
! @item
|
|
|
f55871 |
All instructions set the flags if and only if they have an @code{s}
|
|
|
f55871 |
affix.
|
|
|
f55871 |
@end table
|
|
|
f55871 |
--- 390,418 ----
|
|
|
f55871 |
@code{unified} syntax, which can be selected via the @code{.syntax}
|
|
|
f55871 |
directive, and has the following main features:
|
|
|
f55871 |
|
|
|
f55871 |
! @table @code
|
|
|
f55871 |
! @item 1
|
|
|
f55871 |
Immediate operands do not require a @code{#} prefix.
|
|
|
f55871 |
|
|
|
f55871 |
! @item 2
|
|
|
f55871 |
The @code{IT} instruction may appear, and if it does it is validated
|
|
|
f55871 |
against subsequent conditional affixes. In ARM mode it does not
|
|
|
f55871 |
generate machine code, in THUMB mode it does.
|
|
|
f55871 |
|
|
|
f55871 |
! @item 3
|
|
|
f55871 |
For ARM instructions the conditional affixes always appear at the end
|
|
|
f55871 |
of the instruction. For THUMB instructions conditional affixes can be
|
|
|
f55871 |
used, but only inside the scope of an @code{IT} instruction.
|
|
|
f55871 |
|
|
|
f55871 |
! @item 4
|
|
|
f55871 |
All of the instructions new to the V6T2 architecture (and later) are
|
|
|
f55871 |
available. (Only a few such instructions can be written in the
|
|
|
f55871 |
@code{divided} syntax).
|
|
|
f55871 |
|
|
|
f55871 |
! @item 5
|
|
|
f55871 |
The @code{.N} and @code{.W} suffixes are recognized and honored.
|
|
|
f55871 |
|
|
|
f55871 |
! @item 6
|
|
|
f55871 |
All instructions set the flags if and only if they have an @code{s}
|
|
|
f55871 |
affix.
|
|
|
f55871 |
@end table
|
|
|
f55871 |
*************** Either @samp{#} or @samp{$} can be used
|
|
|
f55871 |
*** 451,478 ****
|
|
|
f55871 |
@cindex register names, ARM
|
|
|
f55871 |
*TODO* Explain about ARM register naming, and the predefined names.
|
|
|
f55871 |
|
|
|
f55871 |
- @node ARM-Neon-Alignment
|
|
|
f55871 |
- @subsection NEON Alignment Specifiers
|
|
|
f55871 |
-
|
|
|
f55871 |
- @cindex alignment for NEON instructions
|
|
|
f55871 |
- Some NEON load/store instructions allow an optional address
|
|
|
f55871 |
- alignment qualifier.
|
|
|
f55871 |
- The ARM documentation specifies that this is indicated by
|
|
|
f55871 |
- @samp{@@ @var{align}}. However GAS already interprets
|
|
|
f55871 |
- the @samp{@@} character as a "line comment" start,
|
|
|
f55871 |
- so @samp{: @var{align}} is used instead. For example:
|
|
|
f55871 |
-
|
|
|
f55871 |
- @smallexample
|
|
|
f55871 |
- vld1.8 @{q0@}, [r0, :128]
|
|
|
f55871 |
- @end smallexample
|
|
|
f55871 |
-
|
|
|
f55871 |
- @node ARM Floating Point
|
|
|
f55871 |
- @section Floating Point
|
|
|
f55871 |
-
|
|
|
f55871 |
- @cindex floating point, ARM (@sc{ieee})
|
|
|
f55871 |
- @cindex ARM floating point (@sc{ieee})
|
|
|
f55871 |
- The ARM family uses @sc{ieee} floating-point numbers.
|
|
|
f55871 |
-
|
|
|
f55871 |
@node ARM-Relocations
|
|
|
f55871 |
@subsection ARM relocation generation
|
|
|
f55871 |
|
|
|
f55871 |
--- 451,456 ----
|
|
|
f55871 |
*************** respectively. For example to load the 3
|
|
|
f55871 |
*** 519,524 ****
|
|
|
f55871 |
--- 497,524 ----
|
|
|
f55871 |
MOVT r0, #:upper16:foo
|
|
|
f55871 |
@end smallexample
|
|
|
f55871 |
|
|
|
f55871 |
+ @node ARM-Neon-Alignment
|
|
|
f55871 |
+ @subsection NEON Alignment Specifiers
|
|
|
f55871 |
+
|
|
|
f55871 |
+ @cindex alignment for NEON instructions
|
|
|
f55871 |
+ Some NEON load/store instructions allow an optional address
|
|
|
f55871 |
+ alignment qualifier.
|
|
|
f55871 |
+ The ARM documentation specifies that this is indicated by
|
|
|
f55871 |
+ @samp{@@ @var{align}}. However GAS already interprets
|
|
|
f55871 |
+ the @samp{@@} character as a "line comment" start,
|
|
|
f55871 |
+ so @samp{: @var{align}} is used instead. For example:
|
|
|
f55871 |
+
|
|
|
f55871 |
+ @smallexample
|
|
|
f55871 |
+ vld1.8 @{q0@}, [r0, :128]
|
|
|
f55871 |
+ @end smallexample
|
|
|
f55871 |
+
|
|
|
f55871 |
+ @node ARM Floating Point
|
|
|
f55871 |
+ @section Floating Point
|
|
|
f55871 |
+
|
|
|
f55871 |
+ @cindex floating point, ARM (@sc{ieee})
|
|
|
f55871 |
+ @cindex ARM floating point (@sc{ieee})
|
|
|
f55871 |
+ The ARM family uses @sc{ieee} floating-point numbers.
|
|
|
f55871 |
+
|
|
|
f55871 |
@node ARM Directives
|
|
|
f55871 |
@section ARM Machine Directives
|
|
|
f55871 |
|
|
|
f55871 |
diff -cp ../binutils-2.23.52.0.1.orig/gas/doc/c-cr16.texi gas/doc/c-cr16.texi
|
|
|
f55871 |
*** ../binutils-2.23.52.0.1.orig/gas/doc/c-cr16.texi 2013-03-04 08:25:32.086931943 +0000
|
|
|
f55871 |
--- gas/doc/c-cr16.texi 2013-03-04 08:28:09.304926971 +0000
|
|
|
f55871 |
*************** Operand expression type qualifier is an
|
|
|
f55871 |
*** 44,69 ****
|
|
|
f55871 |
CR16 target operand qualifiers and its size (in bits):
|
|
|
f55871 |
|
|
|
f55871 |
@table @samp
|
|
|
f55871 |
! @item Immediate Operand
|
|
|
f55871 |
! - s ---- 4 bits
|
|
|
f55871 |
! @item
|
|
|
f55871 |
! - m ---- 16 bits, for movb and movw instructions.
|
|
|
f55871 |
! @item
|
|
|
f55871 |
! - m ---- 20 bits, movd instructions.
|
|
|
f55871 |
! @item
|
|
|
f55871 |
! - l ---- 32 bits
|
|
|
f55871 |
!
|
|
|
f55871 |
! @item Absolute Operand
|
|
|
f55871 |
! - s ---- Illegal specifier for this operand.
|
|
|
f55871 |
! @item
|
|
|
f55871 |
! - m ---- 20 bits, movd instructions.
|
|
|
f55871 |
!
|
|
|
f55871 |
! @item Displacement Operand
|
|
|
f55871 |
! - s ---- 8 bits
|
|
|
f55871 |
! @item
|
|
|
f55871 |
! - m ---- 16 bits
|
|
|
f55871 |
! @item
|
|
|
f55871 |
! - l ---- 24 bits
|
|
|
f55871 |
@end table
|
|
|
f55871 |
|
|
|
f55871 |
For example:
|
|
|
f55871 |
--- 44,76 ----
|
|
|
f55871 |
CR16 target operand qualifiers and its size (in bits):
|
|
|
f55871 |
|
|
|
f55871 |
@table @samp
|
|
|
f55871 |
! @item Immediate Operand: s
|
|
|
f55871 |
! 4 bits.
|
|
|
f55871 |
!
|
|
|
f55871 |
! @item Immediate Operand: m
|
|
|
f55871 |
! 16 bits, for movb and movw instructions.
|
|
|
f55871 |
!
|
|
|
f55871 |
! @item Immediate Operand: m
|
|
|
f55871 |
! 20 bits, movd instructions.
|
|
|
f55871 |
!
|
|
|
f55871 |
! @item Immediate Operand: l
|
|
|
f55871 |
! 32 bits.
|
|
|
f55871 |
!
|
|
|
f55871 |
! @item Absolute Operand: s
|
|
|
f55871 |
! Illegal specifier for this operand.
|
|
|
f55871 |
!
|
|
|
f55871 |
! @item Absolute Operand: m
|
|
|
f55871 |
! 20 bits, movd instructions.
|
|
|
f55871 |
!
|
|
|
f55871 |
! @item Displacement Operand: s
|
|
|
f55871 |
! 8 bits.
|
|
|
f55871 |
!
|
|
|
f55871 |
! @item Displacement Operand: m
|
|
|
f55871 |
! 16 bits.
|
|
|
f55871 |
!
|
|
|
f55871 |
! @item Displacement Operand: l
|
|
|
f55871 |
! 24 bits.
|
|
|
f55871 |
!
|
|
|
f55871 |
@end table
|
|
|
f55871 |
|
|
|
f55871 |
For example:
|
|
|
f55871 |
diff -cp ../binutils-2.23.52.0.1.orig/gas/doc/c-tic54x.texi gas/doc/c-tic54x.texi
|
|
|
f55871 |
*** ../binutils-2.23.52.0.1.orig/gas/doc/c-tic54x.texi 2013-03-04 08:25:32.035931945 +0000
|
|
|
f55871 |
--- gas/doc/c-tic54x.texi 2013-03-04 08:28:38.186926057 +0000
|
|
|
f55871 |
*************** In this example, x is replaced with SYM2
|
|
|
f55871 |
*** 109,115 ****
|
|
|
f55871 |
is replaced with x. At this point, x has already been encountered
|
|
|
f55871 |
and the substitution stops.
|
|
|
f55871 |
|
|
|
f55871 |
! @smallexample @code
|
|
|
f55871 |
.asg "x",SYM1
|
|
|
f55871 |
.asg "SYM1",SYM2
|
|
|
f55871 |
.asg "SYM2",x
|
|
|
f55871 |
--- 109,115 ----
|
|
|
f55871 |
is replaced with x. At this point, x has already been encountered
|
|
|
f55871 |
and the substitution stops.
|
|
|
f55871 |
|
|
|
f55871 |
! @smallexample
|
|
|
f55871 |
.asg "x",SYM1
|
|
|
f55871 |
.asg "SYM1",SYM2
|
|
|
f55871 |
.asg "SYM2",x
|
|
|
f55871 |
*************** Substitution may be forced in situations
|
|
|
f55871 |
*** 126,139 ****
|
|
|
f55871 |
ambiguous by placing colons on either side of the subsym. The following
|
|
|
f55871 |
code:
|
|
|
f55871 |
|
|
|
f55871 |
! @smallexample @code
|
|
|
f55871 |
.eval "10",x
|
|
|
f55871 |
LAB:X: add #x, a
|
|
|
f55871 |
@end smallexample
|
|
|
f55871 |
|
|
|
f55871 |
When assembled becomes:
|
|
|
f55871 |
|
|
|
f55871 |
! @smallexample @code
|
|
|
f55871 |
LAB10 add #10, a
|
|
|
f55871 |
@end smallexample
|
|
|
f55871 |
|
|
|
f55871 |
--- 126,139 ----
|
|
|
f55871 |
ambiguous by placing colons on either side of the subsym. The following
|
|
|
f55871 |
code:
|
|
|
f55871 |
|
|
|
f55871 |
! @smallexample
|
|
|
f55871 |
.eval "10",x
|
|
|
f55871 |
LAB:X: add #x, a
|
|
|
f55871 |
@end smallexample
|
|
|
f55871 |
|
|
|
f55871 |
When assembled becomes:
|
|
|
f55871 |
|
|
|
f55871 |
! @smallexample
|
|
|
f55871 |
LAB10 add #10, a
|
|
|
f55871 |
@end smallexample
|
|
|
f55871 |
|
|
|
f55871 |
*************** The @code{LDX} pseudo-op is provided for
|
|
|
f55871 |
*** 309,315 ****
|
|
|
f55871 |
of a label or address. For example, if an address @code{_label} resides
|
|
|
f55871 |
in extended program memory, the value of @code{_label} may be loaded as
|
|
|
f55871 |
follows:
|
|
|
f55871 |
! @smallexample @code
|
|
|
f55871 |
ldx #_label,16,a ; loads extended bits of _label
|
|
|
f55871 |
or #_label,a ; loads lower 16 bits of _label
|
|
|
f55871 |
bacc a ; full address is in accumulator A
|
|
|
f55871 |
--- 309,315 ----
|
|
|
f55871 |
of a label or address. For example, if an address @code{_label} resides
|
|
|
f55871 |
in extended program memory, the value of @code{_label} may be loaded as
|
|
|
f55871 |
follows:
|
|
|
f55871 |
! @smallexample
|
|
|
f55871 |
ldx #_label,16,a ; loads extended bits of _label
|
|
|
f55871 |
or #_label,a ; loads lower 16 bits of _label
|
|
|
f55871 |
bacc a ; full address is in accumulator A
|