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From a047703bdb55821e77d9a89f484e98e5293dc5bf Mon Sep 17 00:00:00 2001
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From: "plai@redhat.com" <plai@redhat.com>
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Date: Mon, 23 Sep 2019 20:40:24 +0200
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Subject: [PATCH 08/12] x86: define a new MSR based feature word --
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FEATURE_WORDS_ARCH_CAPABILITIES
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RH-Author: plai@redhat.com
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Message-id: <1569271227-28026-8-git-send-email-plai@redhat.com>
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Patchwork-id: 90860
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O-Subject: [RHEL7.8 qemu-kvm PATCH v6 07/10] x86: define a new MSR based feature word -- FEATURE_WORDS_ARCH_CAPABILITIES
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Bugzilla: 1709971
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RH-Acked-by: Eduardo Habkost <ehabkost@redhat.com>
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RH-Acked-by: Bandan Das <bsd@redhat.com>
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RH-Acked-by: Miroslav Rezanina <mrezanin@redhat.com>
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From: Robert Hoo <robert.hu@linux.intel.com>
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Note RSBA is specially treated -- no matter host support it or not, qemu
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pretends it is supported.
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Signed-off-by: Robert Hoo <robert.hu@linux.intel.com>
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Message-Id: <1539578845-37944-4-git-send-email-robert.hu@linux.intel.com>
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[ehabkost: removed automatic enabling of RSBA]
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Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
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Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
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(cherry picked from commit d86f963694df27f11b3681ffd225c9362de1b634)
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Signed-off-by: Paul Lai <plai@redhat.com>
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Resolved Conflicts:
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target/i386/cpu.c
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target/i386/cpu.h
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target/i386/kvm.c
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Signed-off-by: Miroslav Rezanina <mrezanin@redhat.com>
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---
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target-i386/cpu.c | 23 +++++++++++++++++++++++
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target-i386/cpu.h | 8 ++++++++
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target-i386/kvm.c | 10 ++++++++++
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3 files changed, 41 insertions(+)
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diff --git a/target-i386/cpu.c b/target-i386/cpu.c
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index 488634c..24fc000 100644
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--- a/target-i386/cpu.c
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+++ b/target-i386/cpu.c
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@@ -210,6 +210,17 @@ static const char *cpuid_apm_edx_feature_name[] = {
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NULL, NULL, NULL, NULL,
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};
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+static const char *cpuid_arch_capabilities_feature_name[] = {
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+ "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry",
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+ "ssb-no", NULL, NULL, NULL,
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+ NULL, NULL, NULL, NULL,
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+ NULL, NULL, NULL, NULL,
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+ NULL, NULL, NULL, NULL,
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+ NULL, NULL, NULL, NULL,
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+ NULL, NULL, NULL, NULL,
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+ NULL, NULL, NULL, NULL,
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+};
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+
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#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
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#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
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CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
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@@ -392,6 +403,18 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
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.reg = R_EAX,
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},
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},
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+ /*Below are MSR exposed features*/
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+ [FEAT_ARCH_CAPABILITIES] = {
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+ .type = MSR_FEATURE_WORD,
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+ .feat_names = cpuid_arch_capabilities_feature_name,
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+ .msr = {
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+ .index = MSR_IA32_ARCH_CAPABILITIES,
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+ .cpuid_dep = {
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+ FEAT_7_0_EDX,
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+ CPUID_7_0_EDX_ARCH_CAPABILITIES
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+ }
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+ },
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+ },
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};
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typedef struct X86RegisterInfo32 {
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diff --git a/target-i386/cpu.h b/target-i386/cpu.h
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index 0ce479a..5a86b2c 100644
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--- a/target-i386/cpu.h
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+++ b/target-i386/cpu.h
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@@ -416,6 +416,7 @@ typedef enum FeatureWord {
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FEAT_KVM, /* CPUID[4000_0001].EAX (KVM_CPUID_FEATURES) */
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FEAT_SVM, /* CPUID[8000_000A].EDX */
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FEAT_XSAVE, /* CPUID[EAX=0xd,ECX=1].EAX */
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+ FEAT_ARCH_CAPABILITIES,
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FEATURE_WORDS,
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} FeatureWord;
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@@ -636,6 +637,13 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
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#define CPUID_MWAIT_IBE (1U << 1) /* Interrupts can exit capability */
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#define CPUID_MWAIT_EMX (1U << 0) /* enumeration supported */
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+/* MSR Feature Bits */
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+#define MSR_ARCH_CAP_RDCL_NO (1U << 0)
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+#define MSR_ARCH_CAP_IBRS_ALL (1U << 1)
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+#define MSR_ARCH_CAP_RSBA (1U << 2)
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+#define MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY (1U << 3)
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+#define MSR_ARCH_CAP_SSB_NO (1U << 4)
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+
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#ifndef HYPERV_SPINLOCK_NEVER_RETRY
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#define HYPERV_SPINLOCK_NEVER_RETRY 0xFFFFFFFF
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#endif
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diff --git a/target-i386/kvm.c b/target-i386/kvm.c
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index 159ed4c..722cfbc 100644
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--- a/target-i386/kvm.c
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+++ b/target-i386/kvm.c
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@@ -1339,6 +1339,16 @@ static int kvm_put_msrs(X86CPU *cpu, int level)
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kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
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}
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}
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+ /* If host supports feature MSR, write down. */
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+ if (kvm_feature_msrs) {
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+ int i;
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+ for (i = 0; i < kvm_feature_msrs->nmsrs; i++)
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+ if (kvm_feature_msrs->indices[i] == MSR_IA32_ARCH_CAPABILITIES) {
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+ kvm_msr_entry_set(&msrs[n++], MSR_IA32_ARCH_CAPABILITIES,
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+ env->features[FEAT_ARCH_CAPABILITIES]);
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+ break;
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+ }
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+ }
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/*
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* The following MSRs have side effects on the guest or are too heavy
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* for normal writeback. Limit them to reset or full state updates.
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--
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1.8.3.1
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