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From 1d9d6bd6721a92ae161bd7a4e9de202691b90da0 Mon Sep 17 00:00:00 2001
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From: "plai@redhat.com" <plai@redhat.com>
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Date: Tue, 8 May 2018 17:40:48 +0200
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Subject: [PATCH 01/17] x86/cpu: Enable new SSE/AVX/AVX512 cpu features
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RH-Author: plai@redhat.com
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Message-id: <1525801248-24104-1-git-send-email-plai@redhat.com>
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Patchwork-id: 80114
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O-Subject: [RHEL7.6 PATCH BZ 1513686] x86/cpu: Enable new SSE/AVX/AVX512 cpu features
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Bugzilla: 1513686
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RH-Acked-by: Eduardo Habkost <ehabkost@redhat.com>
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RH-Acked-by: Igor Mammedov <imammedo@redhat.com>
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RH-Acked-by: Radim Krcmar <rkrcmar@redhat.com>
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From: Yang Zhong <yang.zhong@intel.com>
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Intel OTC Virt tested.
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Intel IceLake cpu has added new cpu features,AVX512_VBMI2/GFNI/
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VAES/VPCLMULQDQ/AVX512_VNNI/AVX512_BITALG. Those new cpu features
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need expose to guest VM.
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The bit definition:
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CPUID.(EAX=7,ECX=0):ECX[bit 06] AVX512_VBMI2
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CPUID.(EAX=7,ECX=0):ECX[bit 08] GFNI
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CPUID.(EAX=7,ECX=0):ECX[bit 09] VAES
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CPUID.(EAX=7,ECX=0):ECX[bit 10] VPCLMULQDQ
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CPUID.(EAX=7,ECX=0):ECX[bit 11] AVX512_VNNI
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CPUID.(EAX=7,ECX=0):ECX[bit 12] AVX512_BITALG
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The release document ref below link:
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https://software.intel.com/sites/default/files/managed/c5/15/\
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architecture-instruction-set-extensions-programming-reference.pdf
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Signed-off-by: Yang Zhong <yang.zhong@intel.com>
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Message-Id: <1511335676-20797-1-git-send-email-yang.zhong@intel.com>
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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(cherry picked from commit aff9e6e46a343e1404498be4edd03db1112f0950)
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Signed-off-by: Paul Lai <plai@redhat.com>
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Resolved Conflicts:
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target/i386/cpu.c
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target/i386/cpu.h
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changes applied to target-i386/cpu.{c,h}
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Signed-off-by: Miroslav Rezanina <mrezanin@redhat.com>
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---
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target-i386/cpu.c | 6 +++---
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target-i386/cpu.h | 6 ++++++
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2 files changed, 9 insertions(+), 3 deletions(-)
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diff --git a/target-i386/cpu.c b/target-i386/cpu.c
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index 539c202..48a5507 100644
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--- a/target-i386/cpu.c
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+++ b/target-i386/cpu.c
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@@ -156,9 +156,9 @@ static const char *cpuid_7_0_ebx_feature_name[] = {
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static const char *cpuid_7_0_ecx_feature_name[] = {
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NULL, "avx512vbmi", NULL, "pku",
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- "ospke", NULL, NULL, NULL,
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- NULL, NULL, NULL, NULL,
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- NULL, NULL, "avx512-vpopcntdq", NULL,
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+ "ospke", NULL, "avx512vbmi2", NULL,
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+ "gfni", "vaes", "vpclmulqdq", "avx512vnni",
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+ "avx512bitalg", NULL, "avx512-vpopcntdq", NULL,
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NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL,
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diff --git a/target-i386/cpu.h b/target-i386/cpu.h
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index da84443..a781639 100644
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--- a/target-i386/cpu.h
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+++ b/target-i386/cpu.h
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@@ -584,6 +584,12 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
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#define CPUID_7_0_ECX_UMIP (1U << 2)
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#define CPUID_7_0_ECX_PKU (1U << 3)
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#define CPUID_7_0_ECX_OSPKE (1U << 4)
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+#define CPUID_7_0_ECX_VBMI2 (1U << 6) /* Additional VBMI Instrs */
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+#define CPUID_7_0_ECX_GFNI (1U << 8)
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+#define CPUID_7_0_ECX_VAES (1U << 9)
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+#define CPUID_7_0_ECX_VPCLMULQDQ (1U << 10)
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+#define CPUID_7_0_ECX_AVX512VNNI (1U << 11)
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+#define CPUID_7_0_ECX_AVX512BITALG (1U << 12)
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#define CPUID_7_0_ECX_AVX512_VPOPCNTDQ (1U << 14) /* POPCNT for vectors of DW/QW */
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#define CPUID_7_0_ECX_RDPID (1U << 22)
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--
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1.8.3.1
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