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From c3eb11a92f0fa90fe2976c9c5ea59fe8ab862e77 Mon Sep 17 00:00:00 2001
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From: Gerd Hoffmann <kraxel@redhat.com>
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Date: Fri, 29 Apr 2016 07:02:49 +0200
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Subject: [PATCH 4/6] vga: factor out vga register setup
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RH-Author: Gerd Hoffmann <kraxel@redhat.com>
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Message-id: <1461913371-3145-5-git-send-email-kraxel@redhat.com>
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Patchwork-id: 70304
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O-Subject: [virt-devel] [RHEL-7.2.z qemu-kvm PATCH 4/6] vga: factor out vga register setup
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Bugzilla: 1331412
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RH-Acked-by: Miroslav Rezanina <mrezanin@redhat.com>
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RH-Acked-by: Laszlo Ersek <lersek@redhat.com>
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RH-Acked-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
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When enabling vbe mode qemu will setup a bunch of vga registers to make
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sure the vga emulation operates in correct mode for a linear
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framebuffer.  Move that code to a separate function so we can call it
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from other places too.
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Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
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Signed-off-by: Miroslav Rezanina <mrezanin@redhat.com>
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---
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 hw/display/vga.c | 78 ++++++++++++++++++++++++++++++++------------------------
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 1 file changed, 44 insertions(+), 34 deletions(-)
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diff --git a/hw/display/vga.c b/hw/display/vga.c
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index b694a26..4cc0df5 100644
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--- a/hw/display/vga.c
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+++ b/hw/display/vga.c
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@@ -671,6 +671,49 @@ static void vbe_fixup_regs(VGACommonState *s)
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     s->vbe_start_addr  = offset / 4;
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 }
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+/* we initialize the VGA graphic mode */
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+static void vbe_update_vgaregs(VGACommonState *s)
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+{
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+    int h, shift_control;
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+
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+    if (!vbe_enabled(s)) {
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+        /* vbe is turned off -- nothing to do */
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+        return;
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+    }
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+
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+    /* graphic mode + memory map 1 */
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+    s->gr[VGA_GFX_MISC] = (s->gr[VGA_GFX_MISC] & ~0x0c) | 0x04 |
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+        VGA_GR06_GRAPHICS_MODE;
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+    s->cr[VGA_CRTC_MODE] |= 3; /* no CGA modes */
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+    s->cr[VGA_CRTC_OFFSET] = s->vbe_line_offset >> 3;
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+    /* width */
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+    s->cr[VGA_CRTC_H_DISP] =
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+        (s->vbe_regs[VBE_DISPI_INDEX_XRES] >> 3) - 1;
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+    /* height (only meaningful if < 1024) */
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+    h = s->vbe_regs[VBE_DISPI_INDEX_YRES] - 1;
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+    s->cr[VGA_CRTC_V_DISP_END] = h;
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+    s->cr[VGA_CRTC_OVERFLOW] = (s->cr[VGA_CRTC_OVERFLOW] & ~0x42) |
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+        ((h >> 7) & 0x02) | ((h >> 3) & 0x40);
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+    /* line compare to 1023 */
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+    s->cr[VGA_CRTC_LINE_COMPARE] = 0xff;
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+    s->cr[VGA_CRTC_OVERFLOW] |= 0x10;
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+    s->cr[VGA_CRTC_MAX_SCAN] |= 0x40;
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+
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+    if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4) {
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+        shift_control = 0;
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+        s->sr[VGA_SEQ_CLOCK_MODE] &= ~8; /* no double line */
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+    } else {
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+        shift_control = 2;
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+        /* set chain 4 mode */
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+        s->sr[VGA_SEQ_MEMORY_MODE] |= VGA_SR04_CHN_4M;
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+        /* activate all planes */
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+        s->sr[VGA_SEQ_PLANE_WRITE] |= VGA_SR02_ALL_PLANES;
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+    }
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+    s->gr[VGA_GFX_MODE] = (s->gr[VGA_GFX_MODE] & ~0x60) |
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+        (shift_control << 5);
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+    s->cr[VGA_CRTC_MAX_SCAN] &= ~0x9f; /* no double scan */
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+}
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+
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 static uint32_t vbe_ioport_read_index(void *opaque, uint32_t addr)
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 {
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     VGACommonState *s = opaque;
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@@ -757,52 +800,19 @@ void vbe_ioport_write_data(void *opaque, uint32_t addr, uint32_t val)
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         case VBE_DISPI_INDEX_ENABLE:
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             if ((val & VBE_DISPI_ENABLED) &&
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                 !(s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED)) {
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-                int h, shift_control;
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                 s->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] = 0;
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                 s->vbe_regs[VBE_DISPI_INDEX_X_OFFSET] = 0;
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                 s->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET] = 0;
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                 s->vbe_regs[VBE_DISPI_INDEX_ENABLE] |= VBE_DISPI_ENABLED;
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                 vbe_fixup_regs(s);
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+                vbe_update_vgaregs(s);
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                 /* clear the screen */
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                 if (!(val & VBE_DISPI_NOCLEARMEM)) {
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                     memset(s->vram_ptr, 0,
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                            s->vbe_regs[VBE_DISPI_INDEX_YRES] * s->vbe_line_offset);
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                 }
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-
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-                /* we initialize the VGA graphic mode */
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-                /* graphic mode + memory map 1 */
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-                s->gr[VGA_GFX_MISC] = (s->gr[VGA_GFX_MISC] & ~0x0c) | 0x04 |
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-                    VGA_GR06_GRAPHICS_MODE;
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-                s->cr[VGA_CRTC_MODE] |= 3; /* no CGA modes */
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-                s->cr[VGA_CRTC_OFFSET] = s->vbe_line_offset >> 3;
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-                /* width */
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-                s->cr[VGA_CRTC_H_DISP] =
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-                    (s->vbe_regs[VBE_DISPI_INDEX_XRES] >> 3) - 1;
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-                 /* height (only meaningful if < 1024) */
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-                h = s->vbe_regs[VBE_DISPI_INDEX_YRES] - 1;
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-                s->cr[VGA_CRTC_V_DISP_END] = h;
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-                s->cr[VGA_CRTC_OVERFLOW] = (s->cr[VGA_CRTC_OVERFLOW] & ~0x42) |
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-                    ((h >> 7) & 0x02) | ((h >> 3) & 0x40);
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-                /* line compare to 1023 */
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-                s->cr[VGA_CRTC_LINE_COMPARE] = 0xff;
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-                s->cr[VGA_CRTC_OVERFLOW] |= 0x10;
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-                s->cr[VGA_CRTC_MAX_SCAN] |= 0x40;
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-
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-                if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4) {
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-                    shift_control = 0;
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-                    s->sr[VGA_SEQ_CLOCK_MODE] &= ~8; /* no double line */
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-                } else {
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-                    shift_control = 2;
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-                    /* set chain 4 mode */
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-                    s->sr[VGA_SEQ_MEMORY_MODE] |= VGA_SR04_CHN_4M;
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-                    /* activate all planes */
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-                    s->sr[VGA_SEQ_PLANE_WRITE] |= VGA_SR02_ALL_PLANES;
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-                }
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-                s->gr[VGA_GFX_MODE] = (s->gr[VGA_GFX_MODE] & ~0x60) |
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-                    (shift_control << 5);
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-                s->cr[VGA_CRTC_MAX_SCAN] &= ~0x9f; /* no double scan */
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             } else {
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                 s->bank_offset = 0;
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             }
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-- 
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1.8.3.1
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