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Blame SOURCES/kvm-target-ppc-spapr-Add-workaround-option-to-SPAPR_CAP_.patch

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From c1bd7825b1cbe0ff34be196effc7a18992cce269 Mon Sep 17 00:00:00 2001
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From: Sam Bobroff <sbobroff@redhat.com>
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Date: Thu, 29 Aug 2019 05:53:35 +0100
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Subject: [PATCH 02/10] target/ppc/spapr: Add workaround option to
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 SPAPR_CAP_IBS
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RH-Author: Sam Bobroff <sbobroff@redhat.com>
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Message-id: <67946d77e95afc19f2afc5f8dfa4e89335dbb58d.1567057498.git.sbobroff@redhat.com>
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Patchwork-id: 90188
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O-Subject: [RHEL8.1 qemu-kvm BZ1744415 PATCH 1/2] target/ppc/spapr: Add workaround option to SPAPR_CAP_IBS
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Bugzilla: 1744415
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RH-Acked-by: David Gibson <dgibson@redhat.com>
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RH-Acked-by: Laurent Vivier <lvivier@redhat.com>
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RH-Acked-by: Thomas Huth <thuth@redhat.com>
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From: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
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The spapr_cap SPAPR_CAP_IBS is used to indicate the level of capability
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for mitigations for indirect branch speculation. Currently the available
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values are broken (default), fixed-ibs (fixed by serialising indirect
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branches) and fixed-ccd (fixed by diabling the count cache).
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Introduce a new value for this capability denoted workaround, meaning that
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software can work around the issue by flushing the count cache on
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context switch. This option is available if the hypervisor sets the
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H_CPU_BEHAV_FLUSH_COUNT_CACHE flag in the cpu behaviours returned from
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the KVM_PPC_GET_CPU_CHAR ioctl.
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Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
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Message-Id: <20190301031912.28809-1-sjitindarsingh@gmail.com>
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Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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(cherry picked from commit 399b2896d4948a1ec0278d896ea3a561df768d64)
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Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=1744415
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Brew: https://brewweb.engineering.redhat.com/brew/taskinfo?taskID=23229146
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Signed-off-by: Sam Bobroff <sbobroff@redhat.com>
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Testing: Start QEMU with -M cap-ibs=workaround, check guest dmesg
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Signed-off-by: Danilo C. L. de Paula <ddepaula@redhat.com>
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---
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 hw/ppc/spapr_caps.c    | 21 ++++++++++-----------
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 hw/ppc/spapr_hcall.c   |  5 +++++
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 include/hw/ppc/spapr.h |  7 +++++++
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 target/ppc/kvm.c       |  8 +++++++-
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 4 files changed, 29 insertions(+), 12 deletions(-)
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diff --git a/hw/ppc/spapr_caps.c b/hw/ppc/spapr_caps.c
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index 86a7947..dfc8cce 100644
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--- a/hw/ppc/spapr_caps.c
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+++ b/hw/ppc/spapr_caps.c
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@@ -236,11 +236,13 @@ static void cap_safe_bounds_check_apply(sPAPRMachineState *spapr, uint8_t val,
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 }
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 sPAPRCapPossible cap_ibs_possible = {
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-    .num = 4,
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+    .num = 5,
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     /* Note workaround only maintained for compatibility */
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-    .vals = {"broken", "workaround", "fixed-ibs", "fixed-ccd"},
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-    .help = "broken - no protection, fixed-ibs - indirect branch serialisation,"
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-            " fixed-ccd - cache count disabled",
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+    .vals = {"broken", "workaround", "fixed-ibs", "fixed-ccd", "fixed-na"},
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+    .help = "broken - no protection, workaround - count cache flush"
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+            ", fixed-ibs - indirect branch serialisation,"
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+            " fixed-ccd - cache count disabled,"
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+            " fixed-na - fixed in hardware (no longer applicable)",
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 };
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 static void cap_safe_indirect_branch_apply(sPAPRMachineState *spapr,
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@@ -248,15 +250,11 @@ static void cap_safe_indirect_branch_apply(sPAPRMachineState *spapr,
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 {
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     uint8_t kvm_val = kvmppc_get_cap_safe_indirect_branch();
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-    if (val == SPAPR_CAP_WORKAROUND) { /* Can only be Broken or Fixed */
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-        error_setg(errp,
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-"Requested safe indirect branch capability level \"workaround\" not valid, try cap-ibs=%s",
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-                   cap_ibs_possible.vals[kvm_val]);
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-    } else if (tcg_enabled() && val) {
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+    if (tcg_enabled() && val) {
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         /* TODO - for now only allow broken for TCG */
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         error_setg(errp,
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 "Requested safe indirect branch capability level not supported by tcg, try a different value for cap-ibs");
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-    } else if (kvm_enabled() && val && (val != kvm_val)) {
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+    } else if (kvm_enabled() && (val > kvm_val)) {
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         error_setg(errp,
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 "Requested safe indirect branch capability level not supported by kvm, try cap-ibs=%s",
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                    cap_ibs_possible.vals[kvm_val]);
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@@ -338,7 +336,8 @@ sPAPRCapabilityInfo capability_table[SPAPR_CAP_NUM] = {
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     [SPAPR_CAP_IBS] = {
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         .name = "ibs",
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         .description =
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-            "Indirect Branch Speculation (broken, fixed-ibs, fixed-ccd)",
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+            "Indirect Branch Speculation (broken, workaround, fixed-ibs,"
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+            "fixed-ccd, fixed-na)",
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         .index = SPAPR_CAP_IBS,
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         .get = spapr_cap_get_string,
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         .set = spapr_cap_set_string,
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diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
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index 16bccdd..01c4215 100644
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--- a/hw/ppc/spapr_hcall.c
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+++ b/hw/ppc/spapr_hcall.c
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@@ -1705,12 +1705,17 @@ static target_ulong h_get_cpu_characteristics(PowerPCCPU *cpu,
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     }
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     switch (safe_indirect_branch) {
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+    case SPAPR_CAP_FIXED_NA:
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+        break;
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     case SPAPR_CAP_FIXED_CCD:
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         characteristics |= H_CPU_CHAR_CACHE_COUNT_DIS;
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         break;
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     case SPAPR_CAP_FIXED_IBS:
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         characteristics |= H_CPU_CHAR_BCCTRL_SERIALISED;
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         break;
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+    case SPAPR_CAP_WORKAROUND:
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+        behaviour |= H_CPU_BEHAV_FLUSH_COUNT_CACHE;
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+        break;
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     default: /* broken */
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         assert(safe_indirect_branch == SPAPR_CAP_BROKEN);
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         break;
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diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
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index 72cfa49..8bb95bb 100644
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--- a/include/hw/ppc/spapr.h
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+++ b/include/hw/ppc/spapr.h
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@@ -77,12 +77,17 @@ typedef enum {
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 /* Bool Caps */
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 #define SPAPR_CAP_OFF                   0x00
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 #define SPAPR_CAP_ON                    0x01
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+
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 /* Custom Caps */
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+
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+/* Generic */
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 #define SPAPR_CAP_BROKEN                0x00
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 #define SPAPR_CAP_WORKAROUND            0x01
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 #define SPAPR_CAP_FIXED                 0x02
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+/* SPAPR_CAP_IBS (cap-ibs) */
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 #define SPAPR_CAP_FIXED_IBS             0x02
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 #define SPAPR_CAP_FIXED_CCD             0x03
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+#define SPAPR_CAP_FIXED_NA              0x10 /* Lets leave a bit of a gap... */
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 typedef struct sPAPRCapabilities sPAPRCapabilities;
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 struct sPAPRCapabilities {
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@@ -322,9 +327,11 @@ struct sPAPRMachineState {
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 #define H_CPU_CHAR_HON_BRANCH_HINTS             PPC_BIT(5)
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 #define H_CPU_CHAR_THR_RECONF_TRIG              PPC_BIT(6)
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 #define H_CPU_CHAR_CACHE_COUNT_DIS              PPC_BIT(7)
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+#define H_CPU_CHAR_BCCTR_FLUSH_ASSIST           PPC_BIT(9)
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 #define H_CPU_BEHAV_FAVOUR_SECURITY             PPC_BIT(0)
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 #define H_CPU_BEHAV_L1D_FLUSH_PR                PPC_BIT(1)
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 #define H_CPU_BEHAV_BNDS_CHK_SPEC_BAR           PPC_BIT(2)
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+#define H_CPU_BEHAV_FLUSH_COUNT_CACHE           PPC_BIT(5)
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 /* Each control block has to be on a 4K boundary */
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 #define H_CB_ALIGNMENT     4096
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diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c
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index b9858fa..0e94cfc 100644
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--- a/target/ppc/kvm.c
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+++ b/target/ppc/kvm.c
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@@ -2511,7 +2511,13 @@ static int parse_cap_ppc_safe_bounds_check(struct kvm_ppc_cpu_char c)
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 static int parse_cap_ppc_safe_indirect_branch(struct kvm_ppc_cpu_char c)
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 {
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-    if (c.character & c.character_mask & H_CPU_CHAR_CACHE_COUNT_DIS) {
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+    if ((~c.behaviour & c.behaviour_mask & H_CPU_BEHAV_FLUSH_COUNT_CACHE) &&
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+        (~c.character & c.character_mask & H_CPU_CHAR_CACHE_COUNT_DIS) &&
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+        (~c.character & c.character_mask & H_CPU_CHAR_BCCTRL_SERIALISED)) {
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+        return SPAPR_CAP_FIXED_NA;
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+    } else if (c.behaviour & c.behaviour_mask & H_CPU_BEHAV_FLUSH_COUNT_CACHE) {
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+        return SPAPR_CAP_WORKAROUND;
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+    } else if (c.character & c.character_mask & H_CPU_CHAR_CACHE_COUNT_DIS) {
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         return  SPAPR_CAP_FIXED_CCD;
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     } else if (c.character & c.character_mask & H_CPU_CHAR_BCCTRL_SERIALISED) {
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         return SPAPR_CAP_FIXED_IBS;
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-- 
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1.8.3.1
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