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From 5f40ed9dd62b914f259c1b6a51298fedb6bb2a24 Mon Sep 17 00:00:00 2001
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From: Eduardo Habkost <ehabkost@redhat.com>
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Date: Thu, 25 Jun 2015 19:31:26 +0200
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Subject: [PATCH 06/10] target-i386: fix set of registers zeroed on reset
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Message-id: <1435260689-9556-6-git-send-email-ehabkost@redhat.com>
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Patchwork-id: 66505
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O-Subject: [RHEL-7.2 qemu-kvm PATCH 5/8] target-i386: fix set of registers zeroed on reset
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Bugzilla: 1233350
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RH-Acked-by: Igor Mammedov <imammedo@redhat.com>
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RH-Acked-by: Bandan Das <bsd@redhat.com>
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RH-Acked-by: Paolo Bonzini <pbonzini@redhat.com>
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From: Paolo Bonzini <pbonzini@redhat.com>
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BND0-3, BNDCFGU, BNDCFGS, BNDSTATUS were not zeroed on reset, but they
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should be (Intel Instruction Set Extensions Programming Reference
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319433-015, pages 9-4 and 9-6). Same for YMM.
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XCR0 should be reset to 1.
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TSC and TSC_RESET were zeroed already by the memset, remove the explicit
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assignments.
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Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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(cherry picked from commit 05e7e819d7d159a75a46354aead95e1199b8f168)
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Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
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Signed-off-by: Miroslav Rezanina <mrezanin@redhat.com>
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Conflicts:
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target-i386/cpu.c
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Backport notes:
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* The TSC and TSC_RESET reset lines were never added to the
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qemu-kvm-1.5.3 tree
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---
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target-i386/cpu.c | 2 ++
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target-i386/cpu.h | 11 ++++++-----
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2 files changed, 8 insertions(+), 5 deletions(-)
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diff --git a/target-i386/cpu.c b/target-i386/cpu.c
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index 2eeff5c..96af1bf 100644
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--- a/target-i386/cpu.c
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+++ b/target-i386/cpu.c
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@@ -2402,6 +2402,8 @@ static void x86_cpu_reset(CPUState *s)
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cpu_breakpoint_remove_all(env, BP_CPU);
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cpu_watchpoint_remove_all(env, BP_CPU);
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+ env->xcr0 = 1;
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+
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/*
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* SDM 11.11.5 requires:
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* - IA32_MTRR_DEF_TYPE MSR.E = 0
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diff --git a/target-i386/cpu.h b/target-i386/cpu.h
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index 7ebdbb3..715ba63 100644
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--- a/target-i386/cpu.h
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+++ b/target-i386/cpu.h
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@@ -798,6 +798,10 @@ typedef struct CPUX86State {
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target_ulong cr[5]; /* NOTE: cr1 is unused */
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int32_t a20_mask;
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+ BNDReg bnd_regs[4];
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+ BNDCSReg bndcs_regs;
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+ uint64_t msr_bndcfgs;
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+
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/* FPU state */
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unsigned int fpstt; /* top of stack index */
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uint16_t fpus;
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@@ -820,6 +824,8 @@ typedef struct CPUX86State {
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XMMReg xmm_t0;
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MMXReg mmx_t0;
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+ XMMReg ymmh_regs[CPU_NB_REGS];
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+
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/* sysenter registers */
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uint32_t sysenter_cs;
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target_ulong sysenter_esp;
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@@ -931,12 +937,7 @@ typedef struct CPUX86State {
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uint16_t fpus_vmstate;
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uint16_t fptag_vmstate;
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uint16_t fpregs_format_vmstate;
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-
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uint64_t xstate_bv;
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- XMMReg ymmh_regs[CPU_NB_REGS];
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- BNDReg bnd_regs[4];
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- BNDCSReg bndcs_regs;
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- uint64_t msr_bndcfgs;
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uint64_t xcr0;
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--
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1.8.3.1
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