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Blame SOURCES/kvm-target-i386-define-a-new-MSR-based-feature-word-FEAT.patch

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From 127410386296459cf3eec4b12d7451afc50d2503 Mon Sep 17 00:00:00 2001
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From: Paolo Bonzini <pbonzini@redhat.com>
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Date: Fri, 22 Nov 2019 11:53:36 +0000
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Subject: [PATCH 03/16] target/i386: define a new MSR based feature word -
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 FEAT_CORE_CAPABILITY
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RH-Author: Paolo Bonzini <pbonzini@redhat.com>
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Message-id: <20191122115348.25000-4-pbonzini@redhat.com>
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Patchwork-id: 92603
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O-Subject: [RHEL8.2/rhel qemu-kvm PATCH 03/15] target/i386: define a new MSR based feature word - FEAT_CORE_CAPABILITY
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Bugzilla: 1689270
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RH-Acked-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
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RH-Acked-by: Eduardo Habkost <ehabkost@redhat.com>
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RH-Acked-by: Maxim Levitsky <mlevitsk@redhat.com>
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From: Xiaoyao Li <xiaoyao.li@linux.intel.com>
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MSR IA32_CORE_CAPABILITY is a feature-enumerating MSR, which only
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enumerates the feature split lock detection (via bit 5) by now.
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The existence of MSR IA32_CORE_CAPABILITY is enumerated by CPUID.7_0:EDX[30].
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The latest kernel patches about them can be found here:
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https://lkml.org/lkml/2019/4/24/1909
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Signed-off-by: Xiaoyao Li <xiaoyao.li@linux.intel.com>
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Message-Id: <20190617153654.916-1-xiaoyao.li@linux.intel.com>
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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(cherry picked from commit 597360c0d8ebda9ca6f239db724a25bddec62b2f)
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RHEL: context
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Signed-off-by: Danilo C. L. de Paula <ddepaula@redhat.com>
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---
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 target/i386/cpu.c | 22 +++++++++++++++++++++-
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 target/i386/cpu.h |  5 +++++
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 target/i386/kvm.c |  9 +++++++++
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 3 files changed, 35 insertions(+), 1 deletion(-)
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diff --git a/target/i386/cpu.c b/target/i386/cpu.c
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index 8c1338f..52f1f33 100644
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--- a/target/i386/cpu.c
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+++ b/target/i386/cpu.c
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@@ -1045,7 +1045,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
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             NULL, NULL, NULL, NULL,
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             NULL, NULL, NULL, NULL,
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             NULL, NULL, "spec-ctrl", "stibp",
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-            NULL, "arch-capabilities", NULL, "ssbd",
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+            NULL, "arch-capabilities", "core-capability", "ssbd",
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         },
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         .cpuid = {
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             .eax = 7,
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@@ -1163,6 +1163,26 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
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             }
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         },
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     },
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+    [FEAT_CORE_CAPABILITY] = {
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+        .type = MSR_FEATURE_WORD,
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+        .feat_names = {
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+            NULL, NULL, NULL, NULL,
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+            NULL, "split-lock-detect", NULL, NULL,
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+            NULL, NULL, NULL, NULL,
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+            NULL, NULL, NULL, NULL,
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+            NULL, NULL, NULL, NULL,
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+            NULL, NULL, NULL, NULL,
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+            NULL, NULL, NULL, NULL,
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+            NULL, NULL, NULL, NULL,
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+        },
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+        .msr = {
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+            .index = MSR_IA32_CORE_CAPABILITY,
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+            .cpuid_dep = {
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+                FEAT_7_0_EDX,
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+                CPUID_7_0_EDX_CORE_CAPABILITY,
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+            },
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+        },
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+    },
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 };
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 typedef struct X86RegisterInfo32 {
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diff --git a/target/i386/cpu.h b/target/i386/cpu.h
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index 1ad54bd..f9b93be 100644
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--- a/target/i386/cpu.h
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+++ b/target/i386/cpu.h
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@@ -353,6 +353,7 @@ typedef enum X86Seg {
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 #define MSR_IA32_SPEC_CTRL              0x48
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 #define MSR_VIRT_SSBD                   0xc001011f
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 #define MSR_IA32_PRED_CMD               0x49
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+#define MSR_IA32_CORE_CAPABILITY        0xcf
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 #define MSR_IA32_ARCH_CAPABILITIES      0x10a
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 #define MSR_IA32_TSCDEADLINE            0x6e0
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@@ -501,6 +502,7 @@ typedef enum FeatureWord {
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     FEAT_XSAVE_COMP_LO, /* CPUID[EAX=0xd,ECX=0].EAX */
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     FEAT_XSAVE_COMP_HI, /* CPUID[EAX=0xd,ECX=0].EDX */
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     FEAT_ARCH_CAPABILITIES,
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+    FEAT_CORE_CAPABILITY,
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     FEATURE_WORDS,
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 } FeatureWord;
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@@ -690,6 +692,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
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 #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation Single Precision */
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 #define CPUID_7_0_EDX_SPEC_CTRL     (1U << 26) /* Speculation Control */
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 #define CPUID_7_0_EDX_ARCH_CAPABILITIES (1U << 29)  /*Arch Capabilities*/
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+#define CPUID_7_0_EDX_CORE_CAPABILITY   (1U << 30)  /*Core Capability*/
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 #define CPUID_7_0_EDX_SPEC_CTRL_SSBD  (1U << 31) /* Speculative Store Bypass Disable */
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 #define KVM_HINTS_DEDICATED (1U << 0)
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@@ -744,6 +747,8 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
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 #define MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY (1U << 3)
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 #define MSR_ARCH_CAP_SSB_NO     (1U << 4)
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+#define MSR_CORE_CAP_SPLIT_LOCK_DETECT  (1U << 5)
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+
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 #ifndef HYPERV_SPINLOCK_NEVER_RETRY
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 #define HYPERV_SPINLOCK_NEVER_RETRY             0xFFFFFFFF
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 #endif
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diff --git a/target/i386/kvm.c b/target/i386/kvm.c
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index da5f07e..849a11a 100644
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--- a/target/i386/kvm.c
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+++ b/target/i386/kvm.c
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@@ -95,6 +95,7 @@ static bool has_msr_spec_ctrl;
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 static bool has_msr_virt_ssbd;
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 static bool has_msr_smi_count;
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 static bool has_msr_arch_capabs;
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+static bool has_msr_core_capabs;
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 static uint32_t has_architectural_pmu_version;
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 static uint32_t num_architectural_pmu_gp_counters;
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@@ -1428,6 +1429,9 @@ static int kvm_get_supported_msrs(KVMState *s)
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                 case MSR_IA32_ARCH_CAPABILITIES:
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                     has_msr_arch_capabs = true;
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                     break;
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+                case MSR_IA32_CORE_CAPABILITY:
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+                    has_msr_core_capabs = true;
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+                    break;
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                 }
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             }
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         }
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@@ -1947,6 +1951,11 @@ static int kvm_put_msrs(X86CPU *cpu, int level)
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                           env->features[FEAT_ARCH_CAPABILITIES]);
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     }
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+    if (has_msr_core_capabs) {
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+        kvm_msr_entry_add(cpu, MSR_IA32_CORE_CAPABILITY,
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+                          env->features[FEAT_CORE_CAPABILITY]);
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+    }
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+
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     /*
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      * The following MSRs have side effects on the guest or are too heavy
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      * for normal writeback. Limit them to reset or full state updates.
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-- 
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1.8.3.1
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