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From 4adba22c823ecc91cca5aeb835834b3393d5f50b Mon Sep 17 00:00:00 2001
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From: Eduardo Habkost <ehabkost@redhat.com>
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Date: Tue, 3 Dec 2019 22:51:41 +0000
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Subject: [PATCH 2/2] target/i386: add support for MSR_IA32_TSX_CTRL
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RH-Author: Eduardo Habkost <ehabkost@redhat.com>
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Message-id: <20191203225141.501191-3-ehabkost@redhat.com>
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Patchwork-id: 92841
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O-Subject: [RHEL-8.1.0 qemu-kvm PATCH 2/2] target/i386: add support for MSR_IA32_TSX_CTRL
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Bugzilla: 1771970
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RH-Acked-by: Paolo Bonzini <pbonzini@redhat.com>
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RH-Acked-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
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RH-Acked-by: Igor Mammedov <imammedo@redhat.com>
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From: Paolo Bonzini <pbonzini@redhat.com>
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The MSR_IA32_TSX_CTRL MSR can be used to hide TSX (also known as the
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Trusty Side-channel Extension). By virtualizing the MSR, KVM guests
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can disable TSX and avoid paying the price of mitigating TSX-based
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attacks on microarchitectural side channels.
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Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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(cherry picked from commit 2a9758c51e2c2d13fc3845c3d603c11df98b8823)
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Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
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Signed-off-by: Danilo C. L. de Paula <ddepaula@redhat.com>
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---
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target/i386/cpu.c | 2 +-
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target/i386/cpu.h | 4 ++++
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target/i386/kvm.c | 13 +++++++++++++
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target/i386/machine.c | 20 ++++++++++++++++++++
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4 files changed, 38 insertions(+), 1 deletion(-)
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diff --git a/target/i386/cpu.c b/target/i386/cpu.c
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index 7baa5d2..591ebf3 100644
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--- a/target/i386/cpu.c
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+++ b/target/i386/cpu.c
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@@ -1147,7 +1147,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
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.type = MSR_FEATURE_WORD,
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.feat_names = {
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"rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry",
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- "ssb-no", "mds-no", NULL, NULL,
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+ "ssb-no", "mds-no", NULL, "tsx-ctrl",
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"taa-no", NULL, NULL, NULL,
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NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL,
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diff --git a/target/i386/cpu.h b/target/i386/cpu.h
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index 273c90b..b6bef27 100644
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--- a/target/i386/cpu.h
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+++ b/target/i386/cpu.h
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@@ -354,6 +354,9 @@ typedef enum X86Seg {
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#define MSR_VIRT_SSBD 0xc001011f
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#define MSR_IA32_PRED_CMD 0x49
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#define MSR_IA32_ARCH_CAPABILITIES 0x10a
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+#define ARCH_CAP_TSX_CTRL_MSR (1<<7)
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+
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+#define MSR_IA32_TSX_CTRL 0x122
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#define MSR_IA32_TSCDEADLINE 0x6e0
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#define FEATURE_CONTROL_LOCKED (1<<0)
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@@ -1229,6 +1232,7 @@ typedef struct CPUX86State {
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uint64_t msr_smi_count;
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uint32_t pkru;
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+ uint32_t tsx_ctrl;
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uint64_t spec_ctrl;
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uint64_t virt_ssbd;
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diff --git a/target/i386/kvm.c b/target/i386/kvm.c
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index da5f07e..06144f0 100644
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--- a/target/i386/kvm.c
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+++ b/target/i386/kvm.c
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@@ -92,6 +92,7 @@ static bool has_msr_hv_stimer;
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static bool has_msr_hv_frequencies;
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static bool has_msr_xss;
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static bool has_msr_spec_ctrl;
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+static bool has_msr_tsx_ctrl;
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static bool has_msr_virt_ssbd;
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static bool has_msr_smi_count;
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static bool has_msr_arch_capabs;
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@@ -1422,6 +1423,9 @@ static int kvm_get_supported_msrs(KVMState *s)
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case MSR_IA32_SPEC_CTRL:
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has_msr_spec_ctrl = true;
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break;
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+ case MSR_IA32_TSX_CTRL:
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+ has_msr_tsx_ctrl = true;
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+ break;
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case MSR_VIRT_SSBD:
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has_msr_virt_ssbd = true;
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break;
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@@ -1928,6 +1932,9 @@ static int kvm_put_msrs(X86CPU *cpu, int level)
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if (has_msr_spec_ctrl) {
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kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, env->spec_ctrl);
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}
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+ if (has_msr_tsx_ctrl) {
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+ kvm_msr_entry_add(cpu, MSR_IA32_TSX_CTRL, env->tsx_ctrl);
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+ }
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if (has_msr_virt_ssbd) {
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kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, env->virt_ssbd);
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}
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@@ -2310,6 +2317,9 @@ static int kvm_get_msrs(X86CPU *cpu)
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if (has_msr_spec_ctrl) {
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kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, 0);
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}
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+ if (has_msr_tsx_ctrl) {
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+ kvm_msr_entry_add(cpu, MSR_IA32_TSX_CTRL, 0);
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+ }
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if (has_msr_virt_ssbd) {
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kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, 0);
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}
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@@ -2681,6 +2691,9 @@ static int kvm_get_msrs(X86CPU *cpu)
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case MSR_IA32_SPEC_CTRL:
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env->spec_ctrl = msrs[i].data;
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break;
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+ case MSR_IA32_TSX_CTRL:
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+ env->tsx_ctrl = msrs[i].data;
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+ break;
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case MSR_VIRT_SSBD:
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env->virt_ssbd = msrs[i].data;
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break;
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diff --git a/target/i386/machine.c b/target/i386/machine.c
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index fa8d1cc..76b173c 100644
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--- a/target/i386/machine.c
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+++ b/target/i386/machine.c
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@@ -1226,6 +1226,25 @@ static const VMStateDescription vmstate_efer32 = {
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};
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#endif
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+static bool msr_tsx_ctrl_needed(void *opaque)
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+{
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+ X86CPU *cpu = opaque;
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+ CPUX86State *env = &cpu->env;
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+
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+ return env->features[FEAT_ARCH_CAPABILITIES] & ARCH_CAP_TSX_CTRL_MSR;
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+}
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+
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+static const VMStateDescription vmstate_msr_tsx_ctrl = {
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+ .name = "cpu/msr_tsx_ctrl",
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+ .version_id = 1,
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+ .minimum_version_id = 1,
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+ .needed = msr_tsx_ctrl_needed,
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+ .fields = (VMStateField[]) {
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+ VMSTATE_UINT32(env.tsx_ctrl, X86CPU),
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+ VMSTATE_END_OF_LIST()
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+ }
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+};
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+
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VMStateDescription vmstate_x86_cpu = {
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.name = "cpu",
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.version_id = 12,
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@@ -1357,6 +1376,7 @@ VMStateDescription vmstate_x86_cpu = {
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#ifdef CONFIG_KVM
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&vmstate_nested_state,
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#endif
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+ &vmstate_msr_tsx_ctrl,
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NULL
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}
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};
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--
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1.8.3.1
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