yeahuh / rpms / qemu-kvm

Forked from rpms/qemu-kvm 2 years ago
Clone

Blame SOURCES/kvm-target-i386-add-VMX-features-to-named-CPU-models.patch

4ec855
From a958a54a1072e201d209fd54e3fd0b55a331c5da Mon Sep 17 00:00:00 2001
4ec855
From: Paolo Bonzini <pbonzini@redhat.com>
4ec855
Date: Fri, 22 Nov 2019 11:53:47 +0000
4ec855
Subject: [PATCH 14/16] target/i386: add VMX features to named CPU models
4ec855
4ec855
RH-Author: Paolo Bonzini <pbonzini@redhat.com>
4ec855
Message-id: <20191122115348.25000-15-pbonzini@redhat.com>
4ec855
Patchwork-id: 92613
4ec855
O-Subject: [RHEL8.2/rhel qemu-kvm PATCH 14/15] target/i386: add VMX features to named CPU models
4ec855
Bugzilla: 1689270
4ec855
RH-Acked-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
4ec855
RH-Acked-by: Eduardo Habkost <ehabkost@redhat.com>
4ec855
RH-Acked-by: Maxim Levitsky <mlevitsk@redhat.com>
4ec855
4ec855
This allows using "-cpu Haswell,+vmx", which we did not really want to
4ec855
support in QEMU but was produced by Libvirt when using the "host-model"
4ec855
CPU model.  Without this patch, no VMX feature is _actually_ supported
4ec855
(only the basic instruction set extensions are) and KVM fails to load
4ec855
in the guest.
4ec855
4ec855
This was produced from the output of scripts/kvm/vmxcap using the following
4ec855
very ugly Python script:
4ec855
4ec855
    bits = {
4ec855
            'INS/OUTS instruction information': ['FEAT_VMX_BASIC', 'MSR_VMX_BASIC_INS_OUTS'],
4ec855
            'IA32_VMX_TRUE_*_CTLS support': ['FEAT_VMX_BASIC', 'MSR_VMX_BASIC_TRUE_CTLS'],
4ec855
            'External interrupt exiting': ['FEAT_VMX_PINBASED_CTLS', 'VMX_PIN_BASED_EXT_INTR_MASK'],
4ec855
            'NMI exiting': ['FEAT_VMX_PINBASED_CTLS', 'VMX_PIN_BASED_NMI_EXITING'],
4ec855
            'Virtual NMIs': ['FEAT_VMX_PINBASED_CTLS', 'VMX_PIN_BASED_VIRTUAL_NMIS'],
4ec855
            'Activate VMX-preemption timer': ['FEAT_VMX_PINBASED_CTLS', 'VMX_PIN_BASED_VMX_PREEMPTION_TIMER'],
4ec855
            'Process posted interrupts': ['FEAT_VMX_PINBASED_CTLS', 'VMX_PIN_BASED_POSTED_INTR'],
4ec855
            'Interrupt window exiting': ['FEAT_VMX_PROCBASED_CTLS', 'VMX_CPU_BASED_VIRTUAL_INTR_PENDING'],
4ec855
            'Use TSC offsetting': ['FEAT_VMX_PROCBASED_CTLS', 'VMX_CPU_BASED_USE_TSC_OFFSETING'],
4ec855
            'HLT exiting': ['FEAT_VMX_PROCBASED_CTLS', 'VMX_CPU_BASED_HLT_EXITING'],
4ec855
            'INVLPG exiting': ['FEAT_VMX_PROCBASED_CTLS', 'VMX_CPU_BASED_INVLPG_EXITING'],
4ec855
            'MWAIT exiting': ['FEAT_VMX_PROCBASED_CTLS', 'VMX_CPU_BASED_MWAIT_EXITING'],
4ec855
            'RDPMC exiting': ['FEAT_VMX_PROCBASED_CTLS', 'VMX_CPU_BASED_RDPMC_EXITING'],
4ec855
            'RDTSC exiting': ['FEAT_VMX_PROCBASED_CTLS', 'VMX_CPU_BASED_RDTSC_EXITING'],
4ec855
            'CR3-load exiting': ['FEAT_VMX_PROCBASED_CTLS', 'VMX_CPU_BASED_CR3_LOAD_EXITING'],
4ec855
            'CR3-store exiting': ['FEAT_VMX_PROCBASED_CTLS', 'VMX_CPU_BASED_CR3_STORE_EXITING'],
4ec855
            'CR8-load exiting': ['FEAT_VMX_PROCBASED_CTLS', 'VMX_CPU_BASED_CR8_LOAD_EXITING'],
4ec855
            'CR8-store exiting': ['FEAT_VMX_PROCBASED_CTLS', 'VMX_CPU_BASED_CR8_STORE_EXITING'],
4ec855
            'Use TPR shadow': ['FEAT_VMX_PROCBASED_CTLS', 'VMX_CPU_BASED_TPR_SHADOW'],
4ec855
            'NMI-window exiting': ['FEAT_VMX_PROCBASED_CTLS', 'VMX_CPU_BASED_VIRTUAL_NMI_PENDING'],
4ec855
            'MOV-DR exiting': ['FEAT_VMX_PROCBASED_CTLS', 'VMX_CPU_BASED_MOV_DR_EXITING'],
4ec855
            'Unconditional I/O exiting': ['FEAT_VMX_PROCBASED_CTLS', 'VMX_CPU_BASED_UNCOND_IO_EXITING'],
4ec855
            'Use I/O bitmaps': ['FEAT_VMX_PROCBASED_CTLS', 'VMX_CPU_BASED_USE_IO_BITMAPS'],
4ec855
            'Monitor trap flag': ['FEAT_VMX_PROCBASED_CTLS', 'VMX_CPU_BASED_MONITOR_TRAP_FLAG'],
4ec855
            'Use MSR bitmaps': ['FEAT_VMX_PROCBASED_CTLS', 'VMX_CPU_BASED_USE_MSR_BITMAPS'],
4ec855
            'MONITOR exiting': ['FEAT_VMX_PROCBASED_CTLS', 'VMX_CPU_BASED_MONITOR_EXITING'],
4ec855
            'PAUSE exiting': ['FEAT_VMX_PROCBASED_CTLS', 'VMX_CPU_BASED_PAUSE_EXITING'],
4ec855
            'Activate secondary control': ['FEAT_VMX_PROCBASED_CTLS', 'VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS'],
4ec855
            'Virtualize APIC accesses': ['FEAT_VMX_SECONDARY_CTLS', 'VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES'],
4ec855
            'Enable EPT': ['FEAT_VMX_SECONDARY_CTLS', 'VMX_SECONDARY_EXEC_ENABLE_EPT'],
4ec855
            'Descriptor-table exiting': ['FEAT_VMX_SECONDARY_CTLS', 'VMX_SECONDARY_EXEC_DESC'],
4ec855
            'Enable RDTSCP': ['FEAT_VMX_SECONDARY_CTLS', 'VMX_SECONDARY_EXEC_RDTSCP'],
4ec855
            'Virtualize x2APIC mode': ['FEAT_VMX_SECONDARY_CTLS', 'VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE'],
4ec855
            'Enable VPID': ['FEAT_VMX_SECONDARY_CTLS', 'VMX_SECONDARY_EXEC_ENABLE_VPID'],
4ec855
            'WBINVD exiting': ['FEAT_VMX_SECONDARY_CTLS', 'VMX_SECONDARY_EXEC_WBINVD_EXITING'],
4ec855
            'Unrestricted guest': ['FEAT_VMX_SECONDARY_CTLS', 'VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST'],
4ec855
            'APIC register emulation': ['FEAT_VMX_SECONDARY_CTLS', 'VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT'],
4ec855
            'Virtual interrupt delivery': ['FEAT_VMX_SECONDARY_CTLS', 'VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY'],
4ec855
            'PAUSE-loop exiting': ['FEAT_VMX_SECONDARY_CTLS', 'VMX_SECONDARY_EXEC_PAUSE_LOOP_EXITING'],
4ec855
            'RDRAND exiting': ['FEAT_VMX_SECONDARY_CTLS', 'VMX_SECONDARY_EXEC_RDRAND_EXITING'],
4ec855
            'Enable INVPCID': ['FEAT_VMX_SECONDARY_CTLS', 'VMX_SECONDARY_EXEC_ENABLE_INVPCID'],
4ec855
            'Enable VM functions': ['FEAT_VMX_SECONDARY_CTLS', 'VMX_SECONDARY_EXEC_ENABLE_VMFUNC'],
4ec855
            'VMCS shadowing': ['FEAT_VMX_SECONDARY_CTLS', 'VMX_SECONDARY_EXEC_SHADOW_VMCS'],
4ec855
            'RDSEED exiting': ['FEAT_VMX_SECONDARY_CTLS', 'VMX_SECONDARY_EXEC_RDSEED_EXITING'],
4ec855
            'Enable PML': ['FEAT_VMX_SECONDARY_CTLS', 'VMX_SECONDARY_EXEC_ENABLE_PML'],
4ec855
            'Enable XSAVES/XRSTORS': ['FEAT_VMX_SECONDARY_CTLS', 'VMX_SECONDARY_EXEC_XSAVES'],
4ec855
            'Save debug controls': ['FEAT_VMX_EXIT_CTLS', 'VMX_VM_EXIT_SAVE_DEBUG_CONTROLS'],
4ec855
            'Load IA32_PERF_GLOBAL_CTRL': ['FEAT_VMX_EXIT_CTLS', 'VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL'],
4ec855
            'Acknowledge interrupt on exit': ['FEAT_VMX_EXIT_CTLS', 'VMX_VM_EXIT_ACK_INTR_ON_EXIT'],
4ec855
            'Save IA32_PAT': ['FEAT_VMX_EXIT_CTLS', 'VMX_VM_EXIT_SAVE_IA32_PAT'],
4ec855
            'Load IA32_PAT': ['FEAT_VMX_EXIT_CTLS', 'VMX_VM_EXIT_LOAD_IA32_PAT'],
4ec855
            'Save IA32_EFER': ['FEAT_VMX_EXIT_CTLS', 'VMX_VM_EXIT_SAVE_IA32_EFER'],
4ec855
            'Load IA32_EFER': ['FEAT_VMX_EXIT_CTLS', 'VMX_VM_EXIT_LOAD_IA32_EFER'],
4ec855
            'Save VMX-preemption timer value': ['FEAT_VMX_EXIT_CTLS', 'VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER'],
4ec855
            'Clear IA32_BNDCFGS': ['FEAT_VMX_EXIT_CTLS', 'VMX_VM_EXIT_CLEAR_BNDCFGS'],
4ec855
            'Load debug controls': ['FEAT_VMX_ENTRY_CTLS', 'VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS'],
4ec855
            'IA-32e mode guest': ['FEAT_VMX_ENTRY_CTLS', 'VMX_VM_ENTRY_IA32E_MODE'],
4ec855
            'Load IA32_PERF_GLOBAL_CTRL': ['FEAT_VMX_ENTRY_CTLS', 'VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL'],
4ec855
            'Load IA32_PAT': ['FEAT_VMX_ENTRY_CTLS', 'VMX_VM_ENTRY_LOAD_IA32_PAT'],
4ec855
            'Load IA32_EFER': ['FEAT_VMX_ENTRY_CTLS', 'VMX_VM_ENTRY_LOAD_IA32_EFER'],
4ec855
            'Load IA32_BNDCFGS': ['FEAT_VMX_ENTRY_CTLS', 'VMX_VM_ENTRY_LOAD_BNDCFGS'],
4ec855
            'Store EFER.LMA into IA-32e mode guest control': ['FEAT_VMX_MISC', 'MSR_VMX_MISC_STORE_LMA'],
4ec855
            'HLT activity state': ['FEAT_VMX_MISC', 'MSR_VMX_MISC_ACTIVITY_HLT'],
4ec855
            'VMWRITE to VM-exit information fields': ['FEAT_VMX_MISC', 'MSR_VMX_MISC_VMWRITE_VMEXIT'],
4ec855
            'Inject event with insn length=0': ['FEAT_VMX_MISC', 'MSR_VMX_MISC_ZERO_LEN_INJECT'],
4ec855
            'Execute-only EPT translations': ['FEAT_VMX_EPT_VPID_CAPS', 'MSR_VMX_EPT_EXECONLY'],
4ec855
            'Page-walk length 4': ['FEAT_VMX_EPT_VPID_CAPS', 'MSR_VMX_EPT_PAGE_WALK_LENGTH_4'],
4ec855
            'Paging-structure memory type WB': ['FEAT_VMX_EPT_VPID_CAPS', 'MSR_VMX_EPT_WB'],
4ec855
            '2MB EPT pages': ['FEAT_VMX_EPT_VPID_CAPS', 'MSR_VMX_EPT_2MB | MSR_VMX_EPT_1GB'],
4ec855
            'INVEPT supported': ['FEAT_VMX_EPT_VPID_CAPS', 'MSR_VMX_EPT_INVEPT'],
4ec855
            'EPT accessed and dirty flags': ['FEAT_VMX_EPT_VPID_CAPS', 'MSR_VMX_EPT_AD_BITS'],
4ec855
            'Single-context INVEPT': ['FEAT_VMX_EPT_VPID_CAPS', 'MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT'],
4ec855
            'All-context INVEPT': ['FEAT_VMX_EPT_VPID_CAPS', 'MSR_VMX_EPT_INVEPT_ALL_CONTEXT'],
4ec855
            'INVVPID supported': ['FEAT_VMX_EPT_VPID_CAPS', 'MSR_VMX_EPT_INVVPID'],
4ec855
            'Individual-address INVVPID': ['FEAT_VMX_EPT_VPID_CAPS', 'MSR_VMX_EPT_INVVPID_SINGLE_ADDR'],
4ec855
            'Single-context INVVPID': ['FEAT_VMX_EPT_VPID_CAPS', 'MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT'],
4ec855
            'All-context INVVPID': ['FEAT_VMX_EPT_VPID_CAPS', 'MSR_VMX_EPT_INVVPID_ALL_CONTEXT'],
4ec855
            'Single-context-retaining-globals INVVPID': ['FEAT_VMX_EPT_VPID_CAPS', 'MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS'],
4ec855
            'EPTP Switching': ['FEAT_VMX_VMFUNC', 'MSR_VMX_VMFUNC_EPT_SWITCHING']
4ec855
    }
4ec855
4ec855
    import sys
4ec855
    import textwrap
4ec855
4ec855
    out = {}
4ec855
    for l in sys.stdin.readlines():
4ec855
        l = l.rstrip()
4ec855
        if l.endswith('!!'):
4ec855
            l = l[:-2].rstrip()
4ec855
        if l.startswith('    ') and (l.endswith('default') or l.endswith('yes')):
4ec855
            l = l[4:]
4ec855
            for key, value in bits.items():
4ec855
                if l.startswith(key):
4ec855
                    ctl, bit = value
4ec855
                    if ctl in out:
4ec855
                        out[ctl] = out[ctl] + ' | '
4ec855
                    else:
4ec855
                        out[ctl] = '    [%s] = ' % ctl
4ec855
                    out[ctl] = out[ctl] + bit
4ec855
4ec855
    for x in sorted(out.keys()):
4ec855
        print("\n         ".join(textwrap.wrap(out[x] + ",")))
4ec855
4ec855
Note that the script has a bug in that some keys apply to both VM entry
4ec855
and VM exit controls ("load IA32_PERF_GLOBAL_CTRL", "load IA32_EFER",
4ec855
"load IA32_PAT".  Those have to be fixed by hand.
4ec855
4ec855
Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
4ec855
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
4ec855
(cherry picked from commit 0723cc8a5558c94388db75ae1f4991314914edd3)
4ec855
4ec855
RHEL: no Denverton and Snowridge
4ec855
Signed-off-by: Danilo C. L. de Paula <ddepaula@redhat.com>
4ec855
---
4ec855
 target/i386/cpu.c | 617 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
4ec855
 1 file changed, 617 insertions(+)
4ec855
4ec855
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
4ec855
index 9074a2e..36c9252 100644
4ec855
--- a/target/i386/cpu.c
4ec855
+++ b/target/i386/cpu.c
4ec855
@@ -1689,6 +1689,34 @@ static CPUCaches epyc_cache_info = {
4ec855
     },
4ec855
 };
4ec855
 
4ec855
+/* The following VMX features are not supported by KVM and are left out in the
4ec855
+ * CPU definitions:
4ec855
+ *
4ec855
+ *  Dual-monitor support (all processors)
4ec855
+ *  Entry to SMM
4ec855
+ *  Deactivate dual-monitor treatment
4ec855
+ *  Number of CR3-target values
4ec855
+ *  Shutdown activity state
4ec855
+ *  Wait-for-SIPI activity state
4ec855
+ *  PAUSE-loop exiting (Westmere and newer)
4ec855
+ *  EPT-violation #VE (Broadwell and newer)
4ec855
+ *  Inject event with insn length=0 (Skylake and newer)
4ec855
+ *  Conceal non-root operation from PT
4ec855
+ *  Conceal VM exits from PT
4ec855
+ *  Conceal VM entries from PT
4ec855
+ *  Enable ENCLS exiting
4ec855
+ *  Mode-based execute control (XS/XU)
4ec855
+ s  TSC scaling (Skylake Server and newer)
4ec855
+ *  GPA translation for PT (IceLake and newer)
4ec855
+ *  User wait and pause
4ec855
+ *  ENCLV exiting
4ec855
+ *  Load IA32_RTIT_CTL
4ec855
+ *  Clear IA32_RTIT_CTL
4ec855
+ *  Advanced VM-exit information for EPT violations
4ec855
+ *  Sub-page write permissions
4ec855
+ *  PT in VMX operation
4ec855
+ */
4ec855
+
4ec855
 static X86CPUDefinition builtin_x86_defs[] = {
4ec855
     {
4ec855
         /* qemu64 is the default CPU model for all *-rhel7.* machine-types.
4ec855
@@ -1769,6 +1797,24 @@ static X86CPUDefinition builtin_x86_defs[] = {
4ec855
             CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
4ec855
         .features[FEAT_8000_0001_ECX] =
4ec855
             CPUID_EXT3_LAHF_LM,
4ec855
+        .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS,
4ec855
+        .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
4ec855
+        .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
4ec855
+        .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
4ec855
+        .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
4ec855
+             VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS,
4ec855
+        .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
4ec855
+             VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
4ec855
+             VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
4ec855
+             VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
4ec855
+             VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
4ec855
+             VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
4ec855
+             VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
4ec855
+             VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
4ec855
+             VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
4ec855
+             VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
4ec855
+        .features[FEAT_VMX_SECONDARY_CTLS] =
4ec855
+             VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES,
4ec855
         .xlevel = 0x80000008,
4ec855
         .model_id = "Intel(R) Core(TM)2 Duo CPU     T7700  @ 2.40GHz",
4ec855
     },
4ec855
@@ -1796,6 +1842,20 @@ static X86CPUDefinition builtin_x86_defs[] = {
4ec855
                     CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
4ec855
         .features[FEAT_8000_0001_ECX] =
4ec855
             0,
4ec855
+        /* VMX features from Cedar Mill/Prescott */
4ec855
+        .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
4ec855
+        .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
4ec855
+        .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
4ec855
+        .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
4ec855
+             VMX_PIN_BASED_NMI_EXITING,
4ec855
+        .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
4ec855
+             VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
4ec855
+             VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
4ec855
+             VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
4ec855
+             VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
4ec855
+             VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
4ec855
+             VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
4ec855
+             VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING,
4ec855
         .xlevel = 0x80000008,
4ec855
         .model_id = "Common KVM processor"
4ec855
     },
4ec855
@@ -1827,6 +1887,19 @@ static X86CPUDefinition builtin_x86_defs[] = {
4ec855
             CPUID_EXT_SSE3,
4ec855
         .features[FEAT_8000_0001_ECX] =
4ec855
             0,
4ec855
+        /* VMX features from Yonah */
4ec855
+        .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
4ec855
+        .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
4ec855
+        .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
4ec855
+        .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
4ec855
+             VMX_PIN_BASED_NMI_EXITING,
4ec855
+        .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
4ec855
+             VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
4ec855
+             VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
4ec855
+             VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
4ec855
+             VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING |
4ec855
+             VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING |
4ec855
+             VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS,
4ec855
         .xlevel = 0x80000008,
4ec855
         .model_id = "Common 32-bit KVM processor"
4ec855
     },
4ec855
@@ -1848,6 +1921,18 @@ static X86CPUDefinition builtin_x86_defs[] = {
4ec855
             CPUID_EXT_SSE3 | CPUID_EXT_MONITOR,
4ec855
         .features[FEAT_8000_0001_EDX] =
4ec855
             CPUID_EXT2_NX,
4ec855
+        .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
4ec855
+        .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
4ec855
+        .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
4ec855
+        .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
4ec855
+             VMX_PIN_BASED_NMI_EXITING,
4ec855
+        .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
4ec855
+             VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
4ec855
+             VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
4ec855
+             VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
4ec855
+             VMX_CPU_BASED_MOV_DR_EXITING | VMX_CPU_BASED_UNCOND_IO_EXITING |
4ec855
+             VMX_CPU_BASED_USE_IO_BITMAPS | VMX_CPU_BASED_MONITOR_EXITING |
4ec855
+             VMX_CPU_BASED_PAUSE_EXITING | VMX_CPU_BASED_USE_MSR_BITMAPS,
4ec855
         .xlevel = 0x80000008,
4ec855
         .model_id = "Genuine Intel(R) CPU           T2600  @ 2.16GHz",
4ec855
     },
4ec855
@@ -1977,6 +2062,24 @@ static X86CPUDefinition builtin_x86_defs[] = {
4ec855
             CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
4ec855
         .features[FEAT_8000_0001_ECX] =
4ec855
             CPUID_EXT3_LAHF_LM,
4ec855
+        .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS,
4ec855
+        .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE,
4ec855
+        .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT,
4ec855
+        .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
4ec855
+        .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
4ec855
+             VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS,
4ec855
+        .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
4ec855
+             VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
4ec855
+             VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
4ec855
+             VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
4ec855
+             VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
4ec855
+             VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
4ec855
+             VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
4ec855
+             VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
4ec855
+             VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
4ec855
+             VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
4ec855
+        .features[FEAT_VMX_SECONDARY_CTLS] =
4ec855
+             VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES,
4ec855
         .xlevel = 0x80000008,
4ec855
         .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
4ec855
     },
4ec855
@@ -2000,6 +2103,27 @@ static X86CPUDefinition builtin_x86_defs[] = {
4ec855
             CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
4ec855
         .features[FEAT_8000_0001_ECX] =
4ec855
             CPUID_EXT3_LAHF_LM,
4ec855
+        .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS,
4ec855
+        .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
4ec855
+             VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
4ec855
+        .features[FEAT_VMX_EXIT_CTLS] = VMX_VM_EXIT_ACK_INTR_ON_EXIT |
4ec855
+             VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
4ec855
+        .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
4ec855
+        .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
4ec855
+             VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS,
4ec855
+        .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
4ec855
+             VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
4ec855
+             VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
4ec855
+             VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
4ec855
+             VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
4ec855
+             VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
4ec855
+             VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
4ec855
+             VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
4ec855
+             VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
4ec855
+             VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
4ec855
+        .features[FEAT_VMX_SECONDARY_CTLS] =
4ec855
+             VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
4ec855
+             VMX_SECONDARY_EXEC_WBINVD_EXITING,
4ec855
         .xlevel = 0x80000008,
4ec855
         .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
4ec855
     },
4ec855
@@ -2023,6 +2147,46 @@ static X86CPUDefinition builtin_x86_defs[] = {
4ec855
             CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
4ec855
         .features[FEAT_8000_0001_ECX] =
4ec855
             CPUID_EXT3_LAHF_LM,
4ec855
+        .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
4ec855
+             MSR_VMX_BASIC_TRUE_CTLS,
4ec855
+        .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
4ec855
+             VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
4ec855
+             VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
4ec855
+        .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
4ec855
+             MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
4ec855
+             MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
4ec855
+             MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
4ec855
+             MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
4ec855
+             MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
4ec855
+             MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
4ec855
+        .features[FEAT_VMX_EXIT_CTLS] =
4ec855
+             VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
4ec855
+             VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
4ec855
+             VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
4ec855
+             VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
4ec855
+             VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
4ec855
+        .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT,
4ec855
+        .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
4ec855
+             VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
4ec855
+             VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
4ec855
+        .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
4ec855
+             VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
4ec855
+             VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
4ec855
+             VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
4ec855
+             VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
4ec855
+             VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
4ec855
+             VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
4ec855
+             VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
4ec855
+             VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
4ec855
+             VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
4ec855
+             VMX_CPU_BASED_MONITOR_TRAP_FLAG |
4ec855
+             VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
4ec855
+        .features[FEAT_VMX_SECONDARY_CTLS] =
4ec855
+             VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
4ec855
+             VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
4ec855
+             VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
4ec855
+             VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
4ec855
+             VMX_SECONDARY_EXEC_ENABLE_VPID,
4ec855
         .xlevel = 0x80000008,
4ec855
         .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
4ec855
     },
4ec855
@@ -2074,6 +2238,47 @@ static X86CPUDefinition builtin_x86_defs[] = {
4ec855
             CPUID_EXT3_LAHF_LM,
4ec855
         .features[FEAT_6_EAX] =
4ec855
             CPUID_6_EAX_ARAT,
4ec855
+        .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
4ec855
+             MSR_VMX_BASIC_TRUE_CTLS,
4ec855
+        .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
4ec855
+             VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
4ec855
+             VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
4ec855
+        .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
4ec855
+             MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
4ec855
+             MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
4ec855
+             MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
4ec855
+             MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
4ec855
+             MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
4ec855
+             MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
4ec855
+        .features[FEAT_VMX_EXIT_CTLS] =
4ec855
+             VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
4ec855
+             VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
4ec855
+             VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
4ec855
+             VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
4ec855
+             VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
4ec855
+        .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
4ec855
+             MSR_VMX_MISC_STORE_LMA,
4ec855
+        .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
4ec855
+             VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
4ec855
+             VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
4ec855
+        .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
4ec855
+             VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
4ec855
+             VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
4ec855
+             VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
4ec855
+             VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
4ec855
+             VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
4ec855
+             VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
4ec855
+             VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
4ec855
+             VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
4ec855
+             VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
4ec855
+             VMX_CPU_BASED_MONITOR_TRAP_FLAG |
4ec855
+             VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
4ec855
+        .features[FEAT_VMX_SECONDARY_CTLS] =
4ec855
+             VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
4ec855
+             VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
4ec855
+             VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
4ec855
+             VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
4ec855
+             VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST,
4ec855
         .xlevel = 0x80000008,
4ec855
         .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
4ec855
     },
4ec855
@@ -2133,6 +2338,47 @@ static X86CPUDefinition builtin_x86_defs[] = {
4ec855
             CPUID_XSAVE_XSAVEOPT,
4ec855
         .features[FEAT_6_EAX] =
4ec855
             CPUID_6_EAX_ARAT,
4ec855
+        .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
4ec855
+             MSR_VMX_BASIC_TRUE_CTLS,
4ec855
+        .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
4ec855
+             VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
4ec855
+             VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
4ec855
+        .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
4ec855
+             MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
4ec855
+             MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
4ec855
+             MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
4ec855
+             MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
4ec855
+             MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
4ec855
+             MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
4ec855
+        .features[FEAT_VMX_EXIT_CTLS] =
4ec855
+             VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
4ec855
+             VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
4ec855
+             VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
4ec855
+             VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
4ec855
+             VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
4ec855
+        .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
4ec855
+             MSR_VMX_MISC_STORE_LMA,
4ec855
+        .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
4ec855
+             VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
4ec855
+             VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
4ec855
+        .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
4ec855
+             VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
4ec855
+             VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
4ec855
+             VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
4ec855
+             VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
4ec855
+             VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
4ec855
+             VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
4ec855
+             VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
4ec855
+             VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
4ec855
+             VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
4ec855
+             VMX_CPU_BASED_MONITOR_TRAP_FLAG |
4ec855
+             VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
4ec855
+        .features[FEAT_VMX_SECONDARY_CTLS] =
4ec855
+             VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
4ec855
+             VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
4ec855
+             VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
4ec855
+             VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
4ec855
+             VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST,
4ec855
         .xlevel = 0x80000008,
4ec855
         .model_id = "Intel Xeon E312xx (Sandy Bridge)",
4ec855
     },
4ec855
@@ -2200,6 +2446,50 @@ static X86CPUDefinition builtin_x86_defs[] = {
4ec855
             CPUID_XSAVE_XSAVEOPT,
4ec855
         .features[FEAT_6_EAX] =
4ec855
             CPUID_6_EAX_ARAT,
4ec855
+        .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
4ec855
+             MSR_VMX_BASIC_TRUE_CTLS,
4ec855
+        .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
4ec855
+             VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
4ec855
+             VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
4ec855
+        .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
4ec855
+             MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
4ec855
+             MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
4ec855
+             MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
4ec855
+             MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
4ec855
+             MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
4ec855
+             MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS,
4ec855
+        .features[FEAT_VMX_EXIT_CTLS] =
4ec855
+             VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
4ec855
+             VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
4ec855
+             VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
4ec855
+             VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
4ec855
+             VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
4ec855
+        .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
4ec855
+             MSR_VMX_MISC_STORE_LMA,
4ec855
+        .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
4ec855
+             VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
4ec855
+             VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
4ec855
+        .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
4ec855
+             VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
4ec855
+             VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
4ec855
+             VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
4ec855
+             VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
4ec855
+             VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
4ec855
+             VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
4ec855
+             VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
4ec855
+             VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
4ec855
+             VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
4ec855
+             VMX_CPU_BASED_MONITOR_TRAP_FLAG |
4ec855
+             VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
4ec855
+        .features[FEAT_VMX_SECONDARY_CTLS] =
4ec855
+             VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
4ec855
+             VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
4ec855
+             VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
4ec855
+             VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
4ec855
+             VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
4ec855
+             VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
4ec855
+             VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
4ec855
+             VMX_SECONDARY_EXEC_RDRAND_EXITING,
4ec855
         .xlevel = 0x80000008,
4ec855
         .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
4ec855
     },
4ec855
@@ -2347,6 +2637,52 @@ static X86CPUDefinition builtin_x86_defs[] = {
4ec855
             CPUID_XSAVE_XSAVEOPT,
4ec855
         .features[FEAT_6_EAX] =
4ec855
             CPUID_6_EAX_ARAT,
4ec855
+        .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
4ec855
+             MSR_VMX_BASIC_TRUE_CTLS,
4ec855
+        .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
4ec855
+             VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
4ec855
+             VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
4ec855
+        .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
4ec855
+             MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
4ec855
+             MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
4ec855
+             MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
4ec855
+             MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
4ec855
+             MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
4ec855
+             MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
4ec855
+        .features[FEAT_VMX_EXIT_CTLS] =
4ec855
+             VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
4ec855
+             VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
4ec855
+             VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
4ec855
+             VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
4ec855
+             VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
4ec855
+        .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
4ec855
+             MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
4ec855
+        .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
4ec855
+             VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
4ec855
+             VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
4ec855
+        .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
4ec855
+             VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
4ec855
+             VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
4ec855
+             VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
4ec855
+             VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
4ec855
+             VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
4ec855
+             VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
4ec855
+             VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
4ec855
+             VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
4ec855
+             VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
4ec855
+             VMX_CPU_BASED_MONITOR_TRAP_FLAG |
4ec855
+             VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
4ec855
+        .features[FEAT_VMX_SECONDARY_CTLS] =
4ec855
+             VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
4ec855
+             VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
4ec855
+             VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
4ec855
+             VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
4ec855
+             VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
4ec855
+             VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
4ec855
+             VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
4ec855
+             VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
4ec855
+             VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS,
4ec855
+        .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
4ec855
         .xlevel = 0x80000008,
4ec855
         .model_id = "Intel Core Processor (Haswell)",
4ec855
     },
4ec855
@@ -2502,6 +2838,53 @@ static X86CPUDefinition builtin_x86_defs[] = {
4ec855
             CPUID_XSAVE_XSAVEOPT,
4ec855
         .features[FEAT_6_EAX] =
4ec855
             CPUID_6_EAX_ARAT,
4ec855
+        .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
4ec855
+             MSR_VMX_BASIC_TRUE_CTLS,
4ec855
+        .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
4ec855
+             VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
4ec855
+             VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
4ec855
+        .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
4ec855
+             MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
4ec855
+             MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
4ec855
+             MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
4ec855
+             MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
4ec855
+             MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
4ec855
+             MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
4ec855
+        .features[FEAT_VMX_EXIT_CTLS] =
4ec855
+             VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
4ec855
+             VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
4ec855
+             VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
4ec855
+             VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
4ec855
+             VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
4ec855
+        .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
4ec855
+             MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
4ec855
+        .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
4ec855
+             VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
4ec855
+             VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
4ec855
+        .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
4ec855
+             VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
4ec855
+             VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
4ec855
+             VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
4ec855
+             VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
4ec855
+             VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
4ec855
+             VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
4ec855
+             VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
4ec855
+             VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
4ec855
+             VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
4ec855
+             VMX_CPU_BASED_MONITOR_TRAP_FLAG |
4ec855
+             VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
4ec855
+        .features[FEAT_VMX_SECONDARY_CTLS] =
4ec855
+             VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
4ec855
+             VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
4ec855
+             VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
4ec855
+             VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
4ec855
+             VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
4ec855
+             VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
4ec855
+             VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
4ec855
+             VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
4ec855
+             VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
4ec855
+             VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
4ec855
+        .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
4ec855
         .xlevel = 0x80000008,
4ec855
         .model_id = "Intel Core Processor (Broadwell)",
4ec855
     },
4ec855
@@ -2587,6 +2970,51 @@ static X86CPUDefinition builtin_x86_defs[] = {
4ec855
             CPUID_XSAVE_XGETBV1,
4ec855
         .features[FEAT_6_EAX] =
4ec855
             CPUID_6_EAX_ARAT,
4ec855
+        /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
4ec855
+        .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
4ec855
+             MSR_VMX_BASIC_TRUE_CTLS,
4ec855
+        .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
4ec855
+             VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
4ec855
+             VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
4ec855
+        .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
4ec855
+             MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
4ec855
+             MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
4ec855
+             MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
4ec855
+             MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
4ec855
+             MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
4ec855
+             MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
4ec855
+        .features[FEAT_VMX_EXIT_CTLS] =
4ec855
+             VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
4ec855
+             VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
4ec855
+             VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
4ec855
+             VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
4ec855
+             VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
4ec855
+        .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
4ec855
+             MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
4ec855
+        .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
4ec855
+             VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
4ec855
+             VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
4ec855
+        .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
4ec855
+             VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
4ec855
+             VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
4ec855
+             VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
4ec855
+             VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
4ec855
+             VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
4ec855
+             VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
4ec855
+             VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
4ec855
+             VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
4ec855
+             VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
4ec855
+             VMX_CPU_BASED_MONITOR_TRAP_FLAG |
4ec855
+             VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
4ec855
+        .features[FEAT_VMX_SECONDARY_CTLS] =
4ec855
+             VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
4ec855
+             VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
4ec855
+             VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
4ec855
+             VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
4ec855
+             VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
4ec855
+             VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
4ec855
+             VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
4ec855
+        .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
4ec855
         .xlevel = 0x80000008,
4ec855
         .model_id = "Intel Core Processor (Skylake)",
4ec855
     },
4ec855
@@ -2682,6 +3110,54 @@ static X86CPUDefinition builtin_x86_defs[] = {
4ec855
             CPUID_XSAVE_XGETBV1,
4ec855
         .features[FEAT_6_EAX] =
4ec855
             CPUID_6_EAX_ARAT,
4ec855
+        /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
4ec855
+        .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
4ec855
+             MSR_VMX_BASIC_TRUE_CTLS,
4ec855
+        .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
4ec855
+             VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
4ec855
+             VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
4ec855
+        .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
4ec855
+             MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
4ec855
+             MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
4ec855
+             MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
4ec855
+             MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
4ec855
+             MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
4ec855
+             MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
4ec855
+        .features[FEAT_VMX_EXIT_CTLS] =
4ec855
+             VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
4ec855
+             VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
4ec855
+             VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
4ec855
+             VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
4ec855
+             VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
4ec855
+        .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
4ec855
+             MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
4ec855
+        .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
4ec855
+             VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
4ec855
+             VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
4ec855
+        .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
4ec855
+             VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
4ec855
+             VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
4ec855
+             VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
4ec855
+             VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
4ec855
+             VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
4ec855
+             VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
4ec855
+             VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
4ec855
+             VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
4ec855
+             VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
4ec855
+             VMX_CPU_BASED_MONITOR_TRAP_FLAG |
4ec855
+             VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
4ec855
+        .features[FEAT_VMX_SECONDARY_CTLS] =
4ec855
+             VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
4ec855
+             VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
4ec855
+             VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
4ec855
+             VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
4ec855
+             VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
4ec855
+             VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
4ec855
+             VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
4ec855
+             VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
4ec855
+             VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
4ec855
+             VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
4ec855
+        .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
4ec855
         .xlevel = 0x80000008,
4ec855
         .model_id = "Intel Xeon Processor (Skylake)",
4ec855
     },
4ec855
@@ -2785,6 +3261,54 @@ static X86CPUDefinition builtin_x86_defs[] = {
4ec855
             CPUID_XSAVE_XGETBV1,
4ec855
         .features[FEAT_6_EAX] =
4ec855
             CPUID_6_EAX_ARAT,
4ec855
+        /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
4ec855
+        .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
4ec855
+             MSR_VMX_BASIC_TRUE_CTLS,
4ec855
+        .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
4ec855
+             VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
4ec855
+             VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
4ec855
+        .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
4ec855
+             MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
4ec855
+             MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
4ec855
+             MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
4ec855
+             MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
4ec855
+             MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
4ec855
+             MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
4ec855
+        .features[FEAT_VMX_EXIT_CTLS] =
4ec855
+             VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
4ec855
+             VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
4ec855
+             VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
4ec855
+             VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
4ec855
+             VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
4ec855
+        .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
4ec855
+             MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
4ec855
+        .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
4ec855
+             VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
4ec855
+             VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
4ec855
+        .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
4ec855
+             VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
4ec855
+             VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
4ec855
+             VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
4ec855
+             VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
4ec855
+             VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
4ec855
+             VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
4ec855
+             VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
4ec855
+             VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
4ec855
+             VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
4ec855
+             VMX_CPU_BASED_MONITOR_TRAP_FLAG |
4ec855
+             VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
4ec855
+        .features[FEAT_VMX_SECONDARY_CTLS] =
4ec855
+             VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
4ec855
+             VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
4ec855
+             VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
4ec855
+             VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
4ec855
+             VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
4ec855
+             VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
4ec855
+             VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
4ec855
+             VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
4ec855
+             VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
4ec855
+             VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
4ec855
+        .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
4ec855
         .xlevel = 0x80000008,
4ec855
         .model_id = "Intel Xeon Processor (Cascadelake)",
4ec855
     },
4ec855
@@ -2840,6 +3364,51 @@ static X86CPUDefinition builtin_x86_defs[] = {
4ec855
             CPUID_XSAVE_XGETBV1,
4ec855
         .features[FEAT_6_EAX] =
4ec855
             CPUID_6_EAX_ARAT,
4ec855
+        /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
4ec855
+        .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
4ec855
+             MSR_VMX_BASIC_TRUE_CTLS,
4ec855
+        .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
4ec855
+             VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
4ec855
+             VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
4ec855
+        .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
4ec855
+             MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
4ec855
+             MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
4ec855
+             MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
4ec855
+             MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
4ec855
+             MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
4ec855
+             MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
4ec855
+        .features[FEAT_VMX_EXIT_CTLS] =
4ec855
+             VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
4ec855
+             VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
4ec855
+             VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
4ec855
+             VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
4ec855
+             VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
4ec855
+        .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
4ec855
+             MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
4ec855
+        .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
4ec855
+             VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
4ec855
+             VMX_PIN_BASED_VMX_PREEMPTION_TIMER,
4ec855
+        .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
4ec855
+             VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
4ec855
+             VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
4ec855
+             VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
4ec855
+             VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
4ec855
+             VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
4ec855
+             VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
4ec855
+             VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
4ec855
+             VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
4ec855
+             VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
4ec855
+             VMX_CPU_BASED_MONITOR_TRAP_FLAG |
4ec855
+             VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
4ec855
+        .features[FEAT_VMX_SECONDARY_CTLS] =
4ec855
+             VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
4ec855
+             VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
4ec855
+             VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
4ec855
+             VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
4ec855
+             VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
4ec855
+             VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
4ec855
+             VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
4ec855
+        .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
4ec855
         .xlevel = 0x80000008,
4ec855
         .model_id = "Intel Core Processor (Icelake)",
4ec855
     },
4ec855
@@ -2898,6 +3467,54 @@ static X86CPUDefinition builtin_x86_defs[] = {
4ec855
             CPUID_XSAVE_XGETBV1,
4ec855
         .features[FEAT_6_EAX] =
4ec855
             CPUID_6_EAX_ARAT,
4ec855
+        /* Missing: Mode-based execute control (XS/XU), processor tracing, TSC scaling */
4ec855
+        .features[FEAT_VMX_BASIC] = MSR_VMX_BASIC_INS_OUTS |
4ec855
+             MSR_VMX_BASIC_TRUE_CTLS,
4ec855
+        .features[FEAT_VMX_ENTRY_CTLS] = VMX_VM_ENTRY_IA32E_MODE |
4ec855
+             VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL | VMX_VM_ENTRY_LOAD_IA32_PAT |
4ec855
+             VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS | VMX_VM_ENTRY_LOAD_IA32_EFER,
4ec855
+        .features[FEAT_VMX_EPT_VPID_CAPS] = MSR_VMX_EPT_EXECONLY |
4ec855
+             MSR_VMX_EPT_PAGE_WALK_LENGTH_4 | MSR_VMX_EPT_WB | MSR_VMX_EPT_2MB |
4ec855
+             MSR_VMX_EPT_1GB | MSR_VMX_EPT_INVEPT |
4ec855
+             MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT | MSR_VMX_EPT_INVEPT_ALL_CONTEXT |
4ec855
+             MSR_VMX_EPT_INVVPID | MSR_VMX_EPT_INVVPID_SINGLE_ADDR |
4ec855
+             MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT | MSR_VMX_EPT_INVVPID_ALL_CONTEXT |
4ec855
+             MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS | MSR_VMX_EPT_AD_BITS,
4ec855
+        .features[FEAT_VMX_EXIT_CTLS] =
4ec855
+             VMX_VM_EXIT_ACK_INTR_ON_EXIT | VMX_VM_EXIT_SAVE_DEBUG_CONTROLS |
4ec855
+             VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
4ec855
+             VMX_VM_EXIT_LOAD_IA32_PAT | VMX_VM_EXIT_LOAD_IA32_EFER |
4ec855
+             VMX_VM_EXIT_SAVE_IA32_PAT | VMX_VM_EXIT_SAVE_IA32_EFER |
4ec855
+             VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER,
4ec855
+        .features[FEAT_VMX_MISC] = MSR_VMX_MISC_ACTIVITY_HLT |
4ec855
+             MSR_VMX_MISC_STORE_LMA | MSR_VMX_MISC_VMWRITE_VMEXIT,
4ec855
+        .features[FEAT_VMX_PINBASED_CTLS] = VMX_PIN_BASED_EXT_INTR_MASK |
4ec855
+             VMX_PIN_BASED_NMI_EXITING | VMX_PIN_BASED_VIRTUAL_NMIS |
4ec855
+             VMX_PIN_BASED_VMX_PREEMPTION_TIMER | VMX_PIN_BASED_POSTED_INTR,
4ec855
+        .features[FEAT_VMX_PROCBASED_CTLS] = VMX_CPU_BASED_VIRTUAL_INTR_PENDING |
4ec855
+             VMX_CPU_BASED_USE_TSC_OFFSETING | VMX_CPU_BASED_HLT_EXITING |
4ec855
+             VMX_CPU_BASED_INVLPG_EXITING | VMX_CPU_BASED_MWAIT_EXITING |
4ec855
+             VMX_CPU_BASED_RDPMC_EXITING | VMX_CPU_BASED_RDTSC_EXITING |
4ec855
+             VMX_CPU_BASED_CR8_LOAD_EXITING | VMX_CPU_BASED_CR8_STORE_EXITING |
4ec855
+             VMX_CPU_BASED_TPR_SHADOW | VMX_CPU_BASED_MOV_DR_EXITING |
4ec855
+             VMX_CPU_BASED_UNCOND_IO_EXITING | VMX_CPU_BASED_USE_IO_BITMAPS |
4ec855
+             VMX_CPU_BASED_MONITOR_EXITING | VMX_CPU_BASED_PAUSE_EXITING |
4ec855
+             VMX_CPU_BASED_VIRTUAL_NMI_PENDING | VMX_CPU_BASED_USE_MSR_BITMAPS |
4ec855
+             VMX_CPU_BASED_CR3_LOAD_EXITING | VMX_CPU_BASED_CR3_STORE_EXITING |
4ec855
+             VMX_CPU_BASED_MONITOR_TRAP_FLAG |
4ec855
+             VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS,
4ec855
+        .features[FEAT_VMX_SECONDARY_CTLS] =
4ec855
+             VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
4ec855
+             VMX_SECONDARY_EXEC_WBINVD_EXITING | VMX_SECONDARY_EXEC_ENABLE_EPT |
4ec855
+             VMX_SECONDARY_EXEC_DESC | VMX_SECONDARY_EXEC_RDTSCP |
4ec855
+             VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
4ec855
+             VMX_SECONDARY_EXEC_ENABLE_VPID | VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST |
4ec855
+             VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT |
4ec855
+             VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
4ec855
+             VMX_SECONDARY_EXEC_RDRAND_EXITING | VMX_SECONDARY_EXEC_ENABLE_INVPCID |
4ec855
+             VMX_SECONDARY_EXEC_ENABLE_VMFUNC | VMX_SECONDARY_EXEC_SHADOW_VMCS |
4ec855
+             VMX_SECONDARY_EXEC_RDSEED_EXITING | VMX_SECONDARY_EXEC_ENABLE_PML,
4ec855
+        .features[FEAT_VMX_VMFUNC] = MSR_VMX_VMFUNC_EPT_SWITCHING,
4ec855
         .xlevel = 0x80000008,
4ec855
         .model_id = "Intel Xeon Processor (Icelake)",
4ec855
     },
4ec855
-- 
4ec855
1.8.3.1
4ec855