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From 968d0586936c356ca19f6f3b659ab094a2825374 Mon Sep 17 00:00:00 2001
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From: Paolo Bonzini <pbonzini@redhat.com>
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Date: Fri, 22 Nov 2019 11:53:42 +0000
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Subject: [PATCH 09/16] target/i386: add VMX definitions
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RH-Author: Paolo Bonzini <pbonzini@redhat.com>
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Message-id: <20191122115348.25000-10-pbonzini@redhat.com>
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Patchwork-id: 92604
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O-Subject: [RHEL8.2/rhel qemu-kvm PATCH 09/15] target/i386: add VMX definitions
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Bugzilla: 1689270
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RH-Acked-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
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RH-Acked-by: Eduardo Habkost <ehabkost@redhat.com>
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RH-Acked-by: Maxim Levitsky <mlevitsk@redhat.com>
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These will be used to compile the list of VMX features for named
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CPU models, and/or by the code that sets up the VMX MSRs.
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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(cherry picked from commit 704798add83be4ac868ffcb495480065fb665794)
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RHEL: context
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Signed-off-by: Danilo C. L. de Paula <ddepaula@redhat.com>
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---
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target/i386/cpu.h | 130 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
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1 file changed, 130 insertions(+)
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diff --git a/target/i386/cpu.h b/target/i386/cpu.h
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index edba84e..2d1f247 100644
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--- a/target/i386/cpu.h
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+++ b/target/i386/cpu.h
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@@ -459,6 +459,25 @@ typedef enum X86Seg {
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#define MSR_IA32_BNDCFGS 0x00000d90
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#define MSR_IA32_XSS 0x00000da0
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+#define MSR_IA32_VMX_BASIC 0x00000480
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+#define MSR_IA32_VMX_PINBASED_CTLS 0x00000481
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+#define MSR_IA32_VMX_PROCBASED_CTLS 0x00000482
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+#define MSR_IA32_VMX_EXIT_CTLS 0x00000483
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+#define MSR_IA32_VMX_ENTRY_CTLS 0x00000484
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+#define MSR_IA32_VMX_MISC 0x00000485
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+#define MSR_IA32_VMX_CR0_FIXED0 0x00000486
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+#define MSR_IA32_VMX_CR0_FIXED1 0x00000487
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+#define MSR_IA32_VMX_CR4_FIXED0 0x00000488
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+#define MSR_IA32_VMX_CR4_FIXED1 0x00000489
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+#define MSR_IA32_VMX_VMCS_ENUM 0x0000048a
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+#define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b
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+#define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c
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+#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d
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+#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e
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+#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f
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+#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490
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+#define MSR_IA32_VMX_VMFUNC 0x00000491
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+
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#define XSTATE_FP_BIT 0
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#define XSTATE_SSE_BIT 1
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#define XSTATE_YMM_BIT 2
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@@ -749,6 +768,117 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS];
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#define MSR_CORE_CAP_SPLIT_LOCK_DETECT (1U << 5)
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+/* VMX MSR features */
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+#define MSR_VMX_BASIC_VMCS_REVISION_MASK 0x7FFFFFFFull
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+#define MSR_VMX_BASIC_VMXON_REGION_SIZE_MASK (0x00001FFFull << 32)
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+#define MSR_VMX_BASIC_VMCS_MEM_TYPE_MASK (0x003C0000ull << 32)
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+#define MSR_VMX_BASIC_DUAL_MONITOR (1ULL << 49)
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+#define MSR_VMX_BASIC_INS_OUTS (1ULL << 54)
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+#define MSR_VMX_BASIC_TRUE_CTLS (1ULL << 55)
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+
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+#define MSR_VMX_MISC_PREEMPTION_TIMER_SHIFT_MASK 0x1Full
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+#define MSR_VMX_MISC_STORE_LMA (1ULL << 5)
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+#define MSR_VMX_MISC_ACTIVITY_HLT (1ULL << 6)
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+#define MSR_VMX_MISC_ACTIVITY_SHUTDOWN (1ULL << 7)
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+#define MSR_VMX_MISC_ACTIVITY_WAIT_SIPI (1ULL << 8)
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+#define MSR_VMX_MISC_MAX_MSR_LIST_SIZE_MASK 0x0E000000ull
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+#define MSR_VMX_MISC_VMWRITE_VMEXIT (1ULL << 29)
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+#define MSR_VMX_MISC_ZERO_LEN_INJECT (1ULL << 30)
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+
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+#define MSR_VMX_EPT_EXECONLY (1ULL << 0)
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+#define MSR_VMX_EPT_PAGE_WALK_LENGTH_4 (1ULL << 6)
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+#define MSR_VMX_EPT_PAGE_WALK_LENGTH_5 (1ULL << 7)
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+#define MSR_VMX_EPT_UC (1ULL << 8)
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+#define MSR_VMX_EPT_WB (1ULL << 14)
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+#define MSR_VMX_EPT_2MB (1ULL << 16)
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+#define MSR_VMX_EPT_1GB (1ULL << 17)
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+#define MSR_VMX_EPT_INVEPT (1ULL << 20)
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+#define MSR_VMX_EPT_AD_BITS (1ULL << 21)
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+#define MSR_VMX_EPT_ADVANCED_VMEXIT_INFO (1ULL << 22)
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+#define MSR_VMX_EPT_INVEPT_SINGLE_CONTEXT (1ULL << 25)
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+#define MSR_VMX_EPT_INVEPT_ALL_CONTEXT (1ULL << 26)
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+#define MSR_VMX_EPT_INVVPID (1ULL << 32)
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+#define MSR_VMX_EPT_INVVPID_SINGLE_ADDR (1ULL << 40)
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+#define MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT (1ULL << 41)
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+#define MSR_VMX_EPT_INVVPID_ALL_CONTEXT (1ULL << 42)
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+#define MSR_VMX_EPT_INVVPID_SINGLE_CONTEXT_NOGLOBALS (1ULL << 43)
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+
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+#define MSR_VMX_VMFUNC_EPT_SWITCHING (1ULL << 0)
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+
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+
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+/* VMX controls */
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+#define VMX_CPU_BASED_VIRTUAL_INTR_PENDING 0x00000004
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+#define VMX_CPU_BASED_USE_TSC_OFFSETING 0x00000008
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+#define VMX_CPU_BASED_HLT_EXITING 0x00000080
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+#define VMX_CPU_BASED_INVLPG_EXITING 0x00000200
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+#define VMX_CPU_BASED_MWAIT_EXITING 0x00000400
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+#define VMX_CPU_BASED_RDPMC_EXITING 0x00000800
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+#define VMX_CPU_BASED_RDTSC_EXITING 0x00001000
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+#define VMX_CPU_BASED_CR3_LOAD_EXITING 0x00008000
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+#define VMX_CPU_BASED_CR3_STORE_EXITING 0x00010000
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+#define VMX_CPU_BASED_CR8_LOAD_EXITING 0x00080000
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+#define VMX_CPU_BASED_CR8_STORE_EXITING 0x00100000
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+#define VMX_CPU_BASED_TPR_SHADOW 0x00200000
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+#define VMX_CPU_BASED_VIRTUAL_NMI_PENDING 0x00400000
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+#define VMX_CPU_BASED_MOV_DR_EXITING 0x00800000
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+#define VMX_CPU_BASED_UNCOND_IO_EXITING 0x01000000
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+#define VMX_CPU_BASED_USE_IO_BITMAPS 0x02000000
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+#define VMX_CPU_BASED_MONITOR_TRAP_FLAG 0x08000000
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+#define VMX_CPU_BASED_USE_MSR_BITMAPS 0x10000000
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+#define VMX_CPU_BASED_MONITOR_EXITING 0x20000000
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+#define VMX_CPU_BASED_PAUSE_EXITING 0x40000000
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+#define VMX_CPU_BASED_ACTIVATE_SECONDARY_CONTROLS 0x80000000
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+
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+#define VMX_SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001
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+#define VMX_SECONDARY_EXEC_ENABLE_EPT 0x00000002
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+#define VMX_SECONDARY_EXEC_DESC 0x00000004
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+#define VMX_SECONDARY_EXEC_RDTSCP 0x00000008
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+#define VMX_SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE 0x00000010
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+#define VMX_SECONDARY_EXEC_ENABLE_VPID 0x00000020
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+#define VMX_SECONDARY_EXEC_WBINVD_EXITING 0x00000040
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+#define VMX_SECONDARY_EXEC_UNRESTRICTED_GUEST 0x00000080
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+#define VMX_SECONDARY_EXEC_APIC_REGISTER_VIRT 0x00000100
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+#define VMX_SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY 0x00000200
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+#define VMX_SECONDARY_EXEC_PAUSE_LOOP_EXITING 0x00000400
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+#define VMX_SECONDARY_EXEC_RDRAND_EXITING 0x00000800
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+#define VMX_SECONDARY_EXEC_ENABLE_INVPCID 0x00001000
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+#define VMX_SECONDARY_EXEC_ENABLE_VMFUNC 0x00002000
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+#define VMX_SECONDARY_EXEC_SHADOW_VMCS 0x00004000
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+#define VMX_SECONDARY_EXEC_ENCLS_EXITING 0x00008000
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+#define VMX_SECONDARY_EXEC_RDSEED_EXITING 0x00010000
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+#define VMX_SECONDARY_EXEC_ENABLE_PML 0x00020000
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+#define VMX_SECONDARY_EXEC_XSAVES 0x00100000
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+
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+#define VMX_PIN_BASED_EXT_INTR_MASK 0x00000001
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+#define VMX_PIN_BASED_NMI_EXITING 0x00000008
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+#define VMX_PIN_BASED_VIRTUAL_NMIS 0x00000020
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+#define VMX_PIN_BASED_VMX_PREEMPTION_TIMER 0x00000040
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+#define VMX_PIN_BASED_POSTED_INTR 0x00000080
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+
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+#define VMX_VM_EXIT_SAVE_DEBUG_CONTROLS 0x00000004
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+#define VMX_VM_EXIT_HOST_ADDR_SPACE_SIZE 0x00000200
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+#define VMX_VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL 0x00001000
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+#define VMX_VM_EXIT_ACK_INTR_ON_EXIT 0x00008000
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+#define VMX_VM_EXIT_SAVE_IA32_PAT 0x00040000
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+#define VMX_VM_EXIT_LOAD_IA32_PAT 0x00080000
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+#define VMX_VM_EXIT_SAVE_IA32_EFER 0x00100000
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+#define VMX_VM_EXIT_LOAD_IA32_EFER 0x00200000
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+#define VMX_VM_EXIT_SAVE_VMX_PREEMPTION_TIMER 0x00400000
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+#define VMX_VM_EXIT_CLEAR_BNDCFGS 0x00800000
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+#define VMX_VM_EXIT_PT_CONCEAL_PIP 0x01000000
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+#define VMX_VM_EXIT_CLEAR_IA32_RTIT_CTL 0x02000000
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+
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+#define VMX_VM_ENTRY_LOAD_DEBUG_CONTROLS 0x00000004
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+#define VMX_VM_ENTRY_IA32E_MODE 0x00000200
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+#define VMX_VM_ENTRY_SMM 0x00000400
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+#define VMX_VM_ENTRY_DEACT_DUAL_MONITOR 0x00000800
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+#define VMX_VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL 0x00002000
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+#define VMX_VM_ENTRY_LOAD_IA32_PAT 0x00004000
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+#define VMX_VM_ENTRY_LOAD_IA32_EFER 0x00008000
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+#define VMX_VM_ENTRY_LOAD_BNDCFGS 0x00010000
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+#define VMX_VM_ENTRY_PT_CONCEAL_PIP 0x00020000
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+#define VMX_VM_ENTRY_LOAD_IA32_RTIT_CTL 0x00040000
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+
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#ifndef HYPERV_SPINLOCK_NEVER_RETRY
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#define HYPERV_SPINLOCK_NEVER_RETRY 0xFFFFFFFF
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#endif
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--
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1.8.3.1
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