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Blame SOURCES/kvm-target-i386-Add-support-for-save-load-IA32_UMWAIT_CO.patch

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From 9c3757a2d7302918456da459a8d188bb41299891 Mon Sep 17 00:00:00 2001
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From: Tao Xu <tao3.xu@intel.com>
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Date: Fri, 11 Oct 2019 15:41:03 +0800
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Subject: [PATCH 11/11] target/i386: Add support for save/load
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 IA32_UMWAIT_CONTROL MSR
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RH-Author: plai@redhat.com
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Message-id: <1574797015-32564-8-git-send-email-plai@redhat.com>
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Patchwork-id: 92693
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O-Subject: [RHEL8.2 qemu-kvm PATCH 7/7] target/i386: Add support for save/load IA32_UMWAIT_CONTROL MSR
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Bugzilla: 1634827
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RH-Acked-by: Eduardo Habkost <ehabkost@redhat.com>
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RH-Acked-by: Michael S. Tsirkin <mst@redhat.com>
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RH-Acked-by: Igor Mammedov <imammedo@redhat.com>
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UMWAIT and TPAUSE instructions use 32bits IA32_UMWAIT_CONTROL at MSR
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index E1H to determines the maximum time in TSC-quanta that the processor
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can reside in either C0.1 or C0.2.
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This patch is to Add support for save/load IA32_UMWAIT_CONTROL MSR in
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guest.
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Co-developed-by: Jingqi Liu <jingqi.liu@intel.com>
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Signed-off-by: Jingqi Liu <jingqi.liu@intel.com>
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Signed-off-by: Tao Xu <tao3.xu@intel.com>
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Message-Id: <20191011074103.30393-3-tao3.xu@intel.com>
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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Signed-off-by: Danilo C. L. de Paula <ddepaula@redhat.com>
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---
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 target/i386/cpu.h     |  2 ++
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 target/i386/kvm.c     | 13 +++++++++++++
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 target/i386/machine.c | 20 ++++++++++++++++++++
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 3 files changed, 35 insertions(+)
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diff --git a/target/i386/cpu.h b/target/i386/cpu.h
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index fac98aa..ecbe4f0 100644
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--- a/target/i386/cpu.h
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+++ b/target/i386/cpu.h
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@@ -461,6 +461,7 @@ typedef enum X86Seg {
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 #define MSR_IA32_BNDCFGS                0x00000d90
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 #define MSR_IA32_XSS                    0x00000da0
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+#define MSR_IA32_UMWAIT_CONTROL         0xe1
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 #define MSR_IA32_VMX_BASIC              0x00000480
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 #define MSR_IA32_VMX_PINBASED_CTLS      0x00000481
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@@ -1510,6 +1511,7 @@ typedef struct CPUX86State {
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     uint16_t fpregs_format_vmstate;
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     uint64_t xss;
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+    uint32_t umwait;
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     TPRAccess tpr_access_type;
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 } CPUX86State;
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diff --git a/target/i386/kvm.c b/target/i386/kvm.c
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index 0fd5650..ad58bfb 100644
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--- a/target/i386/kvm.c
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+++ b/target/i386/kvm.c
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@@ -91,6 +91,7 @@ static bool has_msr_hv_synic;
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 static bool has_msr_hv_stimer;
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 static bool has_msr_hv_frequencies;
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 static bool has_msr_xss;
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+static bool has_msr_umwait;
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 static bool has_msr_spec_ctrl;
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 static bool has_msr_tsx_ctrl;
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 static bool has_msr_virt_ssbd;
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@@ -1450,6 +1451,9 @@ static int kvm_get_supported_msrs(KVMState *s)
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             case MSR_IA32_XSS:
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                 has_msr_xss = true;
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                 break;
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+            case MSR_IA32_UMWAIT_CONTROL:
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+                has_msr_umwait = true;
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+                break;
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             case HV_X64_MSR_CRASH_CTL:
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                 has_msr_hv_crash = true;
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                 break;
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@@ -2134,6 +2138,9 @@ static int kvm_put_msrs(X86CPU *cpu, int level)
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     if (has_msr_xss) {
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         kvm_msr_entry_add(cpu, MSR_IA32_XSS, env->xss);
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     }
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+    if (has_msr_umwait) {
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+        kvm_msr_entry_add(cpu, MSR_IA32_UMWAIT_CONTROL, env->umwait);
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+    }
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     if (has_msr_spec_ctrl) {
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         kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, env->spec_ctrl);
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     }
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@@ -2533,6 +2540,9 @@ static int kvm_get_msrs(X86CPU *cpu)
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     if (has_msr_xss) {
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         kvm_msr_entry_add(cpu, MSR_IA32_XSS, 0);
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     }
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+    if (has_msr_umwait) {
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+        kvm_msr_entry_add(cpu, MSR_IA32_UMWAIT_CONTROL, 0);
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+    }
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     if (has_msr_spec_ctrl) {
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         kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, 0);
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     }
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@@ -2780,6 +2790,9 @@ static int kvm_get_msrs(X86CPU *cpu)
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         case MSR_IA32_XSS:
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             env->xss = msrs[i].data;
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             break;
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+        case MSR_IA32_UMWAIT_CONTROL:
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+            env->umwait = msrs[i].data;
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+            break;
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         default:
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             if (msrs[i].index >= MSR_MC0_CTL &&
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                 msrs[i].index < MSR_MC0_CTL + (env->mcg_cap & 0xff) * 4) {
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diff --git a/target/i386/machine.c b/target/i386/machine.c
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index 76b173c..960cb51 100644
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--- a/target/i386/machine.c
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+++ b/target/i386/machine.c
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@@ -894,6 +894,25 @@ static const VMStateDescription vmstate_xss = {
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     }
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 };
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+static bool umwait_needed(void *opaque)
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+{
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+    X86CPU *cpu = opaque;
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+    CPUX86State *env = &cpu->env;
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+
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+    return env->umwait != 0;
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+}
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+
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+static const VMStateDescription vmstate_umwait = {
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+    .name = "cpu/umwait",
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+    .version_id = 1,
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+    .minimum_version_id = 1,
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+    .needed = umwait_needed,
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+    .fields = (VMStateField[]) {
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+        VMSTATE_UINT32(env.umwait, X86CPU),
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+        VMSTATE_END_OF_LIST()
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+    }
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+};
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+
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 #ifdef TARGET_X86_64
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 static bool pkru_needed(void *opaque)
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 {
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@@ -1360,6 +1379,7 @@ VMStateDescription vmstate_x86_cpu = {
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         &vmstate_msr_hyperv_stimer,
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         &vmstate_avx512,
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         &vmstate_xss,
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+        &vmstate_umwait,
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         &vmstate_tsc_khz,
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         &vmstate_msr_smi_count,
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 #ifdef TARGET_X86_64
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-- 
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1.8.3.1
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