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From d8871ae2842531130c9b333e7c06a6a5d1561286 Mon Sep 17 00:00:00 2001
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From: Andrew Jones <drjones@redhat.com>
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Date: Fri, 24 Jan 2020 09:14:34 +0100
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Subject: [PATCH 001/116] target/arm/arch_dump: Add SVE notes
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RH-Author: Andrew Jones <drjones@redhat.com>
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Message-id: <20200124091434.15021-2-drjones@redhat.com>
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Patchwork-id: 93443
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O-Subject: [RHEL-AV-8.2.0 qemu-kvm PATCH 1/1] target/arm/arch_dump: Add SVE notes
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Bugzilla: 1725084
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RH-Acked-by: Auger Eric <eric.auger@redhat.com>
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RH-Acked-by: Laszlo Ersek <lersek@redhat.com>
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RH-Acked-by: Gavin Shan <gshan@redhat.com>
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Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=1725084
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Author: Andrew Jones <drjones@redhat.com>
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Date:   Thu, 23 Jan 2020 15:22:40 +0000
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    target/arm/arch_dump: Add SVE notes
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    When dumping a guest with dump-guest-memory also dump the SVE
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    registers if they are in use.
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    Signed-off-by: Andrew Jones <drjones@redhat.com>
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    Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
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    Message-id: 20200120101832.18781-1-drjones@redhat.com
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    [PMM: fixed checkpatch nits]
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    Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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(cherry picked from commit 538baab245ca881e6a6ff720b5133f3ad1fcaafc)
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Signed-off-by: Miroslav Rezanina <mrezanin@redhat.com>
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---
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 include/elf.h          |   1 +
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 target/arm/arch_dump.c | 124 ++++++++++++++++++++++++++++++++++++++++++++++++-
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 target/arm/cpu.h       |  25 ++++++++++
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 target/arm/kvm64.c     |  24 ----------
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 4 files changed, 148 insertions(+), 26 deletions(-)
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diff --git a/include/elf.h b/include/elf.h
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index 3501e0c..8fbfe60 100644
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--- a/include/elf.h
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+++ b/include/elf.h
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@@ -1650,6 +1650,7 @@ typedef struct elf64_shdr {
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 #define NT_ARM_HW_BREAK 0x402           /* ARM hardware breakpoint registers */
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 #define NT_ARM_HW_WATCH 0x403           /* ARM hardware watchpoint registers */
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 #define NT_ARM_SYSTEM_CALL      0x404   /* ARM system call number */
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+#define NT_ARM_SVE      0x405           /* ARM Scalable Vector Extension regs */
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 /*
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  * Physical entry point into the kernel.
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diff --git a/target/arm/arch_dump.c b/target/arm/arch_dump.c
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index 26a2c09..2345dec 100644
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--- a/target/arm/arch_dump.c
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+++ b/target/arm/arch_dump.c
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@@ -62,12 +62,23 @@ struct aarch64_user_vfp_state {
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 QEMU_BUILD_BUG_ON(sizeof(struct aarch64_user_vfp_state) != 528);
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+/* struct user_sve_header from arch/arm64/include/uapi/asm/ptrace.h */
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+struct aarch64_user_sve_header {
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+    uint32_t size;
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+    uint32_t max_size;
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+    uint16_t vl;
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+    uint16_t max_vl;
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+    uint16_t flags;
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+    uint16_t reserved;
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+} QEMU_PACKED;
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+
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 struct aarch64_note {
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     Elf64_Nhdr hdr;
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     char name[8]; /* align_up(sizeof("CORE"), 4) */
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     union {
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         struct aarch64_elf_prstatus prstatus;
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         struct aarch64_user_vfp_state vfp;
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+        struct aarch64_user_sve_header sve;
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     };
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 } QEMU_PACKED;
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@@ -76,6 +87,8 @@ struct aarch64_note {
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             (AARCH64_NOTE_HEADER_SIZE + sizeof(struct aarch64_elf_prstatus))
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 #define AARCH64_PRFPREG_NOTE_SIZE \
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             (AARCH64_NOTE_HEADER_SIZE + sizeof(struct aarch64_user_vfp_state))
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+#define AARCH64_SVE_NOTE_SIZE(env) \
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+            (AARCH64_NOTE_HEADER_SIZE + sve_size(env))
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 static void aarch64_note_init(struct aarch64_note *note, DumpState *s,
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                               const char *name, Elf64_Word namesz,
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@@ -128,11 +141,102 @@ static int aarch64_write_elf64_prfpreg(WriteCoreDumpFunction f,
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     return 0;
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 }
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+#ifdef TARGET_AARCH64
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+static off_t sve_zreg_offset(uint32_t vq, int n)
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+{
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+    off_t off = sizeof(struct aarch64_user_sve_header);
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+    return ROUND_UP(off, 16) + vq * 16 * n;
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+}
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+
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+static off_t sve_preg_offset(uint32_t vq, int n)
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+{
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+    return sve_zreg_offset(vq, 32) + vq * 16 / 8 * n;
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+}
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+
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+static off_t sve_fpsr_offset(uint32_t vq)
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+{
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+    off_t off = sve_preg_offset(vq, 17);
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+    return ROUND_UP(off, 16);
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+}
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+
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+static off_t sve_fpcr_offset(uint32_t vq)
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+{
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+    return sve_fpsr_offset(vq) + sizeof(uint32_t);
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+}
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+
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+static uint32_t sve_current_vq(CPUARMState *env)
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+{
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+    return sve_zcr_len_for_el(env, arm_current_el(env)) + 1;
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+}
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+
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+static size_t sve_size_vq(uint32_t vq)
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+{
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+    off_t off = sve_fpcr_offset(vq) + sizeof(uint32_t);
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+    return ROUND_UP(off, 16);
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+}
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+
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+static size_t sve_size(CPUARMState *env)
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+{
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+    return sve_size_vq(sve_current_vq(env));
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+}
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+
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+static int aarch64_write_elf64_sve(WriteCoreDumpFunction f,
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+                                   CPUARMState *env, int cpuid,
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+                                   DumpState *s)
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+{
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+    struct aarch64_note *note;
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+    ARMCPU *cpu = env_archcpu(env);
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+    uint32_t vq = sve_current_vq(env);
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+    uint64_t tmp[ARM_MAX_VQ * 2], *r;
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+    uint32_t fpr;
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+    uint8_t *buf;
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+    int ret, i;
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+
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+    note = g_malloc0(AARCH64_SVE_NOTE_SIZE(env));
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+    buf = (uint8_t *)&note->sve;
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+
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+    aarch64_note_init(note, s, "LINUX", 6, NT_ARM_SVE, sve_size_vq(vq));
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+
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+    note->sve.size = cpu_to_dump32(s, sve_size_vq(vq));
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+    note->sve.max_size = cpu_to_dump32(s, sve_size_vq(cpu->sve_max_vq));
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+    note->sve.vl = cpu_to_dump16(s, vq * 16);
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+    note->sve.max_vl = cpu_to_dump16(s, cpu->sve_max_vq * 16);
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+    note->sve.flags = cpu_to_dump16(s, 1);
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+
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+    for (i = 0; i < 32; ++i) {
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+        r = sve_bswap64(tmp, &env->vfp.zregs[i].d[0], vq * 2);
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+        memcpy(&buf[sve_zreg_offset(vq, i)], r, vq * 16);
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+    }
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+
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+    for (i = 0; i < 17; ++i) {
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+        r = sve_bswap64(tmp, r = &env->vfp.pregs[i].p[0],
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+                        DIV_ROUND_UP(vq * 2, 8));
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+        memcpy(&buf[sve_preg_offset(vq, i)], r, vq * 16 / 8);
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+    }
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+
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+    fpr = cpu_to_dump32(s, vfp_get_fpsr(env));
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+    memcpy(&buf[sve_fpsr_offset(vq)], &fpr, sizeof(uint32_t));
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+
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+    fpr = cpu_to_dump32(s, vfp_get_fpcr(env));
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+    memcpy(&buf[sve_fpcr_offset(vq)], &fpr, sizeof(uint32_t));
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+
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+    ret = f(note, AARCH64_SVE_NOTE_SIZE(env), s);
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+    g_free(note);
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+
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+    if (ret < 0) {
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+        return -1;
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+    }
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+
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+    return 0;
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+}
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+#endif
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+
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 int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
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                              int cpuid, void *opaque)
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 {
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     struct aarch64_note note;
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-    CPUARMState *env = &ARM_CPU(cs)->env;
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+    ARMCPU *cpu = ARM_CPU(cs);
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+    CPUARMState *env = &cpu->env;
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     DumpState *s = opaque;
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     uint64_t pstate, sp;
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     int ret, i;
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@@ -163,7 +267,18 @@ int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
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         return -1;
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     }
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-    return aarch64_write_elf64_prfpreg(f, env, cpuid, s);
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+    ret = aarch64_write_elf64_prfpreg(f, env, cpuid, s);
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+    if (ret) {
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+        return ret;
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+    }
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+
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+#ifdef TARGET_AARCH64
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+    if (cpu_isar_feature(aa64_sve, cpu)) {
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+        ret = aarch64_write_elf64_sve(f, env, cpuid, s);
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+    }
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+#endif
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+
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+    return ret;
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 }
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 /* struct pt_regs from arch/arm/include/asm/ptrace.h */
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@@ -335,6 +450,11 @@ ssize_t cpu_get_note_size(int class, int machine, int nr_cpus)
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     if (class == ELFCLASS64) {
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         note_size = AARCH64_PRSTATUS_NOTE_SIZE;
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         note_size += AARCH64_PRFPREG_NOTE_SIZE;
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+#ifdef TARGET_AARCH64
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+        if (cpu_isar_feature(aa64_sve, cpu)) {
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+            note_size += AARCH64_SVE_NOTE_SIZE(env);
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+        }
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+#endif
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     } else {
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         note_size = ARM_PRSTATUS_NOTE_SIZE;
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         if (arm_feature(env, ARM_FEATURE_VFP)) {
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diff --git a/target/arm/cpu.h b/target/arm/cpu.h
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index 83a809d..82dd3cc 100644
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--- a/target/arm/cpu.h
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+++ b/target/arm/cpu.h
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@@ -975,6 +975,31 @@ void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq);
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 void aarch64_sve_change_el(CPUARMState *env, int old_el,
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                            int new_el, bool el0_a64);
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 void aarch64_add_sve_properties(Object *obj);
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+
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+/*
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+ * SVE registers are encoded in KVM's memory in an endianness-invariant format.
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+ * The byte at offset i from the start of the in-memory representation contains
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+ * the bits [(7 + 8 * i) : (8 * i)] of the register value. As this means the
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+ * lowest offsets are stored in the lowest memory addresses, then that nearly
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+ * matches QEMU's representation, which is to use an array of host-endian
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+ * uint64_t's, where the lower offsets are at the lower indices. To complete
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+ * the translation we just need to byte swap the uint64_t's on big-endian hosts.
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+ */
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+static inline uint64_t *sve_bswap64(uint64_t *dst, uint64_t *src, int nr)
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+{
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+#ifdef HOST_WORDS_BIGENDIAN
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+    int i;
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+
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+    for (i = 0; i < nr; ++i) {
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+        dst[i] = bswap64(src[i]);
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+    }
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+
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+    return dst;
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+#else
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+    return src;
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+#endif
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+}
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+
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 #else
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 static inline void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq) { }
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 static inline void aarch64_sve_change_el(CPUARMState *env, int o,
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diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
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index 876184b..e2da756 100644
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--- a/target/arm/kvm64.c
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+++ b/target/arm/kvm64.c
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@@ -877,30 +877,6 @@ static int kvm_arch_put_fpsimd(CPUState *cs)
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 }
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 /*
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- * SVE registers are encoded in KVM's memory in an endianness-invariant format.
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- * The byte at offset i from the start of the in-memory representation contains
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- * the bits [(7 + 8 * i) : (8 * i)] of the register value. As this means the
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- * lowest offsets are stored in the lowest memory addresses, then that nearly
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- * matches QEMU's representation, which is to use an array of host-endian
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- * uint64_t's, where the lower offsets are at the lower indices. To complete
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- * the translation we just need to byte swap the uint64_t's on big-endian hosts.
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- */
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-static uint64_t *sve_bswap64(uint64_t *dst, uint64_t *src, int nr)
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-{
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-#ifdef HOST_WORDS_BIGENDIAN
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-    int i;
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-
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-    for (i = 0; i < nr; ++i) {
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-        dst[i] = bswap64(src[i]);
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-    }
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-
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-    return dst;
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-#else
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-    return src;
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-#endif
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-}
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-
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-/*
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  * KVM SVE registers come in slices where ZREGs have a slice size of 2048 bits
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  * and PREGS and the FFR have a slice size of 256 bits. However we simply hard
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  * code the slice index to zero for now as it's unlikely we'll need more than
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-- 
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1.8.3.1
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