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From 28794dca79a94d01c8732b84fe6ac6ba2986ce45 Mon Sep 17 00:00:00 2001
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From: Laurent Vivier <lvivier@redhat.com>
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Date: Wed, 9 Jun 2021 10:05:01 -0400
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Subject: [PATCH 4/4] spapr: Set LPCR to current AIL mode when starting a new
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CPU
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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RH-Author: Laurent Vivier <lvivier@redhat.com>
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Message-id: <20210609100501.427096-3-lvivier@redhat.com>
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Patchwork-id: 101683
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O-Subject: [RHEL-8.5.0 qemu-kvm PATCH 2/2] spapr: Set LPCR to current AIL mode when starting a new CPU
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Bugzilla: 1969768
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RH-Acked-by: Stefano Garzarella <sgarzare@redhat.com>
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RH-Acked-by: David Gibson <dgibson@redhat.com>
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RH-Acked-by: Greg Kurz <gkurz@redhat.com>
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From: Nicholas Piggin <npiggin@gmail.com>
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TCG does not keep track of AIL mode in a central place, it's based on
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the current LPCR[AIL] bits. Synchronize the new CPU's LPCR to the
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current LPCR in rtas_start_cpu(), similarly to the way the ILE bit is
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synchronized.
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Open-code the ILE setting as well now that the caller's LPCR is
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available directly, there is no need for the indirection.
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Without this, under both TCG and KVM, adding a POWER8/9/10 class CPU
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with a new core ID after a modern Linux has booted results in the new
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CPU's LPCR missing the LPCR[AIL]=0b11 setting that the other CPUs have.
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This can cause crashes and unexpected behaviour.
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Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
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Message-Id: <20210526091626.3388262-3-npiggin@gmail.com>
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Reviewed-by: Cédric Le Goater <clg@kaod.org>
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Reviewed-by: Greg Kurz <groug@kaod.org>
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Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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(cherry picked from commit ac559ecbea2649819e7b3fdd09f4e0243e0128db)
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Signed-off-by: Laurent Vivier <lvivier@redhat.com>
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Signed-off-by: Danilo C. L. de Paula <ddepaula@redhat.com>
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---
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hw/ppc/spapr_rtas.c | 14 +++++++++-----
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1 file changed, 9 insertions(+), 5 deletions(-)
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diff --git a/hw/ppc/spapr_rtas.c b/hw/ppc/spapr_rtas.c
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index 295eac986e..5acb7c1f10 100644
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--- a/hw/ppc/spapr_rtas.c
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+++ b/hw/ppc/spapr_rtas.c
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@@ -132,8 +132,8 @@ static void rtas_start_cpu(PowerPCCPU *callcpu, SpaprMachineState *spapr,
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target_ulong id, start, r3;
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PowerPCCPU *newcpu;
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CPUPPCState *env;
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- PowerPCCPUClass *pcc;
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target_ulong lpcr;
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+ target_ulong caller_lpcr;
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if (nargs != 3 || nret != 1) {
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rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
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@@ -152,7 +152,6 @@ static void rtas_start_cpu(PowerPCCPU *callcpu, SpaprMachineState *spapr,
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}
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env = &newcpu->env;
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- pcc = POWERPC_CPU_GET_CLASS(newcpu);
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if (!CPU(newcpu)->halted) {
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rtas_st(rets, 0, RTAS_OUT_HW_ERROR);
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@@ -163,10 +162,15 @@ static void rtas_start_cpu(PowerPCCPU *callcpu, SpaprMachineState *spapr,
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env->msr = (1ULL << MSR_SF) | (1ULL << MSR_ME);
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+ caller_lpcr = callcpu->env.spr[SPR_LPCR];
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lpcr = env->spr[SPR_LPCR];
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- if (!pcc->interrupts_big_endian(callcpu)) {
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- lpcr |= LPCR_ILE;
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- }
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+
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+ /* Set ILE the same way */
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+ lpcr = (lpcr & ~LPCR_ILE) | (caller_lpcr & LPCR_ILE);
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+
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+ /* Set AIL the same way */
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+ lpcr = (lpcr & ~LPCR_AIL) | (caller_lpcr & LPCR_AIL);
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+
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if (env->mmu_model == POWERPC_MMU_3_00) {
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/*
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* New cpus are expected to start in the same radix/hash mode
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--
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2.27.0
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