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Blame SOURCES/kvm-pci-store-PCI-hole-ranges-in-guestinfo-structure.patch

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From 43d319c65b1a27349fd329cb2f9c6f5c54f32379 Mon Sep 17 00:00:00 2001
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Message-Id: <43d319c65b1a27349fd329cb2f9c6f5c54f32379.1387298827.git.minovotn@redhat.com>
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In-Reply-To: <3ed0fb61a3dc912ef036d7ef450bed192090709e.1387298827.git.minovotn@redhat.com>
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References: <3ed0fb61a3dc912ef036d7ef450bed192090709e.1387298827.git.minovotn@redhat.com>
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From: "Michael S. Tsirkin" <mst@redhat.com>
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Date: Tue, 17 Dec 2013 15:17:22 +0100
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Subject: [PATCH 13/56] pci: store PCI hole ranges in guestinfo structure
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RH-Author: Michael S. Tsirkin <mst@redhat.com>
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Message-id: <1387293161-4085-14-git-send-email-mst@redhat.com>
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Patchwork-id: 56318
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O-Subject: [PATCH qemu-kvm RHEL7.0 v2 13/57] pci: store PCI hole ranges in guestinfo structure
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Bugzilla: 1034876
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RH-Acked-by: Igor Mammedov <imammedo@redhat.com>
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RH-Acked-by: Marcel Apfelbaum <marcel.a@redhat.com>
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RH-Acked-by: Laszlo Ersek <lersek@redhat.com>
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Will be used to pass hole ranges to guests.
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Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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(cherry picked from commit 3459a625215449b67b9c67d9151ff72892d0a42a)
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Conflicts:
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	hw/i386/pc_piix.c
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	hw/i386/pc_q35.c
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---
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 include/hw/i386/pc.h      | 19 ++++++++++++++++++-
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 include/hw/pci-host/q35.h |  2 ++
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 include/qemu/typedefs.h   |  1 +
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 hw/i386/pc.c              | 46 +++++++++++++++++++++++++++++++++++++++++++++-
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 hw/i386/pc_piix.c         | 14 +++++++++++++-
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 hw/i386/pc_q35.c          |  6 +++++-
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 hw/pci-host/q35.c         |  8 ++++++++
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 7 files changed, 92 insertions(+), 4 deletions(-)
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Signed-off-by: Michal Novotny <minovotn@redhat.com>
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---
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 hw/i386/pc.c              | 46 +++++++++++++++++++++++++++++++++++++++++++++-
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 hw/i386/pc_piix.c         | 14 +++++++++++++-
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 hw/i386/pc_q35.c          |  6 +++++-
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 hw/pci-host/q35.c         |  8 ++++++++
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 include/hw/i386/pc.h      | 19 ++++++++++++++++++-
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 include/hw/pci-host/q35.h |  2 ++
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 include/qemu/typedefs.h   |  1 +
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 7 files changed, 92 insertions(+), 4 deletions(-)
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diff --git a/hw/i386/pc.c b/hw/i386/pc.c
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index 2948781..68a8e1b 100644
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--- a/hw/i386/pc.c
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+++ b/hw/i386/pc.c
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@@ -985,6 +985,48 @@ void pc_cpus_init(const char *cpu_model, DeviceState *icc_bridge)
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     }
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 }
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+typedef struct PcGuestInfoState {
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+    PcGuestInfo info;
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+    Notifier machine_done;
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+} PcGuestInfoState;
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+
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+static
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+void pc_guest_info_machine_done(Notifier *notifier, void *data)
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+{
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+    PcGuestInfoState *guest_info_state = container_of(notifier,
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+                                                      PcGuestInfoState,
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+                                                      machine_done);
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+}
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+
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+PcGuestInfo *pc_guest_info_init(ram_addr_t below_4g_mem_size,
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+                                ram_addr_t above_4g_mem_size)
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+{
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+    PcGuestInfoState *guest_info_state = g_malloc0(sizeof *guest_info_state);
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+    PcGuestInfo *guest_info = &guest_info_state->info;
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+
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+    guest_info->pci_info.w32.end = IO_APIC_DEFAULT_ADDRESS;
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+    if (sizeof(hwaddr) == 4) {
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+        guest_info->pci_info.w64.begin = 0;
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+        guest_info->pci_info.w64.end = 0;
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+    } else {
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+        /*
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+         * BIOS does not set MTRR entries for the 64 bit window, so no need to
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+         * align address to power of two.  Align address at 1G, this makes sure
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+         * it can be exactly covered with a PAT entry even when using huge
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+         * pages.
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+         */
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+        guest_info->pci_info.w64.begin =
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+            ROUND_UP((0x1ULL << 32) + above_4g_mem_size, 0x1ULL << 30);
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+        guest_info->pci_info.w64.end = guest_info->pci_info.w64.begin +
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+            (0x1ULL << 62);
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+        assert(guest_info->pci_info.w64.begin <= guest_info->pci_info.w64.end);
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+    }
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+
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+    guest_info_state->machine_done.notify = pc_guest_info_machine_done;
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+    qemu_add_machine_init_done_notifier(&guest_info_state->machine_done);
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+    return guest_info;
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+}
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+
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 void pc_acpi_init(const char *default_dsdt)
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 {
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     char *filename;
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@@ -1026,7 +1068,8 @@ FWCfgState *pc_memory_init(MemoryRegion *system_memory,
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                            ram_addr_t below_4g_mem_size,
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                            ram_addr_t above_4g_mem_size,
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                            MemoryRegion *rom_memory,
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-                           MemoryRegion **ram_memory)
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+                           MemoryRegion **ram_memory,
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+                           PcGuestInfo *guest_info)
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 {
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     int linux_boot, i;
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     MemoryRegion *ram, *option_rom_mr;
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@@ -1078,6 +1121,7 @@ FWCfgState *pc_memory_init(MemoryRegion *system_memory,
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     for (i = 0; i < nb_option_roms; i++) {
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         rom_add_option(option_rom[i].name, option_rom[i].bootindex);
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     }
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+    guest_info->fw_cfg = fw_cfg;
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     return fw_cfg;
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 }
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diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
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index 07848c1..3a77998 100644
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--- a/hw/i386/pc_piix.c
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+++ b/hw/i386/pc_piix.c
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@@ -87,6 +87,7 @@ static void pc_init1(QEMUMachineInitArgs *args,
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     MemoryRegion *rom_memory;
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     DeviceState *icc_bridge;
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     FWCfgState *fw_cfg = NULL;
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+    PcGuestInfo *guest_info;
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     icc_bridge = qdev_create(NULL, TYPE_ICC_BRIDGE);
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     object_property_add_child(qdev_get_machine(), "icc-bridge",
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@@ -120,13 +121,24 @@ static void pc_init1(QEMUMachineInitArgs *args,
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         smbios_set_type1_defaults("Red Hat", "KVM", args->machine->desc);
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     }
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+    guest_info = pc_guest_info_init(below_4g_mem_size, above_4g_mem_size);
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+
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+    /* Set PCI window size the way seabios has always done it. */
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+    /* Power of 2 so bios can cover it with a single MTRR */
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+    if (ram_size <= 0x80000000)
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+        guest_info->pci_info.w32.begin = 0x80000000;
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+    else if (ram_size <= 0xc0000000)
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+        guest_info->pci_info.w32.begin = 0xc0000000;
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+    else
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+        guest_info->pci_info.w32.begin = 0xe0000000;
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+
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     /* allocate ram and load rom/bios */
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     if (!xen_enabled()) {
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         fw_cfg = pc_memory_init(system_memory,
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                        args->kernel_filename, args->kernel_cmdline,
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                        args->initrd_filename,
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                        below_4g_mem_size, above_4g_mem_size,
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-                       rom_memory, &ram_memory);
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+                       rom_memory, &ram_memory, guest_info);
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     }
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     gsi_state = g_malloc0(sizeof(*gsi_state));
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diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
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index 8fa6793..9fab93c 100644
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--- a/hw/i386/pc_q35.c
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+++ b/hw/i386/pc_q35.c
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@@ -73,6 +73,7 @@ static void pc_q35_init(QEMUMachineInitArgs *args)
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     ICH9LPCState *ich9_lpc;
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     PCIDevice *ahci;
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     DeviceState *icc_bridge;
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+    PcGuestInfo *guest_info;
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     icc_bridge = qdev_create(NULL, TYPE_ICC_BRIDGE);
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     object_property_add_child(qdev_get_machine(), "icc-bridge",
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@@ -106,13 +107,15 @@ static void pc_q35_init(QEMUMachineInitArgs *args)
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         smbios_set_type1_defaults("Red Hat", "KVM", args->machine->desc);
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     }
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+    guest_info = pc_guest_info_init(below_4g_mem_size, above_4g_mem_size);
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+
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     /* allocate ram and load rom/bios */
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     if (!xen_enabled()) {
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         pc_memory_init(get_system_memory(),
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                        args->kernel_filename, args->kernel_cmdline,
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                        args->initrd_filename,
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                        below_4g_mem_size, above_4g_mem_size,
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-                       rom_memory, &ram_memory);
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+                       rom_memory, &ram_memory, guest_info);
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     }
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     /* irq lines */
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@@ -134,6 +137,7 @@ static void pc_q35_init(QEMUMachineInitArgs *args)
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     q35_host->mch.address_space_io = get_system_io();
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     q35_host->mch.below_4g_mem_size = below_4g_mem_size;
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     q35_host->mch.above_4g_mem_size = above_4g_mem_size;
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+    q35_host->mch.guest_info = guest_info;
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     /* pci */
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     qdev_init_nofail(DEVICE(q35_host));
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     host_bus = q35_host->host.pci.bus;
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diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c
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index ed934c3..0989fc5 100644
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--- a/hw/pci-host/q35.c
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+++ b/hw/pci-host/q35.c
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@@ -245,6 +245,14 @@ static int mch_init(PCIDevice *d)
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     hwaddr pci_hole64_size;
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     MCHPCIState *mch = MCH_PCI_DEVICE(d);
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+    /* Leave enough space for the biggest MCFG BAR */
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+    /* TODO: this matches current bios behaviour, but
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+     * it's not a power of two, which means an MTRR
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+     * can't cover it exactly.
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+     */
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+    mch->guest_info->pci_info.w32.begin = MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT +
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+        MCH_HOST_BRIDGE_PCIEXBAR_MAX;
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+
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     /* setup pci memory regions */
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     memory_region_init_alias(&mch->pci_hole, "pci-hole",
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                              mch->pci_address_space,
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diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
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index 2cf7baa..2518db6 100644
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--- a/include/hw/i386/pc.h
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+++ b/include/hw/i386/pc.h
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@@ -10,8 +10,20 @@
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 #include "exec/memory.h"
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 #include "hw/i386/ioapic.h"
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+#include "qemu/range.h"
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+
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 /* PC-style peripherals (also used by other machines).  */
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+typedef struct PcPciInfo {
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+    Range w32;
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+    Range w64;
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+} PcPciInfo;
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+
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+struct PcGuestInfo {
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+    PcPciInfo pci_info;
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+    FWCfgState *fw_cfg;
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+};
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+
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 /* parallel.c */
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 static inline bool parallel_init(ISABus *bus, int index, CharDriverState *chr)
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 {
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@@ -84,6 +96,10 @@ void pc_acpi_smi_interrupt(void *opaque, int irq, int level);
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 void pc_cpus_init(const char *cpu_model, DeviceState *icc_bridge);
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 void pc_hot_add_cpu(const int64_t id, Error **errp);
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 void pc_acpi_init(const char *default_dsdt);
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+
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+PcGuestInfo *pc_guest_info_init(ram_addr_t below_4g_mem_size,
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+                                ram_addr_t above_4g_mem_size);
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+
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 FWCfgState *pc_memory_init(MemoryRegion *system_memory,
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                            const char *kernel_filename,
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                            const char *kernel_cmdline,
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@@ -91,7 +107,8 @@ FWCfgState *pc_memory_init(MemoryRegion *system_memory,
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                            ram_addr_t below_4g_mem_size,
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                            ram_addr_t above_4g_mem_size,
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                            MemoryRegion *rom_memory,
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-                           MemoryRegion **ram_memory);
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+                           MemoryRegion **ram_memory,
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+                           PcGuestInfo *guest_info);
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 qemu_irq *pc_allocate_cpu_irq(void);
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 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus);
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 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
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diff --git a/include/hw/pci-host/q35.h b/include/hw/pci-host/q35.h
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index e182c82..b083831 100644
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--- a/include/hw/pci-host/q35.h
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+++ b/include/hw/pci-host/q35.h
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@@ -55,6 +55,7 @@ typedef struct MCHPCIState {
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     uint8_t smm_enabled;
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     ram_addr_t below_4g_mem_size;
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     ram_addr_t above_4g_mem_size;
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+    PcGuestInfo *guest_info;
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 } MCHPCIState;
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 typedef struct Q35PCIHost {
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@@ -81,6 +82,7 @@ typedef struct Q35PCIHost {
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 #define MCH_HOST_BRIDGE_PCIEXBAR               0x60    /* 64bit register */
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 #define MCH_HOST_BRIDGE_PCIEXBAR_SIZE          8       /* 64bit register */
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 #define MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT       0xb0000000
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+#define MCH_HOST_BRIDGE_PCIEXBAR_MAX           (0x10000000) /* 256M */
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 #define MCH_HOST_BRIDGE_PCIEXBAR_ADMSK         Q35_MASK(64, 35, 28)
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 #define MCH_HOST_BRIDGE_PCIEXBAR_128ADMSK      ((uint64_t)(1 << 26))
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 #define MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK       ((uint64_t)(1 << 25))
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diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h
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index a332d88..70d250f 100644
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--- a/include/qemu/typedefs.h
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+++ b/include/qemu/typedefs.h
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@@ -64,6 +64,7 @@ typedef struct VirtIODevice VirtIODevice;
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 typedef struct QEMUSGList QEMUSGList;
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 typedef struct SHPCDevice SHPCDevice;
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 typedef struct FWCfgState FWCfgState;
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+typedef struct PcGuestInfo PcGuestInfo;
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 typedef struct Range Range;
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 #endif /* QEMU_TYPEDEFS_H */
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-- 
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1.7.11.7
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