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From 32341d8cf680625def040b44d70b197f2399bbdb Mon Sep 17 00:00:00 2001
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From: "plai@redhat.com" <plai@redhat.com>
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Date: Thu, 21 May 2020 23:56:48 +0100
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Subject: [PATCH 05/12] numa: Extend CLI to provide memory latency and
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 bandwidth information
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RH-Author: plai@redhat.com
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Message-id: <20200521235655.27141-5-plai@redhat.com>
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Patchwork-id: 96731
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O-Subject: [RHEL8.2.1 AV qemu-kvm PATCH 04/11] numa: Extend CLI to provide memory latency and bandwidth information
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Bugzilla: 1600217
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RH-Acked-by: Michael S. Tsirkin <mst@redhat.com>
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RH-Acked-by: Igor Mammedov <imammedo@redhat.com>
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RH-Acked-by: Eduardo Habkost <ehabkost@redhat.com>
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From: Liu Jingqi <jingqi.liu@intel.com>
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Add -numa hmat-lb option to provide System Locality Latency and
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Bandwidth Information. These memory attributes help to build
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System Locality Latency and Bandwidth Information Structure(s)
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in ACPI Heterogeneous Memory Attribute Table (HMAT). Before using
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hmat-lb option, enable HMAT with -machine hmat=on.
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Acked-by: Markus Armbruster <armbru@redhat.com>
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Signed-off-by: Liu Jingqi <jingqi.liu@intel.com>
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Signed-off-by: Tao Xu <tao3.xu@intel.com>
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Message-Id: <20191213011929.2520-3-tao3.xu@intel.com>
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Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
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Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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Reviewed-by: Igor Mammedov <imammedo@redhat.com>
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(cherry picked from commit 9b12dfa03a94d7f7a4b54eb67229a31e58193384)
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Signed-off-by: Paul Lai <plai@redhat.com>
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Signed-off-by: Danilo C. L. de Paula <ddepaula@redhat.com>
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---
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 hw/core/numa.c        | 194 ++++++++++++++++++++++++++++++++++++++++++++++++++
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 include/sysemu/numa.h |  53 ++++++++++++++
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 qapi/machine.json     |  93 +++++++++++++++++++++++-
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 qemu-options.hx       |  47 +++++++++++-
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 4 files changed, 384 insertions(+), 3 deletions(-)
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diff --git a/hw/core/numa.c b/hw/core/numa.c
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index a07eef9..58fe713 100644
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--- a/hw/core/numa.c
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+++ b/hw/core/numa.c
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@@ -23,6 +23,7 @@
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  */
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 #include "qemu/osdep.h"
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+#include "qemu/units.h"
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 #include "sysemu/hostmem.h"
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 #include "sysemu/numa.h"
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 #include "sysemu/sysemu.h"
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@@ -194,6 +195,186 @@ void parse_numa_distance(MachineState *ms, NumaDistOptions *dist, Error **errp)
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     ms->numa_state->have_numa_distance = true;
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 }
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+void parse_numa_hmat_lb(NumaState *numa_state, NumaHmatLBOptions *node,
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+                        Error **errp)
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+{
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+    int i, first_bit, last_bit;
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+    uint64_t max_entry, temp_base, bitmap_copy;
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+    NodeInfo *numa_info = numa_state->nodes;
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+    HMAT_LB_Info *hmat_lb =
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+        numa_state->hmat_lb[node->hierarchy][node->data_type];
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+    HMAT_LB_Data lb_data = {};
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+    HMAT_LB_Data *lb_temp;
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+
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+    /* Error checking */
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+    if (node->initiator > numa_state->num_nodes) {
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+        error_setg(errp, "Invalid initiator=%d, it should be less than %d",
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+                   node->initiator, numa_state->num_nodes);
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+        return;
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+    }
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+    if (node->target > numa_state->num_nodes) {
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+        error_setg(errp, "Invalid target=%d, it should be less than %d",
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+                   node->target, numa_state->num_nodes);
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+        return;
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+    }
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+    if (!numa_info[node->initiator].has_cpu) {
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+        error_setg(errp, "Invalid initiator=%d, it isn't an "
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+                   "initiator proximity domain", node->initiator);
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+        return;
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+    }
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+    if (!numa_info[node->target].present) {
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+        error_setg(errp, "The target=%d should point to an existing node",
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+                   node->target);
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+        return;
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+    }
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+
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+    if (!hmat_lb) {
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+        hmat_lb = g_malloc0(sizeof(*hmat_lb));
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+        numa_state->hmat_lb[node->hierarchy][node->data_type] = hmat_lb;
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+        hmat_lb->list = g_array_new(false, true, sizeof(HMAT_LB_Data));
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+    }
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+    hmat_lb->hierarchy = node->hierarchy;
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+    hmat_lb->data_type = node->data_type;
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+    lb_data.initiator = node->initiator;
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+    lb_data.target = node->target;
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+
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+    if (node->data_type <= HMATLB_DATA_TYPE_WRITE_LATENCY) {
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+        /* Input latency data */
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+
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+        if (!node->has_latency) {
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+            error_setg(errp, "Missing 'latency' option");
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+            return;
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+        }
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+        if (node->has_bandwidth) {
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+            error_setg(errp, "Invalid option 'bandwidth' since "
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+                       "the data type is latency");
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+            return;
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+        }
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+
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+        /* Detect duplicate configuration */
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+        for (i = 0; i < hmat_lb->list->len; i++) {
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+            lb_temp = &g_array_index(hmat_lb->list, HMAT_LB_Data, i);
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+
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+            if (node->initiator == lb_temp->initiator &&
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+                node->target == lb_temp->target) {
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+                error_setg(errp, "Duplicate configuration of the latency for "
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+                    "initiator=%d and target=%d", node->initiator,
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+                    node->target);
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+                return;
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+            }
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+        }
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+
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+        hmat_lb->base = hmat_lb->base ? hmat_lb->base : UINT64_MAX;
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+
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+        if (node->latency) {
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+            /* Calculate the temporary base and compressed latency */
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+            max_entry = node->latency;
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+            temp_base = 1;
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+            while (QEMU_IS_ALIGNED(max_entry, 10)) {
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+                max_entry /= 10;
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+                temp_base *= 10;
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+            }
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+
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+            /* Calculate the max compressed latency */
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+            temp_base = MIN(hmat_lb->base, temp_base);
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+            max_entry = node->latency / hmat_lb->base;
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+            max_entry = MAX(hmat_lb->range_bitmap, max_entry);
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+
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+            /*
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+             * For latency hmat_lb->range_bitmap record the max compressed
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+             * latency which should be less than 0xFFFF (UINT16_MAX)
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+             */
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+            if (max_entry >= UINT16_MAX) {
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+                error_setg(errp, "Latency %" PRIu64 " between initiator=%d and "
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+                        "target=%d should not differ from previously entered "
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+                        "min or max values on more than %d", node->latency,
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+                        node->initiator, node->target, UINT16_MAX - 1);
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+                return;
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+            } else {
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+                hmat_lb->base = temp_base;
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+                hmat_lb->range_bitmap = max_entry;
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+            }
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+
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+            /*
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+             * Set lb_info_provided bit 0 as 1,
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+             * latency information is provided
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+             */
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+            numa_info[node->target].lb_info_provided |= BIT(0);
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+        }
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+        lb_data.data = node->latency;
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+    } else if (node->data_type >= HMATLB_DATA_TYPE_ACCESS_BANDWIDTH) {
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+        /* Input bandwidth data */
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+        if (!node->has_bandwidth) {
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+            error_setg(errp, "Missing 'bandwidth' option");
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+            return;
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+        }
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+        if (node->has_latency) {
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+            error_setg(errp, "Invalid option 'latency' since "
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+                       "the data type is bandwidth");
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+            return;
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+        }
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+        if (!QEMU_IS_ALIGNED(node->bandwidth, MiB)) {
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+            error_setg(errp, "Bandwidth %" PRIu64 " between initiator=%d and "
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+                       "target=%d should be 1MB aligned", node->bandwidth,
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+                       node->initiator, node->target);
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+            return;
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+        }
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+
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+        /* Detect duplicate configuration */
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+        for (i = 0; i < hmat_lb->list->len; i++) {
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+            lb_temp = &g_array_index(hmat_lb->list, HMAT_LB_Data, i);
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+
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+            if (node->initiator == lb_temp->initiator &&
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+                node->target == lb_temp->target) {
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+                error_setg(errp, "Duplicate configuration of the bandwidth for "
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+                    "initiator=%d and target=%d", node->initiator,
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+                    node->target);
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+                return;
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+            }
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+        }
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+
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+        hmat_lb->base = hmat_lb->base ? hmat_lb->base : 1;
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+
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+        if (node->bandwidth) {
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+            /* Keep bitmap unchanged when bandwidth out of range */
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+            bitmap_copy = hmat_lb->range_bitmap;
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+            bitmap_copy |= node->bandwidth;
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+            first_bit = ctz64(bitmap_copy);
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+            temp_base = UINT64_C(1) << first_bit;
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+            max_entry = node->bandwidth / temp_base;
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+            last_bit = 64 - clz64(bitmap_copy);
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+
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+            /*
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+             * For bandwidth, first_bit record the base unit of bandwidth bits,
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+             * last_bit record the last bit of the max bandwidth. The max
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+             * compressed bandwidth should be less than 0xFFFF (UINT16_MAX)
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+             */
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+            if ((last_bit - first_bit) > UINT16_BITS ||
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+                max_entry >= UINT16_MAX) {
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+                error_setg(errp, "Bandwidth %" PRIu64 " between initiator=%d "
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+                        "and target=%d should not differ from previously "
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+                        "entered values on more than %d", node->bandwidth,
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+                        node->initiator, node->target, UINT16_MAX - 1);
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+                return;
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+            } else {
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+                hmat_lb->base = temp_base;
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+                hmat_lb->range_bitmap = bitmap_copy;
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+            }
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+
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+            /*
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+             * Set lb_info_provided bit 1 as 1,
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+             * bandwidth information is provided
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+             */
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+            numa_info[node->target].lb_info_provided |= BIT(1);
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+        }
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+        lb_data.data = node->bandwidth;
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+    } else {
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+        assert(0);
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+    }
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+
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+    g_array_append_val(hmat_lb->list, lb_data);
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+}
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+
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 void set_numa_options(MachineState *ms, NumaOptions *object, Error **errp)
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 {
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     Error *err = NULL;
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@@ -231,6 +412,19 @@ void set_numa_options(MachineState *ms, NumaOptions *object, Error **errp)
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         machine_set_cpu_numa_node(ms, qapi_NumaCpuOptions_base(&object->u.cpu),
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                                   &err;;
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         break;
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+    case NUMA_OPTIONS_TYPE_HMAT_LB:
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+        if (!ms->numa_state->hmat_enabled) {
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+            error_setg(errp, "ACPI Heterogeneous Memory Attribute Table "
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+                       "(HMAT) is disabled, enable it with -machine hmat=on "
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+                       "before using any of hmat specific options");
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+            return;
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+        }
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+
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+        parse_numa_hmat_lb(ms->numa_state, &object->u.hmat_lb, &err;;
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+        if (err) {
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+            goto end;
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+        }
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+        break;
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     default:
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         abort();
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     }
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diff --git a/include/sysemu/numa.h b/include/sysemu/numa.h
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index 788cbec..70f93c8 100644
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--- a/include/sysemu/numa.h
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+++ b/include/sysemu/numa.h
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@@ -14,11 +14,34 @@ struct CPUArchId;
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 #define NUMA_DISTANCE_MAX         254
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 #define NUMA_DISTANCE_UNREACHABLE 255
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+/* the value of AcpiHmatLBInfo flags */
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+enum {
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+    HMAT_LB_MEM_MEMORY           = 0,
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+    HMAT_LB_MEM_CACHE_1ST_LEVEL  = 1,
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+    HMAT_LB_MEM_CACHE_2ND_LEVEL  = 2,
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+    HMAT_LB_MEM_CACHE_3RD_LEVEL  = 3,
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+    HMAT_LB_LEVELS   /* must be the last entry */
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+};
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+
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+/* the value of AcpiHmatLBInfo data type */
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+enum {
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+    HMAT_LB_DATA_ACCESS_LATENCY   = 0,
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+    HMAT_LB_DATA_READ_LATENCY     = 1,
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+    HMAT_LB_DATA_WRITE_LATENCY    = 2,
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+    HMAT_LB_DATA_ACCESS_BANDWIDTH = 3,
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+    HMAT_LB_DATA_READ_BANDWIDTH   = 4,
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+    HMAT_LB_DATA_WRITE_BANDWIDTH  = 5,
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+    HMAT_LB_TYPES   /* must be the last entry */
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+};
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+
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+#define UINT16_BITS       16
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+
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 struct NodeInfo {
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     uint64_t node_mem;
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     struct HostMemoryBackend *node_memdev;
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     bool present;
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     bool has_cpu;
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+    uint8_t lb_info_provided;
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     uint16_t initiator;
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     uint8_t distance[MAX_NODES];
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 };
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@@ -28,6 +51,31 @@ struct NumaNodeMem {
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     uint64_t node_plugged_mem;
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 };
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+struct HMAT_LB_Data {
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+    uint8_t     initiator;
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+    uint8_t     target;
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+    uint64_t    data;
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+};
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+typedef struct HMAT_LB_Data HMAT_LB_Data;
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+
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+struct HMAT_LB_Info {
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+    /* Indicates it's memory or the specified level memory side cache. */
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+    uint8_t     hierarchy;
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+
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+    /* Present the type of data, access/read/write latency or bandwidth. */
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+    uint8_t     data_type;
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+
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+    /* The range bitmap of bandwidth for calculating common base */
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+    uint64_t    range_bitmap;
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+
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+    /* The common base unit for latencies or bandwidths */
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+    uint64_t    base;
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+
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+    /* Array to store the latencies or bandwidths */
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+    GArray      *list;
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+};
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+typedef struct HMAT_LB_Info HMAT_LB_Info;
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+
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 struct NumaState {
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     /* Number of NUMA nodes */
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     int num_nodes;
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@@ -40,11 +88,16 @@ struct NumaState {
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     /* NUMA nodes information */
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     NodeInfo nodes[MAX_NODES];
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+
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+    /* NUMA nodes HMAT Locality Latency and Bandwidth Information */
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+    HMAT_LB_Info *hmat_lb[HMAT_LB_LEVELS][HMAT_LB_TYPES];
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 };
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 typedef struct NumaState NumaState;
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 void set_numa_options(MachineState *ms, NumaOptions *object, Error **errp);
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 void parse_numa_opts(MachineState *ms);
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+void parse_numa_hmat_lb(NumaState *numa_state, NumaHmatLBOptions *node,
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+                        Error **errp);
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 void numa_complete_configuration(MachineState *ms);
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 void query_numa_node_mem(NumaNodeMem node_mem[], MachineState *ms);
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 extern QemuOptsList qemu_numa_opts;
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diff --git a/qapi/machine.json b/qapi/machine.json
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index 27d0e37..cf8faf5 100644
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--- a/qapi/machine.json
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+++ b/qapi/machine.json
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@@ -426,10 +426,12 @@
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 #
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 # @cpu: property based CPU(s) to node mapping (Since: 2.10)
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 #
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+# @hmat-lb: memory latency and bandwidth information (Since: 5.0)
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+#
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 # Since: 2.1
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 ##
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 { 'enum': 'NumaOptionsType',
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-  'data': [ 'node', 'dist', 'cpu' ] }
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+  'data': [ 'node', 'dist', 'cpu', 'hmat-lb' ] }
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 ##
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 # @NumaOptions:
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@@ -444,7 +446,8 @@
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   'data': {
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     'node': 'NumaNodeOptions',
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     'dist': 'NumaDistOptions',
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-    'cpu': 'NumaCpuOptions' }}
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+    'cpu': 'NumaCpuOptions',
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+    'hmat-lb': 'NumaHmatLBOptions' }}
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 ##
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 # @NumaNodeOptions:
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@@ -558,6 +561,92 @@
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    'data' : {} }
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 ##
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+# @HmatLBMemoryHierarchy:
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+#
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+# The memory hierarchy in the System Locality Latency and Bandwidth
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+# Information Structure of HMAT (Heterogeneous Memory Attribute Table)
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+#
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+# For more information about @HmatLBMemoryHierarchy, see chapter
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+# 5.2.27.4: Table 5-146: Field "Flags" of ACPI 6.3 spec.
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+#
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+# @memory: the structure represents the memory performance
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+#
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+# @first-level: first level of memory side cache
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+#
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+# @second-level: second level of memory side cache
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+#
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+# @third-level: third level of memory side cache
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+#
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+# Since: 5.0
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+##
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+{ 'enum': 'HmatLBMemoryHierarchy',
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+  'data': [ 'memory', 'first-level', 'second-level', 'third-level' ] }
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+
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+##
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+# @HmatLBDataType:
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+#
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+# Data type in the System Locality Latency and Bandwidth
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+# Information Structure of HMAT (Heterogeneous Memory Attribute Table)
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+#
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+# For more information about @HmatLBDataType, see chapter
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+# 5.2.27.4: Table 5-146:  Field "Data Type" of ACPI 6.3 spec.
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+#
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+# @access-latency: access latency (nanoseconds)
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+#
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+# @read-latency: read latency (nanoseconds)
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+#
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+# @write-latency: write latency (nanoseconds)
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+#
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+# @access-bandwidth: access bandwidth (Bytes per second)
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+#
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+# @read-bandwidth: read bandwidth (Bytes per second)
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+#
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+# @write-bandwidth: write bandwidth (Bytes per second)
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+#
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+# Since: 5.0
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+##
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+{ 'enum': 'HmatLBDataType',
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+  'data': [ 'access-latency', 'read-latency', 'write-latency',
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+            'access-bandwidth', 'read-bandwidth', 'write-bandwidth' ] }
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+
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+##
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+# @NumaHmatLBOptions:
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+#
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+# Set the system locality latency and bandwidth information
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+# between Initiator and Target proximity Domains.
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+#
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+# For more information about @NumaHmatLBOptions, see chapter
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+# 5.2.27.4: Table 5-146 of ACPI 6.3 spec.
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+#
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+# @initiator: the Initiator Proximity Domain.
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+#
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+# @target: the Target Proximity Domain.
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+#
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+# @hierarchy: the Memory Hierarchy. Indicates the performance
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+#             of memory or side cache.
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+#
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+# @data-type: presents the type of data, access/read/write
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+#             latency or hit latency.
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+#
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+# @latency: the value of latency from @initiator to @target
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+#           proximity domain, the latency unit is "ns(nanosecond)".
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+#
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+# @bandwidth: the value of bandwidth between @initiator and @target
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+#             proximity domain, the bandwidth unit is
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+#             "Bytes per second".
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+#
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+# Since: 5.0
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+##
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+{ 'struct': 'NumaHmatLBOptions',
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+    'data': {
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+    'initiator': 'uint16',
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+    'target': 'uint16',
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+    'hierarchy': 'HmatLBMemoryHierarchy',
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+    'data-type': 'HmatLBDataType',
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+    '*latency': 'uint64',
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+    '*bandwidth': 'size' }}
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+
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+##
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 # @HostMemPolicy:
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 #
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 # Host memory policy types
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diff --git a/qemu-options.hx b/qemu-options.hx
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index e2ce754..86d9d8a 100644
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--- a/qemu-options.hx
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+++ b/qemu-options.hx
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@@ -168,16 +168,19 @@ DEF("numa", HAS_ARG, QEMU_OPTION_numa,
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     "-numa node[,mem=size][,cpus=firstcpu[-lastcpu]][,nodeid=node][,initiator=node]\n"
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     "-numa node[,memdev=id][,cpus=firstcpu[-lastcpu]][,nodeid=node][,initiator=node]\n"
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     "-numa dist,src=source,dst=destination,val=distance\n"
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-    "-numa cpu,node-id=node[,socket-id=x][,core-id=y][,thread-id=z]\n",
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+    "-numa cpu,node-id=node[,socket-id=x][,core-id=y][,thread-id=z]\n"
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+    "-numa hmat-lb,initiator=node,target=node,hierarchy=memory|first-level|second-level|third-level,data-type=access-latency|read-latency|write-latency[,latency=lat][,bandwidth=bw]\n",
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     QEMU_ARCH_ALL)
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 STEXI
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 @item -numa node[,mem=@var{size}][,cpus=@var{firstcpu}[-@var{lastcpu}]][,nodeid=@var{node}][,initiator=@var{initiator}]
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 @itemx -numa node[,memdev=@var{id}][,cpus=@var{firstcpu}[-@var{lastcpu}]][,nodeid=@var{node}][,initiator=@var{initiator}]
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 @itemx -numa dist,src=@var{source},dst=@var{destination},val=@var{distance}
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 @itemx -numa cpu,node-id=@var{node}[,socket-id=@var{x}][,core-id=@var{y}][,thread-id=@var{z}]
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+@itemx -numa hmat-lb,initiator=@var{node},target=@var{node},hierarchy=@var{hierarchy},data-type=@var{tpye}[,latency=@var{lat}][,bandwidth=@var{bw}]
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 @findex -numa
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 Define a NUMA node and assign RAM and VCPUs to it.
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 Set the NUMA distance from a source node to a destination node.
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+Set the ACPI Heterogeneous Memory Attributes for the given nodes.
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 Legacy VCPU assignment uses @samp{cpus} option where
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 @var{firstcpu} and @var{lastcpu} are CPU indexes. Each
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@@ -256,6 +259,48 @@ specified resources, it just assigns existing resources to NUMA
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 nodes. This means that one still has to use the @option{-m},
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 @option{-smp} options to allocate RAM and VCPUs respectively.
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+Use @samp{hmat-lb} to set System Locality Latency and Bandwidth Information
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+between initiator and target NUMA nodes in ACPI Heterogeneous Attribute Memory Table (HMAT).
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+Initiator NUMA node can create memory requests, usually it has one or more processors.
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+Target NUMA node contains addressable memory.
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+
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+In @samp{hmat-lb} option, @var{node} are NUMA node IDs. @var{hierarchy} is the memory
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+hierarchy of the target NUMA node: if @var{hierarchy} is 'memory', the structure
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+represents the memory performance; if @var{hierarchy} is 'first-level|second-level|third-level',
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+this structure represents aggregated performance of memory side caches for each domain.
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+@var{type} of 'data-type' is type of data represented by this structure instance:
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+if 'hierarchy' is 'memory', 'data-type' is 'access|read|write' latency or 'access|read|write'
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+bandwidth of the target memory; if 'hierarchy' is 'first-level|second-level|third-level',
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+'data-type' is 'access|read|write' hit latency or 'access|read|write' hit bandwidth of the
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+target memory side cache.
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+
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+@var{lat} is latency value in nanoseconds. @var{bw} is bandwidth value,
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+the possible value and units are NUM[M|G|T], mean that the bandwidth value are
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+NUM byte per second (or MB/s, GB/s or TB/s depending on used suffix).
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+Note that if latency or bandwidth value is 0, means the corresponding latency or
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+bandwidth information is not provided.
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+
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+For example, the following options describe 2 NUMA nodes. Node 0 has 2 cpus and
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+a ram, node 1 has only a ram. The processors in node 0 access memory in node
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+0 with access-latency 5 nanoseconds, access-bandwidth is 200 MB/s;
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+The processors in NUMA node 0 access memory in NUMA node 1 with access-latency 10
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+nanoseconds, access-bandwidth is 100 MB/s.
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+@example
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+-machine hmat=on \
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+-m 2G \
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+-object memory-backend-ram,size=1G,id=m0 \
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+-object memory-backend-ram,size=1G,id=m1 \
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+-smp 2 \
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+-numa node,nodeid=0,memdev=m0 \
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+-numa node,nodeid=1,memdev=m1,initiator=0 \
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+-numa cpu,node-id=0,socket-id=0 \
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+-numa cpu,node-id=0,socket-id=1 \
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+-numa hmat-lb,initiator=0,target=0,hierarchy=memory,data-type=access-latency,latency=5 \
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+-numa hmat-lb,initiator=0,target=0,hierarchy=memory,data-type=access-bandwidth,bandwidth=200M \
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+-numa hmat-lb,initiator=0,target=1,hierarchy=memory,data-type=access-latency,latency=10 \
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+-numa hmat-lb,initiator=0,target=1,hierarchy=memory,data-type=access-bandwidth,bandwidth=100M
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+@end example
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+
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 ETEXI
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 DEF("add-fd", HAS_ARG, QEMU_OPTION_add_fd,
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-- 
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1.8.3.1
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