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From 96f6d8855246a66bde59fd3e663bee0da00f709b Mon Sep 17 00:00:00 2001
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From: Eduardo Habkost <ehabkost@redhat.com>
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Date: Wed, 13 Jun 2018 18:08:11 +0200
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Subject: [PATCH 152/268] i386: Define the Virt SSBD MSR and handling of it
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 (CVE-2018-3639)
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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RH-Author: Eduardo Habkost <ehabkost@redhat.com>
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Message-id: <20180613180812.28169-2-ehabkost@redhat.com>
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Patchwork-id: 80677
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O-Subject: [RHEL-7.6 qemu-kvm-rhev PATCH 1/2] i386: Define the Virt SSBD MSR and handling of it (CVE-2018-3639)
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Bugzilla: 1574216
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RH-Acked-by: Igor Mammedov <imammedo@redhat.com>
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RH-Acked-by: Miroslav Rezanina <mrezanin@redhat.com>
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RH-Acked-by: Laurent Vivier <lvivier@redhat.com>
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From: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
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"Some AMD processors only support a non-architectural means of enabling
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speculative store bypass disable (SSBD).  To allow a simplified view of
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this to a guest, an architectural definition has been created through a new
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CPUID bit, 0x80000008_EBX[25], and a new MSR, 0xc001011f.  With this, a
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hypervisor can virtualize the existence of this definition and provide an
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architectural method for using SSBD to a guest.
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Add the new CPUID feature, the new MSR and update the existing SSBD
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support to use this MSR when present." (from x86/speculation: Add virtualized
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speculative store bypass disable support in Linux).
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Backport conflicts:
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  * target-i386/machine.c: trivial conflict with vmstate_xsave section
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Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
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Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
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Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
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Message-Id: <20180521215424.13520-4-berrange@redhat.com>
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Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
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(cherry picked from commit cfeea0c021db6234c154dbc723730e81553924ff)
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Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
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Signed-off-by: Miroslav Rezanina <mrezanin@redhat.com>
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---
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 target/i386/cpu.h     |  2 ++
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 target/i386/kvm.c     | 16 ++++++++++++++--
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 target/i386/machine.c | 20 ++++++++++++++++++++
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 3 files changed, 36 insertions(+), 2 deletions(-)
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diff --git a/target/i386/cpu.h b/target/i386/cpu.h
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index 88fdf80..c47db96 100644
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--- a/target/i386/cpu.h
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+++ b/target/i386/cpu.h
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@@ -351,6 +351,7 @@ typedef enum X86Seg {
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 #define MSR_IA32_FEATURE_CONTROL        0x0000003a
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 #define MSR_TSC_ADJUST                  0x0000003b
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 #define MSR_IA32_SPEC_CTRL              0x48
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+#define MSR_VIRT_SSBD                   0xc001011f
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 #define MSR_IA32_TSCDEADLINE            0x6e0
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 #define FEATURE_CONTROL_LOCKED                    (1<<0)
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@@ -1208,6 +1209,7 @@ typedef struct CPUX86State {
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     uint32_t pkru;
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     uint64_t spec_ctrl;
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+    uint64_t virt_ssbd;
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     /* End of state preserved by INIT (dummy marker).  */
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     struct {} end_init_save;
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diff --git a/target/i386/kvm.c b/target/i386/kvm.c
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index bb5e485..00f2141 100644
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--- a/target/i386/kvm.c
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+++ b/target/i386/kvm.c
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@@ -92,6 +92,7 @@ static bool has_msr_hv_stimer;
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 static bool has_msr_hv_frequencies;
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 static bool has_msr_xss;
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 static bool has_msr_spec_ctrl;
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+static bool has_msr_virt_ssbd;
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 static bool has_msr_smi_count;
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 static uint32_t has_architectural_pmu_version;
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@@ -1248,6 +1249,9 @@ static int kvm_get_supported_msrs(KVMState *s)
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                 case MSR_IA32_SPEC_CTRL:
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                     has_msr_spec_ctrl = true;
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                     break;
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+                case MSR_VIRT_SSBD:
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+                    has_msr_virt_ssbd = true;
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+                    break;
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                 }
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             }
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         }
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@@ -1736,6 +1740,10 @@ static int kvm_put_msrs(X86CPU *cpu, int level)
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     if (has_msr_spec_ctrl) {
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         kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, env->spec_ctrl);
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     }
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+    if (has_msr_virt_ssbd) {
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+        kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, env->virt_ssbd);
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+    }
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+
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 #ifdef TARGET_X86_64
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     if (lm_capable_kernel) {
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         kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar);
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@@ -2107,8 +2115,9 @@ static int kvm_get_msrs(X86CPU *cpu)
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     if (has_msr_spec_ctrl) {
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         kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, 0);
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     }
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-
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-
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+    if (has_msr_virt_ssbd) {
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+        kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, 0);
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+    }
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     if (!env->tsc_valid) {
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         kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
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         env->tsc_valid = !runstate_is_running();
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@@ -2474,6 +2483,9 @@ static int kvm_get_msrs(X86CPU *cpu)
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         case MSR_IA32_SPEC_CTRL:
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             env->spec_ctrl = msrs[i].data;
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             break;
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+        case MSR_VIRT_SSBD:
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+            env->virt_ssbd = msrs[i].data;
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+            break;
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         case MSR_IA32_RTIT_CTL:
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             env->msr_rtit_ctrl = msrs[i].data;
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             break;
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diff --git a/target/i386/machine.c b/target/i386/machine.c
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index c9a3b5c..5e9a19b 100644
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--- a/target/i386/machine.c
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+++ b/target/i386/machine.c
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@@ -913,6 +913,25 @@ static const VMStateDescription vmstate_xsave ={
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     }
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 };
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+static bool virt_ssbd_needed(void *opaque)
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+{
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+    X86CPU *cpu = opaque;
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+    CPUX86State *env = &cpu->env;
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+
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+    return env->virt_ssbd != 0;
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+}
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+
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+static const VMStateDescription vmstate_msr_virt_ssbd = {
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+    .name = "cpu/virt_ssbd",
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+    .version_id = 1,
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+    .minimum_version_id = 1,
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+    .needed = virt_ssbd_needed,
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+    .fields = (VMStateField[]){
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+        VMSTATE_UINT64(env.virt_ssbd, X86CPU),
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+        VMSTATE_END_OF_LIST()
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+    }
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+};
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+
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 VMStateDescription vmstate_x86_cpu = {
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     .name = "cpu",
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     .version_id = 12,
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@@ -1036,6 +1055,7 @@ VMStateDescription vmstate_x86_cpu = {
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         &vmstate_mcg_ext_ctl,
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         &vmstate_msr_intel_pt,
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         &vmstate_xsave,
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+        &vmstate_msr_virt_ssbd,
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         NULL
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     }
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 };
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-- 
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1.8.3.1
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