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Blame SOURCES/kvm-i386-Add-new-property-to-control-cache-info.patch

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From c78647f69c02d1004dfc1a2f1e2e24960634c795 Mon Sep 17 00:00:00 2001
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From: Eduardo Habkost <ehabkost@redhat.com>
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Date: Thu, 26 Jul 2018 17:18:57 +0100
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Subject: [PATCH 07/14] i386: Add new property to control cache info
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RH-Author: Eduardo Habkost <ehabkost@redhat.com>
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Message-id: <20180726171904.27418-5-ehabkost@redhat.com>
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Patchwork-id: 81526
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O-Subject: [qemu-kvm RHEL8/virt212 PATCH v2 04/11] i386: Add new property to control cache info
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Bugzilla: 1597739
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RH-Acked-by: Paolo Bonzini <pbonzini@redhat.com>
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RH-Acked-by: Laurent Vivier <lvivier@redhat.com>
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RH-Acked-by: Igor Mammedov <imammedo@redhat.com>
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From: Babu Moger <babu.moger@amd.com>
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The property legacy-cache will be used to control the cache information.
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If user passes "-cpu legacy-cache" then older information will
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be displayed even if the hardware supports new information. Otherwise
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use the statically loaded cache definitions if available.
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Renamed the previous cache structures to legacy_*. If there is any change in
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the cache information, then it needs to be initialized in builtin_x86_defs.
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Signed-off-by: Babu Moger <babu.moger@amd.com>
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Tested-by: Geoffrey McRae <geoff@hostfission.com>
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Message-Id: <20180514164156.27034-3-babu.moger@amd.com>
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Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
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Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
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(cherry picked from commit ab8f992e3e63e91be257e4e343d386dae7be4bcb)
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Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
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Signed-off-by: Danilo C. L. de Paula <ddepaula@redhat.com>
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---
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 include/hw/i386/pc.h |  4 +++
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 target/i386/cpu.c    | 97 ++++++++++++++++++++++++++++++++++++++--------------
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 target/i386/cpu.h    |  5 +++
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 3 files changed, 80 insertions(+), 26 deletions(-)
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diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
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index ae84db4..5aebf6e 100644
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--- a/include/hw/i386/pc.h
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+++ b/include/hw/i386/pc.h
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@@ -979,6 +979,10 @@ extern void igd_passthrough_isa_bridge_create(PCIBus *bus, uint16_t gpu_dev_id);
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             .driver   = "Skylake-Server" "-" TYPE_X86_CPU,\
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             .property = "clflushopt",\
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             .value    = "off",\
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+        },{ /* PC_RHEL7_5_COMPAT from PC_COMPAT_2_12 */ \
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+            .driver   = TYPE_X86_CPU,\
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+            .property = "legacy-cache",\
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+            .value    = "on",\
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         },
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diff --git a/target/i386/cpu.c b/target/i386/cpu.c
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index bd0abc2..7dfc0fc 100644
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--- a/target/i386/cpu.c
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+++ b/target/i386/cpu.c
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@@ -336,10 +336,14 @@ static void encode_cache_cpuid80000006(CPUCacheInfo *l2,
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     }
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 }
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-/* Definitions of the hardcoded cache entries we expose: */
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+/*
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+ * Definitions of the hardcoded cache entries we expose:
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+ * These are legacy cache values. If there is a need to change any
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+ * of these values please use builtin_x86_defs
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+ */
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 /* L1 data cache: */
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-static CPUCacheInfo l1d_cache = {
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+static CPUCacheInfo legacy_l1d_cache = {
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     .type = DCACHE,
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     .level = 1,
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     .size = 32 * KiB,
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@@ -352,7 +356,7 @@ static CPUCacheInfo l1d_cache = {
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 };
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 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
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-static CPUCacheInfo l1d_cache_amd = {
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+static CPUCacheInfo legacy_l1d_cache_amd = {
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     .type = DCACHE,
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     .level = 1,
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     .size = 64 * KiB,
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@@ -366,7 +370,7 @@ static CPUCacheInfo l1d_cache_amd = {
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 };
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 /* L1 instruction cache: */
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-static CPUCacheInfo l1i_cache = {
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+static CPUCacheInfo legacy_l1i_cache = {
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     .type = ICACHE,
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     .level = 1,
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     .size = 32 * KiB,
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@@ -379,7 +383,7 @@ static CPUCacheInfo l1i_cache = {
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 };
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 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
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-static CPUCacheInfo l1i_cache_amd = {
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+static CPUCacheInfo legacy_l1i_cache_amd = {
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     .type = ICACHE,
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     .level = 1,
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     .size = 64 * KiB,
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@@ -393,7 +397,7 @@ static CPUCacheInfo l1i_cache_amd = {
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 };
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 /* Level 2 unified cache: */
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-static CPUCacheInfo l2_cache = {
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+static CPUCacheInfo legacy_l2_cache = {
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     .type = UNIFIED_CACHE,
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     .level = 2,
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     .size = 4 * MiB,
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@@ -406,7 +410,7 @@ static CPUCacheInfo l2_cache = {
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 };
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 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
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-static CPUCacheInfo l2_cache_cpuid2 = {
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+static CPUCacheInfo legacy_l2_cache_cpuid2 = {
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     .type = UNIFIED_CACHE,
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     .level = 2,
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     .size = 2 * MiB,
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@@ -416,7 +420,7 @@ static CPUCacheInfo l2_cache_cpuid2 = {
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 /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
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-static CPUCacheInfo l2_cache_amd = {
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+static CPUCacheInfo legacy_l2_cache_amd = {
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     .type = UNIFIED_CACHE,
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     .level = 2,
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     .size = 512 * KiB,
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@@ -428,7 +432,7 @@ static CPUCacheInfo l2_cache_amd = {
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 };
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 /* Level 3 unified cache: */
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-static CPUCacheInfo l3_cache = {
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+static CPUCacheInfo legacy_l3_cache = {
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     .type = UNIFIED_CACHE,
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     .level = 3,
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     .size = 16 * MiB,
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@@ -3321,6 +3325,10 @@ static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp)
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         env->features[w] = def->features[w];
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     }
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+    /* Store Cache information from the X86CPUDefinition if available */
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+    env->cache_info = def->cache_info;
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+    cpu->legacy_cache = def->cache_info ? 0 : 1;
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+
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     /* Special cases not set in the X86CPUDefinition structs: */
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     /* TODO: in-kernel irqchip for hvf */
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     if (kvm_enabled()) {
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@@ -3670,11 +3678,21 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
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         if (!cpu->enable_l3_cache) {
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             *ecx = 0;
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         } else {
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-            *ecx = cpuid2_cache_descriptor(&l3_cache);
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+            if (env->cache_info && !cpu->legacy_cache) {
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+                *ecx = cpuid2_cache_descriptor(&env->cache_info->l3_cache);
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+            } else {
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+                *ecx = cpuid2_cache_descriptor(&legacy_l3_cache);
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+            }
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+        }
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+        if (env->cache_info && !cpu->legacy_cache) {
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+            *edx = (cpuid2_cache_descriptor(&env->cache_info->l1d_cache) << 16) |
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+                   (cpuid2_cache_descriptor(&env->cache_info->l1i_cache) <<  8) |
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+                   (cpuid2_cache_descriptor(&env->cache_info->l2_cache));
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+        } else {
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+            *edx = (cpuid2_cache_descriptor(&legacy_l1d_cache) << 16) |
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+                   (cpuid2_cache_descriptor(&legacy_l1i_cache) <<  8) |
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+                   (cpuid2_cache_descriptor(&legacy_l2_cache_cpuid2));
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         }
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-        *edx = (cpuid2_cache_descriptor(&l1d_cache) << 16) |
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-               (cpuid2_cache_descriptor(&l1i_cache) <<  8) |
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-               (cpuid2_cache_descriptor(&l2_cache_cpuid2));
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         break;
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     case 4:
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         /* cache info: needed for Core compatibility */
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@@ -3687,27 +3705,35 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
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             }
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         } else {
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             *eax = 0;
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+            CPUCacheInfo *l1d, *l1i, *l2, *l3;
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+            if (env->cache_info && !cpu->legacy_cache) {
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+                l1d = &env->cache_info->l1d_cache;
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+                l1i = &env->cache_info->l1i_cache;
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+                l2 = &env->cache_info->l2_cache;
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+                l3 = &env->cache_info->l3_cache;
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+            } else {
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+                l1d = &legacy_l1d_cache;
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+                l1i = &legacy_l1i_cache;
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+                l2 = &legacy_l2_cache;
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+                l3 = &legacy_l3_cache;
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+            }
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             switch (count) {
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             case 0: /* L1 dcache info */
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-                encode_cache_cpuid4(&l1d_cache,
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-                                    1, cs->nr_cores,
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+                encode_cache_cpuid4(l1d, 1, cs->nr_cores,
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                                     eax, ebx, ecx, edx);
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                 break;
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             case 1: /* L1 icache info */
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-                encode_cache_cpuid4(&l1i_cache,
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-                                    1, cs->nr_cores,
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+                encode_cache_cpuid4(l1i, 1, cs->nr_cores,
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                                     eax, ebx, ecx, edx);
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                 break;
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             case 2: /* L2 cache info */
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-                encode_cache_cpuid4(&l2_cache,
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-                                    cs->nr_threads, cs->nr_cores,
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+                encode_cache_cpuid4(l2, cs->nr_threads, cs->nr_cores,
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                                     eax, ebx, ecx, edx);
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                 break;
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             case 3: /* L3 cache info */
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                 pkg_offset = apicid_pkg_offset(cs->nr_cores, cs->nr_threads);
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                 if (cpu->enable_l3_cache) {
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-                    encode_cache_cpuid4(&l3_cache,
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-                                        (1 << pkg_offset), cs->nr_cores,
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+                    encode_cache_cpuid4(l3, (1 << pkg_offset), cs->nr_cores,
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                                         eax, ebx, ecx, edx);
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                     break;
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                 }
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@@ -3920,8 +3946,13 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
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                (L1_ITLB_2M_ASSOC <<  8) | (L1_ITLB_2M_ENTRIES);
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         *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
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                (L1_ITLB_4K_ASSOC <<  8) | (L1_ITLB_4K_ENTRIES);
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-        *ecx = encode_cache_cpuid80000005(&l1d_cache_amd);
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-        *edx = encode_cache_cpuid80000005(&l1i_cache_amd);
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+        if (env->cache_info && !cpu->legacy_cache) {
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+            *ecx = encode_cache_cpuid80000005(&env->cache_info->l1d_cache);
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+            *edx = encode_cache_cpuid80000005(&env->cache_info->l1i_cache);
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+        } else {
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+            *ecx = encode_cache_cpuid80000005(&legacy_l1d_cache_amd);
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+            *edx = encode_cache_cpuid80000005(&legacy_l1i_cache_amd);
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+        }
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         break;
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     case 0x80000006:
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         /* cache info (L2 cache) */
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@@ -3937,9 +3968,17 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
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                (L2_DTLB_4K_ENTRIES << 16) | \
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                (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
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                (L2_ITLB_4K_ENTRIES);
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-        encode_cache_cpuid80000006(&l2_cache_amd,
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-                                   cpu->enable_l3_cache ? &l3_cache : NULL,
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-                                   ecx, edx);
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+        if (env->cache_info && !cpu->legacy_cache) {
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+            encode_cache_cpuid80000006(&env->cache_info->l2_cache,
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+                                       cpu->enable_l3_cache ?
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+                                       &env->cache_info->l3_cache : NULL,
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+                                       ecx, edx);
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+        } else {
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+            encode_cache_cpuid80000006(&legacy_l2_cache_amd,
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+                                       cpu->enable_l3_cache ?
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+                                       &legacy_l3_cache : NULL,
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+                                       ecx, edx);
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+        }
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         break;
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     case 0x80000007:
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         *eax = 0;
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@@ -5119,6 +5158,12 @@ static Property x86_cpu_properties[] = {
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                      false),
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     DEFINE_PROP_BOOL("vmware-cpuid-freq", X86CPU, vmware_cpuid_freq, true),
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     DEFINE_PROP_BOOL("tcg-cpuid", X86CPU, expose_tcg, true),
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+    /*
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+     * lecacy_cache defaults to CPU model being chosen. This is set in
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+     * x86_cpu_load_def based on cache_info which is initialized in
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+     * builtin_x86_defs
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+     */
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+    DEFINE_PROP_BOOL("legacy-cache", X86CPU, legacy_cache, false),
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     /*
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      * From "Requirements for Implementing the Microsoft
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diff --git a/target/i386/cpu.h b/target/i386/cpu.h
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index 372f8b7..31715d1 100644
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--- a/target/i386/cpu.h
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+++ b/target/i386/cpu.h
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@@ -1394,6 +1394,11 @@ struct X86CPU {
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      */
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     bool enable_l3_cache;
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+    /* Compatibility bits for old machine types.
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+     * If true present the old cache topology information
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+     */
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+    bool legacy_cache;
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+
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     /* Compatibility bits for old machine types: */
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     bool enable_cpuid_0xb;
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-- 
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1.8.3.1
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