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Blame SOURCES/kvm-hw-arm-smmu-common-Manage-IOTLB-block-entries.patch

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From 4770f43dab482e4585d3555933a473cf24e796db Mon Sep 17 00:00:00 2001
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From: eperezma <eperezma@redhat.com>
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Date: Tue, 12 Jan 2021 14:36:30 -0500
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Subject: [PATCH 06/17] hw/arm/smmu-common: Manage IOTLB block entries
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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RH-Author: eperezma <eperezma@redhat.com>
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Message-id: <20210112143638.374060-6-eperezma@redhat.com>
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Patchwork-id: 100598
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O-Subject: [RHEL-8.4.0 qemu-kvm PATCH v2 05/13] hw/arm/smmu-common: Manage IOTLB block entries
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Bugzilla: 1843852
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RH-Acked-by: Xiao Wang <jasowang@redhat.com>
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RH-Acked-by: Peter Xu <peterx@redhat.com>
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RH-Acked-by: Auger Eric <eric.auger@redhat.com>
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From: Eric Auger <eric.auger@redhat.com>
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At the moment each entry in the IOTLB corresponds to a page sized
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mapping (4K, 16K or 64K), even if the page belongs to a mapped
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block. In case of block mapping this unefficiently consumes IOTLB
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entries.
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Change the value of the entry so that it reflects the actual
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mapping it belongs to (block or page start address and size).
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Also the level/tg of the entry is encoded in the key. In subsequent
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patches we will enable range invalidation. This latter is able
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to provide the level/tg of the entry.
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Encoding the level/tg directly in the key will allow to invalidate
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using g_hash_table_remove() when num_pages equals to 1.
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Signed-off-by: Eric Auger <eric.auger@redhat.com>
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Message-id: 20200728150815.11446-6-eric.auger@redhat.com
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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(cherry picked from commit 9e54dee71fcfaae69f87b8e1f51485a832266a39)
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Signed-off-by: Eugenio PĂ©rez <eperezma@redhat.com>
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Signed-off-by: Danilo C. L. de Paula <ddepaula@redhat.com>
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---
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 hw/arm/smmu-common.c         | 67 ++++++++++++++++++++++++++----------
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 hw/arm/smmu-internal.h       |  7 ++++
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 hw/arm/smmuv3.c              |  6 ++--
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 hw/arm/trace-events          |  2 +-
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 include/hw/arm/smmu-common.h | 10 ++++--
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 5 files changed, 67 insertions(+), 25 deletions(-)
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diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
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index 06e9e38b007..8007edeaaa2 100644
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--- a/hw/arm/smmu-common.c
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+++ b/hw/arm/smmu-common.c
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@@ -39,7 +39,7 @@ static guint smmu_iotlb_key_hash(gconstpointer v)
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     /* Jenkins hash */
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     a = b = c = JHASH_INITVAL + sizeof(*key);
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-    a += key->asid;
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+    a += key->asid + key->level + key->tg;
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     b += extract64(key->iova, 0, 32);
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     c += extract64(key->iova, 32, 32);
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@@ -51,24 +51,41 @@ static guint smmu_iotlb_key_hash(gconstpointer v)
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 static gboolean smmu_iotlb_key_equal(gconstpointer v1, gconstpointer v2)
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 {
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-    const SMMUIOTLBKey *k1 = v1;
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-    const SMMUIOTLBKey *k2 = v2;
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+    SMMUIOTLBKey *k1 = (SMMUIOTLBKey *)v1, *k2 = (SMMUIOTLBKey *)v2;
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-    return (k1->asid == k2->asid) && (k1->iova == k2->iova);
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+    return (k1->asid == k2->asid) && (k1->iova == k2->iova) &&
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+           (k1->level == k2->level) && (k1->tg == k2->tg);
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 }
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-SMMUIOTLBKey smmu_get_iotlb_key(uint16_t asid, uint64_t iova)
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+SMMUIOTLBKey smmu_get_iotlb_key(uint16_t asid, uint64_t iova,
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+                                uint8_t tg, uint8_t level)
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 {
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-    SMMUIOTLBKey key = {.asid = asid, .iova = iova};
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+    SMMUIOTLBKey key = {.asid = asid, .iova = iova, .tg = tg, .level = level};
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     return key;
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 }
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 SMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTransCfg *cfg,
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-                                hwaddr iova)
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+                                SMMUTransTableInfo *tt, hwaddr iova)
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 {
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-    SMMUIOTLBKey key = smmu_get_iotlb_key(cfg->asid, iova);
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-    SMMUTLBEntry *entry = g_hash_table_lookup(bs->iotlb, &key);
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+    uint8_t tg = (tt->granule_sz - 10) / 2;
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+    uint8_t inputsize = 64 - tt->tsz;
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+    uint8_t stride = tt->granule_sz - 3;
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+    uint8_t level = 4 - (inputsize - 4) / stride;
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+    SMMUTLBEntry *entry = NULL;
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+
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+    while (level <= 3) {
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+        uint64_t subpage_size = 1ULL << level_shift(level, tt->granule_sz);
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+        uint64_t mask = subpage_size - 1;
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+        SMMUIOTLBKey key;
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+
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+        key = smmu_get_iotlb_key(cfg->asid, iova & ~mask, tg, level);
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+        entry = g_hash_table_lookup(bs->iotlb, &key);
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+        if (entry) {
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+            break;
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+        }
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+        level++;
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+    }
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     if (entry) {
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         cfg->iotlb_hits++;
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@@ -89,13 +106,14 @@ SMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTransCfg *cfg,
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 void smmu_iotlb_insert(SMMUState *bs, SMMUTransCfg *cfg, SMMUTLBEntry *new)
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 {
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     SMMUIOTLBKey *key = g_new0(SMMUIOTLBKey, 1);
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+    uint8_t tg = (new->granule - 10) / 2;
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     if (g_hash_table_size(bs->iotlb) >= SMMU_IOTLB_MAX_SIZE) {
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         smmu_iotlb_inv_all(bs);
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     }
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-    *key = smmu_get_iotlb_key(cfg->asid, new->entry.iova);
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-    trace_smmu_iotlb_insert(cfg->asid, new->entry.iova);
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+    *key = smmu_get_iotlb_key(cfg->asid, new->entry.iova, tg, new->level);
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+    trace_smmu_iotlb_insert(cfg->asid, new->entry.iova, tg, new->level);
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     g_hash_table_insert(bs->iotlb, key, new);
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 }
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@@ -114,12 +132,26 @@ static gboolean smmu_hash_remove_by_asid(gpointer key, gpointer value,
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     return SMMU_IOTLB_ASID(*iotlb_key) == asid;
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 }
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-inline void smmu_iotlb_inv_iova(SMMUState *s, uint16_t asid, dma_addr_t iova)
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+static gboolean smmu_hash_remove_by_asid_iova(gpointer key, gpointer value,
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+                                              gpointer user_data)
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 {
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-    SMMUIOTLBKey key = smmu_get_iotlb_key(asid, iova);
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+    SMMUTLBEntry *iter = (SMMUTLBEntry *)value;
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+    IOMMUTLBEntry *entry = &iter->entry;
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+    SMMUIOTLBPageInvInfo *info = (SMMUIOTLBPageInvInfo *)user_data;
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+    SMMUIOTLBKey iotlb_key = *(SMMUIOTLBKey *)key;
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+
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+    if (info->asid >= 0 && info->asid != SMMU_IOTLB_ASID(iotlb_key)) {
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+        return false;
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+    }
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+    return (info->iova & ~entry->addr_mask) == entry->iova;
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+}
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+
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+inline void smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova)
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+{
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+    SMMUIOTLBPageInvInfo info = {.asid = asid, .iova = iova};
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     trace_smmu_iotlb_inv_iova(asid, iova);
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-    g_hash_table_remove(s->iotlb, &key);
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+    g_hash_table_foreach_remove(s->iotlb, smmu_hash_remove_by_asid_iova, &info;;
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 }
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 inline void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid)
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@@ -247,9 +279,6 @@ static int smmu_ptw_64(SMMUTransCfg *cfg,
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     baseaddr = extract64(tt->ttb, 0, 48);
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     baseaddr &= ~indexmask;
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-    tlbe->entry.iova = iova;
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-    tlbe->entry.addr_mask = (1 << granule_sz) - 1;
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-
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     while (level <= 3) {
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         uint64_t subpage_size = 1ULL << level_shift(level, granule_sz);
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         uint64_t mask = subpage_size - 1;
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@@ -299,7 +328,9 @@ static int smmu_ptw_64(SMMUTransCfg *cfg,
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             goto error;
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         }
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-        tlbe->entry.translated_addr = gpa + (iova & mask);
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+        tlbe->entry.translated_addr = gpa;
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+        tlbe->entry.iova = iova & ~mask;
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+        tlbe->entry.addr_mask = mask;
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         tlbe->entry.perm = PTE_AP_TO_PERM(ap);
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         tlbe->level = level;
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         tlbe->granule = granule_sz;
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diff --git a/hw/arm/smmu-internal.h b/hw/arm/smmu-internal.h
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index 3104f768cd2..55147f29be4 100644
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--- a/hw/arm/smmu-internal.h
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+++ b/hw/arm/smmu-internal.h
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@@ -97,4 +97,11 @@ uint64_t iova_level_offset(uint64_t iova, int inputsize,
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 }
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 #define SMMU_IOTLB_ASID(key) ((key).asid)
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+
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+typedef struct SMMUIOTLBPageInvInfo {
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+    int asid;
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+    uint64_t iova;
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+    uint64_t mask;
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+} SMMUIOTLBPageInvInfo;
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+
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 #endif
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diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
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index ad8212779d3..067c9480a03 100644
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--- a/hw/arm/smmuv3.c
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+++ b/hw/arm/smmuv3.c
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@@ -662,7 +662,7 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr,
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     page_mask = (1ULL << (tt->granule_sz)) - 1;
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     aligned_addr = addr & ~page_mask;
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-    cached_entry = smmu_iotlb_lookup(bs, cfg, aligned_addr);
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+    cached_entry = smmu_iotlb_lookup(bs, cfg, tt, aligned_addr);
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     if (cached_entry) {
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         if ((flag & IOMMU_WO) && !(cached_entry->entry.perm & IOMMU_WO)) {
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             status = SMMU_TRANS_ERROR;
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@@ -732,7 +732,7 @@ epilogue:
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     case SMMU_TRANS_SUCCESS:
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         entry.perm = flag;
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         entry.translated_addr = cached_entry->entry.translated_addr +
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-                                    (addr & page_mask);
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+                                    (addr & cached_entry->entry.addr_mask);
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         entry.addr_mask = cached_entry->entry.addr_mask;
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         trace_smmuv3_translate_success(mr->parent_obj.name, sid, addr,
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                                        entry.translated_addr, entry.perm);
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@@ -960,7 +960,7 @@ static int smmuv3_cmdq_consume(SMMUv3State *s)
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             trace_smmuv3_cmdq_tlbi_nh_vaa(vmid, addr);
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             smmuv3_inv_notifiers_iova(bs, -1, addr);
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-            smmu_iotlb_inv_all(bs);
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+            smmu_iotlb_inv_iova(bs, -1, addr);
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             break;
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         }
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         case SMMU_CMD_TLBI_NH_VA:
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diff --git a/hw/arm/trace-events b/hw/arm/trace-events
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index b808a1bfc19..f74d3e920f1 100644
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--- a/hw/arm/trace-events
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+++ b/hw/arm/trace-events
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@@ -16,7 +16,7 @@ smmu_iotlb_inv_iova(uint16_t asid, uint64_t addr) "IOTLB invalidate asid=%d addr
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 smmu_inv_notifiers_mr(const char *name) "iommu mr=%s"
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 smmu_iotlb_lookup_hit(uint16_t asid, uint64_t addr, uint32_t hit, uint32_t miss, uint32_t p) "IOTLB cache HIT asid=%d addr=0x%"PRIx64" hit=%d miss=%d hit rate=%d"
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 smmu_iotlb_lookup_miss(uint16_t asid, uint64_t addr, uint32_t hit, uint32_t miss, uint32_t p) "IOTLB cache MISS asid=%d addr=0x%"PRIx64" hit=%d miss=%d hit rate=%d"
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-smmu_iotlb_insert(uint16_t asid, uint64_t addr) "IOTLB ++ asid=%d addr=0x%"PRIx64
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+smmu_iotlb_insert(uint16_t asid, uint64_t addr, uint8_t tg, uint8_t level) "IOTLB ++ asid=%d addr=0x%"PRIx64" tg=%d level=%d"
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 # smmuv3.c
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 smmuv3_read_mmio(uint64_t addr, uint64_t val, unsigned size, uint32_t r) "addr: 0x%"PRIx64" val:0x%"PRIx64" size: 0x%x(%d)"
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diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h
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index 277923bdc0a..bbf3abc41fd 100644
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--- a/include/hw/arm/smmu-common.h
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+++ b/include/hw/arm/smmu-common.h
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@@ -97,6 +97,8 @@ typedef struct SMMUPciBus {
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 typedef struct SMMUIOTLBKey {
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     uint64_t iova;
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     uint16_t asid;
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+    uint8_t tg;
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+    uint8_t level;
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 } SMMUIOTLBKey;
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 typedef struct SMMUState {
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@@ -159,12 +161,14 @@ IOMMUMemoryRegion *smmu_iommu_mr(SMMUState *s, uint32_t sid);
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 #define SMMU_IOTLB_MAX_SIZE 256
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-SMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTransCfg *cfg, hwaddr iova);
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+SMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTransCfg *cfg,
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+                                SMMUTransTableInfo *tt, hwaddr iova);
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 void smmu_iotlb_insert(SMMUState *bs, SMMUTransCfg *cfg, SMMUTLBEntry *entry);
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-SMMUIOTLBKey smmu_get_iotlb_key(uint16_t asid, uint64_t iova);
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+SMMUIOTLBKey smmu_get_iotlb_key(uint16_t asid, uint64_t iova,
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+                                uint8_t tg, uint8_t level);
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 void smmu_iotlb_inv_all(SMMUState *s);
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 void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid);
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-void smmu_iotlb_inv_iova(SMMUState *s, uint16_t asid, dma_addr_t iova);
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+void smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova);
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 /* Unmap the range of all the notifiers registered to any IOMMU mr */
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 void smmu_inv_notifiers_all(SMMUState *s);
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-- 
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2.27.0
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