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From fbfa584e58a560f27081043ad8e90ee9022421c0 Mon Sep 17 00:00:00 2001
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From: eperezma <eperezma@redhat.com>
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Date: Tue, 12 Jan 2021 14:36:27 -0500
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Subject: [PATCH 03/17] hw/arm/smmu-common: Add IOTLB helpers
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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RH-Author: eperezma <eperezma@redhat.com>
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Message-id: <20210112143638.374060-3-eperezma@redhat.com>
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Patchwork-id: 100595
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O-Subject: [RHEL-8.4.0 qemu-kvm PATCH v2 02/13] hw/arm/smmu-common: Add IOTLB helpers
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Bugzilla: 1843852
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RH-Acked-by: Xiao Wang <jasowang@redhat.com>
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RH-Acked-by: Peter Xu <peterx@redhat.com>
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RH-Acked-by: Auger Eric <eric.auger@redhat.com>
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From: Eric Auger <eric.auger@redhat.com>
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Add two helpers: one to lookup for a given IOTLB entry and
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one to insert a new entry. We also move the tracing there.
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Signed-off-by: Eric Auger <eric.auger@redhat.com>
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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
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Message-id: 20200728150815.11446-3-eric.auger@redhat.com
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Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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(cherry picked from commit 6808bca939b8722d98165319ba42366ca80de907)
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Signed-off-by: Eugenio PĂ©rez <eperezma@redhat.com>
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Signed-off-by: Danilo C. L. de Paula <ddepaula@redhat.com>
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---
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 hw/arm/smmu-common.c         | 36 ++++++++++++++++++++++++++++++++++++
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 hw/arm/smmuv3.c              | 26 ++------------------------
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 hw/arm/trace-events          |  5 +++--
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 include/hw/arm/smmu-common.h |  2 ++
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 4 files changed, 43 insertions(+), 26 deletions(-)
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diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
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index d2ba8b224ba..8e01505dbee 100644
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--- a/hw/arm/smmu-common.c
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+++ b/hw/arm/smmu-common.c
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@@ -32,6 +32,42 @@
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 /* IOTLB Management */
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+IOMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTransCfg *cfg,
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+                                 hwaddr iova)
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+{
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+    SMMUIOTLBKey key = {.asid = cfg->asid, .iova = iova};
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+    IOMMUTLBEntry *entry = g_hash_table_lookup(bs->iotlb, &key);
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+
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+    if (entry) {
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+        cfg->iotlb_hits++;
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+        trace_smmu_iotlb_lookup_hit(cfg->asid, iova,
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+                                    cfg->iotlb_hits, cfg->iotlb_misses,
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+                                    100 * cfg->iotlb_hits /
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+                                    (cfg->iotlb_hits + cfg->iotlb_misses));
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+    } else {
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+        cfg->iotlb_misses++;
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+        trace_smmu_iotlb_lookup_miss(cfg->asid, iova,
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+                                     cfg->iotlb_hits, cfg->iotlb_misses,
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+                                     100 * cfg->iotlb_hits /
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+                                     (cfg->iotlb_hits + cfg->iotlb_misses));
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+    }
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+    return entry;
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+}
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+
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+void smmu_iotlb_insert(SMMUState *bs, SMMUTransCfg *cfg, IOMMUTLBEntry *entry)
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+{
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+    SMMUIOTLBKey *key = g_new0(SMMUIOTLBKey, 1);
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+
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+    if (g_hash_table_size(bs->iotlb) >= SMMU_IOTLB_MAX_SIZE) {
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+        smmu_iotlb_inv_all(bs);
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+    }
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+
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+    key->asid = cfg->asid;
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+    key->iova = entry->iova;
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+    trace_smmu_iotlb_insert(cfg->asid, entry->iova);
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+    g_hash_table_insert(bs->iotlb, key, entry);
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+}
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+
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 inline void smmu_iotlb_inv_all(SMMUState *s)
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 {
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     trace_smmu_iotlb_inv_all();
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diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
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index e2fbb8357ea..34dea4df4da 100644
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--- a/hw/arm/smmuv3.c
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+++ b/hw/arm/smmuv3.c
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@@ -624,7 +624,6 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr,
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         .addr_mask = ~(hwaddr)0,
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         .perm = IOMMU_NONE,
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     };
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-    SMMUIOTLBKey key, *new_key;
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     qemu_mutex_lock(&s->mutex);
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@@ -663,16 +662,8 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr,
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     page_mask = (1ULL << (tt->granule_sz)) - 1;
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     aligned_addr = addr & ~page_mask;
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-    key.asid = cfg->asid;
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-    key.iova = aligned_addr;
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-
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-    cached_entry = g_hash_table_lookup(bs->iotlb, &key);
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+    cached_entry = smmu_iotlb_lookup(bs, cfg, aligned_addr);
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     if (cached_entry) {
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-        cfg->iotlb_hits++;
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-        trace_smmu_iotlb_cache_hit(cfg->asid, aligned_addr,
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-                                   cfg->iotlb_hits, cfg->iotlb_misses,
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-                                   100 * cfg->iotlb_hits /
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-                                   (cfg->iotlb_hits + cfg->iotlb_misses));
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         if ((flag & IOMMU_WO) && !(cached_entry->perm & IOMMU_WO)) {
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             status = SMMU_TRANS_ERROR;
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             if (event.record_trans_faults) {
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@@ -686,16 +677,6 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr,
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         goto epilogue;
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     }
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-    cfg->iotlb_misses++;
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-    trace_smmu_iotlb_cache_miss(cfg->asid, addr & ~page_mask,
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-                                cfg->iotlb_hits, cfg->iotlb_misses,
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-                                100 * cfg->iotlb_hits /
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-                                (cfg->iotlb_hits + cfg->iotlb_misses));
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-
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-    if (g_hash_table_size(bs->iotlb) >= SMMU_IOTLB_MAX_SIZE) {
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-        smmu_iotlb_inv_all(bs);
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-    }
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-
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     cached_entry = g_new0(IOMMUTLBEntry, 1);
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     if (smmu_ptw(cfg, aligned_addr, flag, cached_entry, &ptw_info)) {
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@@ -741,10 +722,7 @@ static IOMMUTLBEntry smmuv3_translate(IOMMUMemoryRegion *mr, hwaddr addr,
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         }
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         status = SMMU_TRANS_ERROR;
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     } else {
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-        new_key = g_new0(SMMUIOTLBKey, 1);
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-        new_key->asid = cfg->asid;
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-        new_key->iova = aligned_addr;
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-        g_hash_table_insert(bs->iotlb, new_key, cached_entry);
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+        smmu_iotlb_insert(bs, cfg, cached_entry);
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         status = SMMU_TRANS_SUCCESS;
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     }
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diff --git a/hw/arm/trace-events b/hw/arm/trace-events
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index 0acedcedc6f..b808a1bfc19 100644
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--- a/hw/arm/trace-events
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+++ b/hw/arm/trace-events
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@@ -14,6 +14,9 @@ smmu_iotlb_inv_all(void) "IOTLB invalidate all"
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 smmu_iotlb_inv_asid(uint16_t asid) "IOTLB invalidate asid=%d"
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 smmu_iotlb_inv_iova(uint16_t asid, uint64_t addr) "IOTLB invalidate asid=%d addr=0x%"PRIx64
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 smmu_inv_notifiers_mr(const char *name) "iommu mr=%s"
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+smmu_iotlb_lookup_hit(uint16_t asid, uint64_t addr, uint32_t hit, uint32_t miss, uint32_t p) "IOTLB cache HIT asid=%d addr=0x%"PRIx64" hit=%d miss=%d hit rate=%d"
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+smmu_iotlb_lookup_miss(uint16_t asid, uint64_t addr, uint32_t hit, uint32_t miss, uint32_t p) "IOTLB cache MISS asid=%d addr=0x%"PRIx64" hit=%d miss=%d hit rate=%d"
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+smmu_iotlb_insert(uint16_t asid, uint64_t addr) "IOTLB ++ asid=%d addr=0x%"PRIx64
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 # smmuv3.c
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 smmuv3_read_mmio(uint64_t addr, uint64_t val, unsigned size, uint32_t r) "addr: 0x%"PRIx64" val:0x%"PRIx64" size: 0x%x(%d)"
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@@ -46,8 +49,6 @@ smmuv3_cmdq_tlbi_nh_va(int vmid, int asid, uint64_t addr, bool leaf) "vmid =%d a
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 smmuv3_cmdq_tlbi_nh_vaa(int vmid, uint64_t addr) "vmid =%d addr=0x%"PRIx64
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 smmuv3_cmdq_tlbi_nh(void) ""
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 smmuv3_cmdq_tlbi_nh_asid(uint16_t asid) "asid=%d"
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-smmu_iotlb_cache_hit(uint16_t asid, uint64_t addr, uint32_t hit, uint32_t miss, uint32_t p) "IOTLB cache HIT asid=%d addr=0x%"PRIx64" hit=%d miss=%d hit rate=%d"
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-smmu_iotlb_cache_miss(uint16_t asid, uint64_t addr, uint32_t hit, uint32_t miss, uint32_t p) "IOTLB cache MISS asid=%d addr=0x%"PRIx64" hit=%d miss=%d hit rate=%d"
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 smmuv3_config_cache_inv(uint32_t sid) "Config cache INV for sid %d"
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 smmuv3_notify_flag_add(const char *iommu) "ADD SMMUNotifier node for iommu mr=%s"
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 smmuv3_notify_flag_del(const char *iommu) "DEL SMMUNotifier node for iommu mr=%s"
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diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h
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index 1f37844e5c9..a28650c9350 100644
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--- a/include/hw/arm/smmu-common.h
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+++ b/include/hw/arm/smmu-common.h
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@@ -153,6 +153,8 @@ IOMMUMemoryRegion *smmu_iommu_mr(SMMUState *s, uint32_t sid);
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 #define SMMU_IOTLB_MAX_SIZE 256
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+IOMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTransCfg *cfg, hwaddr iova);
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+void smmu_iotlb_insert(SMMUState *bs, SMMUTransCfg *cfg, IOMMUTLBEntry *entry);
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 void smmu_iotlb_inv_all(SMMUState *s);
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 void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid);
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 void smmu_iotlb_inv_iova(SMMUState *s, uint16_t asid, dma_addr_t iova);
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-- 
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2.27.0
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