|
|
9ae3a8 |
From 6420a8c59712cce74ad689c0d692982665a785b0 Mon Sep 17 00:00:00 2001
|
|
|
9ae3a8 |
From: Gerd Hoffmann <kraxel@redhat.com>
|
|
|
9ae3a8 |
Date: Fri, 20 Oct 2017 11:06:19 +0200
|
|
|
9ae3a8 |
Subject: [PATCH 4/7] cirrus: fix oob access in mode4and5 write functions
|
|
|
9ae3a8 |
|
|
|
9ae3a8 |
RH-Author: Gerd Hoffmann <kraxel@redhat.com>
|
|
|
9ae3a8 |
Message-id: <20171020110619.2541-12-kraxel@redhat.com>
|
|
|
9ae3a8 |
Patchwork-id: 77403
|
|
|
9ae3a8 |
O-Subject: [RHEL-7.5 qemu-kvm PATCH 11/11] cirrus: fix oob access in mode4and5 write functions
|
|
|
9ae3a8 |
Bugzilla: 1501295
|
|
|
9ae3a8 |
RH-Acked-by: Stefan Hajnoczi <stefanha@redhat.com>
|
|
|
9ae3a8 |
RH-Acked-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
|
|
|
9ae3a8 |
RH-Acked-by: Miroslav Rezanina <mrezanin@redhat.com>
|
|
|
9ae3a8 |
|
|
|
9ae3a8 |
Move dst calculation into the loop, so we apply the mask on each
|
|
|
9ae3a8 |
interation and will not overflow vga memory.
|
|
|
9ae3a8 |
|
|
|
9ae3a8 |
Cc: Prasad J Pandit <pjp@fedoraproject.org>
|
|
|
9ae3a8 |
Reported-by: Niu Guoxiang <niuguoxiang@huawei.com>
|
|
|
9ae3a8 |
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
|
|
|
9ae3a8 |
Message-id: 20171011084314.21752-1-kraxel@redhat.com
|
|
|
9ae3a8 |
(cherry picked from commit eb38e1bc3740725ca29a535351de94107ec58d51)
|
|
|
9ae3a8 |
Signed-off-by: Miroslav Rezanina <mrezanin@redhat.com>
|
|
|
9ae3a8 |
---
|
|
|
9ae3a8 |
hw/display/cirrus_vga.c | 6 ++----
|
|
|
9ae3a8 |
1 file changed, 2 insertions(+), 4 deletions(-)
|
|
|
9ae3a8 |
|
|
|
9ae3a8 |
diff --git a/hw/display/cirrus_vga.c b/hw/display/cirrus_vga.c
|
|
|
9ae3a8 |
index c1324ab..a07fa9c 100644
|
|
|
9ae3a8 |
--- a/hw/display/cirrus_vga.c
|
|
|
9ae3a8 |
+++ b/hw/display/cirrus_vga.c
|
|
|
9ae3a8 |
@@ -2023,15 +2023,14 @@ static void cirrus_mem_writeb_mode4and5_8bpp(CirrusVGAState * s,
|
|
|
9ae3a8 |
unsigned val = mem_value;
|
|
|
9ae3a8 |
uint8_t *dst;
|
|
|
9ae3a8 |
|
|
|
9ae3a8 |
- dst = s->vga.vram_ptr + (offset &= s->cirrus_addr_mask);
|
|
|
9ae3a8 |
for (x = 0; x < 8; x++) {
|
|
|
9ae3a8 |
+ dst = s->vga.vram_ptr + ((offset + x) & s->cirrus_addr_mask);
|
|
|
9ae3a8 |
if (val & 0x80) {
|
|
|
9ae3a8 |
*dst = s->cirrus_shadow_gr1;
|
|
|
9ae3a8 |
} else if (mode == 5) {
|
|
|
9ae3a8 |
*dst = s->cirrus_shadow_gr0;
|
|
|
9ae3a8 |
}
|
|
|
9ae3a8 |
val <<= 1;
|
|
|
9ae3a8 |
- dst++;
|
|
|
9ae3a8 |
}
|
|
|
9ae3a8 |
memory_region_set_dirty(&s->vga.vram, offset, 8);
|
|
|
9ae3a8 |
}
|
|
|
9ae3a8 |
@@ -2045,8 +2044,8 @@ static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s,
|
|
|
9ae3a8 |
unsigned val = mem_value;
|
|
|
9ae3a8 |
uint8_t *dst;
|
|
|
9ae3a8 |
|
|
|
9ae3a8 |
- dst = s->vga.vram_ptr + (offset &= s->cirrus_addr_mask);
|
|
|
9ae3a8 |
for (x = 0; x < 8; x++) {
|
|
|
9ae3a8 |
+ dst = s->vga.vram_ptr + ((offset + 2 * x) & s->cirrus_addr_mask & ~1);
|
|
|
9ae3a8 |
if (val & 0x80) {
|
|
|
9ae3a8 |
*dst = s->cirrus_shadow_gr1;
|
|
|
9ae3a8 |
*(dst + 1) = s->vga.gr[0x11];
|
|
|
9ae3a8 |
@@ -2055,7 +2054,6 @@ static void cirrus_mem_writeb_mode4and5_16bpp(CirrusVGAState * s,
|
|
|
9ae3a8 |
*(dst + 1) = s->vga.gr[0x10];
|
|
|
9ae3a8 |
}
|
|
|
9ae3a8 |
val <<= 1;
|
|
|
9ae3a8 |
- dst += 2;
|
|
|
9ae3a8 |
}
|
|
|
9ae3a8 |
memory_region_set_dirty(&s->vga.vram, offset, 16);
|
|
|
9ae3a8 |
}
|
|
|
9ae3a8 |
--
|
|
|
9ae3a8 |
1.8.3.1
|
|
|
9ae3a8 |
|