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From 18e92ed681383c787912d0cd4b8164d8e7df26d4 Mon Sep 17 00:00:00 2001
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From: Fam Zheng <famz@redhat.com>
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Date: Thu, 18 May 2017 09:21:15 +0200
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Subject: [PATCH 02/18] char/serial: Use generic Fifo8
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RH-Author: Fam Zheng <famz@redhat.com>
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Message-id: <20170518092131.16571-3-famz@redhat.com>
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Patchwork-id: 75292
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O-Subject: [RHEL-7.4 qemu-kvm PATCH v3 02/18] char/serial: Use generic Fifo8
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Bugzilla: 1451470
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RH-Acked-by: Paolo Bonzini <pbonzini@redhat.com>
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RH-Acked-by: Stefan Hajnoczi <stefanha@redhat.com>
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RH-Acked-by: Eduardo Habkost <ehabkost@redhat.com>
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From: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
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Use the generic Fifo8 helper provided by QEMU, rather than re-implement
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privately.
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Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
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Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
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(cherry picked from commit 8e8638fa87ff045f5dadec7342301bf10de776ff)
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Signed-off-by: Fam Zheng <famz@redhat.com>
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Signed-off-by: Miroslav Rezanina <mrezanin@redhat.com>
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Conflicts:
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	hw/char/serial.c
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Conflict because in downstream we've got 4df7961faa out of order.
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---
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 hw/char/serial.c         | 98 +++++++++++++++++-------------------------------
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 include/hw/char/serial.h | 15 +++-----
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 2 files changed, 39 insertions(+), 74 deletions(-)
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diff --git a/hw/char/serial.c b/hw/char/serial.c
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index 7866b0f..0d4450e 100644
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--- a/hw/char/serial.c
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+++ b/hw/char/serial.c
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@@ -93,8 +93,6 @@
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 #define UART_FCR_RFR        0x02    /* RCVR Fifo Reset */
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 #define UART_FCR_FE         0x01    /* FIFO Enable */
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-#define XMIT_FIFO           0
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-#define RECV_FIFO           1
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 #define MAX_XMIT_RETRY      4
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 #ifdef DEBUG_SERIAL
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@@ -107,50 +105,14 @@ do {} while (0)
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 static void serial_receive1(void *opaque, const uint8_t *buf, int size);
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-static void fifo_clear(SerialState *s, int fifo)
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+static inline void recv_fifo_put(SerialState *s, uint8_t chr)
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 {
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-    SerialFIFO *f = (fifo) ? &s->recv_fifo : &s->xmit_fifo;
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-    memset(f->data, 0, UART_FIFO_LENGTH);
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-    f->count = 0;
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-    f->head = 0;
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-    f->tail = 0;
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-}
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-
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-static int fifo_put(SerialState *s, int fifo, uint8_t chr)
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-{
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-    SerialFIFO *f = (fifo) ? &s->recv_fifo : &s->xmit_fifo;
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-
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     /* Receive overruns do not overwrite FIFO contents. */
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-    if (fifo == XMIT_FIFO || f->count < UART_FIFO_LENGTH) {
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-
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-        f->data[f->head++] = chr;
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-
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-        if (f->head == UART_FIFO_LENGTH)
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-            f->head = 0;
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-    }
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-
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-    if (f->count < UART_FIFO_LENGTH)
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-        f->count++;
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-    else if (fifo == RECV_FIFO)
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+    if (!fifo8_is_full(&s->recv_fifo)) {
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+        fifo8_push(&s->recv_fifo, chr);
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+    } else {
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         s->lsr |= UART_LSR_OE;
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-
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-    return 1;
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-}
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-
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-static uint8_t fifo_get(SerialState *s, int fifo)
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-{
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-    SerialFIFO *f = (fifo) ? &s->recv_fifo : &s->xmit_fifo;
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-    uint8_t c;
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-
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-    if(f->count == 0)
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-        return 0;
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-
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-    c = f->data[f->tail++];
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-    if (f->tail == UART_FIFO_LENGTH)
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-        f->tail = 0;
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-    f->count--;
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-
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-    return c;
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+    }
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 }
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 static void serial_update_irq(SerialState *s)
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@@ -166,7 +128,7 @@ static void serial_update_irq(SerialState *s)
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         tmp_iir = UART_IIR_CTI;
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     } else if ((s->ier & UART_IER_RDI) && (s->lsr & UART_LSR_DR) &&
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                (!(s->fcr & UART_FCR_FE) ||
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-                s->recv_fifo.count >= s->recv_fifo.itl)) {
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+                s->recv_fifo.num >= s->recv_fifo_itl)) {
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         tmp_iir = UART_IIR_RDI;
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     } else if ((s->ier & UART_IER_THRI) && s->thr_ipending) {
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         tmp_iir = UART_IIR_THRI;
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@@ -263,8 +225,9 @@ static gboolean serial_xmit(GIOChannel *chan, GIOCondition cond, void *opaque)
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     if (s->tsr_retry <= 0) {
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         if (s->fcr & UART_FCR_FE) {
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-            s->tsr = fifo_get(s,XMIT_FIFO);
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-            if (!s->xmit_fifo.count) {
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+            s->tsr = fifo8_is_full(&s->xmit_fifo) ?
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+                        0 : fifo8_pop(&s->xmit_fifo);
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+            if (!s->xmit_fifo.num) {
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                 s->lsr |= UART_LSR_THRE;
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             }
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         } else if ((s->lsr & UART_LSR_THRE)) {
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@@ -318,7 +281,11 @@ static void serial_ioport_write(void *opaque, hwaddr addr, uint64_t val,
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         } else {
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             s->thr = (uint8_t) val;
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             if(s->fcr & UART_FCR_FE) {
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-                fifo_put(s, XMIT_FIFO, s->thr);
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+                /* xmit overruns overwrite data, so make space if needed */
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+                if (fifo8_is_full(&s->xmit_fifo)) {
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+                    fifo8_pop(&s->xmit_fifo);
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+                }
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+                fifo8_push(&s->xmit_fifo, s->thr);
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                 s->thr_ipending = 0;
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                 s->lsr &= ~UART_LSR_TEMT;
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                 s->lsr &= ~UART_LSR_THRE;
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@@ -369,28 +336,28 @@ static void serial_ioport_write(void *opaque, hwaddr addr, uint64_t val,
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         if (val & UART_FCR_RFR) {
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             qemu_del_timer(s->fifo_timeout_timer);
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             s->timeout_ipending=0;
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-            fifo_clear(s,RECV_FIFO);
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+            fifo8_reset(&s->recv_fifo);
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         }
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         if (val & UART_FCR_XFR) {
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-            fifo_clear(s,XMIT_FIFO);
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+            fifo8_reset(&s->xmit_fifo);
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         }
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         if (val & UART_FCR_FE) {
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             s->iir |= UART_IIR_FE;
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-            /* Set RECV_FIFO trigger Level */
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+            /* Set recv_fifo trigger Level */
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             switch (val & 0xC0) {
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             case UART_FCR_ITL_1:
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-                s->recv_fifo.itl = 1;
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+                s->recv_fifo_itl = 1;
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                 break;
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             case UART_FCR_ITL_2:
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-                s->recv_fifo.itl = 4;
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+                s->recv_fifo_itl = 4;
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                 break;
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             case UART_FCR_ITL_3:
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-                s->recv_fifo.itl = 8;
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+                s->recv_fifo_itl = 8;
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                 break;
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             case UART_FCR_ITL_4:
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-                s->recv_fifo.itl = 14;
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+                s->recv_fifo_itl = 14;
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                 break;
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             }
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         } else
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@@ -462,8 +429,9 @@ static uint64_t serial_ioport_read(void *opaque, hwaddr addr, unsigned size)
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             ret = s->divider & 0xff;
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         } else {
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             if(s->fcr & UART_FCR_FE) {
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-                ret = fifo_get(s,RECV_FIFO);
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-                if (s->recv_fifo.count == 0) {
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+                ret = fifo8_is_full(&s->recv_fifo) ?
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+                            0 : fifo8_pop(&s->recv_fifo);
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+                if (s->recv_fifo.num == 0) {
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                     s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
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                 } else {
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                     qemu_mod_timer(s->fifo_timeout_timer, qemu_get_clock_ns (vm_clock) + s->char_transmit_time * 4);
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@@ -537,7 +505,7 @@ static uint64_t serial_ioport_read(void *opaque, hwaddr addr, unsigned size)
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 static int serial_can_receive(SerialState *s)
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 {
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     if(s->fcr & UART_FCR_FE) {
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-        if (s->recv_fifo.count < UART_FIFO_LENGTH) {
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+        if (s->recv_fifo.num < UART_FIFO_LENGTH) {
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             /*
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              * Advertise (fifo.itl - fifo.count) bytes when count < ITL, and 1
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              * if above. If UART_FIFO_LENGTH - fifo.count is advertised the
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@@ -545,8 +513,8 @@ static int serial_can_receive(SerialState *s)
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              * the guest has a chance to respond, effectively overriding the ITL
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              * that the guest has set.
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              */
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-            return (s->recv_fifo.count <= s->recv_fifo.itl) ?
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-                        s->recv_fifo.itl - s->recv_fifo.count : 1;
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+            return (s->recv_fifo.num <= s->recv_fifo_itl) ?
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+                        s->recv_fifo_itl - s->recv_fifo.num : 1;
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         } else {
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             return 0;
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         }
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@@ -559,7 +527,7 @@ static void serial_receive_break(SerialState *s)
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 {
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     s->rbr = 0;
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     /* When the LSR_DR is set a null byte is pushed into the fifo */
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-    fifo_put(s, RECV_FIFO, '\0');
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+    recv_fifo_put(s, '\0');
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     s->lsr |= UART_LSR_BI | UART_LSR_DR;
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     serial_update_irq(s);
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 }
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@@ -567,7 +535,7 @@ static void serial_receive_break(SerialState *s)
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 /* There's data in recv_fifo and s->rbr has not been read for 4 char transmit times */
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 static void fifo_timeout_int (void *opaque) {
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     SerialState *s = opaque;
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-    if (s->recv_fifo.count) {
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+    if (s->recv_fifo.num) {
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         s->timeout_ipending = 1;
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         serial_update_irq(s);
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     }
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@@ -589,7 +557,7 @@ static void serial_receive1(void *opaque, const uint8_t *buf, int size)
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     if(s->fcr & UART_FCR_FE) {
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         int i;
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         for (i = 0; i < size; i++) {
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-            fifo_put(s, RECV_FIFO, buf[i]);
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+            recv_fifo_put(s, buf[i]);
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         }
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         s->lsr |= UART_LSR_DR;
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         /* call the timeout receive callback in 4 char transmit time */
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@@ -669,8 +637,8 @@ static void serial_reset(void *opaque)
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     s->char_transmit_time = (get_ticks_per_sec() / 9600) * 10;
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     s->poll_msl = 0;
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-    fifo_clear(s,RECV_FIFO);
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-    fifo_clear(s,XMIT_FIFO);
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+    fifo8_reset(&s->recv_fifo);
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+    fifo8_reset(&s->xmit_fifo);
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     s->last_xmit_ts = qemu_get_clock_ns(vm_clock);
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@@ -693,6 +661,8 @@ void serial_init_core(SerialState *s)
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     qemu_chr_add_handlers(s->chr, serial_can_receive1, serial_receive1,
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                           serial_event, s);
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+    fifo8_create(&s->recv_fifo, UART_FIFO_LENGTH);
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+    fifo8_create(&s->xmit_fifo, UART_FIFO_LENGTH);
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     serial_reset(s);
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 }
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diff --git a/include/hw/char/serial.h b/include/hw/char/serial.h
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index bca79f1..9ab81f6 100644
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--- a/include/hw/char/serial.h
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+++ b/include/hw/char/serial.h
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@@ -28,17 +28,10 @@
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 #include "hw/hw.h"
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 #include "sysemu/sysemu.h"
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 #include "exec/memory.h"
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+#include "qemu/fifo8.h"
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 #define UART_FIFO_LENGTH    16      /* 16550A Fifo Length */
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-typedef struct SerialFIFO {
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-    uint8_t data[UART_FIFO_LENGTH];
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-    uint8_t count;
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-    uint8_t itl;                        /* Interrupt Trigger Level */
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-    uint8_t tail;
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-    uint8_t head;
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-} SerialFIFO;
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-
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 struct SerialState {
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     uint16_t divider;
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     uint8_t rbr; /* receive register */
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@@ -67,8 +60,10 @@ struct SerialState {
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     /* Time when the last byte was successfully sent out of the tsr */
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     uint64_t last_xmit_ts;
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-    SerialFIFO recv_fifo;
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-    SerialFIFO xmit_fifo;
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+    Fifo8 recv_fifo;
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+    Fifo8 xmit_fifo;
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+    /* Interrupt trigger level for recv_fifo */
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+    uint8_t recv_fifo_itl;
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     struct QEMUTimer *fifo_timeout_timer;
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     int timeout_ipending;           /* timeout interrupt pending state */
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-- 
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1.8.3.1
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