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Blame SOURCES/kvm-x86-Add-XFD-faulting-bit-for-state-components.patch

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From 098d6a965ada02f5897b73f0489413a050a176bb Mon Sep 17 00:00:00 2001
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From: Jing Liu <jing2.liu@intel.com>
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Date: Wed, 16 Feb 2022 22:04:30 -0800
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Subject: [PATCH 08/24] x86: Add XFD faulting bit for state components
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RH-Author: Paul Lai <plai@redhat.com>
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RH-MergeRequest: 176: Enable KVM AMX support
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RH-Commit: [8/13] 0b1b46c5d075655ab94bc79e042b187c5dc55551
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RH-Bugzilla: 1916415
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RH-Acked-by: Cornelia Huck <cohuck@redhat.com>
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RH-Acked-by: Igor Mammedov <imammedo@redhat.com>
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RH-Acked-by: Paolo Bonzini <pbonzini@redhat.com>
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Intel introduces XFD faulting mechanism for extended
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XSAVE features to dynamically enable the features in
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runtime. If CPUID (EAX=0Dh, ECX=n, n>1).ECX[2] is set
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as 1, it indicates support for XFD faulting of this
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state component.
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Signed-off-by: Jing Liu <jing2.liu@intel.com>
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Signed-off-by: Yang Zhong <yang.zhong@intel.com>
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Message-Id: <20220217060434.52460-5-yang.zhong@intel.com>
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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(cherry picked from commit 0f17f6b30f3b051f0f96ccc98c9f7f395713699f)
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Signed-off-by: Paul Lai <plai@redhat.com>
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---
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 target/i386/cpu.c | 3 ++-
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 target/i386/cpu.h | 2 ++
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 2 files changed, 4 insertions(+), 1 deletion(-)
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diff --git a/target/i386/cpu.c b/target/i386/cpu.c
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index c19b51ea32..cd27c0eb81 100644
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--- a/target/i386/cpu.c
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+++ b/target/i386/cpu.c
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@@ -5503,7 +5503,8 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
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                 const ExtSaveArea *esa = &x86_ext_save_areas[count];
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                 *eax = esa->size;
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                 *ebx = esa->offset;
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-                *ecx = esa->ecx & ESA_FEATURE_ALIGN64_MASK;
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+                *ecx = esa->ecx &
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+                       (ESA_FEATURE_ALIGN64_MASK | ESA_FEATURE_XFD_MASK);
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             }
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         }
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         break;
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diff --git a/target/i386/cpu.h b/target/i386/cpu.h
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index 58676390e6..f2bdef9c26 100644
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--- a/target/i386/cpu.h
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+++ b/target/i386/cpu.h
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@@ -555,8 +555,10 @@ typedef enum X86Seg {
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 #define XSTATE_DYNAMIC_MASK             (XSTATE_XTILE_DATA_MASK)
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 #define ESA_FEATURE_ALIGN64_BIT         1
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+#define ESA_FEATURE_XFD_BIT             2
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 #define ESA_FEATURE_ALIGN64_MASK        (1U << ESA_FEATURE_ALIGN64_BIT)
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+#define ESA_FEATURE_XFD_MASK            (1U << ESA_FEATURE_XFD_BIT)
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 /* CPUID feature words */
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-- 
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2.35.3
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