|
 |
26ba25 |
From ad1adce48f771ecc03b75575edbe09bca569167a Mon Sep 17 00:00:00 2001
|
|
|
26ba25 |
From: Suraj Jitindar Singh <sursingh@redhat.com>
|
|
|
26ba25 |
Date: Thu, 21 Jun 2018 06:56:48 +0200
|
|
|
26ba25 |
Subject: [PATCH 061/268] target/ppc: Don't require private l1d cache on POWER8
|
|
|
26ba25 |
for cap_ppc_safe_cache
|
|
|
26ba25 |
|
|
|
26ba25 |
RH-Author: Suraj Jitindar Singh <sursingh@redhat.com>
|
|
|
26ba25 |
Message-id: <1529564209-30369-3-git-send-email-sursingh@redhat.com>
|
|
|
26ba25 |
Patchwork-id: 80930
|
|
|
26ba25 |
O-Subject: [RHEL-7.6 qemu-kvm-rhev PATCH 2/3] target/ppc: Don't require private l1d cache on POWER8 for cap_ppc_safe_cache
|
|
|
26ba25 |
Bugzilla: 1560847
|
|
|
26ba25 |
RH-Acked-by: Laurent Vivier <lvivier@redhat.com>
|
|
|
26ba25 |
RH-Acked-by: David Gibson <dgibson@redhat.com>
|
|
|
26ba25 |
RH-Acked-by: Miroslav Rezanina <mrezanin@redhat.com>
|
|
|
26ba25 |
|
|
|
26ba25 |
From: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
|
|
|
26ba25 |
|
|
|
26ba25 |
For cap_ppc_safe_cache to be set to workaround, we require both a l1d
|
|
|
26ba25 |
cache flush instruction and private l1d cache.
|
|
|
26ba25 |
|
|
|
26ba25 |
On POWER8 don't require private l1d cache. This means a guest on a
|
|
|
26ba25 |
POWER8 machine can make use of the cache flush workarounds.
|
|
|
26ba25 |
|
|
|
26ba25 |
Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
|
|
|
26ba25 |
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
|
|
|
26ba25 |
(cherry picked from commit 072f416a53ead5211c987cb2068ee9dbd7ba06cc)
|
|
|
26ba25 |
|
|
|
26ba25 |
Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=1560847
|
|
|
26ba25 |
|
|
|
26ba25 |
Signed-off-by: Suraj Jitindar Singh <sursingh@redhat.com>
|
|
|
26ba25 |
Signed-off-by: Miroslav Rezanina <mrezanin@redhat.com>
|
|
|
26ba25 |
---
|
|
|
26ba25 |
target/ppc/kvm.c | 19 ++++++++++++++++++-
|
|
|
26ba25 |
1 file changed, 18 insertions(+), 1 deletion(-)
|
|
|
26ba25 |
|
|
|
26ba25 |
diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c
|
|
|
26ba25 |
index d787032..192c40d 100644
|
|
|
26ba25 |
--- a/target/ppc/kvm.c
|
|
|
26ba25 |
+++ b/target/ppc/kvm.c
|
|
|
26ba25 |
@@ -2461,11 +2461,28 @@ bool kvmppc_has_cap_mmu_hash_v3(void)
|
|
|
26ba25 |
return cap_mmu_hash_v3;
|
|
|
26ba25 |
}
|
|
|
26ba25 |
|
|
|
26ba25 |
+static bool kvmppc_power8_host(void)
|
|
|
26ba25 |
+{
|
|
|
26ba25 |
+ bool ret = false;
|
|
|
26ba25 |
+#ifdef TARGET_PPC64
|
|
|
26ba25 |
+ {
|
|
|
26ba25 |
+ uint32_t base_pvr = CPU_POWERPC_POWER_SERVER_MASK & mfpvr();
|
|
|
26ba25 |
+ ret = (base_pvr == CPU_POWERPC_POWER8E_BASE) ||
|
|
|
26ba25 |
+ (base_pvr == CPU_POWERPC_POWER8NVL_BASE) ||
|
|
|
26ba25 |
+ (base_pvr == CPU_POWERPC_POWER8_BASE);
|
|
|
26ba25 |
+ }
|
|
|
26ba25 |
+#endif /* TARGET_PPC64 */
|
|
|
26ba25 |
+ return ret;
|
|
|
26ba25 |
+}
|
|
|
26ba25 |
+
|
|
|
26ba25 |
static int parse_cap_ppc_safe_cache(struct kvm_ppc_cpu_char c)
|
|
|
26ba25 |
{
|
|
|
26ba25 |
+ bool l1d_thread_priv_req = !kvmppc_power8_host();
|
|
|
26ba25 |
+
|
|
|
26ba25 |
if (~c.behaviour & c.behaviour_mask & H_CPU_BEHAV_L1D_FLUSH_PR) {
|
|
|
26ba25 |
return 2;
|
|
|
26ba25 |
- } else if ((c.character & c.character_mask & H_CPU_CHAR_L1D_THREAD_PRIV) &&
|
|
|
26ba25 |
+ } else if ((!l1d_thread_priv_req ||
|
|
|
26ba25 |
+ c.character & c.character_mask & H_CPU_CHAR_L1D_THREAD_PRIV) &&
|
|
|
26ba25 |
(c.character & c.character_mask
|
|
|
26ba25 |
& (H_CPU_CHAR_L1D_FLUSH_ORI30 | H_CPU_CHAR_L1D_FLUSH_TRIG2))) {
|
|
|
26ba25 |
return 1;
|
|
|
26ba25 |
--
|
|
|
26ba25 |
1.8.3.1
|
|
|
26ba25 |
|