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Blame SOURCES/kvm-target-i386-cpu-add-new-CPU-models-for-indirect-bran.patch

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From d4caecffd38c2a9c16ea717e9c863d3214093b32 Mon Sep 17 00:00:00 2001
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From: Eduardo Habkost <ehabkost@redhat.com>
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Date: Wed, 13 Dec 2017 15:42:57 -0200
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Subject: [PATCH 3/3] target-i386: cpu: add new CPU models for indirect branch
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 predictor restrictions
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RH-Author: Eduardo Habkost <ehabkost@redhat.com>
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Message-id: <20171213174257.20475-4-ehabkost@redhat.com>
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Patchwork-id: n/a
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O-Subject: [CONFIDENTIAL][RHEL-7.4.z qemu-kvm PATCH v2 3/3] target-i386: cpu: add
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 new CPU models for indirect branch predictor restrictions
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Bugzilla: CVE-2017-5715
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RH-Acked-by: Paolo Bonzini <pbonzini@redhat.com>
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RH-Acked-by: Miroslav Rezanina <mrezanin@redhat.com>
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RH-Acked-by: Wainer dos Santos Moschetta <wainersm@redhat.com>
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To ensure the New CPU models won't introduce any unexpected
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changes except for the spec-ctrl feature (even if people are
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running older machine-types), copy all compat_props entries for
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existing CPU models to their *-IBRS versions.
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The only entries that are not being copied are the ones touching
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"(min-)level" and "(min-)xlevel" because it's an expected result
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of the CPU model change (otherwise the spec-ctrl feature would
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remain unavailable to the guest).
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The entries that had to be copied can be found using:
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  $ git grep -E 'Nehalem|Westmere|SandyBridge|IvyBridge|Haswell-noTSX|Haswell|Broadwell-noTSX|Broadwell|Skylake-Client|Skylake-Server|EPYC'
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Note that the upstream-only PC_COMPAT_* macros are not being
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touched as they are not used by the RHEL machine-types.
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---
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 hw/i386/pc_piix.c |  17 ++++
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 hw/i386/pc_q35.c  |   1 +
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 target-i386/cpu.c | 236 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
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 target-i386/cpu.h |   3 +
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 4 files changed, 257 insertions(+)
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diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
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index b043124..c53a6d4 100644
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--- a/hw/i386/pc_piix.c
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+++ b/hw/i386/pc_piix.c
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@@ -753,7 +753,9 @@ static void pc_compat_rhel700(QEMUMachineInitArgs *args)
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     x86_cpu_compat_set_features("Conroe", FEAT_1_ECX, CPUID_EXT_X2APIC, 0);
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     x86_cpu_compat_set_features("Penryn", FEAT_1_ECX, CPUID_EXT_X2APIC, 0);
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     x86_cpu_compat_set_features("Nehalem", FEAT_1_ECX, CPUID_EXT_X2APIC, 0);
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+    x86_cpu_compat_set_features("Nehalem-IBRS", FEAT_1_ECX, CPUID_EXT_X2APIC, 0);
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     x86_cpu_compat_set_features("Westmere", FEAT_1_ECX, CPUID_EXT_X2APIC, 0);
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+    x86_cpu_compat_set_features("Westmere-IBRS", FEAT_1_ECX, CPUID_EXT_X2APIC, 0);
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     /* SandyBridge and Haswell already have x2apic enabled */
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     x86_cpu_compat_set_features("Opteron_G1", FEAT_1_ECX, CPUID_EXT_X2APIC, 0);
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     x86_cpu_compat_set_features("Opteron_G2", FEAT_1_ECX, CPUID_EXT_X2APIC, 0);
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@@ -928,18 +930,31 @@ static void pc_compat_rhel660(QEMUMachineInitArgs *args)
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     x86_cpu_compat_set_features("Conroe", FEAT_1_ECX, CPUID_EXT_X2APIC, 0);
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     x86_cpu_compat_set_features("Penryn", FEAT_1_ECX, CPUID_EXT_X2APIC, 0);
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     x86_cpu_compat_set_features("Nehalem", FEAT_1_ECX, CPUID_EXT_X2APIC, 0);
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+    x86_cpu_compat_set_features("Nehalem-IBRS", FEAT_1_ECX, CPUID_EXT_X2APIC, 0);
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     x86_cpu_compat_set_features("Westmere", FEAT_1_ECX, CPUID_EXT_X2APIC, 0);
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+    x86_cpu_compat_set_features("Westmere-IBRS", FEAT_1_ECX, CPUID_EXT_X2APIC, 0);
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     x86_cpu_compat_set_features("Westmere", FEAT_1_ECX, 0, CPUID_EXT_PCLMULQDQ);
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+    x86_cpu_compat_set_features("Westmere-IBRS", FEAT_1_ECX, 0, CPUID_EXT_PCLMULQDQ);
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     x86_cpu_compat_set_features("Westmere", FEAT_8000_0001_EDX,
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              CPUID_EXT2_FXSR | CPUID_EXT2_MMX | CPUID_EXT2_PAT |
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              CPUID_EXT2_CMOV | CPUID_EXT2_PGE | CPUID_EXT2_APIC |
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              CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
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              CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
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              0);
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+    x86_cpu_compat_set_features("Westmere-IBRS", FEAT_8000_0001_EDX,
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+             CPUID_EXT2_FXSR | CPUID_EXT2_MMX | CPUID_EXT2_PAT |
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+             CPUID_EXT2_CMOV | CPUID_EXT2_PGE | CPUID_EXT2_APIC |
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+             CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
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+             CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
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+             0);
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     x86_cpu_compat_set_features("Broadwell", FEAT_8000_0001_EDX,
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                                 0, CPUID_EXT2_RDTSCP);
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+    x86_cpu_compat_set_features("Broadwell-IBRS", FEAT_8000_0001_EDX,
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+                                0, CPUID_EXT2_RDTSCP);
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     x86_cpu_compat_set_features("Broadwell", FEAT_7_0_EBX,
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                                 0, CPUID_7_0_EBX_SMAP);
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+    x86_cpu_compat_set_features("Broadwell-IBRS", FEAT_7_0_EBX,
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+                                0, CPUID_7_0_EBX_SMAP);
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     /* RHEL-6 kernel never supported exposing RDTSCP */
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     x86_cpu_compat_set_features(NULL, FEAT_8000_0001_EDX, 0, CPUID_EXT2_RDTSCP);
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@@ -1122,6 +1137,8 @@ static void pc_compat_rhel630(QEMUMachineInitArgs *args)
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     enable_compat_apic_id_mode();
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     x86_cpu_compat_set_features("SandyBridge", FEAT_1_ECX,
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                                 0, CPUID_EXT_TSC_DEADLINE_TIMER);
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+    x86_cpu_compat_set_features("SandyBridge-IBRS", FEAT_1_ECX,
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+                                0, CPUID_EXT_TSC_DEADLINE_TIMER);
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 }
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 static void pc_init_rhel630(QEMUMachineInitArgs *args)
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diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c
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index 850a25a..e6043df 100644
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--- a/hw/i386/pc_q35.c
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+++ b/hw/i386/pc_q35.c
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@@ -228,6 +228,7 @@ static void pc_q35_init_1_4(QEMUMachineInitArgs *args)
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 {
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     x86_cpu_compat_set_features("n270", FEAT_1_ECX, 0, CPUID_EXT_MOVBE);
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     x86_cpu_compat_set_features("Westmere", FEAT_1_ECX, 0, CPUID_EXT_PCLMULQDQ);
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+    x86_cpu_compat_set_features("Westmere-IBRS", FEAT_1_ECX, 0, CPUID_EXT_PCLMULQDQ);
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     pc_q35_init_1_5(args);
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 }
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diff --git a/target-i386/cpu.c b/target-i386/cpu.c
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index 400a7ab..9e238ba 100644
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--- a/target-i386/cpu.c
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+++ b/target-i386/cpu.c
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@@ -882,6 +882,31 @@ static x86_def_t builtin_x86_defs[] = {
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         .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
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     },
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     {
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+        .name = "Nehalem-IBRS",
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+        .level = 11,
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+        .vendor = CPUID_VENDOR_INTEL,
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+        .family = 6,
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+        .model = 26,
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+        .stepping = 3,
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+        .features[FEAT_1_EDX] =
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+            CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
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+             CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
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+             CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
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+             CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
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+             CPUID_DE | CPUID_FP87,
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+        .features[FEAT_1_ECX] =
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+            CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
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+             CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
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+        .features[FEAT_7_0_EDX] =
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+            CPUID_7_0_EDX_SPEC_CTRL,
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+        .features[FEAT_8000_0001_EDX] =
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+            CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
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+        .features[FEAT_8000_0001_ECX] =
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+            CPUID_EXT3_LAHF_LM,
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+        .xlevel = 0x80000008,
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+        .model_id = "Intel Core i7 9xx (Nehalem Core i7, IBRS update)",
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+    },
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+    {
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         .name = "Westmere",
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         .level = 11,
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         .vendor = CPUID_VENDOR_INTEL,
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@@ -906,6 +931,32 @@ static x86_def_t builtin_x86_defs[] = {
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         .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
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     },
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     {
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+        .name = "Westmere-IBRS",
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+        .level = 11,
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+        .vendor = CPUID_VENDOR_INTEL,
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+        .family = 6,
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+        .model = 44,
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+        .stepping = 1,
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+        .features[FEAT_1_EDX] =
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+            CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
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+             CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
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+             CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
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+             CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
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+             CPUID_DE | CPUID_FP87,
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+        .features[FEAT_1_ECX] =
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+            CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
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+             CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
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+             CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
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+        .features[FEAT_8000_0001_EDX] =
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+            CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
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+        .features[FEAT_8000_0001_ECX] =
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+            CPUID_EXT3_LAHF_LM,
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+	.features[FEAT_7_0_EDX] =
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+	    CPUID_7_0_EDX_SPEC_CTRL,
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+        .xlevel = 0x80000008,
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+        .model_id = "Westmere E56xx/L56xx/X56xx (IBRS update)",
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+    },
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+    {
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         .name = "SandyBridge",
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         .level = 0xd,
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         .vendor = CPUID_VENDOR_INTEL,
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@@ -935,6 +986,37 @@ static x86_def_t builtin_x86_defs[] = {
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         .model_id = "Intel Xeon E312xx (Sandy Bridge)",
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     },
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     {
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+        .name = "SandyBridge-IBRS",
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+        .level = 0xd,
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+        .vendor = CPUID_VENDOR_INTEL,
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+        .family = 6,
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+        .model = 42,
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+        .stepping = 1,
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+        .features[FEAT_1_EDX] =
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+            CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
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+             CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
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+             CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
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+             CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
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+             CPUID_DE | CPUID_FP87,
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+        .features[FEAT_1_ECX] =
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+            CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
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+             CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
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+             CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
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+             CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
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+             CPUID_EXT_SSE3,
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+        .features[FEAT_8000_0001_EDX] =
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+            CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
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+             CPUID_EXT2_SYSCALL,
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+        .features[FEAT_8000_0001_ECX] =
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+            CPUID_EXT3_LAHF_LM,
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+	.features[FEAT_7_0_EDX] =
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+	    CPUID_7_0_EDX_SPEC_CTRL,
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+        .features[FEAT_XSAVE] =
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+            CPUID_XSAVE_XSAVEOPT,
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+        .xlevel = 0x80000008,
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+        .model_id = "Intel Xeon E312xx (Sandy Bridge, IBRS update)",
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+    },
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+    {
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         .name = "IvyBridge",
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         .level = 0xd,
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         .vendor = CPUID_VENDOR_INTEL,
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@@ -967,6 +1049,40 @@ static x86_def_t builtin_x86_defs[] = {
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         .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge)",
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     },
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     {
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+        .name = "IvyBridge-IBRS",
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+        .level = 0xd,
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+        .vendor = CPUID_VENDOR_INTEL,
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+        .family = 6,
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+        .model = 58,
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+        .stepping = 9,
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+        .features[FEAT_1_EDX] =
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+            CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
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+            CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
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+            CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
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+            CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
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+            CPUID_DE | CPUID_FP87,
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+        .features[FEAT_1_ECX] =
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+            CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
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+            CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
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+            CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
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+            CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
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+            CPUID_EXT_SSE3 | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
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+        .features[FEAT_7_0_EBX] =
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+            CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_SMEP |
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+            CPUID_7_0_EBX_ERMS,
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+        .features[FEAT_8000_0001_EDX] =
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+            CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
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+            CPUID_EXT2_SYSCALL,
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+        .features[FEAT_8000_0001_ECX] =
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+            CPUID_EXT3_LAHF_LM,
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+	.features[FEAT_7_0_EDX] =
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+	    CPUID_7_0_EDX_SPEC_CTRL,
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+        .features[FEAT_XSAVE] =
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+            CPUID_XSAVE_XSAVEOPT,
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+        .xlevel = 0x80000008,
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+        .model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)",
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+    },
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+    {
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         .name = "Haswell",
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         .level = 0xd,
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         .vendor = CPUID_VENDOR_INTEL,
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@@ -1002,6 +1118,43 @@ static x86_def_t builtin_x86_defs[] = {
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         .model_id = "Intel Core Processor (Haswell)",
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     },
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     {
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+        .name = "Haswell-IBRS",
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+        .level = 0xd,
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+        .vendor = CPUID_VENDOR_INTEL,
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+        .family = 6,
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+        .model = 60,
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+        .stepping = 4,
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+        .features[FEAT_1_EDX] =
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+            CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
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+             CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
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+             CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
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+             CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
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+             CPUID_DE | CPUID_FP87,
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+        .features[FEAT_1_ECX] =
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+            CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
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+             CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
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+             CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
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+             CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
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+             CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
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+             CPUID_EXT_PCID,
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+        .features[FEAT_8000_0001_EDX] =
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+            CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
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+             CPUID_EXT2_SYSCALL,
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+        .features[FEAT_8000_0001_ECX] =
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+            CPUID_EXT3_LAHF_LM,
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+	.features[FEAT_7_0_EDX] =
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+	    CPUID_7_0_EDX_SPEC_CTRL,
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+        .features[FEAT_7_0_EBX] =
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+            CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
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+            CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
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+            CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
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+            CPUID_7_0_EBX_RTM,
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+        .features[FEAT_XSAVE] =
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+            CPUID_XSAVE_XSAVEOPT,
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+        .xlevel = 0x80000008,
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+        .model_id = "Intel Core Processor (Haswell, IBRS)",
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+    },
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+    {
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         .name = "Broadwell",
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         .level = 0xd,
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         .vendor = CPUID_VENDOR_INTEL,
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@@ -1038,6 +1191,44 @@ static x86_def_t builtin_x86_defs[] = {
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         .model_id = "Intel Core Processor (Broadwell)",
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     },
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     {
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+        .name = "Broadwell-IBRS",
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+        .level = 0xd,
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+        .vendor = CPUID_VENDOR_INTEL,
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+        .family = 6,
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+        .model = 61,
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+        .stepping = 2,
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+        .features[FEAT_1_EDX] =
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+            CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
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+            CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
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+            CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
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+            CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
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+            CPUID_DE | CPUID_FP87,
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+        .features[FEAT_1_ECX] =
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+            CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
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+            CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
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+            CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
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+            CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
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+            CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
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+            CPUID_EXT_PCID,
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+        .features[FEAT_8000_0001_EDX] =
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+            CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
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+            CPUID_EXT2_SYSCALL,
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+        .features[FEAT_8000_0001_ECX] =
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+            CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
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+	.features[FEAT_7_0_EDX] =
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+	    CPUID_7_0_EDX_SPEC_CTRL,
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+        .features[FEAT_7_0_EBX] =
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+            CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
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+            CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
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+            CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
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+            CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
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+            CPUID_7_0_EBX_SMAP,
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+        .features[FEAT_XSAVE] =
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+            CPUID_XSAVE_XSAVEOPT,
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+        .xlevel = 0x80000008,
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+        .model_id = "Intel Core Processor (Broadwell, IBRS)",
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+    },
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+    {
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         .name = "Skylake-Client",
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         .level = 0xd,
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         .vendor = CPUID_VENDOR_INTEL,
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@@ -1081,6 +1272,51 @@ static x86_def_t builtin_x86_defs[] = {
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         .model_id = "Intel Core Processor (Skylake)",
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     },
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     {
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+        .name = "Skylake-Client-IBRS",
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+        .level = 0xd,
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+        .vendor = CPUID_VENDOR_INTEL,
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+        .family = 6,
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+        .model = 94,
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+        .stepping = 3,
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+        .features[FEAT_1_EDX] =
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+            CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
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+            CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
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+            CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
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+            CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
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+            CPUID_DE | CPUID_FP87,
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+        .features[FEAT_1_ECX] =
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+            CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
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+            CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
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+            CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
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+            CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
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+            CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
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+            CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
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+        .features[FEAT_8000_0001_EDX] =
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+            CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
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+            CPUID_EXT2_SYSCALL,
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+        .features[FEAT_8000_0001_ECX] =
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+            CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
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+	.features[FEAT_7_0_EDX] =
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+	    CPUID_7_0_EDX_SPEC_CTRL,
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+        .features[FEAT_7_0_EBX] =
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+            CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
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+            CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
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+            CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
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+            CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
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+            CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_MPX,
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+        /* Missing: XSAVES (not supported by some Linux versions,
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+         * including v4.1 to v4.12).
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+         * KVM doesn't yet expose any XSAVES state save component,
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+         * and the only one defined in Skylake (processor tracing)
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+         * probably will block migration anyway.
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+         */
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+        .features[FEAT_XSAVE] =
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+            CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
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+            CPUID_XSAVE_XGETBV1,
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+        .xlevel = 0x80000008,
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+        .model_id = "Intel Core Processor (Skylake, IBRS)",
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+    },
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+    {
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         .name = "Opteron_G1",
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         .level = 5,
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         .vendor = CPUID_VENDOR_AMD,
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diff --git a/target-i386/cpu.h b/target-i386/cpu.h
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index b23242d..9353b48 100644
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--- a/target-i386/cpu.h
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+++ b/target-i386/cpu.h
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@@ -587,6 +587,9 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
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 #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network Instructions */
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 #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation Single Precision */
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+#define CPUID_7_0_EDX_SPEC_CTRL     (1U << 26) /* Indirect Branch - Restrict Speculation */
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+
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+#define CPUID_8000_0008_EBX_IBPB    (1U << 12) /* Indirect Branch Prediction Barrier */
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 #define CPUID_XSAVE_XSAVEOPT   (1U << 0)
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 #define CPUID_XSAVE_XSAVEC     (1U << 1)
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-- 
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1.8.3.1
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