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From 99ce2407227bd5474e69c93ab0f061f2a3438eac Mon Sep 17 00:00:00 2001
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From: Eduardo Habkost <ehabkost@redhat.com>
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Date: Fri, 2 Aug 2013 14:08:52 +0200
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Subject: target-i386: Disable PMU CPUID leaf by default
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RH-Author: Eduardo Habkost <ehabkost@redhat.com>
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Message-id: <1375452533-12507-3-git-send-email-ehabkost@redhat.com>
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Patchwork-id: 52933
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O-Subject: [RHEL-7 PATCH 2/3] target-i386: Disable PMU CPUID leaf by default
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Bugzilla: 853101
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RH-Acked-by: Bandan Das <bsd@redhat.com>
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RH-Acked-by: Markus Armbruster <armbru@redhat.com>
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RH-Acked-by: Gleb Natapov <gleb@redhat.com>
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Bugzilla: 853101
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Bug description: QEMU currently gets all bits from GET_SUPPORTED_CPUID
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for CPUID leaf 0xA and passes them directly to the guest. This makes
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the guest ABI depend on host kernel and host CPU capabilities, and
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breaks live migration if we migrate between hosts with different
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capabilities (e.g., different number of PMU counters).
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Add a "pmu" property to X86CPU, and set it to true only on "-cpu host",
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or on pc-*-1.5 and older machine-types.
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For now, setting pmu=on will enable the current passthrough mode that
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doesn't have any ABI stability guarantees, but in the future we may
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implement a mode where the PMU CPUID bits are stable and configurable.
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Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
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Cc: Paolo Bonzini <pbonzini@redhat.com>
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Signed-off-by: Andreas Färber <afaerber@suse.de>
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(cherry picked from commit 9337e3b6e1d779215423d9b419d42200506deaab)
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Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
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Conflicts:
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include/hw/i386/pc.h
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target-i386/cpu.c
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diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
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index 6692728..45487ba 100644
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--- a/include/hw/i386/pc.h
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+++ b/include/hw/i386/pc.h
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@@ -211,6 +211,10 @@ int e820_add_entry(uint64_t, uint64_t, uint32_t);
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.driver = "Nehalem-" TYPE_X86_CPU,\
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.property = "level",\
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.value = stringify(2),\
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+ },{\
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+ .driver = TYPE_X86_CPU,\
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+ .property = "pmu",\
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+ .value = "on",\
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}
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#define PC_COMPAT_1_4 \
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diff --git a/target-i386/cpu-qom.h b/target-i386/cpu-qom.h
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index 849cedf..5231005 100644
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--- a/target-i386/cpu-qom.h
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+++ b/target-i386/cpu-qom.h
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@@ -68,6 +68,13 @@ typedef struct X86CPU {
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/* Features that were filtered out because of missing host capabilities */
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uint32_t filtered_features[FEATURE_WORDS];
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+
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+ /* Enable PMU CPUID bits. This can't be enabled by default yet because
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+ * it doesn't have ABI stability guarantees, as it passes all PMU CPUID
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+ * bits returned by GET_SUPPORTED_CPUID (that depend on host CPU and kernel
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+ * capabilities) directly to the guest.
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+ */
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+ bool enable_pmu;
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} X86CPU;
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static inline X86CPU *x86_env_get_cpu(CPUX86State *env)
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diff --git a/target-i386/cpu.c b/target-i386/cpu.c
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index 0c9a99a..2bcc21e 100644
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--- a/target-i386/cpu.c
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+++ b/target-i386/cpu.c
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@@ -1479,6 +1479,7 @@ static int cpu_x86_find_by_name(X86CPU *cpu, x86_def_t *x86_cpu_def,
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const char *name)
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{
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x86_def_t *def;
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+ Error *err = NULL;
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int i;
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if (name == NULL) {
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@@ -1486,6 +1487,8 @@ static int cpu_x86_find_by_name(X86CPU *cpu, x86_def_t *x86_cpu_def,
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}
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if (kvm_enabled() && strcmp(name, "host") == 0) {
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kvm_cpu_fill_host(x86_cpu_def);
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+ object_property_set_bool(OBJECT(cpu), true, "pmu", &err;;
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+ assert_no_error(err);
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return 0;
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}
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@@ -2017,7 +2020,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
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break;
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case 0xA:
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/* Architectural Performance Monitoring Leaf */
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- if (kvm_enabled()) {
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+ if (kvm_enabled() && cpu->enable_pmu) {
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KVMState *s = cs->kvm_state;
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*eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
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@@ -2506,6 +2509,11 @@ static int64_t x86_cpu_get_arch_id(CPUState *cs)
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return env->cpuid_apic_id;
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}
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+static Property x86_cpu_properties[] = {
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+ DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
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+ DEFINE_PROP_END_OF_LIST()
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+};
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+
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static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
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{
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X86CPUClass *xcc = X86_CPU_CLASS(oc);
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@@ -2515,6 +2523,7 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
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xcc->parent_realize = dc->realize;
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dc->realize = x86_cpu_realizefn;
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dc->bus_type = TYPE_ICC_BUS;
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+ dc->props = x86_cpu_properties;
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xcc->parent_reset = cc->reset;
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cc->reset = x86_cpu_reset;
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