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From 73b0c0b62c08330e65e9ec3d54ae5738d4b5211d Mon Sep 17 00:00:00 2001
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From: Eduardo Habkost <ehabkost@redhat.com>
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Date: Fri, 9 Sep 2016 19:08:34 +0200
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Subject: [PATCH 2/2] target-i386: Add more Intel AVX-512 instructions support
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RH-Author: Eduardo Habkost <ehabkost@redhat.com>
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Message-id: <1473448114-1430-3-git-send-email-ehabkost@redhat.com>
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Patchwork-id: 72277
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O-Subject: [RHEL-7.3 qemu-kvm PATCH v2 2/2] target-i386: Add more Intel AVX-512 instructions support
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Bugzilla: 1372459
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RH-Acked-by: Bandan Das <bsd@redhat.com>
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RH-Acked-by: Laszlo Ersek <lersek@redhat.com>
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RH-Acked-by: Paolo Bonzini <pbonzini@redhat.com>
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From: Luwei Kang <luwei.kang@intel.com>
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Bugzilla: https://bugzilla.redhat.com/show_bug.cgi?id=1372459
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Add more AVX512 feature bits, include AVX512DQ, AVX512IFMA,
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AVX512BW, AVX512VL, AVX512VBMI. Its spec can be found at:
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https://software.intel.com/sites/default/files/managed/b4/3a/319433-024.pdf
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Signed-off-by: Luwei Kang <luwei.kang@intel.com>
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Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
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(cherry picked from commit cc728d1493eee3e20c1547191862e43d3f55e714)
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Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
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Signed-off-by: Miroslav Rezanina <mrezanin@redhat.com>
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---
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target-i386/cpu.c | 14 +++++++++-----
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target-i386/cpu.h | 13 +++++++++++++
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2 files changed, 22 insertions(+), 5 deletions(-)
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diff --git a/target-i386/cpu.c b/target-i386/cpu.c
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index d9c214c..476306d 100644
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--- a/target-i386/cpu.c
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+++ b/target-i386/cpu.c
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@@ -144,14 +144,18 @@ static const char *svm_feature_name[] = {
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};
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static const char *cpuid_7_0_ebx_feature_name[] = {
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- "fsgsbase", NULL, NULL, "bmi1", "hle", "avx2", NULL, "smep",
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- "bmi2", "erms", "invpcid", "rtm", NULL, NULL, "mpx", NULL,
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- "avx512f", NULL, "rdseed", "adx", "smap", NULL, NULL, NULL,
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- NULL, NULL, "avx512pf", "avx512er", "avx512cd", NULL, NULL, NULL,
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+ "fsgsbase", NULL, NULL, "bmi1",
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+ "hle", "avx2", NULL, "smep",
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+ "bmi2", "erms", "invpcid", "rtm",
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+ NULL, NULL, "mpx", NULL,
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+ "avx512f", "avx512dq", "rdseed", "adx",
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+ "smap", "avx512ifma", NULL, NULL,
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+ NULL, NULL, "avx512pf", "avx512er",
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+ "avx512cd", NULL, "avx512bw", "avx512vl",
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};
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static const char *cpuid_7_0_ecx_feature_name[] = {
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- NULL, NULL, NULL, NULL,
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+ NULL, "avx512vbmi", NULL, NULL,
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NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL,
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NULL, NULL, NULL, NULL,
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diff --git a/target-i386/cpu.h b/target-i386/cpu.h
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index 5c62ee3..d541809 100644
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--- a/target-i386/cpu.h
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+++ b/target-i386/cpu.h
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@@ -560,12 +560,25 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
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#define CPUID_7_0_EBX_RTM (1U << 11)
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#define CPUID_7_0_EBX_MPX (1U << 14)
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#define CPUID_7_0_EBX_AVX512F (1U << 16) /* AVX-512 Foundation */
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+#define CPUID_7_0_EBX_AVX512DQ (1U << 17) /* AVX-512 Doubleword & Quadword Instrs */
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#define CPUID_7_0_EBX_RDSEED (1U << 18)
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#define CPUID_7_0_EBX_ADX (1U << 19)
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#define CPUID_7_0_EBX_SMAP (1U << 20)
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+#define CPUID_7_0_EBX_AVX512IFMA (1U << 21) /* AVX-512 Integer Fused Multiply Add */
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+#define CPUID_7_0_EBX_PCOMMIT (1U << 22) /* Persistent Commit */
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+#define CPUID_7_0_EBX_CLFLUSHOPT (1U << 23) /* Flush a Cache Line Optimized */
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+#define CPUID_7_0_EBX_CLWB (1U << 24) /* Cache Line Write Back */
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#define CPUID_7_0_EBX_AVX512PF (1U << 26) /* AVX-512 Prefetch */
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#define CPUID_7_0_EBX_AVX512ER (1U << 27) /* AVX-512 Exponential and Reciprocal */
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#define CPUID_7_0_EBX_AVX512CD (1U << 28) /* AVX-512 Conflict Detection */
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+#define CPUID_7_0_EBX_AVX512BW (1U << 30) /* AVX-512 Byte and Word Instructions */
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+#define CPUID_7_0_EBX_AVX512VL (1U << 31) /* AVX-512 Vector Length Extensions */
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+
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+#define CPUID_7_0_ECX_VBMI (1U << 1) /* AVX-512 Vector Byte Manipulation Instrs */
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+#define CPUID_7_0_ECX_UMIP (1U << 2)
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+#define CPUID_7_0_ECX_PKU (1U << 3)
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+#define CPUID_7_0_ECX_OSPKE (1U << 4)
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+#define CPUID_7_0_ECX_RDPID (1U << 22)
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#define CPUID_XSAVE_XSAVEOPT (1U << 0)
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#define CPUID_XSAVE_XSAVEC (1U << 1)
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--
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1.8.3.1
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