|
|
619821 |
From d6acc0368578932ee6a2949054a6f640a5b6fa09 Mon Sep 17 00:00:00 2001
|
|
|
b28c64 |
From: Fam Zheng <famz@redhat.com>
|
|
|
619821 |
Date: Thu, 18 May 2017 09:21:26 +0200
|
|
|
b28c64 |
Subject: [PATCH 13/18] serial: update LSR on enabling/disabling FIFOs
|
|
|
b28c64 |
|
|
|
b28c64 |
RH-Author: Fam Zheng <famz@redhat.com>
|
|
|
619821 |
Message-id: <20170518092131.16571-14-famz@redhat.com>
|
|
|
619821 |
Patchwork-id: 75306
|
|
|
619821 |
O-Subject: [RHEL-7.4 qemu-kvm PATCH v3 13/18] serial: update LSR on enabling/disabling FIFOs
|
|
|
619821 |
Bugzilla: 1451470
|
|
|
b28c64 |
RH-Acked-by: Paolo Bonzini <pbonzini@redhat.com>
|
|
|
619821 |
RH-Acked-by: Stefan Hajnoczi <stefanha@redhat.com>
|
|
|
b28c64 |
RH-Acked-by: Eduardo Habkost <ehabkost@redhat.com>
|
|
|
b28c64 |
|
|
|
b28c64 |
From: Paolo Bonzini <pbonzini@redhat.com>
|
|
|
b28c64 |
|
|
|
b28c64 |
When the transmit FIFO is emptied or enabled, the transmitter
|
|
|
b28c64 |
hold register is empty. When it is disabled, it is also emptied and
|
|
|
b28c64 |
in addition the previous contents of the transmitter hold register
|
|
|
b28c64 |
are discarded. In either case, the THRE bit in LSR must be set and
|
|
|
b28c64 |
THRI raised.
|
|
|
b28c64 |
|
|
|
b28c64 |
When the receive FIFO is emptied or enabled, the data ready and break
|
|
|
b28c64 |
bits must be cleared in LSR. Likewise when the receive FIFO is disabled.
|
|
|
b28c64 |
|
|
|
b28c64 |
Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
|
|
|
b28c64 |
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
|
|
|
b28c64 |
(cherry picked from commit 023c3a9707d0d9259a1e858cdf7804dd10973fca)
|
|
|
b28c64 |
Signed-off-by: Fam Zheng <famz@redhat.com>
|
|
|
b28c64 |
Signed-off-by: Miroslav Rezanina <mrezanin@redhat.com>
|
|
|
b28c64 |
|
|
|
b28c64 |
Conflicts:
|
|
|
b28c64 |
hw/char/serial.c
|
|
|
b28c64 |
|
|
|
b28c64 |
Contextual conflict because upstream uses new timer API timer_del while
|
|
|
b28c64 |
downstream still uses qemu_del_timer.
|
|
|
b28c64 |
|
|
|
b28c64 |
hw/char/serial.c | 3 +++
|
|
|
b28c64 |
1 file changed, 3 insertions(+)
|
|
|
b28c64 |
|
|
|
b28c64 |
diff --git a/hw/char/serial.c b/hw/char/serial.c
|
|
|
b28c64 |
index c2be4bd..e0d29a8 100644
|
|
|
b28c64 |
|
|
|
b28c64 |
+++ b/hw/char/serial.c
|
|
|
b28c64 |
@@ -351,12 +351,15 @@ static void serial_ioport_write(void *opaque, hwaddr addr, uint64_t val,
|
|
|
b28c64 |
|
|
|
b28c64 |
|
|
|
b28c64 |
if (val & UART_FCR_RFR) {
|
|
|
b28c64 |
+ s->lsr &= ~(UART_LSR_DR | UART_LSR_BI);
|
|
|
b28c64 |
qemu_del_timer(s->fifo_timeout_timer);
|
|
|
b28c64 |
s->timeout_ipending=0;
|
|
|
b28c64 |
fifo8_reset(&s->recv_fifo);
|
|
|
b28c64 |
}
|
|
|
b28c64 |
|
|
|
b28c64 |
if (val & UART_FCR_XFR) {
|
|
|
b28c64 |
+ s->lsr |= UART_LSR_THRE;
|
|
|
b28c64 |
+ s->thr_ipending = 1;
|
|
|
b28c64 |
fifo8_reset(&s->xmit_fifo);
|
|
|
b28c64 |
}
|
|
|
b28c64 |
|
|
|
b28c64 |
--
|
|
|
b28c64 |
1.8.3.1
|
|
|
b28c64 |
|