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From 3d461e82d134f7370f28ff2def581d39a3e19729 Mon Sep 17 00:00:00 2001
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Message-Id: <3d461e82d134f7370f28ff2def581d39a3e19729.1387298827.git.minovotn@redhat.com>
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In-Reply-To: <3ed0fb61a3dc912ef036d7ef450bed192090709e.1387298827.git.minovotn@redhat.com>
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References: <3ed0fb61a3dc912ef036d7ef450bed192090709e.1387298827.git.minovotn@redhat.com>
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From: "Michael S. Tsirkin" <mst@redhat.com>
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Date: Tue, 17 Dec 2013 15:18:09 +0100
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Subject: [PATCH 31/56] q35: expose mmcfg size as a property
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RH-Author: Michael S. Tsirkin <mst@redhat.com>
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Message-id: <1387293161-4085-32-git-send-email-mst@redhat.com>
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Patchwork-id: 56337
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O-Subject: [PATCH qemu-kvm RHEL7.0 v2 31/57] q35: expose mmcfg size as a property
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Bugzilla: 1034876
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RH-Acked-by: Igor Mammedov <imammedo@redhat.com>
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RH-Acked-by: Marcel Apfelbaum <marcel.a@redhat.com>
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RH-Acked-by: Laszlo Ersek <lersek@redhat.com>
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Address is already exposed, expose size for symmetry.
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Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
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Tested-by: Gerd Hoffmann <kraxel@redhat.com>
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Reviewed-by: Igor Mammedov <imammedo@redhat.com>
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Tested-by: Igor Mammedov <imammedo@redhat.com>
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Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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(cherry picked from commit cbcaf79e3ce1b14084f3e3f4f64365e9bfd70e6a)
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---
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include/hw/pci/pcie_host.h | 1 +
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hw/pci-host/q35.c | 14 ++++++++++++++
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2 files changed, 15 insertions(+)
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Signed-off-by: Michal Novotny <minovotn@redhat.com>
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---
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hw/pci-host/q35.c | 14 ++++++++++++++
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include/hw/pci/pcie_host.h | 1 +
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2 files changed, 15 insertions(+)
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diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c
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index 72d97c8..87691d1 100644
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--- a/hw/pci-host/q35.c
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+++ b/hw/pci-host/q35.c
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@@ -108,6 +108,16 @@ static void q35_host_get_pci_hole64_end(Object *obj, Visitor *v,
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visit_type_uint64(v, &w64.end, name, errp);
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}
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+static void q35_host_get_mmcfg_size(Object *obj, Visitor *v,
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+ void *opaque, const char *name,
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+ Error **errp)
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+{
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+ PCIExpressHost *e = PCIE_HOST_BRIDGE(obj);
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+ uint32_t value = e->size;
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+
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+ visit_type_uint32(v, &value, name, errp);
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+}
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+
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static Property mch_props[] = {
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DEFINE_PROP_UINT64(PCIE_HOST_MCFG_BASE, Q35PCIHost, host.base_addr,
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MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT),
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@@ -152,6 +162,10 @@ static void q35_host_initfn(Object *obj)
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q35_host_get_pci_hole64_end,
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NULL, NULL, NULL, NULL);
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+ object_property_add(obj, PCIE_HOST_MCFG_SIZE, "int",
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+ q35_host_get_mmcfg_size,
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+ NULL, NULL, NULL, NULL);
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+
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/* Leave enough space for the biggest MCFG BAR */
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/* TODO: this matches current bios behaviour, but
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* it's not a power of two, which means an MTRR
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diff --git a/include/hw/pci/pcie_host.h b/include/hw/pci/pcie_host.h
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index 33d75bd..acca45e 100644
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--- a/include/hw/pci/pcie_host.h
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+++ b/include/hw/pci/pcie_host.h
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@@ -29,6 +29,7 @@
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OBJECT_CHECK(PCIExpressHost, (obj), TYPE_PCIE_HOST_BRIDGE)
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#define PCIE_HOST_MCFG_BASE "MCFG"
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+#define PCIE_HOST_MCFG_SIZE "mcfg_size"
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/* pcie_host::base_addr == PCIE_BASE_ADDR_UNMAPPED when it isn't mapped. */
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#define PCIE_BASE_ADDR_UNMAPPED ((hwaddr)-1ULL)
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--
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1.7.11.7
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