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From e27159f910abe099eba5d6959ace2f2de42e5f46 Mon Sep 17 00:00:00 2001
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Message-Id: <e27159f910abe099eba5d6959ace2f2de42e5f46.1387298827.git.minovotn@redhat.com>
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In-Reply-To: <3ed0fb61a3dc912ef036d7ef450bed192090709e.1387298827.git.minovotn@redhat.com>
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References: <3ed0fb61a3dc912ef036d7ef450bed192090709e.1387298827.git.minovotn@redhat.com>
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From: "Michael S. Tsirkin" <mst@redhat.com>
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Date: Tue, 17 Dec 2013 15:17:34 +0100
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Subject: [PATCH 18/56] pc: limit 64 bit hole to 2G by default
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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RH-Author: Michael S. Tsirkin <mst@redhat.com>
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Message-id: <1387293161-4085-19-git-send-email-mst@redhat.com>
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Patchwork-id: 56324
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O-Subject: [PATCH qemu-kvm RHEL7.0 v2 18/57] pc: limit 64 bit hole to 2G by default
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Bugzilla: 1034876
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RH-Acked-by: Igor Mammedov <imammedo@redhat.com>
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RH-Acked-by: Marcel Apfelbaum <marcel.a@redhat.com>
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RH-Acked-by: Laszlo Ersek <lersek@redhat.com>
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From: Igor Mammedov <imammedo@redhat.com>
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It turns out that some 32 bit windows guests crash
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if 64 bit PCI hole size is >2G.
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Limit it to 2G for piix and q35 by default.
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User may override default 64-bit PCI hole size by
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using "pci-hole64-size" property.
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Examples:
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-global i440FX-pcihost.pci-hole64-size=4G
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-global q35-pcihost.pci-hole64-size=4G
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Reported-by: Igor Mammedov <imammedo@redhat.com>,
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Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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Signed-off-by: Igor Mammedov <imammedo@redhat.com>
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Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
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Reviewed-by: Andreas Fรคrber <afaerber@suse.de>
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Message-id: 1375109277-25561-8-git-send-email-imammedo@redhat.com
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Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
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(cherry picked from commit 398489018183d613306ab022653552247d93919f)
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Conflicts:
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hw/i386/pc.c
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hw/pci-host/piix.c
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hw/pci-host/q35.c
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include/hw/i386/pc.h | 14 +++++
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include/hw/pci-host/q35.h | 2 +
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hw/i386/pc.c | 56 ++++++++++++++++
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hw/i386/pc_piix.c | 14 +
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hw/pci-host/piix.c | 99 ++++++++++++++++++++++++++++++++++++++++++++
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hw/pci-host/q35.c | 88 ++++++++++++++++++++++++++++++++++
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6 files changed, 215 insertions(+), 58 deletions(-)
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Signed-off-by: Michal Novotny <minovotn@redhat.com>
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hw/i386/pc.c | 56 ++++++++++++++++
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hw/i386/pc_piix.c | 14 +
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hw/pci-host/piix.c | 99 ++++++++++++++++++++++++++++++++++++++++++++
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hw/pci-host/q35.c | 88 ++++++++++++++++++++++++++++++++++
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include/hw/i386/pc.h | 14 +++++
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include/hw/pci-host/q35.h | 2 +
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6 files changed, 215 insertions(+), 58 deletions(-)
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diff
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index 9d9f5d2..e5ebd52 100644
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@@ -55,6 +55,7 @@
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#include "hw/acpi/acpi.h"
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#include "hw/cpu/icc_bus.h"
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#include "hw/boards.h"
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+#include "hw/pci/pci_host.h"
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//
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@@ -996,15 +997,27 @@ typedef struct PcRomPciInfo {
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static void pc_fw_cfg_guest_info(PcGuestInfo *guest_info)
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{
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PcRomPciInfo *info;
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+ Object *pci_info;
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+ bool ambiguous = false;
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+
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if (!guest_info->has_pci_info || !guest_info->fw_cfg) {
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return;
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}
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+ pci_info = object_resolve_path_type("", TYPE_PCI_HOST_BRIDGE, &ambiguous);
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+ g_assert(!ambiguous);
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+ if (!pci_info) {
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+ return;
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+ }
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info = g_malloc(sizeof *info);
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- info->w32_min = cpu_to_le64(guest_info->pci_info.w32.begin);
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- info->w32_max = cpu_to_le64(guest_info->pci_info.w32.end);
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- info->w64_min = cpu_to_le64(guest_info->pci_info.w64.begin);
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- info->w64_max = cpu_to_le64(guest_info->pci_info.w64.end);
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+ info->w32_min = cpu_to_le64(object_property_get_int(pci_info,
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+ PCI_HOST_PROP_PCI_HOLE_START, NULL));
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+ info->w32_max = cpu_to_le64(object_property_get_int(pci_info,
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+ PCI_HOST_PROP_PCI_HOLE_END, NULL));
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+ info->w64_min = cpu_to_le64(object_property_get_int(pci_info,
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+ PCI_HOST_PROP_PCI_HOLE64_START, NULL));
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+ info->w64_max = cpu_to_le64(object_property_get_int(pci_info,
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+ PCI_HOST_PROP_PCI_HOLE64_END, NULL));
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* Required so guest PCI enumeration does the right thing. */
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fw_cfg_add_file(guest_info->fw_cfg, "etc/pci-info", info, sizeof *info);
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@@ -1030,29 +1043,28 @@ PcGuestInfo *pc_guest_info_init(ram_addr_t below_4g_mem_size,
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PcGuestInfoState *guest_info_state = g_malloc0(sizeof *guest_info_state);
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PcGuestInfo *guest_info = &guest_info_state->info;
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- guest_info->pci_info.w32.end = IO_APIC_DEFAULT_ADDRESS;
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- if (sizeof(hwaddr) == 4) {
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- guest_info->pci_info.w64.begin = 0;
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- guest_info->pci_info.w64.end = 0;
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- } else {
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- /*
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- * BIOS does not set MTRR entries for the 64 bit window, so no need to
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- * align address to power of two. Align address at 1G, this makes sure
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- * it can be exactly covered with a PAT entry even when using huge
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- * pages.
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- */
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- guest_info->pci_info.w64.begin =
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- ROUND_UP((0x1ULL << 32) + above_4g_mem_size, 0x1ULL << 30);
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- guest_info->pci_info.w64.end = guest_info->pci_info.w64.begin +
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- (0x1ULL << 62);
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- assert(guest_info->pci_info.w64.begin <= guest_info->pci_info.w64.end);
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- }
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-
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guest_info_state->machine_done.notify = pc_guest_info_machine_done;
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qemu_add_machine_init_done_notifier(&guest_info_state->machine_done);
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return guest_info;
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}
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+void pc_init_pci64_hole(PcPciInfo *pci_info, uint64_t pci_hole64_start,
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+ uint64_t pci_hole64_size)
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+{
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+ if ((sizeof(hwaddr) == 4) || (!pci_hole64_size)) {
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+ return;
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+ }
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+ /*
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+ * BIOS does not set MTRR entries for the 64 bit window, so no need to
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+ * align address to power of two. Align address at 1G, this makes sure
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+ * it can be exactly covered with a PAT entry even when using huge
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+ * pages.
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+ */
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+ pci_info->w64.begin = ROUND_UP(pci_hole64_start, 0x1ULL << 30);
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+ pci_info->w64.end = pci_info->w64.begin + pci_hole64_size;
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+ assert(pci_info->w64.begin <= pci_info->w64.end);
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+}
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+
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void pc_acpi_init(const char *default_dsdt)
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{
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char *filename;
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diff
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index 6d50a4e..211ff8e 100644
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@@ -125,15 +125,6 @@ static void pc_init1(QEMUMachineInitArgs *args,
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guest_info = pc_guest_info_init(below_4g_mem_size, above_4g_mem_size);
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guest_info->has_pci_info = has_pci_info;
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-
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-
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- if (ram_size <= 0x80000000)
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- guest_info->pci_info.w32.begin = 0x80000000;
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- else if (ram_size <= 0xc0000000)
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- guest_info->pci_info.w32.begin = 0xc0000000;
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- else
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- guest_info->pci_info.w32.begin = 0xe0000000;
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-
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/* allocate ram and load rom/bios */
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if (!xen_enabled()) {
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fw_cfg = pc_memory_init(system_memory,
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@@ -157,10 +148,7 @@ static void pc_init1(QEMUMachineInitArgs *args,
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system_memory, system_io, args->ram_size,
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below_4g_mem_size,
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0x100000000ULL - below_4g_mem_size,
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- 0x100000000ULL + above_4g_mem_size,
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- (sizeof(hwaddr) == 4
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- ? 0
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- : ((uint64_t)1 << 62)),
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+ above_4g_mem_size,
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pci_memory, ram_memory);
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} else {
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pci_bus = NULL;
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diff
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index adc094a..167d1fd 100644
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@@ -32,6 +32,8 @@
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#include "hw/xen/xen.h"
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#include "hw/pci-host/pam.h"
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#include "sysemu/sysemu.h"
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+#include "hw/i386/ioapic.h"
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+#include "qapi/visitor.h"
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/*
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* I440FX chipset data sheet.
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@@ -44,6 +46,8 @@
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typedef struct I440FXState {
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PCIHostState parent_obj;
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+ PcPciInfo pci_info;
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+ uint64_t pci_hole64_size;
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} I440FXState;
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#define PIIX_NUM_PIC_IRQS 16
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@@ -201,9 +205,49 @@ static const VMStateDescription vmstate_i440fx = {
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}
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};
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+static void i440fx_pcihost_get_pci_hole_start(Object *obj, Visitor *v,
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+ void *opaque, const char *name,
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+ Error **errp)
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+{
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+ I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);
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+ uint32_t value = s->pci_info.w32.begin;
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+
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+ visit_type_uint32(v, &value, name, errp);
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+}
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+
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+static void i440fx_pcihost_get_pci_hole_end(Object *obj, Visitor *v,
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+ void *opaque, const char *name,
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+ Error **errp)
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+{
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+ I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);
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+ uint32_t value = s->pci_info.w32.end;
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+
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+ visit_type_uint32(v, &value, name, errp);
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+}
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+
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+static void i440fx_pcihost_get_pci_hole64_start(Object *obj, Visitor *v,
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+ void *opaque, const char *name,
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+ Error **errp)
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+{
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+ I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);
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+
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+ visit_type_uint64(v, &s->pci_info.w64.begin, name, errp);
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+}
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+
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+static void i440fx_pcihost_get_pci_hole64_end(Object *obj, Visitor *v,
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+ void *opaque, const char *name,
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+ Error **errp)
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+{
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+ I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);
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+
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+ visit_type_uint64(v, &s->pci_info.w64.end, name, errp);
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+}
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+
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static int i440fx_pcihost_initfn(SysBusDevice *dev)
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{
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PCIHostState *s = PCI_HOST_BRIDGE(dev);
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+ I440FXState *d = I440FX_PCI_HOST_BRIDGE(s);
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+ Object *obj = OBJECT(s);
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memory_region_init_io(&s->conf_mem, &pci_host_conf_le_ops, s,
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"pci-conf-idx", 4);
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@@ -212,6 +256,27 @@ static int i440fx_pcihost_initfn(SysBusDevice *dev)
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memory_region_init_io(&s->data_mem, &pci_host_data_le_ops, s,
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"pci-conf-data", 4);
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+
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+ object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_START, "int",
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0a122b |
+ i440fx_pcihost_get_pci_hole_start,
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0a122b |
+ NULL, NULL, NULL, NULL);
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0a122b |
+
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+ object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_END, "int",
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+ i440fx_pcihost_get_pci_hole_end,
|
|
|
0a122b |
+ NULL, NULL, NULL, NULL);
|
|
|
0a122b |
+
|
|
|
0a122b |
+ object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_START, "int",
|
|
|
0a122b |
+ i440fx_pcihost_get_pci_hole64_start,
|
|
|
0a122b |
+ NULL, NULL, NULL, NULL);
|
|
|
0a122b |
+
|
|
|
0a122b |
+ object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_END, "int",
|
|
|
0a122b |
+ i440fx_pcihost_get_pci_hole64_end,
|
|
|
0a122b |
+ NULL, NULL, NULL, NULL);
|
|
|
0a122b |
+
|
|
|
0a122b |
+ d->pci_info.w32.end = IO_APIC_DEFAULT_ADDRESS;
|
|
|
0a122b |
+
|
|
|
0a122b |
+ memory_region_init_io(&s->data_mem, &pci_host_data_le_ops, s,
|
|
|
0a122b |
+ "pci-conf-data", 4);
|
|
|
0a122b |
sysbus_add_io(dev, 0xcfc, &s->data_mem);
|
|
|
0a122b |
sysbus_init_ioports(&s->busdev, 0xcfc, 4);
|
|
|
0a122b |
|
|
|
0a122b |
@@ -236,8 +301,7 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state,
|
|
|
0a122b |
ram_addr_t ram_size,
|
|
|
0a122b |
hwaddr pci_hole_start,
|
|
|
0a122b |
hwaddr pci_hole_size,
|
|
|
0a122b |
- hwaddr pci_hole64_start,
|
|
|
0a122b |
- hwaddr pci_hole64_size,
|
|
|
0a122b |
+ ram_addr_t above_4g_mem_size,
|
|
|
0a122b |
MemoryRegion *pci_address_space,
|
|
|
0a122b |
MemoryRegion *ram_memory)
|
|
|
0a122b |
{
|
|
|
0a122b |
@@ -248,6 +312,7 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state,
|
|
|
0a122b |
PIIX3State *piix3;
|
|
|
0a122b |
PCII440FXState *f;
|
|
|
0a122b |
unsigned i;
|
|
|
0a122b |
+ I440FXState *i440fx;
|
|
|
0a122b |
|
|
|
0a122b |
dev = qdev_create(NULL, TYPE_I440FX_PCI_HOST_BRIDGE);
|
|
|
0a122b |
s = PCI_HOST_BRIDGE(dev);
|
|
|
0a122b |
@@ -263,14 +328,31 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state,
|
|
|
0a122b |
f->system_memory = address_space_mem;
|
|
|
0a122b |
f->pci_address_space = pci_address_space;
|
|
|
0a122b |
f->ram_memory = ram_memory;
|
|
|
0a122b |
+
|
|
|
0a122b |
+ i440fx = I440FX_PCI_HOST_BRIDGE(dev);
|
|
|
0a122b |
+
|
|
|
0a122b |
+
|
|
|
0a122b |
+ if (ram_size <= 0x80000000) {
|
|
|
0a122b |
+ i440fx->pci_info.w32.begin = 0x80000000;
|
|
|
0a122b |
+ } else if (ram_size <= 0xc0000000) {
|
|
|
0a122b |
+ i440fx->pci_info.w32.begin = 0xc0000000;
|
|
|
0a122b |
+ } else {
|
|
|
0a122b |
+ i440fx->pci_info.w32.begin = 0xe0000000;
|
|
|
0a122b |
+ }
|
|
|
0a122b |
+
|
|
|
0a122b |
memory_region_init_alias(&f->pci_hole, "pci-hole", f->pci_address_space,
|
|
|
0a122b |
pci_hole_start, pci_hole_size);
|
|
|
0a122b |
memory_region_add_subregion(f->system_memory, pci_hole_start, &f->pci_hole);
|
|
|
0a122b |
+
|
|
|
0a122b |
+ pc_init_pci64_hole(&i440fx->pci_info, 0x100000000ULL + above_4g_mem_size,
|
|
|
0a122b |
+ i440fx->pci_hole64_size);
|
|
|
0a122b |
memory_region_init_alias(&f->pci_hole_64bit, "pci-hole64",
|
|
|
0a122b |
f->pci_address_space,
|
|
|
0a122b |
- pci_hole64_start, pci_hole64_size);
|
|
|
0a122b |
- if (pci_hole64_size) {
|
|
|
0a122b |
- memory_region_add_subregion(f->system_memory, pci_hole64_start,
|
|
|
0a122b |
+ i440fx->pci_info.w64.begin,
|
|
|
0a122b |
+ i440fx->pci_hole64_size);
|
|
|
0a122b |
+ if (i440fx->pci_hole64_size) {
|
|
|
0a122b |
+ memory_region_add_subregion(f->system_memory,
|
|
|
0a122b |
+ i440fx->pci_info.w64.begin,
|
|
|
0a122b |
&f->pci_hole_64bit);
|
|
|
0a122b |
}
|
|
|
0a122b |
memory_region_init_alias(&f->smram_region, "smram-region",
|
|
|
0a122b |
@@ -621,6 +703,12 @@ static const TypeInfo i440fx_info = {
|
|
|
0a122b |
.class_init = i440fx_class_init,
|
|
|
0a122b |
};
|
|
|
0a122b |
|
|
|
0a122b |
+static Property i440fx_props[] = {
|
|
|
0a122b |
+ DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, I440FXState,
|
|
|
0a122b |
+ pci_hole64_size, DEFAULT_PCI_HOLE64_SIZE),
|
|
|
0a122b |
+ DEFINE_PROP_END_OF_LIST(),
|
|
|
0a122b |
+};
|
|
|
0a122b |
+
|
|
|
0a122b |
static void i440fx_pcihost_class_init(ObjectClass *klass, void *data)
|
|
|
0a122b |
{
|
|
|
0a122b |
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
0a122b |
@@ -628,6 +716,7 @@ static void i440fx_pcihost_class_init(ObjectClass *klass, void *data)
|
|
|
0a122b |
|
|
|
0a122b |
k->init = i440fx_pcihost_initfn;
|
|
|
0a122b |
dc->fw_name = "pci";
|
|
|
0a122b |
+ dc->props = i440fx_props;
|
|
|
0a122b |
}
|
|
|
0a122b |
|
|
|
0a122b |
static const TypeInfo i440fx_pcihost_info = {
|
|
|
0a122b |
diff
|
|
|
0a122b |
index 0989fc5..be12eee 100644
|
|
|
0a122b |
|
|
|
0a122b |
|
|
|
0a122b |
@@ -29,6 +29,7 @@
|
|
|
0a122b |
*/
|
|
|
0a122b |
#include "hw/hw.h"
|
|
|
0a122b |
#include "hw/pci-host/q35.h"
|
|
|
0a122b |
+#include "qapi/visitor.h"
|
|
|
0a122b |
|
|
|
0a122b |
/****************************************************************************
|
|
|
0a122b |
* Q35 host
|
|
|
0a122b |
@@ -63,9 +64,49 @@ static int q35_host_init(SysBusDevice *dev)
|
|
|
0a122b |
return 0;
|
|
|
0a122b |
}
|
|
|
0a122b |
|
|
|
0a122b |
+static void q35_host_get_pci_hole_start(Object *obj, Visitor *v,
|
|
|
0a122b |
+ void *opaque, const char *name,
|
|
|
0a122b |
+ Error **errp)
|
|
|
0a122b |
+{
|
|
|
0a122b |
+ Q35PCIHost *s = Q35_HOST_DEVICE(obj);
|
|
|
0a122b |
+ uint32_t value = s->mch.pci_info.w32.begin;
|
|
|
0a122b |
+
|
|
|
0a122b |
+ visit_type_uint32(v, &value, name, errp);
|
|
|
0a122b |
+}
|
|
|
0a122b |
+
|
|
|
0a122b |
+static void q35_host_get_pci_hole_end(Object *obj, Visitor *v,
|
|
|
0a122b |
+ void *opaque, const char *name,
|
|
|
0a122b |
+ Error **errp)
|
|
|
0a122b |
+{
|
|
|
0a122b |
+ Q35PCIHost *s = Q35_HOST_DEVICE(obj);
|
|
|
0a122b |
+ uint32_t value = s->mch.pci_info.w32.end;
|
|
|
0a122b |
+
|
|
|
0a122b |
+ visit_type_uint32(v, &value, name, errp);
|
|
|
0a122b |
+}
|
|
|
0a122b |
+
|
|
|
0a122b |
+static void q35_host_get_pci_hole64_start(Object *obj, Visitor *v,
|
|
|
0a122b |
+ void *opaque, const char *name,
|
|
|
0a122b |
+ Error **errp)
|
|
|
0a122b |
+{
|
|
|
0a122b |
+ Q35PCIHost *s = Q35_HOST_DEVICE(obj);
|
|
|
0a122b |
+
|
|
|
0a122b |
+ visit_type_uint64(v, &s->mch.pci_info.w64.begin, name, errp);
|
|
|
0a122b |
+}
|
|
|
0a122b |
+
|
|
|
0a122b |
+static void q35_host_get_pci_hole64_end(Object *obj, Visitor *v,
|
|
|
0a122b |
+ void *opaque, const char *name,
|
|
|
0a122b |
+ Error **errp)
|
|
|
0a122b |
+{
|
|
|
0a122b |
+ Q35PCIHost *s = Q35_HOST_DEVICE(obj);
|
|
|
0a122b |
+
|
|
|
0a122b |
+ visit_type_uint64(v, &s->mch.pci_info.w64.end, name, errp);
|
|
|
0a122b |
+}
|
|
|
0a122b |
+
|
|
|
0a122b |
static Property mch_props[] = {
|
|
|
0a122b |
DEFINE_PROP_UINT64("MCFG", Q35PCIHost, host.base_addr,
|
|
|
0a122b |
MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT),
|
|
|
0a122b |
+ DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, Q35PCIHost,
|
|
|
0a122b |
+ mch.pci_hole64_size, DEFAULT_PCI_HOLE64_SIZE),
|
|
|
0a122b |
DEFINE_PROP_END_OF_LIST(),
|
|
|
0a122b |
};
|
|
|
0a122b |
|
|
|
0a122b |
@@ -88,6 +129,31 @@ static void q35_host_initfn(Object *obj)
|
|
|
0a122b |
object_property_add_child(OBJECT(s), "mch", OBJECT(&s->mch), NULL);
|
|
|
0a122b |
qdev_prop_set_uint32(DEVICE(&s->mch), "addr", PCI_DEVFN(0, 0));
|
|
|
0a122b |
qdev_prop_set_bit(DEVICE(&s->mch), "multifunction", false);
|
|
|
0a122b |
+
|
|
|
0a122b |
+ object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_START, "int",
|
|
|
0a122b |
+ q35_host_get_pci_hole_start,
|
|
|
0a122b |
+ NULL, NULL, NULL, NULL);
|
|
|
0a122b |
+
|
|
|
0a122b |
+ object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_END, "int",
|
|
|
0a122b |
+ q35_host_get_pci_hole_end,
|
|
|
0a122b |
+ NULL, NULL, NULL, NULL);
|
|
|
0a122b |
+
|
|
|
0a122b |
+ object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_START, "int",
|
|
|
0a122b |
+ q35_host_get_pci_hole64_start,
|
|
|
0a122b |
+ NULL, NULL, NULL, NULL);
|
|
|
0a122b |
+
|
|
|
0a122b |
+ object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_END, "int",
|
|
|
0a122b |
+ q35_host_get_pci_hole64_end,
|
|
|
0a122b |
+ NULL, NULL, NULL, NULL);
|
|
|
0a122b |
+
|
|
|
0a122b |
+
|
|
|
0a122b |
+
|
|
|
0a122b |
+ * it's not a power of two, which means an MTRR
|
|
|
0a122b |
+ * can't cover it exactly.
|
|
|
0a122b |
+ */
|
|
|
0a122b |
+ s->mch.pci_info.w32.begin = MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT +
|
|
|
0a122b |
+ MCH_HOST_BRIDGE_PCIEXBAR_MAX;
|
|
|
0a122b |
+ s->mch.pci_info.w32.end = IO_APIC_DEFAULT_ADDRESS;
|
|
|
0a122b |
}
|
|
|
0a122b |
|
|
|
0a122b |
static const TypeInfo q35_host_info = {
|
|
|
0a122b |
@@ -242,17 +308,8 @@ static void mch_reset(DeviceState *qdev)
|
|
|
0a122b |
static int mch_init(PCIDevice *d)
|
|
|
0a122b |
{
|
|
|
0a122b |
int i;
|
|
|
0a122b |
- hwaddr pci_hole64_size;
|
|
|
0a122b |
MCHPCIState *mch = MCH_PCI_DEVICE(d);
|
|
|
0a122b |
|
|
|
0a122b |
-
|
|
|
0a122b |
-
|
|
|
0a122b |
- * it's not a power of two, which means an MTRR
|
|
|
0a122b |
- * can't cover it exactly.
|
|
|
0a122b |
- */
|
|
|
0a122b |
- mch->guest_info->pci_info.w32.begin = MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT +
|
|
|
0a122b |
- MCH_HOST_BRIDGE_PCIEXBAR_MAX;
|
|
|
0a122b |
-
|
|
|
0a122b |
|
|
|
0a122b |
memory_region_init_alias(&mch->pci_hole, "pci-hole",
|
|
|
0a122b |
mch->pci_address_space,
|
|
|
0a122b |
@@ -260,15 +317,16 @@ static int mch_init(PCIDevice *d)
|
|
|
0a122b |
0x100000000ULL - mch->below_4g_mem_size);
|
|
|
0a122b |
memory_region_add_subregion(mch->system_memory, mch->below_4g_mem_size,
|
|
|
0a122b |
&mch->pci_hole);
|
|
|
0a122b |
- pci_hole64_size = (sizeof(hwaddr) == 4 ? 0 :
|
|
|
0a122b |
- ((uint64_t)1 << 62));
|
|
|
0a122b |
+
|
|
|
0a122b |
+ pc_init_pci64_hole(&mch->pci_info, 0x100000000ULL + mch->above_4g_mem_size,
|
|
|
0a122b |
+ mch->pci_hole64_size);
|
|
|
0a122b |
memory_region_init_alias(&mch->pci_hole_64bit, "pci-hole64",
|
|
|
0a122b |
mch->pci_address_space,
|
|
|
0a122b |
- 0x100000000ULL + mch->above_4g_mem_size,
|
|
|
0a122b |
- pci_hole64_size);
|
|
|
0a122b |
- if (pci_hole64_size) {
|
|
|
0a122b |
+ mch->pci_info.w64.begin,
|
|
|
0a122b |
+ mch->pci_hole64_size);
|
|
|
0a122b |
+ if (mch->pci_hole64_size) {
|
|
|
0a122b |
memory_region_add_subregion(mch->system_memory,
|
|
|
0a122b |
- 0x100000000ULL + mch->above_4g_mem_size,
|
|
|
0a122b |
+ mch->pci_info.w64.begin,
|
|
|
0a122b |
&mch->pci_hole_64bit);
|
|
|
0a122b |
}
|
|
|
0a122b |
|
|
|
0a122b |
diff
|
|
|
0a122b |
index 2992464..fe21bc3 100644
|
|
|
0a122b |
|
|
|
0a122b |
+++ b/include/hw/i386/pc.h
|
|
|
0a122b |
@@ -20,7 +20,6 @@ typedef struct PcPciInfo {
|
|
|
0a122b |
} PcPciInfo;
|
|
|
0a122b |
|
|
|
0a122b |
struct PcGuestInfo {
|
|
|
0a122b |
- PcPciInfo pci_info;
|
|
|
0a122b |
bool has_pci_info;
|
|
|
0a122b |
FWCfgState *fw_cfg;
|
|
|
0a122b |
};
|
|
|
0a122b |
@@ -101,6 +100,16 @@ void pc_acpi_init(const char *default_dsdt);
|
|
|
0a122b |
PcGuestInfo *pc_guest_info_init(ram_addr_t below_4g_mem_size,
|
|
|
0a122b |
ram_addr_t above_4g_mem_size);
|
|
|
0a122b |
|
|
|
0a122b |
+#define PCI_HOST_PROP_PCI_HOLE_START "pci-hole-start"
|
|
|
0a122b |
+#define PCI_HOST_PROP_PCI_HOLE_END "pci-hole-end"
|
|
|
0a122b |
+#define PCI_HOST_PROP_PCI_HOLE64_START "pci-hole64-start"
|
|
|
0a122b |
+#define PCI_HOST_PROP_PCI_HOLE64_END "pci-hole64-end"
|
|
|
0a122b |
+#define PCI_HOST_PROP_PCI_HOLE64_SIZE "pci-hole64-size"
|
|
|
0a122b |
+#define DEFAULT_PCI_HOLE64_SIZE (1ULL << 31)
|
|
|
0a122b |
+
|
|
|
0a122b |
+void pc_init_pci64_hole(PcPciInfo *pci_info, uint64_t pci_hole64_start,
|
|
|
0a122b |
+ uint64_t pci_hole64_size);
|
|
|
0a122b |
+
|
|
|
0a122b |
FWCfgState *pc_memory_init(MemoryRegion *system_memory,
|
|
|
0a122b |
const char *kernel_filename,
|
|
|
0a122b |
const char *kernel_cmdline,
|
|
|
0a122b |
@@ -150,8 +159,7 @@ PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix_devfn,
|
|
|
0a122b |
ram_addr_t ram_size,
|
|
|
0a122b |
hwaddr pci_hole_start,
|
|
|
0a122b |
hwaddr pci_hole_size,
|
|
|
0a122b |
- hwaddr pci_hole64_start,
|
|
|
0a122b |
- hwaddr pci_hole64_size,
|
|
|
0a122b |
+ ram_addr_t above_4g_mem_size,
|
|
|
0a122b |
MemoryRegion *pci_memory,
|
|
|
0a122b |
MemoryRegion *ram_memory);
|
|
|
0a122b |
|
|
|
0a122b |
diff
|
|
|
0a122b |
index b083831..e660a40 100644
|
|
|
0a122b |
|
|
|
0a122b |
+++ b/include/hw/pci-host/q35.h
|
|
|
0a122b |
@@ -52,9 +52,11 @@ typedef struct MCHPCIState {
|
|
|
0a122b |
MemoryRegion smram_region;
|
|
|
0a122b |
MemoryRegion pci_hole;
|
|
|
0a122b |
MemoryRegion pci_hole_64bit;
|
|
|
0a122b |
+ PcPciInfo pci_info;
|
|
|
0a122b |
uint8_t smm_enabled;
|
|
|
0a122b |
ram_addr_t below_4g_mem_size;
|
|
|
0a122b |
ram_addr_t above_4g_mem_size;
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+ uint64_t pci_hole64_size;
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PcGuestInfo *guest_info;
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} MCHPCIState;
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0a122b |
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--
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1.7.11.7
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0a122b |
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