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From cf62577aed781b2515ea97b9f42285c2f608a7bf Mon Sep 17 00:00:00 2001
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From: "plai@redhat.com" <plai@redhat.com>
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Date: Fri, 15 May 2020 18:02:42 +0100
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Subject: [PATCH 16/17] i386: Add new CPU model Cooperlake
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RH-Author: plai@redhat.com
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Message-id: <20200515180243.17488-4-plai@redhat.com>
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Patchwork-id: 96608
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O-Subject: [RHEL8.2.1 AV qemu-kvm PATCH 3/4] i386: Add new CPU model Cooperlake
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Bugzilla: 1769912
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RH-Acked-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
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RH-Acked-by: Igor Mammedov <imammedo@redhat.com>
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RH-Acked-by: Eduardo Habkost <ehabkost@redhat.com>
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From: Cathy Zhang <cathy.zhang@intel.com>
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Cooper Lake is intel's successor to Cascade Lake, the new
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CPU model inherits features from Cascadelake-Server, while
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add one platform associated new feature: AVX512_BF16. Meanwhile,
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add STIBP for speculative execution.
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Signed-off-by: Cathy Zhang <cathy.zhang@intel.com>
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Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com>
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Reviewed-by: Tao Xu <tao3.xu@intel.com>
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Message-Id: <1571729728-23284-4-git-send-email-cathy.zhang@intel.com>
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Reviewed-by: Bruce Rogers <brogers@suse.com>
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Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
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(cherry picked from commit 22a866b6166db5caa4abaa6e656c2a431fa60726)
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Signed-off-by: Paul Lai <plai@redhat.com>
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Signed-off-by: Danilo C. L. de Paula <ddepaula@redhat.com>
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---
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target/i386/cpu.c | 60 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
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1 file changed, 60 insertions(+)
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diff --git a/target/i386/cpu.c b/target/i386/cpu.c
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index 0f0a2db..996a74f 100644
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--- a/target/i386/cpu.c
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+++ b/target/i386/cpu.c
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@@ -3161,6 +3161,66 @@ static X86CPUDefinition builtin_x86_defs[] = {
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}
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},
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{
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+ .name = "Cooperlake",
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+ .level = 0xd,
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+ .vendor = CPUID_VENDOR_INTEL,
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+ .family = 6,
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+ .model = 85,
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+ .stepping = 10,
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+ .features[FEAT_1_EDX] =
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+ CPUID_VME | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
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+ CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
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+ CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
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+ CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
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+ CPUID_DE | CPUID_FP87,
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+ .features[FEAT_1_ECX] =
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+ CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
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+ CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
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+ CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
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+ CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
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+ CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
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+ CPUID_EXT_PCID | CPUID_EXT_F16C | CPUID_EXT_RDRAND,
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+ .features[FEAT_8000_0001_EDX] =
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+ CPUID_EXT2_LM | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP |
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+ CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
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+ .features[FEAT_8000_0001_ECX] =
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+ CPUID_EXT3_ABM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
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+ .features[FEAT_7_0_EBX] =
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+ CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
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+ CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
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+ CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
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+ CPUID_7_0_EBX_RTM | CPUID_7_0_EBX_RDSEED | CPUID_7_0_EBX_ADX |
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+ CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLWB |
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+ CPUID_7_0_EBX_AVX512F | CPUID_7_0_EBX_AVX512DQ |
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+ CPUID_7_0_EBX_AVX512BW | CPUID_7_0_EBX_AVX512CD |
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+ CPUID_7_0_EBX_AVX512VL | CPUID_7_0_EBX_CLFLUSHOPT,
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+ .features[FEAT_7_0_ECX] =
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+ CPUID_7_0_ECX_PKU |
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+ CPUID_7_0_ECX_AVX512VNNI,
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+ .features[FEAT_7_0_EDX] =
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+ CPUID_7_0_EDX_SPEC_CTRL | CPUID_7_0_EDX_STIBP |
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+ CPUID_7_0_EDX_SPEC_CTRL_SSBD | CPUID_7_0_EDX_ARCH_CAPABILITIES,
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+ .features[FEAT_ARCH_CAPABILITIES] =
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+ MSR_ARCH_CAP_RDCL_NO | MSR_ARCH_CAP_IBRS_ALL |
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+ MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY | MSR_ARCH_CAP_MDS_NO,
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+ .features[FEAT_7_1_EAX] =
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+ CPUID_7_1_EAX_AVX512_BF16,
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+ /*
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+ * Missing: XSAVES (not supported by some Linux versions,
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+ * including v4.1 to v4.12).
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+ * KVM doesn't yet expose any XSAVES state save component,
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+ * and the only one defined in Skylake (processor tracing)
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+ * probably will block migration anyway.
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+ */
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+ .features[FEAT_XSAVE] =
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+ CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
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+ CPUID_XSAVE_XGETBV1,
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+ .features[FEAT_6_EAX] =
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+ CPUID_6_EAX_ARAT,
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+ .xlevel = 0x80000008,
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+ .model_id = "Intel Xeon Processor (Cooperlake)",
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+ },
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+ {
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.name = "Icelake-Client",
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.level = 0xd,
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.vendor = CPUID_VENDOR_INTEL,
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--
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1.8.3.1
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