From 3f027ac56449e51a61e76c18b97fd341d302dc80 Mon Sep 17 00:00:00 2001

From: eperezma <eperezma@redhat.com>

Date: Tue, 12 Jan 2021 14:36:32 -0500

Subject: [PATCH 08/17] hw/arm/smmuv3: Get prepared for range invalidation

MIME-Version: 1.0

Content-Type: text/plain; charset=UTF-8

Content-Transfer-Encoding: 8bit

RH-Author: eperezma <eperezma@redhat.com>

Message-id: <20210112143638.374060-8-eperezma@redhat.com>

Patchwork-id: 100600

O-Subject: [RHEL-8.4.0 qemu-kvm PATCH v2 07/13] hw/arm/smmuv3: Get prepared for range invalidation

Bugzilla: 1843852

RH-Acked-by: Xiao Wang <jasowang@redhat.com>

RH-Acked-by: Peter Xu <peterx@redhat.com>

RH-Acked-by: Auger Eric <eric.auger@redhat.com>

From: Eric Auger <eric.auger@redhat.com>

Enhance the smmu_iotlb_inv_iova() helper with range invalidation.

This uses the new fields passed in the NH_VA and NH_VAA commands:

the size of the range, the level and the granule.

As NH_VA and NH_VAA both use those fields, their decoding and

handling is factorized in a new smmuv3_s1_range_inval() helper.

Signed-off-by: Eric Auger <eric.auger@redhat.com>

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Message-id: 20200728150815.11446-8-eric.auger@redhat.com

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

(cherry picked from commit d52915616c059ed273caa2d496b58e5d215c5962)

Signed-off-by: Eugenio Pérez <eperezma@redhat.com>

Signed-off-by: Danilo C. L. de Paula <ddepaula@redhat.com>

---

 hw/arm/smmu-common.c         | 25 +++++++++++---

 hw/arm/smmuv3-internal.h     |  4 +++

 hw/arm/smmuv3.c              | 64 +++++++++++++++++++++++-------------

 hw/arm/trace-events          |  4 +--

 include/hw/arm/smmu-common.h |  3 +-

 5 files changed, 69 insertions(+), 31 deletions(-)

diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c

index 8007edeaaa2..9780404f002 100644

--- a/hw/arm/smmu-common.c

+++ b/hw/arm/smmu-common.c

@@ -143,15 +143,30 @@ static gboolean smmu_hash_remove_by_asid_iova(gpointer key, gpointer value,

     if (info->asid >= 0 && info->asid != SMMU_IOTLB_ASID(iotlb_key)) {

         return false;

     }

-    return (info->iova & ~entry->addr_mask) == entry->iova;

+    return ((info->iova & ~entry->addr_mask) == entry->iova) ||

+           ((entry->iova & ~info->mask) == info->iova);

 }

-inline void smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova)

+inline void

+smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova,

+                    uint8_t tg, uint64_t num_pages, uint8_t ttl)

 {

-    SMMUIOTLBPageInvInfo info = {.asid = asid, .iova = iova};

+    if (ttl && (num_pages == 1)) {

+        SMMUIOTLBKey key = smmu_get_iotlb_key(asid, iova, tg, ttl);

-    trace_smmu_iotlb_inv_iova(asid, iova);

-    g_hash_table_foreach_remove(s->iotlb, smmu_hash_remove_by_asid_iova, &info;;

+        g_hash_table_remove(s->iotlb, &key);

+    } else {

+        /* if tg is not set we use 4KB range invalidation */

+        uint8_t granule = tg ? tg * 2 + 10 : 12;

+

+        SMMUIOTLBPageInvInfo info = {

+            .asid = asid, .iova = iova,

+            .mask = (num_pages * 1 << granule) - 1};

+

+        g_hash_table_foreach_remove(s->iotlb,

+                                    smmu_hash_remove_by_asid_iova,

+                                    &info;;

+    }

 }

 inline void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid)

diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h

index d190181ef1b..a4ec2c591cd 100644

--- a/hw/arm/smmuv3-internal.h

+++ b/hw/arm/smmuv3-internal.h

@@ -298,6 +298,8 @@ enum { /* Command completion notification */

 };

 #define CMD_TYPE(x)         extract32((x)->word[0], 0 , 8)

+#define CMD_NUM(x)          extract32((x)->word[0], 12 , 5)

+#define CMD_SCALE(x)        extract32((x)->word[0], 20 , 5)

 #define CMD_SSEC(x)         extract32((x)->word[0], 10, 1)

 #define CMD_SSV(x)          extract32((x)->word[0], 11, 1)

 #define CMD_RESUME_AC(x)    extract32((x)->word[0], 12, 1)

@@ -310,6 +312,8 @@ enum { /* Command completion notification */

 #define CMD_RESUME_STAG(x)  extract32((x)->word[2], 0 , 16)

 #define CMD_RESP(x)         extract32((x)->word[2], 11, 2)

 #define CMD_LEAF(x)         extract32((x)->word[2], 0 , 1)

+#define CMD_TTL(x)          extract32((x)->word[2], 8 , 2)

+#define CMD_TG(x)           extract32((x)->word[2], 10, 2)

 #define CMD_STE_RANGE(x)    extract32((x)->word[2], 0 , 5)

 #define CMD_ADDR(x) ({                                        \

             uint64_t high = (uint64_t)(x)->word[3];           \

diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c

index ae2b769f891..f4d5d9d8222 100644

--- a/hw/arm/smmuv3.c

+++ b/hw/arm/smmuv3.c

@@ -773,42 +773,49 @@ epilogue:

  * @n: notifier to be called

  * @asid: address space ID or negative value if we don't care

  * @iova: iova

+ * @tg: translation granule (if communicated through range invalidation)

+ * @num_pages: number of @granule sized pages (if tg != 0), otherwise 1

  */

 static void smmuv3_notify_iova(IOMMUMemoryRegion *mr,

                                IOMMUNotifier *n,

-                               int asid,

-                               dma_addr_t iova)

+                               int asid, dma_addr_t iova,

+                               uint8_t tg, uint64_t num_pages)

 {

     SMMUDevice *sdev = container_of(mr, SMMUDevice, iommu);

-    SMMUEventInfo event = {.inval_ste_allowed = true};

-    SMMUTransTableInfo *tt;

-    SMMUTransCfg *cfg;

     IOMMUTLBEntry entry;

+    uint8_t granule = tg;

-    cfg = smmuv3_get_config(sdev, &event);

-    if (!cfg) {

-        return;

-    }

+    if (!tg) {

+        SMMUEventInfo event = {.inval_ste_allowed = true};

+        SMMUTransCfg *cfg = smmuv3_get_config(sdev, &event);

+        SMMUTransTableInfo *tt;

-    if (asid >= 0 && cfg->asid != asid) {

-        return;

-    }

+        if (!cfg) {

+            return;

+        }

-    tt = select_tt(cfg, iova);

-    if (!tt) {

-        return;

+        if (asid >= 0 && cfg->asid != asid) {

+            return;

+        }

+

+        tt = select_tt(cfg, iova);

+        if (!tt) {

+            return;

+        }

+        granule = tt->granule_sz;

     }

     entry.target_as = &address_space_memory;

     entry.iova = iova;

-    entry.addr_mask = (1 << tt->granule_sz) - 1;

+    entry.addr_mask = num_pages * (1 << granule) - 1;

     entry.perm = IOMMU_NONE;

     memory_region_notify_one(n, &entry);

 }

-/* invalidate an asid/iova tuple in all mr's */

-static void smmuv3_inv_notifiers_iova(SMMUState *s, int asid, dma_addr_t iova)

+/* invalidate an asid/iova range tuple in all mr's */

+static void smmuv3_inv_notifiers_iova(SMMUState *s, int asid, dma_addr_t iova,

+                                      uint8_t tg, uint64_t num_pages)

 {

     SMMUDevice *sdev;

@@ -816,28 +823,39 @@ static void smmuv3_inv_notifiers_iova(SMMUState *s, int asid, dma_addr_t iova)

         IOMMUMemoryRegion *mr = &sdev->iommu;

         IOMMUNotifier *n;

-        trace_smmuv3_inv_notifiers_iova(mr->parent_obj.name, asid, iova);

+        trace_smmuv3_inv_notifiers_iova(mr->parent_obj.name, asid, iova,

+                                        tg, num_pages);

         IOMMU_NOTIFIER_FOREACH(n, mr) {

-            smmuv3_notify_iova(mr, n, asid, iova);

+            smmuv3_notify_iova(mr, n, asid, iova, tg, num_pages);

         }

     }

 }

 static void smmuv3_s1_range_inval(SMMUState *s, Cmd *cmd)

 {

+    uint8_t scale = 0, num = 0, ttl = 0;

     dma_addr_t addr = CMD_ADDR(cmd);

     uint8_t type = CMD_TYPE(cmd);

     uint16_t vmid = CMD_VMID(cmd);

     bool leaf = CMD_LEAF(cmd);

+    uint8_t tg = CMD_TG(cmd);

+    hwaddr num_pages = 1;

     int asid = -1;

+    if (tg) {

+        scale = CMD_SCALE(cmd);

+        num = CMD_NUM(cmd);

+        ttl = CMD_TTL(cmd);

+        num_pages = (num + 1) * (1 << (scale));

+    }

+

     if (type == SMMU_CMD_TLBI_NH_VA) {

         asid = CMD_ASID(cmd);

     }

-    trace_smmuv3_s1_range_inval(vmid, asid, addr, leaf);

-    smmuv3_inv_notifiers_iova(s, asid, addr);

-    smmu_iotlb_inv_iova(s, asid, addr);

+    trace_smmuv3_s1_range_inval(vmid, asid, addr, tg, num_pages, ttl, leaf);

+    smmuv3_inv_notifiers_iova(s, asid, addr, tg, num_pages);

+    smmu_iotlb_inv_iova(s, asid, addr, tg, num_pages, ttl);

 }

 static int smmuv3_cmdq_consume(SMMUv3State *s)

diff --git a/hw/arm/trace-events b/hw/arm/trace-events

index c219fe9e828..3d905e0f7d0 100644

--- a/hw/arm/trace-events

+++ b/hw/arm/trace-events

@@ -45,11 +45,11 @@ smmuv3_cmdq_cfgi_ste_range(int start, int end) "start=0x%d - end=0x%d"

 smmuv3_cmdq_cfgi_cd(uint32_t sid) "streamid = %d"

 smmuv3_config_cache_hit(uint32_t sid, uint32_t hits, uint32_t misses, uint32_t perc) "Config cache HIT for sid %d (hits=%d, misses=%d, hit rate=%d)"

 smmuv3_config_cache_miss(uint32_t sid, uint32_t hits, uint32_t misses, uint32_t perc) "Config cache MISS for sid %d (hits=%d, misses=%d, hit rate=%d)"

-smmuv3_s1_range_inval(int vmid, int asid, uint64_t addr, bool leaf) "vmid =%d asid =%d addr=0x%"PRIx64" leaf=%d"

+smmuv3_s1_range_inval(int vmid, int asid, uint64_t addr, uint8_t tg, uint64_t num_pages, uint8_t ttl, bool leaf) "vmid =%d asid =%d addr=0x%"PRIx64" tg=%d num_pages=0x%"PRIx64" ttl=%d leaf=%d"

 smmuv3_cmdq_tlbi_nh(void) ""

 smmuv3_cmdq_tlbi_nh_asid(uint16_t asid) "asid=%d"

 smmuv3_config_cache_inv(uint32_t sid) "Config cache INV for sid %d"

 smmuv3_notify_flag_add(const char *iommu) "ADD SMMUNotifier node for iommu mr=%s"

 smmuv3_notify_flag_del(const char *iommu) "DEL SMMUNotifier node for iommu mr=%s"

-smmuv3_inv_notifiers_iova(const char *name, uint16_t asid, uint64_t iova) "iommu mr=%s asid=%d iova=0x%"PRIx64

+smmuv3_inv_notifiers_iova(const char *name, uint16_t asid, uint64_t iova, uint8_t tg, uint64_t num_pages) "iommu mr=%s asid=%d iova=0x%"PRIx64" tg=%d num_pages=0x%"PRIx64

diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h

index bbf3abc41fd..13489a1ac0d 100644

--- a/include/hw/arm/smmu-common.h

+++ b/include/hw/arm/smmu-common.h

@@ -168,7 +168,8 @@ SMMUIOTLBKey smmu_get_iotlb_key(uint16_t asid, uint64_t iova,

                                 uint8_t tg, uint8_t level);

 void smmu_iotlb_inv_all(SMMUState *s);

 void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid);

-void smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova);

+void smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova,

+                         uint8_t tg, uint64_t num_pages, uint8_t ttl);

 /* Unmap the range of all the notifiers registered to any IOMMU mr */

 void smmu_inv_notifiers_all(SMMUState *s);

-- 

2.27.0