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From c1da33afa02ed4978c34f16ec56d60dbfa5ac2c0 Mon Sep 17 00:00:00 2001
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From: Tarun Gupta <tgupta@redhat.com>
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Date: Wed, 20 Jun 2018 18:54:15 +0200
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Subject: [PATCH 07/17] headers: add drm_fourcc.h
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RH-Author: Tarun Gupta <tgupta@redhat.com>
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Message-id: <1529520865-18127-2-git-send-email-tgupta@redhat.com>
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Patchwork-id: 80909
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O-Subject: [RHEL7.6 qemu-kvm PATCH v3 01/11] headers: add drm_fourcc.h
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Bugzilla: 1555246
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RH-Acked-by: Alex Williamson <alex.williamson@redhat.com>
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RH-Acked-by: Gerd Hoffmann <kraxel@redhat.com>
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RH-Acked-by: Miroslav Rezanina <mrezanin@redhat.com>
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So we can use the drm fourcc codes without a dependency on libdrm-devel.
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Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
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Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
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(cherry picked from 8e8ee8509a0d2d5a65d7533e6e9179b6f3b0a0d4)
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Conflict: qemu-kvm does not have the standard-headers directory.
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So, adding the drm_fourcc.h in include/ directory.
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Signed-off-by: Miroslav Rezanina <mrezanin@redhat.com>
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include/drm_fourcc.h | 411 +++++++++++++++++++++++++++++++++++++++++++++++++++
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1 file changed, 411 insertions(+)
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create mode 100644 include/drm_fourcc.h
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diff
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new file mode 100644
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index 0000000..11912fd
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--- /dev/null
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+++ b/include/drm_fourcc.h
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@@ -0,0 +1,411 @@
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+/*
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+ * Copyright 2011 Intel Corporation
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+ *
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+ * Permission is hereby granted, free of charge, to any person obtaining a
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+ * copy of this software and associated documentation files (the "Software"),
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+ * to deal in the Software without restriction, including without limitation
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+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
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+ * and/or sell copies of the Software, and to permit persons to whom the
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+ * Software is furnished to do so, subject to the following conditions:
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+ *
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+ * The above copyright notice and this permission notice (including the next
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+ * paragraph) shall be included in all copies or substantial portions of the
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+ * Software.
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+ *
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+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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+ * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
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+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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+ * OTHER DEALINGS IN THE SOFTWARE.
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+ */
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+
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+#ifndef DRM_FOURCC_H
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+#define DRM_FOURCC_H
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+
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+
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+#if defined(__cplusplus)
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+extern "C" {
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+#endif
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+
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+
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+ ((uint32_t)(c) << 16) | ((uint32_t)(d) << 24))
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+
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+#define DRM_FORMAT_BIG_ENDIAN (1<<31)
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+
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+
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+#define DRM_FORMAT_C8 fourcc_code('C', '8', ' ', ' ')
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+
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+
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+#define DRM_FORMAT_R8 fourcc_code('R', '8', ' ', ' ')
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+
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+
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+#define DRM_FORMAT_R16 fourcc_code('R', '1', '6', ' ')
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+
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+
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+#define DRM_FORMAT_RG88 fourcc_code('R', 'G', '8', '8')
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+#define DRM_FORMAT_GR88 fourcc_code('G', 'R', '8', '8')
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+
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+
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+#define DRM_FORMAT_RG1616 fourcc_code('R', 'G', '3', '2')
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+#define DRM_FORMAT_GR1616 fourcc_code('G', 'R', '3', '2')
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+
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+
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+#define DRM_FORMAT_RGB332 fourcc_code('R', 'G', 'B', '8')
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+#define DRM_FORMAT_BGR233 fourcc_code('B', 'G', 'R', '8')
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+
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+
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+#define DRM_FORMAT_XRGB4444 fourcc_code('X', 'R', '1', '2')
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+#define DRM_FORMAT_XBGR4444 fourcc_code('X', 'B', '1', '2')
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+#define DRM_FORMAT_RGBX4444 fourcc_code('R', 'X', '1', '2')
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+#define DRM_FORMAT_BGRX4444 fourcc_code('B', 'X', '1', '2')
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+
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+#define DRM_FORMAT_ARGB4444 fourcc_code('A', 'R', '1', '2')
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+#define DRM_FORMAT_ABGR4444 fourcc_code('A', 'B', '1', '2')
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+#define DRM_FORMAT_RGBA4444 fourcc_code('R', 'A', '1', '2')
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+#define DRM_FORMAT_BGRA4444 fourcc_code('B', 'A', '1', '2')
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+
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+#define DRM_FORMAT_XRGB1555 fourcc_code('X', 'R', '1', '5')
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+#define DRM_FORMAT_XBGR1555 fourcc_code('X', 'B', '1', '5')
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+#define DRM_FORMAT_RGBX5551 fourcc_code('R', 'X', '1', '5')
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+#define DRM_FORMAT_BGRX5551 fourcc_code('B', 'X', '1', '5')
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+
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+#define DRM_FORMAT_ARGB1555 fourcc_code('A', 'R', '1', '5')
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+#define DRM_FORMAT_ABGR1555 fourcc_code('A', 'B', '1', '5')
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+#define DRM_FORMAT_RGBA5551 fourcc_code('R', 'A', '1', '5')
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+#define DRM_FORMAT_BGRA5551 fourcc_code('B', 'A', '1', '5')
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+
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+#define DRM_FORMAT_RGB565 fourcc_code('R', 'G', '1', '6')
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+#define DRM_FORMAT_BGR565 fourcc_code('B', 'G', '1', '6')
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+
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+
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+#define DRM_FORMAT_RGB888 fourcc_code('R', 'G', '2', '4')
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+#define DRM_FORMAT_BGR888 fourcc_code('B', 'G', '2', '4')
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+
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+
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+#define DRM_FORMAT_XRGB8888 fourcc_code('X', 'R', '2', '4')
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+#define DRM_FORMAT_XBGR8888 fourcc_code('X', 'B', '2', '4')
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+#define DRM_FORMAT_RGBX8888 fourcc_code('R', 'X', '2', '4')
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+#define DRM_FORMAT_BGRX8888 fourcc_code('B', 'X', '2', '4')
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+
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+#define DRM_FORMAT_ARGB8888 fourcc_code('A', 'R', '2', '4')
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+#define DRM_FORMAT_ABGR8888 fourcc_code('A', 'B', '2', '4')
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+#define DRM_FORMAT_RGBA8888 fourcc_code('R', 'A', '2', '4')
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+#define DRM_FORMAT_BGRA8888 fourcc_code('B', 'A', '2', '4')
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+
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+#define DRM_FORMAT_XRGB2101010 fourcc_code('X', 'R', '3', '0')
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+#define DRM_FORMAT_XBGR2101010 fourcc_code('X', 'B', '3', '0')
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+#define DRM_FORMAT_RGBX1010102 fourcc_code('R', 'X', '3', '0')
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+#define DRM_FORMAT_BGRX1010102 fourcc_code('B', 'X', '3', '0')
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+
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+#define DRM_FORMAT_ARGB2101010 fourcc_code('A', 'R', '3', '0')
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+#define DRM_FORMAT_ABGR2101010 fourcc_code('A', 'B', '3', '0')
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+#define DRM_FORMAT_RGBA1010102 fourcc_code('R', 'A', '3', '0')
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+#define DRM_FORMAT_BGRA1010102 fourcc_code('B', 'A', '3', '0')
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+
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+
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+#define DRM_FORMAT_YUYV fourcc_code('Y', 'U', 'Y', 'V')
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+#define DRM_FORMAT_YVYU fourcc_code('Y', 'V', 'Y', 'U')
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+#define DRM_FORMAT_UYVY fourcc_code('U', 'Y', 'V', 'Y')
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+#define DRM_FORMAT_VYUY fourcc_code('V', 'Y', 'U', 'Y')
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+
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+#define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V')
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+
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+/*
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+ * 2 plane RGB + A
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+ * index 0 = RGB plane, same format as the corresponding non _A8 format has
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+ * index 1 = A plane, [7:0] A
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+ */
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+#define DRM_FORMAT_XRGB8888_A8 fourcc_code('X', 'R', 'A', '8')
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+#define DRM_FORMAT_XBGR8888_A8 fourcc_code('X', 'B', 'A', '8')
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+#define DRM_FORMAT_RGBX8888_A8 fourcc_code('R', 'X', 'A', '8')
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+#define DRM_FORMAT_BGRX8888_A8 fourcc_code('B', 'X', 'A', '8')
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+#define DRM_FORMAT_RGB888_A8 fourcc_code('R', '8', 'A', '8')
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+#define DRM_FORMAT_BGR888_A8 fourcc_code('B', '8', 'A', '8')
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+#define DRM_FORMAT_RGB565_A8 fourcc_code('R', '5', 'A', '8')
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+#define DRM_FORMAT_BGR565_A8 fourcc_code('B', '5', 'A', '8')
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+
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+/*
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+ * 2 plane YCbCr
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+ * index 0 = Y plane, [7:0] Y
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+ * index 1 = Cr:Cb plane, [15:0] Cr:Cb little endian
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+ * or
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+ * index 1 = Cb:Cr plane, [15:0] Cb:Cr little endian
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+ */
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+#define DRM_FORMAT_NV12 fourcc_code('N', 'V', '1', '2')
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+#define DRM_FORMAT_NV21 fourcc_code('N', 'V', '2', '1')
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+#define DRM_FORMAT_NV16 fourcc_code('N', 'V', '1', '6')
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+#define DRM_FORMAT_NV61 fourcc_code('N', 'V', '6', '1')
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+#define DRM_FORMAT_NV24 fourcc_code('N', 'V', '2', '4')
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+#define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2')
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+
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+/*
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+ * 3 plane YCbCr
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+ * index 0: Y plane, [7:0] Y
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+ * index 1: Cb plane, [7:0] Cb
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+ * index 2: Cr plane, [7:0] Cr
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+ * or
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+ * index 1: Cr plane, [7:0] Cr
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+ * index 2: Cb plane, [7:0] Cb
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+ */
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+#define DRM_FORMAT_YUV410 fourcc_code('Y', 'U', 'V', '9')
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+#define DRM_FORMAT_YVU410 fourcc_code('Y', 'V', 'U', '9')
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+#define DRM_FORMAT_YUV411 fourcc_code('Y', 'U', '1', '1')
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+#define DRM_FORMAT_YVU411 fourcc_code('Y', 'V', '1', '1')
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+#define DRM_FORMAT_YUV420 fourcc_code('Y', 'U', '1', '2')
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+#define DRM_FORMAT_YVU420 fourcc_code('Y', 'V', '1', '2')
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+#define DRM_FORMAT_YUV422 fourcc_code('Y', 'U', '1', '6')
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+#define DRM_FORMAT_YVU422 fourcc_code('Y', 'V', '1', '6')
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+#define DRM_FORMAT_YUV444 fourcc_code('Y', 'U', '2', '4')
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+#define DRM_FORMAT_YVU444 fourcc_code('Y', 'V', '2', '4')
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+
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+
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+/*
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+ * Format Modifiers:
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+ *
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+ * Format modifiers describe, typically, a re-ordering or modification
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+ * of the data in a plane of an FB. This can be used to express tiled/
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+ * swizzled formats, or compression, or a combination of the two.
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+ *
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+ * The upper 8 bits of the format modifier are a vendor-id as assigned
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+ * below. The lower 56 bits are assigned as vendor sees fit.
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+ */
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+
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+
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+#define DRM_FORMAT_MOD_NONE 0
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+#define DRM_FORMAT_MOD_VENDOR_NONE 0
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+#define DRM_FORMAT_MOD_VENDOR_INTEL 0x01
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+#define DRM_FORMAT_MOD_VENDOR_AMD 0x02
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+#define DRM_FORMAT_MOD_VENDOR_NVIDIA 0x03
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+#define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04
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+#define DRM_FORMAT_MOD_VENDOR_QCOM 0x05
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+#define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06
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+#define DRM_FORMAT_MOD_VENDOR_BROADCOM 0x07
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+
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+
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+#define DRM_FORMAT_RESERVED ((1ULL << 56) - 1)
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+
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+#define fourcc_mod_code(vendor, val) \
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+ ((((uint64_t)DRM_FORMAT_MOD_VENDOR_
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+
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+/*
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+ * Format Modifier tokens:
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+ *
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+ * When adding a new token please document the layout with a code comment,
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+ * similar to the fourcc codes above. drm_fourcc.h is considered the
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+ * authoritative source for all of these.
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+ */
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+
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+/*
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+ * Invalid Modifier
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+ *
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+ * This modifier can be used as a sentinel to terminate the format modifiers
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+ * list, or to initialize a variable with an invalid modifier. It might also be
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+ * used to report an error back to userspace for certain APIs.
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+ */
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+#define DRM_FORMAT_MOD_INVALID fourcc_mod_code(NONE, DRM_FORMAT_RESERVED)
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+
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+/*
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+ * Linear Layout
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+ *
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+ * Just plain linear layout. Note that this is different from no specifying any
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169b9a |
+ * modifier (e.g. not setting DRM_MODE_FB_MODIFIERS in the DRM_ADDFB2 ioctl),
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+ * which tells the driver to also take driver-internal information into account
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169b9a |
+ * and so might actually result in a tiled framebuffer.
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169b9a |
+ */
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169b9a |
+#define DRM_FORMAT_MOD_LINEAR fourcc_mod_code(NONE, 0)
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+
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169b9a |
+
|
|
|
169b9a |
+
|
|
|
169b9a |
+/*
|
|
|
169b9a |
+ * Intel X-tiling layout
|
|
|
169b9a |
+ *
|
|
|
169b9a |
+ * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
|
|
|
169b9a |
+ * in row-major layout. Within the tile bytes are laid out row-major, with
|
|
|
169b9a |
+ * a platform-dependent stride. On top of that the memory can apply
|
|
|
169b9a |
+ * platform-depending swizzling of some higher address bits into bit6.
|
|
|
169b9a |
+ *
|
|
|
169b9a |
+ * This format is highly platforms specific and not useful for cross-driver
|
|
|
169b9a |
+ * sharing. It exists since on a given platform it does uniquely identify the
|
|
|
169b9a |
+ * layout in a simple way for i915-specific userspace.
|
|
|
169b9a |
+ */
|
|
|
169b9a |
+#define I915_FORMAT_MOD_X_TILED fourcc_mod_code(INTEL, 1)
|
|
|
169b9a |
+
|
|
|
169b9a |
+/*
|
|
|
169b9a |
+ * Intel Y-tiling layout
|
|
|
169b9a |
+ *
|
|
|
169b9a |
+ * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
|
|
|
169b9a |
+ * in row-major layout. Within the tile bytes are laid out in OWORD (16 bytes)
|
|
|
169b9a |
+ * chunks column-major, with a platform-dependent height. On top of that the
|
|
|
169b9a |
+ * memory can apply platform-depending swizzling of some higher address bits
|
|
|
169b9a |
+ * into bit6.
|
|
|
169b9a |
+ *
|
|
|
169b9a |
+ * This format is highly platforms specific and not useful for cross-driver
|
|
|
169b9a |
+ * sharing. It exists since on a given platform it does uniquely identify the
|
|
|
169b9a |
+ * layout in a simple way for i915-specific userspace.
|
|
|
169b9a |
+ */
|
|
|
169b9a |
+#define I915_FORMAT_MOD_Y_TILED fourcc_mod_code(INTEL, 2)
|
|
|
169b9a |
+
|
|
|
169b9a |
+/*
|
|
|
169b9a |
+ * Intel Yf-tiling layout
|
|
|
169b9a |
+ *
|
|
|
169b9a |
+ * This is a tiled layout using 4Kb tiles in row-major layout.
|
|
|
169b9a |
+ * Within the tile pixels are laid out in 16 256 byte units / sub-tiles which
|
|
|
169b9a |
+ * are arranged in four groups (two wide, two high) with column-major layout.
|
|
|
169b9a |
+ * Each group therefore consits out of four 256 byte units, which are also laid
|
|
|
169b9a |
+ * out as 2x2 column-major.
|
|
|
169b9a |
+ * 256 byte units are made out of four 64 byte blocks of pixels, producing
|
|
|
169b9a |
+ * either a square block or a 2:1 unit.
|
|
|
169b9a |
+ * 64 byte blocks of pixels contain four pixel rows of 16 bytes, where the width
|
|
|
169b9a |
+ * in pixel depends on the pixel depth.
|
|
|
169b9a |
+ */
|
|
|
169b9a |
+#define I915_FORMAT_MOD_Yf_TILED fourcc_mod_code(INTEL, 3)
|
|
|
169b9a |
+
|
|
|
169b9a |
+/*
|
|
|
169b9a |
+ * Intel color control surface (CCS) for render compression
|
|
|
169b9a |
+ *
|
|
|
169b9a |
+ * The framebuffer format must be one of the 8:8:8:8 RGB formats.
|
|
|
169b9a |
+ * The main surface will be plane index 0 and must be Y/Yf-tiled,
|
|
|
169b9a |
+ * the CCS will be plane index 1.
|
|
|
169b9a |
+ *
|
|
|
169b9a |
+ * Each CCS tile matches a 1024x512 pixel area of the main surface.
|
|
|
169b9a |
+ * To match certain aspects of the 3D hardware the CCS is
|
|
|
169b9a |
+ * considered to be made up of normal 128Bx32 Y tiles, Thus
|
|
|
169b9a |
+ * the CCS pitch must be specified in multiples of 128 bytes.
|
|
|
169b9a |
+ *
|
|
|
169b9a |
+ * In reality the CCS tile appears to be a 64Bx64 Y tile, composed
|
|
|
169b9a |
+ * of QWORD (8 bytes) chunks instead of OWORD (16 bytes) chunks.
|
|
|
169b9a |
+ * But that fact is not relevant unless the memory is accessed
|
|
|
169b9a |
+ * directly.
|
|
|
169b9a |
+ */
|
|
|
169b9a |
+#define I915_FORMAT_MOD_Y_TILED_CCS fourcc_mod_code(INTEL, 4)
|
|
|
169b9a |
+#define I915_FORMAT_MOD_Yf_TILED_CCS fourcc_mod_code(INTEL, 5)
|
|
|
169b9a |
+
|
|
|
169b9a |
+/*
|
|
|
169b9a |
+ * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
|
|
|
169b9a |
+ *
|
|
|
169b9a |
+ * Macroblocks are laid in a Z-shape, and each pixel data is following the
|
|
|
169b9a |
+ * standard NV12 style.
|
|
|
169b9a |
+ * As for NV12, an image is the result of two frame buffers: one for Y,
|
|
|
169b9a |
+ * one for the interleaved Cb/Cr components (1/2 the height of the Y buffer).
|
|
|
169b9a |
+ * Alignment requirements are (for each buffer):
|
|
|
169b9a |
+ * - multiple of 128 pixels for the width
|
|
|
169b9a |
+ * - multiple of 32 pixels for the height
|
|
|
169b9a |
+ *
|
|
|
169b9a |
+ * For more information: see https:
|
|
|
169b9a |
+ */
|
|
|
169b9a |
+#define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1)
|
|
|
169b9a |
+
|
|
|
169b9a |
+
|
|
|
169b9a |
+
|
|
|
169b9a |
+/*
|
|
|
169b9a |
+ * Vivante 4x4 tiling layout
|
|
|
169b9a |
+ *
|
|
|
169b9a |
+ * This is a simple tiled layout using tiles of 4x4 pixels in a row-major
|
|
|
169b9a |
+ * layout.
|
|
|
169b9a |
+ */
|
|
|
169b9a |
+#define DRM_FORMAT_MOD_VIVANTE_TILED fourcc_mod_code(VIVANTE, 1)
|
|
|
169b9a |
+
|
|
|
169b9a |
+/*
|
|
|
169b9a |
+ * Vivante 64x64 super-tiling layout
|
|
|
169b9a |
+ *
|
|
|
169b9a |
+ * This is a tiled layout using 64x64 pixel super-tiles, where each super-tile
|
|
|
169b9a |
+ * contains 8x4 groups of 2x4 tiles of 4x4 pixels (like above) each, all in row-
|
|
|
169b9a |
+ * major layout.
|
|
|
169b9a |
+ *
|
|
|
169b9a |
+ * For more information: see
|
|
|
169b9a |
+ * https://github.com/etnaviv/etna_viv/blob/master/doc/hardware.md#texture-tiling
|
|
|
169b9a |
+ */
|
|
|
169b9a |
+#define DRM_FORMAT_MOD_VIVANTE_SUPER_TILED fourcc_mod_code(VIVANTE, 2)
|
|
|
169b9a |
+
|
|
|
169b9a |
+/*
|
|
|
169b9a |
+ * Vivante 4x4 tiling layout for dual-pipe
|
|
|
169b9a |
+ *
|
|
|
169b9a |
+ * Same as the 4x4 tiling layout, except every second 4x4 pixel tile starts at a
|
|
|
169b9a |
+ * different base address. Offsets from the base addresses are therefore halved
|
|
|
169b9a |
+ * compared to the non-split tiled layout.
|
|
|
169b9a |
+ */
|
|
|
169b9a |
+#define DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED fourcc_mod_code(VIVANTE, 3)
|
|
|
169b9a |
+
|
|
|
169b9a |
+/*
|
|
|
169b9a |
+ * Vivante 64x64 super-tiling layout for dual-pipe
|
|
|
169b9a |
+ *
|
|
|
169b9a |
+ * Same as the 64x64 super-tiling layout, except every second 4x4 pixel tile
|
|
|
169b9a |
+ * starts at a different base address. Offsets from the base addresses are
|
|
|
169b9a |
+ * therefore halved compared to the non-split super-tiled layout.
|
|
|
169b9a |
+ */
|
|
|
169b9a |
+#define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4)
|
|
|
169b9a |
+
|
|
|
169b9a |
+
|
|
|
169b9a |
+
|
|
|
169b9a |
+/*
|
|
|
169b9a |
+ * Tegra Tiled Layout, used by Tegra 2, 3 and 4.
|
|
|
169b9a |
+ *
|
|
|
169b9a |
+ * Pixels are arranged in simple tiles of 16 x 16 bytes.
|
|
|
169b9a |
+ */
|
|
|
169b9a |
+#define DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED fourcc_mod_code(NVIDIA, 1)
|
|
|
169b9a |
+
|
|
|
169b9a |
+/*
|
|
|
169b9a |
+ * 16Bx2 Block Linear layout, used by desktop GPUs, and Tegra K1 and later
|
|
|
169b9a |
+ *
|
|
|
169b9a |
+ * Pixels are arranged in 64x8 Groups Of Bytes (GOBs). GOBs are then stacked
|
|
|
169b9a |
+ * vertically by a power of 2 (1 to 32 GOBs) to form a block.
|
|
|
169b9a |
+ *
|
|
|
169b9a |
+ * Within a GOB, data is ordered as 16B x 2 lines sectors laid in Z-shape.
|
|
|
169b9a |
+ *
|
|
|
169b9a |
+ * Parameter 'v' is the log2 encoding of the number of GOBs stacked vertically.
|
|
|
169b9a |
+ * Valid values are:
|
|
|
169b9a |
+ *
|
|
|
169b9a |
+ * 0 == ONE_GOB
|
|
|
169b9a |
+ * 1 == TWO_GOBS
|
|
|
169b9a |
+ * 2 == FOUR_GOBS
|
|
|
169b9a |
+ * 3 == EIGHT_GOBS
|
|
|
169b9a |
+ * 4 == SIXTEEN_GOBS
|
|
|
169b9a |
+ * 5 == THIRTYTWO_GOBS
|
|
|
169b9a |
+ *
|
|
|
169b9a |
+ * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format
|
|
|
169b9a |
+ * in full detail.
|
|
|
169b9a |
+ */
|
|
|
169b9a |
+#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(v) \
|
|
|
169b9a |
+ fourcc_mod_code(NVIDIA, 0x10 | ((v) & 0xf))
|
|
|
169b9a |
+
|
|
|
169b9a |
+#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_ONE_GOB \
|
|
|
169b9a |
+ fourcc_mod_code(NVIDIA, 0x10)
|
|
|
169b9a |
+#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_TWO_GOB \
|
|
|
169b9a |
+ fourcc_mod_code(NVIDIA, 0x11)
|
|
|
169b9a |
+#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_FOUR_GOB \
|
|
|
169b9a |
+ fourcc_mod_code(NVIDIA, 0x12)
|
|
|
169b9a |
+#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_EIGHT_GOB \
|
|
|
169b9a |
+ fourcc_mod_code(NVIDIA, 0x13)
|
|
|
169b9a |
+#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_SIXTEEN_GOB \
|
|
|
169b9a |
+ fourcc_mod_code(NVIDIA, 0x14)
|
|
|
169b9a |
+#define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_THIRTYTWO_GOB \
|
|
|
169b9a |
+ fourcc_mod_code(NVIDIA, 0x15)
|
|
|
169b9a |
+
|
|
|
169b9a |
+/*
|
|
|
169b9a |
+ * Broadcom VC4 "T" format
|
|
|
169b9a |
+ *
|
|
|
169b9a |
+ * This is the primary layout that the V3D GPU can texture from (it
|
|
|
169b9a |
+ * can't do linear). The T format has:
|
|
|
169b9a |
+ *
|
|
|
169b9a |
+ * - 64b utiles of pixels in a raster-order grid according to cpp. It's 4x4
|
|
|
169b9a |
+ * pixels at 32 bit depth.
|
|
|
169b9a |
+ *
|
|
|
169b9a |
+ * - 1k subtiles made of a 4x4 raster-order grid of 64b utiles (so usually
|
|
|
169b9a |
+ * 16x16 pixels).
|
|
|
169b9a |
+ *
|
|
|
169b9a |
+ * - 4k tiles made of a 2x2 grid of 1k subtiles (so usually 32x32 pixels). On
|
|
|
169b9a |
+ * even 4k tile rows, they're arranged as (BL, TL, TR, BR), and on odd rows
|
|
|
169b9a |
+ * they're (TR, BR, BL, TL), where bottom left is start of memory.
|
|
|
169b9a |
+ *
|
|
|
169b9a |
+ * - an image made of 4k tiles in rows either left-to-right (even rows of 4k
|
|
|
169b9a |
+ * tiles) or right-to-left (odd rows of 4k tiles).
|
|
|
169b9a |
+ */
|
|
|
169b9a |
+#define DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED fourcc_mod_code(BROADCOM, 1)
|
|
|
169b9a |
+
|
|
|
169b9a |
+#if defined(__cplusplus)
|
|
|
169b9a |
+}
|
|
|
169b9a |
+#endif
|
|
|
169b9a |
+
|
|
|
169b9a |
+#endif
|
|
|
169b9a |
--
|
|
|
169b9a |
1.8.3.1
|
|
|
169b9a |
|