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From 064565e76b986a42d9cdcba72965887528cea90a Mon Sep 17 00:00:00 2001
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From: Maxim Levitsky <mlevitsk@redhat.com>
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Date: Sun, 22 Dec 2019 11:02:06 +0100
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Subject: [PATCH 1/7] exec: Fix MAP_RAM for cached access
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RH-Author: Maxim Levitsky <mlevitsk@redhat.com>
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Message-id: <20191222110207.21384-2-mlevitsk@redhat.com>
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Patchwork-id: 93207
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O-Subject: [RHEL-8.2.0 qemu-kvm PATCH 1/2] exec: Fix MAP_RAM for cached access
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Bugzilla: 1769613
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RH-Acked-by: Paolo Bonzini <pbonzini@redhat.com>
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RH-Acked-by: Cornelia Huck <cohuck@redhat.com>
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RH-Acked-by: Peter Xu <peterx@redhat.com>
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From: Eric Auger <eric.auger@redhat.com>
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When an IOMMUMemoryRegion is in front of a virtio device,
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address_space_cache_init does not set cache->ptr as the memory
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region is not RAM. However when the device performs an access,
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we end up in glue() which performs the translation and then uses
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MAP_RAM. This latter uses the unset ptr and returns a wrong value
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which leads to a SIGSEV in address_space_lduw_internal_cached_slow,
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for instance.
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In slow path cache->ptr is NULL and MAP_RAM must redirect to
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qemu_map_ram_ptr((mr)->ram_block, ofs).
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As MAP_RAM, IS_DIRECT and INVALIDATE are the same in _cached_slow
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and non cached mode, let's remove those macros.
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This fixes the use cases featuring vIOMMU (Intel and ARM SMMU)
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which lead to a SIGSEV.
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Fixes: 48564041a73a (exec: reintroduce MemoryRegion caching)
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Signed-off-by: Eric Auger <eric.auger@redhat.com>
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Message-Id: <1528895946-28677-1-git-send-email-eric.auger@redhat.com>
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Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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(cherry picked from commit a99761d3c85679da380c0f597468acd3dc1b53b3)
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Signed-off-by: Maxim Levitsky <mlevitsk@redhat.com>
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Signed-off-by: Miroslav Rezanina <mrezanin@redhat.com>
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---
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 exec.c            |  6 ------
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 memory_ldst.inc.c | 47 ++++++++++++++++++++++-------------------------
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 2 files changed, 22 insertions(+), 31 deletions(-)
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diff --git a/exec.c b/exec.c
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index 9112d8b..86218ef 100644
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--- a/exec.c
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+++ b/exec.c
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@@ -3608,9 +3608,6 @@ void cpu_physical_memory_unmap(void *buffer, hwaddr len,
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 #define ARG1                     as
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 #define SUFFIX
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 #define TRANSLATE(...)           address_space_translate(as, __VA_ARGS__)
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-#define IS_DIRECT(mr, is_write)  memory_access_is_direct(mr, is_write)
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-#define MAP_RAM(mr, ofs)         qemu_map_ram_ptr((mr)->ram_block, ofs)
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-#define INVALIDATE(mr, ofs, len) invalidate_and_set_dirty(mr, ofs, len)
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 #define RCU_READ_LOCK(...)       rcu_read_lock()
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 #define RCU_READ_UNLOCK(...)     rcu_read_unlock()
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 #include "memory_ldst.inc.c"
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@@ -3643,9 +3640,6 @@ void address_space_cache_destroy(MemoryRegionCache *cache)
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 #define SUFFIX                   _cached
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 #define TRANSLATE(addr, ...)     \
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     address_space_translate(cache->as, cache->xlat + (addr), __VA_ARGS__)
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-#define IS_DIRECT(mr, is_write)  true
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-#define MAP_RAM(mr, ofs)         qemu_map_ram_ptr((mr)->ram_block, ofs)
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-#define INVALIDATE(mr, ofs, len) invalidate_and_set_dirty(mr, ofs, len)
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 #define RCU_READ_LOCK()          rcu_read_lock()
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 #define RCU_READ_UNLOCK()        rcu_read_unlock()
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 #include "memory_ldst.inc.c"
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diff --git a/memory_ldst.inc.c b/memory_ldst.inc.c
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index 5dbff9c..a30060c 100644
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--- a/memory_ldst.inc.c
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+++ b/memory_ldst.inc.c
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@@ -34,7 +34,7 @@ static inline uint32_t glue(address_space_ldl_internal, SUFFIX)(ARG1_DECL,
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     RCU_READ_LOCK();
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     mr = TRANSLATE(addr, &addr1, &l, false);
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-    if (l < 4 || !IS_DIRECT(mr, false)) {
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+    if (l < 4 || !memory_access_is_direct(mr, false)) {
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         release_lock |= prepare_mmio_access(mr);
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         /* I/O case */
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@@ -50,7 +50,7 @@ static inline uint32_t glue(address_space_ldl_internal, SUFFIX)(ARG1_DECL,
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 #endif
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     } else {
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         /* RAM case */
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-        ptr = MAP_RAM(mr, addr1);
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+        ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
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         switch (endian) {
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         case DEVICE_LITTLE_ENDIAN:
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             val = ldl_le_p(ptr);
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@@ -128,7 +128,7 @@ static inline uint64_t glue(address_space_ldq_internal, SUFFIX)(ARG1_DECL,
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     RCU_READ_LOCK();
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     mr = TRANSLATE(addr, &addr1, &l, false);
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-    if (l < 8 || !IS_DIRECT(mr, false)) {
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+    if (l < 8 || !memory_access_is_direct(mr, false)) {
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         release_lock |= prepare_mmio_access(mr);
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         /* I/O case */
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@@ -144,7 +144,7 @@ static inline uint64_t glue(address_space_ldq_internal, SUFFIX)(ARG1_DECL,
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 #endif
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     } else {
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         /* RAM case */
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-        ptr = MAP_RAM(mr, addr1);
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+        ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
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         switch (endian) {
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         case DEVICE_LITTLE_ENDIAN:
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             val = ldq_le_p(ptr);
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@@ -220,14 +220,14 @@ uint32_t glue(address_space_ldub, SUFFIX)(ARG1_DECL,
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     RCU_READ_LOCK();
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     mr = TRANSLATE(addr, &addr1, &l, false);
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-    if (!IS_DIRECT(mr, false)) {
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+    if (!memory_access_is_direct(mr, false)) {
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         release_lock |= prepare_mmio_access(mr);
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         /* I/O case */
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         r = memory_region_dispatch_read(mr, addr1, &val, 1, attrs);
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     } else {
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         /* RAM case */
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-        ptr = MAP_RAM(mr, addr1);
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+        ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
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         val = ldub_p(ptr);
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         r = MEMTX_OK;
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     }
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@@ -262,7 +262,7 @@ static inline uint32_t glue(address_space_lduw_internal, SUFFIX)(ARG1_DECL,
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     RCU_READ_LOCK();
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     mr = TRANSLATE(addr, &addr1, &l, false);
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-    if (l < 2 || !IS_DIRECT(mr, false)) {
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+    if (l < 2 || !memory_access_is_direct(mr, false)) {
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         release_lock |= prepare_mmio_access(mr);
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         /* I/O case */
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@@ -278,7 +278,7 @@ static inline uint32_t glue(address_space_lduw_internal, SUFFIX)(ARG1_DECL,
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 #endif
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     } else {
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         /* RAM case */
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-        ptr = MAP_RAM(mr, addr1);
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+        ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
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         switch (endian) {
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         case DEVICE_LITTLE_ENDIAN:
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             val = lduw_le_p(ptr);
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@@ -357,12 +357,12 @@ void glue(address_space_stl_notdirty, SUFFIX)(ARG1_DECL,
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     RCU_READ_LOCK();
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     mr = TRANSLATE(addr, &addr1, &l, true);
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-    if (l < 4 || !IS_DIRECT(mr, true)) {
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+    if (l < 4 || !memory_access_is_direct(mr, true)) {
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         release_lock |= prepare_mmio_access(mr);
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         r = memory_region_dispatch_write(mr, addr1, val, 4, attrs);
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     } else {
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-        ptr = MAP_RAM(mr, addr1);
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+        ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
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         stl_p(ptr, val);
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         dirty_log_mask = memory_region_get_dirty_log_mask(mr);
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@@ -400,7 +400,7 @@ static inline void glue(address_space_stl_internal, SUFFIX)(ARG1_DECL,
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     RCU_READ_LOCK();
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     mr = TRANSLATE(addr, &addr1, &l, true);
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-    if (l < 4 || !IS_DIRECT(mr, true)) {
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+    if (l < 4 || !memory_access_is_direct(mr, true)) {
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         release_lock |= prepare_mmio_access(mr);
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 #if defined(TARGET_WORDS_BIGENDIAN)
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@@ -415,7 +415,7 @@ static inline void glue(address_space_stl_internal, SUFFIX)(ARG1_DECL,
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         r = memory_region_dispatch_write(mr, addr1, val, 4, attrs);
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     } else {
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         /* RAM case */
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-        ptr = MAP_RAM(mr, addr1);
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+        ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
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         switch (endian) {
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         case DEVICE_LITTLE_ENDIAN:
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             stl_le_p(ptr, val);
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@@ -427,7 +427,7 @@ static inline void glue(address_space_stl_internal, SUFFIX)(ARG1_DECL,
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             stl_p(ptr, val);
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             break;
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         }
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-        INVALIDATE(mr, addr1, 4);
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+        invalidate_and_set_dirty(mr, addr1, 4);
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         r = MEMTX_OK;
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     }
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     if (result) {
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@@ -490,14 +490,14 @@ void glue(address_space_stb, SUFFIX)(ARG1_DECL,
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     RCU_READ_LOCK();
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     mr = TRANSLATE(addr, &addr1, &l, true);
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-    if (!IS_DIRECT(mr, true)) {
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+    if (!memory_access_is_direct(mr, true)) {
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         release_lock |= prepare_mmio_access(mr);
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         r = memory_region_dispatch_write(mr, addr1, val, 1, attrs);
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     } else {
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         /* RAM case */
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-        ptr = MAP_RAM(mr, addr1);
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+        ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
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         stb_p(ptr, val);
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-        INVALIDATE(mr, addr1, 1);
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+        invalidate_and_set_dirty(mr, addr1, 1);
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         r = MEMTX_OK;
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     }
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     if (result) {
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@@ -529,7 +529,7 @@ static inline void glue(address_space_stw_internal, SUFFIX)(ARG1_DECL,
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     RCU_READ_LOCK();
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     mr = TRANSLATE(addr, &addr1, &l, true);
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-    if (l < 2 || !IS_DIRECT(mr, true)) {
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+    if (l < 2 || !memory_access_is_direct(mr, true)) {
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         release_lock |= prepare_mmio_access(mr);
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 #if defined(TARGET_WORDS_BIGENDIAN)
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@@ -544,7 +544,7 @@ static inline void glue(address_space_stw_internal, SUFFIX)(ARG1_DECL,
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         r = memory_region_dispatch_write(mr, addr1, val, 2, attrs);
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     } else {
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         /* RAM case */
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-        ptr = MAP_RAM(mr, addr1);
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+        ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
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         switch (endian) {
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         case DEVICE_LITTLE_ENDIAN:
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             stw_le_p(ptr, val);
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@@ -556,7 +556,7 @@ static inline void glue(address_space_stw_internal, SUFFIX)(ARG1_DECL,
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             stw_p(ptr, val);
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             break;
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         }
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-        INVALIDATE(mr, addr1, 2);
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+        invalidate_and_set_dirty(mr, addr1, 2);
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         r = MEMTX_OK;
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     }
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     if (result) {
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@@ -620,7 +620,7 @@ static void glue(address_space_stq_internal, SUFFIX)(ARG1_DECL,
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     RCU_READ_LOCK();
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     mr = TRANSLATE(addr, &addr1, &l, true);
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-    if (l < 8 || !IS_DIRECT(mr, true)) {
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+    if (l < 8 || !memory_access_is_direct(mr, true)) {
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         release_lock |= prepare_mmio_access(mr);
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 #if defined(TARGET_WORDS_BIGENDIAN)
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@@ -635,7 +635,7 @@ static void glue(address_space_stq_internal, SUFFIX)(ARG1_DECL,
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         r = memory_region_dispatch_write(mr, addr1, val, 8, attrs);
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     } else {
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         /* RAM case */
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-        ptr = MAP_RAM(mr, addr1);
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+        ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
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         switch (endian) {
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         case DEVICE_LITTLE_ENDIAN:
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             stq_le_p(ptr, val);
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@@ -647,7 +647,7 @@ static void glue(address_space_stq_internal, SUFFIX)(ARG1_DECL,
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             stq_p(ptr, val);
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             break;
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         }
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-        INVALIDATE(mr, addr1, 8);
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+        invalidate_and_set_dirty(mr, addr1, 8);
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         r = MEMTX_OK;
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     }
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     if (result) {
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@@ -702,8 +702,5 @@ void glue(stq_be_phys, SUFFIX)(ARG1_DECL, hwaddr addr, uint64_t val)
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 #undef ARG1
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 #undef SUFFIX
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 #undef TRANSLATE
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-#undef IS_DIRECT
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-#undef MAP_RAM
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-#undef INVALIDATE
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 #undef RCU_READ_LOCK
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 #undef RCU_READ_UNLOCK
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-- 
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1.8.3.1
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