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From 76f698948781a148d336ff9032159f6c7c9eccd2 Mon Sep 17 00:00:00 2001
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From: Aurelien Jarno <aurelien@aurel32.net>
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Date: Wed, 28 Aug 2013 14:17:39 +0200
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Subject: [PATCH] pcnet-pci: mark I/O and MMIO as LITTLE_ENDIAN
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Now that the memory subsystem is propagating the endianness correctly,
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the pcnet-pci device should have its I/O ports and MMIO memory marked
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as LITTLE_ENDIAN, as PCI devices are little endian.
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This makes the pcnet-pci NIC to work again on big endian MIPS Malta
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(default NIC).
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Cc: qemu-stable@nongnu.org
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Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
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Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
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(cherry picked from commit a26405b350c0d31d5ef53f3b459aeb6eaaf50db0)
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Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>
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---
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hw/net/pcnet-pci.c | 4 ++--
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1 file changed, 2 insertions(+), 2 deletions(-)
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diff --git a/hw/net/pcnet-pci.c b/hw/net/pcnet-pci.c
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index 2c2301c..23fc33c 100644
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--- a/hw/net/pcnet-pci.c
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+++ b/hw/net/pcnet-pci.c
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@@ -134,7 +134,7 @@ static void pcnet_ioport_write(void *opaque, hwaddr addr,
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static const MemoryRegionOps pcnet_io_ops = {
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.read = pcnet_ioport_read,
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.write = pcnet_ioport_write,
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- .endianness = DEVICE_NATIVE_ENDIAN,
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+ .endianness = DEVICE_LITTLE_ENDIAN,
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};
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static void pcnet_mmio_writeb(void *opaque, hwaddr addr, uint32_t val)
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@@ -256,7 +256,7 @@ static const MemoryRegionOps pcnet_mmio_ops = {
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.read = { pcnet_mmio_readb, pcnet_mmio_readw, pcnet_mmio_readl },
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.write = { pcnet_mmio_writeb, pcnet_mmio_writew, pcnet_mmio_writel },
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},
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- .endianness = DEVICE_NATIVE_ENDIAN,
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+ .endianness = DEVICE_LITTLE_ENDIAN,
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};
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static void pci_physical_memory_write(void *dma_opaque, hwaddr addr,
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