From 37769d27270eff15d878a1c7df23407fc5f09b7f Mon Sep 17 00:00:00 2001

From: Aurelien Jarno <aurelien@aurel32.net>

Date: Sat, 7 Jan 2012 15:20:12 +0100

Subject: [PATCH 19/25] target-sh4: ignore ocbp and ocbwb instructions

ocbp and ocbwb controls the writeback of a cache line to memory. They

are supposed to do nothing in case of a cache miss. Given QEMU only

partially emulate caches, it is safe to ignore these instructions.

This fixes a kernel oops when trying to access an rtl8139 NIC with

recent versions.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

(cherry picked from commit 0cdb95549fedc73e13c147ab9dcabcc303426a07)

---

 target-sh4/translate.c |   14 +++-----------

 1 files changed, 3 insertions(+), 11 deletions(-)

diff --git a/target-sh4/translate.c b/target-sh4/translate.c

index bad3577..e04a6e0 100644

--- a/target-sh4/translate.c

+++ b/target-sh4/translate.c

@@ -1652,18 +1652,10 @@ static void _decode_opc(DisasContext * ctx)

 	}

 	return;

     case 0x00a3:		/* ocbp @Rn */

-	{

-	    TCGv dummy = tcg_temp_new();

-	    tcg_gen_qemu_ld32s(dummy, REG(B11_8), ctx->memidx);

-	    tcg_temp_free(dummy);

-	}

-	return;

     case 0x00b3:		/* ocbwb @Rn */

-	{

-	    TCGv dummy = tcg_temp_new();

-	    tcg_gen_qemu_ld32s(dummy, REG(B11_8), ctx->memidx);

-	    tcg_temp_free(dummy);

-	}

+        /* These instructions are supposed to do nothing in case of

+           a cache miss. Given that we only partially emulate caches

+           it is safe to simply ignore them. */

 	return;

     case 0x0083:		/* pref @Rn */

 	return;

-- 

1.7.7.5