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5544c1 |
From 56018228deac6e704a7ec8befd9e9dc69f2fe73f Mon Sep 17 00:00:00 2001
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5544c1 |
From: Blue Swirl <blauwirbel@gmail.com>
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5544c1 |
Date: Sun, 2 Sep 2012 07:33:35 +0000
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5544c1 |
Subject: [PATCH] target-s390x: rename op_helper.c to misc_helper.c
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5544c1 |
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5544c1 |
Now op_helper.c contains miscellaneous helpers, rename
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5544c1 |
it to misc_helper.c.
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5544c1 |
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5544c1 |
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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5544c1 |
[agraf: fix conflict]
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5544c1 |
Signed-off-by: Alexander Graf <agraf@suse.de>
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5544c1 |
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5544c1 |
Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>
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5544c1 |
---
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5544c1 |
target-s390x/Makefile.objs | 6 +-
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5544c1 |
target-s390x/cpu.h | 2 +-
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5544c1 |
target-s390x/misc_helper.c | 428 +++++++++++++++++++++++++++++++++++++++++++++
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5544c1 |
target-s390x/op_helper.c | 428 ---------------------------------------------
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5544c1 |
4 files changed, 432 insertions(+), 432 deletions(-)
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5544c1 |
create mode 100644 target-s390x/misc_helper.c
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5544c1 |
delete mode 100644 target-s390x/op_helper.c
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5544c1 |
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5544c1 |
diff --git a/target-s390x/Makefile.objs b/target-s390x/Makefile.objs
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5544c1 |
index b9b3061..a87d26f 100644
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5544c1 |
--- a/target-s390x/Makefile.objs
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5544c1 |
+++ b/target-s390x/Makefile.objs
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5544c1 |
@@ -1,10 +1,10 @@
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5544c1 |
-obj-y += translate.o op_helper.o helper.o cpu.o interrupt.o
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5544c1 |
-obj-y += int_helper.o fpu_helper.o cc_helper.o mem_helper.o
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5544c1 |
+obj-y += translate.o helper.o cpu.o interrupt.o
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5544c1 |
+obj-y += int_helper.o fpu_helper.o cc_helper.o mem_helper.o misc_helper.o
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5544c1 |
obj-$(CONFIG_SOFTMMU) += machine.o
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5544c1 |
obj-$(CONFIG_KVM) += kvm.o
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5544c1 |
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5544c1 |
-$(obj)/op_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
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5544c1 |
$(obj)/int_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
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5544c1 |
$(obj)/fpu_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
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5544c1 |
$(obj)/cc_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
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5544c1 |
$(obj)/mem_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
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5544c1 |
+$(obj)/misc_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS)
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5544c1 |
diff --git a/target-s390x/cpu.h b/target-s390x/cpu.h
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5544c1 |
index 97fde5e..0ccb551 100644
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5544c1 |
--- a/target-s390x/cpu.h
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5544c1 |
+++ b/target-s390x/cpu.h
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5544c1 |
@@ -1005,7 +1005,7 @@ uint32_t set_cc_f64(float64 v1, float64 v2);
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5544c1 |
uint32_t set_cc_nz_f32(float32 v);
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5544c1 |
uint32_t set_cc_nz_f64(float64 v);
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5544c1 |
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5544c1 |
-/* op_helper.c */
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5544c1 |
+/* misc_helper.c */
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5544c1 |
void program_interrupt(CPUS390XState *env, uint32_t code, int ilc);
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5544c1 |
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5544c1 |
#endif
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5544c1 |
diff --git a/target-s390x/misc_helper.c b/target-s390x/misc_helper.c
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5544c1 |
new file mode 100644
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5544c1 |
index 0000000..1d5137f
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5544c1 |
--- /dev/null
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5544c1 |
+++ b/target-s390x/misc_helper.c
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5544c1 |
@@ -0,0 +1,428 @@
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5544c1 |
+/*
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5544c1 |
+ * S/390 misc helper routines
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5544c1 |
+ *
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5544c1 |
+ * Copyright (c) 2009 Ulrich Hecht
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5544c1 |
+ * Copyright (c) 2009 Alexander Graf
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5544c1 |
+ *
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5544c1 |
+ * This library is free software; you can redistribute it and/or
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5544c1 |
+ * modify it under the terms of the GNU Lesser General Public
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5544c1 |
+ * License as published by the Free Software Foundation; either
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5544c1 |
+ * version 2 of the License, or (at your option) any later version.
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5544c1 |
+ *
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5544c1 |
+ * This library is distributed in the hope that it will be useful,
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5544c1 |
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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5544c1 |
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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5544c1 |
+ * Lesser General Public License for more details.
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5544c1 |
+ *
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5544c1 |
+ * You should have received a copy of the GNU Lesser General Public
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5544c1 |
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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5544c1 |
+ */
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5544c1 |
+
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5544c1 |
+#include "cpu.h"
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5544c1 |
+#include "memory.h"
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5544c1 |
+#include "cputlb.h"
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5544c1 |
+#include "dyngen-exec.h"
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5544c1 |
+#include "host-utils.h"
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5544c1 |
+#include "helper.h"
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5544c1 |
+#include <string.h>
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5544c1 |
+#include "kvm.h"
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5544c1 |
+#include "qemu-timer.h"
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5544c1 |
+#ifdef CONFIG_KVM
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5544c1 |
+#include <linux/kvm.h>
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5544c1 |
+#endif
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5544c1 |
+
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5544c1 |
+#if !defined(CONFIG_USER_ONLY)
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5544c1 |
+#include "softmmu_exec.h"
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5544c1 |
+#include "sysemu.h"
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5544c1 |
+#endif
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5544c1 |
+
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5544c1 |
+/* #define DEBUG_HELPER */
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5544c1 |
+#ifdef DEBUG_HELPER
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5544c1 |
+#define HELPER_LOG(x...) qemu_log(x)
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5544c1 |
+#else
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5544c1 |
+#define HELPER_LOG(x...)
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5544c1 |
+#endif
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5544c1 |
+
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5544c1 |
+/* raise an exception */
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5544c1 |
+void HELPER(exception)(uint32_t excp)
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5544c1 |
+{
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5544c1 |
+ HELPER_LOG("%s: exception %d\n", __func__, excp);
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5544c1 |
+ env->exception_index = excp;
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5544c1 |
+ cpu_loop_exit(env);
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5544c1 |
+}
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5544c1 |
+
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5544c1 |
+#ifndef CONFIG_USER_ONLY
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5544c1 |
+void program_interrupt(CPUS390XState *env, uint32_t code, int ilc)
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5544c1 |
+{
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5544c1 |
+ qemu_log("program interrupt at %#" PRIx64 "\n", env->psw.addr);
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5544c1 |
+
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5544c1 |
+ if (kvm_enabled()) {
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5544c1 |
+#ifdef CONFIG_KVM
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5544c1 |
+ kvm_s390_interrupt(env, KVM_S390_PROGRAM_INT, code);
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5544c1 |
+#endif
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5544c1 |
+ } else {
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5544c1 |
+ env->int_pgm_code = code;
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5544c1 |
+ env->int_pgm_ilc = ilc;
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5544c1 |
+ env->exception_index = EXCP_PGM;
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5544c1 |
+ cpu_loop_exit(env);
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5544c1 |
+ }
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5544c1 |
+}
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5544c1 |
+
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5544c1 |
+/*
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5544c1 |
+ * ret < 0 indicates program check, ret = 0, 1, 2, 3 -> cc
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5544c1 |
+ */
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5544c1 |
+int sclp_service_call(CPUS390XState *env, uint32_t sccb, uint64_t code)
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5544c1 |
+{
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5544c1 |
+ int r = 0;
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5544c1 |
+ int shift = 0;
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5544c1 |
+
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5544c1 |
+#ifdef DEBUG_HELPER
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5544c1 |
+ printf("sclp(0x%x, 0x%" PRIx64 ")\n", sccb, code);
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5544c1 |
+#endif
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5544c1 |
+
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5544c1 |
+ /* basic checks */
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5544c1 |
+ if (!memory_region_is_ram(phys_page_find(sccb >> TARGET_PAGE_BITS)->mr)) {
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5544c1 |
+ return -PGM_ADDRESSING;
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5544c1 |
+ }
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5544c1 |
+ if (sccb & ~0x7ffffff8ul) {
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5544c1 |
+ return -PGM_SPECIFICATION;
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5544c1 |
+ }
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5544c1 |
+
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5544c1 |
+ switch (code) {
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5544c1 |
+ case SCLP_CMDW_READ_SCP_INFO:
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5544c1 |
+ case SCLP_CMDW_READ_SCP_INFO_FORCED:
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5544c1 |
+ while ((ram_size >> (20 + shift)) > 65535) {
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5544c1 |
+ shift++;
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5544c1 |
+ }
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5544c1 |
+ stw_phys(sccb + SCP_MEM_CODE, ram_size >> (20 + shift));
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5544c1 |
+ stb_phys(sccb + SCP_INCREMENT, 1 << shift);
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5544c1 |
+ stw_phys(sccb + SCP_RESPONSE_CODE, 0x10);
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+
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+ s390_sclp_extint(sccb & ~3);
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5544c1 |
+ break;
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5544c1 |
+ default:
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5544c1 |
+#ifdef DEBUG_HELPER
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5544c1 |
+ printf("KVM: invalid sclp call 0x%x / 0x%" PRIx64 "x\n", sccb, code);
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5544c1 |
+#endif
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+ r = 3;
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+ break;
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+ }
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+
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+ return r;
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+}
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+
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5544c1 |
+/* SCLP service call */
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+uint32_t HELPER(servc)(uint32_t r1, uint64_t r2)
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+{
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5544c1 |
+ int r;
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+
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+ r = sclp_service_call(env, r1, r2);
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+ if (r < 0) {
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+ program_interrupt(env, -r, 4);
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+ return 0;
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+ }
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+ return r;
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5544c1 |
+}
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+
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5544c1 |
+/* DIAG */
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5544c1 |
+uint64_t HELPER(diag)(uint32_t num, uint64_t mem, uint64_t code)
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+{
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5544c1 |
+ uint64_t r;
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+
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5544c1 |
+ switch (num) {
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5544c1 |
+ case 0x500:
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5544c1 |
+ /* KVM hypercall */
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5544c1 |
+ r = s390_virtio_hypercall(env, mem, code);
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+ break;
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5544c1 |
+ case 0x44:
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5544c1 |
+ /* yield */
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+ r = 0;
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+ break;
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5544c1 |
+ case 0x308:
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5544c1 |
+ /* ipl */
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+ r = 0;
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+ break;
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5544c1 |
+ default:
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5544c1 |
+ r = -1;
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5544c1 |
+ break;
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5544c1 |
+ }
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+
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5544c1 |
+ if (r) {
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5544c1 |
+ program_interrupt(env, PGM_OPERATION, ILC_LATER_INC);
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5544c1 |
+ }
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5544c1 |
+
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5544c1 |
+ return r;
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5544c1 |
+}
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5544c1 |
+
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5544c1 |
+/* Store CPU ID */
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5544c1 |
+void HELPER(stidp)(uint64_t a1)
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5544c1 |
+{
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5544c1 |
+ stq(a1, env->cpu_num);
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5544c1 |
+}
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5544c1 |
+
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5544c1 |
+/* Set Prefix */
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5544c1 |
+void HELPER(spx)(uint64_t a1)
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5544c1 |
+{
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5544c1 |
+ uint32_t prefix;
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5544c1 |
+
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5544c1 |
+ prefix = ldl(a1);
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5544c1 |
+ env->psa = prefix & 0xfffff000;
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5544c1 |
+ qemu_log("prefix: %#x\n", prefix);
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5544c1 |
+ tlb_flush_page(env, 0);
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5544c1 |
+ tlb_flush_page(env, TARGET_PAGE_SIZE);
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5544c1 |
+}
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5544c1 |
+
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5544c1 |
+/* Set Clock */
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5544c1 |
+uint32_t HELPER(sck)(uint64_t a1)
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5544c1 |
+{
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5544c1 |
+ /* XXX not implemented - is it necessary? */
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5544c1 |
+
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5544c1 |
+ return 0;
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5544c1 |
+}
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5544c1 |
+
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5544c1 |
+static inline uint64_t clock_value(CPUS390XState *env)
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5544c1 |
+{
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5544c1 |
+ uint64_t time;
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5544c1 |
+
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5544c1 |
+ time = env->tod_offset +
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5544c1 |
+ time2tod(qemu_get_clock_ns(vm_clock) - env->tod_basetime);
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5544c1 |
+
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5544c1 |
+ return time;
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5544c1 |
+}
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5544c1 |
+
|
|
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5544c1 |
+/* Store Clock */
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5544c1 |
+uint32_t HELPER(stck)(uint64_t a1)
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5544c1 |
+{
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5544c1 |
+ stq(a1, clock_value(env));
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5544c1 |
+
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5544c1 |
+ return 0;
|
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5544c1 |
+}
|
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5544c1 |
+
|
|
|
5544c1 |
+/* Store Clock Extended */
|
|
|
5544c1 |
+uint32_t HELPER(stcke)(uint64_t a1)
|
|
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5544c1 |
+{
|
|
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5544c1 |
+ stb(a1, 0);
|
|
|
5544c1 |
+ /* basically the same value as stck */
|
|
|
5544c1 |
+ stq(a1 + 1, clock_value(env) | env->cpu_num);
|
|
|
5544c1 |
+ /* more fine grained than stck */
|
|
|
5544c1 |
+ stq(a1 + 9, 0);
|
|
|
5544c1 |
+ /* XXX programmable fields */
|
|
|
5544c1 |
+ stw(a1 + 17, 0);
|
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|
5544c1 |
+
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5544c1 |
+ return 0;
|
|
|
5544c1 |
+}
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+/* Set Clock Comparator */
|
|
|
5544c1 |
+void HELPER(sckc)(uint64_t a1)
|
|
|
5544c1 |
+{
|
|
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5544c1 |
+ uint64_t time = ldq(a1);
|
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5544c1 |
+
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|
5544c1 |
+ if (time == -1ULL) {
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|
5544c1 |
+ return;
|
|
|
5544c1 |
+ }
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+ /* difference between now and then */
|
|
|
5544c1 |
+ time -= clock_value(env);
|
|
|
5544c1 |
+ /* nanoseconds */
|
|
|
5544c1 |
+ time = (time * 125) >> 9;
|
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|
5544c1 |
+
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|
5544c1 |
+ qemu_mod_timer(env->tod_timer, qemu_get_clock_ns(vm_clock) + time);
|
|
|
5544c1 |
+}
|
|
|
5544c1 |
+
|
|
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5544c1 |
+/* Store Clock Comparator */
|
|
|
5544c1 |
+void HELPER(stckc)(uint64_t a1)
|
|
|
5544c1 |
+{
|
|
|
5544c1 |
+ /* XXX implement */
|
|
|
5544c1 |
+ stq(a1, 0);
|
|
|
5544c1 |
+}
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+/* Set CPU Timer */
|
|
|
5544c1 |
+void HELPER(spt)(uint64_t a1)
|
|
|
5544c1 |
+{
|
|
|
5544c1 |
+ uint64_t time = ldq(a1);
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+ if (time == -1ULL) {
|
|
|
5544c1 |
+ return;
|
|
|
5544c1 |
+ }
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+ /* nanoseconds */
|
|
|
5544c1 |
+ time = (time * 125) >> 9;
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+ qemu_mod_timer(env->cpu_timer, qemu_get_clock_ns(vm_clock) + time);
|
|
|
5544c1 |
+}
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+/* Store CPU Timer */
|
|
|
5544c1 |
+void HELPER(stpt)(uint64_t a1)
|
|
|
5544c1 |
+{
|
|
|
5544c1 |
+ /* XXX implement */
|
|
|
5544c1 |
+ stq(a1, 0);
|
|
|
5544c1 |
+}
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+/* Store System Information */
|
|
|
5544c1 |
+uint32_t HELPER(stsi)(uint64_t a0, uint32_t r0, uint32_t r1)
|
|
|
5544c1 |
+{
|
|
|
5544c1 |
+ int cc = 0;
|
|
|
5544c1 |
+ int sel1, sel2;
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+ if ((r0 & STSI_LEVEL_MASK) <= STSI_LEVEL_3 &&
|
|
|
5544c1 |
+ ((r0 & STSI_R0_RESERVED_MASK) || (r1 & STSI_R1_RESERVED_MASK))) {
|
|
|
5544c1 |
+ /* valid function code, invalid reserved bits */
|
|
|
5544c1 |
+ program_interrupt(env, PGM_SPECIFICATION, 2);
|
|
|
5544c1 |
+ }
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+ sel1 = r0 & STSI_R0_SEL1_MASK;
|
|
|
5544c1 |
+ sel2 = r1 & STSI_R1_SEL2_MASK;
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+ /* XXX: spec exception if sysib is not 4k-aligned */
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+ switch (r0 & STSI_LEVEL_MASK) {
|
|
|
5544c1 |
+ case STSI_LEVEL_1:
|
|
|
5544c1 |
+ if ((sel1 == 1) && (sel2 == 1)) {
|
|
|
5544c1 |
+ /* Basic Machine Configuration */
|
|
|
5544c1 |
+ struct sysib_111 sysib;
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+ memset(&sysib, 0, sizeof(sysib));
|
|
|
5544c1 |
+ ebcdic_put(sysib.manuf, "QEMU ", 16);
|
|
|
5544c1 |
+ /* same as machine type number in STORE CPU ID */
|
|
|
5544c1 |
+ ebcdic_put(sysib.type, "QEMU", 4);
|
|
|
5544c1 |
+ /* same as model number in STORE CPU ID */
|
|
|
5544c1 |
+ ebcdic_put(sysib.model, "QEMU ", 16);
|
|
|
5544c1 |
+ ebcdic_put(sysib.sequence, "QEMU ", 16);
|
|
|
5544c1 |
+ ebcdic_put(sysib.plant, "QEMU", 4);
|
|
|
5544c1 |
+ cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
|
|
|
5544c1 |
+ } else if ((sel1 == 2) && (sel2 == 1)) {
|
|
|
5544c1 |
+ /* Basic Machine CPU */
|
|
|
5544c1 |
+ struct sysib_121 sysib;
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+ memset(&sysib, 0, sizeof(sysib));
|
|
|
5544c1 |
+ /* XXX make different for different CPUs? */
|
|
|
5544c1 |
+ ebcdic_put(sysib.sequence, "QEMUQEMUQEMUQEMU", 16);
|
|
|
5544c1 |
+ ebcdic_put(sysib.plant, "QEMU", 4);
|
|
|
5544c1 |
+ stw_p(&sysib.cpu_addr, env->cpu_num);
|
|
|
5544c1 |
+ cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
|
|
|
5544c1 |
+ } else if ((sel1 == 2) && (sel2 == 2)) {
|
|
|
5544c1 |
+ /* Basic Machine CPUs */
|
|
|
5544c1 |
+ struct sysib_122 sysib;
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+ memset(&sysib, 0, sizeof(sysib));
|
|
|
5544c1 |
+ stl_p(&sysib.capability, 0x443afc29);
|
|
|
5544c1 |
+ /* XXX change when SMP comes */
|
|
|
5544c1 |
+ stw_p(&sysib.total_cpus, 1);
|
|
|
5544c1 |
+ stw_p(&sysib.active_cpus, 1);
|
|
|
5544c1 |
+ stw_p(&sysib.standby_cpus, 0);
|
|
|
5544c1 |
+ stw_p(&sysib.reserved_cpus, 0);
|
|
|
5544c1 |
+ cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
|
|
|
5544c1 |
+ } else {
|
|
|
5544c1 |
+ cc = 3;
|
|
|
5544c1 |
+ }
|
|
|
5544c1 |
+ break;
|
|
|
5544c1 |
+ case STSI_LEVEL_2:
|
|
|
5544c1 |
+ {
|
|
|
5544c1 |
+ if ((sel1 == 2) && (sel2 == 1)) {
|
|
|
5544c1 |
+ /* LPAR CPU */
|
|
|
5544c1 |
+ struct sysib_221 sysib;
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+ memset(&sysib, 0, sizeof(sysib));
|
|
|
5544c1 |
+ /* XXX make different for different CPUs? */
|
|
|
5544c1 |
+ ebcdic_put(sysib.sequence, "QEMUQEMUQEMUQEMU", 16);
|
|
|
5544c1 |
+ ebcdic_put(sysib.plant, "QEMU", 4);
|
|
|
5544c1 |
+ stw_p(&sysib.cpu_addr, env->cpu_num);
|
|
|
5544c1 |
+ stw_p(&sysib.cpu_id, 0);
|
|
|
5544c1 |
+ cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
|
|
|
5544c1 |
+ } else if ((sel1 == 2) && (sel2 == 2)) {
|
|
|
5544c1 |
+ /* LPAR CPUs */
|
|
|
5544c1 |
+ struct sysib_222 sysib;
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+ memset(&sysib, 0, sizeof(sysib));
|
|
|
5544c1 |
+ stw_p(&sysib.lpar_num, 0);
|
|
|
5544c1 |
+ sysib.lcpuc = 0;
|
|
|
5544c1 |
+ /* XXX change when SMP comes */
|
|
|
5544c1 |
+ stw_p(&sysib.total_cpus, 1);
|
|
|
5544c1 |
+ stw_p(&sysib.conf_cpus, 1);
|
|
|
5544c1 |
+ stw_p(&sysib.standby_cpus, 0);
|
|
|
5544c1 |
+ stw_p(&sysib.reserved_cpus, 0);
|
|
|
5544c1 |
+ ebcdic_put(sysib.name, "QEMU ", 8);
|
|
|
5544c1 |
+ stl_p(&sysib.caf, 1000);
|
|
|
5544c1 |
+ stw_p(&sysib.dedicated_cpus, 0);
|
|
|
5544c1 |
+ stw_p(&sysib.shared_cpus, 0);
|
|
|
5544c1 |
+ cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
|
|
|
5544c1 |
+ } else {
|
|
|
5544c1 |
+ cc = 3;
|
|
|
5544c1 |
+ }
|
|
|
5544c1 |
+ break;
|
|
|
5544c1 |
+ }
|
|
|
5544c1 |
+ case STSI_LEVEL_3:
|
|
|
5544c1 |
+ {
|
|
|
5544c1 |
+ if ((sel1 == 2) && (sel2 == 2)) {
|
|
|
5544c1 |
+ /* VM CPUs */
|
|
|
5544c1 |
+ struct sysib_322 sysib;
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+ memset(&sysib, 0, sizeof(sysib));
|
|
|
5544c1 |
+ sysib.count = 1;
|
|
|
5544c1 |
+ /* XXX change when SMP comes */
|
|
|
5544c1 |
+ stw_p(&sysib.vm[0].total_cpus, 1);
|
|
|
5544c1 |
+ stw_p(&sysib.vm[0].conf_cpus, 1);
|
|
|
5544c1 |
+ stw_p(&sysib.vm[0].standby_cpus, 0);
|
|
|
5544c1 |
+ stw_p(&sysib.vm[0].reserved_cpus, 0);
|
|
|
5544c1 |
+ ebcdic_put(sysib.vm[0].name, "KVMguest", 8);
|
|
|
5544c1 |
+ stl_p(&sysib.vm[0].caf, 1000);
|
|
|
5544c1 |
+ ebcdic_put(sysib.vm[0].cpi, "KVM/Linux ", 16);
|
|
|
5544c1 |
+ cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
|
|
|
5544c1 |
+ } else {
|
|
|
5544c1 |
+ cc = 3;
|
|
|
5544c1 |
+ }
|
|
|
5544c1 |
+ break;
|
|
|
5544c1 |
+ }
|
|
|
5544c1 |
+ case STSI_LEVEL_CURRENT:
|
|
|
5544c1 |
+ env->regs[0] = STSI_LEVEL_3;
|
|
|
5544c1 |
+ break;
|
|
|
5544c1 |
+ default:
|
|
|
5544c1 |
+ cc = 3;
|
|
|
5544c1 |
+ break;
|
|
|
5544c1 |
+ }
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+ return cc;
|
|
|
5544c1 |
+}
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+uint32_t HELPER(sigp)(uint64_t order_code, uint32_t r1, uint64_t cpu_addr)
|
|
|
5544c1 |
+{
|
|
|
5544c1 |
+ int cc = 0;
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+ HELPER_LOG("%s: %016" PRIx64 " %08x %016" PRIx64 "\n",
|
|
|
5544c1 |
+ __func__, order_code, r1, cpu_addr);
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+ /* Remember: Use "R1 or R1 + 1, whichever is the odd-numbered register"
|
|
|
5544c1 |
+ as parameter (input). Status (output) is always R1. */
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+ switch (order_code) {
|
|
|
5544c1 |
+ case SIGP_SET_ARCH:
|
|
|
5544c1 |
+ /* switch arch */
|
|
|
5544c1 |
+ break;
|
|
|
5544c1 |
+ case SIGP_SENSE:
|
|
|
5544c1 |
+ /* enumerate CPU status */
|
|
|
5544c1 |
+ if (cpu_addr) {
|
|
|
5544c1 |
+ /* XXX implement when SMP comes */
|
|
|
5544c1 |
+ return 3;
|
|
|
5544c1 |
+ }
|
|
|
5544c1 |
+ env->regs[r1] &= 0xffffffff00000000ULL;
|
|
|
5544c1 |
+ cc = 1;
|
|
|
5544c1 |
+ break;
|
|
|
5544c1 |
+#if !defined(CONFIG_USER_ONLY)
|
|
|
5544c1 |
+ case SIGP_RESTART:
|
|
|
5544c1 |
+ qemu_system_reset_request();
|
|
|
5544c1 |
+ cpu_loop_exit(env);
|
|
|
5544c1 |
+ break;
|
|
|
5544c1 |
+ case SIGP_STOP:
|
|
|
5544c1 |
+ qemu_system_shutdown_request();
|
|
|
5544c1 |
+ cpu_loop_exit(env);
|
|
|
5544c1 |
+ break;
|
|
|
5544c1 |
+#endif
|
|
|
5544c1 |
+ default:
|
|
|
5544c1 |
+ /* unknown sigp */
|
|
|
5544c1 |
+ fprintf(stderr, "XXX unknown sigp: 0x%" PRIx64 "\n", order_code);
|
|
|
5544c1 |
+ cc = 3;
|
|
|
5544c1 |
+ }
|
|
|
5544c1 |
+
|
|
|
5544c1 |
+ return cc;
|
|
|
5544c1 |
+}
|
|
|
5544c1 |
+#endif
|
|
|
5544c1 |
diff --git a/target-s390x/op_helper.c b/target-s390x/op_helper.c
|
|
|
5544c1 |
deleted file mode 100644
|
|
|
5544c1 |
index bb8dbf5..0000000
|
|
|
5544c1 |
--- a/target-s390x/op_helper.c
|
|
|
5544c1 |
+++ /dev/null
|
|
|
5544c1 |
@@ -1,428 +0,0 @@
|
|
|
5544c1 |
-/*
|
|
|
5544c1 |
- * S/390 helper routines
|
|
|
5544c1 |
- *
|
|
|
5544c1 |
- * Copyright (c) 2009 Ulrich Hecht
|
|
|
5544c1 |
- * Copyright (c) 2009 Alexander Graf
|
|
|
5544c1 |
- *
|
|
|
5544c1 |
- * This library is free software; you can redistribute it and/or
|
|
|
5544c1 |
- * modify it under the terms of the GNU Lesser General Public
|
|
|
5544c1 |
- * License as published by the Free Software Foundation; either
|
|
|
5544c1 |
- * version 2 of the License, or (at your option) any later version.
|
|
|
5544c1 |
- *
|
|
|
5544c1 |
- * This library is distributed in the hope that it will be useful,
|
|
|
5544c1 |
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
|
5544c1 |
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
|
|
5544c1 |
- * Lesser General Public License for more details.
|
|
|
5544c1 |
- *
|
|
|
5544c1 |
- * You should have received a copy of the GNU Lesser General Public
|
|
|
5544c1 |
- * License along with this library; if not, see <http://www.gnu.org/licenses/>.
|
|
|
5544c1 |
- */
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-#include "cpu.h"
|
|
|
5544c1 |
-#include "memory.h"
|
|
|
5544c1 |
-#include "cputlb.h"
|
|
|
5544c1 |
-#include "dyngen-exec.h"
|
|
|
5544c1 |
-#include "host-utils.h"
|
|
|
5544c1 |
-#include "helper.h"
|
|
|
5544c1 |
-#include <string.h>
|
|
|
5544c1 |
-#include "kvm.h"
|
|
|
5544c1 |
-#include "qemu-timer.h"
|
|
|
5544c1 |
-#ifdef CONFIG_KVM
|
|
|
5544c1 |
-#include <linux/kvm.h>
|
|
|
5544c1 |
-#endif
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-#if !defined(CONFIG_USER_ONLY)
|
|
|
5544c1 |
-#include "softmmu_exec.h"
|
|
|
5544c1 |
-#include "sysemu.h"
|
|
|
5544c1 |
-#endif
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-/* #define DEBUG_HELPER */
|
|
|
5544c1 |
-#ifdef DEBUG_HELPER
|
|
|
5544c1 |
-#define HELPER_LOG(x...) qemu_log(x)
|
|
|
5544c1 |
-#else
|
|
|
5544c1 |
-#define HELPER_LOG(x...)
|
|
|
5544c1 |
-#endif
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-/* raise an exception */
|
|
|
5544c1 |
-void HELPER(exception)(uint32_t excp)
|
|
|
5544c1 |
-{
|
|
|
5544c1 |
- HELPER_LOG("%s: exception %d\n", __func__, excp);
|
|
|
5544c1 |
- env->exception_index = excp;
|
|
|
5544c1 |
- cpu_loop_exit(env);
|
|
|
5544c1 |
-}
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-#ifndef CONFIG_USER_ONLY
|
|
|
5544c1 |
-void program_interrupt(CPUS390XState *env, uint32_t code, int ilc)
|
|
|
5544c1 |
-{
|
|
|
5544c1 |
- qemu_log("program interrupt at %#" PRIx64 "\n", env->psw.addr);
|
|
|
5544c1 |
-
|
|
|
5544c1 |
- if (kvm_enabled()) {
|
|
|
5544c1 |
-#ifdef CONFIG_KVM
|
|
|
5544c1 |
- kvm_s390_interrupt(env, KVM_S390_PROGRAM_INT, code);
|
|
|
5544c1 |
-#endif
|
|
|
5544c1 |
- } else {
|
|
|
5544c1 |
- env->int_pgm_code = code;
|
|
|
5544c1 |
- env->int_pgm_ilc = ilc;
|
|
|
5544c1 |
- env->exception_index = EXCP_PGM;
|
|
|
5544c1 |
- cpu_loop_exit(env);
|
|
|
5544c1 |
- }
|
|
|
5544c1 |
-}
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-/*
|
|
|
5544c1 |
- * ret < 0 indicates program check, ret = 0, 1, 2, 3 -> cc
|
|
|
5544c1 |
- */
|
|
|
5544c1 |
-int sclp_service_call(CPUS390XState *env, uint32_t sccb, uint64_t code)
|
|
|
5544c1 |
-{
|
|
|
5544c1 |
- int r = 0;
|
|
|
5544c1 |
- int shift = 0;
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-#ifdef DEBUG_HELPER
|
|
|
5544c1 |
- printf("sclp(0x%x, 0x%" PRIx64 ")\n", sccb, code);
|
|
|
5544c1 |
-#endif
|
|
|
5544c1 |
-
|
|
|
5544c1 |
- /* basic checks */
|
|
|
5544c1 |
- if (!memory_region_is_ram(phys_page_find(sccb >> TARGET_PAGE_BITS)->mr)) {
|
|
|
5544c1 |
- return -PGM_ADDRESSING;
|
|
|
5544c1 |
- }
|
|
|
5544c1 |
- if (sccb & ~0x7ffffff8ul) {
|
|
|
5544c1 |
- return -PGM_SPECIFICATION;
|
|
|
5544c1 |
- }
|
|
|
5544c1 |
-
|
|
|
5544c1 |
- switch (code) {
|
|
|
5544c1 |
- case SCLP_CMDW_READ_SCP_INFO:
|
|
|
5544c1 |
- case SCLP_CMDW_READ_SCP_INFO_FORCED:
|
|
|
5544c1 |
- while ((ram_size >> (20 + shift)) > 65535) {
|
|
|
5544c1 |
- shift++;
|
|
|
5544c1 |
- }
|
|
|
5544c1 |
- stw_phys(sccb + SCP_MEM_CODE, ram_size >> (20 + shift));
|
|
|
5544c1 |
- stb_phys(sccb + SCP_INCREMENT, 1 << shift);
|
|
|
5544c1 |
- stw_phys(sccb + SCP_RESPONSE_CODE, 0x10);
|
|
|
5544c1 |
-
|
|
|
5544c1 |
- s390_sclp_extint(sccb & ~3);
|
|
|
5544c1 |
- break;
|
|
|
5544c1 |
- default:
|
|
|
5544c1 |
-#ifdef DEBUG_HELPER
|
|
|
5544c1 |
- printf("KVM: invalid sclp call 0x%x / 0x%" PRIx64 "x\n", sccb, code);
|
|
|
5544c1 |
-#endif
|
|
|
5544c1 |
- r = 3;
|
|
|
5544c1 |
- break;
|
|
|
5544c1 |
- }
|
|
|
5544c1 |
-
|
|
|
5544c1 |
- return r;
|
|
|
5544c1 |
-}
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-/* SCLP service call */
|
|
|
5544c1 |
-uint32_t HELPER(servc)(uint32_t r1, uint64_t r2)
|
|
|
5544c1 |
-{
|
|
|
5544c1 |
- int r;
|
|
|
5544c1 |
-
|
|
|
5544c1 |
- r = sclp_service_call(env, r1, r2);
|
|
|
5544c1 |
- if (r < 0) {
|
|
|
5544c1 |
- program_interrupt(env, -r, 4);
|
|
|
5544c1 |
- return 0;
|
|
|
5544c1 |
- }
|
|
|
5544c1 |
- return r;
|
|
|
5544c1 |
-}
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-/* DIAG */
|
|
|
5544c1 |
-uint64_t HELPER(diag)(uint32_t num, uint64_t mem, uint64_t code)
|
|
|
5544c1 |
-{
|
|
|
5544c1 |
- uint64_t r;
|
|
|
5544c1 |
-
|
|
|
5544c1 |
- switch (num) {
|
|
|
5544c1 |
- case 0x500:
|
|
|
5544c1 |
- /* KVM hypercall */
|
|
|
5544c1 |
- r = s390_virtio_hypercall(env, mem, code);
|
|
|
5544c1 |
- break;
|
|
|
5544c1 |
- case 0x44:
|
|
|
5544c1 |
- /* yield */
|
|
|
5544c1 |
- r = 0;
|
|
|
5544c1 |
- break;
|
|
|
5544c1 |
- case 0x308:
|
|
|
5544c1 |
- /* ipl */
|
|
|
5544c1 |
- r = 0;
|
|
|
5544c1 |
- break;
|
|
|
5544c1 |
- default:
|
|
|
5544c1 |
- r = -1;
|
|
|
5544c1 |
- break;
|
|
|
5544c1 |
- }
|
|
|
5544c1 |
-
|
|
|
5544c1 |
- if (r) {
|
|
|
5544c1 |
- program_interrupt(env, PGM_OPERATION, ILC_LATER_INC);
|
|
|
5544c1 |
- }
|
|
|
5544c1 |
-
|
|
|
5544c1 |
- return r;
|
|
|
5544c1 |
-}
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-/* Store CPU ID */
|
|
|
5544c1 |
-void HELPER(stidp)(uint64_t a1)
|
|
|
5544c1 |
-{
|
|
|
5544c1 |
- stq(a1, env->cpu_num);
|
|
|
5544c1 |
-}
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-/* Set Prefix */
|
|
|
5544c1 |
-void HELPER(spx)(uint64_t a1)
|
|
|
5544c1 |
-{
|
|
|
5544c1 |
- uint32_t prefix;
|
|
|
5544c1 |
-
|
|
|
5544c1 |
- prefix = ldl(a1);
|
|
|
5544c1 |
- env->psa = prefix & 0xfffff000;
|
|
|
5544c1 |
- qemu_log("prefix: %#x\n", prefix);
|
|
|
5544c1 |
- tlb_flush_page(env, 0);
|
|
|
5544c1 |
- tlb_flush_page(env, TARGET_PAGE_SIZE);
|
|
|
5544c1 |
-}
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-/* Set Clock */
|
|
|
5544c1 |
-uint32_t HELPER(sck)(uint64_t a1)
|
|
|
5544c1 |
-{
|
|
|
5544c1 |
- /* XXX not implemented - is it necessary? */
|
|
|
5544c1 |
-
|
|
|
5544c1 |
- return 0;
|
|
|
5544c1 |
-}
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-static inline uint64_t clock_value(CPUS390XState *env)
|
|
|
5544c1 |
-{
|
|
|
5544c1 |
- uint64_t time;
|
|
|
5544c1 |
-
|
|
|
5544c1 |
- time = env->tod_offset +
|
|
|
5544c1 |
- time2tod(qemu_get_clock_ns(vm_clock) - env->tod_basetime);
|
|
|
5544c1 |
-
|
|
|
5544c1 |
- return time;
|
|
|
5544c1 |
-}
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-/* Store Clock */
|
|
|
5544c1 |
-uint32_t HELPER(stck)(uint64_t a1)
|
|
|
5544c1 |
-{
|
|
|
5544c1 |
- stq(a1, clock_value(env));
|
|
|
5544c1 |
-
|
|
|
5544c1 |
- return 0;
|
|
|
5544c1 |
-}
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-/* Store Clock Extended */
|
|
|
5544c1 |
-uint32_t HELPER(stcke)(uint64_t a1)
|
|
|
5544c1 |
-{
|
|
|
5544c1 |
- stb(a1, 0);
|
|
|
5544c1 |
- /* basically the same value as stck */
|
|
|
5544c1 |
- stq(a1 + 1, clock_value(env) | env->cpu_num);
|
|
|
5544c1 |
- /* more fine grained than stck */
|
|
|
5544c1 |
- stq(a1 + 9, 0);
|
|
|
5544c1 |
- /* XXX programmable fields */
|
|
|
5544c1 |
- stw(a1 + 17, 0);
|
|
|
5544c1 |
-
|
|
|
5544c1 |
- return 0;
|
|
|
5544c1 |
-}
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-/* Set Clock Comparator */
|
|
|
5544c1 |
-void HELPER(sckc)(uint64_t a1)
|
|
|
5544c1 |
-{
|
|
|
5544c1 |
- uint64_t time = ldq(a1);
|
|
|
5544c1 |
-
|
|
|
5544c1 |
- if (time == -1ULL) {
|
|
|
5544c1 |
- return;
|
|
|
5544c1 |
- }
|
|
|
5544c1 |
-
|
|
|
5544c1 |
- /* difference between now and then */
|
|
|
5544c1 |
- time -= clock_value(env);
|
|
|
5544c1 |
- /* nanoseconds */
|
|
|
5544c1 |
- time = (time * 125) >> 9;
|
|
|
5544c1 |
-
|
|
|
5544c1 |
- qemu_mod_timer(env->tod_timer, qemu_get_clock_ns(vm_clock) + time);
|
|
|
5544c1 |
-}
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-/* Store Clock Comparator */
|
|
|
5544c1 |
-void HELPER(stckc)(uint64_t a1)
|
|
|
5544c1 |
-{
|
|
|
5544c1 |
- /* XXX implement */
|
|
|
5544c1 |
- stq(a1, 0);
|
|
|
5544c1 |
-}
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-/* Set CPU Timer */
|
|
|
5544c1 |
-void HELPER(spt)(uint64_t a1)
|
|
|
5544c1 |
-{
|
|
|
5544c1 |
- uint64_t time = ldq(a1);
|
|
|
5544c1 |
-
|
|
|
5544c1 |
- if (time == -1ULL) {
|
|
|
5544c1 |
- return;
|
|
|
5544c1 |
- }
|
|
|
5544c1 |
-
|
|
|
5544c1 |
- /* nanoseconds */
|
|
|
5544c1 |
- time = (time * 125) >> 9;
|
|
|
5544c1 |
-
|
|
|
5544c1 |
- qemu_mod_timer(env->cpu_timer, qemu_get_clock_ns(vm_clock) + time);
|
|
|
5544c1 |
-}
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-/* Store CPU Timer */
|
|
|
5544c1 |
-void HELPER(stpt)(uint64_t a1)
|
|
|
5544c1 |
-{
|
|
|
5544c1 |
- /* XXX implement */
|
|
|
5544c1 |
- stq(a1, 0);
|
|
|
5544c1 |
-}
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-/* Store System Information */
|
|
|
5544c1 |
-uint32_t HELPER(stsi)(uint64_t a0, uint32_t r0, uint32_t r1)
|
|
|
5544c1 |
-{
|
|
|
5544c1 |
- int cc = 0;
|
|
|
5544c1 |
- int sel1, sel2;
|
|
|
5544c1 |
-
|
|
|
5544c1 |
- if ((r0 & STSI_LEVEL_MASK) <= STSI_LEVEL_3 &&
|
|
|
5544c1 |
- ((r0 & STSI_R0_RESERVED_MASK) || (r1 & STSI_R1_RESERVED_MASK))) {
|
|
|
5544c1 |
- /* valid function code, invalid reserved bits */
|
|
|
5544c1 |
- program_interrupt(env, PGM_SPECIFICATION, 2);
|
|
|
5544c1 |
- }
|
|
|
5544c1 |
-
|
|
|
5544c1 |
- sel1 = r0 & STSI_R0_SEL1_MASK;
|
|
|
5544c1 |
- sel2 = r1 & STSI_R1_SEL2_MASK;
|
|
|
5544c1 |
-
|
|
|
5544c1 |
- /* XXX: spec exception if sysib is not 4k-aligned */
|
|
|
5544c1 |
-
|
|
|
5544c1 |
- switch (r0 & STSI_LEVEL_MASK) {
|
|
|
5544c1 |
- case STSI_LEVEL_1:
|
|
|
5544c1 |
- if ((sel1 == 1) && (sel2 == 1)) {
|
|
|
5544c1 |
- /* Basic Machine Configuration */
|
|
|
5544c1 |
- struct sysib_111 sysib;
|
|
|
5544c1 |
-
|
|
|
5544c1 |
- memset(&sysib, 0, sizeof(sysib));
|
|
|
5544c1 |
- ebcdic_put(sysib.manuf, "QEMU ", 16);
|
|
|
5544c1 |
- /* same as machine type number in STORE CPU ID */
|
|
|
5544c1 |
- ebcdic_put(sysib.type, "QEMU", 4);
|
|
|
5544c1 |
- /* same as model number in STORE CPU ID */
|
|
|
5544c1 |
- ebcdic_put(sysib.model, "QEMU ", 16);
|
|
|
5544c1 |
- ebcdic_put(sysib.sequence, "QEMU ", 16);
|
|
|
5544c1 |
- ebcdic_put(sysib.plant, "QEMU", 4);
|
|
|
5544c1 |
- cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
|
|
|
5544c1 |
- } else if ((sel1 == 2) && (sel2 == 1)) {
|
|
|
5544c1 |
- /* Basic Machine CPU */
|
|
|
5544c1 |
- struct sysib_121 sysib;
|
|
|
5544c1 |
-
|
|
|
5544c1 |
- memset(&sysib, 0, sizeof(sysib));
|
|
|
5544c1 |
- /* XXX make different for different CPUs? */
|
|
|
5544c1 |
- ebcdic_put(sysib.sequence, "QEMUQEMUQEMUQEMU", 16);
|
|
|
5544c1 |
- ebcdic_put(sysib.plant, "QEMU", 4);
|
|
|
5544c1 |
- stw_p(&sysib.cpu_addr, env->cpu_num);
|
|
|
5544c1 |
- cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
|
|
|
5544c1 |
- } else if ((sel1 == 2) && (sel2 == 2)) {
|
|
|
5544c1 |
- /* Basic Machine CPUs */
|
|
|
5544c1 |
- struct sysib_122 sysib;
|
|
|
5544c1 |
-
|
|
|
5544c1 |
- memset(&sysib, 0, sizeof(sysib));
|
|
|
5544c1 |
- stl_p(&sysib.capability, 0x443afc29);
|
|
|
5544c1 |
- /* XXX change when SMP comes */
|
|
|
5544c1 |
- stw_p(&sysib.total_cpus, 1);
|
|
|
5544c1 |
- stw_p(&sysib.active_cpus, 1);
|
|
|
5544c1 |
- stw_p(&sysib.standby_cpus, 0);
|
|
|
5544c1 |
- stw_p(&sysib.reserved_cpus, 0);
|
|
|
5544c1 |
- cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
|
|
|
5544c1 |
- } else {
|
|
|
5544c1 |
- cc = 3;
|
|
|
5544c1 |
- }
|
|
|
5544c1 |
- break;
|
|
|
5544c1 |
- case STSI_LEVEL_2:
|
|
|
5544c1 |
- {
|
|
|
5544c1 |
- if ((sel1 == 2) && (sel2 == 1)) {
|
|
|
5544c1 |
- /* LPAR CPU */
|
|
|
5544c1 |
- struct sysib_221 sysib;
|
|
|
5544c1 |
-
|
|
|
5544c1 |
- memset(&sysib, 0, sizeof(sysib));
|
|
|
5544c1 |
- /* XXX make different for different CPUs? */
|
|
|
5544c1 |
- ebcdic_put(sysib.sequence, "QEMUQEMUQEMUQEMU", 16);
|
|
|
5544c1 |
- ebcdic_put(sysib.plant, "QEMU", 4);
|
|
|
5544c1 |
- stw_p(&sysib.cpu_addr, env->cpu_num);
|
|
|
5544c1 |
- stw_p(&sysib.cpu_id, 0);
|
|
|
5544c1 |
- cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
|
|
|
5544c1 |
- } else if ((sel1 == 2) && (sel2 == 2)) {
|
|
|
5544c1 |
- /* LPAR CPUs */
|
|
|
5544c1 |
- struct sysib_222 sysib;
|
|
|
5544c1 |
-
|
|
|
5544c1 |
- memset(&sysib, 0, sizeof(sysib));
|
|
|
5544c1 |
- stw_p(&sysib.lpar_num, 0);
|
|
|
5544c1 |
- sysib.lcpuc = 0;
|
|
|
5544c1 |
- /* XXX change when SMP comes */
|
|
|
5544c1 |
- stw_p(&sysib.total_cpus, 1);
|
|
|
5544c1 |
- stw_p(&sysib.conf_cpus, 1);
|
|
|
5544c1 |
- stw_p(&sysib.standby_cpus, 0);
|
|
|
5544c1 |
- stw_p(&sysib.reserved_cpus, 0);
|
|
|
5544c1 |
- ebcdic_put(sysib.name, "QEMU ", 8);
|
|
|
5544c1 |
- stl_p(&sysib.caf, 1000);
|
|
|
5544c1 |
- stw_p(&sysib.dedicated_cpus, 0);
|
|
|
5544c1 |
- stw_p(&sysib.shared_cpus, 0);
|
|
|
5544c1 |
- cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
|
|
|
5544c1 |
- } else {
|
|
|
5544c1 |
- cc = 3;
|
|
|
5544c1 |
- }
|
|
|
5544c1 |
- break;
|
|
|
5544c1 |
- }
|
|
|
5544c1 |
- case STSI_LEVEL_3:
|
|
|
5544c1 |
- {
|
|
|
5544c1 |
- if ((sel1 == 2) && (sel2 == 2)) {
|
|
|
5544c1 |
- /* VM CPUs */
|
|
|
5544c1 |
- struct sysib_322 sysib;
|
|
|
5544c1 |
-
|
|
|
5544c1 |
- memset(&sysib, 0, sizeof(sysib));
|
|
|
5544c1 |
- sysib.count = 1;
|
|
|
5544c1 |
- /* XXX change when SMP comes */
|
|
|
5544c1 |
- stw_p(&sysib.vm[0].total_cpus, 1);
|
|
|
5544c1 |
- stw_p(&sysib.vm[0].conf_cpus, 1);
|
|
|
5544c1 |
- stw_p(&sysib.vm[0].standby_cpus, 0);
|
|
|
5544c1 |
- stw_p(&sysib.vm[0].reserved_cpus, 0);
|
|
|
5544c1 |
- ebcdic_put(sysib.vm[0].name, "KVMguest", 8);
|
|
|
5544c1 |
- stl_p(&sysib.vm[0].caf, 1000);
|
|
|
5544c1 |
- ebcdic_put(sysib.vm[0].cpi, "KVM/Linux ", 16);
|
|
|
5544c1 |
- cpu_physical_memory_rw(a0, (uint8_t *)&sysib, sizeof(sysib), 1);
|
|
|
5544c1 |
- } else {
|
|
|
5544c1 |
- cc = 3;
|
|
|
5544c1 |
- }
|
|
|
5544c1 |
- break;
|
|
|
5544c1 |
- }
|
|
|
5544c1 |
- case STSI_LEVEL_CURRENT:
|
|
|
5544c1 |
- env->regs[0] = STSI_LEVEL_3;
|
|
|
5544c1 |
- break;
|
|
|
5544c1 |
- default:
|
|
|
5544c1 |
- cc = 3;
|
|
|
5544c1 |
- break;
|
|
|
5544c1 |
- }
|
|
|
5544c1 |
-
|
|
|
5544c1 |
- return cc;
|
|
|
5544c1 |
-}
|
|
|
5544c1 |
-
|
|
|
5544c1 |
-uint32_t HELPER(sigp)(uint64_t order_code, uint32_t r1, uint64_t cpu_addr)
|
|
|
5544c1 |
-{
|
|
|
5544c1 |
- int cc = 0;
|
|
|
5544c1 |
-
|
|
|
5544c1 |
- HELPER_LOG("%s: %016" PRIx64 " %08x %016" PRIx64 "\n",
|
|
|
5544c1 |
- __func__, order_code, r1, cpu_addr);
|
|
|
5544c1 |
-
|
|
|
5544c1 |
- /* Remember: Use "R1 or R1 + 1, whichever is the odd-numbered register"
|
|
|
5544c1 |
- as parameter (input). Status (output) is always R1. */
|
|
|
5544c1 |
-
|
|
|
5544c1 |
- switch (order_code) {
|
|
|
5544c1 |
- case SIGP_SET_ARCH:
|
|
|
5544c1 |
- /* switch arch */
|
|
|
5544c1 |
- break;
|
|
|
5544c1 |
- case SIGP_SENSE:
|
|
|
5544c1 |
- /* enumerate CPU status */
|
|
|
5544c1 |
- if (cpu_addr) {
|
|
|
5544c1 |
- /* XXX implement when SMP comes */
|
|
|
5544c1 |
- return 3;
|
|
|
5544c1 |
- }
|
|
|
5544c1 |
- env->regs[r1] &= 0xffffffff00000000ULL;
|
|
|
5544c1 |
- cc = 1;
|
|
|
5544c1 |
- break;
|
|
|
5544c1 |
-#if !defined(CONFIG_USER_ONLY)
|
|
|
5544c1 |
- case SIGP_RESTART:
|
|
|
5544c1 |
- qemu_system_reset_request();
|
|
|
5544c1 |
- cpu_loop_exit(env);
|
|
|
5544c1 |
- break;
|
|
|
5544c1 |
- case SIGP_STOP:
|
|
|
5544c1 |
- qemu_system_shutdown_request();
|
|
|
5544c1 |
- cpu_loop_exit(env);
|
|
|
5544c1 |
- break;
|
|
|
5544c1 |
-#endif
|
|
|
5544c1 |
- default:
|
|
|
5544c1 |
- /* unknown sigp */
|
|
|
5544c1 |
- fprintf(stderr, "XXX unknown sigp: 0x%" PRIx64 "\n", order_code);
|
|
|
5544c1 |
- cc = 3;
|
|
|
5544c1 |
- }
|
|
|
5544c1 |
-
|
|
|
5544c1 |
- return cc;
|
|
|
5544c1 |
-}
|
|
|
5544c1 |
-#endif
|
|
|
5544c1 |
--
|
|
|
5544c1 |
1.7.12.1
|
|
|
5544c1 |
|