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From: Anton Blanchard <anton@ozlabs.org>
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Date: Fri, 24 May 2019 07:53:45 +0100
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Subject: [PATCH] target/ppc: Fix lxvw4x, lxvh8x and lxvb16x
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During the conversion these instructions were incorrectly treated as
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stores. We need to use set_cpu_vsr* and not get_cpu_vsr*.
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Fixes: 8b3b2d75c7c0 ("introduce get_cpu_vsr{l,h}() and set_cpu_vsr{l,h}() helpers for VSR register access")
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Signed-off-by: Anton Blanchard <anton@ozlabs.org>
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Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
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Tested-by: Greg Kurz <groug@kaod.org>
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Reviewed-by: Greg Kurz <groug@kaod.org>
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Message-Id: <20190524065345.25591-1-mark.cave-ayland@ilande.co.uk>
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Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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(cherry picked from commit 2a1224359008e23b051b7b45be4789afa0269f8c)
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---
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target/ppc/translate/vsx-impl.inc.c | 13 +++++++------
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1 file changed, 7 insertions(+), 6 deletions(-)
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diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c
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index 489b2436e4..1df688cc32 100644
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--- a/target/ppc/translate/vsx-impl.inc.c
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+++ b/target/ppc/translate/vsx-impl.inc.c
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@@ -102,8 +102,7 @@ static void gen_lxvw4x(DisasContext *ctx)
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}
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xth = tcg_temp_new_i64();
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xtl = tcg_temp_new_i64();
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- get_cpu_vsrh(xth, xT(ctx->opcode));
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- get_cpu_vsrl(xtl, xT(ctx->opcode));
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+
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gen_set_access_type(ctx, ACCESS_INT);
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EA = tcg_temp_new();
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@@ -126,6 +125,8 @@ static void gen_lxvw4x(DisasContext *ctx)
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tcg_gen_addi_tl(EA, EA, 8);
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tcg_gen_qemu_ld_i64(xtl, EA, ctx->mem_idx, MO_BEQ);
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}
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+ set_cpu_vsrh(xT(ctx->opcode), xth);
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+ set_cpu_vsrl(xT(ctx->opcode), xtl);
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tcg_temp_free(EA);
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tcg_temp_free_i64(xth);
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tcg_temp_free_i64(xtl);
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@@ -185,8 +186,6 @@ static void gen_lxvh8x(DisasContext *ctx)
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}
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xth = tcg_temp_new_i64();
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xtl = tcg_temp_new_i64();
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- get_cpu_vsrh(xth, xT(ctx->opcode));
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- get_cpu_vsrl(xtl, xT(ctx->opcode));
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gen_set_access_type(ctx, ACCESS_INT);
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EA = tcg_temp_new();
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@@ -197,6 +196,8 @@ static void gen_lxvh8x(DisasContext *ctx)
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if (ctx->le_mode) {
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gen_bswap16x8(xth, xtl, xth, xtl);
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}
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+ set_cpu_vsrh(xT(ctx->opcode), xth);
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+ set_cpu_vsrl(xT(ctx->opcode), xtl);
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tcg_temp_free(EA);
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tcg_temp_free_i64(xth);
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tcg_temp_free_i64(xtl);
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@@ -214,14 +215,14 @@ static void gen_lxvb16x(DisasContext *ctx)
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}
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xth = tcg_temp_new_i64();
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xtl = tcg_temp_new_i64();
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- get_cpu_vsrh(xth, xT(ctx->opcode));
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- get_cpu_vsrl(xtl, xT(ctx->opcode));
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gen_set_access_type(ctx, ACCESS_INT);
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EA = tcg_temp_new();
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gen_addr_reg_index(ctx, EA);
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tcg_gen_qemu_ld_i64(xth, EA, ctx->mem_idx, MO_BEQ);
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tcg_gen_addi_tl(EA, EA, 8);
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tcg_gen_qemu_ld_i64(xtl, EA, ctx->mem_idx, MO_BEQ);
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+ set_cpu_vsrh(xT(ctx->opcode), xth);
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+ set_cpu_vsrl(xT(ctx->opcode), xtl);
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tcg_temp_free(EA);
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tcg_temp_free_i64(xth);
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tcg_temp_free_i64(xtl);
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