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From 88f73511fce36aca2043b95476ad5aff95e75e07 Mon Sep 17 00:00:00 2001
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From: Amit Shah <amit.shah@redhat.com>
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Date: Mon, 21 Mar 2011 20:31:45 +0100
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Subject: [PATCH] char: Add a QemuChrHandlers struct to initialise chardev
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handlers
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Instead of passing each handler in the qemu_add_handlers() function,
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create a struct of handlers that can be passed to the function instead.
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Signed-off-by: Amit Shah <amit.shah@redhat.com>
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Signed-off-by: Cole Robinson <crobinso@redhat.com>
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---
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backends/rng-egd.c | 12 +++++++++---
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gdbstub.c | 9 +++++++--
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hw/cadence_uart.c | 9 +++++++--
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hw/ccid-card-passthru.c | 11 +++++++----
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hw/debugcon.c | 2 +-
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hw/escc.c | 9 +++++++--
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hw/etraxfs_ser.c | 13 +++++++++----
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hw/exynos4210_uart.c | 9 +++++++--
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hw/grlib_apbuart.c | 12 +++++++-----
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hw/imx_serial.c | 9 +++++++--
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hw/ipoctal232.c | 9 +++++++--
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hw/ivshmem.c | 28 ++++++++++++++++++++++------
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hw/lm32_juart.c | 8 +++++++-
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hw/lm32_uart.c | 8 +++++++-
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hw/mcf_uart.c | 9 +++++++--
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hw/milkymist-uart.c | 8 +++++++-
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hw/pl011.c | 9 +++++++--
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hw/pxa2xx.c | 13 +++++++++----
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hw/qdev-properties-system.c | 2 +-
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hw/s390x/sclpconsole.c | 9 +++++++--
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hw/serial.c | 11 ++++++++---
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hw/sh_serial.c | 12 +++++++++---
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hw/spapr_vty.c | 8 ++++++--
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hw/strongarm.c | 12 +++++++-----
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hw/usb/dev-serial.c | 11 ++++++++---
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hw/usb/redirect.c | 9 +++++++--
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hw/virtio-console.c | 9 +++++++--
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hw/xen_console.c | 16 +++++++++++-----
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hw/xilinx_uartlite.c | 11 +++++++++--
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include/char/char.h | 13 +++++++++----
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monitor.c | 18 ++++++++++++++----
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net/slirp.c | 8 ++++++--
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qemu-char.c | 32 ++++++++++++++++++++++----------
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qtest.c | 9 ++++++++-
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34 files changed, 280 insertions(+), 97 deletions(-)
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diff --git a/backends/rng-egd.c b/backends/rng-egd.c
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index 5e012e9..b09876a 100644
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--- a/backends/rng-egd.c
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+++ b/backends/rng-egd.c
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@@ -133,6 +133,13 @@ static void rng_egd_cancel_requests(RngBackend *b)
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rng_egd_free_requests(s);
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}
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+static const QemuChrHandlers rng_egd_handlers = {
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+ .fd_can_read = rng_egd_chr_can_read,
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+ .fd_read = rng_egd_chr_read,
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+ .fd_event = NULL,
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+};
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+
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+
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static void rng_egd_opened(RngBackend *b, Error **errp)
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{
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RngEgd *s = RNG_EGD(b);
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@@ -150,8 +157,7 @@ static void rng_egd_opened(RngBackend *b, Error **errp)
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}
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/* FIXME we should resubmit pending requests when the CDS reconnects. */
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- qemu_chr_add_handlers(s->chr, rng_egd_chr_can_read, rng_egd_chr_read,
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- NULL, s);
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+ qemu_chr_add_handlers(s->chr, &rng_egd_handlers, s);
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}
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static void rng_egd_set_chardev(Object *obj, const char *value, Error **errp)
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@@ -190,7 +196,7 @@ static void rng_egd_finalize(Object *obj)
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RngEgd *s = RNG_EGD(obj);
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if (s->chr) {
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- qemu_chr_add_handlers(s->chr, NULL, NULL, NULL, NULL);
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+ qemu_chr_add_handlers(s->chr, NULL, NULL);
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}
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g_free(s->chr_name);
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diff --git a/gdbstub.c b/gdbstub.c
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index 6cd26f1..2da07e9 100644
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--- a/gdbstub.c
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+++ b/gdbstub.c
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@@ -2992,6 +2992,12 @@ static void gdb_sigterm_handler(int signal)
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}
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#endif
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+static const QemuChrHandlers gdb_handlers = {
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+ .fd_can_read = gdb_chr_can_receive,
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+ .fd_read = gdb_chr_receive,
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+ .fd_event = gdb_chr_event,
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+};
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+
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int gdbserver_start(const char *device)
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{
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GDBState *s;
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@@ -3021,8 +3027,7 @@ int gdbserver_start(const char *device)
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if (!chr)
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return -1;
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- qemu_chr_add_handlers(chr, gdb_chr_can_receive, gdb_chr_receive,
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- gdb_chr_event, NULL);
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+ qemu_chr_add_handlers(chr, &gdb_handlers, NULL);
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}
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s = gdbserver_state;
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diff --git a/hw/cadence_uart.c b/hw/cadence_uart.c
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index 5766d38..dd1a7d6 100644
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--- a/hw/cadence_uart.c
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+++ b/hw/cadence_uart.c
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@@ -439,6 +439,12 @@ static void cadence_uart_reset(UartState *s)
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s->rx_wpos = 0;
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}
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+static const QemuChrHandlers cadence_uart_handlers = {
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+ .fd_can_read = uart_can_receive,
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+ .fd_read = uart_receive,
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+ .fd_event = uart_event,
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+};
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+
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static int cadence_uart_init(SysBusDevice *dev)
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{
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UartState *s = FROM_SYSBUS(UartState, dev);
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@@ -460,8 +466,7 @@ static int cadence_uart_init(SysBusDevice *dev)
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cadence_uart_reset(s);
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if (s->chr) {
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- qemu_chr_add_handlers(s->chr, uart_can_receive, uart_receive,
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- uart_event, s);
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+ qemu_chr_add_handlers(s->chr, &cadence_uart_handlers, s);
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}
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return 0;
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diff --git a/hw/ccid-card-passthru.c b/hw/ccid-card-passthru.c
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index 984bd0b..0dde761 100644
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--- a/hw/ccid-card-passthru.c
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+++ b/hw/ccid-card-passthru.c
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@@ -274,6 +274,12 @@ static const uint8_t *passthru_get_atr(CCIDCardState *base, uint32_t *len)
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return card->atr;
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}
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+static const QemuChrHandlers passthru_handlers = {
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+ .fd_can_read = ccid_card_vscard_can_read,
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+ .fd_read = ccid_card_vscard_read,
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+ .fd_event = ccid_card_vscard_event,
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+};
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+
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static int passthru_initfn(CCIDCardState *base)
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{
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PassthruState *card = DO_UPCAST(PassthruState, base, base);
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@@ -282,10 +288,7 @@ static int passthru_initfn(CCIDCardState *base)
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card->vscard_in_hdr = 0;
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if (card->cs) {
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DPRINTF(card, D_INFO, "initing chardev\n");
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- qemu_chr_add_handlers(card->cs,
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- ccid_card_vscard_can_read,
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- ccid_card_vscard_read,
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- ccid_card_vscard_event, card);
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+ qemu_chr_add_handlers(card->cs, &passthru_handlers, card);
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ccid_card_vscard_send_init(card);
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} else {
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error_report("missing chardev");
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diff --git a/hw/debugcon.c b/hw/debugcon.c
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index 81b2bb0..58e1f90 100644
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--- a/hw/debugcon.c
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+++ b/hw/debugcon.c
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@@ -88,7 +88,7 @@ static void debugcon_init_core(DebugconState *s)
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exit(1);
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}
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- qemu_chr_add_handlers(s->chr, NULL, NULL, NULL, s);
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+ qemu_chr_add_handlers(s->chr, NULL, s);
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}
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static int debugcon_isa_initfn(ISADevice *dev)
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diff --git a/hw/escc.c b/hw/escc.c
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index 18c0292..a29784a 100644
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--- a/hw/escc.c
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+++ b/hw/escc.c
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@@ -867,6 +867,12 @@ void slavio_serial_ms_kbd_init(hwaddr base, qemu_irq irq,
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sysbus_mmio_map(s, 0, base);
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}
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+static const QemuChrHandlers serial_handlers = {
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+ .fd_can_read = serial_can_receive,
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+ .fd_read = serial_receive1,
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+ .fd_event = serial_event,
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+};
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+
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static int escc_init1(SysBusDevice *dev)
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{
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SerialState *s = FROM_SYSBUS(SerialState, dev);
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@@ -879,8 +885,7 @@ static int escc_init1(SysBusDevice *dev)
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s->chn[i].chn = 1 - i;
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s->chn[i].clock = s->frequency / 2;
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if (s->chn[i].chr) {
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- qemu_chr_add_handlers(s->chn[i].chr, serial_can_receive,
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- serial_receive1, serial_event, &s->chn[i]);
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+ qemu_chr_add_handlers(s->chn[i].chr, &serial_handlers, &s->chn[i]);
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}
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}
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s->chn[0].otherchn = &s->chn[1];
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diff --git a/hw/etraxfs_ser.c b/hw/etraxfs_ser.c
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index 72c8868..eb93166 100644
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--- a/hw/etraxfs_ser.c
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+++ b/hw/etraxfs_ser.c
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@@ -208,6 +208,12 @@ static void etraxfs_ser_reset(DeviceState *d)
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}
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+static const QemuChrHandlers serial_handlers = {
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+ .fd_can_read = serial_can_receive,
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+ .fd_read = serial_receive,
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+ .fd_event = serial_event,
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+};
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+
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static int etraxfs_ser_init(SysBusDevice *dev)
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{
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struct etrax_serial *s = FROM_SYSBUS(typeof (*s), dev);
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@@ -217,10 +223,9 @@ static int etraxfs_ser_init(SysBusDevice *dev)
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sysbus_init_mmio(dev, &s->mmio);
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s->chr = qemu_char_get_next_serial();
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- if (s->chr)
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- qemu_chr_add_handlers(s->chr,
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- serial_can_receive, serial_receive,
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- serial_event, s);
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+ if (s->chr) {
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+ qemu_chr_add_handlers(s->chr, &serial_handlers, s);
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+ }
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return 0;
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}
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diff --git a/hw/exynos4210_uart.c b/hw/exynos4210_uart.c
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index bdf797a..8419deb 100644
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--- a/hw/exynos4210_uart.c
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+++ b/hw/exynos4210_uart.c
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@@ -625,6 +625,12 @@ DeviceState *exynos4210_uart_create(hwaddr addr,
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return dev;
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}
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+static const QemuChrHandlers exynos4210_handlers = {
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+ .fd_can_read = exynos4210_uart_can_receive,
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+ .fd_read = exynos4210_uart_receive,
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+ .fd_event = exynos4210_uart_event,
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+};
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+
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static int exynos4210_uart_init(SysBusDevice *dev)
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{
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Exynos4210UartState *s = FROM_SYSBUS(Exynos4210UartState, dev);
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96a5f8 |
@@ -636,8 +642,7 @@ static int exynos4210_uart_init(SysBusDevice *dev)
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96a5f8 |
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sysbus_init_irq(dev, &s->irq);
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- qemu_chr_add_handlers(s->chr, exynos4210_uart_can_receive,
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- exynos4210_uart_receive, exynos4210_uart_event, s);
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+ qemu_chr_add_handlers(s->chr, &exynos4210_handlers, s);
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96a5f8 |
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96a5f8 |
return 0;
|
|
|
96a5f8 |
}
|
|
|
96a5f8 |
diff --git a/hw/grlib_apbuart.c b/hw/grlib_apbuart.c
|
|
|
96a5f8 |
index 760bed0..7ede2be 100644
|
|
|
96a5f8 |
--- a/hw/grlib_apbuart.c
|
|
|
96a5f8 |
+++ b/hw/grlib_apbuart.c
|
|
|
96a5f8 |
@@ -222,15 +222,17 @@ static const MemoryRegionOps grlib_apbuart_ops = {
|
|
|
96a5f8 |
.endianness = DEVICE_NATIVE_ENDIAN,
|
|
|
96a5f8 |
};
|
|
|
96a5f8 |
|
|
|
96a5f8 |
+static const QemuChrHandlers grlib_handlers = {
|
|
|
96a5f8 |
+ .fd_can_read = grlib_apbuart_can_receive,
|
|
|
96a5f8 |
+ .fd_read = grlib_apbuart_receive,
|
|
|
96a5f8 |
+ .fd_event = grlib_apbuart_event,
|
|
|
96a5f8 |
+};
|
|
|
96a5f8 |
+
|
|
|
96a5f8 |
static int grlib_apbuart_init(SysBusDevice *dev)
|
|
|
96a5f8 |
{
|
|
|
96a5f8 |
UART *uart = FROM_SYSBUS(typeof(*uart), dev);
|
|
|
96a5f8 |
|
|
|
96a5f8 |
- qemu_chr_add_handlers(uart->chr,
|
|
|
96a5f8 |
- grlib_apbuart_can_receive,
|
|
|
96a5f8 |
- grlib_apbuart_receive,
|
|
|
96a5f8 |
- grlib_apbuart_event,
|
|
|
96a5f8 |
- uart);
|
|
|
96a5f8 |
+ qemu_chr_add_handlers(uart->chr, &grlib_handlers, uart);
|
|
|
96a5f8 |
|
|
|
96a5f8 |
sysbus_init_irq(dev, &uart->irq);
|
|
|
96a5f8 |
|
|
|
96a5f8 |
diff --git a/hw/imx_serial.c b/hw/imx_serial.c
|
|
|
96a5f8 |
index 2d8253e..b0401a1 100644
|
|
|
96a5f8 |
--- a/hw/imx_serial.c
|
|
|
96a5f8 |
+++ b/hw/imx_serial.c
|
|
|
96a5f8 |
@@ -381,6 +381,12 @@ static const struct MemoryRegionOps imx_serial_ops = {
|
|
|
96a5f8 |
.endianness = DEVICE_NATIVE_ENDIAN,
|
|
|
96a5f8 |
};
|
|
|
96a5f8 |
|
|
|
96a5f8 |
+static const QemuChrHandlers imx_handlers = {
|
|
|
96a5f8 |
+ .fd_can_read = imx_can_receive,
|
|
|
96a5f8 |
+ .fd_read = imx_receive,
|
|
|
96a5f8 |
+ .fd_event = imx_event,
|
|
|
96a5f8 |
+};
|
|
|
96a5f8 |
+
|
|
|
96a5f8 |
static int imx_serial_init(SysBusDevice *dev)
|
|
|
96a5f8 |
{
|
|
|
96a5f8 |
IMXSerialState *s = FROM_SYSBUS(IMXSerialState, dev);
|
|
|
96a5f8 |
@@ -391,8 +397,7 @@ static int imx_serial_init(SysBusDevice *dev)
|
|
|
96a5f8 |
sysbus_init_irq(dev, &s->irq);
|
|
|
96a5f8 |
|
|
|
96a5f8 |
if (s->chr) {
|
|
|
96a5f8 |
- qemu_chr_add_handlers(s->chr, imx_can_receive, imx_receive,
|
|
|
96a5f8 |
- imx_event, s);
|
|
|
96a5f8 |
+ qemu_chr_add_handlers(s->chr, &imx_handlers, s);
|
|
|
96a5f8 |
} else {
|
|
|
96a5f8 |
DPRINTF("No char dev for uart at 0x%lx\n",
|
|
|
96a5f8 |
(unsigned long)s->iomem.ram_addr);
|
|
|
96a5f8 |
diff --git a/hw/ipoctal232.c b/hw/ipoctal232.c
|
|
|
96a5f8 |
index c1e3b19..9d1eacf 100644
|
|
|
96a5f8 |
--- a/hw/ipoctal232.c
|
|
|
96a5f8 |
+++ b/hw/ipoctal232.c
|
|
|
96a5f8 |
@@ -535,6 +535,12 @@ static void hostdev_event(void *opaque, int event)
|
|
|
96a5f8 |
}
|
|
|
96a5f8 |
}
|
|
|
96a5f8 |
|
|
|
96a5f8 |
+static const QemuChrHandlers ipoctal_chr_handlers = {
|
|
|
96a5f8 |
+ .fd_can_read = hostdev_can_receive,
|
|
|
96a5f8 |
+ .fd_read = hostdev_receive,
|
|
|
96a5f8 |
+ .fd_event = hostdev_event,
|
|
|
96a5f8 |
+};
|
|
|
96a5f8 |
+
|
|
|
96a5f8 |
static int ipoctal_init(IPackDevice *ip)
|
|
|
96a5f8 |
{
|
|
|
96a5f8 |
IPOctalState *s = IPOCTAL(ip);
|
|
|
96a5f8 |
@@ -556,8 +562,7 @@ static int ipoctal_init(IPackDevice *ip)
|
|
|
96a5f8 |
|
|
|
96a5f8 |
if (ch->dev) {
|
|
|
96a5f8 |
index++;
|
|
|
96a5f8 |
- qemu_chr_add_handlers(ch->dev, hostdev_can_receive,
|
|
|
96a5f8 |
- hostdev_receive, hostdev_event, ch);
|
|
|
96a5f8 |
+ qemu_chr_add_handlers(ch->dev, &ipoctal_chr_handlers, ch);
|
|
|
96a5f8 |
DPRINTF("Redirecting channel %u to %s (%s)\n",
|
|
|
96a5f8 |
i, ch->devpath, label);
|
|
|
96a5f8 |
} else {
|
|
|
96a5f8 |
diff --git a/hw/ivshmem.c b/hw/ivshmem.c
|
|
|
96a5f8 |
index afaf9b3..7577307 100644
|
|
|
96a5f8 |
--- a/hw/ivshmem.c
|
|
|
96a5f8 |
+++ b/hw/ivshmem.c
|
|
|
96a5f8 |
@@ -278,6 +278,18 @@ static void fake_irqfd(void *opaque, const uint8_t *buf, int size) {
|
|
|
96a5f8 |
msix_notify(pdev, entry->vector);
|
|
|
96a5f8 |
}
|
|
|
96a5f8 |
|
|
|
96a5f8 |
+static const QemuChrHandlers ivshmem_handlers = {
|
|
|
96a5f8 |
+ .fd_can_read = ivshmem_can_receive,
|
|
|
96a5f8 |
+ .fd_read = ivshmem_receive,
|
|
|
96a5f8 |
+ .fd_event = ivshmem_event,
|
|
|
96a5f8 |
+};
|
|
|
96a5f8 |
+
|
|
|
96a5f8 |
+static const QemuChrHandlers ivshmem_msi_handlers = {
|
|
|
96a5f8 |
+ .fd_can_read = ivshmem_can_receive,
|
|
|
96a5f8 |
+ .fd_read = fake_irqfd,
|
|
|
96a5f8 |
+ .fd_event = ivshmem_event,
|
|
|
96a5f8 |
+};
|
|
|
96a5f8 |
+
|
|
|
96a5f8 |
static CharDriverState* create_eventfd_chr_device(void * opaque, EventNotifier *n,
|
|
|
96a5f8 |
int vector)
|
|
|
96a5f8 |
{
|
|
|
96a5f8 |
@@ -298,11 +310,10 @@ static CharDriverState* create_eventfd_chr_device(void * opaque, EventNotifier *
|
|
|
96a5f8 |
s->eventfd_table[vector].pdev = &s->dev;
|
|
|
96a5f8 |
s->eventfd_table[vector].vector = vector;
|
|
|
96a5f8 |
|
|
|
96a5f8 |
- qemu_chr_add_handlers(chr, ivshmem_can_receive, fake_irqfd,
|
|
|
96a5f8 |
- ivshmem_event, &s->eventfd_table[vector]);
|
|
|
96a5f8 |
+ qemu_chr_add_handlers(chr, &ivshmem_msi_handlers,
|
|
|
96a5f8 |
+ &s->eventfd_table[vector]);
|
|
|
96a5f8 |
} else {
|
|
|
96a5f8 |
- qemu_chr_add_handlers(chr, ivshmem_can_receive, ivshmem_receive,
|
|
|
96a5f8 |
- ivshmem_event, s);
|
|
|
96a5f8 |
+ qemu_chr_add_handlers(chr, &ivshmem_handlers, s);
|
|
|
96a5f8 |
}
|
|
|
96a5f8 |
|
|
|
96a5f8 |
return chr;
|
|
|
96a5f8 |
@@ -636,6 +647,12 @@ static void ivshmem_write_config(PCIDevice *pci_dev, uint32_t address,
|
|
|
96a5f8 |
msix_write_config(pci_dev, address, val, len);
|
|
|
96a5f8 |
}
|
|
|
96a5f8 |
|
|
|
96a5f8 |
+static const QemuChrHandlers ivshmem_server_handlers = {
|
|
|
96a5f8 |
+ .fd_can_read = ivshmem_can_receive,
|
|
|
96a5f8 |
+ .fd_read = ivshmem_read,
|
|
|
96a5f8 |
+ .fd_event = ivshmem_event,
|
|
|
96a5f8 |
+};
|
|
|
96a5f8 |
+
|
|
|
96a5f8 |
static int pci_ivshmem_init(PCIDevice *dev)
|
|
|
96a5f8 |
{
|
|
|
96a5f8 |
IVShmemState *s = DO_UPCAST(IVShmemState, dev, dev);
|
|
|
96a5f8 |
@@ -726,8 +743,7 @@ static int pci_ivshmem_init(PCIDevice *dev)
|
|
|
96a5f8 |
|
|
|
96a5f8 |
s->eventfd_chr = g_malloc0(s->vectors * sizeof(CharDriverState *));
|
|
|
96a5f8 |
|
|
|
96a5f8 |
- qemu_chr_add_handlers(s->server_chr, ivshmem_can_receive, ivshmem_read,
|
|
|
96a5f8 |
- ivshmem_event, s);
|
|
|
96a5f8 |
+ qemu_chr_add_handlers(s->server_chr, &ivshmem_server_handlers, s);
|
|
|
96a5f8 |
} else {
|
|
|
96a5f8 |
/* just map the file immediately, we're not using a server */
|
|
|
96a5f8 |
int fd;
|
|
|
96a5f8 |
diff --git a/hw/lm32_juart.c b/hw/lm32_juart.c
|
|
|
96a5f8 |
index 8c82c85..840f588 100644
|
|
|
96a5f8 |
--- a/hw/lm32_juart.c
|
|
|
96a5f8 |
+++ b/hw/lm32_juart.c
|
|
|
96a5f8 |
@@ -110,13 +110,19 @@ static void juart_reset(DeviceState *d)
|
|
|
96a5f8 |
s->jrx = 0;
|
|
|
96a5f8 |
}
|
|
|
96a5f8 |
|
|
|
96a5f8 |
+static const QemuChrHandlers juart_handlers = {
|
|
|
96a5f8 |
+ .fd_can_read = juart_can_rx,
|
|
|
96a5f8 |
+ .fd_read = juart_rx,
|
|
|
96a5f8 |
+ .fd_event = juart_event,
|
|
|
96a5f8 |
+};
|
|
|
96a5f8 |
+
|
|
|
96a5f8 |
static int lm32_juart_init(SysBusDevice *dev)
|
|
|
96a5f8 |
{
|
|
|
96a5f8 |
LM32JuartState *s = FROM_SYSBUS(typeof(*s), dev);
|
|
|
96a5f8 |
|
|
|
96a5f8 |
s->chr = qemu_char_get_next_serial();
|
|
|
96a5f8 |
if (s->chr) {
|
|
|
96a5f8 |
- qemu_chr_add_handlers(s->chr, juart_can_rx, juart_rx, juart_event, s);
|
|
|
96a5f8 |
+ qemu_chr_add_handlers(s->chr, &juart_handlers, s);
|
|
|
96a5f8 |
}
|
|
|
96a5f8 |
|
|
|
96a5f8 |
return 0;
|
|
|
96a5f8 |
diff --git a/hw/lm32_uart.c b/hw/lm32_uart.c
|
|
|
96a5f8 |
index 9c89cca..19cfd01 100644
|
|
|
96a5f8 |
--- a/hw/lm32_uart.c
|
|
|
96a5f8 |
+++ b/hw/lm32_uart.c
|
|
|
96a5f8 |
@@ -243,6 +243,12 @@ static void uart_reset(DeviceState *d)
|
|
|
96a5f8 |
s->regs[R_LSR] = LSR_THRE | LSR_TEMT;
|
|
|
96a5f8 |
}
|
|
|
96a5f8 |
|
|
|
96a5f8 |
+static const QemuChrHandlers uart_handlers = {
|
|
|
96a5f8 |
+ .fd_can_read = uart_can_rx,
|
|
|
96a5f8 |
+ .fd_read = uart_rx,
|
|
|
96a5f8 |
+ .fd_event = uart_event,
|
|
|
96a5f8 |
+};
|
|
|
96a5f8 |
+
|
|
|
96a5f8 |
static int lm32_uart_init(SysBusDevice *dev)
|
|
|
96a5f8 |
{
|
|
|
96a5f8 |
LM32UartState *s = FROM_SYSBUS(typeof(*s), dev);
|
|
|
96a5f8 |
@@ -254,7 +260,7 @@ static int lm32_uart_init(SysBusDevice *dev)
|
|
|
96a5f8 |
|
|
|
96a5f8 |
s->chr = qemu_char_get_next_serial();
|
|
|
96a5f8 |
if (s->chr) {
|
|
|
96a5f8 |
- qemu_chr_add_handlers(s->chr, uart_can_rx, uart_rx, uart_event, s);
|
|
|
96a5f8 |
+ qemu_chr_add_handlers(s->chr, &uart_handlers, s);
|
|
|
96a5f8 |
}
|
|
|
96a5f8 |
|
|
|
96a5f8 |
return 0;
|
|
|
96a5f8 |
diff --git a/hw/mcf_uart.c b/hw/mcf_uart.c
|
|
|
96a5f8 |
index c443443..fc491f1 100644
|
|
|
96a5f8 |
--- a/hw/mcf_uart.c
|
|
|
96a5f8 |
+++ b/hw/mcf_uart.c
|
|
|
96a5f8 |
@@ -272,6 +272,12 @@ static void mcf_uart_receive(void *opaque, const uint8_t *buf, int size)
|
|
|
96a5f8 |
mcf_uart_push_byte(s, buf[0]);
|
|
|
96a5f8 |
}
|
|
|
96a5f8 |
|
|
|
96a5f8 |
+static const QemuChrHandlers mcf_uart_handlers = {
|
|
|
96a5f8 |
+ .fd_can_read = mcf_uart_can_receive,
|
|
|
96a5f8 |
+ .fd_read = mcf_uart_receive,
|
|
|
96a5f8 |
+ .fd_event = mcf_uart_event,
|
|
|
96a5f8 |
+};
|
|
|
96a5f8 |
+
|
|
|
96a5f8 |
void *mcf_uart_init(qemu_irq irq, CharDriverState *chr)
|
|
|
96a5f8 |
{
|
|
|
96a5f8 |
mcf_uart_state *s;
|
|
|
96a5f8 |
@@ -280,8 +286,7 @@ void *mcf_uart_init(qemu_irq irq, CharDriverState *chr)
|
|
|
96a5f8 |
s->chr = chr;
|
|
|
96a5f8 |
s->irq = irq;
|
|
|
96a5f8 |
if (chr) {
|
|
|
96a5f8 |
- qemu_chr_add_handlers(chr, mcf_uart_can_receive, mcf_uart_receive,
|
|
|
96a5f8 |
- mcf_uart_event, s);
|
|
|
96a5f8 |
+ qemu_chr_add_handlers(chr, &mcf_uart_handlers, s);
|
|
|
96a5f8 |
}
|
|
|
96a5f8 |
mcf_uart_reset(s);
|
|
|
96a5f8 |
return s;
|
|
|
96a5f8 |
diff --git a/hw/milkymist-uart.c b/hw/milkymist-uart.c
|
|
|
96a5f8 |
index e73eb84..3e03c5c 100644
|
|
|
96a5f8 |
--- a/hw/milkymist-uart.c
|
|
|
96a5f8 |
+++ b/hw/milkymist-uart.c
|
|
|
96a5f8 |
@@ -189,6 +189,12 @@ static void milkymist_uart_reset(DeviceState *d)
|
|
|
96a5f8 |
s->regs[R_STAT] = STAT_THRE;
|
|
|
96a5f8 |
}
|
|
|
96a5f8 |
|
|
|
96a5f8 |
+static const QemuChrHandlers uart_handlers = {
|
|
|
96a5f8 |
+ .fd_can_read = uart_can_rx,
|
|
|
96a5f8 |
+ .fd_read = uart_rx,
|
|
|
96a5f8 |
+ .fd_event = uart_event,
|
|
|
96a5f8 |
+};
|
|
|
96a5f8 |
+
|
|
|
96a5f8 |
static int milkymist_uart_init(SysBusDevice *dev)
|
|
|
96a5f8 |
{
|
|
|
96a5f8 |
MilkymistUartState *s = FROM_SYSBUS(typeof(*s), dev);
|
|
|
96a5f8 |
@@ -201,7 +207,7 @@ static int milkymist_uart_init(SysBusDevice *dev)
|
|
|
96a5f8 |
|
|
|
96a5f8 |
s->chr = qemu_char_get_next_serial();
|
|
|
96a5f8 |
if (s->chr) {
|
|
|
96a5f8 |
- qemu_chr_add_handlers(s->chr, uart_can_rx, uart_rx, uart_event, s);
|
|
|
96a5f8 |
+ qemu_chr_add_handlers(s->chr, &uart_handlers, s);
|
|
|
96a5f8 |
}
|
|
|
96a5f8 |
|
|
|
96a5f8 |
return 0;
|
|
|
96a5f8 |
diff --git a/hw/pl011.c b/hw/pl011.c
|
|
|
96a5f8 |
index 002a50e..3224bc9 100644
|
|
|
96a5f8 |
--- a/hw/pl011.c
|
|
|
96a5f8 |
+++ b/hw/pl011.c
|
|
|
96a5f8 |
@@ -261,6 +261,12 @@ static const VMStateDescription vmstate_pl011 = {
|
|
|
96a5f8 |
}
|
|
|
96a5f8 |
};
|
|
|
96a5f8 |
|
|
|
96a5f8 |
+static const QemuChrHandlers pl011_handlers = {
|
|
|
96a5f8 |
+ .fd_can_read = pl011_can_receive,
|
|
|
96a5f8 |
+ .fd_read = pl011_receive,
|
|
|
96a5f8 |
+ .fd_event = pl011_event,
|
|
|
96a5f8 |
+};
|
|
|
96a5f8 |
+
|
|
|
96a5f8 |
static int pl011_init(SysBusDevice *dev, const unsigned char *id)
|
|
|
96a5f8 |
{
|
|
|
96a5f8 |
pl011_state *s = FROM_SYSBUS(pl011_state, dev);
|
|
|
96a5f8 |
@@ -276,8 +282,7 @@ static int pl011_init(SysBusDevice *dev, const unsigned char *id)
|
|
|
96a5f8 |
s->cr = 0x300;
|
|
|
96a5f8 |
s->flags = 0x90;
|
|
|
96a5f8 |
if (s->chr) {
|
|
|
96a5f8 |
- qemu_chr_add_handlers(s->chr, pl011_can_receive, pl011_receive,
|
|
|
96a5f8 |
- pl011_event, s);
|
|
|
96a5f8 |
+ qemu_chr_add_handlers(s->chr, &pl011_handlers, s);
|
|
|
96a5f8 |
}
|
|
|
96a5f8 |
vmstate_register(&dev->qdev, -1, &vmstate_pl011, s);
|
|
|
96a5f8 |
return 0;
|
|
|
96a5f8 |
diff --git a/hw/pxa2xx.c b/hw/pxa2xx.c
|
|
|
96a5f8 |
index d303320..06f43d5 100644
|
|
|
96a5f8 |
--- a/hw/pxa2xx.c
|
|
|
96a5f8 |
+++ b/hw/pxa2xx.c
|
|
|
96a5f8 |
@@ -1962,6 +1962,12 @@ static int pxa2xx_fir_load(QEMUFile *f, void *opaque, int version_id)
|
|
|
96a5f8 |
return 0;
|
|
|
96a5f8 |
}
|
|
|
96a5f8 |
|
|
|
96a5f8 |
+static const QemuChrHandlers pxa2xx_handlers = {
|
|
|
96a5f8 |
+ .fd_can_read = pxa2xx_fir_is_empty,
|
|
|
96a5f8 |
+ .fd_read = pxa2xx_fir_rx,
|
|
|
96a5f8 |
+ .fd_event = pxa2xx_fir_event,
|
|
|
96a5f8 |
+};
|
|
|
96a5f8 |
+
|
|
|
96a5f8 |
static PXA2xxFIrState *pxa2xx_fir_init(MemoryRegion *sysmem,
|
|
|
96a5f8 |
hwaddr base,
|
|
|
96a5f8 |
qemu_irq irq, qemu_irq rx_dma, qemu_irq tx_dma,
|
|
|
96a5f8 |
@@ -1980,10 +1986,9 @@ static PXA2xxFIrState *pxa2xx_fir_init(MemoryRegion *sysmem,
|
|
|
96a5f8 |
memory_region_init_io(&s->iomem, &pxa2xx_fir_ops, s, "pxa2xx-fir", 0x1000);
|
|
|
96a5f8 |
memory_region_add_subregion(sysmem, base, &s->iomem);
|
|
|
96a5f8 |
|
|
|
96a5f8 |
- if (chr)
|
|
|
96a5f8 |
- qemu_chr_add_handlers(chr, pxa2xx_fir_is_empty,
|
|
|
96a5f8 |
- pxa2xx_fir_rx, pxa2xx_fir_event, s);
|
|
|
96a5f8 |
-
|
|
|
96a5f8 |
+ if (chr) {
|
|
|
96a5f8 |
+ qemu_chr_add_handlers(chr, &pxa2xx_handlers, s);
|
|
|
96a5f8 |
+ }
|
|
|
96a5f8 |
register_savevm(NULL, "pxa2xx_fir", 0, 0, pxa2xx_fir_save,
|
|
|
96a5f8 |
pxa2xx_fir_load, s);
|
|
|
96a5f8 |
|
|
|
96a5f8 |
diff --git a/hw/qdev-properties-system.c b/hw/qdev-properties-system.c
|
|
|
96a5f8 |
index ce3af22..dd37f58 100644
|
|
|
96a5f8 |
--- a/hw/qdev-properties-system.c
|
|
|
96a5f8 |
+++ b/hw/qdev-properties-system.c
|
|
|
96a5f8 |
@@ -138,7 +138,7 @@ static void release_chr(Object *obj, const char *name, void *opaque)
|
|
|
96a5f8 |
CharDriverState **ptr = qdev_get_prop_ptr(dev, prop);
|
|
|
96a5f8 |
|
|
|
96a5f8 |
if (*ptr) {
|
|
|
96a5f8 |
- qemu_chr_add_handlers(*ptr, NULL, NULL, NULL, NULL);
|
|
|
96a5f8 |
+ qemu_chr_add_handlers(*ptr, NULL, NULL);
|
|
|
96a5f8 |
}
|
|
|
96a5f8 |
}
|
|
|
96a5f8 |
|
|
|
96a5f8 |
diff --git a/hw/s390x/sclpconsole.c b/hw/s390x/sclpconsole.c
|
|
|
96a5f8 |
index effe511..7a77d64 100644
|
|
|
96a5f8 |
--- a/hw/s390x/sclpconsole.c
|
|
|
96a5f8 |
+++ b/hw/s390x/sclpconsole.c
|
|
|
96a5f8 |
@@ -238,6 +238,12 @@ static void trigger_ascii_console_data(void *env, int n, int level)
|
|
|
96a5f8 |
sclp_service_interrupt(0);
|
|
|
96a5f8 |
}
|
|
|
96a5f8 |
|
|
|
96a5f8 |
+static const QemuChrHandlers sclp_chr_handlers = {
|
|
|
96a5f8 |
+ .fd_can_read = chr_can_read,
|
|
|
96a5f8 |
+ .fd_read = chr_read,
|
|
|
96a5f8 |
+ .fd_event = chr_event,
|
|
|
96a5f8 |
+};
|
|
|
96a5f8 |
+
|
|
|
96a5f8 |
/* qemu object creation and initialization functions */
|
|
|
96a5f8 |
|
|
|
96a5f8 |
/* tell character layer our call-back functions */
|
|
|
96a5f8 |
@@ -254,8 +260,7 @@ static int console_init(SCLPEvent *event)
|
|
|
96a5f8 |
console_available = true;
|
|
|
96a5f8 |
event->event_type = SCLP_EVENT_ASCII_CONSOLE_DATA;
|
|
|
96a5f8 |
if (scon->chr) {
|
|
|
96a5f8 |
- qemu_chr_add_handlers(scon->chr, chr_can_read,
|
|
|
96a5f8 |
- chr_read, chr_event, scon);
|
|
|
96a5f8 |
+ qemu_chr_add_handlers(scon->chr, &sclp_chr_handlers, scon);
|
|
|
96a5f8 |
}
|
|
|
96a5f8 |
scon->irq_read_vt220 = *qemu_allocate_irqs(trigger_ascii_console_data,
|
|
|
96a5f8 |
NULL, 1);
|
|
|
96a5f8 |
diff --git a/hw/serial.c b/hw/serial.c
|
|
|
96a5f8 |
index f0ce9b0..589c18a 100644
|
|
|
96a5f8 |
--- a/hw/serial.c
|
|
|
96a5f8 |
+++ b/hw/serial.c
|
|
|
96a5f8 |
@@ -674,6 +674,12 @@ static void serial_reset(void *opaque)
|
|
|
96a5f8 |
qemu_irq_lower(s->irq);
|
|
|
96a5f8 |
}
|
|
|
96a5f8 |
|
|
|
96a5f8 |
+static const QemuChrHandlers serial_handlers = {
|
|
|
96a5f8 |
+ .fd_can_read = serial_can_receive1,
|
|
|
96a5f8 |
+ .fd_read = serial_receive1,
|
|
|
96a5f8 |
+ .fd_event = serial_event,
|
|
|
96a5f8 |
+};
|
|
|
96a5f8 |
+
|
|
|
96a5f8 |
void serial_init_core(SerialState *s)
|
|
|
96a5f8 |
{
|
|
|
96a5f8 |
if (!s->chr) {
|
|
|
96a5f8 |
@@ -688,13 +694,12 @@ void serial_init_core(SerialState *s)
|
|
|
96a5f8 |
|
|
|
96a5f8 |
qemu_register_reset(serial_reset, s);
|
|
|
96a5f8 |
|
|
|
96a5f8 |
- qemu_chr_add_handlers(s->chr, serial_can_receive1, serial_receive1,
|
|
|
96a5f8 |
- serial_event, s);
|
|
|
96a5f8 |
+ qemu_chr_add_handlers(s->chr, &serial_handlers, s);
|
|
|
96a5f8 |
}
|
|
|
96a5f8 |
|
|
|
96a5f8 |
void serial_exit_core(SerialState *s)
|
|
|
96a5f8 |
{
|
|
|
96a5f8 |
- qemu_chr_add_handlers(s->chr, NULL, NULL, NULL, NULL);
|
|
|
96a5f8 |
+ qemu_chr_add_handlers(s->chr, NULL, NULL);
|
|
|
96a5f8 |
qemu_unregister_reset(serial_reset, s);
|
|
|
96a5f8 |
}
|
|
|
96a5f8 |
|
|
|
96a5f8 |
diff --git a/hw/sh_serial.c b/hw/sh_serial.c
|
|
|
96a5f8 |
index 21c5b13..1cae7e9 100644
|
|
|
96a5f8 |
--- a/hw/sh_serial.c
|
|
|
96a5f8 |
+++ b/hw/sh_serial.c
|
|
|
96a5f8 |
@@ -352,6 +352,12 @@ static const MemoryRegionOps sh_serial_ops = {
|
|
|
96a5f8 |
.endianness = DEVICE_NATIVE_ENDIAN,
|
|
|
96a5f8 |
};
|
|
|
96a5f8 |
|
|
|
96a5f8 |
+static const QemuChrHandlers sh_serial_handlers = {
|
|
|
96a5f8 |
+ .fd_can_read = sh_serial_can_receive1,
|
|
|
96a5f8 |
+ .fd_read = sh_serial_receive1,
|
|
|
96a5f8 |
+ .fd_event = sh_serial_event,
|
|
|
96a5f8 |
+};
|
|
|
96a5f8 |
+
|
|
|
96a5f8 |
void sh_serial_init(MemoryRegion *sysmem,
|
|
|
96a5f8 |
hwaddr base, int feat,
|
|
|
96a5f8 |
uint32_t freq, CharDriverState *chr,
|
|
|
96a5f8 |
@@ -396,9 +402,9 @@ void sh_serial_init(MemoryRegion *sysmem,
|
|
|
96a5f8 |
|
|
|
96a5f8 |
s->chr = chr;
|
|
|
96a5f8 |
|
|
|
96a5f8 |
- if (chr)
|
|
|
96a5f8 |
- qemu_chr_add_handlers(chr, sh_serial_can_receive1, sh_serial_receive1,
|
|
|
96a5f8 |
- sh_serial_event, s);
|
|
|
96a5f8 |
+ if (chr) {
|
|
|
96a5f8 |
+ qemu_chr_add_handlers(chr, &sh_serial_handlers, s);
|
|
|
96a5f8 |
+ }
|
|
|
96a5f8 |
|
|
|
96a5f8 |
s->eri = eri_source;
|
|
|
96a5f8 |
s->rxi = rxi_source;
|
|
|
96a5f8 |
diff --git a/hw/spapr_vty.c b/hw/spapr_vty.c
|
|
|
96a5f8 |
index 5c63eaa..af2173a 100644
|
|
|
96a5f8 |
--- a/hw/spapr_vty.c
|
|
|
96a5f8 |
+++ b/hw/spapr_vty.c
|
|
|
96a5f8 |
@@ -54,6 +54,11 @@ void vty_putchars(VIOsPAPRDevice *sdev, uint8_t *buf, int len)
|
|
|
96a5f8 |
qemu_chr_fe_write(dev->chardev, buf, len);
|
|
|
96a5f8 |
}
|
|
|
96a5f8 |
|
|
|
96a5f8 |
+static const QemuChrHandlers vty_handlers = {
|
|
|
96a5f8 |
+ .fd_can_read = vty_can_receive,
|
|
|
96a5f8 |
+ .fd_read = vty_receive,
|
|
|
96a5f8 |
+};
|
|
|
96a5f8 |
+
|
|
|
96a5f8 |
static int spapr_vty_init(VIOsPAPRDevice *sdev)
|
|
|
96a5f8 |
{
|
|
|
96a5f8 |
VIOsPAPRVTYDevice *dev = (VIOsPAPRVTYDevice *)sdev;
|
|
|
96a5f8 |
@@ -63,8 +68,7 @@ static int spapr_vty_init(VIOsPAPRDevice *sdev)
|
|
|
96a5f8 |
exit(1);
|
|
|
96a5f8 |
}
|
|
|
96a5f8 |
|
|
|
96a5f8 |
- qemu_chr_add_handlers(dev->chardev, vty_can_receive,
|
|
|
96a5f8 |
- vty_receive, NULL, dev);
|
|
|
96a5f8 |
+ qemu_chr_add_handlers(dev->chardev, &vty_handlers, dev);
|
|
|
96a5f8 |
|
|
|
96a5f8 |
return 0;
|
|
|
96a5f8 |
}
|
|
|
96a5f8 |
diff --git a/hw/strongarm.c b/hw/strongarm.c
|
|
|
96a5f8 |
index ab736e3..9099a06 100644
|
|
|
96a5f8 |
--- a/hw/strongarm.c
|
|
|
96a5f8 |
+++ b/hw/strongarm.c
|
|
|
96a5f8 |
@@ -1200,6 +1200,12 @@ static const MemoryRegionOps strongarm_uart_ops = {
|
|
|
96a5f8 |
.endianness = DEVICE_NATIVE_ENDIAN,
|
|
|
96a5f8 |
};
|
|
|
96a5f8 |
|
|
|
96a5f8 |
+static const QemuChrHandlers strongarm_uart_handlers = {
|
|
|
96a5f8 |
+ .fd_can_read = strongarm_uart_can_receive,
|
|
|
96a5f8 |
+ .fd_read = strongarm_uart_receive,
|
|
|
96a5f8 |
+ .fd_event = strongarm_uart_event,
|
|
|
96a5f8 |
+};
|
|
|
96a5f8 |
+
|
|
|
96a5f8 |
static int strongarm_uart_init(SysBusDevice *dev)
|
|
|
96a5f8 |
{
|
|
|
96a5f8 |
StrongARMUARTState *s = FROM_SYSBUS(StrongARMUARTState, dev);
|
|
|
96a5f8 |
@@ -1212,11 +1218,7 @@ static int strongarm_uart_init(SysBusDevice *dev)
|
|
|
96a5f8 |
s->tx_timer = qemu_new_timer_ns(vm_clock, strongarm_uart_tx, s);
|
|
|
96a5f8 |
|
|
|
96a5f8 |
if (s->chr) {
|
|
|
96a5f8 |
- qemu_chr_add_handlers(s->chr,
|
|
|
96a5f8 |
- strongarm_uart_can_receive,
|
|
|
96a5f8 |
- strongarm_uart_receive,
|
|
|
96a5f8 |
- strongarm_uart_event,
|
|
|
96a5f8 |
- s);
|
|
|
96a5f8 |
+ qemu_chr_add_handlers(s->chr, &strongarm_uart_handlers, s);
|
|
|
96a5f8 |
}
|
|
|
96a5f8 |
|
|
|
96a5f8 |
return 0;
|
|
|
96a5f8 |
diff --git a/hw/usb/dev-serial.c b/hw/usb/dev-serial.c
|
|
|
96a5f8 |
index 47ac8c9..2f8757f 100644
|
|
|
96a5f8 |
--- a/hw/usb/dev-serial.c
|
|
|
96a5f8 |
+++ b/hw/usb/dev-serial.c
|
|
|
96a5f8 |
@@ -414,7 +414,7 @@ static void usb_serial_handle_destroy(USBDevice *dev)
|
|
|
96a5f8 |
{
|
|
|
96a5f8 |
USBSerialState *s = (USBSerialState *)dev;
|
|
|
96a5f8 |
|
|
|
96a5f8 |
- qemu_chr_add_handlers(s->cs, NULL, NULL, NULL, NULL);
|
|
|
96a5f8 |
+ qemu_chr_add_handlers(s->cs, NULL, NULL);
|
|
|
96a5f8 |
}
|
|
|
96a5f8 |
|
|
|
96a5f8 |
static int usb_serial_can_read(void *opaque)
|
|
|
96a5f8 |
@@ -478,6 +478,12 @@ static void usb_serial_event(void *opaque, int event)
|
|
|
96a5f8 |
}
|
|
|
96a5f8 |
}
|
|
|
96a5f8 |
|
|
|
96a5f8 |
+static const QemuChrHandlers usb_serial_handlers = {
|
|
|
96a5f8 |
+ .fd_can_read = usb_serial_can_read,
|
|
|
96a5f8 |
+ .fd_read = usb_serial_read,
|
|
|
96a5f8 |
+ .fd_event = usb_serial_event,
|
|
|
96a5f8 |
+};
|
|
|
96a5f8 |
+
|
|
|
96a5f8 |
static int usb_serial_initfn(USBDevice *dev)
|
|
|
96a5f8 |
{
|
|
|
96a5f8 |
USBSerialState *s = DO_UPCAST(USBSerialState, dev, dev);
|
|
|
96a5f8 |
@@ -491,8 +497,7 @@ static int usb_serial_initfn(USBDevice *dev)
|
|
|
96a5f8 |
return -1;
|
|
|
96a5f8 |
}
|
|
|
96a5f8 |
|
|
|
96a5f8 |
- qemu_chr_add_handlers(s->cs, usb_serial_can_read, usb_serial_read,
|
|
|
96a5f8 |
- usb_serial_event, s);
|
|
|
96a5f8 |
+ qemu_chr_add_handlers(s->cs, &usb_serial_handlers, s);
|
|
|
96a5f8 |
usb_serial_handle_reset(dev);
|
|
|
96a5f8 |
|
|
|
96a5f8 |
if (s->cs->opened && !dev->attached) {
|
|
|
96a5f8 |
diff --git a/hw/usb/redirect.c b/hw/usb/redirect.c
|
|
|
96a5f8 |
index 8c0ead0..bb07c62 100644
|
|
|
96a5f8 |
--- a/hw/usb/redirect.c
|
|
|
96a5f8 |
+++ b/hw/usb/redirect.c
|
|
|
96a5f8 |
@@ -1227,6 +1227,12 @@ static void usbredir_chardev_event(void *opaque, int event)
|
|
|
96a5f8 |
}
|
|
|
96a5f8 |
}
|
|
|
96a5f8 |
|
|
|
96a5f8 |
+static const QemuChrHandlers usbredir_chr_handlers = {
|
|
|
96a5f8 |
+ .fd_can_read = usbredir_chardev_can_read,
|
|
|
96a5f8 |
+ .fd_read = usbredir_chardev_read,
|
|
|
96a5f8 |
+ .fd_event = usbredir_chardev_event,
|
|
|
96a5f8 |
+};
|
|
|
96a5f8 |
+
|
|
|
96a5f8 |
/*
|
|
|
96a5f8 |
* init + destroy
|
|
|
96a5f8 |
*/
|
|
|
96a5f8 |
@@ -1288,8 +1294,7 @@ static int usbredir_initfn(USBDevice *udev)
|
|
|
96a5f8 |
|
|
|
96a5f8 |
/* Let the backend know we are ready */
|
|
|
96a5f8 |
qemu_chr_fe_open(dev->cs);
|
|
|
96a5f8 |
- qemu_chr_add_handlers(dev->cs, usbredir_chardev_can_read,
|
|
|
96a5f8 |
- usbredir_chardev_read, usbredir_chardev_event, dev);
|
|
|
96a5f8 |
+ qemu_chr_add_handlers(dev->cs, &usbredir_chr_handlers, dev);
|
|
|
96a5f8 |
|
|
|
96a5f8 |
qemu_add_vm_change_state_handler(usbredir_vm_state_change, dev);
|
|
|
96a5f8 |
add_boot_device_path(dev->bootindex, &udev->qdev, NULL);
|
|
|
96a5f8 |
diff --git a/hw/virtio-console.c b/hw/virtio-console.c
|
|
|
96a5f8 |
index 46072a0..dd6f614 100644
|
|
|
96a5f8 |
--- a/hw/virtio-console.c
|
|
|
96a5f8 |
+++ b/hw/virtio-console.c
|
|
|
96a5f8 |
@@ -106,6 +106,12 @@ static void chr_event(void *opaque, int event)
|
|
|
96a5f8 |
}
|
|
|
96a5f8 |
}
|
|
|
96a5f8 |
|
|
|
96a5f8 |
+static const QemuChrHandlers chr_handlers = {
|
|
|
96a5f8 |
+ .fd_can_read = chr_can_read,
|
|
|
96a5f8 |
+ .fd_read = chr_read,
|
|
|
96a5f8 |
+ .fd_event = chr_event,
|
|
|
96a5f8 |
+};
|
|
|
96a5f8 |
+
|
|
|
96a5f8 |
static int virtconsole_initfn(VirtIOSerialPort *port)
|
|
|
96a5f8 |
{
|
|
|
96a5f8 |
VirtConsole *vcon = DO_UPCAST(VirtConsole, port, port);
|
|
|
96a5f8 |
@@ -117,8 +123,7 @@ static int virtconsole_initfn(VirtIOSerialPort *port)
|
|
|
96a5f8 |
}
|
|
|
96a5f8 |
|
|
|
96a5f8 |
if (vcon->chr) {
|
|
|
96a5f8 |
- qemu_chr_add_handlers(vcon->chr, chr_can_read, chr_read, chr_event,
|
|
|
96a5f8 |
- vcon);
|
|
|
96a5f8 |
+ qemu_chr_add_handlers(vcon->chr, &chr_handlers, vcon);
|
|
|
96a5f8 |
}
|
|
|
96a5f8 |
|
|
|
96a5f8 |
return 0;
|
|
|
96a5f8 |
diff --git a/hw/xen_console.c b/hw/xen_console.c
|
|
|
96a5f8 |
index 44141f8..db1eea5 100644
|
|
|
96a5f8 |
--- a/hw/xen_console.c
|
|
|
96a5f8 |
+++ b/hw/xen_console.c
|
|
|
96a5f8 |
@@ -215,6 +215,11 @@ out:
|
|
|
96a5f8 |
return ret;
|
|
|
96a5f8 |
}
|
|
|
96a5f8 |
|
|
|
96a5f8 |
+static const QemuChrHandlers xencons_handlers = {
|
|
|
96a5f8 |
+ .fd_can_read = xencons_can_receive,
|
|
|
96a5f8 |
+ .fd_read = xencons_receive,
|
|
|
96a5f8 |
+};
|
|
|
96a5f8 |
+
|
|
|
96a5f8 |
static int con_initialise(struct XenDevice *xendev)
|
|
|
96a5f8 |
{
|
|
|
96a5f8 |
struct XenConsole *con = container_of(xendev, struct XenConsole, xendev);
|
|
|
96a5f8 |
@@ -241,9 +246,9 @@ static int con_initialise(struct XenDevice *xendev)
|
|
|
96a5f8 |
return -1;
|
|
|
96a5f8 |
|
|
|
96a5f8 |
xen_be_bind_evtchn(&con->xendev);
|
|
|
96a5f8 |
- if (con->chr)
|
|
|
96a5f8 |
- qemu_chr_add_handlers(con->chr, xencons_can_receive, xencons_receive,
|
|
|
96a5f8 |
- NULL, con);
|
|
|
96a5f8 |
+ if (con->chr) {
|
|
|
96a5f8 |
+ qemu_chr_add_handlers(con->chr, &xencons_handlers, con);
|
|
|
96a5f8 |
+ }
|
|
|
96a5f8 |
|
|
|
96a5f8 |
xen_be_printf(xendev, 1, "ring mfn %d, remote port %d, local port %d, limit %zd\n",
|
|
|
96a5f8 |
con->ring_ref,
|
|
|
96a5f8 |
@@ -260,8 +265,9 @@ static void con_disconnect(struct XenDevice *xendev)
|
|
|
96a5f8 |
if (!xendev->dev) {
|
|
|
96a5f8 |
return;
|
|
|
96a5f8 |
}
|
|
|
96a5f8 |
- if (con->chr)
|
|
|
96a5f8 |
- qemu_chr_add_handlers(con->chr, NULL, NULL, NULL, NULL);
|
|
|
96a5f8 |
+ if (con->chr) {
|
|
|
96a5f8 |
+ qemu_chr_add_handlers(con->chr, NULL, NULL);
|
|
|
96a5f8 |
+ }
|
|
|
96a5f8 |
xen_be_unbind_evtchn(&con->xendev);
|
|
|
96a5f8 |
|
|
|
96a5f8 |
if (con->sring) {
|
|
|
96a5f8 |
diff --git a/hw/xilinx_uartlite.c b/hw/xilinx_uartlite.c
|
|
|
96a5f8 |
index 9963982..f5e4cde 100644
|
|
|
96a5f8 |
--- a/hw/xilinx_uartlite.c
|
|
|
96a5f8 |
+++ b/hw/xilinx_uartlite.c
|
|
|
96a5f8 |
@@ -192,6 +192,12 @@ static void uart_event(void *opaque, int event)
|
|
|
96a5f8 |
|
|
|
96a5f8 |
}
|
|
|
96a5f8 |
|
|
|
96a5f8 |
+static const QemuChrHandlers uart_handlers = {
|
|
|
96a5f8 |
+ .fd_can_read = uart_can_rx,
|
|
|
96a5f8 |
+ .fd_read = uart_rx,
|
|
|
96a5f8 |
+ .fd_event = uart_event,
|
|
|
96a5f8 |
+};
|
|
|
96a5f8 |
+
|
|
|
96a5f8 |
static int xilinx_uartlite_init(SysBusDevice *dev)
|
|
|
96a5f8 |
{
|
|
|
96a5f8 |
struct xlx_uartlite *s = FROM_SYSBUS(typeof (*s), dev);
|
|
|
96a5f8 |
@@ -204,8 +210,9 @@ static int xilinx_uartlite_init(SysBusDevice *dev)
|
|
|
96a5f8 |
sysbus_init_mmio(dev, &s->mmio);
|
|
|
96a5f8 |
|
|
|
96a5f8 |
s->chr = qemu_char_get_next_serial();
|
|
|
96a5f8 |
- if (s->chr)
|
|
|
96a5f8 |
- qemu_chr_add_handlers(s->chr, uart_can_rx, uart_rx, uart_event, s);
|
|
|
96a5f8 |
+ if (s->chr) {
|
|
|
96a5f8 |
+ qemu_chr_add_handlers(s->chr, &uart_handlers, s);
|
|
|
96a5f8 |
+ }
|
|
|
96a5f8 |
return 0;
|
|
|
96a5f8 |
}
|
|
|
96a5f8 |
|
|
|
96a5f8 |
diff --git a/include/char/char.h b/include/char/char.h
|
|
|
96a5f8 |
index c91ce3c..3027cc1 100644
|
|
|
96a5f8 |
--- a/include/char/char.h
|
|
|
96a5f8 |
+++ b/include/char/char.h
|
|
|
96a5f8 |
@@ -225,10 +225,15 @@ void qemu_chr_be_write(CharDriverState *s, uint8_t *buf, int len);
|
|
|
96a5f8 |
*/
|
|
|
96a5f8 |
void qemu_chr_be_event(CharDriverState *s, int event);
|
|
|
96a5f8 |
|
|
|
96a5f8 |
-void qemu_chr_add_handlers(CharDriverState *s,
|
|
|
96a5f8 |
- IOCanReadHandler *fd_can_read,
|
|
|
96a5f8 |
- IOReadHandler *fd_read,
|
|
|
96a5f8 |
- IOEventHandler *fd_event,
|
|
|
96a5f8 |
+
|
|
|
96a5f8 |
+typedef struct QemuChrHandlers {
|
|
|
96a5f8 |
+ IOCanReadHandler *fd_can_read;
|
|
|
96a5f8 |
+ IOReadHandler *fd_read;
|
|
|
96a5f8 |
+ IOHandler *fd_write_unblocked;
|
|
|
96a5f8 |
+ IOEventHandler *fd_event;
|
|
|
96a5f8 |
+} QemuChrHandlers;
|
|
|
96a5f8 |
+
|
|
|
96a5f8 |
+void qemu_chr_add_handlers(CharDriverState *s, const QemuChrHandlers *handlers,
|
|
|
96a5f8 |
void *opaque);
|
|
|
96a5f8 |
|
|
|
96a5f8 |
void qemu_chr_generic_open(CharDriverState *s);
|
|
|
96a5f8 |
diff --git a/monitor.c b/monitor.c
|
|
|
96a5f8 |
index 20bd19b..be83dd6 100644
|
|
|
96a5f8 |
--- a/monitor.c
|
|
|
96a5f8 |
+++ b/monitor.c
|
|
|
96a5f8 |
@@ -4701,6 +4701,18 @@ static void sortcmdlist(void)
|
|
|
96a5f8 |
* End:
|
|
|
96a5f8 |
*/
|
|
|
96a5f8 |
|
|
|
96a5f8 |
+static const QemuChrHandlers monitor_handlers = {
|
|
|
96a5f8 |
+ .fd_can_read = monitor_can_read,
|
|
|
96a5f8 |
+ .fd_read = monitor_read,
|
|
|
96a5f8 |
+ .fd_event = monitor_event,
|
|
|
96a5f8 |
+};
|
|
|
96a5f8 |
+
|
|
|
96a5f8 |
+static const QemuChrHandlers monitor_control_handlers = {
|
|
|
96a5f8 |
+ .fd_can_read = monitor_can_read,
|
|
|
96a5f8 |
+ .fd_read = monitor_control_read,
|
|
|
96a5f8 |
+ .fd_event = monitor_control_event,
|
|
|
96a5f8 |
+};
|
|
|
96a5f8 |
+
|
|
|
96a5f8 |
void monitor_init(CharDriverState *chr, int flags)
|
|
|
96a5f8 |
{
|
|
|
96a5f8 |
static int is_first_init = 1;
|
|
|
96a5f8 |
@@ -4723,14 +4735,12 @@ void monitor_init(CharDriverState *chr, int flags)
|
|
|
96a5f8 |
if (monitor_ctrl_mode(mon)) {
|
|
|
96a5f8 |
mon->mc = g_malloc0(sizeof(MonitorControl));
|
|
|
96a5f8 |
/* Control mode requires special handlers */
|
|
|
96a5f8 |
- qemu_chr_add_handlers(chr, monitor_can_read, monitor_control_read,
|
|
|
96a5f8 |
- monitor_control_event, mon);
|
|
|
96a5f8 |
+ qemu_chr_add_handlers(chr, &monitor_control_handlers, mon);
|
|
|
96a5f8 |
qemu_chr_fe_set_echo(chr, true);
|
|
|
96a5f8 |
|
|
|
96a5f8 |
json_message_parser_init(&mon->mc->parser, handle_qmp_command);
|
|
|
96a5f8 |
} else {
|
|
|
96a5f8 |
- qemu_chr_add_handlers(chr, monitor_can_read, monitor_read,
|
|
|
96a5f8 |
- monitor_event, mon);
|
|
|
96a5f8 |
+ qemu_chr_add_handlers(chr, &monitor_handlers, mon);
|
|
|
96a5f8 |
}
|
|
|
96a5f8 |
|
|
|
96a5f8 |
QLIST_INSERT_HEAD(&mon_list, mon, entry);
|
|
|
96a5f8 |
diff --git a/net/slirp.c b/net/slirp.c
|
|
|
96a5f8 |
index 4df550f..2868229 100644
|
|
|
96a5f8 |
--- a/net/slirp.c
|
|
|
96a5f8 |
+++ b/net/slirp.c
|
|
|
96a5f8 |
@@ -595,6 +595,11 @@ static void guestfwd_read(void *opaque, const uint8_t *buf, int size)
|
|
|
96a5f8 |
slirp_socket_recv(fwd->slirp, fwd->server, fwd->port, buf, size);
|
|
|
96a5f8 |
}
|
|
|
96a5f8 |
|
|
|
96a5f8 |
+static const QemuChrHandlers guestfwd_handlers = {
|
|
|
96a5f8 |
+ .fd_can_read = guestfwd_can_read,
|
|
|
96a5f8 |
+ .fd_read = guestfwd_read,
|
|
|
96a5f8 |
+};
|
|
|
96a5f8 |
+
|
|
|
96a5f8 |
static int slirp_guestfwd(SlirpState *s, const char *config_str,
|
|
|
96a5f8 |
int legacy_format)
|
|
|
96a5f8 |
{
|
|
|
96a5f8 |
@@ -660,8 +665,7 @@ static int slirp_guestfwd(SlirpState *s, const char *config_str,
|
|
|
96a5f8 |
fwd->port = port;
|
|
|
96a5f8 |
fwd->slirp = s->slirp;
|
|
|
96a5f8 |
|
|
|
96a5f8 |
- qemu_chr_add_handlers(fwd->hd, guestfwd_can_read, guestfwd_read,
|
|
|
96a5f8 |
- NULL, fwd);
|
|
|
96a5f8 |
+ qemu_chr_add_handlers(fwd->hd, &guestfwd_handlers, fwd);
|
|
|
96a5f8 |
}
|
|
|
96a5f8 |
return 0;
|
|
|
96a5f8 |
|
|
|
96a5f8 |
diff --git a/qemu-char.c b/qemu-char.c
|
|
|
96a5f8 |
index d7fa7e6..5abb8b9 100644
|
|
|
96a5f8 |
--- a/qemu-char.c
|
|
|
96a5f8 |
+++ b/qemu-char.c
|
|
|
96a5f8 |
@@ -192,19 +192,26 @@ void qemu_chr_fe_printf(CharDriverState *s, const char *fmt, ...)
|
|
|
96a5f8 |
va_end(ap);
|
|
|
96a5f8 |
}
|
|
|
96a5f8 |
|
|
|
96a5f8 |
+static const QemuChrHandlers null_handlers = {
|
|
|
96a5f8 |
+ /* All handlers are initialised to NULL */
|
|
|
96a5f8 |
+};
|
|
|
96a5f8 |
+
|
|
|
96a5f8 |
void qemu_chr_add_handlers(CharDriverState *s,
|
|
|
96a5f8 |
- IOCanReadHandler *fd_can_read,
|
|
|
96a5f8 |
- IOReadHandler *fd_read,
|
|
|
96a5f8 |
- IOEventHandler *fd_event,
|
|
|
96a5f8 |
- void *opaque)
|
|
|
96a5f8 |
+ const QemuChrHandlers *handlers, void *opaque)
|
|
|
96a5f8 |
{
|
|
|
96a5f8 |
- if (!opaque && !fd_can_read && !fd_read && !fd_event) {
|
|
|
96a5f8 |
+ if (!s) {
|
|
|
96a5f8 |
+ return;
|
|
|
96a5f8 |
+ }
|
|
|
96a5f8 |
+ if (!opaque && !handlers) {
|
|
|
96a5f8 |
/* chr driver being released. */
|
|
|
96a5f8 |
++s->avail_connections;
|
|
|
96a5f8 |
}
|
|
|
96a5f8 |
- s->chr_can_read = fd_can_read;
|
|
|
96a5f8 |
- s->chr_read = fd_read;
|
|
|
96a5f8 |
- s->chr_event = fd_event;
|
|
|
96a5f8 |
+ if (!handlers) {
|
|
|
96a5f8 |
+ handlers = &null_handlers;
|
|
|
96a5f8 |
+ }
|
|
|
96a5f8 |
+ s->chr_can_read = handlers->fd_can_read;
|
|
|
96a5f8 |
+ s->chr_read = handlers->fd_read;
|
|
|
96a5f8 |
+ s->chr_event = handlers->fd_event;
|
|
|
96a5f8 |
s->handler_opaque = opaque;
|
|
|
96a5f8 |
if (s->chr_update_read_handler)
|
|
|
96a5f8 |
s->chr_update_read_handler(s);
|
|
|
96a5f8 |
@@ -442,6 +449,12 @@ static void mux_chr_event(void *opaque, int event)
|
|
|
96a5f8 |
mux_chr_send_event(d, i, event);
|
|
|
96a5f8 |
}
|
|
|
96a5f8 |
|
|
|
96a5f8 |
+static const QemuChrHandlers mux_chr_handlers = {
|
|
|
96a5f8 |
+ .fd_can_read = mux_chr_can_read,
|
|
|
96a5f8 |
+ .fd_read = mux_chr_read,
|
|
|
96a5f8 |
+ .fd_event = mux_chr_event,
|
|
|
96a5f8 |
+};
|
|
|
96a5f8 |
+
|
|
|
96a5f8 |
static void mux_chr_update_read_handler(CharDriverState *chr)
|
|
|
96a5f8 |
{
|
|
|
96a5f8 |
MuxDriver *d = chr->opaque;
|
|
|
96a5f8 |
@@ -456,8 +469,7 @@ static void mux_chr_update_read_handler(CharDriverState *chr)
|
|
|
96a5f8 |
d->chr_event[d->mux_cnt] = chr->chr_event;
|
|
|
96a5f8 |
/* Fix up the real driver with mux routines */
|
|
|
96a5f8 |
if (d->mux_cnt == 0) {
|
|
|
96a5f8 |
- qemu_chr_add_handlers(d->drv, mux_chr_can_read, mux_chr_read,
|
|
|
96a5f8 |
- mux_chr_event, chr);
|
|
|
96a5f8 |
+ qemu_chr_add_handlers(d->drv, &mux_chr_handlers, chr);
|
|
|
96a5f8 |
}
|
|
|
96a5f8 |
if (d->focus != -1) {
|
|
|
96a5f8 |
mux_chr_send_event(d, d->focus, CHR_EVENT_MUX_OUT);
|
|
|
96a5f8 |
diff --git a/qtest.c b/qtest.c
|
|
|
96a5f8 |
index 4663a38..eb8e7ef 100644
|
|
|
96a5f8 |
--- a/qtest.c
|
|
|
96a5f8 |
+++ b/qtest.c
|
|
|
96a5f8 |
@@ -416,6 +416,13 @@ static void qtest_event(void *opaque, int event)
|
|
|
96a5f8 |
}
|
|
|
96a5f8 |
}
|
|
|
96a5f8 |
|
|
|
96a5f8 |
+static const QemuChrHandlers test_handlers = {
|
|
|
96a5f8 |
+ .fd_can_read = qtest_can_read,
|
|
|
96a5f8 |
+ .fd_read = qtest_read,
|
|
|
96a5f8 |
+ .fd_event = qtest_event,
|
|
|
96a5f8 |
+};
|
|
|
96a5f8 |
+
|
|
|
96a5f8 |
+
|
|
|
96a5f8 |
int qtest_init(void)
|
|
|
96a5f8 |
{
|
|
|
96a5f8 |
CharDriverState *chr;
|
|
|
96a5f8 |
@@ -425,7 +432,7 @@ int qtest_init(void)
|
|
|
96a5f8 |
configure_icount("0");
|
|
|
96a5f8 |
chr = qemu_chr_new("qtest", qtest_chrdev, NULL);
|
|
|
96a5f8 |
|
|
|
96a5f8 |
- qemu_chr_add_handlers(chr, qtest_can_read, qtest_read, qtest_event, chr);
|
|
|
96a5f8 |
+ qemu_chr_add_handlers(chr, &test_handlers, chr);
|
|
|
96a5f8 |
qemu_chr_fe_set_echo(chr, true);
|
|
|
96a5f8 |
|
|
|
96a5f8 |
inbuf = g_string_new("");
|