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From 1c596a9498830485a1b2f4a4445643a149179b99 Mon Sep 17 00:00:00 2001
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From: Max Filippov <jcmvbkbc@gmail.com>
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Date: Fri, 21 Sep 2012 02:59:49 +0400
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Subject: [PATCH] target-xtensa: fix extui shift amount
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extui opcode only uses lowermost op1 bit for sa4.
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Reported-by: malc <av1474@comtv.ru>
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Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
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Cc: qemu-stable <qemu-stable@nongnu.org>
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Signed-off-by: malc <av1474@comtv.ru>
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Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>
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---
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target-xtensa/translate.c | 24 +++++++++++++++++++++---
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1 file changed, 21 insertions(+), 3 deletions(-)
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diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
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index 1900bd5..7a1c528 100644
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--- a/target-xtensa/translate.c
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+++ b/target-xtensa/translate.c
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@@ -1778,12 +1778,30 @@ static void disas_xtensa_insn(DisasContext *dc)
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case 5:
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gen_window_check2(dc, RRR_R, RRR_T);
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{
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- int shiftimm = RRR_S | (OP1 << 4);
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+ int shiftimm = RRR_S | ((OP1 & 1) << 4);
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int maskimm = (1 << (OP2 + 1)) - 1;
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TCGv_i32 tmp = tcg_temp_new_i32();
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- tcg_gen_shri_i32(tmp, cpu_R[RRR_T], shiftimm);
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- tcg_gen_andi_i32(cpu_R[RRR_R], tmp, maskimm);
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+
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+ if (shiftimm) {
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+ tcg_gen_shri_i32(tmp, cpu_R[RRR_T], shiftimm);
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+ } else {
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+ tcg_gen_mov_i32(tmp, cpu_R[RRR_T]);
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+ }
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+
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+ switch (maskimm) {
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+ case 0xff:
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+ tcg_gen_ext8u_i32(cpu_R[RRR_R], tmp);
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+ break;
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+
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+ case 0xffff:
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+ tcg_gen_ext16u_i32(cpu_R[RRR_R], tmp);
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+ break;
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+
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+ default:
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+ tcg_gen_andi_i32(cpu_R[RRR_R], tmp, maskimm);
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+ break;
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+ }
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tcg_temp_free(tmp);
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}
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break;
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--
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1.7.12.1
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